NAU8810
Mono Audio Codec with 2-wire Control Interface
1.

GENERAL DESCRIPTIONThe NAU8810 is a cost effective low power wideband Monophonic audio CODEC. It is suitable for a wide range ofaudio applications, including voice telephony. Supported functions include a 5-band Graphic Equalizer, Automatic Level
Control (ALC) with noise gate, PGA, standard I2S or PCM audio interface, optional PCM time slot assignment, and afull Fractional-N on-chip PLL. This device includes one differential microphone input, and multiple variable gain control
stages in the audio paths. Both a Mono headset/line-level output and a high power differential BTL speaker driver
output is provided.

The analog input path includes a PGA enabling dynamic range optimization of a wide range of input sources with
programmable gain from -12dB to +35.25dB. In addition to a digital high pass filter to remove DC offset voltages, theADC also features programmable voice band digital filtering. Audio data is communicated via the audio interface that
supports multiple I2S and PCM data formats. The DAC converter path includes filtering, mixing, programmable-gain
amplifiers, and soft muting. The 2-Wire digital control interface has an independent supply voltage to enable easy
integration into multiple supply voltage systems.

The NAU8810 operates at supply voltages from 2.5V ~ 3.6V, and the digital core can operate at a voltage as low as
1.71V to conserve power. The NAU8810 is specified for operation from -40°C ~ +85°C.
2.

FEATURES

24-bit signal processing linear Audio CODEC
 Audio DAC: 93dB SNR and -84dB THD
 Audio ADC: 91dB SNR and -79dB THD
 Support variable sample rates from 8 - 48kHz

Low Power, Low Voltage
 Analog Supply: 2.5V ~ 3.6V
 Digital Supply: 1.71V ~ 3.6V
 Nominal Operating Voltage: 3.3V

Analog I/O
 Integrated programmable Microphone Amplifier Integrated BTL Speaker Driver 1 W (8Ω / 5V)
 Earphone / Speaker / Line-Output Mixing /Routing Integrated Headset Driver 40mW (16Ω / 3.3V)
 Low Noise bias supply voltage for microphone On-chip full fractional-N PLL

Additional features 5-band Graphic Equalizer Programmable ALC
 ADC Notch Filter
 Programmable High Pass Filter
 Digital ADC/DAC Passthrough Mono data output on both channels
 Industrial temperature range: –40°C ~ +85°C
 Package is Halogen-free, RoHS-compliant andTSCA-compliant

Interfaces
 I2S digital interface PCM time slot assignment
 2-Wire serial control Interface (I2C style; /Writecapable)Feb 1, 2023

Applications
 All types of wired/wireless telephony Security Systems
 Mobile Telephone Hands-free Kits
 Residential & Consumer Intercoms

Page 1 of 101

Rev 1.9

MICMIC+

Microphone
Interface

Input
Mixers &
Gain
Stage

ADC Filter
VolumeControl
HPF
Notch
FilterADC

MOUT
DAC Filter
VolumeControl
Limiter

DAC

OutputMixersSPKOUT+-1

MICBIAS

Microphone
Bias

Digital Audio Interface
I2S

Control IF

PCM

2-wireDigital I/O

Audio I/O

MIC+

MIC-

VREF

VDDSPK

SPKOUT -

20

19

18

17

16

PIN CONFIGURATION

3

13

MOUT

VDDD

4

12

SDIO

VSSD

5

11

SCLK

Metal
Paddle(VSSA)

10

VSSA

MCLK

SPKOUT+

9

14

BCLK

2

8

VDDA

FS

VSSSPK

7

15

DACIN

1

6

MICBIASADCOUT

3.

SPKOUT-

Figure 1: 20-Pin QFN Package

Feb 1, 2023

Page 2 of 101

Rev 1.9

4.

PIN DESCRIPTION
Pin Name

24-PinMICBIAS

1

VDDA
VSSA

Functionality

A/D

Pin Type

Microphone Bias

A

O

2

Analog Supply

A

I

3

Analog Ground

A

O

VDDD

4

Digital Supply

D

I

VSSD

5

Digital Ground

D

O

ADCOUT

6

Digital Audio Data Output

D

O

DACIN

7

Digital Audio Data Input

D

I

FS

8

Frame Sync

D

I/O

BCLK

9

Bit Clock

D

I/O

MCLK

10

Master Clock

D

I

SCLK

11

2-Wire Serial Clock

D

I

SDIO

12

2-Wire I/O

D

O

MOUT

13

MONO Output

A

O

SPKOUT+

14

Speaker Positive Output

A

O

VSSSPK

15

Speaker GroundA

O

SPKOUT-

16

Speaker Negative Output

AO

VDDSPK

17

Speaker Supply

A

I

VREF

18

Decoupling internal analog mid supply reference

A

O

MIC-

19

Microphone Negative Input

A

I

MIC+

20

Microphone Positive Input

A

I

Table 1: Pin Description

Notes
1.

The 20-QFN package includes a bulk ground connection pad on the underside of the chip. This bulk groundshould be thermally tied to the PCB, and electrically tied to the analog ground.

2.

Unused analog input pins should be left as no-connection.

3.

Any unused digital input pin must be tied high or low as appropriate.

Feb 1, 2023

Page 3 of 101

Rev 1.9

Feb 1, 2023

Page 4 of 101

MICBIASEN[4](0x2F)ALC
NOTCH
FILTER

DIGITAL AUDIO INTERFACE

VDDA

R

R

VDDA

ADC
DAC

PLL

(Sidetone) BYPASSLIMITERMCLKCONTROL
INTERFACE

VSSA

VREF

MICBIAS

MICROPHONE
BIAS

PMICBSTGAIN[6:4](0x2F) = 000

PMICBSTGAIN[6:4](0x2F)ΣHPF

VDDSPK

PMICPGAPGAGAIN(0x2D)PGAMT[6](0x2D)PGABST[8](0x2F)VSSD

VREFNMICPGA[1](0x2C)VSSSPK

MIC+

MIC-

VSSD

-12 dB to+35.25 dB

PGAEN[2](0x02)BYPSPK[1](0x32)DACSPK[0](0X32)BYPMOUT[1](0x38)DACMOUT[0](0x38)SPKGAIN[5:0](0x36)SPKMOUT[x:0](0xxx)SPKMXEN[2](0x03)

ΣΣ

MOUTMXEN[3](0x03)SPKBST[2](0x31)MOUTBST[3](0x31)

1.5X
1.0X

1.5X
1.0X

1.5X
1.0X

SPKOUT-SPKOUT+

MOUT

5.
BLOCK DIAGRAM

SCLK
SDIO

ADCOUT

DACIN

FS

BCLK

Figure 2: NAU8810 General Block Diagram

Rev 1.9

6.

Table of Contents

1.
GENERAL DESCRIPTION .................................................................................................................................1
2.
FEATURES .........................................................................................................................................................1
3.
PIN CONFIGURATION .......................................................................................................................................24.
PIN DESCRIPTION .............................................................................................................................................3
5.
BLOCK DIAGRAM .............................................................................................................................................46.
TABLE OF CONTENTS ......................................................................................................................................57.
LIST OF TABLES ............................................................................................................................................. 10
8.
ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 119.
OPERATING CONDITIONS.............................................................................................................................. 1110.
ELECTRICAL CHARACTERISTICS ................................................................................................................ 1211.
FUNCTIONAL DESCRIPTION .......................................................................................................................... 15
11.1. INPUT PATH .............................................................................................................................................. 15
11.1.1. The differential microphone input (MIC- & MIC+ pins)................................................................... 15
11.1.1.1.

Positive Microphone Input (MIC+) ........................................................................................... 16

11.1.1.2.

Negative Microphone Input (MIC-) ........................................................................................... 17

11.1.1.3. PGA Gain Control ..................................................................................................................... 17
11.1.2. PGA Boost / Mixer Stage .................................................................................................................. 18
11.2. MICROPHONE BIASING ........................................................................................................................... 19
11.3. ADC DIGITAL FILTER BLOCK ................................................................................................................. 21
11.3.1. Programmable High Pass Filter (HPF) ............................................................................................ 22
11.3.2. Programmable Notch Filter (NF) ...................................................................................................... 23
11.3.3. Digital ADC Gain Control.................................................................................................................. 23
11.4. PROGRAMMABLE GAIN AMPLIFIER (PGA) .......................................................................................... 24
11.4.1. Automatic level control (ALC) .......................................................................................................... 24
11.4.1.1.

Normal Mode ............................................................................................................................. 27

11.4.1.2. ALC Hold Time (Normal mode Only) .......................................................................................... 27
11.4.2. Peak Limiter Mode ............................................................................................................................ 28
11.4.3. Attack Time ........................................................................................................................................ 30
11.4.4. Decay Times ...................................................................................................................................... 30
11.4.5. Noise gate (normal mode only) ........................................................................................................ 30
11.4.6. Zero Crossing .................................................................................................................................... 31
11.5. DAC DIGITAL FILTER BLOCK ................................................................................................................. 32
11.5.4. Hi-Fi DAC De-Emphasis and Gain Control ...................................................................................... 34
11.5.5. Digital DAC Output Peak Limiter ..................................................................................................... 34
11.5.6. Volume Boost .................................................................................................................................... 34
11.5.7. 5-Band Equalizer ............................................................................................................................... 35
11.6. ANALOG OUTPUTS .................................................................................................................................. 36
11.6.1. Speaker Mixer Outputs ..................................................................................................................... 36
11.6.2. Mono Mixer Output .......................................................................................................................... 37
11.6.3. Differential Output Configuration .................................................................................................... 38
11.6.4. Unused Analog I/O ............................................................................................................................ 38
11.7. GENERAL PURPOSE CONTROL............................................................................................................. 41
11.7.1. Slow Timer Clock .............................................................................................................................. 41
11.8. CLOCK GENERATION BLOCK ................................................................................................................ 41
11.9. CONTROL INTERFACE ............................................................................................................................ 45

Feb 1, 2023

Page 5 of 101

Rev 1.9

11.9.1.

2-WIRE Serial Control (I2C Style Interface) ..................................................................................... 45

11.9.1.1.

2-WIRE Protocol Convention ................................................................................................... 45

11.9.1.2.

2-WIRE Write Operation ........................................................................................................... 46

11.9.1.3. 2-WIRE Operation .................................................................................................................... 46
11.10. DIGITAL AUDIO INTERFACES ................................................................................................................ 47
11.10.1. Right Justified audio data ................................................................................................................ 48
11.10.2. Left Justified audio data ................................................................................................................... 49
11.10.3. I2S audio data .................................................................................................................................... 50
11.10.4. PCM audio data ................................................................................................................................. 51
11.10.5. PCM Time Slot audio data ................................................................................................................ 52
11.10.6. Companding ...................................................................................................................................... 53
11.11. POWER SUPPLY ...................................................................................................................................... 54
11.11.1. Power-On Reset ................................................................................................................................ 54
11.11.2. Power Related Software Considerations ........................................................................................ 54
11.11.3. Software Reset .................................................................................................................................. 55
11.11.4. Power Up/Down Sequencing............................................................................................................ 55
11.11.5. Reference Impedance (REFIMP) and Analog Bias ......................................................................... 57
11.11.6. Power Saving..................................................................................................................................... 57
11.11.7. Estimated Supply Currents .............................................................................................................. 58
12.
REGISTER DESCRIPTION............................................................................................................................... 59
12.1. SOFTWARE RESET .................................................................................................................................. 61
12.2. POWER MANAGEMENT REGISTERS ..................................................................................................... 61
12.2.1. Power Management 1 ....................................................................................................................... 61
12.2.2. Power Management 2 ....................................................................................................................... 62
12.2.3. Power Management 3 ....................................................................................................................... 62
12.3. AUDIO CONTROL REGISTERS ............................................................................................................... 62
12.3.1. Audio Interface Control .................................................................................................................... 62
12.3.2. Audio Interface Companding Control ............................................................................................. 63
12.3.3. Clock Control Register ..................................................................................................................... 64
12.3.4. Audio Sample Rate Control Register .............................................................................................. 65
12.3.5. DAC Control Register ....................................................................................................................... 65
12.3.6. DAC Gain Control Register .............................................................................................................. 66
12.3.7. ADC Control Register ....................................................................................................................... 66
12.3.8. ADC Gain Control Register .............................................................................................................. 67
12.4. 5-BAND EQUALIZER CONTROL REGISTERS ........................................................................................ 68
12.5. DIGITAL TO ANALOG CONVERTER (DAC) LIMITER REGISTERS ....................................................... 69
12.6. NOTCH FILTER REGISTERS ................................................................................................................... 70
12.7. AUTOMATIC LEVEL CONTROL REGISTER ........................................................................................... 71
12.7.1. ALC1 REGISTER ............................................................................................................................... 71
12.7.2. ALC3 REGISTER ............................................................................................................................... 71
12.8. NOISE GAIN CONTROL REGISTER ........................................................................................................ 73
12.9. PHASE LOCK LOOP (PLL) REGISTERS ................................................................................................. 74
12.9.1. PLL Control Registers ...................................................................................................................... 74
12.9.2. Phase Lock Loop Control (PLL) Registers ..................................................................................... 74
12.10. INPUT, OUTPUT, AND MIXERS CONTROL REGISTER ......................................................................... 75
12.10.1. Attenuation Control Register ........................................................................................................... 75
12.10.2. Input Signal Control Register........................................................................................................... 75

Feb 1, 2023

Page 6 of 101

Rev 1.9

12.10.3. PGA Gain Control Register .............................................................................................................. 76
12.10.4. ADC Boost Control Registers .......................................................................................................... 77
12.10.5. Output Register ................................................................................................................................. 77
12.10.6. Speaker Mixer Control Register ....................................................................................................... 78
12.10.7. Speaker Gain Control Register ........................................................................................................ 78
12.10.8. MONO Mixer Control Register.......................................................................................................... 79
12.10.9. Power Management 4 ....................................................................................................................... 79
12.11. PCM TIME SLOT CONTROL & ADCOUT IMPEDANCE OPTION CONTROL ......................................... 80
12.11.1. PCM1 TIMESLOT CONTROL REGISTER ......................................................................................... 80
12.11.2. PCM2 TIMESLOT CONTROL REGISTER ......................................................................................... 80
12.12. REGISTER ID ............................................................................................................................................ 81
12.12.1. Device revision register.................................................................................................................... 81
12.12.2. 2-WIRE ID Register............................................................................................................................ 81
12.12.3. Additional ID ...................................................................................................................................... 81
12.13. Reserved ................................................................................................................................................... 81
12.14. OUTPUT Driver Control Register ............................................................................................................ 82
12.15. AUTOMATIC LEVEL CONTROL ENHANCED REGISTER ...................................................................... 83
12.15.1. ALC1 Enhanced Register ................................................................................................................. 83
12.15.2. ALC Enhanced 2 Register ................................................................................................................ 83
12.16. MISC CONTROL REGISTER .................................................................................................................... 84
12.17. Output Tie-Off REGISTER........................................................................................................................ 85
12.18. AGC PEAK-TO-PEAK OUT REGISTER ................................................................................................... 85
12.19. AGC PEAK OUT REGISTER .................................................................................................................... 85
12.20. AUTOMUTE CONTROL AND STATUS REGISTER ................................................................................ 86
12.21. Output Tie-off Direct Manual Control REGISTER .................................................................................. 86
13.
CONTROL INTERFACE TIMING DIAGRAM .................................................................................................... 87
13.1. 2-WIRE TIMING DIAGRAM ....................................................................................................................... 87
14.
AUDIO INTERFACE TIMING DIAGRAM .......................................................................................................... 88
14.1. AUDIO INTERFACE IN SLAVE MODE ...................................................................................................... 88
14.2. AUDIO INTERFACE IN MASTER MODE .................................................................................................. 88
14.3. PCM AUDIO INTERFACE IN SLAVE MODE (PCM Audo Data)................................................................ 89
14.4. PCM AUDIO INTERFACE IN MASTER MODE (PCM Audo Data) ............................................................ 89
14.5. PCM AUDIO INTERFACE IN SLAVE MODE (PCM Time Slot Mode )....................................................... 90
14.6. PCM AUDIO INTERFACE IN MASTER MODE (PCM Time Slot Mode ) ................................................... 90
14.7. System Clock (MCLK) Timing Diagram ...................................................................................................... 91
14.8. µ-LAW ENCODE DECODE CHARACTERISTICS .................................................................................... 92
14.9. A-LAW ENCODE DECODE CHARACTERISTICS.................................................................................... 93
14.10. µ-LAW / A-LAW CODES FOR ZERO AND FULL SCALE ........................................................................ 94
14.11. µ-LAW / A-LAW OUTPUT CODES (DIGITAL MW) .................................................................................. 94
15.
DIGITAL FILTER CHARACTERISTICS ........................................................................................................... 95
16.
TYPICAL APPLICATION .................................................................................................................................. 97
17.
PACKAGE SPECIFICATION ............................................................................................................................ 98
18.
ORDERING INFORMATION ............................................................................................................................. 99
19.
REVISION HISTORY ...................................................................................................................................... 100
IMPORTANT NOTICE ............................................................................................................................................... 101

Feb 1, 2023

Page 7 of 101

Rev 1.9

List of Figures
Figure 1: 20-Pin QFN Package .....................................................................................................................................2
Figure 2: NAU8810 General Block Diagram .................................................................................................................4
Figure 3: Input PGA Circuit Block Diagram ................................................................................................................. 16
Figure 4: Boost Stage Block Diagram ......................................................................................................................... 18
Figure 5: Microphone Bias Schematic......................................................................................................................... 19
Figure 6: ADC Digital Filter Path Block Diagram ......................................................................................................... 21
Figure 7: ALC Block Diagram ...................................................................................................................................... 24
Figure 8: ALC Response Graph .................................................................................................................................. 25
Figure 9: ALC Normal Mode Operation ....................................................................................................................... 27
Figure 10: ALC Hold Time ........................................................................................................................................... 28
Figure 11: ALC Limiter Mode Operations .................................................................................................................... 28
Figure 12: ALC Operation with Noise Gate disabled ................................................................................................... 30
Figure 13: ALC Operation with Noise Gate Enabled ................................................................................................... 31
Figure 14: DAC Digital Filter Path ............................................................................................................................... 32
Figure 15: DAC Digital Limiter Control ........................................................................................................................ 34
Figure 16: Speaker and MONO Analogue Outputs [To Update ? output from Auxilliary Amplifier] ............................. 36
Figure 17: Tie-off Options for the Speaker and MONO output Pins ............................................................................ 39
Figure 18: PLL and Clock Select Circuit...................................................................................................................... 41
Figure 19: Valid START Condition .............................................................................................................................. 45
Figure 20: Valid Acknowledge ..................................................................................................................................... 45
Figure 21: Valid STOP Condition ................................................................................................................................ 45
Figure 22: Slave Address Byte, Control Address Byte, and Data Byte ....................................................................... 46
Figure 23: Byte Write Sequence ................................................................................................................................. 46
Figure 24: 2-Wire Read Sequence .............................................................................................................................. 47
Figure 25: Right Justified Audio Interface (Normal Mode)........................................................................................... 48
Figure 26: Right Justified Audio Interface (Special mode) .......................................................................................... 49
Figure 27: Left Justified Audio Interface (Normal Mode) ............................................................................................. 49
Figure 28: Left Justified Audio Interface (Special mode) ............................................................................................. 50
Figure 29: I2S Audio Interface (Normal Mode) ............................................................................................................ 50
Figure 30: I2S Audio Interface (Special mode)............................................................................................................ 51
Figure 31: PCM Mode Audio Interface (Normal Mode) ............................................................................................... 51
Figure 32: PCM Mode Audio Interface (Special mode) ............................................................................................... 52
Figure 33: PCM Time Slot Mode (Time slot = 0) (Normal Mode) ................................................................................ 52
Figure 34: PCM Time Slot Mode (Time slot = 0) (Special mode) ................................................................................ 53
Figure 35: The Programmable ADCOUT Pin .............................................................................................................. 80
Figure 36: 2-Wire Timing Diagram .............................................................................................................................. 87
Figure 37: Audio Interface Slave Mode Timing Diagram ............................................................................................. 88

Feb 1, 2023

Page 8 of 101

Rev 1.9

Figure 38: Audio Interface in Master Mode Timing Diagram ....................................................................................... 88
Figure 39: PCM Audio Interface Slave Mode Timing Diagram .................................................................................... 89
Figure 40: PCM Audio Interface Slave Mode Timing Diagram .................................................................................... 89
Figure 41: PCM Audio Interface Slave Mode (PCM Time Slot Mode )Timing Diagram.............................................. 90
Figure 42: PCM Audio Interface Master Mode (PCM Time Slot Mode )Timing Diagram............................................. 90
Figure 43: MCLK Timing Diagram ............................................................................................................................... 91
Figure 44: DAC Filter Frequency Response ............................................................................................................... 96
Figure 45: ADC Filter Frequency Response ............................................................................................................... 96
Figure 46: DAC Filter Ripple ....................................................................................................................................... 96
Figure 47: ADC Filter Ripple ....................................................................................................................................... 96
Figure 48: Application Diagram For 20-Pin QFN ......................................................................................................... 97

Feb 1, 2023

Page 9 of 101

Rev 1.9

7.

List of Tables

Table 1: Pin Description ................................................................................................................................................3
Table 2: Register associated with Input PGA Control ................................................................................................. 16
Table 3: Microphone Non-Inverting Input Impedances................................................................................................. 17
Table 4: Microphone Inverting Input Impedances ....................................................................................................... 17
Table 5: Registers associated with ALC and Input PGA Gain Control ........................................................................ 18
Table 6: Registers associated with PGA Boost Stage Control .................................................................................... 19
Table 7: Register associated with Microphone Bias .................................................................................................... 20
Table 8: Microphone Bias Voltage Control .................................................................................................................. 21
Table 9: Register associated with ADC ....................................................................................................................... 22
Table 10: High Pass Filter Cut-off Frequencies (HPFAM=1)....................................................................................... 22
Table 11: Registers associated with Notch Filter Function.......................................................................................... 23
Table 12: Equations to Calculate Notch Filter Coefficients ......................................................................................... 23
Table 13: Register associated with ADC Gain ............................................................................................................ 23
Table 14: Registers associated with ALC Control ....................................................................................................... 26
Table 15: ALC Maximum and Minimum Gain Values .................................................................................................. 26
Table 16: Registers associated with DAC Gain Control .............................................................................................. 32
Table 17: Registers associated with Equalizer Control ............................................................................................... 35
Table 18: Speaker Output Controls ............................................................................................................................. 37
Table 19: MONO Output Controls ............................................................................................................................... 37
Table 20: General Purpose Control............................................................................................................................. 41
Table 21: Registers associated with PLL .................................................................................................................... 42
Table 22: Registers associated with PLL .................................................................................................................... 43
Table 23: PLL Frequency Examples ........................................................................................................................... 44
Table 24: Standard Interface modes ........................................................................................................................... 48
Table 25: Audio Interface Control Registers ............................................................................................................... 48
Table 26: Companding Control ................................................................................................................................... 53
Table 27: Power up sequence..................................................................................................................................... 56
Table 28: Power down Sequence ............................................................................................................................... 57
Table 29: Registers associated with Power Saving..................................................................................................... 57
Table 30: VDDA 3.3V Supply Current ......................................................................................................................... 58
Table 31: 2-WireTiming Parameters ........................................................................................................................... 87
Table 32: Audio Interface Timing Parameters ............................................................................................................. 91
Table 33: MCLK Timing Parameter ............................................................................................................................. 91

Feb 1, 2023

Page 10 of 101

Rev 1.9

8.

ABSOLUTE MAXIMUM RATINGSCONDITION

MIN

MAX

Units

VDDD, VDDA supply voltages

-0.3

+3.63

V

VDDSPK supply voltage (MOUTBST=0, SPKBST=0)

-0.3

+3.63

V

VDDSPK supply voltage (MOUTBST=1, SPKBST=1)

-0.3

+5.50

V

Core Digital Input Voltage range

VSSD – 0.3

VDDD + 0.30

V

Analog Input Voltage range

VSSA – 0.3

VDDA + 0.30

V

Industrial operating temperature TA

-40

+85

0C

Junction Temperature TJ

-40

+150

0C

Storage temperature range

-65

+150

0C

CAUTION: Do not operate at or near the maximum ratings listed for extended period of time. Exposure to suchconditions may adversely influence product reliability and result in failures not covered by warranty. These devices are
sensitive to electrostatic discharge; follow proper IC Handling Procedures.

9.

OPERATING CONDITIONS
Condition

SymbolMin Value

Analogue supplies range

VDDA

Digital supply range
Speaker supply (MOUTBST=0,SPKBST=0)

Speaker supply (MOUTBST=1,
SPKBST=1)

GroundTypicalValue

Max Value

Units

2.501

3.60

V

VDDD

1.71

3.60

V

VDDSPK

2.50

3.60

V

VDDSPK

2.50

5.50

V

VSSD, VSSA,VSSSPK

0

V

Note 1. VDDA must be ≥ VDDD.

Feb 1, 2023

Page 11 of 101

Rev 1.9

10. ELECTRICAL CHARACTERISTICS
VDDD = 1.8V, VDDA = VDDSPK = 3.3V (VDDSPK = 1.5*VDDA when Boost), TA = +25oC, 1kHz signal, fs = 48kHz,
24-bit audio data unless otherwise stated.
PARAMETERSYMBOLTEST CONDITIONS

MIN

TYP

MAX

UNIT

Analogue to Digital Converter (ADC)
Full scale input signal 1

VINFS

PGABST = 0dB
PGAGAIN = 0dB

Signal to Noise Ratio 2

SNR

Gain = 0dB, A-weighted

Total Harmonic Distortion 3

THD

Input = -1dBFS, Gain = 0dB

87

1.0
0

VRMS
dBV

91

dB

-79

-65

dB

Digital to Analogue Converter (DAC) to MONO output (all data measured with 10kΩ / 50pF load)
MOUTBST=0

1.0x(VREF)MOUTBST=1

1.5 x
VREF

Full Scale output signal 1

Signal to Noise Ratio 2

SNR

A-weighted (ADC/DAC oversampling rateof 128)

Total Harmonic Distortion 3

THD

RL = 10 KΩ; -1.0dBfs

90

Programmable input PGA gain

Programmable Boost PGA
gain

RAUX

Positive Microphone Input
resistance

RMIC+

Input Capacitance

CMIC

-70

0.75

PGABST = 1

20

dB
VRMS
dBV

35.25

Guaranteed monotonic
PGABST = 0

dB
dB

0

Mute Attenuation
PGA equivalent output noise

dB

1
0
-12

Programmable Gain Step Size

Auxiliary Input resistance93-84

Microphone Inputs (MICN & MICP) and MIC Input Programmable Gain Amplifier (PGA)
PGABST = 0dB
Full-scale Input Signal Level 1
VINFS
PGAGAIN = 0dB

VRMS

dB

100

dB

0 to 20kHz,
Gain set to 35.25dB

110

µV

PGA Gain = 35.25dB

1.6

kΩ

PGA Gain = 0dB

47kΩ

PGA Gain = -12dB

75kΩ

PMICPGA = 1

94

kΩ

10

pF

Speaker Output PGA
Programmable Gain
Programmable Gain Step Size

Feb 1, 2023

-57
Guaranteed monotonic

Page 12 of 101

6

dB
dB

1

Rev 1.9

VDDD = 1.8V, VDDA = VDDSPK = 3.3V (VDDSPK = 1.5*VDDA when Boost), TA = +25oC, 1kHz signal, fs = 48kHz,
24-bit audio data unless otherwise stated.
PARAMETERSYMBOLTEST CONDITIONSBTL Speaker Output (SPKOUT+, SPKOUT- with 8Ω bridge tied load)
SPKBST = 0
VDDSPK = VDDA
Full scale output 7
SPKBST = 1
VDDSPK = 1.5 * VDDA
Output Power

Signal to Noise Ratio

PO

SNR

PSRR

UNIT

VDDA / 3.3
VRMS(VDDA / 3.3) * 1.590dB

VDDSPK = 1.5*VDDA
RL = 8Ω

90

dB

-63

dB

-56

dB

-60

dB

-61

dB

PO =1W-34dB

VDDSPK = 3V, SPKBST = 050dB

VDDSPK = 1.5*VDDA, SPKBST = 1

50

dB

VDDA / 3.3

VRMS

90

dB

-84

dB

-85

dB

(MICBIASV = 0)

0.9*
VDD
A

V

(MICBIASV = 1)

0.65*
VDD
A

V

3

mA

MICBIASM = 0(1kHz to 20kHz)

14nV/√HzMICBIASM = 1(1kHz to 20kHz)

4nV/√HzVDDSPK=3.3V

PO =360mW

RL =8Ω

PO =800mW
Power Supply Rejection Ratio(50Hz - 22kHz)MAX

VDDSPK = 3.3V
RL = 8Ω

PO =400mW
THD

TYP

Output power is very closely correlated with THD;
see below

PO =180mW
Total Harmonic DistortionMIN

VDDSPK =1.5*VDDA

Headphone’ output (SPKOUTP, SPKOUTN with resistive load to ground)
Full scale output 7
Signal to Noise Ratio

SNR

A-weighted
Po = 20mW

Total Harmonic Distortion

THD
Po = 20mW

RL=16
Ω
RL=32
Ω

VDDSPK=3.3V

Microphone Bias

Bias Voltage

Bias Current Source

VMICBIASIMICBIAS

Output Noise Voltage
VN

Automatic Level Control (ALC)/Limiter – ADC only
Target Record Level-28.5

Programmable Gain

-12

Programmable Gain Step Size
Gain Hold Time 4, 6

Feb 1, 2023

Guaranteed MonotonictHOLD

MCLK=12.288MHz

Page 13 of 101

-6

dB

35.25

dB
dB

0.75
0 / 2.67 / …/ 43691(time doubles with eachstep)

Rev 1.9msVDDD = 1.8V, VDDA = VDDSPK = 3.3V (VDDSPK = 1.5*VDDA when Boost), TA = +25oC, 1kHz signal, fs = 48kHz,
24-bit audio data unless otherwise stated.
PARAMETERSYMBOLTEST CONDITIONS

MIN

TYP

MAX

UNIT

ALC Mode
ALCM=0MCLK=12.288MHz

3.3 / 6.6 / 13.1 / … / 3360
(time doubles every step)ms

Limiter Mode
ALCM=1MCLK=12.288MHz

0.73 / 1.45 / 2.91 / … /744 (time doubles every
step)

ms

ALC Mode
ALCM=0MCLK=12.288MHz

0.83 / 1.66 / 3.33 / … /852 (time doubles every
step)

ms

Limiter Mode
ALCM=1MCLK=12.288MHz

0.18 / 0.36 / 0.73 / … /186 (time doubles every
step)

ms

0.7 ×
VDDD

V

Automatic Level Control (ALC)/Limiter – ADC only

Gain Ramp-Up (Decay) Time 5,
6

Gain Ramp-Down (Attack)Time 5, 6

tDCY

tATK

Digital Input / Output
Input HIGH Level

VIH

Input LOW Level

VIL

Output HIGH Level

VOH

IOL = 1mA

Output LOW Level

VOL

IOH = -1mA

0.3 ×
VDDD
0.9 ×
VDDD

V
0.1 x
VDDD

Notes
1. Full Scale is relative to VDDA (FS = VDDA/3.3.).
2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full-scale output and the output
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
3. THD+N (dB) - THD+N are a ratio, of the RMS values, of (Noise + Distortion)/Signal.
4. Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. It
does not apply to ramping down the gain when the signal is too loud, which happens without a delay.
5. Ramp-up and Ramp-Down times are defined as the time to change the PGA gain by 6dB of its gain range.
6. All hold, ramp-up and ramp-down times scale proportionally with MCLK (specified for MCLK = 12.288MHz)
7. The maximum output voltage can be limited by the speaker power supply. If MOUTBST or SPKBST is, set thenVDDSPK should be 1.5xVDDA to prevent clipping taking place in the output stage (when PGA gains are set to 0dB).

Feb 1, 2023

Page 14 of 101

V

Rev 1.9V11. FUNCTIONAL DESCRIPTIONThe NAU8810 is a Mono Audio CODEC with very robust ADC and DAC capabilities. The device provides one
differential microphone input pair (MIC- & MIC+ pins) supported by a two-stage amplification path for amplification by
as much as 55.25dB. Additionally, the MIC+ pin can be used independently from the MIC- pin enabling two independent
mixing inputs for some applications.

The device also has an internal configurable biasing circuit for biasing the microphone, which reduces external
components. The PGA output has programmable ADC gain. An advanced Sigma Delta ADC and DAC are used alongwith digital decimation and interpolation filters to give high quality audio at sample rates from 8 KHz to 48 KHz. The
Digital Filter blocks include ADC high pass filters, a Notch Filter, and a 5-band equalizer. The device has two output
mixers, one for the Mono output, and the other for the speaker output.

The NAU8810 has a 2-Wire read/write serial control interface for device control. Audio data is supported in many
commonly used industry formats as either I2S or PCM formatted data. Additionally, the PCM mode supports timeslotting for added design flexibility, such as in creation of multichannel systems using a shared audio data bus.

The NAU8810 can operate as a master or slave audio device. It can operate with sample rates ranging from 8 kHz to
48 kHz, depending on the values of MCLK and its pre-scaler. The NAU8810 includes a PLL block, where it takes theexternal clock (MCLK pin) to generate other clocks for the audio data transfer such as Bit clock (BCLK), Frame Sync
(FS), and I2S clocks. The power control registers help save power by controlling the major individual functional blocksof the NAU8810.

11.1.

INPUT PATH

The NAU8810 microphone inputs are maintained at a DC bias at approximately a half of the VDDA supply voltage.
Connections to these inputs should be AC-coupled by means of DC blocking capacitors suitable for the device
application.

11.1.1. The differential microphone input (MIC- & MIC+ pins)
The NAU8810 features a low-noise, high common mode rejection ratio (CMRR), differential microphone inputs (MIC& MIC+ pins) which are connected to a PGA Gain stage. The differential input structure is essential in noisy digitalsystems where amplification of low-amplitude analog signals is required in products such as notebooks and PDAs.
When properly employed, the differential input architecture offers an improved power-supply rejection ratio (PSRR) andhigher ground noise immunity.

Feb 1, 2023

Page 15 of 101

Rev 1.9

PGAGAIN[5:0](0x2D)NMICPGA[1](0x2C)NMICPGA[1](0x2C)RMIC-

R
PGAGAIN[5:0](0x2D)PMICPGA[0](0x2C)MIC+
To PGA
Boost

R-12 dB to +35.25 dB

VREF
PGAGAIN[5:0](0x2D)

Figure 3: Input PGA Circuit Block Diagram

Bit(s)

Addr

Parameter

Programmable Range

PMICPGA[0]0x2C

Positive Microphone to PGA

0 = Input PGA Positive terminal to VREF
1 = Input PGA Positive terminal to MICP

NMICPGA[1]0x2C

Negative Microphone to
PGA

0 = MICN not connected to input PGA
1 = MICN to input PGA Negative terminal.

Table 2: Register associated with Input PGA Control

11.1.1.1.

Positive Microphone Input (MIC+)

The positive microphone input (MIC+) can be used as part of the differential input. It connects to the positive terminalof the PGA gain amplifier by setting PMICPGA[0] address (0x2C) to HIGH or can be connected to VREF by setting
PMICPGA[0] address (0x2C) to LOW.

In single ended applications where the MIC+ input is used without using MIC-, the PGA gain values will be valid only if
the MIC- pin is terminated to a low impedance signal point. This termination should normally be an AC coupled pathto signal ground. The non-inverting input impedance is constant regardless of the gain value. The following table gives
the nominal input impedance for both inputs. Impedance for specific gain values not listed in this table can be estimatedthrough interpolation between listed values.

Feb 1, 2023

Page 16 of 101

Rev 1.9

MIC+ to non-inverting PGA input
Nominal Input Impedance

MIC- to inverting PGA input
Nominal Input ImpedanceGain (dB)

Impedance (kΩ)

Gain (dB)

Impedance (kΩ)

-12
-9
-6
-3
0
3
6
9
12
18
30
35.25

94
94
94
94
94
94
94
94
94
94
94
94

-12
-9
-6
-3
0
3
6
9
12
18
30
35.25

75
69
63
55
47
39
31
25
19
11
2.9
1.6

Table 3: Microphone Non-Inverting
Input Impedances

11.1.1.2.

Table 4: Microphone Inverting Input
Impedances

Negative Microphone Input (MIC-)

The negative microphone input (MIC-) may be used as either a differential input in conjuction with MIC+, or as a single
ended intput. This input connects to the negative terminal of the PGA gain amplifier by setting NMICPGA[1] address(0x2C) to HIGH. When the MIC- is used as a single ended input, MIC+ should be connected to VREF by setting
PMICPGA[0] address (0x2C) bit to LOW, or MIC+ may be used as an independent input.

When the associated control bit NMICPGA[1] address 0X2C is set to logic = 0, the MIC- pin is connected to a resistor
of approximately 30kΩ which is tied to VREF. The purpose of the tie to VREF is to reduce any pop or click sound bykeeping the DC level of the MIC- pin close to VREF at all times. It is important for a system designer to know that the
MIC-input impedance varies as a function of the selected PGA gain. This is normal and expected for a difference
amplifier type topology. The above table gives the nominal resistive impedance values for this input over the possible
gain range. Impedance for specific gain values not listed in this table can be estimated through interpolation between
listed values.

11.1.1.3.

PGA Gain Control

The PGA amplification is common to both microphone input pins MIC-, MIC+, and enabled by PGAEN[2] address(0x02). It has a range of -12dB to +35.25dB in 0.75dB steps, controlled by PGAGAIN[5:0] address (0x2D). Input PGA
gain will not be used when ALC is enabled using ALCEN[8] address (0x20).

Feb 1, 2023

Page 17 of 101

Rev 1.9

Addr

Bit 8

Bit 7

Bit 6

Bit5

0x2D

0

PGAZC

PGAMT

0x20

ALCEN

0

0

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

PGAGAIN[5:0]
ALCMXGAIN[2:0]0x010
ALCMNGAIN[2:0]0x038Table 5: Registers associated with ALC and Input PGA Gain Control

11.1.2.

PGA Boost / Mixer Stage

The boost stage has two inputs connected to the PGA Boost Mixer. Both inputs can be individually connected or
disconnected from the PGA Boost Mixer. The boost stage can be enabled by setting BSTEN[4] address (0x02) to
HIGH. The following figure shows the PGA Boost stage.

PGABST[8] PGAMT[6](0x2F)(0x2D)
Output fromPGA Gain

To ADCPMICBSTGAIN[6:4](0x2F)
MIC+
Pin

Figure 4: Boost Stage Block Diagram
The signal from the PGA stage to the PGA Boost Mixer is disconnected or muted by setting PGAMT[6] address (0x2D)
to HIGH. In this path, the PGA boost can be a fixed value of +20dB or 0dB, controlled by the PGABST[8] address(0x2F) bit.

The signal from MIC+ pin to the PGA Boost Mixer is disconnected by setting ‘000’ binary value to PMICBSTGAIN[6:4]
address (0x2F) and any other combination connects the path.

Bit(s)

Addr

Parameter

Programmable Range

BSTEN[4]0x02Enable PGA Boost Block0 = Boost stage OFF
1 = Boost stage ON

PGAMT[6]0x2D

Mute control for input PGA

0=Input PGA not muted
1=Input PGA muted

PMICBSTGAIN[6:4]

0x2F

Boost MIC+ signal

Range: -12dB to +6dB @ 3dB increment

Feb 1, 2023

Page 18 of 101

Rev 1.9

Bit(s)Addr

PGABST[8]0x2F

Parameter

Programmable Range
0 = PGA output has +0dB
1 = PGA output has +20dB

Boost PGA stage

Table 6: Registers associated with PGA Boost Stage Control

11.2.

MICROPHONE BIASINGMICBIASM[0](0x28)VREF
MICBIASR

R

MICBIASV[1:0](0x2C)

Figure 5: Microphone Bias Schematic

The MICBIAS pin is a low-noise microphone bias source for an external microphone, and it can provide a maximum of
3mA of bias current. This DC bias voltage is suitable for powering either traditional ECM (electret) type microphones,
or for MEMS types microphones with an independent power supply pin. Seven different bias voltages are available for
optimum system performance, depending on the specific application. The microphone bias pin normally requires anexternal filtering capacitor as shown on the schematic in the Application section.
The output bias can be enabled by setting MICBIASEN[4] address (0x01) to HIGH. It has various voltage values
selected by a combination of bits MICBIASM[4] address (0x3A) and MICBIASV[8:7] address (0x2C).
The low-noise feature results in greatly reduced noise in the external MICBIAS voltage by placing an internal resistor
of approximately 200-ohms in series with the output pin. This creates a low pass filter in conjunction with the external
microphone-bias filter capacitor, but without any other additional external components.
Bit(s)Addr

MICBIASEN[4]0x01

Microphone bias enable

MICBIASM[4](0x3A)

Microphone bias mode selection

MICBIASV[8:7](0x2C)

Microphone bias voltage selection

Feb 1, 2023

Parameter

Page 19 of 101

Programmable Range
0 = Disable
1 = Enable

0 = Disable
1 = Enable

Rev 1.9

Table 7: Register associated with Microphone Bias

Below are the unloaded values when MICBIASM[4] is set to 1 and 0. When loaded, the series resistor will cause thevoltage to drop, depending on the load current.

Feb 1, 2023

Page 20 of 101

Rev 1.9

Microphone Bias Voltage Control
MICBIASV[8:7]

MICBIASM[4] = 0

MICBIASM[4]= 1

000.9* VDDA

0.85* VDDA

010.65* VDDA

0.60* VDDA

100.75* VDDA

0.70* VDDA

110.50* VDDA

0.50* VDDA

Table 8: Microphone Bias Voltage Control
11.3.

ADC DIGITAL FILTER BLOCKADC Digital Filters
ADC

DigitalDecimator

DigitalFilter/Gain

5-BandEqualizer

High
Pass
Filter

Notch
FilterDigital
Audio
Interface

Figure 6: ADC Digital Filter Path Block Diagram

The ADC digital filter block performs a 24-bit signal processing. The block consists of an oversampled analog sigmadelta modulator, digital decimator, digital filter, 5-band graphic equalizer, high pass filter, and a notch filter. For digitaldecimator and 5-band graphic equalizer details, refer to “Output Signal Path”. The oversampled analog sigma-delta
modulator provides a bit stream to the decimation stages and filter. The ADC coding scheme is in twos-complement
format, and the full-scale input level is proportional to VDDA. With a 3.3V supply voltage, the full-scale level is 1.0VRMS
and any voltage greater than full scale may overload the ADC and cause distortion. The ADC is enabled by setting
ADCEN[0] address (0x02) bit. Polarity and oversampling rate of the ADC output signal can be changed by ADCPL[0]address (0x0E) and ADCOS[3] address (0x0E) respectively.

Feb 1, 2023

Page 21 of 101

Rev 1.9

Bit(s)Addr

Parameter

Programmable Range

ADCPL[0]0x0E

ADCOS[3]0x0E

HPFEN[8]0x0E

HPFAM[7]0x0E

Audio or Application Mode

0 = Audio (1st order, fc ~ 3.7 kHz)
1 = Application (2nd order, fc =HPF)

HPF[6:4]

0x0E

High Pass Filter frequencies

82 Hz to 612 Hz depending on the sample
rate

ADCEN[0]0x02Enable ADC

0 = Disable
1 = Enable

SMPLR[3:1]0x07Sample rate

8k Hz to 48 kHz

0 = Normal
1 = Inverted

ADC Polarity

0=64x (Lowest power)
1=128x (best SNR at typical condition)

ADC Over Sample
Rate
High Pass Filter
Enable0 = Disable
1 = Enable

Table 9: Register associated with ADC
11.3.1. Programmable High Pass Filter (HPF)
The high pass filter (HPF) has two different operational modes set by bit HPFAM[7] at address (0x0E). In Audio Mode
(HPFAM=0), the filter is first order, with a cut-off frequency of 3.7Hz. In Application mode (HPFAM=1), the filter issecond order, with a cut-off frequency selectable via the HPF[2:0] register bits. Cut-off frequency of the HPF depends
on sample frequency selected by SMPLR[3:1] address (0x07). The HPF is enabled by setting HPFEN[8] address(0x0E) to HIGH. Table below shows the cut-off frequencies with different sampling rates.

HPF[2:0]8

SMPLR=101/100
11.02512

fs (kHz)SMPLR=011/010
16
22.05
24

SMPLR=001/000
32
44.1
48

000

82

113

122

82

113

122

82

113

122

001

102

141

153

102

141

153

102

141

153

010

131

180

156

131

180

156

131

180

156

011

163

225

245

163

225

245

163

225

245

100

204

281

306

204

281

306

204

281

306

101

261

360

392

261

360

392

261

360

392

110

327

450

490

327

450

490

327

450

490

111

408

563

612

408

563

612

408

563

612

Table 10: High Pass Filter Cut-off Frequencies (HPFAM=1)

Feb 1, 2023

Page 22 of 101

Rev 1.9

11.3.2. Programmable Notch Filter (NF)
The NAU8810 has a programmable notch filter which passes all frequencies except those in a stop band centered ona given center frequency. The filter gives lower distortion and flattens response. The notch filter is enabled by setting
NFCEN[7] address (0x1B) to HIGH. The variable center frequency is programmed by setting two’s complement values
to NFCA0[6:0] address (0x1C), NFCA0[13:7] address (0x1B) and NFCA1[6:0] address (0x1E), NFCA1[13:7] address(0x1D) registers. The coefficients are updated in the circuit when the NFCU[8] bit is set HIGH in a write to any of theregisters NF1-NF4 address (0x1B, 0x1C, 0x1D, 0x1E).

Addr

Bit 8

Bit 7

Bit 6

Bit5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

0x1B

NFCU

NFCEN

NFCA0[13:7]

0x000

0x1C

NFCU

0

NFCA0[6:0]

0x000

0x1D

NFCU

0

NFCA1[13:7]

0x000

0x1E

NFCU

0

NFCA1[6:0]0x000Table 11: Registers associated with Notch Filter Function

A0

CoefficientA1 2 π fb 
1 − tan  2 fs  2 π fb 
1 + tan  2 fs − (1 + A0 )

 2 π fc x cos fs

Notation

Register Value (DEC)fc = center frequency (Hz)fb = -3dB bandwidth (Hz)fs = sample frequency(Hz)

NFCA0 = -A0 x 213
NFCA1 = -A1 x 212(then convert to 2’scomplement)

Table 12: Equations to Calculate Notch Filter Coefficients
11.3.3. Digital ADC Gain Control
The digital ADC can be muted by setting “0000 0000” to ADCGAIN[7:0] address (0x0F). Any other combination digitallyattenuates the ADC output signal in the range -127dB to 0dB in 0.5dB increments].

Addr

Name

Bit 8

0x0F

ADCG

0

Bit 7

Bit 6

Bit5

Bit 4

Bit 3

Bit 2

ADCGAIN

Bit 1

Bit 0

Default
0x0FF

Table 13: Register associated with ADC GainFeb 1, 2023

Page 23 of 101

Rev 1.9

11.4. PROGRAMMABLE GAIN AMPLIFIER (PGA)
NAU8810 has a programmable gain amplifier (PGA) which controls the gain under program control, or automaticallysupporting either of these two features:

Automatic level control (ALC) or

Input peak limiter

The Automatic Level Control (ALC) seeks to control the PGA gain in response to the amplitude of the input signal suchthat the PGA output maintains a relatively constant level. The peak limiter simply prevents the output signal fromexceeding a specified level.

11.4.1.

Automatic level control (ALC)The ALC seeks to control the PGA gain such that the PGA output maintains a constant envelope. This helps to prevent
clipping at the input of the sigma delta ADC while maximizing the full dynamic range of the ADC. The ALC monitors
the output of the ADC, and adjusts the PGA gain as required. The ADC output is fed into a peak detector, which
updates the measured peak value whenever the absolute value of the input signal is higher than the current measured
peak.

The measured peak gradually decays to zero unless a new peak is detected, allowing for an accurate

measurement of the signal envelope. Based on a comparison between the measured peak value and the target value,
the ALC block adjusts the gain control, which is fed back to the PGA.

Rate Convert/ Decimator

Input
Pin

PGA

ADC

Sinc
FilterDigitalDecimator

DigitalFilter

ALC

Figure 7: ALC Block Diagram

The ALC is enabled by setting ALCEN[8] address (0x20) bit to HIGH. The ALC has two functional modes, which is set
by ALCM[8] address (0x22).
Normal mode (ALCM = LOW)

Peak Limiter mode (ALCM = HIGH)

When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must
be made by writing to the PGAGAIN[5:0] address (0x2D). A digital peak detector monitors the input signal amplitudeand compares it to a register defined threshold level ALCSL[3:0] address (0x21).

Feb 1, 2023

Page 24 of 101

Rev 1.9

Output Level

Blue
Green
Red

Input < noisegate threshold

Original Input signal (linear line from zero to maximum)
PGA gain value over time (inverse to signal in target range)
Output signal (held to a constant value in target range)

ALC operation range
Target ALCSL -6dB

Gain (Attenuation) Clipped
at ALCMNGAIN -12dB+33 dBPGA Gain
0 dB-12 dB

ALCNEN = 1
ALCNTH = -39dB
MIC Boost Gain = 0dB
ALCSL = -6dB
ALCMNGAIN = -12dB
ALCMXGAIN = +35.25dB

-39dB

-39dB

-6dB +6dB
Input Level

Figure 8: ALC Response Graph

The registers listed in the following section allow configuration of ALC operation with respect to:

ALC target level

Gain increment and decrement rates



Minimum and maximum PGA gain values for ALC operating range

Hold time before gain increments in response to input signal

Inhibition of gain increment during noise inputs

Limiter mode operation

Feb 1, 2023

Page 25 of 101

Rev 1.9

Bit(s)Addr

ALCMNGAIN[2:0]

Parameter

Programmable Range

Minimum Gain of PGA

Range: -12dB to +30dB @ 6dB increment

Maximum Gain of PGA

Range: -6.75dB to +35.25dB @ 6dB increment

ALCEN[8]Enable ALC function

0 = Disable
1 = Enable

ALCSL[3:0]

ALC Target

Range: -28.5dB to -6dB @ 1.5dB increment

ALC Hold Time

Range: 0ms to 1s, time doubles with every step)

ALCZC[8]ALC Zero Crossing

0 = Disable
1 = Enable

ALCATK[3:0]

ALC Attack time

ALCM=0 - Range: 125us to 128ms
ALCM=1 - Range: 31us to 32ms (time doubles withevery step)

ALC Decay time

ALCM=0 - Range: 500us to 512ms
ALCM=1 - Range: 125us to 128ms(Both ALC time doubles with every step)

ALC Select0 = ALC mode
1 = Limiter mode

ALCMXGAIN[2:0]

ALCHT[3:0]

0x20

0x21

0x22

ALCDCY[3:0]

ALCM[8]

Table 14: Registers associated with ALC Control

The operating range of the ALC is set by ALCMXGAIN[5:3] address (0x20) and ALCMNGAIN[2:0] address (0x20) bits
such that the PGA gain generated by the ALC is between the programmed minimum and maximum levels. When the
ALC is enabled, the PGA gain is disabled.

In Normal mode, the ALCMXGAIN bits set the maximum level for the PGA in the ALC mode but in the Limiter mode
ALCMXGAIN has no effect because the maximum level is set by the initial PGA gain setting upon enabling of the ALC.
ALCMAXGAIN

Maximum Gain (dB)

ALCMINGAIN

Minimum Gain (dB)

111
110

35.25
29.25

000
001

-12
-6

ALC Max Gain Range 35.25dB to -6dB @
6dB increments
001
000

ALC Min Gain Range -12dB to 30dB @
6dB increments

-0.75
-6.75

110
111

24
30

Table 15: ALC Maximum and Minimum Gain Values

Feb 1, 2023

Page 26 of 101

Rev 1.9

11.4.1.1.

Normal Mode

Normal mode is selected when ALCM[8] address (0x22) is set LOW and the ALC is enabled by setting ALCEN[8]address (0x20) HIGH. This block adjusts the PGA gain setting up and down in response to the input level. A peakdetector circuit measures the envelope of the input signal and compares it to the target level set by ALCSL[3:0] address(0x21). The ALC decreases the gain when the measured envelope is greater than the target and increases the gain
when the measured envelope is less than - 1.5dB. The following waveform illustrates the behavior of the ALC.

PGA Input

PGA Output

PGA Gain

Figure 9: ALC Normal Mode Operation

11.4.1.2.

ALC Hold Time (Normal mode Only)

The hold parameter ALCHT[3:0] configures the time between detection of the input signal envelope being outside of
the target range and the actual gain increase.

Input signals with different characteristics (e.g., voice vs. music) may require different settings for this parameter for
optimal performance. Increasing the ALC hold time prevents the ALC from reacting too quickly to brief periods ofsilence such as those that may appear in music recordings; having a shorter hold time, on the other hand, may be
useful in voice applications where a faster reaction time helps to adjust the volume setting for speakers with different
volumes. The waveform below shows the operation of the ALCHT parameter.

Feb 1, 2023

Page 27 of 101

Rev 1.9

PGA Input

PGA Output

PGA Gain
Hold Delay
ChangeFigure 10: ALC Hold Time11.4.2. Peak Limiter ModePeak Limiter mode is selected when ALCM[8] address (0x22) is set to HIGH and the ALC is enabled by setting
ALCEN[8] address (0x20). In limiter mode, the PGA gain is constrained to be less than or equal to the gain setting at
the time the limiter mode is enabled. In addition, attack and decay times are faster in limiter mode than in normal mode
as indicated by the different lookup tables for these parameters for limiter mode. The following waveform illustrates
the behavior of the ALC in Limiter mode in response to changes in various ALC parameters.

PGA Input

PGA
OutputPGA Gain
Limiter
EnabledFigure 11: ALC Limiter Mode Operations

Feb 1, 2023

Page 28 of 101

Rev 1.9

When the input signal exceeds 87.5% of full scale, the ALC block ramps down the PGA gain at the maximum attack
rate (ALCATK=0000), regardless of the mode and attack rate settings until the ADC output level has been reduced
below this threshold. This minimizes ADC clipping, if there is a sudden increase in the input signal level.

Feb 1, 2023

Page 29 of 101

Rev 1.9

11.4.3. Attack Time
When the absolute value of the ADC output exceeds the level set by the ALC threshold, ALCSL[3:0] address (0x21),
attack mode is initiated at a rate controlled by the attack rate register ALCATK[3:0] address (0x22). The peak detector
in the ALC block loads the ADC output value when the absolute value of the ADC output exceeds the current measured
peak; otherwise, the peak decays towards zero, until a new peak has been identified. This sequence is continuously
running. If the peak is ever below the target threshold, then there is no gain decrease at the next attack timer time; if it
is ever above the target-1.5dB, then there is no gain increase at the next decay timer time.
11.4.4. Decay Times
The decay time ALCDCY[6:4] address (0x22) is the time constant used when the gain is increasing. In limiter mode,
the time constants are faster than in ALC mode.
11.4.5. Noise gate (normal mode only)
A noise gate may be used to limit the ALC gain when there is no input signal, or a signal less than the noise gate
threshold. This noise from excess input gain, when there is no useful signal to amplify. The noise gate is enabled by
setting ALCNEN[3] address (0x23) to HIGH. It does not remove noise from the signal. The noise gate threshold
ALCNTH[2:0] address (0x23) is set to a desired level so when there is no signal or a very quiet signal (pause), whichis composed mostly of noise, the ALC holds the gain constant instead of amplifying the signal towards the target
threshold. The noise gate only operates in conjunction with the ALC and ONLY in Normal mode. The noise gate flagis asserted when
(Signal at ADC – PGA gain – MIC Boost gain) < ALCNTH (ALC Noise Gate Threshold) (dB)
Levels at the extremes of the range may cause inappropriate operation, so care should be taken when setting up thefunction.

PGA Input

PGA Output

PGA Gain

Figure 12: ALC Operation with Noise Gate disabled

Feb 1, 2023

Page 30 of 101

Rev 1.9

PGA Input

Noise Gate Threshold

PGA Output

PGA Gain

Figure 13: ALC Operation with Noise Gate Enabled
11.4.6. Zero Crossing
The PGA gain comes from either the ALC block when the ALC is enabled, or directly from the PGA gain register setting
when the ALC is disabled. Zero crossing detection may be enabled to force PGA gain changes to occur only at an
input zero crossing event. Enabling zero crossing detection limits clicks and pops that will occur if the gain changes
while the input signal is at a voltage that is significantly higher or lower than zero.

There are two zero crossing detection enables:Register ALCZC[8] address (0x21) – is only relevant when the ALC is enabled.

Register PGAZC[7] address (0x2D) – is only relevant when the ALC is disabled.

If the zero crossing function is enabled (using either register) and SCLKEN[0] address (0x07) is asserted, the zerocross timeout function may take effect. If the zero crossing flag does not change polarity within 0.25 seconds of a PGA
gain update (either via ALC update or PGA gain register update), then the gain will update automatically. This backup
system prevents the gain from locking up if the input signal has a small swing and/or a DC offset that prevents the zerocrossing flag from triggering.

Feb 1, 2023

Page 31 of 101

Rev 1.9

11.5.

DAC DIGITAL FILTER BLOCKDAC Digital Filters
Digital
Audio
Interface

DigitalGain

5-BandEqualizer

DigitalPeak
Limiter

DigitalFilters

Interpolation

Sigma
Delta
Modulator

DAC

Figure 14: DAC Digital Filter Path

The DAC digital block uses 24-bit signal processing to generate analog audio using data from the audio data bus orfrom the ADC output. This block consists of a sigma-delta modulator, 5-band graphic equalizer, high pass filter, digital
gain/filters, de-emphasis, and analog mixers. The DAC coding scheme is in twos complement format and the full-scale
output level is proportional to VDDA. With a 3.3V supply voltage, the full-scale output level is 1.0VRMS. The DAC isenabled by setting DACEN[0] address (0x03) bit HIGH.

Bit(s)

Addr

Parameter

Programmable Range

DACEN[0]0x03

DAC enable

0 = Disable
1 = Enable

ADDAP[0]0x05

Pass-through of ADC output data
into DAC input

0 = Disable
1 = Enable

DACPL[0]DAC Polarity

0 = No Inversion
1 = DAC Output Inverted

AUTOMT[2]Auto Mute

0 = Disable
1 = Enable

DEEMP[5:4]Sample Rate

32 kHz, 44.1 kHz, and 48 kHz

DACMT[6]Soft Mute

0 = Disable
1 = Enable

DAC Volume Control

Range: -127dB to 0dB @ 0.5dB
increment, 00 hex is Muted

DAC Limiter Attack

Range: 68us to 139ms

DAC Limiter Decay

Range: 544us to 1.1s

DAC Limiter Enable

0 = Disable
1 = Enable

DAC Limiter Volume Boost

Range: 0dB to +12dB @ 1dB increment

DAC Limiter Threshold

Range: -6dB to -1bB @ 1dB increment

0x0A

DACGAIN[7:0]0x0B

DACLIMATK[3:0]
DACLIMDCY[7:4]0x18

DACLIMEN[8]DACLIMBST[3:0]
DACLIMTHL[6:4]0x19Table 16: Registers associated with DAC Gain Control

Feb 1, 2023

Page 32 of 101

Rev 1.9

11.5.1.

DAC Soft Mute

The NAU8810 also has a Soft Mute function, which smoothly attenuates the volume of the digital signal to zero. When
un-muted, the gain will ramp back up to the register determined digital gain setting. This feature provides a tool that isuseful to enable/disable DAC output without introducing pop and click sounds. To output any DAC signal, Soft Mutemust be disabled by setting the DACMT[6] address (0x0A) bit to LOW.

11.5.2.

DAC Auto MuteThe output of the DAC can also be muted by the analog Auto Mute function. The Auto Mute function is enabled by
setting AUTOMT[2] address (0x0A) to HIGH and applied to the DAC output when there are 1024 or more consecutive
zeros at its input. If at any time there is a non-zero DAC input sample value, the DAC will be un-muted, and the 1024
count will be reinitialized to zero.

11.5.3.

DAC Sampling / Oversampling rate, Polarity, DAC Volume control and Digital Pass-throughThe sampling rate of the DAC is determined entirely by the frequency of its input clock and the oversampling ratesetting. The oversampling rate of the DAC can be changed to 64x or 128x. In the 128x oversampling mode, audio
performance is improved at slightly higher power consumption. Because the additional supply current is only 1mA, in
most applications, the 128x oversampling is preferred for maximum audio performance.
The polarity of the DAC output signal can be changed as a feature, and this can useful in management of the audio
phase. This feature can help minimize audio processing that may be otherwise required as the data are passed toother stages in the system.

The effective output audio volume of the DAC can be changed using the digital volume control feature. This processes
the output of the DAC to scale the output by the amount indicated in the volume register setting. Included is a “digitalmute” value which will completely mute the signal output of the DAC. The digital volume setting can range from 0dB
through -127dB in 0.5dB steps.

Digital audio pass-through allows the output of the ADC to be directly sent to the DAC as the input signal to the DAC
for DAC output. In this mode of operation, the external digital audio signal for the DAC will be ignored. The passthrough function is useful for many test and application purposes, and the DAC output may be utilized in any way thatis normally supported for the DAC analog output signals.

Feb 1, 2023

Page 33 of 101

Rev 1.9

11.5.4.

Hi-Fi DAC De-Emphasis and Gain Control

The NAU8810 has Hi-Fi DAC gain control for signal conditioning. The level of attenuation for an eight-bit code X isgiven by:

0.5 × (X-255) dB

for 1 ≤ X ≤ 255;

MUTE for X = 0

It includes on-chip digital de-emphasis and is available for sample rates of 32 kHz, 44.1 kHz, and 48 kHz. The digitalde-emphasis can be enabled by setting DEEMP[5:4] address (0x0A) bits depending on the input sample rate. The deemphasis feature is included to accommodate audio recordings that utilize 50/15 µs pre-emphasis equalization as ameans of noise reduction.

11.5.5.

Digital DAC Output Peak Limiter

Output Peak-Limiters optimize the dynamic range by ensuring the signal will not exceed a certain threshold, while
maximizing the RMS of the resulted audio signal, and minimizing audible distortions. NAU8810 has a digital output
limiter function. The operation of this is shown in figure below. In this diagram, the upper graph shows the envelopeof the input/output signals and the lower graph shows the gain characteristic. The limiter has a programmablethreshold, DACLIMTHL[6:4] address (0x19), which ranges from -1dB to -6dB in 1dB increments. The digital peak limiterseeks to keep the envelope of the output signal within the target threshold +/- 0.5dB. The attack and decay rates
programmed in registers DACLIMATK[3:0] address (0x18) and DACLIMDCY[7:4] address (0x18) specify how fast thedigital peak limiter decrease and increase the gain, respectively, in response to the envelope of the output signal fallingoutside of this range. In normal operation LIMBST=000 signals below this threshold are unaffected by the limiter.

DAC Input
Data

DAC Output
SignalThreshold
-1dB

0dB

Digital Gain

-0.5dB

Figure 15: DAC Digital Limiter Control

11.5.6.

Feb 1, 2023

-1dB

Volume Boost

Page 34 of 101

Rev 1.9

The limiter has programmable upper gain, which boosts signals below the threshold to compress the dynamic range ofthe signal and increase its perceived loudness. This operates as an ALC function with limited boost capability. The
volume boost is from 0dB to +12dB in 1dB steps, controlled by the DACLIMBST[3:0] register bits. The output limitervolume boost can also be used as a stand-alone digital gain boost when the limiter is disabled.

11.5.7.

5-Band Equalizer

NAU8810 features 5-band graphic equalizer with low distortion, low noise, and wide dynamic range, and is an ideal
choice for Hi-Fi applications. All five bands are fully parametric with independently adjustable bandwidth that displays
exceptional tonal qualities. Each of the five bands offers +/- 12dB of boost and cut with 1dB resolution. The five bands
are divided in to three sections Low, Mid and High bands. The High and the Low bands are shelving filters and the mid
three are peak filters. The equalizer can be applied to the ADC or DAC path under control of the EQM[8] address(0x12) register bit.

Bit(s)

Address

EQM[8]
EQ1CF[6:5]

Parameter

Programmable Range

Equalizer Enable
0x12Band 1 Cut-off Frequency

Range: 80 Hz to 175 Hz

EQ1GC[4:0]Band 1 Gain Control

Range: -12 dB to +12 dB@ 1.0dB increment

EQ2BW[8]Band 2 Equalizer Bandwidth

Narrow or Wide

Band 2 Centre Frequency

Range: 230 Hz to 500 Hz

EQ2GC[4:0]Band 2 Gain Control

Range: -12 dB to +12 dB@ 1.0dB increment

EQ2BW[8]Band 3 Equalizer Bandwidth

Narrow or Wide

Band 3 Centre Frequency

Range: 650 Hz to 1.4 kHz

EQ3GC[4:0]Band 3 Gain Control

Range: -12 dB to +12 dB@ 1.0dB increment

EQ4BW[8]Band 4 Equalizer Bandwidth

Narrow or Wide

Band 4 Centre Frequency

Range: 1.8 kHz to 4.1 kHz

Band 4 Gain Control

Range: -12 dB to +12 dB@ 1.0dB increment

Band 5 Cut-off Frequency

Range: 5.3 kHz to 11.7 kHz

Band 5 Gain Control

Range: -12 dB to +12 dB@ 1.0dB increment

EQ2CF[6:5]

EQ3CF[6:5]

EQ4CF[6:5]

0x13

0x14

0x15

EQ4GC[4:0]
EQ5CF[6:5]
0x16
EQ5GC[4:0]

Table 17: Registers associated with Equalizer Control

Feb 1, 2023

Page 35 of 101

Rev 1.9

11.6. ANALOG OUTPUTSThe NAU8810 features two different types of outputs, a single-ended or differential Mono output (MOUT) and adifferential speaker outputs (SPKOUT+ and SPKOUT-). The speaker amplifiers designed to drive a load differentially;a configuration referred to as Bridge-Tied Load (BTL).

MOUTBST[3](0x31)
Output from
Auxiliary Amplifier

VDDSPK

MOUTMXEN[3](0x03)DACOUT[0](0x38)MOUTDAC Output
MONO
MIXER

MOUTBST GAIN
0
1.0x
1
1.5x

DC output
1.0 x VREF
1.5 x VREF

-10dB or +0dB
SIDETONE
Output from PGA BoostVSSSPKVDDSPK

Zero Cross
Detection
SPEAKERMIXER-1SPKOUTSPKBST GAIN
1.0x
0
1.5x
1

DC output
1.0 x VREF
1.5 x VREF

SPKOUT+-10dB or 0dB
SPKMXEN[2](0x03)
Zero Cross
Detection
BufferSPKVOL[5:0](0x36)SPKBST[2](0x31)VSSSPK

Figure 16: Speaker and MONO Analogue Outputs [To Update ? output from Auxilliary Amplifier]

Important: For analog outputs depopping purpose, when powering up speakers, headphone,
AUXOUTs, certain delays are generated after enabling sequence. However, the delays are created by
MCLK and sample rate register. For correct operation, sending I2S signal no earlier than 250ms after
speaker or headphone enabled and MCLK appearing
11.6.1.

Speaker Mixer Outputs

The speaker amplifiers are designed to drive a load differentially; a configuration referred to as Bridge-Tied Load (BTL).
The differential speaker outputs can drive a single 8Ω speaker or two headphone loads of 16Ω or higher, including
differential line output applications. Driving the load differentially doubles the output voltage. The output of the speakercan be manipulated by changing attenuation and the volume (loudness of the output signal).

The output stage is powered by the speaker supply, VDDSPK, which are capable of driving up to 1.5VRMS signals(equivalent to 3VRMS into a BTL speaker). The speaker outputs can be controlled and can be muted individually. The
output pins are at reference DC level when the output is muted.

Feb 1, 2023

Page 36 of 101

Rev 1.9

Bit(s)Addr

Parameter

Programmable Range

SPKMXEN[2]0x03

Speaker Mixer enable

0 – Disabled
1 – Enabled

PSPKEN[5]0x03

Speaker positive terminal
enable0 – Disabled
1 – Enabled

NSPKEN[6]0x03

Speaker negative terminal
enable0 – Disabled
1 – Enabled

SPKATT[1]0x28

Speaker output attenuation0 - 0dB
1 - -10dB

SPKBST[2]0x31

Speaker output Boost

0 – (1.0x VREF) Boost
1- (1.5 x VREF) BoostSPKGAIN[5:0]0x36

Speaker output Volume

Range: -57dB to +6dB @ 6dB increment

SPKMT[6]0x36Speaker output Mute

0 – Speaker Enabled
1 – Speaker Muted

Table 18: Speaker Output Controls

11.6.2. Mono Mixer Output
The single ended output can drive headphone loads of 16Ω or 32Ω or a line output. The MOUT can be manipulated
by changing attenuation and the volume (loudness of the output signal).

The output stage is powered by the speaker supply, VDDSPK, which are capable of driving up to 1.5VRMS signals. The
Mono output can be enabled for signal output or muted. The output pins are at reference DC level when the output ismuted.

Bit(s)

Addr

Parameter

Programmable Range

MOUTMXEN[3]0x03

MONO mixer enable

0 – Disabled
1 – Enabled

MOUTEN[7]0x03

MONO output enable

0 – Disabled
1 – Enabled

MOUTATT[2]0x28

MONO output attenuation0 - 0dB
1 - -10dB

MOUTBST[3]0x31

MONO output boost

0 – (1.0x VREF) Boost
1 - (1.5 x VREF) Boost

MOUTMXMT[6]0x38MONO Output Mixer Mute0 – MONO Mixer Normal Mode1 – MONO Mixer Muted

MOUTMT[4]0x45

MONO Output Mute0 – MONO Output Normal Mode1 – MONO Output Muted

Table 19: MONO Output Controls

Feb 1, 2023

Page 37 of 101

Rev 1.9

11.6.3. Differential Output Configuration
The NAU8810 features two different types of outputs, a single-ended or differential Mono output (MOUT) and adifferential speaker output (SPKOUT+ and SPKOUT-). The speaker amplifiers are designed to drive a load differentially
as Bridge-Tied Load (BTL).

Three differential output options can be configured from the three output pins: MOUT, SPKOUT+ and SPKOUT-. To
enable differential outputs, three registers need to be configured accordingly: SPK2MOUT=1 (0x45[5]), AOUTMP=1(0x31[0]) and 0x4F=0x100.
-

Option 1: Two differential outputs by using pair of MOUT and SPKOUT-, SPKOUT+ and SPKOUT- for driving both
headphone/earpiece and Speaker. Register setting: MOUTEN=1, NSPKEN=1, and PSPKEN =1-

Option 2: One differential output by using MOUT and SPKOUT- for driving headphone/earpiece. Register setting:
MOUTEN=1, NSPKEN=1, and PSPKEN =0-

Option 3: One differential output by using SPKOUT+ and SPKOUT- for driving speaker. Register setting:
MOUTEN=0, NSPKEN=1 and PSPKEN =1

11.6.4. Unused Analog I/O

Feb 1, 2023

Page 38 of 101

Rev 1.9

SMOUT[3](0x4F)MIC-

MOUTBST[3] = 1(0x31)30k

1K

NMICPGA[1](0x2C)
MIC+

MOUT
30K

40k

PMICPGA[0](0x2C)MOUTBST[3] = 0(0x31)SPSPK[4](0x4F)
1.0 x VREF

1K

VREF

SPKOUT+
SBUFL[6](0x4F)DCBUFEN[8](0x01)

SBUFH[7](0x4F)SNSPK[5](0x4F)SPKBST[2] = 0(0x31)IOBUFEN[2](0x01)SPKBST[2] = 1(0x31)

30K

1K

SPKOUT-

1.5 x VREF
30K

AOUTIMP[0](0x31)

R

R

Figure 17: Tie-off Options for the Speaker and MONO output Pins

In audio and voice systems, any time there is a sudden change in voltage to an audio signal, an audible pop or clicksound may be the result. Systems that change inputs and output configurations dynamically, or which are required to
manage low power operation, need special attention to possible pop and click situations. The NAU8810 includes many
features, which may be used to greatly reduce or eliminate pop and click sounds. The most common cause of a pop
or click signal is a sudden change to an input or output voltage. This may happen either in a DC coupled system, or inan AC coupled system.

The strategy to control pops and clicks is similar for both a DC coupled system and an AC coupled system. The caseof the AC coupled system is the most common and the more difficult situation, and therefore, the AC coupled case willbe the focus for this information section. When an input or output pin is being used, the DC level of that pin will be very
close to half of the VDDA voltage that is present on the VREF pin. The only exception is that when outputs are operated
in the 5-Volt mode known as the 1.5x boost condition, then the DC level for those outputs will be equal to 1.5xVREF.
In all cases, any input or output capacitors will become charged to the operating voltage of the used input or output pin.

Feb 1, 2023

Page 39 of 101

Rev 1.9

The goal to reduce pops and clicks is to insure that the charge voltage on these capacitors does not change suddenly
at any time.

When an input or output is in a not-used operating condition, it is desirable to keep the DC voltage on that pin at thesame voltage level as the DC level of the used operating condition. This is accomplished using special internal DC
voltage sources that are at the required DC values. When an input or output is in the not-used condition, it is connectedto the correct internal DC voltage as not to have a pop or click. This type of connection is known as a “tie-off” condition.

Two internal DC voltage sources are provided for making tie-off connections. One DC level is equal to the VREF
voltage value, and the other DC level is equal to 1.5x the VREF value. All inputs are always tied off to the VREF voltage
value. Outputs will automatically be tied to either the VREF voltage value or to the 1.5xVREF value, depending on thevalue of the “boost” control bit for that output. That is to say, when an output is set to the 1.5x gain condition, then thatsame output will automatically use the 1.5xVREF value for tie-off in the not-used condition. The input pull-ups areconnected to IOBUFEN[2] address (0x01) buffer with a voltage source (VREF). The output pull-ups can be connected
two different buffers depending on the voltage source. IOBUFEN[2] address (0x01) buffer is enabled if the voltage
source is (VREF) and DCBUFEN[8] address (0x01) buffer is enabled if the voltage source is (1.5 x VREF). IOBUFEN[2]address (0x01) buffer is shared between input and output pins.

To conserve power, these internal voltage buffers may be enabled/disabled using control register settings. To better
manage pops and clicks, there is a choice of impedance of the tie-off connection for unused outputs. The nominal
values for this choice are 1kΩ and 30kΩ. The low impedance value will better maintain the desired DC level in thecase when there is some leakage on the output capacitor or some DC resistance to ground at the NAU8810 output pin.
A tradeoff in using the low-impedance value is primarily that output capacitors could change more suddenly during
power-on and power-off changes.

Automatic internal logic determines whether an input or output pin is in the used or un-used condition. This logic
function is always active. An output is determined to be in the un-used condition when it is in the disabled unpowered
condition, as determined by the power management registers. An input is determined to be in the un-used condition
when all internal switches connected to that input are in the “open” condition.

Feb 1, 2023

Page 40 of 101

Rev 1.9

11.7. GENERAL PURPOSE CONTROL
11.7.1. Slow Timer Clock

Addr

D8

D7

D6

D5

D4

0x07

0

0

0

0

0

D3

D2

D1

SMPLR[2:0]D0Default

SCLKEN 0x000

Table 20: General Purpose Control
An internal Slow Timer Clock is supplied to automatically control features that happen over a relatively long period oftime, or time-spans. This enables the NAU8810 to implement long time-span features without any host/processor
management or intervention.

The Slow Timer Clock supports automatic time out for the zero-crossing holdoff of PGA volume changes. If this featureis required, the Slow Timer Clock must be enabled. The Slow Timer Clock is initialized in the disabled state.

The Slow Timer Clock rate is derived from MCLK using an integer divider that is compensated for the sample rate as
indicated by the register address (0x07). If the sample rate register value precisely matches the actual sample rate,then the internal Slow Timer Clock rate will be a constant value of 128ms. If the actual sample rate is, for example,
44.1kHz and the sample rate selected in register 0x07 is 48kHz, the rate of the Slow Timer Clock will be approximately
10% slower in direct proportion of the actual vs. indicated sample rate. This scale of difference should not be importantin relation to the dedicated end uses of the Slow Timer Clock.
11.8.

CLOCK GENERATION BLOCKADCOS[3](0x0E)f1

MCLK

MCLKSEL[7:5](0x06)fPLL

PLLMCLK[4](0x24)

PLL1
R=f2/f1

f2

IMCLK

f/N

f/4

f/N

ADC

f/N

DAC

f/2
DACOS[3](0x0A)

CLKM[8](0x06)PLL BLOCKBCLKSEL[4:2](0x06)

GPIO1
/CSb

…

IMCLK/NIMCLK/
256

CLKIOEN[0](0x06)

f/N
Digital Audio
InterfaceFS
BCLK

GPIO1PLL[5:4](0x08)
GPIO1SEL[2:0](0x08)

Figure 18: PLL and Clock Select Circuit

Feb 1, 2023

Page 41 of 101

Rev 1.9

The NAU8810 has two basic clock modes that support the ADC and DAC data converters. It can accept external clocks
in the slave mode, or in the master mode, it can generate the required clocks from an external reference frequency
using an internal PLL (Phase Locked Loop). The internal PLL is a fractional type scaling PLL, and therefore, a very
wide range of external reference frequencies can be used to create accurate audio sample rates.

Separate from this ADC and DAC clock subsystem, audio data are clocked to and from the NAU8810 by means of thecontrol logic described in the Digital Audio Interfaces section. The Frame Sync (FS) and Bit Clock (BCLK) pins in the
Digital Audio Interface manage the audio bit rate and audio sample rate for this data flow.

It is important to understand that the Digital Audio Interface does not determine the sampling rate for the ADC and DAC
data converters, and instead, this rate is derived exclusively from the Internal Master Clock (IMCLK). It is therefore arequirement that the Digital Audio Interface and data converters be operated synchronously, and that the FS, BCLK,
and IMCLK signals are all derived from a common reference frequency.

If these three clocks signals are notsynchronous, audio quality will be reduced.

The IMCLK is always exactly 256 times the sampling rate of the data converters. IMCLK is output from the Master
Clock Prescaler. The prescaler reduces by an integer division factor the input frequency input clock. The source of
this input frequency clock is either the external MCLK pin, or the output from the internal PLL Block.
Addr

D8

D7

D6

D5

D4

0x01

DCBUFEN0

PLLEN

MICBIASEN

0x06

CLKM

0x07

0

0

0

0

0

0x24

0

0

0

0

PLLMCLK

0x25

0

0

0

MCLKSEL[2:0]

D3

D2

D1

ABIASEN IOBUFENBCLKSEL[2:0]

PLLN[3:0]
PLLK[23:18]

Default

REFIMP0

SMPLR[2:0]

D0

CLKIOEN

0x140

SCLKEN

0x000
0x008
0x00C

0x26

PLLK[17:9]

0x093

0x27

PLLK[8:0]

0x0E9Table 21: Registers associated with PLL

In Master Mode, the IMCLK signal is used to generate FS and BCLK signals that are driven onto the FS and BCLK
pins and input to the Digital Audio Interface. FS is always IMCLK/256 and the duty cycle of FS is automatically adjusted
to be correct for the mode selected in the Digital Audio Interface. The frequency of BCLK may optionally be divided to
optimize the bit clock rate for the application scenario.

In Slave Mode, there is no connection between IMCLK and the FS and BCLK pins. In this mode, FS and BLCK are
strictly input pins, and it is the responsibility of the system designer to insure that FS, BCLK, and IMCLK aresynchronous and scaled appropriately for the application.

Feb 1, 2023

Page 42 of 101

Rev 1.9

11.8.1.

Phase Locked Loop (PLL) General description

The PLL may be optionally used to multiply an external input clock reference frequency by a high resolution fractional
number. To enable the use of the widest possible range of external reference clocks, the PLL block includes an optional
divide-by-two prescaler for the input clock, a fixed divide-by-four scaler on the PLL output, and an additional
programmable integer divider that is the Master Clock Prescaler.

The high resolution fraction for the PLL is the ratio of the desired PLL oscillator frequency (f2), and the reference
frequency at the PLL input (f1). This can be represented as R = f2/f1, with R in the form of a decimal number:
xy.abcdefgh. To program the NAU8810, this value is separated into an integer portion (“xy”), and a fractional portion,“abcdefgh”. The fractional portion of the multiplier is a value that when represented as a 24-bit binary number (stored
in three 9-bit registers on the NAU8810), very closely matches the exact desired multiplier factor.

To keep the PLL within its optimal operating range, the integer portion of the decimal number (“xy”), must be any of thefollowing decimal values: 6, 7, 8, 9, 10, 11, or 12. The input and output dividers outside of the PLL are often helpful toscale frequencies as needed to keep the “xy” value within the required range. Also, the optimum PLL oscillator
frequency is in the range between 90MHz and 100MHz, and thus, it is best to keep f2 within this range.
In summary, for any given design, choose:

Equations

Description

IMCLK = (256) * (desired codec
sample rate)

IMCLK = desired Master Clockf2 = (4 * P * IMCLK)

where P is the Master Clock divider
integer value;
optimal f2: 90MHz< f2 <100MHz

f1 = (MCLK / D)where D is the PLL Prescale factor of 1,
or 2, and MCLK is the frequency at the
MCLK pin

R = f2 / f1 = xy.abcdefgh decimalvaluewhich is the fractional frequency
multiplication factor for the PLL

N = xytruncated integer portion of the R value
and limited to decimal value 6, 7, 8, 9,
10, 11, or 12

K = (224) * (0.abcdefgh)rounded to the nearest whole integer
value then converted to a binary 24-bit
value

Notes

The integer values for D and P
are chosen to keep the PLL in its
optimal operating range. It may
be best to assign initial values of
1 to both D and P, and then byinspection, determine if theyshould be a different value.

Table 22: Registers associated with PLL

Feb 1, 2023

Page 43 of 101

Rev 1.9

11.8.2.

Phase Locked Loop (PLL) Design Example

In an example application, a desired sample rate for the DAC is known to be 48.000kHz. Therefore, it is also known
that the IMCLK rate will be 256fs, or 12.288MHz. Because there is a fixed divide-by-four scaler on the PLL output, thenthe desired PLL oscillator output frequency will be 49.152MHz.

In this example system design, there is any an available 12.000MHz clock from the USB subystem. To reduce systemcost, this clock will also be used for audio. Therefore, to use the 12MHz clock for audio, the desired fractional multiplier
ratio would be R = 49.152/12.000 = 4.096. This value, however, does not meet the requirement that the “xy” whole
number portion of the multiplier be in the inclusive range between 6 and 12. To meet the requirement, the Master Clock
Prescaler can be set for an additional divide-by-two factor. This now makes the PLL required oscillator frequency
98.304 MHz, and the improved multiplier value is now R = 98.304/12.000 = 8.192.

To complete this portion of the design example, the integer portion of the multiplier is truncated to the value, 8 and thefractional portion is multiplied by 224, as to create the needed 24-bit binary fractional value. The calculation for this is:(224)(0.192) = 3221225.472.

It is best to round this value to the nearest whole value of 3221225, or hexadecimal 0x3126E9.

Below are additional examples of results for this calculation applied to commonly available clock frequencies anddesired IMCLK 256fs sample rates.

MCLK
(MHz)

DesiredOutput(MHz)

Input
Frequency
(f1)

f2
(MHz)

MCLK
Divider
bits

R

N
(Hex)

K (Hex)12.0

11.28960

MCLK/190.3168

fPLL/2

7.526400

712.0

12.28800

MCLK/198.3040

fPLL/2

8.192000

14.4

11.28960

MCLK/190.3168

fPLL/2

14.4

12.28800

MCLK/198.3040

19.2

11.28960

MCLK/2

19.2

12.28800

19.8

Actual Register Setting
PLLK[23:18]

PLLK[17:9]

PLLK[8:0]

86C226

21

161

26

8

3126E90C

93

E96.272000

6

45A1CA

11

D0

1CA

fPLL/26.826667

6

D3A06D

34

1D0

6D

90.3168

fPLL/29.408000

96872B01A

39

B0

MCLK/298.3040

fPLL/2

10.240000

10

3D70A30F

B8

A3

11.28960

MCLK/290.3168

fPLL/2

9.122909

9

1F76F8

07

1BB

F8

19.8

12.28800

MCLK/298.3040

fPLL/2

9.929697

9EE009E

3B

100

9E

24.0

11.28960

MCLK/290.3168

fPLL/2

7.526400

7

86C226

21

161

26

24.0

12.28800

MCLK/298.3040

fPLL/2

8.19200083126E9

0C

93

E9

26.0

11.28960

MCLK/290.3168

fPLL/2

6.9474466F28BD4

3C

145

1D4

26.0

12.28800

MCLK/298.3040

fPLL/27.56184678FD526

23

1EA

126

Table 23: PLL Frequency Examples

Feb 1, 2023

Page 44 of 101

Rev 1.9

11.9.

CONTROL INTERFACEThe NAU8810 features a 2-Wire control interface compatible with industry I2C serial bus protocol using a bidirectional
data signal (SDIO) and a clock signal (SCLK).

11.9.1.

2-WIRE Serial Control (I2C Style Interface)

The NAU8810 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto thebus as a transmitter and the receiving device as the receiver. Therefore, the 2-Wire operates as slave interface. All
communication over the 2-Wire interface is conducted by sending the MSB of each byte of data first.

11.9.1.1.

2-WIRE Protocol Convention

All 2-Wire interface operations must begin with a START condition, which is a HIGH to LOW transition of SDIO while
SCLK is HIGH. All 2-Wire and all interface operations are terminated by a STOP condition, which is a LOW to HIGHtransition of SDIO while SCLK is HIGH. A STOP condition at the end of a write operation places the device in standby
mode. An acknowledge (ACK), is a software convention used to indicate a successful data transfer. The transmitting
device, either master or slave, releases the SDIO bus after transmitting eight bits. During the ninth clock cycle, thereceiver pulls the SDIO line LOW to acknowledge the reception of the eight bits of data.

Following a START condition, the master must output a device address byte. The 7-MSB bits “0011010” are the device
address. The LSB of the device address byte is the R/W bit and defines a (R/W = 0) or write (R/W = 1) operation.
When this, R/W, bit is a “1”, then a operation is selected and when “0” the device selects a write operation. The device
outputs an acknowledge LOW for a correct device address and HIGH for an incorrect device address on the SDIO pin.

SCLK

SCLK

SDIO
Receive

SDIO

9th
Clock

SCLK

ACK

SDIO
START

SDIO
Transmit

STOP

Figure 19: Valid START Condition

Feb 1, 2023

Figure 20: Valid Acknowledge

Page 45 of 101

Figure 21: Valid STOP Condition

Rev 1.9

0

0

1

1

0

1

0

R/W

DeviceAddress Byte

A6

A5

A4

A3

A2

A1

A0

Write - D8
Read - 0

Control
Address Byte

D7

D6

D5

D4

D3

D2

D1

D0

Data Byte

Figure 22: Slave Address Byte, Control Address Byte, and Data Byte

11.9.1.2.

2-WIRE Write Operation

A Write operation consists of a two-byte instruction followed by one or more Data Bytes. A Write operation requires a
START condition, followed by a valid device address byte, a valid control address byte, data byte(s), and a STOP
condition. After each three bytes sequence, the NAU8810 responds with an ACK and the 2-Wire interface enters astandby state.

SCLK

0

SDIO

0

1

1

0

1

0

0

S
T
A
R
T

A6

A5 A4 A3 A2 A1 A0

ACKDevice Address

= 34h

R/W

D8

D7 D6 D5 D4 D3 D2

S
A
C

A
C
K
Control Register Address

D1 D0

K

T
O
P

9-bit Data Byte

Figure 23: Byte Write Sequence
11.9.1.3.

2-WIRE Operation

A 2-wire read operation consists of a three-byte instruction followed by one or more Data Bytes. The master initiates
the operation issuing the following sequence: a START condition, device address byte with the R/W bit set to “0”, acontrol address byte, a second START condition, and a second device address byte with the R/W bit set to “1”.

After each of the three bytes, the NAU8810 responds with an ACK. Then the NAU8810 transmits Data Bytes as longas the master responds with an ACK during the SCLK cycle following the ninth bit of each byte. The master terminates
the operation (issuing a STOP condition) following the last bit of the last Data Byte.

After reaching the memory location 7Fh the pointer “rolls over” to 00h, and the device continues to output data for each
ACK received.

Feb 1, 2023

Page 46 of 101

Rev 1.9

SCLK

0
S
T
A
R
T

0

1

1

0

1

Device Address = 34h

00

A6 A5 A4 A3 A2 A1 A0
A
C
K

0

0
A
C
K

Control Register Address

0

0

0

0

0

0

0

D8

S
T
A
R
T

0

1
ND

2

1

0

1

0

1

Device Address = 35h

ACK

D7 D6 D5 D4 D3 D2 D1 D0
ACK

16-bit Data

N
A
C
K

S
T
O
P

Figure 24: 2-Wire Read Sequence

11.10.

DIGITAL AUDIO INTERFACES

NAU8810 only uses the Left channel to transfer data in normal mode. It supports an independent digital interface forvoice and audio. The digital interface is used to input digital data to the DAC, or output digital data from the ADC.
The digital interface can be configured to Master mode or Slave mode.

Master mode is configured by setting CLKIOEN[0] address (0x06) bit to HIGH. The main clock (MCLK) of the digitalinterface is provided from an external clock either from a crystal oscillator or from a microcontroller. With an appropriate
MCLK, the device generates bit clock (BCLK) and frame sync (FS) internally in the master mode. By generating the
bit clock and frame sync internally, the NAU8810 has full control of the data transfer.

Slave mode is configured by setting CLKIOEN[0] address (0x06) bit to LOW. In this mode, an external controller has
to supply the bit clock and the frame sync. The NAU8810 uses ADCOUT, DACIN, FS, and BCLK pins to control thedigital interface. Care needs to be exercised when designing a system to operate the NAU8810 in this mode as therelationship between the sample rate, bit clock, and frame sync needs to be controlled by other controller. In bothmodes of operation, the internal MCLK and MCLK prescalers determine the sample rate for the DAC and ADC.

The output state of the ADCOUT pin by default is pulled-low. Depending on the application, the output can be
configured to be Hi-Z, pull-low, pull-high, Low or High. To configure the output, three different bits have to be set. Firstthe output switched to the mask by setting PUDOEN[5] address (0x3C), then the mask has to be enabled be setting
PUDPE[4] address (0x3C) and finally output state select pulled up or down by PUDPS[3] address (0x3C). Six different
audio formats are supported by NAU8810 with MSB first and they are as follows.

Feb 1, 2023

Page 47 of 101

Rev 1.9

AIFMT[4]Addr: (0x04)
0

AIFMT[3]Addr: (0x04)
0

PCMTSEN[8]Addr: (0x3C)
0PCMB[1]
Addr: (0x3C)
0Right Justified

0

1

0

0

Left Justified

1

0

0

0

I2 S

1

1

0

0

PCM A

1

1

0

1

PCM B

1

1

1

Don’t Care

PCM Mode

PCM Time Slot

Table 24: Standard Interface modes

Addr

D8

D7

D6

D5

0x04

BCLKP

FSP

WLEN[1:0]

0x06

CLKM

D4

D3

AIFMT[1:0]

MCLKSEL[2:0]

D2

D1

DACPHS ADCPHSBCLKSEL[2:0]

0x3B

0

TSLOT[8:0]0x3C PCMTSEN

TRI

PCM8BIT PUDOEN

PUDPE

D0

Default

00x050

CLKIOEN

0x140
0x000

PUDPS

LOUTR

PCMB

TSLOT[9:8] 0x000

Table 25: Audio Interface Control Registers
11.10.1.

Right Justified audio dataIn right justified interface (normal mode), the left channel serial audio data is synchronized with the frame sync. Leftchannel data is transferred during the HIGH frame sync. The MSB data is sampled first. The data is latched on thelast rising edge of BCLK before frame sync transition (FS). The LSB is aligned with the falling edge of the frame sync
signal (FS). Right justified format is selected by setting AIFMT[1:0] address (0x04) to “00” binary in conjunction with
PCMTSEN[8] address (0x3C) set to LOW.

FS

LEFT CHANNELRIGHT CHANNELBCLKDACIN/ADCOUT

1

2

N-1 N

MSB

LSB

Figure 25: Right Justified Audio Interface (Normal Mode)

NAU8810 features a special mode where the device outputs Left channel data to both Left and Right channels. Thisis accomplished by setting LOUTR[2] address (0x3C) to “1”

Feb 1, 2023

Page 48 of 101

Rev 1.9

FS

LEFT CHANNELRIGHT CHANNELBCLKADCOUT

1

2

N-1 N

MSB

LSB

1

2

MSB

N-1 N
LSB

Figure 26: Right Justified Audio Interface (Special mode)
11.10.2.

Left Justified audio data

In Left justified interface (normal mode), the left channel serial audio data is synchronized with the frame sync. Leftchannel data is transferred during the HIGH frame sync. The MSB data is sampled first and is available on the firstrising edge of BCLK following a frame sync transition (FS). Left justified format is selected by setting AIFMT[1:0]
address (0x04) to “01” binary in conjunction with PCMTSEN[8] address (0x3C) set to LOW.

FS

LEFT CHANNELRIGHT CHANNELBCLKDACIN/ADCOUT

1
MSB

2

N-1 N
LSB

Figure 27: Left Justified Audio Interface (Normal Mode)

NAU8810 features a special mode where the device outputs Left channel data to both Left and Right channels. Thisis accomplished by setting LOUTR[2] address (0x3C) to “1”

Feb 1, 2023

Page 49 of 101

Rev 1.9

FS

LEFT CHANNELRIGHT CHANNELBCLKADCOUT

1

2

1

N-1 N

MSB

2

N-1 N

MSB

LSB

LSB

Figure 28: Left Justified Audio Interface (Special mode)

11.10.3.

I2S audio data

In I2S interface (normal mode), the left channel serial audio data is synchronized with the frame sync. Left channel
data is transferred during the LOW frame sync. The MSB data is sampled first. The data is latched on the second
rising edge of BCLK following a frame sync transition (FS). I2S format is selected by setting AIFMT[1:0] address (0x04)
to “10” binary in conjunction with PCMTSEN[8] address (0x3C) set to LOW.

FS

LEFT CHANNELRIGHT CHANNELBCLKDACIN/ADCOUT

1
MSB

2

N-1 N
LSB

1 BCLK

Figure 29: I2S Audio Interface (Normal Mode)

NAU8810 features a special mode where the device outputs Left channel data to both Left and Right channels. Thisis accomplished by setting LOUTR[2] address (0x3C) to “1”

Feb 1, 2023

Page 50 of 101

Rev 1.9

FS

LEFT CHANNELRIGHT CHANNELBCLKADCOUT

1

1

N-1 N

2

N-1 N

MSB

LSB

MSB

2

LSB

1 BCLK

1 BCLK

Figure 30: I2S Audio Interface (Special mode)

11.10.4.

PCM audio data

In PCM interface (normal mode), the left channel serial audio data is synchronized with the frame sync. Left channel
data is transferred during the LOW frame sync. The MSB data is sampled first. The data is latched on the second
rising edge of BCLK following a frame sync transition (FS). PCM format is selected by setting AIFMT[4:3] address(0x04) to “11” binary in conjunction with PCMTSEN[8] address (0x3C) set to LOW.
The digital data can be forced to appear on the right phase of the FS by setting ADCPHS[0] and DACPHS[1] address(0x04) bits to HIGH respectively. The starting point of the right phase data depends on the word length WLEN[6:5]
address (0x04) after the frame sync transition (FS).

1 BCLKFS

LEFT CHANNELBCLKDACIN/ADCOUT

1
MSB

2

N-1 N
LSB

Word Length, WLEN[6:5]

Figure 31: PCM Mode Audio Interface (Normal Mode)

NAU8810 features a special mode where the device outputs Left channel data to both Left and Right channels. Thisis accomplished by setting LOUTR[2] address (0x3C) to “1”

Feb 1, 2023

Page 51 of 101

Rev 1.9

1 BCLKFSLEFT CHANNELRIGHT CHANNELBCLKADCOUT

1

2

N-1 N

1

LSB

MSB

MSB

Word Length, WLEN[6:5]

2

N-1 N
LSB

Word Length, WLEN[6:5]

Figure 32: PCM Mode Audio Interface (Special mode)
11.10.5.

PCM Time Slot audio data

In PCM Time-Slot interface (normal mode), the left channel serial audio data is synchronized with the frame sync. Leftchannel data is transferred during the LOW frame sync. The MSB data is sampled first. The starting point of thetimeslot is controlled by a 10-bit byte TSLOT[9:0] address (0x3B and 0x3C). The data is latched on the first rising edgeof BCLK following a frame sync transition (FS) providing PCM is in timeslot zero (TSLOT[9:0] = 000). PCM Time-Slotformat is selected by setting AIFMT[4:3] address (0x04) to “11” binary in conjunction with PCMTSEN[8] address (0x3C)
set to HIGH. The digital data can be forced to appear on the right phase of the FS by setting ADCPHS[0] andDACPHS[1] address (0x04) bits to HIGH respectively. The starting point of the right phase data depends on the word
length WLEN[6:5] address (0x04) and timeslot assignment TSLOT[9:0] address (0x3B and 0x3C) after the frame synctransition (FS). DACIN will return to the bus condition either on the negative edge of BCLK during the LSB, or on thepositive edge of BCLK following the LSB depending on the setting of TRI[7] address (0x3C). Tri-stating on the negativeedge allows the transmission of data by multiple sources in adjacent timeslots without the risk of driver contention.

1 BCLKFS

LEFT CHANNELBCLKDACIN/ADCOUT

1
MSB

2

N-1 N
LSB

Word Length, WLEN[6:5]

Figure 33: PCM Time Slot Mode (Time slot = 0) (Normal Mode)

NAU8810 features a special mode where the device outputs Left channel data to both Left and Right channels. Thisis accomplished by setting LOUTR[2] address (0x3C) to “1”

Feb 1, 2023

Page 52 of 101

Rev 1.9

1 BCLKFSLEFT CHANNELRIGHT CHANNELBCLKADCOUT

1

2

N-1 N

MSB

1

N-1 N

2

LSB MSB

Word Length, WLEN[6:5]

LSB

Word Length, WLEN[6:5]

Figure 34: PCM Time Slot Mode (Time slot = 0) (Special mode)
11.10.6.

Companding

Companding is used in digital communication systems to optimize signal-to-noise ratios with reduced data bit rates,
and make use of non-linear algorithms. NAU8810 supports two different types of companding A-law and µ-law on bothtransmit and receive sides. A-law algorithm is used in European communication systems and µ-law algorithm is usedby North America, Japan, and Australia. This feature is enabled by setting DACCM[4:3] address (0x05) or ADCCM[2:1]
address (0x05) register bits. Companding converts 13 bits (µ-law) or 12 bits (A-law) to 8 bits using non-linear
quantization. The companded signal is an 8-bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits).
As recommended by the G.711 standard (all 8-bits are inverted for µ-law, all even data bits are inverted for A-law).
Setting CMB8[5] address 0x05 to 1 will cause the PCM interface to use 8-bit word length for data transfer, overriding
the word length configuration setting in WLEN[6:5] address 0x04.

Addr

D8

D7

D6

D5

0x05

0

0

0

CMB8

D4

D3

DACCM[1:0]

D2

D1

ADCCM[1:0]D0Default

ADDAP

0x000

Table 26: Companding Control

The following equations for data compression (as set out by ITU-T G.711 standard):µ-law (where µ=255 for the U.S. and Japan):F(x) = ln( 1 + µ|x|) / ln( 1 + µ)

-1 ≤ x ≤ 1

A-law (where A=87.6 for Europe):
F(x) = A|x| / ( 1 + lnA) for x ≤ 1/A
F(x) = ( 1 + lnA|x|) / (1 + lnA) for 1/A ≤ x ≤ 1

Feb 1, 2023

Page 53 of 101

Rev 1.9

11.11. POWER SUPPLYThis device has been designed to operate reliably using a wide range of power supply conditions and power-on/poweroff sequences. There are no special requirements for the sequence or rate at which the various power supply pinschange. Any supply can rise or fall at any time without harm to the device. However, pops and clicks may result fromsome sequences. Optimum handling of hardware and software power-on and power-off sequencing is described in
more detail in the Power Up/Down Sequencing section of this document.

11.11.1.

Power-On Reset

The NAU8810 does not have an external reset pin. The device reset function is automatically generated internallywhen power supplies are too low for reliable operation. The internal reset is generated any time that either VDDA or
VDDD is lower than is required for reliable maintenance of internal logic conditions. The threshold voltage for VDDA
is approximately ~1.52Vdc and the threshold voltage for VDDD is approximately ~0.67Vdc. Note that these are much
lower voltages than are required for normal operation of the chip. These values are mentioned here as generalguidance as to overall system design.

If either VDDA or VDDD is below its respective threshold voltage, an internal reset condition may be asserted. During
this time, all registers and controls are set to the hardware determined initial conditions. Software access during thistime will be ignored, and any expected actions from software activity will be invalid.

When both VDDA and VDDD reach a value above their respective thresholds, an internal reset pulse is generated
which extends the reset condition for an additional time. The duration of this extended reset time is approximately 50
microseconds, but not longer than 100 microseconds. The reset condition remains asserted during this time. If either
VDDA or VDDD at any time becomes lower than its respective threshold voltage, a new reset condition will result. The
reset condition will continue until both VDDA and VDDD again higher than their respective thresholds. After VDDA and
VDDD are again both greater than their respective threshold voltage, a new reset pulse will be generated, which again
will extend the reset condition for not longer than an additional 100 microseconds.

11.11.2.

Power Related Software Considerations

There is no direct way for software to determine that the device is actively held in a reset condition. If there is apossibility that software could be accessing the device sooner than 100 microseconds after the VDDA and VDDD
supplies are valid, the reset condition can be determined indirectly. This is accomplished by writing a value to any
register other than register 0x00, with that value being different than the power-on reset initial values. The optimum
choice of register for this purpose may be dependent on the system design, and it is recommended the system engineer
choose the register and register test bit for this purpose. After writing the value, software will then back the sameregister. When the register test bit s back as the new value, instead of the power-on reset initial value, software canreliably determine that the reset condition has ended.

Feb 1, 2023

Page 54 of 101

Rev 1.9

Although it is not required, it is strongly recommended that a Software Reset command should be issued after poweron and after the power-on-reset condition is ended. This will help insure reliable operation under every power
sequencing condition that could occur.

11.11.3.

Software Reset

The control registers can be reset to default conditions by writing any value to RST address (0x00), using any of thecontrol interface modes. Writing valid data to any other register disables the reset, but all registers will need to be
initiated again appropriate to the operation. See the applications section on powering NAU8810 up for information on
avoiding pops and clicks after a software reset.
11.11.4.

Power Up/Down Sequencing

Most audio products have issues during power up and power down in the form of pop and click noise. To avoid cuchissues the NAU8810 provides four different power supplies VDDA, VDDD and VDDSPK with separated grounds VSSA,
VSSD and VSSSPK. The audio CODEC circuitry, the input amplifiers, output amplifiers and drivers, the audio ADC
and DAC converters, the PLL, and so on, can be powered up and down individually by software control via 2-Wireinterface. The zero cross function should be used when changing the volume in the PGAs to avoid any audible pops
or clicks. There are two different modes of operation 5.0V and 3.3V mode. The recommended power-up and powerdown sequences for both the modes are outlined as following.

Feb 1, 2023

Page 55 of 101

Rev 1.9

Power Up
NamePower supplies

Mode

Power
Management

VDDSPK - 3.3V operation

VDDSPK - 5.0V operation

Analog – VDDA

Analog – VDDA

Digital – VDDD

Digital – VDDD

Output driver - VDDSPK

Output driver – VDDSPKSPKBST[2] = 0

SPKBST[2] = 1

MOUTBST[3] = 0
MOUTBST[3] = 1
REFIMP[1:0]
as required (value of the REFIMP bits based on the startup
time which is a combination of the reference impedance andthe decoupling capacitor on VREF)
ABIASEN[3] = 1(enables the internal device bias for all analog blocks)
IOBUFEN[2] = 1(enables the internal device bias buffer)

Clock divider
PLL
DAC, ADC
Mixers

Output stages
Un-mute DAC

CLKIOEN[0] if required

CLKIOEN[0] if required

BCLKSEL[4:2] if required

BCLKSEL[4:2] if required

MCLKSEL[7:5] if required

MCLKSEL[7:5] if required

PLLEN[5] if required

PLLEN[5] if required

DACEN[0] = 1

DACEN[0] = 1

ADCEN[0] = 1

ADCEN[0] = 1

SPKMXEN[2]SPKMXEN[2]MOUTMXEN[3]MOUTMXEN[3]MOUTEN[7]MOUTEN[7]NSPKEN[6]NSPKEN[6]PSPKEN[5]PSPKEN[5]DACMT[6] = 0

DACMT[6] = 0

Table 27: Power up sequence

Feb 1, 2023

Page 56 of 101

Rev 1.9

Name

Power Down Both Cases

Mute DACDACMT[6] = 1

Power Management

PWRM1 = 0x000
MOUTEN[7]Output stages

NSPKEN[6]PSPKEN[5]Analog – VDDA

Power supplies

Digital – VDDD
Output driver – VDDSPKTable 28: Power down Sequence

11.11.5.

Reference Impedance (REFIMP) and Analog Bias

Before the device is functional or any of the individual analog blocks are enabled REFIMP[1:0] address (0x01) and
ABIASEN[3] address (0x01) must be set. The REFIMP[1:0] bits control the resistor values (“R” in Figure3) thatgenerates the mid supply reference, VREF. REFIMP[1:0] bits control the power up ramp rate in conjunction with theexternal decoupling capacitor. A small value of “R” allows fast ramp up of the mid supply reference and a large valueof “R” provides higher PSRR of the mid supply reference.

The master analog biasing of the device is enabled by setting ABIASEN[3] address (0x01). This bit has to be set before
for the device to function.

11.11.6.

Power Saving

Saving power is one of the critical features in a semiconductor device specially ones used in the Bluetooth headsets
and handheld device. NAU8810 has two oversampling rates 64x and 128x. The default mode of operation for the DAC
and ADC is in 64x oversampling mode which is set by programming DACOS[3] address (0x0A) and ADCOS[3] address(0x0E) respectively to LOW. Power is saved by choosing 64x oversampling rate compared to 128x oversampling rate
but slightly degrades the noise performance. To each lowest power possible after the device is functioning set
ABIASEN[3] address (0x01) bit to LOW.

Addr
D8
D7
D6
D5
D4
D3
D2
0x01 DCBUFEN
0
PLLEN MICBIASEN ABIASEN IOBUFEN
0x0A
0
0
DACMT
DEEMP[1:0]
DACOS AUTOMT
0x0E MOUTFEN MOUTFAM
MOUTF[2:0]ADCOS
00x3A LPIPBSTLPADC LPSPKD LPDAC MICBIASM
TRIMREG[3:2]

D1
D0
REFIMP
0
DACPL
0
ADCPL
IBADJ[1:0]Default
0x000
0x000
0x100
0x000

Table 29: Registers associated with Power Saving

Feb 1, 2023

Page 57 of 101

Rev 1.9

11.11.7. Estimated Supply Currents
NAU8810 can be programmed to enable or disable various analog blocks individually. The table below shows theamount of current consumed by certain analog blocks. Sample rate settings will vary current consumption of the VDDD
supply. VDDD consumes approximately 4mA with VDDD = 1.8V and fs = 48kHz. Lower sampling rates will draw lower
current.

BIT

Address

REFIMP[1:0]
IOBUFEN[2]ABIASEN[3]0x01

VDDA CURRENT
10K => 300 uA
161k/595k < 100 uA
40uA
600uA

MICBIASEN[4]500 uA

PLLEN[5]2.5mA Clocks Applied

DCBUFEN[8]80uA
x64 - ADCOS= 0 => 2.0mA
x128 – ADCOS= 1 => 3.0mA
400uA

ADCEN[0]PGAEN[2]0x02

BSTEN[4]200 uAX64 (DACOS=0)=>1.6mA
x128(DACOS=1)=>1.7mA
400uA

DACEN[0]SPKMXEN[2]MOUTMXEN[3]

0x03

200uA

NSPKEN[6]1mA from VDDSPK + 100uA (VDDA = 5V mode)

PSPKEN[5]1mA from VDDSPK + 100uA (VDDA = 5V mode)

MOUTEN[7]100uA
Table 30: VDDA 3.3V Supply Current

Feb 1, 2023

Page 58 of 101

Rev 1.9

12. REGISTER DESCRIPTION
Register
Address
DEC

HEX

0

0

Register Bits
Register Names

Default
D8

D7

D6

D5

D4

Software Reset

D3

D2

D1

D0

RESET (SOFTWARE)

000

POWER MANAGEMENT
101

Power Management 1 DCBUFEN

0

0

PLLEN

MICBIASENABIASENIOBUFENREFIMP000

202Power Management 2

0

0

0

0

BSTEN

0

PGAEN

0

ADCEN

000

3

03

Power Management 30

MOUTENNSPKENPSPKEN0

MOUTMXEN SPKMXEN

0

DACEN

000

ADCPHS

0050

ADCCM[1:0]

ADDAP

000

0

CLKIOEN140

SCLKEN

000
000

AUDIO CONTROL
4

04

Audio Interface

BCLKP

FSP

WLEN[1:0]

505

Companding

0

0

6

06

Clock Control 1

CLKM

7

07

Clock Control 2

0

0

0

10

0A

DAC CTRL

0

0

DACMT

11

0B

DAC Volume

0

14

0E

ADC CTRL

HPFEN

15

0F

ADC Volume

0

0

AIFMT[1:0]0

DACPHSDACCM[1:0]

MCLKSEL[2:0]

BCLKSEL[2:0]00SMPLR[2:0]

DEEMP[1:0]

DACOS

AUTOMT

0

DACPL

0

0

ADCPL

DACGAIN
HPFAM

HPF[2:0]

0FF

ADCOS
ADCGAIN

100
0FF

EQUALISER
18

0x12 EQ1-Low Cutoff

EQM

0

EQ1CF[1:0]

EQ1GC[4:0]

12C

19

0x13 EQ2-Peak 1

EQ2BW

0

EQ2CF[1:0]

EQ2GC[4:0]

02C

20

0x14 EQ3-Peak 2

EQ3BW

0

EQ3CF[1:0]

EQ3GC[4:0]

02C

21

0x15 EQ4-Peak3

EQ4BW

0

EQ4CF[1:0]

EQ4GC[4:0]

02C

22

0x16 EQ5-High Cutoff

00

EQ5CF[1:0]

EQ5GC[4:0]

02C

24

18

DAC Limiter 1

DACLIMEN

25

19

DAC Limiter 2

0

DIGITAL TO ANALOG (DAC) LIMITERDACLIMDCY[3:0]0

DACLIMTHL[2:0]

DACLIMATK[3:0]032

DACLIMBST[3:0]000

NOTCH FILTER
27

1B

Notch Filter High

NFCU

NFCEN

NFCA0[13:7]

000

28

1C

Notch Filter Low

NFCU

0

NFCA0[6:0]

000

29

1D

Notch Filter High

NFCU

0

NFCA1[13:7]

000

30

1E

Notch Filter Low

NFCU

0

NFCA1[6:0]000

ALC CONTROL
32

20

ALC CTRL 1

ALCEN

0

33

21

ALC CTRL 2

ALCZC

ALCHT[3:0]

ALCSL[3:0]

00B

34

22

ALC CTRL 3

ALCM

ALCDCY[3:0]

ALCATK[3:0]

032

35

23

Noise Gate

0

0

0

0

ALCMXGAIN[2:0]00

ALCMNGAIN[2:0]

ALCNENALCNTH[2:0]

038

000

PLL CONTROL
36

24

PLL N CTRL

0

0

0

37

25

PLL K 1

0

0

0

38

26

PLL K 2

Feb 1, 2023

0

PLLMCLKPLLN[3:0]008

PLLK[23:18]

00C

PLLK[17:9]

Page 59 of 101

093

Rev 1.9

Register
Address
DEC

HEX

39

27

Register Bits
Register Names

Default
D8

D7

D6

D5

D4

PLL K 3

D3

D2

D1

D0

PLLK[8:0]

0E9

INPUT, OUTPUT & MIXER CONTROL
40

28

Attenuation CTRL

44

2C

Input CTRL

0

0

45

2D

PGA Gain

0

PGAZC

47

2F

ADC Boost

PGABST

0

49

31

Output CTRL

0

0

0

0

50

32

Mixer CTRL

0

0

0

0

54

36

SPKOUT Volume

0

SPKZC

SPKMT

56

38

MONO Mixer Control

00

MOUTMTMICBIASV

0

0

0

0

MOUTATTSPKATT

0

000

0

0

0

0

0

NMICPGAPMICPGA

003

PGAMT

PGAGAIN[5:0]
PMICBSTGAIN

010

0

0

0

0

100

0

MOUTBSTSPKBSTTSEN

AOUTIMP

002

0

0

0

BYPSPK

DACSPK001

SPKGAIN[5:0]
0

0

0

0

039
BYPMOUTDACMOUT001

LOW POWER CONTROL
58

3A

Power Management 4

LPIPBSTLPADC

LPSPKDLPDAC

MICBIASM

TRIMREG

IBADJ

000

PCM TIME SLOT & ADCOUT IMPEDANCE OPTION CONTROL
59

3B

Time Slot

60

3C

ADCOUT Drive

TSLOT[8:0]
PCMTSENTRI

PCM8BITPUDOEN

PUDPE

000
PUDPS

LOUTR

PCMB

TSLOT[9:8]020

REGISTER ID
62

3E

Silicon Revision

0

1

1

1

0

1

1

1

0

0EE

63

3F

2-Wire ID

0

0

0

0

1

1

0

1

0

01A

64

40

Additional ID

0

1

1

0

0

1

0

1

0

0CA

65

41

Reserved

1

0

0

1

0

0

1

0

0

124

69

45

High Voltage CTRL

0

0

0

0

MOUTMT

0

HVOPU

0

HVOP

001

70

46

ALC Enhancements 1 ALCTBLSEL ALCPKSEL ALCNGSEL

71

47

ALC Enhancements 2

PKLIMEN

73

49

Additional IF CTRL

0

75

4B

Power/Tie-off CTRL

0

76

4C

AGC P2P Detector

P2PDET ( ONLY)

000

77

4D

AGC Peak Detector

PDET ( ONLY)

000

78

4E

Control and Status

00

AMTCTRLHVDETNSGATE

AMUTE

DMUTE

0

FTDEC

000

79

4F

Output tie-off CTRLMANOUTEN

SBUFH

SBUFL

SNSPK

SPSPK

SMOUT

0

0

0

000

Feb 1, 2023

0

0

1

FSERRVAL[1:0]
LPSPKAALCGAINL ( ONLY)

0

1

FSERFLSH FSERRENA
0

1

0

0

1

039

NFDLY

DACINMT

PLLLOCKPDACOS256000

MANVREFH MANVREFM MANVREFL

000

0Page 60 of 101000

0

Rev 1.9

12.1. SOFTWARE RESET
Addr

D8

D7

D6

D5

0x00

D4

D3

D2

D1

D0

Default

RESET (SOFTWARE)

0x000

This is device Reset register. Performing a write instruction to this register with any data will reset all the bits in theregister map to default.
12.2. POWER MANAGEMENT REGISTERS
12.2.1.

Power Management 1

Addr

D8

D7

D6

D5

D4

0x01

DCBUFEN

0

0

PLLEN

D3

D2

MICBIASEN ABIASEN IOBUFEN

D1

D0

Default

REFIMP[1:0]

0x000

Name

Buffer for DC
level shifting
Enable

PLL enable

Microphone
Bias
EnableAnalogue
amplifierbias control

Unusedinput/output tie
off buffer enable

Bit

DCBUFEN[8]PLLEN[5]MICBIASEN[4]ABIASEN[3]IOBUFEN[2]0DisableDisableDisableDisableDisable1

Enable(required for1.5x gain)

EnableEnableEnableEnableThe DCBUFEN[8] address (0x01) is a dedicated buffer for DC level shifting output stages when in 1.5x gain boost
configuration. There are three different reference impedance selections to choose from as follows:
VREF REFERENCEIMPEDANCE SELECTION(“R” refers to “R” as shown in Figure3)
REFIMP[1]
REFIMP[0]Mode

Feb 1, 2023

00

Disable01

R = 80 kΩ

1

0

R = 300 kΩ

1

1

R = 3 kΩ

Page 61 of 101

Rev 1.9

12.2.2.

Power Management 2

Addr

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x02

0

0

0

0

BSTEN

0

PGAEN

0

ADCEN

0x000

D1

D0

Default

0

DACEN

0x000

12.2.3.

Name

Input Boost
EnableMIC(+/-)PGA Enable

ADC Enable

Bit

BSTEN[4]PGAEN[2]ADCEN[0]0Stage Disable

DisableDisable1

Stage Enable

EnableEnablePower Management 3

Addr

D8

0x03

0

D7

D6

D5

D4

MOUTEN NSPKEN PSPKEN

D3

0

D2

MOUTMXEN SPKMXEN

Name

MOUT
EnableSPKOUTEnable

SPKOUT+
EnableMONO Mixer
EnableSpeaker
Mixer Enable

DAC
EnableBit

MOUTEN[7]NSPKEN[6]PSPKEN[5]MOUTMXEN[3]SPKMXEN[2]DACEN[0]0DisableDisableDisableDisableDisableDisable1

EnableEnableEnableEnableEnableEnable12.3. AUDIO CONTROL REGISTERS
12.3.1.

Audio Interface Control

Addr

D8

D7

0x04

BCLKP

FSP

D6

D5

D4

WLEN[1:0]

D3

AIFMT[1:0]

D2

D1

DACPHS ADCPHS

D0

Default

00x050

The following table explains the PCM control register bits.

Name

BCLK
Polarity

Frame Clock
Polarity

DAC Data ‘right’ or ‘left’
phases of FRAME clock

ADC Data ‘right’ or ‘left’
phases of FRAME clock

Bit

BCLKP[8]FSP[7]DACPHS[2]ADCPHS[1]0NormalNormalDAC data appear in ‘left’ phase of
FRAME

ADC data appear in ‘left’ phase of
FRAME

1

Inverted

Inverted

DAC data appears in ‘right’ phase of
FRAME

ADC data appears in ‘right’ phase of
FRAME

There are three different CODEC modes to choose from as follows:

Feb 1, 2023

Page 62 of 101

Rev 1.9

Word Length Selection

Audio Data Format Select

WLEN[6]WLEN[5]Bits

AIFMT[4]AIFMT[3]Format

0

0

16

0

0

Right
Justified

0

1

20

0

1

Left Justified

1

0

24

1

0

I2S

1

1

32

1

1

PCM A

12.3.2.

Audio Interface Companding Control

Addr

D8

D7

D6

D5

D4

0x05

0

0

0

CMB8

D3

DACCM[1:0]

D2

D1

ADCCM[1:0]D0Default

ADDAP

0x000

The NAU8810 provides a Digital Loopback ADDAP[0] address (0x05) bit. Setting ADDAP[0] bit to HIGH enables theloopback so that the ADC data can be fed directly into the DAC input.

Companding Mode 8-bit
word enable
CMB8[5]01Modenormaloperation
8-bit operation

Feb 1, 2023

DAC Companding Selection

ADC Companding SelectDACCM[4]DACCM[3]Mode

ADCCM[2]ADCCM[1]

Mode

0

0

Disabled00

Disabled

01

Reserved

01

Reserved

1

0

µ-Law

1

0

µ-Law

1

1

A-Law

1

1

A-Law

Page 63 of 101

Rev 1.9

12.3.3.

Clock Control Register

Addr

D8

0x06

CLKM

D7

D6

D5

D4

MCLKSEL[2:0]

D3

D2

BCLKSEL[2:0]Master Clock Selection
MCLKSEL[7]

MCLKSEL[6]

MCLKSEL
[5]

0

0

0

0

0

1

0

1

0

0

1

1
1

D0

Default

0

CLKIOEN

0x140

Bit Clock SelectBCLKSEL[4]

BCLKSEL[3]

BCLKSEL
[2]

0

0

0

0

0

1

÷2

0

1

0

÷1
(BCLK=MCLK)÷2(BCLK=MCLK/2)
÷4

1

÷3

0

1

1

÷8

0

0

÷4

1

0

0

÷ 16

0

1

÷6

1

0

1

÷ 32

1

1

0

Reserved

1

1

1

Reserved

Mode
÷1
÷ 1.5

1

1

0

÷8

1

1

1

÷ 12

Feb 1, 2023

D1

Name

Source of Internal Clock

FRAME and BCLKBit

CLKM[8]

CLKIOEN[0]0MCLK (PLL Bypassed)

Slave Mode

1

MCLK (PLL Output)

Master Mode

Page 64 of 101

Mode

Rev 1.9

12.3.4.

Audio Sample Rate Control Register

Addr

D8

D7

D6

D5

D4

0x07

0

0

0

0

0

D3

D2

D1

SMPLR[2:0]D0Default

SCLKEN

0x000

The Audio sample rate configures only the coefficients for the internal digital filters to match the actual sample rate. It
does not in any way actually set or change the ADC or DAC audio sample rate.
Sample Rate Selection
SMPLR[3]SMPLR[2]SMPLR[1]Mode (Hz)

0

0

0

48 k

0

0

1

32 k

0

1

0

24 k

0

1

1

16 k

1

0

0

12 k

1

0

1

8k

1

1

0

Reserved

1

1

1

Reserved

NAU8810 provides a slow clock to be used for the zero cross timeout.
Slow Clock EnableBit

12.3.5.

SCLKEN[0]

0

MCLK

1

PLL Output (Period 221 * MCLK)DAC Control Register

Addr

D8

D7

D6

0x0A

0

0

DACMT

Feb 1, 2023

D5

D4

DEEMP[1:0]

D3

D2

D1

D0

Default

DACOS

AUTOMT

0

DACPL

0x000

Name

Soft Mute Enable

Over Sample Rate

Auto Mute enable

Polarity Invert

Bit

DACMT[6]DACOS[3]

AUTOMT[2]DACPL[0]0Disable64x(Lowest power)

DisableNormal1

Enable128x(best SNR)

EnableDAC Output
Inverted

Page 65 of 101

Rev 1.9

De-emphasis

12.3.6.

DEEMP[5]DEEMP[4]

Mode

0

0

No de-emphasis

0132kHz sample rate

10

44.1kHz sample rate

1

1

48kHz sample rate

DAC Gain Control Register

Addr

D8

0x0B

0

D7

D6

D5

D4

D3

D2

D1

D0

DACGAIN

Default
0x0FF

DAC Gain
DACGAIN[7:0]Mode (dB)

B7

B6

B5

B4

B3

B2

B1

B0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

DigitalMute-127.0

0

0

0

0

0

0

1

0

-126.5

0

0

0

0

0

0

1

1

-126.0DAC Gain Range -127dB to 0dB @ 0.5 increments

12.3.7.

1

1

1

1

1

1

0

0

-1.5

1

1

1

1

1

1

0

1

-1.0

1

1

1

1

1

1

1

0

-0.5

1

1

1

1

1

1

1

1

0.0

ADC Control Register

Addr

D8

D7

0x0E

HPFEN

HPFAM

Name

High Pass Filter
EnableAudio or Application
Mode

Over Sample
Rate

ADC Polarity

Bit

HPFEN[8]HPFAM[7]ADCOS[3]ADCPL[0]0DisableAudio (1st order, fc ~ 3.7 Hz)

64x (Lowest power)

NormalEnableApplication (2nd order, fc = HPF)

128x (best SNR)

Inverted1

Feb 1, 2023

D6

D5

D4

HPF[2:0]

D3

D2

D1

D0

Default

ADCOS

0

0

ADCPL

0x100

Page 66 of 101

Rev 1.9

High Pass Filter

fs ( kHz)SMPLR=101
SMPLR=100

SMPLR=011
SMPLR=010

SMPLR=001
SMPLR=000

HPF[6]

HPF[5]

HPF[4]

B2

B1

B0

8

11.025

12

16

22.05

24

32

44.1

48

0

0

0

82

113

122

82

113

122

82

113

122

0

0

1

102

141

153

102

141

153

102

141

153

0

1

0

131

180

156

131

180

156

131

180

156

0

1

1

163

225

245

163

225

245

163

225

245

1

0

0

204

281

306

204

281

306

204

281

306

1

0

1

261

360

392

261

360

392

261

360

392

1

1

0

327

450

490

327

450

490

327

450

490

1

1

1

408

563

612

408

563

612

408

563

612

D0

Default

12.3.8.

ADC Gain Control Register

Addr

D8

0x0F

0

D7

D6

D5

D4

D3

D2

D1

ADCGAIN

0x0FF

ADC Gain
ADCGAIN[7:0]Mode (dB)

B7

B6

B5

B4

B3

B2

B1

B0

0

0

0

0

0

0

0

0

Unused

0

0

0

0

0

0

0

1

-127.0

0

0

0

0

0

0

1

0

-126.5

0

0

0

0

0

0

1

1

-126.0ADC Gain Range -127dB to 0dB @ 0.5 increments

Feb 1, 2023

1

1

1

1

1

1

0

0

-1.5

1

1

1

1

1

1

0

1

-1.0

1

1

1

1

1

1

1

0

-0.5

1

1

1

1

1

1

1

1

0.0

Page 67 of 101

Rev 1.9

12.4. 5-BAND EQUALIZER CONTROL REGISTERS
Address

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x12

EQM

0

EQ1CF[1:0]

EQ1GC[4:0]

0x12C

0x13

EQ2BW

0

EQ2CF[1:0]

EQ2GC[4:0]

0x02C

0x14

EQ3BW

0

EQ3CF[1:0]

EQ3GC[4:0]0x 02C

0x15

EQ4BW

0

EQ4CF[1:0]

EQ4GC[4:0]

0x02C

0x16

0

0

EQ5CF[1:0]

EQ5GC[4:0]0x02C

Equalizer Gain
EQ1GC, EQ2GC, EQ3GC, EQ4GC, EQ5GC [4:0]Mode (dB)

B4

B3

B2

B1

B0

0

0

0

0

0

+12

0

0

0

0

1

+11

:::

:::

:::

:::

:::

:::

0

1

0

1

1

+1

0

1

1

0

0

0

0

1

1

0

1

-1

Equalizer Gain Range -12dB to +12dB @ 1.0 increment
:::

:::

:::

:::

:::

:::

1

0

1

1

1

-11

1

1

0

0

0

-12

1

1

0

0

1

To
1

1

Reserved

1

1

1Center Frequencies

Feb 1, 2023

B1

B0

EQ2CF[6:5]

EQ3CF[6:5]

EQ4CF[6:5]

0

0

230

650

1.8 k

0

1

300

850

2.4 k

1

0

385

1.1 k

3.2 k

1

1

500

1.4 k

4.1 k

Page 68 of 101

Rev 1.9

Cut-off Frequencies
B0

EQ1CF[6:5]

EQ5CF[6:5
]

0

0

80

5.3 k

0

1

105

6.9 k

1

0

135

9.0 k

1

1

175

11.7 kBandwidth Control

Equalizer Path

EQ2BW – EQ4BW

EQM[8]

0

Narrow bandwidth

ADC path1

Wide bandwidth

DAC path

Bit

12.5.

B1

DIGITAL TO ANALOG CONVERTER (DAC) LIMITER REGISTERS

Addr

D8

D7

0x18

DACLIMEN

0x19

0

D6

D5

D4

D3

DACLIMDCY[3:0]0

DACLIMTHL[2:0]

DAC Limiter Decay time (per 6dB gain change) for 44.1
kHz sampling. Note that these will scale with sample
rate

D2

D1

D0

Default

DACLIMATK[3:0]0x032

DACLIMBST[3:0]0x000

DAC Limiter Attack time (per 6dB gain change) for 44.1
kHz sampling. Note that these will scale with sample rate

DACLIMDCY[3:0]

DACLIMATK[3:0]

B3

B2

B1

B0

Decay Time

0

0

0

0

544.0 us

0

0

0

0

68 us

0

0

0

1

1.1 ms0001

136 us001

0

2.2 ms0010272 us00

1

1

4.4 ms0011544 us01

0

0

8.7 ms010

0

1.1 ms01

0117.4 ms

0

1

0

1

2.2 ms01

1035.0 ms

0

1

1

0

4.4 ms01

1

169.6 ms

0

1

1

1

8.7 ms1000139.0 ms

1

0

0

0

17.4 ms

1

0

0

1

278.5 ms

1

0

0

1

35 ms

1

0

1

0

557.0 ms

1

0

1

0

69.6 ms

1

0

1

1

1

0

1

1

To
1

1

Feb 1, 2023

B3

B2

1

B0

To

1.1 s
1

B1

1

Page 69 of 101

1

Attack Time

139 ms1

1

Rev 1.9

DAC Limiter volume Boost (can be used asastand alone volume Boost when
DACLIMEN=0)DACLIMBST[3:0]
Boost
(dB)
B3
B2
B1
B0

DAC Limiter Programmable signal threshold level(determines level at which the limiter starts tooperate)DACLIMTHL[3:0]
B2

B1

B0

Threshold
(dB)

0

0

0

-1

0

0

0

0

0

0

0

1

-2

0

0

0

1

+1

0

1

0

-3

0

0

1

0

+2

0

1

1

-4

0

0

1

1

+3

1

0

0

-5

0

1

0

0

+4

1

0

1

0

1

0

1

+5

0

1

1

0

+6

0

1

1

1

+7

1

0

0

0

+8

1

0

0

1

+9

-6

To
1

1

1

1

0

1

0

+10

Bit

DAC Digital Limiter
DACLIMEN[8]

1

0

1

1

+11

0

Disabled

1

1

0

0

+12

1

Enabled1

10

1Reserved

To
1

1

1

1

12.6. NOTCH FILTER REGISTERS

Addr

D8

D7

0x1B

NFCU

NFCEN

D6

D5

D4

NFCA0[13:7]

D3

D2

D1

D0

Default
0x000

0x1C

NFCU

0

NFCA0[6:0]

0x000

0x1D

NFCU

0

NFCA1[13:7]

0x000

0x1E

NFCU

0

NFCA1[6:0]0x000

The Notch Filter is enabled by setting NFCEN[7] address (0x1B) bit to HIGH. The coefficients, A0 and A1, should be
converted to 2’s complement numbers to determine the register values. A0 and A1 are represented by the register bits
NFCA0[13:0] and NFCA1[13:0]. Since there are four register of coefficients, a Notch Filter Update bit is provided sothat the coefficients can be updated simultaneously. NFCU[8] is provided in all registers of the Notch Filter coefficientsbut only one bit needs to be toggled for LOW – HIGH – LOW for an update. If any of the NFCU[8] bits are left HIGH
then the Notch Filter coefficients will continuously update. An example of how to calculate is provided in the Notch
Filter section.

Feb 1, 2023

Page 70 of 101

Rev 1.9

Name

A0

A1

Notation

Register Value (DEC)

Coefficient 2πfb 
1 − tan 2fs 
 2πfb 
1 + tan 2fs 

 2πf − (1 + A0 ) x cos c  fs 

fc = center frequency (Hz)fb = -3dB bandwidth (Hz)fs = sample frequency (Hz)NFCA0 = -A0 x 213
NFCA1 = -A1 x 212(then convert to 2’scomplement)

12.7. AUTOMATIC LEVEL CONTROL REGISTER
12.7.1.

ALC1 REGISTER

Addr

D8

D7

D6

0x20

ALCEN

0

0

D5

D4

D3

ALCMXGAIN[2:0]

B2

B1

B0

0

0

0

0

0

0

D1

D0

ALCMNGAIN[2:0]

Maximum Gain
ALCMXGAIN[2:0]

D2

0x038

Minimum Gain
ALCMNGAIN[2:0]

Mode

Mode

B2

B1

B0

-6.75dB

0

0

0

-12dB

1

-0.75dB

0

0

1

-6dB

1

0

+5.25dB

0

1

0

0dB

0

1

1

+11.25dB

0

1

1

+6dB

1

0

0

+17.25dB

1

0

0

+12dB

1

0

1

+23.25dB

1

0

1

+18dB

1

1

0

+29.25dB

1

1

0

+24dB

1

1

1

+35.25dB

1

1

1

+30dB

12.7.2.

Default

Name

ALC Enable

Bit

ALCEN[8]0Disabled (PGA gain set by PGAGAIN
register bits)

1

Enabled(ALC controls PGA gain)

ALC3 REGISTER

Addr

D8

0x22

ALCM

Feb 1, 2023

D7

D6

D5

D4

ALCDCY[3:0]

D3

D2

D1

ALCATK[3:0]Page 71 of 101

D0

Default
0x032

Rev 1.9

ALC DECAY TIMEALCDCY[3:0]

ALCM = 0 (Normal Mode)

ALCM = 1 (Limiter Mode)

B3

B2

B1

B0

Per Step

Per 6dB

90% ofRange

Per Step

Per 6dB

90% of
Range

0

0

0

0

500 us

4 ms

28.78 ms

125 us1 ms

7.2 ms

0

0

0

1

1 ms

8 ms

57.56 ms

250 us2 ms

14.4 ms

0

0

1

0

2 ms

16 ms

115 ms500 us4 ms

28.8 ms

Time doubles with every increment
1

0

0

0

128 ms1s7.37 s32 ms

256 ms

1.8 s

1

0

0

1

256 ms2s14.7 s

64 ms

512 ms

3.7 s

1

0

1

0
512 ms4s29.5 s

128 ms1s7.37 s

To
1

1

1

1

ALC ATTACK TIME
ALCATK[3:0]

ALCM = 0 (Normal Mode)

ALCM = 1 (Limiter Mode)

90% ofRange

Per Step

Per 6dB

90% of
Range

B3

B2

B1

B0

Per Step

Per 6dB

0

0

0

0

125 us1 ms

7.2 ms31 us

248 us

1.8 ms0001

250 us2 ms

14.4 ms

62 us

496 us

3.6 ms0010500 us4 ms

28.85 ms

124 us992 us7.15 ms

Time doubles with every increment
1

0

0

0

26.5 ms

256 ms1.53 s

7.9 ms63.2 ms

455.8 ms

1

0

0

1

53 ms

512 ms3.06 s

15.87 ms

127 ms

916 ms10

10
128 ms1s7.89 s31.7ms254 ms1.83 s

1

1

To
1

1

Feb 1, 2023

Page 72 of 101

Rev 1.9

12.8. NOISE GAIN CONTROL REGISTER
Addr

D8

D7

D6

D5

D4

D3

0x23

0

0

0

0

0

ALCNEN

Noise Gate Enable

D2

D1
ALCNTH[2:0]D0Default
0x000

Noise Gate Threshold

Bit

ALCNEN[3]ALCNTH[2:0]0Disabled

B2

B1

B0

1

Enabled000-39 dB001-45 dB01

0-51 dB01

1-57 dB100-63 dB10

1-69 dBMode

Feb 1, 2023

1

1

0

-75 dB1

1

1-81 dB

Page 73 of 101

Rev 1.9

12.9. PHASE LOCK LOOP (PLL) REGISTERS
12.9.1.

PLL Control Registers

Addr

D8

D7

D6

D5

D4

0x24

0

0

0

0

PLLMCLK

D3

D2

D0

Default

PLLN[3:0]

PLL Integer

0x008

PLL Clock

PLLN[3:0]
B3

B2

B1

B0

0

0

0

1

Bit

Frequency
Ratio

PLLMCLK[4]0

MCLK not divided

1

Divide MCLK by 2 before input
PLL

Not Valid

To
0

1

0

0

0

1

0

1

5

0

1

1

0

6

0

1

1

1

7

1

0

0

0

8

1

0

0

1

9

1

0

1

0

10

1

0

1

1

11

1

1

0

0

12

1

1

0

1

13

1

1

1

0

1

1

1

1

12.9.2.

D1

Not Valid

Phase Lock Loop Control (PLL) Registers

Addr

D8

D7

D6

0x25

0

0

0

D5

D4

D3

D2

PLLK[23:18]

D1

D0

Default
0x00C

0x26

PLLK[17:9]

0x093

0x27

PLLK[8:0]

0x0E9

Fractional (K) part of PLLK1 – PLLK3 input/output frequency ratio

Feb 1, 2023

Page 74 of 101

Rev 1.9

12.10.

INPUT, OUTPUT, AND MIXERS CONTROL REGISTER

12.10.1.

Attenuation Control Register

Addr

D8

D7

D6

D5

D4

D3

0x28

0

0

0

0

0

0

D2

D1

MOUTATT SPKATT

D0

Default

0

0x000

D0

Default

Attenuation Control
Attenuation control for bypass path (output of
input boost stage) to speaker mixer and MONO
mixer input

Name

12.10.2.

Addr
0x2C

Bit

MOUTATT[2]SPKATT[1]

0

0 dB

0 dB

1

-10 dB-10 dB

Input Signal Control Register

D8

D7

D6

D5

D4

D3

D2

MICBIASV

0

0

0

0

0

D1

NMICPGA PMICPGAMICN to input PGA
negative terminal

Input PGA amplifier
positive terminal to
MIC+ or VREF

Bit

NMICPGA[1]PMICPGA[0]0MICN not connected to
input PGA

Input PGA Positive
terminal to VREF

1

MICN to input PGA
Negative terminal.

Input PGA Positive
terminal to MICP
through variable resistor

0x003

Microphone Bias Voltage Control
MICBIASV[8:7]
Address (0x2C)

Feb 1, 2023

MICBIASM[4] = 0
Address (0x28)

MICBIASM[4] = 1
Address (0x28)

000.9* VDDA

0.85* VDDA

010.65* VDDA

0.60* VDDA

100.75* VDDA

0.70* VDDA

110.50* VDDA

0.50* VDDA

Page 75 of 101

Rev 1.9

12.10.3.

PGA Gain Control Register

Addr

D8

D7

D6

D5

0x2D

0

PGAZC

PGAMT

D4

D3

D2

PGAGAIN[5:0]

D1

D0

Default
0x010

Programmable Gain Amplifier GainPGAGAIN[5:0]
B5

B4

B3

B2

B1

B0

Gain

0

0

0

0

0

0

-12.00 dB

0

0

0

0

0

1

-11.25 dB

0

0

0

0

1

0

-10.50 dB

:::

:::

:::

:::

:::

:::

:::

0

0

1

1

1

1

-0.75 dB

0

1

0

0

0

0

0 dB

0

1

0

0

0

1

+0.75 dBPGA Gain Range -12dB to +35.25dB @ 0.75
increment

Feb 1, 2023

:::

:::

:::

:::

:::

:::

:::

1

1

1

1

0

1

33.75

1

1

1

1

1

0

34.50

1

1

1

1

1

1

35.25

PGA Zero Cross Enable

Mute Control for PGA

Bit

PGAZC[7]PGAMT[6]0Update gain when gain
register changes

Normal Mode

1

Update gain on 1st zerocross after gain register
write

PGA Muted

Page 76 of 101

Rev 1.9

12.10.4.

ADC Boost Control Registers

Addr

D8

D7

0x2F

PGABST

0

D6

D5

D4

D3

D2

D1

D0

Default

0

0

0

0

0x100

D1

D0

Default

TSEN

AOUTIMP

0x002

PMICBSTGAIN

MIC+ pin to the input Boost Stage(NB, when using this path set
PMICPGA=0):
PMICBSTGAIN[2:0]12.10.5.

Gain (dB)

B2

B1

B0

0

0

0

0

0

1

Path
Disconnected
-12

0

1

0

-9

0

1

1

-6

1

0

0

-3

1

0

1

0

1

1

0

+3

1

1

1

+6

Name

Input Boost

Bit

PGABST[8]0PGA output has +0dB gain through input Boost stage

1

PGA output has +20dB gain through input Boost stage

Output Register

Addr

D8

D7

D6

D5

D4

0x31

0

0

0

0

0

D3

D2

MOUTBST SPKBSTMONO Output BoostStage

Speaker Output Boost
Stage

Thermal Shutdown

Analog Output Resistance

Bit

MOUTBST[3]SPKBST[2]

TSEN[1]AOUTIMP[0]0(1.0 x VREF) Gain Boost(1.0 x VREF) Gain Boost

Disabled~1kΩ

1(1.5 x VREF) Gain Boost(1.5 x VREF) Gain Boost

Enabled~30 kΩ

Feb 1, 2023

Page 77 of 101

Rev 1.9

12.10.6.

Speaker Mixer Control Register

Addr

D8

D7

D6

D5

D4

D3

D2

0x32

0

0

0

0

0

0

0

12.10.7.

D1

D0

Default

BYPSPK DACSPKBypass path (output of
Boost stage) to Speaker
Mixer

DAC to Speaker Mixer

Bit

BYPSPK[1]DACSPK[0]0Disconnected

Disconnected1

Connected

Connected

0x001

Speaker Gain Control Register

Addr

D8

D7

D6

0x36

0

SPKZC

SPKMT

D5

D4

D3

D2

D1

SPKGAIN[5:0]D0Default
0x039

Speaker GainSPKGAIN[5:0]
B5

B4

B3

B2

B1

B0

Gain (dB)

0

0

0

0

0

0

-57.0

0

0

0

0

0

1

-56.0

0

0

0

0

1

0

-55.0

:::

:::

:::

:::

:::

:::

:::

1

1

1

0

0

0

-1.0

1

1

1

0

0

1

0.0

1

1

0

1

0

+1.0

1

Speaker Gain Range -57 dB to +6 dB @ +1
increment

Feb 1, 2023

:::

:::

:::

:::

:::

:::

:::

1

1

1

1

0

1

+4.0

1

1

1

1

1

0

+5.0

1

1

1

1

1

1

+6.0

Speaker Gain Control Zero Cross

Speaker Output

Bit

SPKZC[7]SPKMT[6]0Change Gain on Zero Cross
ONLY

Speaker Enabled

1

Change Gain Immediately

Speaker Muted

Page 78 of 101

Rev 1.9

12.10.8.

MONO Mixer Control Register

Addr

D8

D7

D6

D5

D4

D3

D2

0x38

0

0

MOUTMXMT

0

0

0

0

D1

D0

Default

BYPMOUT DACMOUT 0x001

MOUT Mute

Bypass path (output of
Boost Stage) to MONO
Mixer

DAC toMONO Mixer

Bit

MOUTMXMT[6]BYPMOUT[1]DACMOUT[0]0Not Muted

Disconnected

Disconnected

1

Muted

Connected

Connected

During mute, the MONO output will output VREF that can be used as a DC reference for a headphone out.

12.10.9.

Power Management 4

Addr

D8

D7

D6

D5

0x3A

LPIPBSTLPADC

LPSPKD

B1

B0

D4

D3

LPDAC MICBIASM

D2

TRIMREG[3:2]

D1

D0

Default

IBADJ[1:0]0x000Trim Output Regulator (V)Adjust Master Bias of the Analog Portion

TRIMREG[3:2]

IBADJ[1:0]

0

0

1.800

Default Current Consumption

0

1

1.610

25% Current Increase from Default

1

0

1.400

14% Current Decrease from Default

1

1

1.218

25% Current Decrease from Default

Trim regulator bits can be used only when VDDD <2.7V.

Low Power IP
Boost

Low Power ADC

Low Power
Speaker Driver

Low Power DAC

Microphone bias
Mode selection

Bit

LPIPBST[8]LPADC[7]LPSPKD[6]LPDAC[5]MICBIASM[4]0Normal Function

Normal Function

Normal Function

Normal Function

Disable1

Cut power in half

Cut power in half

Cut power in half

Cut power in half

EnableNote cutting the power in half will directly affect the audio performances.

Feb 1, 2023

Page 79 of 101

Rev 1.9

12.11.

PCM TIME SLOT CONTROL & ADCOUT IMPEDANCE OPTION CONTROL

12.11.1. PCM1 TIMESLOT CONTROL REGISTER

Addr

D8

D7

D6

D5

0x3B

D4

D3

D2

D1

D0

TSLOT[8:0]Default
0x000

Transmit and receive timeslot are expressed in number of BCLK cycles in a 10-bit word. The most significant bit
TSLOT[9] is located in register PCMTS2[0] address (0x3C). Timeslot, TSLOT[9:0], determines the start point for thetimeslot on the PCM interface for data in the transmit direction.

12.11.2. PCM2 TIMESLOT CONTROL REGISTER
Addr

D8

D7

0x3C

PCMTSEN

TRI

D6

D5

D4

PCM8BIT PUDOEN PUDPE

D3

D2

D1

PUDPS

LOUTR

PCMB

D0

Default

TSLOT[9] 0x000

PUDPE

PUDPS

iADCOUTADCOUT

PUDOE

Name

PCM Transit
EnableTri-state PCMTLSB

PCM Word Length

Left and Right
Channel havesame data

PCM Mode2

Bit

PCMTSEN[8]

TRI[7]

PCM8BIT[6]

LOUTR

PCMB

0

PCM A

Drive the full Clockof LSB

DisableDisable1

PCM Time Slot

Tri-State the 2nd
half of LSB

Use WLEN[6:5] toselect Word Length
Audio interface willbe 8 Bit Word
LengthEnableEnableIf TRI = 1 and PUDOEN = 0, the device will drive the LSB bit 1st half of BCLK out of the ADCOUT pin (stop driving
after LSB BCLK Rising edge) but if TRI = 0 or PUDOEN = 1 this feature is disabled, full BCLK of LSB will be driven
the LSB value.
Figure 35: The Programmable ADCOUT Pin

Feb 1, 2023

Page 80 of 101

Rev 1.9

Internal ADC
out data

Power Up and Down
Output Enable

Power Up andDown Pull Enable

Power Up and Down
Pull SelectOUTPUTiADCOUTPUDOEN[5]PUDPE[4]PUDPS[3]

PAD

0

1

x

x

0

1

1

x

x

1

x

0

0

x

Hi-Z

x

0

1

0

Pull-Low

x

0

1

1

Pull-High12.12.

REGISTER ID

12.12.1. Device revision register
Addr

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x3E

0

1

1

1

0

1

1

1

0

0x0EE

Device revision ID

12.12.2. 2-WIRE ID Register

Addr

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x3F

0

0

0

0

1

1

0

1

0

0x01A

First 7 bits (D0 – D6) of the 2-Wire device ID excluding the LSB /write bit.

12.12.3. Additional ID

Addr

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x40

0

1

1

0

0

1

0

1

0

0x0CA

ONLY
12.13. Reserved

Addr

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x41

1

0

0

1

0

0

1

0

0

0x124

Feb 1, 2023

Page 81 of 101

Rev 1.9

12.14.

Addr

OUTPUT Driver Control Register

D8

0x45

Bit
Location

0

2
4
5

D7

D6

0

D5

D4

SPKMOUT MOUTMT

D3

D2

D1

D0

Default

0

HVOPU

0

HVOP

0x001

Bit Value
Bit Description

Bit Name01

set internal output biasing to be
optimal for 3.6Vdc or lower
operation

set internal output biasing to be
optimal for higher than 3.6Vdc
operation

Note: For this to be effective
HVOPU[2] address 0x45 must
set

Override to automatic 3V/5V
bias selection

HVOP

Update bit for HV overridefeatureHVOPU

High Voltage override Disable

MOUTMT

DisableNote: For this to be effective
HVOPU[2] address 0x45
must setThis bit must set in conjunction
with HVOP[0] address 0x45 forthe automatic override to beeffective
EnableSPKMOUTDisableEnableHeadphone output muteSpeaker signals go to
MOUT

During mute, the MONO output will output VREF that can be used as a DC reference for a headphone out.

Feb 1, 2023

Page 82 of 101

Rev 1.9

12.15.

AUTOMATIC LEVEL CONTROL ENHANCED REGISTER

12.15.1.

ALC1 Enhanced Register

Addr

D8

D7

D6

D5

D4

D3

0x46 ALCTBLSEL ALCPKSEL ALCNGSELBit Description

Bit Name

6

Selects one of two tables
used to set the target level
for the ALC
Choose peak or peak-topeak value for ALC
threshold logic
Choose peak or peak-topeak value for Noise Gate
threshold logic

812.15.2.

D1

D0

ALCGAIN ( ONLY)

Bit
Location

7

D2

Default
0x001

Bit Value
0

1

ALCNGSEL

default recommended
target level table spanning 1.5dB through -22.5dB FS

optional ALC target level
table spanning -6.0dB
through -28.5dB FS

ALCPKSEL

use rectified peak detector
output value

use peak-to-peakdetector output value

ALCTBLSEL

use rectified peak detector
output value

use peak-to-peakdetector output value

ALC Enhanced 2 Register

Addr

D8

D7

0x47

PKLIMEN

D6

D5

D4

D3

D1

D0

0

Bit
Location

Bit Description

Bit Name

8

Enable control for ALC fastpeak limiter function

PKLIMENFeb 1, 2023

D2

Page 83 of 101

Default
0x000

Bit Value0

1

EnableDisableRev 1.9

12.16.

MISC CONTROL REGISTER

Addr

D8

0x49

0

Bit
Location

D7

D6

D5

D4

Bit Name0

Set DAC to use 256x
oversampling rate

DACOS2561

Enable control to use PLL
output when PLL is not inphase locked condition

PLLLOCKP

3
4
5

D2

D1

D0

Default

FSERRVAL[1:0] FSERFLSH FSERRENA NFDLY DACINMT PLLLOCKP DACOS256 0x000

Bit Description

2

D3

Enable control to mute
DAC limiter output whensoftmute is enabled
Enable control to delay useof notch filter output whenfilter is enabled
Enable control for shortframe cycle detection logic
Enable DSP state flush on
short frame sync event

Feb 1, 2023

DACINMTNFDLYFSERRENAFSERFLSH

Bit Value0
Use oversampling rate as
determined by Register 0x0A[3](default)1
Set DAC to 256x
oversampling rate regardlessof Register 0x0A[3]PLL VCO output disabled when
PLL is in unlocked condition(default)

PLL VCO output used as-is
when PLL is in unlocked
condition

DAC limiter output may not
move to exactly zero during
Softmute (default)
Delay using notch filter output
512 sample times after notch
enabled (default)
Short frame cycle detection
logic enabled
Ignore short frame sync events(default)

B1

B0

Short frame sync detection period value
trigger if frame time less than
FSERRVAL[1:0]00255 MCLK edges

01

253 MCLK edges

10

254 MCLK edges

1

1

255 MCLK edges

Page 84 of 101

DAC limiter output muted toexactly zero during Softmute
Use notch filter output
immediately after notch filter
is enabled
Short frame cycle detection
logic disabled
Set DSP state to initialconditions on short frame
sync event

Rev 1.9

12.17.

Output Tie-Off REGISTER

Addr

D8

D7

0x4B

0

LPSPKA

D6

D5

D4

D3

D2

D1

D0

Default

MANVREFH MANVREFM MANVREFL 0x000

Bit
Location

Bit Description

Bit Name0

Direct manual control for switch for
VREF 6k-ohm resistor to ground1

Bit Value
0

1

MANVREFL

switch to ground controlled
by Register 0x01 setting

switch to ground in theclosed position

Direct manual control for switch for
VREF 160k-ohm resistor to ground

MANVREFM

switch to ground controlled
by Register 0x01 setting

switch to ground in theclosed position2

Direct manual control of switch for
VREF 600k-ohm resistor to ground

MANVREFH

switch to ground controlled
by Register 0x01 setting

switch to ground in theclosed position

7

Amplifier StageLPSPKA

Two-stage amplifier for
speaker driverThree-stage amplifier for
speaker driver

12.18.
Addr

AGC PEAK-TO-PEAK OUT REGISTER
D8

D7

D6

D5

0x4C

D4

D3

D2

D1

D0

P2PDET

Default
0x000

Bit
Location

Bit Description

Bit Name

0–8

ONLY Register
Outputs the instantaneous value contained in the peak-to-peak amplitude register
used by the ALC for signal level dependent logic. Value is highest of left or right input
when both inputs are under ALC control.

P2PDET

12.19.
Addr

AGC PEAK OUT REGISTER
D8

0x4D

D7

D6

D5

D4

D3

D2

D1

PDET

D0

Default
0x000

Bit
Location

Bit Description

Bit Name

0–8

ONLY Register
Outputs the instantaneous value contained in the peak detector amplitude register
used by the ALC for signal level dependent logic. Value is highest of left or right
input when both inputs are under ALC control.

PDET

Feb 1, 2023

Page 85 of 101

Rev 1.9

12.20.

AUTOMUTE CONTROL AND STATUS REGISTER

Addr

D8

D7

0x4E

0

0

D6

D5

AMTCTRL HVDET

D4

D3

D2

D1

D0

Default

NSGATE

AMUTE

DMUTE

0

FTDEC

0x000

Bit Value

Bit
Location

Bit Description

Bit Name00Peak limiter indicator

FASTDEC

1

Below 87.5% of full scale

Above 87.5% of full scale

2

ONLY BIT
Digital Mute function of the DAC

DMUTEDigital gain greater than zero

Digital gain is zero either by.- Direct setting.- Softmute function

3

ONLY BIT
Analog Mute function applied to DAC

AMUTE

Automute Disabled

Automute Enabled

4

ONLY BIT
Logic controlling the Noise Gate

NSGATE

Signal is greater than the noisegate threshold and ALC gain
can change

Signal is less than the noisegate threshold and ALC gain
is held constant

5

ONLY BIT
High voltage detection circuit
monitoring VDDSPK voltage

HVDET

VDDSPK logic switch voltage
threshold measured as 4.0Vdc
or LessVDDSPK logic switch voltage
threshold measured as
4.0Vdc or Greater

6

Select observation point used by DAC
output Automute feature

AMTCTRL

Automute operates on data at
the input to the DAC digitalattenuator (default)

Automute operates on data at
the DACIN input pin

12.21.

Addr

Output Tie-off Direct Manual Control REGISTER

D8

D7

0x4F MANOUTEN SBUFH

Bit
Location
3

4

5

6

7

8

D6

D5

SBUFL SNSPKBit Description

D4

D3

D2

D1

D0

Default

SPSPK

SMOUT

0

0

0

0x000

Bit Value

Bit Name
0

If MANUOUTEN = 1, use this bit tocontrol Auxout1 output tie-off
resistor switch
If MANUOUTEN = 1, use this bit tocontrol left speaker output Tie-off
resistor switch
If MANUOUTEN = 1, use this bit tocontrol left speaker output Tie-off
resistor switch
If MANUOUTEN = 1, use this bit tocontrol bypass switch around 1.0x
non-boosted output Tie-off buffer
amplifierIf MANUOUTEN = 1, use this bit tocontrol bypass switch around 1.5x
boosted output Tie-off buffer
amplifier
Enable direct control over output
Tie-off resistor switching

Feb 1, 2023

1

SMOUT

Tie-off resistor switch for MOUT
output is forced open

SPSPK

Tie-off resistor switch for
SPKOUTP speaker output isforced open

Tie-off resistor switch for
MOUT output is forced
closedTie-off resistor switch for
SPKOUTP speaker output
is forced closed

SNSPK

Tie-off resistor switch for
SPKOUTN speaker output isforced open

Tie-off resistor switch for
SPKOUTN speaker output
is forced closed

SBUFL

Normal automatic operation of
bypass switch

Bypass switch in closed
position when output buffer
amplifier is disabled

SBUFH

Normal automatic operation of
bypass switch

Bypass switch in closed
position when output buffer
amplifier is disabled

MANOUTEN

Ignore Register 0x4F bits tocontrol input Tie-off
resistor/buffer switching

Use Register 0x4F bits tooverride automatic Tie-off
resistor/buffer switching

Page 86 of 101

Rev 1.9

13. CONTROL INTERFACE TIMING DIAGRAM
13.1. 2-WIRE TIMING DIAGRAMTSTAHTSDIOSTSDIOH

TSTAH

SDIO

TSCKH

TFALL

SCLK
TSCKL

TRISE

TSTAS

TSTOS

Figure 36: 2-Wire Timing Diagram

SYMBOLDESCRIPTION

MIN

TYP

MAX

UNIT

TSTAH

START / Repeat START condition, SCLK falling edge to
SDIO falling edge hold timing

600

---

---

ns

TSTAS

Repeat START condition, SDIO rising edge to SCLK
falling edge setup timing

600

---

---

ns

TSTOS

STOP condition, SDIO rising edge to SCLK rising edge
setup timing

600

---

---

ns

TSCKH

SCLK High Pulse Width

600

---

---

ns

TSCKL

SCLK Low Pulse Width

1.3

---

---

us

TRISE

Rise Time for all 2-Wire Signals

---

---

300

ns

TFALL

Fall Time for all 2-Wire Signals

---

---

300

ns

TSDIOSSDIO to SCLK Rising Edge DATA Setup Time

400

---

---

ns

TSDIOHSCLK falling Edge to SDIO DATA Hold Time

0

---

600

ns

Table 31: 2-WireTiming Parameters

Feb 1, 2023

Page 87 of 101

Rev 1.9

14. AUDIO INTERFACE TIMING DIAGRAM
14.1. AUDIO INTERFACE IN SLAVE MODE

TBCK

TFALL

TRISE

BCLK
(Slave)
TFSH

TBCKH

TFSH
TBCKL

TFSS

TFSS

FS
(Slave)
TDIS
TDIH

DACIN

TDOD

ADCOUT

Figure 37: Audio Interface Slave Mode Timing Diagram
14.2. AUDIO INTERFACE IN MASTER MODE

BCLK
(Master)
TFSD

TFSD

FS
(Master)
TDIS
TDIH

DACIN

TDOD

ADCOUT

Figure 38: Audio Interface in Master Mode Timing DiagramFeb 1, 2023

Page 88 of 101

Rev 1.9

14.3. PCM AUDIO INTERFACE IN SLAVE MODE (PCM Audo Data)

TBCK

TFALL

TRISE

BCLK
(Slave)
TFSH

TBCKH

TFSH

TBCKL

TFSS

TFSS

FS
(Slave)
TDIS
TDIH

MSB

DACIN

TDOD

MSB

ADCOUT

Figure 39: PCM Audio Interface Slave Mode Timing Diagram
14.4. PCM AUDIO INTERFACE IN MASTER MODE (PCM Audo Data)

BCLK(Master)
TFSD

TFSD

TFSD

FS
(Master)
TDIS
TDIH

DACIN

MSB

TDOD

ADCOUT

MSB

Figure 40: PCM Audio Interface Slave Mode Timing DiagramFeb 1, 2023

Page 89 of 101

Rev 1.9

14.5. PCM AUDIO INTERFACE IN SLAVE MODE (PCM Time Slot Mode )

TBCK

TFALL

TRISE

BCLK
(Slave)
TFSH

TBCKH

TFSH

TBCKL

TFSS

TFSS
FS
(Slave)

TDIS
TDIH
DACIN

MSB
TDOD1
TDOD

ADCOUT

MSB

Figure 41: PCM Audio Interface Slave Mode (PCM Time Slot Mode )Timing Diagram
14.6. PCM AUDIO INTERFACE IN MASTER MODE (PCM Time Slot Mode )BCLK(Master)
TFSD

TFSD

FS
(Master)

TDIS
TDIH
DACIN

MSB

TDOD

ADCOUT

MSB

Figure 42: PCM Audio Interface Master Mode (PCM Time Slot Mode )Timing DiagramFeb 1, 2023

Page 90 of 101

Rev 1.9

SYMBOLDESCRIPTION

MIN

TYP

MAX

UNIT

TBCK

BSCK Cycle Time (Slave Mode)

50

---

---

ns

TBCKH

BSCK High Pulse Width (Slave Mode)

20

---

---

ns

TBCKL

BSCK Low Pulse Width (Slave Mode)

20

---

---

ns

TFSS

fs to SCK Rising Edge Setup Time (Slave Mode)

20

---

---

ns

TFSH

SCK Rising Edge to fs Hold Time (Slave Mode)

20

---

---

ns

TFSD

fs to SCK falling to fs transition (Master Mode)

---

---

10

ns

TRISE

Rise Time for All Audio Interface Signals

---

---

0.135TBCK

ns

TFALL

Fall Time for All Audio Interface Signals

---

---

0.135TBCK

ns

TDIS

ADCIN to SCK Rising Edge Setup Time

15

---

---

ns

TDIH

SCK Rising Edge to ADCIN Hold Time

15

---

---

ns

TDOD

Delay Time from SCLK falling Edge to DACOUT

---

---

10

ns

Table 32: Audio Interface Timing Parameters14.7. System Clock (MCLK) Timing Diagram

TMCLKHMCLK

TMCLKL

Figure 43: MCLK Timing Diagram

PARAMETERMCLK Duty Cycle

SYMBOLTMCLKDCTEST CONDITIONS

MIN
60:40

TYP

MAX
40:60

UNIT

MCLK High Pulse Width

TMCLKH

20

---

---

ns

MCLK Low Pulse Width

TMCLKL

20

---

---

ns

Table 33: MCLK Timing ParameterFeb 1, 2023

Page 91 of 101

Rev 1.9

14.8. µ-LAW ENCODE DECODE CHARACTERISTICS
Normalized
EncodeDecision
LevelsDigital Code
D4
D3

D2

D1

D0

Step

Step

Step

Step

Normalized
DecodeLevels

0

0

0

0

0

8031

:

:

:

:

:

:

:

0

0

0

1

1

1

1

4191

:

:

:

:

:

:

:

:

:

1

0

0

1

1

1

1

1

2079

:

:

:

:

:

:

:

:

:

1

0

1

0

1

1

1

1

1023

:

:

:

:

:

:

:

:

:

1

0

1

1

1

1

1

1

495

:

:

:

:

:

:

:

:

:

1

1

0

0

1

1

1

1

231

:

:

:

:

:

:

:

:

:

1

1

0

1

1

1

1

1

99

:

:

:

:

:

:

:

:

:

D7

D6

D5

Sign

Chord

Chord

Chord

1

0

0

:

:

1

8159
7903
:
4319
4063
:
2143
2015
:
1055
991
:
511
479
:
239
223
:
103
95
:
35

1

1

1

0

1

1

1

1

33

31
:
3

:

:

:

:

:

:

:

:

:

1

1
:
1

1
:
1

1
:
1

1
:
1

1
:
1

1
:
1

1
:
1

0
:
1

2
:
0

0

Notes:
Sign bit = 0 for negative values, sign bit = 1 for positive values

Feb 1, 2023

Page 92 of 101

Rev 1.9

14.9. A-LAW ENCODE DECODE CHARACTERISTICS
Normalized
EncodeDecision
LevelsDigital Code
D4
D3

D2

D1

D0

Step

Step

Step

Step

Normalized
DecodeLevels

0

1

0

1

0

4032

:

:

:

:

:

:

:

0

1

0

0

1

0

1

2112

:

:

:

:

:

:

:

:

:

1

0

1

1

0

1

0

1

1056

:

:

:

:

:

:

:

:

:

1

0

0

0

0

1

0

1

528

:

:

:

:

:

:

:

:

:

1

0

0

1

0

1

0

1

264

:

:

:

:

:

:

:

:

:

1

1

1

0

0

1

0

1

132

:

:

:

:

:

:

:

:

:

1

1

1

0

0

1

0

1

66

:

:

:

:

:

:

:

:

:

1

1

0

1

0

1

0

1

1

D7

D6

D5

Sign

Chord

Chord

Chord

1

0

1

:

:

1

4096
3968
:

2176
2048
:

1088
1024
:

544
512
:

272
256
:

136
128
:

68
64
:

2
0

Notes:
1. Sign bit = 0 for negative values, sign bit = 1 for positive values
2. Digital code includes inversion of all even number bits

Feb 1, 2023

Page 93 of 101

Rev 1.9

14.10.

µ-LAW / A-LAW CODES FOR ZERO AND FULL SCALE

µ-Law
Level

A-Law

Sign bit(D7)

Chord bits
(D6,D5,D4)

Step bits(D3,D2,D1,D0)

Sign bit(D7)

Chord bits
(D6,D5,D4)

Step bits(D3,D2,D1,D0)+ Full Scale

1

000

0000

1

010

1010

+ Zero

1

111

1111

1

101

0101

- Zero

0

111

1111

0

101

0101

- Full Scale

0

000

0000

0

010

1010

14.11.

µ-LAW / A-LAW OUTPUT CODES (DIGITAL MW)µ-Law
SampleA-Law

Sign bit(D7)

Chord bits
(D6,D5,D4)

Step bits(D3,D2,D1,D0)

Sign bit(D7)

Chord bits
(D6,D5,D4)

Step bits(D3,D2,D1,D0)

1

0

001

1110

0

011

0100

2

0

000

1011

0

010

0001

3

0

000

1011

0

010

0001

4

0

001

1110

0

011

0100

5

1

001

1110

1

011

0100

6

1

000

1011

1

010

0001

7

1

000

1011

1

010

0001

8

1

001

1110

1

011

0100

Feb 1, 2023

Page 94 of 101

Rev 1.9

15. DIGITAL FILTER CHARACTERISTICSPARAMETERTESTCONDITIONS

MIN+/- 0.025dB

0

TYP

MAX

UNIT

ADC Filter
0.454*fs

Passband-6dB

0.5*fsPassband Ripple+/-0.025

StopbanddB

0.546*fs

Stopband
Attenuationf > 0.546*fs-60

Group Delay

dB
21/fs

ADC High Pass Filter

High Pass Filter
Corner Frequency

-3dB

3.7

-0.5dB

10.4-0.1dB

21.6

Hz

DAC Filter+/- 0.035dB

00.454*fs

Passband-6dB

0.5*fsPassband Ripple+/-0.035

Stopband
Stopband
AttenuationdB

0.546*fs
f > 0.546*fs-55

Group Delay

dB
29/fs

Table 57 Digital Filter Characteristics
TERMINOLOGY
1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band)
2. Pass-band Ripple – any variation of the frequency response in the pass-band region
3. Note that this delay applies only to the filters and does not include

Feb 1, 2023

Page 95 of 101

Rev 1.9

Figure 44: DAC Filter Frequency Response

Figure 45: ADC Filter Frequency Response

Figure 46: DAC Filter Ripple

Figure 47: ADC Filter Ripple

Feb 1, 2023

Page 96 of 101

Rev 1.9

16. TYPICAL APPLICATION

VDDA

VDDD

VDDSPKVSSSPK
2
4

17
4.7µF
4.7µF

VDDA
VDDD

VSSA
VSSD

SPKOUT+SPKOUT-

4.7uF

1uF

4.7uF

1uF

1
20
19
18

1.2 K Ohm

3
5
0 Ohm

VDDSPK

NAU8810
1.2 K Ohm

15

MICBIAS
MIC+
MIC-

14
16

MOUT

13

MCLK
BCLK
FS

10
9

ADCOUT
DACIN

1uF

Digital Audio
Interface

8
6
7

200 Ohm for Digital Audio Interface

VREF

SCLK
SDIO

4.7uF

11
200

12

33PF

200

ControlInterface

33PF

Figure 48: Application Diagram For 20-Pin QFNNote 1: All non-polar capacitors are assumed to be low ESR type parts, such as with MLC construction or similar. If
capacitors are not low ESR, additional 0.1uF and/or 0.01uF capacitors may be necessary in parallel with thebulk 4.7uF capacitors on the supply rails.
Note 2: Load resistors to ground on outputs may be helpful in some applications to insure a DC path for the output
capacitors to charge/discharge to the desired levels. If the output load is always present and the output load
provides a suitable DC path to ground, then the additional load resistors may not be necessary. If needed,such load resistors are typically a high value, but a value dependent upon the application requirements.
Note 3: To minimize pops and clicks, large polarized output capacitors should be a low leakage type.
Note 4: Depending on the microphone device and PGA gain settings, common mode rejection can be improved bychoosing the resistors on each node of the microphone such that the impedance presented to any noise on
either microphone wire is equal.
Note 5: SCLK and SDIO are added a low pass filter to prevent glitch; the corner frequency is 8MHz to 33Mhz.

Feb 1, 2023

Page 97 of 101

Rev 1.9

17. PACKAGE SPECIFICATION

Feb 1, 2023

Page 98 of 101

Rev 1.9

18. ORDERING INFORMATIONPart Number
NAU8810YG

Dimension
4x4 mmPackage
QFN-20

Package Material
Green

NAU8810 _ _Package Material:
G=

Green Package (Halogen-free, RoHS-compliant)& TSCA-compliant

Package Type:Y=
QFN-20Feb 1, 2023

Page 99 of 101

Rev 1.9

19. REVISION HISTORYREVISIONDATE

DESCRIPTION

1.0

Jan, 2016

Initial Release

1.1

Aug, 2016

Revision ID changed

1.2

Mar, 2017

Adding power consumption table for various applications

1.3

Nov, 2017

PLL integers range changed from 6-12 to 5-13
0x3[5] removal ADDED READ ONLY for READ ONLY
Register
0x5[5] removal
12.4.1.1 ALC description
Damping resistors added for I2S, and low pass filter for I2C
in typical application diagram
0x45[5] adding SPKMOUT
Added 12.6.3 differential output configuration secession

1.4

Feb,2018

1.5

Mar, 2018

1.6

Sep, 2019

1.7

Sep 13, 2022

Update junction temperature information

1.8

Jan 10, 2023

Update Table 24

1.9

Feb 1, 2023

Update Halogen-free, RoHS-compliant and TSCA-compliant
description

Feb 1, 2023

Page 100 of 101

Rev 1.9

IMPORTANT NOTICE
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or
failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are
deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control
instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems
designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended
to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton
as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by
Nuvoton.

Feb 1, 2023

Page 101 of 101

Rev 1.9