NAU8315 DataSheet

Feb 1, 2023

Page 1 of 42

Rev 1.8

1 Contents
1

CONTENTS .................................................................................................................................... 2
1.1

List of Figures ......................................................................................................................................... 4

1.2

List of Tables .......................................................................................................................................... 42

GENERAL DESCRIPTION ............................................................................................................ 53

PIN CONFIGURATIONS ................................................................................................................ 74

PIN DESCRIPTIONS ................................................................................................................... 10

5

SYSTEM DIAGRAM ..................................................................................................................... 11
5.1

Reference System Diagram.................................................................................................................. 11

6

BLOCK DIAGRAM ....................................................................................................................... 127

ELECTRICAL CHARACTERISTICS ............................................................................................ 13
7.1

Absolute Maximum Ratings .................................................................................................................. 13

7.2

Operating Conditions ............................................................................................................................ 13

7.3

Electrical Parameters............................................................................................................................ 13

7.4

Digital Input Parameters ....................................................................................................................... 15

7.5

Typical Operating Plots......................................................................................................................... 16

8

FUNCTIONAL DESCRIPTION..................................................................................................... 21
8.1

Inputs .................................................................................................................................................... 21

8.2

Outputs ................................................................................................................................................. 23

8.3

Digital Interfaces ................................................................................................................................... 23

8.4

Power Supply ....................................................................................................................................... 23

8.5Power-On-and-Off Reset ...................................................................................................................... 24

8.6

Power Up & Down Sequence ............................................................................................................... 24

8.7

Clocking and Sample Rates ................................................................................................................. 25

8.7.1

Clock Control and Detection .......................................................................................................... 25

8.7.2

Automatic Power Control and Mute. .............................................................................................. 25

8.7.3

Input Clock Rates .......................................................................................................................... 26

8.7.4

Sample and Over Sampling Rates ................................................................................................ 27

8.8

Automatic Level Control........................................................................................................................ 29

8.8.1

ALC Operation ............................................................................................................................... 29

8.8.2

ALC Parameter Definitions ............................................................................................................ 29

8.9

Device Protection ................................................................................................................................. 31

8.10Power-up and Power-Down Control ..................................................................................................... 31

8.11

Bypass Capacitors ................................................................................................................................ 31

8.12

Printed Circuit Board Layout Considerations ........................................................................................ 31

8.12.1
8.13

PCB Layout Notes ......................................................................................................................... 32

Filters .................................................................................................................................................... 32

8.13.1

Feb 1, 2023

Class D without Filters ................................................................................................................... 32

Page 2 of 42

Rev 1.8

8.13.2

9Class D with Filters ........................................................................................................................ 32

CONTROL .................................................................................................................................... 35
9.1

Digital Audio Interface........................................................................................................................... 35

9.1.1

I2S Audio Data .............................................................................................................................. 35

9.1.2

PCM Time Slot Audio Data ............................................................................................................ 35

9.2

Digital Audio Interface Timing Diagrams............................................................................................... 36

9.2.1

I2S Audio Interface ........................................................................................................................ 36

9.2.2

PCM Audio .................................................................................................................................... 37

10

PACKAGE SPECIFICATION ....................................................................................................... 38

11

ORDERING INFORMATION ........................................................................................................ 41

12

REVISION HISTORY ................................................................................................................... 42

IMPORTANT NOTICE ........................................................................................................................... 43

Feb 1, 2023

Page 3 of 42

Rev 1.8

1.1

List of Figures

Figure 1

Pin Configuration of WLCSP12 NAU8315 (TOP VIEW) .......................................................................7

Figure 2

Pin Configuration of WLCSP9 NAU8315 (TOP VIEW) .........................................................................8

Figure 3

Pin Configuration of QFN20 NAU8315 .................................................................................................9

Figure 4

NAU8315 Simplified System Diagram ................................................................................................ 11

Figure 5

NAU8315 Block Diagram ................................................................................................................... 12

Figure 6

NAU8315 Power Up & Down Sequence ............................................................................................ 24

Figure 7

NAU8315 Clock Detection Circuit ...................................................................................................... 25

Figure 8

PWRUPEN startup sequence. ........................................................................................................... 26

Figure 9

ALC Control Loop Block Diagram ...................................................................................................... 29

Figure 10

NAU8315 Speaker Connections without Filter ................................................................................... 32

Figure 11

NAU8315 Speaker Connections with Ferrite Bead Filters.................................................................. 33

Figure 12

NAU8315 Speaker Connections with LC Filters ................................................................................. 33

Figure 13

NAU8315 Speaker Connections with Low-Pass Filters...................................................................... 33

Figure 14

I2S Audio Data ................................................................................................................................... 35

Figure 15

PCM Time Slot Audio Data ................................................................................................................ 36

Figure 16

I2S Audio Interface............................................................................................................................. 36

Figure 17

PCM Audio Interface .......................................................................................................................... 37

1.2

List of Tables

Table 1

Pin Descriptions for the NAU8315 ....................................................................................................... 10

Table 2GAIN Configurations for the NAU8315 ................................................................................................ 21

Table 3

Audio Interface Configurations for the NAU8315 ................................................................................. 22

Table 4

Range of Input Clocks ......................................................................................................................... 26

Table 5

BCLK/FS ratios and Over Sampling Rates .......................................................................................... 27

Table 6

Ranges of Sampling Frequencies and BCLK Rates ............................................................................ 28

Table 7

Digital Audio Interface Timing Parameter .......................................................................................... 37

Feb 1, 2023

Page 4 of 42

Rev 1.8

2 GENERAL DESCRIPTIONThe NAU8315 is a mono high efficiency filter-free Class-D audio amplifier, which is capable of driving a4Ω load with up to 3.2W output power. This device provides Enable control and I2S audio input with low
standby current and fast start-up time.
The NAU8315 is ideal for the portable applications, as it has advanced features like 80dB PSRR, 91%
efficiency, ultra-low quiescent current and superior EMI performance. NAU8315 is available in a 12 ballMiniature WLCSP package, a 9 ball Miniature WLCSP package and a 20-pin QFN package.
Key Features












Pin Selectable Gain Setting
Pin Selectable I2S Left or Right Channel
selection
Pin Selectable PCM time slot
Low Output Noise: 12 µVRMS
80dB PSRR @217Hz
Low Current Shutdown and Standby Modes
Click-and Pop Suppression: 26 µVRMS
Sampling rate from 8K to 96 KHz
Package: 9 or 12 ball WLCSP & 20-pin QFNPowerful Mono Class-D Amplifier:
3.2W (4Ω @ 5V, 10% THD+N)

Feb 1, 2023






1.76W (4Ω @ 4.2V, 1% THD+N)
1.8W (8Ω @ 5V, 10% THD+N)
1.0W (8Ω @ 4.2V, 1% THD+N)
Package is Halogen-free, RoHS-compliant andTSCA-compliant

Applications
 Gaming Controllers
 Wireless (VR) Headset
 Smart Remote Controller
 Notebooks / Tablet PCs
 Personal Media Players
 Ultrasonic speakers

Page 5 of 42

Rev 1.8

3 PIN CONFIGURATIONSThe NAU8315 12 Ball WLCSP package is shown in Figure 1.

TOP VIEW
2

3

OUTN

VSS

OUTP

A

GAIN

VDD

EN

B

FSL

VDD

FSR

C

DACIN

VDD

BCLK

D

Part Number

Dimension

NAU8315B31VG

1.18mm x
1.95mmFigure 1

Feb 1, 2023

1

Package12-bumpWLCSP

Package
MaterialGreen(0.4 mm pitch)

Pin Configuration of WLCSP12 NAU8315 (TOP VIEW)

Page 7 of 42

Rev 1.8

The NAU8315 9 Ball WLCSP package is shown in Figure 1.

TOP VIEW
2

3

OUTN

VSS

OUTP

A

FSL

VDD

FSR

B

DACIN

NC

BCLK

C

Part Number

Dimension

NAU8315A31VG

1.18mm x
1.95mmFigure 2

Feb 1, 2023

1

Package
9-bumpWLCSP

Package
MaterialGreen(0.4 mm pitch)

Pin Configuration of WLCSP9 NAU8315 (TOP VIEW)

Page 8 of 42

Rev 1.8

The NAU8315 20-pin QFN package is shown in Figure 1.

QFN exposed thermal pad must be connected to VSS

Part Number

Dimension

Package

Package
Material

NAU8315YG

4mm x 4mm

QFN-20Green

Figure 3

Feb 1, 2023

Pin Configuration of QFN20 NAU8315

Page 9 of 42

Rev 1.8

4 PIN DESCRIPTIONS
Pin descriptions for the NAU8315 are provided in Table 1.
Table 1

Pin Descriptions for the NAU8315

12 BallWLCSP#

9 BallWLCSP#

20-pin
QFN #

Name

Type

D1

C1

9

DACIN

Digital Input

I2S I/F DAC digital audio data

C1

B1

8

FSL

Digital Input

I2S I/F Left Channel Frame clock

B1

-

13

GAIN

Analog IO

Gain Selection

A1

A1

16

OUTN

Analog Output

B2

B2

2

VDD

SupplyPower Supply

C2

-

11

VDD

SupplyPower Supply

D2

-

14

VDD

SupplyPower Supply

A2

A2

4,12,17,

VSS

SupplyGroundDescription

Speaker negative output

18,19
D3

C3

6

BCLK

Digital Input

I2S I/F bit clock

C3

B3

7

FSR

Digital Input

I2S I/F Right Channel Frame clock

B3

-

3

EN

Digital Input

Device Enable Input

A3

A3

20

OUTP

Analog Output

Speaker positive output

-

C2**

1,5,

NC

No Connection

No Connection

10,15***Note: For WLCSP9 the NC ball C2 can be tied to VDD for convenient PCB layout.
*Note: For 20 pin QFN the NC pins can be tied to VSS for convenient PCB layout.

Feb 1, 2023

Page 10 of 42

Rev 1.8

5 SYSTEM DIAGRAM
5.1 Reference System Diagram
A basic system reference diagram for stereo I2S is provided in Figure 4.

Figure 4

Feb 1, 2023

NAU8315 Simplified System Diagram

Page 11 of 42

Rev 1.8

6 BLOCK DIAGRAM
A Block Diagram for the NAU8315 is provided in Figure 5.

UVLO
FSL

Bandgap

TalarmShutdown
Control

EN

VDD

Digital Core Supply

FSR

Clock
Detection

BCLK

Clock
Doubler

ADC

GAIN

L,R,CH0,CH1, (L+R)/2

DACIN

Serial Audio
Interface

Clip
VDD

Softunmute& GainInterpolation

Filter

DAC

Class-D
Modulator

Short
Circuit
Protection

Slew
Rate
Control

VSS

VDD

pseudorandomRamp
AnalogDigitalFigure 5

Feb 1, 2023

OUTP

Short
Circuit
Protection

Slew
Rate
Control

OUTN

VSS

NAU8315 Block Diagram

Page 12 of 42

Rev 1.8

7 Electrical Characteristics
The tables in this chapter provide the various electrical parameters for the NAU8315 and their values.

7.1

Absolute Maximum Ratings
Parameter

Min

Max

Units

VDD Battery Supply Range

-0.3

6.0

V

Voltage Input I/O Range

VSS - 0.3

VDD + 0.3

V

Junction Temperature, TJ

-40

+150

°C

Storage Temperature

-65

+150

°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure
to such conditions may adversely influence product reliability and result in failures notcovered by the warranty.

7.2 Operating Conditions
Recommended Operating Conditions
Condition

SymbolMin

Typical

Max

Units

VDD

2.50

4.2

5.25

V

Battery Supply Range
Digital IO Range
Ground1.8
VSS

Industrial Operating Temperature

VDD
0

-40

V
+85

°C

7.3 Electrical Parameters
Conditions: VDD= 4.2V. RL = 8 Ω + 33 µH, f = 1kHz, 48kHz sample rate, BCLK=12.288MHz, gain=12dB, unlessotherwise specified. Limits apply for TA = 25°C
SymbolParameter

Conditions

Typical

Limit

Units

ISD

Shutdown Supply Current

VDD, all clocks off

0.3

16

µA

ISB

Standby Mode Supply Current

VDD, clocks off, EN=VDD

0.3

µA

IDD

Operating Mode Supply Current

VDD, idle Channel

4.0

mA

VDD=4.2V RL = 8 Ohm + 33 µH and
Total Harmonic Distortion+Noise(THD+N) = 1%, Gain=12dB, QFN-20

0.98

W

VDD=4.2V RL = 8 Ohm + 33 µH and
Total Harmonic Distortion+Noise(THD+N) = 1%, Gain=12dB, WLCSP12

1.0

WClass-D Channel

PO

Feb 1, 2023

Output Power

Page 13 of 42

Rev 1.8

SymbolParameter

Conditions

Typical

Limit

Units

VDD=5V RL = 8 Ohm + 33 µH and
Total Harmonic Distortion+Noise(THD+N) = 10%, Gain=12dB, QFN-20

1.73

W

VDD=5V RL = 8 Ohm + 33 µH and
Total Harmonic Distortion+Noise(THD+N) = 10%, Gain=12dB, WLCSP12

1.8

W

VDD=4.2V RL = 4 Ohm + 33 µH and
Total Harmonic Distortion+Noise(THD+N) = 1%, Gain=12dB, QFN-20

1.69

W

VDD=4.2V RL = 4 Ohm + 33 µH and
Total Harmonic Distortion+Noise(THD+N) = 1%, Gain=12dB, WLCSP12

1.76

W

VDD=5V RL = 4 Ohm + 33 µH and
Total Harmonic Distortion+Noise(THD+N) = 10%, Gain=12dB, QFN-20

3.03

W

VDD=5V RL = 4 Ohm + 33 µH and
Total Harmonic Distortion+Noise(THD+N) = 10%, Gain=12dB, WLCSP12

3.2

W

THD+N

Total Harmonic Distortion +Noise

RL = 8 Ω + 33 µH, f=1kHz, PO = 0.15
W, Gain=12dB

0.017

%

eOS

Output Noise

A-Weighted, 20Hz-20kHz, no DAC
input signal

11.8

µVrms

DC, VDD = 3.2V – 4.2V, amplifiervoltage GAIN = 6dB

85

dB

fRIPPLE = 1020Hz, VRIPPLE = 100mVP_P
amplifier voltage GAIN = 6dB

82

fRIPPLE = 4kHz, VRIPPLE = 100mVP_P
amplifier voltage GAIN = 6dB

77

PSRR

Power Supply Rejection Ratio(Note 1)

60

dB
dB

+0.06/

Fres

Frequency Response

F = 20Hz ~ 20KHz, 1Watt, RL = 8 Ω +
33 µH

VOS

Output Offset Voltage

Idle Channel, Gain= 6dB±1

A-weighted, Idle DAC input, toggling
clocks on/off, Gain= 6dB

0.026

mVrms

A-weighted, Idle DAC input, toggling
EN pin with clocks running, Gain= 6dB

0.019

mVrms

Average

300

Kpop

Fsw

dB

-0.06
±5

mV

Pop and Click Noise

Switching Frequency

400

kHz

Class-D
Neff

Feb 1, 2023

Power Efficiency

Output Power = 1.48W, VDD = 4.2 V

Page 14 of 42

91%

Rev 1.8

Note 1 : PSRR = 20 x LOG10(GAIN x ∆VDD/∆(SPKP-SPKN)) dB

7.4 Digital Input Parameters
Digital Inputs FS, BCLK, DACIN & EN.
Parameter

SymbolComments/Conditions

Input LOW level

VIL

VDD = 2.5V – 5.25V

Input HIGH level

VIH

VDD = 2.5V – 5.25V

1.4*

Input Leakage Current

IIL

VDD = 2.5V – 5.25V-0.001

Note:

Min

Max

Units

0.4

V
V

+0.001mA

I2S signals can be 1.8V

Feb 1, 2023

Page 15 of 42

Rev 1.8

7.5 Typical Operating Plots
Conditions: VDD= 4.2V. RL = 8 Ω + 33 µH, f = 1kHz, 48kHz sample rate, BCLK=12.288MHz, TA = 25°C,
gain=12dB, unless otherwise specified.
QFN
WLCSP
Normalised Frequency Response Sample
Rate=96kHz

1

0.5

0.5

0

0

Normalized Level (dB)Normalized Level (dB)Normalised Frequency Response
1

-0.5
-1
-1.5
3.7V
-2

-1
-1.5
3.7V
-2

4.2V

-2.5
-3

10

100

1000

4.2V
5V

5V
-2.5
-3

-0.5

10000

100000

10

100

QFN

100000THDN vs Frequency Vdd=5.0V Rl=4 Ohms

0

0

-10

-10

-20

-20

100mW
500mW

-30
-40
-50
-60

-50
-60
-70

-80

-80

-90

-90

-100

-100

100

1000

10000

500mW

-40

-70

10

100mW

-30

THDN (dB)

THDN (dB)

10000

QFN
THDN vs Frequency Vdd=5.0V Rl=8 Ohms

100000

10

100

1000

10000

100000Frequency (Hz)Frequency (Hz)

QFN

QFN
THDN vs Frequency Vdd=4.2V Rl=4 Ohms

THDN vs Frequency Vdd=4.2V Rl=8 Ohms
0

0

-10

-10

-20

-20

100mW
500mW

-30
-40
-50
-60

-50
-60
-70

-80

-80

-90

-90

-100

-100

100

1000

10000

100000

10

100

1000

10000

100000Frequency (Hz)Frequency (Hz)Feb 1, 2023

500mW

-40

-70

10

100mW

-30

THDN (dB)

THDN (dB)1000
Frequency (Hz)Frequency (Hz)Page 16 of 42

Rev 1.8

Conditions: VDD= 4.2V. RL = 8 Ω + 33 µH, f = 1kHz, 48kHz sample rate, BCLK=12.288MHz, TA = 25°C,
gain=12dB, unless otherwise specified.
QFN
QFN
THDN vs Frequency Vdd=3.7V Rl=8 Ohms

THDN vs Frequency Vdd=3.7V Rl=4 Ohms

0

0

-10

-10

-20

500mW

-30
-40
-50
-60

-50
-60
-70

-80

-80

-90

-90

-100

-100

100

1000

10000

500mW

-40

-70

10

100mW

-30

THDN (dB)

THDN (dB)

-20

100mW

100000

10

100

1000

Frequency (Hz)

10000

100000Frequency (Hz)

WLCSP
0
-10

Vspk=5V
Zspk=4Ohm+33uH"-20
THD+N(dB)

-30
-40
-50

Po=100mW-60

Po=500mW

-70
-80
-90
-100

10

100

1000

10000

100000Frequency(Hz)

WLCSP
0
-10
-20

Vspk=4.2V
Zspk=4Ohm+33uH

THD+N(dB)

-30
-40
-50

Po=100mW-60

Po=500mW

-70
-80
-90
-100

10

100

1000

10000

100000Frequency(Hz)Feb 1, 2023

Page 17 of 42

Rev 1.8

WLCSP
0-10-20

Vspk=3.7V
Zspk=4Ohm+33uH

THD+N(dB)

-30
-40
-50

Po=100mW-60

Po=500mW

-70
-80
-90
-100

10

100

1000

10000

100000Frequency (Hz)QFN package

QFN package
THDN vs Output Power Vdd=5.0V Rl=4 Ohms
0

-10

-10

-20

-20

-30

-30

-40

-40

THDN (dB)

THDN (dB)

THDN vs Output Power Vdd=5.0V Rl=8 Ohms
0

-50
-60
-70

-50
-60
-70

100Hz

-80
-90

0.01

0.1

1

1kHz

-90

6kHz

-100
0.001

100Hz

-80

1kHz

6kHz

-100
0.001

10

0.01

Output Power (W)QFN package

10

1

QFN package
THDN vs Output Power Vdd=4.2V Rl=4 Ohms

THDN vs Output Power Vdd=4.2V Rl=8 Ohms
0

0

-10

-10

-20

-20

-30

-30

-40

100Hz

-50

THDN (dB)

THDN (dB)0.1
Output Power (W)

1kHz
6kHz

-60

-40

-70

-80

-80

-90

-90

-100
0.001

-100
0.001

0.1

1

10

1kHz
6kHz

-60

-70

0.01

100Hz

-50

0.01

0.1

1

10

Output Power (W)Output Power (W)Conditions: VDD= 4.2V. RL = 8 Ω + 33 µH, f = 1kHz, 48kHz sample rate, BCLK=12.288MHz, TA = 25°C,
gain=12dB, unless otherwise specified.

Feb 1, 2023

Page 18 of 42

Rev 1.8

QFN package

QFN package
THDN vs Output Power Vdd=3.7V Rl=4 Ohms

THDN vs Output Power Vdd=3.7V Rl=8 Ohms
0

0

-10

-10

-20

-20

-30

-30
100Hz

-50

1kHz
6kHz

-60

-40

THDN (dB)

THDN (dB)

-40

100Hz

-50

1kHz
6kHz

-60

-70

-70

-80

-80

-90

-90

-100
0.001

-100
0.001

0.01

0.1

1

10

0.01

QFN package

90

90

80

80

70

70

60

Efficiency (%)

Efficiency (%)

100

3V7

50

4V2
5V0

40

60

30
20

10

10

1

1.5

0

2

4V2
5V0

40

20

0.5

3V7

50

30

0

1

WLCSP package

3

4

WLCSP package
THDN vs Output Power 5.0V Rl=4 Ohms

THDN vs Output Power 5.0V 8 Ohms
0

0

-10

-10

-20

-20

-30

-30

-40

-40

THDN (dB)

THDN (dB)2
Output Power (W)Output Power (W)

-50
-60

-50
-60
-70

-70
100Hz

-80

0.1

1

1kHz

-90

6kHz
0.01

100Hz

-80

1kHz

-90
-100
0.001

10

Efficiency vs Output Power Rl=4 Ohms

100

0

1

QFN package

Efficiency vs Output Power Rl=8 Ohms

00.1
Output Power (W)Output Power (W)

10

-100
0.001

6kHz
0.01

0.1

1

10

Output Power (W)Output Power (W)Conditions: VDD= 4.2V. RL = 8 Ω + 33 µH, f = 1kHz, 48kHz sample rate, BCLK=12.288MHz, TA = 25°C,
gain=12dB, unless otherwise specified.

Feb 1, 2023

Page 19 of 42

Rev 1.8

WLCSP package

WLCSP package
THDN vs Output Power 4.2V Rl=4 Ohms

THDN vs Output Power 4.2V Rl=8 Ohms
0

0

-10

-10

-20

-20

-30

-30

100Hz

-50

1kHz
6kHz

-60

-40

THDN (dB)

THDN (dB)

-40

100Hz

-50

1kHz
6kHz

-60

-70

-70

-80

-80

-90

-90

-100
0.001

-100
0.001

0.01

0.1

1

10

0.01

WLCSP package

0

-10

-10

-20

-20

-30

-30
100Hz

-50

1kHz
6kHz

-60

-40

THDN (dB)

THDN (dB)

-40

100Hz

-50

1kHz
6kHz

-60

-70

-70

-80

-80

-90

-90

-100
0.001

-100
0.001

0.1

1

10

0.01

Output Power (W)

100

90

90

80

80

70

70

60

Efficiency (%)

Efficiency (%)

10

Efficiency vs Output Power Rl=4 Ohms

100

3V7

50

4V2
5V0

40

60

30
20

10

10

1.5

2

4V2
5V0

40

20

1

3V7

50

30

0

0

1

2

3

4

Output Power (W)Output Power (W)Feb 1, 2023

1

WLCSP package

Efficiency vs Output Power Rl=8 Ohms

0.5

0.1
Output Power (W)WLCSP package

0

10

THDN vs Output Power 3.7V Rl=4 Ohms

0

0

1

WLCSP package

THDN vs Output Power 3.7V Rl=8 Ohms

0.01

0.1
Output Power (W)Output Power (W)Page 20 of 42

Rev 1.88 FUNCTIONAL DESCRIPTIONThis chapter provides detailed descriptions of the major functions of the NAU8315 Amplifier.

8.1 Inputs
The NAU8315 provides digital inputs to acquire and process audio signals with high fidelity and flexibility.
The audio input path is from an I2S/PCM Interface, using the FSL, FSR, BCLK & DACIN pins.
The device is enabled by setting the EN pin high and disabled by setting EN to 0V. The EN, FSL, FSR,BCLK & DACIN pins all have a low input threshold voltage to allow for operation from a host with low IO
supply voltage.
The GAIN input pin is a special input pin which essentially is an ADC input. The ADC tied to this pin has
5 decision levels and can therefore select 5 modes of operation each.

The GAIN input pin can be configured as shown in the table below. The GAIN set represents the signal
voltage gain of the differential DAC outputs to the differential modulator outputs or speaker outputs. The
differential DAC full scale reference is 1.8Vpk. Note that on the 9-Ball WLCSP package the gain is set
to 12dB fixed.

Table 2GAIN Configurations for the NAU8315

Gain
Mode #GAIN (dB)
MODE-6dBFs
Output(Vpk)

Min Reference
Tolerance
VDD = 2.5V
(Vpk)

Max Reference
Tolerance
VDD = 5.25V
(Vpk)

1

9

2.535

2.515

2.535

GAIN pin tied to VSS

2

3

1.265

1.268

1.293

GAIN pin tied to VSS through 100 KOhm+/- 5% resistor

3

12

3.595

2.231
(clipping)

3.678

GAIN pin tied to VDD

4Max. 12
CLIP ALC

3.595(no clipping)

2.231(clipping)

3.678

GAIN pin tied to VDD through 100 KOhm+/- 5% resistor

5

6

1.795

1.793

1.836

GAIN pin floating

GAIN Pin Configuration

The GAIN input ADC converts the input levels set by the external pin configuration and internal voltage
dividers into a digital representation that sets the internal GAIN mode. There are a total of 5 modes
having different gains as shown above. Gain mode 4 also enables the CLIP detection ALC, which thenallows the gain to be reduced automatically as the supply voltage decreases.

Feb 1, 2023

Page 21 of 42

Rev 1.8

The FSR & FSL input pins are used to set the I2S and PCM interface modes. The table below shows
the modes supported.
Table 3
Interface
Mode #

Interface
MODE

1

Power Down or Standby

2

Audio Interface Configurations for the NAU8315
FSL Pin Configuration

FSR Pin Configurationtied to VDD or VSS

tied to VDD or VSS

Left Channel I2S

Toggling with valid BCLK/FSL ratio
and FSL is high for more than 2 BCLK
rising edges

tied to VDD or VSS

3

Right Channel I2S

tied to VDD or VSS

Toggling with valid BCLK/FSR ratio
and FSR is high for more than 2 BCLK
rising edges

4

I2S (L+R)/2

Toggling with valid BCLK/FSL ratio
and FSL is high for more than 2 BCLK
rising edges. FSL & FSR signals are
the same.

Toggling with valid BCLK/FSR ratio
and FSR is high for more than 2 BCLK
rising edges. FSL & FSR signals are
the same.

5

16 bit PCM Timeslot 0

Toggling with valid BCLK/FSL ratio
and FSL is high for less than 2 BCLK
rising edges

tied to VSS

6

16 bit PCM Timeslot 1

tied to VSS

Toggling with valid BCLK/FSR ratio
and FSR is high for less than 2 BCLK
rising edges

7

16 bit PCM Timeslot 2

Toggling with valid BCLK/FSL ratio
and FSL is high for less than 2 BCLK
rising edges

tied to VDD

8

16 bit PCM Timeslot 3

tied to VDD

Toggling with valid BCLK/FSR ratio
and FSR is high for less than 2 BCLK
rising edges

9

16 bit PCM(Timeslot0+Timeslot1)/2

Toggling with valid BCLK/FSL ratio
and FSL is high for less than 2 BCLK
rising edges. FSL & FSR signals are
the same.

Toggling with valid BCLK/FSR ratio
and FSR is high for less than 2 BCLK
rising edges. FSL & FSR signals are
the same.

I2S data is 24-bit by default. For the PCM Timeslot interface modes the host can also sent 24 bit or 32
bit data. However, only the 16 MSB bits will be used to process the audio in this mode.
Internal mask options can be used to select other timeslots or 24-bit data or 32-bit PCM data upon
special request.

Feb 1, 2023

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Rev 1.8

8.2 Outputs
The NAU8315 Mono Class-D PWM Amplifier has a gain range from 3dB to 12dB, and is powered by aseparate power supply VDD, which can go up to 5V. This amplifier is capable of delivering up to 3.2W
into a 4Ω load with a 5V supply.

8.3 Digital Interfaces
Audio data is passed to the device through a serial data interface compatible with industry standard I2S
and PCM devices, using the FSL, FSR, BCLK & DACIN pins. The NAU8315 has no serial interface forcontrol input. Operating modes are defined by the external pin configurations.

8.4 Power Supply
This NAU8315 has been designed to operate reliably under a wide range of power supply conditions
and Power-On/Power-Off sequences. However, the Electro Static Detection (ESD) protection diodes
between the supplies and the IO pins impact the application of the supplies.

Feb 1, 2023

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Rev 1.8

8.5 Power-On-and-Off Reset
The NAU8315 includes a Power-On-and-Off Reset circuit on-chip. The circuit resets the internal logic
control at VDD supply power-up and this reset function is automatically generated internally when power
supply is too low for reliable operation. Typical reset thresholds are 1.88 V for VDD during a power-on
ramp, and 1.61 V for VDD during a power-down ramp. It should be noted that these values are much
lower than the required voltage for normal operation of the chip.
The reset is held ON while the power level for VDD is below the threshold. Once the power level rises
above the threshold, the reset is released. Once the reset is released, the device will respond to control
from external inputs.
An additional internal RC filter-based circuit is added which helps the circuit to respond for fast ramp
rates (~3 µsec) and to generate the desired reset period width (~3 µsec at typical corner). This filter isalso used to eliminate supply glitches which can generate a false reset condition, typically 50 nsec.
In addition setting the enable pin ‘EN’ low will reset the internal logic.

8.6 Power Up & Down Sequence
A diagram of the typical power up sequence is shown in the figure below. At first, the power supply isramped up.

VDD

ENFS,BCLK,DACINOUTP,OUTN
status2048 DACIN zeros
recommended

OFF

MUTE

Soft
UnMUTEENABLED

Figure 6

OFF

NAU8315 Power Up & Down Sequence

Once the supply is powered up, the enable pin ‘EN’ can be set high in order to set the device instandby state. Note that the ‘EN’ pin can also ramp up the same time as the supply voltage. During thestandby state the outputs OUTN & OUTP are still off. After enabling VDD & EN ,the BCLK detection
circuit is activated. External clocks and data can be applied right away if needed. Once the FS & BCLK
are applied the clock detection module will validate the BCLK/FS ratio and set the internal clock
dividers. When a valid BCLK/FS ratio is detected and the clock dividers are set, a 4 millisecond muteperiod is enabled during which all circuits are powered up and the DAC digital volume control is in the
muted state. The mute period is followed by a soft-unmute, which gradually increases the DAC digital
volume to full scale. After this event the signal path is fully active and the outputs are fully enabled. At
the end of playback it is recommended to add 2048 zero samples to the DACIN input for a pop-lessshutdown. When either one or both of the FS & BCLK clocks is stopped the clock detection circuit will
power down the device. The detection time depends on the clock frequency used, but is approximately
50usec. Once detected, the output drivers will shut down.
Feb 1, 2023

Page 24 of 42

Rev 1.8

8.7

Clocking and Sample Rates

The internal clocks for the NAU8315 are derived from the external BCLK clock source. This mastersystem clock can set directly by the BCLK input or it can be generated from a clock multiplier using the
BCLK as a reference.

8.7.1 Clock Control and Detection
The NAU8315 includes a Clock Detection circuit that is used to enable and disable the audio paths. The
actual power up/down is gated by the clock detection circuit. The block diagram of the clock detection
circuit is shown in Figure 7.
BCLK
DETECTIONBCLKDET

1/N1

Delay

MCLKSELMultiplexer

CLOCKCONTROL

50 %DUTYCYCLE

x N2
Clock
Multiplier
1,2,4,8x

MCLK_SRC
FSL
FSR
BCLK

PWRUPEN

BCLK/FS
Detection

I2SPCM

Mode
Detection

CHANNEL

CLOCK
DETECTION

EN

Figure 7

NAU8315 Clock Detection Circuit

Clock Detection by the NAU8315 uses the BCLK FSL, FSR and EN to control the internal PWRUPEN
signal and set the clock divider ratios.

8.7.2 Automatic Power Control and Mute.
Clock detection and automatic power control in the NAU8315 is enabled by meeting two conditions,depending on the configuration. If all conditions are met, the PWRUPEN signal will be asserted to 1. If
any of the conditions are not met, the PWRUPEN signal is set to 0.
The conditions for generating the PWRUPEN signal are:Feb 1, 2023

Page 25 of 42

Rev 1.8

1) The NAU8315 has custom logic clock detection circuits that detect if BCLK is present. Upon
BCLK detection, the detector output BCLKDET goes to 1. When the BCLK disappears,
BCLKDET goes back to 0. Up to 1 µsec is required to detect BCLK and the BCLK release time
is about 50 µsec.
2) The clock detection logic also needs to detect the ratio BCLK /FS of 32, 50, 64, 100, 125, 128,
200, 250, 256, 400, 500.

The PWRUPEN signal is capable of controlling all the analog power consuming blocks.
A Mode Detection circuit also determines one of the I2S/PCM operating mode and channel (as shownin Table 3) once a valid BCLK/FS ratio is detected.
When PWRUPEN goes high an internal sequence is triggered to bring up analog functions. This includes
an analog MUTE to allow stabilization of internal analog blocks, followed by a soft unmute of the DAC.
The analog MUTE time is 4ms. The soft unmute then ramps the gain 512 MCLK_SRC periods per gain
step. For the 512 setting, the soft unmute takes 256 * 512 * Tmclk_src seconds to reach 0dB (10ms for12.288MHz MCLK_SRC). This ensures pop free startup of the amplifier. An example of this startup is
shown in figure below.

Figure 8

PWRUPEN startup sequence.

Before reaching the DAC the incoming PCM signal is processed by a digital signal path. To ensurecomplete flushing and transient free audio of this path it is recommended that 2048 zero samples aresent to the device before stopping clocks. The DAC soft unmute function is also beneficial for eliminating
any audio transients from audio path

8.7.3 Input Clock Rates
The range of the input clocks is shown in Table 4.
Table 4

Feb 1, 2023

Range of Input Clocks

Page 26 of 42

Rev 1.8

SignalMin

Max

Frame Synch (FS) (kHz)896

Bit Clock BCLK (MHz)1.411224.5768.7.4 Sample and Over Sampling Rates
Possible BCLK/FS ratios are shown in Table 5 and Table 6. Table 4 shows the relation between the
BCLK/FS ratio and the internal OSR and MCLK_SRC/FS ratio. The divider and multiplier N1 & N2 are
set accordingly by the clock detection logic. Table 5 shows the possible FS & BCLK ranges for each
BCLK/FS ratio.

Table 5

BCLK/FS
ratio
32
50
64
100
125
128
200
250
256
400
500

Feb 1, 2023

BCLK/FS ratios and Over Sampling Rates

Lower
Upper
Decision
Decision
Threshold Threshold
31
49
63
99
124
127
199
249
255
399
499

33
51
65
101
126
129
201
251
257
401
501

N1

N2

MCLK_SRC/FS

OSR

1
1
2
2
2
2
2
2
1
1
1

8
8
8
8
8
4
4
4
1
1
1

256
400
256
400
500
256
400
500
256
400
500

64
100
64
100
100
64
100
100
64
100
100

Page 27 of 42

Rev 1.8

Table 6

Ranges of Sampling Frequencies and BCLK Rates

BCLK/FSRatio

FS (kHz)BCLK (MHz)

Min

Max

Min

Max

32

44.1

96

1.4112

3.072

50

32

48

1.600

2.400

64

44.1

96

2.8224

6.144

100

32

48

3.200

4.800

125

24

48

3.000

6.000

128

24

96

3.072

12.288

200

16

48

3.200

9.600

250

12

48

3.000

12.000

256

8

96

2.048

24.576

400

8

48

3.200

19.200

500

8

48

4.000

24.000The MCLK_SRC frequency is defined as:
F_MCLK_SRC = N2 x F_BCLK / N1
For BCLK/FS ratios of 32 & 50 a low jitter BCLK source with accurate duty cycle must be used.

Feb 1, 2023

Page 28 of 42

Rev 1.8

8.8

Automatic Level Control

The digital Automatic Level Control (ALC) function supports the DAC digital audio path of the NAU8315.
It can be enabled as by setting the GAIN pin to 12dB gain with ALC. This function can be used to manage
the gain to optimize the signal level at the output of the Class-D Amplifier by automatically amplifying
input signals that are too small or automatically decreasing the amplitude signals that are too loud. The
ALC is designed such that it adjusts the output level in order to prevent clipping. This may be use-full inbattery operated applications, where the battery supply voltage decreases as the battery discharges. At
lower supply voltages the outputs will more likely clip at higher output levels. In such case, the ALC
would decrease the output level just below the clipping level and maintain high quality sound as well as
decreasing the peak power drain from the battery.
The Figure below illustrates the relationship of the ALC to other major functions of the NAU8315.

DigitalProgrammable Gain
Amplifier

VDDSPK

DAC

From
DACIN

ALC
Control

CLIP

Class-D
Modulator

NuvoClip
Detection

AND

ALCEN

Figure 9

ALC Control Loop Block Diagram

8.8.1 ALC Operation
A clip detection signal is provided by the clip detection circuit as soon as the input signal is clipping at
its peak levels. The ALC block then ramps down the gain at the pre-programmed ALC Attack Timerate. This continues until the clipping detection no longer detects a clipping signal or until the
maximum gain decrement per clipping event is reached. When the clipping is no longer occurring, the
ALC gain is held for the hold time. The ALC gain is then ramped up to the target following the preprogrammed ALC Release Time rate

8.8.2 ALC Parameter Definitions
ALC Minimum Gain (ALCMIN): This sets the minimum allowed gain during all modes of ALC
operation. This is useful to keep the ALC operating range close to the desired range for a given
application scenario.
ALC Attack Time (ALCATK): Attack time refers to how quickly a system responds to a clipping event.
Typically, attack time is much faster than decay time.

Feb 1, 2023

Page 29 of 42

Rev 1.8

ALC Decay Time (ALCDCY): Decay time refers to how quickly a system responds after the hold time.
Typically, decay time is much slower than attack time. When no more clipping events occur, thegain will increase at a rate determined by this parameter.
ALC Hold Time (ALCHLD): Hold time refers to the duration of time when no action is taken. This is
typically to avoid undesirable sounds that can happen when an ALC responds too quickly to achanging input signal. In the NAU8315, the hold time value is the duration from the last clipping
event before there is an actual gain increase during the decay time.
CLIP_GAINADJUST sets the maximum gain decrease per clipping event. During a clipping even thegain decreases by 0.250dB (1-1/64) per attack time step until the clipping event no longer occurs
or the maximum gain reduction limit set in CLIP_GAINADJUST has been reached or the ALC
Minimum Gain is reached.

Feb 1, 2023

Page 30 of 42

Rev 1.8

8.9

Device Protection

The NAU8315 includes the following types of device protection:Over Current Protection (OCP)
Under Voltage Lock Out (UVLO)
Over Temperature Protection (OTP)
Clock Termination Protection (CTP)

Over Current Protection is provided in the NAU8315. If a short circuit is detected on any of the pull-up
or pull-down devices on the output drivers for at least 14µs, the output drivers will be disabled for 100ms.
The output drivers will then be re-enabled and checked for a short circuit again. If the short circuit isstill present for another 14µs, the cycle will repeat until the short circuit has been fixed. The short circuit
threshold is set at 2.1A.
Under Voltage Lock Out (UVLO) provides Supply Under Voltage Protection in the NAU8315 If the
VDD drops under 2.1V, the output drivers are disabled, however, the NAU8315 control circuitry will still
operate. This is useful to help avoid the battery supply voltage dropping before the host processor cansafely shutdown the devices on the system. If the VDD drops below 1.61V, the internal power-onreset will activate and put the class-D driver in power down state.
Over Temperature Protection (OTP) is provided in the event of thermal overload. When the device
internal junction temperature reaches 143°C, the NAU8315 will disable the output drivers. Once thedevice cools down to a safe operating temperature (123°C) for at least 100us, the output drivers will
be re-enabled.
Clock Termination Protection (CTP) is provided in the NAU8315. If the FS and/or BCLK clock stops
running, the NAU8315 automatically shuts down the Class-D driver and therefore prevents DC voltages
to remain at the outputs.

8.10

Power-up and Power-Down Control

When the supply voltage ramps up, the internal power on reset circuit is triggered. At this time, all internal
circuits will be set to the power-down state. The device can be enabled by setting EN to VDD and startingthe clocks. Upon starting the clocks, the device will go through an internal power-up sequence in orderto minimize ‘pops’ on the speaker output. The complete power-up sequence requires about 14 msec.
The device will typically power down in about 22 µsec, when the clocks are stopped.
NOTE:

8.11

It is important to keep the input signal at zero amplitude or enable the mute condition in orderto minimize ‘pops’ when the clocks are stopped.

Bypass Capacitors

Bypass capacitors are required to remove the AC ripple on the VDD pins. The value of thesecapacitors depends on the length of the VDD trace. In most cases, 2 x 4.7 µF and 0.1 µF are sufficientto achieve good performance.

8.12

Printed Circuit Board Layout Considerations

Good Printed Circuit Board (PCB) layout and grounding techniques are essential to achieve good audio
performance. It is better to use low-resistance traces as these devices are driving low impedance loads.
The resistance of the traces has a significant effect on the output power delivered to the load. In order
to dissipate more heat, use wide traces for the power and ground lines.

Feb 1, 2023

Page 31 of 42

Rev 1.8

8.12.1 PCB Layout Notes
The Class-D Amplifier is a high power switching circuits that can cause Electro Magnetic Interference(EMI) when poorly connected. Therefore, care must be taken to design the PCB eliminate Electro
Magnetic Interference (EMI), reduce IR drops, and maximize heat dissipation.
The following notes are provided to assist product design and enhance product performance:












Use a VSS plane, preferably on both sides, to shield clocks and reduce EMI
Maximize the copper to the VSS pins and have solid connections to the plane
Planes on VDD are optional
The VDD connection needs to be a solid piece of copper
Use thick copper options on the supply layers if cost permits
Keep the speaker connections short and thick. Do not use VIAs
Use a small speaker connector like a wire terminal block (Phoenix Contact)
For better heat dissipation, use VIAs to conduct heat to the other side of the PCB
Do not use VIA’s to connect OUTP & OUTN. Use a direct top layer copper connection to the pins.
Thick copper is preferred.
Use large or multiple parallel VIAs to decoupling capacitors when connecting to a ground plane
The digital IO lines can be shielded between power planes

8.13

Filters

The NAU8315 is designed for use without any filter on the output line. However, the NAU8315 may be
used with or without various types of filters, depending on the needs of the application.

8.13.1 Class D without Filters
The NAU8315 is designed for use without any filter on the output line. That means the outputs can bedirectly connected to the speaker in the simplest configuration. This type of filter-less design is suitablefor portable applications where the speaker is very close to the amplifier. In other words, this is preferable
in applications where the length of the traces between the speaker and amplifier is short. Figure 10
illustrates this simple configuration.

SPKP

SPKN

Figure 10

NAU8315 Speaker Connections without Filter

8.13.2 Class D with Filters
In some applications, shorter trace lengths are not possible because of speaker size limitations andother layout reasons. In these applications, long traces will cause EMI issues. Several types of filter
circuits are available to reduce the EMI effects. These are Ferrite Bead Filters, LC filters, Low-Pass LCR
Filters, and High-Pass Filters.
Ferrite Bead Filters are used to reduce high-frequency emissions. The characteristic of a Ferrite Bead
Filter is such that it offers higher impedance at high frequencies. For better EMI performance, select a
Ferrite Bead Filter which offers the highest impedance at high frequencies, so that it will attenuate thesignals at higher frequencies. The typical circuit diagram using a Ferrite Bead Filter for each output tothe speaker is shown Figure 11.

Feb 1, 2023

Page 32 of 42

Rev 1.8

NOTE:

Usually, the ferrite beads have low impedance in the audio range, so they will act as passthrough filters in the audio frequency range.
Ferrite Bead

VOUTP
1nF

Ferrite Bead

VOUTN
1 nF

Figure 11

NAU8315 Speaker Connections with Ferrite Bead Filters

LC Filters are used to suppress low-frequency emissions. The diagram in Figure 12 shows the
NAU8315 outputs connected to the speaker with an LC Filter circuit. RL is the resistance of the speaker
coil.

VOUTP

L
RL

C

L

VOUTN

Figure 12

C

NAU8315 Speaker Connections with LC Filters

Low-Pass LCR Filters may also be useful in some applications where long traces or wires to the
speakers are used. Figure 13 shows the speaker connections using standard Low-Pass LCR Filters.
L

Input

OutputC

Figure 13

R

NAU8315 Speaker Connections with Low-Pass Filters

The following equations apply for critically damped (ζ = 0.707) standard Low-Pass LCR Filters:

Feb 1, 2023

Page 33 of 42

Rev 1.82𝜋𝜋𝜋𝜋𝑐𝑐 =
NOTE:

1

√(𝐿𝐿𝐿𝐿)𝑓𝑓𝑐𝑐 is the cut-off frequency𝜁𝜁 = 0.707 =

1
𝐿𝐿
∗√
2𝑅𝑅
𝐶𝐶

The L and C values for differential configuration can be calculated by duplicating the singleended configuration values and substituting RL = 2R.

Feb 1, 2023

Page 34 of 42

Rev 1.8

9 Control
The NAU8315 Audio Interface is set to default I2S and PCM time slot modes as described in the
FSL & FSR operating mode table. Other modes may be feasible through metal mask option changes
upon special request.

9.1 Digital Audio Interface
The NAU8315 is an I2S or PCM Timeslot slave device. In I2S Slave Mode, an external controller
supplies BCLK (bit clock) and the frame synchronization or FS signal. Data is latched on the rising edgeof BCLK.
The NAU8315 reads 24 bit I2S data on DACIN. For the BCLK/FS rate of 32, only the 16 MSB bits areread.

9.1.1 I2S Audio Data
In I2S Mode, the MSB is clocked on the second BCLK rising edge after the FS transitions. When FS is
LOW, Left Channel data is received; when FS is HIGH, Right Channel data is received. This can beseen in Figure 14.

LEFT CHANNELFSRIGHT CHANNEL

BCLK

DATA

N-1
MSB

1

0

N-1

LSB

MSB

Figure 14

1

0
LSB

I2S Audio Data

9.1.2 PCM Time Slot Audio Data
PCM Time Slot Mode is used to delay the time at which the DAC data is clocked into the device. Thiscan be useful when multiple NAU8315 chips or other devices share the same audio bus. This will allow
the audio from the chips to be delayed around each other without interference.
Normally, the DAC data is clocked immediately after the Frame Sync (FS); however, in PCM Time Slot
Mode, the audio data can be delayed. These delays can be seen before the MSB in Figure 15.

Feb 1, 2023

Page 35 of 42

Rev 1.8

CHANNEL 0FS

CHANNEL 2 … 7

CHANNEL 1

BCLK

N-1 N-2DATA

0N-1 N-2

LSB

MSB

1

MSB

Figure 15

1

0
LSB

N-1 N-2

1

0
LSB

MSB

PCM Time Slot Audio Data

9.2 Digital Audio Interface Timing Diagrams
9.2.1 I2S Audio Interface
TBCK

T FALLTRISE

BCLK( Slave )TFSH

T BCKH

T FSH
T FSS

TBCKL

T FSS

FS
( Slave )
T DIS
T DIH

DACIN

MSB

Figure 16

Feb 1, 2023

I2S Audio Interface

Page 36 of 42

Rev 1.8

9.2.2 PCM Audio

TBCK

TRISE

T FALL

BCLK( Slave )
TFSH

TBCKH

T FSH
T FSS

T FSS

TBCKL

FS
( Slave )
T DIS
T DIH

DACIN

MSB

Figure 17

Table 7

PCM Audio Interface

Digital Audio Interface Timing Parameter

BCLK=3.072MHz, Fs=48KHz, 64Bit, VDD 2.5 -5.25V, Room Temperature
Description

SymbolMinTyp

BCLK Cycle Time

TBCK

35

---

---

ns

BCLK High Pulse Width

TBCKH

20

---

---

ns

BCLK Low Pulse Width

TBCKL

50

---

---

ns

Fs to CLK Rising Edge Setup Time

TFSS

20

---

---

ns

BCLK Rising Edge to Fs Hold Time

TFSH

40

---

---

ns

Rise Time for All Audio Interface Signals

TRISE

---

---

0.135TBCK

ns

Fall Time for All Audio Interface Signals

TFALL

---

---

0.135TBCKns

BCLK Rising Edge to DACIN Hold Time

TDIH

15

---

---

ns

Feb 1, 2023

Page 37 of 42

Max

Unit

Rev 1.8

10 Package Specification
The NAU8315 Mono Class-D Amplifier is available in a small, 20 pin QFN package, using 0.5 mm
pitch, as shown below.
TOP VI EW

15

BOTTOM VI EW

16

15

11

11

10

10

6

6

16

20

20

1

5

5

1

NAU8315 20 pin QFN Package Specification

Feb 1, 2023

Page 38 of 42

Rev 1.8

The NAU8315 Mono Class-D Amplifier is also available in a small, 12 Ball WLCSP package, using 0.4
mm pitch, as shown below.

NAU8315 12 Ball WLCSP Package Specification

Feb 1, 2023

Page 39 of 42

Rev 1.8

The NAU8315 Mono Class-D Amplifier is also available in a small, 9 Ball WLCSP package, using 0.4
mm pitch, as shown below.

NAU8315 9 Ball WLCSP Package Specification

Feb 1, 2023

Page 40 of 42

Rev 1.8

11 ORDERING INFORMATIONPart Number

Dimension

Package

Package Material

NAU8315YG

4mm x 4mm

QFN-20Green

NAU8315A31VG

1.95mm x 1.18mm

9 Ball WLCSPGreenNAU8315B31VG

1.95mm x 1.18mm

12 Ball WLCSPGreenNAU8315 _ _Package Material:
G=

Green Package (Halogen-free, RoHS-compliant)& TSCA-compliant

Package Type:Y

Feb 1, 2023=

QFN-20

A31V =WLCSP-9

B31V =WLCSP-12

Page 41 of 42

Rev 1.8

12 REVISION HISTORYREVISION

DATE

1.0

Sep 23, 2019

Initial Release

1.1

Sep 23, 2019

Updated WLCSP 9 pinout and package drawing

1.2

Oct 25, 2019

Updated VIL & VIH conditions. Add WLCSP & QFN20 charts and
WLCSP parameters

1.3

Jan 29, 200

Move electrical characteristic section

1.4

Feb 18,2020Part number change
Added more information for I2S

1.5

Mar 30, 2020

Added Section 9.2

1.6

Jun 23, 2021

WLCSP 9 Ball C2 pin description
Table 3, changed FSL to FSR

1.7

May 19, 2022

Update Figure 16, Figure 17, Table 7

1.8

Feb 1, 2023

Update Halogen-free, RoHS-compliant and TSCA-compliant
description

Feb 1, 2023

DESCRIPTION

Page 42 of 42

Rev 1.8

IMPORTANT NOTICE
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all typesof safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims
to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages andliabilities thus incurred by Nuvoton.

Feb 1, 2023

Page 43 of 42

Rev 1.8