Parformance Evaluation among Four types ofFive-level Topologies using Pareto Front Curves
Yugo Kashihara Jun-ichi ItohJun-ichi Itoh

Energy and Environmental Science
Nagaoka University of Technology
Nagaoka, Japankasihara@stn.nagaokaut.ac.jp

Electrical Engineering
Nagaoka University of Technology
Nagaoka, Japan
itoh@stn.nagaokaut.ac.jp

Abstract— This paper discusses and evaluates the performanceof four types of five-level inverter topologies by referring toPareto front curves. The four types of multilevel topologies are,Active neutral-point-clamp converter (ANPC), two various
types of Stacked multicell converter (SMC) and Switch gear
cell converter (SGC). From the comparison studies, the fivelevel ANPC inverter can achieve the highest efficiency andhighest power density among other converters even theswitching frequency is changed from 5 kHz to 500 kHz.

I.

INTRODUCTION

Recently, the multilevel converters are actively studied
and discussed in the medium voltage application such asindustrial variable speed drive and also grid transmission line[1]-[3]. The multilevel converters feature advantages asfollows: reduce the voltage stress of a switching device to1/(n-1) of the DC input voltage and also reduce the harmoniccomponent of the output voltage. Lately, the implementationof multilevel converters in the field of low voltage
applications, such as the uninterrupted power supply (UPS)
and photo voltaic Cell (PV) power converter [4], also has
been receiving high attentions, in order to achieve highefficiency.
However, the multilevel converters is a complex circuit
topology because the structure of the circuit in proportional
to the number of levels. In addition, there are many types ofcircuit topologies that can obtain the same level. It is
important to select the circuit topology to meet the
specification of the applications. One of the selection criteria
for the circuit topologies are the controllability of capacitor
voltage because certain types of multilevel converters (suchas the diode clamp converter) need capacitor voltage balance
circuit, which is further increasing the costs and complexity[5]. In constant, some multilevel topologies in spite of morethan five-level does not require the capacitor voltage balance
circuit [1]-[3]. Besides, the loss and volumes analysis arevery important to choose the best circuit topology in subjects
to applications. Loss analysis by using simulator is a simple
method among the multilevel converter topologies under asame device specification. However the loss estimation bysimulation is not capable to achieve the design optimization,
since high numbers of simulation results are required under
different conditions. Therefore, the loss analysis andvolumes estimation by mathematical expressions are
requiredThis paper discusses and demonstrates the loss analysis
and volume estimation by mathematical expressions for fourtypes of five-level inverter topologies [4] [6] which are notrequiring the capacitor voltage valance circuit. The
multilevel converters are, the active neutral-point-clamp
converter (ANPC), two types of stacked multi cell converter(SMC) and the switch gear cell converter (SGC) [1]-[3].
These inverter topologies are then evaluated using Pareto
front curves which reveal the relationships between the
power density and efficiency in subjecting to the switchingfrequency.
First of all, the four types of multilevel converters areillustrated. Then the design procedures for the multilevel
converters are discussed, including the loss analysis, volume
design for capacitor, reactor and heatsink. Lastly, thetheoretical, simulation and experimental results are provided
to demonstrate the validity of the design procedure. From thecomparison results, it is shown that the five-level ANPC
inverter can achieve the highest efficiency and highest power
density.
II.

CIRCUIT TOPOLOGIES AND DESIGN FLOWCHART

A. Circuit topologies
Figure1 shows the four types of multilevel inverter
topologies, as previously discussed. The active neutral-pointclamp (ANPC) converter is a combined of flying capacitor
topology and diode clamp topology [1]. The stacked
multicell A (SMC-A) type is a combined of three-level diodeclamp topology and three-level T-type neutral point clamp(NPC) topology[2]. The stacked multicell B (SMC-B) type is
a combined of two three-level T-type NPC topology [2]. The
switch gear cell (SGC) type is a combined of H bridge circuitand 3-level T-type NPC topology [3]. The performance of

the ANPC inverter is compared with the performances of the
SMC-A inverter, the SMC-B inverter, and the SGC inverter.
B. Design flowchart
Figure 2 shows the design procedure of a pareto front
curve for an inverter. The input variables for the design
procedure, which are the converter specifications and thedevice parameters, are decided directly from thespecification. The parameters of the four elements, which are
the semiconductor, the capacitor, the inductor, and theheatsink, are then calculated using the input parameters. The
efficiency and power density are the output parameters. Notethat each design procedure for the semiconductor, capacitor,
and inductor can be calculated individually without
sequence, because the same input parameters are applied foreach design procedure.
The parameter such as the power loss is calculated
mathematically. Loss analysis using a circuit simulator is abasic method for the multilevel converter topologies under
the same device specifications. However, loss estimation bysimulator is not a useful tool for design optimization because
hundreds of simulations are required under different
conditions in order to determine the optimization point. Notethat the semiconductor losses do not depend on the capacitor
and inductor parameters because the voltage and current
ripples are considered equal to zero. In addition, the cases ofcapacitor and inductor design follows to the same procedure.

*Voltage rating of switching device S1-S4 SA SB is a quarter of input
voltage. Voltage rating of switching device S5-S8 is a half of input voltage.
Voltage rating of switching device S9-S10 is a two-third of input voltage.

The design of the heatsink calculates the thermal
resistance and volume. The total loss of the semiconductor
can be determined from the design of the semiconductor.
The volume of the heatsink is calculated using the Cooling
System Performance Index (CSPI), which is defined as theinverse of the product of thermal resistance and the volume.
The CSPI is a very convenient tool for selecting the correctheatsink because the same CSPI value indicates the same
volume in the heatsink. Generally, the CSPI of air coolingheatsink with fans is between approximately 3 and 10.
In the design of the capacitor, the capacitance, thecapacitor current ripple, the capacitor loss, and the capacitor
volume are calculated based on input parameters. The
capacitance is decided using the voltage ripple according to
the specifications. The capacitor current ripple is identified
mathematically. In the design of the capacitor, the power
density and volume of the capacitor are important factors inorder to achieve a higher power density in the converter. The
volume of the capacitor is calculated by the converter
specifications, and the volume coefficient is obtained basedon surveys studies of commercial capacitors.
The design of the inductor calculates the inductance, theinductor loss and the inductor volume based on input
parameters. The inductance is decided by the current ripple
based on the specifications. In the design of inductor, thecore selection is an important factor. The core is selected by
the product of the window area and the cross-sectional area[6]. The core volume is proportional to the three-quarter(3/4) power of the area product value.

III.

Fig.2. Inverter design procedure.
APPLICATION TO MULTILEVEL INVERTERS

This section explains the power loss expression for thefour multilevel converter topologies. Then, the total loss PLoss
is given by
PLoss = PSw + PCap + PL,

(1)

where PSw is the semiconductor loss, PCap is the capacitor
loss, and PL is the inductor loss. In addition, thesemiconductor loss is given by
PSw = Pcon + Pswitching,(2)

where Pcon is the conduction loss of the semiconductor, andPswitching is the switching loss of the semiconductor. On theother hand, the total volume Vol is given by
Vol = Vol Sw + Vol Cap + Vol L + Vol H,(3)

where VolSw is the semiconductor volume, VolCap is thecapacitor volume, VolL is the inductor volume, and VolH is
the heatsink volume. In addition, the power density ρ isgiven by
ρ=

Pout
Vol ,

(4)

where Pout is the output power [5].
A. Power loss of the semiconductor
These multilevel converter topologies are assumed tooperate under ideal conditions. The power losses for the four
multilevel converter topologies are calculated under ideal
conditions, i.e., no current ripple and no voltage ripple in thecapacitors. The voltage fluctuation in the flying capacitor
occurs only during the switching cycle. In addition, theapplied voltage of the switches fluctuates during theswitching cycle. However, there are two switches that apply
low voltage and high voltage for the same switching pattern.
Thus, the loss by voltage ripple is counterbalanced.
1) ANPC inverter topology (Figure 1 (a))
The conduction loss is separated into the switch-side loss
and the FWD-side loss [3]. In addition, if the switching
device of the two-level converter is a MOSFET, both thepositive and negative currents flow into the switch side due
to low on-resistance. We assume that positive current flows
into the switch side and negative current flows into the FWD
side. The conduction loss P5A_con_Cell1_sw on the switch side
can be given by
P5 A _ con _ Cell1 _ sw =1 ⎛ ⎡11
4⎤
2⎜ sin 2φ − φ + a cosφ ⎥ ron I m .
2π ⎜⎝ ⎢⎣ 42
3⎦

P5 A _ con _ Cell1 _ FWD =where v0 is the on-state voltage when I is approximately 0 A,
Im is the peak phase current, ron is the on-resistance, a is themodulation index, and cosφ is the fundamental power factorof the output side. The on-state voltage occurs in theswitching device from the on-resistance and the p-n junction,
which is expressed in equation (5). On the other hand, if theswitching device for the multilevel converter is a MOSFET,
v0 = 0 in equation (5). Note that these equations for themultilevel converter are described in detail in a previous
study [3].
On the other hand, the conduction loss P5A_con_Cell1_FWD on
the switch side is given by

(6)

⎞
⎡
⎛ 1 ⎞⎤+ ⎢1 + π cos φ ⎜1 − a ⎟⎥ v0 I m ⎟⎟⎝ 2 ⎠⎦⎣⎠

The conduction loss in Cell 2 is obtained by the same
formula that is used to calculate the conduction loss in Cell
1. However, the current that flows into the Cell 2 switches isdifferent from that flowing into the Cell 1 switches because
S5 and S7 are turned on when the output voltage command ispositive and S6 and S8 are turned on when the output voltage
command is negative.
Therefore, the conduction loss P5A_con_Cell2_swA for theswitch side of S5 and S8 is given by
P5 A _ con _ Cell 2 _ swA =a ⎡⎛ 12
1⎞
2⎜ cos 2φ + cos φ + ⎟ron I m
2π ⎢⎣⎝ 632⎠
1⎤+ (− sin φ + (π + φ ) cos φ ) v 0 I m ⎥
2
⎦

.

(7)

The conduction loss P5A_con_Cell2_FWDA for the FWD side of
S5 and S6 is given by
P5 A _ con _ Cell 2 _ FWDA =4⎞⎤
1 ⎡ ⎛⎜⎛φ ⎞2⎢ a⎜ 8 sin ⎜ ⎟ ron I m + 3(− sin φ + φ cos φ )v0 I m ⎟⎟ ⎥12π ⎢⎣ ⎝
⎝2⎠
⎠ ⎥⎦

.

(8)

Likewise, the conduction loss P5A_con_Cell2_swB for theswitch side of S6 and S7 is given by
P5 A _ con _ Cell 2 _ swB =1 ⎡ ⎡⎛ π φ 1
2
1 ⎞⎤
⎞ ⎛1
2
⎢ ⎜ + − sin 2φ ⎟ + a⎜ cos 2φ + cos φ + ⎟ ⎥ ron I m
2 ⎠⎦2π ⎣ ⎢⎣⎝ 2 2 4
3
⎠ ⎝6

⎤
⎡
1
1
⎛π
⎞⎤
+ ⎢(cos φ + 1) − a⎜ cos φ − sin φ + φ cos φ ⎟⎥ v 0 I m ⎥
2
2
⎝2
⎠⎦
⎣
⎦

, (9)

and the conduction loss P5A_con_Cell2_FWDB for the FWD side of
S6 and S7 is given by

(5)

⎞
⎡
⎛ 1 ⎞⎤+ ⎢1 − π cosφ ⎜1 + a ⎟⎥v0 I m ⎟⎟⎝ 2 ⎠⎦⎣⎠

1 ⎛⎡ 1π⎤
142⎜ − sin 2φ + φ − a cos φ + ⎥ ron I m .
2π ⎜⎝ ⎢⎣ 42
3
2⎦

P5 A _ con _ Cell 2 _ FWDB =1 ⎡⎡⎛ φ 1
2
1 ⎞⎤
⎞ ⎛1
2
⎢ ⎜ − sin 2φ ⎟ + a⎜ cos 2φ − cos φ + ⎟⎥ ron I m
2π ⎣⎢⎣⎝ 2 4
3
2 ⎠⎦
⎠ ⎝6

1
⎤
⎡
⎤
+ ⎢− 1 + cos φ − a (sin φ − φ cos φ )⎥v 0 I m ⎥2⎣⎦⎦. (10)

Since the switching loss of the switches in Cell 1 is
proportional to the applied voltage and current. Therefore,
the switching loss of Cell 1 depends on the current flows
through the switches and the numbers of switching. The Cell
1 switching loss P5A_switching_Cell1 is given by
P5 A _ switching_ Cell1 =1

Edc I m(n − 1)π Edcd I md

(e + e ) f
on

off

c

,

(11)

where Edc is the input voltage, eon is the turn-on energy per
switching from the datasheet, eoff is the turn-off energy per
switching from the datasheet, Edcd is the voltage under themeasurement condition of switching loss from the datasheet,
Imd is the current under the measurement condition ofswitching loss from the datasheet, fc is the carrier frequency,
and n is output voltage level. The recovery loss P5A_rec_Cell1 isgiven byEdc I m1
P5 A _ rec _ Cell1 =e f(n − 1)π Edcd I md rr c ,(12)2) SMC-A inverter topology (Figure 1(b))
This section explains the power loss expression of the
SMC-A inverter (Figure 1(b)). The current flows into theswitches are different because of the three different voltage
conditions. Therefore, the conduction loss P5SA_con_Cell1__swA
for the switch S1 and S4 side is given bya ⎧⎡ 12
1⎤
2,⎨ cos (2φ ) + cos (φ ) + ⎥ ron I m
2π ⎩ ⎢⎣ 6
3
2⎦

(13)

The conduction loss P5SA_con_Cell1_FWDA for the FWD S1 and S4side are given by⎤ ron 2 .
a ⎧⎡
2⎛φ ⎞
2
Im
⎨ 4 sin ⎜ ⎟ − sin φ ⎥2π ⎩ ⎢⎣
⎝2⎠
⎦ 3

(14)

The conduction loss P5SA_con_Cell1__swB for the switch side S2and S3 is given by1 ⎧⎪⎡ π 1 ⎛ 2
2 ,2 ⎛ φ ⎞ ⎞⎤⎨⎢ + a⎜ sin φ − 4 sin ⎜ ⎟ ⎟⎟⎥ ron I m
2π ⎪⎩⎣ 2 3 ⎜⎝⎝ 2 ⎠ ⎠⎦

(15)

⎫
1
⎤
⎡
+ ⎢2 + a(sin φ − cos φ )⎥ v0 I m ⎬
2
⎣
⎦
⎭

a ⎧⎡
2 .
2⎛φ ⎞
2 ⎤1
⎨ 4 sin ⎜ ⎟ − sin φ ⎥ ron I m
2π ⎩⎢⎣
⎝2⎠
⎦3

(16)

v I ⎫
− [sin φ − φ cos φ ] 0 m ⎬2 ⎭The conduction loss P5SA_con_D for diodes D1 and D2 is given
by
2
⎧⎡π
⎡1
4
2
1 ⎤⎫ r I⎛φ ⎞ 1P5 SA _ con _ D = ⎨ ⎢ + a ⎢ sin 2 φ − sin 2 ⎜ ⎟ − cos 2φ − cos φ − ⎥ ⎬ on m .(17)332 ⎦ ⎭ 2π
⎝2⎠ 6
⎣3
⎩⎣ 2

⎧
⎡
π ⎞⎤ ⎫ v I⎛+ ⎨2 + a ⎢sin φ − cos φ ⎜ φ + ⎟ ⎥ ⎬ 0 m
2 ⎠ ⎦ ⎭ 2π⎝⎣⎩

The switching loss P5SA_switching_Cell1 in the Cell 1 is given by

on

off

c

2 .

(18)

fc

e

(n −1)π Edcd I md rr 2 .

(19)

The switching operations of S5 and S6 in the Cell 2 are
the same as those of S1 and S4 in the Cell 1. Thus, theconduction loss P5SA_con_Cell2__swA for the switches S5 and S6side and the conduction loss P5SA_con_Cell2__FWDA for the FWD
S5 and S6 side are given by equations (13) and (14),respectively. On the other hand, the switching operations ofSA and SB in the Cell 2 are the same as those of D1 and D2 in
the Cell 1. Thus, the conduction loss P5SA_con_Cell2__swB for theswitches SA and SB side is same to the conduction loss
P5SA_con_Cell2__FWDB for the FWD S5 and S6 side. Those
conduction losses are given by⎧⎪⎡⎛π ⎞ ⎞⎤ ⎫⎪ v I⎛+ ⎨2 + a ⎢⎜⎜ sin φ − cos φ ⎜ φ + ⎟ ⎟⎟⎥ ⎬ 0 m
2 ⎠ ⎠⎦ ⎪⎭ 2π⎪⎩⎝⎣⎝

The switching losses P5SA_switching_Cell2_swA for the switch S5and S6 are given by
Edc I m2(n − 1)π Edcd I md

(e + e ) f
on

off

c

2 ,

(21)

The recovery losses P5SA_rec_Cell2_swA for the S5 and S6 aregiven by
P5SA_ rec _ Cell2 _ swA =2

Edc I mefc(n − 1)π Edcd I md rr 2 .

(22)

On the other hand, the switching losses
P5SA_switching_Cell2_swB for the switch SA and SB are given by

The conduction loss P5SA_con_Cell1_FWDB for the FWD S2 and S3side is given by
P5 SA _ con _ Cell 2 _ FWDB =(e + e ) f

Edc I m1

P5SA _ rec _ Cell1 =P5SA _ switching_ Cell 2 _ swA =1⎫− [sin φ − φ cos φ ] v 0 I m ⎬2⎭

P5 SA _ con _ Cell1 _ swB =Edc I m

2
⎧⎪⎡ π
⎡⎛ 1
4
2
1 ⎞ ⎤ ⎫⎪ r I⎛φ ⎞ 1P5 SA _ con _ Cell 2 _ swB = ⎨⎢ + a ⎢⎜⎜ sin 2 φ − sin 2 ⎜ ⎟ − cos 2φ − cos φ − ⎟⎟ ⎥ ⎬ on m .(20)
3
3
2
6
3
2
2
π
⎪⎩⎣ 2
⎪
⎝ ⎠
⎠⎦ ⎭
⎣⎝

⎫
φ
1
⎤
⎡π
+ ⎢ cos φ − sin φ + cos φ ⎥ v 0 I m ⎬
2
2
⎦
⎣2
⎭

P5 SA _ con _ Cell 1 _ FWDA =1(n −1)π Edcd I md

The recovery losses P5SA_rec_Cell1 for switches and diodes in
the Cell 1 are given by

where err is the recovery energy per switching from thedatasheet. The switching loss in Cell 2 depends on the output
frequency (50 Hz). As a result, the switching loss in Cell 2 islower than that in Cell 1, which is approximately zero, andcan therefore be disregarded.

P5 SA _ con _ Cell 1 _ swA =P5SA_ switching_ Cell1 =P5SA _ switching_ Cell 2 _ swB =2

Edc I m(n − 1)π Edcd I md

(e + e ) f
on

off

c

.

(23)

The recovery losses P5SA_rec_Cell2_swB for the SA and SB aregiven by
P5SA _ rec _ Cell2 _ swB =2

Edc I me f(n −1)π Edcd I md rr c .

(24)3) SMC-B inverter topology (Figure 1(c))
This section explains the power loss expression of the
SMC-B inverter (Figure 1(c)). The SMC-B inverter is acombined of two three-level T-type NPC topology. Thus, theswitching operation of the Cell 1 is same to the switching
operation of the Cell 2. In addition, the switching operationof the Cell 1 and Cell 2 in the SMC-B inverter are same tothe switching operation of the Cell 1in the SMC-A. Thus, theconduction loss P5SB_con_Cell1__swA for the switches S1 and S2side and the conduction loss P5SB_con_Cell2__swA for the switches
S5 and S6 side are given by equation (13). The conduction
loss P5SB_con_Cell1__FWDA for the FWDs S1 and S2 side and the
conduction loss P5SB_con_Cell2__FWDA for the switches S5 and S6side are given by equation (14). On the other hand, theconduction loss P5SB_con_Cell1__swB for the switches S3 and S4side, the conduction loss P5SB_con_Cell2__swB for the switches SA
and SB side, the conduction loss P5SB_con_Cell1__FWDB for the
FWDs S3 and S4 side, and the conduction loss
P5SB_con_Cell2__FWDB for the FWDs SA and SB side are given byequation (20).
In addition, the switching losses P5SB_switching_Cell1_swA forthe switches S1 and S2 and the switching losses
P5SB_switching_Cell2_swA for the switchse S5 and S6 are given byequations (21). The switching losses P5SB_switching_Cell1_swB for
the switches S3 and S4 and the switching losses
P5SB_switching_Cell2_swB for the switches SA and SB are given byequations (23).
On the other hand, the recovery losses P5SB_rec_Cell1_swA forthe switches S1 and S2 and the switching losses
P5SB_rec_Cell2_swA for the switches S5 and S6 are given byequations (22). The recovery losses P5SB_rec_Cell1_swB for theswitches S3 and S4 and the recovery losses P5SB_rec_Cell2_swB
for the switches SA and SB are given by equations (24)On the other hand, the conduction losses
P5SG_con_Cell1_FWDB on the switch S1 and S2 side are given by
P5 SG _ con _ Cell 1 _ FWDB =1 ⎧ ⎡⎛ 1
φ ⎞ ⎛1 2
4
2 . (28)
2 φ ⎞⎤⎟ ron I m
⎨ ⎜ sin 2φ − ⎟ + a ⎜ sin φ − sin
2π ⎩ ⎢⎣⎝ 42⎠3
2 ⎠ ⎥⎦
⎝3
⎫
⎡
1
⎛1
⎞⎤
+ ⎢(1 − cos φ ) + a ⎜ sin φ − φ cos φ ⎟ ⎥ v 0 I m ⎬
2
⎝2
⎠⎦
⎣
⎭

The switching loss P5SG_switching_Cell1 for the switch S1 and S2
are given by
P5SG _ switching _ Cell1 =Edc I m1(n − 1)π Edcd I md

(e + e ) f
on

off

c

.

(29)

The recovery losses P5SG_rec_Cell1 for the switches S1 and S2
are given by
P5SG _ rec _ Cell1 =1

E dc I me f(n − 1)π Edcd I md rr c .

(30)

The switching losses of the switches S3 and S4 depend on
the output frequency (50 Hz). As a result, the switchinglosses of switches S3 and S4 is lower than that the switchinglosses of switches S1 and S2 in Cell 1, which areapproximately zero, and therefore can be disregarded.

The switching operation of the Cell 2 in the SGC inverter
is same to the switching operation of the Cell 1 and Cell 2 in
4) SGC inverter topology (Figure 1(d))
the SMC-B inverter. Thus, the conduction loss
This section explains the power loss expression of the
P5SG_con_Cell2__swA for the switches S9 and S10 side are given by
SGC inverter (Figure 1(d)). The conduction losses
equation (13). The conduction loss P5SG_con_Cell2__FWDA for the
P5SG_con_Cell1_swA on the switch S1 and S2 side are given by
FWD S9 and S10 side are given by equation (14). On theother hand, the conduction loss P5SG_con_Cell2__swB for theswitch SA and SB side and the conduction loss
1 ⎧ ⎡⎛ 1φ⎞
P5 SG _ con _ Cell1 _ swA =.
(25)⎨ ⎜ sin 2φ − ⎟2π ⎩ ⎢⎣⎝ 4
2⎠
P5SG_con_Cell2__FWDB for the FWD SA and SB side are given byequation (20).
21 1 2
4 2 φ ⎞⎤
⎛1
2
+ a⎜ cos 2φ + cos φ + + sin φ − sin ⎟⎥ ron I m
3
2 ⎠⎦
3
2 3
⎝6

⎫
π
⎡
⎤
+ ⎢(1 − cos φ ) + a cos φ ⎥ v 0 I m ⎬2⎣⎦⎭

The conduction losses P5SG_con_Cell1_FWDA on the switch S1 andS2 side are given by
P5 SG _ con _ Cell1 _ FWDA =1 ⎧⎡⎛ π φ 1⎞⎨ ⎜ + − sin 2φ ⎟2π ⎩⎢⎣⎝ 2 2 4⎠.

On the other hand, the recovery losses P5SG_rec_Cell2_swA forthe switches S9 and S10 are given by equations (22). The
recovery losses P5SG_rec_Cell2_swB for the switches SA and SB(26) are given by equations
(24)

2
1 1
4
φ ⎞⎤
⎛ 1
2
+ a⎜ − cos 2φ − cos φ − − sin 2 φ + sin 2 ⎟ ⎥ ron I m
3
2 3
3
2 ⎠⎦
⎝ 6
⎫
π
⎡
⎤
+ ⎢(1 + cos φ ) − a cos φ ⎥ v 0 I m ⎬2⎣⎦⎭

The conduction losses P5SG_con_Cell1_swB on the switch S3 andS4 side are given by
P5 SG _ con _ Cell1 _ swB =1 ⎧⎡⎛ π φ 1
2
1 ⎞⎤
⎞
⎛1
2
⎨ ⎜ + − sin 2φ ⎟ − a⎜ cos 2φ + cos φ + ⎟⎥ ron I m
2π ⎩⎢⎣⎝ 2 2 4
3
2 ⎠⎦
⎠
⎝6

⎫
1
⎡
⎛ 1
⎞⎤
+ ⎢(cos φ + 1) − a⎜ − sin φ + (π + φ ) cos φ ⎟⎥ v 0 I m ⎬
2
⎝ 2
⎠⎦
⎣
⎭

In addition, the switching losses P5SG_switching_Cell2_swA forthe switches S9 and S10 are given by equations (21). The
switching losses P5SG_switching_Cell2_swB for the switches SA and
SB are given by equations (23).

5) Experimental cerification
Table 1 and Table 2 show the experimental conditions
and the device parameters. This section discusses the validityof mathematically calculated losses based on theexperimental prototype.

Figure 3 shows the efficiency comparison between theexperimental results and calculation results of the four five. (27) level inverters from 5 kHz to 80 kHz at a 3.3 kW load. Notethat there results are contained within capacitor loss and wire
resistance loss. The wire resistance loss is calculated fromwire resistance value 15 mΩ. The four calculated efficiencies
from 5 kHz to 80 kHz are in good agreement with theexperimental results. In addition, the error ratio is under
0.1%. The validity of the loss calculation method for the four
five-level inverters is confirmed by the experimental result.
B. Heatsink design
The performance of the heatsink is discussed based on
the Cooling System Performance Index (CSPI) [8], which isan expressed value of the thermal resistance at per unit
volume. The cooling performance per unit volume increaseas the CSPI increases. The CSPI is given by
CSPI =1
Rth(s−a )VolH,

Table 1 Experimental condition.
Rated power
Input voltage
Modulation index
ANPC
SMC-A
Switchingdevice

SMC-B

SGC

(31)

Flying capacitor

where Rth(s-a) is the thermal resistance heatsink to ambient(K/W), and VolH is the volume of the heatsink. In addition,
Rth(s-a) is given by
Rth ( s −a ) =T j − TaPSw

− Rth ( j − s ),DC smoothing
capacitor

3300 W
Output frequency
50 Hz
350 V
Output voltage
115 V
0.933
Output current
29 A
Cell1 MOSFET:IRFP4668pBF(IR)
Cell2 MOSFET:IXFB170N30P(IXYS)
Cell1 MOSFET:IRFP4668pBF(IR)MOSFET(S5,S6):IXFB170N30P(IXYS)Cell2
MOSFET(SA,SB):IRFP4668pBF(IR)MOSFET(S1,S2):IXFB170N30P(IXYS)Cell1
MOSFET(S3,S4):IRFP4668pBF(IR)MOSFET(S5,S6):IXFB170N30P(IXYS)Cell2
MOSFET(SA,SB):IRFP4668pBF(IR)Cell1 MOSFET:IRFP4668pBF(IR)MOSFET(S9,S10):IXFB132N50P3(IXYS)Cell2
MOSFET(SA,SB):IRFP4668pBF(IR)LGU2W101MELZ (Panasonic)
100 F 450 V
FXA2G472YE (Hitachi)
4700 F 400 V

Table 2 Device parameters.

(32)

where Rth(j-s) is the thermal resistance junction to heatsink(K/W), Tj is the junction temperature of the semiconductor
device (K), and Ta is the ambient temperature (K).
C. Capacitor design
1) CapacitanceThe capacitances of the four multilevel inverter
topologies are calculated under an ideal condition, i.e., nooutput current ripple. The capacitance of the flying capacitor
in the ANPC inverter is calculated based on the capacitor
current, the ripple voltage, and the integration time of thecharge period or discharge period. The capacitance of theflying capacitor, CFC, is given by
C FC =I mT E dc
8ΔVFC Vm,

(33)

where ΔVFC is the ripple voltage of the flying capacitor, EDC
is the DC link voltage, Vm is the maximum value of theoutput voltage, and T is the reciprocal of the carrier
frequency. In addition, the capacitances of the flying
capacitor for C1 and C2 in the SMC-A inverter, C1 and C2 in
the SMC-B inverter, and C1 in the SGC inverter are also
given by equation (33)
The capacitance CDCSC of DC smoothing capacitors C2
and C3 in the ANPC inverter is given by
C DCSC =Vmπ⎞⎛Im⎜ 3 − ⎟2ωΔVcn Edc ⎝
3 ⎠,

(34)

where ΔVcn is the maximum voltage ripple of the DCsmoothing capacitor, and ω is anglar frequency of the carrier.
In addition, the capacitances of the DC smoothing capacitor
for C1 and C2 in the SMC-A inverter, C1 and C2 in the SMCB inverter, and C1 and C2 in the SGC inverter are also given
by equation (34)

Fig.3. Efficiency comparison of the four five-level inverters.

2) Capacitor loss
The conduction loss PCap that occurs in the capacitor isbased on the equivalent series resistance (ESR) and is givenby2

PCap = I rms _ Cap RESR

,

(35)

where Irms_Cap is the rms value of the capacitor current, and
RESR is the ESR value of the capacitor.
The rms value of the capacitor is given byI rms _ Cap = K Cap I m

,

2

(36)

using the capacitor current coefficient KCap. The capacitor
current coefficient KCap is calculated from the normalized
simulation [4].
3) Capacitor volume
The capacitors volume is calculated based oncommercially available film capacitors and electrolytic
capacitors [4].
The volume of the film capacitor is proportional to theenergy stored in the capacitor. The volume VolCF of the film
capacitor is given by

PL =

Im
RL
2
,

(41)

where RL is the resistance of the winding wire of the inductor.
Note that the inductor loss considers only copper loss of theinductor in this paper. The iron loss of the inductor is notconsidered in this paper.
IV.

COMPARISON OF MULTILEVEL INVERTERS USINGPARETO-FRONTThis section discusses the performances of five-level
converters, namely, the ANPC inverter, the SMC-A inverter,
the SMC-B inverter, and the SGC inverter using Pareto-front
curves.

−1 1
VolCF = γ VCF
CFUO2
2
,

Figure 4 shows the loss analysis results for the five(37) inverter topologies. Table 2 shows the converter
specifications and device parameters. In figure 5, thewhere γ-1VCF is the proportionality factor between the energy
efficiencies for each of the converter are follows, the ANPC
and the volume, CF is the capacity of the film capacitor, andtype is 99.03 %, the SMC-A type is 98.91 %, SMC-B type is
UO is the applied voltage of the film capacitor.
99.01 % and SGC type is 98.83 %. The efficiency of the
ANPC type is shown to be the highest among the inverter
The volume of the electrolytic capacitor is proportional
topologies. It should be noted that the inductor loss is notto the rms value of the ripple current of the electrolytic
considered. Basically the inductor loss is the same even thecapacitor. The volume VolCE of the electrolytic capacitor is
topology is different because the current waveform in thegiven byinductor is the same. The ANPC inverter, SMC-A, and−1
SMC-B uses 200 V rated voltage and 300 V rated voltage
Vol CE = γ VCE
I C , RMS,
(38) devices. The SGC inverter uses 200 V rated voltage and 500
V rated voltage devices.
where γ-1VCE is the proportionality factor between the rms
Figure 5 shows the volume analysis results of four types
value of the ripple current and the volume, and IC,RMS is theof
5-levelinverter topologies. In figure 5, the volumes forrms value of the ripple current of the electrolytic capacitor.
each of the converter are follows; the ANPC type is 0.83
D. Inductor design
dm3, the SMC-A type is 1.06 dm3, SMC-B type is 1.00 dm3
and
SGC type is 1.07 dm3. The volume of the ANPC type is
The inductor parameters for the four multilevel converter
shown to be the smallest among the other inverter
topologies are calculated under ideal conditions, i.e., no
topologies.
current ripple and no voltage ripple in the capacitors.
This utility interaction inductor, L, suppresses the output
current ripple and is given byL=

Edc − 3Vm ⎛V
1⎞⎜ 3 m − ⎟T(n − 1)ΔI ⎜⎝ E dc 2 ⎟⎠Figure 6 shows the Pareto front curves for the four typesof five-level inverter topologies at the range of switchingfrequency from 5 kHz to 500 kHz. Table 3 shows the
Table 2 Converter specifications and devices

,

(39)

where ΔI is the ripple current.

Rated power
Input voltage
Modulation index
ANPC

The volume VolL of the inductor is calculated by the area
product [6] as follows
Switchingdevice3
4⎛ 2W ⎞⎟⎟
VolL = KV ⎜⎜⎝ K u Bm J w ⎠ ,

SMC-B

(40)

where KV is a constant value determined by the figuration of
the core, Ku is the window utilization factor, W is the
maximum energy of the inductor, Jw is the current density of
the winding wire, and Bm is the flux density.
The inductor loss is given by

SMC-A

SGC

Flying capacitor
DC smoothing
capacitor
Heatsink

10 kW
350 V
0.933
Cell1
Cell2
Cell1

Output frequency
50 Hz
Output voltage
200 V
Output current
29 A
MOSFET:IRFP4668pBF(IR)MOSFET:IXFB170N30P(IXYS)MOSFET:IRFP4668pBF(IR)MOSFET(S5,S6):IXFB170N30P(IXYS)Cell2
MOSFET(SA,SB):IRFP4668pBF(IR)MOSFET(S1,S2):IXFB170N30P(IXYS)Cell1
MOSFET(S3,S4):IRFP4668pBF(IR)MOSFET(S5,S6):IXFB170N30P(IXYS)Cell2
MOSFET(SA,SB):IRFP4668pBF(IR)MOSFET:IRFP4668pBF(IR)Cell1
MOSFET(S9,S10):IXFB132N50P3(IXYS)Cell2
MOSFET(SA,SB):IRFP4668pBF(IR)TACD series (Nippon chemi-con)
3.3 F – 88 F, 22.5A, 315 V 4 parallel connection
Ripple Voltage 30 %LXS series (Nippon chemi-con)
9000 F, 17.9 A, 400 V 5 parallel connection
Ripple Voltage 5 %CSPI 10performance comparison of the inverter topologies at
maximum power density point. In the figure 6, the efficiency
and the power density of the ANPC inverter are the highest
in the inverter topologies. On the other hand, the efficiency
and the power density of the SGC inverter are the lowest in
the inverter topologies.
These converters use two kind of the semiconductor. We
assume that the on-resistance of the semiconductor is
proportional to breakdown voltage, SGC inverter uses 200 V
rated voltage and 500 V rated voltage devices. The
semiconductor loss of the SGC inverter is highest in the
inverter topologies. In addition, volume of the heatsink is
proportional to semiconductor loss. Thus, the performance of
the SGC inverter is lowest in the inverter topologies. On theother hand, ANPC inverter, SMC-A inverter, and SMC-B
inverter use same semiconductors. Thus, the loss of the
ANPC inverter is as same as the losses of the SMC-A
inverter and the SMC-B inverter. However, the number ofthe flying capacitor in the SMC-A inverter and the SMC-B
inverter is twice the number of flying capacitor of the ANPC
inverter. Thus, the volumes of the SMC-A inverter and the
SMC-B inverter are larger than the ANPC inverter. Based on
the results, the ANPC inverter can achieve the highest
efficiency and highest power density in five-level inverter
topologies.
V.

Fig. 4. Loss analysis of the inverter topologies.

CONCLUSION
Fig. 5. Volume analysis of the inverter topologies.

This paper discussed the performance of four five-level
inverter topologies which are calculated by using the
optimize design method. The comparison results based on
Pareto front curve demonstrated that the five-level ANPC
inverter can achieve high efficiency and high power density
among the converters even the switching frequency ischanges from 5 kHz to as high as 500kHz.

99.5

SGC

[2]

[3]
[4]

[5]

[6]

SMC-A

98.5

ANPC

98

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100kHz99

In the future, the performance comparison at deferent
conditions will be discussed with the four types of multilevel
topologies in experiment.
[1]

Specification : 10-kW rating, input 350V,
output 200V/28.9A/50Hz
Flying Capacitor (Film) : 4-parallel connection
DC smoothing Capacitor : 5-parallel connection

97.5
8

SMC-B

9

10
11
12
Power density[kW/dm3]

13

14

Fig. 6. Pareto front curve of the inverter topologies.
Talbe 4.Performance comparison of the inverter
topologies at maximum power density.

[7]

Wm. T. Mclyman: “Transformer and inductor design handbook”,
Marcel Dekker Inc. (2004)