PCI-DAS1602/12

Specifications

Document Revision 4.2, February, 2010
© Copyright 2010, Measurement Computing Corporation

Specifications
Typical for 25 °C unless otherwise specified.
Specifications in italic text are guaranteed by design.

Analog input
Table 1. Analog input specifications
A/D converter type
Resolution
Number of channels
Input ranges(SW programmable)
Polarity
A/D pacing(SW programmable)

A/D conversion time

ADS7800
12 bits
16 single ended / 8 differential, software selectable
Bipolar: ±10 V, ±5 V, ±2.5 V, ±1.25 V
Unipolar: 0 to 10 V, 0 to 5 V, 0 to 2.5 V, 0 to 1.25 V
Unipolar/Bipolar, software selectable
Internal counter
External source (A/D External Pacer)
Software polled
Software selectable option, burst rate = 3 µS.
External digital (A/D External Trigger)
External analog (Analog Trigger In)
External digital: Software configurable for: edge (triggered) level-activated (gated).
Programmable polarity (rising/falling edge trigger, high/low gate).
External analog: Software-configurable for:
 Positive or negative slope.
 Above or below reference Positive or negative hysteresis
 In or out of window
Trigger levels set by DAC0 and/or DAC1, 4.88 mV resolution.
Unlimited pre- and post-trigger samples. Total # of samples must be > 512. Compatible withboth digital and analog trigger options.
From 1024 sample FIFO via REPINSW
Programmed I/O
3.0 µS max

Throughput
Calibration

330 kS/s min
Auto-calibration, calibration factors for each range stored on board in non-volatile RAM.

Burst mode
A/D trigger sources
A/D triggering modes

Data transfer1

PCI-DAS1602/12

Specifications

Accuracy
330 kHz sampling rate, single channel operation and a 60-minute warm-up. Accuracies are listed for operationaltemperatures within ±2 ºC of internal calibration temperature. Calibrator test source high side tied to Channel 0High, and low side tied to Channel 0 Low. Low-level ground is tied to Channel 0 Low at the user connector.
Table 2. Absolute accuracy specifications
Range

Absolute Accuracy (LSB)

Absolute Accuracy (mV)

±10 V
±5 V
±2.5 V±1.25 V
0 V to +10 V
0 V to +5 V
0 V to +2.5 V
0 V to +1.25 V±2.5 LSB±2.5 LSB±2.5 LSB±2.5 LSB±2.5 LSB±2.5 LSB±2.5 LSB±2.5 LSB±12.2±6.10±3.05±1.53±6.10±3.05±1.53±0.76

Table 3. Accuracy components (errors in LSBs)
Range

Gain Error

Offset Error

DLE

ILE

±10 V
±5 V
±2.5 V±1.25 V
0 to +10 V
0 to +5 V
0 to +2.5 V
0 to +1.25 V±1.0 max±1.0 max±1.0 max±1.0 max±1.0 max±1.0 max±1.0 max±1.0 max±1.0 max±1.0 max±1.0 max±1.0 max±1.0 max±1.0 max±1.0 max±1.0 max±0.75 max
±0.75 max
±0.75 max
±0.75 max
±0.75 max
±0.75 max
±0.75 max
±0.75 max

±1.5 max±1.5 max±1.5 max±1.5 max±1.5 max±1.5 max±1.5 max±1.5 max

Each PCI-DAS1602/12 is tested at the factory to assure the board’s overall error does not exceed accuracy
limits described in Table 2.
As shown in Table 3, total board error is a combination of gain, offset, differential linearity error (DLE) andintegral linearity error (ILE). The theoretical worst-case error of the board may be calculated by summing thesecomponent errors. Worst case errors are realized only in the unlikely event that each of the component errors isat their maximum level, and causing error in the same direction.
Table 4. Analog input drift specifications
ADC full-scale gain drift
ADC zero drift
No missing codes guaranteed
Common mode range
CMRR @ 60 Hz
Input impedance
Input leakage current
Absolute maximum input voltage
Warm-up time

±6 ppm/°C±6 ppm/°C
12 bits±10 V-70 dB typ
10 MOhm min
200 nA max±35 V power on or off60 minutes

2PCI-DAS1602/12

Specifications

Noise performance
Table 5 summarizes the noise performance for the PCI-DAS1602/12. Noise distribution is determined bygathering 50 K samples @ 330 kHz with inputs tied to ground at the user connector.
Table 5. Noise performance specifications
Range% within ±2 counts% within ±1 count

MaxCounts

LSBrms*±10 V±5 V±2.5 V±1.25 V
0 to +10 V
0 to +5 V
0 to +2.5 V
0 to +1.25 V

100%
100%
100%
100%100%
100%
100%
100%

100%100%
100%
100%
100%
100%
100%
100%

333533350.45
0.45
0.45
0.76
0.45
0.45
0.45
0.76

* RMS noise is defined as the peak-to-peak bin spread divided by 6.6.

Analog output
Table 6. Analog output specifications
A/D converter type
Resolution
Number of channels
Voltage ranges
Monotonicity
Overall analog output drift
Slew rate

Settling time
Current drive
Output short-circuit duration
Output coupling
Output impedancePower up and reset

AD7945BR multiplying type12-bits2±10 V, ±5 V, 0 to 5 V, 0 to 10 V. Each independently programmable
Guaranteed monotonic over temperature ±0.02 LSB/°C
 ±10 V Range:
15 V/µs
 ±5 V Range:
10 V/µs
 0 to 10 V Range:
7.5V/µs
 0 to 5 V Range:
5 V/µs20 V step to 0.012%: 4 µs max±5 mA
Indefinite @ 25 mA
DC
0.1 ohms
DACs cleared to 0 volts ±200 mV max

Accuracy
Table 7. Absolute accuracy specifications
Range

Absolute Accuracy

±10 V
±5 V
0 V to +10 V
0 V to +5 V

±3.0 LSB±3.0 LSB±3.0 LSB±3.0 LSB

3

PCI-DAS1602/12Specifications

Table 8. Accuracy components (errors in LSBs)
Range

Gain Error (LSB)

Offset Error (LSB)

DLE (LSB)

ILE (LSB)

±10 V
±5 V
0 to +10 V
0 to +5 V±2.0 max±2.0 max±2.0 max±2.0 max±0.1 max±0.2 max±0.2 max±0.4 max±1.0 max±1.0 max±1.0 max±1.0 max±1.0 max±1.0 max±1.0 max±1.0 max

Each PCI-DAS1602/12 is tested at the factory to assure the board’s overall error does not exceed ±3.0 LSB.
Total board error is a combination of gain, offset, integral linearity and differential linearity error. The
theoretical worst-case error of the board may be calculated by summing these component errors. Worst caseerror is realized only in the unlikely event that each of the component errors are at their maximum level, andcausing error in the same direction. Although an examination of the chart and a summation of the maximum
theoretical errors shows that the board could theoretically exhibit a ±4.4 LSB error, our testing assures this error
is never realized in a board that we ship.

Analog output pacing and triggering
Table 9. Analog output pacing and triggering specifications
D/A pacing(SW programmable)
D/A trigger Modes
Data transfer

Throughput

Internal counter
External source (D/A EXTERNAL PACER)
Software paced
External digital (EXTERNAL D/A PACER GATE)Software triggered
From 1024 sample FIFO via REPOUTSW mode. Data interleaved for dual analog output mode.
Programmed I/OUpdate DACs individually or simultaneously (SW selectable)
250 KHz max per channel, 2 channels simultaneous

Digital input/output
Table 10. Digital input/output specifications
Digital type
Number of I/OConfiguration

Input high voltage
Input low voltage
Output high voltage(IOH = -2.5 mA)
Output low voltage(IOL = 2.5 mA)
Power-up / reset state

82C55
24 (FIRSTPORTA Bit 0 through FIRSTPORTC Bit 7)
2 banks of 8 and 2 banks of 4 or
3 banks of 8 or
2 banks of 8 with handshake
2.0 V min, 5.5 V absolute max
0.8 V max, –0.5 V absolute min
3.0 V min
0.4 V max
Input mode (high impedance)

4

PCI-DAS1602/12

Specifications

Interrupts
Table 11. Interrupt specifications
Interrupt
PCI Interrupt enableInterrupt sources

INTA# - mapped to IRQn via PCI BIOS at boot-time
Programmable External (rising TTL edge event) Residual sample counter A/D end of conversion
 A/D end of channel scan
 A/D FIFO-not-empty
 A/D FIFO-half-full D/A FIFO-not-empty
 D/A FIFO-half-fullCounters
Table 12. Counter specifications
Counter type
Configuration
Counter 1 — ADC residual sample
counterCounter 2 — ADC pacer lower divider

Counter 3 — ADC pacer upper divider

Counter 4 — Pre-trigger mode

Counter 4 — Non pre-trigger mode

Counter 5 — DAC pacer lower divider

Counter 6 — DAC pacer upper divider

Gate width highGate width low
Input highInput low
Output highOutput low
Crystal oscillator frequency

82C54
Two 82C54 devices. 3 down counters per 82C54, 16 bits each
Source:
ADC Clock
Gate:
Programmable source
Output:End-of-Acquisition interrupt source
Source:Internal 10 MHz
Gate:
Tied to counter 3 gate, programmable source.
Output:Chained to counter 3 clock
Source:Counter 2 output
Gate:
Tied to counter 2 gate, programmable source
Output:
ADC Pacer clock (if software selected), available at userconnector
Source:
ADC ClockGate:
A/D External Trigger
Output:End-of-Acquisition interrupt source
Source:User input at 100-pin connector (CLK 4) or internal 10 MHz(software selectable)
Gate:
User input at 100-pin connector (GATE 4)
Output:Available at 100-pin connector (OUT 4)
Source:Internal 10 MHz
Gate:
Tied to counter 6 gate, programmable source.
Output:Chained to counter 6 clock
Source:Counter 5 output
Gate:
Tied to Counter 5 gate, programmable source.
Output:DAC Pacer clock, available at user connector(D/A INTERNAL PACER OUTPUT)
50 ns min
50 ns min
2.0 volts min, 5.5 volts absolute max
0.8 volts max, -0.5 volts absolute min
3.0 volts min @ -2.5 mA
0.4 volts max @ 2.5 mA
10 MHz5

PCI-DAS1602/12Specifications

Power consumption
Table 13. Power consumption specifications+5 V+12 V

1.2 A typical, 1.5 A max
30 mA max

Environmental
Table 14. Environmental specifications
Operating temperature range
Storage temperature range
Humidity

0 to 70°C-40 to 100°C
0 to 95% non-condensing

Mechanical
Table 15. Mechanical specifications
Card dimensionsPCI half card: 174.4 mm (L) x 100.6 mm (W) x 11.65 mm (H)Main connector and pin out
Table 16. Main connector specifications
Connector typeCompatible cables
Compatible accessory products

100-pin high-density Robinson-Nugent.
C100FF-x
ISO-RACK16/P
ISO-DA02/P
BNC-16SE
BNC-16DI
CIO-MINI50
CIO-TERM100
SCB-50SSR-RACK24 (DADP-5037 adaptor required)
SSR-RACK08 (DADP-5037 with TN-MC78M05CT adaptor required)
CIO-ERB24 (DADP-5037 adaptor required)
CIO-ERB08 (DADP-5037 adaptor required)
CIO-SERB08 (DADP-5037 adaptor required)

6PCI-DAS1602/12

Specifications

Table 17. 8-channel differential mode
Pin1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950Signal Name
LLGND
CH0 HI
CH0 LOCH1 HI
CH1 LOCH2 HI
CH2 LOCH3 HI
CH3 LOCH4 HI
CH4 LOCH5 HI
CH5 LOCH6 HI
CH6 LOCH7 HI
CH7 LO
LLGND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
D/A GND 0
D/A OUT 0
D/A GND 1
D/A OUT 1
CTR4 CLK
CTR4 GATECTR4 OUT
A/D EXTERNAL PACER
ANALOG TRIGGER IN
D/A EXTERNAL PACER IN
A/D EXTERNAL TRIGGER IN
N/CN/CPC +5 V
SSH OUT
GND

Pin
515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991007Signal Name
FIRSTPORTA Bit 0
FIRSTPORTA Bit 1
FIRSTPORTA Bit 2
FIRSTPORTA Bit 3
FIRSTPORTA Bit 4
FIRSTPORTA Bit 5FIRSTPORTA Bit 6
FIRSTPORTA Bit 7
FIRSTPORTB Bit 0
FIRSTPORTB Bit 1
FIRSTPORTB Bit 2
FIRSTPORTB Bit 3
FIRSTPORTB Bit 4
FIRSTPORTB Bit 5
FIRSTPORTB Bit 6
FIRSTPORTB Bit 7
FIRSTPORTC Bit 0
FIRSTPORTC Bit 1
FIRSTPORTC Bit 2
FIRSTPORTC Bit 3
FIRSTPORTC Bit 4
FIRSTPORTC Bit 5
FIRSTPORTC Bit 6
FIRSTPORTC Bit 7
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND+12 V
GND-12 V
N/C
N/C
A/D INTERNAL PACER OUTPUT
D/A INTERNAL PACER OUTPUT
EXTERNAL D/A PACER GATE
N/C
EXTERNAL INTERRUPT
GND

PCI-DAS1602/12

Specifications

Table 18. 16-channel single-ended modePin
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950Signal Name
LLGND
CH0 HI
CH8 HICH1 HI
CH9 HICH2 HI
CH10 HI
CH3 HI
CH11 HI
CH4 HI
CH12 HICH5 HI
CH13 HICH6 HI
CH14 HI
CH7 HI
CH15 HI
LLGND
N/C
N/C
N/C
N/C
N/CN/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
D/A GND 0
D/A OUT 0
D/A GND 1
D/A OUT 1
CTR4 CLK
CTR4 GATECTR4 OUT
A/D EXTERNAL PACER
ANALOG TRIGGER IN
D/A EXTERNAL PACER IN
A/D EXTERNAL TRIGGER IN
N/C
N/C
PC +5 VSSH OUT
GND

Pin
51525354555657585960
6162636465
66
6768
69
7071
72
73
747576777879808182838485
86878889909192939495969798991008Signal Name
FIRSTPORTA Bit 0
FIRSTPORTA Bit 1FIRSTPORTA Bit 2FIRSTPORTA Bit 3
FIRSTPORTA Bit 4
FIRSTPORTA Bit 5
FIRSTPORTA Bit 6
FIRSTPORTA Bit 7
FIRSTPORTB Bit 0
FIRSTPORTB Bit 1
FIRSTPORTB Bit 2
FIRSTPORTB Bit 3
FIRSTPORTB Bit 4
FIRSTPORTB Bit 5
FIRSTPORTB Bit 6
FIRSTPORTB Bit 7
FIRSTPORTC Bit 0
FIRSTPORTC Bit 1
FIRSTPORTC Bit 2
FIRSTPORTC Bit 3
FIRSTPORTC Bit 4
FIRSTPORTC Bit 5
FIRSTPORTC Bit 6
FIRSTPORTC Bit 7
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/CN/C
N/C
GND
+12 V
GND
-12 V
N/C
N/C
A/D INTERNAL PACER OUTPUT
D/A INTERNAL PACER OUTPUT
EXTERNAL D/A PACER GATE
N/C
EXTERNAL INTERRUPTGND

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PCI-DAS1602_12 SPEC.doc