ZA03W10
WDR60FPS

Brief data sheet
Version 1.0
2011.10.25

ZeeAnn Co., Ltd.
107, Chogwang-ro 46beon-gil, Hanam-si, Gyeonggi-do, 465-230 Korea
T.+82-70-8224-4582
F.+82-2-482-0088
http://www.zeeann.com
sales@zeeann.com

ZA03W10

Applications■■

security and surveillance cameras
automotive cameras

Features
Automatic controls :automatic exposure control(AEC), automatic gain
control (AGC), automatic black level calibration (ABLC),
automatic white balance (AWB),
auto flicker detection (AFD)■

Programmable controls :exposure, gain, frame rate, horizontal mirror, verticalflip, scaling, windowing■

Support for eclipse cancellation■

Support for flash strobe and output enable■

Support for serial interface compatible with I2C■

Support for output formats :10-bit raw / denoised / ISP Bayer,YUV422, BT656, HREF, RGB565■

Support for image size :480p @ 60fps / 30fps
VGA @ 60fps / 30fps■ Support for input clock : 13.5/18/27/54MHz■

Image adjusting functions :lens shading correction, color correction, gamma
correction, hue and saturation, brightness, contrast,sharpness(edge enhancement), false color suppression,chroma suppression,■ Efficient denoising coupled with defective pixel
correction■■

On-chip phase locked loop (PLL, 108MHz)

Key specifications■

Active pixel array : 720H X 480V■

Optical format : 1/3 inch■

Pixel size : 6.9um X 6.9um■

Scan mode : progressive■

Shutter : rolling shutter■

Maximum image transfer rate :480p and VGA (Bayer) : 60fps
480p and VGA (YUV) : 60fps

Output interface : 10-bit parallel
Output formats : 10-bit raw / denoised / ISP
Bayer, YUV422, BT656, HREF, RGB565■

Sensitivity :

■

SNR :

■

Dynamic range : 120dB■

Dark current :■Input clock frequency : 13.5/18/27/54MHz■

On-chip phase locked loop (PLL):108MHz■

Power supply :analog : 3.3V ± 10%
core : 1.8V ± 5%
I/O : 2.6~3.6V (3.3V Typical)■

Power requirement :active : 223mW
standby : 611uW (master clock on)
power down : 178uW (master clock off)■

Temperature range :operating :■■1/3-inch 480p WDR color CMOS Image Sensor

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ZA03W10

1. Signal DescriptionsTable 1-1 lists the signal descriptions and their corresponding pin names for the ZA03W10 imagesensor. Refer to the “chip information” file for the package information.

Table 1-1 Signal Descriptions (sheet 1 of 2)
NameI/O
TypeATEST

OutputAnalog test pin.

AVDD

SupplyAnalog power 3.3V with 0.1uF to AGND. †AGND

SupplyAnalog power ground.

PVDD

SupplyPixel power 3.3V with 0.1uF to AGND. †AGND

SupplyAnalog power ground.

AVDD

SupplyAnalog power 3.3V with 0.1uF to AGND. †AGND

SupplyAnalog power ground.

RVDD

SupplyInternal regulator power 3.3V with 0.1uF to AGND. †IOVDDSupplyI/O power 2.6V~3.3V with 0.1uF to IOGND. †PLLGND

SupplyPLL power ground.

SYSCLK

Input

Master clock. (13.5/18/27/54 Mhz)

PLLVDD

SupplyPLL control block power 1.8V with 0.1uF to PLLGND. †DGND

SupplyDigital power ground.

D9I/O

Parallel pixel data output 9.

D8

I/O

Parallel pixel data output 8.

D7

I/O

Parallel pixel data output 7.

DVDD

SupplyD6I/O

Parallel pixel data output 6.

D5I/O

Parallel pixel data output 5.

D4I/O

Parallel pixel data output 4.

IOGND

SupplyD3I/O

Parallel pixel data output 3.

D2

I/O

Parallel pixel data output 2.

Functions / Descriptions

Digital power 1.8V with 0.1uF to DGND. †I/O power ground.

†. The decoupled capacitors must be tied to the corresponding ground pins.

1/3-inch 480p WDR color CMOS Image Sensor

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ZA03W10

Table 1-1 Signal Descriptions (sheet 2 of 2)
NameI/O
Type

D1

I/O

Parallel pixel data output 1.

D0I/O

Parallel pixel data output 0.

PIXCLK

OutputPixel clock. Data can be latched by external devices at therising or falling edge of PIXCLK. The polarity and drivability
can be controlled.

DVDD

SupplyDigital power 1.8V with 0.1uF to DGND. †DGND

SupplyDigital power ground.

HSYNC

I/O

Horizontal synchronization output. Asserted when pixel dataoutput is valid.

VSYNC

I/O

Vertical sync : Indicates the start of a new frame.

IOVDDSupplySDATA

I/O

Two-wire serial interface data.

SCLK

Input

Two-wire serial interface clock.

FSTROBE

OutputFlash or LED strobe output.

SADR1

Input

Two-wire serial interface slave address bit5.

SADR0

Input

Two-wire serial interface slave address bit2.

OUTEN

Input

Data output enable. When OUTEN is ‘LOW’, D[9:0] are tristate mode. But, sensor is operation or not.

RSTB

Input

Asynchronous system reset. All registers are set to theirdefault values.

STDBY

Input

Power down sensor operation. When STDBY=‘1’ there’s nocurrent flow in any analog circuit branch, neither any beat ofdigital clock. D[9:0] and PIXCLK, HSYNC, VSYNC pins can be
programmed to tri-state or all ‘1’ or all ‘0’. But it is possible tocontrol internal registers through I2C bus interface in STDBY
mode. All registers retain their current values.

TEInput

Chip test mode enable.

IOGND

SupplyI/O power ground.

DVDD

SupplyDigital power 1.8V with 0.1uF to DGND. †DGND

SupplyDigital power ground.

Functions / Descriptions

I/O power 2.6V~3.3V with 0.1uF to IOGND. †1/3-inch 480p WDR color CMOS Image Sensor

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