SPECIFICATIONSCIO-DAS16/330
Analog Input & Digital I/O

Revision 4, October, 2001

© Copyright 2001, MEASUREMENT COMPUTING CORPORATIONPower Consumption+5V:

900 mA typical, mA max

Analog Input Section
A/D converter type
Resolution
Number of channels
Programmable ranges
Polarity
A/D pacing
A/D Trigger sources
A/D Triggering Modes
Digital:

AD780012 bits
8 differential or 16 single-ended, switch-selectable±10V, ±5V, ±2.5V, ±1.25V , ±0.625V, 0 to 10V, 0 to 5V,0 to 2.5V, 0 to 1.25V, 0 to 0.625V, fully programmable
Unipolar/Bipolar, software-selectable
Programmable: internal counter or external source (DIG. IN 0 /TRIGGER, rising edge) or software-polled
External hardware/software (DIG. IN 0 / TRIGGER, active high)

DMA
A/D conversion timeThroughput

Gated pacer, software-polled. (Gate must be disabled by software
after trigger event.)
From 512 sample FIFO via REPINSW, interrupt,
DMA or software polled
Channel 1 or 3, switch-selectable
3 µs330 kHz

Absolute accuracy
Differential Linearity error
Integral Linearity error
Differential Linearity error
No missing codes guaranteed
Gain drift (A/D specs)
Zero drift (A/D specs)

0.01% of reading ±1 LSB±1 LSB±1 LSB±1 LSB
12 bits±25 ppm/°C±10 ppm/°C

Common Mode Range
CMRR @ 60 Hz
Input leakage current
Input impedance
Absolute max. input voltage

±10V
−72dB
200 nA (@25 Deg C)
10 MegOhms min±35V

Data transfer

Digital Input / Output
Digital type:
Input:
Output:Configuration
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Absolute max. input voltage

74LS367
74LS197
Two ports, 4 input bits and 4 output bits
0.8V max
2.0V min
0.5V max (IOL = 8 mA)
2.7V min (IOH = −0.4 mA)−0.5V, +7V

Interrupts
Interrupt enable
Interrupt sources

2 through 7, 10 and 11, programmable
Programmable
A/D End-of-conversion, A/D FIFO-half-full, Residual counter,
DMA terminal countCounter Section
Counter type
Configuration

82C54
Two 82C54 devices, 3 down-counters each device; 16 bits each.

82C54A:Counter 0 - Independent, available to user
Source: 100 kHz on board clock or external (CTR 0 Clock In)
Gate:External (Dig In 2 / CTR 0 Gate)
Output: Available at user connector (CTR 0 Out)Counter 1 - ADC Pacer Lower Divider
Source: 1 or 10 MHz oscillator, jumper-selectable
Gate:
Tied to Counter 2 gate, programmable source (internal orexternal (Dig In 0 / Trigger).
Output: Chained to Counter 2 Clock.
Counter 2 - ADC Pacer Upper Divider
Source: Counter 1 Output.
Gate:
Tied to Counter 1 gate, programmable source: internal orexternal (Dig In 0 / Trigger).
Output: ADC Pacer clock, available at user connector (CTR 2Out)
82C54B:Counter 0 - Total samples (residual) counter upper divider
Source: Counter 1 output (total samples lower divider)
Gate:
Internal
Output: InternalCounter 1 - Total samples (residual) counter lower divider
Source: ADC conversion complete
Gate:
Tied to Counter 2 gate, internal source.
Output: Counter 0 input (total samples upper divider)Counter 2 - Trigger index counter
Source: ADC conversion complete
Gate:
Tied to Counter 1 gate, internal source.
Output: Not used
Clock input frequency
High pulse width (clock input)
Low pulse width (clock input)
Gate width highGate width low
Input low voltage
Input high voltage
Output low voltage
Output high voltage

10 MHz max
30 ns min
50 ns min
50 ns min
50 ns min
0.8V max
2.0V min
0.4V max
3.0V minCrystal Oscillator Frequency
Frequency accuracy

10 MHz
100 ppmEnvironmental
Operating temperature range
Storage temperature range
Humidity

0 to 50°C−20 to 70°C
0 to 90% non-condensing

Measurement Computing Corporation
10 Commerce Way
Suite 1008
Norton, Massachusetts 02766(508) 946-5100
Fax: (508) 946-9500
E-mail: info@mccdaq.com
www.mccdaq.com