RS72XP-Q1

13MHz, Rail-to-Rail I/O CMOS Operational Amplifier
1 FEATURES


Qualified for Automotive Applications



AEC-Q100 Qualified with the Grade 1

HIGH GAIN BANDWIDTH: 13MHz

RAIL-TO-RAIL INPUT AND OUTPUT±0.5mV Typical Vos



INPUT VOLTAGE RANGE: -0.1V to +5.6V
with VS = 5.5V



SUPPLY RANGE: +2.7V to +5.5V



SPECIFIED UP TO +125°C

Micro SIZE PACKAGES: SOT23-5, SOP8

2 APPLICATIONSSENSORSPHOTODIODE AMPLIFICATIONACTIVE FILTERSTEST EQUIPMENTDRIVING A/D CONVERTERS

3 DESCRIPTIONSThe RS72XP-Q1 families of products offer low
voltage operation and rail-to-rail input and output, as
well as excellent speed/power consumption ratio,
providing an excellent bandwidth (13MHz) and slew
rate of 8V/us. The op-amps are unity gain stable andfeature an ultra-low input bias current.
The devices are ideal for sensor interfaces, active
filters and portable applications. The RS72XP-Q1
families of operational amplifiers are specified at thefull temperature range of -40°C to +125°C undersingle or dual power supplies of 2.7V to 5.5V.

Device Information(1)PART
NUMBER
RS721P-Q1
RS722P-Q1

PACKAGEBODY SIZE (NOM)

SOT23-5

2.92mm×1.62mm

SOP8

4.90mm×3.90mm

MSOP8

3.00mm×3.00mm(1) For all available packages, see the orderable addendum
at the end of the data sheet.

REV A.3.1

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RS72XP-Q1
Table of Contents
1 FEATURES .......................................................................................................................................................1
2 APPLICATIONS ................................................................................................................................................1
3 DESCRIPTIONS ................................................................................................................................................1
4 Revision History ..............................................................................................................................................3
5 PACKAGE/ORDERING INFORMATION (1) ......................................................................................................4
6 Pin Configuration and Functions (Top View) ...............................................................................................5
7 SPECIFICATIONS ............................................................................................................................................7
7.1 Absolute Maximum Ratings ........................................................................................................................7
7.2 ESD Ratings................................................................................................................................................7
7.3 Recommended Operating Conditions .........................................................................................................7
7.4 ELECTRICAL CHARACTERISTICS ...........................................................................................................8
7.5 TYPICAL CHARACTERISTICS ............................................................................................................... 10
8 Detailed Description ..................................................................................................................................... 11
8.1 Overview .................................................................................................................................................. 12
8.2 Phase Reversal Protection ...................................................................................................................... 12
8.3 EMIRR IN+ Test Configuration ................................................................................................................ 12
9 Application and Implementation ................................................................................................................. 13
9.1 APPLICATION NOTE .............................................................................................................................. 13
9.2 25-kHz Low-pass Filter ............................................................................................................................ 13
9.3 Design Requirements .............................................................................................................................. 13
9.4 Detailed Design Procedure ...................................................................................................................... 13
9.5 Application Curve ..................................................................................................................................... 14
10 LAYOUTS..................................................................................................................................................... 15
10.1 Layout Guidelines .................................................................................................................................. 15
10.2 Layout Example ..................................................................................................................................... 15
11 PACKAGE OUTLINE DIMENSIONS ........................................................................................................... 16
12 TAPE AND REEL INFORMATION .............................................................................................................. 20

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RS72XP-Q1
4 Revision History
Note: Page numbers for previous revisions may different from page numbers in the current version.
VERSION

Change Date

Change Item

A.1

2022/10/18

A.2

2023/02/16

A.3

2023/07/03

Official version completed
1. Update IB/IOS in 7.4 ELECTRICAL CHARACTERISTICS
2. Add IOS、PSRR、CMRR curve in 7.5 TYPICAL CHARACTERISTICS
3. Update PACKAGE OUTLINE DIMENSIONS
Delete RS724P-Q1related content

A.3.1

2024/03/07

Modify packaging naming

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RS72XP-Q1
5 PACKAGE/ORDERING INFORMATION (1)Orderable
Device
RS721PXF-Q1
RS722PXK-Q1
RS722PXM-Q1

Lead
finish/Ballmaterial (2)PackageType

Pin

SOT23-55

1

NIPDAUAG

SOP8

8

2

NIPDAUAG

MSOP8

8

2

NIPDAUAG

Channel

MSL PeakTemp (3)MSL1-260°-Unlimited
MSL1-260°-Unlimited
MSL1-260°-Unlimited

Op Temp(°C)

DeviceMarking(4)-40°C ~125°C

721P-40°C ~125°C

RS722P-40°C ~125°C

RS722P

Package
Qty
Tape and
Reel,3000
Tape and
Reel,4000
Tape and
Reel,4000

NOTE:(1) This information is the most current data available for the designated devices. This data is subject to change without notice and revisionof this document. For browser-based versions of this data sheet, refer to the right-hand navigation.
(2) Lead finish/Ball material. Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruledline. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.
(3) MSL Peak Temp. The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
(4) There may be additional marking, which relates to the lot trace code information (data code and vendor code), the logo or theenvironmental category on the device.

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RS72XP-Q1
6 Pin Configuration and Functions (Top View)
RS721 P-Q1
OUT

1

V-

2

+IN

3

+

5

V+

4

-IN

-

SOT23-5

Pin Description
PIN
NAME

RS721P-Q1

I/O (1)DESCRIPTION

SOT23-5

(1)

-IN

4

I

Negative (inverting) input

+IN

3

I

Positive (noninverting) input

OUT

1

O

OutputV-

2-

Negative (lowest) power supply

V+

5

-

Positive (highest) power supply

I = Input, O = Output.

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RS72XP-Q1
Pin Configuration and Functions (Top View)
RS722P-Q1
OUT A

1

-IN A

2

8

V+

7

OUTB

6

-IN B

5

+IN B

A
+IN A

+

3

B
V-

4

+

SOP8,MSOP8

Pin Description
PIN
NAME

RS722P-Q1

I/O (1)DESCRIPTION

SOP8/MSOP8
-INA

2

I

Inverting input, channel A

+INA

3

I

Noninverting input, channel A

-INB

6

I

Inverting input, channel B

+INB

5

I

Noninverting input, channel B

OUTA

1

O

Output, channel A

OUTB

7

O

Output, channel B

V-

4

-

Negative (lowest) power supply

V+

8

-

Positive (highest) power supply(1) I = Input, O = Output.

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RS72XP-Q1
7 SPECIFICATIONS
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN

MAX

Supply, VS=(V+) - (V-)
Voltage

Current

7Signal input pin (2)(V-)-0.5(V+) +0.5

Signal output pin (3)(V-)-0.5(V+) +0.5

Signal input pin (2)

-10

10

mA

Signal output pin (3)

-200

200

mA

Output short-circuits (4)θJA

SOT23-5

230

SOP8

110

MSOP8

°C/W

170

Operating range, TA
Junction, TJ

V

Continuous

Package thermal impedance (5)Temperature

UNIT

(6)

Storage, Tstg

-40

125

-40

150

-65

150

°C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should
be current-limited to 10mA or less.
(3) Output terminals are diode-clamped to the power-supply rails. Output signals that can swing more than 0.5V beyond the supply rails
should be current-limited to ±200mA or less.
(4) Short-circuit to ground, one amplifier per package.
(5) The package thermal impedance is calculated in accordance with JESD-51.
(6) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (T J(MAX) - TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.

7.2 ESD Ratings
The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only.
VALUE
V(ESD)

Electrostatic discharge

Human-Body Model (HBM), per AEC Q100-002 (1)±2000

Charged-Device Model (CDM), per AEC Q100-011±500

Latch-Up (LU), per AEC Q100-004

±100

UNIT
V
mA

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

ESD SENSITIVITY CAUTION
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.

7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted).
MIN
Supply voltage，VS= (V+) - (V-)

NOM

MAX

Single-supply

2.7

5.5

Dual-supply

±1.35

±2.75

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UNIT
V

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RS72XP-Q1
7.4 ELECTRICAL CHARACTERISTICS(At TA = +25C, VS=2.7V to 5.5V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, Full (9) = -40°C to +125°C, unless otherwise
noted.) (1)
RS72XP-Q1
PARAMETERCONDITIONSTJMIN (2)TYP (3)

MAX (2)

UNIT

5.5

V

POWER SUPPLYVSOperating Voltage Range

IQ

Quiescent Current/Amplifier

VS=±2.5V, Io=0mA

PSRR

Power-Supply Rejection Ratio

VS=2.7V to 5.5V

VOS

Input Offset Voltage

VCM=VS/2

VOS TC

Input Offset Voltage Average
Drift

25C

2.7
1.15

25C
Full

1.35
1.85

25C

75

Full

70

25C

-1.5

Full

-3

93

mA
dB

INPUT

IB

Input Bias Current (4) (5)VCM=VS/2

3

mV

±2.6

25C

±1

±10

pA

Full

0.5

±10

nA

25C

±1

±10

pA

±10

nA

5.6

V

Input Offset Current (5)VCM=VS/2

VCM

Common-Mode Voltage Range

VS= 5.5V

25C

-0.1

VS= 5.5V, VCM=-0.1V
to 3.5V

25C

73

Full

70

VS= 5.5V, VCM=-0.1V
to 5.6V

25C

60

Full

59

Open-Loop Voltage Gain

RL=10KΩ, Vo=(V-)+0.1V to (V+)-0.1V

25C

110

Full

94

Output Swing from Rail

VS=±2.5V, RL=10KΩ

IOUT

Output Short-Circuit Current(6) (7)VS=±2.5V, Vo=0V

CLOAD

Capacitive Load Drive

Full

Common-Mode Rejection Ratio

1.5

Full

IOS

CMRR

±0.5

uV/C

90
dB

77

OUTPUT
AOL

127
10

25C
Full

dB
20
25

25C

±80

Full

±60

±150

mV
mA

25C

100

pF

25C

8

V/us

25C

13

MHz

25C

0.8

us

25C

0.4

us

25C

5

uVPP

FREQUENCY RESPONSE
SR

Slew Rate (8)GBP

Gain-Bandwidth ProducttS

Settling Time,0.1%

tOR

Overload Recovery Time

G=+1, CL=100pF
VS=±2.5V, G=+1,
CL=100pF, Step=2V
VIN·Gain≥VS, G=-10

NOISE
En

Input Voltage Noisef = 0.1Hz to 10Hz,
VS=±2.5V

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RS72XP-Q1
NOTE:(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statisticalquality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may varyover time and will also depend on the application and configuration.
(4) Positive current corresponds to current flowing into the device.
(5) This parameter is ensured by design and/or characterization and is not tested in production.
(6) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (T J(MAX) - TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
(7) Short circuit test is a momentary test.
(8) Number specified is the slower of positive and negative slew rates.
(9) Specified by characterization only.

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RS72XP-Q1
7.5 TYPICAL CHARACTERISTICS

1.8

10K

1.6

Input Bias Current(pA)

1.4
1.2
1
0.8
0.6
0.4

100
10
1
0.1

-55 -35 -15

5 25 45 65
Temperature(℃)

85 105 125

20mV/div

20mV/div

Figure 1. Quiescent Current vs Temperature

VIN

1K

-40 -20

20 40 60 80 100 120 140
Temperature(℃)

Figure 2. Input Bias Current vs Temperature

VIN

VOUT

0

500mV/div 500mV/div

Quiescent Current/Amplifier (mA)

NOTE: The graphs and tables provided following this note are a statistical summary based on a limited number of samples
and are provided for informational purposes only.
At TA = +25C, VS=5V, RL = 10kΩconnected to VS/2, VOUT = VS/2, unless otherwise noted.

VOUT
VS=±2.5V
CL=100pF

VS=±2.5V
CL=100pF

1us/div

5us/div

Figure 3. Small-Signal Step Response

Figure 4. Large-Signal Step Response

1uV/div

Input Offset Current(pA)

10K
1K
100
10

1
0.1

1s/div

Figure 5. 0.1Hz to 10Hz Input Voltage Noise-40 -200

20 40 60 80 100 120 140
Temperature(℃)

Figure 6. Input Offset Current vs Temperature

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RS72XP-Q1
TYPICAL CHARACTERISTICS

100
80
60
40
20
0
-20

10

100

1K

10K

100K

1M

Common-Mode Rejection Ratio (dB)

Power-Supply Rejection Ratio (dB)

NOTE: The graphs and tables provided following this note are a statistical summary based on a limited number of samples
and are provided for informational purposes only.
At TA = +25C, VS=5V, RL = 10kΩconnected to VS/2, VOUT = VS/2, unless otherwise noted.

Frequency(Hz)Figure 7. PSRR vs Frequency

100
80
60
40
20
0
-20

10

100

1K
10K
Frequency(Hz)

100K

1M

Figure 8. CMRR vs Frequency

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RS72XP-Q1
8 Detailed Description
8.1 Overview
The RS721P-Q1, RS722P-Q1 are high precision, rail-to-rail operational amplifiers that can be run from a singlesupply voltage 2.7V to 5.5V (±1.35V to ±2.75V). Supply voltages higher than 7V (absolute maximum) canpermanently damage the amplifier. Rail-to-rail input and output swing significantly increases dynamic range,
especially in low-supply applications. Good layout practice mandates use of a 0.1uF capacitor place closely
across the supply pins.

8.2 Phase Reversal Protection
The RS72XP-Q1 family has internal phase-reversal protection. Many op amps exhibit phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output toreverse into the opposite rail. The input of the RS72XP-Q1 prevents phase reversal with excessive commonmode voltage. Instead, the appropriate rail limits the output voltage. This performance is shown in figure 9.
3

Voltage (V)

2
1
0
-1
-2
VIN
VOUT

-3

Time (125us/div)
C004

Figure 9. Output Waveform Devoid of Phase Reversal During an Input Overdrive Condition

8.3 EMIRR IN+ Test Configuration
Figure 10 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to theoperational amplifier noninverting input pin using a transmission line. The operational amplifier is configured ina unity-gain buffer topology with the output connected to a low-pass filter (LPF) and a digital multimeter (DMM).
A large impedance mismatch at the operational amplifier input causes a voltage reflection; however, this effectis characterized and accounted for when determining the EMIRR IN+. The resulting dc offset voltage is sampled
and measured by the multimeter. The LPF isolates the multimeter from residual RF signals that can interferewith multimeter accuracy.
Ambient temperature: 25°C
+VS

50Ω

Low-Pass Filter+
RF source
DC Bias: 0 V
Modulation: None (CW)
Frequency Sweep: 201 pt. Log-VS
Not shown: 0.1 µF and 10 µF
supply decoupling

Sample /Averaging

Digital Multimeter

Figure 10. EMIRR IN+ Test Configuration Schematic

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RS72XP-Q1
9 Application and Implementation
Information in the following applications sections is not part of the RUNIC component specification, and RUNIC
does not warrant its accuracy or completeness. RUNIC’s customers are responsible for determining suitabilityof components for their purposes. Customers should validate and test their design implementation to confirm
system functionality.

9.1 APPLICATION NOTEThe RS72XP-Q1 are high precision, rail-to-rail operational amplifiers that can be run from a single-supply
voltage 2.7V to 5.5V (±1.35V to ±2.75V). Supply voltages higher than 7V (absolute maximum) can permanently
damage the amplifier. Rail-to-rail input and output swing significantly increases dynamic range, especially in
low-supply applications. Good layout practice mandates use of a 0.1uF capacitor place closely across the supply
pins.

Typical Applications
9.2 25-kHz Low-pass Filter
R4
2.94 kΩ
R1
590Ω

Input

C5
1 nF
R3
499Ω

-

Output+
RS72XP-Q1

C2
39 nF

Figure 11. 25-kHz Low-Pass Filter

9.3 Design Requirements
Low-pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing.
The RS72XP-Q1 devices are ideally suited to construct high-speed, high-precision active filters. Figure 11
shows a second-order, low-pass filter commonly encountered in signal processing applications.
Use the following parameters for this design example:• Gain = 5 V/V (inverting gain)• Low-pass cutoff frequency = 25 kHz• Second-order Chebyshev filter response with 3-dB gain peaking in the passband.

9.4 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 11. Use Equation
1 to calculate the voltage transfer function.
Output−1/R1 R3 C2 C5(s) = 2Input
S +(S/C2 )(1/R1 +1/R3 +1/R4 )+1/R3 R4 C2 C5(1)This circuit produces a signal inversion. For this circuit, the gain at dc and the low-pass cutoff frequency arecalculated by Equation 2:
R4
Gain =
R1
1
fc = √(1/R 3 R 4 C2 C5 )(2)2π

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RS72XP-Q1
9.5 Application Curve

Figure 12. Low-pass filter transfer function

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RS72XP-Q1
10 LAYOUTS
10.1 Layout Guidelines
Attention to good layout practices is always recommended. Keep traces short. When possible, use a PCB
ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1uF
capacitor closely across the supply pins.
These guidelines should be applied throughout the analog circuit to improve performance and provide benefits
such as reducing the EMI susceptibility.

10.2 Layout Example
+

VIN A

+

VIN B
VOUT ARG

VOUT B

RG

RF

RF

Figure 13. Schematic Representation
Place compon ents
close to device and toeach other to reduceparasitic e rro rs.

OUT A

Use low-ESR,
ceramic bypass
capacitor. Pla ce as
close to the d evice
as possible.

VS+

OUT A

V+

-IN A

OUT B

+IN A

-IN B

GND

RF

OUT B

GND
RG
VIN A

RF

GND
RG

V-

Use low-ESR,
ceramic bypass
capacitor. Pla ce as
close to the d evice
as possible.

+IN B

Ground (GND) plane on another layer
GND

VS-

VIN B

Keep input traces shortand run the input tra ces
as far aw ay fromthe supply lines
as possible.

Figure 14. Layout Example
NOTE: Layout Recommendations have been shown for dual op-amp only, follow similar precautions for Single and four.

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RS72XP-Q1
11 PACKAGE OUTLINE DIMENSIONSSOT23-5
D

1.90
b

2.6

E1

E

1.1
0.95

0.6

e
e1

RECOMMENDED LAND PATTERN (Unit: mm)

0.2
A A2

c

θ
L

A1

Dimensions In Millimeters

Dimensions In Inches

Symbol
Min

Max

A

Min

Max

1.250

0.049

A1

0.000

0.150

0.000

0.006

A2

1.000

1.200

0.039

0.047

b

0.360

0.500

0.014

0.020

c

0.100

0.200

0.004

0.008

D

2.826

3.026

0.111

0.119

E

1.526

1.726

0.060

0.068

E1

2.600

3.000

0.102

0.118

e

0.950(BSC)

0.037(BSC)

e1

1.800

2.000

0.071

0.079

L

0.350

0.600

0.014

0.024

θ

0°

8°

0°

8°

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RS72XP-Q1
MSOP8
b

e

E

E1

4.8

1.02
D

0.65

0.41

RECOMMENDED LAND PATTERN (Unit: mm)

A2
c

A
A1

L

Dimensions In MillimetersθDimensions In Inches

Symbol
Min

Max

Min

Max

A

0.820

1.100

0.032

0.043

A1

0.020

0.150

0.001

0.006

A2

0.750

0.950

0.030

0.037

b

0.250

0.380

0.010

0.015

c

0.090

0.230

0.004

0.009

D

2.900

3.100

0.114

0.122

e

0.650(BSC)

0.026(BSC)

E

2.900

3.100

0.114

0.122

E1

4.750

5.050

0.187

0.199

L

0.400

0.800

0.016

0.031

θ

0°

6°

0°

6°

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RS72XP-Q1
SOP8
D

E
X

c

y

HE

z

5.4

1.55

Q
A2

A3

A1

A
1.27

pin 1 index

LP
L
e

0.6

θ
RECOMMENDED LAND PATTERN (Unit: mm)

Detail X

bp

Dimensions In Millimeters

Dimensions In Inches

Symbol
Min

Max

A

Min

Max

1.750

0.069

A1

0.100

0.250

0.004

0.010

A2

1.250

1.450

0.049

0.057

A3

0.25

0.010

bp

0.360

0.490

0.014

0.019

c

0.190

0.250

0.007

0.010

D(A)

4.800

5.000

0.190

0.200

E(B)

3.800

4.000

0.150

0.160

HE

5.800

6.200

0.228

0.244

e

1.270

0.050

L

1.05

0.041

LP

0.400

1.000

0.016

0.039

Q

0.600

0.700

0.024

0.028

Z(A)

0.300

0.700

0.012

0.028

y
θ

0.1
0°

0.004
8°

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RS72XP-Q1
NOTE:
A. Plastic or metal protrusions of 0.15mm maximum per side are not included.
B. Plastic interlead protrusions of 0.25mm maximum per side are not included.
C. All linear dimension is in millimeters.
D. This drawing is subject to change without notice.
E. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
F. BSC: Basic Dimension. Theoretically exact value shown without tolerances.

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RS72XP-Q1
12 TAPE AND REEL INFORMATIONREEL DIMENSIONSTAPE DIMENSION

Reel
DiameterReel Width(W1)

DIRECTION OF FEEDNOTE: The picture is only for reference. Please make the object as the standard.

KEY PARAMETER LIST OF TAPE AND REEL
SOT23-5

Reel
Diameter7’’

Reel
Width(mm)
9.5

A0
(mm)
3.20

B0
(mm)
3.20

K0
(mm)
1.40

P0
(mm)
4.0

P1
(mm)
4.0

P2
(mm)
2.0

W
(mm)
8.0

Pin1
Quadrant
Q3

SOP8

13’’

12.4

6.40

5.40

2.10

4.0

8.0

2.0

12.0

Q1

MSOP8

13’’

12.4

5.20

3.30

1.50

4.0

8.0

2.0

12.0

Q1

Package TypeNOTE:
1. All dimensions are nominal.
2. Plastic or metal protrusions of 0.15mm maximum per side are not included.

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RS72XP-Q1
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data sheets), design resources (including reference designs), application or other design advice, WEB tools,
safety information and other resources, without warranty of any defect, and will not make any express or implied
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specific purpose or does not infringe the intellectual property rights of any third party.
These resources are intended for skilled developers designing with RUNIC products You will be solely
responsible for: (1) Selecting the appropriate products for your application; (2) Designing, validating and testing
your application; (3) Ensuring your application meets applicable standards and any other safety, security orother requirements; (4) RUNIC and the RUNIC logo are registered trademarks of RUNIC INCORPORATED. All
trademarks are the property of their respective owners; (5) For change details, review the revision history
included in any revised document. The resources are subject to change without notice. Our company will not
be liable for the use of this product and the infringement of patents or third-party intellectual property rights due
to its use.

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