CIO-DAS800
User's Guide

Revision 2A
October, 2000

Trademark and Copyright Information
Measurement Computing Corporation, InstaCal, Universal Library, and the Measurement Computing logo areeither trademarks or registered trademarks of Measurement Computing Corporation. Refer to the Copyrights &Trademarks section on mccdaq.com/legal for more information about Measurement Computing trademarks.
Other product and company names mentioned herein are trademarks or trade names of their respective
companies.
© 2000 Measurement Computing Corporation. All rights reserved. No part of this publication may be
reproduced, stored in a retrieval system, or transmitted, in any form by any means, electronic, mechanical, by
photocopying, recording, or otherwise without the prior written permission of Measurement Computing
Corporation.
NoticeMeasurement Computing Corporation does not authorize any Measurement Computing Corporation product for
use in life support systems and/or devices without prior written consent from Measurement Computing
Corporation. Life support devices/systems are devices or systems that, a) are intended for surgical implantation
into the body, or b) support or sustain life and whose failure to perform can be reasonably expected to result ininjury. Measurement Computing Corporation products are not designed with the components required, and are
not subject to the testing required to ensure a level of reliability suitable for the treatment and diagnosis ofpeople.

(C) Copyright 2000 Measurement Computing Corp.

HM CIO-DAS800.lwp

ii

TABLE OF CONTENTS

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 INSTALLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1 SOFTWARE INSTALLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.2 HARDWARE INSTALLATION.............................................. 1
2.3 INTERRUPT LEVEL SELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 CONNECTOR DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 OPERATIONAL ASPECTS - CIO-DAS800 VS CIO-DAS08..................... 5
4.1 Conversion Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.2 IMPROVED CHANNEL SEQUENCER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.3 CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.4 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.5 FIFO HALF-FULL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.6 WAIT STATE JUMPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.7 REFERENCE VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.8 SINGLE-ENDED ANALOG INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.9 DIGITAL OUTPUTS & INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.10 COUNTER TIMER CIRCUIT............................................... 7
5 REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

iii

This page intentionally left blank.

iv

1 INTRODUCTION
The primary function of the board is to accept up to eight analog voltages and convert them to digital
equivalents for transmission to an ISA-bus computer. The inputs circuits are single-ended and accept
voltages in a +/-5V range. The board has a resolution of 12 bits (1 in 4096) and a maximum sampling rateof 50 kHz when using the built-in 256-sample FIFO buffer.
The board also contains three 16-bit down-counters.
There are seven bits of digital I/O (3-input, 4-output) that are typically used to control external channel
expansion and signal conditioning boards.

2 INSTALLATION
2.1 SOFTWARE INSTALLATION
Before you open your computer and install the board, install and run InstaCal™, the installation,
calibration and test utility included with your board. InstaCal™ will guide you through switch andjumper settings for your board. Detailed information regarding these settings can be found below. Pleaserefer to the Software Installation Manual for InstaCal™ installation instructions.

2.2 HARDWARE INSTALLATIONThe CIO-DAS800 board is an extension of the popular CIO-DAS08 architecture. The CIO-DAS800 has
a set of registers identical to the CIO-DAS08, and an additional set of registers for the extended
functions. Software written for the DAS08 will work without modification, but will not provide accessto the extended functions. The connector is nearly identical to the CIO-DAS08. There are two jumpers
and a switch that should be set before installing the CIO-DAS800 into your computer.

2.2.1 BASE ADDRESSThe base address of the CIO-DAS800 is set by switching a bank of DIP switches on the board. This bankof switches is labeled ADDRESS and numbered 9 to 3.
Ignore the word ON and the numbers printed on the switch
The switch works by adding up the weights of individual switches to make a base address. A 'weight' isactive when the switch is down. As shown in Figure 2-1, switches 9 and 8 are down, all others are up.

1

Weights 200h and 100h are active, totalling a 300h base address. Table 2-1 lists PC I/O addresses andtheir uses.

Figure 2-1. Base Address Switches
Table 2-1. PC I/O Addresses
HEX
RANGE
000-00F
020-021040-043060-063060-064070-071080-08F
0A0-0A1
0A0-0AF
0C0-0DF
0F0-0FF
1F0-1FF
200-20F
210-21F
238-23B
23C-23F
270-27F
2B0-2BF

FUNCTION
8237 DMA #1
8259 PIC #1
8253 TIMER
8255 PPI (XT)8742 CONTROLLER (AT)
CMOS RAM & NMI MASK (AT)DMA PAGE REGISTERS
8259 PIC #2 (AT)NMI MASK (XT)8237 #2 (AT)80287 NUMERIC CO-P (AT)HARD DISK (AT)GAME CONTROLEXPANSION UNIT (XT)BUS MOUSEALT BUS MOUSEPARALLEL PRINTER
EGA

HEX
RANGE
2C0-2CF
2D0-2DF
2E0-2E7
2E8-2EF
2F8-2FF
300-30F
310-31F
320-32F
378-37F
380-38F
3A0-3AF
3B0-3BB
3BC-3BF
3C0-3CF
3D0-3DF
3E8-3EF
3F0-3F7
3F8-3FFFUNCTION
EGA
EGA
GPIB (AT)SERIAL PORTSERIAL PORTPROTOTYPE CARD
PROTOTTYPE CARD
HARD DISK (XT)
PARALLEL PRINTER
SDLC
SDLC
MDA
PARALLEL PRINTEREGACGASERIAL PORTFLOPPY DISKSERIAL PORT

2.2.2 INTERRUPT LEVEL SELECT
The interrupt jumper need only be set if the software you are using
requires it. The Universal Library and other programs which takeadvantage of the REP-INSW high speed transfer capability of theboard require an interrupt. If you do set the interrupt jumper, pleasecheck your PC's current configuration for interrupt conflicts.
There is a jumper block on the CIO-DAS800 located just above thePC bus interface (gold pins). The factory default setting is that nointerrupt level is set. The jumper is in the 'X' position at the factory.
It is shown in Figure 2-2 set for IRQ 5.
Figure 2-2. IRQ Jumper Block2

Table 2-2 lists typical interrupt assignments.
Table 2-2. Typical IRQ Assignments
NAME
NMI
IRQ0
IRQ1
IRQ2

DESCRIPTIONPARITYTIMER
KEYBOARD
RESERVED (XT)

NAME
IRQ8
IRQ9
IRQ10
IRQ11

DESCRIPTIONREAL TIME CLOCK (AT)RE-DIRECTED TO IRQ2 (AT)UNASSIGNEDUNASSIGNED

IRQ3
IRQ4
IRQ5
IRQ6
IRQ7

INT 8-15 (AT)COM OR SDLCCOM OR SDLC
HARD DISK (XT) LPT (AT)FLOPPY DISK
LPT

IRQ12
UNASSIGNED
IRQ1380287 NUMERIC CO-P
IRQ14
HARD DISKIRQ15UNASSIGNED
Note: IRQ8-15 are AT only

2.2.3 WAIT STATE
A wait state can be enabled on the CIO-DAS800 by selecting WAIT STATE ON at the jumper provided
on the board. Enabling the wait state causes the personal computer's bus transfer rate to slow down
whenever the CIO-DAS800 is written to or read from. The wait state jumper is provided in case you one
day own a personal computer with an I/O bus transfer rate which is too fast for the CIO-DAS800. If yourboard fails sporadically in random ways, try setting the wait state ON.

2.2.4 INSTALLING THE CIO-DAS800 IN THE COMPUTER
1. Turn the power off.
2. Remove the cover of your computer. Please be careful not to dislodge any of the cables installedon the boards in your computer as you slide the cover off.
3. Locate an empty expansion slot in your computer.
4. Push the board firmly down into the expansion bus connector. If it is not seated fully it may failto work and could short circuit the PC bus power onto a PC bus signal. This could damage themotherboard in your PC as well as the board.
5. Power up your computer and run the InstaCal test to verify your hardware installation.

33 CONNECTOR DIAGRAM
The CIO-DAS800 analog connector is a 37-pin, D-type connector accessible from the rear of the PC
through the expansion backplate (Figure 3-1). The connector accepts female 37-pin D-type connectors,
such as those on the C37FF-2, a 2-foot cable with connectors.
If frequent changes to signal connections or signal conditioning is required, please refer to theinformation on the CIO-TERMINAL and CIO-MINI37 screw terminal boards, CIO-EXP32, 32 channel
analog MUX/AMP. Isolation amplifiers can be mounted using the ISO-RACK08 and 5B isolation
modules.

Figure 3-1. Analog Connector
WARNING - PLEASE READ
Measure the voltage between the ground signal at the signal source and the PC. Use ahigh input impedance voltmeter. If there more the 10 volts, do not connect the
CIO-DAS800 to this signal source because you will not be able to make a reading. If thedifference is more than 30 volts, DO NOT connect this signal to the CIO-DAS800
because IT WILL DAMAGE the board and possibly the computer.

44 OPERATIONAL ASPECTS - CIO-DAS800 VS. CIO-DAS08
4.1 CONVERSION TRIGGER
A trigger is the event that begins an acquisition/transfer cycle. There are three ways to trigger a
CIO-DAS800; software, interrupt service routine or hardware. The hardware trigger is a new feature on
the CIO-DAS800, not found on the other DAS08 family boards. This new, improved trigger allows theboard to run much faster than the other DAS08 boards.
Briefly, there are three methods to trigger a data conversion:
A software trigger starts an A/D conversion when an addressed port is written to. This is how a single
sample may be taken.
An interrupt service routine is a set of instructions executed by the computer when an interrupt isreceived. The source of the interrupt is the IR input pin. The signal on the IR input pin is routed to the
PC bus via the interrupt jumper on the CIO-DAS800. The event that causes the interrupt may be theinternal 82C54 counter or an external event.
The hardware trigger is a direct input to the A/D chip's start conversion pin. When the trigger isreceived, the A/D starts a conversion. When the conversion is complete, the data is transferred to the
FIFO buffer. The source for the hardware trigger can be the 82C54 counter/pacer or an external event.
A trigger is useful for synchronizing samples to a known time base, such as the on board 82C54
programmable divider. Using an external trigger allows you to synchronize samples to an external event.

4.2

IMPROVED CHANNEL SEQUENCER

When the acquisition strategy you set up requires a scan of data from multiple channels, the channel
sequencer controls the internal multiplexer that routes the signal to the A/D. The DAS08 family employsa register that must be written to each time the mux is incremented.
The improved hardware channel sequencer on the CIO-DAS800 is set up, then takes over control of theinternal multiplexer, freeing the CPU from that task. This gives faster sampling.

4.3

CONTROL REGISTERS

The CIO-DAS800 is compatible with DAS08 software because the basic I/O register have identical
functions on each board. I/O registers are the locations which the computer writes commands and data to
and reads status and data from. Table 1-1 is a summary of board registers. The register at BASE+2 is amulti-function register. It and the others are described in the register section of this manual.
Table 1-1. Register Summary
I/O ADDRESSBASE + 0
BASE + 1
BASE + 2
BASE + 3

FUNCTION Read/ Write
A/D Low Byte / Start Conv A/DA/D High Byte / Start Conv A/DSpecial Multi-Functions Register
Gain & Range Control / Status
5

BASE + 4
BASE + 5
BASE + 6
BASE + 7

Read Counter 0/ Load Counter 0
Read Counter 1 / Load Counter 1
Read Counter 2 / Load Counter 2
Status & ID / Counter Control

4.4 FIFO
The FIFO buffer is 256 bytes deep. A larger FIFO makes higher throughput of A/D conversions possible.
This is important when running Windows, and will be more important in future versions of that OS. This
does not affect compatibility in any way because it is a hardware-only function and is transparent to thesoftware.

4.5

FIFO HALF-FULL INTERRUPTIn addition to a larger FIFO, the CIO-DAS800 has a 1/2-full interrupt. This means that a transfer request
is made after the CIO-DAS800 accumulates 128 samples instead of after every sample. This greatly
improves throughput. This does not affect compatibility with other similar boards in any way because it
is a hardware function and is transparent to the software.

4.6

WAIT STATE JUMPER

Adding this jumper causes a wait state to be inserted into each CPU cycle whenever the CIO-DAS800 isaccessed. This may be necessary on machines with very fast ISA busses, but the need for the wait state isvery rare. This jumper does not affect compatibility in any way because it is a hardware function and istransparent to the software.

4.7

REFERENCE VOLTAGE

The CIO-DAS800 A/D converter, an AD674, provides a precision 10V reference.

6

4.8

SINGLE-ENDED ANALOG INPUTS

The board accepts single-ended inputs only. Each input has two wires connected to the CIO-DAS800; achannel high (CH# HI) and a Low Level Ground (LLGND). The LLGND signal must be the sameground the PC is on. The CH# HI is the voltage signal source in the range of +/-5V maximum.

4.9

DIGITAL OUTPUTS & INPUTS

The digital inputs and outputs on the CIO-DAS800 are TTL level. TTL is an electronics industry term,
short for Transistor Transistor Logic, which describes a standard for digital signals. For a listing of the
TTL level specifications for these digital lines, please see the specifications at the end of this manual.

There are three digital inputs and four digital outputs. The digital outputs are controlled by a register on
the board and are updated each time the register is written to. The digital inputs are buffered by aregister on the board. Each time the register is read, the current high/low state of the digital I/O lines isobtained. The lines are pulled high so a one (1) is read when no signal is connected to an input

Typically, the digital lines are used to control external expansion boards (all four outputs) and to trigger
and gate A/D conversions (IP0 input).

4.10 COUNTER TIMER CIRCUIT
There is an 82C54 counter/timer on the board which can be used to:yPace analog conversionsyMeasure frequencyyCount eventsyPrecisely time intervals

The Universal Library has software to support the timer. The connections to the hardware are explained
here. For detailed information on the 82C54 registers, please refer to the Intel or AMD data sheet for thispart if you wish to program the 82C54 registers directly.
The 82C54 contains three counters, each is 16 bits wide. Of the three counters, two are dedicated topacing analo-to-digital conversions. These two, CTR1 and CTR2, when not in use by the A/D, areavailable for other tasks but are limited to some extent by access to I/O pins. The first counter, CTR0, isavailable for user applications.

7

+ 5V D C
A LL
1 0K

C TR 0 O U T

2

3

OUT 0

C LK 0G AT E 0
G AT E 1

22

C TR 1 O U T
OUT 1C LK 1

5

8 2C 54

4
G AT E 2
1 0 M H Z C RY S TA LO S C IL L ATO R

D IV ID E B Y
10C TR 2OUTOUT 2C LK 2

6

CASCADECONTROLL O G ICS TA R T C O N V E R T

PA C E R
CONTROLLO G ICD IN 1/T R IG25
IN T IN P U T /XCLK24Figure 1-1. Counter/Timer Functional Diagram
Figure 1-1 shows the 82C54 functions, I/O pins and how these are connected on the CIO-DAS800.
The CIO-DAS800 CTR2 input is connected to the PC bus clock/2 or the 1 MHz. crystal signal. The
system default is the PC bus clock.
Software controls the counters that generate the A/D pacing pulse.
Note: A/D conversions are triggered by falling-edge signals. The pulses generated by the 82C54 are
low-going for one count length. The A/D is triggered as the signal goes low. Any A/D trigger signal you
supply externally must also be low-going at the desired moment of A/D conversion.

8

5 REGISTER MAP
Tables 4-1 and 4-2 contain the write and read functions of the board’s registers. Table 4-3 defines thefunctions of each bit.
Note that the register at BASE + 2 is a multi-function register. Its function is set by bits CS0 and CS1 in
BASE + 3 register. Coding for Base + 02 register functions is contained in Table 4-4.
Table 4-5 gives the Gain Select codes for the CIO-DAS800.
NOTE: ONLY +/-5V IS SUPPORTED.
Table 4-6 provides special programming instructions.

Table 4-1. Register Map - Write Functions
WRITE
Functions

Data Bits
D7

D6

D5

D4

Function
D3

D2

D1

D0

Base + 0

Start Conversion*

Base + 1

Start Conversion*Special Function - (Depends on value of

Base + 2
CS1/0=0/0

OP4

OP3

CS0,1)
OP2

OP1

INTE

MA2

MA1

MA0

Control Register 1

CS1/0=0/1

HCEN

NA

GTEN

EACS

IEOC

DTEN

CASC

ITE

Conversion Control

CS1/0=1/0

NA

NA

EC2

EC1

EC0

SC2

SC1

SC0

Scan Limits Register

Base + 3

CSE

CS1

CS0

ENHF

R3

R2

R1

R0

Control SelectBase + 4

8254 C/T 0 Control Register

Base + 58254 C/T 1 Control Register

A/D Timer

Base + 6

8254 C/T 2 Control Register

Cascade Pre-scaler

Base + 7

8254 Counter/Timer Control Register

Register* Writing (anything) to either BASE + 0 or BASE + 1 starts a conversion.

9

Table 4-2. Register Map - Read Functions
READ

Data Bits

Functions

Function

RegisterBase + 0

D7
AD3

D6
AD2

D5
AD1

D4
AD0

D3
FF3

D2
FF2

D1
FFOV

D0
FFEM Low byte read

Base + 1

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

High byte read

Base + 2

EOC

IP3

IP2

IP1

IRQ

MA2

MA1

MA0

Status Register 1

Base + 3

EACS

MA2

MA1

MA0

R3

R2

R1

R0

Control Status

Base + 4

8254 C/T 0 Status Register

Base + 58254 C/T 1 Status Register

Base + 6

8254 C/T 2 Status Register

Base + 7

Function depends on value of CS0/1 bits in Base +3:

CS1/0=
0/0,0/1,1/0
CS1/0 = 1/1

HCEN

GTEN

INTE

IEOC

DT

DTEN

CASC

ITE

Status Register 2

ID7

ID6

ID5

ID4

ID3

ID2

ID1

ID0

ID Reg (ID1,0 = 0/0)

10

Table 4-3. Bit Definitions
DEFINITIONS:R
AD 11:0
RW
MA2:0
RW
INTE
R
EOC
RW
HCEN
RW
GTEN*
RW
EACS*
RW
IEOC
RW
DTEN*
RW
CASC*
RW
ITE*
W
CSE
W
CS1:0
RW
R3:0
W
ENHF*
DT*
FFEM*
FFOV*
FF2*

R
R
R
R

FF3*

R

SC2:0*
EC2:0*
IP3:1
OP4:1

W
W
R
W

Analog data input (Read low byte first)
Mux address bits
Interrupt enable (0 = disable, 1 = enable)
End-of-conversion (1 = busy, 0 = ready)
Hardware Convert Enable
Gate Enable (Req. DTEN to enable HW gate)
Enable Auto channel-scan
Interrupt Source (1 = End of Convert, 0 = Ext)
External Digital Trigger Enable (Edge trig if GTEN=0)
Cascade AD Pacing Mode Enable (include CT/2)
Internal Time Base (8254) Enable
Register Select Enable/Range Select Disable
Register Selection (See Table Below)(N/A)
Enable Interrupt on FIFO Half Full (Req. IEOC=1, HCEN must =1 to enable
FIFO)
State of Digital Trigger (1=Trigger occured)
FIFO Empty =1. 0 if HCEN =0.
FIFO Overflow (full) =1. 0 if HCEN =0.
0 if HCEN =0. 0 if HCEN =1 & FIFO not empty. Undefined if HCEN = 1 and FIFO
empty
0 if HCEN =0. 0 if HCEN =1 & FIFO not empty. Undefined if HCEN = 1 and FIFO
empty
Channel-scan start value.
Channel-scan end value
Digital Input bits.
Digital Output bits.

* Asterisk indicates that HCEN is required (as a final step) to makethis bit functional.

11

Table 4-4. Coding for Base + 02 Register Functions
CS1
0
0
1
1

CS0
0
1
0
1

Control Register Selected
Write Function
Read Function
Control Reg # 1
Status Register #2
Conversion Control Status Register #2
Scan Limits Reg
Status Register #2
Not defined
ID Register

Table 4-5. Special Programming Instructions
Special Programming instructions
RegisterConv/Control HCEN is used as a master enable for AD Pacing
Set HCEN last, by itself (ie write 80h) , set the other bits first
Scan Limits

Ending channel (n) can be lower than starting channel (m) :Select Start and End Channel before setting EACS

m,...,6,7,0,1,...,n,m...

ID

Only the 1st two bits are needed for software, the upper six are for compatibility with KMB
software
ID 1/0: 0/0= (DAS800], 0/1= reserved, 1/0= N/A, 1/1= N/A)

Gain/Range

Not appplicable.

Operatingmodes
PacingNormal CT/2 divides the 1MHz timebase; AD converts when CT/2 counts to zeroCascade CT/1 decrements each time CT/2 counts to zero; AD converts when CT/1 counts
to zeroTriggering
Gating

Edge
Level

Bit
INT/XCLK

Requires DTEN=1, GTEN=0"Gate", Requires DTEN=1, GTEN=0

External Interrupt and External (Pacer) Clock are mutually exclusive
External Interrupt is rising edge, External Pacer is falling edge

12

6 SPECIFICATIONSPower consumption+5V quiescent
Analog input section
A/D converter type
Resolution
Number of channels
Input Ranges
Polarity
A/D pacing

450 mA typical, 600 mA max

A/D Trigger sources
Data transfer

AD674A, Successive Approximation
12 bits
8±5V fixed
Bipolar fixed
Programmable: internal counter or external source (IR Input/ XCLK, falling edge) or software polled
External hardware (Digital In 1 / Trig, rising edge)
Interrupt or software polled from 256 sample FIFO buffer

Channel configuration
DMA
A/D conversion timeThroughput

Single-ended
None
20 µs
50 kHzAccuracy
Differential Linearity error
Integral Linearity error
No missing codes (guaranteed)±0.01% of full scale ±1 LSB typ, ±0.05% of full scale ±1
LSB max±0.5 LSB max±1 LSB
12 bits

Gain drift (A/D specs)
Zero drift (A/D specs)±50 ppm/°C±10 ppm/°C

Common Mode Range±10V
CMRR @ 60 Hz
70 dB min
Input leakage current (@ 25 deg C)± 30 nA
Input leakage current (over temperature)±250 nA
Input impedance>1000 Mohm typicalAbsolute maximum input voltage
±35V

13

Counter section
Counter type
Configuration

82C54
3 down-counters , 16 bit resolution
Counter 0 - independent user counter
Source:external, user connector (Counter 0 In)
Gate:
external, user connector (Gate 0)
Output:user connector (Counter 0 Out)Counter 1 - ADC Pacer Lower Divider or independent user counter
Source:user connector (Counter 1 In) and optionally,
Counter 2 Out, selectable by software
Gate: Programmable, disabled or user connector (Gate 1)
Output: User connector (Counter 1 Out) and optionally to A/D
start convert, software selectable
Counter 2 - ADC Pacer Upper Divider
Source: Internal 1 MHz oscillator
Gate: Programmable, disabled or user connector (Gate 2)
Output: User connector (Counter 2 Out) and optionally tocounter 1 input, software selectable
Clock input frequency
10 MHz max
High pulse width (clock input)
30 ns minLow pulse width (clock input)
50 ns minGate width high50 ns minGate width low
50 ns min
Input low voltage
0.8V max
Input high voltage
2.0V minOutput low voltage
0.4V max
Output high voltage
3.0V minCrystal oscillator
Frequency
1 MHz
Frequency accuracy
100 ppm

Digital I/O section
Digital type
FPGA
Configuration
Two ports, 3 input and 4 output
Input low voltage
0.8V max
Input high voltage
2.0V minOutput low voltage (IOL = 4 mA) 0.32V max
Output high voltage (IOH = −4 mA) 3.86V min
Absolute maximum input voltage −0.5V , +5.5V
Interrupts
Interrupt enable:
Interrupt sources:

Jumper selectable: levels 2, 3, 4, 5, 6, 7 or not connected
Positive-edge triggered
Programmable
External (IR Input / XCLK), A/D End-of-conversion, A/D FIFO Half-Full

Environmental
Operating temperature range
Storage temperature range
Humidity

0 to 50°C−20 to 70°C
0 to 90% non-condensing
14

EC Declaration of Conformity
We, Measurement Computing Corp., declare under sole responsibility that the product:
CIO-DAS800
Part Number

Analog input board with counters and digital I/O
Description

to which this declaration relates, meets the essential requirements, is in conformity with, and CE marking has been applied according to
the relevant EC Directives listed below using the relevant section of the following EC standards and other normative documents:
EU EMC Directive 89/336/EEC: Essential requirements relating to electromagnetic compatibility.
EU 55022 Class B: Limits and methods of measurements of radio interference characteristics of information technology equipment.
EN 50082-1: EC generic immunity requirements.
IEC 801-2: Electrostatic discharge requirements for industrial process measurement and control equipment.
IEC 801-3: Radiated electromagnetic field requirements for industrial process measurements and control equipment.
IEC 801-4: Electrically fast transients for industrial process measurement and control equipment.

Carl Haapaoja, Director of Quality Assurance

Measurement Computing Corporation
10 Commerce Way
Suite 1008
Norton, Massachusetts 02766(508) 946-5100
Fax: (508) 946-9500
E-mail: info@mccdaq.com
www.mccdaq.com