REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)APPROVEDA

Update boilerplate paragraphs to current VID description requirements.
- PHN

22-06-21

Muhammad A. Akbar

Prepared in accordance with ASME Y14.24

Vendor Item Drawing

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PMIC N/A
Original date of drawing
YY MM DD

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
https://www.dla.mil/LandandMaritime

PREPARED BY
Phu H. Nguyen

TITLE

CHECKED BY
Phu H. Nguyen
APPROVED BY

17-04-25

Thomas M. HessSIZE

CAGE CODE

A

REV A

16236

MICROCIRCUIT, LINEAR-DIGITAL, MIXEDSIGNAL MICROCONTROLLER, MONOLITHIC
SILICONDWG NO.

PAGE

V62/16627

1 OF 49

AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

5962-V036-22

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance Mixed-Signal Microcontroller microcircuit, with
an operating temperature range of -55ºC to +95ºC.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/16627-

Drawing
number01

X

E

Device type(see 1.2.1)

Case outline(see 1.2.2)

Lead finish(see 1.2.3)

1.2.1 Device type(s).
Device type

Generic

Circuit function

01

MSP430FR5989 –EP

Mixed-Signal Microcontroller

1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

X

64

JEDEC MS-026

Package style
Plastic Quad Flat Pack (PQFP) Package

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator

Material

A
B
C
D
E
F
Z

DLA LAND AND MARITIMECOLUMBUS, OHIO

Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy
Other

SIZE
A

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PAGE 2

1.3 Absolute maximum ratings.

1/

Voltage applied at DVCC and AVCC pins to VSS ...................................................................... -0.3 to 4.1 V
Maximum Voltage difference between DVCC and AVCC pins ................................................. ±0.3 V
2/Voltage applied to any pin ........................................................................................................ -0.3 to VCC + 0.3 V (4.1 max)
Maximum Diode current at any device pin ............................................................................... ±2 mA
Storage temperature range ...................................................................................................... -55°C to 125°C 4/
Electrostatic discharge:
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ........................................... ±1000 V 5/
Charged-device model (CDM), per JEDEC specification JESD22-C101 .......................... ± 250 V 6/3/

1.4 Recommended operating conditions. 7/
Supply voltage range applied at all DVCC, AVCC, and ESIDVCC pins (VCC) 8/ 9/ 10/ .......... 1.8 V 11/ to 3.6 V
Supply voltage applied at all DVSS, AVSS, and ESIDVSS pins (VSS) .................................... 0 Nomial
Capacitor value at DVCC and ESIDVCC (CVDCC) 12/ ............................................................1-20% µF
Processor frequency (maximum MCLK frequency) (fSYSTEM) 13/
No FRAM wait states (NWAITSx = 0) ............................................................................... 0 to 8 14/ MHz
With FRAM wait states (NWAITSx = 1) 15/ ....................................................................... 0 to 16 16/ MHz
Maximum ACLK frequency (fACLK) ............................................................................................ 50 kHz
Maximum SMCLK frequency (fSMCLK) ....................................................................................... 16 MHz 16/___________________
1/

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
2/ Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including
erroneous writes to RAM and FRAM.
3/ All voltage values are with respect to VSS, unless otherwise noted.
4/ Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
5/ JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as±1000 V may actually have higher performance.
6/ JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as±250 V may actually have higher performance.
7/ Typical data are based on VCC = 3 V, TJ = 25°C unless otherwise noted.
8/ Manufacturer recommends powering the DVCC, AVCC, and ESIDVCC pins from the same source. At a minimum, during powerup, power down, and device operation, the voltage difference between DVCC, AVCC, and ESIDVCC must not exceed the limits
specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and FRAM.
9/ See TABLE I.00 for additional important information.
10/ Modules may have a different supply voltage range specification. See the specification of each module in this data sheet.
11/ The minimum supply voltage is defined by the supervisor SVS levels. See TABLE I.01 for the exact values.
12/ Connect a low-ESR capacitor with at least the value specified and a maximum tolerance of 20% as close as possible to the DVCC
and ESIDVCC pins.
13/ Modules may have a different maximum input clock specification. See the specification of each module in this data sheet.
14/ DCO settings and HF crystals with a typical value less than or equal to the specified MAX value are permitted.
15/ Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always
executed without wait states.
16/ DCO settings and HF crystals with a typical value less than or equal to the specified MAX value are permitted. If a clock sources
with a llarger typical value is used, the clock must be divided in the clock system.

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PAGE 3

1.5 Thermal Resistance Characteristics.
Thermal metric

17/

Case outline X

Units

Junction to ambient thermal resistance, still air RθJA 18/

29.2

°C/W

Junction to case (top) thermal resistance, RθJCtop 19/

13.9

Junction to board thermal resistance, RθJB 20/

8.1

Junction to top characterization parameter, ΨJT

8.0

Junction to board characterization parameter, ΨJB

0.2

Junction to case (bottom) thermal resistance, RθJCbot

21/

1.0

2. APPLICABLE DOCUMENTSJEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)JEP95–
JESD51-2a–
JESD51-7–
JESD51-8–
JEDEC JS-001 –JEDEC J-STD020
JEP155
JEP157JESD22-C101–––

Registered and Standard Outlines for Semiconductor Devices
Integrated Circuits Thermal Test Method Environment Conditions – Natural Convection (Still Air)High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Integrated Circuits Thermal Test Method Environment Conditions – Junction-to-board
Joint JEDEC/ESDA standard for electrostatic discharge sensitivity test – Human Body Model (HBM)
Standard for moisture/reflow sensitivity classification for nonhermetric solid state surface mountdevices.
For electrostatic discharge sensitivity test Human Body Model (HBM) – component level.
Recommended ESD target levels for HBM/MM qualification.
Recommended ESD-CDM target levels.
Field-Induced Charged-Device Model (FIDCM) Test Method for Electrostatic-Discharge-WithstandThresholds of Microelectronic Components(Copies of these documents are available online at https://www.jedec.org ).
AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD
ANSI SEMI STANDARD G30-88– Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic
Packages(Copies of these documents are available online at https:/www.ansi.org.

___________
17/
18/
19/
20/
21/

For more information about traditional and new thermal metrics, see manufacturer data.
The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-Kboard, as specified in JESD51-7, in an environment described in JESD51-2a.
The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specified
JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the
PCB temperature, as described in JESD51-8.
The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No
specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88

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PAGE 4

3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1

Case outline. The case outline shall be as shown in 1.2.2 and figure 1.

3.5.2

Terminal connections. The terminal connections shall be as shown in figure 2.

3.5.3

Functional block diagram. The functional block diagram shall be as shown in figure 3.

3.5.4

Brownout Power-Down Level vs Supply Voltage Down Slope. The Brownout Power-Down Level vs Supply Voltage Down
Slope shall be as shown in figure 4.

3.5.5

Average LPM Currents vs Wake-Up Frequency at 25°C. The Average LPM Currents vs Wake-Up Frequency at 25°C shallbe as shown in figure 5.

3.5.6

Average LPM Currents vs Wake-Up Frequency at 85°C. The Average LPM Currents vs Wake-Up Frequency at 85°C shallbe as shown in figure 6.

3.5.7

SPI Master Mode, CKPH = 0. The SPI Master Mode, CKPH = 0 shall be as shown in figure 7.

3.5.8

SPI Master Mode, CKPH = 1. The SPI Master Mode, CKPH = 1 shall be as shown in figure 8.

3.5.9

SPI Slave Mode, CKPH = 0. The SPI Slave Mode, CKPH = 0 shall be as shown in figure 9.

3.5.10SPI Slave Mode, CKPH = 1. The SPI Slave Mode, CKPH = 1 shall be as shown in figure 10.

3.5.11I2C Mode Timing. The I2C Mode Timing shall be as shown in figure 11.

3.5.12

Typical Temperature Sensor Voltage. The Typical Temperature Sensor Voltage shall be as shown in figure 12.

3.5.13P6.x/ESICHx Timing, ESICHx Function Selected. The P6.x/ESICHx Timing, ESICHx Function Selected shall be as shownin figure 13.

3.5.14

Voltage Drop Due to ON-Resistance. The Voltage Drop Due to ON-Resistance shall be as shown in figure 14.

3.5.15

Typical Active Mode Supply Currents, No Wait States. The Typical Active Mode Supply Currents, No Wait States shall be
as shown in figure 15.

3.5.16

LPM3 Supply Current vs Temperature (LPM3, XT3.7). The LPM3 Supply Current vs Temperature (LPM3, XT3.7) shall be
as shown in figure 16.

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PAGE 5TABLE I. Electrical performance characteristics. 1/
Test

EXECUTIONMEMORY

VCC

Frequency(fMCLK =fSMCLK)

Unit

1 MHz
4 MHz
8 MHz
12 MHz16 MHz0 WAIT
0 WAIT
0 WAIT
1 WAIT
1 WAIT
STATES
STATES
STATESSTATESTATE(NWAITSx = 0) (NWAITSx = 0) (NWAITSx = 0) (NWAITSx = 1) (NWAITSx = 1)

TYP MAX TYPMAX
TYP MAXTABLE I.a0 Active Mode Supply Current Into VCC Excluding External Current
over recommended operating junction temperature (unless otherwise noted) 97/ 98/
IAM, FRAM_UNI
FRAM
3.0 V
210
640
1220
(Unifiedmemory) 99/
FRAM
IAM, FRAM(0%)
3.0 V
375
1290
2525
0% cache hit
100/ 101/
ratio
FRAM
IAM, FRAM(50%)
3.0 V
240
745
1440
50% cache hit
100/ 101/
ratio
FRAM
IAM, FRAM(66%)
3.0 V
200
560
1070
66% cache hit
100/ 101/
ratio
FRAM
IAM, FRAM(75%)
3.0 V
170
255
480
890 1085
75% cache hit
100/ 101/
ratio
FRAM
IAM, FRAM(100%)
3.0 V
110
235
420
100% cache100/ 101/
hit
ratio

TYP

640

730

µA

IAM, RAM101/ 102/

RAM

3.0 V

130

µA

IAM, RAM101/ 103/

RAM

3.0 V

100

180

MAX

TYP

MAX

1475

1845

µA

2100

2675

µA

1575

1990

µA

1300

1620

µA

1155

1310

1420

320

585

890

1070

290

555

860

1040

1620

1300

See footnote at end of table.

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TABLE I. Electrical performance characteristics - Continued. 1/
Test

Frequency (fMCLK = fSMCLK)

VCC
1 MHz

4 MHz

Unit

8 MHz

12 MHz16 MHz

TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
TABLE I.a1 Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
over recommended operating junction temperature (unless otherwise noted) 104/ 105/
ILPM0
ILPM1

2.2 V

75

3.0 V

85

2.2 V

40

3.0 V

40

120
65

105

165

250

230

115

175

260

240

65

130

215

195

65

130

215

195

MAX

µA
275
220

See footnote at end of table.

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TABLE I. Electrical performance characteristics - Continued. 1/
SymbolVCC

TEM PERATURE
–55°C

25°C

(TJ)

60°C

Unit
95°C

TYP MAX TYPMAX
TYP MAX TYPTABLE I.a2 Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
106/
Low-power mode 2, 12-pF
ILPM2,XT12
2.2 V
0.6
1.2
3.1
8.8
crystal 107/ 108/ 109/

Low-power mode 2, 3.7-pF
crystal 107/ 109/ 110/
Low-power mode 2, VLO,
includes SVS 111/
Low-power mode 3, 12-pF

ILPM2,XT3.7
ILPM2,VLO
ILPM3,XT12

crystal, excludes SVS 107/108/ 112/
Low-power mode 3, 3.7-pF
crystal, excludes SVS 107/
110/ 113/ (also see FIGURE 16)

ILPM3,XT3.7

Low-power mode 3,

ILPM3,VLO

VLO, excludes SVS 114/
Low-power mode 3,
VLO, excludes SVS, RAM
powered-down completely 115/
Low-power mode 4, includes

ILPM3,VLO,

ILPM4,SVS

Low-power mode 4, excludes

ILPM4

SVS
SVS, RAM powered-down
completely
Additional idle current if one ormore modules from Group A(see TABLE I.a6) are activatedin LPM3 or LPM4Additional idle current if one ormore modules from Group B(see TABLE I.a6) are activatedin LPM3 or LPM4Additional idle current if one ormore modules from Group C(see TABLE I.a6) are activatedin LPM3 or LPM4Additional idle current if one ormore modules from Group D(see TABLE I.a6) are activatedin LPM3 or LPM4

0.6

1.2

2.2 V

0.5

3.0 V

0.5

2.2 V

0.3

0.9

3.0 V

0.3

0.9

2.2

3.1

8.8

1.1

3.0

8.7

1.1

3.0

8.7

2,8

8.5

2.0

2.8

8.5

1.2

2.5

1.0

1.2

2.5

2.2 V

0.5

0.7

3.0 V

0.5

0.7

2.2 V

0.4

0.6

1.1

2.4

3.0 V

0.4

0.6

1.1

2.4

2.2 V

0.3

0.4

0.9

2.2

3.0 V

0.3

0.4

2.2 V

0.3

0.4

3.0 V

0.3

0.4

2.2 V

0.4

0.5

3.0 V

0.4

0.5

2.2 V

0.2

0.3

3.0 V

0.2

0.3

2.2 V

0.2

0.3

3.0 V

0.2

0.3

0.8

µA
20.8

20.5
6.4

0.9

2.2

0.8

2.1

6.1

0.8

2.1

0.9

2.3

0.9

2.3

0.7

2.0

0.6

0.7

2.0

0.7

1.9

0.6

0.7

1.9

5.1

RAMoffSVS

Low-power mode 4, excludes

3.0 V

MAX

ILPM4,RAMoff

0.7
0.8

5.2
6.2
6.0

IIDLE,GroupA

3.0 V

0.02

1.18

2.6

IIDLE,GroupB

3.0 V

0.02

1.15

2.6

IIDLE,GroupC

3.0 V

0.02

1.5

2.8

IIDLE,GroupD

3.0 V

0.015

1.4

2.4

See footnote at end of table.

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PAGE 8TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolVCC

T EMPERATUR
–55°C

(TJ)

25°C

Unit
60°C

TYP MAX TYPMAX
TYP MAXTABLE I.a3 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
ILPM3,XT12
Low-power mode 3 (LPM3)
3.0 V
0.7
0.9
1.5
LCD,
current,12-pF crystal, LCD 4- mux
ext. biasmode, external biasing, excludes
SVS 119/ 120/
Low-power mode 3 (LPM3) current,
ILPM3,XT12
3.0 V
2.0
2.2
2.9
2.8
12-pF crystal, LCD 4- mux mode,
LCD,
internal biasing, charge pumpint. bias
disabled, excludes SVS 119/
121/
Low-power mode 3 (LPM3)
5.0
5.2
5.8
2.2 V
current,12-pF crystal, LCD 4ILPM3,XT12
mux mode, internal biasing,
LCD,CPcharge pump enabled, 1/3 bias,
3.0 V
4.5
4.7
5.3
excludes SVS 119/ 122/

95°C
TYP

MAX

3.1

4.4

µA

9.3

7.4

6.9

TABLE I.a4 Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) 123/
Low-power mode 3.5, 12-pF
ILPM3.5,XT12
2.2 V
0.4
0.45
0.55
0.75
crystal including SVS(2) 124/
125/ 126/
Low-power mode 3.5, 3.7-pF
crystal excluding SVS 124/ 127/
128/
Low-power mode 4.5, including SVS
129/

ILPM3.5,XT3.7

ILPM4.5,SVS

Low-power mode 4.5, excluding
SVS 130/

ILPM4.5

3.0 V

0.4

0.45

2.2 V

0.3

3.0 V

0.7

0.55

0.75

0.35

0.4

0.65

0.3

0.35

0.4

0.65

2.2 V

0.2

0.2

0.25

0.35

3.0 V

0.2

0.2

0.25

0.35

2.2 V

0.02

0.02

0.03

0.14

3.0 V

0.02

0.02

0.03

0.13

0.4

µA
1.6

0.7

0.5

See footnote at end of table.

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PAGE 9TABLE I. Electrical performance characteristics - Continued. 1/
MODULETABLE I.a5

TEST CONDITIONSREFERENCE
CLOCK

Typical Characteristics, Current Consumption per Module

MIN

TYP

MAX

UNIT

131/

Timer_A

Module input clock3

μA/MHzTimer_B

Module input clock

5

μA/MHzeUSCI_AUART mode

Module input clock

5.5

μA/MHzeUSCI_A

SPI mode

Module input clock

3.5

μA/MHzeUSCI_B

SPI mode

Module input clock

3.5

μA/MHzeUSCI_B

I2C mode, 100 kbaud

Module input clock

3.5

μA/MHz

RTC_C

32 MHz

100

nA

MPY

Only from start to end of operation

MCLK

25

μA/MHzAES

Only from start to end of operation

MCLK

21

μA/MHz

CRC16

Only from start to end of operation

MCLK

2.5

μA/MHz

CRC32

Only from start to end of operation

MCLK

2.5

μA/MHzSee footnote at end of table.

TABLE I.a6

Peripheral Groups

GROUP AGROUP BGROUP CGROUP D

Timer TA0

Timer TA1
Extended Scan Interface (ESI)

Timer TA2

Timer TA3

Timer B0

LCD_C

ADC12_B

eUSCI_A0

eUSCI_A1

REF_A

eUSCI_B0

Comparator

USCI_B1

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TABLE I. Electrical performance characteristics - Continued. 1/

Test

SymbolTest conditions
2/

TABLE I.b00

Min

VVCC_BOR–

Brownout power-up level 4/

VVCC_BOR+Max| dDVCC/dt | < 3 V/s

5/

0.7

| dDVCC/dt | > 300 V/s 5/0| dDVCC/dt | < 3 V/s 6/

0.79

1.66

V

1.68

SVS

SVSH current consumption, lowpower modes
SVSH power-down level
SVSH power-up level
SVSH hysteresis
SVSH propagation delay, activemode
TABLE I.b02 Reset Input

ISVSH,LPM
VSVSHVSVSH+
VSVSH_hys
tPD,SVSH,

1.74
1.76
40
dVVcc/dt = –10 mV/μs

170

300

nA

1.81
1.88

1.86
1.99
120

V
V
mV
µs

10

AM

External reset pulse duration on
�����
RST
7/

TABLE I.b03

Typ

Unit

Power ramp requirements

Brownout power-down level 3/ 4/

TABLE I.b01

LimitsVCC

2.2 V,
3.0 V

2

µs

Low-Frequency Crystal Oscillator, LFXT 8/

Current consumption

LFXT oscillator crystal frequency
LFXT oscillator duty cycle
LFXT oscillator logic-levelsquare-wave input frequency
LFXT oscillator logic-levelsquare-wave input duty cycle
Oscillation allowance for LF
crystals
11/

fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},TJ = 25°C, CL,eff = 3.7 pF, ESR ≈ 44 kΩ

3.0 V

180

3.0 V

185

3.0 V

225

3.0 V

330

fLFXT
DCLFXT

fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {1},TJ = 25°C, CL,eff = 6 pF, ESR ≈ 40 kΩ
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {2},TJ = 25°C, CL,eff = 9 pF, ESR ≈ 40 kΩ
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},TJ = 25°C, CL,eff = 12.5 pF, ESR ≈ 40 kΩ
LFXTBYPASS = 0
Measured at ACLK, fLFXT = 32768 Hz

fLFXT,SWLFXTBYPASS = 1 9/

DCLFXT,LFXTBYPASS = 1

IVCC.LFXT

SW

10/

32768
30%
10.5

Integrated load capacitance at
LFXIN terminal
12/ 13/Integrated load capacitance at
LFXOUT terminal 12/ 13/Hz70%

32.76830%

LFXTBYPASS = 0, LFXTDRIVE = {1},fLFXT = 32768 Hz, CL,eff = 6 pF
LFXTBYPASS = 0, LFXTDRIVE = {3},fLFXT = 32768 Hz, CL,eff = 12.5 pF

nA

50

kHz

70%

kQ

210
300
2

pF

2

pF

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/16627
PAGE 11TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

Limits

VCC

2/

Min

Low-Frequency Crystal Oscillator, LFXT – Continued.
8/fOSC = 32768 Hz,
tSTART,LFXT LFXTBYPASS = 0, LFXTDRIVE = {0},Start-up time 14/
TJ = 25°C, CL,eff = 3.7 pF
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},TJ = 25°C, CL,eff = 12.5 pF
Oscillator fault
fFault,LFXT
frequency 15/ 16/

Typ

Unit
Max

TABLE I.b03

3.0 V

800

3.0 V

1000
0

High-Frequency Crystal Oscillator, HFXT 17/
fOSC = 4 MHz,HFXTBYPASS =0, HFXTDRIVE =0, HFFREQ =1 18/
TJ = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
HFXT oscillator crystal
IDVCC.HFX fOSC = 8 MHz,
current HF mode at
HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 1,Ttypical ESR
TJ = 25°C, CL,eff = 18 pF, Typical ESR, Cshun
fOSC = 16 MHz,HFXTBYPASS = 0, HFXTDRIVE = 2, HFFREQ = 2,
TJ = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
fOSC = 24 MHz,HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3,
TJ = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
HFXT oscillator crystal
fHFXT
HFXTBYPASS = 0, HFFREQ = 1 18/ 20/
frequency, crystal mode
HFXTBYPASS = 0, HFFREQ = 2
19/
HFXTBYPASS = 0, HFFREQ = 3
19/
HFXT oscillator duty
DCHFXT
Measured at SMCLK, fHFXT = 16 MHz
cycle
HFXT oscillator logic
HFXTBYPASS = 1, HFFREQ = 0 19/ 20/level square- wave
fHFXT,SWHFXTBYPASS = 1, HFFREQ = 1 19/ 20/
input frequency,
HFXTBYPASS = 1, HFFREQ = 2 19/ 20/
bypass mode
HFXTBYPASS = 1, HFFREQ = 3 19/ 20/
HFXT oscillator logic
DCHFXT,HFXTBYPASS = 1
level square-wave inputSW
duty cycle
fOSC = 4 MHz,
Start-up time 21/
tSTART,HF HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 1,
TJ = 25°C, CL,eff = 16 pF
XT
fOSC = 24 MHz ,HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3,
TJ = 25°C, CL,eff = 16 pF
Integrated load
capacitance at HFXIN
terminaI 22/ 23/

ms

3500

Hz

TABLE I.b04

Integrated load
capacitance at HFXOUT
terminaI 22/ 23/
Oscillator fault
frequency 24/ 25/

3.0 V

75

µA

120
190
250
4
8.01
16.01
40%

50%

0.9
4.01
8.01
16.01
40%

8
16
24
60%

MHz

4
8
16
24
60%

MHz

1.6

0.6
2

2

fFault,HFXT

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

ms

DWG NO.
V62/16627
PAGE 12pF

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions
2/

TABLE I.b05

Limits

VCC
Min

Unit

Typ

Max

DCO

DCO frequency range 1 MHz,
trimmedfDCO1

Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 0,
DCORSEL = 1, DCOFSEL = 0

1

±3.5%

DCO frequency range 2.7 MHz,
trimmedfDCO2.7

Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 1

2.667

±3.5%

DCO frequency range 3.5 MHz,
trimmedfDCO3.5

Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 2

3.5

±3.5%

DCO frequency range 4 MHz,
trimmed

fDCO4

Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 3

4

±3.5%

DCO frequency range 5.3 MHz,
trimmedfDCO5.3

Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 4,
DCORSEL = 1, DCOFSEL = 1

5.3333±3.5%

DCO frequency range 7 MHz,
trimmedfDCO7

Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 5,
DCORSEL = 1, DCOFSEL = 2

7

±3.5%

DCO frequency range 8 MHz,
trimmed

fDCO8

Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 6,
DCORSEL = 1, DCOFSEL = 3

8

±3.5%

DCO frequency range 16 MHz,
trimmedfDCO16

Measured at SMCLK, divide by 1,
DCORSEL = 1, DCOFSEL = 4

16

±3.5%
26/

DCO frequency range 21 MHz,
trimmedfDCO21

Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 5

21

±3.5%
26/

DCO frequency range 24 MHz,
trimmedfDCO24

Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 6

24

±3.5%
26/

50%

52%

Duty cycle

fDCO,DC2

3

DCO jittertDCO,
JITTERDCO temperature drift 27/

48%

Measured at SMCLK, divide by 1,
no external divide, all
DCORSEL/DCOFSEL settings except
DCORSEL = 1, DCOFSEL = 5 and
DCORSEL = 1, DCOFSEL = 6
Based on fsignal = 10 kHz and DCO
used for 12-bit SAR ADC sampling
source. This achieves >74 dB SNR
due
to jitter (that is, it is limited by ADC
performance).

dfDCO/dT

3.0 V

0.01

DLA LAND AND MARITIMECOLUMBUS, OHIOCAGE CODE
16236
REV

A

ns

%/ºC

See footnote at end of table.

SIZE
A

MHz

DWG NO.
V62/16627
PAGE 13TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions
2/

TABLE I.b06

Limits

VCC
Min

Typ

Unit
Max

Internal Very-Low-Power Low-Frequency Oscillator (VLO)

Current consumption

IVLO

VLO frequency

fVLO

Measured at ACLKVLO frequency temperature drift

dfVLO/dT

Measured at ACLK

28/

0.2

%/ºC

VLO frequency supply voltage drift

dfVLO/dVCC

Measured at ACLK

29/

0.7

%/V

fVLO,DC

Measured at ACLK

Current consumption

IMODOSC

EnabledMODOSC frequency

fMODOSC

MODOSC frequency temperature drift
28/

fMODOSC/dT

0.08

%/ºC

MODOSC frequency supply voltage drift
29/

fMODOSC/dVCC

1.4

%/V

Duty cycle

DCMODOSC

Duty cycle
TABLE I.b07

TABLE I.b08

100
5

9.9

40%

50%

4,0

4.8

nA
15

kHz

60%

Module Oscillator (MODOSC)
25

Measured at SMCLK,
divide by 1

40%

µA
5.4

MHz

50%

60%

6

10

µs

400 +
1.5 /
fDCO

ns

Wake-up Times From Low-Power Modes and Reset(Additional) wake-up time to activate the
FRAM in AM if previously disabled by the
FRAM controller or from an LPM if
immediate activation is selected for
wakeuptWAKE-UP FRAM

Wake-up time from LPM0 to active modetWAKE-UP LPM030/

Wake-up time from LPM1 to active modetWAKE-UP LPM1

30/

6

µs

Wake-up time from LPM2 to active modetWAKE-UP LPM2

30/

6

µs

Wake-up time from LPM3 to active modetWAKE-UP LPM3

30/

7

10

µs

Wake-up time from LPM4 to active modetWAKE-UP LPM4

30/

7

10

µs

Wake-up time from LPM3.5 to active
mode

tWAKE-UP LPM3.5

31/

250

375

µs

Wake-up time from LPM4.5 to active

tWAKE-UP LPM4.5

SVSHE = 1

31/

250

375

µs

SVSHE = 0

31/

1

1.5

ms

mode

2.2 V,
3.0 V

Wake-up time from a RST pin triggered
reset to active modetWAKE-UP-RST

31/

318

400

µs

Wake-up time from power-up to active
mode

tWAKE-UP-BOR

31/

1

1.5

ms

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/16627
PAGE 14TABLE I. Electrical performance characteristics - Continued. 1/

Test

SymbolTest conditions
2/

TABLE I.b09 Typical Wake-up Charge
Charge used for activating the FRAM in AM
or during wake-up from LPM0 if previously
disabled by the FRAM controller.
Charge used for wake-up from LPM0 to
active mode (with FRAM active)
Charge used for wake-up from LPM1 toactive mode (with FRAM active)
Charge used for wake-up from LPM2 toactive mode (with FRAM active)
Charge used for wake-up from LPM3 toactive mode (with FRAM active)
Charge used for wake-up from LPM4 toactive mode (with FRAM active)
Charge used for wake-up from LPM3.5 toactive mode (with FRAM active) 33/
Charge used for wake-up from LPM4.5 toactive mode (with FRAM active) 33/
����� or BOR
Charge used for reset from RST
event to active mode 33/
TABLE I.b10 Digital Inputs

Limits

VCC
Min

Typ

Unit
Max

32/ (See FIGURE 5 and FIGURE 6)
QWAKE-UP FRAM

15.1

QWAKE-UP LPM04.4

QWAKE-UP LPM0

15.1

QWAKE-UP LPM015.3

QWAKE-UP LPM016.5

QWAKE-UP LPM016.5

QWAKE-UP LPM076

QWAKE-UP LPM0SVSHE = 1

77

SVSHE = 077.5

QWAKE-UP-

nA

75

RESET

Positive-going input threshold voltage

VIT+

2.2 V

1.2

1.65

3.0 V

1.65

2.25

2.2 V

0.55

1.00

3.0 V

0.75

1.35

2.2 V

0.44

0.98

3.0 V

0.60

Negative-going input threshold voltage

VIT–

Input voltage hysteresis (VIT+ – VIT–)

Vhys

Pullup or pulldown resistor

RPull

For pullup: VIN = VSS
For pulldown: VIN =VCCInput capacitance, digital only port pins

CI,dig

VIN = VSS or VCC

3

pF

Input capacitance, port pins with sharedanalog functions
34/

CI,ana

VIN = VSS or VCC

5

pF

High-impedance input leakage current

Ilkg(Px.y)

See 35/

20

36/

2.2 V

-20

V

1.30
35

50

+20

kΩ

nA

3.0 V
External interrupt timing (external trigger
pulse duration to set interrupt flag) 37/
External reset pulse duration on �����
RST 38/t(int)

Ports with interrupt

2.2 V

capability

3.0 Vt(RST)

2.2 V

20

ns

2

µs

3.0 V

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/16627
PAGE 15TABLE I. Electrical performance characteristics - Continued. 1/

Test

SymbolTest conditions
2/

TABLE I.b11

Min

Typ

Unit
Max

Digital Outputs

High-level output voltage/

VOH

Low-level output voltage

VOL

Port output frequency (with load)
41/
Clock output frequency

41/

Port output rise time, digital only

fPx.y
fPort_CLK

trise,dig

I(OHmax) = –1 mA

39/

I(OHmax) = –3 mA

40/

I(OHmax) = –2 mA

39/

I(OHmax) = –6 mA

40/

I(OHmax) = 1 mA

39/

I(OHmax) = 3 mA

40/

I(OHmax) = 2 mA

39/

I(OHmax) = 6 mA

40/

CL = 20 pF, RL

42/ 43/

2.2 V

3.0 V

2.2 V

Port output fall time, digital only

tfall,dig

3.0 V

with shared analog functions
Port output fall time, port pinswith shared analog functions

trise,ana
tfall,ana

VCC

VCC –
0.60
VCC –
0.25
VCC –
0.60
VSS

VCC

VCC
VSS +
0.25
VSS +
0.60
VSS +
0.25
VSS +
0.60

VSS

2.2 V
3.0 V

16
16

ACLK, MCLK, or SMCLK at

2.2 V

16

configured output port
CL = 20 pF 43/

3.0 V

16

CL = 20 pF

2.2 V

4

15

3.0 V

3

15

2.2 V

4

15

3.0 V

3

15

2.2 V

6

15

3.0 V

4

15

2.2 V

6

15

3.0 V

4

15

3.0 V
3.0 V

1200
650

CL = 20 pF
CL = 20 pF
CL = 20 pF

V

VCC

VSS

port pins
Port output rise time, port pins

VCC –
0.25

VSS

port pins

TABLE I.b12

Limits

VCC

MHz

ns

Pin-Oscillator Frequency, Ports Px

Pin-oscillator frequency

foPx.yPx.y, CL = 10 pF
Px.y, CL = 20 pF

44/
44/

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/16627
PAGE 16kHzTABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions
2/

TABLE I.b13

Min

Typ

Unit
Max

Timer_A

Timer_A input clock frequency

fTA

Timer_A capture timingtTA,cap

TABLE I.b14

Limits

VCC

Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%
All capture inputs, minimum pulse
duration required for capture

2.2 V,
3.0 V

Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
All capture inputs, minimum pulse
duration required for capture

2.2 V,
3.0 V

2.2 V,
3.0 V

16

MHz

20

ns

Timer_B

Timer_B input clock frequency

fTA

Timer_B capture timingtTA,cap

2.2 V,
3.0 V

16

MHz

20

ns

eUSCI (UART Mode) Clock Frequency
Internal: SMCLK or ACLK,eUSCI input clock frequency
feUSCI
External: UCLK,
Duty cycle = 50% ±10%
BITCLK clock frequency
fBITCLK(equals baud rate in MBaud)TABLE I.b16 eUSCI (UART Mode)
TABLE I.b15

16
4

UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
TABLE I.b17 eUSCI (SPI Master Mode) Clock Frequency
nternal: SMCLK or ACLK,eUSCI input clock frequency
feUSCI
Duty cycle = 50% ±10%
TABLE I.b18 eUSCI (SPI Master Mode)
UART receive deglitch time45/

2.2 V,
3.0 V

tt

STE lead time, STE active toclock

tSTE,LEAD

STE lag time, last clock to
STE inactivetSTE,LAG

STE access time, STE active
to SIMO data outtSTE,ACC

STE disable time, STE
inactive to SOMI highimpedance
SOMI input data setup timetSTE,DISSOMI input data hold time

tHD,MISIMO output data valid time(tVALID,MO

SIMO output data hold time(

tHD,MOMHzUCSTEM = 1,
UCMODEx = 01 or 10
UCSTEM = 1,
UCMODEx = 01 or 10
UCSTEM = 0,
UCMODEx = 01 or 10
UCSTEM = 0,
UCMODEx = 01 or 10

5
20
35
50

30
90
160
220

ns

16

MHz

UCxCLK
cycles1
1
2.2 V,
3.0 V

60
80

tSU,MI

2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V

UCLK edge to SIMO valid,
CL = 20 pF
CL = 20 pF

40
40
0
0
10
10
0
0

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/16627
PAGE 17ns

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions
2/

TABLE I.b19

eUSCI (SPI Slave Mode)

STE lead time, STE active toclock
STE lag time, Last clock to STE
inactive
STE access time, STE active to
SOMI data out
STE disable time, STE inactive
to SOMI high impedance
SIMO input data setup time

Min

Typ

Unit
Max

49/

tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIStSU,SISIMO input data hold time

tHD,SISOMI output data valid timetVALID,SO

SOMI output data hold time

tHD,SOTABLE I.b20

LimitsVCC

UCLK edge to SOMI valid,
CL = 20 pF
CL = 20 pF

2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V

45
40
2
3

ns

45
40
50
45
4
4
7
7
35
35
0
0

eUSCI (I2C Mode) (See FIGURE 11)

eUSCI input clock frequency

feUSCISCL clock frequency
Hold time (repeated) STARTfSCLtHD,STA

Setup time for a repeated
START
Data hold time
Data setup time
Setup time for STOP

tSU,STABus free time between STOP
and START conditions
Pulse duration of spikes
suppressed by input filter

Clock low time-out

tHD,DATtSU,DATtSU,STOtBUF
tSP

tTIMEOUT

Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
2.2 V, 3.0 V
2.2 V, 3.0 V

fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz

2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V

fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3

2.2 V, 3.0 V

2.2 V, 3.0 V

0
4.0
0.6
4.7
0.6
0
100
4.0
0.6
4.7
1.3
50
25
12.5
6.3

16

MHz

400

kHz
µs

ns
ns
µs

250
125
62.5
31.5
27
30
33

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/16627
PAGE 18

ns

msTABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

Limits2/

Min

TABLE I.b21 LCD_C, Recommended Operating Conditions
Supply voltage range, charge
VCC,LCD_C,CP en,3.6 LCDCPEN = 1, 0000b < VLCDx ≤pump enabled, VLCD ≤ 3.6 V
1111b(charge pump enabled, VLCD ≤ 3.6 V)
Supply voltage range, charge
VCC,LCD_C,CP en,3.3 LCDCPEN = 1, 0000b < VLCDx ≤pump enabled, VLCD ≤ 3.3 V
1100b(charge pump enabled, VLCD ≤ 3.3 V)
Supply voltage range, internal
VCC,LCD_C,int. bias
LCDCPEN = 0, VLCDEXT = 0
biasing, charge pump disabled
Supply voltage range, external
VCC,LCD_C,ext. bias LCDCPEN = 0, VLCDEXT = 0
biasing, charge pump disabled
Supply voltage range, external VCC,LCD_C,VLCDEXT LCDCPEN = 0, VLCDEXT = 1
LCD voltage, internal orexternal biasing, charge pumpdisabled
External LCD voltage at
VLCDCAPLCDCPEN = 0, VLCDEXT = 1
LCDCAP, internal or externalbiasing, charge pump disabled
Capacitor value on LCDCAP
when charge pump enabled

CLCDCAPACLK input frequency range

fACLK,infLCD

LCD frequency range
LCD frame frequency range

fFRAME,4mux

LCD frame frequency range

fFRAME,8mux

LCDCPEN = 1, VLCDx > 0000b (charge
pump enabled)
fFRAME = 1/(2 × mux) × fLCD with mux=1(static) to 8
fFRAME,4mux(MAX) = 1/(2 × 4) ×
fLCD(MAX) = 1/(2 × 4) × 1024 Hz
fFRAME,8mux(MAX) = 1/(2 × 4) ×
fLCD(MAX) = 1/(2 × 8) × 1024 Hz
fLCD = 1024 Hz, all common lines
equally loaded
LCDCPEN = 0, VLCDEXT = 1

Typ

Unit
Max

2.2

3.6

2.0

3.6

2.4

3.6

2.4

3.6

2.0

3.6

2.4

3.6

4.7
-20%
30
0

Panel capacitance

CPanelAnalog input voltage at R33

VR33

Analog input voltage at R23

VR23,1/3bias

LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0VR13

Analog input voltage at R13
with 1/3 biasing

VR13,1/3bias

LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0

VR03

Analog input voltage at R13
with 1/2 biasing

VR13,1/2bias

LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1

VR03

Analog input voltage at R03
Voltage difference between
VLCD and R03
External LCD reference
voltage applied at LCDREF

VR03
VLCD-VR03

R0EXT = 1
LCDCPEN = 0, R0EXT = 1

VSS
2.4

VLCDREFVLCDREFx = 01

0.8

4.7

10

DLA LAND AND MARITIMECOLUMBUS, OHIOCAGE CODE
16236
REV

A

µF

+20%

32.7682.4
VR03 + 2/3
× (VR33VR03)
VR03 + 1/3
× (VR33 –VR03)
VR03 + 1/2
× (VR33 –
VR03)

1.0

40
1024

kHz
Hz

128

Hz

64

Hz

10000

pF

VCC +
0.2
VR33

V

VR23

VR33

VCC +
0.2
1.2

See footnote at end of table.

SIZE
A

V

DWG NO.
V62/16627
PAGE 19

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions
2/

TABLE I.b22

Limits

VCC
Min

Typ

Unit
Max

LCD_C Electrical Characteristics

LCD voltage

Time to charge CLCD when
discharged

tLCD,CP,on

Maximum charge pump load
current

ICP,Load

VLCDx = 0000, VLCDEXT = 0
LCDCPEN = 1, VLCDx = 0001b
LCDCPEN = 1, VLCDx = 0010b
LCDCPEN = 1, VLCDx = 0011b
LCDCPEN = 1, VLCDx = 0100b
LCDCPEN = 1, VLCDx = 0101b
LCDCPEN = 1, VLCDx = 0110b
LCDCPEN = 1, VLCDx = 0111b
LCDCPEN = 1, VLCDx = 1000b
LCDCPEN = 1, VLCDx = 1001b
LCDCPEN = 1, VLCDx = 1010b
LCDCPEN = 1, VLCDx = 1011b
LCDCPEN = 1, VLCDx = 1100b
LCDCPEN = 1, VLCDx = 1101b
LCDCPEN = 1, VLCDx = 1110b
LCDCPEN = 1, VLCDx = 1111b
LCDCPEN = 1, VLCDx = 0111b,
VLCDREFx = 01b,
VLCDREF = 0.8 V
LCDCPEN = 1, VLCDx = 0111b,
VLCDREFx = 01b,
VLCDREF = 1.0 V
LCDCPEN = 1, VLCDx = 0111b,
VLCDREFx = 01b,
VLCDREF = 1.2 V
ΔVLCD = VLCD,x - VLCD,x-1
with x = 0010b to 1111b
LCDCPEN = 1, VLCDx = 1111b
external, with decoupling
capacitor
on DVCC supply ≥ 1 µF
CLCD = 4.7 μF, LCDCPEN =0→1,
VLCDx = 1111b
LCDCPEN = 1, VLCDx = 1111b

LCD driver output impedance,
segment lines

RLCD,Seg

LCDCPEN = 0, ILOAD = ±10 μA

2.2 V

10

LCD driver output impedance,
common lines

RLCD,COMLCDCPEN = 0, ILOAD = ±10 μA

2.2 V

10

CAGE CODE
16236

DWG NO.
V62/16627

LCD voltage with externalreference of 0.8 V

VLCD,0
VLCD,1
VLCD,2
VLCD,3
VLCD,4
VLCD,5
VLCD,6
VLCD,7
VLCD,8
VLCD,9
VLCD,10
VLCD,11
VLCD,12
VLCD,13
VLCD,14
VLCD,15
VLCD,7,0.8

LCD voltage with externalreference of 1.0 V

VLCD,7,1.0

LCD voltage with externalreference of 1.2 V

VLCD,7,1.2

Voltage difference between
consecutive VLCDx settings
Peak supply currents due tocharge pump activities

ΔVLCD
ICC,Peak,CP

2.4 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2.2 V to 3.6 V
2.2 V to 3.6 V
2.2 V to 3.6 V

2.49

3.32

VCC
2.60
2.66
2.72
2.78
2.84
2.90
2.96
3.02
3.08
3.14
3.20
3.26
3.32
3.38
3.44

2 V to 3.6 V

2.96 x
0.8

2 V to 3.6 V

2.96 x
1.0 V

2 V to 3.6 V

2.96 x
1.2 V
40

60

2.2 V

600

2.2 V

100

2.2 V

V
2.72

3.6
V

80

µA

500

50

DLA LAND AND MARITIMECOLUMBUS, OHIO

REV

A

ms
µA

See footnote at end of table.

SIZE
A

mV

PAGE 20kΩ

/
TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions
2/

TABLE I.b23

Limits

VCC
Min

Unit

Typ

Max

3.0 V

145

AVCC
199

2.2 V

140

190

3.0 V

175

245

2.2 V

170

230

2.2 V

10

15

>2 V
<2 V

0.5
1

4
10

kΩ

5.4

MHz

12-Bit ADC, Power Supply and Input Range Conditions

Analog input voltage range 52/
Operating supply current into
AVCC and DVCC terminals
53/ 54/
Operating supply current into
AVCC and DVCC terminal
53/ 54/V(Ax)
I(ADC12_B)
singleendedmode
I(ADC12_B)
differentia
mode

Input capacitance

CI

Input MUX ON resistance

RI

All ADC12 analog input pins Ax
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 0,
REFON = 0, ADC12SHTx = 0,
ADC12DIV = 0
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 1,
REFON = 0, ADC12SHTx= 0,
ADC12DIV = 00Only one terminal Ax can be selected
at one time
0 V ≤ V(Ax) ≤ AVCC

12-Bit ADC, Timing Parameters
For specified performance of ADC12Frequency for specified
fADC12CLK
linearity parameter with ADC12PWRMD =performance0.
If ADC12PWRMD = 1, the maximum is
1/4 of the value shown here.
Frequency for reduced
fADC12CLK
Linearity parameters have reduced
performance
performance
Internal oscillator 55/
fADC12OSC ADC12DIV = 0, fADC12CLK =fADC12OSC from MODCLKREFON = 0, Internal oscillator,
fADC12CLK = fADC12OSC from
Conversion timetCONVERTMODCLK, ADC12WINC = 0
External fADC12CLK from ACLK, MCLK,or SMCLK, ADC12SSEL ≠ 0

V
µA

pF

TABLE I.b24

Turn on settling time of the
ADC

tADC12ON

See 57/

Time ADC must be off before
it can be turned on again

tADC12OFF

tADC12OFF must be met to make surethat tADC12ON time holds.
All pulse sample mode
(ADC12SHP = 1) andextended sample mode
(ADC12SHP = 0) withbuffered reference
RS = 400 Ω,(ADC12VRSEL = 0x1,
RI = 4 kΩ,
0x3, 0x5, 0x7, 0x9, 0xB,
CI = 15 pF,
0xD, 0xF) 1 μs
Extended sample mode
Cpext= 8 pF
(ADC12SHP = 0) withunbuffered reference(ADC12VRSEL= 0x0,
0x2, 0x4, 0x6, 0xC,
0xE)

Sampling time

tSample0.45

32.768
4

4.8

2.6

kHz
5.4

MHz

3.5

µs

See
56/
100

ns

100

ns

1

µs

See
59/

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/16627
PAGE 21

TABLE I. Electrical performance characteristics - Continued. 1/

Test

SymbolTest conditions

Limits2/
TABLE I.b25

12-Bit ADC, Linearity Parameters With External Reference

Min

Typ

Unit
Max

60/

Number of no missing code
output-code bits

Resolution

Integral linearity error (INL) for
differential input

EI

1.2 V ≤ VR+ – VR– ≤ AVCC

+2.4

LSB

Integral linearity error (INL) for
single ended inputs

EI

1.2 V ≤ VR+ – VR– ≤ AVCC

+2.8

LSB

Differential linearity error (DNL)

ED

+1.0

LSB

Offset error 61/ 62/

EO

EG,extGain error

Total unadjusted error-0.99
ADC12VRSEL = 0x2 or 0x4 without TLV
calibration, TLV calibration data can be used
to improve the parameter.

±0.5

±1.5

mV

With external voltage reference without
internal buffer (ADC12VRSEL = 0x2 or 0x4)
without TLV calibration,
TLV calibration data can be used to improve
the parameter
63/,
VR+ = 2.5 V, VR– = AVSS

±0.8

±2.5

LSB

With external voltage reference with internalbuffer (ADC12VRSEL = 0x3),
VR+ = 2.5 V, VR– = AVSS

±1

With external voltage reference without
internal buffer (ADC12VRSEL = 0x2 or 0x4)
without TLV calibration,
TLV calibration data can be used to improve
the parameter 63/ ,VR+ = 2.5 V, VR– = AVSS

±1.4

With external voltage reference with internalbuffer (ADC12VRSEL = 0x3),
VR+ = 2.5 V, VR– = AVSS

±1.4

SNR

VR+ = 2.5 V, VR– = AVSS

ENOB

VR+ = 2.5 V, VR– = AVSS

64/
dB

11.2

bits

VR+ = 2.5 V, VR– = AVSS

10.7

bits

12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference

67/

12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference

TABLE I.b27

Effective number of bits 65/

ENOB

Signal-to-noise

SNR

VR+ = 2.5 V, VR– = AVSS

Effective number of bits 65/

ENOB

VR+ = 2.5 V, VR– = AVSS

12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference

Effective number of bits 65/
TABLE I.b30

±4.7

71

Effective number of bits 65/

TABLE I.b29

bits

12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference

TABLE I.b26
Signal-to-noise

TABLE I.b28

ET,ext12

ENOB

VR+ = 2.5 V, VR– = AVSS

66/

68

dB

10.7

bits

68/
10.4

bits

10

bits

12-Bit ADC, Dynamic Performance With 32.768-kHz Clock

Effective number of bits 65/

ENOB

Reduced performance with fADC12CLKfrom ACLK LFXT 32.768 kHz,
VR+ = 2.5 V, VR– = AVSS

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/16627
PAGE 22

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

Limits2/
TABLE I.b31

Min

Max

12-Bit ADC, Temperature Sensor and Built-In V1/2

See 69/ 70/ and FIGURE 12
See 70/VSENSORTCSENSOR

ADC12ON = 1, ADC12TCMAP = 1,
TA = 0°C
ADC12ON = 1, ADC12TCMAP = 1

Sample time required if ADCTCMAP = 1
and channel (MAX – 1) is selected 71/

tSENSOR(sample)

AVCC voltage divider for
ADC12BATMAP = 1 on MAX input
channelCurrent for battery monitor during sample
time
Sample time required if ADC12BATMAP= 1 and channel MAX is selected 72/

V1/2

ADC12ON = 1, ADC12TCMAP = 1,
Error of conversion result ≤ 1 LSB
ADC12ON = 1, ADC12BATMAP = 1

IV 1/2

ADC12ON = 1, ADC12BATMAP = 1

tV 1/2 (sample)

ADC12ON = 1, ADC12BATMAP = 1

TABLE I.b32

Typ

Unit

700

mV

2.5

mV/ºC

30
47.5%

µs
50%

52.5%

38

63

1.7

µA
µs

12-Bit ADC, External Reference 73/

Positive external reference voltage input
VeREF+ or VeREF- based on
ADC12VRSEL bit
Negative external reference voltage
input VeREF+ or VeREF- based on
ADC12VRSEL bit

VR+

1.2

AVCC

VR–

0

1.2

Differential external reference voltage
input

VR+ – VR–

1.2

AVCC

Static input current, singled-ended input
mode

IVeREF+,IVeREF

Peak input current with single-ended
input
Peak input current with differential input

IVeREF+

1.2 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
ADC12DIF = 0, ADC12PWRMD = 0
1.2 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
ADC12DIF = 0, ADC12PWRMD = 01
1.2 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
ADC12DIF = 1, ADC12PWRMD = 0
1.2 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
ADC12DIF = 1, ADC12PWRMD = 1
0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 0

IVeREF+

0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 1

Capacitance at VeREF+ or VeREF- terminal

CVeREF+/-See 74/

Static input current, differential input
mode

IVeREF+, IVeREF

±10

±20

±5
1.5

mA

3

mA

10

DLA LAND AND MARITIMECOLUMBUS, OHIOCAGE CODE
16236
REV

A

µA

±2.5

µF

See footnote at end of table.

SIZE
A

V

DWG NO.
V62/16627
PAGE 23

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions
2/

TABLE I.b33

Limits

VCC
Min

Typ

Unit
Max

REF, Built-In Reference

Positive built-in
reference voltage
output output
RMS noise at VREF 75/

VREF+

Noise

VREF ADC BUF_INT
buffer offset 76/

VOS_BUF_INT

VREF ADC BUF_EXT
buffer offset 76/

VOS_BUF_EXT

AVCC minimum
voltage,
Positive built-in
reference
activeOperating supply
current into AVCC
terminal 77/

AVCC(min)Operating supply
current into
AVCC termi/nal 77/

IREF+

REFVSEL = {2} for 2.5 V, REFON = 1
REFVSEL = {1} for 2.0 V, REFON = 1
REFVSEL = {0} for 1.2 V, REFON = 1
From 0.1 Hz to 10 Hz, REFVSEL = {0}

2.7 V
2.2 V
1.8 V

VREF maximum load
current, VREF+ terminal

IO(VREF+)

Load-current regulation,
VREF+ terminal

ΔVout/ΔIo(VREF+)

Capacitance at VREF+
and VREF- terminals
Temperature coefficientof built-in reference

CVREF+/-

Power supply rejection
ratio (DC)Power supply rejection
ratio (AC)Settling time ofreference Voltage 79/

PSRR_DCTCREF+

PSRR_ACtSETTLE

±1.5%
±1.5%
±1.5%

V

µV

TJ = 25°C , ADC ON, REFVSEL = {0},REFON = 1, REFOUT = 0
TJ = 25°C, REFVSEL = {0} , REFOUT = 1,
REFON = 1 or ADC ON

-12

+12

mV

-12

+12

mV

REFVSEL = {0} for 1.2 V

1.8

REFVSEL = {1} for 2.0 V

2.2

REFVSEL = {2} for 2.5 V
REFON = 1

2.7

ADC ON, REFOUT = 0, REFVSEL = {0, 1, 2},
ADC12PWRMD = 0,
IREF+_ADC_BUF

2.5
2.0
1.2
110

V

3V

8

15

µA

3V

225

355

µA

1030

1660

120

185

545

895

ADC ON, REFOUT = 1, REFVSEL = {0, 1, 2},
ADC12PWRMD = 0
ADC ON, REFOUT = 0, REFVSEL = {0, 1, 2},
ADC12PWRMD = 1
ADC ON, REFOUT = 1, REFVSEL = {0, 1, 2},
ADC12PWRMD = 1
ADC OFF, REFON = 1, REFOUT = 1,
REFVSEL = {0, 1, 2}
REFVSEL = {0, 1, 2}, AVCC = AVCC(min) for
each reference level,
REFON = REFOUT = 1
REFVSEL = {0, 1, 2},
IO(VREF+) = +10 μA or –1000 μA,
AVCC = AVCC(min) for each reference level,
REFON = REFOUT = 1
REFON = REFOUT = 1
REFVSEL = {0, 1, 2}, REFON = REFOUT =1,
TA = –55°C to 95°C 78/
AVCC = AVCC(min) to AVCC(max), TJ = 25°C,
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1
dAVCC= 0.1 V at 1 kHz
AVCC = AVCC (min) to AVCC(max),
REFVSEL = {0, 1, 2}, REFON = 0 → 1

1085
-1000

+10

µA

2500

µV/mA

100

pF

18

50

ppm/K

120

400

µV/V

0

3.0
75

mV/V
80

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/16627
PAGE 24µs

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions
2/

TABLE I.b34

Limits

VCC
Min

Unit

Typ

Max

11

20

9

17

Comparator_E

Comparator operating
supply current into
AVCC, excludes
reference resistor ladder

IAVCC_COMP

Quiescent current ofresistor ladder into
AVCC, including REF
module current

IAVCC_REF

Reference voltage level

VREF

Common-mode input
range
Input offset voltage

VIC
VOFFSET

Input capacitance

CIN

Series input resistance

RSIN

Propagation delay,
response time

tPD

Propagation delay withfilter active

Comparator enable time

Comparator andreference ladder andreference voltage enable
time
Reference voltage for agiven tap

tPD,filter

tEN_CMPtEN_CMP_VREF

VCE_REFCEPWRMD = 00, CEON = 1,
CERSx = 00 (fast)
CEPWRMD = 01, CEON = 1,
CERSx = 00 (medium)
CEPWRMD = 10, CEON = 1,
CERSx = 00 (slow), TJ = 30°C
CEPWRMD = 10, CEON = 1,
CERSx = 00 (slow), TJ = 95°C
CEREFLx = 01, CERSx = 10, REFON = 0,
CEON = 0, CEREFACC = 0
CEREFLx = 01, CERSx = 10, REFON = 0,
CEON = 0, CEREFACC = 1
CERSx = 11, CEREFLx = 01, CEREFACC = 0
CERSx = 11, CEREFLx = 10, CEREFACC = 0
CERSx = 11, CEREFLx = 11, CEREFACC = 0
CERSx = 11, CEREFLx = 01, CEREFACC = 1

2.2 V,
3.0 V

1.8 V
2.2 V
2.7 V
1.8 V

CERSx = 11, CEREFLx = 10, CEREFACC = 1
CERSx = 11, CEREFLx = 11, CEREFACC = 1

2.2 V
2.7 V

0.6
1.3
12

15

5

7

1.17
1.92
2.40
1.10

1.2
2.0
2.5
1.2

V

1.90
2.35
0

2.0
2.5

1.23
2.08
2.60
1.24
5
2.08
2.60
VCC-1
32
32
30

mV

3

kΩ

CEPWRMD = 00
CEPWRMD = 01
CEPWRMD = 10
CEPWRMD = 00 or CEPWRMD = 01
CEPWRMD = 10
On (switch closed)

-32
-32
-30

Off (switch open)
CEPWRMD = 00, CEF = 0, Overdrive ≥ 20 mV
CEPWRMD = 01, CEF = 0, Overdrive ≥ 20 mV
CEPWRMD = 10, CEF = 0, Overdrive ≥ 20 mV
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 00
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 01
CEPWRMD = 00 or 01, CEF = 1, μs
Overdrive ≥ 20 mV, CEFDLY = 10
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 11
CEON = 0 → 1, VIN+, VIN- from pins,
Overdrive ≥ 20 mV, CEPWRMD = 00
CEON = 0 → 1, VIN+, VIN- from pins, μs
Overdrive ≥ 20 mV, CEPWRMD = 01
CEON = 0 → 1, VIN+, VIN- from pins,
Overdrive ≥ 20 mV, CEPWRMD = 10
CEON = 0 → 1, CEREFLX = 10, CERSx = 10
or 11,
CEREF0 = CEREF1 = 0x0F,
Overdrive ≥ 20 mV
VIN = reference into resistor ladder,n = 0 to 31

50

VIN x
(n+0.5)
/32

9
9
1
260
350
700

330
460
15
1000

1.0

1.8

2.0

3.5

4.0

7.0

0.9

1.5

0.9

1.5

15

100

350

1500

VIN x
(n+1)
/32

VIN x
(n+1.5)/32

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

µA

DWG NO.
V62/16627
PAGE 25

pF

MΩ
ns
µs
ns
µs

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

Limits

VCC

2/

Min

TABLE I.b35 Extended Scan Interface, Port Drive, Port Timing
Voltage drop due to ONVOL(ESICHx)
I(ESICHx) = 2 mA, ESITEN = 1
resistance of excitationtransistor (see FIGURE 13)
Voltage drop due to ONVOH(ESICHx)
I(ESICHx) = –200 μA, ESITEN = 1
resistance of damping
transistor(1) (see FIGURE
13)
VOL(ESICOM)I(ESICOM) = 3 mA, ESISH = 1
V(ESICHx) = 0 V to AVCC, portfunction disabled, ESISH = 1
TABLE I.b36 Extended Scan Interface, Sample Capacitor/Ri Timing 81/
Sample capacitance on
CSHC(ESICHx)
ESIEx(tsm) = 1, ESISH = 1
selected ESICHx pin
IESICHx(tri-state)

Serial input resistance atthe ESICHx pin

0.3

V

3V

0.1

V

0

0.1

V

-50

50

nA

2.2 V,
3V
3V

2.2 V,
3V

ESIEx(tsm) = 1, ESISH = 1

tHold

ESI VCC/2 generator supply
voltage

VCC

ESI VCC/2 generator
quiescent current

IVMID

VCC/2 refresh frequency
Output voltage at pin
ESICOMTime to reach 98% after
VCC / 2 is switched on
Settling time to ±VCC / 2560
(2 LSB) after AVCC voltagechangefrefresh(ESICOM)
V(ESICOM)
ton(ESICOM)tVccSettle(ESICOM)

Max

3V

ESISHTSM 83/ = 1, measurement
sequence uses at least two ESICHx
inputs, ΔVsample < 3 mV
Extended Scan Interface, VCC/2 Generator

Maximum hold time 82/
TABLE I.b37

Ri(ESICHx)

Typ

Unit

AVCC = DVCC = ESIDVCC(connected together), AVSS = DVSS
= ESIDVSS (connected together)
CL at ESICOM pin = 470 nF ±20%,
frefresh(ESICOM) = 32768 Hz,
T = 0°C to 95°C,
Rext = 1k in series to CL
CL at ESICOM pin = 470 nF ±20%,
frefresh(ESICOM) = 32768 Hz,
T = –55°C to 95°C
Source clock = ACLK

2.2

CL at ESICOM pin = 470 nF ±20%,
ILoad = 1 μA
CL at ESICOM pin = 470 nF ±20%,
frefresh(ESICOM) = 32768 Hz
ESIEN = 1, ESIVMIDEN 84/ = 1,
ESISH = 0, AVCC = AVCC –100 mV,
frefresh(ESICOM) = 32768 Hz
AVCC = AVCC + 100 mV,
frefresh(ESICOM) = 32768 Hz

AVCC / 2
–0.07

7

pF

1.5

kΩ

62

µs

3.6

V

370

500

nA

370

1600

32.768

2.2 V,
3V

AVCC /
2
1.7

kHz
AVCC / 2+ 0.076

3
3

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/16627
PAGE 26

ms

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

Limits

VCC

2/

Min

Extended Scan Interface, 12-Bit DAC
ESIDVCC = AVCC = DVCC
(connected together),ESI DAC supply voltage
VCC
ESIDVSS = AVSS = DVSS
(connected together)
ESI 12-bit DAC operating supply
ICC
current into AVCC terminal 85/
Resolution
RL = 1000 MΩ, CL = 20 pF
Integral nonlinearity
INL
With autozeroing
RL = 1000 MΩ, CL = 20 pF,
Differential nonlinearity
DNL
Without autozeroing
RL = 1000 MΩ, CL = 20 pF,
With autozeroing
Offset error
EOS
With autozeroing
Gain error
EGWith autozeroing
On time after AVCC of ESIDAC iston(ESIDAC)
V+ESICA – VESIDAC = ±6 mV
switched on
Settling time
tSettle(ESIDAC)
ESIDAC code = 0h → A0h
ESIDAC code = A0h → 0h
TABLE I.b39 Extended Scan Interface, Comparator
ESIDVCC = AVCC = DVCC
(connected together),
ESI comparator supply voltage
VCC
ESIDVSS = AVSS = DVSS
(connected together)
ESI comparator operating
ICC
supply current into AVCC
terminal 86/
Common-mode input voltage
VIC
range 87/

Typ

Unit
Max

TABLE I.b38

Input offset voltage
Temperature coefficient ofVOffset 88/
VOffset supply voltage (VCC)
sensitivity 89/
Input voltage hysteresis

VOffsetdVOffset/dT
dVOffset/dVCC
Vhys

On time after ESICA is switchedonton(ESICA)

Settle time

tSettle(ESICA)

Autozeroing time of comparator

tautozero

After autozeroing
Without autozeroing
After autozeroing
Without autozeroing
After autozeroing
V+ terminal = V- terminal =0.5 × VCC
V+ESICA – VESIDAC = +6 mV,
V+ESICA = 0.5 × AVCC
V+ESICA – VESIDAC = –12 mV →6 mV,
V+ESICA = 0.5 × AVCC
Vinput = VCC / 2,
|Voffset| < 1 mV

2.2

2.2 V
3V
2.2 V,
3V

10
14
12
±2

3.6

V

27
35

µA

+10

bit
LSB
µA

-10

+10

LSB

-10

+10

LSB

-10

0

V
0.6%

2

µs

2
2
2.2

2.2 V,
3V

25
0
-1.5

2.2 V,
3V

40
2
0.3
0.2
0.5

3.5

V

42

µA

VCC 1
1.5

V
mV
µV/ºC
mV/V
LSB

2.0

µs

3.0
3.0

See footnote at end of table.

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Test

SymbolTest conditions
2/

TABLE I.b40

Limits

VCC
Min

Typ

Max

Extended Scan Interface, ESICLK Oscillator and TSM Clock Signals

ESI oscillator supply voltage

VCC

ESI oscillator operating supply
current

ICC

2.2

ESIDVCC = AVCC = DVCC
(connected together),
ESIDVSS = AVSS = DVSS
(connected together)

3.6

fESIOSC= 4.8 MHz, ESIDIV1x = 00b,
ESICLKGON = 1, ESIEN = 1,

2.2 V

45

no TSM sequence running

3V

50

ESI oscillator at minimum
setting

fESIOSC_min

TJ = 30°C, ESICLKFQ = 000000

2.3

ESI oscillator at maximum
setting

fESIOSC_max

TJ = 30°C, ESICLKFQ = 111111

7.9

Start-up time including
synchronization cycles

ton(ESIOSC)

fESIOSC = 4.8 MHz

ESIOSC frequency temperature
drift
88/

fESIOSC/dT

ESIOSC frequency supply
voltage drift
89/

fESIOSC/dVCC

TSM low-frequency state clock

fESILFCLKTSM high-frequency state clock

fESIHFCLKTABLE I.b41

Unit

2.2 V,
3V

V

µA

MHz

400

ns

fESIOSC= 4.8 MHz

0.15

%/ºC

fESIOSC= 4.8 MHz

2%/V

32.768
0.25

50

kHz

8

MHz

FRAM

Read and write endurance

1015

cycles

TJ = 25°C

100

years

TJ = 70°C

40

TJ = 95°C

10

Data retention durationtRetention

Current to write into FRAM

IWRITE

IREAD
91/

Erase current

IERASE92/

Write timetWRITE

tREAD
93/

ns

Read time

tREAD

NWAITSx = 0

1/
fSYSTEM
94/

ns

NWAITSx = 1

2/
fSYSTEM94/

See footnote at end of table.

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Test

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Min

TABLE I.b42 JTAG and Spy-Bi-Wire Interface
Supply current adder when JTAG
IJTAG
active (but not clocked)
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse duration
Spy-Bi-Wire enable time (TEST highto acceptance of first clock edge)
95/
Spy-Bi-Wire return to normal
operation time
TCK input frequency, 4-wire JTAG
96/
Internal pulldown resistance on
TEST
TCLK/MCLK frequency during JTAG
access, no FRAM access (limited by
fSYSTEM)TCLK low or high clock pulse
duration, no FRAM access
TCLK/MCLK frequency during JTAG
access, including FRAM access(limited by fSYSTEM with no FRAM
wait states)
TCLK low or high clock pulse
duration, including FRAM accesses

LimitsVCC

2.2 V,
3.0 V

Unit

Typ

Max

40

100

µA

fSBW
tSBW,LowtSBW, En

0
0.04

10
15
110

MHz
µs
µs

tSBW,Rst

15

100

µs

0
0
20

16
16
50

MHz
MHz
kΩ

fTCLK

16

MHz

tTCLK,Low/High25

ns

fTCLK,FRAM

4MHz

tTCLK,FRAM,Low/High

100

ns

fTCK

2.2 V
3.0 V
2.2 V,
3.0 V

Rinternal

35

See footnote at end of table.

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Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may notnecessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
Over recommended ranges of supply voltage and operation junction temperature unless otherwise noted.
In case of a supply voltage brownout, the device supply voltages must ramp down to the specified brownout power-down level(VVCC_BOR-) before the voltage is ramped up again to ensure a reliable device start-up and performance according to the data
sheet including the correct operation of the on-chip SVS module.
Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted
BOR resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/μs). Following the data sheet
recommendation for capacitor CDVCC should limit the slopes accordingly.
The brownout levels are measured with a slowly changing supply. With faster slopes, the MIN level required to reset the device
properly can decrease to 0 V. Use the graph in FIGURE 4 to estimate the VVCC_BOR- level based on the down slope of the
supply voltage. After removing VCC, the down slope can be estimated based on the current consumption and the capacitance on
DVCC: dV/dt = I/C where dV/dt = slope, I = current, C = capacitance.
The brownout levels are measured with a slowly changing supply.
�����/NMI pin is configured as NMI.
Not applicable if the RST
To improve EMI on the LFXT oscillator, observe the following guidelines.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.
• Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:• For LFXTDRIVE = {0}, CL,eff = 3.7 pF.
• For LFXTDRIVE = {1}, CL,eff = 6 pF
• For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 9 pF
• For LFXTDRIVE = {3}, 9 pF ≤ CL,eff ≤ 12.5 pF
This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bondand package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN
and COUT are the total capacitance at the LFXIN and LFXOUT terminals, respectively.
Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers.
Recommended effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of
1.6 pF. The PCB adds additional capacitance, so it must also be considered in the overall capacitance. Verify that therecommended effective load capacitance of the selected crystal is met.
Includes start-up counter of 1024 clock cycles.
Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set
the flag. A static condition or stuck at fault condition sets the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
To improve EMI on the HFXT oscillator, observe the following guidelines.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.
• Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator HFXIN and HFXOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
HFFREQ = {0} is not supported for HFXT crystal mode of operation.

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Maximum frequency of operation of the entire device cannot be exceeded.
When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave withparametrics defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCHFXT,
SW.
Includes start-up counter of 1024 clock cycles.
This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bondand package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN
and COUT is the total capacitance at the HFXIN and HFXOUT terminals, respectively.
Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers.
Recommended effective load capacitance values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF.
The PCB adds additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended
effective load capacitance of the selected crystal is met.
Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag. A
static condition or stuck at fault condition set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
After a wakeup from LPM1, LPM2, LPM3, or LPM4, the DCO frequency fDCO might exceed the specified frequency range for a
few clock cycles /by up to 5% before settling into the specified steady-state frequency range.
Calculated using the box method: (MAX(–55°C to 95°C) – MIN(–55°C to 95°C)) / MIN(–55°C to 95°C) / (95°C – (–55°C)).
Calculated using the box method: (MAX(–55°C to 95°C) – MIN(–55°C to 95°C)) / MIN(–55°C to 95°C) / (95°C – (–55°C))
Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to thefirst externally observable MCLK clock edge. MCLK is sourced by the DCO and the MCLK divider is set to divide-by-1 (DIVMx =000b, fMCLK = fDCO). This time includes the activation of the FRAM during wakeup.
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until
the first instruction of the user program is executed.
Charge used during the wake-up time from a given low-power mode to active mode. This does not include the energy required in
active mode (for example, for an interrupt service routine).
Charge required until start of user code. This does not include the energy required to reconfigure the device.
If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-MΩ
resistor in series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of
PJ.4/LFXIN and/or PJ.5/LFXOUT.
The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown
resistor is disabled.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger
signals shorter than t(int).
�����/NMI pin configured as NMI.
Not applicable if RST
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage
drop specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum
voltage drop specified.
The port can output frequencies at least up to the specified limit - it might support higher frequencies.
A resistive divider with 2 × R1 and R1 = 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tapof the divider. CL = 20 pF is connected from the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
CL is the external load capacitance connected from the output to VSS and includes all parasitic effects such as PCB traces.
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected
deglitch time can limit the max. useable baud rate. To ensure that pulses are correctly recognized their width should exceed the
maximum specification of the deglitch time.
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)). For the slave parameters tSU,SI(Slave) andtVALID,SO(Slave), see the SPI parameters of the attached slave.

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Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing
diagrams in FIGURE 7 and FIGURE 8.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate thatthe data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing
diagrams in FIGURE 7 and FIGURE 8.
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)). For the master parameters tSU,MI(Master)and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing
diagrams in FIGURE 9 and FIGURE 10.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in
FIGURE 9 and FIGURE 10.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
The internal reference supply current is not included in current consumption parameter I(ADC12_B).
Approximately 60% (typical) of the total current into the AVCC and DVCC terminals is from AVCC.
The ADC12OSC is sourced directly from MODOSC inside the UCS.
14 × 1 / fADC12CLK. If ADC12WINC = 1, then 15 × 1 / fADC12CLK.
The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are
already settled.
Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB: tsample = ln(2n+2) × (RS + RI) × (CI + Cpext), RS < 10 kΩ,
where n = ADC resolution = 12, RS= external source resistance, Cpext = external parasitic capacitance.
6 × 1 / fADC12CLK.
See TABLE I.b27 and TABLE I.b33 for more information on internal reference performance, and see manufacturer Designing
With the MSP430FR59x and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the
choice of internal or external reference.
Offset is measured as the input voltage (at which ADC output transitions from 0 to 1) minus 0.5 LSB
Offset increases as IR drop increases when VR– is AVSS.
For details, see the device descriptor in the manufacturer MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, andMSP430FR69xx Family User's Guide.
See TABLE I.b27 and TABLE I.b33 for more information on internal reference performance, and see manufacturer Designing
With the MSP430FR59xx and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the
choice of internal or external reference.
ENOB = (SINAD – 1.76) / 6.02
See TABLE I.b33 for more information on internal reference performance, and see manufacturer Designing With the
MSP430FR59xx and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice ofinternal or external reference
See TABLE I.b29 and TABLE I.b33 for more information on internal reference performance, and see manufacturer Designing
With the MSP430FR59xx and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the
choice of internal or external reference.
See TABLE I.b33 for more information on internal reference performance, and see manufacturer Designing With the
MSP430FR59xx and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice ofinternal or external reference.
The temperature sensor offset can be as much as ±30°C. TI recommends a single-point calibration to minimize the offset error of
the built-in temperature sensor.
The device descriptor structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each available reference voltage
level. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR
can be computed from the calibration values for higher accuracy.
The typical equivalent impedance of the sensor is 250 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tV1/2(on) is included in the sampling time tV1/2(sample); no additional on time is needed.

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103/

The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI,
is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should
follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
Connect two decoupling capacitors, 10 μF and 470 nF, to VeREF to decouple the dynamic current required for an externalreference source if it is used for the ADC12_B. Also see the manufacturer data on MSP430FR58xx, MSP430FR59xx,
MSP430FR68xx, and MSP430FR69xx Family User's Guide.
Internal reference noise affects ADC performance when ADC uses internal reference. See manufacturer Designing With the
MSP430FR59xx and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice ofinternal versus external reference.
Buffer offset affects ADC gain error and thus total unadjusted error.
The internal reference current is supplied through terminal AVCC.
Calculated using the box method: (MAX(–55°C to 95°C) – MIN(–55°C to 95°C)) / MIN(–55°C to 95°C)/(95°C – (–55°C)).
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
ESICOM = 1.5 V, supplied externally (see FIGURE 14).
The minimum sampling time (7.6 tau for 1/2 LSB accuracy) with maximum CSHC(ESICHx) and Ri(ESICHx) and Ri(source) is tsample(min) ≈ 7.6
× CSHC(ESICHx) × (Ri(ESICHx) + Ri(source)) with Ri(source) estimated at 3 kΩ, tsample(min) = 319 ns.
The sampled voltage at the sample capacitance varies less than 3 mV (ΔVsample) during the hold time tHold. If the voltage issampled after tHold, the sampled voltage may be any other value.
The control bit ESIVSS was renamed to ESISHTSM to avoid confusion with supply pin naming.
The control bit ESIVCC2 was renamed to ESIVMIDEN to avoid confusion with supply pin naming.
This parameter covers one ESI 12-bit DAC, either ESI AFE1 12-bit DAC or ESI AFE2 12-bit DAC.
This parameter covers one single ESI comparator; either ESI AFE1 comparator or ESI AFE2 comparator.
The comparator output is reliable when at least one of the input signals is within the common-mode input voltage range.
Calculated using the box method: (MAX(–55°C to 95°C) – MIN(–55°C to 95°C)) / MIN(–55°C to 95°C) / (95°C – (–55°C))
Calculated using the box method: ABS((Voffset_Vcc_max – Voffset_Vcc_min)/(Vcc_max – Vcc_min))Calculated using the box method: (MAX(2.2 V to 3.6 V) – MIN(2.2 V to 3.6 V)) / MIN(2.2 V to 3.6 V) / (3.6 V – 2.2 V)
Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM readcurrent IREAD is included in the active mode current consumption numbers IAM,FRAM.
FRAM does not require a special erase sequence.
Writing into FRAM is as fast as reading.
The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).
Tools that access the Spy-Bi-Wire and BSL interfaces must wait for the tSBW,En time after the first transition of the
TEST/SBWTCK pin (low to high), before the second transition of the pin (high to low) during the entry sequence.
fTCK may be restricted to meet the timing requirements of the module selected.
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Characterized with program executing typical data processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO = 24 MHz and
fMCLK = fSMCLK = fDCO / 2.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK
frequenc(fMCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by
the number of wait states or the cache hit ratio.
The following equation can be used to compute fMCLK,eff:
fMCLK,eff = fMCLK / [wait states × (1 – cache hit ratio) + 1]
For example, with 1 wait state and 75% cache hit ratio fMCKL,eff = fMCLK / [1 × (1 – 0.75) + 1] = fMCLK / 1.25.
Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.
Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified.
Cache hit ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 75% ratio
implies three of every four accesses is from cache, and the remaining are FRAM accesses.
See FIGURE 15 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method
for best linear fit using the typical data shown in TABLE I.a0.
Program and data reside entirely in RAM. All execution is from RAM.
Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.

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TABLE I. Electrical performance characteristics - Continued.
104/ All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
105/ Current for watchdog timer clocked by SMCLK included. fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO at specified frequency,
except for 12 MHz: here fDCO = 24 MHz and fSMCLK = fDCO / 2.
106/ All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
107/ Not applicable for devices with HF crystal oscillator only.
108/ Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF load.
109/ Low-power mode 2, crystal oscillator test conditions. Current for watchdog timer clocked by ACLK and RTC clocked by XT1
included. Current for brownout and SVS included. CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2), fXT1 = 32768 Hz,
fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
110/ Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load
capacitance are chosen to closely match the required 3.7-pF load.
111/ Low-power mode 2, VLO test conditions: Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1).
Current for brownout and SVS included. CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2), fXT1 = 0 Hz, fACLK = fVLO,
fMCLK = fSMCLK = 0 MHz.
112/ Low-power mode 3, 12-pF crystal excluding SVS test conditions: Current for watchdog timer clocked by ACLK and RTC clocked
by XT1 included. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3), fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz Activating
additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
113/ Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled(SVSHE = 0). CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3), fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due toadditional idle current. See the idle currents specified for the respective peripheral groups.
114/ Low-power mode 3, VLO excluding SVS test conditions: Current for watchdog timer clocked by ACLK included. RTC disabled(RTCHOLD = 1). Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due toadditional idle current. See the idle currents specified for the respective peripheral groups.
115/ Low-power mode 3, VLO excluding SVS test conditions: Current for watchdog timer clocked by ACLK included. RTC disabled(RTCHOLD = 1). RAM disabled (RCCTL0 = 5A55h). Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due toadditionalidle current. See the idle currents specified for the respective peripheral groups.
116/ Low-power mode 4 including SVS test conditions: Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due toadditional idle current. See the idle currents specified for the respective peripheral groups.
117/ Low-power mode 4 excluding SVS test conditions: Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due toadditional idle current. See the idle currents specified for the respective peripheral groups.
118/ Low-power mode 4 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). RAM disabled (RCCTL0 = 5A55h).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due toadditional idle current. See the idle currents specified for the respective peripheral groups.

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PAGE 34TABLE I. Electrical performance characteristics - Continued.
119/

120/

121/
122/
123/
124/
125/
126/

127/
128/

129/

130/

131/

Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled(SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due toadditional idle current - idle current of Group containing LCD module already included. See the idle currents specified for therespective peripheral groups
LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge
pump disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz) Current through external
resistors not included (voltage levels are supplied by test equipment). Even segments S0, S2, .. = 0, odd segments S1, S3, .. =1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge
pump disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz) Even segments S0, S2,...=0, odd segments S1, S3, ... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge
pump enabled), VLCDx = 1000 (VLCD= 3 V typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 /4 = 256 Hz) Even segments S0, S2, ...=0, odd segments S1, S3, ... = 1. No LCD panel load. CLCDCAP = 10 μF
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Not applicable for devices with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF load.
Low-power mode 3.5, 1-pF crystal including SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load
capacitance are chosen to closely match the required 3.7-pF load.
Low-power mode 3.5, 3.7-pF crystal excluding SVS test conditions:
Current for RTC clocked by XT1 included.Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5 including SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
LCD_C: See TABLE I.a3. For other module currents not listed here, see the module-specific parameter sections.

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Case XNOTES:
1. All linear dimensions are in millimeters. Dimensioning and toleracing per ASME Y14.5-1994.
2. This drawing is subject to change without notice.
3. Quad Flatpack, No-leads (QFN) package configuration.
4. The package thermal pad must be soldered to the board for thermal and mechanical performance,
5. See addition figure in the manufacturer Product data for the exposed thermal pad features and dimensions..
FIGURE 1. Case outline.

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PAGE 36FIGURE 2. Terminal connections.

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FIGURE 3. Functional block diagram.

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PAGE 38FIGURE 4. Brownout Power-Down Level vs Supply Voltage Down Slope.

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NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt service routineor to reconfigure the device.
FIGURE 5. Average LPM Currents vs Wake-Up Frequency at 25°C.

NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt service routineor to reconfigure the device.
FIGURE 6. Average LPM Currents vs Wake-Up Frequency at 85°C.

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PAGE 40FIGURE 7. SPI Master Mode, CKPH = 0.

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FIGURE 8. SPI Master Mode, CKPH = 1.

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PAGE 42FIGURE 9. SPI Slave Mode, CKPH = 0.

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PAGE 43FIGURE 10. SPI Slave Mode, CKPH = 1.

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PAGE 44FIGURE 11. I2C Mode Timing.

FIGURE 12. Typical Temperature Sensor Voltage.

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FIGURE 13. P6.x/ESICHx Timing, ESICHx Function Selected.

FIGURE 14. Voltage Drop Due to ON-Resistance.

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NOTE:
1.

2.

I(AM, cache hit ratio): Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-tomiss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of
FRAM accesses. For example, a 75% ratio implies three of every four accesses is from cache, and the remaining are FRAM
accesses.
I(AM, RAMonly): Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.

FIGURE 15. Typical Active Mode Supply Currents, No Wait States.

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FIGURE 16. LPM3 Supply Current vs Temperature (LPM3, XT3.7).

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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.
Vendor item drawing
administrative control
number 1/

Devicemanufacturer

V62/16627-01XE

01295

Vendor part number

CAGE code
MSP430FR5989-EP

1/ The vendor item drawing establishes an administrative control number for
identifying the item on the engineering documentation.

CAGE code

Source of supply

01295

DLA LAND AND MARITIMECOLUMBUS, OHIO

Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

SIZE
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