PEAK HOLD DETECTOR

PH300

STATE-OF-THE-ART
PERFORMANCE• High Speed (250 ns rise time)• Extremely Low Droop Rate (10 nV/ms)• Low Power (<36 mW)• Ramp & Dump Hold Discharge

Model PH300 is a high performance, thin film hybrid, peak-hold unit, designed to track and hold the peakof analog input signals with rise times (10% to 90% of Vmax) as short as 250 ns. The unit also has the lowest
Droop Rate of the held voltage available and consumes less than 36 mW of power in quiescent mode.
While this unit was designed for use in satellite instrumentation, the following unique characteristics makeit equally useful in a broad range of space, laboratory and commercial applications.

FEATURESAPPLICATIONS• Operates from -55 °C to +125 °C• Small size (16 pin hybrid DIP)
• Very low power (36 mW quiescent)• High speed• Low droop rate
• Ramp discharge• Fast reset• Build-in linear gate
• Internal hold capacitor• High reliability screening• One year warranty• Aerospace• Portable instrumentation• Nuclear monitoring• Particle, x-ray and gamma ray detection• Imaging• Research experiments• Medical and nuclear electronics• Electro-optical systems

PH300 Mechanical Diagram
TOP VIEW

SIDE VIEW

0.100 TYP.
(2.540)160.24(6.096)

90.80(20.32)0.600(15.240)
180.95(24.13)

AMPTEK INC.

0.25(6.350)

0.018 TYP.
(0.457)

DIMENSIONS:inches(mm)

14 DeAngelo Drive, Bedford, MA 01730-2204 U.S.A.

Tel: +1 (781) 275-2242 Fax: +1 (781) 275-3470 email: sales@amptek.com www.amptek.com

SPECIFICATIONSPIN DESCRIPTIONINPUT CHARACTERISTICSPINDESCRIPTION

Signal Analog

Range: 0 to (V+ - 1.5V)
Input impedance: >1 kΩ
Rise time (10% - 90%): 250 ns (min)1Linear Gate
Control Digital

Logic level: TTL
Gate open: HIGH
Gate closed: LOW
Gate turn on/off: 40 ns (60 ns max)2

IN is the analog input of the PH300. This input accepts a positive signal. The input
signal should not be driven greater than the positive analog power supply, or lessthan -0.5 V. Schottky diode input protection is recommended.
V- (-5 V to -6 V)

Ramp slew rate: 5 V/µs to 0.001 V/µs
Ramp control: TTL
Ramp active: LOW
Fast reset: <800 ns (dump mode)
Dump control: TTL
Dump active: LOWResetControl- Digital

OUTPUT CHARACTERISTICS
AnalogRange-load: >5 kΩ: 0 to (V+ - 1.5 V)(typical)
Output slew rate: 30 V/µs
Droop rate: <100 nV/µs @ 25 °C<5 µV/µs @ 70 °C
Linearity: ±0.01% (typical)
DC offset: ±2 mV (max)
Output current: Internally limited to 15 mA

Digital Peak
DetectLogic level: TTL
Vin > Vout : HIGH
Vin < Vout: LOWPropagation delay: <500 ns (typical)

HoldCapacitor

Internal: 470 pF ±5%
External: 50 pF - 1000 pF (optional)

3

RCEXT is a node that allows connection of an external hold resistor and holdcapacitor. When internal hold components are used, RCEXT is left unconnected.

4

HRES is the node of the internal hold resistor.

5

HCAP is the node of the internal hold capacitor. This node is normally connected
to HRES and DSCHG.

6

DSCHG is a node of the current generator used to reset the hold capacitor of thePH300. The RAMP reset current is set by an external current source or an external
resistor. This node is in a high impedance state when PH300 is in hold mode.
Normally this node is connected to the HCAP node.

7

ISET is a node of the current mirror that sets the discharge current. This nodesinks positive current. The discharge current is twice the current at this node. An
external resistor R can be connected between ISET and ground. In this case thereset current is approximately set to: 2*(Vˉ+ 0.6 V)/(R + 500 Ω). Amptek recommends a minimum value of 1 k for the external resistor.
NOTE! To ensure proper PH300 tracking mode operation, a reset current must beset regardless of the reset scheme (RAMP or DUMP) used to discharge the holdcapacitor.

8GND

9DUMP (active low) is a TTL compatible signal used for fast reset of the PH300. Thissignal must be used only in conjunction with the RAMP signal. The DUMP signal
can be active only when RAMP is active. A LOW state of this signal causes thedischarge current to peak up to 20 μA, causing fast discharge of the hold capacitor.
The duration of the DUMP signal should be keep as short as possible, since the highreset current increases substantially the power consumption of the PH300. A fixedduration of 1 μs usually is sufficient to completely reset the built in hold capacitor.
The PKDT signal can be used as an indicator for the discharge of the hold capacitor
and may provide a function to control the duration of the DUMP signal.

10RAMP (active low) is a TTL compatible input that controls the linear discharge ofthe PH300. When this signal is LOW, the DSCHG node sinks current that resets thehold capacitor. Since the reset current is constant, the output of PH300 decays
linearly.

ENVIRONMENTCaseOperating: -55 °C to +125 °C
Temperature Storage: -55 °C to +150 °C
Radiation

Hardness: 105 rad(Si) (optional withPH300RH only)

Screening

Amptek High Reliability

11Power Supply

Quiescent power: <36 mW @ -5V/+10V
V+: +5 V to +12 V (absolute maximum 18 V)
V¯: -5 V to -6 V (absolute maximum (V+- V¯) <30 V)
Quiescent I+: <2.4 mA (-55 °C to +125 °C)
Quiescent I¯: <2.4 mA (-55 °C to +125 °C)

GATE (open high) is a TTL compatible logic input that controls the linear gate ofthe PH300. When GATE is in an active HIGH state, the linear gate is open and theerror amplifier of the PH300 can sense the input signal. When GATE is inactive,the error amplifier input is tied to ground.

12

PKDT is an TTL output that indicates the state of the PH300. When this signal isLOW, the PH300 is in a hold mode.

13Vd (+5 V)

DigitalVd: +5 V (absolute maximum +7 V)
Quiescent Id: <0.01 mA (-55 °C to +125 °C)

14V+ (+5 V to +12 V)

15PackageHermetic, 16 pin hybrid, 600 mil DIP

COMP is a node for frequency compensation of the PH300 when an external holdcapacitor is used. In this case a resistor between 20 and 100 Ω can be used to reduce
output signal oscillations. This resistor must be connected between COMP and V+.
When the internal hold capacitor is used, COMP must be connected to V+.

16OUT is the analog output of the PH300. This output is protected for short circuits toground or any voltage between ground and the positive analog power supply.
WARNING! Shorting this output to any negative voltage may destroy the PH300
circuit. This output can drive capacitive loads up to 50 pf (typical). For higher
capacitive loads, use a resistor of 50 to 100 Ω in series with OUT. Range is 0 to(V+ - 1.5 V), typical.

AnalogFUNCTIONAL DIAGRAM

PRINCIPLE OF OPERATION (con’t)
HOLD MODE

Peak
Detector

GATE

PKDT

Charging
Diode
Buffer

Amplifier
IN

Gate

HoldResistor

RCEXT

COMP

HoldCapacitor

ISET
RAMPOUTResetCircuit

HRES
HCAPDSCHGDUMPV+V-VdGND

PRINCIPLE OF OPERATIONThe PH300 is a peak-hold device, designed to track an analog input pulse and keep the maximum amplitude as a peakvoltage on a hold capacitor. Major functional elements are
identified in the functional diagram above. An innovative
boot-strap circuit in the input stage of the output buffer amplifier, minimizes the droop error which occurs during periodsof long peakhold duration.
Inputs to the IN terminal are gated through a linear gate (gateinput), which is controlled by a TTL compatible logic signal.
When the gate is open (gate high), the input signal is sensed
by the error amplifier. When the gate is closed (gate low), theinput to the error amplifier is grounded and the input signal
does not have any effect on the output of PH300.
During the rise time of the input signal, the hold capacitor ischarged through a charging diode and a hold resistor. For thePH300, this mode of operation is referred to as the charging
mode. The device goes into hold mode as soon as the input
reaches Vmax and starts to decay. This state can be terminatedby discharging the hold capacitor. When the circuitry to accomplish this is enabled, the PH300 is placed in discharge
mode. A special case of the discharge mode is the tracking
mode. Additional information on each of these operationalmodes follows.

CHARGING MODE

The hold capacitor is charged during the rise time of the input
signal. The rise time of the input pulses can be as short as 250
ns. When the PH300 is in charging mode, negative feedback
is applied to the amplifier through the high impedance output
buffer. Under this condition, the output voltage follows theinput signal and the peak-detector logic output is in the inactive state. The feedback circuit brakes immediately after
the input goes through a maximum level and starts decaying.
The PH300 then enters hold mode.

In this mode, the charging diode is reverse biased and thevoltage across the hold capacitor is held equal to Vmax. The
peak-detector logic output is in the active state. The leakage
currents of the components connected to the hold capacitor
causes it to discharge. The rate of this discharge is the drooprate of the PH300.

DISCHARGE MODE

The hold capacitor could be intentionally discharged byenabling the reset circuit within the PH300. Two types ofreset are possible. They are: (i) ramp or linear reset and (ii)dump or fast reset.
In ramp discharge mode, the hold capacitor is discharged
through a constant current draw, which is set with an external
resistor or by an external current source. Constant current
discharge results in a linear decrease of the held voltage.
This operating mode is used in Wilkinson type analog todigital converters.
In fast discharge mode, the hold capacitor is discharged
through a large current draw for a short period of time. The
frequency and duration of this mode of operation determines
the upper limit of power consumption for the device.

TRACKING MODE

Negative feedback to the amplifier could become active(and correspondingly the peak-detector logic output goes tothe inactive state) in discharge mode operation, if the holdcapacitor voltage becomes less than or equal to the voltage
at the amplifier input. Therefore, if the discharge rate of
the hold capacitor is higher than the decay rate of the input
signal, the output of the PH300 will follow the input evenwhen the signal is decaying. This mode of PH300 operationis referred to as the tracking mode.

INPUT PROTECTION - CAUTION

The input (Pin 1) of the PH300 connects internallydirectly to an input of a CD4066 Quad Bilateral
Switch. Vdd, the positive supply for this chip, connects to V+ (+5 to +12V), Pin 14 of the PH300 and
Vss connects to GND, Pin 8. Normal precautions
for the use of the CD4066 must be observedwith the PH300 to avoid damage. These precautions include keeping the input voltage within(Vss - 0.5V) and (Vdd + 0.5V).
In particular, care should be taken that these conditions are not violated on power-up or power-down,or when a connector is mated or de-mated withpower on.
Input protection can be provided by a current-limiting resistor (>200 Ω) in series with the input, or byconnecting a diode from the input (Pin1) to ground(Pin 8), with anode grounded.

+10 V+5 V

V+Vd

APPLICATION NOTESCOMPPKDTPEAK
DETECTOR

INPUT

INPUT

OUTOUTPUT

GATE

GATE

RCEXT

RAMP

RAMP

HRES

DUMP

DUMP

HCAP

ISET

DSCHG

GND

1k

IN

OUT

RAMP

V-PKDT

T-5 V

Figure 1. - PH300 typical wiring diagram.
Figure 1 shows a typical wiring diagram of PH300 using
the internal hold and reset components. The board design
should prevent any possible paths for leakage currents tothe DSCHG, HCAP, HRES and RCEXT nodes.

CHDT

Figure 3. - Timing diagram illustrating RAMP
reset of PH300.

IN

A

B

C

D

OUT

IN

RAMP

DUMP

OUT

PKDTTCH

DT

GATE
RAMP

Figure 4. - Timing diagram illustrating DUMP
reset of PH300.

PKDT

Figure 2. - Gate function of PH300.
Figure 2 shows the use of the linear gate. Four pulses marked
A, B, C, and D are applied to the input of PH300. The linear
gate is open for the first three pulses and closed for the last
pulse, D. The PH300 is not discharged between the pulses.
Only the peaks of the pulses A and C will be detected. Pulse B
passes through the linear gate. However, since its amplitudeis less than the held amplitude of pulse A, there is no changeof the PH300 output. Pulse D does not affect the held peakvoltage of pulse C because the linear gate is closed.

AMPTEK INC.

Figures 3 and 4 illustrate the modes of operationof the PH300 with RAMP and DUMP reset of thehold capacitor. The linear gate is open. The modesof operation are indicated with bold characters as
follows:
C = charging modeD = discharge mode
H = hold mode
T = tracking mode

14 DeAngelo Drive, Bedford, MA 01730-2204 U.S.A.

Tel: +1 (781) 275-2242 Fax: +1 (781) 275-3470 email: sales@amptek.com www.amptek.com