S-82K3/K4 Series
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BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACKWITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION(SECONDARY PROTECTION)© ABLIC Inc., 2022-2023

Rev.1.2_00

This IC is used for secondary protection of lithium-ion rechargeable batteries, and incorporates high-accuracy voltage
detection circuits and delay circuits. The S-82K3 Series enable connection of 3-serial cell, and the S-82K4 Series enable
connection of 4-serial cell.
This IC provides a wake-up function to prevent the fuse from blowing during battery connection, and allows the lithium battery
to be connected in any order.
Since this IC also comes with a constant voltage output circuit, it can be used as a constant-voltage power supply for an
external RTC (Real-Time clock IC).

 Features• High-accuracy voltage detection circuit for each cell
Overcharge detection voltage n
3.600 V to 4.800 V (5 mV step)

Accuracy ±15 mV (Ta = +25°C)
Accuracy ±20 mV (Ta = −10°C to +60°C)
Overcharge release voltage n*1
3.600 V to 4.800 V
Accuracy ±50 mVVRTC pin shutdown voltage n
2.500 V to 2.800 V (100 mV step)
Accuracy ±50 mV• The wake-up function monitoring battery connection prevents CO pin output errors during battery connection• Delay times for overcharge detection are generated only by an internal circuit (external capacitors are unnecessary)
Overcharge detection delay time, VRTC pin shutdown delay time:
1 s, 2 s, 4 s, 6 s• Overcharge timer reset function:
Available, unavailable• CO pin output voltage is limited to 7.5 V max.
• VRTC pin output voltage:
1.800 V to 3.300 V (100 mV step)
Accuracy ±2% (Ta = +25°C)• VRTC pin output current:
2 mA max.
• Wide operation temperature range:
Ta = −40°C to +85°C• Low current consumption
During operation (VCU − 1.0 V for each cell):
4.0 μA max.
1.0 μA max.
During VRTC pin shutdown (VRSD − 1.0 V for each cell):• Lead-free (Sn 100%), halogen-free*1. Overcharge release voltage = Overcharge detection voltage − Overcharge hysteresis voltage(Overcharge hysteresis voltage can be selected from a range of 0 mV to 400 mV in 50 mV step.)
Remarkn = 1, 2, 3, 4

 Application• Lithium-ion rechargeable battery packs (for secondary protection)

 Packages• DFN-8(2020)A• HSNT-8(1616)

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BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
S-82K3/K4 Series
Rev.1.2_00
 Block Diagrams
1. S-82K3 Series

VDD

VC1
Constant voltage
output circuit

VC2

VRTC pin shutdown
comparator 1

VRTC

CO pin output voltage
limit circuit

CO

Overcharge detection
comparator 1
VC3

VRTC pin shutdown
comparator 2

Overcharge detection
comparator 2
VC4

VRTC pin shutdown
comparator 3

Overcharge detection
comparator 3
VSS

Battery connection
monitoring circuit

Remark Diodes in the figure are parasitic diodes.
Figure 1
2

Control logic
Delay circuit
Oscillator

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
Rev.1.2_00
S-82K3/K4 Series
2. S-82K4 Series

VDD

VC1

VRTC pin shutdown
comparator 1
Constant voltage
output circuit

VRTC

Overcharge detection
comparator 1
VC2

VRTC pin shutdown
comparator 2

CO pin output voltage
limit circuit

CO

Overcharge detection
comparator 2
VC3

VC4

VRTC pin shutdown
comparator 3

Control logic
Delay circuit
Oscillator

Overcharge detection
comparator 3
VRTC pin shutdown
comparator 4

Overcharge detection
comparator 4
VSS

Battery connection
monitoring circuit

Remark Diodes in the figure are parasitic diodes.
Figure 2
3

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
S-82K3/K4 Series
Rev.1.2_00
 Product Name Structure
1. Product name
S-82Kx

xxx

-

xxxx

U

Environmental codeU:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
A8T8: DFN-8(2020)A, Tape
A8T2: HSNT-8(1616), Tape
Serial code*2
Sequentially set from AAA to ZZZ
Number of cells in series
3:3-serial cell
4:4-serial cell

*1. Refer to the tape drawing.
*2. Refer to "3. Product name list".

2. Packages

Package Name
DFN-8(2020)A
HSNT-8(1616)

4

Table 1 Package Drawing Codes
Dimension
Tape
Reel
IB008-A-P-SD
IB008-A-C-SD
IB008-A-R-SD
PY008-A-P-SD
PY008-A-C-SD
PY008-A-R-SD

Land
IB008-A-L-SD
PY008-A-L-SD

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
Rev.1.2_00
S-82K3/K4 Series
3. Product name list
3. 1 S-82K3 Series
3. 1. 1 DFN-8(2020)A
Table 2
Overcharge Overcharge VRTC Pin VRTC Pin VRTC Pin Overcharge VRTC Pin
Overcharge
Detection
Release
Detection
Shutdown
OutputShutdown Recovery
Timer
Reset
Product Name
Voltage Delay Time*1 Delay Time*1
Voltage
Voltage
Voltage
Voltage
Function*2[VRST][VCU][VCL][VVRTC][VRSD][tCU][tRSD]
S-82K3AAA-A8T8U
4.600 V
4.300 V
3.300 V
2.500 V
2.700 V
6s
6s
Unavailable
S-82K3AAB-A8T8U
4.550 V
4.300 V
3.300 V
2.500 V
2.700 V
6s
6s
Unavailable*1. Overcharge detection delay time, VRTC pin shutdown delay time:
1 s, 2 s, 4 s, 6 s*2. Overcharge timer reset function:
Available, unavailable
Remark Please contact our sales representatives for products other than the above.
3. 2 S-82K4 Series
3. 2. 1 DFN-8(2020)A
Table 3
Overcharge Overcharge VRTC Pin VRTC Pin VRTC Pin Overcharge VRTC Pin
Overcharge
Detection
Release
Detection
Shutdown
OutputShutdown Recovery
Timer
Reset
Product Name
Voltage Delay Time*1 Delay Time*1
Voltage
Voltage
Voltage
Voltage
Function*2[VRST][VCU][VCL][VVRTC][VRSD][tCU][tRSD]
S-82K4AAA-A8T8U
4.600 V
4.300 V
3.300 V
2.500 V
2.700 V
6s
6s
Unavailable
S-82K4AAB-A8T8U
4.550 V
4.300 V
3.300 V
2.500 V
2.700 V
6s
6s
Unavailable*1. Overcharge detection delay time, VRTC pin shutdown delay time:
1 s, 2 s, 4 s, 6 s*2. Overcharge timer reset function:
Available, unavailable
Remark Please contact our sales representatives for products other than the above.

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BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
S-82K3/K4 Series
Rev.1.2_00
 Pin Configuration
1. DFN-8(2020)A
Table 4 S-82K3 Series
Pin No.

Figure 3

Symbol

1
2
3

VDD
VC1
VC2

4

VC3

5

VC4

6

VSS

7
8

CO
VRTC

Description
Positive power supply input pin
Positive power supply input pin
Positive voltage connection pin of battery 1
Negative voltage connection pin of battery 1
Positive voltage connection pin of battery 2
Negative voltage connection pin of battery 2
Positive voltage connection pin of battery 3
Negative power supply input pin
Negative voltage connection pin of battery 3
FET gate connection pin for charge control
Voltage output pin for Real-time Clock (RTC)
Table 5 S-82K4Series

Pin No.

Symbol

1

VDD

2

VC1

3

VC2

4

VC3

5

VC4

6

VSS

7
8

CO
VRTC

Description
Positive power supply input pin
Positive power supply input pin
Positive voltage connection pin of battery 1
Negative voltage connection pin of battery 1
Positive voltage connection pin of battery 2
Negative voltage connection pin of battery 2
Positive voltage connection pin of battery 3
Negative voltage connection pin of battery 3
Positive voltage connection pin of battery 4
Negative power supply input pin
Negative voltage connection pin of battery 4
FET gate connection pin for charge control
Voltage output pin for Real-time Clock (RTC)*1. Connect the heat sink of backside at shadowed area to the board, and set electric potential open or VC1.
However, do not use it as the function of electrode.

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BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
Rev.1.2_00
S-82K3/K4 Series
2. HSNT-8(1616)
Top view
1

8

4

5

Bottom view
8

1

5

4

Table6 S-82K3 Series
Pin No.
1
2
3

Symbol
VDD
VC1
VC2

4

VC3

5

VC4

6

VSS

7
8

CO
VRTC

*1

Figure 4

Description
Positive power supply input pin
Positive power supply input pin
Positive voltage connection pin of battery 1
Negative voltage connection pin of battery 1
Positive voltage connection pin of battery 2
Negative voltage connection pin of battery 2
Positive voltage connection pin of battery 3
Negative power supply input pin
Negative voltage connection pin of battery 3
FET gate connection pin for charge control
Voltage output pin for Real-time Clock (RTC)

Table7 S-82K4 Series
Pin No.

Symbol

1

VDD

2

VC1

3

VC2

4

VC3

5

VC4

6

VSS

7
8

CO
VRTC

Description
Positive power supply input pin
Positive power supply input pin
Positive voltage connection pin of battery 1
Negative voltage connection pin of battery 1
Positive voltage connection pin of battery 2
Negative voltage connection pin of battery 2
Positive voltage connection pin of battery 3
Negative voltage connection pin of battery 3
Positive voltage connection pin of battery 4
Negative power supply input pin
Negative voltage connection pin of battery 4
FET gate connection pin for charge control
Voltage output pin for Real-time Clock (RTC)*1. Connect the heat sink of backside at shadowed area to the board, and set electric potential open or VC1.
However, do not use it as the function of electrode.

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BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
S-82K3/K4 Series
Rev.1.2_00
 Absolute Maximum Ratings
Table 8(Ta = +25°C unless otherwise specified)
Item
Input voltage between VDD pin and VSS pin
Input voltage between VC1 pin and VSS pin
Input pin voltage
CO pin output voltage
VRTC pin output voltage
Operation ambient temperature
Storage temperature
CautionSymbol
VDS1
VDS2
VIN
VCO
VVRTC
Topr
Tstg

Applied Pin
VDD
VC1
VC2, VC3, VC4
CO
VRTC
−
−

Absolute Maximum Rating
VSS − 0.3 to VSS + 28
VSS − 0.3 to VSS + 28
VSS − 0.3 to VVC1 + 0.3
VSS − 0.3 to VDD + 0.3
VSS − 0.3 to VSS + 6−40 to +85−40 to +125

Unit
V
V
V
V
V
°C
°C

The absolute maximum ratings are rated values exceeding which the product could suffer physicaldamage. These values must therefore not be exceeded under any conditions.

 Thermal Resistance Value
Item

SymbolTable 9Condition

Board A
Board B
DFN-8(2020)A Board C
Board D
Board E
Junction-to-ambient thermal resistance*1 θJA
Board A
Board B
HSNT-8(1616) Board C
Board D
Board E
*1. Test environment: compliance with JEDEC STANDARD JESD51-2A
Remark8

Refer to " Power Dissipation" and "Test Board" for details.

Min.
−
−
−
−
−
−
−
−
−
−

Typ.
242
182
−
−
−
214
172
−
−
−

Max.
−
−
−
−
−
−
−
−
−
−

Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
Rev.1.2_00
S-82K3/K4 Series Electrical Characteristics
Table 10
(Ta = +25°C unless otherwise specified)
Item

SymbolCondition

Min.

Typ.

Max.

Unit

Test
Circuit

V

1

V

1

V

1

V

2

V

2

Detection Voltage
Overcharge detection voltage n(n = 1, 2, 3, 4)
Overcharge release voltage n(n = 1, 2, 3, 4)
VRTC pin shutdown voltage n(n = 1, 2, 3, 4)
VRTC pin recovery voltage n(n = 1, 2, 3, 4)
Input Voltage
Operation voltage between
VDD pin and VSS pin
Output Voltage
CO pin output voltage "H"
Input Current
Current consumption
during operation
Current consumption
during VRTC pin shutdown
VC1 pin input current
VCn pin input current(n = 2, 3, 4)
Output Current
CO pin source current
CO pin sink current
Delay Time
Overcharge detection delay time
Overcharge release delay time

Ta = +25°C
VCUn
Ta = −10°C to +60°C*1

VCU− 0.015
VCU− 0.020
VCL− 0.050
VRSD− 0.050
VRST− 0.100

VCU
VCU

VCU
+ 0.015
VCU+ 0.020
VCL+ 0.050
VRSD+ 0.050
VRST+ 0.100

VCLn

−

VRSDn

−

VRSTn

−

VDSOP

−

3.6

−

24

V

−

VCOH

−

4.0

6.0

7.5

V

2

IOPE

V1 = V2 = V3 = V4 = VCU − 1.0 V

−

2.0

4.0

μA

2

IOPED

V1 = V2 = V3 = V4 = VRSD − 1.0 V

−

−

1.0

μA

2

IVC1

V1 = V2 = V3 = V4 = VCU − 1.0 V

−

−

3.7

μA

2

IVCn

V1 = V2 = V3 = V4 = VCU − 1.0 V

−0.42

0

−

μA

2

ICOH
ICOL

−
−

−
20

−
−

−20
−

μA
μA

2
2

tCU × 0.7
8

tCU
16

tCU × 1.3
32

s
ms

2
2

6

12

20

ms

−

−
tRSD × 0.7
1

−

10
ms
tRSD × 1.3 s
3
s

−
2
2

Transition time to test mode
VRTC pin shutdown delay time
Wake-up delay time
VRTC Pin Output

tTST
tRSD
tWU

−
−
With overcharge timer resetfunction−−−

VRTC pin output voltage

VVRTC

IVRTC = 10 μA, SW2 = ON

tCU
tCL

Overcharge timer reset delay time tTR

VVRTC
× 0.98
−

VCL
VRSD
VRST

tRSD
2
VVRTC

VVRTC
× 1.02
2

V

2

−
−
−
VRTC pin output current
IVRTC
mA*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteedby design, not tested in production.

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BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
S-82K3/K4 Series
Rev.1.2_00
 Test Circuit

V0
V1
V2
V3

V4

1 VDD

VRTC 8

2 VC1

CO 7

0.1 μF

3 VC2

VSS 6

0.1 μF

4 VC3

VC4 5

100 Ω
1 kΩ
1 kΩ
1 kΩ

V

0.1 μF0.1 μF1 kΩ
0.1 μF0.1 μF

Figure 5 Test Circuit 1

1 VDD

VRTC 8

A

2 VC1

CO 7

A

3 VC2

VSS 6

4 VC3

VC4 5

V0
V1
SW1

V2
V3

V

V5

SW2

V

0.1 μF

V4

Figure 6 Test Circuit 2
In the initial status of the test circuit, SW1 and SW2 should be OFF.
This section provides explanations of test items using test circuit 1 and test circuit 2.

1. Overcharge detection voltage n (VCUn), overcharge release voltage n (VCLn)(Test Circuit 1)
After setting V0 = 0 V, V1 = V2 = V3 = V4 = VCU − 0.1 V, V1 is gradually increased. When the CO pin output inverts, thevoltage V1 is defined as the overcharge detection voltage 1 (VCU1). After that, V1 is then set to VCU + 0.1 V, V2 = V3 = V4
= 3.5 V. V1 is gradually decreased. When the CO pin output inverts again, the voltage V1 is defined as the overcharge
release voltage (VCL1).
Overcharge detection voltage n (VCUn) and overcharge release voltage n (VCLn) can be determined in the same way as
when n = 1.
Remark n = 1, 2, 3, 4

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BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
Rev.1.2_00
S-82K3/K4 Series
2. VRTC pin shutdown voltage n (VRSDn), VRTC pin recovery voltage n (VRSTn)(Test Circuit 2)
After setting V0 = 0 V, V1 = V2 = V3 = V4 = 3.5 V, V1 is gradually decreased. When the VRTC pin output becomes VSS,
the voltage V1 is defined as the VRTC pin shutdown voltage 1 (VRSD1). After that, V1 is then set to VRSD − 0.15 V, V2 =V3 = V4 = 3.5 V. V1 is gradually increased. When the VRTC pin output voltage becomes the VRTC pin output voltage(VVRTC), the voltage V1 is defined as the VRTC pin recovery voltage 1 (VRST1).
VRTC pin shutdown voltage n (VRSDn) and VRTC pin recovery voltage n (VRSTn) can be determined in the same way as
when n = 1.

3. CO pin output voltage "H" (VCOH)(Test Circuit 2)
The CO pin output voltage "H" (VCOH) is the voltage between the CO pin and the VSS pin when V0 = 0 V, V1 = 4.9 V, V2= V3 = V4 = 3.5 V.

4. CO pin source current (ICOH)(Test Circuit 2)
Set SW1 to ON after setting V0 = 0 V, V1 = 4.9 V, V2 = V3 = V4 = 3.5 V, V5 = VCOH − 0.5 V. The CO pin current is the CO
pin source current (ICOH) at that time.

5. CO pin sink current (ICOL)(Test Circuit 2)
Set SW1 to ON after setting V0 = 0 V, V1 = V2 = V3 = V4 = 3.5 V, V5 = 0.5 V. The CO pin current is the CO pin sinkcurrent (ICOL) at that time.

6. Overcharge detection delay time (tCU), overcharge release delay time (tCL)(Test Circuit 2)
After setting V0 = 0 V, V1 = V2 = V3 = V4 = 3.5 V, V1 is increased to 4.9 V. The overcharge detection delay time (tCU) is
the time period until the CO pin output inverts. After that, decrease V1 to 3.5 V. The overcharge release delay time (tCL)
is the time period until the CO pin output inverts.

7. VRTC pin shutdown delay time (tRSD)(Test Circuit 2)
After setting V0 = 0 V, V1 = V2 = V3 = V4 = 3.5 V, V1 is decreased to 2.4 V. The VRTC pin shutdown delay time (tRSD) isthe time period until the VRTC pin output becomes VSS.
Remark n = 1, 2, 3, 4

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BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
S-82K3/K4 Series
Rev.1.2_00
 Operation
Remark Refer to " Battery Protection IC Connection Examples".

1. Wake-up function operation during battery connection
The IC monitors whether or not all batteries have been connected to prevent CO pin output errors during battery
connection from blowing the protection fuse. When all batteries have been connected, the IC transitions to the normal
status. This is what we call the wake-up function. When 3.5 V or higher voltage batteries are connected to all battery
connection pins and this state continues for at least the wake-up delay time (tWU) = 2.0 s typ., the VRTC pin outputs the
VRTC pin output voltage (VVRTC) and the device enters the normal status.
No other operations are possible until the IC is in the normal status. The wake-up function is disabled when the IC
enters the normal status and is enabled access to other operations.

2. Normal status
When all battery voltages are higher than the VRTC pin shutdown voltage n (VRSDn) but lower than overcharge detection
voltage n (VCUn), the CO pin outputs "L" and the VRTC pin outputs VVRTC. This status is called the normal status.

3. Overcharge status
When the voltage of any of all batteries exceeds the overcharge detection voltage n (VCUn) and this condition continues
for the overcharge detection delay time (tCU) or longer, the CO pin output inverts. This status is called the overcharge
status. Charge control and secondary protection can be enabled by connecting an FET to the CO pin.
When all battery voltages fall below the overcharge release voltage (VCLn) and this condition continues for theovercharge release delay time (tCL) or longer, this IC returns to the normal status.

4. VRTC pin shutdown status
When the voltage of any of the batteries falls below the VRTC pin shutdown voltage n (VRSDn) and this condition
continues for the VRTC pin shutdown delay time (tRSD) or longer, the VRTC pin output becomes VSS. This status iscalled the VRTC pin shutdown status.
When all battery voltages exceed the VRTC pin recovery voltage n (VRSTn), this IC returns to the normal status.

5. Overcharge timer reset function
During tCU, which is from when the voltage of any of the batteries being charged exceeds VCUn until charging stops, thisIC has the following operations.
Even if an overcharge release noise, which temporarily forces the battery voltage below VCUn, is input, tCU iscontinuously counted as long as the overcharge release noise time is shorter than the overcharge timer reset delay time(tTR). Under the same conditions, if the overcharge release noise time is tTR or longer, counting of tCU is reset once. After
that, when VCUn has been exceeded, counting of tCU resumes.
Remark12

n = 1, 2, 3, 4

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
Rev.1.2_00
S-82K3/K4 Series
6. Test mode
In this IC, the overcharge detection delay time (tCU) and VRTC pin shutdown delay time (tRSD) can be shortened byentering the test mode.
The test mode can be set by retaining the VDD pin voltage 7.0 V or higher than the VC1 pin voltage for at least
10 ms (V1 = V2 = V3 = V4 = 3.5 V, Ta = +25°C). The status is retained by the internal latch and the test mode is retainedeven if the VDD pin voltage is decreased to the same voltage as that of the VC1 pin.
When this IC becomes the detection status after the delay time following the detection of an overcharge or VRTC pin
shutdown has elapsed, the latch for retaining the test mode is reset and this IC is released from the test mode.
VDD pin voltage

VC1 pin voltage

7.0 V orhigherPin voltage

VCUn
VCLn
Battery voltage

Test modetTST = 10 ms max.

CO pin(Active "H")tCU × 1 / 256 s typ.

tCL

Figure 7
Caution

1. Set the test mode when no batteries are overcharged.
2. The overcharge timer reset delay time (tTR) is not shortened in the test mode.

Remarkn = 1, 2, 3, 4

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BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
S-82K3/K4 Series
Rev.1.2_00
 Timing Charts
1. Wake-up function operation during battery connection (S-82K4 Series)

BAT1 to BAT4
Battery voltage
3.5 V

VRTC pin

VVRTC

tWU

Figure 8

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BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
Rev.1.2_00
S-82K3/K4 Series
2. Overcharge detection operation (With overcharge timer reset function)

VCUn
VCLn
Battery voltagetTR or longertTR or shortertCU or shorter

CO pin(Active "H")

VCOH

tCU

tCL

Figure 9
Remarkn = 1, 2, 3, 4

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BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
S-82K3/K4 Series
Rev.1.2_00
3. VRTC pin shutdown operation

Battery
voltage

VRSTn
VRSDn

tRSD or shorter

VRTC pin

VVRTC

tRSD

Figure 10
Remark16

n = 1, 2, 3, 4

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
Rev.1.2_00
S-82K3/K4 Series
4. Overcharge timer reset operation (With overcharge timer reset function)tTR or shortertTR or shorter tTR or longer
VCUn
VCLn
Battery voltagetCU orshorter
CO pin(Active "H")

tTR

VCOH
Timer resettCU

Figure 11
Remarkn = 1, 2, 3, 4

17

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
S-82K3/K4 Series
Rev.1.2_00
 Battery Protection IC Connection Examples
1. S-82K3 Series (3-serial cell)
SCP

EB+

VDD
RVDD

CVDD
VC1
VRTC
VC2

BAT1

R1

C1

CVR

FET*1

VC3
BAT2

R2

C2

CO

DP

RTC

VC4
BAT3

R3

C3
VSS

EB−

*1. This IC limits its CO pin output voltage to 7.5 V max., so a FET with the gate withstand voltage of 8 V can be
used.
Figure 12
Table 11 Constants for External Components
Max.
No.
Part
Min.
Typ.*11
1
1
1
R1 to R3
0.1
0.1
1
2
C1 to C3, CVDD
100
100
1000
3
RVDD
−
0.1
−
4
CVR
*1. Accuracy of overcharge detection voltage is guaranteed by typ. value in Table 11.
Connecting components with other values will worsen the accuracy.
Caution

18

Unit
kΩ
μF
Ω
μF

1. The constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than theconnection examples. In addition, the connection examples and the constants do notguarantee proper operation. Perform thorough evaluation using the actual application to set
the constants.
3. Set the same constants to R1 to R3 and to C1 to C3 and CVDD.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
Rev.1.2_00
S-82K3/K4 Series

2. S-82K4 Series (4-serial cell)
SCP

EB+

VDD
RVDD

CVDD
VC1

R1

BAT1

C1

VRTC
VC2

R2

BAT2

C2

CVR

FET*1

VC3
R3

BAT3

C3

CO

DP

RTC

VC4
R4

BAT4

C4
VSS

EB−

*1. This IC limits its CO pin output voltage to 7.5 V max., so a FET with the gate withstand voltage of 8 V can be
used.
Figure 13*1.

Table 12 Constants for External Components
No.
Part
Min.
Typ.*1Max.
1
1
R1 to R4
1
1
0.1
2
C1 to C4, CVDD
0.1
1
100
3
RVDD
100
1000
−
−
4
CVR
0.1
Accuracy of overcharge detection voltage is guaranteed by typ. value in Table 12.
Connecting components with other values will worsen the accuracy.

Caution

Unit
kΩ
μF
Ω
μF

1. The constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than theconnection examples. In addition, the connection examples and the constants do notguarantee proper operation. Perform thorough evaluation using the actual application to
set the constants.
3. Set the same constants to R1 to R4 and to C1 to C4 and CVDD.

19

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
S-82K3/K4 Series
Rev.1.2_00[For SCP, contact]
Dexerials Corporation
Tokyo Office
Address: Mitsui Sumitomo Kaijo Tepco Building 9F, 1-6-1 Kyobashi, Chuo-ku, Tokyo 104-0031, Japan
Tel: +81-3-3538-1230 (main)
https://www.dexerials.jp/en/

 Precaution• Before the battery connection, short-circuit the battery side pins RVDD and R1, shown in the figures in " Battery
Protection IC Connection Examples".
• The application conditions for the input voltage, output voltage, and load current should not exceed the power
dissipation.
• Do not apply to this IC an electrostatic discharge that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement of patents
owned by a third party by products including this IC.

20

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
Rev.1.2_00
S-82K3/K4 Series
 Characteristics (Typical Data)
1. Current consumption
1. 2 IOPE vs. Ta

12

5

10

4

8

IOPE [μA]

IOPE [μA]

1. 1 IOPE vs. VDD

6
4

3
2
1

2

0

0
0

5

10
15
VDD [V]20

25−40 −25025Ta [°C]

50

75 85

0

25
Ta [°C]

50

75 85

0

25
Ta [°C]50

75 85

1. 3 IOPED vs. Ta

1.0

IOPED [μA]

0.8
0.6
0.4
0.2
0.0

−

−
Ta [°C]

2. Detection voltage, release voltage
2. 2 VCL vs. Ta

4.63

4.36

4.62

4.34

4.61

4.32

VCL [V]VCU [V]2. 1 VCU vs. Ta

4.60
4.59
4.58
4.57

−40 −254.24
025Ta [°C]50

75 85−40 −25

2. 4 VRST vs. Ta

2.56

2.80

2.54

2.75

2.52

VRST [V]VRSD [V]

4.28
4.26

2. 3 VRSD vs. Ta

2.50
2.48

2.70
2.65

2.46
2.44

4.30

−40 −252.60
025Ta [°C]50

75 85−40 −25

21

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
S-82K3/K4 Series
Rev.1.2_00
3. Delay time
12

10

10

8

8

tRSD [ms]3. 2 tRSD vs. Ta

12tCU [s]3. 1 tCU vs. Ta

6
4

6
4

2
0

2
0

−40 −25025Ta [°C]50

75 85−40 −25025Ta [°C]50

75 85

4. Output pin
4. 2 ICOH vs. VDD

10

0

8

−10

ICOH [μA]

VCOH [V]4. 1 VCOH vs. VDD

6
4
2

−20
−30
−40
−50
−60

0
0

5

10
15
VDD [V]

20

25

0

5

10
15
VDD [V]2025

4. 3 ICOL vs. VDD

600

ICOL [μA]

500
400
300
200
100
0
0

5

10
15
VDD [V]2025

4. 5 VVRTC vs. VDD

5

5

4

4

VVRTC [V]VVRTC [V]4. 4 VVRTC vs. Ta

3
2
1
0

22

3
2
1

−40 −250025Ta [°C]

50

75 85

0

5

10
15
VDD [V]

20

25

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
Rev.1.2_00
S-82K3/K4 Series Marking Specifications
1. DFN-8(2020)A
8

Top view
7
6

5

1

2

4

3

(1):
(2) to (4):(5) to (7):Blank
Product code (Refer to Product name vs. Product code)
Lot number

Product name vs. Product code
1. 1 S-82K3 Series

1. 2 S-82K4 Series
Product code
(2)
(3)
(4)
9
L
A
9
L
B

Product name
S-82K3AAA-A8T8U
S-82K3AAB-A8T8U

Product name
S-82K4AAA-A8T8U
S-82K4AAB-A8T8U

(2)
9
9

Product code
(3)
(4)
L
L

R
S

2. HSNT-8(1616)

8

Top view
7
6

5

(1):
(2) ~ (4):(5) ~ (7):Blank
Product code
Lot number(1) (2) (3) (4)(5) (6) (7)

1

2

3

4

23

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK WITH CONSTANT VOLTAGE OUTPUT PIN FOR REAL-TIME CLOCK ENABLING ANY ORDER OF BATTERY CONNECTION (SECONDARY PROTECTION)
S-82K3/K4 Series
Rev.1.2_00
 Power Dissipation
HSNT-8(1616)

DFN-8(2020)A
Tj = +125°C max.

0.8
0.6 B
0.4

A

0.2
0.0

0

25

50

75

100

125

150

175

Tj = +125°C max.

1.0

Power dissipation (PD) [W]Power dissipation (PD) [W]

1.0

0.8
B

0.6

0.4 A
0.2
0.0

0

25

Ambient temperature (Ta) [°C]
Board
A
B
C
D
E

24

Power Dissipation (PD)
0.41 W
0.55 W
−
−
−

50

75

100

125

150

Ambient temperature (Ta) [°C]
Board
A
B
C
D
E

Power Dissipation (PD)0.47 W
0.58 W−−−

175

DFN-8(2020)A Test Board
IC Mount Area

(1) Board A
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]

1
2
3
4

Thermal via

Specification
114.3 x 76.2 x t1.6
FR-4
2Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.070-(2) Board B
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]Thermal via

1
2
3
4

Specification
114.3 x 76.2 x t1.6
FR-4
4Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070-

enlarged viewNo. DFN8-E-Board-SD-1.0

ABLIC Inc.

HSNT-8(1616) Test Board
IC Mount Area
(1) Board A
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]

1
2
3
4

Thermal via

Specification
114.3 x 76.2 x t1.6
FR-4
2Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.070-(2) Board B
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]Thermal via

1
2
3
4

Specification
114.3 x 76.2 x t1.6
FR-4
4Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070-

No. HSNT8-B-Board-SD-1.0

ABLIC Inc.

2.0±0.1

0~0.05

0.6 max.

0.25±0.1

0.5

0.25±0.1(0.9)

2.0±0.1(1.6)

The heat sink of back side has different electric
potential depending on the product.
Confirm specifications of each product.
Do not use it as the function of electrode.

No. IB008-A-P-SD-1.0

TITLE

DFN-8-E-PKG Dimensions

No.

IB008-A-P-SD-1.0

ANGLE
UNIT

mm

ABLIC Inc.

1.75±0.1+0.1

1.0 -00.25±0.05

4.0±0.1

2.25

+0.3

3.5±0.05

4.0±0.1

8.0 -0.1

2.0±0.05+0.1

1.5 -0

0.75

2.25

4

1

5

8

Feed direction

No. IB008-A-C-SD-1.0

TITLE

DFN-8-E-Carrier TapeNo.

IB008-A-C-SD-1.0

ANGLE
UNIT

mm

ABLIC Inc.

+0

180 -3+1.0

60 -0.0+1.0

9.0 - 0.0
11.4±1.0

Enlarged drawing in the central part±0.813±0.2
2±
0.5

21

(60°)

(60°)

No. IB008-A-R-SD-1.0

TITLE

DFN-8-E-ReelNo.

IB008-A-R-SD-1.0
QTY.

ANGLE
UNIT

mm

ABLIC Inc.

4,000

Land Pattern

0.50

1.80

2.40

1.00

0.50

0.30

Cauion It is recommended to solder the heat sink to a board
in order to ensure the heat radiation.
PKG

0.50

1.60

2.40

0.50

0.90

Metal Mask Pattern

0.30
CautionMask aperture ratio of the lead mounting part is 100%.
Mask aperture ratio of the heat sink mounting part is 80%.
Mask thickness: t0.12 mm
100%
80%
t0.12 mm

TITLE

DFN-8-E-Land Recommendation

No.

IB008-A-L-SD-1.0

ANGLE
UNIT

mm

No. IB008-A-L-SD-1.0

ABLIC Inc.

0.38±0.02

1.60±0.1(1.40)

0.1±0.04

0.2±0.05

0.4

The heat sink of back side has different electric
potential depending on the product.
Confirm specifications of each product.
Do not use it as the function of electrode.

No. PY008-A-P-SD-1.0

TITLE

HSNT-8-B-PKG Dimensions

No.

PY008-A-P-SD-1.0

ANGLE
UNIT

mm

ABLIC Inc.

2.0±0.05+0.1
ø1.5 -0ø0.35

4.0±0.1
0.20±0.05

4.0±0.1

0.55

1.80

4

1

5

8

Feed direction

No. PY008-A-C-SD-1.0

TITLE

HSNT-8-B-Carrier TapeNo.

PY008-A-C-SD-1.0

ANGLE
UNIT

mm

ABLIC Inc.

+1.0

9.0 - 0.0
11.4±1.0

Enlarged drawing in the central part

ø13±0.2

(60°)

(60°)

No. PY008-A-R-SD-1.0

TITLE

HSNT-8-B-ReelNo.

PY008-A-R-SD-1.0
QTY.

ANGLE
UNIT

mm

ABLIC Inc.

5,000

0.40

Land Pattern

1.30

0.25
Caution It is recommended to solder the heat sink to a board
in order to ensure the heat radiation.
PKG

0.40

Metal Mask Pattern

0.82

0.25
CautionMask aperture ratio of the lead mounting part is 100%.
Mask aperture ratio of the heat sink mounting part is 40%.
Mask thickness: t0.12 mm
100%
40%
t0.12 mm

TITLE

HSNT-8-B-Land Recommendation

No.

PY008-A-L-SD-1.0

ANGLE
UNIT

mm

No. PY008-A-L-SD-1.0

ABLIC Inc.

Disclaimers (Handling Precautions)1.

All the information described herein (product data, specifications, figures, tables, programs, algorithms andapplication circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.

2.

The circuit examples and the usages described herein are for reference only, and do not guarantee the success ofany specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any otherright due to the use of the information described herein.

3.

ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information describedherein.

4.

Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due tothe use of the products outside their specified ranges.

5.

Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.

6.

When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-relatedlaws, and follow the required procedures.

7.

The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,biological or chemical weapons or missiles, or use any other military purposes.

8.

The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.

9.

In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products areallowed to apply for the system on customer's own responsibility.

10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of thisdocument described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07

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