AN10911
SD(HC)-memory card and MMC interface conditioning
Rev. 2 — 4 April 2013

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Document information
Info

Content

Keywords

SD-memory card, Multi Media Card (MMC), ElectroStatic
Discharge (ESD) protection, ElectroMagnetic Interference (EMI) filtering

Abstract

This document gives an overview about different ESD protection and EMI
filter devices optimized for SD-memory card and MMC interfaces. These
devices cover the range from 1-bit to current standard 4-bit (SD-memory
card, SD 2.0) or 8-bit (MMC) high-speed memory card interfaces.

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SD(HC)-memory card and MMC interface conditioning

Revision history
Rev

Date

Description

2

20130404

Discontinued products removed

1

20100429

Initial version

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1. Introduction
The SD-memory card and MMC are the most popular memory cards in modern
communication, computer and consumer appliances. They support state-of-the-art
security and capacity requirements of modern audio and video applications in consumer
and communication products.
SD-memory cards support content protection, prevention of illegal use of content andsecurity systems based on, for example ISO-7816. An embedded version of MMC is
eMMC, according to the JESD84-A43. It offers up to 8-bit wide interface and can beapplied in SD-memory card compatible hardware interfaces.
While the SD-memory card adds an advanced data storage function to an application,
there is a more general Secure Digital Input Output (SDIO) card.
The SDIO card specification provides separately a specified interface to different I/Ounits. It provides various functions to an SD host, including memory storage that iscompatible with the SD-memory card specification. Even if an SD host is not SDIO
compatible (just supporting SD-memory cards), no physical damage or disruption ofoperation will occur.
An SD-memory card communication is based on an advanced 8/9-pin interface (clock,command, 1- or 4-bit data and 2/3 ×power/GND) designed to operate at a maximum
operating frequency of 50 MHz according to SD 2.0 specification.
The MMC works with an up to 52 MHz clock but supports in its latest versions up to 8
data bits in a 13-pin interface (clock, command, 1-, 4- or 8-bit data, 3 ×power/GND).
While the SD-memory card can contain some ESD protection (see chapter 8.1.3. of Ref. 1“SD specifications, part 1, Physical Layer Specification version 2.00, May 9, 2006”), SD
host interfaces require an additional high-level ESD protection according to theIEC61000-4-2 standard in addition to the host-interface integrated ESD protection which
is typically very weak.
Strict EMI regulations and system requirements, as specified in GSM mobile phones,
request filters that reduce the radiated and/or conducted EMI but still comply with theelectrical requirements of the interface specification.
The continuing trend in miniaturization of portable appliances implies that interface
devices offering ESD protection and EMI filtering should also, where possible, integratebiasing circuits or resistors into a single small-sized package.
Nexperia SD-memory card interface conditioning devices explained in this document
fully support this continuing trend and offer interface conditioning functions such as:• High-level ESD protection according the IEC61000-4-2 standard, often exceeding thehighest specified level 4• EMI filtering, suppressing unwanted Radio Frequencies (RF), in combination with
SD interface compliant physical signaling• Integrated biasing resistor networks to reduce the component count and to free up
additional space on the Printed-Circuit Board (PCB) surface

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2. SD-memory card electrical interface
Today many appliances use 2.7 V to 3.6 V operating mode. It enables the use of a fixedvoltage interface and power supply to reduce cost and complexity of the control circuitry.
All further descriptions are related to this high-voltage range: 2.7 V to 3.6 V supply voltage
operated interfaces.
A list of SD-memory card threshold levels for this range is listed in Table 2.

2.1 SD-memory card and microSD card interfaces
The SD-memory card exhibits nine pins (eight pins in case of microSD card) that are used
to support electrical communication in two alternative communication protocols: SD and
SPI (Serial Peripheral Interface). The host system can choose either one of these modes.
The card detects which mode is requested by the host when the reset command isreceived and expects all further communication to be in the same communication mode(see Ref. 1).
Figure 1 shows an SD-memory card and microSD card with the interface pins.

9

1 2 3 4 5 6 7 8
WP

SD-memorycard

9 1 2 456 78

microSDcard

microSD card pin numbering complies with Table 1

Fig 1.

Shapes and interfaces of SD-memory card and microSD card (bottom view)

The SD bus includes the following signals:• CLK: host to card clock signal• CMD: bidirectional command/response signal• DAT0 - DAT3: four bidirectional data signals• VDD, VSS1, VSS2: power and ground signals

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The SPI bus includes the following signals:• CS: host to card chip select signal• CLK: host to card clock signal• DataIn: host to card data signal• DataOut: card to host data signal
The SPI interface uses 7 out of the SD 9 signals (DAT1 and DAT 2 are not used, DAT3 isthe CS signal) of the SD bus.
Table 1 summarizes the pins of the SD card interface as used in SD and SPI modes:
Table 1.

Interface pins of an SD-memory card and microSD cardPin
SD modenumber NameType

Description

SPI mode
Name

Type

Description

1

CD/DAT3

I/O/PP

card-detect / data line (bit3)

CS

I

chip select (active low)

2

CMD

PP

command/responseDIIdata in3

GND1/VSS1

S

supply voltage ground

VSS

S

supply voltage ground

4

VDD

S

supply voltage

S

supply voltage

5

CLK

I

clock

I

clock

6

GND2/VSS2

S

supply voltage groundS

supply voltage ground

7

DAT0

I/O/PPdata line (bit 0)

DO

O/PP

data out

8

DAT1

I/O/PPdata line (bit 1)

RSV-

reserved

9

DAT2

I/O/PPdata line (bit 2)

RSV-

reserved

[1]

SCLK

I: input, O: output, PP: input / output using push-pull drivers, S: power supply.

The signals listed in Table 1 are directly provided from the SD-memory card itself.
Additionally card holder can provide mechanical switches for card detection (CD) andwrite protection (WP) mechanisms.

2.2 Bus operation conditions
The minimum output level of the driving device and the input level of the receiving device
are specified in Table 2 (see Ref. 1).
To decouple the SD-memory card interface specification from the signal-conditioning
device (EMI filter, ESD protection, etc.), an intermediate signal threshold is specified inTable 3. This “EMI filter, card interface side” leveling is taken as a minimum requirement
for an SD-memory card compliant interface conditioning device.
As ESD protection and EMI filter devices should be placed as close as possible to thecontacts of the protected interface and integrate a major portion of the total bus
capacitance CBUS, they are responsible, as any other filter device, for most of the voltage
drop.
Then the high-level and the low-level output voltages of the filter or conditioning device
can be reduced (refer to VOH and VOL in Table 3) comparing to the output threshold levels(see Table 2) and still exceed the input voltage level requirements.

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A detailed graphical overview of the different threshold levels at different positions of thesignal path is depicted in Figure 2, starting with the driver output on the left side andending with the receiving side on the right side of the drawing.
Three different threshold levels are shown in relation to each other in Figure 3,
comparing the SD-memory card output, the Nexperia signal-conditioning device output
and the SD-memory card input threshold levels.
Table 2.
SD-memory card threshold levels for high-voltage range
Values taken from Ref. 1
SymbolParameter

Min

Max

Unit

VSD

SD-memory card supply
voltage

Condition

2.7

3.6

V

VOH

high-level output voltage IOH = 100 A;
VSD = 2.7 V

0.75  VSD

-

V

VOL

low-level output voltage-

0.125  VSD V

VIH

high-level input voltage

0.625  VSD

-

V

VIL

low-level input voltage-

0.25  VSD

V

tPup

power up time

-

250

ms

Table 3.

SD-memory card operating conditions

IOL = 100 A;
VSD = 2.7 V

0 V  VSD  2.7 V

SymbolParameter

Min

Max

Unit

VSD

SD-memory card supply voltage

2.7

3.6

V

IDD

supply current in high-speed mode

-

200

mA

high-level output voltage[1][3]

0.7  VSD -VOL

low-level output voltage[2][3]-

CLload capacitance

-

40

pF

CCARD

SD-memory card signal line capacitance

-

10

pF

-

30

pF

VOH

CHOST + BUS capacitance of host interface and signal bus

AN10911

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0.2  VSD V

RCMDexternal pull-up resistor value to prevent bus
floating

10

100

k

RDAT

external pull-up resistor value to prevent bus
floating; DAT0, DAT1 and DAT2

10

100

k

RDAT3

SD-memory card internal pull-up resistor value
DAT3/CD pin only

10

90

k

Lch

single line inductance

-

16

nH

[1]

SD-memory card specification is: VOH minimum is 0.75 ×VSD and VIH minimum is 0.625 ×VSD in Ref. 1;
Nexperia VOH minimum is 0.7 ×VSD.

[2]

SD-memory card specification is: VOL maximum is 0.125 ×VSD and VIL maximum is 0.25 ×VSD in Ref. 1;
Nexperia VOL minimum is 0.2 ×VSD.

[3]

20 % to 70 % limits are chosen also to cover MMC specification.

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SD(HC)-memory card and MMC interface conditioning

Nexperia Interface
Conditioning Output
Requirement

Host Output
Voltage Thresholds
VSD

VOH = 0.75 * VSD
VOH = 0.7 * VSD

VOH = 0.7 * VSD
VIH = 0.625 * VSD
VIL = 0.25 * VSD
VOL = 0.2 * VSD

VOL = 0.2 * VSD
VOL = 0.125 * VSD
GND

VOL = 0.125 * VSD
GND

Host Output, driving
Fig 2.

VSD

VSD

VOH = 0.75 * VSD

SD Memory Card Input
Voltage Thresholds

GND

EMI-Filter

SD Memory Cardinterface, receiving

Threshold voltage levels along the signal path

Driver side
minimum
requirement

Receiver side
minimum
requirement

Receiver side
minimum
requirement

VSD

VOH = 0.75 * VSD
VOH = 0.7 * VSD
VIH = 0.625 * VSD

Host output
threshold level

Nexperia filter output
threshold level
SD-memory card
input threshold level

VIL = 0.25 * VSD
VOL = 0.2 * VSD
VOL = 0.125 * VSD
GND

Fig 3.

Threshold voltage levels, output levels versus input levels

All further considerations are based on a chosen 20 % and 70 % threshold respectively,
related to the SD-memory card supply voltage VSD, as specified in Table 3, unlessotherwise indicated. These relative voltage levels also simplify an alignment with the MMC
specification.

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SD(HC)-memory card and MMC interface conditioning

2.3 SD-memory card bus timing conditions
The SD-memory card interface has different timing requirements for the default mode andfor the high-speed mode up to 50 MHz clock frequency.
Special attention should be paid to the clock signal rise time and fall time requirements(3 ns maximum).
All Nexperia devices support both the high-speed mode and the default mode
requirements. Since high-speed mode requirements contain default mode requirements,
only the former considered in this document.
Table 4.

SD-memory card timing conditions (high-speed mode)[1]SymbolParameter

fPP

operating clock
frequencytrrise time

Condition

fall time

tf

Min

Max

Unit

0

50

MHz

20 % to 70 % of VDD

[2]

-

3

ns

70 % to 20 % of VDD

[2]

-

3

ns

[1]

Other timing parameters such as hold time, set-up time, high-level and low-level are dependent on the hostand SD-memory card interface and not significantly influenced by the Nexperia interface conditioning
devices.

[2]

Values refer to VOH and VOL specified for the EMI filter output.

2.4 Capacitive load at the interface conditioning device output
Nexperia devices, such as IP4352CX24, have rise time and fall timerequirements specified similarly to the data shown in Table 5.
Table 5.
Time domain response
Tamb = 25 C, VCC = 1.8 V, VBAT = 3.5 V, VSD = 2.9 V; 20 % to 70 % LOW-to-HIGH limits.
SymbolParameter

Test conditions

Min

Typ

Max

Unit

tr, tfrise time, fall time

Zload = 20 pF || 100 k

-

1.5

2.5

ns

tr, tfrise time, fall time

Zload = 40 pF || 100 k

-

2.7

3.6

ns

The following abbreviations are used:• Zload: capacitive load representing CPCB2 + CHOLD + CCARD in Nexperia data sheets• CPCBx: PCB trace capacitance• CHOLD: card holder capacitance• CBUS: total single bus channel capacitance excluding the SD-memory card
• CL: total single bus channel capacitance including the SD-memory card
For further details refer to Figure 4.
In this specification, Zload represents CCARD and a part of CBUS.
Figure 4 depicts the various basic capacitances of the signal path summing up to:
C BUS = C PCB1 + C CH/2 + C CH/2 + C PCB2 + C HOLD  30 pF

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Note that a significant portion (Nexperia assumption 20 % to 30 %) of the SD-memory
cards available on the market today have a card capacitance (CCARD) of more than 10
pF.
According to the SD-memory card specification (refer to chapter 6.5.5 of Ref. 1), thetotal channel capacitance CL is defined as:
C L = C BUS + C CARD  40 pF
Assuming that state-of-the-art host interfaces show a capacitance of C HOST  4 pF and
the Nexperia interface-conditioning devices add a capacitance in the range of
C CH = 2  C CH/2  20 pF , a capacitance of C PCB1 + C PCB2 + C HOLD  6 pF is left for therouting on the PCB and the card holder, which can already amount to 3 pF to 5 pF.
Due to Zload representing a lumped capacitance of 20 pF in addition to the filter channel
capacitance, it is obvious that the rise time and fall time requirement of 3 ns can be easily
fulfilled.

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Host Interface

EMI-Filter

Memory Card Interface

A

B
CHOST

SD:
CCARD = 10 pF
MMC: CCARD 12 pF – 18 pF

CBUS

C

CPCB1

CHOLD

Cch/2
Cch/2

CPCB2

CHOST

SD:
CCARD = 10 pF
MMC: CCARD 12 pF – 18 pF

CFilter = 20 pF

SD:
MMC:

CHOST + CBUS = 30 pF
CHOST + CBUS = 18 pF

SD Memory Card:
Multi Media Card:

CL = 40 pF
CL = 30 pF

Note: CBUS is a lumped representative of the total channel capacitances of PCB, interface
conditioning and card holder.
A. Basic simplified memory card signal channel
B. More detailed level
C. Detailed memory card signal channel showing the relevant capacitive contributors

Fig 4.

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Basic signal channel depicted in three different detail levels

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2.5 SD-memory card-detect mechanism
To detect an SD-memory card two different mechanisms can be used.
The conventional detection mechanism uses a mechanical switch in the card holder. The
other mechanism is based on the pull-up resistor integrated into the SD-memory card.
This resistor is connected to the DAT3/CD pin (where CD is card-detect). A detailed
schematic showing both detection mechanisms is depicted in Figure 6.
If MMC and SD-memory card are used in the same holder, only the mechanicalswitch-based card detection can be used.
In contrast to the SD-memory card specification, the MMC specification does not specify
any internal pull-up resistors for an electrical card detection mechanism.
Additionally, the SD-memory card specification gives clear priority to the mechanicalswitch detection method.

3. MMC electrical interface
Advanced appliances optimized for low-power consumption can operate MMCs at two
different supply voltages with small disadvantage of the increased control effort and aselectable supply voltage. A number of MMC threshold levels for the high-voltage range
are listed in Table 6.

3.1 Bus operating conditions
The minimum output level of the driving device, together with the receiving device input
level is specified in Table 6 (see Ref. 2 “Multi Media Card System Specification version
4.3, JESD84-A43, November 2007”).
Similar considerations as shown in Section 2.3 “SD-memory card bus timing conditions”,
are also applicable to the MMC.
For high-voltage operation mode the threshold conditions are identical to the SD-memory
card conditions. Therefore both can be operated if connected to the same physicalinterface as long as the electrical card detection mechanism is not used.

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Table 6.
MMC threshold levels(values taken from Ref. 2)
SymbolParameter

Condition

VMMC

MMC supply voltage
high-voltage range[1]

low-voltage range

Min

Max

Unit

2.7

3.6

V

1.7

1.95

V

0.75  VMMC-

V

Push-pull mode bus signal level for high-voltage MMC
IOH = 100 A;
VMMCmin

VOH

high-level output
voltageVOL

low-level output voltage IOL = 100 A;
VMMCmin-

0.125*VMMC

V

VIH

high-level input voltage

0.625  VMMC

VMMC + 0.3

VVIL

low-level input voltage

VSS  0.3

0.25  VMMC

V

Push-pull mode bus signal level for the dual voltage MMC in 1.70 V to 1.95 V mode forhigh-voltage specified above for high-voltage MMC
VMMC  0.2-

V

low-level output voltage IOL = 100 A;
VMMCmin

-

0.2

V

VIH

high-level input voltage

0.7  VMMC

VMMC + 0.3

VVIL

low-level input voltage

VSS  0.3

0.3  VMMC

V

VOH

high-level output
voltage

VOL[1]

IOH = 100 A;
VMMCminLow-voltage levels are part of the dual voltage range card specification including high-voltage range. The
voltage range from 1.95 V to 2.7 V is not specified.

Compared to the SD-memory card, the MMC bus is limited to a maximum of 30 pF(SD-memory card is 40 pF maximum).
Two basic differences between MMC and SD-memory card are:• minimum resistor value of RCMD which is less than a half of the specified minimum of
the SD-memory card specification• DAT0 to DAT7 pull-up resistor values, starting at 50 k instead of 10 k in the
SD-memory card specification (see Table 3).
The Embedded Multi Media Card (eMMC) contains internal pull-up resistors at the pins
DAT1 to DAT7 to prevent floating of unconnected data lines (see Ref. 2). All other MMCs
do not contain any pull-up resistors to prevent bus floating.

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Table 7.

MMC operating conditions

SymbolParameter

Min

Max

Unit

CL

total bus capacitance for each signal line

-

30

pF

CCARD

single card signal line capacitance
CMICRO-

12

pF

CMOBILE

-

18

pF

CBGA

-

12

pF

4.7

100

k

50

100

k

RCMD

CMD pull-up resistor value

RDAT7-DAT0 external DAT7 to DAT0 pull-up resistor value[1]

RintDATeMMC internal DAT7 to DAT0 pull-up resistor value

50

150

k

Lch

maximum signal line capacitance

-

16

nH

[1]

except eMMC

3.2 Bus timing conditions
The MMC interface has different timing requirements for the default mode and for thehigh-speed mode running up to 52 MHz. Special attention should be paid to the clock
signal rise and fall time requirement (3 ns maximum) which is similar to the high-voltage
range cards and the SD-memory card timing conditions (see Table 4).
Also, a reduced clock speed of up to 26 MHz can be used with these cards to save power
in appliances that do not require high data rates.
All Nexperia devices support both the high-speed mode and the default mode
requirements. Since high-speed mode requirements contain default mode requirements,
only the former considered in this document.
Table 8.

MMC timing conditions (high-speed mode)[1]SymbolParameter

fPP

operating clock frequency

trisehigh-speed mode clock rise time

tfall

high-speed mode clock fall time

[2]

Min

Max

Unit

0

52

MHz

-

3

ns

-

3

ns

[1]

Other timing parameters such as hold time, set-up time, high-time and low-time depend on thehost and MMC interface. They are not significantly influenced by Nexperia interface conditioning
devices.

[2]

Refer to Ref. 2, chapter 12.7.1 for further details.

3.3 Capacitive load at the interface conditioning device output
Refer to Section 2.4 for a detailed overview and calculation.
The drawing depicted in Figure 4 shows that it is difficult to build an MMC
specification-compliant bus system that includes high-level ESD protection and EMI
filtering. Nevertheless, most implementations used are related to the SD-memory card
application and use only slightly higher total channel capacitances, reaching the
SD specification for the value of CHOST + CBUS.

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4. SD-memory card and MMC interface comparison
A short summary of the main electrical interface parameters of the SD-memory card
versus the MMC are listed in the following table:
Table 9.

SD-memory card and MMC electrical parameters comparison

SymbolParameter

Vsd/MMC

memory card supply voltage

SD-memory
card

MMC

Unit

V

high-voltage range

2.7 - 3.6

2.7 - 3.6

low-voltage range-

1.7 - 1.95 V

fPP

maximum operating clock frequency

50

52

MHz

trise

maximum high-speed mode clock rise time

3

3

ns

tfall

maximum high-speed mode clock fall time

3

3

ns

CL

maximum total bus capacitance for eachsignal line

40

30

pF

CCARD

maximum capacitance single card signal line

10

-

pF

CMICRO-

12

pF

CMOBILE

-

18

pF

CBGA

-

12

pF

10 - 100

4.7 - 100k

10 - 100

50 - 100k

-

50 - 150k

RCMD

CMD pull-up resistor value[1]

RDAT7(3)-0

external DAT7(3) - DAT0 pull-up resistor
value to prevent bus floating

RintDAT3

eMMC internal DAT7- DAT0 pull-up resistor
value
DAT3/CD (SD)10 - 90

-

k

Lch

maximum signal line inductance

16

16

nH

[1]

except eMMC

5. Passive ESD protection and EMI filter devices
Nexperia offers a wide range of devices for the interface conditioning of the SDmemory card and/or MMC interface. The product range covers EMI filters and ESD
protection devices, such as IP4252CZ12-6 or IP4252CZ16-8.
These devices can be also used for Serial Peripheral Interface (SPI)-based interface
operation modes. In this case 4-channel devices can be used although this is not thepreferred method of data exchange with SD-memory cards due to the lower speed andsingle bit access.
An overview is given in Table 10 and a detailed description is given in the next chapters.
These filter devices are available in leadless plastic packages (DFN) and Wafer Level
Chip Size Packages (WLCSP).

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Even though the MMC and SD-memory card specifications state exact minimum andmaximum values for the various internal and external pull-up and pull-down resistors, amajority of implemented interfaces in available appliances do not follow theserecommendations. This is especially true for the minimum CMD signal pull-up resistor
value, which is often undercut to guarantee a sufficiently short rise time in an open-drain
communication mode. The minimum values of the external pull-up resistor values of the
MMC specification are also sometimes replaced by values from the SD-memory card
specification range.
Therefore most Nexperia devices can be used in both interface applications, MMCs andSD-memory cards, even though data sheets are referring to just one interface type.
Modern memory cards typically support interfaces which are slightly out of the related
general interface specification.
Table 10.

SD-memory card and MMC interface devices overview

Product name

Device type

Additionalfeatures

Number Package type and sizeof filterchannels

Memory card interface ESD protection and EMI filter devices with integrated biasing (pull-up-/pull-down) resistors,
ESD protection level > 15 kV contact, far exceeding the IEC61000-4-2, level 4 (8 kV contact, 15 kV air)
IP4340CX15

ESD protection and EMI filter

IP4350CX24

ESD protection and EMI filter

IP4352CX24

ESD protection and EMI filter

IP4357CX17

ESD protection and EMI filter

6

CSP, 0.4 mm pitch
1.56  1.56  0.47 mm3

including
WP and CD

6 (+5) [1]

CSP, 0.4 mm pitch
2.01  2.02  0.61 mm3including
WP and CD

6 (+5) [1]

CSP, 0.4 mm pitch
2.01  2.02 mm2
CSP, 0.4 mm pitch (staggered)
1.1  2.4 mm2Memory card interface ESD protection and EMI filter devices, ESD protection level according IEC61000-4-2, level 4(8 kV contact, 15 kV air discharge)
IP4252CZ8-4

ESD protection and EMI filter

4

DFN, 0.4 mm pitch
1.35  1.7  0.5 mm3IP4252CZ12-6

ESD protection and EMI filter

6

DFN, 0.4 mm pitch
1.35  2.5  0.5 mm3IP4252CZ16-8

ESD protection and EMI filter

8

DFN, 0.4 mm pitch
1.35  3.3  0.5 mm3[1]

Numbers in brackets represent additional channels such as pull-up and pull-down channels, WP and CD that are not required for thebasic data communication.

AN10911

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SD(HC)-memory card and MMC interface conditioning

5.1 ESD protection EMI filter devices in plastic package IP4252CZ8-4,
IP4252CZ12-6, IP4252CZ16-8
If pull-up resistors are integrated in the host interface, then ESD protection and EMI
filtering devices such as IP4252 family are recommended. These devices are available
in 4-, 6- and 8-channel versions: IP4252CZ8-4, IP4252CZ12-6 andIP4252CZ16-8.
They all contain an RC-based pi-filter (also called Capacitor-Resistor-Capacitor (CRC)
filter) consisting of two ESD protection diodes, acting as filter capacitors, and a serial
channel resistor connected between the cathodes of these diodes.
Single filter channel schematic is shown in Figure 5 (left side) together with DFN plastic
packages (right side). These packages have 0.4 mm contact pitch and 0.5 mm maximum
package height.

Rs(ch)
Cch
2

Cch
2

GND

a. Schematic view for a single channel
Fig 5.

b. IP4252CZ8-4, IP4252CZ12-6 and IP4252CZ16-8
package (top to bottom)

IP4252: schematic view and package photograph
Table 11.

IP4252 parameters

Symbol Parameter

Conditions

VCC

supply voltage

VESD

electrostatic
discharge voltage

Min

Typ

Max

Unit

0.5

-

+5.6

V

8

-

+8

kV

IEC 61000-4-2, level 4;
all pins to groundcontact discharge

15

-

+15

kV

Rs(ch)

channel series
resistance

32

40

48



Cch

channel capacitance Vbias(DC) = 0 V,
f = 100 kHz
C ch= 2 --------Vbias(DC) = 2.5 V,2
f = 100 kHz

-

18

-

pF

-

12

-

pF

air discharge[1]

Total channel capacitance is distributed between both ports of the channels, see Figure 5.

Due to the integrated symmetrical pi-filter structure (often referred to as CRC structure)
all Nexperia IP4252 devices offer a direction-independent and symmetrical ESD
protection as well as a direction-independent and symmetrical EMI filter performance.
Integrated pi-filter structures provide very low ESD clamping voltage compared to single
diode ESD protection implementations and/or devices.
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5.1.1 Application details of IP4252CZ12-6 and IP4252CZ16-8
Figure 6 shows a typical application of IP4252CZ12-6 and/or IP4252CZ16-8 in an
SD-memory card interface including both options for card detection. The grey-coloredcomponents are optional and depend on the exact details of the interface implementation.
Especially with respect to the card-detect mechanism, either using a mechanical switch inthe card holder (preferred, see Ref. 1) or using integrated pull-up resistor at pin DAT3/CD
in combination with selectable pull-down / pull-up resistors. The exact resistor values haveto be aligned with all details described in Ref. 1.
This schematic does not include details concerning card-supply and typical power-supply
decoupling capacitors.
For the basic SD-memory card operation an IP4252CZ12-6 and 4 pull-up resistors(10 k to 100 k) are sufficient for the digital data transmission from and to theSD-memory card. MMCs require higher pull-up resistor values starting at 50 k. The card
detection mechanism has to be implemented using a CD channel as shown in Figure 7,
based on a mechanical card detection switch, in case SD-memory card and MMC areused with the same interface.

optional
electrical
Card Detect

VCC(VSD)

DAT3/CD-pull -up
10 kΩ - 100 kΩ

Pull-up resistors
10 kΩ – 100 kΩ

to host interface

IP4252 CZ12-6(IP4252 CZ16-8)

DAT1

DAT1
DAT0
CLK
CMD

GND

DAT3/CD
DAT2

CLK

CD
WP

SET_CLR_CARD_DETECT(ACMD42)

V CC(VSD )CMD

DAT3/CD-pull -down> 270kΩExact value depends
on required logic levels

SD Memory Card

DAT0

Optional :2-additional channels
of IP4252 CZ16-8

10 kΩ - 90 kΩ

DAT3/CD
DAT2

CD

WP

Optional :Card Detect switch

Optional :Write Protect switch

Fig 6.

Application diagram of IP4252CZ12-6 and IP4252CZ16-8 in a SD-memory card interface

AN10911

Application note

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SD(HC)-memory card and MMC interface conditioning

The implementation of write protection contact is only possible in applications supporting
standard-size SD-memory cards. Smaller form-factor versions such as miniSD or
microSD do not support this feature. In case the mechanical slider mechanism of thestandard-size SD-memory card is used, a pull-up resistor is connected to the host supply
and a mechanical contact to ground. This contact is open until a WP slider is closing it(mechanical adaptors converting a micro or mini SD-memory card into a standard
SD-card size typically do not support this feature).

VCC(VSD)

Pull -up resistors
10 kΩ – 100 kΩ

to host interface

IP4252 CZ16-8

DAT1

DAT1
DAT0
CLK
CMD

DAT0

SD Memory Card

GND

DAT3/CD
DAT2
CD

CLK
VCC (V SD )WP
CMD
DAT3/CD
DAT2

CD

WP

Fig 7.

Application diagram of IP4252CZ16-8 using a mechanical card-detect switch

In case a mechanical card detection switch is not possible to apply (for example, due tosize constraints for the card holder), an electrical card detection can be used but only for
an SD-memory card interface.
After power-up DAT3/CD is connected to a 50 k (nominal value, specified range is 10 k
to 90 k) pull-up resistor inside the card. In case DAT3/CD is connected to a high-ohmic
pull-down resistor, the connected host can detect a logic level change from low to highlevel1. The card internal pull-up resistor should be disconnected during regular datatransmission with SET_CLR_CARD_DETECT (ACMD42) command.

1.

It is recommended that pull-down resistor is >270 k to fulfill the logic voltage level requirements. The exact value depends on the
logic level requirements.

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Rev. 2 — 4 April 2013

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Figure 8 shows a diagram for this implementation.

VCC(VSD)
Optional electrical
Card Detect
Pull-up resistors
10 kΩ – 100 kΩ

host interface

IP4252CZ12-6

SD Memory Card

DAT1

DAT1
DAT0
CLK
CMD

DAT0
GND

DAT3/CD
DAT2

SET_CLR_CARD_DETECT(ACMD42)

CLK
VCC(V SD )50 kΩpull-up

CMD
DAT3/CD
DAT3/CD-pull-down> 270 kΩ,Exact value depends
on required logic levels

Fig 8.

DAT2

Application diagram of IP4252CZ12-6 using electrical card detection

For the latest 8-bit MMC interface, 10 channels have to be ESD-protected andEMI-filtered. A combination of IP4252CZ8-4 (4-channel) and IP4252CZ12-6 (6-channel) is
best-matching filter combination to cover the full interface (see Figure 9).

V CC(VMMC)

CMD Pull-up
resistor see text

Pull-up resistors
50 kΩ – 100 kΩ

IP4252 CZ12-6
DAT1
DAT0
DAT7
DAT6

DAT1

host interface

CLK

C7

VSS2

C6

CLK

C5

V CC
(VMMC )

C4

VSS1

C3

CMD

C2

DAT3

C1

DAT5

CMD
DAT4
DAT3
DAT2

C8
DAT7

C13

DAT6

C12

DAT5

C11

DAT4

C10
C9

IP4252 CZ8-4

Fig 9.

DAT0

DAT2

Application schematic diagram of IP4252CZ12-6 and IP4252CZ8-4 in an 8-bit MMC interface

AN10911

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SD(HC)-memory card and MMC interface conditioning

5.2 MicroSD card ESD protection and EMI filter device IP4340CX15
The IP4340CX15 is a 6-channel microSD card ESD protection and EMI filter device with 5
additionally integrated pull-up resistors in a tiny 0.4 mm ball pitch CSP.
The only channel without a pull-up resistor is the clock channel (see Figure 10). Due tothe pull-up resistor implementation, the electrical card detection method cannot be used.
Detection using a mechanical switch is mandatory.
The maximum filter channel capacitance is 14 pF which makes the device suitable to workin high clock speed applications, too.
Table 12.

IP4340CX15 electrical parameters

Symbol Parameter

Conditions

VI

input voltage

VESD

electrostatic discharge
voltageMin

Typ

Max Unit

0.5 -+5.0 V

15

+15

kV

IEC 61000-4-2, level 4, pins on
microSD card side
contact discharge

-

15

-

+15

kV

Rs(ch)

channel series resistance R1 to R6

36

40

44



Rpu

pull-up resistanceR9 to R12

40

50

60

k

R13

12

15

18

k

including diode capacitance;
VI = 0 V; f = 1 MHz;VCC = GND

8

11

14

pF

air discharge

Cline

line capacitance

VCC

R13

R12

R11

R10

R9
R1

CLK

SDCLK
R2

CMD

SDCMD
R3

DATA0

SDDATA0R4DATA1SDDATA1R5DATA2SDDATA2R6DATA3SDDATA3

GND

aaa-003575

Fig 10. Schematic view for IP4340CX15

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SD(HC)-memory card and MMC interface conditioning

5.3 Very highly integrated memory card interface device IP4350CX24
The IP4350CX24 demonstrates the highest level of integration, consisting of ESD
protection, EMI filter and biasing resistors in a passive device. As the package is a 0.4 mm
pitch CSP type, the total device size is only 1.95  2.11 mm2.
This device fully supports high-speed memory card interfaces working with clock speed
up to 52 MHz.
A special diode structure using a rail-to-rail (also known as “crow-bar”) diode concept on
the high-level ESD protection side in combination with single diodes on the low-level ESD
protection side guarantee a balanced distribution of the channel capacitance. This leads
to symmetrical EMI filter performance which is independent from the read/write direction.
IP4350CX24 supports electrical card detection of an SD-memory card using the pins
DAT3_PD and R21 connected to GND. Figure 11 shows detailed schematic with the driverand control circuitry required to use electrical card detection. Electrical card-detect isavailable as long as the “control” inverter output is low and 'driver_pu' is 3-stated, so R21
is acting as a pull-down to GND.
If normal operation is needed, the “control” inverter drives a high signal to enable the'driver _pu' buffer, drives a high signal at R11 and also drives R21 to a high level to avoid
any unnecessary quiescent current.
The maximum voltage at the pin to the host interface may exceed the host supply voltage
as it is derived from: V SD   R 11   R 11 + R DAT3  CD pu   . In this case a voltage tolerant
input has to be selected.
If electrical card detection is not required, DAT3_PU (R11) should be connected to VSD
instead.
Since the CMD line is connected to the pull-up resistor R15, which is typically 15 k,IP4350CX24 can also be used in combination with an MMC. The MMC can be initializedusing a 400 kHz open-drain mode.
The channels for the mechanical WP, CD and the combined WP+CD require an additional
pull-up resistor which is not integrated. Often pull-up resistors integrated into the GPIOs of
the host processor are used for this purpose as they can be switched off after detection.
The lower CMD pull-up resistor value and lower total line capacitance value make theIP4350CX24 an excellent match for MMC interfaces in case a compliance with the latest
standard specification is mandatory.
Three additional channels support any configuration of CD and WP switches for thevarious memory card holders (see Figure 11).
The most important electrical parameters are listed in Table 13.

AN10911

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SD(HC)-memory card and MMC interface conditioning

Table 13.

IP4350CX24 electrical parameters

Symbol ParameterVI

input voltage

VESD

electrostatic discharge
voltageRs(ch)Cch

AN10911

Application note

Conditions

Typ

Max Unit

0.5 -+5.0 V

contact discharge

8

-

+8

kV

air discharge

15

-

+15

kV

IEC 61000-4-2, level 4
SDxxx pins to GND

12

15

18



R11 to R14

35

50

65

k

R15

3.29 4.7

6.11 k

R21

329

470

611

k

each data channel fromSD card to I/O interface

-

8.8

-

pF

CLK channel

-

7.8

-

pF

channel series resistance R1 to R9channel capacitanceMin

including diode capacitance;
VI = 0 V; f = 100 kHz

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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Nexperia

AN10911

Application note

IP4352CX24
DAT3_PU driver:
tri-stated for card detection
HIGH level during operation

IP4350CX24VCC(VSD)SD Memory Card

DAT3_PU
DAT1

PU driverControl

DAT3_PD:
LOW level for card detection
HIGH level during operation

R12

R13

R14

R15
R4

SDDATA1DATA0R3SDDATA0

R1

SDCLK

CMD

R2

SDCMD

DATA3

R6

SDDATA3DATA2R5SDDATA2

CD

R7

SDCD

WP

R8

SDWP

WP+CD

R9

SDWP+CD

DAT3_PD

GND
CLK

CLK

(microSD)

DAT0

VCC(VSD)

50 kOhm
pull-up
SET_CLR_CARD_DETECT(command ACMD42)

CMD
DAT3/CD
DAT2

R21
WP

GND_H

host side

Fig 11. IP4350CX24 connected to an SD-memory card using electrical card-detect

GND_C

connector side

AN10911© Nexperia B.V. 2013. All rights reserved.

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SD(HC)-memory card and MMC interface conditioning

Rev. 2 — 4 April 2013

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Card detect signal
or
DATA3 during operation

R11
DATA1

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Nexperia

AN10911

Application note

IP4352CX24

optional
electricalcard detect

IP4350CX24VCC(VSD)

DAT3_PU
DAT1

R11

R12

R13

R14

R4

DATA1

SDDATA1

DAT0
GND

R3

SDDATA0

CLK

R1

SDCLK

CMD

R2

SDCMD

DATA3

R6

SDDATA3DATA2R5SDDATA2

CD

R7

SDCD

WP

R8

SDWP

WP+CD

R9

SDWP+CD

CLK
VCC(VSD)
CMD
DAT3/CD
DAT2

R21
CD

WP

GND_C

GND_H

host side(microSD)

connector side

Fig 12. IP4350CX24 connected to an SD-memory card using mechanical card-detect

AN1091124 of 27

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SD(HC)-memory card and MMC interface conditioning

Rev. 2 — 4 April 2013

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DATA0

DAT3_PDSD Memory Card

R15

AN10911

Nexperia

SD(HC)-memory card and MMC interface conditioning

6. Conclusion
Nexperia offers a comprehensive portfolio of SD-memory card and MMC compatible
interface conditioning and protection devices.
These devices are optimized for compliance with their respective memory card interface
in terms of channel capacitance, serial resistance and biasing resistor values.
Passive devices explained in this document protect from destruction from system level
ESD and also prevent disturbance of, for example wireless interfaces, from the harmonics
of the digital memory interfaces. Integrated biasing resistors contribute to gain the
maximum space savings comparing to discrete solutions.
All devices presented support a simple PCB layout, reduce the risk of EMI due to complex
layout of scattered discrete components and allow to minimize compliance testing.
The high integration level and the final test of each device before shipment also improve
the overall quality. The integrated protection and filter components reduce the number ofindividual components, solder joints and pick-and-place processes.

7. References

AN10911

Application note[1]

SD specifications, part 1, Physical Layer Specification version 2.00, May 9, 2006

[2]

Multi Media Card System Specification version 4.3, JESD84-A43, November 2007

All information provided in this document is subject to legal disclaimers.

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8. Legal information
8.1

Definitions

Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included
herein and shall have no liability for the consequences of use of suchinformation.

8.2

Disclaimers

Limited warranty and liability — Information in this document is believed tobe accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy orcompleteness of such information and shall have no liability for theconsequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outsideof Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost profits,
lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with theTerms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes toinformation published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-criticalsystems or equipment, nor in applications where failure or malfunction of an
Nexperia product can reasonably be expected to result in personal injury,
death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products insuch equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. Nexperia makes norepresentation or warranty that such applications will be suitable for the
specified use without further testing or modification.

Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability forany assistance with applications or customer product design. It is
customer’s sole responsibility to determine whether the Nexperia product issuitable and fit for the customer’s applications and products planned, as well
as for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards tominimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for thecustomer’s applications and products using Nexperia products in order toavoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Evaluation products — This product is provided on an “as is” and “with all
faults” basis for evaluation purposes only. Nexperia, its affiliates and their
suppliers expressly disclaim all warranties, whether express, implied or
statutory, including but not limited to the implied warranties of
non-infringement, merchantability and fitness for a particular purpose. The
entire risk as to the quality, or arising out of the use or performance, of thisproduct remains with customer.
In no event shall Nexperia, its affiliates or their suppliers be liable tocustomer for any special, indirect, consequential, punitive or incidental
damages (including without limitation damages for loss of business,business interruption, loss of use, loss of data or information, and the like)arising out the use of or inability to use the product, whether or not based on
tort(including negligence), strict liability, breach of contract, breach of warranty
or any other theory, even if advised of the possibility of such damages.
Notwithstanding any damages that customer might incur for any reason
whatsoever (including without limitation, all damages referenced above andall direct or general damages), the entire liability of Nexperia, its affiliates
and their suppliers and customer’s exclusive remedy for all of the foregoingshall be limited to actual damages incurred by customer based onreasonable reliance up to the greater of the amount actually paid bycustomer for the product or five dollars (US$5.00). The foregoing limitations,exclusions and disclaimers shall apply to the maximum extent permitted byapplicable law, even if any remedy fails of its essential purpose.

8.3

Trademarks

Notice: All referenced brands, product names, service names andtrademarks are the property of their respective owners.

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9. Contents
1
2
2.1
2.2
2.3
2.4
2.5
3
3.1
3.2
3.3
4
5
5.1

5.1.1
5.2
5.3
6
7
8
8.1
8.2
8.3
9

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
SD-memory card electrical interface . . . . . . . . 4
SD-memory card and microSD card interfaces 4
Bus operation conditions . . . . . . . . . . . . . . . . . 5
SD-memory card bus timing conditions . . . . . . 8
Capacitive load at the interface conditioning
device output . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SD-memory card-detect mechanism . . . . . . . 11
MMC electrical interface . . . . . . . . . . . . . . . . . 11
Bus operating conditions . . . . . . . . . . . . . . . . 11
Bus timing conditions . . . . . . . . . . . . . . . . . . . 13
Capacitive load at the interface conditioning
device output . . . . . . . . . . . . . . . . . . . . . . . . . 13
SD-memory card and MMC interface
comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Passive ESD protection and EMI filter
devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ESD protection EMI filter devices in plastic
package IP4252CZ8-4, IP4252CZ12-6,
IP4252CZ16-8 . . . . . . . . . . . . . . . . . . . . . . . . 16
Application details of IP4252CZ12-6 andIP4252CZ16-8 . . . . . . . . . . . . . . . . . . . . . . . . 17
MicroSD card ESD protection and EMI filter
device IP4340CX15 . . . . . . . . . . . . . . . . . . . . 20
Very highly integrated memory card interface
device IP4350CX24 . . . . . . . . . . . . . . . . . . . . 21
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Legal information. . . . . . . . . . . . . . . . . . . . . . . 26
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.

© Nexperia B.V. 2013.

All rights reserved.

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to:salesaddresses@nexperia.com
Date of release: 4 April 2013
Document identifier: AN10911