AN90009

Leakage of small-signal MOSFETs
Rev. 1.0 — 8 November 2019

application note

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Content

Keywords

Leakage current, small-signal MOSFET

Abstract

Description of current leakage behavior for small-signal MOSFETs. Examples for typical gatesource and drain-source leakage of MOSFETs is shown. Distinguish between ESD protected andunprotected devices.

AN90009

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Leakage of small-signal MOSFETs

1. Introduction
Device current leakage is an important factor for the energy consumption of a circuit application.
This is especially true for mobile electronic devices such as smart phones, tablets, wearables ormedical devices as the off-state current leakage may influence battery life and therefore operation
time. The scope of this application note is the current leakage description of a small-signal trench
MOSFET in different pin configurations.

2. Leakage currents
The following chapters are related to the pin configurations drain-source (D-S) andgate-source (G-S) as illustrated in Fig. 1 below.
D

D
G

VDS

±VGS

±VGS
S

aaa-030427

a. ESD protected small signal MOSFET
Fig. 1.

VDS

G
S

aaa-030428

b. Non protected small signal MOSFET

Illustrated pin configuration for device leakage
For gate-source leakage it is important to distinguish between ESD protected MOSFETs and nonprotected ones. Due to the presence of additional ESD protection circuit the VGS to IGS leakage
characteristic of such a device is different while the drain-source characteristic is independent fromthis constructional feature.

2.1. Drain-source leakage
For an enhancement mode MOSFET in the off-state (VGS = 0 V), the drain-source leakage is given
by a p-n junction diode in reverse direction. In the ideal case this is given by the rectifier equation:(1)
Where V is the applied voltage, q the electronic charge, k the Boltzmann constant and T theabsolute temperature. V > 0 represents the diode in reverse direction with a remaining IS, (the socalled saturation current):(2)

with the cross-section area A, the diffusion coefficients of holes and electrons Dp, Dn, the donor andacceptor concentrations ND, NA, the intrinsic carrier concentration ni and the carrier lifetime of holes
and electronstp .

It can be seen that the ideal description of the leakage is independent from the applied voltage.
The leakage increases with the cross section area A and therefore the channel width which is
proportional to the Xtal size if the same technology is used. The larger the Xtal the higher the
leakage.

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Leakage of small-signal MOSFETs
In practice an additional current is added to the ideal saturation current which is increased at higher
reverse voltage applied. (Moll, 1958) Reasons for this component are:•••Surface leakage and inversion layers
Body defects
Generation and recombination
aaa-030429

10-3
ID
(A)
10-4

VDS(max)

10-5
IDSS(max)

10-6
10-7

PMCM6501VPE
10-8
PMCM4401VPE
10-9
10-10

Fig. 2.

0

5

10

15

VDS (V)

20

Drain-source ID leakage current as a function of drain-source voltage for
PMCM4401VPE and PMCM6501VPE at Tj = 25 °C

The drain-source leakage as a function of drain-source voltage is given by Fig. 2. Both types
have a specified maximum voltage of 12 V with a safety margin up to the breakdown voltage
of approximately 17 V when avalanche occurs. Specified maximum value for IDSS leakage at
maximum drain source voltage specified is 1 μA however in reality for small signal MOSFET thiscurrent is significantly below this standardized limit. Due to the larger chip size by a factor of 2.3 thePMCM6501VPE has an increased leakage which is related to the higher channel width describedin equation (2). Even for the larger chip the real leakage is more than one order of magnitude awayfrom the specification limit.
The saturation current IS is temperature dependent. In case of silicon the recombination andgeneration of carriers is increased above room temperature leading to increased leakage. This
relation is given as example for PMCM4401VNE in the figure below:
aaa-030430

10-4
ID
(A)
10-5

aaa-030431

10-4
ID
(A)
10-5

150 °C
10-6

10-6

10-7

10-7
70 °C

10-8
10-9
10-10

10-8
10-9

25 °C

0

5

10

15

20
25
VDS (V)a. As a function of drain-source voltage; VGS = 0 V
Fig. 3.

10-10

0

25

50

75

100

125

150
175
Tj (°C)b. As a function of junction temperature;
VDS = 12 V, VGS = 0 V

Drain-source leakage current of PMCM4401VNE

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Leakage of small-signal MOSFETs

2.2. Gate to Source leakage
An unprotected MOSFET has an electrically isolated gate with very small leakage from gate tosource while a protected MOSFET shows the typical leakage curve of a bidirectional Zener diode.
Fig. 4 below shows the gate-source leakage current of the ESD protected BSS138BK and theunprotected BSS138P. Both types are specified with a maximum gate to source voltage of 20 V.
Channel width and gate oxide are equal.
aaa-030432

0.001

aaa-030433

10-4
IG
(A)
10-5

IG
(A)
0.0008

BSS138BK

10-6
BSS138BK

0.000610-7
10-8

0.0004

BSS138P

10-9

BSS138P

10-10

0.0002

10-11
0

0

10

20

30

10-12

40
50
VDS (V)a. Gate-source current as a function of drain-source
voltageFig. 4.

0

10

20

30

40
50
VGS (V)b. Gate-source current as a log function of gatesource voltage

Gate-source leakage current of ESD protected BSS138BK and non protected BSS138P
It can be seen that where minimizing gate-source leakage is essential an unprotected MOSFET
gives the best choice over a wide voltage range. The Zener diode of a protected device is a tradeoff between ESD protection and device gate-source leakage. It is designed in a way that theclamping voltage is lower than the oxide breakdown voltage to protect the ESD most vulnerable
part of the MOSFET and higher than the specification to keep the leakage at a minimum over
specified range. Due to the poly-crystalline construction of the Zener diode the leakage below
breakdown voltage is still higher compared to a single crystal diode. The gate leakage temperaturedependency for the Zener diode is similar to a silicon p-n junction. The following figure shows anincrease in leakage for higher temperature. The leakage of an un-protected MOSFET remains
almost constant in the same temperature range.
aaa-030434

10-5
IGS
(A)

150 °C

10-6

70 °C
25 °C

10-7

10-8

10-9

10-10

0

2

4

6

8

10

VGS (V)

12

VGS(max)= 8 V
Fig. 5.

Gate-source leakage current of an ESD protected MOSFET at different junction temperatures

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Leakage of small-signal MOSFETs

3. Applications
Normally, when selecting a MOSFET for an application, the typical selection criteria are things
like VDS voltage, RDSon, gate threshold voltage and so on. With the ongoing trend towards battery
driven and even energy harvesting based applications, other performance criteria such as leakage
start to be become more important.
There are several use-case scenarios where ultra-low leakage of a MOSFET is a key parameterand one of the first things a designer looks at when selecting the component.

3.1. Load switch
When powering an application from a finite power source such as a battery, designers often
implement so called low power modes of operation. Most modern microcontrollers feature several
levels of low power operational modes. Nevertheless, to get the lowest possible application
standby power, the best way is still to simply power everything down while leaving a small fractionof the circuit powered up to handle detection for waking back up. The whole application operates
then in a PWM mode of operation. It is powered off most of the time, while only waking up
periodically.
The common method to implement this powering-up and down is to use a load-switch that(dis)connects the circuit power from the battery. Many load-switch IC solutions exist, often offering
additional features such a current limit, in-rush limit and more. Still, the simplest way to implementa load-switch function is to use a MOSFET. Refer to Fig. 6. Here we see a high-side switch
implemented with a P-channel MOSFET.

Battery
R1P-channel MOSFET

Application
Power Plane

R2

CTRL

N-channel MOSFET

aaa-030435

Fig. 6.

Load-switch using MOSFETs

One of the nice “side-effects” of using a MOSFET for this function is that the leakage current canbe very low. Clearly when implementing a switch to turn some circuit completely off, you would
want that switch to be as high Ohmic as possible, i.e. the leakage current between source anddrain should approximate zero as much as possible.
Per Fig. 6 a separate N-channel MOSFET is often used to control the P-channel MOSFET. A
high level on the gate of the N-channel MOSFET will pull the gate of the P-channel MOSFET low
and turn it on (connecting battery to the application power plane). Here we see another importantleakage path, the one from the control drive line via the gate of the N-channel to either Source or
Drain. For optimal application standby time an N-channel MOSFET with very low gate leakage
is required. Resistors R1 and R2 are used to further optimize leakage levels. Their values are a
trade-off between lowest leakage levels obtainable, VGS switch levels reachable and switching
speed of the load-switch circuit.

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Leakage of small-signal MOSFETs

3.2. General purpose logic
For those applications that require the absolute lowest leakage, it may actually be better toimplement basic logic functionality (such as gates) using discrete MOSFETs. While not very
commonplace, this is sometimes required in applications using energy harvesting as their only
source of power.
The exact circuit implementation dictates what is required, but refer to Fig. 7, where a basic
discretely build inverter is shown (simplified). Clearly, for lowest possible system level leakage,gate-source and drain-source leakage are important here.

P-channel MOSFETIN

OUT
N-channel MOSFET

aaa-030436
Fig. 7.

Inverter using MOSFETs (simplified)

4. Selecting a low leakage MOSFETThe data as shown in this note elaborates on the (physical) background of leakage in MOSFETs.
To help with selecting the right product for low leakage applications, we can summarize this asfollows:••••

As the drain-source voltage across the MOSFET gets closer to the maximum specified VDS
there is a risk of significantly increased channel leakage. Hence the need to stay away from the
maximum specified VDS
At higher temperatures, leakage goes up significantly and not the same for all MOSFETs. Low
threshold parts will see a bigger increase
With rising temperature, leakage increases. Leakage will increase faster in low VGS(th) devices
Gate protection structures cause an increase to gate leakage.

Combining all of the above, we can argue that the highest chance for lowest possible leakage is toselect a device that:
1. Has a max VDS that is at least twice as high the highest VDS that will be seen in the application
2. Has the highest acceptable VGS(th) to help minimize leakage increases at higher temperature
3. Does not have protection on the gate. While not ideal for ESD sensitivity, an unprotected gate
will help keep gate leakage down, especially at elevated temperatures
4. Has the highest acceptable RDSon. While not 100% accurate, if we assume the same process
for two different devices, the type with the lower RDSon has a larger die size, and hence willshow a (minimally) higher leakage.
In all cases Nexperia can only guarantee the limit as per specification.

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Leakage of small-signal MOSFETs

5. Nexperia low leakge MOSFET portfolio
The market shows a large and growing interest in MOSFETs with a low leakage specification for
IDSS and IGSS due to an increasing number of battery-driven applications in the market such as
wearables, Bluetooth trackers, wireless measurement devices, computing accessories, e-meteringand smoke detectors. In applications that are required to have a long battery life time, althoughdriven by a small coin-cell, every additional leakage current has to be avoided.
Nexperia introduced a low leakage MOSFET portfolio depicted in Table 1 below. The space saving
leadless packages DFN1006-3, DFN1006B-3 and DFN1010B-6 have been chosen to support
compact board designs. The height of DFN1006-3 is 0.48 mm, DFN1006B-3 and DFN1010B-6
have a reduced height of 0.37 mm only. In DFN1006 single FETs as 20 V P-channel and N-channel
version are available. The DFN1010 variants are dual-FETs containing a dual N-channel, a dual
P-channel or a complementary pair. Using the complementary PMCXB900UEL allows for a very
compact load switch, with the topology of a high-side switch shown in Fig. 6. For small batterydriven applications, the load currents are normally not very high so that an RDSon of about 1 - 2
Ohms is fully sufficient.
Table 1. Low leakage current MOSFET portfolio
Type name
Polarity
VDS
VGS

ID

RDSon @
VGS = 4.5 V

RDSon @
VGS = 2.5 V

RDSon @
VGS =1.8 V

(V)

(V)

(A)

(mΩ)

(mΩ)

(mΩ)

Package

PMZ600UNEL

N

20

8

0.6

470

620

845

DFN1006-3

PMZB600UNEL

N

20

8

0.6

470

620

845

DFN1006B-3

PMZ950UPEL

P

20

8

0.5

1020

1270

1700

DFN1006-3

PMZB950UPEL

P

20

8

0.5

1020

1270

1700

DFN1006B-6

PMDXB600UNEL

dual N

20

8

0.6

470

620

845

DFN1006B-6

PMDXB950UPEL

dual P

20

8

0.5

1020

1270

1700

DFN1006B-6

PMCXB900UEL

N

20

8

0.6

470

620

845

DFN1006B-6

P

20

8

0.5

1020

1270

1700

DFN1006B-6

The maximum leakage for the drain -source path is reduced from 1 µA down to 25 nA specified for
VDS equal 5 V. The gate-source leakage limit is lowered from 10 µA to 50 nA for a gate voltage of
1.8 V.
Table 2. Comparison of maximum leakage current ratings between standard and low leakage
MOSFETs
Standard typeLow leakage type

AN90009

application note

IDSS(max)

1 μA

25 nA @ VDS = 5 V

IDSS(max)

10 μA

50 nA @ VDS = 1.8 V

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6. References
Moll, J. L. (1958). The Evolution of the Theory for the Voltage-Current Characteristic of P-N
Junctions. Proceedings of the IRE (Volume:46 , Issue: 6 ), 1076 - 1082.

7. Revision history
Table 3. Revision history
Revision
Date
numberDescription

1.0

AN90009 initial version

2019-11-08

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warranties as to the accuracy or completeness of information included hereinand shall have no liability for the consequences of use of such information.

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Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with theTerms and conditions of commercial sale of Nexperia.
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or warranty that such applications will be suitable for the specified use
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Customers are responsible for the design and operation of their applications
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Leakage of small-signal MOSFETs

List of Tables
Table 1. Low leakage current MOSFET portfolio................. 7
Table 2. Comparison of maximum leakage current
ratings between standard and low leakage MOSFETs.........7
Table 3. Revision history......................................................8

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List of Figures
Fig. 1. Illustrated pin configuration for device leakage......... 2
Fig. 2. Drain-source ID leakage current as a functionof drain-source voltage for PMCM4401VPE andPMCM6501VPE at Tj = 25 °C.............................................3
Fig. 3. Drain-source leakage current of PMCM4401VNE.....3
Fig. 4. Gate-source leakage current of ESD protected
BSS138BK and non protected BSS138P............................ 4
Fig. 5. Gate-source leakage current of an ESD
protected MOSFET at different junction temperatures.........4
Fig. 6. Load-switch using MOSFETs....................................5
Fig. 7. Inverter using MOSFETs (simplified)........................ 6

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Leakage of small-signal MOSFETs

Contents
1. Introduction................................................................... 2
2. Leakage currents..........................................................2
2.1. Drain-source leakage...................................................2
2.2. Gate to Source leakage...............................................4
3. Applications.................................................................. 5
3.1. Load switch..................................................................5
3.2. General purpose logic................................................. 6
4. Selecting a low leakage MOSFET............................... 6
5. Nexperia low leakge MOSFET portfolio...................... 7
6. References.................................................................... 8
7. Revision history............................................................8
8. Legal information......................................................... 9© Nexperia B.V. 2019. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 8 November 2019

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