P02
Low-Power Super-Lattice Phase-Change Memory without Melting andWrite-Pulse Down Slope
Koh Johguchi, Toru Egami and Ken Takeuchi
Department of Electrical, Electronic, and Communication Engineering, Chuo University, Tokyo, JapanI.

Introduction

Phase change memory (PCM) is one of the promising candidates for the next generation storage memory
due to its high speed and low energy consumption [1]. A Ge2Sb2Te5 (GST) film is often used as the phasechange material and requires proper heat control because the quenching speed determines amorphization(RESET) or crystallization (SET). Therefore, it is important for a PCM to control the pulse down slope, which
is difficult due to large BL parasitic parameters. Additionally since Joule heating is used to change the state,
the thermal disturb [2] and the electro-migration (EM) due to large write-current are critical issues for thereliability of scaled devices. Thus a super-lattice PCM (SL-PCM) has been developed for further scaling andreliable operation [3-6]. In SL-PCM, a meta-material structure composed of GeTe and SbTe layers is used forthe phase change material, and SET or RESET operations are carried out by Ge atom flip-flop transition [4, 5].
Therefore, the SL-PCM is not melted during phase change and unnecessary energy consumption, which is aspreviously dissipated as Joule heating, can be saved.

II. Measurement results

Fig. 1 depicts the experimental comparison results between the conventional GST- and SL-PCMs. The
measurement results show that the energy dissipation of SL-PCM is less then ×0.1-×0.01 that of theconventional GST due to the efficient resister switching. Fig. 2(a) shows the SET pulse width (Tpw)
dependence of a 300-nm SL-PCM device. 100 ns pulse width is needed for SET complete. Although SET iscomplete when Tpw > 100 ns, the optimum SET condition is Tpw = 100 ns since too long SET pulse causes
large energy dissipation. Fig. 2(b) gives the pulse slope dependency of SET operation. If Tf is too long, notonly the energy is wasted but the resistance may change to RESET state again after SET complete (SETdisturb) unlike the conventional Ge2Sb2Te5 PCM. In other word, too long pulse slope causes SET failure [8].
Therefore, for SL-PCM, the pulse slope becomes a factor contributing to disturb in SET operation. From thisresult, it is found that SL-PCM does not melt during SET [4, 5] and the conductivity of SL-PCM is caused notby Joule heating but by Ge-atom transition. In addition, the retention-time is measured at high-temperature
10M SL-PCM

Resistance [Ω](This work)

Normal GST(Conv.)

1M

10-100
smallercurrent

100k

10k
10-4
0.000110-30.001-2
100.01

SET/RESET current [A]Fig. 1 SET/RESET characteristics of SL-PCM and the conventional GST.

(HT = 85 ºC) to evaluate the reliability of SL-PCM. Even at HT, over 105 sec of data retention time is achieved.
The read disturb problem is also verified with Vread = 0.3 V and Tread = 100 ns. From the measurement results,
the read disturb is insignificant for data retention.

300 nm device, V1 = 1.3 V, Tpw = 100 ns

10M

5.000.E-04
500

1M300
200

100k

1.000.E+05

100
10k0100 200 300 400 500

1.000.E+04
0.000.E+00
0.0E+00 1.0E-07 2.0E-07 3.0E-07 4.0E-07 5.0E-070Tpw [ns]10M5001.000.E+07

5.000.E-04

400
1M

1.000.E+06

300
200

100k

1.000.E+05

100
10k

1.000.E+04
0.0.E+00

05.0.E-0850

1.0.E-07100

1.5.E-07

150

SET current [µA]4001.000.E+06

SET current [µA]

Resistance [Ω]1.000.E+07

Resistance [Ω]300 nm device, V1 = 1.3 V, Tf = 1 ns

0200

0.000.E+00
2.0.E-07

Tf [ns](a)(b)
Fig. 2 (a) SET pulse width (Tpw) and (b) pulse down slope (Tf) dependence with Tpw = 100 ns.
III. Conclusions

A low power, high reliability SL-PCM is measured and investigated. The measurement results show that thepulse falling edge of SET is ineffective and that SET is not dependent on Joule heating. This result suggests thestate transition of SL-PCM is carried out not by melting, but by a Ge flip-flop, which can provide low-power
operation and simpler write circuit with reliability. Moreover, the temperature dependencies of SL-PCM areinvestigated. As the temperature rises, the conductivity increases which makes the SET operation easier while
the RESET condition becomes more difficult. Positive retention-time and read-disturb test results also indicate
potential as a future storage device.
Acknowledgement
This work was done in “Ultra-Low Voltage Device Project" of LEAP and supported by METI and NEDO

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