AN90034
Rev. 1.2 — 30 April 2024

Application note

Nexperia Precision Electrothermal models in
SPICE and VHDL-AMS for Power MOSFETs

Abstract:

This application note introduces Nexperia electrothermal MOSFET models. Details are provided on how
to use them in simulations. Simulation results for key MOSFET characteristics are included.

Keywords:

Electrothermal, SPICE, VHDL-AMS, simulation, modelAN90034

Nexperia

Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs

1. Introduction
Nexperia provides MOSFET electrothermal models that link the electrical and thermal
performance. The models are available in SPICE and VHDL-AMS for multiple simulation platform
support. They represent all the key MOSFET behaviours relevant to MOSFET applications. As
such it is possible to estimate device performance quickly and accurately within widely available
simulation tools before any physical prototyping. By using the latest MOSFET models errors can be
spotted and designs can be optimised for cost and performance much earlier in the design cycle
and changes can be implemented timelier, thus improving time to market. This application note
introduces the models, how to use them, what their capabilities and limitations are, and where tofind them.
The models will be available in “families” of devices – that is one model file will contain all the
products of a given technology and voltage rating. For example, the Trench9 40 V Standard Level
Automotive portfolio is one such model family. Importing the model file to your simulation tool
should give access to all the device models i.e., each RDSon value in each package type within thatfamily. The simulation tool used will vary how this works e.g., LTspice™ or PSpice.

2. Importing models in LTspice™
Download the electrothermal model ZIP file from Nexperia.com, e.g. BUK7xxxx-40H_LTspice. The
ZIP file contains the library file and symbol. The model can be viewed in a text editor, here theproduct models included can be seen in Fig. 1.
First place the provided symbol on the schematic, the easiest way is to have the symbol in thesame directory as the schematic and then it is accessible via the component library and bychanging the Top Directory to the local directory, see Fig. 2.
The easiest way is to link the symbol to the full library is to use the “.inc” command and point to
the file. If the file is saved in the same location as the simulation, then only filename is needed,otherwise, the full file path is required. Finally change the value “NMOS_5Pin” to any of the models
listed library file, for example “BUK7S1R0-40H”, see Fig. 3.

Fig. 1.

LTspice™ library file showing devices modeled within

AN90034
Submit document feedback

All information provided in this document is subject to legal disclaimers.

Application note

Rev. 1.2 — 30 April 2024

© Nexperia B.V. 2024. All rights reserved

2 / 18

AN90034

Nexperia

Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs

C:\Users\Username\LTSpice_projects

C:\Users\Username\LTSpice_projects

Fig. 2.

Adding the symbol to a schematicFig. 3.

Pointing a symbol to the model file

3. Using Models in Part Quest Explore
The models are also available in VHLD-AMS format which is supported by PartQuest™ Explore(https://explore.partquest.com). Here, the models are available within the partner library and areready to be used with no additional set-up.
Further examples of models and simulations using PartQuest™ Explore can be found on Nexperia’s
Interactive Application Notes (https://www.nexperia.com/applications/interactive-app-notes).

Fig. 4.

Nexperia’s new Precision Electrothermal models found in the partner library within
PartQuest™ Explore

AN90034
Submit document feedback

All information provided in this document is subject to legal disclaimers.

Application note

Rev. 1.2 — 30 April 2024

© Nexperia B.V. 2024. All rights reserved

3 / 18

AN90034

Nexperia

Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs

4. 5 pin MOSFET model
The electrothermal models have 5 pins, the 3 traditional electrical pins for Gate, Drain, and Source
and two additional pins for interacting with the thermal properties of the MOSFET, see Fig. 5.
These are namely the junction temperature pin, Tj and the mounting-base pin, Tmb. Tj can beprobed like a voltage node and gives the junction temperature (1 V is equivalent to 1 °C). In
addition, this pin can be connected to a fixed voltage source to set the junction temperature as aconstant, this disables the self-heating behaviour of the model, Fig 6 a). Otherwise, it can be left
open and monitored.

Fig. 5.

Schematic symbol of the 5-pin electrothermal MOSFET model

Tmb represents the thermal connection of the device to the outside world e.g., the heat path fromthe mounting base of the MOSFET to a PCB or heatsink. This pin can also be connected to a fixedvoltage source, this will set the ambient temperature, Fig 6 b). In addition, thermal models of PCBs
can be connected to the MOSFET Tmb pin model to simulate the system thermal performance,
Fig. 7.

a. setting an ambient temperature
Fig. 6.

Interacting with the thermal pins

Fig. 7.

Adding an external thermal network

AN90034
Submit document feedback

All information provided in this document is subject to legal disclaimers.

Application note

Rev. 1.2 — 30 April 2024

b. fixing the junction temperature to a
constant© Nexperia B.V. 2024. All rights reserved

4 / 18

AN90034

Nexperia

Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs

5. Model behaviour
The following characteristics may be modelled using the 5 pin electrothermal MOSFET model:
•
•
•
•
•
•
•
•
•
•

Gate-source threshold voltage (VGSth) as a function of junction temperature (Tj)
RDSon as a function of VGS and temperature
Output characteristics (ID as a function of VD) vs temperature
Transfer characteristics (ID as a function of VGS) vs temperature
Diode forward characteristics (VSDS) as a function of temperature
Drain source leakage (IDSS) as a function of temperature
Breakdown voltage (BVDSS) as a function of temperature
Internal capacitances as a function of drain-source voltage
Diode reverse recovery
Package related parameters

Where possible an example circuit is shown to demonstrate each behaviour. For each of thefollowing examples the Tj pin will be shorted to Tmb, turning off the self-heating.
Note: the characteristics are always typical values and do not represent the limits ofprocess variation.
The device used in the simulations is BUK7S1R0-40H a 40 V, 1 mΩ power MOSFET in the
LFPAK88 package. It is from the Trench9 40 V Standard Level Automotive portfolio.

AN90034
Submit document feedback

All information provided in this document is subject to legal disclaimers.

Application note

Rev. 1.2 — 30 April 2024

© Nexperia B.V. 2024. All rights reserved

5 / 18

AN90034

Nexperia

Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs

5.1. Threshold voltage, ID / VGS sweep
The ID / VGS sweep fixes the VDS and sweeps the VGS, turning the MOSFET on, the resultant
drain current (ID) is probed. Set-up of the ID / VGS sweep is shown in Fig. 8 which also shows theambient temperature is stepped.

Fig. 8.

DC sweep

Value

Unit

Source

V2

-

Start

0

V

Stop

5.5

V

Step

0.1

V

ID / VGS schematic and simulation parameters

The waveforms in Fig. 9 shows two operating regimes, the sub-threshold slope and the transfer
characteristic.
aaa-034839

400

ID

ID

10

(A) 10

(A)
300

1
10
T j = 175 °C

100

T j = 175 °C

-1

25 °C
-55 °C-2

10-55 °C

25 °C

-3

10

-4

0

a. linear scaleFig. 9.

2

10

200

0

aaa-034840

3

2

4

V GS (V)

6

10

0

2

4

V

GS

(V)

6

b. log scale

Drain current as a function of gate-source voltage; simulation results

AN90034
Submit document feedback

All information provided in this document is subject to legal disclaimers.

Application note

Rev. 1.2 — 30 April 2024

© Nexperia B.V. 2024. All rights reserved

6 / 18

AN90034

Nexperia

Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs

5.2. RDSon
RDSon is measured with a fixed current source typically 25 A but may be less for smaller die. The
VGS is stepped in the same manner as ID vs VGS. The simulation set-up is in Fig. 10. Fig. 11 shows
the RDSon vs VGS, this can be derived by dividing the drain-source voltage (VDS) by the ID.

DC sweep

Value

Unit

Source

V2

-

Start

0

V

Stop

20

V

Step

0.1

V

Fig. 10. RDSon schematic and simulation parameters
aaa-034841

5

R DSon

(mΩ)
4

3

2
Tj =
175 °C1
025 °C-55 °C
0

5

10

15

20

V

GS

(V)

25

Fig. 11. RDSon as a function of VGS; simulation results

AN90034
Submit document feedback

All information provided in this document is subject to legal disclaimers.

Application note

Rev. 1.2 — 30 April 2024

© Nexperia B.V. 2024. All rights reserved

7 / 18

AN90034

Nexperia

Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs

5.3. Output characteristics (ID / VDS)
Here VGS is held constant and VDS is stepped. This is repeated for different VGS values. The ID isprobed. The schematic set-up is shown in Fig. 12 and resultant waveforms are shown in Fig. 13.
DC sweep 1

Value

Unit

Source

V3

-

Start

0

V

Stop

2

V

Step

0.01

V

DC sweep 2

Value

Unit

Source

V2

-

list

-

-

1st value

4.0

V

2nd value

4.5V

3rd value

5.0

V

4th value

10

V

Fig. 12. ID / VD schematic and simulation parameters
aaa-034842

400
10 V

ID

V GS = 5 V

(A)
300

200
4.5 V
100
4V
0

0

0.5

1

1.5

V DS (V)2

Fig. 13. ID as a function of VDS; simulation results

AN90034
Submit document feedback

All information provided in this document is subject to legal disclaimers.

Application note

Rev. 1.2 — 30 April 2024

© Nexperia B.V. 2024. All rights reserved

8 / 18

AN90034

Nexperia

Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs

5.4. Diode characteristics (VSDS)MOSFETs have an anti-parallel diode within the structure, as such it conducts when the sourcedrain voltage (VSD) reaches the forward voltage drop (VF) of the diode. This is also temperaturedependent; the diode’s VF decreases with temperature and its slope resistance increases. Fig. 14
shows the test set-up and Fig. 15 shows the simulated charts.

DC sweep 1

Value

Unit

Source

V2

-

Start

0

V

Stop

-1

V

Step

-0.01

V

Fig. 14. VSDS diode forward schematic and simulation parameters
aaa-034843

0
ID
(A)
-100

T j = -55 °C

25 °C

175 °C

-200

-300

-1.2

-0.8

-0.4

V DS (V)0Fig. 15. Diode VF simulation results

5.5. Body Effect
In many half-bridge applications, the MOSFET may replace the free-wheeling diode to achieve
synchronous rectification. The MOSFET’s RDSon produces a lower voltage drop Drain to Source
than the diode’s VF so power loss is reduced making the application more efficient. However,
MOSFETs conducting current through the channel in reverse, such as in synchronous rectification,
will have lower threshold voltage. This is known as the Body Effect and is accounted for in themodels operating with negative VDS and ID. The Body Effect is also sometimes referred to as third
quadrant operation.
Fig. 16 shows the simulation set-up for observing the Body Effect and Fig. 17 shows both the first
and third quadrant of operation. The first quadrant is ID / VD as previously shown and in the third
quadrant when the VGS = 0 is the diode curve. However, Fig. 17 also shows operating in the third
quadrant with a positive VGS and the increased ID due to the Body Effect.

AN90034
Submit document feedback

All information provided in this document is subject to legal disclaimers.

Application note

Rev. 1.2 — 30 April 2024

© Nexperia B.V. 2024. All rights reserved

9 / 18

AN90034

Nexperia

Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs

DC sweep 1

Value

Unit

DC sweep 2

Value

Unit

SourceV3-

Source

V2

-

Start

-1.0

V

list

-

-

Stop

2.0

V

1st value

0

V

Step

0.1

V

2nd value

3.0

V

3rd value

3.2

V

4th value

3.4V

5th value

3.6V

6th value

3.8V

7th value

4V

8th value

10

V

Fig. 16. Body Effect schematic and simulation parametersID

aaa-034844

200

st

1 Quadrant(8)(A) 100

(7)

0

(1)
(2)

-100

(3)
(4)

-200

(5)
(6)
(7)

-300
-400
-500

(8)
3 rd Quadrant

-1

-0.5

0

(1) VGS = 0 V (VSDS)(2) VGS = 3.0 V(3) VGS = 3.2 V(4) VGS = 3.4 V(5) VGS = 3.6 V(6) VGS = 3.8 V(7) VGS = 4.0 V(8) VGS = 10 V

VDS (V)

0.5

Fig. 17. Full quadrant operation of a MOSFET showing ID / VD, VSDS and the Body Effect; simulation results

AN90034
Submit document feedback

All information provided in this document is subject to legal disclaimers.

Application note

Rev. 1.2 — 30 April 2024

© Nexperia B.V. 2024. All rights reserved

10 / 18

AN90034

Nexperia

Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs

5.6. Drain leakage (IDSS), breakdown voltage (BVDSS) and avalanche
breakdown
Included in the model are temperature dependant drain leakage current and breakdown voltage. In
addition, the slope resistance of avalanche breakdown is modelled. Fig. 18 is the simulation set up
and Fig. 19 shows the simulation results.

DC sweep 1

Value

Unit

Source

V3

-

Start

0

V

Stop

55

V

Step

0.05

V

Fig. 18. IDSS, BVDSS and avalanche breakdown schematic and simulation parameters
aaa-034845

500

ID

ID

(A)

(A)
400

Tj =
-55 °C
25 °C

300

aaa-034846

10 3
10

Tj =
-55 °C
25 °C

10 -1
175
°C

10

200

175
°C

-3

-5

10
100

0

10

0

a. linear scale

20

40

VDS (V)

60

10

-7

-9

0

20

40

V DS (V)60

b. log scaleFig. 19. Avalanche breakdown; ID as a function of VDS simulation results

AN90034
Submit document feedback

All information provided in this document is subject to legal disclaimers.

Application note

Rev. 1.2 — 30 April 2024

© Nexperia B.V. 2024. All rights reserved

11 / 18

AN90034

Nexperia

Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs

5.7. Capacitances and gate charge
Capacitances
The MOSFET’s internal parasitic capacitances and their voltage dependence is modelled. Thisis critical for accurate switching time simulations and gate charge modelling. The capacitancevalues have insignificant temperature dependence so in the model they are fixed with respect
to temperature. The gate charge does have some temperature dependence; the Miller plateau
voltage is dependent on the gain of the MOSFET which in turn is temperature dependant. To
simulate the capacitance values, refer to Fig. 20 and Fig. 21 and the resultant waveforms in
Fig. 22.

+

V1 - Pulse

Value

Unit

oﬀ

0

V

on

36

V

delay

0.99m

s

Rise me12m

s

Fall me1s

On me1sPeriod1sTransient

Value

Unit

Stop me12m

sTime tostart saving
data

1m

s

Fig. 20. Coss and Crss schematic and simulation parameters

V6 - Pulse

Value

Unit

oﬀ

0

V

on

-36

V

delay

0.99m

s

Rise me12m

s

Fall me1s

On me1sPeriod1sTransient

Value

Unit

Stop me12m

sTime tostart saving
data

1m

s

Fig. 21. Ciss schematic and simulation parameters

AN90034
Submit document feedback

All information provided in this document is subject to legal disclaimers.

Application note

Rev. 1.2 — 30 April 2024

© Nexperia B.V. 2024. All rights reserved

12 / 18

AN90034

Nexperia

Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs
10

aaa-034847

2

Capacitance
(nF)
10

C iss

Coss

1

C rss
-1

10

10 -1

1

10

V DS (V)102

Fig. 22. Capacitances as a function of VDS; simulation results

Gate charge
Fig. 23 shows the gate charge set-up and by probing the Vgs node one can see the Vgs charging
with respect to time. To determine the gate charge, use the relationship in Equation (1), the gate
current IG is determined by the settings of Ig1 in the schematic set-up. The result of this is shown in
Fig. 24.

Q = IG · t

V1 - Pulse

Value

Unit

I1 - Pulse

(1)

Value

Transient

Value

Unit

Stop me120usTime tostart saving
data

10u

s

Unit

Ig1 - Pulse

Value

Unit

0

A

oﬀ

5

V

oﬀ

0

A

oﬀ

on

0

V

on

25

A

on

1m

A

10u

s

delay

10u

s

delay

0

s

delay

Rise me1ns

Rise me

1ms

Rise me

1n

s

1n

s

Fall me1nsFall me1ms

Fall meOn me10s

On me1s

On me1mssPeriod2msPeriod100sPeriod1

Fig. 23. Gate charge schematic and simulation parameters

AN90034
Submit document feedback

All information provided in this document is subject to legal disclaimers.

Application note

Rev. 1.2 — 30 April 2024

© Nexperia B.V. 2024. All rights reserved

13 / 18

AN90034

Nexperia

Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs
aaa-034848

12
VGS
(V)
8

4

0

0

40

80

Q G (nC)

120

Fig. 24. Gate charge simulation results

5.8. Body diode reverse recovery charge (QRR)
QRR is not solely dependent on the MOSFET but on the test circuit too. Specifically, the strayinductances of the PCB are critical in determining the QRR behaviour. As such it is difficult torepresent the QRR in a simulation with a great accuracy without knowing or characterising the test
bench being compared to the simulation. In addition, there are two standard methods of measuring
QRR that will again yield different results. The preferred method for testing QRR is the double pulse
method which more closely aligns with application uses cases, for example half-bridge topologies
such as DC-to-DC convertors and motor drives.
Further information about simulating the QRR in a double pulse set-up is detailed in Nexperia
application note AN90011. Further to this our paper SPICE models for predicting EMC performanceof a MOSFET based half-bridge configuration details how to use the new models and double pulse
simulations to predict Electromagnetic interference (EMI) behaviour before any physical testing,helping to mitigate errors sooner in the design cycle saving time and cost.
Fig. 25 shows an example QRR waveform.

ID

aaa-034849

16

(A)
12

8

4
0

-4

0

0.1

0.2

0.3

0.4

0.5

time (µs)

0.6

Fig. 25. Diode reverse recovery (QRR) simulation results

AN90034
Submit document feedback

All information provided in this document is subject to legal disclaimers.

Application note

Rev. 1.2 — 30 April 2024

© Nexperia B.V. 2024. All rights reserved

14 / 18

AN90034

Nexperia

Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs

5.9. Package related parameters
Impedances due to the packaging are modelled, these include resistances associated with theclip and lead frame and solder interconnects etc. The package resistance also changes withtemperature. Further to this the parasitic inductance is included in the model. This is critical for
simulating for EMI investigations.

6. Comparing models to data sheet
Nexperia electrothermal models are based on a scalable model that takes a trend line across theparameters and die sizes in each portfolio. This means the model represents the mean device, but
the data sheet represents a typical device that may not necessarily be the mean. So, whilst themodel may not match the data sheet exactly, it will always be within part-to-part variation for thatparameter. In general there is good alignment between the simulations and the data sheet.
A second factor where models may deviate from the data sheet is due to self-heating effects that
occur on measurements. Some measurements such as diode-forward characteristics and output
characteristics generate a lot of power in the device. Whilst the measurements are taken in as
short a time possible the pulse is a finite period and self-heating will always occur.
Fig. 26 shows the difference caused by the self-heating within the VSDS simulation. The self-heating
is causing a drop in the VF as the power increases allowing more current to flow for a given VDS.
aaa-034936

0
ID
(A)
-100

without self-heatingwith self-heating

-200

-300

-0.8

-1.2

-0.4

V DS (V)0Fig. 26. VSDS self-heating effects

7. Simulation tips and tricks
Whilst we endeavour to make the models as stable as possible some simulations may notconverge, here are some tips and tricks:•••

When using current sources to drive the pins of the model, placing a resistor to ground from theoutput of the current source may help, start at 1.0E9 Ω first, and go down in decades
Changing the tolerances may help, SPICE is originally targeted at ICs with low currents sodecreasing the tolerance may be acceptable for power electronics simulations
In LTspice™ specifically using the alternate solver is often more successful in achieving
convergences

AN90034
Submit document feedback

All information provided in this document is subject to legal disclaimers.

Application note

Rev. 1.2 — 30 April 2024

© Nexperia B.V. 2024. All rights reserved

15 / 18

AN90034

Nexperia

Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs

8. Full simulation validity range
Table 1 shows the range over which the models are valid.
Table 1. Range over which the models are valid
Characteristics
Operating condition range

Temperature range

RDSon

VDS = -1.2 V to 8.0 V; VGS = 0 V to
VGS(max)-55 °C to 175 °C

ID/VG

VDS = 0 V to 8.0 V-55 °C to 175 °C

ID/VD

VDS = 0 V to 8.0 V-55 °C to 175 °C

VSDSID ≤ pulsed drain current limit (IDM)-55 °C to 175 °C

BVDSS

ID ≤ pulsed drain current limit (IDM)-55 °C to 175 °C

QG and capacitancefull data sheet voltage range-55 °C to 175 °C

not temperature dependant

QRR

VDS = 0.5 x VDSmax-55 °C to 175 °C

not temperature dependant

Thermal impedance (Zth)NA-55 °C to 175 °C

worst case value as per data
sheet

IDSS

VDS = 0 to BVDSS-55 °C to 175 °C

IGSS

NA

NA

Comments

not modelled

9. Summary
Nexperia's new electrothermal MOSFET models have been introduced and their use in LTspice™
simulations have been demonstrated. Electrothermal models will feature in future interactive
application notes, please visit the Nexperia website to learn more: https://www.nexperia.com/
applications/interactive-app-notes/.

10. Revision history
Table 2. Revision history
Revision
Date
numberDescription

1.2

2024-04-30

Document updated to the latest Nexperia template. Minor text correction in Section 4.

1.1

2023-10-09

Fig. 20 updated.

1.0

2022-04-08

Initial version.

AN90034
Submit document feedback

All information provided in this document is subject to legal disclaimers.

Application note

Rev. 1.2 — 30 April 2024

© Nexperia B.V. 2024. All rights reserved

16 / 18

AN90034

Nexperia

Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs

11. Legal information
Definitions
Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included hereinand shall have no liability for the consequences of use of such information.

Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for theconsequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outsideof Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removalor replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with theTerms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-criticalsystems or equipment, nor in applications where failure or malfunctionof an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products insuch equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability forany assistance with applications or customer product design. It is customer’ssole responsibility to determine whether the Nexperia product is suitableand fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards tominimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for thecustomer’s applications and products using Nexperia products in order toavoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.

Trademarks
Notice: All referenced brands, product names, service names andtrademarks are the property of their respective owners.

AN90034
Submit document feedback

All information provided in this document is subject to legal disclaimers.

Application note

Rev. 1.2 — 30 April 2024

© Nexperia B.V. 2024. All rights reserved

17 / 18

AN90034

Nexperia

Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs

Contents
1. Introduction................................................................... 2
2. Importing models in LTspice™.................................... 2
3. Using Models in Part Quest Explore...........................3
4. 5 pin MOSFET model................................................... 4
5. Model behaviour........................................................... 5
5.1. Threshold voltage, ID / VGS sweep.............................. 6
5.2. RDSon........................................................................... 7
5.3. Output characteristics (ID / VDS).................................. 8
5.4. Diode characteristics (VSDS)........................................ 95.5. Body Effect.................................................................95.6. Drain leakage (IDSS), breakdown voltage (BVDSS)
and avalanche breakdown................................................. 115.7. Capacitances and gate charge..................................125.8. Body diode reverse recovery charge (QRR)............... 14
5.9. Package related parameters......................................15
6. Comparing models to data sheet..............................15
7. Simulation tips and tricks..........................................15
8. Full simulation validity range.................................... 16
9. Summary..................................................................... 16
10. Revision history........................................................16
11. Legal information......................................................17© Nexperia B.V. 2024. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 30 April 2024

AN90034
Submit document feedback

All information provided in this document is subject to legal disclaimers.

Application note

Rev. 1.2 — 30 April 2024

© Nexperia B.V. 2024. All rights reserved

18 / 18