TN90001

LFPAK MOSFET thermal resistance Rth(j-a) simulation, test
and optimisation of PCB layout
Rev. 1.0 — 17 May 2018

Technical note

Document information

Information

Content

Keywords

LFPAK, MOSFET, thermal resistance, simulation, PCB design

Abstract

This technical note considers the thermal modeling of Nexperia LFPAK MOSFETs. Different
Printed Circuit Board materials and layouts are considered.

TN90001

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LFPAK MOSFET thermal resistance Rth(j-a) simulation, test and optimisation of PCB layout

1

Introduction
MOSFET data sheets contain a parameter Rth(j-a) which is the thermal resistance fromjunction to ambient. This is a guide to how much heat can be dissipated from the device
to its surroundings in a typical application. For a surface-mounted device such as an
LFPAK MOSFET this is highly dependent on the type of Printed Circuit Board (PCB) on
which it is mounted. The type of PCB material, the thickness of copper and the shape ofthe copper footprint all contribute to Rth(j-a).
This technical note looks at the structure of an LFPAK MOSFET and the way it ismounted on a PCB. It uses thermal modelling techniques to analyse how heat, generated
inside the device, is transferred to its surroundings. Various circuit layouts are considered
and tested so that developers can use an accurate value for Rth(j-a) that closely reflects
practical applications.

2

Definition of Thermal Resistance Rth(j-a)
Rth(j-a) is the thermal resistance from working surface of the silicon crystal to thesurrounding environment. It is a value that represents the net effect of all the possible
series and parallel paths from the semiconductor junction to ambient and includes heattransfer by means such as conduction, convection and radiation.
Rth(j-a) is defined as the temperature difference between junction and ambient thattransfers one watt of power to the environment. It is given by:where:
Rth(j-a) is measured in K/W
Tj is the junction temperature (°C)
Ta is the ambient temperature (°C)
P is the heating power dissipated inside the MOSFET (W)TN90001

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LFPAK MOSFET thermal resistance Rth(j-a) simulation, test and optimisation of PCB layout

3

Test method
The method used to measure Rth(j-a) is defined by JEDEC standard 51-2A. The Device
Under Test (DUT) is soldered to a FR4 test board and placed in the geometric centreof the test enclosure as shown in Figure 1 and Figure 2. The enclosure comprisesa 305 mm cube made from low thermal conductivity materials such as cardboard,polycarbonate, polypropylene, wood, etc.

Figure 1. Test enclosure - left side view

Figure 2. Isometric view of the PCB and test fixture

3.1 Heat transfer in the JEDEC enclosure
Within the JEDEC enclosure, heat is transferred from the DUT to the PCB andsurroundings by three basic mechanisms; conduction, convection and radiation.
Conduction is the process by which heat transfers from high temperature parts to lowtemperature parts that are in contact with each other. Figure 3 shows how heat istransferred from the semiconductor junction to the copper clip and from the clip to theencapsulant. Also, from the junction through the silicon die to the mounting base, andfrom the mounting base to the PCB.
Convection refers to the heat transfer process caused by displacement of air surrounding
the test fixture. The movement is caused by the tendency of hotter and therefore less

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LFPAK MOSFET thermal resistance Rth(j-a) simulation, test and optimisation of PCB layout
dense air to rise, and colder, denser air to sink under the influence of gravity, whichconsequently results in transfer of heat.
Radiation does not depend on contact as heat conduction and convection do. Thermalradiation is when an object loses energy in the form of electromagnetic radiation from theinfrared part of the spectrum. In the example shown in Figure 3, heat is radiated from thesurfaces of the MOSFET and the PCB into the space inside the box.

Figure 3. LFPAK MOSFET - heat transfer model

The measured thermal resistance of a MOSFET, Rth(j-a), depends upon the package size,
the material properties and the internal structure of the device. It also depends on the
PCB that is used in the test fixture. Modern surface-mount MOSFETs are designed touse the PCB as a heat sink and rely on the copper traces to spread the heat over a large
area to assist with cooling.
SMD Power MOSFET data sheets usually specify two values for Rth(j-a) – one with aminimum footprint that conforms with the JEDEC standard, and another with a 25.4 mm
square of 70 µm thick copper on the top surface.
Table 1. Rth(j-a) specification in a data sheet

SymbolRth(j-a)Parameter
thermal resistancefrom junction toambient

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Technical note

Conditions

Min

Typ

Max Unit

2

Mounted on a 25.4 mm square copper, 70 μm
thick, FR4 1.5 mm thick PCB

-

50

-

K/W

Mounted on a minimum footprint, 70 μm copper,
FR4 1.5 mm thick PCB

-

125

-

K/W

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LFPAK MOSFET thermal resistance Rth(j-a) simulation, test and optimisation of PCB layout

4

MOSFET drain-source current pathModern power MOSFETS have an ‘on’ resistance in the order of milliohms andsurface-mount variants are capable of switching hundreds of Amperes. In these cases
consideration must be given to the Joule heating effect of the current as it flows throughthe device and also the PCB traces.
Figure 4, below, shows the current path through a LFPAK MOSFET. The clip is attacheddirectly to the semiconductor junction and at low current it acts as a heat sink, conducting
heat away from the junction to the PCB. At high current, however, it becomes heatedby its own resistance and requires cooling by being connected to a cooling surface
connected to the source.

Figure 4. LFPAK package MOSFET current path shown

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LFPAK MOSFET thermal resistance Rth(j-a) simulation, test and optimisation of PCB layout

5

PCB trace width calculations
To examine the heating effect of the PCB trace let us consider as an example a Nexperia
LFPAK MOSFET, PSMN1R0-30YLD. This has an ‘on’ resistance of 1 milliohm and at a2
2
typical current of 55 A the power dissipation, given by I R will be 55 x 0.001 = 3 W. Thisis easily dissipated by the PCB if it has a small amount of copper to spread the heat.
If we use the IPC2221 trace width calculator to work out the size of trace required tocarry 55 A and allow a manageable 30 °C rise in the trace temperature, then assuming
70 µm (2 oz) thick copper, Figure 5 shows that a trace almost 20 mm wide is required.

Figure 5. IPC-2221 trace width calculator

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LFPAK MOSFET thermal resistance Rth(j-a) simulation, test and optimisation of PCB layout

6

Board layout optimisation
A number of thermal simulations have been carried out using a PSMN1R0-30YLD as an
example to find the optimum PCB layout that extracts the maximum amount of heat fromthe device and therefore gives the lowest possible value for Rth(j-a). All the simulations
were on a 25.4 mm square of 70 µm thick copper. The MOSFET was fully turned on witha constant current that produced 3 W loss in the device.
The investigation examined different positions of the MOSFET within the copper square.
It also considered allocating different percentages of the copper square to the sourceand drain. Finally, it examined the heating effect of trace width on the temperature of the
MOSFET and the consequences for Rth(j-a) measurement.

6.1 Test layout 1
In Figure 6 and Figure 7, the device is mounted on the edge of a 25.4 mm square copperpad.
Rth(j-a) = 41.8 K/W according to the simulation result.
This layout assumes that the main heat transfer path is from the junction, throughthe silicon die to the mounting base. All of the copper pad is allocated to cooling themounting base. We see from the thermal profile that very little heat reaches parts of thecopper furthest away from the MOSFET and these contribute little to the cooling. The
source trace is very hot because of inefficient cooling of the source pins. This is evidently
not an optimum solution resulting in a relatively high value for Rth(j-a).
Table 2. Test layout 1 and surface temperature profile

Figure 6. Test layout 1

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Technical note

Figure 7. Surface temperature profile

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LFPAK MOSFET thermal resistance Rth(j-a) simulation, test and optimisation of PCB layout

6.2 Test layout 2
The test layout of Figure 8 and Figure 9 shows the MOSFET mounted in the middle ofthe 25.4 mm copper square with the copper area divided equally between source anddrain.
The simulation result gives Rth(j-a) = 39.1 K/W
Placing the device in the middle of the copper has improved the cooling and reduced
the thermal resistance. However, the copper area connected to the drain tab is hotter
than that connected to the source pins which suggest that more heat flows through thedrain tab. Selecting the proper ratio of source to drain copper is important to obtain the
optimum Rth(j-a) value.
Table 3. Test layout 2 and surface temperature profile

Figure 8. Test layout 2

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Technical note

Figure 9. Surface temperature profile

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LFPAK MOSFET thermal resistance Rth(j-a) simulation, test and optimisation of PCB layout

6.3 Test layouts 3, 4 and 5
In Figure 10, Figure 11, Figure 12, Figure 13, Figure 14 and Figure 15 different layouts
examine the effect of various trace widths for the source connection.
Layout 3 has the MOSFET located in the centre of the copper pad and the Joule heating
effect of the source trace is not considered.
The simulated result gives Rth(j-a) = 38.6 K/W
Table 4. Test layout 3 and surface temperature profile

Figure 10. Test layout 3

Figure 11. Surface temperature profile

But in a practical working circuit when low RDSon MOSFETs are fitted, the drain-source
current can reach tens or even hundreds of Amperes, and the heat generated in the PCB
traces cannot be neglected.
Test layout 4 shows what happens when the Joule heating of the source trace is taken
into account. In this case the trace width is 0.8 mm. The power loss in the MOSFET
is 3 W as before, but the power loss in the trace is 8.8 W. Figure 13 shows the rise intemperature of the source trace which is higher than the die temperature of the MOSFET
and is therefore heated significantly.
The simulated Rth(j-a) is 92.4 K/W

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LFPAK MOSFET thermal resistance Rth(j-a) simulation, test and optimisation of PCB layout
Table 5. Test layout 4 and surface temperature profile

Figure 12. Test layout 4

Figure 13. Surface temperature profile

Test layout 5 has the source trace increased to 3 mm. The test conditions are the sameas in layout 4. This time the power loss in the source trace is reduced to 2.4 W but Figure
15 shows that the temperature still exceeds that of the die.
The simulated result for Rth(j-a) is 56.7 K/W.
Table 6. Test layout 5 and surface temperature profile

Figure 14. Test layout 5

Figure 15. Surface temperature profile

We can deduce from test layouts 4 and 5 that in a practical application involving an
LFPAK MOSFET careful consideration must be given to trace thickness and width so that
the Joule heating of the current path does not contribute to the heating of the MOSFET.

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6.4 Optimal circuit board layout 6
Test layout 6, shown in Figure 16, attempts to optimise the copper traces to obtain thelowest possible Rth(j-a). Approximately 1/3 of the 25.4 mm copper pad is allocated to thesource pins whilst the width of the source trace is a maximum.
The simulation result gives Rth(j-a) = 37.1 K/W.
Table 7. Test layout 6 and surface temperature profile

Figure 16. Test layout 6

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Technical note

Figure 17. Surface temperature profile

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LFPAK MOSFET thermal resistance Rth(j-a) simulation, test and optimisation of PCB layout

7

Conclusion
LFPAK MOSFETS are designed to be soldered to a heat sink. In this case the heatsink is formed from the copper traces that make the electrical connections. This meansthat care must be taken in the design of the PCB and the layout of the copper traces
that connect to the MOSFET. This becomes more important as the current handlingcapabilities of MOSFETs increases. It is now possible for a LFPAK MOSFET such as
PSMN1R0-30YLD to carry 300 A and therefore not only the heat sinking properties of thecopper, but the current-carrying capabilities must be taken into account by the designer.

8

Reference documents
PSMN1R0-30YLD data sheet
JEDEC 51-2A
PCB trace width calculator

9

Revision history

Table 8. Revision history

Rev

Date

Description

TN90001 v.1

20180517

Initial version

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10 Legal information
10.1 Definitions
Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included hereinand shall have no liability for the consequences of use of such information.

10.2 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for theconsequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outsideof Nexperia. In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removalor replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory. Notwithstanding any damages that
customer might incur for any reason whatsoever, Nexperia's aggregate andcumulative liability towards customer for the products described herein shallbe limited in accordance with the Terms and conditions of commercial sale of
Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-criticalsystems or equipment, nor in applications where failure or malfunctionof an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products insuch equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification. Customers are responsible for thedesign and operation of their applications and products using Nexperia
products, and Nexperia accepts no liability for any assistance withapplications or customer product design. It is customer’s sole responsibility
to determine whether the Nexperia product is suitable and fit for thecustomer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products. Nexperia does not accept
any liability related to any default, damage, costs or problem which is basedon any weakness or default in the customer’s applications or products, orTN90001

Technical notethe application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using Nexperia products in order to avoid a default of theapplications and the products or of the application or use by customer’s third
party customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above thosegiven in the Recommended operating conditions section (if present) or theCharacteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement isconcluded only the terms and conditions of the respective agreement shallapply. Nexperia hereby expressly objects to applying the customer’s generalterms and conditions with regard to the purchase of Nexperia products bycustomer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, theproduct is not suitable for automotive use. It is neither qualified nor tested inaccordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications. In the event that customer
uses the product for design-in and use in automotive applications toautomotive specifications and standards, customer (a) shall use the productwithout Nexperia's warranty of the product for such automotive applications,use and specifications, and (b) whenever customer uses the product for
automotive applications beyond Nexperia's specifications such use shall besolely at customer’s own risk, and (c) customer fully indemnifies Nexperia
for any liability, damages or failed product claims resulting from customer
design and use of the product for automotive applications beyond Nexperia's
standard warranty and Nexperia's product specifications.
Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.

10.3 Trademarks
Notice: All referenced brands, product names, service names andtrademarks are the property of their respective owners.

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LFPAK MOSFET thermal resistance Rth(j-a) simulation, test and optimisation of PCB layout

TablesTab. 1.
Tab. 2.
Tab. 3.
Tab. 4.

Rth(j-a) specification in a data sheet .................4
Test layout 1 and surface temperature
profile .................................................................7
Test layout 2 and surface temperature
profile .................................................................8
Test layout 3 and surface temperature
profile .................................................................9

Tab. 5.

Tab. 8.

Test layout 4 and surface temperature
profile ...............................................................10
Test layout 5 and surface temperature
profile ...............................................................10
Test layout 6 and surface temperature
profile ...............................................................11
Revision history ...............................................12

Fig. 9.
Fig. 10.
Fig. 11.
Fig. 12.
Fig. 13.
Fig. 14.
Fig. 15.
Fig. 16.
Fig. 17.

Surface temperature profile ...............................8
Test layout 3 ..................................................... 9
Surface temperature profile ...............................9
Test layout 4 ................................................... 10
Surface temperature profile .............................10
Test layout 5 ................................................... 10
Surface temperature profile .............................10
Test layout 6 ................................................... 11
Surface temperature profile .............................11

Tab. 6.
Tab. 7.

FiguresFig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.

Test enclosure - left side view .......................... 3
Isometric view of the PCB and test fixture .........3
LFPAK MOSFET - heat transfer model .............4LFPAK package MOSFET current pathshown ................................................................ 5
IPC-2221 trace width calculator ........................ 6
Test layout 1 ..................................................... 7
Surface temperature profile ...............................7
Test layout 2 ..................................................... 8

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Contents
1
2
3
3.1
4
5
6
6.1
6.2
6.3
6.4
7
8
9
10

Introduction ......................................................... 2
Definition of Thermal Resistance Rth(j-a) ......... 2
Test method .........................................................3
Heat transfer in the JEDEC enclosure ...............3
MOSFET drain-source current path .................. 5
PCB trace width calculations .............................6
Board layout optimisation ..................................7
Test layout 1 ......................................................7
Test layout 2 ......................................................8
Test layouts 3, 4 and 5 ..................................... 9
Optimal circuit board layout 6 ..........................11
Conclusion .........................................................12
Reference documents .......................................12
Revision history ................................................ 12
Legal information .............................................. 13

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section 'Legal information'.

© Nexperia B.V. 2018.

All rights reserved.

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 17 May 2018
Document identifier: TN90001