AN11261

RC Thermal Models

Rev. 5.0 — 18 March 2021

application note

Document information
Information

Content

Keywords

RC thermal, SPICE, Models, Zth, Rth, discrete devices, Foster, Cauer

Abstract

Analysis of the thermal performance of discrete semiconductor devices is necessary to efficiently
and safely design any system utilizing such devices. This application note presents a quick andinexpensive way to infer the thermal performance using a thermal electrical analogy. This method
is applicable to devices such as power MOSFETs, small-signal MOSFETs, diodes and bipolartransistors.

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1. Introduction
The thermal behaviour of discrete semiconductor devices can be predicted using RC thermal
models. The model types presented in this application note are known as Foster and Cauer
models, consisting in networks of resistors and capacitors. Foster and Cauer models are equivalent
representations of the thermal performance of a discrete device and they can be used within a
SPICE environment. This document provides some basic theory behind the principle, and how to
implement Foster and Cauer RC thermal models. For convenience, Foster and Cauer RC thermal
models are referred to as RC models in the rest of this application note. Several methods of using
RC thermal models, including worked examples, will be described.

2. Thermal impedance
RC models are derived from the thermal impedance (Zth) of a device (see Fig. 1). This figure
represents the thermal behavior of a device under transient power pulses. The Zth can begenerated by measuring the power losses as a result of applying a step function of varying time
periods.
A device subjected to a power pulse of duration > ~1 second, i.e. steady-state, has reachedthermal equilibrium and the Zth plateaus becomes the Rth. The Zth illustrates the fact that materials
have thermal inertia. Thermal inertia means that temperature does not change instantaneously. As
a result, the device can handle greater power for shorter duration pulses.
The Zth curves for repetitive pulses with different duty cycles, are also shown in Fig. 1. These
curves represent the additional RMS temperature rise due to the dissipation of RMS power.
To assist this discussion, the thermal resistance junction to mounting base (Rth(j-mb)) from theBUK7S1R0-40H data sheet, has been included in Table 1. The Zth in Fig. 1 also belongs to the
BUK7S1R0-40H data sheet. This graph shows the thermal behaviour of a power MOSFET but thismethod can also be applied for other discrete devices such as diodes or bipolar junction transistor(BJT).
Table 1. Steady state thermal impedance of BUK7S1R0-40H
SymbolParameter
Conditions

Min

Typ

Rth(j-mb)-

0.35 0.4

thermal resistancefrom junction tomounting base

Max Unit
K/W

aaa-028930

1
Zth(j-mb)(K/W)δ = 0.5
10-1

0.2
0.1
0.05

10-2 0.02

single shot

P

δ=

tp
10-3
10-6

Fig. 1.

10-5

10-4

10-3

10-2

10-1

tp
T

t
T
tp (s)

1

Transient thermal impedance from junction to mounting base as a function of pulse duration for the
BUK7S1R0-40H

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3. Calculating junction temperature rise
To calculate the temperature rise within the junction of a semiconductor device with a single active
area (i.e. heat source at the junction), the power and duration of the pulse delivered to the device
must be known. If the power pulse is a square, then the thermal impedance can be read from theZth chart. The product of this value with the power gives the temperature rise within the junction.
If constant power is applied to the device, the steady state thermal impedance can be used i.e. Rth.
Again the temperature rise is the product of the power and the Rth.
For a transient pulse e.g. sinusoidal or pulsed, the temperature rise within the device junction
becomes more difficult to calculate.
The mathematically correct way to calculate Tj is to apply the convolution integral. The calculation
expresses both the power pulse and the Zth curve as functions of time, and use the convolution
integral to produce a temperature profile (see Ref. 2).
(1)
However, this is difficult as the Zth(τ-t) is not defined mathematically.
An alternative way is to approximate the waveforms into a series of rectangular pulse and apply
superposition (see Ref. 1).
While relatively simple, applying superposition has its disadvantages. The more complex the
waveform, the more superpositions that must be imposed to model the waveform accurately.
To represent Zth as a function of time, we can draw upon the thermal electrical analogy andrepresent it as a series of RC charging equations or as an RC ladder. Zth can then be represented
in a SPICE environment for ease of calculation of the junction temperature.

4. Association between Thermal and Electrical parameters
The thermal electrical analogy is summarized in Table 2. If the thermal resistance and capacitanceof a semiconductor device is known, electrical resistances and capacitances can represent them
respectively. Using current as power, and voltage as the temperature difference, any thermal
network can be handled as an electrical network.

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Table 2. Fundamental parameters
Type
Resistance
Potential

EnergyCapacitanceElectrical(R = V/I)

R = resistance(Ohms)

V = PD (Volts)

I = current(Amps)

C = capacitance(Farads)

Thermal(Rth = K/W)

Rth = thermal
resistance (K/W)

K = temperature
difference (Kelvin)

W = dissipatedpower (Watts)

Cth = thermal
capacitance(thermal mass)

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5. Foster and Cauer RC thermal models
Foster models are derived by semi-empirically fitting a curve to the Zth, the result of which is a
one-dimensional RC network Fig. 2. The R and C values in a Foster model do not correspond togeometrical locations on the physical device. Therefore, these values cannot be calculated fromdevice material constants as can be in other modeling techniques. Finally, a Foster RC modelcannot be divided or interconnected through, i.e. have the RC network of a heat sink connected.
R1

R2

Rn

C1

C2

Cn
aaa-010334

Fig. 2.

Foster RC thermal models

Foster RC models have the benefit of ease of expression of the thermal impedance Zth as
described at the end of Section 2. For example, by measuring the heating or cooling curve andgenerating a Zth curve, Equation 2 can be applied to generate a fitted curve Fig. 3:(2)(3)

Where:The model parameters Ri and Ci are the thermal resistances and capacitances that build up thethermal model depicted in Fig. 2. The parameters in the analytical expression can be optimized
until the time response matches the transient system response by applying a least square fit
algorithm.
The individual expression, “i”, also draws parallels with the electrical capacitor charging equation.
Fig. 3 shows how the individual Ri and Ci combinations, sum to make the Zth curve.
aaa-010335

Zth Curve
overlaid withsummed RC
Zth

RC ModelZth
RC curves,
representing
RC elements
Time

Fig. 3.

Foster RC thermal models
Foster models have no physical meaning since the node-to-node heat capacitances have nophysical reality. However, a Foster model can be converted into its Cauer counter-part by means ofa mathematical transformation (see Ref. 4).
An n-stage Cauer model can be derived from an n-stage Foster model and they will be equivalent
representations of the device thermal performance.

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As seen for the Foster model, the Cauer Model also consists of an RC network but the thermal
capacitances are all connected to the thermal ground, i.e. ambient temperature as represented
in Fig. 4. The nodes in the Cauer Model can have physical meaning and allow access to thetemperature of the internal layers of the semiconductor structure.
R2

R1
C1

C2

Rn
Cn

aaa-031516

Fig. 4.

Cauer RC thermal models

Nexperia provides Foster and Cauer RC models for many of their products on the Product
Information Pages, e.g.
••

BUK7S1R0-40H
BC817K-40H

The models can be found under the tabs “Documentation” and “Support” as shown for
BUK7S1R0-40H in Fig. 5.

Fig. 5.

Nexperia RC thermal model documentation
Foster and Cauer RC thermal models allow application engineers to perform fast calculations of thetransient response of a package to complex power profiles.
In the following sections several examples of using RC thermal models will be presented. Foster
models and Cauer models are equivalent representations of the device thermal behaviour but inthe described examples Cauer models will be used as more representative of the physical structureof the device.
As shown in Fig. 8, a schematic file is available on Nexperia website for BUK7S1R0-40H Cauer
model. Other products may not have this schematic file available and may be provided with a
netlist file for the Cauer network as shown in Fig. 6:

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RC Thermal Models*Part: BUK7S1R0-40H.subckt cauer 1 6 7
R1

1

2

0.00272144

R2

2

3

0.0220255

R3

3

4

0.00713124

R4

4

5

0.185679R5

5

60.182443

C1

1

79.29451e-05

C2

2

7

0.000514739

C3

3

7

0.00195047

C4

4

7

0.00305028

C5

5

7

0.0279554.end cauer
Fig. 6.

BUK7S1R0-40H Cauer model netlist

The netlist describes the same Cauer network as in Fig. 8, and can be used to build the same
schematic. Pin 1 in the netlist can be identified as the junction temperature pin Tj in the schematic.
Similarly pins 6, 7 as the Tamb pins in the schematic.
In order to simulate only the device pins 6 and 7 will both be tied to the ambient voltage source, as
shown in Fig. 8.
However, one of the advantages of using Cauer models is to allow to add external networks
to the device model, for example to model PCBs, heatsinks etc. In order to do so pin 7 will betied to ambient and pin 6 to the first pin of the external Cauer network. For correct results, it isfundamental to make sure that the end pin of the external Cauer network is tied to the ambient
source.

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6. Thermal simulation examples
For highest simulation accuracy, all components losses must be considered, depending on thechosen semiconductor technology:•••

Total losses for MOSFETs: P = (VDS × ID + VGS × IG)
Total losses for BJTs: P = (VCE × IC + VBE × IB)
Total losses for diodes: P = (VF × IF)

6.1. Example 1
RC thermal models are generated from the Zth curve. This example shows how to work back froman RC model and plot a Zth curve within a SPICE simulator. It allows for greater ease when trying
to read values of the Zth curve from the data sheet.
This and subsequent examples use the RC thermal model of BUK7S1R0-40H. Tmb represents
the mounting base temperature. It is treated as an isothermal and for this example it is set as
0 °C. A single shot pulse of 1 W power is dissipated in the device. Referring to Fig. 7; for a single
shot pulse, the time period between pulses is infinite and therefore the duty cycle δ = 0. Then thejunction temperature Tj represents the transient thermal impedance Zth.
P

tp

t
T
aaa-010337

Fig. 7.

Single-shot pulse(4)(5)

Equation 5 demonstrates that with P = 1 W, the magnitude of Zth equates to ΔT.
The following steps are used to set up and run simulations:
1.
2.
3.
4.
5.
6.

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set up the RC thermal model of BUK7S1R0-40H in SPICE as shown in Fig. 8
set the value of voltage source Vmb to 0, which is the value of Tmb
set the value of the current source I1 to 1
create a simulation profile and set the run time to 1 s
run the simulation
Plot the voltage at node Tj

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BUK7S1R0-40H

1
I1

C1
0.00009295

Tj

R1
0.00272144

Tamb
C2
0.000514739

R2
0.0220255

TambC30.0019547

R3
0.00713124

TambC40.00305028

R4
0.185679

Tamb
C50.0279554

R5
0.182443

Tamb
vmb
0

Tamb
.tran 1 uic
aaa-031522

Fig. 8.

BUK7S1R0-40H thermal model setup in SPICE
The simulation result in Fig. 9 shows the junction temperature (voltage at Tj) which is also thethermal impedance of BUK7S1R0-40H. The values of Zth at different times can be read using the
cursors on this plot within SPICE.
aaa-031523

1
Tj
(°C)
10-1

10-2

10-3
10-6

Fig. 9.

10-5

10-4

10-3

10-2

10-1

t (s)

1

A plot of Tj from simulation
The value of the current source in this example is set to 1 A to represent 1 W dissipating throughthe device. It can be easily changed to represent any value of power. The simulation command canbe changed for any duration to represent a range of square power pulses.

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6.2. Example 2
Another method of generating the power profile, is to use measurements from the actual
circuit. This information is presented to the SPICE simulation in the form of a comma-separated
value (CSV) file giving pairs of time/power values. It can be generated either as a summary ofobservations showing the points of change or from an oscilloscope waveform capture.
Two further methods of generating a power profile are discussed. One method is using a PWL
file. The other is to generate the power from a semiconductor device electrical circuit modeled in
SPICE. The former is outlined first.
A source within a SPICE simulator can use a PWL file as an input. The contents of a typical PWL
file is shown in Table 3. It can list the current, voltage or in this example, power over time. Thesefiles can be generated by typing values into a spreadsheet editor and saving as a .csv file, oralternatively exporting waveforms from an oscilloscope. The actual file itself should not contain any
column headings.
To implement this procedure within a SPICE environment, follow the same steps as described in
Section 6.1 “Example 1”, but with the exceptions:
1. Set the property value of the current source to read from a PWL FILE and point it to a .csv filefor example: C:\Pulse file\filepulse.csv, which contains the power profile listed in Table 3
2. Set the mounting base Tmb (Vmb) to 125 °C
3. Set the simulation run time to 0.6 s

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Table 3. Data example for use in a PWL fileTime (seconds)

Power (Watts)

0.000000

00.000001

120

0.004000120

0.004001

24

0.004002

24

0.100000

240.100001

240.10000280

0.200000800.20000280

0.200003

00.300000

00.30000180

0.315000800.315001240.400000

240.400001

00.500000

00.500001

120

0.515000120

0.515001

240.600000

24

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BUK7S1R0-40H

Tj.tran 0.6 uic
PWL file=powerProfile.csv
I1

C1
0.00009295

R1
0.00272144

Tamb
C2
0.000514739

R2
0.0220255

TambC30.0019547

R3
0.00713124

TambC40.00305028

R4
0.185679

Tamb
C50.0279554

R5
0.182443

Tamb
vmb

Tamb

125
aaa-031526

Fig. 10. SPICE circuit implementing a PWL file with the thermal model of the BUK7S1R0-40H
The simulation result is shown in Fig. 11. The junction temperature and thermal impedance values
labeled in Fig. 11 demonstrate that the Zth value at 4 ms, and Rth value, are in line with Fig. 12. It
represents the thermal impedance waveform shown in the BUK7S1R0-40H data sheet.

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aaa-031527

180

Tj
(°C)
150

180

Rth = 0.4 K/Wtemperature

150

120

120
power

90

90

60

60

30

30

0

P
(W)

0

0.1

0.2

0.3

0.4

0.5

0.6

t (s)

0

a) simulation results
aaa-031528

180

Zth = 0.26 K/W

Tj
(°C)
150

temperature

180
150

120

120

90

90

60

60
power

30
0

0

2

4

6

P
(W)

30

8

0
10

t (ms)b) first power pulse
Fig. 11. Simulation results and first power pulse
aaa-028930

1
Zth(j-mb)(K/W)

Rth = 0.4 K/W

δ = 0.5
10-1

Zth = 0.26 K/W

0.2
0.1
0.05

10-2

single shot

0.02

P

δ=

tp

10-3
10-6

10-5

10-4

10-3

10-2

10-1

tp
T

t
T

tp (s)

1

The red lines highlight the thermal resistance and impedance for the example shown in Fig. 11
Fig. 12. Transient thermal impedance for BUK7S1R0-40H

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6.3. Example 3
The aim of this example is to show how to perform thermal simulation using the power profile
generated from a MOSFET circuit.
Following the steps in Section 6.1, set up the thermal model of BUK7S1R0-40H, and set themounting base temperature to 85 °C.
To set the power value in the current source, construct a MOSFET electrical circuit as provided inFig. 13. The power supply is 12 V. The gate drive supply is assigned a value of 10 V. It is set to run
for 50 cycles with a 1 ms period and a 50 % duty cycle.
The power dissipated in the MOSFET can be calculated from Equation 6 or for greater accuracy;
the gate current can be included into the calculation to give Equation 7:(6)
To improve accuracy:(7)
The current source into the thermal model can now be defined as:(8)
Fig. 13 demonstrates the link between the electrical circuit and the thermal model circuit.
BUK7S1R0-40H.tran 50m uic.inc BUK7S1R0-40H.lib
1
B1
I1

Tj
V1

I = V(d)*I(Vd)+V(g)*I(Vg)
C1
0.00009295

R6
10 m

R1
0.00272144

12

Tamb

Vd
C2
0.000514739

R2
0.0220255

0

Tamb
C3
0.0019547

R3
0.00713124

Vg

Tamb

0

C4
0.00305028

R4
0.185679

Tamb

BUK7S1R0-40H
d
Rg
g

M1

s

10

V2

PULSE (0 10 0 1u 1u 0.1m 1m 50)

C50.0279554

R5
0.182443

Tamb
Tamb

vmb1
0
85

aaa-031529

Fig. 13. SPICE circuit illustrating how to integrate an electrical circuit with a thermal model
The resultant plot of Tj is shown in Fig. 14. The maximum temperature of the junction can once
again be calculated from data sheet values by following the steps outlined in Ref. 1.

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aaa-031530

180
Tj
(°C)
150
120
90
60
30

0

0

0.1

0.2

0.3

0.4

t (ms)

0.5

Fig. 14. Inferred junction temperature (Tj) rise provided by Fig. 12

7. Discussions
RC thermal models are not perfect. The physical materials used to build Semiconductors havetemperature-dependent characteristics. These characteristics mean that thermal resistanceis also a temperature-dependent parameter. Whereas in Ohm’s law, the Ohmic resistance isusually considered to be constant and independent of the voltage. So the correspondence
between electrical and thermal parameters is not perfectly symmetrical but gives a good basis for
fundamental thermal simulations.
A further limitation of the models presented is that the mounting base temperature of the device
Tmb, is set as an isothermal. This is rarely the case in real applications where a rise in the mounting
base temperature must be considered. This rise is determined by calculating the temperaturerise due to the average power dissipation (i.e. the heat flow) from the mounting base through toambient. It means that the models are of limited use for pulses greater than 1 s, where heat begins
to flow into the environment of the device. In this situation, the thermal model for the devices, PCB,
heat sink and other materials in proximity must be included.

8. Summary
RC thermal models are available for Nexperia products e.g. power MOSFETs and bipolar discretes
on the Nexperia website. The models can be used in SPICE or other simulation tools to simulate
the junction temperature rise in transient conditions. They provide a quick, simple and accurate
method for application engineers to perform the thermal design.

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9. Abbreviations
Table 4. Key to symbols used in equations
SymbolDescription
P(t)power as a function of time

Zth(t)

transient thermal impedanceRththermal resistancetotal time of heating pulse
thermal time constantRiconstituent thermal resistance element

Ci

constituent thermal capacitance element

Tmbmounting base temperature of the device

Tjjunction temperature of the device

Tj(rise)junction temperature rise in the device

ΔTchange in temperature

Vds

MOSFET drain to source voltage

Vgs

MOSFET gate to source voltage

Id

MOSFET drain current

VCE

BJT collector-emitter voltage

IC

BJT collector curent

VBE

BJT base-emitter voltage

IB

BJT base current

VF

Diode forward voltage

IF

Diode forward current

10. References
1. Application note AN11156 - “Using Power MOSFET Zth Curves”. Nexperia Semiconductors
2. Application note AN10273 - “Power MOSFET single-shot and repetitive avalanche ruggedness
rating”. Nexperia Semiconductors
3. Combination of Thermal Subsystems Modeled by Rapid Circuit Transformation. Y.C.
Gerstenmaier, W. Kiffe, and G. Wachutka
4. JEDEC Standard JESD51-14 Transient Dual Interface Test Method for the Measurement of the
Thermal Resistance Junction-to-Case of Semiconductor Devices with Heat Flow Through aSingle Path

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11. Revision history
Table 5. Revision history
Revision
Date
numberDescription

5.0

20210318

Modifications:• Text updated to include reference to BJT as well as MOSFETs.

4.0

20200511

Modifications:• Section 5 updated to include Cauer model netlist.

3.0

20200504

Modifications:• Updated to include Cauer models.
• Simulations have been updated using latest released technology T9 and replacing
Foster models with Cauer models.
• The format of this application note has been redesigned to comply with the identity
guidelines of Nexperia. Legal texts have been adapted to the new company namewhere appropriate.

2.0

20140519

Second issue.
Modifications:• Fig. 9 is updated.

1.0

20140129

first issue

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12. Legal information
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modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included hereinand shall have no liability for the consequences of use of such information.

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to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for theconsequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outsideof Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removalor replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with theTerms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
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suppliers accept no liability for inclusion and/or use of Nexperia products insuch equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability forany assistance with applications or customer product design. It is customer’ssole responsibility to determine whether the Nexperia product is suitableand fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards tominimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for thecustomer’s applications and products using Nexperia products in order toavoid a default of the applications and the products or of the application or
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RC Thermal Models

List of Tables
Table 1. Steady state thermal impedance ofBUK7S1R0-40H................................................................... 2
Table 2. Fundamental parameters....................................... 3
Table 3. Data example for use in a PWL file....................... 9
Table 4. Key to symbols used in equations....................... 14
Table 5. Revision history....................................................15

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RC Thermal Models

List of Figures
Fig. 1. Transient thermal impedance from junction tomounting base as a function of pulse duration for the
BUK7S1R0-40H................................................................... 2
Fig. 2. Foster RC thermal models........................................4
Fig. 3. Foster RC thermal models........................................4
Fig. 4. Cauer RC thermal models........................................ 5
Fig. 5. Nexperia RC thermal model documentation............. 5
Fig. 6. BUK7S1R0-40H Cauer model netlist........................6
Fig. 7. Single-shot pulse...................................................... 7
Fig. 8. BUK7S1R0-40H thermal model setup in SPICE....... 8
Fig. 9. A plot of Tj from simulation.......................................8
Fig. 10. SPICE circuit implementing a PWL file withthe thermal model of the BUK7S1R0-40H......................... 10
Fig. 11. Simulation results and first power pulse................11
Fig. 12. Transient thermal impedance for BUK7S1R0-40H11
Fig. 13. SPICE circuit illustrating how to integrate anelectrical circuit with a thermal model................................ 12
Fig. 14. Inferred junction temperature (Tj) riseprovided by Fig. 12............................................................ 13

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RC Thermal Models

Contents
1. Introduction................................................................... 2
2. Thermal impedance...................................................... 2
3. Calculating junction temperature rise........................ 3
4. Association between Thermal and Electricalparameters.......................................................................... 3
5. Foster and Cauer RC thermal models........................ 4
6. Thermal simulation examples..................................... 7
6.1. Example 1................................................................... 7
6.2. Example 2................................................................... 96.3. Example 3..................................................................12
7. Discussions.................................................................13
8. Summary..................................................................... 13
9. Abbreviations.............................................................. 14
10. References................................................................ 14
11. Revision history........................................................ 15
12. Legal information......................................................16© Nexperia B.V. 2021. All rights reserved

For more information, please visit: http://www.nexperia.com
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Date of release: 18 March 2021

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