APPLICATION NOTE
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IGBT Basic II
AN-9020/D
SECTION I. GATE DRIVE CONSIDERATIONSIntroduction − IGBT Structure
GATE

EMITTEREMITTER
N−CH.
RS

.
GATE

NPN

RS

NPN

P−

N+

RMODULATIONN−CHANNEL

J3
P+
J2

N− epi. (N− drift)
PNP

PNP

N+

J1

P+ substrate.

COLLECTOR

COLLECTOR

Figure 1. Structure of IGBT

which means the design of the gate drive must be different
depending on the application of each IGBT. For example,
hard−switching applications such as motor drives or UPS,
the switching waveform must ensure that the IGBT’s loci ofoperation do not exceed SOA, and the gate drive parametersmust be set accordingly. This means that it may be necessary
to sacrifice switching speed from the loss of switching aswell as VCE(sat) from the loss of conduction. On the other
hand, in soft−switching applications, there is less burden
from SOA, so it is possible to select a device with VCE(sat) andtf with good char− acteristics, and it is possible to choose thetrade−off between VCE(sat) and tf with gate drive parameter
depending on whether switching loss or on−state loss isgreater. In this chapter, we would like to examine
characteristics of IGBT and gate drive parameter, discuss
the relation− ships between the two, and some issues toconsider in designing a gate drive.

The structure of the IGBT is the combination of the P+
layer added to the MOSFET structure as shown in Figure 1.
The IGBT, constructed by adding the P+ layer, has thecharacteristics of the power transistor (BJT), which has highconductivity in its n−layer by injecting hole into the n−layer
with high resistance. As such, IGBT is easier to drive, andit combines the advantages of MOSFET’s faster switching
speed and power BJT’s lower conduction loss. IGBT is a
useful device in that it overcomes the shortfall of MOSFET
in that it is not suitable for high voltage, high current
applications due to its high conduction loss, while IGBT has
the advantage over power BJT, which has limitations in highfrequency applications due to its switching speed. Demandfor IGBT is increasing in mid to low power applications, andthe applications are becoming more varied, as the capacityof IGBT continues to increase. In order to obtain the
optimum performance from the IGBT with suchcharacteristics, it is of foremost importance to design a gate
drive that is suited for the application. As such, this paper
intends to discuss the characteristics of IGBT and someissues to consider in designing a gate drive as well as
providing necessary information in designing an application
system to help engineers who design systems using IGBT.

IGBT Switching Waveforms

Switching waveform of the IGBT in a circuit under aclamped inductive load (CIL) is shown in Figure 2. This
waveform can be applied to both inverter and chopper
circuits using inductive load. This is a real waveform thatreflects the effects of diode recovery and stray inductance,and principles of their operations will be considered byregion. Consolidated understanding of IGBT’s realapplication switching waveforms and principles ofoperation is necessary in designing an IGBT gate drive.

Gate Drive Considerations

The IGBT can change its switching properties through thegate drive, so designing a proper gate drive is extremely
important to the performance of the IGBT. So−called the“best performance” of the IGBT is different by application,© Semiconductor Components Industries, LLC, 2002

May, 2023 − Rev. 2

1

Publication Order Number:
AN−9020/D

AN−9020/D
Analysis of Turn−on Transient
VGE(t)VGE(t)
VGG+

VGE, Io
VGE(th)0

VCE(t), IC(t)VGG−
VCE(t), IC(t)

VCE

VCE
IC

IC

MOSFET current
VCE(sat)0t0

t1 t2 t3 t4

BJT current
0

t5

t6

t7

t8

t9

(b) Turn−off(a) Turn−on

Figure 2. IGBT Switching Waveforms

LOAD
Ls

Ls

+
23

Vdc
DUT

−

Figure 3. IGBT Switching Test Circuit

The test circuit illustrating the characteristics of IGBT isshown in Figure 3. In addition, Figure 2 shows IGBT
switching waveforms obtained from the test circuit in
Figure 3. IGBT’s turn−on switching waveform is very
similar to MOSFET switching characteristics, and turn−offswitching characteristics are similar as well except IGBT’s
tail current. The following are descriptions of each region
shown in Figure 2 and their principle of operation.

t1 region
As vGE passes VGE(th), a channel is formed on p base region
below the gate oxide, and cur− rent begins to conduct.
During this time, IGBT is in an active region, and iC
increases in relation to vGE, which rises beyond VGE(th). In thisregion, iC increases in relation to the increase in vGE andfinally reaches the full load current (IO). In t1 and t2 region,
the value of vCE appears shaved off compared with the valueof Vd. This is because VLS = LS*diC/dt, which is the volt− ageacross LS as shown in Fig. 2, while iC current increases. The
amount shaved off is related to the size of diC/dt and LS, andits shape changes according to iC pattern.

Turn−on Transient Region
t0 region
This is a region where iG (gate current) charges parasitic
input +capacitance Cge, Cgc, and vGE rises to VGE(th).
Waveform of increasing vGE is shown to be linear, but inreality it is an exponential curve with time constant ofRG(Cge+Cgc). In this region, there is no change in vCE and iC.
Delay time is defined as the time it takes for the gate voltage
to go from 10% of VGG+ to the moment iC becomes 10% of
IO. As such, most of turn−on delay falls in this region.

t2, t3 region
In iD pattern, diode current decreases beginning in the t1
region. However, it does not immediately decrease to 0A,
but there is a reverse recovery, as it flows in the reverse
direction. This current is added to iC current to show the same
pattern as iC in the t2 and t3 region. At this time, voltage

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AN−9020/D
Gate Drive Design Basics

across the diode recovers and increases, while vCE falls, andit falls rapidly as Cgc has small value when vCE has high value.
Due to this phenomenon, dvCE/dt is rather large at this time.
In t3 region, Cgc absorbs and discharges the current from thegate drive and the discharge current from Cge. At the end of
the t3 region, reverse recovery of the diode comes to a close.

IGBT can be made to conduct when appropriate voltage(generally +15V) is introduced to the gate of IGBT, and thecurrent is cut off if vGE is below the threshold voltage (VGE(th),generally, less than 0V). Under the ideal condition, thevoltage should be zero between the collector and the emitter(VCE), and it should be zero in blocking, and its switchingloss is also zero, since IGBT is generally a device that works
in a switch−mode, not as a linear amplifier. Although it is notpossible in reality, a good device should approach these
conditions in operation. In order to do so, one must select a
device that satisfies the ideal conditions as much as possible,
then the optimum gate drive must be designed for the system
to realize the best performance. VGG+ (positive gate bias
voltage), RG, max IG, drive layout, drive power rating aresome of the basic parameters necessary in designing a gate
drive. It is necessary to understand each of the parameters aswell as the characteristics of IGBT switching in order todesign a gate drive. The value of VGG+ are related to on−stateloss and switching speed, while the value of RG is related toswitching performance. In addition, if the power of a gate
drive, or supply capacity of IG is not enough, then the valuesof VGG+ and RG become meaningless. At the same time,attention is required in the layout of the gate drive to prevent
induced turn−on due to dv/dt. The aforementioned
parameters will be discussed in following sections based on
the commonly used half bridge topology (Figure 3).
(Devices with better performances, in general, have lower
power dissipation. Minimizing power dissipation is directly
related to the cost, size, efficiency and fidelity of the overallsystem. As such, other topics discussed in this chapter must
be understood with device power dissipation in mind.)t4 region
Also in this region, iG is charging Cgc, and vGE maintains
VGE,Io, and iC maintains full load current (IO), while vCE falls
at a rate of (VGG−VGE,Io)/(RGCgc). By this time, vCE has
diminished significantly, and there is a voltage tail, as Cgc has
a large value when vCE is low.
t5 region
In this region, vGE increases again until VGG+ with
RG(Cge+Cgc,miller) as time constant. Cgc,miller is the Cgc that rosefrom low vCE value due to the miller effect. In this region, vCE
slowly diminishes to the collector−to−emitter on−statevoltage and becomes completely saturated. This is because
the IGBT pnp transistor portion is slower than the MOSFET
portion in crossing the active region to reach on−state (hardsaturation) as well as the effect from Cgc,miller.
Turn−off Transient Region
t6 region
This is the region of td(off) (Turn off delay time), where vGE
falls from injected VGG+ to VGE,Io with a time constant of RG(Cge+Cgc,miller). At this time, there is no change in the valuesof vCE or iC.
t7 regionvCE increases in this region, and the rate can be controlledwith RG as shown in the equation below:
V GE,Io
dv CE+
dt
C res @ R G

VGG+

VGG+ is the voltage across the gate and the emitter terminal
during conduction, and it is one of the most importantparameter in designing the gate drive. The value of VGG+
must be made with considerations for trans−conductancecharacteristics or I−V characteristics shown in the data
sheet; diagrams of SOA (Forward Bias, Reverse Bias, Short
Circuit); maximum values of IC and VCE; value of tf, and theinterrelationships among these parameters must be
considered.

t8 region
In this region, the value of vCE is maintained at vd, while
iC decreases at a rate equivalent to the following equations.
The rate of increase can also be controlled with RG.
V GE,Io
di C+ g fs @dt
C IES @ R G

Like the turn−on transient region, there is over−voltage int7 and t8 regions, as the voltage VLS = LS×diC/dt, which is
injected into the stray inductance from the effect of diC/dt, isadded to the C−E region of the IGBT. t8, which is the firstof the 2 regions where iC decreases, is the region where
MOSFET current disappears from the IGBT’s iC.

Minimum/Maximum Rating
The maximum value of VGG+ is determined by theisolation limit of the gate oxide. If a voltage exceeding the
maximum rated voltage between the gate and the emitter,then the gate oxide would be destroyed and become useless.
As such, the absolute value of VGG+ in application must be
smaller than the maximum value. The minimum value of
VGG+ is the lowest value within the limits of saturation duringconduction.

t9 region
BJT current of the IGBT’s iC disappears in this region, andthis current is often called the current tail. It is caused by therecombination of the minority carrier (hole), which is
injected into the N− drift region Due to this region, IGBT
switching characteristics are inferior to that of the power
MOSFET.

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AN−9020/D
noise, it is necessary to set an upper limit. Fundamental
method to limit over−current in IC is to select a device whosebuilt−in diode has better recovery characteristics. However,once the device has been decided and setup is completed, ICpeak current can be kept below the rated amount by reducing
VGG+ or by increasing RG. IGBT’s over−current and the
FWD’s over−voltage on the opposite side can also reduce
diC/dt by limiting VGG+ or by increasing RG. In selecting adevice with built−in diode (co−pak IGBT), the peak value ofthe over−voltage must not exceed the rated voltage of thediode on the specification. The snappiness factor (refer toFigure 2: S=tb/ ta) of the built−in diode must not be too
small.

Effect on StateFor the same value of IC, VCE(sat) is inversely related to thevalue of VGG+. The smaller the VGG+, the thinner the channel
between n+ layer and n−drift layer becomes, and theresistance in the channel increases. Due to the conductivity
modulation effect not found in MOSFET, volt− age drop in
the n−drift region is significantly smaller than in MOSFET.
As such, the portion of resistance in the channel increases inthe voltage drop between the collector and the emitter duringon−state. Considering the aforementioned factors, VGE
decreases during IGBT switching, and the channel becomesthinner to increase resistance. This leads to an increase in
VCE(sat), and on−state loss becomes greater. As such, it would
be better to use the largest possible value of VGG+ from therespect of on−state loss. In applications where on−state loss
takes a large portion, it is important to increase the value of
VGG+, lowering VCE(sat) in order to reduce conduction loss.
For more detailed values, refer to the transfer characteristics
curve in the data sheet. (Example: Figure 4)
Common Emitter
TC = 25 ℃

140

20V

Effect on the Short Circuit Capability
IGBT’s short−circuit endurance capability can becontrolled with the value of VGG+. The smaller the VGG+, thesmaller clamping voltage during short circuit and power
dissipation as shown in Figure 3. In another word, shortcircuit endurance time increases. With these characteristics,
short circuit protection can be devised with VGE. However,with increases in VGG+, one must assume increases inon−state losses. RUF Series by onsemi can withstand shortcircuit condition for about 10 ms.

15V

Collector Current, I

C

[A]

120
12V

100

Effect on Turn−off
As the turn−on characteristics of IGBT are largely
affected by VGG+, turn−off characteristics of IGBT are
affected by VGG− (negative gate bias voltage). However, thetail section of the IC comes from the BJT characteristics of
IGBT, which is an integral nature of the device and can− notbe controlled from outside with VGG−. As the value of VGG−
becomes greater, the turn−off switching loss of IC decreases.
As the value of VGG− increases, di/dt of IC increases, and di/dt
of ID increases by the same amount. di/dt of ID and strayinductance LS is added to VDC according to the equation,
V = LS * di/dt to form over−voltage. As the absolute valueof VGG− increases, diC/dt and dvCE/dt increases, and as diC/dt
increases, the over−voltage of VCE increases. The peak valueof this over−voltage must not exceed IGBT’s maximum
rating, so the value of VGG− can be reduced to control it. On
the other hand, as the value of VGG− is increased, thepossibility of dv/dt shoot through (RG: refer to Effect onturn−on) is reduced.

80
60

VGE = 10V

40
20
0
0

2

4

6

8

Collector − Emitter Voltage, VCE [V]Figure 4. onsemi SGL50N60RUFD Typical
Output Characteristics

Effects on Turn−on
As VGG+, (VGG+ – VGE(th)) increases, switching timedecreases and switching loss becomes smaller. Greater the
IG flowing into the gate during turn−on, the quicker it charges
Cge, and VGE increases rapidly, which leads to a quicker
increase in IC. As seen in the following equation, IG increases
as VGG+ increases, and it leads to an increase in diC/dt.
IG = (VGG + − VGE ) ⁄ RG
Since recovery characteristics of the freewheeling diode(FWD) on the opposite side are a function of diC/dt, peak
recovery current (Irr) of FWD (refer to Figure 2) (which is
IGBT’s over−cur− rent), over−voltage of FWD and dvCE/dt
are affected by changes in diC/dt. When diC/dt increases,over−current of IGBT and over−voltage stress of FWD
increases, while it also causes increases in falling dvCE/dt of
IGBT and rising dvCE/dt of diode voltage on the opposite
side. Large values of diC/dt and dvCE/dt indicate thatswitching speed, or switching loss, is small, which could be
an advantage, but from the perspective of limiting EMI

RG

Effect on Turn−on
Series resistance (RG), which is connected to the gate, isa parameter that has a significant effect on switching
waveform. When RG decreases, diC/dt and dvCE/dt increases
in both turn− on and turn−off, and switching loss becomes
smaller. There are some important significant advantages
when RG is smaller, which included improved dv/dt noise
immunity. Dangerous surge voltage on the IGBT gatecaused by Miller effect or dv/dt coupled noise, which means
induced turn−on can be avoided. When one side of IGBT of
the half−bridge turns on, then the freewheeling diodewww.onsemi.com
4

AN−9020/D(FWD) of the IGBT on the opposite side recovers reverse
voltage and there is dv/dt. This dv/dt can instantly conduct
IGBT on the other side. As the parasitic capacitance Ccg
between the gate and the collector on the other side ischarged by dvCE/dt at the IGBT on the other side, this current
then flows to the gate to reduce voltage. This leads the gate
voltage to exceed the threshold voltage momentarily, thenthe IGBT is in conduction. This is called dv/dt shootthrough. This causes unnecessary loss, but reducing RG
decreases the amount of reduction in voltage at the ends.
Increasing the value of VGG− is also effective as it reduces thepossibility of IGBT’s gate voltage to rise above VGE(th).
Despite these advantages, the minimum value of RG islimited, and it is limited by the FWD recovery
characteristics of the IGBT on the opposite side. di/dt anddv/dt stress of FWD on the opposite side change with thevalue of RG under hard switching inductive load. If diC/dt islarge there can be oscillation, and when diC/dt increases,
dvCE/dt also increases. As diC/dt becomes greater, the greater
the possibility of dv/dt shoot through on the IGBT on the
opposite side. Under this situation, one must assume theturn−on switching loss, and increase RG to reduce FWD
stress.

Ate charge (Qg) of the IGBT is greater, or smaller value of
RG has been chosen for faster operation of the IGBT, the peakvalue IG current becomes greater. According to the value atthe peak, it may be necessary to amplify the power at the gate
by using push−pull circuit. Qg is greater for devices withhigher rated current, and the amount of necessary gate
current increases accordingly. When power amplification isnecessary because the necessary value of the current is large,
careful selection in the device for push−pull is needed. This
device must be able to provide the amount of current
demanded by the gate and must have quick response.
One of the most important values necessary in designinga gate drive is the maximum value of IG, which is provided
by the gate drive. Average value of IG provided by the gate
drive can be obtained easily by dividing the average current
by the voltage, but the maximum value of IG is moremeaningful. This is because the types and the current ratingof the devices that make up the gate drive are determined by
the maximum instant current. In general, the amount of cur−rent the gate drive must supply increases in relation to theoperating frequency as shown in the following equation, but
a gate drive with a few Watts is enough for several Amp
IGBT and operating frequency of several 10s of kHz. The
total power by the gate drive can be computed with thefollowing equation
PGD_TOTAL= f × PSW + PGD_INTERNALPGD_TOTAL : Total supplied power to the gate drive
PSW : Sum of the charge and the discharge power respect
to pulse PGD_INTERNAL : Power consumed by gate drive
itself
PSW = QIN × VGG6
VGG : VGG+ - VGG−
It is possible to use what is generally called gate charge(Qg) for QIN, but if in this case, it is possible to use the amountof current the gate drive must provide the IGBT in a single
pulse. As such, we can obtain the value by integrating the
IGBT IG curve on the oscilloscope. This becomes a valid
value in obtaining gate drive current through the above
equation. Gate charge can be obtained from gate
capacitance, and its curve is available on the data sheet, but
its value would be smaller than Qg or QIN if gate capacitanceis used simply with the equation Q = C×V. This is because
gate capacitance has non−linear dependency on the gate andthe collector voltage.
Power consumed by the gate drive itself must also be
considered as shown in the above equation, and it must also
take into consideration that the amount of power consumed
increases as the operating frequency increases. As such,there must be a safety margin in the calculation of PGD_TOTAL.
In application, the maximum amount of power may only bea few watts, but the maximum current may be more than a
few Amps. The maximum current can be obtained with thefollowing equation:
IG(max) = VGG ⁄ RG(min)Effect on Turn−off
Although RG is small, it has the same effect as increasing
VGG−. As RG becomes larger, turn−off fall time increases andswitching loss rises. However, the effect is generally lessthan during turn−on. Since IC current is divided into
MOSFET and PNP transistor, only the current fromMOSFET can be controlled during turn−off. From theperspective of dv/dt noise immunity, dv/dt malfunction fromthe IGBT on the opposite side can be reduced during turn−on
if the value of RG is large. On the contrary, from the off state,
the possibility of dv/dt shoot through during turn−on from
IGBT increases. As such, if different values of turn−on RG
and turn−off RG are used, the values can be adjusted
accordingly in consideration of the two cases.
Gate Drive Power Requirement
The proper gate voltage does not mean the proper
operation of the IGBT. When IGBT turns on and off, then thegate is either charged or discharged and the current IG flows
out of or into the gate. The value of the current should beenough to charge and discharge in order to properly turn onor turn off the IGBT. The waveform is shown in Figure 5.

Figure 5. IGBT VGE, IG Waveform
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AN−9020/D
When the maximum current is actually measured, onemust be aware that it may be less than the calculated amountdue to the falling voltage on the wire and stray inductance.
When IGBTs are connected in parallel and are operated at a
low frequency, low RMS current could lead to a mistakencomplacency. However, under such situation, the maximum
current would be twice as large, since there are 2 IGBTs in
operation, and one must be careful that it could lead to theoverload of the power supply of the gate drive. Wattage of
the RG can be decided with the maximum calculated amountof current.

Wiring Pattern

G−E
terminals

Gate Drive Layout Considerations

Figure 6. Gate Drive Pattern 6

Effect of Gate Line Inductance on the Induced Turn−on
Possibility of induced turn−on is greater, as the gate drive
impedance is increased during turn−on and turn−offtransient due to stray inductance from the line connectedwith the gate. As gate impedance becomes smaller, morecurrent flows through RG to reduce the charging current ofCge, which causes the amount of increase in VGE to reduce.
In order to prevent this, leakage inductance from DC power
supply must be minimized, and RG should be kept at
minimum.

The final push−pull wiring pattern should be short andthick, and if a direct connection between the gate drive andthe IGBT is not possible, then gate wire and the emitter wire
could be twisted to reduce stray inductance. In addition, if
the area of the loop that encompasses the final push−pullstage, the power source pattern, RG, and G−E terminals of
the IGBT is minimized as shown in Figure 6, effect on the
VGE, from diC/dt could be minimized when VGG+ is injected.
Common Emitter Problems

Power Source Stabilizing Capacitor
During IGBT switching, current flows to the gate, and atthat time, supply voltage of the gate circuit can oscillate. As
a result, the gate drive loss can exceed the designed amount,or it could reduce the short circuit capability. In such case,
it is advised to keep PCB pattern wide and flat and use
enough capacitor for supply voltage stability.

Gate
Drive

Gate
Drive

Lgs
Les
Les

Isolation Problem
In half bridge topology and similar systems, the upper
IGBT gate drive circuits must be insulated from the bottom
IGBT circuits. The control board and the gate drive mustalso be insulated because the upper IGBT emitter free floats
as the IGBT switches. As the power DC voltage rises, theinsulating voltage should also rise accordingly. In general,
the insulating voltage should be at least twice the rated
voltage for the IGBT. In addition, care has to be taken with
the noise that comes about from insulating interface.
Immunity to noise differs depending on the how and where
the circuits lines are placed, so wiring and placement should
be designed to minimize parasitic capacitance. Parasitic
capacitance should be minimized to reduce C×dv/dt
coupling noise between neighboring drive circuits. Whenusing a common transformer to provide current to both theupper and the lower gate drive, the wire must be wound tominimize combined capacitance. In using opto−coupler, theopto−coupler must have insulating capacity with highcommon mode voltage and transient noise immunity. Upperand lower, or different types of gate leads of the gate drive
must not be wound together.

Lgs

Figure 7. Common Emitter

At the time of switching, voltage is induced across thestray inductance of the power circuit because of di/dt fromthe main current. When control signals from the gate drive
and the same path as the main current are used, gate voltage
decreases during turn−on, and voltage is added to the gate
voltage during turn−off to slow the turn−on/turn−off. As
such, it is better not to share stray inductance between
control emitter terminal and power emitter terminal. As
such, control emitter terminal and power emitter terminal
should be separate. If the two terminals are together,common emitter inductance increases to slow the switching
speed and switching loss.
Voltage oscillation, slow gate voltage rise, noise
immunity deterioration, gate voltage reduction, falling gate
protection circuit efficiency are some of the effects of thelayout. These can be solved with designs to reduce stray

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AN−9020/D
within the latch−up−free PT IGBT chip is known to bedifferent from the two above switching stress.
There have been much research into preventing device
destruction from short−circuit and turn−off switching stressof CIL. We would like to discuss them in relation to SOA andprotection mechanism.

inductance and stray resistance such as making patterns
short and thick. In addition, attention must be paid to thepower circuit layout to minimize stray inductance. For
example, the area of the closed loop must be minimized withDC link capacitor, load, power output, half−bridge leg andsnubbers in the case of inverter, and in the case of resistive
load, line to the load should be twisted to reduce the strayinductance of the power circuit, while snubber should be
strengthened depending on the amount of over−voltage forinductive load. As the frequency increases, voltage couldchange due to slowing response of the dc link capacitor, sohigh−speed electrolyte cap for inverter should be used, andcapacitor with better characteristics such as film capacitor
should be inserted in the main cap in parallel.

FBSOA and Short Circuit Destruction
FBSOA

Forward bias safe operating area (FBSOA or SOA) is
generally referred to as the current and voltage limits where
the device can operate normally during on state. FBSOA of
IGBT is illustrated in Figure 8. The SOA of IGBT is nearlya rectangle for a short period of time, but as shown in
Figure 8, FBSOA decreases as on−time increases. Lower
limit is determined by DC operation. Parasitic thyristor
latch−up and thermal breakdown are the two major failure
mechanisms of IGBT under extreme stress. Even the device
that prevents static latch−up could be prone to dynamic
latch−up. In the device that prevents latch−up, carrier
multiplication, which was accelerated by thermal effect,
becomes the cause of breakdown. It is limited by parasitic
thyristor latch−up at high collector current and dynamic
avalanche break−up at high voltage region.

Conclusion

We have examined some issues to consider in the gate
drive of the IGBT. The gate drive, IGBT’s operating circuits,
are simple and lends it self easily to miniaturization, so thesystem designer can design the gate drive, but it is not aneasy task to design an optimum gate drive for the system. IC
type gate drive solutions are designed to fit the needs of theuser’s system to customize some significant parameters bylinking simple passive devices. Furthermore, they havebuilt−in OCP (over current protection) and SCP (shortcircuit protection) functions to easily build a more stablesystem. It is becoming even more popular with theintroduction of the IPM (intelligent power module), whichputs inverter with gate drive, which is used often in theindustrial application, in the same package.

50
Ic MAX. (Pulsed)

Collector Current, I C [A]50us

SECTION II. IGBT PROTECTIONSIntroduction − IGBT Failure Mechanism

IGBT applications with power converter received highelectrical and thermal stress under short−circuit or turn−offswitching of clamped inductive load (CIL). As such, theability to endure stress is one of the important requirements.
If there is a large power loss within the device due toelectrical stress, much heat is generated to the limitations inpackaging and due to semiconductor’s thermal parameters.
It would lead to thermal breakdown if this continues.
Hot−spot generation from impact ionization and current
crowding are the reasons. The existence of parasitic thyristor
also has an effect on the robustness of the device. Latch−upof the parasitic thyristor is also a reason for breakdown.
Design for IGBT comes from an understanding of themechanisms of various stresses that can lead to thedestruction of the device, and the IGBT is optimized towithstand stress from a large current. SOA evaluation
methods for the device are different for short−circuit inexperiment and for clamped inductive switching stress.
IGBT’s short circuit performance generally determines
forward bias SOA, while turn−off at clamped inductive load
determines reverse bias SOA. Position of thermal failure10

Ic MAX. (Continuous)

0.01
0.1

100us

DC Operation

1

0.1

1㎳

Single Nonrepetitive
Pulse T C = 25 °C
Curves must be derated
linearly with increasein temperature
1

10

100

1000

Collector−Emitter Voltage, V CE [V]Figure 8. Typical IGBT FBSOA

Short−circuit threatens this FBSOA. If there is a
short−circuit, IGBT’s IC increases. However, depending on
the IGBT’s output characteristics—IC current is limited by
the value of VGG+, but since the voltage is high when thecircuits are shorted, the device must withstand extreme lossof power. As time passes, temperature rises from power loss,
and the temperature of the device continues to increase. In
this case the IGBT must turn off within 10 ms.
In order to protect the IGBT from short circuit situations,the device’s short circuit capability must first be known. In
general, the simplest short circuit test is testing the IGBT’s
short circuit capability. However, this is different from realapplication short circuit conditions. In this test, it is notpossible to see the effects of dynamic dv/dt, which induces

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AN−9020/D
IGBT’s latch−up. It is possible to obtain short circuit timewith short circuit testing of different products from many
companies. In general, short circuit time becomes longer
with high saturation voltage and VCE (sat). (In measuring VCE(sat), gate voltage should be enough for the minimum value of
VCE(sat), and that level must be maintained during fault test.)

On the other hand, when short circuit is limited, loss is
reduced and short circuit endurance time is increased. As
short circuit endurance time increases, more time would besecured for the protection circuit to respond. As such, whenshort circuit is detected through a fault in the sensor circuit,
reducing short current by lowering VGG+ is a good protection
method. Using low value of resistance RG is effective in
reducing short current, but it has the opposite effects onover−voltage, dv/dt during turn−off, especially during shortcircuit, so the value of the resistance must be set with suchtrade off in mind.

Types of Short Circuit

Short circuit can happen while IGBT’s normal function.
Short circuit can be divided into two different types. The
first is short−circuiting when the device was in on state,
which is called “fault under load” and the second is acircumstance where the device turns on under short circuit,which is called “hard switch fault”.

Type II. Hard Switch Fault (HSF)
In this case, short−circuit is caused when the device isturned on from off state with DC link voltage applied to thedevice. In such case, di/dt and the value of the fault current
are directly proportional to charging speed of the input
capacitance. The fault current can be cut off by turning off
the gate. The amount of the over−voltage created is directly
proportional to “DC loop” inductance and the ratio of the fallin current when the fault current is cut off, which is di/ dt.
Since the fault current is significantly greater than the rated
current, large value of RG can be used to prevent the creationof large over−voltage due to di/dt.

Type I. Fault Under Load (FUL)

Figure 9. Fault Under Load Test Circuit

Figure 11. Hard Switch Fault Test Circuit6

Figure 10. Fault Under Load Waveform

Fault under load (FUL) is a situation where short−circuittakes place when the device is in on state, so the VCE is low
before short circuit. In fault under load test circuit, shortcircuit can happen with a shoot−through when the IGBT on
the opposite side turns on while the DUT remains turned on.
Current rises quickly, and IGBT escapes from complete
conduction and enters the active region. VCE rises, and iCG
begins to flow in CCG, which is Miller capacitance. At thistime, if the gate resistance is large, it could rise above VGG+.
Fault current, VGE=VGG+, could rise above the limit for
current, and the possibility of device breakdown increases.
As such, it is recommended that low gate resistance be used
as a way to guard against “FUL”. Using low gate resistancewould prevent a rise in VGE during FUL to limit short current.

Figure 12. Hard Switch Fault Waveform6

VCE voltage does not change significantly under hardswitch fault, so the dv/dt is relatively smaller than in fault
under load. Furthermore, Miller capacitance is small underhigh voltage. As such, Miller effect, which is an important
issue for fault under load, is less significant under hardswitch fault.

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AN−9020/D
Short Circuit Protection

the short circuit current, is necessary as abrupt turn−off leads
to a large dv/dt, which increases the possibility for alatch−up. Principles of short circuit protection circuit design
to be added in a gate drive can be summed up as thefollowing:• Fault must be detected as soon as possible.
• Must suppress fault current to secure more time for theprotection circuit to respond, and send the gate off
signal as quickly as possible.
• Induce soft turn−off to avoid the dangers of turn−off
over−voltage.

We have discussed types of short circuits, and several
ways to prevent short circuits have been reviewed. However,methods mentioned above are not fundamental ways to deal
with short circuit, so there has to be a way to safely turn off
the device when it short circuits.
Protecting Against Over−current Condition
Over−current is when more than the rated current flows
through the system, and it can be classified into over−load,
short−circuit, turn−on over−current. In traditional
applications, over−current is possible in several cases.
Generally, over−current from over−load comes from inrush
current, filter inrush and a rapid change in load during
beginning of operation of electrical devices. In this case, we
can only rely on short circuit capability of the device.
Over−load, in general, lasts much longer than the IGBT’s
short circuit endurance time. As such, other methods must
be sought to remove the overload. Closed loop control
moderates the timing signal of the gate drive pulse, tomodifies the time of switching, and this is used to keep thecurrent output at a determined level. Response control of thecontrol loop would have to be set to the rate of changes in thecurrent and pace of the electrical devices or filter inductance.
Protection from over−current due to short−circuit isdifferent from turn−off over current. In the following
sections, protection from short−circuit would be discussed.

We shall discuss the short circuit protection scheme indetail in the following sections.
Short Circuit Protection Scheme
There are certain conditions to be met in constructing aprotection circuit. These conditions maximize the efficiencyof the protection circuit and minimize the effect on othercircuits. In order to obtain the protection function desired by
the designer without sacrificing other functions, protection
circuit design must satisfy the following conditions as muchas possible. The conditions are as follows:First, the protection circuit must shut down the IGBT
before device failure. This is applicable at all times
regardless of the conditions of operation for the IGBT. In
addition, the protection circuit must limit the maximum fault
current, and it must reduce stress on the device and thesystem, where high current flows. The device would have tobe shut down more quickly if the maximum fault current is
not limited.
Protection circuit must be responsive to both “fault underload” and “hard switch fault.” In addition, it must notdegrade switching or conduction characteristics, because
this causes temperature to rise, and it is reflected in theefficiency and fidelity of components. Trip point, which is
the minimum current recognized as short−circuit, must be
easy to manipulate. Production cost must be minimized as
it has a significant impact on the viability of the product.
The above conditions for protection circuits could be easy
or difficult to meet depending on the fault detection method.
The following are some typical fault detection methods andthe effects on the conditions mentioned above.

Protecting Against Short Circuit Current Condition
In the overload situations mentioned above, removing theclosed loop does not considerably shorten the life of the
IGBT. On the other hand, short circuit provides worse
condition for the life of the device than overload or theover−current at turn−on, and there are ground faults,
terminal−to−terminal faults. Such short circuit current
bypasses the electrical devices or filter inductance andincreases rapidly for IGBT to flow. Conventional PWM loop
controls power output, but it has no control over this type of
fault. At the beginning of the fault, the IGBT must withstandwith its own short circuit capability, and protection
mechanism receives the fault signal to reduce the gate
voltage while IGBT withstands the short circuit. However,if the fault disappears while during IGBT’s endurance time,then the IGBT must continue to function and must not turnoff unnecessary devices or turn off the entire system. The
most notable is the IGBT turn−on over−current due to thereverse recovery current of the diode. As such, theprotection circuit must be designed to return the circuit tonormal operation if the fault is removed before the IGBT
shuts down the system.
When conduction time increases, the border of SOA(SCSOA) decreases. Junction temperature increases
instantly during on state, and as a result, the maximum
possible controllable current decreases. As such, shortcircuit, whose current rises rapidly, must be turned off in avery short period of time, and the time from moment shortcircuit occurs to the moment it is turned off is should bewithin 10us. In addition, soft turn−off, which slowly cuts off

Detection Through ResistanceThis is fault detection method is the easiest to understand.
Resistance is introduced at the passage of the load current,
and it is made to produce voltage that can be monitored by
the protection circuit. Sense resistor can measure current
precise enough for over−current and fault detection. In
addition, it can be used in analog feedback. However, it takes
up a lot of space and requires a low inductance resistor, whileself−inductance and wiring inductance within the sense
resistor makes transient response characteristics get worse.
When resistance is inserted into the DC loop, there is anadverse effect of inductance that deteriorates the system’s
performance. In addition, sense resistor is not insulated fromthe main power circuit, so the protection circuit must be

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AN−9020/D
insulated from the logic circuit, which processes the sense
signals. This can cause the system to become complex. In
other cases, sense IGBT, which as a built−in sensing resistor,
in the current sense path. This would be easier than installingit in the main current path. However, there are problems withhigh cost IGBT, limited uses, consistency among sense
ratios among devices, and their trade−offs must be
considered.

Load

Gate
Drive

VsenseHall Sensor

Load

Figure 14. Short−circuit Sensing Circuit with CT
Gate
Drive

De−saturation Detection
This method detects VCE in its operation. Short circuit hasa switching device but no load, so all of the supplied voltage
appears across the device. As such, during short circuit, VCEof the IGBT diverges from the low on−state voltage and rise
to DC loop voltage following the power output curve. If suchhigh voltage appears in C−E terminal, where low on−statevoltage region, then it is detected by the VCE(sat) sensing
circuit and protection circuit. This method has no loss fromcomponents in detecting the current, which improves theoverall efficiency of the circuit. In addition, there is lessstray inductance due to the protection current, which enables
faster operations. Furthermore, since it uses thecharacteristics of the device without any additional device
in the circuit, it is an effective circuit in both AC and DC
circuits. It has reasonable cost, and integration is easier as it
uses simple passive devices. However, this method cannot
detect exact amount of operating current that has been set,
and it provides only fault/no−fault command. In thismethod, protection circuit is not insulated from the powerstage, so gate signals are eliminated by IGBT, and insulationis necessary in the process of sending error mes− sage to thelogic circuit. This circuit cannot be left in sensing mode at
all times. It is not operational when IGBT off, but it becomes
operational with the conduction signal. However, there must
be a blanking time in the turn−on transient period to allow
turn−on switching process. (refer to AN−9001)

VsenseFigure 13. Short−circuit Sensing Circuit witha Sensing Resistor

Current Transformer
This is also an excellent fault detection method. Current
transformer is placed on the power output needed to bemonitored or on the conductor where short circuit current is
expected to flow. This method has an advantage in that itallows the selection of the transformer for precise AC
sensing. Since the transformer itself provides insulation
between the power circuit and the protection circuit, there
need not be additional considerations for insulation. It also
provides high−level signal output with noise immunity since
the protection circuit is driven by current. However, DC
level cannot be detected without the use of the much more
complex DC transformers. These are Hall Effect sensors,which are generally expensive. Aside from the Hall Effectsensors, current transformers are expensive in general, sothey are not very economical. In addition, it is not an easytask to design a proper transformer since current
transformers must operate in a large bandwidth. If a quick
response to a rapid rise in fault current is necessary, it must
operate in the MHz region as well as the system’s minimum
operating frequency.

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AN−9020/D
allows n−channel IGBT to have excellent avalanche induced
SOA limits. In addition, N base region sheet resistance of thep−channel IGBT is about 2.5 times lower than the P baseregion sheet resistance of the n−channel IGBT, so p−channel
IGBT is superior to the n−channel IGBT in current induced
latch−up limit.

Vdc

L
O
A
D

Over−voltage Protection
VsenseFigure 15. Short−circuit Sensing Circuit
using De−saturation Method
RBSOA

Collector Current, I C [A]40

Figure 17. Turn−off Waveform of IGBT with Snubber
10

When a power device turns off rapidly, energy that has
been stored in stray inductance is dissipated in the switching
device. Because of this, there is voltage overshoot in eitherside of the device. The size of this transient voltage isdirectly related to the size of the stray inductance and thefalling rate of the turn−off current. In particular, large
capacity IGBT module switches a large amount of energy ina short time, and it is possible for a large current to be
injected to lead to the destruction of the device. Such module
for a large current is generally made of several IGBT chips.
Individual chip switches a portion of the current in theamount equivalent to di/ dt as determined by the gate drive
circuit. The total amount of the current and di/dt for themodule is equivalent to the sum of the current and di/dt foreach chip, respectively. The moment the device turns off toprotect the IGBT during short circuit is the most dangerous
moment. At this time, di/dt could exceed several thousand
A/ms. To shut down the device to protect it from a fault
condition, care must be taken to minimize the accompanying
over−voltage, or the device could be destroyed.
Over−voltage protection circuit optimized for normal
switching may not be adequate in fault current shut−off
process, so there must be additional response toover−voltage. Snubber circuit is often used as a protection
circuit to protect normal switching. Over−voltage atturn−off can be suppressed by controlling the value of RG orby inserting Cg, but these methods hinders othercharacteristics. As such, snubber circuit is often used. In thenext section, types, characteristics as well as advantages anddisadvantages of the snubber circuit are discussed.

Safe Operating Area
V GE = 20V, TC = 100℃

1
1

10

100

1000

Collector−Emitter Voltage, V CE [V]Figure 16. Typical RBSOA of IGBT

During turn−off transient, the gate bias with a positive
value is switched to zero or to a negative value, which leaves
the device with high voltage and hole current. Safe operatingarea for such operations is called RBSOA (refer to Fig. 9).
Unlike FBSOA, snubber circuit design is important for safe
operation during IGBT turn−off. Wider RBSOA can beobtained by reducing PNP transistor’s current gain. If
RBSOAs of p−channel and n−channel IGBT with identical
doping profile and cell structure are compared, n−channel
has larger SOA for the collector voltage (avalanche induced
SOA limit), but the SOA for the collector current (current
induced latch−up limit) is smaller. p−channel, on the other
hand, is the opposite of n−channel. The limit of theavalanche induced SOA is affected by the impact ionization
coefficient for the carrier of the depletion layer. Impact
ionization coefficient of the holes transported from then−channel IGBT is lower than that of electrons, whichwww.onsemi.com
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AN−9020/D
Snubber Circuit

Ed: DC supply voltage
f: switching frequency

Types of Snubber Circuits and their Features
Snubber circuit is a supplementary circuit used in theconverter circuit to reduce stress put on the power
semiconductor. The ultimate goal of the snubber circuit is toimprove the transient waveform. The snubber circuit
suppresses over−current or over−voltage or improves dv/dt
and di/dt to ease the transient waveform to reduce stress on
the device. There are many uses for snubber circuits, but this
discussion will center on its ability to suppress over−current
at turn−off.
Snubber circuit can be divided into those connected in
between the DC power supply bus and ground, and thoseconnected to each IGBT. The first types of circuits include
RC snubber circuits, charge and discharge RCD snubber
circuits and discharge−suppressing RCD snubber circuits,
and the second type includes C snubber circuits and RCD
snubber circuits. The following are detailed descriptions ofeach snubber circuit.

However, losses from this circuit (mostly from snubber
resistance) are significantly larger than the same indischarging suppressing RCD snubber circuit. As such, it is
not suitable for high frequency switching applications.
There is a lot of turn−on losses with bridge configuration.
There are the disadvantages of relatively many parts anddifficulties in selecting parts.
Discharge−suppressing RCD Snubber Circuit
Functions of this circuit are similar to those of voltage
clamp snubber circuit. Snubber capacitor is charged to theDC link voltage while the IGBT is in conduction, and VCE
rises rapidly when IGBT is in turn−off. Due to the strayinductance of the DC loop, VCE rapidly rises above DC link
voltage. When VCE rises above DC link voltage, snubber
diode is in forward biased conduction, and snubber begins
operation. Energy stored in stray inductance moves tosnubber capacitor. This capacitor absorbs the energy
without a rise in voltage.
It has the advantage of small oscillation in DC link
voltage, and it is most practical in mid−to−large current
applications. Its effect on the turn−on voltage transient isneither large nor small. It is ideal for high frequency
switching as its losses from the snubber circuits small.
Losses from the circuit is as follows:

RC Snubber Circuit
This snubber circuit is effective in turn−off surge voltage
and is suitable for chopper circuits. It is also effective foroscillation by parasitic reactance and dv/dt noise. However,when it is applied in large capacity IGBT, resistance for thesnubber must be set low due to dissipation of heat, so it has
the disadvantage of worsening loading conditions atturn−on. Loss at snubber itself is quite large, so it is notsuitable for high frequency. In very large capacity IGBT
circuit, it is better to use small snubber “RC snubber circuit”
along with the main snubber “discharge− suppressing RCD
snubber circuit.” When used together, it helps parasitic
oscillation control of the main snubber loop. Mainapplications include arc welder and switching power supply.

P + (L+ 1ń2

2f)ń2 ) (C S

C sn

2

IO

V pk

Ed

2

f)ń2 [W]Its disadvantages are that it has many necessary parts andis less than effective on turn−off surge voltage. It is often
used in inverters.
C Snubber Circuit
This is the simplest snubber circuit, so it has the advantage
of suppressing over−current at minimum cost. It is effectivein mid−to−low current, low power applications, and as thepower level increases, it becomes more likely for the circuit
to oscillate as the snubber capacitor and the main circuit
inductance form LC resonance circuit. It is often used ininverters.

Charge and Discharge RCD Snubber Circuit
This snubber suppresses over−voltage at turn−off toreduce switching losses at turn−off, and its effectiveness insurge voltage suppression is about average. The snubber
capacitor is completely discharged at turn−on, and it is fullyrecharged at turn−off. Unlike the discharge−suppressing
RCD snubber circuit below which acts as a clamp, thiscircuit reduces IGBT dv/dt during turn−off. As such, soft
switching is possible, and IGBT loss is reduced. Since thestructure of this circuit is snubber diode added to an RC
snubber, snubber resistance can be increased, which
alleviates the load problem at turn−on. It is effective chopper
applications, which uses large current and low DC link
voltage. Its advantage also includes no oscillation at its DC
link voltage.
Power loss due to the resistance is as follows:
P + (LIO

RCD Snubber Circuit
It operates in the same manner as the C snubber circuit, but
it is different in that it operates during turn−off switching. It
is a circuit that solved oscillation of the C snubber circuit byusing the fast recovery diode. Energy that was stored in DC
loop inductance moves to the capacitor while the IGBT turns
off. The snubber diode prevents oscillation from taking
place. Charge from the capacitor is discharged through thesnubber resistor. (RC time constant should be about 1/3 ofthe switching cycle. (τ = T/3 = 1/3f))
This circuit reduces turn−off voltage transient directly.
Switching waveform is significantly smoother and snubber
loss is small. Effect on the turn−on voltage transient is fine,and it has the advantage of stable wave as the snubber diodeblocks oscillation. It is practical in medium current range,
but operation in large capacity IGBT, parasitic inductancef)ń2 +

f sw [W]

L: wiring inductance of the main circuit
IO : collector current at IGBT turn−off
CS: capacitance of snubber capacitor

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AN−9020/D
This circuit cannot use low inductance snubber capacitors
designed to be attached directly to the IGBT, and theblocking diode added to the protection circuit can increase
the total snubber inductance. Furthermore, if the recovery
characteristics of the diode are not good, VCE overshoot anddv/dt at either sides of the IGBT/diode, or the output voltage
can oscillate. Turn−off mechanism is nearly the same as thatof the discharge−suppressing RCD snubber circuit.

increases to present problems in controlling over−voltage.
In such large current applications, discharge−suppressing
RCD snubber circuits are generally used. Functions of thedischarge−suppressing RCD snubber circuit are similar to
the functions of the RCD snubber circuits, but thedischarge−suppressing RCD snubber circuit has theadvantage of smaller loop inductance as it is attached to thecollector and the emitter of each device.

(a)

(b)

(d)

(c)

(e)

(a) RC Subber Circuit(b) Charge and Discharge RCD Snubber Circuit(c) Discharge−suppressing RCD Snubber Circuit(d) C Snubber Circuit(e) RCD Snubber Circuit

Figure 18. Scheme of Each Type of Snubber Circuit

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AN−9020/D
References[9] Malay Trivedi and Krishina Shenai, “Trade−Off in
IGBT Safe Operating Area and Performance
Parameters”, IAS Conf., pp. 949−954, 1997.
[10] Yi Zhang, Saed Sobhani and Rahul Chokhawala,“Snubber Considerations for IGBT Applications”,
IPEMC, pp. 261−269, 1994.
[11] Malay Trivedi and Krishina Shenai, “Investigationof the Short−Circuit Performance of an IGBT”, IEEE
Trans. Electron Devices, vol. 45, no. 1, pp. 313−320,
1998.
[12] Malay Trivedi and Krishina Shenai, “IGBT
Dynamics For Short−Circuit And Clamped Inductive
Switching”, IEEE APEC, vol. 2, pp. 743−748, 1998.
[13] Rahul S. Chokhawala, Jamie Catt, and Brian R.
Pelly, “Gate Drive considerations for IGBT Modules”,
IEEE Trans. Industry Applications, vol. 31, issue 3,
pp.603−611, 1995.
[14] Rahul S. Chokhawala, Jamie Catt, and Laszlo
Kiraly, “A Discussion on IGBT Short−circuit Behavior
and Fault Protection Schemes”, IEEE Trans. Industry
Applications, vol. 31, issue 2, pp.256−263, 1995.
[15] Malay Trivedi and Krishina Shenai, “IGBT
Dynamics for Clamped Inductive Switching”,IEEE
Trans. Electron Devices, vol. 45, no. 12, pp.2537−2545,
1998.
[16] C. Aniceto, R.Letor, “How Short Circuit
Capabilities Govern the Desired Characteristics of
IGBTs” Power Conversion – PCIM, 1992,[17] R. Locher, “Short Circuit Proof IGBTs Simplify
Overcurrent Protection”, IAS,1991[1] Malay Trivedi and Krishna Shenai, “Failure
Mechanism of IGBT’s Under Short−Circuit andClamped Inductive Switching Stress”, IEEE Trans.
Power Electronics, vol. 14, no. 1, pp. 108−116, 1999.
[2] Rahul S. Chokhawala and Saed Sobhani,“Switching Voltage Transient Protection Schemes forHigh−Current IGBT Modules”, IEEE Trans. Industry
Applications, vol. 33, no. 6, pp. 1601−1610, 1997.
[3] Rahul S. Chokhawala, Jamie Catt and Laszlo
Kiraly, “A Discussion on IGBT Short−Circuit Behavior
and Fault Protection Schemes”, IEEE Trans. Industry
Applications, vol. 31, no. 2, pp. 256−263, 1995.
[4] Malay Trivedi and Krishna Shenai, “Internal
Dynamics of IGBT During Short Circuit Switching”,
IEEE BCTM, pp. 77−80, 1996.
[5] J. Yamashita, A. Uenishi, Y. Tomomatsu H.
Haruguchi, H. Dakahashi, I. Takata and H. Hagino, “A
Study on the Short Circuit Destruction of IGBTs”,
ISPSD, pp. 35−39, 1993.
[6] Rahul Chokhawala and Giuseppe Castino, “IGBT
Fault Current Limiting Circuit”, IEEE IAS,
pp.1339−1345, 1993.
[7] Tadashi Miyasaka and Shyuji Miyashita,“Protection of IGBT Modules in Inverter Circuits”,
Power Conversion, pp. 211−216, 1991.
[8] Hiroyasu Hagino, Junichi Yamashita, Akio Uenishi
and Hideki Haruguchi, “An Experimen tal andNumerical Study on the Forward Biased SOA of
IGBT’s”, IEEE Trans. Electron Devices, vol. 43, no. 3,
pp. 490−499, 1996.

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