CSD88599Q5DC
SLPS597D – APRIL 2017 – REVISED JUNE 2024

CSD88599Q5DC 60V Half-Bridge NexFET™ Power Block
1 Features

3 Description•••

The CSD88599Q5DC 60V power block is an
optimized design for high-current motor control
applications, such as handheld, cordless garden andpower tools. This device utilizes TI's stacked die
technology in order to minimize parasitic inductances
while offering a complete half bridge in a spacesaving thermally enhanced DualCool™ 5mm × 6mm
package. With an exposed metal top, this power blockdevice allows for simple heat sink application to draw
heat out through the top of the package and awayfrom the PCB, for superior thermal performance at
the higher currents demanded by many motor control
applications.

2 Applications•••

Three-phase bridge for brushless DC motor control
Up to 12s battery power tools
Other half and full bridge topologies

GL
NC

VIN

GH
SH

VIN
PGND

GH

VSW

VSW

SH

Bottom View

GL

PGND
PGND

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Power Block Schematic
Top View
Device Information
DEVICEQTY

MEDIA

PACKAGESHIP

CSD88599Q5DC

2500

13 Inch Reel

CSD88599Q5DCT

250

7 Inch ReelSON
5.00mm × 6.00mm
Plastic Package

Tape
and
Reel

6

VIN

VM

GH_A

CSD88599

Motor

GL_A

DRV832X GH_B
Gate Driver GL_B
GH_C

CSD88599

CSD88599

Power Loss (W)

•
•
•
•
•

Half-bridge power block
High-density SON 5mm × 6mm footprint
Low RDS(ON) for minimized conduction Losses– 3.0W PLoss at 30A
DualCool™ thermally Enhanced Package
Ultra-low-inductance package
RoHS compliant
Halogen free
Lead-free terminal plating

VIN = 36 V
VDD = 10 V
5 D.C. = 50%
L = 480 PH
fSW = 20 kHz
4 T = 25qC
A
3
2
1

GL_C

0
0

5

10

15
20
25
RMS Phase Current (A)

30

35

40
D000

Power Loss vs Output Current
Copyright © 2017, Texas Instruments Incorporated

Typical Circuit

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Specifications.................................................................. 3
4.1 Absolute Maximum Ratings........................................ 3
4.2 Recommended Operating Conditions.........................3
4.3 Power Block Performance.......................................... 3
4.4 Thermal Information....................................................3
4.5 Electrical Characteristics.............................................4
4.6 Typical Power Block Device Characteristics............... 5
4.7 Typical Power Block MOSFET Characteristics........... 7
5 Application and Implementation.................................... 9
5.1 Application Information............................................... 9
5.2 Brushless DC Motor With Trapezoidal Control......... 10
5.3 Power Loss Curves...................................................122

5.4 Safe Operating Area (SOA) Curve............................13
5.5 Normalized Power Loss Curves................................13
5.6 Design Example – Regulate Current to Maintain
Safe Operation............................................................ 13
5.7 Design Example – Regulate Board and Case
Temperature to Maintain Safe Operation.................... 14
5.8 Layout....................................................................... 15
6 Device and Documentation Support............................18
6.1 Receiving Notification of Documentation Updates....18
6.2 Support Resources................................................... 18
6.3 Trademarks............................................................... 18
6.4 Electrostatic Discharge Caution................................18
6.5 Glossary....................................................................18
7 Revision History............................................................ 18
8 Mechanical, Packaging, and Orderable Information.. 19

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4 Specifications
4.1 Absolute Maximum Ratings
TJ = 25°C (unless otherwise noted)(1)
PARAMETERCONDITIONS

Voltage

Pulsed current rating, IDM

MIN

MAX

VIN to PGND

–0.8

60

VSW to PGND

–0.3

60

GH to SH

–20

20

GL to PGND

–20

20

(2)

Power dissipation, PD
Avalanche energy, EAS

UNIT

V

400

A

12

W

High-side FET, ID = 95A, L = 0.1mH

448

Low-side FET, ID = 95A, L = 0.1mH

448

mJ

Operating junction temperature, TJ

–55

150

°C

Storage temperature, Tstg

–55

150

°C

(1)
(2)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Single FET conduction, max RθJC = 1.1°C/W, pulse duration ≤ 100μs, single pulse.

4.2 Recommended Operating Conditions
TJ = 25°C (unless otherwise noted)
PARAMETERCONDITIONS

MIN

MAX

UNIT

4.5

16

V

VDD

Gate drive voltage

VIN

Input supply voltage(1)ƒSWSwitching frequency

IOUT

RMS motor winding current

40

A

TJ

Operating temperature

125

°C

(1)

CBST = 0.1 µF (min)

5

54

V

50

kHz

Up to 42V input use one capacitor per phase, MLCC 10nF, 100V, X7S, 0402, PN: C1005X7S2A103K050BB from VIN to GND return.
Between 42V to 54V input operation, add RC switch-node snubber as described in the Section 5.8.1.1 section of this data sheet.

4.3 Power Block Performance
TJ = 25°C (unless otherwise noted)
PARAMETER
PLOSS

PLOSS

(1)

CONDITIONS

MIN

TYP

MAX

UNIT

Power loss(1)VIN = 36V, VDD = 10V,
IOUT = 30A, ƒSW = 20kHz,
TJ = 25°C, duty cycle = 50%,
L = 480µH

3.0WPower loss

VIN = 36V, VDD = 10V,
IOUT = 30A, ƒSW = 20kHz,
TJ = 125°C, duty cycle = 50%,
L = 480µH

3.4W

Measurement made with eight 10µF 50V ±10% X5R (TDK C3225X5R1H106K250AB or equivalent) ceramic capacitors placed across
VIN to PGND pins and using UCC27210DDAR 100V, 4A driver IC.

4.4 Thermal Information
TJ = 25°C (unless otherwise stated)
THERMAL METRIC
RθJA

MIN

TYP

MAX

Junction-to-ambient thermal resistance (min Cu)(2)125

Junction-to-ambient thermal resistance (max Cu)(2) (1)

50

UNIT
°C/W

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4.4 Thermal Information (continued)
TJ = 25°C (unless otherwise stated)
THERMAL METRIC
RθJC
(1)
(2)

MIN

TYP

MAX

Junction-to-case thermal resistance (top of package)(2)2.1

Junction-to-case thermal resistance (VIN pin)(2)

1.1

UNIT
°C/W

Device mounted on FR4 material with 1in2 (6.45cm2) Cu.
RθJC is determined with the device mounted on a 1in2 (6.45cm2), 2oz (0.071mm) thick Cu pad on a 1.5in × 1.5in(3.81cm × 3.81cm), 0.06in (1.52mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board design.

4.5 Electrical Characteristics
TJ = 25°C (unless otherwise stated)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

1

µA

STATIC CHARACTERISTICS
BVDSS

Drain-to-source voltage

VGS = 0V, IDS = 250µA

IDSS

Drain-to-source leakage current

VGS = 0V, VDS = 48V

IGSS

Gate-to-source leakage current

VDS = 0V, VGS = 20V

VGS(th)Gate-to-source threshold voltage

VDS = VGS, IDS = 250µA

RDS(on)Drain-to-source on-resistancegfs

Transconductance

60

V
100

nA

2.0

2.5

V

VGS = 4.5V, IDS = 30A

2.5

3.3

VGS = 10V, IDS = 30A

1.7

2.1

VDS = 6V, IDS = 30A

130

1.4

mΩ
S

DYNAMIC CHARACTERISTICS
CISS

Input capacitance

COSS

Output capacitance

CRSS

Reverse transfer capacitance

RG

Series gate resistance

Qg

Gate charge total (4.5 V)

Qg

Gate charge total (10 V)

Qgd

Gate charge gate-to-drain

Qgs

Gate charge gate-to-source

Qg(th)

Gate charge at Vth

QOSS

Output charge

td(on)trtd(off)Turnoff delay time

tf

Fall time

VGS = 0V, VDS = 30V,
ƒ = 1MHzVDS = 30V,
IDS = 30A

3720

4840

pF

670

870

pF

12

16

pF

0.9

1.8

Ω

21

27

nC

43

56

nC

7.0

nC

10.1

nC

6.3

nC

VDS = 30V, VGS = 0V

100

nC

Turnon delay time

9

ns

Rise time

VDS = 30V, VGS = 10V,
IDS = 30A, RG = 0Ω

20

ns

23

ns

3

ns

DIODE CHARACTERISTICS

4

VSD

Diode forward voltage

Qrr

Reverse recovery chargetrr

Reverse recovery time

IDS = 30A, VGS = 0V

0.8

VDS = 30V, IF = 30A,
di/dt = 300A/µs

172

nC

36

ns

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V

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Max RθJA = 125°C/W when
mounted on minimum padarea of 2oz (0.071mm) thickCu.

Max RθJA = 50°C/W when
mounted on 1in2 (6.45cm2)of 2oz (0.071mm) thick Cu.

4.6 Typical Power Block Device Characteristics
The typical power block system characteristic curves (Figure 4-1 through Figure 4-6) are based on
measurements made on a PCB design with dimensions of 4in (W) × 3.5in (L) × 0.062in (H) and 6 copper layersof 2oz copper thickness. See Section 5 section for detailed explanation. TJ = 125°C, unless stated otherwise.
1.2

8
TypicalMax

1.1

Power Loss, Normalized

7

5
4
3
2

1
0.9
0.8
0.7
0.6

1
0
0

5

10

15
20
25
Output Current (A)VIN = 36V
ƒSW = 20kHz

VDD = 10V
L = 480µH

30

35

0.5
-50

40

D.C. = 50%

104

Top Case Temperature (qC)
108
112
116
120

124

VDD = 10V
L = 480µH

125

150
D002

D.C. = 50%
IOUT = 40 A

1.4

2.7

1.3

2.1

1.2

1.4

1.1

0.7

1

0.0

0.9

-0.7

128

Power Loss, Normalized

35

Output Current (A)

25
50
75
100
Junction Temperature (qC)

Figure 4-2. Power Loss vs Temperature

TX

40

0

VIN = 36V
ƒSW = 20kHz

Figure 4-1. Power Loss vs Output Current
100
45

-25

D001

30
25
20
15
10

SOA Temperature Adj. (qC)

Power Loss (W)

6

5
0
100

0.8
104

108
112
116
120
Board Temperature (qC)

VIN = 36V
ƒSW = 20kHz

VDD = 10V
L = 480µH

124

128

5

10

D005

D.C. = 50%

Figure 4-3. Typical Safe Operating Area

15

20
25
30
35
Switching Frequency (kHz)

VIN = 36V
L = 480µH

VDD = 10V
D.C. = 50%

40

45

-1.4
50
D006

IOUT = 40A

Figure 4-4. Normalized Power Loss vs Switching
Frequency

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1.05

0.3

1.025

0.2

1

0.0

0.975

-0.2

0.95

-0.3

0.925

-0.5

0.9
15

20

25

D.C. = 50%
ƒSW = 20kHz

30
35
Input Voltage (V)VDD = 10V
L = 480µH

40

45

-0.7
50

1.2

1.4

1.15

1.0

1.1

0.7

1.05

0.3

1

0.0

0.95
10

20

30

40

50
60
70
Duty Cycle (%)

VIN = 36V
ƒSW = 20kHz

VDD = 10V
L = 480µH

D007

IOUT = 40A

Figure 4-5. Normalized Power Loss vs Input
Voltage

6

Power Loss, Normalized

0.5

SOA Temperature Adj. (qC)

Power Loss, Normalized

1.075

80

90

SOA Temperature Adj. (qC)

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-0.3
100
D009

Figure 4-6. Normalized Power Loss vs Duty Cycle

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4.7 Typical Power Block MOSFET Characteristics

450

200

400

180

IDS - Drain-to-Source Current (A)Single Pulse Current (A)TJ = 25°C, unless stated otherwise.

350
300
250
200
150
100
50

160
140
120
100
80
60
40

VGS = 4.5 V
VGS = 8 V
VGS = 10 V

20

0
1E-5

0

0.00010.001
0.01
Duration (s)

0.1

0

1

0.1

0.2

0.3 0.4 0.5 0.6 0.7 0.8
VDS - Drain-to-Source Voltage (V)

0.9

1
D010

Figure 4-8. MOSFET Saturation Characteristics

Max RθJA = 125°C/W

Figure 4-7. Single Pulse Current vs Pulse Duration
10
TC = 125° C
TC = 25° C
TC = -55° C

10

VGS - Gate-to-Source Voltage (V)IDS - Drain-to-Source Current (A)

100

1

0.1

0.01

0.001
0

0.5

1
1.5
2
2.5
VGS - Gate-to-Source Voltage (V)

3

9
8
7
6
5
4
3
2
1
0

3.5

0

D012

5

10

VDS = 5V

ID = 30A

Figure 4-9. MOSFET Transfer Characteristics

40

45

50
D014

VDS = 30V

Figure 4-10. MOSFET Gate Charge
2.55

VGS(th) - Threshold Voltage (V)10000

C - Capacitance (pF)

15
20
25
30
35
Qg - Gate Charge (nC)

1000

100

10
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
10

2.15
1.95
1.75
1.55
1.35
1.15

1
0

2.35

20
30
40
VDS - Drain-to-Source Voltage (V)

50

60

0.95
-75

-50

D016

Figure 4-11. MOSFET Capacitance

-25

0
25
50
75 100 125
TC - Case Temperature (° C)

150

175
D018

ID = 250µA

Figure 4-12. Threshold Voltage vs Temperature

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2

TC = 25° C
TC = 125° C

9Normalized On-State ResistanceRDS(on) - On-State Resistance (m:)

10

8
7
6
5
4
3
2
1
2

4

6
8
10
12
14
16
VGS - Gate-to-Source Voltage (V)

18

1.6
1.4
1.2
1
0.8
0.6
0.4
-75

0
0

VGS = 4.5 V
VGS = 10 V

1.8

20

-50

D020

150

175
D022

VDS = 30V

Figure 4-14. MOSFET Normalized RDS(on) vs
Temperature

Figure 4-13. MOSFET RDS(on) vs VGS

1000

100
TC = 25° C
TC = 125° C

10

IAV - Peak Avalanche Current (A)ISD - Source-to-Drain Current (A)02550
75 100 125
TC - Case Temperature (° C)

ID = 30A

ID = 30A

1
0.1
0.01
0.001
0.0001
0

0.2

0.4
0.6
0.8
VSD - Source-to-Drain Voltage (V)1

TC = 25q C
TC = 125q C

100

10

1
0.01

D024

Figure 4-15. MOSFET Body Diode Forward Voltage

8

-25

0.1
TAV - Time in Avalanche (ms)1
D026

Figure 4-16. MOSFET Single Pulse Unclamped
Inductive Switching

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5 Application and Implementation
Note
Information in the following Application section is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI customers are responsible for determining
suitability of components selection for their designs. Customers should validate and test their design
implementation to confirm system functionality.

5.1 Application Information
Historically, battery powered tools have favored brushed DC configurations to spin their primary motors, butmore recently, the advantages offered by brushless DC operation (BLDC) operation have brought about theadvent of popular designs that favor the latter. Those advantages include, but are not limited to higher efficiency
and therefore longer battery life, superior reliability, greater peak torque capability, and smooth operation overa wider range of speeds. However, BLDC designs put increased demand for higher power density and current
handling capabilities on the power stage responsible for driving the motor.
The CSD88599Q5DC is part of TI’s power block product family and is a highly optimized product designed
explicitly for the purpose driving higher current DC motors in power and gardening tools. It incorporates TI’s
latest generation silicon which has been optimized for low resistance to minimize conduction losses and offer
excellent thermal performance. The power block utilizes TI’s stacked die technology to offer one complete half
bridge vertically integrated into a single 5mm × 6mm package with a DualCool exposed metal case. This featureallows the designer to apply a heatsink to the top of the package and pull heat away from the PCB, thus
maximizing the power density while reducing the power stage footprint by up to 50%.

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5.2 Brushless DC Motor With Trapezoidal Control
The trapezoidal commutation control is simple and has fewer switching losses compared to sinusoidal control.
Vin

PB1
PWM1

DRV8323RX

SH1SPEED SETTORQUE SETMICROCONTROLLER

PWM2

Vin

Q1

GH1

Vin

PB2

GH1

PB3
Q2

GH2

Vin

Q3

GH3

GL1
PWM3
PWM4

SH2

SH1

GH2

Three Phase
Gate Driver

SH3

Vsw1

SH2

Vsw3

Vsw2

GL2

PWM5

U

GH3
PWM6

Q4

GL1

SH3

VCS

Q5

GL2

N

Q6

A
B
C

GL3
PGND
SPA

A
B
C
Hall
InputsGL3

Hall
Sensors

SPA

PGND
SPB

PGND
SPC

V

S

W

SPB
SPC
0

Rcs1

Rcs2

Rcs3

0

0

0

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Figure 5-1. Functional Block Diagram
The block diagram shown in Figure 5-1 offers a simple instruction of what is required to drive a BLDC motor: one
microcontroller, one three-phase driver IC, three power blocks (historically six power MOSFETs) and three Hall
effect sensors. The microcontroller responsible for block commutation must always know the rotor orientation or
its position relative to the stator coils. This is easy achieved with a brushed DC motor due to the fixed geometry
and position of the rotor windings, shaft and commutator.
A three-phase BLDC motor requires three Hall effect sensors or a rotary encoder to detect the rotor position
in relation to stator armature windings. With input from these three Hall effect sensors output signals, themicrocontroller can determine the proper commutation sequence. The three Hall sensors named A, B, and C
are mounted on the stator core at 120° intervals and the stator phase windings are implemented in a starconfiguration. For every 60° of motor rotation, one Hall sensor changes its state. Based on the Hall sensors'
output code, at the end of each block commutation interval the ampere conductors are commutated to the next
position. There are 6 steps required to complete a full electrical cycle. The number of block commutation cycles
to complete a full mechanical rotation is determined by the number of rotor pole pairs.

10

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1 0 1

1 0 0

1 1 0

0 1 0

0 1 1

0 0 1

i _ U
0

i _ V
0

i _ W
0

Figure 5-2. Winding Current Waveforms on a BLDC Motor
Figure 5-2 above shows the three phase motor winding currents i_U, i_V, and i_W when running at 100% duty
cycle.
Trapezoidal commutation control offers the following advantages:• Only two windings in series carry the phase winding current at any time while the third winding is open.
• Only one current sensor is necessary for all three windings U, V, and W.
• The position of the current sensor allows the use of low-cost shunt resistors.
However, trapezoidal commutation control has the disadvantage of commutation torque ripple. The current
sense on a three-phase inverter can be configured to use a single-shunt or three different sense resistors. For
cost sensitive applications targeting sensorless control, the three Hall effect sensors can be replaced with BEMF
voltage feedback dividers.
To obtain faster motor rotations and higher revolutions per minute (RPM), shorter periods and higher VIN voltage
are necessary. Contrarily, to reduce the rotational speed of the motor, it is necessary to lower the RMS voltage
applied across stator windings. This can easily be easily achieved by modulating the duty cycle, while maintaina constant switching frequency. Frequency for the three-phase inverter chosen is usually low between 10kHz to
50kHz to reduce winding losses and to avoid audible noise.

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5.3 Power Loss Curves
CSD88599Q5DC was designed to operate up to 10-cell Li-Ion battery voltage applications ranging from 30V
to 42V, typical 36V. For 11 and 12s, input voltages between 42V to 54V, RC snubbers are required for eachswitch-node U, V, and W. To reduce ringing, refer to the Section 5.8.1.1 section. In an effort to simplify the design
process, Texas Instruments has provided measured power loss performance curves over a variety of typicalconditions.
Figure 4-1 plots the CSD88599Q5DC power loss as a function of load current. The measured power loss
includes both input conversion loss and gate drive loss.
Equation 1 is used to generate the power loss curve:(1)Power loss (W) = (VIN × IIN_SHUNT) + (VDD × IDD_SHUNT) – (VSW_AVG × IOUT)

The power loss measurements were made on the circuit shown in Figure 5-3. Power block devices for legs
U and V, PB1 and PB2 were disabled by shorting the CSD88599Q5DC high-side and low-side FETs' gate-tosource terminals. Current shunt Iin_SHUNT provides input current and Idd_SHUNT provides driver supply
current measurements. The winding current is measured from the DC load. An averaging circuit provides switch
node W equivalent RMS voltage.
Iin_SHUNT

PB1
Cin1

Vin

Vin

PB2

Cin2

PB3

Idd_SHUNT

Vin

Vdd
0

0

GH1

GH2

SH1

SH2

Vsw1

Vin

Vdd

GH3
0

0

U

Vsw2

SH3
HI

V

Vsw3

W

GATE
DRIVER

Lout

U 1A
1

GL2

GL1

PGND
0

0

2

LI

DCR

GL3

PGND

0

0

Iout

PGND

0

0

LOAD

0

PWM

0

0

AVERAGING

AVERAGESWITCH NODECIRCUIT

Vsw_AVG

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Figure 5-3. Power Loss Test Circuit
The RMS current on the CSD88599Q5DC device depends on the motor winding current. For trapezoidal control,
the MOSFET RMS current is calculated using Equation 2.
(2)

IRMS = IOUT × √2

Taking into consideration system tolerances with the current measurement scheme, the inverter design needs towithstand a 20% overload current.
Table 5-1. RMS and Overload Current Calculations

12

Winding RMS Current (A)CSD88599Q5DC IRMS (A)Overload 20% × IRMS (A)

20

28

34

30

42

51

40

56

68

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5.4 Safe Operating Area (SOA) Curve
The SOA curve in Figure 4-3 provides guidance on the temperature boundaries within an operating system
by incorporating the thermal resistance and system power loss. This curve outlines the board and casetemperatures required for a given load current. The area under the curve dictates the safe operating area.
This curve is based on measurements made on a PCB design with dimensions of 4in (W) × 3.5in (L) × 0.062in(H) and 6 copper layers of 2oz copper thickness.

5.5 Normalized Power Loss Curves
The normalized curves in the CSD88599Q5DC data sheet provide guidance on the power loss and SOA
adjustments based on application specific needs. These curves show how the power loss and SOA temperatureboundaries will adjust for different operation conditions. The primary Y-axis is the normalized change in power
loss while the secondary Y-axis is the change in system temperature required in order to comply with the SOA
curve. The change in power loss is a multiplier for the typical power loss. The change in SOA temperature issubtracted from the SOA curve.

5.6 Design Example – Regulate Current to Maintain Safe Operation
If the case and board temperature of the power block are known, the SOA can be used to determine themaximum allowed current that will maintain operation within the safe operating area of the device. The following
procedure outlines how to determine the RMS current limit while maintaining operation within the confines of the
SOA, assuming the temperatures of the top of the package and PCB directly underneath the part are known.
1. Start at the maximum current of the device on the Y-axis and draw a line from this point at the known top
case temperature to the known PCB temperature.
2. Observe where this point intersects the TX line.
3. At this intersection with the TX line, draw vertical line until you hit the SOA current limit. This intercept is the
maximum allowed current at the corresponding power block PCB and case temperatures.
In the example below, we show how to achieve this for the temperatures TC = 124°C and TB = 120°C. First we
draw from 40 A on the Y-axis at 124°C to 120°C on the X-axis. Then, we draw a line up from where this line
crosses the TX line to see that this line intercepts the SOA at 34A. Thus we can assume if we are measuring a
PCB temperature of 124°C, and a top case temperature of 120°C, the power block can handle 34A RMS, at thenormalized conditions. At conditions that differ from those in Figure 4-1, the user may be required to make an
SOA temperature adjustment on the TX line, as shown in the next section.

Figure 5-4. Regulating Current to Maintain Safe Operation

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5.7 Design Example – Regulate Board and Case Temperature to Maintain Safe Operation
In the previous example we showed how given the PCB and case temperature, the current of the power block
could be limited to ensure operation within the SOA. Conversely, if the current and other application conditions
are known, one can determine from the SOA what board or case temperature the user will need to limit theirdesign to. The user can estimate product loss and SOA boundaries by arithmetic means. Though the power loss
and SOA curves in this data sheet are taken for a specific set of test conditions, the following procedure outlines
the steps the user should take to predict product performance for any set of system conditions.

14

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5.8 Layout
The two key system-level parameters that can be optimized with proper PCB design are electrical and thermal
performance. A proper PCB layout will yield maximum performance in both areas. Below are some tips for how
to address each.
5.8.1 Layout Guidelines
5.8.1.1 Electrical Performance

The CSD88599Q5DC power block has the ability to switch at voltage rates greater than 1kV/µs. Special caremust be then taken with the PCB layout design and placement of the input capacitors; high-current, high dI/dT
switching path; current shunt resistors; and GND return planes. As with any high-power inverter operated in
hard switching mode, there will be voltage ringing present on the switch nodes U, V, and W. Switch-node
ringing appears mainly at the HS FET turnon commutation with positive winding current direction. The U, V,
and W phase connections to the BLDC motor can be usually excluded from the ringing behavior since they
are subjected to high-peak currents but low dI/dT slew-rates. However, a compact PCB design with short andlow-parasitic loop inductances is critical to achieve low ringing and compliance with EMI specifications.
For safe and reliable operation of the three-phase inverter, motor phase currents have to be accurately
monitored and reported to the system microcontroller. One current sensor needs to be connected on each
motor phase winding U, V, and W. This sensing method is best for current sensing as it provides good accuracy
over a wide range of duty cycles, motor torque, and winding currents. Using current sensors is recommended
because it is less intrusive to the VIN and GND connections.
PB1

Vin

PB2

PB3

Vin

C4

Vin

C5

GH1

C6

GH2

GH3

0

0

0

SH3

SH2

SH1

U

Vsw

V

Vsw

W

Vsw

V in
C s1

GL3

GL2

GL1

C s3

C s2

PGND

PGND

PGND

R cs

R s1

R s2

R s3

GND
0

0

0

0

0

Copyright © 2017, Texas Instruments Incorporated

Figure 5-5. Recommended Ringing Reduction Components
However, for cost sensitive applications, current sensors are generally replaced with current sense resistors.
••

For designs using the 60V three-phase smart gate driver DRV8320SRHBR, current sense resistor RCS canbe placed between common source terminals for all 3 power block devices CSD88599Q5DC to PGND andmeasured using an external current sense amplifier as depicted in Figure 5-5 above.
For designs using the 60V three-phase gate driver DRV8323RSRGZT, three current sense resistors RCS1,
RCS2 and RCS3 can be used between each CSD88599Q5DC source terminal to GND and measured by the
included DRV8323 current sense amplifiers. The three-phase driver IC should be placed as close as possible
to the power block gate GL and GH terminals.

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Breaking the high-current flow path from the source terminals of the power block to GND by introducing the RCS
current shunt resistors introduces parasitic PCB inductance. In the event the switch node waveforms exhibits
peak ringing that reaches undesirable levels, the ringing can be reduced by using the following ringing reduction
components:•••

The use of a high-side gate resistor in series with the GH pin is one effective way to reduce peak ringing.
The recommended HS FET gate resistor value will range between 4.7Ω to 10Ω depending on the driver IC
output characteristics used in conjunction with the power block device. The low-side FET gate pin GL should
connect directly to the driver IC output to avoid any parasitic cdV/dT turnon effect.
Low-inductance MLCC caps C4, C5, and C6 can be used across each power block device from VIN
to the source terminal PGND. MLCC 10nF, 100V, ±10%, X7S, 0402, PN: C1005X7S2A103K050BB are
recommended.
Ringing can be reduced via the implementation of RC snubbers from each switch node U, V, and W to GND.
Recommended snubber component values are as follows:– Snubber resistors Rs1, Rs2, Rs3: 2.21Ω, 1%, 0.125W, 0805, PN: CRCW08052R21FKEA– Snubber caps Cs1, Cs2, and Cs3: MLCC 4.7nF, 100V, X7S, 0402, PN: C1005X7S2A472M050BB

With a switching frequency of 20kHz on the three-phase inverter, the power dissipation on the RC snubber
resistor is 80mW per channel. As a result, 0805 package size for resistors Rs1, Rs2, and Rs3 is sufficient.
5.8.1.2 Thermal Considerations

The CSD88599Q5DC power block device has the ability to utilize the PCB copper planes as the primary thermal
path. As such, the use of thermal vias included in the footprint is an effective way to pull away heat fromthe device and into the system board. Concerns regarding solder voids and manufacturability issues can beaddressed through the use of three basic tactics to minimize the amount of solder attach that will wick down thevia barrel.
• Intentionally space out the vias from one another to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed by the design. The example in Figure 5-6 uses vias with a 10-mil drill holeand a 16mil solder pad.
• Tent the opposite side of the via with solder-mask. Ultimately the number and drill size of the thermal vias
should align with the end user’s PCB design rules and manufacturing capabilities.
To take advantage of the DualCool thermally enhanced package, an external heatsink can be applied on top of
the power block devices. For low EMI, the heatsink is usually connected to GND through the mounting screws
to the PCB. Gap pad insulators with good thermal conductivity should be used between the top of the package
and the heatsink. The Bergquist Sil-Pad 980 is recommended which provides excellent thermal impedance of
1.07°C/W @ 50psi.

16

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5.8.2 Layout Example

Figure 5-6. Top Layer

Figure 5-7. Bottom Layer

The placement of the input capacitors C4, C5, and C6 relative to VIN and PGND pins of CSD88599Q5DC device
should have the highest priority during the component placement routine. It is critical to minimize the VIN to GND
parasitic loop inductance. A shunt resistor R21 is used between all three U4, U5, and U6 power block source
terminals to the input supply GND return pin.
Input RMS current filtering is achieved via two bulk caps C17 and C18. Based on the RMS current ratings, therecommended part number for input bulk is CAP AL, 330µF, 63V, ±20%, PN: EMVA630ADA331MKG5S.

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6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. Forchange details, review the revision history included in any revised document.

6.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straightfrom the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

6.3 Trademarks
NexFET™ and DualCool™ are trademarks of TI.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.

6.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handledwith appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.

6.5 Glossary
TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

7 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2018) to Revision D (June 2024)
Page• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1• Added PGND to the Top View pinout diagram................................................................................................... 1• Added Pin Configuration Table......................................................................................................................... 19

Changes from Revision B (January 2018) to Revision C (April 2018)
Page• Corrected Figure 5-4 to show 40A maximum................................................................................................... 13

Changes from Revision A (May 2017) to Revision B (January 2018)
Page• Updated the mechanical data........................................................................................................................... 19

Changes from Revision * (April 2017) to Revision A (May 2017)
Page• Updated Typical Circuit drawing......................................................................................................................... 1• Changed the copper thickness to 2oz in Typical Power Block Device Characteristics conditions..................... 5• Changed the copper thickness to 2oz in Safe Operating Area (SOA) Curve paragraph..................................13

18

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8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Table 8-1. Pin Configuration Table
POSITIONPIN NAME

DESCRIPTION

1GHHigh Side Gate

2

SHHigh Side Gate Return

3-11

VSW

Switch Node

12-20

PGND

Power Ground

21

NC

No Connect

22

GL

Low Side Gate

23-26

NC

No Connect

27

VIN

Input Voltage

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PACKAGE OPTION ADDENDUM
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24-Jun-2024

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking(3)

Samples

(4/5)

(6)

CSD88599Q5DC

ACTIVE

VSON-CLIP

DMM

22

2500

RoHS-Exempt& GreenSN

Level-1-260C-UNLIM-55 to 150

88599

Samples

CSD88599Q5DCTACTIVE

VSON-CLIP

DMM

22

250

RoHS-Exempt& GreenSN

Level-1-260C-UNLIM-55 to 150

88599

Samples(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM
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24-Jun-2024

Addendum-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

25-Sep-2024

TAPE AND REEL INFORMATIONREEL DIMENSIONSTAPE DIMENSIONS
K0

P1

B0 W
Reel
DiameterCavity
A0
B0
K0
W
P1

A0

Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers

Reel Width (W1)QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes

Q1

Q2

Q1

Q2

Q3

Q4

Q3

Q4

User Direction of Feed

Pocket Quadrants*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)CSD88599Q5DC

VSONCLIP

DMM

22

2500

330.0

15.4

CSD88599Q5DCTVSONCLIP

DMM

22

250

178.0

12.4

Pack Materials-Page 1

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

6.3

5.3

1.2

8.0

12.0

Q2

6.3

5.3

1.2

8.0

12.0

Q2

PACKAGE MATERIALS INFORMATION
www.ti.com

25-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)

W

L

H

*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)CSD88599Q5DC

VSON-CLIP

DMM

22

2500

333.2

345.9

28.6

CSD88599Q5DCTVSON-CLIP

DMM

22

250

180.0

180.0

79.0

Pack Materials-Page 2

PACKAGE OUTLINE

DMM0022A

LSON-CLIP - 1.05 mm max height
SCALE 2.200

PLASTIC SMALL OUTLINE - NO LEAD
A

5.1
4.9

B

PIN 1 INDEX AREA

6.1
5.9

2X (0.35)
3.329 0.1

EXPOSEDHEAT SLUG(0.701)2.284 0.1

(1.486)C

1.05 MAXSEATING PLANE
0.05
0.00

0.08 C

3.3 0.1
4X (1.9)

4X

2X (2)

0.48
0.38

4X (0.25)

24

25

11

12

4X (0.175)

EXPOSEDTHERMAL
PAD(0.2) TYP

2X (0.3)

2X
5

PKG

27

5.4 0.1

1
20X 0.5
PIN 1 ID
(OPTIONAL)

23

26

SYMM
22X

22

0.55
0.45

22X

0.3
0.2
0.1
0.05

C A
C

B
4222731/B 07/2020

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Tie bar size and position may vary.

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EXAMPLE BOARD LAYOUT

DMM0022A

LSON-CLIP - 1.05 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(3.3)
22X (0.7)

4X (2.115)
26

23(R0.05) TYP

1
2222X (0.25)

21

2
3

20

20X (0.5)

4X(3.013)

27

PKG

(5.4)
METAL UNDERSOLDER MASK
2X

6X
(1.32)SOLDER MASKOPENING
2X( 0.2) VIA
TYP

2X(1.13)
11(R0.05) TYP

1224

6X (1.4)25

SYMM
4X (0.375)(0.3) TYP

4X (0.43)(4.7)

LAND PATTERN EXAMPLESCALE:15X

0.05 MIN
ALL AROUND

0.05 MAXALL AROUNDSOLDER MASKOPENINGMETALMETAL UNDERSOLDER MASKNON SOLDER MASKDEFINED
PADS: 1, 2, 21-26
PAD 27: OPTIONALSOLDER MASKOPENINGSOLDER MASKDEFINED
PADS: 3-20
PAD 27: OPTIONALSOLDER MASK DETAILS
4222731/B 07/2020
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
6. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

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EXAMPLE STENCIL DESIGNDMM0022A

LSON-CLIP - 1.05 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM
22X (0.7)

4X (2.115)
METAL
TYP

23

26

8X (1.41)27

1

22
22X (0.25)

2

21

3

8X
(1.12)

20

4X(3.013)20X (0.5)

SYMM(0.66)
TYP(R0.05) TYP

METAL UNDERSOLDER MASK
2X

(1.32)
TYP

1211(0.8) TYP

24
4X (0.375)

25(0.3) TYP

4X (0.43)(4.7)

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCILEXPOSED PAD 23
71% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGESCALE:20X
4222731/B 07/2020

NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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