DATA SHEET
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Automotive Power Over
Coax Power Management
IC for Safety Camera
QFNW20 3.5x3.5, 0.5P
CASE 484AV

NCV92310
The NCV92310 is part of the onsemi image sensor power
management IC (PMIC) family. It is optimized to supply power overcoax (POC) automotive application sub−systems such as rear, frontand surround view cameras. This NCV92310 integrates one powerover coax DCDC converter, 2 high efficiency (1 A and 500 mA)
Step−down DCDC converters with DVS (Dynamic Voltage Scale) and1 low dropout (LDO) voltage regulators in a 3.5x3.5 mm QFNW20
package.

MARKING DIAGRAM
NCV92
310AB
AWLYWW

NCV92310AB
A
WL
Y
WW

Features• 1 Power Over Coax DCDC Converter (2.15 MHz, 2.2 mH/10 mF,

PGND3

PVIN3

FB3

PGND1

SDA

THERMAL
PAD

SW 1

/RST

AGND

SCL

VINLDO

SW 2

PGND2

PVIN2

FB2

May, 2024 − Rev. 0

SW 3

/INT

© Semiconductor Components Industries, LLC, 2024

VCORE

• Power Over Coax POL Supply• Automotive ADAS Camera Modules• Industrial Camera Modules

PVIN1

VOUTL
DO

Applications

PIN CONNECTIONS
FB1

1.2 A)♦ Programmable Output Voltage from 2.8 V to 5.0 V by 100 mV
Steps• 1 DCDC Converters (2.15 MHz, 1 mH/10 mF, 1 A)
♦ Programmable Output Voltage from 0.6 V to 2.175 V by 25 mV
Steps• 1 DCDC Converters (2.15 MHz, 1 mH/10 mF, 500 mA)♦ Programmable Output Voltage from 0.6 V to 2.175 V by 25 mV
Steps• 1 Low Noise − Low Drop Out Regulator (2.2 mF, 300 mA)♦ Programmable Output Voltage from 2.6 V to 3.3 V by 100 mV
Steps♦ 50 mVrms Typical Low Output Noise (Vout = 2.8 V, 10 Hz to
100 kHz)• Control♦ 400 kHz / 1 MHz I2C Compatible♦ I2C Enable Control Bits
♦ /RST and Interrupt Output Pin♦ Customizable Power Up / Down Sequence with Soft Start• Extended Input Voltage Range from 4.6 V to 18 V
• Footprint: 3.5x3.5 mm QFNW−20 0.5 mm Pitch= Specific Device Code= Assembly Location= Wafer Lot= Year= Work Week

(Top View)
20−Pins 3.5x3.5 0.50 mm pitch DFN

ORDERING INFORMATION
See detailed ordering and shipping information on page 59 of
this data sheet.

1

Publication Order Number:
NCV92310/D

NCV92310
TABLE OF CONTENTS
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Out Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Detailed Operating Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Functional Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I2C Compatible Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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NCV92310
4.6 V → 18 V
POC Input

PVIN1
10 mF
SW1
FB1

Vcore
1 mF

DCDC1 Out
2.2 mH
10 mF

PGND1

Core
AGND
DCDC 1
1.2 A
ThermalProtection

/RST

PVIN2
SW2

DCDC 2
1.0 A

GPIOs
/INT

FB2

1 mH

PGND2

SDA
SCL

10 mF

I2C

PVIN3

Power Upand Down
Sequencer

10 mF

SW3

DCDC 3500 mAFB3
PGND3

DCDC2 Out
10 mF

1 mH

DCDC3 Out
10 mF

VINLDOInternal
voltagemonitoring

LDO 1
300 mAVOUTLDOLDO1 Out
2.2 mF

Figure 1. Typical Application Circuit

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NCV92310
FUNCTIONAL BLOCK DIAGRAM

Voltage
Monitoring
2nd
Bandgap

Windows
Voltage
Comparators

FB1
Filtering

FB2
FB3
VOUTLDO

Bandgap

SDA

I2C
Interface
Oscillator
/INT
/RST
ENDCD C1VCORE

ENDCD C3
ENLDO

SCL

Ipeak pos neg fault DCDC1,2,3
Ilim fault LDO

TSD

Power
Up andDown
Sequence

ENDCD C2LDO

Core, Control
Logic and Soft
Start

OTP
MemoryPOR / UVLO /
OVF

AGND

VCORE

PVIN1

VCORE
Ipeak pos

PVIN2

Ipeak pos /neg fault
Ipeak pos
Ipeak pos /neg fault
Gate
DriverPWM
Regulation

PWM
Regulation

Gate
DriverSW1

SW2

Ipeak neg

PGND2
DAC

Ipeak neg

Vref
FB2
ActiveDischarge

PGND1
Vref

DAC

VCORE

FB1
Ipeak pos

ActiveDischarge

PVIN3

Ipeak pos /neg fault

VINLDO

Gate
DriverPWM
Regulation

Ilim

SW3

LDO Control+−

Ilim fault

DAC

Vref

Ipeak neg

PGND3
DAC

Vref
FB3

VOUTLDO
ActiveDischarge

ActiveDischarge

Figure 2. Simplified Block Diagram

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NCV92310
PIN OUT DESCRIPTION

PGND3

PVIN3

FB3

VCORE

FB1

PVIN1

SW 3

PGND1

SDA

THERMAL
PAD

SW 1

/RST

AGND

SCL

VINLDO

SW 2

PGND2

PVIN2

FB2

/INT

VOUTL
DO

Figure 3. Pin Out (Top view)

PIN FUNCTION DESCRIPTION
Pin

Name

Type

Description

GENERAL
19

VCORE

Analog Output

Reference voltage. A 1 mF ceramic capacitor (220 nF minimum) must bypass this pin to ground.

4

AGND

Analog Ground

Analog Ground. Analog and digital modules ground. Must be connected to the system ground.

7

/INT

Digital Output

Interrupt push−pull output.

13

/RST

Digital Output

Reset push−pull output.

12

SCL

Digital Input

I2C interface Clock

14

SDA

Digital Input

I2C interface Data

21

PAD

Exposed Pad

Exposed Pad. Must be soldered to system ground to achieve power dissipation performances.
This pin is internally unconnected.

PoC DC−DC CONVERTERS
1

PVIN1

Power Input

DCDC1 and Core Power Supply. This pin must be decoupled to ground by a 10 mF ceramic
capacitor. This capacitor should be placed as close as possible to this pin.

3

SW1Power Output

DCDC1 Switch Power. This pin connects the power transistors to one end of the inductor.
Typical application uses 2.2 mH inductor; refer to Application section for more information.

20

FB1

Analog Input

DCDC1 Feedback Voltage. This pin is the input to the error amplifier and must be connected tothe output capacitor.

2

PGND1

Power Ground

DCDC Power Ground. This pin is the power ground and carries the high switching current.
A high quality ground must be provided to prevent noise spikes. A local ground plane isrecommended to avoid high−density current flow in a limited PCB track.

1 A LOW VOLTAGE DC−DC CONVERTERS
9

PVIN2

Power Input

DCDC2 Power Supply. This pin must be decoupled to ground by a 10 mF ceramic capacitor.
This capacitor should be placed as close as possible to this pin.

11

SW2

Power Output

DCDC2 Switch Power. This pin connects the power transistors to one end of the inductor.
Typical application uses 1.0 mH inductor; refer to Application section for more information.

8

FB2

Analog Input

DCDC2 Feedback Voltage. This pin is the input to the error amplifier and must be connected tothe output capacitor.

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NCV92310
PIN FUNCTION DESCRIPTION (continued)
Pin

Name

Type

Description

1 A LOW VOLTAGE DC−DC CONVERTERS
10

PGND2

Power Ground

DCDC2 Power Ground. This pin is the power ground and carries the high switching current.
A high quality ground must be provided to prevent noise spikes. A local ground plane isrecommended to avoid high−density current flow in a limited PCB track.

500 mA LOW VOLTAGE DC−DC CONVERTERS
17

PVIN3

Power Input

DCDC3 Power Supply. This pin must be decoupled to ground by a 10 mF ceramic capacitor. This
capacitor should be placed as close as possible to this pin.

15

SW3

Power Output

DCDC3 Switch Power. This pin connects the power transistors to one end of the inductor.
Typical application uses 1.0 mH inductor; refer to Application section for more information.

18

FB3

Analog Input

DCDC3 Feedback Voltage. This pin is the input to the error amplifier and must be connected tothe output capacitor.

16

PGND3

Power Ground

DCDC3 Power Ground. This pin is the power ground and carries the high switching current.
A high quality ground must be provided to prevent noise spikes. A local ground plane isrecommended to avoid high−density current flow in a limited PCB track.

LDO REGULATORS
5

VINLDOPower Input

LDO Power Supply

6

VOUTLDO

Power Output

LDO Output Power. This pin requires a 2.2 mF decoupling capacitor.

MAXIMUM RATINGS
Min

Typ

Max

Unit

VP1−DC

SymbolPower Pins DC Non Switching: PVIN1, SW1 (Note 1)

Parameter

−0.3

−

20

V

VP2−DCPower Pins DC Non Switching: PVIN2, PVIN3, SW2, SW3 (Note 1)

−0.3

−

6.0

V

VA1−DC

Analog Pins DC Non Switching: FB2, FB3 (Note 1)

−0.3

−

VCORE

V

VA2−DC

Analog Pins DC Non Switching: VCORE, FB1, VINLDO, VOUTLDO (Note 1)

−0.3

−

6.0

V

VA3−DC

Analog Pins DC Non Switching: VOUTLDO (Note 1)

−0.3

−

VINLDOV

VP1−TR

Between PVIN1−PGND1 Pins, Transient 3 ns – 2.15 MHz (Note 1)

−0.3

−

24

V

VP2−TR

Between PVIN2−PGND2 and PVIN3−PGND3 Pins, Transient 3 ns – 2.15
MHz (Note 1)

−0.3

−

7.0

V

VDG1

Digital Pins: SDA, SCL, /INT (Note 1)

−0.3

−

6.0

V

VDG2

Digital Pins: /RST (Note 1)

−0.3

−

VCORE

V

HBM

ESD Withstand Voltage (Human Body Model) (Note 2)

500

−

−

V

CDM_CORNER

ESD Withstand Voltage (CDM)
PVIN1, VINLDO, VOUTLDO, SW2, SW3, FB1 (Note 2)

750

−

−

V

CDM

ESD Withstand Voltage (CDM) All Others Pins than Corners (Note 2)

500

−

−

V

ILU

Latch Up Current (Note 3)

−

100

−

mA

TSTG

Storage Temperature Range

−65

−

150

°C

TJMAX

Junction Temperature Range

−40

−

170

°C

MSL

Moisture Sensitivity (Note 4)−

Level1−Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series contains ESD protection and passes the following ratings:
Human Body Model (HBM) ±500 V per JEDEC standard: JESD22−A114.
Charged Device Model (CDM) 750 V (corner pins) and 500 V (others pins) per JEDEC standard: JESD22−C101 Class IV.
3. Latch up Current per JEDEC standard: JESD78 class II.
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.

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NCV92310
RECOMMENDED OPERATING CONDITIONS
Min

Typ

Max

Unit

PVIN1_RANGE

SymbolPower Input Supply

4.6

9

18

V

VVIN_RANGE

Power Input Supply

2.8

−

5.5

V

LOUT1

Inductor for the PoC DC to DC Converter (Note 5)

−

2.2

−

mH

LOUT2

Inductor for the 1 A LV DC to DC Converter (Note 5)

−

1.0

−

mH

LOUT3

Inductor for the 500 mA LV DC to DC Converter (Note 5)

−

1.0

−

mH

CCORE

Vcore Pin Capacitor (Note 5)0.120*1−mF

CPVIN1

Input Capacitor for the PoC DC to DC Converter (Note 5)

3*

10**

−

mF

CPVIN2

Input Capacitor for the 1 A LV DC to DC Converter (Note 5)

5*

10**

−

mF

CPVIN3

Input Capacitor for the 500 mA LV DC to DC Converter (Note 5)

5*

10**

−

mF

CVINLDO1

Input Capacitor for the Internal LDO
VINLDO Connected to the DCDC1 Output (Note 5)

−

0**

−

mF

CVINLDO2

Input Capacitor for the Internal LDO
VINLDO Connected to an External Supply (Note 5)

1**

2.2**

−

mF

COUT1

Output Capacitor for PoC DC to DC Converter (Note 5)

6.4*

10**

100**

mF

COUT2

Output Capacitor for the 1 A LV DC to DC Converter (Note 5)

5*

10**

100**

mF

COUT3

Output Capacitor for 500 mA LV DC to DC Converter (Note 5)

5*

10**

100**

mF

COUTLDO

Output Capacitor for the Internal LDO (Note 5)

1.65*

2.2**

47**

mF

Junction Temperature Range (Note 6)

−40

25

+150

°C

TJ

Parameter

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
* derated value.
** nominal value.
5. Including de−ratings (Refer to the Application Information section of this document for further details)
6. The thermal shutdown set to 170°C (typical) avoids potential irreversible damage on the device due to power dissipation.
7. The RqJA is dependent of the PCB heat dissipation. Board used to drive this data was a NCV92100EVB board.
8. The maximum power dissipation (PD) is dependent by input voltage, maximum output current, pcb stack up and layout, and external
components selected.

THERMAL INFORMATION

SymbolParameterJEDEC
JESD51−3(Calculated)

Demo
Board
(Measured)

Unit

qJ−C TOP

Thermal Resistance Junction to Case Top Resistance (Note 9)

27.6

−

°C/W

qJB

Thermal Resistance Junction to Bottom Top Resistance (Note 10)

1.6

−

°C/W

qJA

Thermal Resistance Junction to Ambient QFNW20 on Demo−board (Note 11)

31

35

°C/W

9. Calculated with infinite heatsink affixed to case top without any board present.
10. Calculated with infinite heatsink affixed to case bottom without any board present.
11. The RqJA is dependent of the PCB heat dissipation. Board used to drive this data was a NCV92100EVB board.

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NCV92310
ELECTRICAL CHARACTERISTICS (Refer to the Application Information section of this data sheet for more details. Min and Max
Limits apply for TJ = −40°C to +150°C, VIN range (PVIN_RANGE and VIN_RANGE) and default configuration, unless otherwise specified.
Typical values are referenced to TJ = +25°C, VIN = range and default configuration, unless otherwise specified.)Parameter

Symbol

Min

Typ

Max

Unit

−

13

−

mA

4.37

4.8

4.9

V

SUPPLY CURRENT: PIN VIN
IQOperating Quiescent Current, No Load Vin = 9 V, Default
Configuration

INTERNAL VOLTAGE REFERENCE
VCOREInternal Voltage Reference for Core Supply

DCDC1 (PoC DCDC CONVERTER)
VOUT1

Output Voltage Accuracy Vin Range, Iout Range

−1.5

−

+1.5

%

VOUT1_33_100mA

Default Output Voltage Vin = 9 V, Iout = 100 mA

3.2505

3.3

3.3495V

DMAX1Maximum Duty Cycle

−

92

−

%

DCLOAD1

Load Regulation, Iout from 100 mA to 1 A

−

0.05

−

%/A

DCLINE1

Line Regulation, Vin from 5 V to 18 V, Iout = 100 mA

−

0.001

−

%/V

IOUTMAX1

Output Current Range (Note 12)

1.2

−

−

A

ILIMP1

Output Peak Current High Side Switch (Note 12)

1.5

1.8

2.1

A

ILIMN1

Output Peak Current Low Side Switch (Note 12)

−

1

−

A

RON_H1High−Side MOSFET ON Resistance

−

385

−

mW

RON_L1

Low−Side MOSFET ON Resistance

−

250

−

mW

RDIS1

Internal Active Output Discharge, from FB to PGND Vout = 3.3 V

−

80

−

W

−1

−

+1

%

1.188

1.2

1.212

V

DCDC2 (1 A LV DCDC CONVERTER)
VOUT21
VOUT2_12_100mA

Output Voltage Accuracy
Vin Range, Vout Range, Iout Range
Default Output Voltage Vin = 3.3 V, Iout = 100 mA

DCLOAD2

Load Regulation, Iout from 100 mA to 1 A

−

0.05

−

%/A

DCLINE2

Line Regulation, Vin from 2.8 V to 5.5 V, Iout = 100 mA

−

0.001

−

%/V

IOUTMAX2

Output Current Range (Note 12)

1

−

−

A

ILIMP2

Output Peak Current High Side Switch
PVIN2 = 3.3 V (Note 12)

1.65

2.0

2.35

A

ILIMN2

Output Peak Current Low Side Switch
PVIN2 = 3.3 V (Note 12)

−

1.2

−

A

RON_H2High−Side MOSFET ON Resistance

−

120

−

mW

RON_L2

Low−Side MOSFET ON Resistance

−

90

−

mW

RDIS2

Internal Active Output Discharge, from FB to PGND Vout = 1.2 V

−

100

−

W

−1

−

+1

%

DCDC3 (500 mA LV DCDC CONVERTER)
VOUT31
VOUT3_18_100mA

Output Voltage Accuracy
Vin Range, Vout Range, Iout Range

1.782

1.8

1.818

V

DCLOAD3

Default Output Voltage Vin = 3.3 V, Iout = 100 mA
Load Regulation, Iout from 100 mA to 500 mA

−

0.05

−

%/A

DCLINE3

Line Regulation, Vin from 2.8 V to 5.5 V, Iout = 100 mA

−

0.001

−

%/V

IOUTMAX3

Output Current Range (Note 12)

0.5

−

−

A

ILIMP3

Output Peak Current High Side Switch
PVIN3 = 3.3 V (Note 12)

1.35

1.7

2.05

A

ILIMN3

Output Peak Current Low Side Switch
PVIN3 = 3.3 V (Note 12)

−

1.2

−

A

RON_H3High−Side MOSFET ON Resistance

−

220

−

mW

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NCV92310
ELECTRICAL CHARACTERISTICS (Refer to the Application Information section of this data sheet for more details. Min and Max
Limits apply for TJ = −40°C to +150°C, VIN range (PVIN_RANGE and VIN_RANGE) and default configuration, unless otherwise specified.
Typical values are referenced to TJ = +25°C, VIN = range and default configuration, unless otherwise specified.) (continued)
SymbolParameter

Min

Typ

Max

Unit

DCDC3 (500 mA LV DCDC CONVERTER)
RON_L3Low−Side MOSFET ON Resistance

−

145

−

mW

RDIS3

Internal Active Output Discharge, from FB to PGND Vout = 1.8 V

−

100

−

W

LOW DROPOUT REGULATORIOUTLDO_1

Maximum Output Current, VIN Range, VOUT ≤ VIN – 200 mV(Note 12)

300

−

−

mA

ILIMITLDO

Current Limit, VINLDO = 3.1 V, VOUTLDO = 2.8 V

350

−

620

mA

DVOUT_LDO_1

Output Voltage Accuracy, VIN = 3.3 V, VOUT = 2.8 V No Load

−1.0

VNOM

+1.0

%

DVOUT_LDO_2

Output Voltage Accuracy, VINLDO Range, IOUTLDO Range

−1.0

VNOM

+1.0

%

DCLOADLDO

Load Regulation, IOUT = 0 mA to 200 mA

−

0.04

−

%

DCLINELDOLine Regulation, VINLDO = 3.1 V to 5.5 V IOUTLDO = 200 mA

−

0.04

−

%

VDROP

Dropout Voltage, VOUT = 2.8 V, IOUT = 300 mA

80

110

210

mV

PSRR_1k

Ripple Rejection, F = 1 kHz
VINLDO = 3.3 V, VOUTLDO = 2.8 V, IOUTLDO = 100 mA

−

−80

−

dB

PSRR_10k

Ripple Rejection, F = 10 kHz
VINLDO = 3.3 V, VOUTLDO = 2.8V, IOUTLDO = 100 mA

−

−75

−

dB

PSRR_100k

Ripple Rejection, F = 100 kHz
VINLDO = 3.3 V, VOUTLDO = 2.8V, IOUTLDO = 100 mA

−

−60

−

dB

PSRR_1M

Ripple Rejection, F = 1 MHz
VINLDO = 3.3 V, VOUTLDO = 2.8V, IOUTLDO = 100 mA

−

−35

−

dB

Noise

Output Noise, 10 Hz → 100 kHz
VOUTLDO = 2.8 V

−

34

−

mV

RDISLDOLDO Active Output Discharge, VOUT = 2.8 V

−

105

−

W

VINUV−

VIN UVLO Falling Threshold, PVIN1 Pin, Default Setting

5

5.1

−

V

VINUV+

VIN UVLO Rising Threshold, PVIN1 Pin, Default Setting

6.8

7

V

UVLO AND OVLOVINUV−_RANGE

VIN UVLO Falling Threshold, PVIN1 Pin, Programmability Range(See Table x)

4.35

−

7

V

VINUV+_RANGE

VIN UVLO Rising Threshold, PVIN1 Pin, Programmability Range(See Table x)

4.5

−

8

V

VIN OVF Rising Threshold, PVIN1 Pin

18

18.3

18.6

V

VINOVHYSTVIN OVF Hysteresis

−

204

−

mV

VINOVDBN

VIN OVF Debounce Time, PVIN1 Pin

−

10

−

ms

VINOV+WINDOWS VOLTAGE MONITORING
VL

Undervoltage Detection Threshold, Programmability (3 Bits)

−10

−

−3

%

VH

Overvoltage Detection Threshold, Programmability (3 Bits)

3

−

10

%

VLH

Undervoltage Detection Hysteresis, VOUT ≤ 2.2 V

−

4.5

7.6

mV

VHH

Overvoltage Detection Hysteresis, VOUT ≤ 2.2 V

−

4.5

7.6

mV

VLH_SC

Undervoltage Detection Hysteresis, VOUT > 2.2 V

−

11.25

19

mV

VHH_SC

Overvoltage Detection Hysteresis, VOUT > 2.2 V

−

11.25

19

mV

DACC1

Detection Accuracy, 0.6 V ≤ VOUT < 1 V

−10

−

10

mV

DACC2

Detection Accuracy, VOUT ≥ 1 V

−1

−

1

%

TL_R

Undervoltage Detection Debounce Programmability, Rising Edge

32

−

256

ms

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NCV92310
ELECTRICAL CHARACTERISTICS (Refer to the Application Information section of this data sheet for more details. Min and Max
Limits apply for TJ = −40°C to +150°C, VIN range (PVIN_RANGE and VIN_RANGE) and default configuration, unless otherwise specified.
Typical values are referenced to TJ = +25°C, VIN = range and default configuration, unless otherwise specified.) (continued)
SymbolParameter

Min

Typ

Max

Unit

TL_F

Undervoltage Detection Debounce Programmability, Falling Edge

0

−

128

ms

TH_R

Overvoltage Detection Debounce Programmability, Rising Edge

0

−

128

ms

TH_F

Overvoltage Detection Debounce Programmability, Falling Edge

32

−

256

ms

VDISABLE_DCDC1

Disable Detection Threshold DCDC1

−

2000

−

mV

VDISABLE_DCDC2

Disable Detection Threshold DCDC2

−

600

−

mV

VDISABLE_DCDC3

Disable Detection Threshold DCDC3

−

600

−

mV

VDISABLE_LDO1

Disable Detection Threshold LDO1

−

100

−

mV

WINDOWS VOLTAGE MONITORING

TURN ON TIME AND SOFT−STARTTSSTurn ON time, Default Setting, from PVIN1 to Power Up Sequence
Start

−

5.12

−

ms

TSS1

Soft−start Time DCDC1, Time from 10% to 90% of Output Voltage
Target (Default Setting), Vout = 3.3 V

−

0.845

−

ms

TSS2

Soft−start Time DCDC2, Time from 10% to 90% of Output Voltage
Target (Default Setting), Vout = 1.2 V

−

0.31

−

ms

TSS3

Soft−start Time DCDC3, Time from 10% to 90% of Output Voltage
Target (Default Setting), Vout = 1.8 V

−

0.45

−

ms

TSS4

Soft−start Time LDO, Time from 10% to 90% of Output Voltage
Target (Default Setting), Vout = 2.8 V, COUT = 2.2 mF

−

1.45

−

ms

Internal System Clock

1.86

2.00

2.14

MHz

DCDC Switching Frequency

2

2.15

2.3

MHz

FDCDC2_DCDC1

Phase Shift between DCDC2 and DCDC1

−

120

−

°

FDCDC3_DCDC1

Phase Shift between DCDC3 and DCDC1

−

240

−

°

INTERNAL CLOCKS
CLKSYSOSC
FSW

THERMAL SHUTDOWN
TSD

Thermal Shutdown

−

163

−

°C

TWNG

Thermal Warning

−

152

−

°C

TWNGH

Thermal Warning Hysteresis

−

10

−

°C

TPWNG

Thermal Pre−Warning (Default)

−

138

−

°C

TPWNGH

Thermal Pre−Warning Hysteresis (Default)

−

6

−

°C

TGATING

Thermal Gating Threshold / Thermal Shutdown Low Threshold

−

125

−

°C

−

−

0.3

V

/RST AND /INT PINS (PUSH−PULL)
VINT_L/INT Pin Low Voltage, IINT = 3 mA

VINT_H1/INT Pin High Voltage, IINT = −3 mA VOUT ≥ 1.2 V

VOUT_DCDC3
x 0.65−−

V

VINT_H2/INT Pin High Voltage, IINT = −3 mA VOUT < 1.2 V

VOUT_DCDC3– 0.45−−V

VRST_L/RST Pin Low Voltage, IRST = 3 mA

−

−

0.3

V

VRST_H1/RST Pin High Voltage, IRST = −3 mA VOUT ≥ 1.2 V

VOUT_DCDC3
x 0.65−−V

VRST_H2/RST Pin High Voltage, IRST = −3 mA VOUT < 1.2 V

VOUT_DCDC3– 0.45−−

V

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NCV92310
ELECTRICAL CHARACTERISTICS (Refer to the Application Information section of this data sheet for more details. Min and Max
Limits apply for TJ = −40°C to +150°C, VIN range (PVIN_RANGE and VIN_RANGE) and default configuration, unless otherwise specified.
Typical values are referenced to TJ = +25°C, VIN = range and default configuration, unless otherwise specified.) (continued)
SymbolParameter

Min

Typ

Max

Unit

I2C INTERFACE
VI2C_HSCL and SDA Input Logic High (Note 13, 14, 15)

1.15

−

−

V

VI2C_LSCL and SDA Input Logic Low (Note 16)

−

−

0.45

V

VSDAO_LSDA Output Active Low, Sink 15 mA (Note 17)

−

−

0.4

V

ISDAO_HSDA Output Open Drain Leakage, 5.5 V

−

500

nA

FI2C

SCL Clock Frequency, 1.8 V Supplied I/O Rail (Note 13, 17, 18)

0

−

1

MHz

I2CSS

Pulse Width of Spikes that Must Be Suppressed by the Pinout
Filter (Note 19)

−

−

50

ns

CI2C

SCL and SDA Input Pin Capacitance

−

5

−

pF

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.
12. Junction temperature must be maintained below 150°C. Output load current capability depends on the application thermal capability.
13. In support of Fast Mode Plus, 1.8 V supplied I/O rails and the related 100 mV of drop totaling 1.7 V minimum.
14. For any input voltage greater than the minimum value indicated the signal is guaranteed detected high.
15. I2C typical VIO 1.8 V to 3.3 V.
16. For any input voltage smaller than the maximum value indicated the signal is guaranteed detected low.
17. Fast Mode Plus fall time (tf) and rise time (tr) required (120 ns maximum).
18. I2C bus frequency may be adjusted depending on the actual operating voltage, pull−up resistance, bus capacitance (which could be up to
400 pF) and master GPIO driver strength.
19. Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.

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NCV92310
TYPICAL OPERATING CHARACTERISTICS(PVIN1 = 9 V (Unless otherwise noted). TA = +25°C, DCDC2 = 1.20 V, DCDC2 = 1.3 V, LDO1 = 2.8 V, CLDO = 2.2 mF 0603, LDCDC = 1.0 mH(2016) − CDCDC = 10 mF 0603 / X7T)

PVIN1 = 9 V

PVIN1 = 12 V

90

90

80

80

70
60
50

−40°C

100

EFF (%)EFF (%)

100

25°C

60

0

0.2

0.4

0.6

0.8

50

1

0

0.5

−40°C

100

25°C

1
(A)

Figure 4. DCDC1 Efficiency vs. ILOAD and VIN,
VOUT = 3.30 V, TFM252012ALMA2R2 Inductor
105°C

Figure 5. DCDC1 Efficiency Temperature
VIN = 9.0 V, VOUT = 3.30 V, TFM252012ALMA2R2 Inductor

125°C

−40°C

100

90

90

80

80

EFF (%)EFF (%)125°C

70

IOUT1 (A)

70
60
50

105°C

25°C

105°C

125°C

70
60

0

0.5

50

1
(A)

−40°C

25°C

0.1

0.2

0.5

1
(A)

Figure 6. DCDC1 Efficiency Temperature
VIN = 12.0 V, VOUT = 3.30 V, TFM252012ALMA2R2 Inductor
100

0

105°C

Figure 7. DCDC2 Efficiency vs. ILOAD and Temperature
VIN = 3.3 V, VOUT = 1.2 V, DFEMCAH2R2 Inductor

125°C

EFF (%)

90
80
70
60
50

0

0.3

0.4

0.5

Figure 9. DCDC1 Load Transient
VIN = 9 V, VOUT = 3.3 V, ILOAD from 10 mA to 1A(A)

Figure 8. DCDC3 Efficiency vs. ILOAD and Temperature
VIN = 3.3 V, VOUT = 1.8 V, DFEMCAH2R2 Inductor
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NCV92310
TYPICAL OPERATING CHARACTERISTICS(PVIN1 = 9 V (Unless otherwise noted). TA = +25°C, DCDC2 = 1.20 V, DCDC2 = 1.3 V, LDO1 = 2.8 V, CLDO = 2.2 mF 0603, LDCDC = 1.0 mH(2016) − CDCDC = 10 mF 0603 / X7T) (Continued)

Figure 10. DCDC2 Load Transient
VIN = 3.3 V, VOUT = 1.2 V, ILOAD from 10 mA to 1 A

Figure 11. DCDC3 Load Transient
VIN = 3.3 V, VOUT = 1.8 V, ILOAD from 10 mA to 500 mA

0

100000−10Noise (nV/sqrt Hz)

PSRR (dB)

−20
−30
−40
−50
−60
−70

10000

1000

100

−80
−90
100

1000

10000

10000010
0.01

1000000

Frequency (Hz)

0.1

1

10

100

Frequency (Hz)Figure 13. LDO Output Noise
VIN = 3.3 V, VOUT = 2.8 V, IOUT = 100 mA)

Figure 12. LDO1 PSRR
VIN = 3.3 V, VOUT = 2.8 V, IOUT = 100 mA

Figure 14. LDO1 Load Transient
VIN = 3.3 V, VOUT = 2.8 V, ILOAD from 10 mA to 300 mA

Figure 15. Power−up Sequence Example

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1000

NCV92310
DETAILED OPERATING DESCRIPTION
Generalmonitors are also used to verify if the order of the power up
and power down sequences are respected. Both mechanisms
are essential in reaching a high level of functional safety.
The overall operation of the NCV92310 PMIC isgoverned by a state machine that will handle theinitialization of the IC and the built−in self−test, the fault
states, and the different operating modes.
All regulators include an active output discharge which
can be independently enabled / disabled by the appropriate
settings in the DIS register (refer to the register definition
section). However to prevent any disturbances on the
power−up sequence, a quick active output discharge is done
during the start−up sequence for all output channels.

The NCV92310 is optimized to supply cameras ofautomotive Power over Coax applications.
It integrates one Power Over Coax switched mode DCDC
converters, two low voltage switched mode DCDC
converters and one low dropout linear regulator. The IC is
widely programmable through an I2C interface with adefault setting provided by the internal OTP memory set
during the manufacturing process. The core of theNCV92310 is supplied from PVIN1 from where a low
voltage core voltage VCORE is derived. The VCORE
supplies most of the on−chip analog and digital circuitry.
PVIN1 can be supplied from a 5 V regulated source orconnected directly to the filtered power over coax supply.
The output voltage range, current capabilities andperformances of the switched mode DCDC converters arewell suited to supply a camera module. For PWM operation,
the converters run on a local 2.15 MHz. All the switchingcomponents are integrated including the compensation
networks and synchronous rectifier. Only a small size
inductor (2.2 mH for the PoC DCDC and 1 mH for the LV
DCDCs) and 10 mF bypass capacitor are required for typicalapplications. Higher output capacitor value may be needed
depending on the load transient requirement.
The low noise low dropout regulator can be used to supply
the lower power rails in the application. The regulator is
bypassed with a small size 2.2 mF capacitor. Higher output
capacitor value may be needed depending on the loadtransient requirement.
The low voltage regulators (DCDC2, DCDC3, LDO1)
each have their own input supply pin to be able to connect
it either independently to the system supply rail or to the
DCDC converter output, in the application. Like DCDC1,
each converter and LDO is enabled smoothly with acontrolled ramp up in order to avoid any inrush current.
All supply rails are monitored by on−chip voltage window
monitors. The window size and detection speed areprogrammable. When a monitor is tripped, an interrupt isgenerated and shutdown scenarios can be engaged. The

DCDCs PWM Mode Operation

All internal DCDCs operate in PWM mode from a fixedclock and adapts its duty cycle to regulate the desired output
voltage. In this mode, the inductor current is in CCM and thevoltage is regulated by PWM. The internal low side switch
operates as synchronous rectifier and is driven
complementary to the high side switch. In CCM, the lower
side switch in a synchronous converter provides a lower
voltage drop than the diode in an asynchronous converter,
which provides less loss and higher efficiency.
DCDCs Switching Clock and Spread Spectrum

Switching Clock of the 3 DCDCs operates at 2.15 MHz.
To avoid a too high inrush current, a phase shift is applied foreach DCDC converter (DCDC1: 0°, DCDC2: 120°,
DCDC3: 240°)
In order to optimize the peak emission of the DC to DC
converters switching frequency, a frequency spreading
option allows to spread the switching frequency of theconverters which can be useful in meeting system EMI
requirements. This option, available with on chip internal
oscillator, is factory programmable and can be changed thru
I2C.
NCV92310 integrates a random spread spectrum (16frequencies) with OTPs and I2C programmable tolerance(5% max and 10% max).

ÁÁÁÁÁÁÁÁ +
ÁÁÁÁ−7% +7%1.80

2.00 2.15 2.30

MHz

ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ForbiddenBand< 1.8 MHz

1.80

1.80

2.00 2.15 2.30

2.53 MHzÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
+17.7%−16.3%
Forbidden
NCV92310 FSW
Band
Tolerance + Spread Spectrum< 1.8 MHzFree Band
2.0 to 2.3
MHz2.00 2.15 2.30

ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
−10 %
+10 %
Maximum
Spread Spectrum
Variation

FSW
Tolerance

MHz

1.80

2.00 2.15 2.30

2.53 MHz

Figure 16. Tolerance + Spread Spectrum with Spread = 10% Max

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NCV92310
Different spread spectrum modulations are available
based on 16 frequency bins. By default, the triangular
double peak modulation is used with OTPs and I2C
programmable tolerance (±5% max, ±10% max). The
frequency change can occur every n buck cycles (n is spread

spectrum modulation divider from 1 to 128). Resulting
modulation frequency is
FM +

F SW
n

(eq. 1)32(with n is spread spectrum modulation divider)

Frequency+DFSW

PATTERN

FSWC
FSWC: Unmodulated Frequency
FM: Modulation Frequency
DFSW: Switching frequency deviation

−DFSW

Time

TM = 1 / FM

Figure 17. Tolerance + Spread Spectrum with Spread = 10% Max
Regulator Stability

Pseudorandom modulation with 16 bits pattern is alsoavailable.

DCDC Regulators
DCDC1, DCDC2 and DCDC3 use a voltage modearchitecture. Regulators stability depends on the output LC
filter.
Each regulator embeds an OTP bit that allow managing
the stability versus the total output capacitor value. With thedefault inductor value (DCDC1 = 2.2 mH, DCDC2 and
DCDC3 = 1 mH), output capacitor range without derating is:• 10 mF to 50 mF (default setting).
• 50 mF to 100 mF.

Low Dropout Regulator

Internal LDO is a low noise, high PSRR and highbandwidth regulator intended to supply image sensor analog
pixel input.
Its extended bandwidth allows best in class load transient
performances, which helps improve image quality.
Internal LDO limit the output current at 90 mA worst case
(ILDO_STARTUP) during the startup phase. LDO soft startsetting and total output capacitor connected at the
VOUTLDO is selected by the following equation:
Cout_ldo_max + Ildo_startup

Dt
DV

Low Dropout Regulator
Bandwidth of the low dropout regulator has been adapted
to improve the load transient response. In case lower ripple
is required, internal LDO of the NCV92310 allows using
high output capacitor value. In that case, internal stability
has to be set thru OTP:
• Up to 50 mF (default setting).
• 50 mF to 100 mF.

(eq. 2)

If COUT_LDO exceed COUT_LDO_MAX, internal shortcircuit protection may be triggered.
Soft Start Time Setting

Soft start timing is set thru I2C and On Time
Programmable internal memory.
Table 1. SOFT START SETTINGS
Buck Soft Start Time (ms)LDO Soft Start Time (ms)0.64(ms/V) x VOUT

1.28(ms/V) x VOUT

0.32(ms/V) x VOUT (default)

0.64(ms/V) x VOUT (default)

0.16(ms/V) x VOUT

0.32(ms/V) x VOUT

0.08(ms/V) x VOUT

0.16(ms/V) x VOUT

It allows limiting the inrush current at the input during thepower−up sequence.

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NCV92310
STATE MACHINEThe overall operation of the NCV92310 is governed by astate machine that handles the initialization of the IC and thebuilt−in self−test, the fault states, and the different operating
modes.

UN
POWERED

Removal of All
Power

Power
of Logic
Power

RESET

The below diagram represents the behavior as describedin the remainder of this document.

INITIALIZATION STATES

Retry

INIT

BIST

Power
of Analog
Power

Reapplicationof logic power

INIT OK

INIT Failure

OFF

BIST OK

BIST Failure
Valid Enable

PD DonePU−SEQ

PD−SEQ

Unlock

Auto
Rearm

LOCK

Reset PD Done

OPERATIONAL STATES

Shutdown DoneNo Rearm

PU F ault

PU DoneFlag

INVALIDRESETPD−SEQ

ERROR
PD

Fatal Error

Forced Reset

Error

DisableFAULT
PD

ACTIVE

Fault

From Any StateTi me Out
Fault

Fla g
Flag
ClearedACTIVEFLAG

Soft Reset

ERROR and FAULT HANDLING

Figure 18. Default State Machine

The state machine is comprised of a number of states ofwhich some are only transitional. The state machinetransitions from state to state based on certain specificconditions. Below tables provide a detailed description ofeach of the states as well as of the transitions.

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NCV92310
Table 2. STATE MACHINE STATES
Group

State

Type

RSTB

INTB

I2C

Description

NO POWER

−

−

−

−

−

The supply conditions on PVIN1 and VCORE are
too low for the state machine to operate.

INITIALIZATIONRESETSteadyL

L

No

Only the logic circuitry has sufficient supply and isbeing held in reset.

INIT

Transitional

L

L

No

Upon entry, all logic is reset to default and OTP
content is loaded. The analog circuitry is enabled.

BIST

Transitional

L

L

No

Upon entry, a built−in self−test is started

OFF

SteadyLl

R/W

The IC is biased and ready to accept a power up
sequence request

ACTIVE

SteadyRl

R/W

A power up sequence has been executed and the
IC is operating normally

ACTIVE
FLAG

Transitional

R

L

R/W

Similar to ACTIVE but a flag is raised and uponentry a flag timer starts running

PU−SEQ

Transitional

See
PUS

See
PUS

R onlyUpon entry, a power up sequence is started.

PD−SEQ

Transitional

See
PDS

See
PDS

R onlyUpon entry, a power down sequence is started

RESET
PD−SEQ

TransitionalLl

R onlyUpon entry, a power down sequence is started

FAULT PD

TransitionalLl

R onlyUpon entry, all supplies are powered down
simultaneously. Internal delay equal to PDS Time
Out delay is integrated before going to next state

ERROR PD

TransitionalLl

R onlyUpon entry, all supplies are powered down
simultaneously

LOCK

SteadyLl

R/W

The state machine is in the safe state with all
supplies disabled.

INVALID

SteadyLl

No

Upon entry, an emergency powered down is
initiated and product set in reset.

OPERATIONALERROR & FAULTHANDLING

L means Low, R means Released, I reflect the actual state of the Interrupts

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NCV92310
Table 3. STATE MACHINE TRANSITIONSTransition

From

To

Description

Application of
Logic PowerNO POWERRESETApplication of
Analog Power

RESET

INIT

PVIN1 becomes greater than the PVIN1 undervoltage lockout detection level

INIT Done

INIT

BIST

The initialization has been finished

BIST OK

BIST

OFF

The built−in self−test was successful

BIST Failure

BIST

LOCK

The built−in self−test failed, and the BIST error counter has reached its limit

Retry

BIST

BIST

The built−in self−test failed, the BIST error counter has not reached its limit,
and a new built in self−test is started

Valid Enable

OFF

PU−SEQ

A power up sequence is requested through I2C

PU DonePU−SEQACTIVEThe power up sequence has been executed and no faults are detected in
the sequencing

PU Fault

PU−SEQFAULT PD

A fault is detected during the power up sequence

Flag

ACTIVE

ACTIVE FLAG

Flag Cleared

ACTIVE FLAG

ACTIVEThe signaled event is cleared by the host through I2C before a time out
occursTime Out Fault

ACTIVE FLAG

FAULT PD

The signaled event is not cleared in time by the host

DisableACTIVE &ACTIVE FLAG

PD−SEQ

A power down sequence is requested through I2C

PD Done

ACTIVE &ACTIVE FLAGOFF

The power down sequence has been executed

Reset PD DoneRESET PD−SEQ

INIT

The power down sequence has been executedSoft Reset

ACTIVE &ACTIVE FLAG

ACTIVE &ACTIVE FLAG

Fault

ACTIVE &ACTIVE FLAG

FAULT PD

A fault is detected that necessitates a power down

Forced reset

Any State

RESET PD−SEQ

A power down sequence is requested through I2C.

Error

Any State

ERROR PD

Fatal Error

Any State

INVALID

Removal of Logic
Power

Any State

UNPOWEREDPVIN1 falls below the logic POR threshold

INVALIDUNPOWEREDPVIN1 falls below the logic POR threshold. Power cycling is the only way torecover from an internal clock error

Reapplication of
Logic PowerINVALIDRESETVCORE supply recovers its default voltage from a previous short circuit
condition

Shutdown DoneERROR PDLOCKThe shutdown has been executedAuto Rearm

FAULT PDBIST

A shutdown has been executed and the fault counter has not reached its
limit. Only allowed if the source of the fault has disappeared.

No Rearm

FAULT PD

LOCK

A shutdown has been executed and the fault counter has reached its limit

UnlockLOCKINIT

An unlock has been requested through I2C or a restart after TSD or UVLO
was permitted. The transition is only permitted if the source of the error has
disappeared.
NOTE: The IC can also be unlocked by cycling power (from any state,removal of logic power and reapplication).

PVIN1 becomes greater than the logic undervoltage detection level

An event occurred and is signaled to the host through INTBThe RSTB pin is temporarily made low by the Watchdog engine, or uponrequest through I2C

An abnormal operation condition has occurred which necessitates a powerdown
A short circuit condition is detected at VCORE or an internal clock error
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NCV92310
Auto Rearm Description

Power Up Sequence
All supply rails can be assigned to the power up sequencer.
The sequence can be started upon application of power at
PVIN1 or through I2C. The sequence is preprogrammed
through OTP but can be overwritten through I2C as well.
Once a sequence is started it cannot be interrupted with the
exception of the occurrence of a fault or error.
A sequence is built up out of three portions: initialization,
the sequence with its slots, and a sequence done wait period.
During the initialization it is verified that all assigned rails
have no residual voltage on their outputs. A delay can beinserted before starting the first rail, allowing for a delay
between the request for a power up sequence and the actual
start. The sequence itself consists of slots, and at each slot, one
or more power rails can be enabled. A slot is started after therails of the previous slot are successfully powered up plus anoptional delay. The sequence done wait period is added at theend of the sequence and can be used to delay the RSTB signal.
During the initialization phase, the active discharge on theassigned rails is enabled. If, at the end of the initialization
phase, one of the assigned supply rails still has a residual
voltage on its output, this event is logged and a power up
sequence is not started.
A supply is considered enabled when its output voltage isestablished above the undervoltage detection thresholds ofthat rail, including its debounce “See VOLTAGE
MONITORING” section.
Each rail needs to power up within a timeout period. Incase of a timeout, the sequence is considered fault and a
shutdown is engaged. The event, and the rail causing this arelogged. The device will attempt a new startup sequence if theconditions allow.
Rails can be enabled while operating the device. Whenenabling, and if that rail is originally assigned to a power up
sequence, it is being verified that the rail powers up within
the timeout period. Any violation is logged. The violation
can be cleared through I2C.
The sequence will power up each voltage rail at its default
output voltage setting as set through OTP. This default
setting can be overwritten through I2C.
During the power up sequence, and despite the soft startmechanisms in place, it may be that, during the soft start of
DCDC1, the PVIN1 trips the undervoltage lockout detection
due to an excessive impedance of the coaxial cable. If
DCDC1 is assigned to slot 0 and enabled, and only in thisspecific case, the device enters a hiccup mode. The power up
sequence is aborted so the input supply can recover, andonce recovered, the device will continue to soft start DCDC1
repeatedly until the rail is successfully powered up within
the timeout period. In all other configurations (DCDC1
assigned to another slot, disabled or another rail assigned toslot 0), this recovery procedure is not supported.

Aftera“FAULT”,
if
AutoRearmCnt<
AutoRearmCntMax (I2C and OTP programmable)
NCV92310 restart automatically and goes to the BIST state.
if AutoRearmCnt = AutoRearmCntMax, NCV92310
goes in LOCK mode. PVIN1 has to be removed and applied
again to restart the NCV92310. Otherwise a new power−up
sequence is started.
and“FUNCTIONAL
See“INTERRUPTION”
SAFETY” sections to have the FAULT description.
Table 4. AUTO REARM COUNTER
Bits

AutoRearmCnt_max

00

No restart

01

3

10

15

11

63

Bist Retry Description

BIST error has its own error counter. If BistCnt < BistCnt
max, a BIST retry is performed. If BistCnt = BistCntMax(I2C and OTP programmable), NCV92310 goes in lockmode.
Table 5. BIST COUNTER
Bits

BistCnt_max

0

No retry11

Unlock Description

Once in lock state, NCV92310 regulators are off with
INTB and RSTB pins low. Any I2C command to start a new
power−up sequence or enable one of the regulators will beacknowledged, but power up sequence cannot start if theNCV92310 is locked.
To recover, the NCV92310 must receive one of thefollowing unlock commands.
• Cycling power on PVIN1 pin or• Set high NLOCK bit or• In case of TSD having TSD_REARM bit set high or• In case of UVLO having UVLO_REARM bit set high.
After an unlock command, NCV92310 goes in INIT state
and reloads the default value of the OTP by resetting all theregisters
withtheexception
ofthe
INTERRUPT_FLAG_ERR1 and
INTERRUPT_FLAG_ERR2 registers.

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NCV92310
POWER UP SEQUENCER (PU−SEQ)
SLOT 0OFF

Valid
EnablePU
INIT

PU INIT
Done

SLOT 0INIT

SLOT 0 INIT
Done

SLOT 0DELAY

SLOT xSLOT 0
DELAY Done
Slot empty

SLOT 0 DELAY Done
Slot not empty

Outputs notdisabled

Slot 0 Timeout

Soft
Start 0SLOT 0WAIT

SLOT xINIT

AllowSLOT 0 WAIT
Done

SLOT x INIT
Done

Reset Delay
ExpiredSLOT x
DELAY

Output 0 Validated

Undervoltage
Lockout*

ERROR

Slot 0 Timeout
During Hiccup

Error

PD

INTB

SLOT x
DELAY Done
Slot empty

SLOT x DELAY Done
Slot not empty

Allow

SLOT xWAIT
SLOT x WAIT
Done

RSTB
Assigned
Slots
Remaining

All Assigned
Slots
Done

SupplyRecovers

HICCUPCheck

HICCUP
RestartUndervoltage
Lockout*

Output 0 Validated
During HiccupSoft
Start xSLOT xEnd

Output x Validated

PU Done

ACTIVE

Slot x Timeout

FAULT
PD

PU Fault

Fault for validated slots

From any PU−SEQ state* For all other states, an undervoltage lockout will cause a direct transition to ERROR PD

Figure 19. Power−up Sequence State Machine

Table 6. POWER UP SEQUENCER STATESGroupSLOT 0SLOT x

State

Type

I2C

Description

PU INIT

Transitional

R onlyOnly the active discharge on all assigned rails are activated, a timeout isstarted (64 ms max), the output voltage of the rails are verified with respect tothe disable threshold. The state of INTB is frozen and will not change during
the power up sequence itself, RSTB is forced low,

Allow INTB

Transitional

R onlyThe INTB pin is no longer frozen and reflects the actual state of the interrupts,
a sequence done wait timer is started

Allow RSTB

Transitional

R onlyThe RSTB pin is released

SLOT 0 INIT

Transitional

R onlyUpon entry, the slot counter is set to 0, the active discharge of the rails assigned
to slot 0 are disabled

SLOT 0 DELAY

Transitional

R onlyAn initial delay timer is started upon entry

SLOT 0 WAIT

Transitional

R onlyAn optional slot length wait timer is started upon entry

Soft Start 0

Transitional

R onlyThe slot length timer is started upon entry and the assigned rails are rampedup

HICCUP Check

Transitional

R onlyThe ramp up of the assigned rails is stopped, the active discharge remains
disabled, the slot length timer continues running, the under voltage lockout ischecked.

HICCUP
RestartTransitional

R onlyThe soft start resumes. The active discharge remains disabled, the slot length
timer continues running.

SLOT x INIT

Transitional

R onlyUpon entry the slot counter is increased with +1, the active discharge of therails assigned to slot x are disabled

SLOT x DELAY

Transitional

R onlyAn optional initial delay timer is started upon entry

SLOT x WAIT

Transitional

R onlyAn optional slot length wait timer is started upon entry

Soft Start x

Transitional

R onlyThe slot length timer is started upon entry and the assigned rails are ramped up

SLOT x End

Transitional

R onlyUpon entry it is verified if there is still an assigned rail on the remaining slots

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NCV92310
Table 7. POWER UP SEQUENCER TRANSITIONSTransition

From

To

Valid Enable

OFF(PU−SEQ) PU
INIT

Description
A power up sequence is requested through I2C, or, in case the GPIO isconfigured for this, through the HWEN signal going high.

PU Fault(PU−SEQ)

FAULT PD

A fault is detected during the power up sequence

Outputs Not
Disabled

PU INITFAULT PD

After the initialization timeout, one or more of the assigned rails still has
a residual voltage above the disable threshold. The state of non−assigned rails
has no influence.

PU INIT Done

PU INITSLOT 0 INIT

The PU INIT has been executed and no faults are detected

SLOT 0 INIT
Done

SLOT 0 INIT

SLOT 0 DELAY

The SLOT 0 INIT has been executed

SLOT 0 DELAY SLOT 0 DELAY
Done, Slot Empty

SLOT 0 WAIT

The initial delay timer has expired and slot 0 is not assigned

SLOT 0 WAIT
Done

SLOT 0 WAIT

SLOT x INIT

The optional slot wait timer has expired

SLOT 0 DELAY
Done, Slot Not
Empty

SLOT 0 DELAY

Soft Start 0

The initial delay timer has expired and slot 0 is assigned

Output 0
Validated

Soft Start 0

SLOT x INIT

The output voltage of all the rails assigned to slot 0 have raised to above theundervoltage detection level for that rail

Slot 0 Timeout

Soft Start 0

FAULT PD

The output voltage of one or more of the rails assigned to slot 0 did not cross theundervoltage detection level for that rail within the slot timeout

Undervoltage
Lockout

Soft Start 0 &HICCUP
RestartHICCUP Check

An undervoltage lockout is detected at PVIN1 during the ramp up of DCDC1.
This transition is allowed if, and only if, DCDC1 is enabled and assigned to Slot
0. In all other cases an undervoltage lockout is treated as an abnormal operating
condition leading to ERROR PD.

SupplyRecovers

HICCUP Check

HICCUP
Restart

The input supply at PVIN1 raised to above the undervoltage lockout threshold

Output 0
Validated
During Hiccup

HICCUP
Restart

SLOT x INIT

The output voltage of all the rails assigned to slot 0 have raised to above theundervoltage detection level for that rail

Slot 0 Timeout
During Hiccup

HICCUP Check& HICCUP
RestartERROR PD

The input supply at PVIN1 did not raise to above the undervoltage lockout
threshold before the slot timeout, or the rails assigned to slot 0 did not cross theundervoltage detection level for that rail within the slot timeout

SLOT x INIT
Done

SLOT x INIT

SLOT x DELAY

The SLOT x INIT has been executed

SLOT x DELAY SLOT x DELAY
Done, Slot Empty

SLOT x WAIT

The initial delay timer has expired and slot x is not assigned

SLOT x WAIT
Done

SLOT x WAIT

SLOT x END

The optional slot wait timer has expired

SLOT x DELAY
Done, Slot Not
Empty

SLOT x DELAY

Soft Start x

The initial delay timer has expired and slot x is assigned

Output x
Validated

Soft Start x

SLOT x END

The output voltage of all the rails assigned to slot x have raised to above theundervoltage detection level for that rail

Slot x Timeout

Soft Start x

FAULT PD

The output voltage of one or more of the rails assigned to slot x did not cross theundervoltage detection level for that rail within the slot timeout

Assigned Slots
Remaining

SLOT x END

SLOT x INIT

Not all rails that were assigned to the power up sequencer are yet enabled

All Assigned
Slots Done

SLOT x END

Allow INTB

All rails that were assigned to the power up sequencer are enabled, the remaining slots will be skipped.

Reset Delay
ExpiredAllow INTB

Allow RSTB &PG

The sequence done wait timer has expired

PU Done(PU−SEQ)

ACTIVEThe power up sequence has been executed and no faults are detected in thesequencing

Fault for
Validated Slots

Any PU−SEQ
State

FAULT PD

A fault has occurred on an already validated slot such as an unexpectedundervoltage detection

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NCV92310
A supply is considered disabled when its output voltage
has fallen below the disable threshold of that rail, “See
VOLTAGE MONITORING” section.
Each rail needs to power down within a timeout period. Incase of a timeout, this violation is logged but no further
specific action is taken. Upon the next power up, thesequence will not be started until all rails that are assigned
to the power up sequence are below the disable threshold.
The programming of the power down sequence is fully
independent from the power up sequence.
The power down sequence flow diagram and detailed
description of each state and transition are provided below.

Power Down Sequence
All supply rails can be assigned to the power down
sequencer. The sequence can be started through I2C. The
sequence is preprogrammed through OTP but can be
overwritten through I2C as well. Once a sequence is started
it cannot be interrupted.
A sequence is built up out of two portions: an initial delay
and the sequence with its slots. The initial delay allows for
inserting a delay between the request for a power down
sequence and the actual start. The sequence itself consists ofslots, and at each slot, one or more power rails can bedisabled. A slot is started after the rails of the previous slot
are successfully powered down. The INTB and RSTB signal
are made low after the initial delay timing.

POWER DOWN SEQUENCER (PD−SEQ, RESET PD−SEQ)
Slots Remaining

ACTIVEDisablePD
INIT

PD INIT Done

SLOTx
INIT

Slot not empty

SLOT x Output Disabled SLOT x
PD
EndSlot empty

All Slots DoneTime OutReset PD
Done

From Any Forced Reset
State

PD
WAIT

PD DoneOFF

INIT

PD WAIT Done

Figure 20. Power Down Sequence State Machine

Table 8. POWER UP SEQUENCER STATES
Group

State

Type

I2C

GlobalPD INIT

Transitional

R onlyUpon entry an optional initial delay timer is started

SLOT x INIT

Transitional

R onlyIt is verified if slot x has a rail assigned to it

PD WAIT

Transitional

R onlyUpon entry a timeslot wait timer is started

SLOT x PD

Transitional

R onlyFor the rails assigned to slot x, the active output discharge is enabled and theoutput voltage ramped down

SLOT x End

Transitional

R onlyIt is verified if there are still slots left to be treated. The slot number is increased
by +1

Description

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NCV92310
Table 9. POWER UP SEQUENCER TRANSITIONSTransition

From

To

Description

DisableACTIVE(PD−SEQ)PD INITA power down sequence is requested through I2C.

Forced Reset

Any State(PD−SEQ)PD INITA power down sequence is requested through I2C.

PD INIT DonePD INITSLOT x INIT

The initial delay timer has expired

Slot Empty

SLOT x INIT

PD WAIT

Slot x has no rail assigned to it

PD WAIT Done

PD WAITSLOT x End

The timeslot timer has expired

Slot Not Empty

SLOT x INIT

SLOT x PD

Slot x has one or more rails assigned to it

Output Disabled

SLOT x PD

SLOT x End

The output voltages of all rails assigned to slot x have crossed the disable
thresholdTime OutSLOT x PD

SLOT x End

One or more of the output voltages of the rails assigned to slot x did not crossthe disable threshold before the timeslot timer expired

Slots
Remaining

SLOT x End

SLOT x INIT

Not all slots have yet been treated (being assigned or not).

All Slots Done,
PD Done(PD−SEQ)
SLOT x End

OFF

All slots have been treated and the power down sequence has been executed

All Slots Done,
Reset PD Done

(PD−SEQ)
SLOT x End

INIT

All slots have been treated and the power down sequence has been executed

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NCV92310
INTERRUPTION
In order to inform the system about essential events aninterrupt pin INTB is provided. This avoids continuous
software pulling for status verification and reduces overalllatency for reporting events. There are different interrupt
behavior configurations possible.
• Dual edge interrupt: INTB is by default released (high),
and is pulled low upon the occurrence of a fault condition
or upon the resolution of it. The pin is released when theflag is cleared, even if a fault condition is still present.
• Single edge interrupt: INTB is by default released (high),
and is pulled low upon the occurrence of a fault condition.

The pin is released when the flag is cleared, even if a fault
condition is still present. For INTB released, it is notpulled low upon the resolution of a fault.
Nearly all events have three bits associated: a sense bit, aninterrupt flag bit and a mask bit. Below diagrams show thebasic functioning of these for all four interrupt
configurations. The arrow indicates the edge of the eventthat influences the other signals.

Dual Edge Interrupt Behavior

Sense X
Flag X

Write 1

Mask X
INTB

Unmasked
Released

Write 1

Write 1

MaskedLow

Power Up Sequence RunningPower Up Sequence Done
Single Edge Interrupt Behavior

Sense X
Flag X

Write 1

Mask X
INTB

Unmasked
Released

Write 1

MaskedLow

Released

Power Up Sequence RunningPower Up Sequence Done

Figure 21. Interrupt Behavior

Given the number of possible interrupts and in order toreduce the read−out time, a status register regroups all
interrupts of the same type to a single bit. Only unmasked
interrupts will be reflected through the status bits. As an
example, if one of the unmasked undervoltage interrupts isgenerated, the undervoltage status bit is also set. By reading
only the status register software can decide if the type ofinterrupt is of high importance or verify that the IC is the onethat pulled the interrupt line low.
In case of a single edge interrupt configuration, thebehavior of the sense bits is identical to that of the dual edge
configuration. The behavior of the interrupt flag bit and
INTB behavior is slightly different. Like for the dual edge
interrupt, when the sense bit changes from 0 to a 1, theassociated interrupt flag bit will be set and latched to a 1.
This interrupt flag bit can be cleared by writing a 1 which
will release the INTB pin, however, as long as thecorresponding sense bit remains high, the read back of theBelow, the behavior of the dual edge interrupt is
described, followed by a short description of the differenceswith the other configurations.
The sense bit reflects the real time status of a detector, likefor instance the undervoltage detection of LDO2. When thesense bit changes, the associated interrupt flag bit will be set
and latched to a 1. When an interrupt flag bit is 1, the pin
INTB is pulled low. An interrupt flag bit is cleared by writinga 1 to the interrupt bit location. If all unmasked interrupt flag
bits are cleared the INTB pin will be released. The INTB line
will only go high if no other device on the bus continuous topull it low.
Each interrupt flag bit has an associated mask bit. Whenthe mask bit is set 1 the interrupt flag bit value is of no
influence on the interrupt pin INTB. Masking interrupt bits
will make sure only the most essential interrupts will cause
INTB to be pulled low. Mask bit default settings depends on
OTP configuration.

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NCV92310
flag bit stays a 1. A cleared flag bit will automatically readback a 0 when the corresponding sense bit reverts to 0. Thisway, the INTB pin will only be forced low upon the detectionof the event reflected by the sense bit, but not when the event
disappears. The mask bit behavior is identical to the dualedge configuration.
After the startup of the device the INTB pin (push−pullconfiguration) is driven low and will be driven high at theend of the power –up sequence. If a flag event has occurred
during the power−up sequence, NCV92310 will keep the pin
low until the flag is cleared.
Due to defects, such as short to supply, the interrupt line
might stay high permanently. Therefore, I2C content should
be consulted after power up even if the interrupt line pin is
not going low in order to verify the integrity of the interrupt
line. A dedicated read/write bit is provided to force INTB
low if set to 1 or let INTB released when set to 0 in order toassist the system in verifying the overall signal integrity.

Table 11. INTERRUPT SOURCES (FAULT AND FLAG)
Interrupt Sources
FAULT
Fault_Time_Out
PUS_FAILPower up sequence Failure

UVT_BUCK1

DCDC1 Under Voltage Threshold

OVT_BUCK1

DCDC1 Over Voltage Threshold

Description

DCDC1_IPK pos

DCDC1 Converter Positive Inductor
Peak Current Protection

DCDC1_IPK neg

DCDC1 Converter Negative Inductor
Peak Current Protection

DCDC2_IPK pos

DCDC2 Converter Positive Inductor
Peak Current Protection

DCDC2_IPK neg

DCDC2 Converter Negative Inductor
Peak Current Protection

DCDC3_IPK pos

DCDC3 Converter Positive Inductor
Peak Current Protection

DCDC3_IPK neg

DCDC3 Converter Negative Inductor
Peak Current Protection

OVERTEMP (ERROR)
TSD

Thermal Shutdown

SELF TEST FAILURE (ERROR)
BIST
OTP_ERROR

BIST error
Error not corrected during OTP loading

ABNORMAL OPERATING CONDITIONS (ERROR)
SC_DCDC1

Short Circuit DCDC1

SC_DCDC2

Short Circuit DCDC2

SC_DCDC3

Short Circuit DCDC3

SC_LDO1

Short Circuit LDO1

SC_SW1_DCDC1

DCDC1 SW pin

SC_SW2_DCDC2

DCDC2 SW pin

SC_SW3_DCDC3

DCDC3 SW pin

I2C_REGERROR

Register map integrity error

UVLO

UVLO state

OVE

Input Over Voltage Error(input overvoltage flag disable)

FB1 open

LDO1_OCPLDO1 Output Over Current

I2C_FAILI2C communication lost

I2C_CRC_ERROR

I2C communication error

TSD_PWRNG

Thermal Pre−Warning

TSD_WRNG

Thermal Warning

OVF

Input Over Voltage Flag
(input overvoltage error disable)

PDS_FAILPower down sequence Failure

FAULT OR FLAG (DEPENDS ON OTP CONFIGURATION)

DCDC1 feedback pin open

UVT_BUCK2

DCDC2 Under Voltage Threshold

OVT_BUCK2

DCDC2 Over Voltage Threshold

UVT_BUCK3

DCDC3 Under Voltage Threshold

OVT_BUCK3

DCDC3 Over Voltage Threshold

UVT_LDO1

LDO1 Under Voltage Threshold

OVT_LDO1

LDO1 Over Voltage Threshold

FB2_OPENDCDC2 feedback pin open

FB3_OPENDCDC3 feedback pin open

CORE FAILURE (FATAL ERROR)
SC_VCORE

Short Circuit Internal Vcore Supply

Clock_Error

Internal Clock Error

Time out when in ACTIVE FLAG mode

FLAG

Table 10. INTERRUPT SOURCES (ERROR)
Interrupt Sources

Description

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NCV92310
FUNCTIONAL SAFETY
voltage comparator is used to detect if an established supply
rail does not go below the under voltage threshold VUVwhile the overvoltage comparator is used to detect if a
supply rail does not exceed the overvoltage threshold VOV.

NCV92310 embeds several safety mechanism, whichallow the part to be ASIL B compliant.
Voltage Monitoring

NCV92310 integrates four windows voltage monitoring(one per channel). During normal operation, the under
OV Max Threshold

VOVMAXOV Nom Threshold

VOVOV Min Threshold

VOVMINOV Accuracy

Load Transient

Vout nominal+0%

DC Accuracy + Load
Regulation

Load Transient
UV Min Threshold

VUVMINUV Nom Threshold

VOVUV Max Threshold

VUVMAXUV Accuracy

Figure 22.

A second bandgap is dedicated to the voltage monitoring
to reach high level of functional safety.
NCV92310 windows monitoring function embeds digital
filters which validate that the output of the comparators do
not change state during the programmed debounce time. For
each given channel, the debounce time TL_F for theundervoltage falling edge, the TL_R for the rising edge, as
well as the TH_R for the overvoltage rising edge and TH_F for
the falling edge are all independently programmable. The
debouncers are programmable in a ratiometric fashion. Thismeans that every next binary code will multiply thedebounce of the previous binary code by a factor of 2, seeparametric table for more details.
The digital filters can be bypassed for the undervoltage
falling edge TL_F and the overvoltage rising edge TH_R. In
that case the comparator output gets latched to avoid any
synchronization error with the clock digital circuitry.

Overall monitoring accuracy is the sum of multiple
accuracies:• DC Accuracy.
• Load and Line Regulation.
• OV or OV monitoring accuracy.
• Load transient.
DC Accuracy, Load Regulation, Line Regulation, OV
monitoring accuracy and UV monitoring accuracy are
specified in the parametric table (see Electrical
Characteristics section).
Load transient performance is dependent on both the
NCV92310 and application implementation. The NCV92310
internal regulators load transient performance depends on the
DI / Dt and COUT. It can be estimated with the following
equation:
DV +

2

p

DI
COUT derated

BW(eq. 3)

VUVMAX and VOVMAX are the maximum value of themonitoring threshold. VUV and VOV are I2C and OTP
programmable with the following nominal thresholds:

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NCV92310
Overvoltage
Threshold
Undervoltage
Threshold
Voltage
Monitoring
Input

DisableThreshold

DIS_SNS
Sequencer
Tagging

Power upÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ

ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ

ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ

Power GoodPower down

Debounce TH_R

OV_SNS

TL_F

UV_SNS

Debounce TL_R

DIS_SNS

Sequencer
Tagging

Debounce TL_R
Power up

Not debounced

UV_SNS

ÉÉ ÉÉ
ÉÉ
ÉÉ
ÉÉ ÉÉ
ÉÉ
ÉÉ
ÉÉ ÉÉ

TL_F

Debounce TL_R

With debounce

OV_SNSPower down

Figure 23. Illustration of Comparator Behavior
Self Test

Output voltages of DCDC1, DCDC2, DCDC3, LDO1
shall be at their respective VOUT targets with a tolerance
window defined by VH and VL.
Any violation of the respective VOUT windows greaterthan their respective TH_R or TL_F debounce time shall be
detected.
Once one of the output voltages cross a VOV or VUVthreshold, /INT goes low and in respect with the OTP/I2C
configuration DCDCs and LDO are turned off and /RST pingoes low.

• ECC

A One Time Programmable memory with Error CodeCorrection is embedded with 6 ECC bits and 26 OTP bits
per 32 OTP bits bank.
If one error is detected per bank, internal ECC correct thefailing bit and ACK_BIST bit is flagged.
If 2 errors are detected per bank, part goes in lock modeand ACK_BIST bit is flagged. To recover, ACK_BIST bit
has to be cleared and an unlock command has to be done:
set high the NLOCK bit or remove and re−apply PVIN.
• Windows voltage monitoring self test
At startup, an internal self test validate the windows
voltage monitoring functionality (BIST state in the
STATE MACHINE) :♦ Overvoltage and undervoltage detection.
♦ Overvoltage and undervoltage hysteresis
functionality.
♦ Leakage detection.
♦ Offset calibration.
If failed ACK_BIST is set high. One retry can be done if
BistCnt bit is set high (OTP and I2C configurable).
Otherwise part goes in lock mode.

VCORE Short Circuit Protection

Once a short circuit protection is detected in the VCORE
pin, the NCV92310 goes into the RESET state until the shortis removed. Short circuit current is limited at ≈ 60 mA.
Clock Error Protection

NCV92310 embeds a 2 MHz system clock in addition of
the 2.15 MHz DCDCs clock.
Once one regulator is turned on, availability and shift ofthe 2 MHz clock is monitored. In case of failure, NCV92310
is locked in RESET state. To recover, PVIN1 has to be
removed and re−applied again.

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NCV92310
I2C Register Map Integrity Checking

To protect against excessive short to high voltage, if 2
Ipeak neg are counted when in power fail (so when VOV istrigged) the NCV92310 goes in ERROR PD state with all therail turned off immediately.

Integrity of the configuration register in the register map
is monitored continuously. If one configuration bit changed
without the appropriate I2C command, NCV92310 goes in
LOCK state.

DCDC Switching Node Short Circuit Protection
NCV92310 embeds a short circuit on the SW pin of eachregulator to avoid any damage in the part due to excessive
current thru the internal output power stage. Once a shortcircuit is detected, part is turned OFF.
DCDC1 embeds a protection from SW1 to PGND1.
DCDC2 and DCDC3 embeds a protection from SW2/3 to
PVIN2/3 and PGND2/3.
Protection in case of internal short between PVIN1 andSW1. IC will flag it but it will not remove the short and avoid
any damage thru the inductor on FB1 andPVIN2/PViN3/VINLDO if these 3 pins are connected at theoutput of the DCDC1.

I 2C Communication Lost Protection
To be able to check that the I2C communication operates
properly and allow the system to do the appropriate action
once a fault is flagged thru the interrupt pin, system has towrite periodically in the I2CTMOUT register with a period
defined by the I2C_TIMEOUT bits in the
IC_CONFIGURATION_I2CTMOUT register.
If not done, NCV92310 will flag the system thru theinterrupt pin, which goes in ACTIVE Flag state and flag thededicated acknowledge bit.
DCDC Positive Current Limitation
The internal DCDCs protect the device from over current
with a fixed−value cycle−by−cycle current limitation. If
inductor current exceeds the current limit threshold, theHigh Side Switch will be turned off cycle−by−cycle. Due tothe propagation delay of the internal comparator, dynamic
current limitation can be higher than the peak current
threshold that is set internally.
The maximum peak current in the inductor can becomputed with:I PEAKPOS + I LIMP )ǒVIN * V OUTǓT DELAYL

DCDCs Feedback Pin Open Protection
DCDC1
FB1 pin is connected internally to a resistor bridge. In caseof open, internally the input of the error amplifier will be tied
to ground and undervoltage detection will be triggued and
NCV92310 turned off.
DCDC2 and DCDC3
FB2 and FB3 pins, in addition of the connection to theerror amplifier, are tied to Vin internally. Output voltage will
decrease and overvoltage detection will be triggued to avoid
any damage to the IC which are supplied by the NCV92310.

(eq. 4)

With TDELAY DCDC1 = 30 ns (typ) and
TDELAY DCDC2/DCDC3 = 40 ns (typ).
The maximum output current can be computed with:I MAX + I PEAK )2

LDO Over Current Protection and Output Short CircuitProtection
The low drop out regulator (LDO) on the IC is based onan embedded PMOS and requires no external stability
components or feedback networks.
The output must be bypassed with at least a 2.2 mF ceramic
capacitor.
Internal LDO includes an over current protection circuit(ILIMITLDO). Once crossed, the dedicated acknowledge bit
is set high to advise the system that the LDO is overloaded.
After crossing the ILIMITLDO, if the load continue toincrease internal LDO will start to deregulate. A short circuit
protection is embedded with ISCLDO set 15 mA higher thanILIMITLDO. Once in short circuit, NCV92310 goes in
ERROR PD state and all the regulators are turned off
immediately.

ǒV IN * V OUTǓ

V OUT

V IN

f SW

L

(eq. 5)

Where VIN is input supply voltage, VOUT is output
voltage, L is inductance of the filter inductor, and FSW is
2.15 MHz normal switching frequency.
DCDC Negative Current Protection
In addition, to protect the Low Side switch, the negative
current protection (Ipeakn) limits potential excessive
current from output (for example, when fault condition
causes the output voltage to be higher than the nominal
output voltage).
The maximum negative peak current in the inductor canbe computed with:I PEAKNEG + * I LIMN *

V OUT
L

T DELAY

With TDELAY DCDC1 = 50
TDELAY DCDC2/DCDC3 = 20 ns (typ).

Under Voltage Lockout
The input voltage PVIN1 must reach or exceed the UVLO
rising threshold before the NCV92310 enables the converter
output to begin the power up sequence.
When PVIN1 cross the UVLO falling threshold, no power
down sequence is expected. All the supplies are disabled andoutput discharged simultaneously.
UVLO Thresholds and hysteresis are I2C and OTP
programmable to fit multiple camera applications use cases.

(eq. 6)

ns

(typ)

and

DCDC Short Circuit Protection
To protect against excessive load or short circuit toground, if 2 Ipeak pos are counted when in power fail (sowhen VUV is trigged) the NCV92310 goes in ERROR PD
state with all the rail turned off immediately.

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28

NCV92310
To prevent the camera application, and in particular theimage sensor, from powering up under too high ambient
temperature conditions, the power up sequence isconditioned by the die temperature of the IC. Before
engaging a power up sequence, the on−chip dissipation isclose to zero, which makes that the die temperature of the IC
will be a good representation of the ambient temperature.
(Thermal gating threshold, can be deactivated by I2C /OTP).

Over Voltage Detection
To protect from input voltage higher than 18V,
NCV92310 includes an internal comparator in the PVIN1
pin. Depending on the OTP configuration:• NCV92310 will flag the system thru the /INT pin if a
supply voltage higher than 18.3 V (typical) is detected on
PVIN1 input. System has to safely turn off the load of theNCV92310 before removing the power supply if the
OverVoltage is still present. Otherwise the system has toclear the fault in the dedicated acknowledge bit.
• NCV92310 will turn off all the regulators, pull low INTB
and RSTB pins and goes in lock state.

Fault Time Out
Once in Active Flag state after an internal FLAG
highlighted to the system thru the /INT pin, system has toclear the dedicated acknowledge bit within a delay set thru
the FAULT_TIMEOUT[0:1] bits. If not done, NCV92310
goes in FAULT PD state and can restart or goes in lock mode
dependingonthe
AutoRearmsetting.
ACK_FAULT_TIMEOUT bit is set high to highlight thefault.

Thermal Protection
NCV92310 has a thermal shutdown protection to protect
the device from overheating. After the thermal protection istriggered, All the supplies are disabled and output
discharged simultaneously.
NCV92310 includes a thermal warning and thermal
pre−warning thresholds to advise the system that the dietemperature has become too high. The dedicated
ACK_THERMAL_PRWNG, ACK_THERMAL_WNG bits
and /INT pin are flagged depending on the
MSK_THERMAL_PRWNG and MSK_THERMAL_WNG
setting. Thermal Warning Threshold is the last flag before
going in TSD and shutdown the part.
Thermal Pre−Warning threshold is I2C and OTP
programmable.
If TSD_REARM bit is high, NCV92310 recovers
automatically and goes to the INIT state to reload the OTP
and restart with the default settings.

Power−up Sequence FailDuring the PUS, if a rail does not reach its default value
by triggering its undervoltage rising monitoring thresholdonce the SLOT time out is done, NCV92310 goes in FAULT
PD state and flag the ACK_PUS bit.
Power−down Sequence FailDuring the PDS, if a rail does not reach the VDISABLE
threshold once the SLOT time out is done, NCV92310
continue the power down sequence but flag the ACK_PUS
bit and /INT pin goes low.

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29

NCV92310
I2C COMPATIBLE INTERFACE
NCV92310 can support a subset of the I2C protocol as
detailed below (Read, Write, Write then read sequences).

is transmitted as the last byte of the transfer. Below, theprotocol is shown in detail for the different use cases, withand without CRC.
When using CRC, for a write access, the PEC is calculated
over the 3 bytes included in the entire transfer from Start to
Stop. This includes the I2C address and R/W bit, the register
address and the data, but excludes the (Repeated)Start/Stopand the ACK/NACK signaling. The PEC is appended by themaster as the second data byte at the end of the transfer. If
the PEC received by the slave does not correspond the PEC
byte calculated by the slave, the data written will be ignored
and the transaction will be NACKed by the slave. Since also
the NACK could get corrupted an interrupt is generated aswell.
For a read access the PEC is calculated over the 4 bytes
included in the entire transfer from Start to Stop. This
includes the I2C address and R/W bit, the register address,
again the I2C address and R/W bit and the data, but excludes
the (Repeated) Start/Stop and the ACK/NACK signaling.
The PEC is appended by the slave as the second data byte at
the end of the transfer.
For clarification, the bytes over which the PEC iscalculated are highlighted in below diagram.

I2C Communication Description

The device is widely programmable through an I2C
compatible interface available at SCL and SDA. The I2C
interface has no dedicated I/O supply and the logic low andhigh levels are therefore fixed and not adjusted to the actual
drive levels. Events are signaled on a side signal at INTB.
The address of the device on the I2C bus is 7−bit long of
which the 3 bits can be set with OTP.
For robust I2C transfers an 8−bit CRC (cyclic redundancy
check) mechanism is implemented with fixed CRC code
X8+X2+X+1. This is the same code as used in SMBus
communication, for more information refer to the System
Management Bus Specification version 3.1, sections 6.4 and
6.5 (specifically, refer to section 6.4.1.3 for details on slave
implementation). The CRC−coding can be enabled or
disabled based on OTP setting and I2C programming.
With CRC−coding disabled, single byte write and read aswell as continuous write and read are supported. With
CRC−coding enabled, only single byte write and read aresupported. In the latter case an 8−bit PEC (packet error code)www.onsemi.com
30

NCV92310
I2C Compatible Interface − Protocol without CRC
Single Write
Register N

S

Slave Address

W

A

Register Address N

A

Data Register N

A

Multiple Single Register
Register N, K

S

Slave Address

W

A

Register Address N

A

Data Register NA

Sr
Slave Address
PS
Continuous Write
Registers N to N+mWrite followed by Read
Register N

WARegister Address K

A

Data Register K

P

A

P

Not supported

S

Slave Address

W

A

Register Address N

Sr
Slave Address
PS

W

A

A

Register Address N

Data Register NA

Sr Slave Address

R

A

Data Register N

NA

Slave Address

W

A

Register Address N

A

Sr
Slave Address
PS

R

A

Data Register N

NA

Multiple Single Read
Register N, K

S

Slave Address

W

A

Register Address N

A

Sr
Slave Address
PS

R

A

Data Register NNA

Sr
Slave Address
PS

R

A

R

A

Data Register N

Continuous Read
Registers N to N+mS

Multiple Single Write
Register N, K

0 = WriteR

1 = ReadA

ACKnowledge

P

Sr
Slave Address
PS

W

A

Slave Address

W

A

Register Address N

Sr
Slave Address
PS

W

A

Register Address N

A

Sr
Slave Address
PS

R

A

Data Register NNA

Sr
Slave Address
PS

W

A

Register Address N

A

Sr
Slave Address
PS

R

A

Data Register N

NA

Slave Address

A

Register Address N

A

Data Register N

W

Register Address K

A

A

A

Sr
Slave AddressPS

Sr
Slave Address
PS

R

Data Register K

NA

P

NA

A

S

Slave Address

W

A

Register Address N

A

Data Register N

A

PEC

A

P

S

Slave Address

W

A

Register Address N

A

Data Register N

A

PEC

A

P

S

Slave Address

W

A

Register Address K

A

Data Register K

A

PEC

A

P

Continuous Write
Registers N to N+mPark (Stop)P

P

Data Register N+1

A

Data Register N+m

I2C Compatible Interface − Protocol with CRC
Single Write
Register N

P
W

A

S

S

Start
Repeated Start
or Park − Start

NA Not ACKnowledge

Single Read
Register N

Multiple Read
Register N(Polling)

S
Sr
PS

Not supported

NA

P

S

Start

Sr

Repeated Sta rt

P

Park (Stop)W

0 = WriteR

1 = ReadA

ACKnowledge

NA Not ACKnowledge
Bytes used for PEC

Write followed by Read
Register N

S

Slave Address

W

A

Register Address N

A

Data Register N

PEC

A

A

P

S

Slave Address

W

A

Register Address N

A

Sr Slave Address

R

A

Data Register N

A

PEC

NA

P

Single Read
Register N

S

Slave Address

W

A

Register Address N

A

Sr

Slave Address

R

A

Data Register N

A

PEC

NA

P

Multiple Single Read
Register N, K

S

Slave Address

W

A

Register Address N

A

Sr

Slave Address

R

A

Data Register N

A

PEC

NA

P

S

Slave Address

W

A

Register Address K

A

Sr

Slave Address

R

A

Data Register K

A

PEC

NA

P

S

Slave Address

W

A

Register Address N

A

Sr

Slave Address

R

A

Data Register N

A

PEC

NA

P

S

Slave Address

W

A

Register Address N

A

Sr

Slave Address

R

A

Data Register N

A

PEC

NA

P

S

Slave Address

W

A

Register Address N

A

Sr

Slave Address

R

A

Data Register N+m

A

PEC

NA

P

S

Slave Address

W

A

Register Address N

A

Sr

Slave Address

R

A

Data Register N

A

PEC

NA

P

S

Slave AddressW

A Register Address N+1

A

Sr

Slave Address

R

A

Data Register N+1

A

PEC

NA

P

S

Slave AddressW

A Register Address N+mA

Sr

Slave Address

R

A

Data Register N+m

A

PEC

NA

P

Multiple Read
Registers N(Polling)

Multiple Read
Registers N to N+mContinuous Read
Registers N to N+m

Not supported

Byte

PEC

Byte

PEC

Byte

PEC

Rev A

Figure 24. I2C Bus Protocol
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31

NCV92310
I2C Slave Address

The NCV92310 has 8 available I2C addresses selectableby factory settings (ADD0 to ADD7). Different address
settings can be generated upon request to onsemi.
Table 12. I2C SLAVE ADDRESSI2C Slave
Address

Hex

A7

A6

A5

A4

A3

A2

A1

A0

ADD0

W 0x20R 0x21

0

0

1

0

0

0

0

R/W

ADD1
(default)

W 0x28R 0x29

0

0

1

0

1

0

0

R/W

Add

−

Add
ADD2

W 0x30R 0x31

−
0

0

1

1

0

0

0

R/W

0

0

1

1

1

0

0

R/W

1

1

0

0

0

0

0

R/W

1

1

0

0

1

0

0

R/W

Add
ADD3

W 0x38R 0x39ADD4W 0xC0R 0xC1ADD5

W 0xC8R 0xC9

−

Add

−

Add

−

Add
ADD6

W 0xD0R 0xD1

−
1

1

0

1

0

0

0

Add
ADD7

W 0xD8R 0xD9

R/W
−

1

1

0

1

Add

1

0

0

R/W
−

I2C UNLOCK Write Protected Register

By
default,alltheregisters
afterthe
UNLOCK_WRITE_PROTECT_REG register are locked.
Only read access is allowed.
To write in a register, user has to send a write commandwith 0x69 in the unlock register, and then send a write
command with the register address to write. Once the write
command has been sent to the unlocked register with thewrite data, this register is locked again.

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32

NCV92310
Table 13. REGMAP
Addr

Register Name

Register
Type

Def.

0h

PID

R

00111010b (3Ah)

Product Id

1h

RID

R

00000000b (0h)

Revision Id

2h

FID

R

00000000b (0h)Features Id

3h

INT_STATUS

R

00000000b (0h)Interrupt Status Register

4h

INTERRUPT_FLAG_IC

W1CSingle

00000000b (0h)Interrupt Flag IC Acknowledge Register

5h

INTERRUPT_FLAG_ERR1

W1CSingle

00000000b (0h)Interrupt Flag Error Acknowledge Register 1

6h

INTERRUPT_FLAG_ERR2

W1CSingle

00000000b (0h)Interrupt Flag Error Acknowledge Register 2

7h

INTERRUPT_FLAG_OV

W1CSingle

00000000b (0h)Interrupt Flag Over Voltage Threshold Monitoring
Acknowledge Register

8h

INTERRUPT_FLAG_UVW1CSingle

00000000b (0h)Interrupt Flag Under Voltage Threshold Monitoring
Acknowledge Register

9h

INTERRUPT_FLAG_OC

W1CSingle

00000000b (0h)Interrupt Over Current Acknowledge Register

0Ah

INTERRUPT_SENSE_IC

R

00000000b (0h)Interrupt Flag IC Sense Register

0Bh

INTERRUPT_SENSE_ERR

R

00000000b (0h)Interrupt Flag Error System Sense Register

0Ch

INTERRUPT_SENSE_OV

R

00000000b (0h)Interrupt Flag Over Voltage Threshold Monitoring Sense
Register

0Dh

INTERRUPT_SENSE_UV

R

00000000b (0h)Interrupt Flag Under Voltage Threshold Monitoring
Sense Register

0Eh

IC_STATUS_DISCHARGED

R

00000000b (0h)IC output discharged status register

0Fh

IC_STATUS_SAFE_STATE

R

00000000b (0h)IC Regulator safe state status register10h

IC_STATUS_MISCELLANEOUS_1

R

00000000b (0h)IC status error counter register11h

IC_STATUS_MISCELLANEOUS_2

R

00000000b (0h)IC status state machine counter register

12h

I2CTMOUT

RW

00000000b (0h)

I2C Timeout Write register

13h

UNLOCK_WRITE_PROTECT_REG

RW

00000000b (0h)Unlock Register14h

IC_CONFIGURATION_I2CTMOUT

CRC

00000000b (0h)I2C timeout setting register15h

IC_CONFIGURATION_1

CRC00100101b (25h)

IC Configurations Register 1

16h

IC_CONFIGURATION_2

CRC00000000b (0h)

IC Configurations Register 2

17h

IC_CONFIGURATION_3

CRC

00001100b (Ch)IC Configurations Register 3

18h

IC_CONFIGURATION_4

CRC

00000000b (0h)

IC Configurations Register 4

19h

INTERRUPT_MASK_IC

CRC

00000000b (0h)Interrupt Flag IC Mask Register

1Ah

INTERRUPT_MASK_OV

CRC

00000000b (0h)Interrupt mask register Overvoltage monitoring
threshold

1Bh

INTERRUPT_MASK_UV

CRC

00000000b (0h)Interrupt mask register Undervoltage monitoring
threshold

1Ch

INTERRUPT_MASK_OC

CRC

00101010b (2Ah)

Interrupt mask register Overcurrent protection

1Dh

OUTPUT_VOLTAGE_DCDC1

CRC00000101b (5h)

DCDC1 Output Voltage Programmation Register

1Eh

CONFIGURATION_DCDC1

CRC00001101b (Dh)

DCDC1 Configuration register

1Fh

OUTPUT_VOLTAGE_DCDC2

CRC00011000b (18h)

DCDC2 Output Voltage Programmation Register

20h

CONFIGURATION_DCDC2

CRC00001101b (Dh)

DCDC2 Configuration register

21h

OUTPUT_VOLTAGE_DCDC3

CRC00110000b (30h)

DCDC3 Output Voltage Programmation Register

22h

CONFIGURATION_DCDC3

CRC00001101b (Dh)

DCDC3 Configuration register

23h

OUTPUT_VOLTAGE_LDO1

CRC00000010b (2h)

LDO1 Output Voltage Programmation Register

24h

CONFIGURATION_LDO1

CRC

00001101b (Dh)LDO1 Configuration registerwww.onsemi.com
33

Function

NCV92310
Table 13. REGMAP (continued)
Addr

Register Name

Register
Type

Def.

25h

MONITORING_UV_DCDC1

CRC00100100b (24h)Monitoring Undervoltage DCDC1 settings

26h

MONITORING_OV_DCDC1

CRC

01010000b (50h)Monitoring Overvoltage DCDC1 settings

27h

MONITORING_UV_DCDC2

CRC00100100b (24h)Monitoring Undervoltage DCDC2 settings

28h

MONITORING_OV_DCDC2

CRC

01010000b (50h)Monitoring Overvoltage DCDC2 settings

29h

MONITORING_UV_DCDC3

CRC00100100b (24h)Monitoring Undervoltage DCDC3 settings

2Ah

MONITORING_OV_DCDC3

CRC

01010000b (50h)Monitoring Overvoltage DCDC3 settings

2Bh

MONITORING_UV_LDO1

CRC00100100b (24h)Monitoring Undervoltage LDO1 settings

2Ch

MONITORING_OV_LDO1

CRC

01010000b (50h)Monitoring Overvoltage LDO1 settings

2Dh

SEQUENCER_ASSIGNMENT_DCDC1

CRC00000000b (0h)Sequencer Assignment DCDC1 register

2Eh

SEQUENCER_ASSIGNMENT_DCDC2

CRC00010001b (11h)Sequencer Assignment DCDC2 register

30h

SEQUENCER_ASSIGNMENT_DCDC3

CRC00100010b (22h)Sequencer Assignment DCDC3 register

31h

SEQUENCER_ASSIGNMENT_LDO1

CRC

00110011b (33h)Sequencer Assignment LDO1 register

32h

SEQUENCER_CONFIGURATION_1

CRC

00001101b (Dh)Sequencer configuration register 1

33h

SEQUENCER_CONFIGURATION_2

CRC

01101011b (6Bh)

Sequencer configuration register 2

Function

Table 14. PRODUCT ID
Register Name

PID

Address

00

Type

R

Default

00111010b (3Ah)

Trigger
Bit

Name

Description

7

PID

Product Id

6
5
4
3
2
1
0

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34

NCV92310
Table 15. REVISION ID
Register Name

RID

Address

01

Type

R

Default

00000000b (0h)Trigger
Bit

Name

Description

7

RID

Revision Id

6
5
4
3
2
1
0

Table 16. FEATURES ID
Register Name

FID

Address

02

Type

R

Default

00000000b (0h)Trigger
Bit

Name

Description

7

FID

Features Id

6
5
4
3
2
1
0

Table 17. INTERRUPT STATUS REGISTER
Register Name

INT_STATUS

Address

03

Type

R

Default

00000000b (0h)Trigger
Bit

Name

Description

7

empty

6

empty

5

ST_OC

Status bit Over current Fault
Or between FLAG_OC bits (unmasked bits)

4

ST_DIS

Status bit disable threshold not crossed during a PDS

3

ST_MUV

Status bit monitoring undervoltage
Or between FLAG_OV bits (unmasked bits)2

ST_MOV

Status bit monitoring overvoltage
Or between FLAG_OV bits (unmasked bits)

1

ST_ERR

Status bit Interrupt flar error
Or between FLAG_ERR bits (unmasked bits)

0

ST_IC

Status bit flag IC
Or between FLAG_IC bits (unmasked bits)

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NCV92310
Table 18. INTERRUPT FLAG IC ACKNOWLEDGE REGISTER
Register Name

INTERRUPT_FLAG_IC

Address

04

Type

W1CSingle

Default

00000000b (0h)Trigger
Bit

Name

7

ACK_PDSPower down sequence Fault Acknowledge
0: Cleared
1: Event Detected

Description

6

ACK_PUSPower up sequence Fault Acknowledge
0: Cleared
1: Event Detected

5

ACK_TSD_WRNG

Thermal Warning Fault Acknowledge
0: Cleared
1: Event Detected

4

ACK_TSD_PTWRNG

Thermal Pre−Warning Fault Acknowledge
0: Cleared
1: Event Detected

3

ACK_I2CFAIL

Watchdog Fault Acknowledge
0: Cleared
1: Event Detected

2

ACK_FAULT_TIMEOUT

Fault timeout Acknowledge
0: Cleared
1: Event Detected

1

ACK_I2CERROR

0

ACK_OVFI2C interface CRC Fault Acknowledge
0: Cleared
1: Event Detected
Input Over Voltage Detection Flag Acknowledge (depends on OTP configuration)
0: Cleared
1: Event Detected

Table 19. INTERRUPT FLAG ERROR ACKNOWLEDGE REGISTER 1
Register Name

INTERRUPT_FLAG_ERR1

Address

05

Type

W1CSingle

Default

00000000b (0h)Trigger
Bit

Name

Description

7

ACK_FRCRST

Force reset power down sequence
0: cleared
1: Force Reset done6

ACK_UVLO

Input Under Voltage Threshold Fault Acknowledge
0: Cleared
1: Event Detected

5

ACK_TSD

Thermal Shutdown Fault Acknowledge
0: Cleared
1: Event Detected

4

empty

3

ACK_OVE

2

ACK_AUTOREARMCNT

Auto Rearm Error Acknowledge
0: Cleared
1: Event Detected

1

ACK_I2CREGERROR

Write Register CRC Fault Acknowledge
0: Cleared
1: Event Detected

0

ACK_BIST

Input Over Voltage Detection Error Acknowledge (depends on OTP configuration)
0: Cleared
1: Event Detected

BIST Fault Acknowledge (BIST or OTP ECC Error)
0: Cleared
1: Event Detected

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36

NCV92310
Table 20. INTERRUPT FLAG ERROR ACKNOWLEDGE REGISTER 2
Register Name

INTERRUPT_FLAG_ERR2

Address

06

Type

W1CSingle

Default

00000000b (0h)Trigger
Bit

Name

Description

7

empty

6

ACK_SC_SW_DCDC3

DCDC3 Short Circuit Protection
0: Cleared
1: Event Detected

5

ACK_SC_SW_DCDC2

DCDC2 Short Circuit Protection
0: Cleared
1: Event Detected

4

ACK_SC_SW_DCDC1

DCDC1 Short Circuit Protection
0: Cleared
1: Event Detected

3

ACK_SC_LDO1

LDO1 Short Circuit Protection
0: Cleared
1: Event Detected

2

ACK_SC_VOUT_DCDC3

DCDC3 Short Circuit Protection
0: Cleared
1: Event Detected

1

ACK_SC_VOUT_DCDC2

DCDC2 Short Circuit Protection
0: Cleared
1: Event Detected

0

ACK_SC_VOUT_DCDC1

DCDC1 Short Circuit Protection
0: Cleared
1: Event Detected

Table 21. INTERRUPT FLAG OVER VOLTAGE THRESHOLD MONITORING ACKNOWLEDGE REGISTER
Register Name

INTERRUPT_FLAG_OV

Address

07

Type

W1CSingle

Default

00000000b (0h)Trigger
Bit

Name

7

empty

6

empty

5

empty

Description

4

empty

3

ACK_OV_LDO1

LDO1 Monitoring Over Voltage Threshold Acknowledge
0: Cleared
1: Event Detected

2

ACK_OV_DCDC3

DCDC3 Monitoring Over Voltage Threshold Acknowledge
0: Cleared
1: Event Detected

1

ACK_OV_DCDC2

DCDC2 Monitoring Over Voltage Threshold Acknowledge
0: Cleared
1: Event Detected

0

ACK_OV_DCDC1

DCDC1 Monitoring Over Voltage Threshold Acknowledge
0: Cleared
1: Event Detected

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37

NCV92310
Table 22. INTERRUPT FLAG UNDER VOLTAGE THRESHOLD MONITORING ACKNOWLEDGE REGISTER
Register Name

INTERRUPT_FLAG_UV

Address

08

Type

W1CSingle

Default

00000000b (0h)Trigger
Bit

Name

Description

7

empty

6

empty

5

empty

4

empty

3

ACK_UV_LDO1

LDO1 Monitoring Under Voltage Threshold Acknowledge
0: Cleared
1: Event Detected

2

ACK_UV_DCDC3

DCDC3 Monitoring Under Voltage Threshold Acknowledge
0: Cleared
1: Event Detected

1

ACK_UV_DCDC2

DCDC2 Monitoring Under Voltage Threshold Acknowledge
0: Cleared
1: Event Detected

0

ACK_UV_DCDC1

DCDC1 Monitoring Under Voltage Threshold Acknowledge
0: Cleared
1: Event Detected

Table 23. INTERRUPT OVER CURRENT ACKNOWLEDGE REGISTER
Register Name

INTERRUPT_FLAG_OC

Address

09

Type

W1CSingle

Default

00000000b (0h)Trigger
Bit

Name

7

empty

Description

6

ACK_LDO1_OCP

5

ACK_IPEAK_NEG_DCDC3

DCDC3 Negative current limitation Acknowledge
0: Cleared
1: Event Detected

4

ACK_IPEAK_POS_DCDC3

DCDC3 Inductor IPEAK current limitation Acknowledge
0: Cleared
1: Event Detected

3

ACK_IPEAK_NEG_DCDC2

DCDC2 Negative current limitation Acknowledge
0: Cleared
1: Event Detected

2

ACK_IPEAK_POS_DCDC2

DCDC2 Inductor IPEAK current limitation Acknowledge
0: Cleared
1: Event Detected

1

ACK_IPEAK_NEG_DCDC1

DCDC1 Negative current limitation Acknowledge
0: Cleared
1: Event Detected

0

ACK_IPEAK_POS_DCDC1

DCDC1 Inductor IPEAK current limitation Acknowledge
0: Cleared
1: Event Detected

LDO1 Over Current Protection Acknowledge
0: Cleared
1: Event Detected

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NCV92310
Table 24. INTERRUPT FLAG IC SENSE REGISTER
Register Name

INTERRUPT_SENSE_IC

Address

0A

Type

R

Default

00000000b (0h)Trigger
Bit

Name

Description

7

empty

6

empty

5

SEN_TSD_WRNG

TSD Warning Sense
0: Thermal warning below threshold
1: Thermal warning above threshold

4

SEN_TSD_PRWRNG

TSD Pre−Warning Sense
0: Thermal Pre−warning below threshold
1: Thermal Pre−warning above threshold

3

empty

2

empty

1

empty

0

SEN_OVFOVF Sense
0: PVIN1 below threshold
1: PVIN1 above threshold

Table 25. INTERRUPT FLAG ERROR SYSTEM SENSE REGISTER
Register Name

INTERRUPT_SENSE_ERR

Address

0B

Type

R

Default

00000000b (0h)Trigger
Bit

Name

Description

7

empty

6

SEN_UVLOUVLO Sense
0: PVIN1 above threshold
1: PVIN1 below threshold

5

SEN_TSDTSD Sense
0: Thermal Shutdown below threshold
1: Thermal shutdown above threshold

4

empty

3

empty

2

empty

1

empty

0

empty

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NCV92310
Table 26. INTERRUPT FLAG OVER VOLTAGE THRESHOLD MONITORING SENSE REGISTER
Register Name

INTERRUPT_SENSE_OV

Address

0C

Type

R

Default

00000000b (0h)Trigger
Bit

Name

Description

7

empty

6

empty

5

empty

4

empty

3

SEN_OV_LDO1

LDO1 Monitoring Over Voltage Threshold Sense
0: LDO1 Output Voltage within nominal range
1: LDO1 Output Voltage Above Target

2

SEN_OV_DCDC3

DCDC3 Monitoring Over Voltage Threshold Sense
0: DCDC3 Output Voltage within nominal range
1: DCDC3 Output Voltage Above Target

1

SEN_OV_DCDC2

DCDC2 Monitoring Over Voltage Threshold Sense
0: DCDC2 Output Voltage within nominal range
1: DCDC2 Output Voltage Above Target

0

SEN_OV_DCDC1

DCDC1 Monitoring Over Voltage Threshold Sense
0: DCDC1 Output Voltage within nominal range
1: DCDC1 Output Voltage Above Target

Table 27. INTERRUPT FLAG UNDER VOLTAGE THRESHOLD MONITORING SENSE REGISTER
Register Name

INTERRUPT_SENSE_UV

Address

0D

Type

R

Default

00000000b (0h)Trigger
Bit

Name

7

empty

Description

6

empty

5

empty

4

empty

3

SEN_UV_LDO1

LDO1 Monitoring Over Voltage Threshold Sense
0: LDO1 Output Voltage within nominal range
1: LDO1 Output Voltage Above Target

2

SEN_UV_DCDC3

DCDC3 Monitoring Over Voltage Threshold Sense
0: DCDC3 Output Voltage within nominal range
1: DCDC3 Output Voltage Above Target

1

SEN_UV_DCDC2

DCDC2 Monitoring Over Voltage Threshold Sense
0: DCDC2 Output Voltage within nominal range
1: DCDC2 Output Voltage Above Target

0

SEN_UV_DCDC1

DCDC1 Monitoring Over Voltage Threshold Sense
0: DCDC1 Output Voltage within nominal range
1: DCDC1 Output Voltage Above Target

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NCV92310
Table 28. IC OUTPUT DISCHARGED STATUS REGISTER
Register Name

IC_STATUS_DISCHARGED

Address

0E

Type

R

Default

00000000b (0h)Trigger
Bit

Name

Description

7

empty

6

empty

5

empty

4

OVLO_SAFEOVLO SafeState status
0: DCDC1 windows monitoring used a interrupt
1: DCDC1 windows monitoring used as Error (safetstate)

3

S_LDO1_DIS

Status bit for LDO1 discharge during previous PD SEQ

2

S_DCDC3_DIS

Status bit for DCDC3 discharge during previous PD SEQ

1

S_DCDC2_DIS

Status bit for DCDC2 discharge during previous PD SEQ

0

S_DCDC1_DIS

Status bit for DCDC1 discharge during previous PD SEQ

Table 29. IC REGULATOR SAFE STATE STATUS REGISTER
Register Name

IC_STATUS_SAFE_STATE

Address

0F

Type

R

Default

00000000b (0h)Trigger
Bit

Name

Description

7

LDO1_OV_SAFELDO1 SafeState status
0: LDO1 windows monitoring used a interrupt
1: LDO1 windows monitoring used as Error (safetstate)

6

DCDC3_OV_SAFEDCDC3 SafeState status
0: DCDC3 windows monitoring used a interrupt
1: DCDC3 windows monitoring used as Error (safetstate)

5

DCDC2_OV_SAFEDCDC2 SafeState status
0: DCDC2 windows monitoring used a interrupt
1: DCDC2 windows monitoring used as Error (safetstate)

4

DCDC1_OV_SAFEDCDC1 SafeState status
0: DCDC1 windows monitoring used a interrupt
1: DCDC1 windows monitoring used as Error (safetstate)

3

LDO1_UV_SAFELDO1 SafeState status
0: LDO1 windows monitoring used a interrupt
1: LDO1 windows monitoring used as Error (safetstate)

2

DCDC3_UV_SAFEDCDC3 SafeState status
0: DCDC3 windows monitoring used a interrupt
1: DCDC3 windows monitoring used as Error (safetstate)

1

DCDC2_UV_SAFEDCDC2 SafeState status
0: DCDC2 windows monitoring used a interrupt
1: DCDC2 windows monitoring used as Error (safetstate)

0

DCDC1_UV_SAFEDCDC1 SafeState status
0: DCDC1 windows monitoring used a interrupt
1: DCDC1 windows monitoring used as Error (safetstate)www.onsemi.com
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NCV92310
Table 30. IC STATUS ERROR COUNTER REGISTER
Register Name

IC_STATUS_MISCELLANEOUS_1

Address

10

Type

R

Default

00000000b (0h)Trigger
Bit

Name

7

STAT_BIST

6

AutoRearmCnt_STAT

5

Description
Bist done
Auto Rearm Counter status.
Counter resetted when AutoRearmCnt_RST bit is set to 1

4
3
2
1
0

Table 31. IC STATUS STATE MACHINE COUNTER REGISTER
Register Name

IC_STATUS_MISCELLANEOUS_2

Address

11

Type

R

Default

00000000b (0h)Trigger
Bit

Name

7

STATPU

6
5

STATSLOTPU

432

STATMCH

1
0

Description
00: PUS ok
01: Rail required discharged
10: Restart required due to UVLO for DCDC1 in SLOT0
11: Rail required discharged and Restart required due to UVLO for DCDC1 in SLOT0
00: No slot timeout fault 100: Slot timeout SLOT 0
101: Slot timeout SLOT 1
110: Slot timeout SLOT 2
111: Slot timeout SLOT 3(updated at the end of the PUS)State Machine status 000: OFF
001: PU−SEQ
010: ACTIVE − ACTIVE FLAG
011: PD−SEQ
100: FAULT PD
101: ERROR PD
110: RESET−SEQ
111: LOCK

Table 32. I2C TIMEOUT WRITE REGISTER
Register Name

I2CTMOUT

Address

12

Type

RW

Default

00000000b (0h)Trigger
Bit

Name

7

empty

6

empty

5

empty

4

empty

3

empty

2

empty

1

empty

0

I2C_TIMEOUT_WR

Description

I2C access to this register has to be done continuously with a max period defined by the I2CTime Out delay.
If not done, the dedicated ACK bit is flagged and /INT pin is pulled low.

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NCV92310
Table 33. UNLOCK REGISTER
Register NameUNLOCK_WRITE_PROTECT_REG

Address

13

Type

RW

Default

00000000b (0h)Trigger
Bit

Name

7

UNLOCK

6

Description
8 bits to unlock configuration registers.
By default, configuration registers are locked to avoid unexpected change thru I2C

5
4
3
2
1
0

Table 34. I2C TIMEOUT SETTING REGISTER
Register Name

IC_CONFIGURATION_I2CTMOUT

Address

14

Type

CRC

Default

00000000b (0h)Trigger
Bit

Name

7

empty

6

empty

5

empty

4

empty

3

empty

2

empty

1

I2C_TIMEOUT

0

Description

2 bits for I2C communication timeout
00: disable
01: 16 ms
10: 128 ms
11: 1024 ms

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NCV92310
Table 35. IC CONFIGURATIONS REGISTER 1
Register Name

IC_CONFIGURATION_1

Address

15

Type

CRC

Default

00100101b (25h)

Trigger
Bit

Name

7

UVLO_REARMUVLO Auto rearm when in lock mode:
0: no rearm.
1: auto rearm.

6

TSD_REARMTSD Auto rearm when in lock mode:
0: no rearm.
1: auto rearm.

5

TSD_Gating

Avoid startup of power−up sequence if Tj > 125°C
0: disable
1: enable

4

TSD_PRWRNG

3

UVLO

2

1

0

Description

Thermal shutdown pre−warning selection
0: 140°C
1: 130°C
UVLO Programmability:
Rising
Falling
0000:
4.5 V
4.3 V
0001:
6.0 V
4.3 V
0010:
7.0 V
4.3 V
0011:
8.0 V
4.3 V
0100:
6.0 V
5.0 V
0101:
7.0 V
5.0 V
0110:
8.0 V
5.0 V
0111:
6.0 V
5.5 V
1000:
7.0 V
5.5 V
1001:
8.0 V
5.5 V
1010:
7.0 V
6.0 V
1011:
8.0 V
6.0 V
1100:
N/A
N/A
1101:
N/A
N/A
1110:
N/A
N/A
1111:
N/A
N/A

Table 36. IC CONFIGURATIONS REGISTER 2
Register Name

IC_CONFIGURATION_2

Address

16

Type

CRC

Default

00000000b (0h)Trigger
Bit

Name

7

empty

6

CRCEN

5

AutoRearmCnt_RST

4

empty

3

AutoRearmCnt

2
1

empty

0

BistCnt

Description

I2C communication CRC enable
0: I2C communication without CRC
1: I2C communication with CRC
Once set to 1, internal error counter is resetted.
This bit is self cleared to 0 once the counter is resetted.

Safe state auto restart:
00: No restart
01: 3 restarts
10: 15 restarts
11: 63 restarts

BIST Retry:
0: no retry
1: one retry

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NCV92310
Table 37. IC CONFIGURATIONS REGISTER 3
Register Name

IC_CONFIGURATION_3

Address

17

Type

CRC

Default

00001100b (Ch)

Trigger
Bit

Name

7

FRCINTB

Bit to force interrupt pin low or high0: INTB follow the state machine description
1: INTB pin forced low

6

NLOCK

NLOCK bit when NCV92310 in lock mode. Self cleared once done.
0: no unlock
1: NCV92310 unlocked

5

FAULT_TIMEOUT

2 bits for Active Flag Mode state timeout:
00: disable
01: 45 ms
10: 95 ms
11: 150 ms

Soft_RST_Timer

Soft Reset Timer:
00: 1 ms
01: 16 ms

4
3
2

Description

01: 4 ms
11: 64 ms

1

Soft_RSTSoft Reset bit:
0: no soft reset.
1: /RST pin pulled low. Timing set in the Soft Reset Timer. Self cleared once done0

Forced_RST

Forced Reset bit:
0: no reset
1: Reset, NCV92310 will start a Power down sequence followed by a BIST and a Power up
Sequence. Bit is cleared once done.

Table 38. IC CONFIGURATIONS REGISTER 4
Register Name

IC_CONFIGURATION_4

Address

18

Type

CRC

Default

00000000b (0h)Trigger
Bit

Name

7

empty

6

empty

5

empty

4

SPREAD_FSW

Spread Spectrum Switching Frequency Variation:
0: 10% max
1: 5% max

3

SPREAD_MODF

Spread spectrum divider (frequency changed every x cycles)
LFSR
Triangular
00: Divider = 1, Divider = 4
01: Divider = 2, Divider = 5
10: Divider = 3, Divider = 6
11: Divider = 4, Divider = 7

1

SPREAD_MODT

Spread Spectrum modulation scheme
0: LFSR (16 bits Pseudo random equal distribution)
1: Triangular (dual peak)0

SPREAD_EN

2

Description

Spread Spectrum Enable bit:0: Disable
1: Enable

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NCV92310
Table 39. INTERRUPT FLAG IC MASK REGISTER
Register Name

INTERRUPT_MASK_IC

Address

19

Type

CRC

Default

00000000b (0h)Trigger
Bit

Name

Description

7

empty

6

empty

5

MSK_TSD_WRNG

Thermal Shutdown Warning Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked

4

MSK_TSD_PRWRNG

Thermal Shutdown Pre−Warning Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked

3

empty

2

empty

1

MSK_I2CERROR

I2C communication error Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
OTP bit available to desactivate the whole function

0

MSK_OVFOVD Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
OTP bit available to desactivate the whole function

Table 40. INTERRUPT MASK REGISTER OVERVOLTAGE MONITORING THRESHOLD
Register Name

INTERRUPT_MASK_OV

Address

1A

Type

CRC

Default

00000000b (0h)Trigger
Bit

Name

Description

7

empty

6

empty

5

empty

4

empty

3

MSK_OV_LDO1

LDO1 Monitoring Over Voltage Threshold Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
If LDO1_SAFE bit is set high, fault cannot be masked

2

MSK_OV_DCDC3

DCDC3 Monitoring Over Voltage Threshold Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
If DCDC3_SAFE bit is set high, fault cannot be masked

1

MSK_OV_DCDC2

DCDC2 Monitoring Over Voltage Threshold Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
If DCDC2_SAFE bit is set high, fault cannot be masked

0

MSK_OV_DCDC1

DCDC1 Monitoring Over Voltage Threshold Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
If DCDC1_SAFE bit is set high, fault cannot be masked

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NCV92310
Table 41. INTERRUPT MASK REGISTER UNDERVOLTAGE MONITORING THRESHOLD
Register Name

INTERRUPT_MASK_UV

Address

1B

Type

CRC

Default

00000000b (0h)Trigger
Bit

Name

Description

7

empty

6

empty

5

empty

4

empty

3

MSK_UV_LDO1

LDO1 Monitoring Under Voltage Threshold Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
If LDO1_SAFE bit is set high, fault cannot be masked

2

MSK_UV_DCDC3

DCDC3 Monitoring Under Voltage Threshold Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
If DCDC3_SAFE bit is set high, fault cannot be masked

1

MSK_UV_DCDC2

DCDC2 Monitoring Under Voltage Threshold Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
If DCDC2_SAFE bit is set high, fault cannot be masked

0

MSK_UV_DCDC1

DCDC1 Monitoring Under Voltage Threshold Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
If DCDC1_SAFE bit is set high, fault cannot be masked

Table 42. INTERRUPT MASK REGISTER OVERCURRENT PROTECTION
Register Name

INTERRUPT_MASK_OC

Address

1C

Type

CRC

Default

00101010b (2Ah)

Trigger
Bit

Name

Description

7

empty

6

MSK_LDO1_OCP

5

MSK_IPEAK_NEG_DCDC3

DCDC3 Negative current limitation Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
OTP bit available to mask the /INTB pin pulled low when Ipeak neg is triggered

4

MSK_IPEAK_POS_DCDC3

DCDC3 Inductor IPEAK current limitation Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked

3

MSK_IPEAK_NEG_DCDC2

DCDC2 Negative current limitation Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
OTP bit available to mask the /INTB pin pulled low when Ipeak neg is triggered

2

MSK_IPEAK_POS_DCDC2

DCDC2 Inductor IPEAK current limitation Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked

1

MSK_IPEAK_NEG_DCDC1

DCDC1 Negative current limitation Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
OTP bit available to mask the /INTB pin pulled low when Ipeak neg is triggered

0

MSK_IPEAK_POS_DCDC1

DCDC1 Inductor IPEAK current limitation Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked

LDO1 Over Current Protection Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked

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NCV92310
Table 43. DCDC1 OUTPUT VOLTAGE PROGRAMMATION REGISTER
Register NameOUTPUT_VOLTAGE_DCDC1

Address

1D

Type

CRC

Default

00000101b (5h)Trigger
Bit

Name

7

empty

6

empty

5

empty

4

empty

3

VDCDC10

Description

DCDC1 Output Voltage Programmability
0000: 2.8 V
0001: 2.9 V
0010: 3.0 V
0011: 3.1 V
0100: 3.2 V
0101: 3.3 V
0110: 3.4 V
0111: 3.5 V
1000: 3.6 V
1001: 3.8 V
1010: 4.0 V
1011: 4.2 V
1100: 4.4 V
1101: 4.6 V
1101: 4.8 V
1111: 5.0 V

Table 44. DCDC1 CONFIGURATION REGISTER
Register NameCONFIGURATION_DCDC1

Address

1E

Type

CRC

Default

00001101b (Dh)

Trigger
Bit

Name

7

empty

6

empty

5

empty

4

empty

3

DIS_DCDC1

2

Soft_Start_DCDC1

1
0

ENDCDC1

Description

DCDC1 active output discharge
0: Disabled (valid if PWR SEQ_EN = 0)
1: Enabled
2 bits to set the DCDC1 soft start
00: 0.08 ms/V
01: 0.16 ms/V
10: 0.32 ms/V
11: 0.64 ms/V
DCDC1 enable bit: (valid if SEQ_EN = 0)
0: Disabled
1: Enabled

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NCV92310
Table 45. DCDC2 OUTPUT VOLTAGE PROGRAMMATION REGISTER
Register NameOUTPUT_VOLTAGE_DCDC2

Address

1F

Type

CRC

Default

00011000b (18h)

Trigger
Bit

Name

7

empty

6

empty

5

VDCDC2

4

Description

DCDC2 Output Voltage Programmability
From 0.6 V to 2.175 V with 25 mV Step

3
2
1
0

Table 46. DCDC2 CONFIGURATION REGISTER
Register NameCONFIGURATION_DCDC2

Address

20

Type

CRC

Default

00001101b (Dh)

Trigger
Bit

Name

7

empty

6

empty

5

empty

4

empty

3

DIS_DCDC22

Soft_Start_DCDC2

1
0

ENDCDC2

Description

DCDC2 active output discharge
0: Disabled (valid if PWR SEQ_EN = 0)
1: Enabled
2 bits to set the DCDC2 soft start
00: 0.08 ms/V
01: 0.16 ms/V
10: 0.32 ms/V
11: 0.64 ms/V
DCDC2 enable bit: (valid if SEQ_EN = 0)
0: Disabled
1: Enabled

Table 47. DCDC3 OUTPUT VOLTAGE PROGRAMMATION REGISTER
Register NameOUTPUT_VOLTAGE_DCDC3

Address

21

Type

CRC

Default

00110000b (30h)

Trigger
Bit

Name

7

empty

6

empty

5

VDCDC3

4

Description

DCDC3 Output Voltage Programmability
From 0.6 V to 2.175 V with 25 mV Step

3
2
1
0

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NCV92310
Table 48. DCDC3 CONFIGURATION REGISTER
Register NameCONFIGURATION_DCDC3

Address

22

Type

CRC

Default

00001101b (Dh)

Trigger
Bit

Name

7

empty

6

empty

5

empty

4

empty

3

DIS_DCDC32

Soft_Start_DCDC3

1
0

ENDCDC3

Description

DCDC3 active output discharge
0: Disabled (valid if PWR SEQ_EN = 0)
1: Enabled
2 bits to set the DCDC3 soft start
00: 0.08 ms/V
01: 0.16 ms/V
10: 0.32 ms/V
11: 0.64 ms/V
DCDC3 enable bit: (valid if SEQ_EN = 0)
0: Disabled
1: Enabled

Table 49. LDO1 OUTPUT VOLTAGE PROGRAMMATION REGISTER
Register NameOUTPUT_VOLTAGE_LDO1

Address

23

Type

CRC

Default

00000010b (2h)Trigger
Bit

Name

7

empty

6

empty

5

empty

4

empty

3

empty

2

VLDO1

1

Description

LDO1 Output Voltage Programmability
From 2.6 V to 3.3 V with 100 mV step0

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NCV92310
Table 50. LDO1 CONFIGURATION REGISTER
Register NameCONFIGURATION_LDO1

Address

24

Type

CRC

Default

00001101b (Dh)

Trigger
Bit

Name

7

empty

6

empty

5

empty

4

empty

3

DIS_LDO1

2

Soft_Start_LDO1

1
0

ENLDO1

Description

LDO1 active output discharge
0: Disabled (valid if PWR SEQ_EN = 0)
1: Enabled
2 bits to set the LDO1 soft start
00: 0.16 ms/V
01: 0.32 ms/V
10: 0.64 ms/V
11: 1.28 ms/V
LDO1 enable bit: (valid if SEQ_EN = 0)
0: Disabled
1: Enabled

Table 51. MONITORING UNDERVOLTAGE DCDC1 SETTINGS
Register NameMONITORING_UV_DCDC1

Address

25

Type

CRC

Default

00100100b (24h)

Trigger
Bit

Name

7

DCDC1_UVT

6
5
4

1
0

DCDC1 Under Voltage Monitoring Threshold in % of the programmed output voltage:
000: −3.0%001: −3.5%
010: −4.0%
011: −4.5%
100: −5.0%
101: −6.0%
110: −8.0%
111: −10%

DCDC1_DBN_TLR

Debounce Rising edge programmability:
00: 32 ms
01: 64 ms
10: 128 ms
11: 256 ms

DCDC1_DBN_TLF

Debounce falling edge programmability:
000: none
001: 2 ms
010: 4 ms
011: 8 ms
100: 16 ms
101: 32 ms
110: 64 ms
111: 128 ms

3
2

Description

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NCV92310
Table 52. MONITORING OVERVOLTAGE DCDC1 SETTINGS
Register NameMONITORING_OV_DCDC1

Address

26

Type

CRC

Default

01010000b (50h)

Trigger
Bit

Name

7

DCDC1_OVT

654

DCDC1 Under Voltage Monitoring Threshold in % of the programmed output voltage:
000: 3.0%001: 3.5%010: 4.0%
011: 4.5%
100: 5.0%
101: 6.0%
110: 8.0%
111: 10%

DCDC1_DBN_THR

Debounce rising edge programmability:
000: none
001: 2 ms
010: 4 ms
011: 8 ms
100: 16 ms
101: 32 ms
110: 64 ms
111: 128 ms

DCDC1_DBN_THF

Debounce falling edge programmability:
00: 32 ms
01: 64 ms
10: 128 ms
11: 256 ms

3
2
1

Description

0

Table 53. MONITORING UNDERVOLTAGE DCDC2 SETTINGS
Register NameMONITORING_UV_DCDC2

Address

27

Type

CRC

Default

00100100b (24h)

Trigger
Bit

Name

7

DCDC2_UVT

654

DCDC2 Under Voltage Monitoring Threshold in % of the programmed output voltage:
000: −3.0%001: −3.5%
010: −4.0%
011: −4.5%
100: −5.0%
101: −6.0%
110: −8.0%
111: −10%

DCDC2_DBN_TLR

Debounce Rising edge programmability:
00: 32 ms
01: 64 ms
10: 128 ms
11: 256 ms

DCDC2_DBN_TLF

Debounce falling edge programmability:
000: none
001: 2 ms
010: 4 ms
011: 8 ms
100: 16 ms
101: 32 ms
110: 64 ms
111: 128 ms

3
2

Description

1
0

Table 54. MONITORING OVERVOLTAGE DCDC2 SETTINGS
Register NameMONITORING_OV_DCDC2

Address

28

Type

CRC

Default

01010000b (50h)

Trigger
Bit

Name

7

DCDC2_OVT

654

Debounce rising edge programmability:
000: none
001: 2 ms
010: 4 ms
011: 8 ms
100: 16 ms
101: 32 ms
110: 64 ms
111: 128 ms

DCDC2_DBN_THF

Debounce falling edge programmability:
00: 32 ms
01: 64 ms
10: 128 ms
11: 256 ms

2

0

DCDC2 Under Voltage Monitoring Threshold in % of the programmed output voltage:
000: 3.0%001: 3.5%010: 4.0%
011: 4.5%
100: 5.0%
101: 6.0%
110: 8.0%
111: 10%

DCDC2_DBN_THR

3

1

Description

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NCV92310
Table 55. MONITORING UNDERVOLTAGE DCDC3 SETTINGS
Register NameMONITORING_UV_DCDC3

Address

29

Type

CRC

Default

00100100b (24h)

Trigger
Bit

Name

7

DCDC3_UVT

654

DCDC3 Under Voltage Monitoring Threshold in % of the programmed output voltage :000: −3.0%001: −3.5%
010: −4.0%
011: −4.5%
100: −5.0%
101: −6.0%
110: −8.0%
111: −10%

DCDC3_DBN_TLR

Debounce Rising edge programmability:
00: 32 ms
01: 64 ms
10: 128 ms
11: 256 ms

DCDC3_DBN_TLF

Debounce falling edge programmability:
000: none
001: 2 ms
010: 4 ms
011: 8 ms
100: 16 ms
101: 32 ms
110: 64 ms
111: 128 ms

3
2

Description

1
0

Table 56. MONITORING OVERVOLTAGE DCDC3 SETTINGS
Register NameMONITORING_OV_DCDC3

Address

2A

Type

CRC

Default

01010000b (50h)

Trigger
Bit

Name

7

DCDC3_OVT

654

DCDC3_DBN_THR

Debounce rising edge programmability:
000: none
001: 2 ms
010: 4 ms
011: 8 ms
100: 16 ms
101: 32 ms
110: 64 ms
111: 128 ms

DCDC3_DBN_THF

Debounce falling edge programmability:
00: 32 ms
01: 64 ms
10: 128 ms
11: 256 ms

3
2
1

Description
DCDC3 Under Voltage Monitoring Threshold in % of the programmed output voltage:
000: 3.0%001: 3.5%010: 4.0%
011: 4.5%
100: 5.0%
101: 6.0%
110: 8.0%
111: 10%0

Table 57. MONITORING UNDERVOLTAGE LDO1 SETTINGS
Register NameMONITORING_UV_LDO1

Address

2B

Type

CRC

Default

00100100b (24h)

Trigger
Bit

Name

7

LDO1_UVT

6
5
4

1
0

LDO1 Under Voltage Monitoring Threshold in % of the programmed output voltage :000: −3.0%001: −3.5%
010: −4.0%
011: −4.5%
100: −5.0%
101: −6.0%
110: −8.0%
111: −10%

LDO1_DBN_TLR

Debounce Rising edge programmability:
00: 32 ms
01: 64 ms
10: 128 ms
11: 256 ms

LDO1_DBN_TLF

Debounce falling edge programmability:
000: none
001: 2 ms
010: 4 ms
011: 8 ms
100: 16 ms
101: 32 ms
110: 64 ms
111: 128 ms

3
2

Description

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NCV92310
Table 58. MONITORING OVERVOLTAGE LDO1 SETTINGS
Register NameMONITORING_OV_LDO1

Address

2C

Type

CRC

Default

01010000b (50h)

Trigger
Bit

Name

7

LDO1_OVT

65
4

LDO1 Under Voltage Monitoring Threshold in % of the programmed output voltage:
000: 3.0%001: 3.5%010: 4.0%
011: 4.5%
100: 5.0%
101: 6.0%
110: 8.0%
111: 10%

LDO1_DBN_THR

Debounce rising edge programmability:
000: none
001: 2 ms
010: 4 ms
011: 8 ms
100: 16 ms
101: 32 ms
110: 64 ms
111: 128 ms

LDO1_DBN_THF

Debounce falling edge programmability:
00: 32 ms
01: 64 ms
10: 128 ms
11: 256 ms

3
2
1

Description

0

Table 59. SEQUENCER ASSIGNMENT DCDC1 REGISTER
Register Name

SEQUENCER_ASSIGNMENT_DCDC1

Address

2D

Type

CRC

Default

00000000b (0h)Trigger
Bit

Name

7

empty

6

empty

5

SLOTPDS_DCDC1

Description

DCDC1 Power Down Sequence SLOT assignment

4
3

empty

2

empty

1

SLOTPUS_DCDC1

DCDC1 Power up Sequence SLOT assignment

0

Table 60. SEQUENCER ASSIGNMENT DCDC2 REGISTER
Register Name

SEQUENCER_ASSIGNMENT_DCDC2

Address

2E

Type

CRC

Default

00010001b (11h)

Trigger
Bit

Name

7

empty

6

empty

5

SLOTPDS_DCDC2

Description

DCDC2 Power Down Sequence SLOT assignment

4
3

empty

2

empty

1

SLOTPUS_DCDC2

DCDC2 Power up Sequence SLOT assignment

0

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NCV92310
Table 61. SEQUENCER ASSIGNMENT DCDC3 REGISTER
Register Name

SEQUENCER_ASSIGNMENT_DCDC3

Address

30

Type

CRC

Default

00100010b (22h)

Trigger
Bit

Name

7

empty

6

empty

5

SLOTPDS_DCDC3

Description

DCDC3 Power Down Sequence SLOT assignment

4
3

empty

2

empty

1

SLOTPUS_DCDC3

DCDC3 Power up Sequence SLOT assignment

0

Table 62. SEQUENCER ASSIGNMENT LDO1 REGISTER
Register Name

SEQUENCER_ASSIGNMENT_LDO1

Address

31

Type

CRC

Default

00110011b (33h)

Trigger
Bit

Name

7

empty

6

empty

5

SLOTPDS_LDO

Description

LDO1 Power Down Sequence SLOT assignment

4
3

empty

2

empty

1

SLOTPUS_LDO

LDO1 Power up Sequence SLOT assignment

0

Table 63. SEQUENCER CONFIGURATION REGISTER 1
Register Name

SEQUENCER_CONFIGURATION_1

Address

32

Type

CRC

Default

00001101b (Dh)

Trigger
Bit

Name

Description

7

empty

6

PUS_Init_Delay

Power Up Sequence Init Delay at the beginiing of SLOTx
00: 0 ms
01: 128 ms
10: 256 ms
11: 1024 ms

4

PUS_DELAY

PUS_Init_Delay assignment:
0: only SLOT 0
1: All SLOT

3

PUSTO

Time period of empty slot, power up sequence fault for assigned slot
00: 2 ms
01: 4 ms
10: 8 ms
11: 16 ms

RST_DLY

Power up Sequence Reset Delay (/RST pin)
00: 2 ms
01: 8 ms
10: 16 ms
11: 32 ms

5

2
1
0

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NCV92310
Table 64. SEQUENCER CONFIGURATION REGISTER 2
Register Name

SEQUENCER_CONFIGURATION_2

Address

33

Type

CRC

Default

01101011b (6Bh)

Trigger
Bit

Name

7

empty

6

PDS_Init_Delay

5
4

empty

3

PDSTO

2

1

PWR_SEQ_EN

0

PS

Description

Power Down Sequence Init Delay
00: 128 ms
01: 512 ms
10: 2048 ms
11: 8192 ms
Time period of empty slot, no power down sequence fault for assigned slot (continues to next
slot once delay is reached)
00: 4 ms
01: 8 ms
10: 16 ms
11: 32 ms
Bit to enable / disable the internal sequencer:
0: disabled (internal regulator controlled by ENx bits)
1: enabled
0: start the power down sequence
1: start the power up sequence

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NCV92310
APPLICATION INFORMATION
Output Filter Design Considerations

The output filter introduces a double pole in the system ata frequency off LC +

L+ǸLp(eq. 7)

C

V IN

f SW

V OUT
I L_PP(eq. 8)The selected inductor must have high enough saturation
current rating to be higher than the maximum peak current
that is12ǒVIN * V OUTǓThe internal compensation network design of theNCV92310 is optimized for the typical output filter.

I L_MAX + I OUT_MAX +Inductor Selection

I L_PP(eq. 9)2

The inductor also needs to have high enough current
rating based on temperature rise concern. Low DCR is goodfor efficiency improvement and temperature rise reduction.
Table 65 shows some recommended inductors for highpower applications and Table 65 shows some recommended
inductors for low power applications.

The inductance of the inductor is determined by givenpeak−to−peak ripple current IL_PP of approximately 20% to
50% of the maximum output current IOUT_MAX for a
trade−off between transient response and output ripple. The
inductance corresponding to the given current ripple isTable 65. LIST OF RECOMMENDED INDUCTORSManufacturer

Part #

Case Size(mm)

L (mH)

Rdc (W)
Typ / Max

Rac (W)

Rated Current (mA)
(Inductance Drop)

MURATADFE2HCAH2R2MJ0

2520

2.2

84 / 101

0.85

3100

TDK

TFM252012ALMA2R2MTAA

2520

2.2

75 / 84

1.14

3300

MURATADFE2MCAH1R0MJ0

2016

1.0

57 / 68

0.48

3100

TDK

TFM201610ALMA1R0MTAA

2016

1.0

50 / 60

0.54

3700

TDK

TFM201612BLEA1R0MTCA

2016

1.0

34 / 42

−

4300

TDK

TFM201612BLEA2R2MTCA

2016

2.2

80 / 105−2800

Output Capacitor Selection

In applications with all ceramic output capacitors, themain ripple component of the output ripple is VOUT_PP(C).
So that the minimum output capacitance COUT_MIN can becalculated regarding to a given output ripple requirement
VOUT_PP in PWM operation mode.

The output capacitor selection is determined by output
voltage ripple and load transient response requirement. For
a given peak−to−peak ripple current IL_PP in the inductorof the output filter, the output voltage ripple across theoutput capacitor is the sum of three ripple components as
below
V OUT_PP [ V OUT_PP(C) ) V OUT_PP(ESR) ) V OUT_PP(ESL)C OUT_MIN +(eq. 10)CV OUT_PP(ESR) + I L_PP
V OUT_PP(ESL) +f SW(eq. 11)

C IN_MIN +ESR(eq. 12)Where(eq. 13)

D+

ESL

V IN

ESL ) LAnd the peak−to−peak ripple current is
I L_PP +ǒVIN * VOUTǓ
V IN

f SW

(eq. 15)I OUT_MAXV IN_PP(D * D 2)
f SW(eq. 16)

V OUT
V IN

(eq. 17)

In addition, the input capacitor needs to be able to absorb
the input current, which has an RMS value ofǸD * D2
I
+I

V OUT
L

f SW

One of the input capacitor selection guides is the input
voltage ripple requirement. To minimize the input voltage
ripple and get better decoupling in the input power supply
rail, ceramic capacitor is recommended due to low ESR and
ESL. The minimum input capacitance CIN_MIN regarding to
the input ripple voltage VIN_PP isI L_PP
8

V OUT_PP

Input Capacitor Selection

Where VOUT_PP(C) is a ripple component by an equivalent
total capacitance of the output capacitors, VOUT_PP(ESR) isa ripple component by an equivalent ESR of the output
capacitors, and VOUT_PP(ESL) is a ripple component by anequivalent ESL of the output capacitors. In PWM operationmode, the three ripple components can be obtained by
V OUT_PP(C) +I L_PP8(eq. 14)

IN_RMS

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OUT_MAX(eq. 18)

NCV92310
4.7 mF capacitor is required. The input capacitor should belocated as close as possible to the IC on PCB.

The input capacitor also needs to be sufficient to protect
the device from over voltage spike, and normally at least a

Table 66. LIST OF RECOMMENDED INPUT AND OUTPUT CAPACITORSManufacturer

Part #

Case Size (mm)Technology

C (mF)

Rated Voltage (V)TDK

CGA5L1X7R1E106K160AC

1206

X7R

10

25

MurataGCM31CC71E106KA03L

1206

X7S

10

25

TDK

CGA4J1X7S1E106K125AC

0805

X7S

10

25

TDK

CGA4J1X7R0J106K125AC

0805

X7R

10

6.3

Murata

GCM21BR71A106KE22L

0805

X7R

10

10

TDK

CGA3E1X7T0J106M080AC

0603

X7T

10

6.3

TDK

CGA3E1X7R0J225K080AC

0603

X7R

2.2

6.3

TDK

CGA2B3X7R1E224K050BB

0402

X7R

0.22

50

TDK

CGA2B3X7R1E104K050BB

0402

X7R

0.1

25

TDK

CGA2B3X7R1E474K050BB

0402

X7S

0.47

10

MURATAGCM155C71A105K

0402

X7S

1

10

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NCV92310
PCB LAYOUT CONSIDERATIONS• SW node should be a large copper pour, but compact

Electrical Layout Considerations

Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction. Electricallayout guidelines are:• Use wide and short traces for power paths (such as PVIN,
VOUT, SW, and PGND) to reduce parasitic inductance andhigh−frequency loop area. It is also good for efficiency
improvement.
• The device should be well decoupled by input capacitor
and input loop area should be as small as possible toreduce parasitic inductance, input voltage spike, andnoise emission.

because it is also a noise source.

• It would be good to have separated local ground planes for
PGND and AGND. Directly connect AGND pin to the
exposed pad and then connect to AGND ground planethrough vias. Try best to avoid overlap of input groundloop and output ground loop to prevent noise impact on
output regulation.
• Arrange a “quiet” path for output voltage sense, and makeit surrounded by a ground plane.

To be updated

Figure 25. Recommended PCB Layout

ORDERING INFORMATION
Package

Shipping†

QFNW203000 / Tape & Reel

TBD

TBD

TBD / Tape & Reel

TBD

TBD

TBD / Tape & Reel

Device
NCV92310ABMTWTXG†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

onsemi is licensed by the Philips Corporation to carry the I2C bus protocol.

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NCV92310
PACKAGE DIMENSIONSQFNW20 3.5x3.5, 0.5P
CASE 484AV
ISSUE Awww.onsemi.com
60

NCV92310

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