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NA555, NE555, SA555, SE555
SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014

xx555 Precision Timers
1 Features

3 Description

•
•
•
•

These devices are precision timing circuits capable ofproducing accurate time delays or oscillation. In thetime-delay or mono-stable mode of operation, thetimed interval is controlled by a single external
resistor and capacitor network. In the a-stable modeof operation, the frequency and duty cycle can becontrolled independently with two external resistors
and a single external capacitor.

1•

Timing From Microseconds to Hours
Astable or Monostable Operation
Adjustable Duty Cycle
TTL-Compatible Output Can Sink or Source
Up to 200 mA
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include
Testing of All Parameters.

The threshold and trigger levels normally are twothirds and one-third, respectively, of VCC. Theselevels can be altered by use of the control-voltage
terminal. When the trigger input falls below the trigger
level, the flip-flop is set, and the output goes high. If
the trigger input is above the trigger level and thethreshold input is above the threshold level, the flipflop is reset and the output is low. The reset (RESET)
input can override all other inputs and can be used toinitiate a new timing cycle. When RESET goes low,
the flip-flop is reset, and the output goes low. Whenthe output is low, a low-impedance path is provided
between discharge (DISCH) and ground.

2 Applications•••

Fingerprint Biometrics
Iris Biometrics
RFID Reader

The output circuit is capable of sinking or sourcing
current up to 200 mA. Operation is specified forsupplies of 5 V to 15 V. With a 5-V supply, output
levels are compatible with TTL inputs.
Device Information(1)PART NUMBER

xx555

PACKAGEBODY SIZE (NOM)

PDIP (8)9.81 mm × 6.35 mm

SOP (8)6.20 mm × 5.30 mm

TSSOP (8)3.00 mm × 4.40 mm

SOIC (8)4.90 mm × 3.91 mm(1) For all available packages, see the orderable addendum atthe end of the datasheet.

4 Simplified Schematic
VCC
8

6
THRES

2
TRIG

CONT
5

Î
Î
Î Î
Î Î
Î
Î Î

RESET
4

Î
Î
Î
Î
Î
Î
Î

R1
R

3
OUT

1

S

7

DISCH

1
GND

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

NA555, NE555, SA555, SE555
SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014

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Table of Contents
1
2
3
4
5
6
7

Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Simplified Schematic............................................. 1
Revision History..................................................... 2
Pin Configuration and Functions ......................... 3
Specifications......................................................... 4
7.1
7.2
7.3
7.4
7.5
7.6

8

Absolute Maximum Ratings ..................................... 4
Handling Ratings....................................................... 4
Recommended Operating Conditions....................... 4
Electrical Characteristics........................................... 5
Operating Characteristics.......................................... 6
Typical Characteristics .............................................. 7

Detailed Description .............................................. 9

8.1
8.2
8.3
8.4

9

Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................... 9
Device Functional Modes........................................ 12

Applications and Implementation ...................... 13
9.1 Application Information............................................ 13
9.2 Typical Applications ................................................ 13

10 Power Supply Recommendations ..................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4

Related Links ........................................................ 19
Trademarks ........................................................... 19
Electrostatic Discharge Caution ............................ 19
Glossary ................................................................ 19

12 Mechanical, Packaging, and Orderable
Information ........................................................... 19

5 Revision History
Changes from Revision H (June 2010) to Revision I

Page

•

Updated document to new TI enhanced data sheet format. .................................................................................................. 1•

Deleted Ordering Information table. ...................................................................................................................................... 1•

Added Military Disclaimer to Features list. ............................................................................................................................. 1•

Added Applications. ................................................................................................................................................................ 1•

Added Device Information table. ............................................................................................................................................ 1•

Moved Tstg to Handling Ratings table. .................................................................................................................................... 4•

Added DISCH switch on-state voltage parameter. ................................................................................................................. 5•

Added Device and Documentation Support section............................................................................................................. 19•

Added ESD warning. ............................................................................................................................................................ 19•

Added Mechanical, Packaging, and Orderable Information section..................................................................................... 192

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SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014

6 Pin Configuration and Functions
NA555...D OR P PACKAGE
NE555...D, P, PS, OR PW PACKAGE
SA555...D OR P PACKAGE
SE555...D, JG, OR P PACKAGE(TOP VIEW)
1

8

2

7

3

6

4

5

VCC
DISCH
THRES
CONT

NC
GND
NC
VCC
NC
NC
TRIG
NC
OUT
NC

4

3 2 1 20 19
18

5

17

6

16

7

15
14
9 10 11 12 13

8

NC
DISCH
NC
THRES
NC

NC
RESET
NC
CONT
NC

GND
TRIG
OUT
RESET

SE555...FK PACKAGE(TOP VIEW)

NC – No internal connection

Pin Functions
PIN
NAME

D, P, PS,PW, JGFK

I/O

DESCRIPTION

NO.
CONT

5

12

I/O

Controls comparator thresholds, Outputs 2/3 VCC, allows bypass capacitor
connection

DISCH

7

17

O

Open collector output to discharge timing capacitor

GND

1

2

–

Ground

1, 3, 4, 6, 8,
9, 11, 13,
14, 16, 18,
19–

No internal connection

NC
OUT

3

7

O

High current timer output signal

RESET

4

10

I

Active low reset input forces output and discharge low.

THRES

6

15

I

End of timing input. THRES > CONT sets output low and discharge low

TRIG

2

5

I

Start of timing input. TRIG < ½ CONT sets output high and discharge open

VCC

8

20

–

Input supply voltage, 4.5 V to 16 V. (SE555 maximum is 18 V)

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7 Specifications
7.1 Absolute Maximum Ratings (1)over operating free-air temperature range (unless otherwise noted)
MIN
VCC

Supply voltage (2)VI

Input voltage

IO

Output current

θJA

CONT, RESET, THRES, TRIG

Package thermal impedance (3) (4)θJC

Package thermal impedance (5) (6)TJ

Operating virtual junction temperature

(1)
(2)
(3)
(4)
(5)
(6)

MAX

UNIT

18

V

VCC

V

±225

mA

D package97

P package85

PS package

95

PW package

149

FK package

5.61

JG package

14.5

°C/W

°C/W

150

°C

Case temperature for 60 s

FK package

260

°C

Lead temperature 1,6 mm (1/16 in) from case for 60 s

JG package

300

°C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) - TA) / θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
Maximum power dissipation is a function of TJ(max), θJC, and TC. The maximum allowable power dissipation at any allowable casetemperature is PD = (TJ(max) - TC) / θJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with MIL-STD-883.

7.2 Handling Ratings
PARAMETER
Tstg

DEFINITION
Storage temperature range

MIN

MAX

UNIT

–65

150

°C

UNIT

7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)

VCC

Supply voltage

VI

Input voltage

IO

Output current

TA

4

Operating free-air temperature

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MIN

MAX

NA555, NE555, SA555

4.5

16

SE555

4.5

18

CONT, RESET, THRES, and TRIG

V

VCC

V

±200

mA

NA555

–40

105

NE555

0

70

SA555

–40

85

SE555

–55

125

°C

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SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014

7.4 Electrical Characteristics
VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted)
PARAMETERTHRES voltage level

TEST CONDITIONS
MIN

TYP

MAX

MIN

TYP

MAX

9.4

10

10.6

8.8

10

11.2

VCC = 5 V

2.7

3.3

4

2.4

3.3

4.2

30

250

5

5.2

1.67

1.9

4.8

VCC = 15 V

TA = –55°C to 125°C

TRIG voltage level

RESET current

3
1.45

VCC = 5 V

RESET voltage level

0.3

5.6

1.1

1.67

2.2

0.5

2

0.7

1

nA

V

0.9
1

0.3

1.1

μA
V

RESET at VCC

0.1

0.4

0.1

0.4

RESET at 0 V

–0.4

–1

–0.4

–1.5

20

100

20

100

nA

0.15

0.4

V

9

10

11

2.6

3.3

4

0.1

0.25

0.4

0.75

2

2.5

VCC = 5 V, IO = 8 mA
9.6
TA = –55°C to 125°C
TA = –55°C to 125°C

VCC = 15 V, IOL = 10 mA
VCC = 15 V, IOL = 50 mA
VCC = 15 V, IOL = 100 mA

VCC = 5 V, IOL = 5 mA

Output low, No load
Supply current
Output high, No load

3.8

0.1

0.15
0.5
1

2
TA = –55°C to 125°C

2.2
2.7

V

2.5
TA = –55°C to 125°C

2.5
0.35

0.1
TA = –55°C to 125°C

0.2

0.1

0.35

0.15

0.4

0.8
0.15
13

0.25

13.3

12.75

13.3

12
12.5
3

TA = –55°C to 125°C

V

0.2

TA = –55°C to 125°C

TA = –55°C to 125°C

mA

3.8

0.4

VCC = 15 V, IOH = –200 mA
VCC = 5 V, IOH = –100 mA

3.3

TA = –55°C to 125°C

VCC = 5 V, IOL = 8 mA
VCC = 15 V, IOH = –100 mA

10.4
10.4

2.9

VCC = 15 V, IOL = 200 mA
VCC = 5 V, IOL = 3.5 mA

10

9.6
2.9

VCC = 5 V

(1)

0.7

TA = –55°C to 125°C

CONT voltage(open circuit)

High-level output voltage

250

5

V

1.9
0.5

VCC = 15 V

Low-level output voltage

30
4.5

6

TA = –55°C to 125°C

TRIG at 0 V

DISCH switch off-state
current
DISCH switch on-statevoltage

UNIT

VCC = 15 V

THRES current (1)TRIG current

NA555
NE555
SA555

SE555

12.5

3.3

2.75

V

3.3

2

VCC = 15 V

10

12

10

15

VCC = 5 V

3

5

3

6

VCC = 15 V

9

10

9

13

VCC = 5 V

2

4

2

5

mA

This parameter influences the maximum value of the timing resistors RA and RB in the circuit of Figure 12. For example,
when VCC = 5 V, the maximum value is R = RA + RB ≉ 3.4 MΩ, and for VCC = 15 V, the maximum value is 10 MΩ.

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7.5 Operating Characteristics
VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted)
PARAMETER

MIN
Initial error of timing
interval (2)Each timer, monostable (3)Temperature coefficient oftiming interval

Each timer, monostable (3)Each timer, astable
Each timer, astable

TA = 25°C

(5)

TYP

MAX

0.5

1.5 (4)

1.5
TA = MIN to MAX

(5)

(3)
Supply-voltage sensitivity of Each timer, monostable(5)
timing interval
Each timer, astable

NA555
NE555
SA555

SE555

TEST
CONDITIONS (1)

30
0.05

TYP

MAX

1

3

2.25
100 (4)90
TA = 25°C

MIN

UNIT

50

ppm/
°C

150
0.2 (4)

0.15

0.1

%

0.5

0.3

%/V

Output-pulse rise time

CL = 15 pF,
TA = 25°C

100

200 (4)

100

300

ns

Output-pulse fall time

CL = 15 pF,
TA = 25°C

100

200 (4)

100

300

ns

(1)
(2)
(3)
(4)
(5)

6

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
Timing interval error is defined as the difference between the measured value and the average value of a random sample from eachprocess run.
Values specified are for a device in a monostable circuit similar to Figure 9, with the following component values: RA = 2 kΩ to 100 kΩ,
C = 0.1 μF.
On products compliant to MIL-PRF-38535, this parameter is not production tested.
Values specified are for a device in an astable circuit similar to Figure 12, with the following component values: RA = 1 kΩ to 100 kΩ,
C = 0.1 μF.

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SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014

7.6 Typical Characteristics
Data for temperatures below –40°C and above 105°C are applicable for SE555 circuits only.
10
7

VCC = 5 V

42

VOL − Low-Level Output Voltage − V

VOL − Low-Level Output Voltage − V

107

TA = −55°C

1
0.7

TA = 25°C

0.4
TA = 125°C

0.2
0.1
0.07
0.04

2

TA = 25°C

10.7

TA= −55°C

0.4

TA = 125°C

0.2
0.1
0.07
0.04
0.02

0.02

0.01

0.01
1

2

4

7

10

20

40

1

70 100

4

7

10

20

40

70 100

IOL − Low-Level Output Current − mA

Figure 1. Low-Level Output Voltage
vs Low-Level Output Current

Figure 2. Low-Level Output Voltage
vs Low-Level Output Current
TA = −55°C

VCC = 15 V

1.8

4

( VCC − VOH) − Voltage Drop − V

TA = −55°C

2
1
0.7
0.4

TA = 25°C

0.2
TA = 125°C
0.1
0.07
0.04
0.02

1.6

TA = 25°C

1.4
1.2

TA = 125°C

1
0.8
0.6
0.4
0.2

0.01
1

2

4

7

10

20

40

0

70 100VCC = 5 V to 15 V
1

2
4
7 10
20
40
70 100IOH − High-Level Output Current − mA

IOL − Low-Level Output Current − mA

Figure 3. Low-Level Output Voltage
vs Low-Level Output Current
Output Low,
No Load98TA = 25°C
7
6
5
TA = −55°C
4Figure 4. Drop Between Supply Voltage and Output
vs High-Level Output Current
Pulse Duration Relative to Value at VCC = 10 V

10I CC − Supply Current − mA

2

IOL − Low-Level Output Current − mA

2.0

10
7

VOL − Low-Level Output Voltage − V

VCC = 10 V

4

TA = 125°C

3
2
1

1.015

1.010

1.005

1

0.995

0.990
8
0.985

0
5

6

7

8

9

10

11

12

13

14

15

0

5

10

15

20

VCC − Supply Voltage − V

VCC − Supply Voltage − V

Figure 5. Supply Current
vs Supply Voltage

Figure 6. Normalized Output Pulse Duration(Monostable Operation)
vs Supply Voltage

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Typical Characteristics (continued)
Data for temperatures below –40°C and above 105°C are applicable for SE555 circuits only.
1000
VCC = 10 V

900
TA = 125°C

1.010

t PD – Propagation Delay Time – ns

Pulse Duration Relative to Value at TA = 25 C

1.015

1.005

1

0.995

0.990
8

700
TA = 70°C
600
500
TA = 25°C
400
300
T A = 0° C
200
TA = –55°C
100

0.985
−75

8

−50

−25

0

25

50

75

100 125TA − Free-Air Temperature − °C

Figure 7. Normalized Output Pulse Duration(Monostable Operation)
vsFree-Air Temperature

8800

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000.05 0.1 0.15
0.2 0.25 0.3 0.35
Lowest Level of Trigger Pulse – ×VCC

0.4

Figure 8. Propagation Delay TimevsLowest Voltage Level of Trigger Pulse

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8 Detailed Description
8.1 Overview
The xx555 timer is a popular and easy to use for general purpose timing applications from 10 µs to hours or from
< 1mHz to 100 kHz. In the time-delay or mono-stable mode of operation, the timed interval is controlled by asingle external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle
can be controlled independently with two external resistors and a single external capacitor. Maximum output sinkand discharge sink current is greater for higher VCC and less for lower VCC.

8.2 Functional Block Diagram
VCC
8

6
THRES

2
TRIG

CONT
5

Î
Î
Î Î
Î
Î Î
Î Î

RESET
4

Î
Î
Î
Î
Î
Î
Î

R1
R

3
OUT

1

S

7

DISCH

1
GND
A.

Pin numbers shown are for the D, JG, P, PS, and PW packages.

B.

RESET can override TRIG, which can override THRES.

8.3 Feature Description
8.3.1 Mono-stable Operation
For mono-stable operation, any of these timers can be connected as shown in Figure 9. If the output is low,
application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high,and turns off Q1. Capacitor C then is charged through RA until the voltage across the capacitor reaches thethreshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the thresholdcomparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q1.

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Feature Description (continued)
VCC(5 V to 15 V)

RA

Î
Î
Î

4
7
6
Input

2

5

8

CONT

VCC

RL

RESET
DISCH
OUT

3

Output

THRES
TRIG
GND
1

Pin numbers shown are for the D, JG, P, PS, and PW packages.

Figure 9. Circuit for Monostable Operation
Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, thesequence ends only if TRIG is high for at least 10 µs before the end of the timing interval. When the trigger isgrounded, the comparator storage time can be as long as 10 µs, which limits the minimum monostable pulse
width to 10 µs. Because of the threshold level and saturation voltage of Q1, the output pulse duration isapproximately tw = 1.1RAC. Figure 11 is a plot of the time constant for various values of RA and C. The thresholdlevels and charge rates both are directly proportional to the supply voltage, VCC. The timing interval is, therefore,
independent of the supply voltage, so long as the supply voltage is constant during the time interval.

ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ

Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges
C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as longas the reset pulse is low. To prevent false triggering, when RESET is not used, it should be connected to VCC.
10
RA = 10 MΩ
1

Input VoltageÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
Output Voltage

Capacitor Voltage

tw − Output Pulse Duration − s

Voltage − 2 V/div

RA = 9.1 kΩ
CL = 0.01 µF
RL = 1 kΩ
See Figure 9

RA = 1 MΩ

10−1

10−2

10−3
RA = 100 kΩ
RA = 10 kΩ

10−4

RA = 1 kΩ
10−5
0.001

0.01

Figure 10. Typical Monostable Waveforms

10

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0.1

1

10

100

C − Capacitance − µF

Time − 0.1 ms/div

Figure 11. Output Pulse Duration vs Capacitance

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Feature Description (continued)
8.3.2 A-stable Operation
As shown in Figure 12, adding a second resistor, RB, to the circuit of Figure 9 and connecting the trigger input tothe threshold input causes the timer to self-trigger and run as a multi-vibrator. The capacitor C charges throughRA and RB and then discharges through RB only. Therefore, the duty cycle is controlled by the values of RA andRB.

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ

This astable connection results in capacitor C charging and discharging between the threshold-voltage level (≈0.67 × VCC) and the trigger-voltage level (≈ 0.33 × VCC). As in the mono-stable circuit, charge and discharge
times (and, therefore, the frequency and duty cycle) are independent of the supply voltage.
VCC(5 V to 15 V)ÎÎÎ

0.01 µF

Open(see Note A) 5

8
VCC

CONT

4
7
RB

6
2

RL

RESET
DISCH

3
OUT

Output

THRES

t
H

TRIG
GND

C

RL = 1 kW
See Figure 12

Voltage − 1 V/div

RA

RA = 5 kW
RB = 3 kW
C = 0.15 µF

tL

Output Voltage

1

Pin numbers shown are for the D, JG, P, PS, and PW packages.
NOTE A: Decoupling CONT voltage to ground with a capacitor can
improve operation. This should be evaluated for individual
applications.

Figure 12. Circuit for Astable Operation

Capacitor Voltage
Time − 0.5 ms/div

Figure 13. Typical Astable Waveforms

Figure 12 shows typical waveforms generated during astable operation. The output high-level duration tH andlow-level duration tL can be calculated as follows:

tH = 0.693 (R A + RB )C(1)

tL = 0.693 (RB )C(2)

Other useful relationships are shown below:

period = tH + tL = 0.693 (R A + 2RB )C

(3)

1.44
frequency »(R A +2RB )C

(4)

tL
RB
Output driver duty cycle ==tH + tL R A + 2RB(5)

Output waveform duty cycle =tH
RB= 1tH + tL
R A + 2RB

(6)

t
RB
Low-to-high ratio = L =tH R A + RB

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Feature Description (continued)
100 k
RA + 2 RB = 1 kΩ
f − Free-Running Frequency − Hz

RA + 2 RB = 10 kΩ
10 k
RA + 2 RB = 100 kΩ
1k

100

10

1

RA + 2 RB = 1 MΩ
RA + 2 RB = 10 MΩ

0.1
0.001

0.01

0.1

1

10

100

C − Capacitance − µF

Figure 14. Free-Running Frequency
8.3.3 Frequency Divider
By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency
divider. Figure 15 shows a divide-by-three circuit that makes use of the fact that re-triggering cannot occur during
the timing cycle.

ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ

Voltage − 2 V/div

VCC = 5 V
RA = 1250 Ω
C = 0.02 µF
See Figure 9

Input Voltage

Output Voltage

Capacitor Voltage
Time − 0.1 ms/div

Figure 15. Divide-by-Three Circuit Waveforms

8.4 Device Functional Modes
Table 1. Function Table

(1)

12

RESET

TRIGGER VOLTAGE (1)

THRESHOLD VOLTAGE (1)OUTPUTDISCHARGE SWITCH

Low

Irrelevant

Irrelevant

Low

On

High

<1/3 VCC

Irrelevant

High

Off

High

>1/3 VCC>2/3 VCC

Low

High

>1/3 VCC<2/3 VCCOn
As previously established

Voltage levels shown are nominal.

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www.ti.com

SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014

9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information
The xx555 timer devices use resistor and capacitor charging delay to provide a programmable time delay oroperating frequency. This section presents a simplified discussion of the design process.

9.2 Typical Applications
9.2.1 Missing-Pulse Detector
The circuit shown in Figure 16 can be used to detect a missing pulse or abnormally long spacing between
consecutive pulses in a train of pulses. The timing interval of the monostable circuit is re-triggered continuously
by the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing,missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output
pulse as shown in Figure 17.
VCC (5 V to 15 V)

4
RESET

Input
2

8

RL

VCC
OUT

3

TRIG
DISCH

5
0.01 µF

CONT

THRES
GND

7

ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
RA

Output6C

1
A5T3644

Pin numbers shown are shown for the D, JG, P, PS, and PW packages.

Figure 16. Circuit for Missing-Pulse Detector
9.2.1.1 Design Requirements
Input fault (missing pulses) must be input high. Input stuck low will not be detected because timing capacitor "C"
will remain discharged.
9.2.1.2 Detailed Design Procedure
Choose RA and C so that RA× C > [maximum normal input high time]. RL improves VOH, but it is not required for
TTL compatibility.

Copyright © 1973–2014, Texas Instruments Incorporated

Product Folder Links: NA555 NE555 SA555 SE555

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www.ti.com

ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ

Typical Applications (continued)
9.2.1.3 Application Curves

Voltage − 2 V/div

VCC = 5 V
RA = 1 kΩ
C = 0.1 µF
See Figure 15

Input Voltage

ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Output Voltage

Capacitor Voltage
Time − 0.1 ms/div
Figure 17. Completed Timing Waveforms for Missing-Pulse Detector

9.2.2 Pulse-Width Modulation
The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which isaccomplished by applying an external voltage (or current) to CONT. Figure 18 shows a circuit for pulse-widthmodulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates thethreshold voltage. Figure 19 shows the resulting output pulse-width modulation. While a sine-wave modulation
signal is shown, any wave shape could be used.
VCC (5 V to 15 V)

4
RESET
Clock
Input

2

RL

8
VCC
OUT

TRIG

RA

3
Output7

DISCH
Modulation
5
Input(see Note A)

CONT
THRES

6

GND
C

1

Pin numbers shown are for the D, JG, P, PS, and PW packages.
NOTE A: The modulating signal can be direct or capacitively coupled
to CONT. For direct coupling, the effects of modulation source
voltage and impedance on the bias of the timer should beconsidered.

Figure 18. Circuit for Pulse-Width Modulation

14

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SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014

Typical Applications (continued)
9.2.2.1 Design Requirements
Clock input must have VOL and VOH levels that are less than and greater than 1/3 VCC. Modulation input canvary from ground to VCC. The application must be tolerant of a nonlinear transfer function; the relationshipbetween modulation input and pulse width is not linear because the capacitor charge is based RC on an negative
exponential curve.
9.2.2.2 Detailed Design Procedure
Choose RA and C so that RA × C = 1/4 [clock input period]. RL improves VOH, but it is not required for TTL
compatibility.

ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏ

9.2.2.3 Application Curves

RA = 3 kΩ
C = 0.02 µF
RL = 1 kΩ
See Figure 18

Voltage − 2 V/div

Modulation Input Voltage

Clock Input Voltage

Output Voltage

Capacitor Voltage

Time − 0.5 ms/div
Figure 19. Pulse-Width-Modulation Waveforms

9.2.3 Pulse-Position Modulation
As shown in Figure 20, any of these timers can be used as a pulse-position modulator. This application
modulates the threshold voltage and, thereby, the time delay, of a free-running oscillator. Figure 21 shows atriangular-wave modulation signal for such a circuit; however, any wave shape could be used.

Copyright © 1973–2014, Texas Instruments Incorporated

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Typical Applications (continued)

VCC (5 V to 15 V)

4
RESET
2

8

RL

VCC
OUT

3
OutputTRIG
DISCH

Modulation
Input 5(see Note A)

RA

CONT

THRES

7

6

RB

GND
C
Pin numbers shown are for the D, JG, P, PS, and PW packages.
NOTE A: The modulating signal can be direct or capacitively coupled
to CONT. For direct coupling, the effects of modulation
source voltage and impedance on the bias of the timer
should be considered.

Figure 20. Circuit for Pulse-Position Modulation
9.2.3.1 Design Requirements
Both DC and AC coupled modulation input will change the upper and lower voltage thresholds for the timing
capacitor. Both frequency and duty cycle will vary with the modulation voltage.
9.2.3.2 Detailed Design Procedure
The nominal output frequency and duty cycle can be determined using formulas in A-stable Operation section. RL
improves VOH, but it is not required for TTL compatibility.

16

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SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014

Typical Applications (continued)

ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ

9.2.3.3 Application Curves

Voltage − 2 V/div

RA = 3 kΩ
RB = 500 Ω
RL = 1 kΩ
See Figure 20

Modulation Input Voltage

Output Voltage

Capacitor Voltage

Time − 0.1 ms/div
Figure 21. Pulse-Position-Modulation Waveforms

9.2.4 Sequential Timer
Many applications, such as computers, require signals for initializing conditions during start-up. Other
applications, such as test equipment, require activation of test signals in sequence. These timing circuits can beconnected to provide such sequential control. The timers can be used in various combinations of astable ormonostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 22
shows a sequencer circuit with possible applications in many systems, and Figure 23 shows the output
waveforms.
VCC

4
RESET
2

8
VCC
3
OUT

TRIG

S

DISCH
5

0.01
µF

CONT

4
RESET

RA 33 kΩ
2
0.001
µF

7

1
CA = 10 µF
RA = 100 kΩ

6

0.01
µF

CA

RB

Output A

CONT

THRES
GND
1
CB

CB = 4.7 µF
RB = 100 kΩ

4
RESET

33 kΩ
2
0.001
µF

DISCH 7
5

THRES
GND

TRIG

8
VCC
3
OUT

DISCH
5

6

0.01
µF

Output B

TRIG

8
VCC
3
OUT

CONT

THRES
GND
1
CC

CC = 14.7 µF
RC = 100 kΩ

RC

7
6

Output C

Pin numbers shown are for the D, JG, P, PS, and PW packages.
NOTE A: S closes momentarily at t = 0.

Figure 22. Sequential Timer Circuit

Copyright © 1973–2014, Texas Instruments Incorporated

Product Folder Links: NA555 NE555 SA555 SE555

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www.ti.com

Typical Applications (continued)
9.2.4.1 Design Requirements
The sequential timer application chains together multiple mono-stable timers. The joining components are the 33kΩ resistors and 0.001-µF capacitors. The output high to low edge passes a 10-µs start pulse to the next
monostable.
9.2.4.2 Detailed Design Procedure
The timing resistors and capacitors can be chosen using this formula. tw = 1.1 × R × C.

ÏÏÏÏÏ
ÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏ
ÏÏÏÏÏ
ÏÏÏÏ
ÏÏ ÏÏÏÏÏ
ÏÏÏÏÏÏ ÏÏÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏ

9.2.4.3 Application Curves

See Figure 22

Voltage − 5 V/div

Output A

twA

twA = 1.1 RACA
twB

Output B

twB = 1.1 RBCB

Output C

twC

twC = 1.1 RCCC

t=0t − Time − 1 s/div
Figure 23. Sequential Timer Waveforms

10 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 4.5 V and 16 V. (18 V for
SE555). A bypass capacitor is highly recommended from VCC to ground pin; ceramic 0.1 µF capacitor issufficient.

18

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NA555, NE555, SA555, SE555
www.ti.com

SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 201411 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related LinksPARTS

PRODUCT FOLDERSAMPLE & BUY

TECHNICALDOCUMENTS

TOOLS &SOFTWARE

SUPPORT &COMMUNITY

NA555

Click here

Click here

Click here

Click here

Click here

NE555

Click here

Click here

Click here

Click here

Click here

SA555

Click here

Click here

Click here

Click here

Click here

SE555

Click here

Click here

Click here

Click here

Click here

11.2 Trademarks
All trademarks are the property of their respective owners.

11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.

12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser based versions of this data sheet, refer to the left hand navigation.

Copyright © 1973–2014, Texas Instruments Incorporated

Product Folder Links: NA555 NE555 SA555 SE555

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PACKAGE OPTION ADDENDUM
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18-Sep-2024

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking(3)

Samples

(4/5)

(6)

JM38510/10901BPA

ACTIVE

CDIP

JG

8

NA555DOBSOLETE

SOIC

D

8

NA555DR

ACTIVE

SOIC

D

8NA555P

ACTIVE

PDIP

P

NA555PE4ACTIVE

PDIP

50

Non-RoHS& Green

SNPB

N / A for Pkg Type

-55 to 125

JM38510/10901BPA

TBD

Call TI

Call TI-40 to 105

NA555

2500

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 105

NA555

Samples

8

50

RoHS & Green

NIPDAU | SN

N / A for Pkg Type

-40 to 105

NA555P

SamplesP

8

50

RoHS & Green

NIPDAUN / A for Pkg Type

-40 to 105

NA555P

Samples

TBD

Call TI

Call TI

0 to 70

NE555

2500

RoHS & Green

NIPDAU | SN

Level-1-260C-UNLIM

0 to 70

NE555

Samples

NE555DOBSOLETE

SOIC

D

8

NE555DR

ACTIVE

SOIC

D

8

NE555DRG4OBSOLETE

SOIC

D

8

TBD

Call TI

Call TI

0 to 70

NE555

NE555P

ACTIVE

PDIP

P

8

50

RoHS & Green

NIPDAU | SN

N / A for Pkg Type

0 to 70

NE555P

Samples

NE555PE4ACTIVE

PDIP

P

8

50

RoHS & Green

NIPDAUN / A for Pkg Type

0 to 70

NE555P

Samples

NE555PSACTIVE

SO

PS

8

80

RoHS & Green

NIPDAU

Level-1-260C-UNLIM

N555

Samples

NE555PSRACTIVE

SO

PS

8

2000

RoHS & Green

NIPDAU

Level-1-260C-UNLIM

0 to 70

N555

Samples

TBD

Call TI

Call TI

0 to 70

N555

2000

RoHS & Green

NIPDAU

Level-1-260C-UNLIM

0 to 70

N555

TBD

Call TI

Call TI-40 to 85

SA555

2500

RoHS & Green

NIPDAU | SN

Level-1-260C-UNLIM-40 to 85

SA555

TBD

Call TI

Call TI-40 to 85

SA555

RoHS & Green

NIPDAUN / A for Pkg Type

-40 to 85

SA555P

NE555PWOBSOLETE

TSSOP

PW

8

NE555PWR

ACTIVE

TSSOP

PW

8

SA555DOBSOLETE

SOIC

D

8

SA555DR

ACTIVESOIC

D

8SA555DRG4OBSOLETE

SOIC

D

8

SA555P

ACTIVE

PDIP

P

8

50

Samples

Samples

Samples

Samples

SE555DOBSOLETE

SOIC

D

8

TBD

Call TI

Call TI-55 to 125

SE555

SE555DG4OBSOLETE

SOIC

D

8

TBD

Call TI

Call TI-55 to 125

SE555

SE555DR

ACTIVE

SOIC

D

8

2500

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-55 to 125

SE555

Samples

SE555DRG4ACTIVE

SOIC

D

8

2500

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-55 to 125

SE555

Samples

Addendum-Page 1

PACKAGE OPTION ADDENDUM
www.ti.com

18-Sep-2024

Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking(3)

Samples

(4/5)

(6)

SE555FKBACTIVE

LCCC

FK

20

55

Non-RoHS& Green

SNPB

N / A for Pkg Type

-55 to 125

SE555FKB

Samples

SE555JG

ACTIVE

CDIP

JG

8

50

Non-RoHS& Green

SNPB

N / A for Pkg Type

-55 to 125

SE555JG

Samples

SE555JGB

ACTIVE

CDIP

JG

8

50

Non-RoHS& Green

SNPB

N / A for Pkg Type

-55 to 125

SE555JGB

Samples

SE555P

ACTIVE

PDIP

P

8

50

RoHS & Green

NIPDAUN / A for Pkg Type

-55 to 125

SE555P

Samples(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 2

PACKAGE OPTION ADDENDUM
www.ti.com

18-Sep-2024

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SE555, SE555M :• Catalog : SE555• Military : SE555M• Space : SE555-SP, SE555-SP
NOTE: Qualified Version Definitions:• Catalog - TI's standard catalog product• Military - QML certified for Military and Defense Applications• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 3

PACKAGE MATERIALS INFORMATION
www.ti.com

25-Sep-2024

TAPE AND REEL INFORMATIONREEL DIMENSIONSTAPE DIMENSIONS
K0

P1

B0 W
Reel
DiameterCavity
A0
B0
K0
W
P1

A0

Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers

Reel Width (W1)QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes

Q1

Q2

Q1

Q2

Q3

Q4

Q3

Q4

User Direction of Feed

Pocket Quadrants*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

NA555DR

SOIC

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)

D

8

2500

330.0

12.4

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

6.4

5.2

2.1

8.0

12.0

Q1

NE555DR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

NE555PSR

SO

PS

8

2000

330.0

16.4

8.35

6.6

2.4

12.0

16.0

Q1

NE555PWR

TSSOP

PW

8

2000

330.0

12.4

7.0

3.6

1.6

8.0

12.0

Q1

SA555DR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

SE555DR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

SE555DRG4

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

25-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)

W

L

H

*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)NA555DR

SOIC

D

8

2500

353.0

353.0

32.0

NE555DR

SOIC

D

8

2500

353.0

353.0

32.0

NE555PSR

SO

PS

8

2000

356.0

356.0

35.0

NE555PWR

TSSOP

PW

8

2000

356.0

356.0

35.0

SA555DR

SOIC

D

8

2500

353.0

353.0

32.0

SE555DR

SOIC

D

8

2500

350.0

350.0

43.0

SE555DRG4

SOIC

D

8

2500

350.0

350.0

43.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

25-Sep-2024

TUBE
T - TubeheightL - Tube length

W - Tubewidth

B - Alignment groove width*All dimensions are nominal

DevicePackage Name

Package Type

Pins

SPQ

L (mm)W (mm)

T (µm)B (mm)

NA555PPPDIP

8NA555P

P

PDIP

8

50

506

13.97

11230

4.32

50

506.1

9

600

NA555PE4

P

PDIP

5.4

8

50

506

13.97

11230

4.32

NE555PP

NE555P

P

PDIP

8

50

506

13.97

11230

4.32

PDIP

8

50

506.1

9

600

5.4

NE555PE4
NE555PS

P

PDIP

8

50

506

13.97

11230

4.32

PS

SOP

8

80

530

10.5

4000

SA555P

4.1

P

PDIP

8

50

506

13.97

11230

4.32

SE555FKB

FK

LCCC

20

55

506.98

12.06

2030

NA

SE555P

P

PDIP

8

50

506

13.97

11230

4.32

Pack Materials-Page 3

GENERIC PACKAGE VIEW

FK 20

LCCC - 2.03 mm max height
LEADLESS CERAMIC CHIP CARRIER

8.89 x 8.89, 1.27 mm pitch

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

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PACKAGE OUTLINE

D0008ASOIC - 1.75 mm max height
SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUITCSEATING PLANE.228-.244 TYP[5.80-6.19]
A.004 [0.1] C

PIN 1 ID AREA
6X .050[1.27]
8

1

2X
.150
[3.81].189-.197[4.81-5.00]
NOTE 3

4X (0 -15 )4
5
B

8X .012-.020[0.31-0.51].010 [0.25]
C A B.150-.157[3.81-3.98]
NOTE 4.069 MAX[1.75].005-.010 TYP[0.13-0.25]

4X (0 -15 )SEE DETAIL A.010[0.25].004-.010[0.11-0.25]

0 -8.016-.050[0.41-1.27]

DETAIL A(.041)[1.04]TYPICAL

4214825/C 02/2019

NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

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EXAMPLE BOARD LAYOUT

D0008ASOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )[1.55]SYMM

SEE
DETAILS

1
8
8X (.024)[0.6]

6X (.050 )[1.27]

SYMM

5

4(R.002 ) TYP[0.05](.213)[5.4]

LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:8X

METAL

SOLDER MASKOPENINGEXPOSED
METAL.0028 MAX
[0.07]ALL AROUNDSOLDER MASKOPENINGMETAL UNDERSOLDER MASKEXPOSED
METAL.0028 MIN
[0.07]ALL AROUNDSOLDER MASKDEFINEDNON SOLDER MASKDEFINEDSOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

D0008ASOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )[1.55]SYMM
1
88X (.024)[0.6]

6X (.050 )[1.27]

SYMM

5

4(R.002 ) TYP[0.05](.213)[5.4]

SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCILSCALE:8X

4214825/C 02/2019

NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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PACKAGE OUTLINE

PW0008ATSSOP - 1.2 mm max height
SCALE 2.800

SMALL OUTLINE PACKAGE

C
6.6
TYP
6.2

SEATING PLANE

PIN 1 ID
AREA

A

0.1 C
6X 0.65

8

1
3.1
2.9
NOTE 3

2X
1.95
4

5
B

4.5
4.3
NOTE 4

SEE DETAIL A

8X

0.30
0.19
0.1

C A

1.2 MAXB(0.15) TYP

0.25
GAGE PLANE

0 -8

0.15
0.05

0.75
0.50

DETAIL A
TYPICAL

4221848/A 02/2015

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.

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EXAMPLE BOARD LAYOUT

PW0008ATSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)

8X (0.45)

SYMM

1
8

(R0.05)TYP
SYMM

6X (0.65)

5

4
(5.8)

LAND PATTERN EXAMPLESCALE:10X

SOLDER MASKOPENINGMETALSOLDER MASKOPENINGMETAL UNDERSOLDER MASK

0.05 MAXALL AROUND

0.05 MIN
ALL AROUNDSOLDER MASKDEFINEDNON SOLDER MASKDEFINEDSOLDER MASK DETAILSNOT TO SCALE

4221848/A 02/2015

NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGNPW0008ATSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)
8X (0.45)

SYMM(R0.05) TYP

1
8
SYMM

6X (0.65)

5

4
(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCILSCALE:10X

4221848/A 02/2015

NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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PACKAGE OUTLINE

JG0008A

CDIP - 5.08 mm max height
CERAMIC DUAL IN-LINE PACKAGE

A

7.11
6.22

B

1.60
0.38

6X 2.54

10.16
9.00

4X

1.65
1.14

4X (0.94)

8X
0.51
MIN

0.58
0.38
0.25 C A B

5.08 MAX

7.87
7.37

0.36
TYP
0.20

3.30
MIN

SEATING PLANE
C

0 -15 TYP

4230036/A 09/2023

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package can be hermetically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification.
5. Falls within MIL STD 1835 GDIP1-T8

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EXAMPLE BOARD LAYOUT

JG0008A

CDIP - 5.08 mm max height
CERAMIC DUAL IN-LINE PACKAGE(7.62)
0.05 MAXALL AROUND
TYP
1

6X (2.54)

8

(1.6)

(R0.05) TYP

SYMM
7X ( 1.6)

8X ( 1)
THRU

METAL
TYP
SOLDER MASKOPENING
TYP

5

4

SYMM

LAND PATTERN EXAMPLENON SOLDER MASK DEFINEDSCALE: 9X

4230036/A 09/2023

www.ti.com

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