Self-Service

Model Generator(SSPMG)
User Guide

Public Information© onsemi 2024

Outline of User Guide

2

1

Introduction to Self-Service PLECS Model Generator:
What is it and What are the benefits

2

Step by Step Tool Flow3

Deploying PLECS Models in Elite Power Simulator and
PLECS Stand Alone

Public Information© onsemi 2024

Outline of User Guide

3

1

Introduction to Self-Service PLECS Model Generator:
What is it and What are the benefits

2

Step by Step Tool Flow3

Deploying PLECS Models in Elite Power Simulator and
PLECS Stand Alone

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PLECS Basics• PLECS is a system level simulator that facilitates the modeling and simulation ofcomplete systems with optimized device models for maximum speed and accuracy.
PLECS is not a SPICE-based circuit simulator, where the focus is on low-level behavior of
circuit components .
• Power transistors are treated as simple switches that can be easily configured todemonstrate losses associated with conduction and switching transitions.
• The PLECS models, referred to as “thermal models”, are composed of lookup tables forconduction and switching losses, along with a thermal chain in the form of a Cauer or
Foster equivalent network.
• During simulation, PLECS interpolates and/or extrapolates using the loss tables to get thebias point conduction and switching losses for the circuit operation. Access the onsemi
Elite Power Simulator powered bywww.onsemi.com/elite-power-simulator
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onsemi’s State-of-the-Art PLECS Models:• Typical industry PLECS models are composed of measurement based loss tables that areconsistent with datasheets provided by the manufacturer.
There are four major problems with this approach:1.

The switching energy loss data is dependent on the parasitics of the measurements set ups and circuits.

2.

The conduction and switching energy loss data is limited and thus is often not dense enough to ensure
accurate interpolation and minimal extrapolation by PLECS.

3.

The loss data is based on nominal semiconductor process conditions only.

4.

The switching energy loss data comes from datasheet double pulse generated loss data. This means thePLECS models are only valid for hard switching topology simulation. The models are highly inaccurate if
used in soft switching topology simulation.

• onsemi’s Self-Service PLECS Model Generator (SSPMG) provides solutions to all four problems.
• Ultimate power is delivered to the user to build PLECS models tailored for the user’s application.
Unleash the power here: www.onsemi.com/self-plecs-generator
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Measurement Parasitics Influence on Switching Performance
Example Datasheet
Switching Schematic with Parastics

Customer Application

Parameter

Switching
LossParameter

Switching
Loss

Eon [uJ]490

Eon [uJ]

415

Eoff [uJ]221

Eoff [uJ]231

Etotal [uJ]711

Etotal [uJ]646

• Crucial to understand that the lab test circuit’s
passives, parasitics, gate driver performance, etc. allaffect losses.
• Where does this leave the user for a PLECS model?
The user application will surely have a different
environment than any of the component supplier’s
lab and board setups.
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Loss Table Density and Limits Influence Results• Datasheet data is often not dense enough to ensure
accurate interpolation by PLECS in nonlinear
environments.
• Datasheet data limits often do not bound the entireoperating range causing highly inaccurate extrapolation
by PLECS.

TypicalDatasheet

SSPMG

Interpolation
with small data set

7

Extrapolation
with small data set

Interpolation &Extrapolation
with large data set
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Corner PLECS Models• Conventional PLECS models based on measurements are only valid for the typical or nominal process case inmanufacturing. onsemi has developed accurate corner PLECS models based on real manufacturing distribution.
• Physics dictates that worst case conduction and switching losses do not happen simultaneously for example.
• Depending on the application, the influence of conduction and switching energy losses on the overall system
performance will vary. The onsemi corner PLECS models provide the user the flexibility to investigate the entire
correlated space.
• Corner models currently available for EliteSiC and T10M 40V products. More T10 and FS7 IGBT corner models
are coming soon.
• Accurate corner and statistical modeling covered in detail in− SiC MOSFET Corner and Statistical SPICE Model Generation – Proceeding of International Symposium on Power
Semiconductor Devices and ICs (ISPSD), pp. 154-147, September 2020
Process Condition

RDSon, Vth, BV

Capacitance,Device RG

Conduction
Loss

Switching Energy
LossNominalNominalNominalNominalBest Case Conduction Loss, Worst Case
Switching Loss

Low

HighLowHigh

Worst Case Conduction Loss, Best Case
Switching Loss

HighLow

HighLow

NominalPublic Information© onsemi 2024

onsemi provides industry first Full
Switching PLECS models valid for hard,
soft, and partial soft switching including
Synchronous Rectifier Operations. Example
Full Switching topologies include DC-DC
LLC and CLLC Resonant, Dual ActiveBridge, and Phase Shifted Full Bridge.
*The Double Pulse Test is NOT representative of SoftSwitching. Using double pulse switching energy losses in thesimulation of a Soft Switching Topology is highly inaccurate.
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Soft Switching

Full Switching Simulation*

Hard Switching

Full Switching Energy Losses

Access SSPMG with MYON Account
MYON
Login

MyON is required to use the SSPMG

Returning UserFirst Time User

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Outline of User Guide

11

1

Introduction to Self-Service PLECS Model Generator:
What is it and What are the benefits

2

Step by Step Tool Flow3

Deploying PLECS Models in Elite Power Simulator andPLECS Stand Alone

Public Information© onsemi 2024

Getting Started
Go to landing pagewww.onsemi.com/self-plecs-generator
and select Generate Model OR find
SSPMG link on product pages.

Link to Elite Power Simulator

User Guide andDetailed Application Note
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Step 1: Select Product

Discrete or Module
Device Type* & Technology Generation
Blocking Voltage
Product list filtered based on previous choices*EliteSiC MOSFETs, Field Stop 7 (FS7) IGBTs, and T10 Si MOSFETs are supported.
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Step 2: Set Process Condition

Corner models currently only available
for EliteSiC and T10M 40V products.
More T10 Si MOSFET and FS7 IGBT
corner models are coming soon.

Process Condition

RDSon, Vth, BV

Capacitance, Device
RG

Conduction
Loss

Switching Energy Loss

NominalNominalNominalNominalBest Case Conduction Loss, Worst
Case Switching Loss

Low

HighLowHigh

Worst Case Conduction Loss, Best
Case Switching Loss

HighLow

HighLow

Nominal14

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Step 3: Set Switching Type

Regular Hard Switching or Full Switching including transition from Hard to Soft

Option for Hard Switching:
Half bridge or quarter bridge with ideal diode or EliteSiC Schottky diode• Choose the switching type based on the intended application or topology.
• If hard switching chosen, user has choice for high side device to be in half bridge configuration or quarter bridge with ideal diodeor EliteSiC Schottky diode on the high side.
• Full Switching is valid for hard, soft, and partial soft switching. Example Full Switching topologies include DC-DC LLC and CLLC
Resonant, Dual Active Bridge, and Phase Shifted Full Bridge.
• Subsequent step 4 “Characteristics” change slightly based on the Switching Type.
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Step 3: Quarter Bridge with EliteSiC Schottky Diode

Technology Generation
Blocking Voltage
Product list filtered based on previous choices• User should make sure EliteSiC Schottky diode current rating is suitable to switch with the low side EliteSiC MOSFET.
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Step 4: Set Characteristics (Hard Switching)• Drain current can be in 1st and/or
3rd quadrant, so positive and/ornegative.

Descriptive fields guide user.

• Diode Current is for diode forward
conduction mode at the low VGS
condition. Values are given inabsolute scale.
• Default Gate Drive conditions are
the recommended values. User
can change Low and High VGS
within a specified range thatensures proper device operation.
• If(Stop-Start)/(Step Size) != Integer
then last point=Stop. Example:
Start=1 Stop=9 Step Size=3
Simulated points are: 1 4 7 917

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Step 4: Set Characteristics (Full-Soft Switching)• Full Switching Changes:− Drain current is 1st and 3rd quadrant,
so positive and negative when aswitching event happens• Full Switching Additions:− dI/dt: in the resonant inductor when theswitching event happens. This dI/dt isdirectly linked to the resonant inductor
voltage by the Faraday’s law ofinduction E=L*di/dt. “didt” is a PLECS
circuit parameter passed into thePLECS model to evaluate the losses insoft switching.
− Max Delay: maximum dead timeallowed between high side and low sideswitches for the resonant transition tooccur− Resonant Inductor

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Step 5: Circuit Schematic (Half Bridge Discrete)
Descriptive fields guide user• Table of parameters
matches circuit schematic.
• Default parameters aregenerally 0, allowing user tojust enter needed values.
• Min and Max GateResistance parameter
facilitate RG scaling in the
PLECS model.
• Gate drive signal can bemodeled through Rdriver,
TF, and TR.

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Step 5: Circuit Schematic (Quarter Bridge Discrete)• High side choice can be:− Ideal diode with capacitance=0− EliteSiC Schottky diode• Parasitic output capacitor is
split into high side (COH) andlow side (COL).

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Step 5: Circuit Schematic (Half Bridge Module)• All module parasitics areincluded in power module
SPICE model.
• Remaining parameters are
the same as discrete version.

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Step 5: Circuit Parameters – Full list

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Step 5 : Input Filter Parameters

LFx (with RLFx as seriesresistance) is the PCB leakage
inductance or a discrete
filtering inductor.
The filter capacitor or
decoupling capacitor CF
includes ESL and ESR
parameters.

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Step 5 : Switching Loop Leakage Inductances

The switching loop inductance(in between the decoupling
capacitor and the switchingcell) is represented by Lloopx(with Rloopx as seriesresistance) on the positive andnegative branch.

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Step 5 : Interconnections leakage inductances

Drain and Source
interconnections can also bemodeled by inductances (withseries resistances). There are 4
in total for the two switching
devices.

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Step 5 : Load parameters

In hard switching. results areindependent of switching or
load inductor. Its value is linked
to current value and time.
However, the inductor quality orperformances can be definedby its equivalent series
resistance and its equivalentparallel parasitic capacitor.

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Step 5 : Input Filter parameters

A current sense measurement
based on a shunt resistor canbe included in the loop in
various place :- in switching device Drain,- in switching device Source- in switching inductor
If the shunt is located in either
the device drain or source, theinterconnection series
resistance can be increasedaccordingly.

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Step 5 : Gate Drive Circuit parameters

The gate drive circuit includes
two parasitic inductances LGxand LKx for interconnection
and split gate resistors (RGonand RGoff) to control turn-on
and turn-off speed.

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Step 5 : Driver extra parameters

The driver is model by a pulse
voltage source with Minimumand Maximum (ON and Off)
voltage defined in Step 4.
In Step 5, the user defines theRise (TR) and Fall (TF) times.
The user can also give thedriver internal resistance valueRdriver.

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Step 5 : EMI Damping parameters

For EMI reduction, twodamping circuits can be added.
Between Drain to Source, aparallel capacitor linearizes theswitching device output
capacitor. A snubber circuit canalso be added.
Between Gate and (Kelvin)
Source, an R-C series damping
network will damp the Miller
effect ringing.
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Step 6: Submit Request• From the 5 Circuit
Schematic Tab, once all
circuit parameters areentered, Submit Request
button becomes active.
• User clicks on Submit
Request and is broughtto the Request Details
page• Requests take several
minutes to complete
depending on the densityof the input
characteristics.
• Modules take longer due
to higher complexity
compared to discretes.

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Step 7: Review Request Details Page
• The Request Details page
provides user with− Details of the input
parameters

PLECS Model Download− Plots of the simulation results− Status field:
 Pending – simulation in queue Running – simulation running Done – simulation completed− PLECS Model (XML File)download− Recall button: Enable users
to recall the current request
into a new request wherechanges can be made before
submitting the new request.
The current request ismaintained.

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Step 7: Review Request Details Page – Plots Tab• The Plots tab provides users
with multiple plots
representing the data in theXML file.
− Eoff, Eon, Err vs. ID (current)for different temperatures andvoltage @default RG− Eoff at negative ID isessentially Err.
− Eoff, Eon, Err vs. RG fordifferent currents @maximum
temperature and voltage.
− Transistor conduction plot
VDSon vs. ID for differenttemperatures.
− Diode conduction plot Vsd vs.
ID for different temperatures.

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Example Full Switching Model Results

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Example Full Switching Model Results

Negative Eon
duringSoftSwitching

Hard-Switching
PartialSoft-Switching
Soft-Switching
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Example Full Switching Model Results: 3D View
• Eoff• Eon
Negative Eon
duringSoft-Switching

Main Switch
Synchronous Rectifier
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APEC 2024

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Step 8: Review Requests Summary Page
Sort and Search these fields
Note* User will only see their requests

Download
XML Model

Click on request #to access
Request Details Page

Recall request intonew request

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FAQ: Common Causes of SSPMG Failed Runs
• Very small switching current step (<1A) causing very long simulation times while not really improving theaccuracy of the table model.
• Switching currents too close to 0 (<1A): In the EOFF extraction, 1% ID point by IEC standard will yield very small
curents which can cause extraction errors due to leakage. For example, when ID=0.1A,the 1%ID will be only
1mA,which could be less than the leakage for some high temparture conditions.
• Switching load voltages are too low. Very low Vload can cause errors in the EON extraction, in which we need tomeasure 3%VDS by IEC standard.
• Switching load voltage too close to the device breakdown voltage BV can cause issues if there is overshoot ofVDS in turn off. If the overshoot is higher than BV, the breakdown current will generate strange behaviors.
• For full switching, users put very small negative current. For these inputs, there would be only 1 or 2 points fornegative current yielding poor results. There should be at least 3 points in the negative current range.
− Iswitch_min=-1

Iswitch_max=50 Iswitch_step=5− Iswitch_min=-10 Iswitch_max=50 Iswitch_step=5• Very large dI/dt could cause convergence issues or very strange behavior.
• In general check ranges of parasitics. Unreasonable large inductors, resistors and capacitors can cause issues.
For example, large CLOAD/CO could cause very long turn on/off edge.
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Outline of User Guide

39

1

Introduction to Self-Service PLECS Model Generator:
What is it and What are the benefits

2

Step by Step Tool Flow3

Deploying PLECS Models in Elite Power Simulator andPLECS Stand Alone

Public Information© onsemi 2024

Deploying SSPMG PLECS Models in the Elite Power Simulator
onsemi power products inyour own environment

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Application/Systemsimulation withonsemi power products

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Load SSPMG models into Elite Power Simulator
In Device Configuration Tab, user can select to upload SSPMG generated model

Browse for SSPMG XML file41

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Load SSPMG models into PLECS Stand Alone• First download PLECS models from Elite Power Simulator
and follow instructions in “Install.txt” file.
− To install the onsemi SiC library components and corresponding
thermal descriptions (XML files), simply add this directory(containing the "onsemiThermalDescriptions/" folder,"onsemiComponentLibrary_public.plecs" PLECS model, and"info.xml" file) into the list of thermal description search paths in
the Thermal tab of the PLECS Preferences window. Click theRefresh button on the left side of the list and click OK to load theonsemi files into PLECS. Then a new entry in the PLECS LibraryBrowser should appear "onsemi Block Library" containing several
components that can be dragged into your own circuit models
and directly be used with the provided thermal descriptions.

• Create subfolder sspmg here and place SSPMG XML files inthis directory. Note folder can be any name.

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Load SSPMG models into PLECS Stand Alone• Place an onsemi SiC-Si MOSFET or Si IGBT in PLECS schematic.
• Double click MOSFET/IGBT symbol and browse for SSPMG XML file.

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Load SSPMG models into PLECS Stand Alone• Review XML data under Window →Thermal Library Browser• Run simulation

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Questions?
Have questions, comments, or need support with your Self-Service PLECS Model Generator
needs? We’re here to help! Write us an email at sspmg@onsemi.com.
• Self-Service PLECS Model Generator:
www.onsemi.com/self-plecs-generator• Elite Power Simulator:
www.onsemi.com/elite-power-simulator

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