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AND9764/D
NCV7685 I2C Programming
Guidewww.onsemi.com

APPLICATION NOTEINTRODUCTION AND DOCUMENT SCOPE
This document deals with the recommendation how tocontrol the NCV7685 devices using I2C protocol and how toconfigure OTPs.
PREREQUISITES
The following guidelines are required:• VDD supply has to be in range between 3.15 V to5.5 V.
• Proper selection of the Pull−up resistors in respect withI2C speed, VDD supply voltage and bus capacitance.
• For Hard coding and OTP register access, the ISET pin
has to be put to high.
• To Burn OTP, the VS supply has to be > 13 V.
• Every I2C message is protected by repeating address
safety mechanism.
• Additional CRC may be activated based on the ERREN
flag.

Figure 1. Rp(min) Versus VDD Voltage

PULL UP RESISTOR SELECTION
Open drain I2C communication protocol needs pull−up
resistors for communication. The pull−up resistors keep theI2C pins in high while there is no communication on the bus.
The selection of the resistor value depends on bus
capacitance, VDD supply, I2C speed and power
consumption.
The equations for 400 kbps:Rp(min) +VDD * 0.4
W0.003Rp(max) +300ns
0.8473 @ C B

W© Semiconductor Components Industries, LLC, 2018

May, 2020 − Rev. 2(eq. 1)Figure 2. Rp (max) Versus Bus Capacity

For VDD = 3.3 V and bus capacity 100 pF the Pull−up
resistors should be in range of 0.98 kW to 3.45 kW(eq. 2)

1

Publication Order Number:AND9764/D

AND9764/D
FORMAT OF THE I2C FRAMES
Writing and reading data to the NCV7685 drivers uses asimple protocol: the address is written, and then data aretransferred until the end of the message.
A single message writes to the NCV7685 driver. After theSTART command, the master sends the chip’s bus 7−bit
address with the direction bit clear (write), then sends therepeated address data byte and then sends the message
identifier (ID) followed with data bytes to be written
followed by a STOP. Every transmitted byte is
acknowledged by slave device.

To read the data from NCV7685 driver a combined
message has to be used. After a START, the master firstwrites chip’s bus 7−bit address with the direction bit clear(write) and then the repeated address 8−bit followed by ID
message. Then the (repeated) START is send and the chip’sbus 7−bit address with the direction bit set (read). The
NCV7685 will then respond with the data bytes which areacknowledged except the last byte and then the stop
condition terminate the communication.

’0’ = Write’1’ = ReadReadS

NCV7685 address 0

A

Repeated address AID

A

Read + CRC

S

NCV7685 address 0A

Repeated address AIDASr

NCV7685 address 1CRCASrN bytes +acknowledge

A

Data

NCV7685 address 1’0’ = Write

Last data byte
Not acknowledge

A/A* PA

DataA

CRC

A*N bytes +acknowledge’1’ = Read
S = Start conditionSr = Repeated start condition
P = Stop condition
A = Acknowledge
A* = Not acknowledge

From master to NCV7685
From NCV7685 to masterFigure 3. Format of the I2C Read Frames with Repeated Start Condition’1’ = ReadReadS

NCV7685 address 0

A

Repeated address AID

A

Read + CRC

S

NCV7685 address 0

A

Repeated address AID

ASP
CRC

NCV7685 address 1AS

N bytes +acknowledge

AData

A/A* P

NCV7685 address 1’0’ = Write

A’1’ = Read
From master to NCV7685
From NCV7685 to master

Last data byte
Not acknowledge

Data

N bytes +acknowledge

S = Start conditionSr = Repeated start condition
P = Stop condition
A = Acknowledge
A* = Not acknowledge

Figure 4. Format of the I2C Read Frames with Stop and Start Condition

Write

S

NCV7685 address 0

A Repeated address AID

A

Data

A

Write + CRC

S

NCV7685 address 0

A Repeated address AID

AData

A

N bytes +acknowledge’0’ = Write
From master to NCV7685
From NCV7685 to masterS = Start condition
P = Stop condition
A = Acknowledge
A* = Not acknowledge

Figure 5. Format of the I2C Write Frames

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2PCRCAA

PCRC

A*PP

AND9764/D
NCV7685 I2C ADDRESSING
The NCV7685 driver is using 7−bit I2C address. Up to 32
NCV7685 devices can be addressed using the 5−bits
ADD[4:0] OTP register. The remaining two bits of the I2C
address are fixed: ADD[6:5] = 11.

The default I2C address configuration of the non−zapped
device is 0b1100000 = 0x60 + R/W flag which is
automatically generated by mC.

Table 1. THE 1ST BYTE STRUCTURE OF I2C DEVICE ADDRESSA6A5A4A3A2A1A0R/W

11000001/0

After first address byte which is automatically send byMaster I2C device, the repeated address data byte has to besend. The second I2C address data byte is safety mechanism

to improve the immunity of the system. This byte contains
8−bits of the data where the address (ADD[4:0]) and W = 0flag is included in the data byte.

Table 2. THE 2ND BYTE STRUCTURE OF I2C DEVICE ADDRESS
D7D6D5D4D3D2

D1D011000000This second byte is send as regular data content. Thedefault value for not zapped device is 0xC0. The list of theall possible combinations is mentioned in the Table 3.
Table 3. LIST OF THE I2C DEVICE ADDRESS
5−bit

7−bit

8−bit

ADD [4:0] Device#

1st I2C Address byte

2nd I2C Address byte

00x60

0xC0

10x61

0xC2

20x62

0xC430x63

0xC640x64

0xC850x65

0xCA

60x66

0xCC70x67

0xCE

80x68

0xD0

90x69

0xD2

100x6A0xD4

110x6B

0xD6

120x6C

0xD8

130x6D

0xDA

140x6E

0xDC

150x6F

0xDE

160x700xE0170x710xE2180x720xE4

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3AND9764/D
Table 3. LIST OF THE I2C DEVICE ADDRESS
5−bit

7−bit

8−bit

190x730xE6200x740xE8

210x750xEA

220x760xEC

230x770xEE

240x780xF0

250x790xF2

260x7A

0xF4

270x7B

0xF6

280x7C

0xF8

290x7D

0xFA

300x7E0xFC

310x7F0xFE

I2C COMMUNICATIONThis second byte is send as regular data content. The
volatile registers can be accessed by sending appropriate ID
message. The list of the addressing identifiers is describedin the datasheet.

CRC ERROR DETECTION ALGORITHM
The CRC protection is turned off by default. It can beenabled by activation of the OTP ERREN bit (ERREN = 1).
The every I2C byte including both addresses with R/W flag
are calculated using CRC8 algorithms. The CRC
polynomial is following: x8 + x5 + x3 + x2 + x + 1.

I2C REGISTER READINGThe volatile registers: I2C Status, Fault Status, and I2C
Channel status can be read using dedicated ID messages.
The Hard Coding and OTP registers can be read using
ID_READ_OTP message.
To read the I2C data from the NCV7685, the 7−bit address
has to be sent with Write Flag. After repeated address theID_STATUS, ID_FAULT or ID_READALL is send. Either
repeated start or stop condition followed by start condition
can be used for second part of the I2C communication. The
7−bit address with Read flag has to be transmitted before
slave device transmit all requested data bytes. The graphic
representation of the I2C reading is shown in Figure 3 andFigure 4.

Table 4. CRC DETAILED PARAMETERS
Parameter

Value

CRC Width

CRC−8

Polynomial

0x2F

Initial Value

0xFF

Final Xor Value

0x00

Input Reflected

noResult Reflected

no

CRC Calculation Reference
Example of the CRC used in the I2C message withI2C_CONF byte = 0xCFFF and with I2C address 0x60
(0xC0) is 0x2E.

Table 5. EXAMPLE OF THE I2C MESSAGE WITH CRC8 PROTECTION
Device Address & R/W bitRepeated addressID

I2C CONF [15:8]

I2C CONF [7:0]

CRC

0xC0

0xC0

0x00

0xCF

0xFF

0x2E

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4

AND9764/D
OTP PROGRAMMING
To access the Hardcoding and OTP registers the ISET pin
has to be put to high; otherwise the slave device will not
respond on these three OTP I2C messages (ID_SET_OTP,
ID_LOCK_OTP and ID_READ_OTP).
The I2C address, Open Load detection modes, CRC
activation, silicon ID device and channel configuration canbe read/(write) by OTP messages.
The ISET pin has to be externally pulled high to thevoltage between 2.5 V and 3.3 V otherwise the driver will
not accept the I2C message.
The main intention of forcing 2.5 V – 3.3 V to the ISET
pin is protection against entering to the programming mode
during the normal operation. And this technique is also usedas chip select functionality for the End−Of−Line OTP
programming procedure.
Three sets of the commands are available to access theOTP registers: ID_SET_OTP (W), ID_LOCK_OTP (W)and ID_READ_OTP(R).
The ID_SET_OTP message will write the information
into shadow registers without affecting the OTP registers.
The information in registers is lost when both power
supplies (VDD and VS) are turned off.
The ID_LOCK_OTP message will zap the OTPs. No
further change will be possible. It is necessary to have VS
supply voltage higher than 13 V to ensure proper zapping
procedure.

Please note that as soon as the ID_SET_OTP or
ID_LOCK_OTP is processed, all other I2C messages haveto be sent with respect to the new I2C address or CRC
activation setting.
REQUIRED TIME DELAY FOR OTP ZAPPING
As soon as the ID_LOCK_OTP message is received, theI2C acknowledge is immediately sent out to the MCU.
However, the internal circuitries still requires 500 ms timedelay to complete the OTP zapping of one OTP bit.
Therefore, no I2C confirmation is send. The number of OTP
bits that are zapped corresponds with each change from thedefault values. It is needed 16.5 ms in total to successfully
finish the zapping sequence of all 32 customer bits + one
internal bit. The verification of the OTP banks can be doneby readout of the ID_READ_OTP I2C message after
zapping delay.
CHANGING THE OTP ADDRESS ON THE SAMEI2C BUS
Every non−zapped device has the same I2C address. Tochange the address, the ID_SET_OTP or ID_LOCK_OTP
message with appropriate content has to be sent. It isnecessary to put the ISET pin to high, to address appropriate
device. The graphic representation of the End−of−Line OTP
programming is shown in Figure 6.

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5AND9764/D
Default configuration of non zapped devices
VDD
VSVS

VS

VDD

NCV7685

NCV7685

ISETI 2 C address = 0x60
S
DA

MASTER
MCU

1VS

VDD

NCV7685ISETI 2 C address = 0x60
S
DA

SCL

VDD
ISET

I 2 C address = 0x60

SCL

SDASCLSDA
SCLAll non-zapped devices will respond on the same address (0x60) to read/write volatile registers
Access to the OTP and hardcoding registers is denied.

Changing the I2 C address of the second device
VDD
VS

VS

VS>13V

VDD

NCV7685

NCV7685ISET

2MASTER
MCU

2SDA
SCL

ISET

2I C address = 0x60
S
DA

Apply
Externalvoltage

VDD

I C address = 0x60
S
DAS
CL

VS

VDD

NCV76852.5V− 3.3VISET

2I C address = 0x60

SCLSDASCL

Send I 2 C message at address 0x60.
The ID_SET_OTP (ID _LOCK_OTP) message which will contain data ADD[4:0] = 1 will beprocessed only by second device because of ISET pin is in range of 2.5 V – 3.3 V
Other devices will ignore this ID_SET_OTP (ID _LOCK_OTP) message
After this ID_SET_OTP message, the second device will communicate at I2 C address = 0x61
Changing the I 2C address of the third device

VDD
VSVSVSVDDNCV7685

NCV7685ISET

2MASTER
MCU

3SDA
SCL

I C address = 0x61
S
DASCL

ApplyExternalvoltage

VDD

NCV7685ISET

2I C address = 0x60
SDA

VS>13V

VDD

ISET

2I C address = 0x60

SCL

S
DA

SC
L

Send I2C message at address 0x60.
The ID_SET_OTP (ID _LOCK_OTP) message which will contain data ADD[4:0] = 2 will beprocessed only by third device because of ISET pin is in range of 2.5 V – 3.3 V
First device will ignore this ID_SET_OTP (ID _LOCK_OTP) message
After this ID_SET_OTP message, the third device will communicate at I 2 C address = 0x62
Devices after End-Of -Line configuration

VDD
VS

VDD

VS

NCV7685

NCV7685

ISET

24MASTER
MCU
SDA
SCL

VS

I C address = 0x61
S
DA

SCL

2Volatile registers can be read/write using unique I 2C address.
Access to the Hardcoding / OTP Registers is not possible because ISET pin is not put Highwww.onsemi.com
6

ISET

I C address = 0x62

SCL

Figure 6. Changing OTP Address

VDD

NCV7685ISET

2I C address = 0x60SDAVDDVSSDASCL

2.5V− 3.3V

AND9764/DON Semiconductor andare trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are notdesigned, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, andexpenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if suchclaim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
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