User's Guide
SLAU236A – November 2007 – Revised October 2008

DAC5681/81z/82z EVM

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Contents
Overview ...................................................................................................................... 3
1.1
Purpose .............................................................................................................. 3
1.2
EVM Basic Functions............................................................................................... 3
1.3
Power Requirements ............................................................................................... 3
Software Installation ......................................................................................................... 4
2.1
Minimum Requirements ............................................................................................ 4
2.2
Installing the EVM Control Software ............................................................................. 4
2.3
Installing the DAC5681/81z/82z EVM Instrument Drivers ..................................................... 5
2.4
Installing the DAC5681/81z/82z EVM Hardware ............................................................... 5
DAC5681/81z/82z EVM Description ...................................................................................... 6
3.1
Texas Instruments Components on the DAC5681/81z/82z EVM ............................................ 6
DAC5681/81Z/82z EVM Hardware Description .......................................................................... 7
4.1
Jumper Settings ..................................................................................................... 7
4.2
Input/Output Connectors ........................................................................................... 8
4.3
USB Interface ....................................................................................................... 8
4.4Power Management ................................................................................................ 8
4.5
Input Connector .................................................................................................... 8
4.6
Clock Configuration ................................................................................................. 9
4.7
Output Configurations .............................................................................................. 9
4.8
Reference Operation .............................................................................................. 11
DAC5681/81z/82z EVM Software ........................................................................................ 12
5.1
Software Functionality Overview ................................................................................ 12
5.2
EVM Home Area .................................................................................................. 13
5.3
DAC Register Configuration and Block Diagram .............................................................. 15
5.4
CDCM7005 Register Configuration ............................................................................. 17
5.5
TSW3100 Configuration and Pattern Generation ............................................................. 19
5.6
Help ................................................................................................................. 20
DAC5681/81z/82z Initial Power Up and Test ........................................................................... 21
6.1
Test Setup Block Diagram ....................................................................................... 21
6.2
Test Equipment .................................................................................................... 21
6.3
Calibration .......................................................................................................... 21
6.4
Typical Performance Measurements ........................................................................... 22
6.5
DAC5681/81z/82z Test Procedure.............................................................................. 23
PC Board Layouts, Bill of Materials and Schematics .................................................................. 24
7.1
Board Layouts ..................................................................................................... 24
7.2
Bill of Materials .................................................................................................... 34
7.3
Schematics ......................................................................................................... 36
List of Figures

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EVM Installation Wizard..................................................................................................... 4
Windows USB Driver Warning ............................................................................................. 5
Hardware Device Manager ................................................................................................. 5
Basic Radio System ......................................................................................................... 6

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DAC5682z Option Block Diagram ......................................................................................... 6
DAC5682Z DAC Output Resistor Configuration ....................................................................... 10
DAC5682z RF Output Resistor Configuration .......................................................................... 10
Response of Default Baseband Filter ................................................................................... 11
EVM Home Displaying EVM Status Settings ........................................................................... 13
DAC Block Diagram and Register Configuration Settings ............................................................ 15
The CDCM7005 and DAC5682 Register Configuration Settings .................................................... 17
TSW3100 Pattern Generator and DAC Register Configuration Settings .......................................... 19
DAC5682z EVM Driven by TSW3100 Pattern Generator............................................................. 21
DAC5681/81z/82z EVM Transformer Output With a Low IF at 30.72 MHz ........................................ 22
DAC5682z EVM output at RF LO + low IF of 30.72M (6 dB lower than DAC output) ............................ 23
Silkscreen (top) ............................................................................................................. 24
Layer 2 ....................................................................................................................... 25
Layer 3 ....................................................................................................................... 26
Layer 4 ....................................................................................................................... 27
Layer 5 ....................................................................................................................... 28
Layer 6 ....................................................................................................................... 29
Layer 7 ....................................................................................................................... 30
Layer 8 ....................................................................................................................... 31
Layer 9 ....................................................................................................................... 32
Screen (Bottom) ............................................................................................................ 33
List of Tables

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Jumper List ................................................................................................................... 7
Input and Output Connectors .............................................................................................. 8
Input Connector .............................................................................................................. 8
Software Main Menu Selections .......................................................................................... 12
Software Area Descriptions ............................................................................................... 12
EVM Home Software Functionality....................................................................................... 14
DAC Register Configuration Software Functionality ................................................................... 15
CDCM7005 Register Configuration Software Functionality........................................................... 18
TSW3100 Configuration and Pattern Generation Functionality ...................................................... 19

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1

Overview

1.1

PurposeThe DAC5681/81z/82z EVM provides a platform for evaluating the DAC5681, DAC5681z and DAC5682z
family of 16-bit, 1GSPS digital-to-analog converters (DAC) under various signal, reference, and supply
conditions. The evaluation module allows designers using the DAC5682z to analyze either atransformer-coupled output from the DAC or an RF-modulated output using Texas Instruments TRF3703
analog quadrature modulator. The DAC5681 and DAC5681z options only allow the use of atransformer-coupled output. Use this document with the EVM schematic diagram and the corresponding
device datasheet ( DAC5681 - SLLS864, DAC5681z - SLLS865A, and DAC5682z - SLLS853B ).

1.2

EVM Basic Functions
Digital inputs to the DAC can be provided with LVDS level signals up to 1 GSPS through a SEMTEKconnector compatible with various pattern generation solutions. The analog outputs from the DAC are
available via SMA connectors. Because of its flexible design the analog outputs of the DAC device can be
configured to drive a 50-Ω terminated cable using a 4:1 or 1:1 impedance ratio transformer, or
single-ended referred to AVDD. The EVM also allows for an option to use Texas Instrument’s TRF3703
analog quadrature modulator to mix the DAC outputs to RF. This option is only available when using the
DAC5682z.
The EVM also includes a Texas Instrument’s CDCM7005 clock distribution device to clock the system.
The CDCM7005 can be used in conjunction with an on-board VCXO for full PLL functionality or with an
external signal source in which case the CDCM7005 functions as a buffer.
Power connections to the EVM are via banana jack sockets. In addition to the internal bandgap reference
provided by the DAC devices, the EVM allows an external reference to be provided to the DAC.
The DAC5681/81z/82z EVM allows the user to program the DAC and CDCM7005 registers through a
USB port. The interface allows read and write access to all the DAC registers and write-only access to the
CDCM7005 registers.

1.3

Power Requirements
The DAC5681/81z/82z EVM requires 1.8-Vdc and 3.3-Vdc supplies for normal operation. An additional
5-Vdc supply is required to power up the TRF3703 for RF measurements.

1.3.1

Voltage Limits
CAUTION
Exceeding the maximum input voltages can damage EVM components.
Undervoltage may cause improper operation of some or all of the EVM
components.

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Software Installation
The DAC5681/81z/82z EVM comes with a software package that allows the user to configure the DAC
and CDCM7005 registers, save and load register settings to/from text files, and visualize the data paththrough the DAC. Communication with the EVM is achieved through a USB port on the host PC. Once thesoftware is installed, the GUI is accessible from Start > All Programs > Texas Instruments DACs >DAC5682z EVM Control.

2.1

Minimum Requirements
Before installing the software, verify that the PC meets the following requirements:•••

Microsoft Windows™ 2000 or later operating system
1024 x 768 screen resolution for optimal viewing
USB 1.1 or later compatible input port

Other configurations may work; however, they remain untested.

2.2

Installing the EVM Control Software
Double-click the setup.exe file located on the installation CD. The EVM Installation Wizard will open
(Figure 1).

Figure 1. EVM Installation Wizard

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2.3

Installing the DAC5681/81z/82z EVM Instrument Drivers
As part of the Install Wizard, the EVM instrument drivers are installed automatically. Because the USB
device driver is unsigned by Windows, the warning in Figure 2 appears. Press Continue Anyway tocomplete the installation.

Figure 2. Windows USB Driver Warning
To finalize the installation, the Installation Wizard asks the user to restart the computer. The system must
be rebooted prior to running the software.

2.4

Installing the DAC5681/81z/82z EVM Hardware
After installing the EVM control software and drivers, connect the DAC5681/81z/82z EVM to a spare USB
port of the host PC. If this is the first time connecting to the device, the Windows Found New Hardware
Wizard guides you through the final setup steps. If the Hardware Wizard does not start, ensure that thecable is connected properly.
Instruct the Hardware Wizard to find the software automatically. If Windows is unable to find the drivers
automatically, point it to the DAC5682 program folder. The default folder is C:\Program Files\Texas
Instruments\DAC5682z\DAC5682z Drivers. A warning indicating that the drivers are unsigned by Windows
appears. Press Continue Anyway to complete the setup.
To verify a complete installation, open Windows Hardware Device Manager and observe that the
DAC5682 EVM is listed under the USB controllers list as shown in Figure 2.

Figure 3. Hardware Device Manager

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DAC5681/81z/82z EVM Description
The DAC5681/81z/82z EVM provides a robust and flexible evaluation system for the 16-bit, 1GSPS
DAC5681/DAC5681z/DAC5682z DAC family. In addition to the DAC, the EVM includes a CDCM7005 forclock distribution and in the DAC5682z option a TRF3703 analog quadrature modulator path for RF
measurements. For a complete hardware description, consult the schematics and layout sections at theend of this guide. See the DAC5681, DAC5681z, DAC5682z, CDCM7005, and TRF3703 data sheets formore information on each device.

3.1

Texas Instruments Components on the DAC5681/81z/82z EVM
A basic radio system block diagram is shown in Figure 4. The dashed-line box illustrates where the EVM
fits in the system.

Figure 4. Basic Radio System
The block diagram of the DAC5682z EVM option is shown in Figure 5. As illustrated on the block diagram,the DAC5682z EVM option includes three Texas Instruments components that make the entire solution an
excellent choice for radio systems.

Figure 5. DAC5682z Option Block Diagram

3.1.1

DAC5681/81z/82z
The DAC5681/81z/82z is a family of high-performance, 16-bit, 1.0-GSPS DACs with wideband LVDS data
input and internal voltage reference. The family integrates a wideband LVDS port with on-chip termination.
An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control fot the LVDS input
data clock.

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The DAC5681and DAC5681z are single-channel devices while the DAC5682z supports two-channels. The
DAC5681z and DAC5682z include 2x/4x interpolation filters and on-board clock multiplier with superior
phase noise performance. Each interpolation FIR is configurable in either Low-Pass or High-Pass mode,
allowing selection of a higher order output spectral image.
The DAC5682z is the only member of the family that allows a complex output. An optional Fs/4 coarse
mixer in complex mode provides coarse frequency upconversion and the dual DAC output produces acomplex Hilbert Transform pair. An external RF quadrature modulator then performs the final single
sideband up-conversion.
3.1.2

CDCM7005
The CDCM7005 is a high-performance, low-phase noise and low-skew clock synchronizer thatsynchronizes a VCXO (voltage-controlled crystal oscillator) or VCO (voltage-controlled oscillator)
frequency to a reference clock. The CDCM7005 is used to generate and synchronize the clock outputs tothe system. The device has five outputs which can be configured to LVPECL or LVCMOS levels and canbe divided down by 1, 2, 3, 4, 6, 8, and 16. The divide by 16 can be replaced with a divide by 4 or 8 with a
90° phase shift.

3.1.3

TRF3703
The TRF3703 is a very-low-noise direct quadrature modulator, capable of converting complex modulated
signals from baseband or IF directly up to RF-based on the LO frequency.

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DAC5681/81Z/82z EVM Hardware Description
The DAC5681/81z/82z EVM can be set up in a variety of configurations to accommodate a specific modeof operation. Before starting evaluation, the user should decide on the configuration and make theappropriate connections or changes. The demonstration board comes with the following factory-set
configuration:• No VCXO installed. CDCM7005 in buffer mode which requires an input single-ended clock signal to
SMA connector J6.
• On the DAC5682z EVM outputs are set by default to drive the TRF3703. The DAC5681 andDAC5681z output is connected to J3.
• The converter is set to operate with internal reference. Jumper JP8 EXTLO is installed between pins 2
and 3.
• Full-scale output current set to 20mA through RBIAS resistor R18.

4.1

Jumper Settings
The DAC5681/81z/82z EVM has onboard jumpers that allow the user to modify the board configuration.
Table 1 explains the functionality of the jumpers.
Table 1. Jumper List
Jumper

Label

JP8

EXTLO

Internal (GND) or external (3.3V) voltage reference

Function

JP10

VFUSE

Factory use only. Connect to 1.8VDD for normal operation.

JP12

CDC_PD

Low active power down of CDCM7005

JP13

VCXOB

Choose internal VCXO or external VCXO INBJP14VCXO_P

Choose internal VCXO or external VCXO positive input

External VCXO

Pin 2-3

JP15

VCXO_N

Choose CDCM7005 or external VBB

CDCM7005

Pin 1-2

JP16

REF_CLK

Choose internal 10-MHz ref or external ref

Internal Ref

Pin 2-3

JP17+3.3V_IN

Main or TP3 3.3 voltage source for CDCM7005 and USB

Main

Pin 1-2

JP19+3.3VCLKVCXO power down

3.3 VCLK

Pin 1-2

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Condition

Default

GND

Pin 2-3

1.8 VDD

Pin 1-2

3.3 VCLK

Pin 1-2

External VCXO

Pin 2-3

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Input/Output Connectors
Table 2 lists the input and output connectors on the EVM.
Table 2. Input and Output Connectors
Reference
Designator

Label

Connector Type

Description

J1

IOUTB2SMADACB transformer output. Optional IOUTB2 output. Not populated
on DAC5681/81z.

J2

IOUTB1

SMA

Optional IOUTB1 output. Not populated on DAC5681/81z.

J3

IOUTA2

SMA

DACA transformer output. Optional IOUTA2 output.

J4

IOUTA1

SMA

Optional IOUTA1 output.

J5

4.3

SEMTEK

Input LVDS data to DAC. Output clock to data source.

J6

EXT_VCXO_P

SMAExternal main clock input.

J7

EXT_VCXO_N

SMAExternal VCXO negative connection. Not required.

J8

Y2A_CLK

SMA

Optional CDCM7005 clock output.

J9

EXT_REF_CLK

SMA

External reference clock input.

J10

Y2B_CLK

SMA

Optional CDCM7005 clock output.

J13

USB_CONNUSB

USB connector for software communication.

J14/J15+1.8V_IN

Banana Plug

J16

RFOUT

SMA

J17/J18+3.3V_IN

Banana Plug

+3.3V connection pair.

J19/J20+5VA_IN

Banana Plug

+5V connection pair. Required only for RF measurements.

J23

RF_LO_IN

SMA

TRF3703 LO source input. Not populated on DAC5681/81z.

+1.8V connection pair.
RF output from TRF3703.

USB Interface
The DAC5681/81z/82z EVM has a 4-pin USB port connector that interfaces to a USB 1.1 (or later)compliant USB port. Programming of the CDCM7005 and DAC is accomplished through this port.

4.4

Power Management
The DAC5681/81z/82z EVM requires 1.8-V and 3.3-V supplies for normal operation. An additional 5-V
supply is required supply power up the TRF3073 for RF measurements.

4.5

Input Connector
The DAC5681/81z/82z EVM accepts LVDS inputs through a SEMTEK connector. These inputs drive
DCLK, SYNC and D15-D0 LVDS pairs on the DAC device. An LVDS clock signal from the CDCM7005 isalso output through this connector. This output clock is useful for synchronization with the patterngeneration source.
Table 3. Input Connector
Pin

8

Description

Pin

47

D15P

101

D7P

49

D15N

103

D7N

53

D14P

107

D6P

55

D14N

109

D6N

59

D13P

113

D5P

61

D13N

115

D5N

65

D12P

119

D4P

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Table 3. Input Connector (continued)

4.6

Pin

Description

Pin

Description

67

D12N

121

D4N

71

D11P

125

D3P

73

D11N

127

D3N

77

D10P

131

D2P

79

D10N

133

D2N

83

D9P

137

D1P

85

D9N

139

D1N

89

D8P

143

D0P

91

D8N

145

D0N

95

DCLKP

155

SYNCP

97

DCLKN

157

SYNCN

96

Synchronizing Positive LVDS
output clock

161,162,163,164,165,166,167,16
8,169,170,171,172

GND

98

Synchronizing Negative LVDS
output clock

All others

UnusedClock Configuration
The CDCM7005 requires a VCXO or external clock source to derive its output clock signals.

4.6.1

Buffer Mode
The DAC5681/81z/82z EVM does not come populated with a VCXO and requires an external sine wave
source with a 1-Vrms, 0-V offset on SMA J6. Under this setup, the CDCM7005 operates as a buffer. To
select this mode, the following changes need to be made:1. JP13 and JP14 need to be set in position 2-3.
2. If a VCXO is installed, it is recommended to disable it by removing jumper JP19.

4.6.2

PLL Mode
A VCXO can be installed in U6 to operate the CDCM7005 as a PLL. The following changes need to be
made:
1. JP13 and JP14 need to be in the 1-2 position.
2. Install jumper JP19.
3. A frequency reference (internal or external) needs to be provided.

4.7

Output Configurations
The DAC5681 and DAC5681z options are configured such that the single DAC output drives a a doubly
terminated 50-Ω cable using a 4:1 impedance ratio transformer with the center tap of the transformer
connected to +3.3 V. The output signal is found at SMA connector J3.
The DAC5682z EVM option has a resistor network that can be configured such that the DAC outputs arerouted to the TRF3703 for an RF measurement or routed to the transformer path for a DAC measurement.
The default setup on the board is for RF output.

4.7.1

DAC Outputs
To configure the DAC5682z EVM to evaluate the DAC outputs, the following changes need to be done tothe board:
1. R137, R153, R155 and R156 need to be uninstalled

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2. R109, R134, R135 and R136 need to be installed

Figure 6. DAC5682Z DAC Output Resistor Configuration
If the board is configured for DAC outputs, the TRF3703 modulator is not used and the 5-Vdc supply is
unnecessary. The DAC outputs in this setup are in J1 and J3.
4.7.2

RF Output
To configure the DAC5682z EVM to evaluate the RF output (default setup), the following changes need to
be done to the board:
1. R137, R153, R155 and R156 need to be installed
2. R109, R134, R135 and R136 need to be uninstalled

Figure 7. DAC5682z RF Output Resistor Configuration
If the board is configured for RF output, the 5-Vdc must be applied to power up the modulator. The output
in this setup is in J16.

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4.7.2.1

TRF3703 LO Source

The DAC5682z EVM requires an external local oscillator (LO) source to drive the onboard TRF3703
modulator. This external LO input needs to be connected to the SMA connector J23. The signal level ofthe LO source must comply with the requirements in the TRF3703 data sheet (SLWS184), but typically an
LO power around 6-to-8 dBm is adequate.
4.7.2.2

DAC-to-Modulator Interface

The TRF3703 quadrature modulator requires a common-mode dc voltage of approximately 3.3 V. In order
to use the dc-offset adjustment capabilities of the DAC5682z for carrier suppression, it is imperative tomaintain a dc path from the DAC output to the modulator input. The common-mode voltage for themodulator is maintained with a passive resistor network that is designed to provide the proper operation
point for the DAC5682z and the TRF3703 modulator.
The DAC5682z EVM is configured with enough pads to provide a specific fifth-order differential passive
LC filter. By default, it is only populated with a simple LC low-pass filter to attenuate the higher clock
harmonics. The 3-dB corner of this filter is approximately 300 MHz.

Figure 8. Response of Default Baseband Filter
The DAC5682z EVM also includes a pi pad network on the modulator output to provide some matching or
filtering, if desired. In its default state, the pad is not used and a series capacitor is used on the RF output.

4.8

Reference Operation
The DAC5681/81z/82z full-scale output current is set by applying an external resistor (R18) between the
BIASJ pin of the device and ground. The full-scale output current can be adjusted from 20 mA down to 2
mA by varying this resistor. The full-scale output current, IOUTFS, is defined as follows:

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öæV
IOUTFS = 16 ´ ç EXTIO ÷è R18 øwhere VEXTIO is the voltage at pin EXTIO. This voltage is 1.2 V when using the internally provided
bandgap reference voltage source. The internal reference can be disabled and overridden by an externalreference by connecting a voltage source to EXTIO and connecting EXTLO to +3.3 VA (JP8 EXTLO
connected between pins 1 and 2). The specified range for external reference voltages must be observed.

5

DAC5681/81z/82z EVM Software
The EVM Control Software is started by accessing the Windows start → All Programs →Texas Instruments DACs cascading menus.
The DAC EVM application helps you to:• Configure the DAC and CDCM7005 registers.
• Save and load these register settings using text files.
• Visualize the data path through the DAC• Download a pattern to a TSW3100 Pattern Generator System (link to TSW3100 EVM folder).

5.1

Software Functionality Overview
This section provides you an overview of the software settings and functionality for the entire DAC
Graphical User Interface. The software has five groups of settings that help you modify the functionality of
the active panels. You can switch between these settings by selecting one of the Menu items described inTable 4.
Table 4. Software Main Menu Selections
Menu Item

Top Panel

Bottom Panel

SectionExample Screen
Functionality Reference

EVM Home

EVM and DAC serial information.
EVM communication status

not applicable

Section 5.2
Figure 9
Table 6

DAC5682z
Diagram

DAC Register Configuration

DAC data path under the current Section 5.3
register settings
Figure 10
Table 7

Register Config

DAC Register Configuration

CDCM7005 Register
Configuration

Section 5.4
Figure 11
Table 8TSW3100 Config

DAC Register Configuration

TSW3100 Configuration
Pattern Generator display

Section 5.5
Figure 12
Table 9Help

DAC Register Configuration

DAC data path and help window

Section 5.6

The DAC software interface controls are divided into areas. The functionality of these areas is described in
Section 5.2 through Section 5.6.
Table 5. Software Area Descriptions

12

Area

Description

Menu

Switch between the main functionality settings described in Table 4.

DAC5682Z Home

Displays DAC part serial information and EVM status.

USB and Readback buttons

Reset the USB port to begin a new data session. Disable DAC read capabilities (simulationmode).

DAC5682z Register Table

Displays DAC register settings in binary and hexadecimal formats.

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Table 5. Software Area Descriptions (continued)
Area

Description

DAC5682z Register Configuration

Read/Write DAC register configuration.

CDCM7005 Register Configuration

Write CDCM7005 register configuration (no read capability)

DAC5682z Diagram

Graphical representation of the DAC data path under current register configuration.

TSW3100 Configuration

Controls TSW3100 pattern generation system (See TSW3100 User's Guide SLLU101 formore information)

Help

Information about specific DAC register configuration GUI controls

Figure 9 through Figure 12 displays some of the Menu software areas.

5.2

EVM Home Area
The EVM Home Area includes these GUI controls:• Menu—switches between the major functionality listed in Table 4 and displayed in Figure 9.
• Home—displays DAC part information and EVM status.
• USB/Readback—reset the USB port to begin a new data session. Disable DAC read capabilities(simulation mode).
• DAC5682z Register Table—displays DAC register settings in binary and hexadecimal formats(Figure 10 - Regs).
Note:

The numbers on Figure 9 through Figure 12 correspond to the numbered graphical userinterface subareas (X), described in each table for the DAC EVM software functionality.

Figure 9. EVM Home Displaying EVM Status Settings

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Table 6. EVM Home Software Functionality
Input
OutputDescription

EVM Home

Input

DAC EVM Home area - part number information and EVM status messages

DAC5682z Diagram

Input

DAC Register Configuration and DAC5682z Diagram areas

Register Config

Input .

DAC and CDCM7005 Register Configuration areas

TSW3100 Config

Input

DAC Register Configuration and TSW3100 Configuration areas

Help

Input

Help area

Subarea Name
Menu Area (1)DAC5682z EVM Home Area (2)Functionality

Output

DAC device

Version

OutputChip version

Wafer number

Output

DAC wafer number

Column (x)Output

DAC column position

Row (y)Output

DAC row position

Lot Number

Output

DAC lot number

Fab

OutputFabrication facility where the DAC was manufactured

EVM Serial Number

OutputSerial number for this EVM

Status Messages

OutputDisplays the status of the communication session.

USB / Readback Area (3)Reset USB Port

Input

Begins a new USB session. Click this button if you see a status error message.

Readback

Input/Output

Disables DAC register reads (simulation mode)

DAC5682z Register Table Area (See Figure 10, Figure 11, and Figure 12)
Register Table

14

DAC5681/81z/82z EVM

OutputDisplays the DAC register configuration in binary and hexadecimal formats for all menu
settings.

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5.3

DAC Register Configuration and Block Diagram

Figure 10. DAC Block Diagram and Register Configuration Settings
Table 7. DAC Register Configuration Software Functionality
Input
OutputDescription of Functionality (GUI Setting)

PLL

Input/Output

Phased-locked Loop (PLL) is bypassed (disabled)

PLL Sleep

Input/Output

PLL is put into sleep mode (selected)

PLL Lock

OutputInternal PLL is locked (Green)

PLL Reset

Input/Output

PLL loop filter is pulled down to 0V (set).
Toggle to restart the PLL if an over-speed lock-up occurs.

VCO Frequency

Input/Output

PLL clock output is one-half the PLL VCO frequency (2x).
Runs the VCO at twice the needed clock frequency to reduce phase noise for lower input clock
rates.

PLL Gain (MHz/V)

Input/Output

Adjust the PLL Voltage Controlled Oscillator (VCO) gain.

PLL Range (MHz)Input/Output

Sets the PLL VCO frequency range.

M value

Input/Output

M portion of the M/N divider of the PLL.

N value

Input/Output

N portion of the M/N divider of the PLL. This value should be chosen to divide down the input CLKIN
to maintain a maximum PFD of 160 MHz.

DLL

Input/Output

Delay lock loop (DLL) is bypassed and LVDS data source provides correct setup and hold timing(disabled)

DLL Sleep

Input/Output

DLL is put into sleep mode (selected)

Auto-DLLInput

DLL is restarted automatically when DLL settings change, so there is no need to press the DLL
restart control (selected).

DLL Lock

OutputInternal DLL is locked (Green)

DLL restart

Input/Output

Restarts the DLL manually

DLL Delay (deg.)

Input/Output

Manually adjust the DLL delay ± from the DLL fixed current delay.

Subarea NamePLL Settings (1)DLL Settings (2)SLAU236A – November 2007 – Revised October 2008
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Table 7. DAC Register Configuration Software Functionality (continued)
Subarea Name

Input
OutputDescription of Functionality (GUI Setting)

DLL fixed current
delay (ps/µA)

Input/Output

Adjusts the DLL delay line bias current. Used in conjunction with the DLL inv clock to selectappropriate delay range for a given DCLK frequency

DLL inv clock

Input/Output

Inverts the internal DLL clock to force convergence to a different solution. Used when the DLL delay
adjustment has exceeded the limits of its range.

formatInput/Output

Select 2’s complement or offset binary format.

reverse bus

Input/Output

Reverses the LVDS input data bus so that the MSB to LSB order is swapped (enabled)swap data

Input/Output

A/B data paths are swapped prior to routing to the DACA and DACB outputs (enabled)same data

Input/Output

Data routed to DACA is also routed to DACB (enabled)

FIFO offset

Input/Output

Sets the FIFO’s output pointer location, allowing the input pointer to be shifted –4 to +3 positions
upon SYNC. Default offset is 0 and is updated upon each sync event.

digital logic

Input/Output

Uses the interpolation filters (enabled)interpolation

Input/Output

Selects the interpolation rate.

CM0 mode

Input/Output

Determines the mode of FIR0 and CMIX0 blocks. Since CMIX0 is located between FIR0 and FIR1,
its output is half-rate. Settings apply to both A and B channels.

CM1 mode

Input/Output

Determines the mode of FIR1 and final CMIX1 blocks. Settings apply to both A and B channels.

digital delay

Input/Output

DAC data delay adjustment (0–3 periods of the DAC clock). Used to adjust system level output
timing. The same delay is applied to both DACA and DACB data paths.

clock delay

Input/Output

Changes the number of buffers that the input clock goes through. This allows some adjustment of
the setup/hold of the handoff between the receivers and the digital section.

DAC mode

Input/Output

Selects dual DAC mode or single DAC mode. Used to select input interleaved data (dual DAC).

DACA Sleep

Input/Output

DACA is put into sleep mode (selected)

DACB Sleep

Input/Output

DACB is put into sleep mode (selected). DACB is not automatically set into sleep mode when
configured for single DAC mode. Use this control with single DAC mode to get the lowest power
configuration for DACA output only.

DACA Gain

Input/Output

Scales the DACA output current in 16 equal steps.

DACB Gain

Input/Output

Scales the DACB output current in 16 equal steps.

OffsetInput/Output

Offset A and Offset B values are summed into the DACA and DACB data paths (enabled). Provides
a system-level offset adjustment capability that is independent of the input data.

offset sync

Input/Output

Transfers the Offset A and Offset B values to the registers used in the DACA and DACB offset
calculations. This control is enabled automatically for any change in the Offset A or Offset B values.

Offset A

Input/Output

Offset adjustment value for the A data path.

Offset B

Input/Output

Offset adjustment value for the B data path.

DAC A LPF

Input/Output

95 kHz low pass filter corner on the DACA current source bias (enabled). Uses a 472 Hz filter
corner (disabled).

DAC B LPF

Input/Output

95 kHz low pass filter corner on the DACB current source bias (enabled). Uses a 472 Hz filter
corner (disabled).

SLFST Error

Input/Output

Masks out SLFTST Errors.

FIFO Error

Input/Output

Masks out FIFO Errors.

Setup/Hold Error

Input/Output

Masks out Setup/Hold Errors.

SLFST error reset

Input/Output

Asserted when the Digital Self Test (SLFTST) fails. Clear to reset a SLFST error.

FIFO error reset

Input/Output

Asserted when the FIFO pointers overrun each other, causing a sample to be missed. Clear to reseta FIFO error.

Input Settings (3)Digital Settings (4)DAC Settings (5)Error Settings (6)Setup/Hold error reset Input/Output

Any received data pattern other than 0xAAAA or 0x5555 causes this bit to be set. Clear to reset a
Setup/Hold error.

SDO

Input/Output

Selects the signal polarity on the SDO pin (normal or inverted)

Input/Output

Selects 3-pin or 4-pin serial interface mode.

SYNC Settings (7)serial interface

16

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Table 7. DAC Register Configuration Software Functionality (continued)
Subarea Name

Input
OutputDescription of Functionality (GUI Setting)sync source

Input/Output

Selects the synchronization signal source. If soft sync is selected the software sync control is usedas the only synchronization input and the LVDS external SYNC input pins (hard sync) are ignored.

software sync

Input/Output

Substitute for the LVDS external SYNC input pins for both synchronization and transmit enable
control.

hold sync

Input/Output

Enables the sync to the FIFO output HOLD block.

clk div sync

Input/Output

Enables the clock divider sync.

FIFO sync

Input/Output

Enables the FIFO offset sync.

self test

Input/Output

Enables a Digital Self Test (SLFTST) of the core logic.

FA002

Input/Output

Keep disabled. Used only for factory test purposes.

Fuse A

Input/Output

Keep disabled. Used only for factory test purposes.

Fuse B

Input/Output

Keep disabled. Used only for factory test purposes.

ATEST

Input/Output

Keep disabled. Used only for factory test purposes.

SEND/SAVE Button Settings (8)Send All

Input

Writes all registers to the DAC device.

Read All

Input

Reads all registers from the DAC device. It is rarely necessary to use this as the registers are readevery time a DAC control changes.

Load Regs

Input

Loads a DAC register configuration from a text file. Files need to consist of a single column with theregister values in hexadecimal format.

Save Regs

Input

Saves a DAC register configuration to a text file.

5.4

CDCM7005 Register Configuration

Figure 11. The CDCM7005 and DAC5682 Register Configuration Settings

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Table 8. CDCM7005 Register Configuration Software Functionality
Input
OutputDescription

Output Settings

Input

Switches the display between the CDCM7005 output settings and advanced settings.

CDCM7005 Operation

Input

Select Buffer Mode when there is no VCXO installed or the VCXO is enabled. In this case the
CDCM7005 operates as a buffer. Select PLL Mode when a VCXO is being used by the
CDCM7005.

M & N Selection

Input(Auto) M and N divider values are calculated automatically based on Reference and VCXO
frequencies.

Ref. Freq. (MHz)Input

Frequency of the reference oscillator given to the CDCM7005.

VCXO Freq. (MHz)Input

Frequency of the VCXO used.

M Divider

Input/Output

M divider value.

N Divider

Input/Output

N divider value.

FB_MUX

Input/Output

Feedback MUX select.

Phase Shift

Input

Phase shift select.

Output Freq (MHz)OutputOutput frequency of the CDCM7005 based on the Reference and VCXO frequencies, and M andN values. If Output Freq differs from VCXO Freq, Output Freq displays using a red text.

Y0-Y4 Dividers

Input

Selects the output dividers of the CDCM7005 outputs.

Y0-Y4 Levels

Input

Selects between CMOS or LVPECL levels of the CDCM7005 outputs.

Y0-Y4 States

Input

Selects the operating state of the CDCM7005 outputs.

Subarea Name
General Settings (1)PLL Settings (2)Output Settings (3)SEND/SAVE Button Settings (4)Send All

Input

Writes all registers to the DCDM7005 device.

Load Regs

Input

Loads a DCDM7005 register configuration from a text file. Files need to consist of a single
column with the register values in hexadecimal format.

Save Regs

Input

Saves a DCDM7005 register configuration to a text file.

Advanced Settings (not shown)
Advanced Registers

18

DAC5681/81z/82z EVM

Input CDCM7005 advanced registers. See the CDCM7005 data sheet (SCAS793) for more
information about these registers.

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5.5

TSW3100 Configuration and Pattern Generation
The TSW3100 can be loaded with a custom pattern file using the GUI options. For further details on thefile format of the custom pattern, see the TSW3100 Users Guide (SLLU101).

Figure 12. TSW3100 Pattern Generator and DAC Register Configuration Settings
Table 9. TSW3100 Configuration and Pattern Generation Functionality
Input
OutputDescription

File Format

Input

Selects Binary and 16-bit signed Integer format. If Binary is selected, the file must comply withthe requirements described on the TSW3100 (SLLU101) documentation. If integer format isselected, the file must consist of a single column for a real signal or two columns for a
two-channel or complex signal.

Browse Button

Input

Navigate to the folder containing the input pattern file name. Select the file to use.

Column Delimiter

Input

Column separator used in the two-channel or complex integer input file. (Not displayed)

Output Level

Input

LVDS or CMOS outputs. Only LVDS is available for the DAC5682z.

Data Format

Input

2's complement or offset binary format.

IP Address

Input

Specify final digit (1, 2, 3, or 4) of the IP address for the TSW3100 pattern generator.

TSW3100 State

Input

Master or Slave mode. The default state is Master mode. See TSW3100 (SLLU101)
documentation for more information.

Load and Start

Input

Load a pattern file and start the TSW3100.

Stop Pattern

Input

Stop the pattern transfer.

Re-start Pattern

Input

Re-start the pattern. A pattern must be loaded in memory for this command to work.

Subarea Name
Pattern Selection (1)Output Mode (2)Command Buttons (3)Pattern Generation Results (4)Command

OutputShows sequence of commands sent to the TSW3100.

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Table 9. TSW3100 Configuration and Pattern Generation Functionality (continued)
Subarea Name

Input
OutputDescription

Status

OutputStatus of the TSW3100 transaction.

Bytes loaded

OutputNumber of bytes loaded to the TSW3100.

5.6

Help
When you select the the Help menu item, the DAC Diagram screen (Figure 10) and a detached, pop-up
Help text window display. As you move the cursor over the DAC Diagram GUI controls, thecontext-sensitive help text changes in the pop-up window.

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6

DAC5681/81z/82z Initial Power Up and Test

6.1

Test Setup Block Diagram
The recommended test setup for the EVM is shown in Figure 13. In this setup the Texas Instruments
TSW3100 pattern generator solution is used to supply the LVDS input data.

Figure 13. DAC5682z EVM Driven by TSW3100 Pattern Generator

6.2

Test Equipment
The test equipment listed below is required to evaluate the EVM. Other equipment may be substituted,
however results may vary due to instrument limitations.
• Power supplies—1.8 V (DAC digital), 3.3 V (DAC analog), and 5 V (RF modulator)• Spectrum Analyzer—Rhode & Schwarz FSU, FSQ, or equivalent. This is necessary to measure thenoise floor ACPR greater than 70 dBm with the noise correction option.
• Pattern generator—TSW3100 using LVDS mode, or some other LVDS capable generator.
• Oscilloscope—probe clock and data lines for troubleshooting.
• Digital volt meter—verify signal levels.

6.3

Calibration
To measure the proper output power, the insertion loss of the analyzer cable must be calibrated. Measurea calibrated 0 dBm source to see how much loss is in the cable at the frequency of interest.

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6.4

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Typical Performance Measurements
The DAC5681, DAC5681z and DAC5682z measurements at the transformer outputs J1 and J3 will havebetter performance than the RF output at low output frequencies. The RF output is typically limited by theperformance of the RF parts. In this case the DAC output at 0 IF or low IF is several dB better than thenoise floor of the modulator output at J16.

Ref -12 dBm

* Att

10 dB

* RBW 30 kHz* VBW 300 kHz* SWT 2 s

-20
-30

A

-40
1 RM *
-50
CLRWR
-60
-70
-80

NOR

-90
-100
-110
Center 30.72 MHz

2.55 MHz/

Span 25.5 MHz

Tx Channel
Bandwidth

3.84 MHzW-CDMA 3GPP FWD

Power-8.02 dBm

Adjacent Channel
Bandwidth
Spacing

3.84 MHz
5 MHz

Lower
Upper

-81.73 dB-81.65 dB

Alternate Channel
Bandwidth
Spacing

3.84 MHz
10 MHz

Lower
Upper

-82.95 dB-82.74 dB

Figure 14. DAC5681/81z/82z EVM Transformer Output With a Low IF at 30.72 MHz

22

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Ref -13.2 dBm

* Att

5 dB

* RBW 30 kHz* VBW 300 kHz* SWT 2 s

-20
-30

A

-40
1 RM *
-50
CLRWR
-60
-70
-80

NOR

-90
-100
-110
Center 2.53072 GHz

2.55 MHz/

Span 25.5 MHz

Tx Channel
Bandwidth

W-CDMA 3GPP FWD
3.84 MHz

Power-8.95 dBm

Adjacent Channel
Bandwidth
Spacing

3.84 MHz
5 MHz

Lower
Upper

-75.79 dB-75.42 dB

Alternate Channel
Bandwidth
Spacing

3.84 MHz
10 MHz

Lower
Upper

-78.44 dB-77.21 dB

Figure 15. DAC5682z EVM output at RF LO + low IF of 30.72M (6 dB lower than DAC output)

6.5

DAC5681/81z/82z Test Procedure
The steps described in this section show how to connect and configure the DAC5681/81z/82z EVM forevaluation under the default settings.
1. Connect the DAC5681/81z/82z EVM SEMTEK connector to a digital test pattern generator that
supports this interface such as Texas Instruments TSW3100.
2. Connect the 1.8-V (J14/J15) and 3.3-V (J17/J18) power supplies. If using the modulator the 5-V(J19/J20) supply also needs to be connected. Ensure that each supply is not drawing more than 1-A ofcurrent.
3. Provide a single-ended, 1-Vrms, 0-V, offset sine-wave signal to the EVM EXT_VCXO_P (J6) SMA
connector. LED D1 should illuminate indicating that a signal has been detected. If not, verify that thecorrect signal is being provided.
4. If testing at RF (DAC5682z EVM option) provide a 6-dBm LO signal to the RF_LO_IN (J23) SMA
connector.
5. Connect one end of the supplied USB cable to an available USB port on the host PC. Connect theother end of the cable to J13 on the EVM.
6. Open the DAC5682z EVM software. The DAC software detects if the USB port is active and if it iscapable of reading the EVM serial number. The EVM Home menu (Figure 9 and Table 6) of the
DAC8652z GUI software provides this status information.
7. Program the CDCM7005 and DAC registers as necessary. An example configuration file is included
under the installation folder: C:\Program Files\Texas Instruments\DAC5682z\DAC5682z Configuration
Files\
8. Program and run the pattern generator. If using the TSW3100, see the user's guide for more
information on how to set up a digital pattern.
9. Analyze the DAC or RF output using an spectrum analyzer.

SLAU236A – November 2007 – Revised October 2008
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7

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PC Board Layouts, Bill of Materials and Schematics
This section contains the PC-board layouts, bill of materials and schematics for the DAC5681/81z/82z
EVM.

7.1

Board Layouts

Figure 16. Silkscreen (top)24

DAC5681/81z/82z EVM

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Figure 17. Layer 2

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Figure 18. Layer 3

26

DAC5681/81z/82z EVM

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Figure 19. Layer 4

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Figure 20. Layer 5

28

DAC5681/81z/82z EVM

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Figure 21. Layer 6

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Figure 22. Layer 7

30

DAC5681/81z/82z EVM

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Figure 23. Layer 8

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Figure 24. Layer 9

32

DAC5681/81z/82z EVM

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Figure 25. Screen (Bottom)

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PC Board Layouts, Bill of Materials and Schematics

7.2

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Bill of Materials

QTY.

Part ReferenceValue

PCB Footprint

MFR. Name

MFR. Part Number

12

C1 C2 C5 C8 C56 C70
C76 C79 C84 C87
C121 C124

0.01 µF

0603

Panasonic

ECJ-1VB1C103K

1

C3

0.15 µF

0402

Murata

GRM36X5R154K10H520

6

C4 C29 C48 C104
C106 C127

1000 pF

0402

Panasonic

ECJ-0EB1E102K

38

C6 C7 C9-C15 C17
C18 C20 C23-C25 C27
C33 C38-C47 C50-C52
C57 C61 C94 C95
C107 C114 C130 C131

0.1 µF

0402

Panasonic

ECJ-0EB1C104K

16

C16 C21 C32 C36 C53
C54 C71 C74 C80 C82
C88 C93 C97 C98
C120 C126

10 µF

tant_aKermet

T494A106M016AS

0

C19 C26 C28 C30

0.01 µF

0603

Panasonic

ECJ-1VB1C103K_DNI

1

C22560 pF

0402

Panasonic

ECJ-0EB1H561K

2

C31 C113

100 pF

0402

Panasonic

ECJ-0EB1E101K

8

C34 C69 C75 C78 C83
C86 C122 C125

1 µF

0603

Panasonic

ECJ-1V41E105M

1

C35

0.47 µF

0603

Murata

GRM188R71C474KA88D

3

C49 C128 C1290.01 µF

0402

Panasonic

ECJ-0EB1E103K

3

C58 C108 C115

4.7 µF

tant_aAVX

TAJA475K020R

2

C59 C60

47 pF

0603

Panasonic

ECJ-1VC1H470J

7C72 C77 C81 C85 C89
C119 C123

47 µF

tant_b

Kemet

T494B476M010AS

0

C73 C100 C101 C116

4.7 pF

0603

Panasonic

ECJ-1VC1H047C_DNI

2C99 C109

3.3 pF

0402

Murata

GRM1555C1H3R3CZ01D

2

C102 C103

22 pF

0402

Panasonic

ECJ-0EC1H220J

0C105 C112

2.2 pF

0603

AVX

06035A2R2CAT2A_DNI

2C110 C111

2.7 pF

0603

AVX

06035A2R7CAT2A

0

C117 C118

0.01 µF

0402

Panasonic

ECJ-0EB1E103K_DNI

3

D1-D3

LED green

LED_0805

Panasonic

LNJ306G5UUX

34

Note

DNI

DNI

DNI

DNI

3

D12-D14

MBRB2515L

DIODE_MBRB2515L

ON Semiconductor

MBRB2515LT4G

13

FB1-FB1368 Ω at 100 MHz

1206

Panasonic

EXC-ML32A680U

4

J1-J4

SMA_PCB_THVT

SMA_THVT_312x312

Johnson Components

142-0701-201

7

J6-J10 J16 J23

SMA_END_JACK_RND

SMA_SMEL_218x247_096

Johnson Components

142-0761-801

1J13

USB_B_S_F_B_TH

CON_THRT_USB_B_F

SAMTEC

USB-B-S-F-B-TH

3

J14 J17 J20

BANANA_JACK_RED

CON_THVT_BANANA_JACK_250DIASPC Technology

845-R

3

J15 J18 J19

BANANA_JACK_BLK

CON_THVT_BANANA_JACK_250DIASPC Technology

845-B

1

J5

ASP-122952-01

CON_SMVT_160POS_ASP_122952

SAMTECASP-122952-01

4

JP8 JP13 JP14 JP16

Jumper_1x3_100_430L

HDR_THVT_1x3_100_M

SAMTECHMTSW-103-07-G-S-.230(SHUNT 2-3)

4

JP10 JP12 JP15 JP17

Jumper_1x3_100_430L

HDR_THVT_1x3_100_M

SAMTECHMTSW-103-07-G-S-.230(SHUNT 1-2)

1

JP19

Jumper_1x2_100_430L

HDR_THVT_1x2_100_M

SAMTECHMTSW-102-07-G-S-.230

0

L6 L7

56 nH

IND_0603

Panasonic

ELJ-RE56NJF3_DNI

4

L8 L9 L14 L15

10 nH

IND_0603

Coilcraft

0603CS-10NXLU

4

L10-L13

68 nH

0603

Coilcraft

0603CS-68NXJL

0

R1 R2 R4 R5 R12 R14
R17 R19

1K

0402

Panasonic

ERJ-2RKF1001X_DNI10

R3 R7 R13 R21 R26
R80 R82 R90 R93 R96

100

0402

Panasonic

ERJ-2RKF1000X

0

R6 R9 R15 R20 R23
R27 R109 R134-R136

0

0603

Panasonic

ERJ-3GEY0R00V_DNI

5

R8 R22 R44 R49 R62

0

0402

Panasonic

ERJ-2GE0R00X

1

R10

93.1

0402

Panasonic

ERJ-2RKF93R1X

0

R11 R24 R132 R133

60.4

0603

Yageo

RC0603FR-0760R4L_DNI

DNI

0

R16

100

0603

Panasonic

ERJ-3EKF1000V_DNI

DNI

1

R18

953

0402

Panasonic

ERJ-2RKF9530X

1

R25

1K

0402

Panasonic

ERJ-2RKF1001X

3

R28-R307500402

Panasonic

ERJ-2RKF7500X

8

R31-R34 R42 R43 R66
R67

130

0402

Panasonic

ERJ-2RKF1300X

DAC5681/81z/82z EVM

DNI

DNI

DNI

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QTY.

Part ReferenceValue

PCB Footprint

MFR. Name

MFR. Part Number

8

R36-R39 R46 R47 R69
R70

82.5

0402

Panasonic

ERJ-2RKF82R5X

Note

2

R40 R116

150

0402

Panasonic

ERJ-2RKF1500X

2

R41 R150

90.9

0603

Panasonic

ERJ-3EKF90R9V

0

R45 R51 R122 R123

0

0402

Panasonic

ERJ-2GE0R00X_DNI

DNI0

R48 R541300402

Panasonic

ERJ-2RKF1300X_DNI

DNI9R50 R56 R78 R79 R81
R84 R89 R95 R97

22.1

0402

Panasonic

ERJ-2RKF22R1X

0

R52 R57 R110 R111

150

0402

Panasonic

ERJ-2RKF1500X_DNI

DNI0

R53 R58

82.5

0402

Panasonic

ERJ-2RKF82R5X_DNI

DNI

0

R55

49.9

0402

Panasonic

ERJ-2RKF49R9X_DNI

DNI7

R59-R61 R64 R108
R113 R114

10K

0402

Panasonic

ERJ-2RKF1002X

1

R63

162

0402

Panasonic

ERJ-2RKF1620X

1

R65

4.75K

0402

Panasonic

ERJ-2RKF4751X

1

R92

100

0603

Panasonic

ERJ-3EKF1000V

18

R137 R140-R142 R145
R153 R155 R156
R159-R168

00603

Panasonic

ERJ-3GEY0R00V

4

R138 R151 R152 R154

60.4

0603

Yageo

RC0603FR-0760R4L

1

R139

49.9

0402

Panasonic

ERJ-2RKF49R9X

4

R143 R144 R147 R148

634

0603

Yageo

RC0603FR-07634RL

4

R146 R149 R157 R158

115

0603

Yageo

RC0603FR-07115RL

1

SW1SW RESET

SW_SMVT_RESET

C&K

KT11P3JM

2

T1 T2

ADT4-1T

TFMR_6_250x340_100

Mini-Circuits

ADT4-1T

8

TP1-TP8

Testloop_Black

TP_THVT_060_RND

Components Corporation

TP-105-01-00

1

U1

DAC5681/81Z/82Z

QFN_64_360x360_0p50mm_pwrpad

Texas Instruments

DAC5681,81Z,82Z

TI

1

U2

CDCM7005

QFN_48_281x281_0p50mm_pwrpad

Texas Instruments

CDCM7005RGZT

TI

1

U3

OSC-VECTRON

OSC_4_SM_460x386

VectronVTD3-J0BC-10M000

TI

1

U5

FT245RL

SSOP_28_413x220_26

FTDI Chip

FT245RL

0U62115-491.52MHZ

VCXO_6

Toyocom

TCO-2111-491.52_DNI

DNI

1

U8

TRF3703-33

QFN_24_163x163_0p50mm_pwrpad

Texas Instruments

TRF3703-33IRGET

TI

1

U10

SN74AHC541PWTSSOP_20_260x177_26

Texas Instruments

SN74AHC541PW

TI

1

U11

SN74HC241PWTSSOP_20_260x177_26

Texas Instruments

SN74HC241PW

TI

4Z_SCREW1Z_SCREW4SCREW PANHEAD
4-40 x 3/8

Building Fasteners

PMS 440 0038 PH

SCREW FOR
STANDOFF8

Z_SH-H1-Z_SH-H6
Z_SH-H9 Z_SH-H10

SHUNT-HEADER

Keltron

MJ-5.97-G

SHUNT FORHEADER

4

Z_STANDOFF1Z_STANDOFF4

STANDOFF ALUM
HEX 4-40 x 0.500

Keystone

2203

STANDOFF

Notes:
1.

DNI = DO NOT INSTALL

2.

SHUNT 2-3

3.

SHUNT 1-2

4.

SCREW FOR STANDOFF

5.

SHUNT FOR HEADER

6.

STANDOFFSLAU236A – November 2007 – Revised October 2008
Submit Documentation Feedback

DAC5681/81z/82z EVM

35

PC Board Layouts, Bill of Materials and Schematics

7.3

www.ti.com

Schematics
The DAC5681/81z/82z schematics are appended to the end of this document.

36

DAC5681/81z/82z EVM

SLAU236A – November 2007 – Revised October 2008
Submit Documentation Feedback

5

4

3

2

1

+1.8VCLKNOTES:R1
1K
DNI

CLKINCR3 +1.8VCLK
100
R4
1K
DNI

CLKIN

SYNCP
SYNCN
D15P
D15N
D14P
D14N
D13P
D13N
D12P
D12N

C95 + C97
10uF
.1uF
10V

D12N
D12P
D13N
D13P
D14N
D14P
DVDD
IOVDD
D15N
D15P
SYNCN
SYNCP
GND
CLKINC
CLKIN
CLKVDD.01uF+1.8VD

C

R12
1K
DNI

C5

SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2

R122

SH3 INT_DCLKP
.01uF

0
DNI

R14
1K
DNI
+1.8VD
R17
1K
DNI

C8

R92
100

R16
100
DNI

R123

SH3 INT_DCLKN
0
DNI

SH2
SH2
SH2
SH2
SH2
SH2

D7P
D7N
D6P
D6N
D5P
D5N

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

D11P
D11N
D10P
D10N
D9P
D9N
D8P
D8N
DCLKP
DCLKN
D7P
D7N
D6P
D6N
D5P
D5N

PWRPAD
LPF
DVDD
AVDD
IOUTB1IOUTB2
AVDD
EXTLO
BIASJ
EXTIO
AVDD
AVDD
IOUTA2IOUTA1AVDD
DVDD
RESETBU1
DAC5681/81Z/82Z

65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

B

C9

C13
.1uF

C14
.1uF

C15 + C16
.1uF
10uF
10V

+ C93
10uF
10V

C17
.1uF

SH6

1000pFIOUTB1

SH6

C6
.1uF

+ C98
C20
10uF
.1uF
10V

953

.1uF

L6
56nH
DNI

DNI

R134

JP8
EXTLO +3.3VA
1
2
3+3.3VA

5SM

J1
IOUTB2MJ2IOUTB1M

J3IOUTA2

3

R15

1

S
A

C

R13
100

+3.3VA+3.3VA

R21
100+3.3VA

R133
60.4

SH3,4

R20
0
DNI

R22
0

DNI
IOUTA2

1

IOUTA1

SH6
SH6

R23
0
DNI

T2

4

3

L7
56nH
DNI

5

S

DNI

B

2
1
ADT4-1T

R24
60.4

SH4
SH4
SH4
SH4

1

A

6

R25
1K

C10
.1uF

R27

1

S
A

0
DNI

R26
100

M

J4
IOUTA1+3.3VATP8SDO
A(SHUNT 1-2)

Size

B
Date:
4

1

2

C7
.1uF

Title

5

1

0
DNI

0
DNI

SDENB
SCLK
SDIO
SDO

C94
.1uF

T1

6

4

0
DNI

+1.8VD1

C18.1uF

IOUTB2R136

JP10+1.8VD
VFUSE
1
2
3

R9
0
DNI
A

+3.3VA+1.8VD

C12
.1uF

C4

4
2
SW RESET

A

C11
.1uF

0.15uF

SW1
RESET+1.8VD+3.3VA

DNI

R135

RESET

C127
1000pF

0
DNI

R8
0

(SHUNT 2-3)

3
D4P
D4N
D3P
D3N
D2P
D2N
D1P
D1N
D0P
D0N

R6

ADT4-1T

R18

.01uF

SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2

R11
60.4

0
DNI

33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

SH2 EXT_DCLKN

C3+1.8VD1+1.8VD1

C129

0
DNI

+3.3VA

R132
60.4

D4P
D4N
D3P
D3N
D2P
D2N
DVDD
D1P
D1N
D0P
D0N
VFUSE
SDO
SDIO
SCLK
SDENB

R19
1K
DNI

.01uF

D11P
D11N
D10P
D10N
D9P
D9N
D8P
D8N

93.1

+1.8VCLK

SH2 EXT_DCLKP

R7
100

R109

R10

C128

SH3

.01uF

R5
1K
DNI

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2

C2

5
4
3
2

SHEET 6ALL COMPONENTS ARE DNI

D+3.3VA

5
4
3
2+3.3VA

5
4
3
2+1.8VD

SH3

.01uF

R2
1K
DNI

5
4
3
2

SHEET 1
R109,R134,R135,R136 ARE INSTALLED
R7 AND R13 = 0 OHMS
R8,C7,T1,J1,J2 = DNI

D

C1

1

FOR DAC5681/81Z OPTION:

2

2)

1

DNI = DO NOT INSTALL

2

1)

3

2

Document Number

DAC5682Z EVM

Rev

DAC

Wednesday, August 06, 2008

D
Sheet
1

1

of

6

5

4

3

2

1

D

D

J5A

C

B

J5B

1
3

1
3

2
4

2
4

5
7

5
7

6
8

6
8

9
11

9
11

10
12

10
12

13
15

13
15

14
16

14
16

17
19

17
19

18
20

18
20

21
23

21
23

22
24

22
24

25
27

25
27

26
28

26
28

29
31

29
31

30
32

30
32

33
35

33
35

34
36

34
36

37
39

37
39

38
40

38
40

161
163

GND
GND

GND
GND

162
164

SH1
SH1

D15P
D15N

SH1
SH1

D14P
D14N

SH1
SH1

D13P
D13N

SH1
SH1

D12P
D12N

SH1
SH1

D11P
D11N

SH1
SH1

D10P
D10N

SH1
SH1

D9P
D9N

SH1
SH1

D8P
D8N

SH1 EXT_DCLKPSH1 EXT_DCLKN

ASP-122952-01

J5C

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

165
167

GND
GND

GND
GND

166
168

FPGA_CLKOUTP SH3
FPGA_CLKOUTN SH3

SH1
SH1

D7P
D7N

SH1
SH1

D6P
D6N

SH1
SH1

D5P
D5N

SH1
SH1

D4P
D4N

SH1
SH1

D3P
D3N

SH1
SH1

D2P
D2N

SH1
SH1

D1P
D1N

SH1
SH1

D0P
D0N

SH1 SYNCPSH1 SYNCN

ASP-122952-01

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159

102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160

102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160

169
171

GND
GND

GND
GND

170
172

C

B

ASP-122952-01

A

A

Title
Size

B
Date:
5

4

3

2

Document Number

DAC5682Z EVM

Rev

INTERFACE CONTROL

Monday, August 04, 2008

Sheet
1

2

D
of

6

5

4

3

2

1

NOTES:R28

DNI = DO NOT INSTALL+3.3VCLK

R29

750

VCXO
D1

LED green

REF
D2

LED green

LOCK
D3

LED green

750

2+3.3VCLKR30
JP19+3.3VCLK

D

FB1
C22
560pF
10%
50V

68 OHM @ 100MHz + C21
10uF
10V

+3.3VCLK

C23
.1uF
10%
16V
JP13
VCXOB
1
2
3

U6

1
2
3

V_CTRL VCC
NC
OUTB
GND
OUT

1

(SHUNT 2-3)

C24

JP14
VCXO_P
1
2
3

R44
0

R45 .1uF
0
DNI

4
3
2
5

C

1

4
3
2
5

R51 .1uF
0
DNI
J9
EXT_REF_CLK

R59+3.3VCLK(SHUNT 1-2)

SMA

10K

1

END

+3.3VCLK

10K
U3

1
8

FB2
C32
10uF
10V

C27
.1uF
10%
16V

R55
49.9
DNI

REF
VDD

5
4

OUT
GND

R62
0

JP16
REF_CLK
1
2
3(SHUNT 2-3)C29
1000pF
25V
10%

OSC-VECTRON
C31
100pF

+3.3VCLK
U2

R40
150

R61

+3.3VCLK

68 OHM @ 100MHz +

R116
150

JP15
VCXO_N
1
2
3

4
3
2
5

TP1
REF_ADJ+3.3VCLK

AVCC

R49
0

R37
82.5

(SHUNT 2-3)

C25
SMA
J7
EXT_VCXO_N END

R36
82.5

6
5
4

2115-491.52MHZ
DNI
SMA
J6
EXT_VCXO_P END

R33
130

+3.3VCLK

V_CTRL

B

R32
130

R60
10K

48
47
46
45
44
43
42
41
40
39
38

VCC
Y0B
Y0A
VCC
VCC
VCXO_IN
VCXO_INB
VCC
VBB
AVCC
AVCC

37
36

SEC_REF
PRI_REF35

REF_SEL

34
33

NC
VCC_CP

32
31
30

AVCC
CP_OUT
AVCC

29
28

CTRL_LECTRL_CLK

27

AVCC

/PD
VCC
Y4A
Y4B
VCC
VCC
Y3A
Y3B
VCC
VCC
Y2A
Y2B
VCC
/RESET or /HOLD
VCC
Y1A
Y1B
VCC
VCC
VCC
VCC
STATUS_VCXO or I_REF_CP
STATUS_REF or PRI_SEC_CLKGND
PWRPAD

1
2
16
17
5
6
11
12
9
10
7
8
13
14
15
3
4
18
19
20
21
22
23
24
49

PLL_LOCKCTRL_DATA

25
26

JP12
CDC_PD
1
2
3

R34
130

CLKINC SH1
CLKIN SH1
R38
82.5

(SHUNT 1-2)

R39
82.5

+3.3VCLK
R42
130

INT_DCLKN SH1
INT_DCLKP SH1
C

RESET

SH1,4

R46
82.5

+3.3VCLK

R110
150
DNI

R111
150
DNI

R66
130

R47
82.5

R67
130

R159

R161

0

0
FPGA_CLKOUTN SH2
FPGA_CLKOUTP SH2

R160

R162

0

0
R69
82.5

CTRL_DATA SH4

R70
82.5
+3.3VCLKCDCM7005

R64
10K

22.1
CTRL_LE

R163

R50

CTRL_CLK SH4

C33
.1uF

R63

SH4

R52
150
DNI

R65
4.75K

V_CTRL

1

C34
1uF
20%
25V

+

B

1

SMA
END

R53
82.5
DNI

J8
Y2A_CLK+3.3VCLK

C35
.47uF
10%
16V

R164

R56
22.1

2

C36
22uF
20%
10V

R48
130
DNI

0

162

+3.3VCLK

A

R43
130

4
3
2
5

1

D

R31
130

750

R57
150
DNI

0

R54
130
DNI

1

SMA
END

R58
82.5
DNI

J10
Y2B_CLKC

4
3
2
5

1)

AVCC

A

FB3
C53 + C38
10uF
.1uF
10V

C39
.1uF

C40
.1uF

C41
.1uF

C42
.1uF

C43
.1uF

C44
.1uF

C45
.1uF

C46
.1uF

C47
.1uF

68 ohm @ 100MHz

C48.001uF

C49
.01uF

C50
.1uF

C51
.1uF

C52 + C54
.1uF
10uF
10V

Title
Size

B
Date:
5

4

3

2

Document Number

DAC5682Z EVM

Rev

CDC

Wednesday, August 06, 2008

D
Sheet
1

3

of

6

5

4

3

2

1

D

D

FB4
68 OHM @ 100MHz
C56
10nF

C57
.1uF

+3.3V_LOGIC

+ C58
4.7uF
20V

C130
.1uF

J13
USB_CONN

5
6

1
2
3
4

GND1 VCC
-DATA
+DATA
GND2 GND+3.3V_LOGIC

USB_B_S_F_B_TH

R113
10K

R114
10K
U11

C59
47pF

C60
47pF

1
2
4
6
8
11
13
15
17
10

U5

20

VCC

D0

1

R78

16

USBDM

D1

5

R81

22.1

15

USBDP

D2

3

R84

22.1

4

VCCIO

D3

11

8

NC1

D4

2

R89

22.1

19

RESET

D5

9

R79

22.1

24

NC2

D6

10

R97

22.1

27

OSCI

D7

6

R95

22.1

28

OSCO

RXF

23

17

3V3OUT

TXE

22

25
7
18
21
26

AGND
GND
GND
GND
TEST

RD

13

WR

14

PWREN

12

C

C61
.1uF

22.1

1OE VCC
1A1 2OE
1A2 1Y1
1A3 1Y2
1A4 1Y3
2A1 1Y4
2A2 2Y1
2A3 2Y2
2A4 2Y3
GND 2Y4

20
19
18
16
14
12
9
7
5
3

SDIO

SH1

C

SN74HC241PW+3.3V_LOGIC+3.3V_LOGIC

C131
.1uF

R108
10K

FT245RL

U10

B

SH1

SDO

1
2
3
4
5
6
7
8
9
10

OE1 VCC
A1 OE2
A2
Y1
A3
Y2
A4
Y3
A5
Y4
A6
Y5
A7
Y6
A8
Y7
GND Y8

20
19
18
17
16
15
14
13
12
11

R82
R96
R80

100
100
100

R90
R93

100
100

B

SCLK
SH1
CTRL_CLK SH3
SDENB
SH1
CTRL_DATA SH3
CTRL_LE SH3

SN74AHC541PW

A

A

Title
Size

B
Date:
5

4

3

2

Document Number

DAC5682Z EVM

Rev

USB INTERFACE

Wednesday, August 06, 2008

Sheet
1

D
4

of

6

5

4

3

2

1

+1.8VDDD12
MBRB2515L

C69
1uF
20%
25V

C70
+
.01uF

C72
47uF
20%
10V

1
2
3

68 OHM @ 100MHz+
D14
MBRB2515L

BANANA_JACK_BLK
J19
GND+1.8V_IN+5VA_IN
C122
1uF
20%
25V

C120
10uF
10V

C119
47uF
20%
10V

C121 +
.01uF

D

1
2
3

68 OHM @ 100MHz
C71
10uF
10V

FB12

4

BANANA_JACK_RED
J20+5VA_IN+1.8V_IN+

BANANA_JACK_BLK
J15
GND

+5VA

FB5

4

BANANA_JACK_RED
J14+1.8V_IN+1.8VCLK
FB7
68 OHM @ 100MHz

+

C80
10uF
10V

C78
1uF
20%
25V

+1.8V_IN

C79
+
.01uF

C81
47uF
20%
10V

+1.8VD1
FB13

C68 OHM @ 100MHz
+

C126
10uF
10V

C125
1uF
20%
25V

C124 +
.01uF

C

C123
47uF
20%
10V

+3.3VA+3.3V_IN
68 OHM @ 100MHz+
D13
MBRB2515L

TP2
GND

TP3
+3.3V_IN

C74
10uF
10V

JP17
+3.3V_IN
1
2
3(SHUNT 1-2)

C75
1uF
20%
25V

C76
+
.01uF

TP5
GND

TP6
GND

TP7
GND

C77
47uF
20%
10V

B

1
2
3

B

BANANA_JACK_BLK
J18
GND

TP4
GND

FB6

4

BANANA_JACK_RED
J17+3.3V_IN

Z_SCREW1

Z_SCREW2

Z_SCREW3

Z_SCREW4SCREW PANHEAD 4-40 x 3/8

SCREW PANHEAD 4-40 x 3/8

SCREW PANHEAD 4-40 x 3/8

SCREW PANHEAD 4-40 x 3/8

Z_STANDOFF1

Z_STANDOFF2

Z_STANDOFF3

Z_STANDOFF4

STANDOFF ALUM HEX 4-40 x .500

STANDOFF ALUM HEX 4-40 x .500

STANDOFF ALUM HEX 4-40 x .500

STANDOFF ALUM HEX 4-40 x .500

+3.3V_LOGICFB868 OHM @ 100MHz
+

C82
10uF
10V

C83
1uF
20%
25V

C84
+
.01uF

C85
47uF
20%
10V

+3.3VCLK
FB9AA

68 OHM @ 100MHz
+

C88
10uF
10V

C86
1uF
20%
25V

C87
+
.01uF

C89
47uF
20%
10V
Title
Size

B
Date:
5

4

3

2

Document Number

DAC5682Z EVM

Rev

POWER DISTRIBUTION

Monday, August 04, 2008

Sheet
1

5

D
of

6

5

4

3

2

1

+5VA

1)

DNI = DO NOT INSTALL

2)

FOR DAC5681/81Z OPTION ALL
COMPONENTS ON SHEET 6 ARE DNISH1 IOUTB1

D

R146
115

C19
.01uF DNI

R137

R165

0

0

R149
115

1

L12

R138

2
68nH

60.4

2

NOTES:

C112
2.2pF
DNI

C110
2.7pF

2

R41
90.9

C26

L15
10nH

.01uF DNISH1 IOUTB2

R166

0

0

1

L13

R151

2

60.4

68nH

R148
634

1

R153

D

C100
4.7pF
DNI

1

L14
10nH

C101
4.7pF
DNI

R147
634

R145
0

R142
0

+5VA
FB10
+ C115
4.7uF
20V

C

C104
1000pF

C114
.1uF

C99
3.3pF

+5VA
FB11

+

25
24
23
22
21
20
19

68 ohm @ 100MHz

SMA

1
22pF

R139

C103

NC3
GND
QN
QP
GND
GND

49.9

22pF

7
8
9
10
11
12

VCCI
GND
RFOUT
U8
NC5
TRF3703-33
GND
NC4

4
3
2
5

END

NC1
GND
LOP
LON
GND
NC2

PWRPAD
VCC2
GND
IN
IP
GND
GND

1
2
3
4
5
6

C102
J23
RF_LO_IN

C109
3.3pF

18
17
16
15
14
13

C107
.1uF

C106
1000pF

C108
4.7uF
20V

68 ohm @ 100MHz

C113

1

SMA
END

C118
.01uF
DNI

100pF

C117
.01uF
DNI

J16
RFOUT

4
3
2
5

C

+5VA
B

B

R157
115

R158
115

C28

R141
0

R140
0

.01uF DNI
R168

0

0

SH1 IOUTA1

L10

1

R152

2
68nH

60.4

2

R155

C111
2.7pF

C105
2.2pF
DNI

2

R150
90.9

C30

L8
10nH

R156

R167

0

0

SH1 IOUTA2
R144
634

L11

1

R154

2
68nH

60.4

R143
634

1

.01uF DNI
A

C116
4.7pF
DNI

1

L9
10nH

A

C73
4.7pF
DNI
Title
Size

Document Number

DAC5682Z EVM

B
Date:
5

4

3

2

Friday, August 22, 2008

Rev

MODULATOR
Sheet
1

D
6

of

6

EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must haveelectronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be completein terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental
measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does
not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days fromthe date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER
AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY
INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents orservices described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This
notice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/or
safety programs, please contact the TI application engineer or visit www.ti.com/esh.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used.

FCC WarningThis evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radio
frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which aredesigned to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may
cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may
be required to correct this interference.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2008, Texas Instruments Incorporated

EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 1.8 V to 5.0 V and the output voltage range of 0.0 V to 3.3 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions
concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 60° C. The EVM is designed to operateproperly with certain components above 60° C as long as the input and output ranges are maintained. These components include but are
not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified
using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation,please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2008, Texas Instruments Incorporated

IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products andapplications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or awarranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompaniedby all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
Logic
Power Mgmt
Microcontrollers
RFID
RF/IF and ZigBee® Solutions

amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf

Applications
Audio
Automotive
Broadband
Digital Control
MedicalMilitary
Optical Networking
Security
Telephony
Video & Imaging
Wireless

www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2008, Texas Instruments Incorporated