UCC21520-Q1
SLUSCQ2E – OCTOBER 2017 – REVISED JUNE 2024

UCC21520-Q1 4A, 6A, 5.7kVRMS Isolated Dual-Channel Gate Driver for Automotive
1 Features

3 Description••

The UCC21520-Q1 is an isolated dual-channel gate
driver with 4A source and 6A sink peak current. It is
designed to drive power MOSFETs, IGBTs, and SiC
MOSFETs up to 5MHz.

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Qualified for automotive applications
AEC-Q100 qualified with the following results:– Device temperature grade 1
Functional safety quality-managed– Documentation available to aid functional safetysystem design
Junction temperature range –40 to +150°C
Switching parameters:– 33ns typical propagation delay– 20ns minimum pulse width– 6ns maximum pulse-width distortion
Common-mode transient immunity (CMTI) greaterthan 125V/ns
Surge immunity up to 10kV
Isolation barrier life >40 years
4A peak source, 6A peak sink output
3V to 18V input VCCI range to interface with both
digital and analog controllers
Up to 25V VDD output drive supply– 5V and 8V VDD UVLO options
Programmable overlap and dead time
Fast disable for power sequencing
Safety-related certifications:– 8000VPK reinforced Isolation per DIN EN IEC
60747-17 (VDE 0884-17)– 5.7kVRMS isolation for 1 minute per UL 1577
– CSA certification per IEC 60950-1, IEC
62368-1, IEC 61010-1 and IEC 60601-1 end
equipment standards– CQC certification per GB4943.1-2022

The input side is isolated from the two output
drivers by a 5.7kVRMS reinforced isolation barrier,with a minimum of 125V/ns common-mode transient
immunity (CMTI). Internal functional isolation between
the two secondary-side drivers allows a working
voltage of up to 1500VDC.
Every driver can be configured as two low-side
drivers, two high-side drivers, or a half-bridge driverwith programmable dead time (DT). A disable pin
shuts down both outputs simultaneously , and allows
normal operation when left open or grounded. Asa fail-safe measure, primary-side logic failures force
both outputs low.
Each device accepts VDD supply voltages up to 25V.
A wide input VCCI range from 3V to 18V makes thedriver suitable for interfacing with both analog anddigital controllers. All supply voltage pins have undervoltage lock-out (UVLO) protection.
With all these advanced features, the UCC21520Q1 enables high efficiency, high power density, androbustness.
Device Comparison
PACKAGE(1)UVLO Level

UCC21520-Q1

DW (SOIC 16)

8V

2 Applications

UCC21520A-Q1

DW (SOIC 16)

5V

•
•

(1)

For all available packages, see Section 13.

VCCI 3,8

16 VDDA
Driver

INA

1

DIS

5

NC

7

DT

6

MOD

DEMOD

Reinforced Isolation•

HEV and BEV battery chargers
Isolated converters in DC-DC and AC-DC power
supplies
Uninterruptible power supply (UPS)PART NUMBER

Disable,UVLO
andDeadtime

UVLO

15 OUTA

14 VSSA
13 NC
Functional Isolation

12 NC
11 VDDB

Driver
INB

2

GND

4

MOD

DEMOD

UVLO

10 OUTB

9VSSB

Copyright © 2017, Texas Instruments Incorporated

Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 ESD Ratings (Automotive).......................................... 4
5.3 Recommended Operating Conditions.........................4
5.4 Thermal Information....................................................4
5.5 Power Ratings.............................................................5
5.6 Insulation Specifications............................................. 6
5.7 Safety Limiting Values.................................................7
5.8 Electrical Characteristics.............................................7
5.9 Timing Requirements ................................................. 8
5.10 Switching Characteristics..........................................8
5.11 Insulation Characteristics Curves..............................95.12 Typical Characteristics............................................ 10
6 Parameter Measurement Information.......................... 14
6.1 Propagation Delay and Pulse Width Distortion......... 14
6.2 Rising and Falling Time.............................................14
6.3 Input and Disable Response Time............................ 14
6.4 Programable Dead Time........................................... 15
6.5 Power-up UVLO Delay to OUTPUT..........................15
6.6 CMTI Testing.............................................................162

7 Detailed Description......................................................17
7.1 Overview................................................................... 17
7.2 Functional Block Diagram......................................... 17
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................22
8 Application and Implementation.................................. 25
8.1 Application Information............................................. 25
8.2 Typical Application.................................................... 25
9 Power Supply Recommendations................................37
10 Layout...........................................................................38
10.1 Layout Guidelines................................................... 38
10.2 Layout Example...................................................... 39
11 Device and Documentation Support..........................41
11.1 Third-Party Products Disclaimer............................. 41
11.2 Documentation Support.......................................... 41
11.3 Certifications........................................................... 41
11.4 Receiving Notification of Documentation Updates.. 41
11.5 Support Resources................................................. 41
11.6 Trademarks............................................................. 41
11.7 Electrostatic Discharge Caution.............................. 41
11.8 Glossary.................................................................. 41
12 Revision History.......................................................... 42
13 Mechanical, Packaging, and Orderable
Information.................................................................... 43

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4 Pin Configuration and Functions
INA

1

16

VDDA

INB

2

15

OUTA

VCCI

3

14

VSSA

GND

4

13

NC

DISABLE

5

12

NC

DT

6

11

VDDB

NC

7

10

OUTB

VCCI

8

9

VSSB

Not to scale

Figure 4-1. DW Package 16-Pin SOIC Top View
Table 4-1. Pin Functions
PIN
NAME

NO.

DISABLE

5

TYPE(1)DESCRIPTIONIDisables both driver outputs if asserted high, enables if set low or left open. This pin is pulled
low internally if left open. It is recommended to tie this pin to ground if not used to achieve
better noise immunity. Bypass using a ≈1nF low ESR/ESL capacitor close to DIS pin whenconnecting to a micro controller with distance.

DT

6

I

Programmable dead time function.
Tying DT to VCCI allows the outputs to overlap. Placing a 2-kΩ to 500-kΩ resistor (RDT)
between DT and GND adjusts dead time according to: DT (in ns) = 10 x RDT (in kΩ). It is
recommended to parallel a ceramic capacitor, <1nF, close to the DT pin with RDT to achieve
better noise immunity. It is not recommended to leave DT floating.

GND

4

P

Primary-side ground reference. All signals in the primary side are referenced to this ground.

INA

1

I

Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin
is pulled low internally if left open. It is recommended to tie this pin to ground if not used toachieve better noise immunity.

INB

2

I

Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin
is pulled low internally if left open. It is recommended to tie this pin to ground if not used toachieve better noise immunity.

NC

7

–

No Internal connection.

NC

12

–

No internal connection.

NC

13

–

No internal connection.

OUTA

15

O

Output of driver A. Connect to the gate of the A channel FET or IGBT.

OUTB

10

O

Output of driver B. Connect to the gate of the B channel FET or IGBT.

VCCI

3

P

Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor
located as close to the device as possible.

VCCI

8

P

Primary-side supply voltage. This pin is internally shorted to pin 3.

VDDA

16

P

Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL
capacitor located as close to the device as possible.

VDDB

11

P

Secondary-side power for driver B. Locally decoupled to VSSB using low ESR/ESL
capacitor located as close to the device as possible.

VSSA

14

P

Ground for secondary-side driver A. Ground reference for secondary side A channel.

VSSB

9

P

Ground for secondary-side driver B. Ground reference for secondary side B channel.

(1)

P = Power, G = Ground, I = Input, O = Output

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN

MAX

UNIT

Input bias pin supply voltage

VCCI to GND

–0.3

20

V

Driver bias supply

VDDA-VSSA, VDDB-VSSB

–0.3

30

V

OUTA to VSSA, OUTB to VSSB

–0.3 VDDA/B + 0.3

V–2 VDDA/B + 0.3

VOutput signal voltage

OUTA to VSSA, OUTB to VSSB, Transient for 200 ns

Input signal voltage
Junction temperature, TJ

INA, INB, DIS, DT to GND–0.3

VCCI + 0.3

V

INA, INB Transient for 50ns

–5

VCCI + 0.3

V

–40

150

℃

–65

150

℃

(2)

Storage temperature, Tstg
(1)

(2)

Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stressratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicatedunder Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
To maintain the recommended operating conditions for TJ, see the Section 6.4

5.2 ESD Ratings (Automotive)
VALUE
V(ESD)(1)

Electrostatic discharge

Human body model (HBM), per AEC Q100-002(1)±2000

Charged device model (CDM), per AEC Q100-011

±1000

UNIT
V

AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCCI

MIN

MAX

UNIT

VCCI Input supply voltage

3

18

V

Driver output bias supply

UCC21520A 5-V
UVLO version

6.5

25

V

VDDA,
VDDB

Driver output bias supply

UCC21520 8-V
UVLO version

9.2

25

V

TJ

Junction temperature

–40

150

℃

VDDA,
VDDB

5.4 Thermal Information
THERMAL METRIC(1)UCC21520-Q1
DW-16 (SOIC)

UNIT

RθJA

Junction-to-ambient thermal resistance

69.8

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

33.1

°C/W

RθJB

Junction-to-board thermal resistance

36.9

°C/W

ΨJT

Junction-to-top(center) characterization parameter

22.2

°C/W

ΨJB

Junction-to-board characterization parameter

36

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

4

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5.5 Power Ratings
PARAMETERPD

Maximum power dissipation (both sides)

PDI

Maximum power dissipation bytransmitter side

PDA, PDB

Maximum power dissipation by eachdriver side

TEST CONDITIONSVCCI = 5V, VDDA/VDDB = 20V, INA/B= 3.3V, 460kHz 50% duty cycle squarewave, CL=2.2nF, TJ=150℃, TA=25℃

MIN

TYP

MAX

UNIT

950

mW

50

mW

450

mW

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5.6 Insulation Specifications
PARAMETERTEST CONDITIONSSPECIFIC
ATION

UNIT

GeneralExternal clearance(1)Shortest terminal-to-terminal distance through air >8

mm

CPG

External Creepage(1)Shortest terminal-to-terminal distance across the
package surface

>8

mm

DTI

Distance through the insulation

Minimum internal gap (internal clearance)

>17

µm

CTI

Comparative tracking index

DIN EN 60112 (VDE 0303-11); IEC 60112

> 600

V

Material Group

According to IEC 60664-1

I

Rated mains voltage ≤ 600 VRMS

I-IV

Rated mains voltage ≤ 1000 VRMS

I-III

Maximum repetitive peak isolation voltage

AC voltage (bipolar)

2121

VPK

Maximum isolation working voltage

AC voltage (sine wave); time-dependent dielectric
1500
breakdown (TDDB) test

VRMS

DC voltage

2121

VDC

CLR

Overvoltage category IEC 60664-1
DIN EN IEC 60747-17 (VDE 0884-17)
VIORM
VIOWM

(2)

VIMP

Maximum inpulse voltage

Tested in air, 1.2/50-µs waveform per IEC
62368-1

7692

VPK

VIOTM

Maximum transient isolation voltage

VTEST = VIOTM, t = 60 s (qualification)
VTEST = 1.2 × VIOTM, t = 1 s (100% production)

8000

VPK

VIOSM

Maximum surge isolation voltage(3)VIOSM ≥ 1.3 x VIMP; Tested in oil (qualificationtest), 1.2/50-μs waveform per IEC 62368-1

10000

VPK

Method a: After I/O safety test subgroup 2/3, Vini
= VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10s≤5Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm =
10 s

≤5

Apparent charge(4)

qpd

pC

Method b1: At routine test (100% production) andpreconditioning (type test), Vini = 1.2 × VIOTM, tini ≤5= 1 s; Vpd(m) = 1.875 × VIORM , tm = 1 sBarrier capacitance, input to output(5)CIO

Insulation resistance, input to output(5)RIO

VIO = 0.4 × sin (2πft), f = 1 MHz~1.2

VIO = 500 V, TA = 25°C

>1012

VIO = 500 V, 100°C ≤ TA ≤ 125°C>1011

VIO = 500 V at TS = 150°C>109

Pollution degree

2

Climatic category

40/125/21

pFΩ

UL 1577
VISO(1)

Withstand isolation voltage

VTEST = VISO = 5700 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100%5700
production)

VRMS

(3)
(4)
(5)

Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of theisolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equalin certain cases. Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these
specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-pin device.

6

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5.7 Safety Limiting Values
PARAMETER

IS

Safety output supply current

PS

Safety supply power

SIDE

Rθ JA = 69.8°C/W, VDDA/B = 15 V, TJ =150°C, TA = 25°C

DRIVERA,
DRIVER
B

58

INPUT

50

DRIVERA

870

DRIVER
B

870

TOTAL

1790

Rθ JA = 69.8°C/W, VDDA/B = 25 V, TJ =150°C, TA = 25°C

Rθ JA = 69.8°C/W, TJ = 150°C, TA =
25°C

MIN

TYP

MAX

UNIT

mA
34

mW

Maximum safety temperature(1)TS(1)

TEST CONDITIONS

150

°C

The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ , specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RqJA, in the Thermal Informationtable is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value
for each parameter: TJ = TA + RqJA ´ P, where P is the power dissipated in the device. TJ(max) = TS = TA + RqJA ´ PS, where TJ(max) is the
maximum allowed junction temperature. PS = IS ´ VI , where VI is the maximum supply voltage.

5.8 Electrical Characteristics
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, TJ = –40°C to +150°C, unless otherwise noted
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENTS
IVCCIVCCI quiescent current

VINA = 0 V, VINB = 0 V

1.4

2.0

mA

IVDDA, IVDDBVDDA and VDDB quiescent current

VINA = 0 V, VINB = 0 V

1.0

2.5

mA

IVCCI

VCCI operating current(f = 500 kHz) current per channel

3

3.5

mA

VDDA and VDDB operating current(f = 500 kHz) current per channel, COUT
= 100 pF

2.5

4.2

mA

IVDDA, IVDDBVCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDSVVCCI_ONUVLO Rising threshold

2.55

2.7

2.85

V

VVCCI_OFFUVLO Falling threshold

2.35

2.5

2.65

V

VVCCI_HYSUVLO Threshold hysteresis

0.2

V

VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDSVVDDA_ON,VVDDB_ONUVLO Rising threshold

5-V UVLO

5.7

6.0

6.3

V

VVDDA_OFF,VVDDB_OFFUVLO Falling threshold

5-V UVLO

5.4

5.7

6.0

V

VVDDA_HYS,VVDDB_HYSUVLO Threshold hysteresis

5-V UVLOVVDDA_ON,VVDDB_ONUVLO Rising threshold

8-V UVLO

7.7

8.5

8.9

V

VVDDA_OFF,VVDDB_OFFUVLO Falling threshold

8-V UVLO

7.2

7.9

8.4

V

VVDDA_HYS,VVDDB_HYSUVLO Threshold hysteresis

8-V UVLO

0.3

V

0.6

V

INA, INB AND ENABLE
VINAH, VINBH, VENH

Input high threshold voltage

1.2

1.8

2

V

VINAL, VINBL, VENL

Input low threshold voltage

0.8

1

1.2

V

VINA_HYS, VINB_HYS,
VEN_HYS

Input threshold hysteresis

VINA, VINB

Negative transient, ref to GND, 100
ns pulse

0.8
Not production tested, bench test only

–5

V
V

OUTPUT

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5.8 Electrical Characteristics (continued)
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, TJ = –40°C to +150°C, unless otherwise noted
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

IOA+, IOB+Peak output source current

CVDD = 10 µF, CLOAD = 0.18 µF, f = 1
kHz, bench measurement

4A

IOA-, IOB-Peak output sink current

CVDD = 10 µF, CLOAD = 0.18 µF, f = 1
kHz, bench measurement

6A

ROHA, ROHB

Output resistance at high state

IOUT = –10 mA, TA = 25°C, ROHA,ROHB do not represent drive pull-up
performance. See tRISE in Section 5.10
and Section 7.3.4 for details.

5Ω

ROLA, ROLB

Output resistance at low state

IOUT = 10 mA, TA = 25°C

0.55

Ω

VOHA, VOHB

Output voltage at high state

VVDDA, VVDDB = 15 V, IOUT = –10 mA, TA= 25°C

14.95

V

VOLA, VOLB

Output voltage at low state

VVDDA, VVDDB = 15 V, IOUT = 10 mA, TA= 25°C

5.5mV

5.9 Timing Requirements
DEADTIME AND OVERLAP PROGRAMMING

MIN

NOM

MAX

UNIT

OvelapOvelapdetermined determinedby INA, INB by INA, INB

Ovelapdeterminedby INA, INB

nsDT

DT pin tied to VCCIDT

Dead time, RDT = 10 kΩ

80

100

120

ns

DT

Dead time, RDT = 20 kΩ

160

200

240

ns

DT

Dead time, RDT = 50 kΩ

400

500

600

ns

5.10 Switching Characteristics
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB
to VSSA and VSSB, load capacitance COUT = 0 pF, TJ = –40°C to +150°C. (over recommended operating conditions unlessotherwise noted)
PARAMETER

8

TYP

MAX

UNIT

COUT = 1.8 nF

6

16

ns

Output fall time, 90% to 10%
measured points

COUT = 1.8 nF

7

12

ns

tPWminMinimum pulse width

Output off for less thanminimum, COUT = 0pF

20

ns

tPDHL

Propagation delay from INx to OUTx
falling edges

26

33

45

ns

tPDLH

Propagation delay from INx to OUTx
rising edges

26

33

45

ns

6

ns

6.5

ns

tRISE

Output rise time, 20% to 80%
measured points

tFALL

TEST CONDITIONS

MIN

tPWD

Pulse width distortion |tPDLH – tPDHL|

tDM

Propagation Delay Matching for Dual
Channel Driver

Input Pulse Width = 100ns, 500kHz, TJ = -40°C to -10°C|tPDLHA – tPDLHB|, |tPDHLA – tPDHLB|

tDM

Propagation Delay Matching for Dual
Channel Driver

Input Pulse Width = 100ns, 500kHz, TJ = -10°C to+150°C|tPDLHA – tPDLHB|, |tPDHLA – tPDHLB|

5

ns

tVCCI+ to OUT

VCCI Power-up Delay Time: UVLO
Rise to OUTA, OUTBINA or INB tied to VCCI50

μs

tVDD+ to OUT

VDDA. VDDB Power-up Delay Time:UVLO Rise to OUTA, OUTBINA or INB tied to VCCI

10

μs

|CMH|

High-level common-mode transient
immunity (See Section 6.6)

Slew rate of GND versus VSSA/B, INA and INB both aretied to GND or VCCI; VCM = 1500V

125

V/ns

|CML|

Low-level common-mode transient
immunity (See Section 6.6)

Slew rate of GND versus VSSA/B, INA and INB both aretied to GND or VCCI; VCM = 1500V

125

V/ns

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5.11 Insulation Characteristics Curves
1.E+12
1.E+11
1.E+1054 Yrs

1.E+09Time to Fail (sec)

1.E+08TDDB Line (< 1 ppm Fail Rate)

1.E+07
1.E+06

VDE Safety Margin Zone

1.E+05

1.E+04
1.E+03
1.E+02
1800VRMS

1.E+01

200

1200

2200

3200

4200

5200

6200

Applied Voltage (VRMS)

60

1800

IVDDA/B for VDD=15V
IVDDA/B for VDD=25V

50

1600

Safety Limiting Power (mW)

Safety Limiting Current per Channel (mA)

Figure 5-1. Reinforced Isolation Capacitor Life Time Projection

40
30
20
10

1400
1200
1000
800
600
400
200
0

0
0

20

40

60
80
100
120
Ambient Temperature (°C)

140

160

Figure 5-2. Thermal Derating Curve for Safety-Related Limiting
Current (Current in Each Channel with Both Channels Running
Simultaneously)

0

20

40

60
80
100
120
Ambient Temperature (°C)

140

160

Figure 5-3. Thermal Derating Curve for Safety-Related Limiting
Power

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5.12 Typical Characteristics
VDDA = VDDB= 15 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.
50

17.5

45

15

40
35

Current (mA)

Current (mA)

12.5
10
7.5
5

0
100

1000 1500 2000 2500 3000 3500 4000 4500 5000
Frequency (kHz)

200

300

400 500 600 700
Frequency (kHz)12
10

Current (mA)

21
18
15
12
9

1000

500kHz1000kHz2000kHz3000kHz

8
6
4

6

2

VDD=15V
VDD=25V

3
20

30

40

50
60
70
Frequency (kHz)

80

90

0
-40

100

Figure 5-6. Per Channel Current Consumption (IVDDA/B) vs
Frequency (10-nF Load, VDD = 15 V or 25 V)

-20

0

20

40
60
80 100Temperature (°C)

120

140

160

Figure 5-7. Per Channel (IVDDA/B) Supply Current vs
Temperature (No Load, Different Switching Frequencies)

2

1.6

1.6

Current (mA)

1.5

1.2

0.8

1.4

1.3

0.4
VDD=15V
VDD=25V
-20

0

20

40
60
80 100Temperature (°C)

120

140

160

Figure 5-8. Per Channel (IVDDA/B) Quiescent Supply Current vs
Temperature (No Load, Input Low, No Switching)

10

900

14

24

0
-40

800

Figure 5-5. Per Channel Current Consumption (IVDDA/B) vs
Frequency (1-nF Load, VDD = 15 V or 25 V)

27Current (mA)

VDD=15V
VDD=25V

530

Current (mA)

20

10

VDD=15V
VDD=25V

Figure 5-4. Per Channel Current Consumption vs Frequency(No Load, VDD = 15 V or 25 V)

0
10

25

15

2.5
0
500

30

VCC=3.3V
VCC=5V
1.2
-40

-20

0

20

40
60
80 100Temperature (°C)

120

140

160

Figure 5-9. IVCCI Quiescent Supply Current vs Temperature (NoLoad, Input Low, No Switching)Submit Document Feedback

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5.12 Typical Characteristics (continued)

30

6

27.5

5.5

25

5

22.5

4.5

Resistance (Ohm)Time (ns)VDDA = VDDB= 15 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.

20
17.5
15
12.5
10

2

3

4

5
6
Load (nF)

7

8

9

3
2.5
2
1

5
1

4
3.5

1.5

tRise
tFall

7.5

0.5
-40

10

Figure 5-10. Rising and Falling Times vs Load (VDD = 15 V)

-20

0

20

40
60
80 100Temperature (°C)

140

160

36

Propagation Delay (ns)

36

32

28

24

34

32

30

Rising Edge (tPDLH)
Falling Edge (tPDHL)
20
-40

-20

0

20

40
60
80 100Temperature (°C)

120

140

Rising Edge (tPDLH)
Falling Edge (tPDHL)
28
3.2

160

Figure 5-12. Propagation Delay vs Temperature

3.6

3.8

4
4.2
VCCI (V)

4.4

4.6

4.8

5

Propagation Delay Matching (ns)

2

2
1
0
-1
-2
-3
-40

3.4

Figure 5-13. Propagation Delay vs VCCI

3

Pulse Width Distortion (ns)120

Figure 5-11. Output Resistance vs Temperature40

Propagation Delay (ns)Output Pull-Up
Output Pull-Down

-20

0

20

40
60
80 100Temperature (°C)

120

140

Figure 5-14. Pulse Width Distortion vs Temperature

160

1.5
1
0.5
0
-0.5
-1
Rising Edge
Falling Edge

-1.5
-2
15

16

17

18

19

20
21
VDD (V)

22

23

24

25

Figure 5-15. Propagation Delay Matching (tDM) vs VDD

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5.12 Typical Characteristics (continued)
VDDA = VDDB= 15 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.
0.8

1.5

0.7

1

UVLO Hysteresis (V)Propagation Delay Matching (ns)

2

0.5
0
-0.5
-1

-2
-40

-20

0

20

40
60
80
Temperature (°C)

100

120

0.4

0.2
-40

140

-20

0

20

40
60
80 100Temperature (°C)

120

140

160

Figure 5-17. VDD 5-V UVLO Hysteresis vs Temperature

Figure 5-16. Propagation Delay Matching (tDM) vs Temperature
8

1

VVDD_ONVVDD_OFF7

0.9

UVLO Hysteresis (V)UVLO Threshold (V)

0.5

0.3

Rising Edge
Falling Edge

-1.5

0.6

6

0.8
0.7
0.6

5
0.5

4
-40

-20

0

20

40
60
80 100Temperature (°C)

120

140

0.4
-40

160

-20

0

20

40
60
80 100Temperature (°C)

120

140

160

Figure 5-19. VDD 8-V UVLO Hysteresis vs Temperature

Figure 5-18. VDD 5-V UVLO Threshold vs Temperature
10

0.9

VVDD_ONVVDD_OFF
0.89

Hysteresis (V)UVLO Threshold (V)

9

8

7

VCC=3.3V
VCC=5V

-20

0

20

40
60
80 100Temperature (°C)

120

140

160

Figure 5-20. VDD 8-V UVLO Threshold vs Temperature

12

0.87

0.86

6

5
-40

0.88

0.85
-40

-20

0

20

40
60
80
Temperature (°C)

100

120

140

Figure 5-21. IN/DIS Hysteresis vs Temperature

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5.12 Typical Characteristics (continued)

1.2

2

1.14

1.92

IN/DIS High Threshold (V)IN/DIS Low Threshold (V)VDDA = VDDB= 15 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.

1.08

1.02

0.96

0.9
-40

VCC=3.3V
VCC= 5V
VCC=12V
-20

0

20

40
60
80
Temperature (qC)

100

120

1.84

1.76

1.68

1.6
-40

140

VCC=3.3V
VCC= 5V
VCC=12V
-20

0

20

D001

Figure 5-22. IN/DIS Low Threshold

40
60
80
Temperature (qC)

100

120

140
D001

Figure 5-23. IN/DIS High Threshold
5

1500

1200

-6

900

-17

'DT (ns)

Dead Time (ns)RDT= 20k:
RDT= 100k:

600

300

0
-40

-28

-39
RDT= 20k:
RDT = 100k:
-20

0

20

40
60
80
Temperature (qC)

100

120

140

-50
-40

-20

0

20

D001

Figure 5-24. Dead Time vs Temperature (with RDT = 20 kΩ and100 kΩ)40
60
80
Temperature (qC)

100

120

140
D001

Figure 5-25. Dead Time Matching vs Temperature (with RDT = 20kΩ and 100 kΩ)20
CL=2.2nF
CL=10nF

Voltage (V)

15

10

5

0

-5
0

100

200

300

400
500
Time (ns)

600

700

800

Figure 5-26. Typical Output Waveforms

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6 Parameter Measurement Information
6.1 Propagation Delay and Pulse Width Distortion
Figure 6-1 shows how one calculates pulse width distortion (tPWD) and delay matching (tDM) from the
propagation delays of channels A and B. It can be measured by ensuring that both inputs are in phase anddisabling the dead time function by shorting the DT Pin to VCC.

INA/B

tPDHLAtPDLHA

tDM

OUTA

tPDLHBtPDHLBtPWDB = |tPDLHB t tPDHLB|

OUTB

Figure 6-1. Overlapping Inputs, Dead Time Disabled

6.2 Rising and Falling Time
Figure 6-2 shows the criteria for measuring rising (tRISE) and falling (tFALL) times. For more information on how
short rising and falling times are achieved see Section 7.3.4.

80%
tRISE

90%
tFALL

20%
10%

Figure 6-2. Rising and Falling Time Criteria

6.3 Input and Disable Response Time
Figure 6-3 shows the response time of the disable function. It is recommended to bypass using a ≈1nF low
ESR/ESL capacitor close to DIS pin when connecting DIS pin to a micro controller with distance. For more
information, see Section 7.4.1.
INA

DIS High
Response TimeDISDIS Low
Response Time
OUTA
90%

90%

tPDLH

tPDHL
10%

10%

10%

Figure 6-3. Disable Pin Timing

14

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6.4 Programable Dead Time
Leaving the DT pin open or tying it to GND through an appropriate resistor (RDT) sets a dead-time interval. For
more details on dead time, refer to Section 7.4.2.

INA
INB

90%
OUTA

10%

tPDHL

tPDLH

90%

OUTB
10%

tPDHL

Dead Time(Set by RDT)

Dead Time(Determined by Input signals if
longer than DT set by RDT)

Figure 6-4. Dead-Time Switching Parameters

6.5 Power-up UVLO Delay to OUTPUT
Before the driver is ready to deliver a proper output state, there is a power-up delay from the UVLO rising edge
to output and it is defined as tVCCI+ to OUT for VCCI UVLO (typically 40us) and tVDD+ to OUT for VDD UVLO (Max10us). It is recommended to consider proper margin before launching PWM signal after the driver's VCCI and
VDD bias supply is ready. Figure 6-5 and Figure 6-6 show the power-up UVLO delay timing diagram for VCCIand VDD.
If INA or INB are active before VCCI or VDD have crossed above their respective on thresholds, the output will
not update until tVCCI+ to OUT or tVDD+ to OUT after VCCI or VDD crossing its UVLO rising threshold. However, wheneither VCCI or VDD receive a voltage less than their respective off thresholds, there is <2µs delay, depending on
the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay is designed toensure safe operation during VCCI or VDD brownouts.

VCCI,
INx

VDDx

VVCCI_ONVVCCI_OFF

VCCI,
INx

VDDx

tVCCI+ to OUT

OUTx

VVDD_ONtVDD+ to OUT

VVDD_OFF

OUTx

Figure 6-5. VCCI Power-up UVLO Delay

Figure 6-6. VDDA/B Power-up UVLO Delay

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6.6 CMTI Testing
Figure 6-7 is a simplified diagram of the CMTI testing configuration.
VCC

VDD

VCC

VCCI

GND

DIS

DT

VCCI

2

15

3

14

4

5

Reinforced Isolation

INB

16

1

Input Logic

INA

VDDA

OUTA

OUTA

VSSA

Functional
Isolation
11

6

10

8

9

VDDB

OUTB

OUTB

VSSB

GND

VSS
Common Mode Surge
Generator
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Figure 6-7. Simplified CMTI Testing Setup

16

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7 Detailed Description
7.1 Overview
In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers areoften placed between the output of control devices and the gates of power transistors. There are several
instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors.
This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V
logic signal capable of only delivering a few mA.
The UCC21520-Q1 is a flexible dual gate driver which can be configured to fit a variety of power supply andmotor drive topologies, as well as drive several types of transistors, including SiC MOSFETs. The UCC21520-Q1
has many features that allow it to integrate well with control circuitry and protect the gates it drives such as:
resistor-programmable dead time (DT) control, a DISABLE pin, and under voltage lock out (UVLO) for both input
and output voltages. The UCC21520-Q1 also holds its outputs low when the inputs are left open or when the
input pulse is not wide enough. The driver inputs are CMOS and TTL compatible for interfacing to digital andanalog power controllers alike. Each channel is controlled by its respective input pins (INA and INB), allowing fulland independent control of each of the outputs.

7.2 Functional Block Diagram

INA

1

16 VDDA
200 k
MOD

VCCI

DEMOD
UVLO

GND

4

DT

6

DIS

5

UVLO

Reinforced Isolation

VCCI 3,8

Deadtime
Control

DriverDeglitch
Filter

15 OUTA
14 VSSA
13 NC

Functional Isolation

12 NC
11 VDDB

200 k
MOD
INB

DEMOD
UVLO

2

DriverDeglitch
Filter

10 OUTB
9

VSSB

200 k
NC

7
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7.3 Feature Description
7.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)The UCC21520-Q1 has an internal undervoltage lock out (UVLO) protection feature on the supply circuit blocks
between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than VVDD_ON at device
start-up or lower than VVDD_OFF after start-up, the VDD UVLO feature holds the effected output low, regardless ofthe status of the input pins (INA and INB).
When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low byan active clamp circuit that limits the voltage rise on the driver outputs (Illustrated in Figure 7-1). In this condition,
the upper PMOS is resistively held off by RHi-Z while the lower NMOS gate is tied to the driver output through
RCLAMP. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS
device, typically around 1.5 V, when no bias power is available.

VDD
RHI_Z

OutputControl

OUT
RCLAMPRCLAMP is activatedduring UVLO

VSSFigure 7-1. Simplified Representation of Active Pulldown Feature
The VDD UVLO protection has a hysteresis feature (VVDD_HYS). This hysteresis prevents chatter when there isground noise from the power supply. Also this allows the device to accept small drops in bias voltage, which isbound to happen when the device starts switching and operating current consumption increases suddenly.
The input side of the UCC21520-Q1 also has an internal undervoltage lock out (UVLO) protection feature. The
device isn't active unless the voltage, VCCI, is going to exceed VVCCI_ON on start up. And a signal will cease
to be delivered when that pin receives a voltage less than VVCCI_OFF. And, just like the UVLO for VDD, there ishysteresis (VVCCI_HYS) to ensure stable operation.

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All versions of the UCC21520-Q1 can withstand an absolute maximum of 30 V for VDD, and 20 V for VCCI.
Table 7-1. UCC21520-Q1 VCCI UVLO Feature Logic
INPUTS

CONDITIONINAOUTPUTS
INB

OUTA

OUTB

VCCI-GND < VVCCI_ON during device start up

H

L

L

L

VCCI-GND < VVCCI_ON during device start up

L

H

L

L

VCCI-GND < VVCCI_ON during device start up

H

H

L

L

VCCI-GND < VVCCI_ON during device start up

L

L

L

L

VCCI-GND < VVCCI_OFF after device start up

H

L

L

L

VCCI-GND < VVCCI_OFF after device start up

L

H

L

L

VCCI-GND < VVCCI_OFF after device start up

H

H

L

L

VCCI-GND < VVCCI_OFF after device start up

L

L

L

L

Table 7-2. UCC21520-Q1 VDD UVLO Feature Logic
CONDITIONINPUTSOUTPUTS

INA

INB

OUTA

OUTB

VDD-VSS < VVDD_ON during device start up

H

L

L

L

VDD-VSS < VVDD_ON during device start up

L

H

L

L

VDD-VSS < VVDD_ON during device start up

H

H

L

L

VDD-VSS < VVDD_ON during device start up

L

L

L

L

VDD-VSS < VVDD_OFF after device start up

H

L

L

L

VDD-VSS < VVDD_OFF after device start up

L

H

L

L

VDD-VSS < VVDD_OFF after device start up

H

H

L

L

VDD-VSS < VVDD_OFF after device start up

L

L

L

L

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7.3.2 Input and Output Logic Table
Table 7-3. INPUT/OUTPUT Logic Table(1)Assume VCCI, VDDA, VDDB are powered up. See Section 7.3.1 for more information on UVLO operation modes.
INPUTSINAINBDISABLEOUTPUTS
OUTA

NOTE

OUTB

L

L

L or Left Open

L

L

L

H

L or Left Open

L

H

H

L

L or Left Open

H

L

H

H

L or Left OpenLL

DT is left open or programmed with RDT
DT pin pulled to VCCIIf Dead Time function is used, output transitions occur after thedead time expires. See Section 7.4.2

H

H

L or Left Open

H

H

Left Open

Left Open

L or Left Open

L

L

-

X

X

H

L

L

-

(1)

"X" means L, H or left open.

7.3.3 Input Stage
The input pins (INA, INB, and DIS) of the UCC21520-Q1 are based on a TTL and CMOS compatible inputthreshold logic that is totally isolated from the VDD supply voltage. The input pins are easy to drive withlogic-level control signals (such as those from 3.3-V micro-controllers), since the UCC21520-Q1 has a typicalhigh threshold (VINAH) of 1.8 V and a typical low threshold of 1 V, which vary little with temperature (see Figure
5-22, Figure 5-23). A wide hysterisis (VINA_HYS) of 0.8 V makes for good noise immunity and stable operation. If
any of the inputs are ever left open, internal pull-down resistors force the pin low. These resistors are typically
200 kΩ (see Section 7.2). However, it is still recommended to ground an input if it is not being used.
Since the input side of the UCC21520-Q1 is isolated from the output drivers, the input signal amplitude can belarger or smaller than VDD, provided that it doesn’t exceed the recommended limit. This allows greater flexibility
when integrating with control signal sources, and allows the user to choose the most efficient VDD for theirchosen gate. That said, the amplitude of any signal applied to INA or INB must never be at a voltage higher than
VCCI.

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7.3.4 Output StageThe UCC21520-Q1 output stages feature a pull-up structure which delivers the highest peak-source current
when it is most needed, during the Miller plateau region of the power-switch turn on transition (when the powerswitch drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-channel
MOSFET and an additional Pull-Up N-channel MOSFET in parallel. The function of the N-channel MOSFET is toprovide a brief boost in the peak-sourcing current, enabling fast turn on. This is accomplished by briefly turningon the N-channel MOSFET during a narrow instant when the output is changing states from low to high. The
on-resistance of this N-channel MOSFET (RNMOS) is approximately 1.47 Ω when activated.
The ROH parameter is a DC measurement and it is representative of the on-resistance of the P-channel device
only. This is because the Pull-Up N-channel device is held in the off state in DC condition and is turned on only
for a brief instant when the output is changing states from low to high. Therefore the effective resistance of the
UCC21520-Q1 pull-up stage during this brief turn-on phase is much lower than what is represented by the ROH
parameter. Therefore, the value of ROH belies the fast nature of the UCC21520-Q1's turn-on time.
The pull-down structure in the UCC21520-Q1 is simply composed of an N-channel MOSFET. The ROL
parameter, which is also a DC measurement, is representative of the impedance of the pull-down state in thedevice. Both outputs of the UCC21520-Q1 are capable of delivering 4-A peak source and 6-A peak sink current
pulses. The output voltage swings between VDD and VSS provides rail-to-rail operation, thanks to the MOS-out
stage which delivers very low drop-out.
To ensure robust and reliable operation of gate drivers, pay special attention to the minimum pulse width.
The minimum pulse width shown in the electrical characteristics table describes the minimum input pulse thatwould be passed to the output in an unloaded driver. This is dictated by the deglitch filter present in thedriver IC. An input ON or OFF pulse width longer than the maximum specification is needed to guarantee an
output state change and avoid potential shoot-through. With a loaded driver, extra precaution must be taken
to ensure robust operation of the system. During gate switching, if the output state changes before the drivercompletes each transition, a non-zero current switching event occurs. Combined with layout parasitics, non-zerocurrent switching can cause internal rail overshoot and EOS damage of the gate driver. Thus, a minimum
output width is needed for reliable system operation. This minimum output pulse width is dependent on several
factors: gate capacitance, VDD supply voltage, gate resistance, and PCB layout parasitics. The minimum pulse
width for robust operation might be magnitudes larger than the minimum pulse width shown in the electricalcharacteristics table. System-level study should be carried out to determine the minimum output pulse width
required for each system.

VDD
ROH
Input
SignalShootThroughPrevention
Circuitry

RNMOS
OUT
Pull UpROL

VSS
Figure 7-2. Output Stage

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7.3.5 Diode Structure in the UCC21520-Q1
Figure 7-3 illustrates the multiple diodes involved in the ESD protection components of the UCC21520-Q1. This
provides a pictorial representation of the absolute maximum rating for the device.
VCCI

VDDA

3,8

16

30 V
20 V
INA

1

INB

2

DIS

5

DT

6

20 V

15

OUTA

14

VSSA

11

VDDB

10

OUTB

30 V

4

9

GND

VSSB

Figure 7-3. ESD Structure

7.4 Device Functional Modes
7.4.1 Disable Pin
Setting the DISABLE pin high shuts down both outputs simultaneously. Grounding (or left open) the DISABLE
pin allows the UCC21520-Q1 to operate normally. The DISABLE response time is in the range of 20 ns and quite
responsive, which is as fast as propagation delay. The DISABLE pin is only functional (and necessary) when
VCCI stays above the UVLO threshold. It is recommended to tie this pin to ground if the DISABLE pin is not
used to achieve better noise immunity, and it is recommended to bypass using a ≈1-nF low ESR/ESL capacitor
close to DIS pin when connecting DIS pin to a micro controller with distance.

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7.4.2 Programmable Dead-Time (DT) Pin
The UCC21520-Q1 allows the user to adjust dead time (DT) in the following ways:
7.4.2.1 Tying the DT Pin to VCC

Outputs completely match inputs, so no dead time is asserted. This allows outputs to overlap.
7.4.2.2 DT Pin Connected to a Programming Resistor Between DT and GND Pins

One can program tDT by placing a resistor, RDT, between the DT pin and GND. The appropriate RDT value canbe determined from Equation 1, where RDT is in kΩ and tDT is in ns:
tDT » 10 ´ RDT(1)The steady state voltage at DT pin is around 0.8 V, and the DT pin current will be less than 10uA when
RDT=100kΩ. When using RDT> 5kΩ, it is recommended to parallel a ceramic capacitor, <1nF, close to thechip with RDT to achieve better noise immunity and better dead time matching between two channels. It is notrecommended to leave the DT pin floating.
An input signal’s falling edge activates the programmed dead time for the other signal. The output signals’ deadtime is always set to the longer of either the driver’s programmed dead time or the input signal’s own dead time.
If both inputs are high simultaneously, both outputs will immediately be set low. This feature is used to prevent
shoot-through, and it doesn’t affect the programmed dead time setting for normal operation. Various driver deadtime logic operating conditions are illustrated and explained in:
INA

INB

DT
OUTA

OUTB

A

B

C

D

E

F

Figure 7-4. Input and Output Logic Relationship With Input Signals
Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed deadtime to OUTA. OUTA is allowed to go high after the programmed dead time.
Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed
dead time to OUTB. OUTB is allowed to go high after the programmed dead time.
Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed deadtime for OUTA. In this case, the input signal’s own dead time is longer than the programmed dead time. Thus,
when INA goes high, it immediately sets OUTA high.
Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed deadtime to OUTB. INB’s own dead time is longer than the programmed dead time. Thus, when INB goes high, it
immediately sets OUTB high.
Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, INA immediately pulls
OUTB low and keeps OUTA low. After some time OUTB goes low and assigns the programmed dead time to
OUTA. OUTB is already low. After the programmed dead time, OUTA is allowed to go high.
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Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, INB immediately pulls
OUTA low and keeps OUTB low. After some time OUTA goes low and assigns the programmed dead time to
OUTB. OUTA is already low. After the programmed dead time, OUTB is allowed to go high.

24

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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible fordetermining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information
The UCC21520-Q1 effectively combines both isolation and buffer-drive functions. The flexible, universal
capability of the UCC21520-Q1 (with up to 18-V VCCI and 25-V VDDA/VDDB) allows the device to be used
as a low-side, high-side, high-side/low-side or half-bridge driver for MOSFETs, IGBTs or SiC MOSFETs. With
integrated components, advanced protection features (UVLO, dead time, and disable) and optimized switching
performance; the UCC21520-Q1 enables designers to build smaller, more robust designs for enterprise,
telecom, automotive, and industrial applications with a faster time to market.

8.2 Typical Application
The circuit in Figure 8-1 shows a reference design with the UCC21520-Q1 driving a typical half-bridge
configuration which could be used in several popular power converter topologies such as synchronous buck,synchronous boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications.
VDD
VCC

RBOOT

VCC

INB

C

VCCI

CIN
CVCC

GND
AnalogorDigitalDIS

Disable

RDIS

1nF

DT

16

2

15

VDDA

ROFF

OUTA

RON
CBOOT

3

4

5

6

14
SW
Functional
Isolation

VDD
11

10

VDDB

ROFF

OUTB

RON
CVDD

VCCI

RDT

8

CIN
RGS

VSSA
Reinforced Isolation

RIN
PWM-B

1

Input Logic

INA

PWM-A

HV DC-Link

VSSB

RGS

9
VSS

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Figure 8-1. Typical Application Schematic

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8.2.1 Design Requirements
Table 8-1 lists reference design parameters for the example application: UCC21520-Q1 driving 1200-V SiCMOSFETs in a high side-low side configuration.
Table 8-1. UCC21520-Q1 Design Requirements
PARAMETER

VALUE

UNITS

Power transistor

C2M0080120D

-

VCC

5.0

V

VDD

20

V

Input signal amplitude

3.3

V

Switching frequency (fs)

100

kHz

DC link voltage

800

V

8.2.2 Detailed Design Procedure
8.2.2.1 Designing INA/INB Input Filter

It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay)
the signal at the output. However, a small input RIN-CIN filter can be used to filter out the ringing introduced by
non-ideal layout or long PCB traces.
Such a filter should use an RIN in the range of 0 Ω to100 Ω and a CIN between 10 pF and 100 pF. In theexample, an RIN = 51 Ω and a CIN = 33 pF are selected, with a corner frequency of approximately 100 MHz.
When selecting these components, it is important to pay attention to the trade-off between good noise immunityand propagation delay.
8.2.2.2 Select External Bootstrap Diode and its Series Resistor

The bootstrap capacitor is charged by VDD through an external bootstrap diode every cycle when the low sidetransistor turns on. Charging the capacitor involves high-peak currents, and therefore transient power dissipationin the bootstrap diode may be significant. Conduction loss also depends on the diode’s forward voltage drop.
Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate drivercircuit.
When selecting external bootstrap diodes, it is recommended that one chose high voltage, fast recovery diodes
or SiC Schottky diodes with a low forward voltage drop and low junction capacitance in order to minimize theloss introduced by reverse recovery and related grounding noise bouncing. In the example, the DC-link voltage
is 800 VDC. The voltage rating of the bootstrap diode should be higher than the DC-link voltage with a good
margin. Therefore, a 1200-V SiC diode, C4D02120E, is chosen in this example.
When designing a bootstrap supply, it is recommended to use a bootstrap resistor, RBOOT. A bootstrap resistor,
is also used to reduce the inrush current in DBOOT and limit the ramp up slew rate of voltage of VDDA-VSSA
during each switching cycle.
Failure to limit the voltage to VDDx-VSSx to less than the Absolute Maximum Ratings of the FET and UCC21520
may result in permanent damage to the device in certain cases.
The recommended value for RBOOT is between 1 Ω and 20 Ω depending on the diode used. In the example, acurrent limiting resistor of 2.2 Ω is selected to limit the inrush current of bootstrap diode. The estimated worst
case peak current through DBoot is,
IDBoot pk

VDD VBDF
RBoot

20V 2.5V
| 8A
2.2:

(2)

where
•

26

VBDF is the estimated bootstrap diode forward voltage drop at 8 A.
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8.2.2.3 Gate Driver Output Resistor

The external gate driver resistors, RON/ROFF, are used to:
1.
2.
3.
4.

Limit ringing caused by parasitic inductances/capacitances.
Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.
Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss.
Reduce electromagnetic interference (EMI).

As mentioned in Section 7.3.4, the UCC21520-Q1 has a pull-up structure with a P-channel MOSFET and an
additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peaksource current can be predicted with:

IOA

IOB

§
·
VDD VBDF
min ¨ 4A,¸¨
RNMOS || ROH RON RGFET _ Int ¸¹
©

(3)

§
VDD
min ¨ 4A,
¨
R
||
R
RON
NMOS
OH
©

(4)

·
¸
RGFET _ Int ¸¹

where
•
•
•

RON: External turn-on resistance.
RGFET_INT: Power transistor internal gate resistance, found in the power transistor datasheet.
IO+ = Peak source current – The minimum value between 4 A, the gate driver peak source current, and thecalculated value based on the gate drive loop resistance.

In this example:

IOA

IOB

VDD VBDFRNMOS || ROH RON RGFET _ Int

20V 0.8V| 2.4A
1.47: || 5: 2.2: 4.6:

(5)

VDD
RNMOS || ROH RON

20V
1.47: || 5: 2.2:

(6)

RGFET _ Int

4.6:| 2.5A

Therefore, the high-side and low-side peak source current is 2.4 A and 2.5 A respectively. Similarly, the peaksink current can be calculated with:

IOA

IOB

§
·
VDD VBDF VGDF
min ¨ 6A,¸¨
ROL ROFF || RON RGFET _ Int ¸¹
©

(7)

§
min ¨ 6A,
¨
ROL
©

(8)

·
VDD VGDF¸
ROFF || RON RGFET _ Int ¸¹

where
•
•
•

ROFF: External turn-off resistance;
VGDF: The anti-parallel diode forward voltage drop which is in series with ROFF. The diode in this example isan MSS1P4.
IO-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated
value based on the gate drive loop resistance.

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In this example,

VDD VBDF VGDF
ROL ROFF || R ON R GFET _ Int

IOA

IOB

ROL

VDD VGDF
ROFF || R ON RGFET _ Int

20V 0.8V 0.75V| 3.6A
0.55: 0: 4.6:

(9)

20V-0.75V| 3.7A
0.55: 0: 4.6:

(10)

Therefore, the high-side and low-side peak sink current is 3.6 A and 3.7 A respectively.
Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic
inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot andundershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other
hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (CISS) of thepower transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close
to the parasitic ringing period.
Failure to control OUTx voltage to less than the Absolute Maximum Ratings in the datasheet (includingtransients) may result in permanent damage to the device in certain cases. To reduce excessive gate ringing,
it is recommended to use a ferrite bead near the gate of the FET. External clamping diodes can also be addedin the case of extended overshoot/undershoot, in order to clamp the OUTx voltage to the VDDx and VSSx
voltages.
8.2.2.4 Gate to Source Resistor Selection

A gate to source resistor, RGS, is recommended to pull down the gate to the source voltage when the gate driver
output is unpowered and in an indeterminate state. This resistor also helps to mitigate the risk of dv/dt induced
turn-on due to Miller current before the gate driver is able to turn on and actively pull low. This resistor is typically
sized between 5.1kΩ and 20kΩ, depending on the Vth and ratio of CGD to CGS of the power device.
8.2.2.5 Estimate Gate Driver Power Loss

The total loss, PG, in the gate driver subsystem includes the power losses of the UCC21520-Q1 (PGD) andthe power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is notincluded in PG and not discussed in this section.
PGD is the key power loss which determines the thermal safety-related limits of the UCC21520-Q1, and it can be
estimated by calculating losses from several components.
The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as wellas driver self-power consumption when operating with a certain switching frequency. PGDQ is measured on thebench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency andambient temperature. Figure 5-4 shows the per output channel current consumption vs operating frequency
with no load. In this example, VVCCI = 5 V and VVDD = 20 V. The current on each power supply, with INA/INB
switching from 0 V to 3.3 V at 100 kHz is measured to be IVCCI = 2.5 mA, and I VDDA = IVDDB = 1.5 mA. Therefore,
the PGDQ can be calculated withPGDQ

VVCCI u IVCCIVVDDA u IDDAVVDDB u IDDB | 72mW

(11)

The second component is switching operation loss, PGDO, with a given load capacitance which the drivercharges and discharges the load during each switching cycle. Total dynamic loss due to load switching, PGSW,
can be estimated withPGSW

2 u VDD u QG u fSW

(12)

where
28

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QG is the gate charge of the power transistor.

If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive railto the negative rail.
So, for this example application:

PGSW

2 u 20V u 60nC u 100kHz

240mW

(13)

QG represents the total gate charge of the power transistor switching 800 V at 20 A, and is subject to changewith different testing conditions. The UCC21520-Q1 gate driver loss on the output stage, PGDO, is part of PGSW.
PGDO will be equal to PGSW if the external gate driver resistances are zero, and all the gate driver loss isdissipated inside the UCC21520-Q1. If there are external turn-on and turn-off resistances, the total loss will
be distributed between the gate driver pull-up/down resistances and external gate resistances. Importantly, thepull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A,
however, it will be non-linear if the source/sink current is saturated. Therefore, PGDO is different in these two
scenarios.
Case 1 - Linear Pull-Up/Down Resistor:PGDOPGSW §
ROH || RNMOSu¨¨ ROH || RNMOS RON RGFET _ Int
2
©

ROL

·
ROL
¸
ROFF || RON RGFET _ Int ¹¸(14)In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC21520-Q1
gate driver loss can be estimated with:

PGDO

240mW §
5: || 1.47:u¨
2© 5: || 1.47: 2.2: 4.6:·
0.55:
¸ | 30mW
0.55: 0: 4.6: ¹(15)

Case 2 - Nonlinear Pull-Up/Down Resistor:

PGDO

TR _ Sysª
2 u fSW u « 4A u ³ VDD
0
¬«

º
V
t
dt
»
OUTA/B³0¼»

TF _ Sys

VOUTA/B t dt

6A u

(16)

where
•

VOUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be
simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load
capacitor. Then, the VOUTA/B(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted.

For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the
PGDO will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up
and pull-down based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver
UCC21520-Q1, PGD, is:

PGD

PGDQ

PGDO

(17)

which is equal to 102 mW in the design example.
8.2.2.6 Estimating Junction Temperature

The junction temperature (TJ) of the UCC21520-Q1 can be estimated with:

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where
•
•

TC is the UCC21520-Q1 case-top temperature measured with a thermocouple or some other instrument, andΨJT is the Junction-to-top characterization parameter from the Thermal Information table.

Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance(RΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermalenergy of most ICs is released into the PCB through the package leads, whereas only a small percentage of thetotal energy is released through the top of the case (where thermocouple measurements are usually conducted).
RΘJC can only be used effectively when most of the thermal energy is released through the case, such as withmetal packages or when a heatsink is applied to an IC package. In all other cases, use of RΘJC will inaccurately
estimate the true junction temperature. ΨJT is experimentally derived by assuming that the amount of energy
leaving through the top of the IC will be similar in both the testing environment and the application environment.
As long as the recommended layout guidelines are observed, junction temperature estimates can be madeaccurately to within a few degrees Celsius. For more information, see the Semiconductor and IC Package
Thermal Metrics Application Report.
8.2.2.7 Selecting VCCI, VDDA/B Capacitor

Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is
recommended that one choose low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC)
with sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an
MLCC will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only
500 nF when a DC bias of 15 VDC is applied.
8.2.2.7.1 Selecting a VCCI Capacitor

A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total
current consumption, which is only a few mA. Therefore, a 50-V MLCC with over 100 nF is recommended forthis application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum orelectrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.
8.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor

A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows forgate drive current transients up to 6 A, and needs to maintain a stable gate drive voltage for the power transistor.
The total charge needed per switching cycle can be estimated with

QTotalQG

IVDD @100kHz No Load
fSW

60nC

1.5mA
100kHz

75nC
(19)

where
•
•
•
•

QTotal: Total charge needed
QG: Gate charge of the power transistor.
IVDD: The channel self-current consumption with no load at 100kHz.
fSW: The switching frequency of the gate driver

Therefore, the absolute minimum CBoot requirement is:

CBoot

QTotal'VVDDA

75nC
0.5V

150nF
(20)

where
•

30

ΔVVDDA is the voltage ripple at VDDA, which is 0.5 V in this example.

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In practice, the value of CBoot is greater than the calculated value. This allows for the capacitance shift caused by
the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients.
Therefore, it is recommended to include a safety-related margin in the CBoot value and place it as close to the
VDD and VSS pins as possible. A 50-V 1-µF capacitor is chosen in this example.

CBoot

1 )

(21)

Care should be taken when selecting the bootstrap capacitor to ensure that the VDD to VSS voltage does notdrop below the recommended minimum operating level listed in section 6.3. The value of the bootstrap capacitor
should be sized such that it can supply the initial charge to switch the power device, and then continuously
supply the gate driver quiescent current for the duration of the high-side on-time.
If the high-side supply voltage drops below the UVLO falling threshold, the high-side gate driver output will turnoff and switch the power device off. Uncontrolled hard-switching of power devices can cause high di/dt and highdv/dt transients on the output of the driver and may result in permanent damage to the device.
To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor
placed very close to VDDx - VSSx pins with a low ESL/ESR. In this example a 100 nF, X7R ceramic capacitor, isplaced in parallel with CBoot to optimize the transient performance.
Note
Too large CBOOT is not good. CBOOT may not be charged within the first few cycles and VBOOT could
stay below UVLO. As a result, the high-side FET does not follow input signal command. Also duringinitial CBOOT charging cycles, the bootstrap diode has highest reverse recovery current and losses.

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8.2.2.7.3 Select a VDDB Capacitor

Chanel B has the same current requirements as Channel A, Therefore, a VDDB capacitor (Shown as CVDD in
Figure 8-1) is needed. In this example with a bootstrap configuration, the VDDB capacitor will also supply current
for VDDA through the bootstrap diode. A 50-V, 10-µF MLCC and a 50-V, 220-nF MLCC are chosen for CVDD. If
the bias power supply output is a relatively long distance from the VDDB pin, a tantalum or electrolytic capacitor,
with a value over 10 µF, should be used in parallel with CVDD.
8.2.2.8 Dead Time Setting Guidelines

For power converter topologies utilizing half-bridges, the dead time setting between the top and bottom transistor
is important for preventing shoot-through during dynamic switching.
The UCC21520-Q1 dead time specification in the electrical table is defined as the time interval from 90% of one
channel’s falling edge to 10% of the other channel’s rising edge (see Figure 6-4). This definition ensures thatthe dead time setting is independent of the load condition, and guarantees linearity through manufacture testing.
However, this dead time setting may not reflect the dead time in the power converter system, since the deadtime setting is dependent on the external gate drive turn-on/off resistor, DC-Link switching voltage/current, as
well as the input capacitance of the load transistor.
Here is a suggestion on how to select an appropriate dead time for UCC21520-Q1:

DTSetting

DTReq

TF _ Sys

TR _ Sys

TD on

(22)

where
•
•
•
•
•

DTsetting: UCC21520-Q1 dead time setting in ns, DTSetting = 10 × RDT(in kΩ).
DTReq: System required dead time between the real VGS signal of the top and bottom switch with enoughmargin, or ZVS requirement.
TF_Sys: In-system gate turn-off falling time at worst case of load, voltage/current conditions.
TR_Sys: In-system gate turn-on rising time at worst case of load, voltage/current conditions.
TD(on): Turn-on delay time, from 10% of the transistor gate signal to power transistor gate threshold.

In the example, DTSetting is set to 250 ns.
It should be noted that the UCC21520-Q1 dead time setting is decided by the DT pin configuration (see Section
7.4.2), and it cannot automatically fine-tune the dead time based on system conditions. It is recommended toparallel a ceramic capacitor, <1nF, close to the DT pin with RDT to achieve better noise immunity.

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8.2.2.9 Application Circuits with Output Stage Negative Bias

When parasitic inductances are introduced by non-ideal PCB layout and long package leads (for example,
TO-220 and TO-247 type packages), there could be ringing in the gate-source drive voltage of the powertransistor during high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk ofunintended turn-on and even shoot-through. Applying a negative bias on the gate drive is a popular way to keepsuch ringing below the threshold. Below are a few examples of implementing negative gate drive bias.
Figure 8-2 shows the first example with negative bias turn-off on the channel-A driver using a Zener diode on theisolated power supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power
supply, VA, is equal to 25 V, the turn-off voltage will be –5.1 V and turn-on voltage will be 25 V – 5.1 V ≈ 20 V.
The channel-B driver circuit is the same as channel-A, therefore, this configuration needs two power supplies fora half-bridge configuration, and there will be steady state power consumption from RZ.
HV DC-Link
16

1

15

2

VDDA

ROFF
CA1
RZ

OUTA

25 V

+
VA
±

CIN

RON

4

5

Input Logic

3

Reinforced Isolation

CA2
VSSA
14
VZ = 5.1 V
SW

Functional
Isolation

6

11

10

VDDB

OUTB
VSSB

8

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9

Figure 8-2. Negative Bias with Zener Diode on Iso-Bias Power Supply Output

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Figure 8-3 shows another example which uses two supplies (or single-input-double-output power supply). Powersupply VA+ determines the positive drive output voltage and VA– determines the negative turn-off voltage. The
configuration for channel B is the same as channel A. This solution requires more power supplies than the firstexample, however, it provides more flexibility when setting the positive and negative rail voltages.
16

1

15

2

VDDA
CA1
OUTA

Reinforced Isolation

CA2

4

Input Logic

3

5

VSSA
14

HV DC-Link

ROFF
+
VA+
±

RON

CIN

+
VA±

Functional
Isolation

SW

11

6

10

8

9

VDDB

OUTB
VSSB

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Figure 8-3. Negative Bias with Two Iso-Bias Power Supplies

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The last example, shown in Figure 8-4, is a single power supply configuration and generates negative bias
through a Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply
and the bootstrap power supply can be used for the high side drive. This design requires the least cost anddesign effort among the three solutions. However, this solution has limitations:
1. The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, whichmeans the negative bias voltage will change when the duty cycle changes. Therefore, converters with afixed duty cycle (~50%) such as variable frequency resonant convertors or phase shift convertors favor thissolution.
2. The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range,
which means the low side switch must turn-on or have free-wheeling current on the body (or anti-parallel)
diode for a certain period during each switching cycle to refresh the bootstrap capacitor. Therefore, a 100%
duty cycle for the high side is not possible unless there is a dedicated power supply for the high side, like inthe other two example circuits.
VDD
RBOOT
HV DC-Link
1

16

2

15

VDDA

CZ

ROFF

OUTA

VZ

RON

CBOOT

4

5

Input Logic

3

Reinforced Isolation

VSSA

CIN
RGS

14
SW

Functional
Isolation

6

VDD
11

10

VDDB

CZ

ROFF

OUTB

VZ

RON

CVDD
8

RGS

VSSB
9
VSS

Copyright © 2017, Texas Instruments Incorporated

Figure 8-4. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path

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8.2.3 Application Curves
Figure 8-5 and Figure 8-6 shows the bench test waveforms for the design example shown in Figure 8-1 underthese conditions: VCC = 5 V, VDD = 20 V, fSW = 100 kHz, VDC-Link = 0 V.
Channel 1 (Yellow): UCC21520-Q1 INA pin signal.
Channel 2 (Blue): UCC21520-Q1 INB pin signal.
Channel 3 (Pink): Gate-source signal on the high side power transistor.
Channel 4 (Green): Gate-source signal on the low side power transistor.
In Figure 8-5, INA and INB are sent complimentary 3.3-V, 50% duty-cycle signals. The gate drive signals on
the power transistor have a 250-ns dead time, shown in the measurement section of Figure 8-5. The dead-time
matching is less than 1 ns with the 250-ns dead-time setting.
Figure 8-6 shows a zoomed-in version of the waveform of Figure 8-5, with measurements for propagation
delay and rising/falling time. Cursors are also used to measure dead time. Importantly, the output waveform ismeasured between the power transistors’ gate and source pins, and is not measured directly from the driver
OUTA and OUTB pins. Due to the split on and off resistors (Ron,Roff) and different sink and source currents,
different rising (16 ns) and falling time (9 ns) are observed in Figure 8-6.

Figure 8-5. Bench Test Waveform for INA/B and
OUTA/B36

Figure 8-6. Zoomed-In Bench Test Waveform

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9 Power Supply Recommendations
The recommended input supply voltage (VCCI) for the UCC21520-Q1 is between 3 V and 18 V. The output
bias supply voltage (VDDA/VDDB) range depends on which version of UCC21520-Q1 one is using. The lower
end of this bias supply range is governed by the internal under voltage lockout (UVLO) protection feature ofeach device. One mustn’t let VDD or VCCI fall below their respective UVLO thresholds (For more information
on UVLO see Section 7.3.1). The upper end of the VDDA/VDDB range depends on the maximum gate voltageof the power device being driven by the UCC21520-Q1. The UCC21520-Q1 have a recommended maximum
VDDA/VDDB of 25 V.
A local bypass capacitor should be placed between the VDD and VSS pins. This capacitor should be positioned
as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is further
suggested that one place two such capacitors: one with a value of ≈10-µF for device biasing, and an additional≤100-nF capacitor in parallel for high frequency filtering.
Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amountof current drawn by the logic circuitry within the input side of the UCC21520-Q1, this bypass capacitor has aminimum recommended value of 100 nF.

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10 Layout10.1 Layout Guidelines
One must pay close attention to PCB layout in order to achieve optimum performance for the UCC21520-Q1.
Below are some key points.
Component Placement:••••

Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pinsand between the VDD and VSS pins to support high peak currents when turning on the external powertransistor.
To avoid large negative transients on the switch node VSSA (HS) pin, the parasitic inductances between thesource of the top transistor and the source of the bottom transistor must be minimized.
It is recommended to place the dead-time setting resistor, RDT, and its bypassing capacitor close to DT pin of
the UCC21520-Q1.
It is recommended to bypass using a ≈1nF low ESR/ESL capacitor, CDIS, close to DIS pin when connecting toa µC with distance.

Grounding Considerations:••

It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal
physical area. This will decrease the loop inductance and minimize noise on the gate terminals of thetransistors. The gate driver must be placed as close as possible to the transistors.
Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSBreferenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor
is recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This
recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length andarea on the circuit board is important for ensuring reliable operation.

High-Voltage Considerations:••

To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB
traces or copper below the driver device. A PCB cutout is recommended in order to prevent contaminationthat may compromise the UCC21520-Q1’s isolation performance.
For half-bridge, or high-side/low-side configurations, where the channel A and channel B drivers could
operate with a DC-link voltage up to 1500 VDC, one should try to increase the creepage distance of the PCB
layout between the high and low-side PCB traces.

Thermal Considerations:
•
•
•

38

A large amount of power may be dissipated by the UCC21520-Q1 if the driving voltage is high, the load isheavy, or the switching frequency is high (refer to Section 8.2.2.5 for more details). Proper PCB layout canhelp dissipate heat from the device to the PCB and minimize junction to board thermal impedance (θJB).
Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority
on maximizing the connection to VSSA and VSSB (see Figure 10-2 and Figure 10-3). However, high voltage
PCB considerations mentioned above must be maintained.
If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA andVSSB pins to internal ground or power planes through multiple vias of adequate size. However, keep in mind
that there shouldn’t be any traces/coppers from different high voltage planes overlapping.

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10.2 Layout Example
Figure 10-1 shows a 2-layer PCB layout example with the signals and key components labeled.

Figure 10-1. Layout Example
Figure 10-2 and Figure 10-3 shows top and bottom layer traces and copper.
Note
There are no PCB traces or copper between the primary and secondary side, which ensures isolation
performance.

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PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize thecreepage distance for high-voltage operation, which will also minimize cross-talk between the switching node
VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.

Figure 10-3. Bottom Layer Traces and Copper

Figure 10-2. Top Layer Traces and Copper

Figure 10-4 and Figure 10-5 are 3D layout pictures with top view and bottom views.
Note
The location of the PCB cutout between the primary side and secondary sides, which ensuresisolation performance.

Figure 10-4. 3-D PCB Top View

40

Figure 10-5. 3-D PCB Bottom View

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11 Device and Documentation Support
11.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOTCONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHERALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:• Semiconductor and IC Package Thermal Metrics Application Report• Isolation Glossary

11.3 Certifications
UL Online Certifications Directory, "FPPT2.E181974 Nonoptical Isolating Devices - Component" Certificate
Number: 20160516-E181974,
VDE Pruf- und Zertifizierungsinstitut Certification, Certificate of Conformity with Factory Surveillance
CQC Online Certifications
Number:CQC16001155011

Directory,"GB4943.1-2011,

DigitalIsolator

Certificate"

Certificate

CSA Online Certifications Directory, "CSA Certificate of Compliance" Certificate Number:70097761, Master
Contract Number:220991

11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For changedetails, review the revision history included in any revised document.

11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straightfrom the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

11.6 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.

11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handledwith appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.

11.8 Glossary
TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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12 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (June 2020) to Revision E (June 2024)
Page• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1• Deleted 5ns maximum delay matching from Features section...........................................................................1• Changed Typ propagation delay from 19ns to 33ns...........................................................................................1• Changed 10ns minmum pulse width to 20ns......................................................................................................1• Changed operating temperature range to junction temeperature range............................................................ 1• Changed CMTI specification from 100V/ns to 125V/ns......................................................................................1• Changed surge immunity value from 12.8kV to 10kV........................................................................................ 1• Deleted "Rejects input pulses and noise transients shorter than 5ns"............................................................... 1• Deleted HBM and CDM ESD classification levels in Features........................................................................... 1• Updated safety certifications to latest standards................................................................................................ 1• Updated Description section to match new spec values.................................................................................... 1• Updated DT pin description to recommend ≤1nF capacitor on DT pin...............................................................3• Changed DT pin Min resistor recommendations from 500Ω to 2kΩ...................................................................3• Updated ESD spec from HBM = ±4000 and CDM = ±1500 to HBM = ±2000 and CDM = ±1000 to match ESD
industry standards.............................................................................................................................................. 4• Deleted ambient temperature spec.................................................................................................................... 4• Changed Max junction temp to 150C................................................................................................................. 4• Updated values from RθJA = 67.3°C/W, RθJC(top) = 34.4°C/W, RθJB = 32.1°C/W, ψJT = 18°C/W, ψJB =
31.6°C/W to RθJA = 69.8°C/W, RθJC(top) = 33.1°C/W, RθJB = 36.9°C/W, ψJT = 22.2°C/W, ψJB = 36°C/W.. 4• Updated values from PD = 1.05W, PDI = 0.05W, PDA/PDB = 0.5W to PD = 950mW, PDI = 50mW, PDA/PDB= 450mW............................................................................................................................................................ 5• Updated values from DTI = >21mm, VIOSM = 8000VPK to DTI = >17mm, VIOSM = 10000VPK and added
VIMP = 7692VPK................................................................................................................................................6• Deleted safety related certifications section....................................................................................................... 6• Updated values from IS = 75mA/36mA, PS = 50mW/900mW/900mW/1850mW to IS = 58mA/34mA, PS =50mW/870mW/870mW/1790mW ...................................................................................................................... 7• Updated IVDDA/IVDDB quiescent current spec Max value from 1.8mA to 2.5mA............................................ 7• Updated IVCCI operating current Typ value from 2.0mA to 3.0mA and added Max value 3.5mA..................... 7• Added IVDDA/IVDDB operating current Max = 4.2mA.......................................................................................7• Updated values from Rising threshold Min = 8.3V, Typ = 8.7V, Max = 9.2V to Min = 7.7V, Typ = 8.5V, Max =8.9V ................................................................................................................................................................... 7• Updated values from Falling threshold Min = 7.8V, Typ = 8.2V, Max = 8.7V to Min = 7.2V, Typ = 7.9V, Max =8.4V ................................................................................................................................................................... 7• Updated 8-V UVLO hysteresis typ = 0.5V to 0.6V..............................................................................................7• Updated Input high threshold Min value from 1.6V to 1.2V................................................................................7• Deadtime parameter broken to a its own table and added more parameters.................................................... 8• Changed propagation delay TPDHL and TPDLH from Typ = 19ns, Max = 30ns to Typ = 33ns, Max = 45ns
and adding Min = 26ns....................................................................................................................................... 8• Changed propagation delay matching from Max = 5ns to Max = 6.5ns from TJ = -40C to -10C and Max = 5ns
from TJ = -10C to 150C......................................................................................................................................8• Added VCCI power up delay ............................................................................................................................. 8• Updated VDDA/VDDB power-up delay from Max = 100us to 10us ...................................................................8• Updated CMTI from Min = 100V/ns to 125V/ns..................................................................................................8• Updated insulation curves to match updated characteristics............................................................................. 9• Updated typical characteristics figures............................................................................................................. 10• Updated Power-up UVLO Delay to OUTPUT section to match device electrical characteristics .................... 15• Changed the Functional Block Diagram to add deglitch filter block................................................................. 17• Added paragraph on minimum pulse width to Output Stage section................................................................21

42

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Updated DT Pin Connected to a Programming Resistor Between DT and GND Pins section to recommend<1nF capacitor on DT pin. ............................................................................................................................... 23
Updated typical schematic DT pin capacitor recommendation ........................................................................25
Updated Dead Time Setting Guidelines section to recommend <1nF capacitor on DT pin. ........................... 32

Changes from Revision C (March 2020) to Revision D (June 2020)
Page• Added Functional Safety Quality-Managed to features list.................................................................................1

Changes from Revision B (July 2018) to Revision C (March 2020)
Page• Changed DT pin description .............................................................................................................................. 3• Changed DT pin configuration recommendations ........................................................................................... 23• Added update to bootstrap circuit recommendations ...................................................................................... 26• Added update to gate resistor selection recommendations .............................................................................27• Added gate to source resistor recommendation ..............................................................................................28• Added update to Cboot selection recommendations .......................................................................................30

Changes from Revision A (May 2018) to Revision B (July 2018)
Page• Changed UCC21520A-Q1 Advance Information marketing status to initial release.......................................... 1• Added detailed description for DISABLE Pin and DT Pin...................................................................................3• Added feature descriptions for UVLO delay to OUTPUT ................................................................................ 15• Added bullet "It is recommended..." bullet to the component placement in the Layout Guidelines. ................38

Changes from Revision * (October 2017) to Revision A (May 2018)
Page• Added UCC21520A-Q1 device (5V UVLO Option) in this datasheet ................................................................ 1• Added UCC21520A-Q1 Advance Information.................................................................................................... 1• Added typical curves of 5-V UVLO hysteresis and ON-OFF thresholds.......................................................... 10

13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM
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14-Mar-2024

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)(3)

Device Marking

Samples

(4/5)

(6)

UCC21520AQDWQ1LIFEBUY

SOIC

DW

16

40

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 125

UCC21520AQ

UCC21520AQDWRQ1

ACTIVE

SOIC

DW

16

2000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 125

UCC21520AQ

UCC21520QDWQ1LIFEBUY

SOIC

DW

16

40

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 125

UCC21520Q

UCC21520QDWRQ1

ACTIVE

SOIC

DW

16

2000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 125

UCC21520Q(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

Samples

SamplesPACKAGE OPTION ADDENDUM
www.ti.com

14-Mar-2024

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC21520-Q1 :• Catalog : UCC21520
NOTE: Qualified Version Definitions:• Catalog - TI's standard catalog product

Addendum-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

15-Jun-2024

TAPE AND REEL INFORMATIONREEL DIMENSIONSTAPE DIMENSIONS
K0

P1

B0 W
Reel
DiameterCavity
A0
B0
K0
W
P1

A0

Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers

Reel Width (W1)QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes

Q1

Q2

Q1

Q2

Q3

Q4

Q3

Q4

User Direction of Feed

Pocket Quadrants*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

UCC21520AQDWRQ1

SOIC

DW

16

2000

330.0

16.4

10.75

10.7

2.7

12.0

16.0

Q1

UCC21520AQDWRQ1

SOIC

DW

16

2000

330.0

16.4

10.75

10.7

2.7

12.0

16.0

Q1

UCC21520QDWRQ1

SOIC

DW

16

2000

330.0

16.4

10.75

10.7

2.7

12.0

16.0

Q1

UCC21520QDWRQ1

SOIC

DW

16

2000

330.0

16.4

10.75

10.7

2.7

12.0

16.0

Q1

UCC21520QDWRQ1

SOIC

DW

16

2000

330.0

16.4

10.75

10.7

2.7

12.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

15-Jun-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)

W

L

H

*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)UCC21520AQDWRQ1

SOIC

DW

16

2000

350.0

350.0

43.0

UCC21520AQDWRQ1

SOIC

DW

16

2000

356.0

356.0

35.0

UCC21520QDWRQ1

SOIC

DW

16

2000

356.0

356.0

35.0

UCC21520QDWRQ1

SOIC

DW

16

2000

350.0

350.0

43.0

UCC21520QDWRQ1

SOIC

DW

16

2000

356.0

356.0

35.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

15-Jun-2024

TUBE
T - TubeheightL - Tube length

W - Tubewidth

B - Alignment groove width*All dimensions are nominal

DevicePackage Name

Package Type

Pins

SPQ

L (mm)W (mm)

T (µm)B (mm)

UCC21520AQDWQ1

DW

SOIC

16

UCC21520AQDWQ1

DW

SOIC

16

40

507

12.83

5080

6.6

40

506.9812.7

4826

UCC21520QDWQ1

DW

SOIC

6.6

16

40

507

12.83

5080

6.6

UCC21520QDWQ1

DW

SOIC

16

40

506.98

12.7

4826

6.6

Pack Materials-Page 3

GENERIC PACKAGE VIEW

DW 16

SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

7.5 x 10.3, 1.27 mm pitch

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224780/A

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PACKAGE OUTLINE

DW0016B

SOIC - 2.65 mm max height
SCALE 1.500

SOIC

C
10.63
TYP
9.97

SEATING PLANE

PIN 1 ID
AREA

A

0.1 C
14X 1.27
16

1

2X
8.89

10.5
10.1
NOTE 3

8
9

0.51
0.31
0.25
C A

16X
B

7.6
7.4
NOTE 42.65 MAX

B

0.33
TYP
0.10

SEE DETAIL A
0.25
GAGE PLANE

0.3
0.1

0 -8
1.27
0.40

DETAIL A(1.4)

TYPICAL
4221009/B 07/2016

NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.

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EXAMPLE BOARD LAYOUT

DW0016B

SOIC - 2.65 mm max height
SOIC

SYMM

SYMM

16X (2)16X (1.65)

SEE
DETAILS

1SEE
DETAILS116

16
16X (0.6)

16X (0.6)

SYMM

SYMM

14X (1.27)

14X (1.27)
9

8

9

8
R0.05 TYP

R0.05 TYP
(9.3)

(9.75)

IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE

HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLESCALE:4X

METAL

SOLDER MASKOPENINGSOLDER MASKOPENING0.07 MAXALL AROUND

METAL

0.07 MIN
ALL AROUNDSOLDER MASKDEFINEDNON SOLDER MASKDEFINEDSOLDER MASK DETAILS
4221009/B 07/2016

NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

DW0016B

SOIC - 2.65 mm max height
SOIC

SYMM

SYMM
16X (1.65)

16X (2)

1

1

16

16
16X (0.6)

16X (0.6)
SYMM

SYMM

14X (1.27)

14X (1.27)
9

8

9

8

R0.05 TYP

R0.05 TYP
(9.3)

(9.75)

IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE

HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCILSCALE:4X

4221009/B 07/2016

NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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