参考資料
MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020
JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

MSP430i204x、MSP430i203x、MSP430i202x ミックスド・シグナル・マイコン
1 特長
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電源電圧範囲：2.2V～3.6V
高性能アナログ– MSP430i204x：4 つの 24 ビット・シグマ・デルタ
A/D コンバータ (ADC)、差動 PGA 入力付き
– MSP430I203x：3 つの 24 ビット・シグマ・デルタ
A/D コンバータ (ADC)、差動 PGA 入力付き
– MSP430I202x：2 つの 24 ビット・シグマ・デルタ
A/D コンバータ (ADC)、差動 PGA 入力付き
超低消費電力– アクティブ・モード (AM)：すべてのシステム・クロックがアクティブ
16.384MHz、3.0V、フラッシュ・プログラム実行時
で 275μA/MHz (標準値)– スタンバイ・モード (LPM3)：
ウォッチドッグ・タイマがアクティブ、RAM 全体を保持
3.0V で 210μA (標準値)– オフ・モード (LPM4)：
RAM 全体を保持
3.0V で 70µA (標準値)– シャットダウン・モード (LPM4.5)：
3.0V で 75µA (標準値)
インテリジェントなデジタル・ペリフェラル– 2 つの 16 ビット・タイマ、それぞれに 3 つのキャプ
チャ / 比較レジスタを搭載– ハードウェア乗算器で 16 ビットの演算をサポート
拡張ユニバーサル・シリアル通信インターフェイス(eUSCI)– eUSCI_A0• 自動ボーレート検出機能付きの拡張 UART
• IrDA エンコーダおよびデコーダ• 同期 SPI– eUSCI_B0• 同期 SPI• I2C
フレキシブルな電源管理システム– レギュレートされた 1.8V のコア電源電圧を持つ統合 LDO– 検出レベルをプログラム可能な電源電圧モニタ– ブラウンアウト検出器– 電圧リファレンスを内蔵– 温度センサ
クロック・システム– 16.384MHz の内部デジタル制御発振器 (DCO)– 内部抵抗または外部抵抗を使用した DCO の動作– 外部デジタル・クロック・ソース

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開発ツールとソフトウェア (「ツールとソフトウェア」も参照)– 計測用の EVM430-I2040S 評価基板 (EVM)– MSP-TS430RHB32A 100 ピン・ターゲット開発基
板– MSP430Ware™ サンプル・コード
スタンバイ・モードから 1µs でウェークアップ
16 ビット RISC アーキテクチャ、最高 16.384MHz のシステム・クロック
シリアルのオンボード・プログラミング、外部からのプロ
グラミング電圧は不要
28 ピン TSSOP (PW) および 32 ピン VQFN (RHB)
パッケージで供給「デバイスの比較」に、提供しているファミリ製品を要約
主なソフトウェアとリファレンス・デザイン– MSP430 MCU 向けエネルギー測定デザイン・センターのアプリケーション・ソフトウェアとフレームワーク– MSP430 マイコン用のデジタル信号処理 (DSP) ラ
イブラリのソフトウェア・ライブラリ– 単相および DC 組込みメーターのリファレンス・デ
ザイン– 3 出力のスマート・パワー・ストリップのリファレンス・
デザイン

2 アプリケーション
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計量
サブメーター
電力監視および制御
産業用センサ単相の AC および DC 電力監視
2 相の電子電力量計
スマート・プラグ
スマート電力ストリップ
医療 - 複数パラメータの患者監視

英語版の TI 製品についての情報を翻訳したこの資料は、製品の概要を確認する目的で便宜的に提供しているものです。該当する正式な英語版の最新情報は、
www.ti.com で閲覧でき、その内容が常に優先されます。TI では翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、必ず最新版の英語版をご参照くださいますようお願いいたします。

English Data Sheet: SLAS887

MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020

www.ti.com/ja-jp

JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

3 概要
テキサス・インスツルメンツの MSP430i204x、MSP430I203x、MSP430I202x マイクロコントローラ (MCU) は、MSP430™ 計測および監視ポートフォリオの一部です。アーキテクチャおよび内蔵ペリフェラルと、5 つの低消費電力モードの組み合わせにより、携帯用のバッテリ駆動測定アプリケーションのバッテリ駆動時間を延長するよう最適化されています。この
デバイスには強力な 16 ビット RISC CPU、16 ビット・レジスタ、および定数ジェネレータが搭載されているため、最高水
準のコード効率を実現できます。デジタル制御発振器 (DCO) により、このデバイスは低消費電力モードからアクティブ・
モードへ 5µs 未満でウェークアップできます。
MSP430i204x MCU には、4 つの高性能 24 ビット・シグマ・デルタ ADC、2 つの eUSCI (1 つの eUSCI_A モジュールと 1 つの eUSCI_B モジュール)、2 つの 16 ビット・タイマ、ハードウェア乗算器、および最大 16 の I/O ピンが搭載されています。
MSP430I203x MCU には、3 つの高性能 24 ビット・シグマ・デルタ ADC、2 つの eUSCI (1 つの eUSCI_A モジュールと 1 つの eUSCI_B モジュール)、2 つの 16 ビット・タイマ、ハードウェア乗算器、および最大 16 の I/O ピンが搭載されています。
MSP430I202x MCU には、2 つの高性能 24 ビット・シグマ・デルタ ADC、2 つの eUSCI (1 つの eUSCI_A モジュールと 1 つの eUSCI_B モジュール)、2 つの 16 ビット・タイマ、ハードウェア乗算器、および最大 16 の I/O ピンが搭載されています。
これらのデバイスの代表的なアプリケーションとして、エネルギー測定、アナログおよびデジタル・センサ・システム、LED
ライティング、デジタル電源、モーター制御、リモート制御、サーモスタット、デジタル・タイマ、ハンドヘルド・メータが挙げられます。
MSP430i204x、MSP430I203x、MSP430I202x MCU は、広範囲にわたるハードウェアおよびソフトウェアのエコシステ
ムによってサポートされており、リファレンス・デザインやコード・サンプルによって設計を迅速に開始できます。開発キットには、計量用の EVM430-I2040S 評価基板 (EVM) と、MSP-TS430RHB32A 100 ピン・ターゲット開発基板が含まれています。MSP430 MCU 用のエネルギー測定デザイン・センターは、これらのデバイスでエネルギー測定を可能にする迅
速な開発ツールとして提供されています。また、テキサス・インスツルメンツは無償の MSP430Ware™ ソフトウェアも提供しており、Code Composer Studio ™ IDE デスクトップのコンポーネントとして利用できます。また、TI Resource Explorer
ではクラウド・バージョンを利用できます。MSP430 MCU には、広範囲にわたるオンライン資料、トレーニング、および TI
E2E™ サポート・フォーラムによるオンライン・サポートも用意されています。
モジュールの完全な説明については、『MSP430i2xx ファミリ・ユーザーズ・ガイド』を参照してください。
製品情報(1)部品番号

パッケージ

本体サイズ (2)

MSP430i2041TPWTSSOP (28)9.7mm × 4.4mm

MSP430i2041TRHB

VQFN (32)5mm × 5mm

(1)
(2)

2

提供中の全デバイスに関する最新の製品、パッケージ、および注文情報については、セクション 12 の「付録：パッケージ・オプション」または www.tij.co.jp の TI Web サイトを参照してください。
ここに記載されているサイズは概略です。公差を含めたパッケージの寸法については、セクション 12 の「メカニカル・データ」を参照してください。

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Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: MSP430I2041 MSP430I2040 MSP430I2031 MSP430I2030 MSP430I2021 MSP430I2020
English Data Sheet: SLAS887

MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020

www.ti.com/ja-jp

JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

4 Functional Block Diagram
図 4-1 shows the functional block diagram for the MSP430i204x devices in the RHB package. For the functional
block diagrams of all device variants and packages, see セクション 9.2.
ROSC

VCC DVSS AVSS VCORE RST/NMI

P1.x
8

P2.x
8

ACLK
Clock
System

Flash

RAM

32KB
16KB

2KB
1KB

Power
Management

SD24

SMCLK
MCLK

16.384-MHz
CPU
with 16
registers

TA0

TA1

Port P1

Port P2

Timer_A
3 CC
Registers

Timer_A
3 CC
Registers

8 I/Os,Interrupt
capability

8 I/Os,Interrupt
capability

HardwareMultiplier(16x16)

eUSCI_A0

eUSCI_B0

UART,
IrDA, SPISPI, I C

MAB
MDBEmulation
2BP
JTAG
Interface
Spy-BiWire

LDO
REF
VMON
Brownout

Watchdog
4
WDT
Sigma-Delta
Analog-to- 15 or 16 bit
DigitalConverters

MPY,
MPYS,
MAC,
MACS

2

図 4-1. Functional Block Diagram – RHB Package – MSP430i204x

Copyright © 2023 Texas Instruments Incorporated

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Product Folder Links: MSP430I2041 MSP430I2040 MSP430I2031 MSP430I2030 MSP430I2021 MSP430I2020
English Data Sheet: SLAS887

MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020

www.ti.com/ja-jp

JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

Table of Contents
1 特長................................................................................... 1
2 アプリケーション...................................................................1
3 概要................................................................................... 2
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 5
6 Device Comparison......................................................... 6
6.1 Related Products........................................................ 6
7 Terminal Configuration and Functions..........................7
7.1 Pin Diagrams.............................................................. 7
7.2 Signal Descriptions................................................... 10
7.3 Pin Multiplexing.........................................................12
7.4 Connection of Unused Pins...................................... 12
8 Specifications................................................................ 13
8.1 Absolute Maximum Ratings...................................... 13
8.2 ESD Ratings............................................................. 13
8.3 Recommended Operating Conditions.......................13
8.4 Active Mode Supply Current (Into VCC)
Excluding External Current .........................................14
8.5 Low-Power Mode Supply Currents (Into VCC)
Excluding External Current .........................................15
8.6 Thermal Resistance Characteristics......................... 15
8.7 Timing and Switching Characteristics....................... 16
9 Detailed Description......................................................32
9.1 Overview................................................................... 32
9.2 Functional Block Diagrams....................................... 32

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9.3 CPU.......................................................................... 38
9.4 Instruction Set........................................................... 39
9.5 Operating Modes...................................................... 40
9.6 Interrupt Vector Addresses....................................... 41
9.7 Special Function Registers....................................... 42
9.8 Flash Memory........................................................... 42
9.9 JTAG Operation........................................................ 43
9.10 Peripherals..............................................................45
9.11 Input/Output Diagrams............................................ 49
9.12 Device Descriptor....................................................56
9.13 Memory................................................................... 57
9.14 Identification............................................................60
10 Applications, Implementation, and Layout............... 61
11 Device and Documentation Support..........................62
11.1 Getting Started and Next Steps.............................. 62
11.2 Device Nomenclature..............................................62
11.3 Tools and Software..................................................63
11.4 Documentation Support.......................................... 64
11.5 サポート・リソース.......................................................65
11.6 Trademarks............................................................. 65
11.7 静電気放電に関する注意事項.................................. 66
11.8 用語集..................................................................... 66
12 Mechanical, Packaging, and Orderable
Information.................................................................... 67

Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: MSP430I2041 MSP430I2040 MSP430I2031 MSP430I2030 MSP430I2021 MSP430I2020
English Data Sheet: SLAS887

www.ti.com/ja-jp

MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020
JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

5 Revision History
資料番号末尾の英字は改訂を表しています。その改訂履歴は英語版に準じています。
Changes from revision B to revision C
Changes from March 4, 2020 to March 16, 2021
•
•

Page

文書全体にわたって表、図、相互参照の採番方法を更新...................................................................................... 1
セクション 1「特長」の「主なソフトウェアとリファレンス・デザイン」を更新....................................................................1

Changes from revision A to revision B
Changes from May 3, 2018 to March 3, 2020
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Page

セクション 1「特長」を更新.....................................................................................................................................1
セクション 3「概要」を更新.....................................................................................................................................2
Added 2 and 4 to the SD24GAINx options in the test conditions of the "Gain error" parameter in セクション
8.7.7.5, SD24 Performance, Internal Reference (SD24REFS = 1, SD24OSRx = 256) ...................................23
Added 2 and 4 to the SD24GAINx options in the test conditions of the "Gain error" parameter in セクション
8.7.7.6, SD24 Performance, External Reference (SD24REFS = 0, SD24OSRx = 256) ..................................24
Changed the MIN values for the tHD,STA, tSU,STA, tHD,DAT, tSU,DAT, and tSU,STO parameters in セクション 8.7.8.6,
eUSCI (I2C Mode) Timing ................................................................................................................................ 30
Updated descriptions and links in セクション 10, Applications, Implementation, and Layout ............................61

Changes from the initial release to revision A
Changes from August 31, 2014 to May 2, 2018
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Page

セクション 2「アプリケーション」のアプリケーションのリストを変更..............................................................................1
Added セクション 6.1, Related Products ............................................................................................................. 6
Added typical conditions statements at the beginning of セクション 8, Specifications ...................................... 13
Added SD24 input pins and AUXVCCx pins to exception list on "Voltage applied to pins" parameter, andadded SD24 input pin limits in "Diode current at pins" parameter in セクション 8.1, Absolute Maximum Ratings..........................................................................................................................................................................13
Added セクション 8.2, ESD Ratings .................................................................................................................. 13
Added セクション 8.6, Thermal Resistance Characteristics .............................................................................. 15
Changed the MAX value of the tWAKE-UP-LPM4 parameter from 35 µs to 45 µs in セクション 8.7.3.1, Wake-up
Times From Low Power Modes ....................................................................................................................... 17
Added the CAUTION that begins "The CPU will lock up if..." in セクション 9.3, CPU ....................................... 38

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Product Folder Links: MSP430I2041 MSP430I2040 MSP430I2031 MSP430I2030 MSP430I2021 MSP430I2020
English Data Sheet: SLAS887

MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020

www.ti.com/ja-jp

JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

6 Device Comparison
表 6-1 summarizes the available family members.
表 6-1. Device Comparison
DEVICE(1)

FLASH
(KB)

SRAM
(KB)

SD24
CONVERTERS

MULTIPLIER

Timer_A(2)eUSCI_A:
UART, IrDA,
SPI

eUSCI_B:
SPI, I2CMSP430i2041

32

2

4

1

3, 3

1

1

MSP430i2040

MSP430i2031

16

32

1

2

4

3

1

1

3, 3

3, 3

1

1

1

1

MSP430i2030

16

1

3

1

3, 3

1

1

MSP430i2021

32

2

2

1

3, 3

1

1

MSP430i2020

(1)
(2)

16

1

2

1

3, 3

1

1

I/O

PACKAGE

16

32 RHB

12

28 PW

16

32 RHB

12

28 PW

16

32 RHB

12

28 PW

16

32 RHB

12

28 PW

16

32 RHB

12

28 PW

16

32 RHB

1228 PW

For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in セクション
12, or see the TI website at www.ti.com.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and
PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

6.1 Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers
High-performance, low-power solutions to enable the autonomous future
MSP430 ultra-low-power sensing and measurement microcontrollers
One platform. One ecosystem. Endless possibilities.
Reference designs for MSP430i2041
Find reference designs leveraging the best in TI technology to solve your system-level challenges. All designs
include a schematic, test data and design files.

6

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Product Folder Links: MSP430I2041 MSP430I2040 MSP430I2031 MSP430I2030 MSP430I2021 MSP430I2020
English Data Sheet: SLAS887

MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020

www.ti.com/ja-jp

JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

7 Terminal Configuration and Functions
7.1 Pin Diagrams
P2.0/TA1.0/CLKIN

P2.1/TA1.1

P2.2/TA1.2

P2.3/VMONIN

P2.4/TA1.0

P2.5/TA0.0

P2.6/TA0.1

P2.7/TA0.2

図 7-1 shows the pin assignments for the MSP430i2041 and MSP430i2040 devices in the RHB package.

32 31 30 29 28 27 26 25
A0.0+

1

24

P1.7/UCB0SDA/UCB0SIMO/TA1CLK

A0.0-

2

23

P1.6/UCB0SCL/UCB0SOMI/TA0.2

A1.0+

3

22

P1.5/UCB0CLK/TA0.1

MSP430i2041TRHB
MSP430i2040TRHB

A1.0-

4

21

P1.4/UCB0STE/TA0.0

A2.0+

5

20

P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI

A2.0-

6

19

P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK

A3.0+

7

18

P1.1/UCA0CLK/SMCLK/TMS

A3.0-

8

17

P1.0/UCA0STE/MCLK/TCK

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

VCORE

DVSS

ROSC

AVSS

VREF

9 10 11 12 13 14 15 16

NOTE: TI recommends connecting the thermal pad on the RHB package to DVSS.

図 7-1. 32-Pin RHB Package (Top View) – MSP430i2041, MSP430i2040
図 7-2 shows the pin assignments for the MSP430i2041 and MSP430i2040 devices in the PW package.
A0.0+

1

28

P2.3/VMONIN

A0.0-

2

27

P2.2/TA1.2

A1.0+

3

26

P2.1/TA1.1

A1.0-

4

25

P2.0/TA1.0/CLKIN

A2.0+

5

24

P1.7/UCB0SDA/UCB0SIMO/TA1CLK

A2.0-

6

23

P1.6/UCB0SCL/UCB0SOMI/TA0.2

A3.0+

7

22

P1.5/UCB0CLK/TA0.1

A3.0-

8

21

P1.4/UCB0STE/TA0.0

VREF

9

20

P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI

AVSS

10

19

P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK

ROSC

11

18

P1.1/UCA0CLK/SMCLK/TMS

DVSS

12

17

P1.0/UCA0STE/MCLK/TCK

VCC

13

16

TEST/SBWTCK

VCORE

14

15

RST/NMI/SBWTDIOMSP430i2041TPW
MSP430i2040TPW

図 7-2. 28-Pin PW Package (Top View) – MSP430i2041, MSP430i2040

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English Data Sheet: SLAS887

MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020

www.ti.com/ja-jp

JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

P2.0/TA1.0/CLKIN

P2.1/TA1.1

P2.2/TA1.2

P2.3/VMONIN

P2.4/TA1.0

P2.5/TA0.0

P2.6/TA0.1

P2.7/TA0.2

図 7-3 shows the pin assignments for the MSP430i2031 and MSP430i2030 devices in the RHB package.

32 31 30 29 28 27 26 25
A0.0+

1

24

P1.7/UCB0SDA/UCB0SIMO/TA1CLK

A0.0-

2

23

P1.6/UCB0SCL/UCB0SOMI/TA0.2

A1.0+

3

22

P1.5/UCB0CLK/TA0.1

MSP430i2031TRHB
MSP430i2030TRHB

A1.0-

4

21

P1.4/UCB0STE/TA0.0

A2.0+

5

20

P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI

A2.0-

6

19

P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK

NC

7

18

P1.1/UCA0CLK/SMCLK/TMS

NC

8

17

P1.0/UCA0STE/MCLK/TCK

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

VCORE

DVSS

ROSC

AVSS

VREF

9 10 11 12 13 14 15 16

NOTE: TI recommends connecting the thermal pad on the RHB package to DVSS.
NOTE: TI recommends connecting NC pins to AVSS.

図 7-3. 32-Pin RHB Package (Top View) – MSP430i2031, MSP430i2030
図 7-4 shows the pin assignments for the MSP430i2031 and MSP430i2030 devices in the PW package.
A0.0+

1

28

P2.3/VMONIN

A0.0-

2

27

P2.2/TA1.2

A1.0+

3

26

P2.1/TA1.1

A1.0-

4

25

P2.0/TA1.0/CLKIN

A2.0+

5

24

P1.7/UCB0SDA/UCB0SIMO/TA1CLK

A2.0-

6

23

P1.6/UCB0SCL/UCB0SOMI/TA0.2

NC

7

22

P1.5/UCB0CLK/TA0.1

NC

8

21

P1.4/UCB0STE/TA0.0

VREF

9

20

P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI

AVSS

10

19

P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK

ROSC

11

18

P1.1/UCA0CLK/SMCLK/TMS

DVSS

12

17

P1.0/UCA0STE/MCLK/TCK

VCC

13

16

TEST/SBWTCK

VCORE

14

15

RST/NMI/SBWTDIOMSP430i2031TPW
MSP430i2030TPW

NOTE: TI recommends connecting NC pins to AVSS.

図 7-4. 28-Pin PW Package (Top View) – MSP430i2031, MSP430i2030

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JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

P2.0/TA1.0/CLKIN

P2.1/TA1.1

P2.2/TA1.2

P2.3/VMONIN

P2.4/TA1.0

P2.5/TA0.0

P2.6/TA0.1

P2.7/TA0.2

図 7-5 shows the pin assignments for the MSP430i2021 and MSP430i2020 devices in the RHB package.

32 31 30 29 28 27 26 25
A0.0+

1

24

P1.7/UCB0SDA/UCB0SIMO/TA1CLK

A0.0-

2

23

P1.6/UCB0SCL/UCB0SOMI/TA0.2

A1.0+

3

22

P1.5/UCB0CLK/TA0.1

A1.0-

4

21

P1.4/UCB0STE/TA0.0

NC

5

20

P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI

NC

6

19

P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK

NC

7

18

P1.1/UCA0CLK/SMCLK/TMS

NC

8

17

P1.0/UCA0STE/MCLK/TCK

MSP430i2021TRHB
MSP430i2020TRHB

TEST/SBWTCK

RST/NMI/SBWTDIO

VCC

VCORE

DVSS

AVSS

ROSC

VREF

9 10 11 12 13 14 15 16

NOTE: TI recommends connecting the thermal pad on the RHB package to DVSS.
TI recommends connecting NC pins to AVSS.

図 7-5. 32-Pin RHB Package (Top View) – MSP430i2021, MSP430i2020
図 7-6 shows the pin assignments for the MSP430i2021 and MSP430i2020 devices in the PW package.
A0.0+

1

28

P2.3/VMONIN

A0.0-

2

27

P2.2/TA1.2

A1.0+

3

26

P2.1/TA1.1

A1.0-

4

25

P2.0/TA1.0/CLKIN

NC

5

24

P1.7/UCB0SDA/UCB0SIMO/TA1CLK

NC

6

23

P1.6/UCB0SCL/UCB0SOMI/TA0.2

NC

7

22

P1.5/UCB0CLK/TA0.1

NC

8

21

P1.4/UCB0STE/TA0.0

VREF

9

20

P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI

AVSS

10

19

P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK

ROSC

11

18

P1.1/UCA0CLK/SMCLK/TMS

DVSS

12

17

P1.0/UCA0STE/MCLK/TCK

VCC

13

16

TEST/SBWTCK

VCORE

14

15

RST/NMI/SBWTDIOMSP430i2021TPW
MSP430i2020TPW

TI recommends connecting NC pins to AVSS.

図 7-6. 28-Pin PW Package (Top View) – MSP430i2021, MSP430i2020

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JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

7.2 Signal Descriptions
セクション 7.2 describes the signals for all device variants and package options.
表 7-1. Signal Descriptions
TERMINALNAME

NO.(2)

I/O(1)DESCRIPTION

PW

RHB

A0.0+

1

1

I

SD24 positive analog input A0.0(3)

A0.0-

2

2

I

SD24 negative analog input A0.0(3)

A1.0+

3

3

I

SD24 positive analog input A1.0(3)

A1.0-

4

4

I

SD24 negative analog input A1.0(3)

A2.0+

5

5

I

SD24 positive analog input A2.0(3) (4)

A2.0-

6

6

I

SD24 negative analog input A2.0(3) (4)

A3.0+

7

7

I

SD24 positive analog input A3.0 (3) (4) (5)

A3.0-

8

8

I

SD24 negative analog input A3.0 (3) (4) (5)I

SD24 external reference voltage input

VREF(6)

9

9

AVSS

10

10

Analog supply voltage, negative terminal

ROSC

11

11

External resistor pin for DCO.
Connect recommended resistor between ROSC and AVSS for DCO operationin external resistor mode. Connect ROSC to AVSS while operating DCO ininternal resistor mode.

DVSS

12

12

Digital supply voltage, negative terminal

VCC

13

13

Analog and digital supply voltage, positive terminal

VCORE (7)1414Regulated core power supply (internal use only, no external current loading)

RST/NMI/SBWTDIO

15

15

I/O

Reset or nonmaskable interrupt input.
Spy-Bi-Wire test data input/output for device programming and test.

TEST/SBWTCK

16

16

I

Selects test mode for JTAG pins on P1.0 to P1.3.
Spy-Bi-Wire test clock input for device programming and test.

I/O

General-purpose digital I/O pin.
eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI).
MCLK output.
JTAG test clock. TCK is the clock input port for device programming and test.

I/O

General-purpose digital I/O pin.
eUSCI_A0 clock input/output (direction controlled by eUSCI).
SMCLK output.
JTAG test mode select. TMS is used as an input port for device programmingand test.

I/O

General-purpose digital I/O pin.
eUSCI_A0 UART receive data or eUSCI_A0 SPI slave out/master in (direction
controlled by eUSCI).
ACLK output.
JTAG test data input or test clock input for device programming and test.

I/O

General-purpose digital I/O pin.
eUSCI_A0 UART transmit data or eUSCI_A0 SPI slave in/master out (direction
controlled by eUSCI).
Timer external clock input TACLK for TA0.
JTAG test data output port. TDO/TDI data output or programming data input
terminal.

P1.0/UCA0STE/MCLK/TCK

P1.1/UCA0CLK/SMCLK/TMS

P1.2/UCA0RXD/UCA0SOMI/
ACLK/TDI/TCLK

P1.3/UCA0TXD/UCA0SIMO/
TA0CLK/TDO/TDI

10

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17

18

19

20

17

18

19

20

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JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

表 7-1. Signal Descriptions (continued)
TERMINALNAME

NO.(2)

I/O(1)DESCRIPTION

PW

RHB

P1.4/UCB0STE/TA0.0

21

21

I/O

General-purpose digital I/O pin.
eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI).
Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output.

P1.5/UCB0CLK/TA0.1

22

22

I/O

General-purpose digital I/O pin.
eUSCI_B0 clock input/output (direction controlled by eUSCI).
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output.

I/O

General-purpose digital I/O pin.
eUSCI_B0 I2C clock or eUSCI_B0 SPI slave out/master in (direction controlled
by eUSCI).
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output.

P1.6/UCB0SCL/UCB0SOMI/
TA0.2

23

23

P1.7/UCB0SDA/UCB0SIMO/
TA1CLK

24

24

I/O

General-purpose digital I/O pin.
eUSCI_B0 I2C data or eUSCI_B0 slave input/master output (direction
controlled by eUSCI).
Timer external clock input TACLK for TA1.

P2.0/TA1.0/CLKIN

25

25

I/O

General-purpose digital I/O pin.
Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output.
DCO bypass clock input.

P2.1/TA1.1

26

26

I/O

General-purpose digital I/O pin.
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output.

P2.2/TA1.2

27

27

I/O

General-purpose digital I/O pin.
Timer TA1 CCR2 capture: CCI2A input, compare: Out2 output.

P2.3/VMONIN

28

28

I/O

General-purpose digital I/O pin.
Voltage monitor input.

P2.4/TA1.0(8)

N/A

29

I/O

General-purpose digital I/O pin.
Timer TA1 CCR0 capture: CCI0B input, compare: Out0 output.

P2.5/TA0.0(8)

N/A

30

I/O

General-purpose digital I/O pin.
Timer TA0 CCR0 capture: CCI0B input, compare: Out0 output.

P2.6/TA0.1(8)

N/A

31

I/O

General-purpose digital I/O pin.
Timer TA0 CCR1 compare: Out1 output.

P2.7/TA0.2(8)

N/A

32

I/O

General-purpose digital I/O pin.
Timer TA0 CCR2 compare: Out2 output.

(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)

I = input, O = output
N/A = not available
Short unused analog input pairs and connect them to analog ground (see セクション 7.4 for recommendations on all unused pins).
Not available on MSP430i2021 and MSP430i2020 devices.
Not available on MSP430i2031 and MSP430i2030 devices.
When the SD24 operates with the internal reference (SD24REFS = 1), the VREF pin must not be loaded externally. Connect only therecommended capacitor value (CVREF) from the VREF pin to AVSS (see セクション 8.7.7.2).
VCORE is for internal use only. No external current loading is possible. Connect VCORE to only the recommended capacitor value(CVCORE) (see セクション 8.3).
These pins are not available on the 28-pin PW package. Program these four pins to output direction and drive value 0 in software.

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JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

7.3 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if thedevice is in test mode). For details of the settings for each pin and schematics of the multiplexed ports, see セク
ション 9.11.

7.4 Connection of Unused Pins
表 7-2 lists the correct termination of all unused pins.
表 7-2. Connection of Unused Pins

(1)
(2)

12

PIN(1)POTENTIAL

AVCC

DVCC

AVSS

DVSS

COMMENT

VREF

Open

ROSC

AVSS

Connect the ROSC pin to AVSS when the DCO is used in internal resistor mode.

Px.0 to Px.7

Open

Set to port function, output direction.

Ax.0+ and Ax.0-

AVSS

Short unused analog input pairs and connect them to analog ground.

RST/NMI

DVCC or VCC

47-kΩ pullup with 10 nF (or 2.2 nF(2)) pulldown

TEST

Open

This pin always has an internal pulldown enabled.

P1.3/TDO
P1.2/TDI
P1.1/TMS
P1.0/TCKOpenThe JTAG pins are shared with general-purpose I/O function (P1.x). If these pins are notused, set them to port function and output direction. When used as JTAG pins, leave thesepins open.

For any unused pin with a secondary function that is shared with general-purpose I/O, follow the guidelines for the Px.0 to Px.7 unused
pin connection.
The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire
JTAG mode with TI tools like FET interfaces or GANG programmers.

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JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

8 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.

8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)Supply voltage applied at VCC
Voltage applied to pins

Diode current at pins

All pins except VCORE(3), ROSC(4), and SD24 input pins
(A0.0+, A0.0-, A1.0+, A1.0-, A2.0+, A2.0-, A3.0+, A3.0-)(5)

MIN

MAX

UNIT

–0.3

4.1

V

–0.3

VCC + 0.3

V

All pins except SD24 input pins (A0.0+, A0.0-, A1.0+, A1.0-,
A2.0+, A2.0-, A3.0+, A3.0-)±2

A0.0+, A0.0-, A1.0+, A1.0-, A2.0+, A2.0-, A3.0+, A3.0-(6)2Maximum junction temperature, TJ,MAX
Storage temperature, Tstg (7)
(1)
(2)
(3)
(4)
(5)
(6)
(7)

–55

mA

115

°C

150

°C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are referenced to VSS.
VCORE is for internal device use only. Do not apply external DC loading or voltage at VCORE.
Do not apply external DC loading or voltage at ROSC. Connect the recommended resistor at ROSC using the DCO in external resistor
mode. Connect ROSC to AVSS when operating the DCO in internal resistor mode.
See セクション 8.7.7.1 for SD24 specifications.
A protection diode is connected to VCC for the SD24 input pins. No protection diode is connected to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.

8.2 ESD Ratings
over operating free-air temperature range (unless otherwise noted)
VALUE
V(ESD)(1)(2)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±1000

Charged-device model (CDM), per JEDEC specification JESD22-C101(2)

±250

UNIT
V

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as±250 V may actually have higher performance.

8.3 Recommended Operating Conditions
MIN
VCC

Supply voltage during program execution and flash programming or erase (VCC = VCC)

VSS

Supply voltage (AVSS = DVSS = VSS)TA

Operating free-air temperature

T temperature range

–40

TJ

Operating junction temperature

T temperature range–40

CVCORE

Recommended capacitor at VCORE

CVCC/
CVCORE

Capacitor ratio of VCC to VCORE

10fSYSTEM

Processor frequency (maximum MCLK frequency) (1) (2)

0

(1)
(2)

NOM

2.2

MAX

UNIT

3.6

V

105

°C

0

V
105

°C

470

nF

16.384MHz

The MSP430i CPU is clocked directly with MCLK.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

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System Frequency (MHz)JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

16.3840
2.2

3.6
Supply Voltage (V)

図 8-1. Maximum System Frequency

8.4 Active Mode Supply Current (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)PARAMETERTEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

IAM, 1.024MHz

Active modecurrent at
1.024 MHzfDCO = 16.384 MHz, fMCLK = fSMCLK = 1.024 MHz,fACLK = 32 kHz,
Program executes from flash,
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0

3V

1.6

mA

IAM, 8.192MHz

Active modecurrent at
8.192 MHzfDCO = 16.384 MHz, fMCLK = fSMCLK = 8.192 MHz,fACLK = 32 kHz,
Program executes from flash,
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0

3V

3.0

mA

IAM, 16.384MHz

Active modecurrent at
16.384 MHz

fDCO = fMCLK = fSMCLK = 16.384 MHz,fACLK = 32 kHz,
Program executes from flash,
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0

3V

4.5

mA

(1)
(2)

All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
All peripherals are inactive.
4.5

4.5

3.5
3
2.5
2
1.5
1
0.5

fMCLK = 1.024 MHz
fMCLK = 2.048 MHz
fMCLK = 4.096 MHz

fMCLK = 8.192 MHz
fMCLK = 16.348 MHz

0
2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
VCC - Supply Voltage (V)D007

図 8-2. Active Mode Current vs Supply Voltage

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IAM - Active Mode Current (mA)

IAM - Active Mode Current (mA)

4

4
3.5
3
2.5
2

TA = 25°C, VCC = 2.2 V
TA = 25°C, VCC = 3 V
TA = 105°C, VCC = 2.2 V
TA = 105°C, VCC = 3 V

1.5
1
0

2

4

6
8
10
12
fMCLK - Frequency (MHz)

14

16

18
D008

図 8-3. Active Mode Current vs MCLK Frequency

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8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETERTEST CONDITIONS

TA

VCC

MIN

TYP MAX UNIT

ILPM3

Low-power mode 3(LPM3) current (2)fDCO = 16.384 MHz, fMCLK = fSMCLK = 0 MHz,fACLK = 32 kHz,CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0

25°C

3V

210

µA

ILPM4

Low-power mode 4(LPM4) current (3)fDCO = fMCLK = fSMCLK = fACLK = 0 MHz,CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1

25°C

3V

70

µA

Low-power mode 4.5(LPM4.5) current (3)fDCO = fMCLK = fSMCLK = fACLK = 0 MHz,REGOFF = 1, CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1

75

nA

ILPM4.5

325

nA

(1)
(2)
(3)

25°C
105°C

3V

All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
Current for watchdog timer clocked by ACLK included. All other peripherals are inactive.
All peripherals are inactive.

8.6 Thermal Resistance Characteristics
THERMAL METRIC(1)PACKAGEVALUE(2) (3)

UNIT

RθJA

Junction-to-ambient thermal resistance, still air

35.9

°C/W

RθJC(TOP)

Junction-to-case (top) thermal resistance

25.5

°C/W

RθJB

Junction-to-board thermal resistance

8.6

°C/W

ΨJB

Junction-to-board thermal characterization parameter

8.6

°C/W

ΨJT

Junction-to-top thermal characterization parameter

0.3

°C/W

RθJC(BOTTOM)

Junction-to-case (bottom) thermal resistance

1.4

°C/W

RθJA

Junction-to-ambient thermal resistance, still air

77.5

°C/W

RθJC(TOP)

Junction-to-case (top) thermal resistance

18.2

°C/W

RθJB

Junction-to-board thermal resistance

35.5

°C/W

ΨJB

Junction-to-board thermal characterization parameter

35.0

°C/W

ΨJT

Junction-to-top thermal characterization parameter

0.5

°C/W

RθJC(BOTTOM)

Junction-to-case (bottom) thermal resistance

N/A

°C/W

(1)
(2)

(3)

QFN-32 (RHB)

TSSOP-28 (PW)For more information about traditional and new thermal metrics, see Semiconductor and IC package thermal metrics.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC
standards:• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
N/A = Not applicable

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8.7 Timing and Switching Characteristics
8.7.1 Reset Timing
8.7.1.1 Reset Timing
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERtRESET

MIN

Pulse duration required at the RST/NMI pin to accept a reset

MAX

4

UNIT
µs

8.7.2 Clock Specifications
8.7.2.1 DCO in External Resistor Mode
recommended resistor at ROSC pin: 20 kΩ, 0.1%, ±50 ppm/°C)(1)over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IDCO
fDCO

TEST CONDITIONS

MIN

TYP

UNIT

DCO current consumption

85µA

DCO frequency calibrated

16.384MHz

DCO absolute tolerance calibrated

VCC = 3 V, TA = 25°C

±0.25%

dfDCO/dT

DCO frequency temperature drift

dfDCO/dVCC

DCO frequency supply voltage drift

200

DCDCO

Duty cycle

50%

Tdcoon

DCO start-up time

(1)

MAX

±20

ppm/°C

600

ppm/V

40

µs

The maximum parasitic capacitance at ROSC pin should not exceed 5 pF to ensure the specified DCO start-up time.

8.7.2.2 DCO in Internal Resistor Modeover recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IDCO
fDCO

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DCO current consumption

85µA

DCO frequency calibrated

16.384MHz

DCO absolute tolerance calibrated

VCC = 3 V, TA = 25°C

±0.9%

dfDCO/dT

DCO frequency temperature drift

dfDCO/dVCC

DCO frequency supply voltage drift

200

DCDCO

Duty cycle

50%

Tdcoon

DCO start-up time

40

±200

ppm/°C

600

ppm/V
µs

8.7.2.3 DCO Overall Tolerance Table
over operating free-air temperature range (unless otherwise noted)
RESISTOR OPTIONTEMPERATURE
CHANGETEMPERATURE
DRIFT (%)

VOLTAGECHANGEVOLTAGEDRIFT (%)

OVERALL
DRIFT (%)

OVERALL
ACCURACY(%)–40°C to 105 °C±2.9

2.2 V to 3.6 V±0.084±2.984±3.8840°C

02.2 V to 3.6 V±0.084±0.084±0.984

Internal resistor–40°C to 105 °C

±2.9

0V

0

±2.9

±3.8

–40°C to 105 °C±0.29

2.2 V to 3.6 V±0.084±0.374±0.6240°C

02.2 V to 3.6 V±0.084±0.084±0.334–40°C to 105 °C

±0.29

0V

0

±0.29

±0.54

External resistor with
50-ppm TCR

16

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8.7.2.4 DCO in Bypass Mode Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERfDCOBYP(1)

Frequency in DCO bypass mode(1)

MIN

MAX

UNIT

0

16.384MHz

External digital clock frequency in DCO bypass mode must be 16.384 MHz for the SD24 module to meet the specified performance.

8.7.3 Wake-up Characteristics
8.7.3.1 Wake-up Times From Low Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

tWAKE-UP-LPM3

Wake-up time from LPM3 to active mode

MCLK = SMCLK = 1.024 MHz

1µs

tWAKE-UP-LPM4

Wake-up time from LPM4 to active mode

MCLK = SMCLK = 1.024 MHz

45µs

tWAKE-UP-LPM4.5-IO

Wake-up time from LPM4.5 to activemode upon I/O event(1)CVCORE = 470 nF

0.45

ms

Wake-up time from LPM4.5 to activemode upon external reset ( RST)(1)

CVCORE = 470 nF

0.45

ms

tWAKE-UP-LPM4.5RESET(1)This value represents the time from the wake-up event to the reset vector execution by CPU.

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8.7.4 I/O Ports
8.7.4.1 Schmitt-Trigger Inputs – General-Purpose I/Oover recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VIT+

Positive-going input threshold voltage

VIT-

Negative-going input threshold voltage

Vhys

Input voltage hysteresis (VIT+ – VIT-)

CI

Input capacitance

VCC

MIN

3V

TYP

MAX

0.5 VCC

0.7 VCC

1.50

2.10

0.25 VCC

0.55 VCC

3V

0.75

1.65

3V

0.4

1.1

VIN = VSS or VCC

5

UNIT
V
V
V
pF

8.7.4.2 Inputs – Ports P1 and P2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
External interrupt timing(1)t(int)(1)TEST CONDITIONSPort P1, P2: P1.x to P2.x, External trigger pulse
duration to set interrupt flag

VCC

MIN

3V

20

MAX

UNIT
ns

An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).

8.7.4.3 Leakage Current – General-Purpose I/Oover recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Py.x)(1)(2)

TEST CONDITIONS
See (1) (2)High-impedance leakage current

VCC

MIN

3V

MAX

UNIT

±50

nA

MAX

UNIT

The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input.

8.7.4.4 Outputs – General-Purpose I/Oover recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCC

MIN

= –6 mA(1)3.0 V

VCC – 0.60

VCC

V

3.0 V

VSS

VSS + 0.60

V

VOH

High-level output voltage

I(OHmax)VOL

Low-level output voltage

I(OLmax) = 6 mA(1)(1)

The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.

8.7.4.5 Output Frequency – General-Purpose I/Oover recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fPy.x

Port output frequency (with load)

fPort_CLK Clock output frequency

TEST CONDITIONS

VCC

TYP

UNIT

= 3.2 kΩ (1) (2)3V

16.384MHz

3V

16.384MHz

Py.x, CL = 20 pF, RL
Py.x, CL = 20 pF(2)

(1)
(2)

A resistive divider with two times 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
The output voltage reaches at least 10% and 90% of VCC at the specified toggle frequency.

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8.7.4.6 Typical Characteristics – Outputs
One output loaded at a time.
22
20

12

IOL - Low Output Current (mA)

IOL - Low-Level Output Current (mA)

14

10
8
6
4
2
0

TA = 25°C
TA = 105°C

16
14
12
10
8
6
4
2

TA = 25°C
TA = 105°C

0

-2

-2
0

0.25

0.5 0.75
1
1.25 1.5 1.75
VOL - Low-Level Output Voltage (V)VCC = 2.2 V

2

2.25

0

0.3

D004

Measured at P1.3

0.6

0.9 1.2 1.5 1.8 2.1 2.4
VOL - Low Output Voltage (V)VCC = 3 V

図 8-4. Typical Low-Level Output Current vs LowLevel Output Voltage

2.7

3
D003

Measured at P1.3

図 8-5. Typical Low-Level Output Current vs LowLevel Output Voltage00TA = 25°C
TA = 105°C-2

IOH - High-Level Output Current (mA)IOH - High-Level Output Current (mA)

18

-4
-6
-8
-10

TA = 25°C
TA = 105°C

-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
-22

-12
0

0.2

0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VOH - High-Level Output Voltage (V)VCC = 2.2 V

2

2.2
D006

Measured at P1.3

図 8-6. Typical High-Level Output Current vs HighLevel Output Voltage

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0

0.3

0.6 0.9 1.2 1.5 1.8 2.1 2.4
VOH - High-Level Output Voltage (V)VCC = 3 V

2.7

3
D005

Measured at P1.3

図 8-7. Typical High-Level Output Current vs HighLevel Output Voltage

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8.7.5 Power Management Module
8.7.5.1 PMM, High-Side Brownout Reset (BORH)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

V(VCC_BOR_IT–)BORH on voltage, VCC falling level| dVCC/dt | < 3 V/s

1.08

V

V(VCC_BOR_IT+)BORH off voltage, VCC rising level| dVCC/dt | < 3 V/s

1.18

V

V(VCC_BOR_hys)

BORH hysteresistPOWERUP (1)Cold power-up time

(1)

100

mV
0.75

ms

MAX

UNIT

This is the time duration between application of VCC and execution of reset vector by CPU.

8.7.5.2 PMM, Low-Side SVS (SVSL)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(SVSL)

MIN

TYP
1.70

V

V(SVSL_hys) SVSL hysteresis

SVSL trip voltage on VCORE

14mV

I(SVSL)

3µA

SVSL current consumption

8.7.5.3 PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCORE

MIN

TYP

Core voltage

MAX

1.83

UNIT
V

8.7.5.4 PMM, Voltage Monitor (VMON)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER

VMONtrip_level

MIN

TYP

VMONLVLx = 111b

1.17

VCC trip level – 1

VMONLVLx = 001b

2.32

VCC trip level – 2

VMONLVLx = 010b

2.62

VCC trip level – 3

VMONLVLx = 011b

2.82

IVMON

VMON current consumptiontVMON

VMON settling time

20

TEST CONDITIONSVMONIN trip level

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MAX

UNIT

V

6

µA

0.5

µs

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8.7.6 Reference Module
8.7.6.1 Voltage Reference (REF)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCCSupply voltage range

VBG

Bandgap output voltage calibrated

VCC = 3 V

PSRR_DCPower supply rejection ratio (DC)VCC = 2.2 V to 3.6 V

PSRR_ACPower supply rejection ratio (AC)VCC = 2.2 V to 3.6 V, f = 1 kHz,ΔVpp = 100 mV

dVBG/dT

Bandgap reference temperature coefficient

VCC = 3 V

MIN

TYP

2.2
1.146

1.158

MAX

UNIT

3.6

V

1.17

V

50

µV/V

0.35

mV/V

10

50 ppm/°C

8.7.6.2 Temperature Sensor
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Vsensor

Temperature sensor output voltage

Isensor

Temperature sensor quiescent current consumption

TCsensor

Temperature coefficient of sensor

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TEST CONDITIONS

MIN

TYP

MAX

VCC = 3 V, TA = 30°C

610

650

690

VCC = 3 V, TA = 105°C

765

805

845

1.96

2.07

UNIT

3

mV
µA

2.17 mV/°C

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8.7.7 SD24
8.7.7.1 SD24 Power Supply and Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETERVCCTEST CONDITIONS

Supply voltage range
Analog plus digital supply current perconverter (reference current not included)

ISD24

VCC

AVSS = DVSS = 0 V
SD24OSRx = 256

MIN

TYP

2.2

GAIN: 1, 2, 4, 8, 16

3V

GAIN: 1, 16

3V

MAX

UNIT

3.6

V

190
250

µA

8.7.7.2 SD24 Internal Voltage Reference
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETERTEST CONDITIONSVSD24REF

SD24 internal reference voltage

SD24REFS = 1

CVREF

Recommended capacitor at VREF

tSD24REF_settle SD24 reference buffer settling time
(1)

VCC

MIN

TYP

MAX

UNIT

3V

1.146

1.158

1.17

V

SD24REFS = 0 → 1, CVREF = 100 nF

100

nF

200

µs

When SD24 operates with internal reference (SD24REFS = 1), the VREF pin must not be loaded externally. Only the recommended
capacitor value, CVREF must be connected at the VREF pin to AVSS.

8.7.7.3 SD24 External Voltage Reference
over operating free-air temperature range (unless otherwise noted)
VCC

MIN

TYP

MAX

UNIT

VREF(I)

Input voltage range

PARAMETER
SD24REFS = 0

TEST CONDITIONS

3V

1.0

1.2

1.5

V

IREF(I)

Input current

SD24REFS = 0

3V

50

nA

MAX

UNIT

+VREF/
GAIN

V

8.7.7.4 SD24 Input Range
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
VID,FSR

VID

Differential full-scale input voltage
range

Differential input voltage range for
specified performance(2)TEST CONDITIONS

VCC

TYP

–VREF/GAIN

VID = VI,A+ – VI,A–

SD24REFS = 1

MIN

SD24GAINx = 1±928

SD24GAINx = 2±464

SD24GAINx = 4±232

SD24GAINx = 8±116

SD24GAINx = 16

±58

mV

ZI

Input impedance(pin A+ or A- to AVSS)(3)SD24GAINx = 1, 16

3V

ZID

Differential input impedance (pin A+
to pin A-)(3)SD24GAINx = 1, 16

3V

VI

Absolute input voltage range

AVSS – 1

VCC

V

VIC

Common-mode input voltage range

AVSS – 1

VCC

V

(1)
(2)

300

200

kΩ

400

kΩ

(3)

All parameters pertain to each SD24 channel.
The full-scale range is defined by VFSR+ = +VREF/GAIN and VFSR– = –VREF/GAIN; FSR = VFSR+ – VFSR– = 2xVREF/GAIN. If VREF issourced externally, the analog input range should not exceed 80% of VFSR+ or VFSR–; that is, VID = 0.8 VFSR– to 0.8 VFSR+. If VREF issourced internally, the given VID ranges apply.
Applicable for SD24 modulator OFF as well as ON conditions.

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8.7.7.5 SD24 Performance, Internal Reference (SD24REFS = 1, SD24OSRx = 256)over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCSD24GAINx = 1

MIN

TYP

84

89

SD24GAINx = 2
SINAD

Signal-to-noise +distortion ratio

SD24GAINx = 43V

83

SD24GAINx = 16

77
100
fIN = 50 Hz(1)3V

95

SD24GAINx = 16
Spurious-free dynamic
range

INL

Integral nonlinearity,
end-point fit

SD24GAINx = 8

100
fIN = 50 Hz(1)3V

95

SD24GAINx = 16
SD24GAINx: 1, 8, 16

3V–0.003

SD24GAINx = 4

8

SD24GAINx = 16

16

Gain error

SD24GAINx: 1, 2, 4, 8, 16

3V

ΔEG/ ΔT

Gain error temperature
coefficient

SD24GAINx: 1, 8, 16

3V

EOS

Offset error

ΔEOS/ΔT

Offset error temperature SD24GAINx = 1
coefficient
SD24GAINx = 16

SD24GAINx = 16

SD24GAINx = 1, Common-mode input signal:
Common-mode rejection VID = 928 mV, fIN = 50 Hz
ratio at 50 Hz
SD24GAINx = 16, Common-mode input signal:

AC power supply
rejection ratio

3V

Crosstalk between
converters

50 ppm/°C
4
2
±5
±3

±25

ppm
±10 FSR/°C

dB
–60

3V

–90

SD24GAINx: 8, VCC = 3 V ±50 mV × sin(2π × fVCC × t), fVCC =50 Hz, Inputs grounded (no analog signal applied)

3V

–95

SD24GAINx: 16, VCC = 3 V ±50 mV × sin(2π × fVCC × t), fVCC =50 Hz, Inputs grounded (no analog signal applied)

3V

–95

Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
possible VPP, fIN = 50 Hz or 100 Hz, Converter under test:
SD24GAINx = 8

mV

–55

SD24GAINx: 1, VCC = 3 V ±50 mV × sin(2π × fVCC × t), fVCC =50 Hz, Inputs grounded (no analog signal applied)

Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
possible VPP, fIN = 50 Hz or 100 Hz, Converter under test:
SD24GAINx = 16

(1)

2%

3V

Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
possible VPP, fIN = 50 Hz or 100 Hz, Converter under test:
SD24GAINx = 1
XT

–2%

3V

VID = 58 mV, fIN = 50 Hz

AC PSRR

4

SD24GAINx = 8

SD24GAINx = 1

% FSR

2
3V

EG

CMRR,50Hz

0.003
1

SD24GAINx = 2
Nominal gaindB

90

SD24GAINx = 1

G

dB

90

SD24GAINx = 1
SFDR

dB

87

SD24GAINx = 8

Total harmonic distortion SD24GAINx = 8

UNIT

89
fIN = 50 Hz(1)SD24GAINx = 1
THD

MAX

dB

–120

3V

–110

dB

–110

The following voltages are applied to the SD24 inputs:
VI,A+(t) = 0 V + VPP/2 × sin(2π × fIN × t)
VI,A–(t) = 0 V – VPP/2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VIN,A+(t) – VIN,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24 input range).

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8.7.7.6 SD24 Performance, External Reference (SD24REFS = 0, SD24OSRx = 256)
external reference voltage is 1.2 V., over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCC

MIN

SD24GAINx = 1
Signal-to-noise + distortion
ratio

SD24GAINx = 4

Total harmonic distortion

3V

83

SD24GAINx = 16

77
100
fIN = 50 Hz(1)3V

95

SD24GAINx = 16
Spurious-free dynamic
range

INL

Integral nonlinearity, endpoint fit

SD24GAINx = 8

100
fIN = 50 Hz(1)3V

95

SD24GAINx = 16
SD24GAINx: 1, 8, 16

3V–0.003

SD24GAINx = 4

8

SD24GAINx = 16

16

Gain error

SD24GAINx: 1, 2, 4, 8, 16

3V

ΔEG/ ΔT

Gain error temperature
coefficient

SD24GAINx: 1, 8, 16

3V

EOS

Offset error

ΔEOS/ΔT

Offset error temperature
coefficient

CMRR,50Hz

Common-mode rejection
ratio at 50 Hz

AC power supply rejection
ratio

SD24GAINx = 16
SD24GAINx = 1
SD24GAINx = 16
SD24GAINx = 1, Common-mode input signal:
VID = 928 mV, fIN = 50 Hz
SD24GAINx = 16, Common-mode input signal:
VID = 58 mV, fIN = 50 Hz

Crosstalk between
converters

–1%

+1%
10 ppm/°C
4

3V

3V

2
±5
±3

ppm
±10 FSR/°C

dB

3V

–90

SD24GAINx: 8, VCC = 3 V ±50 mV × sin(2π × fVCC × t), fVCC =50 Hz, Inputs grounded (no analog signal applied)

3V

–95

SD24GAINx: 16, VCC = 3 V ±50 mV × sin(2π × fVCC × t), fVCC
= 50 Hz, Inputs grounded (no analog signal applied)

3V

–95

Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
possible VPP, fIN = 50 Hz or 100 Hz, Converter under test:
SD24GAINx = 16

±25

–60

SD24GAINx: 1, VCC = 3 V ±50 mV × sin(2π × fVCC × t), fVCC =50 Hz, Inputs grounded (no analog signal applied)

Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
possible VPP, fIN = 50 Hz or 100 Hz, Converter under test:
SD24GAINx = 8

mV

–55
3V

Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
possible VPP, fIN = 50 Hz or 100 Hz, Converter under test:
SD24GAINx = 1
XT

4

SD24GAINx = 8

SD24GAINx = 1

% FSR

2
3V

EG

AC PSRR

0.003
1

SD24GAINx = 2
Nominal gaindB

90

SD24GAINx = 1

G

dB

90

SD24GAINx = 1
SFDR

dB

88

SD24GAINx = 8

SD24GAINx = 8

UNIT

90
fIN = 50 Hz(1)SD24GAINx = 1
THD

MAX

91

SD24GAINx = 2
SINAD

TYP

dB

–120

3V

–110

dB

–110

(1)

The following voltages are applied to the SD24 inputs:
VI,A+(t) = 0 V + VPP/2 × sin(2π × fIN × t)
VI,A–(t) = 0 V – VPP/2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VIN,A+(t) – VIN,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24 input range).

24

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8.7.7.7 Typical Characteristics
90

90

87
85

84

80

78

SINAD (dB)

SINAD (dB)

81

75
72
69

75
70
65

66
63

60

60
57
25

A.

55

50

75

100

fSD24 = 1.024 MHz

125

150 175
OSR

200

SD24REFS = 1

図 8-8. SINAD vs OSR

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225

250

0

275

0.2

0.4

D001

SD24GAINx = 1

A.

fSD24 = 1.024 MHz
OSR = 256

0.6
VPP (V)

0.8

1

1.2
D002

SD24REFS = 1
SD24GAINx = 1

図 8-9. SINAD vs VPP

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8.7.8 eUSCI
8.7.8.1 eUSCI (UART Mode) Clock Frequency
PARAMETER
feUSCIeUSCI input clock frequency

fBITCLKBITCLK clock frequency(equals baud rate in MBaud)TEST CONDITIONSMINInternal: SMCLK or ACLK,
External: UCLK
Duty cycle = 50% ±10%

MAX

UNIT

fSYSTEM

MHz

4

MHz

8.7.8.2 eUSCI (UART Mode) Deglitch Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCC

MIN

TYP

8

15

30

50

60

50

70

100

70

100

150

UCGLITx = 0
UART receive deglitch time(1)tt

UCGLITx = 1

2.2 V, 3 V

UCGLITx = 2
UCGLITx = 3(1)

MAX UNIT
20
ns

Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses arecorrectly recognized their width should exceed the maximum specification of the deglitch time.

8.7.8.3 eUSCI (SPI Master Mode) Clock Frequency
PARAMETER
feUSCIeUSCI input clock frequency

TEST CONDITIONSMINInternal: SMCLK or ACLK,
Duty cycle = 50% ±10%

MAX

UNIT

fSYSTEM

MHz

MAX

UNIT

8.7.8.4 eUSCI (SPI Master Mode) Timing
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
VCC

MIN

tSTE,LEAD

STE lead time, STE active to clock

PARAMETERUCSTEM = 1, UCMODEx = 01 or 10

TEST CONDITIONS

2.2 V, 3 V

150tSTE,LAG

STE lag time, Last clock to STE inactive

UCSTEM = 1, UCMODEx = 01 or 10

2.2 V, 3 V

200tSTE,ACC

STE access time, STE active to SIMO
data out

UCSTEM = 0, UCMODEx = 01 or 10

tSTE,DIS

STE disable time, STE inactive to SIMO
high impedance

UCSTEM = 0, UCMODEx = 01 or 10

tSU,MISOMI input data setup time

tHD,MISOMI input data hold timetVALID,MO

SIMO output data valid time(2)UCLK edge to SIMO valid, CL = 20 pF

tHD,MOSIMO output data hold time(3)CL = 20 pF

(1)
(2)
(3)

26

ns
ns

2.2 V

40

3V

30

2.2 V

40

3V

30

2.2 V

50

3V

30

2.2 V, 3 V

0

ns
7

3V

5
0

ns
ns

2.2 V
2.2 V, 3 V

ns

ns
ns

fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), refer to the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in 図 8-10 and 図 8-11.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the dataon the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in 図
8-10 and 図 8-11.

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UCMODEx = 01
tSTE,LEAD

STEtSTE,LAGUCMODEx = 10
1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLOW/HIGHtLOW/HIGH

tSU,MI
tHD,MI

SOMI
tHD,MOtSTE,ACC

tSTE,DIStVALID,MOSIMO

図 8-10. SPI Master Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD

STEtSTE,LAGUCMODEx = 10
1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLOW/HIGHtLOW/HIGH
tSU,MI

tHD,MI

SOMI
tHD,MOtSTE,ACCtVALID,MOtSTE,DISSIMO

図 8-11. SPI Master Mode, CKPH = 1

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8.7.8.5 eUSCI (SPI Slave Mode) Timing
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
VCC

MIN

tSTE,LEAD

STE lead time, STE active to clock

PARAMETERTEST CONDITIONS

2.2 V, 3 V

3tSTE,LAG

STE lag time, Last clock to STE inactive

2.2 V, 3 V

0

3V

25
35

tSTE,DIS

STE disable time, STE inactive to SOMI highimpedance

2.2 V, 3 V

tSU,SISIMO input data setup time

2.2 V, 3 V

1tHD,SISIMO input data hold time

2.2 V, 3 V

5SOMI output data valid time(2)UCLK edge to SOMI valid,
CL = 20 pF

tHD,SOSOMI output data hold time(3)CL = 20 pF

(1)
(2)
(3)

ns
35

STE access time, STE active to SOMI data out

3V

25

3V

25

ns

ns
35

35

ns

ns

2.2 V
2.2 V

UNIT
ns

2.2 V

tSTE,ACCtVALID,SO

MAX

ns
ns

fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), refer to the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in 図 8-12 and 図 8-13.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in 図
8-12 and 図 8-13.

UCMODEx = 01
tSTE,LEAD

STEtSTE,LAGUCMODEx = 10
1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLOW/HIGHtSU,SItLOW/HIGHtHD,SI
SIMO
tHD,SOtSTE,ACCtVALID,SOtSTE,DISSOMI

図 8-12. SPI Slave Mode, CKPH = 0

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UCMODEx = 01
tSTE,LEAD

STEtSTE,LAGUCMODEx = 10
1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLOW/HIGHtLOW/HIGHtHD,SItSU,SI

SIMO
tHD,SOtSTE,ACCtVALID,SOtSTE,DISSOMI

図 8-13. SPI Slave Mode, CKPH = 1

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8.7.8.6 eUSCI (I2C Mode) Timing
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 図 8-14)
PARAMETERTEST CONDITIONS

feUSCIeUSCI input clock frequencyfSCL

SCL clock frequency

MIN

2.2 V, 3 V

tHD,STA

Hold time (repeated) STARTtSU,STA

Setup time for a repeated STARTtHD,DAT

Data hold time

tSU,DAT

Data setup time

tSU,STO

Setup time for STOPfSCL = 100 kHz

TYP

02.2 V, 3 V

fSCL > 100 kHz
fSCL = 100 kHz

fSCL = 100 kHz
fSCL = 100 kHz

kHz
µs
µs
µs

4.7

µs

1.08
4.9

µs

1.18

UCGLITx = 0

75

110

160

UCGLITx = 1

35

50

80

15

25

40

10

15

20

2.2 V, 3 V

UCGLITx = 2
UCCLTOx = 1

37

2.2 V, 3 V

UCCLTOx = 3

ms

41

tSU,STAtHD,STAns

33

UCCLTOx = 2

Clock low timeout

400

0.12

UCGLITx = 3
tTIMEOUT

MHz

1.26

2.2 V, 3 V

fSCL > 100 kHz

fSYSTEM

4.9

2.2 V, 3 V

fSCL > 100 kHz

UNIT

1.2

2.2 V, 3 V

fSCL > 100 kHz

MAX

4.8

2.2 V, 3 V

Pulse duration of spikes suppressedby input filter

tSP

VCC

Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%

tHD,STA

tBUF

SDA
tLOW

tHIGH

tSP

SCL

tSU,DATtSU,STOtHD,DAT

図 8-14. I2C Mode Timing

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8.7.9 Timer_A
8.7.9.1 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

fTA

Timer_A input clock frequency

Internal: SMCLK
External: TACLKtTA,cap

Timer_A capture timing

All capture inputs, Minimum pulse
duration required for capture

VCC
3.0 V
3.0 V

MIN

TYP

MAX UNIT
16.384

MHz

20

ns

8.7.10 Flash8.7.10.1 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTESTCONDITIONS

VCC

MIN

TYP

MAX

UNIT

VCC(PGM/ERASE)

Program and erase supply voltage

2.2

3.6

V

fFTG

Flash timing generator frequency

257

476

kHz

IPGM

Supply current from VCC during program

2.2 V, 3.6 V

8mA

IERASE

Supply current from VCC during erase

2.2 V, 3.6 V

13

mA

tCPT

Cumulative program time(1)2.2 V, 3.6 V

Program and erase endurance

8
20000

tRetention

Data retention duration

TJ = 25°C

tWord

Word or byte program time

(2)

25

tBlock, 0

Block program time for first byte or word

(2)

20

tBlock, 1-63

Block program time for each additional byte or
word

(2)

11

tBlock, End

Block program end-sequence wait time

(2)

6

tMass Erase

Mass erase time

(2)

10593

Segment erase time

(2)

9628

tSeg Erase
(1)
(2)

ms
cycles

100

years

tFTG

The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word-write mode, individual byte-write mode, and block-write mode.
These values are hardwired into the state machine of the flash controller (tFTG = 1/fFTG).

8.7.11 Emulation and Debug
8.7.11.1 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER

VCC

MIN

TYP

MAX

UNIT

fSBW

Spy-Bi-Wire input frequency

3.0 V

0

20

MHz

tSBW,Low

Spy-Bi-Wire low clock pulse duration

3.0 V

0.025

15

μs

tSBW, En

Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)(1)

3.0 V

1

μs

tSBW,Rst

Spy-Bi-Wire return to normal operation time

3.0 V

15

100

μs

fTCK

TCK input frequency, 4-wire JTAG(2)

3.0 V

0

10

MHz

Rinternal

Internal pulldown resistance on TEST

3.0 V

45

80

kΩ

(1)
(2)

60

Tools that access the Spy-Bi-Wire interface must wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.

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9 Detailed Description
9.1 Overview
The MSP430i204x, MSP430i203x, MSP430i202x devices consist of a powerful 16-bit RISC CPU, a DCO-based
clock system that generates system clocks, a power-management module (PMM) with built-in voltage reference
and voltage monitor, two to four 24-bit sigma-delta analog-to-digital converters (ADCs), a temperature sensor, a16-bit hardware multiplier, two 16-bit timers, one eUSCI-A module and one eUSCI-B module, a watchdog timer(WDT), and up to 16 I/O pins.

9.2 Functional Block Diagrams
図 9-1 shows the functional block diagram for the MSP430i2041 and MSP430i2040 in the RHB package.
ROSC

VCC DVSS AVSS VCORE RST/NMI

P1.x
8

P2.x
8

ACLK
Clock
System

Flash

RAM

32KB
16KB

2KB
1KB

Power
Management

SD24

SMCLK
MCLK

16.384-MHz
CPU
with 16
registers

TA0

TA1

Port P1

Port P2

Timer_A
3 CC
Registers

Timer_A
3 CC
Registers

8 I/Os,Interrupt
capability

8 I/Os,Interrupt
capability

HardwareMultiplier(16x16)

eUSCI_A0

eUSCI_B0

UART,
IrDA, SPISPI, I C

MAB
MDBEmulation
2BP
JTAG
Interface
Spy-BiWire

LDO
REF
VMON
Brownout

Watchdog
4
WDT
Sigma-Delta
Analog-to- 15 or 16 bit
DigitalConverters

MPY,
MPYS,
MAC,
MACS

2

図 9-1. Functional Block Diagram – RHB Package – MSP430i2041, MSP430i2040

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図 9-2 shows the functional block diagram for the MSP430i2041 and MSP430i2040 in the PW package.
ROSC

VCC

DVSS

AVSS VCORE

RST/NMI

P1.x

P2.x

8

4

ACLK
Clock
System

Flash

RAM

32KB
16KB

2KB
1KB

Power
Management

SD24

SMCLK
MCLK

16.384-MHz
CPU

MAB

with 16
registers

MDB

TA0

TA1

Port P1

Port P2

Timer_A
3 CC
Registers

Timer_A
3 CC
Registers

8 I/Os,Interrupt
capability

4 I/Os,Interrupt
capability

HardwareMultiplier(16x16)

eUSCI_A0

Emulation
2BP

JTAG
Interface

Spy-BiWire

LDO
REF
VMON
Brownout

4
Sigma-Delta
Analog-toDigital
Converters

Watchdog
WDT
15 or 16 bit

MPY,
MPYS,
MAC,
MACS

UART,
IrDA, SPI

eUSCI_B0
2

SPI, I C

図 9-2. Functional Block Diagram – PW Package – MSP430i2041, MSP430i2040

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JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

図 9-3 shows the functional block diagram for the MSP430i2031 and MSP430i2030 in the RHB package.
ROSC

VCC

DVSS

AVSS VCORE

RST/NMI

P1.x

P2.x

8

8

ACLK
Clock
System

Flash

RAM

32KB
16KB

2KB
1KB

Power
Management

SD24

SMCLK
MCLK

16.384-MHz
CPU

MAB

with 16
registers

MDB

TA0

TA1

Port P1

Port P2

Timer_A
3 CC
Registers

Timer_A
3 CC
Registers

8 I/Os,Interrupt
capability

8 I/Os,Interrupt
capability

HardwareMultiplier(16x16)

eUSCI_A0

Emulation
2BP

JTAG
Interface

Spy-BiWire

LDO
REF
VMON
Brownout

3
Sigma-Delta
Analog-toDigital
Converters

Watchdog
WDT
15 or 16 bit

MPY,
MPYS,
MAC,
MACS

UART,
IrDA, SPI

eUSCI_B0
2

SPI, I C

図 9-3. Functional Block Diagram – RHB Package – MSP430i2031, MSP430i2030

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JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

図 9-4 shows the functional block diagram for the MSP430i2031 and MSP430i2030 in the PW package.
ROSC

VCC

DVSS

AVSS VCORE

RST/NMI

P1.x

P2.x

8

4

ACLK
Clock
System

Flash

RAM

32KB
16KB

2KB
1KB

Power
Management

SD24

SMCLK
MCLK

16.384-MHz
CPU

MAB

with 16
registers

MDB

TA0

TA1

Port P1

Port P2

Timer_A
3 CC
Registers

Timer_A
3 CC
Registers

8 I/Os,Interrupt
capability

4 I/Os,Interrupt
capability

HardwareMultiplier(16x16)

eUSCI_A0

Emulation
2BP

JTAG
Interface

Spy-BiWire

LDO
REF
VMON
Brownout

3
Sigma-Delta
Analog-toDigital
Converters

Watchdog
WDT
15 or 16 bit

MPY,
MPYS,
MAC,
MACS

UART,
IrDA, SPI

eUSCI_B0
2

SPI, I C

図 9-4. Functional Block Diagram – PW Package – MSP430i2031, MSP430i2030

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JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

図 9-5 shows the functional block diagram for the MSP430i2021 and MSP430i2020 in the RHB package.
ROSC

VCC

DVSS

AVSS VCORE

RST/NMI

P1.x

P2.x

8

8

ACLK
Clock
System

Flash

RAM

32KB
16KB

2KB
1KB

Power
Management

SD24

SMCLK
MCLK

16.384-MHz
CPU

MAB

with 16
registers

MDB

TA0

TA1

Port P1

Port P2

Timer_A
3 CC
Registers

Timer_A
3 CC
Registers

8 I/Os,Interrupt
capability

8 I/Os,Interrupt
capability

HardwareMultiplier(16x16)

eUSCI_A0

Emulation
2BP

JTAG
Interface

Spy-BiWire

LDO
REF
VMON
Brownout2
Sigma-Delta
Analog-toDigital
Converters

Watchdog
WDT
15 or 16 bit

MPY,
MPYS,
MAC,
MACS

UART,
IrDA, SPI

eUSCI_B0
2

SPI, I C

図 9-5. Functional Block Diagram – RHB Package – MSP430i2021, MSP430i2020

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JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

図 9-6 shows the functional block diagram for the MSP430i2021 and MSP430i2020 in the PW package.
ROSC

VCC

DVSS

AVSS VCORE

RST/NMI

P1.x

P2.x

8

4

ACLK
Clock
System

Flash

RAM

32KB
16KB

2KB
1KB

Power
Management

SD24

SMCLK
MCLK

16.384-MHz
CPU

MAB

with 16
registers

MDB

TA0

TA1

Port P1

Port P2

Timer_A
3 CC
Registers

Timer_A
3 CC
Registers

8 I/Os,Interrupt
capability

4 I/Os,Interrupt
capability

HardwareMultiplier(16x16)

eUSCI_A0

Emulation
2BP

JTAG
Interface

Spy-BiWire

LDO
REF
VMON
Brownout2
Sigma-Delta
Analog-toDigital
Converters

Watchdog
WDT
15 or 16 bit

MPY,
MPYS,
MAC,
MACS

UART,
IrDA, SPI

eUSCI_B0
2

SPI, I C

図 9-6. Functional Block Diagram – PW Package – MSP430i2021, MSP430i2020

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9.3 CPU
The MSP430i CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constantgenerator respectively. The remaining registers are general-purpose registers (see 図 9-7).
Peripherals are connected to the CPU using data, address, and control buses and can be handled with all
instructions.
Program Counter

PC/R0

Stack Pointer

SP/R1

Status Register

SR/CG1/R2

Constant Generator

CG2/R3General-Purpose Register

R4

General-Purpose Register

R5

General-Purpose Register

R6

General-Purpose Register

R7

General-Purpose Register

R8

General-Purpose Register

R9

General-Purpose Register

R10

General-Purpose Register

R11

General-Purpose Register

R12

General-Purpose Register

R13

General-Purpose Register

R14

General-Purpose RegisterR15

図 9-7. CPU Registers
注意
The CPU will lock up if the device enters a low-power mode (CPU off) within 64 cycles after reset.

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9.4 Instruction Set
The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction canoperate on word and byte data. 表 9-1 gives examples of the three types of instruction formats; 表 9-2 lists theaddress modes.
表 9-1. Instruction Word Formats
INSTRUCTION FORMAT

EXAMPLEOPERATION

Dual operands, source and destination

ADD R4,R5

R4 + R5 → R5

Single operands, destination only

CALL R8

PC → (TOS), R8 → PC

Relative jump, unconditional or conditional

JNE

Jump-on-equal bit = 0

表 9-2. Address Mode Descriptions

(1)
(2)

ADDRESS MODE

S (1)

D (2)

SYNTAX

EXAMPLEOPERATION

Register✓✓

MOV Rs,Rd

MOV R10,R11

R10 → R11

Indexed✓✓MOV X(Rn),Y(Rm)

MOV 2(R5),6(R6)M(2+R5) → M(6+R6)

Symbolic (PC relative)✓✓

MOV EDE,TONI

M(EDE) → M(TONI)

Absolute✓✓

MOV &MEM,&TCDAT

M(MEM) → M(TCDAT)

Indirect✓

MOV @Rn,Y(Rm)

MOV @R10,Tab(R6)

M(R10) → M(Tab+R6)

Indirect autoincrement✓

MOV @Rn+,Rm

MOV @R10+,R11

M(R10) → R11
R10 + 2 → R10

Immediate✓

MOV #X,TONI

MOV #45,TONI#45 → M(TONI)

S = source
D = destination

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9.5 Operating Modes
MSP430i204x, MSP430i203x, MSP430i202x devices have one active mode and four software-selectable lowpower modes. An interrupt event can wake up the device from the low-power modes LPM0 to LPM4, service therequest, and restore back to the low-power mode on return from the interrupt program.
The following five operating modes can be configured by software:
•
•

•

•

•

40

Active mode (AM)– All clocks are active.
Low-power mode 0 or low-power mode 1 (LPM0 = LPM1)– CPU is disabled– Internal regulator remains enabled– DCO remains enabled– MCLK is disabled– ACLK and SMCLK remain active
Low-power mode 2 or low-power mode 3 (LPM2 = LPM3)– CPU is disabled– Internal regulator remains enabled– DCO remains enabled– MCLK and SMCLK are disabled– ACLK remains active
Low-power mode 4 (LPM4)– CPU is disabled– Internal regulator remains enabled– DCO is disabled– MCLK, SMCLK, and ACLK are disabled
Low-power mode 4.5 (LPM4.5)– Internal regulator is disabled– No RAM retention– I/O pad state retention– Wake from RST/NMI, ports pins P2.1 or P2.2

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9.6 Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are in the address range 0FFFFh to 0FFE0h. The vector
contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed), theCPU goes into LPM4 immediately after power up.
表 9-3. Interrupt Vector Addresses
INTERRUPT SOURCEINTERRUPT FLAG

Power upExternal reset
Watchdog
Flash key violation
PC out-of-range (1)BORIFGRSTIFGWDTIFGKEYV

SYSTEM INTERRUPTWORD ADDRESSPRIORITY

Reset

0FFFEh15, highest

NMI
Oscillator fault
Flash memory access violation

NMIIFGOFIFG
ACCVIFG (2) (4)(Non)maskable,(Non)maskable,(Non)maskable

0FFFCh14

Timer TA1

TA1CCR0 CCIFG (3)Maskable

0FFFAh13

Timer TA1

TA1CCR1 CCIFG,
TA1CCR2 CCIFG,
TA1CTL TAIFG (2) (3)Maskable

0FFF8h12Voltage monitor

VMONIFG

Maskable

0FFF6h11(2)

Watchdog timer

WDTIFG

Maskable

0FFF4h10

eUSCI_A0 receive or transmit

UCA0RXIFG, UCA0TXIFG

Maskable

0FFF2h9

eUSCI_B0 receive or transmit

UCB0RXIFG, UCB0TXIFG

Maskable

0FFF0h8

SD24

SD24CCTLx SD24OVIFG,
SD24CCTLx SD24IFG(2) (3)Maskable

0FFEEh7Timer TA0

TA0CCR0 CCIFG (3)Maskable

0FFECh6Timer TA0

TA0CCR1 CCIFG,
TA0CCR2 CCIFG,
TA0CTL TAIFG (2) (3)Maskable

0FFEAh5

I/O port P1

P1IFG.0 to P1IFG.7 (2) (3)Maskable

0FFE8h4

0FFE6h3

0FFE4h2

0FFE2h10FFE0h0, lowest

I/O port P2

(1)
(2)
(3)
(4)

P2IFG.0 to P2IFG.7 (2) (3)Maskable

A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or fromwithin unused address range.
Multiple source flags
Interrupt flags are in the module.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

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9.7 Special Function Registers
Some interrupt enable and interrupt flag bits are collected into the lowest address space. Special function
register bits not allocated to a functional purpose are not physically present in the device. Simple software
access is provided with this arrangement.
Legendrw

Bit can be read and written.

rw-0, rw-1

Bit can be read and written. It is Reset or Set by PUC.

rw-(0), rw-(1)Bit can be read and written. It is Reset or Set by POR.

rw-[0], rw-[1]Bit can be read and written. It is Reset or Set by BOR.
SFR bit is not present in device.

表 9-4. Interrupt Enable 1 (Address = 00h)
7

6

5

4

1

0

ACCVIE

NMIIE

3

2

OFIE

WDTIE

rw-0

rw-0

rw-0

rw-0

WDTIE

Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer
mode.

OFIE

Oscillator fault interrupt enable

NMIIE(Non)maskable interrupt enable

ACCVIE

Flash access violation interrupt enable

表 9-5. Interrupt Flag Register 1 (Address = 02h)
7

6

5

4

3

2

1

0

NMIIFGRSTIFGBORIFGOFIFG

WDTIFG

rw-0

rw-[0]

rw-[1]

rw-0

rw-(0)WDTIFG

Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.

OFIFG

Flag set on oscillator fault. This flag can be cleared by software when the oscillator runs free of fault.

BORIFG

Brown out reset flag. This bit is set after VCC power up and can be cleared by software.

RSTIFG

External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.

NMIIFGSet by the RST/NMI pin in NMI configuration.

9.8 Flash Memory
The flash memory can be programmed through the Spy-Bi-Wire or JTAG port, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory:
•
•
•
•
•

42

Flash memory has n segments of main memory and one segment of information memory.
Segment size is 1KB for both main memory and information memory.
Segments 0 to n in main memory can be erased in one step, or each segment may be individually erased.
Information memory segment can be erased separately or as a group with main memory segments 0 to n.
Information memory segment contains calibration data. After reset, information memory segment is protectedagainst programming and erasing. It can be unlocked but care should be taken not to erase this segment if
the device-specific calibration data is required.

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9.9 JTAG Operation
9.9.1 JTAG Standard Interface
The MSP430i family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430i
development tools and device programmers. 表 9-6 lists the JTAG pin requirements. For further details oninterfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide.
表 9-6. JTAG Pin Requirements and Functions
DEVICE SIGNAL

DIRECTIONFUNCTION

P1.0/UCA0STE/MCLK/TCKIN

JTAG clock input

P1.1/UCA0CLK/SMCLK/TMS

IN

JTAG state control

P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLKIN

JTAG data input/TCLK input

P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDIOUTJTAG data output

TEST/SBWTCKIN

Enable JTAG pins

RST/NMI/SBWTDIO

IN

External reset

VCC

Power supply

DVSS

Ground supply

9.9.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430i family supports the 2-wire Spy-Bi-Wire interface. SpyBi-Wire can be used to interface with MSP430i development tools and device programmers. 表 9-7 lists the SpyBi-Wire interface pin requirements. For further details on interfacing to development tools and device
programmers, see the MSP430 Hardware Tools User's Guide.
表 9-7. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL

DIRECTIONFUNCTION

TEST/SBWTCKIN

Spy-Bi-Wire clock input

RST/NMI/SBWTDIO

IN, OUT

Spy-Bi-Wire data input/output

VCC

Power supply

DVSS

Ground supply

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9.9.3 JTAG Disable Register
The SYSJTAGDIS register can disable the JTAG port to provide code protection and device security. JTAG is
disabled when software writes the value 0xA5A5 to this register within 64 MCLK clock cycles after a BOR or
POR reset; otherwise, the JTAG port is enabled. Any writes to this register after the first 64 MCLK clock cycles
are ignored. Reads from this register at any time return the JTAG enable or disable status. The value 0xA5A5
indicates that JTAG is disabled, and 0x9696 indicates that JTAG is enabled. The SYSJTAGDIS register ismapped to address 01FEh.
注
Application programming the device to any of the low power modes within first 64 MCLK clock cycles
after a BOR or POR reset will lock the device for any JTAG/SBW access.
表 9-8. SYSJTAGDIS Register
15

14

13

12

rw-[1]

rw-[0]

rw-[1]

rw-[0]

7

6

5

4

11

10

9

8

rw-[0]

rw-[1]

rw-[0]

rw-[1]

3

2

1

0

rw-[0]

rw-[1]

rw-[0]

rw-[1]JTAGKEYJTAGKEY
rw-[1]JTAGKEY44

rw-[0]

rw-[1]

rw-[0]

0xA5A5 indicates JTAG is disabled and 0x9696 indicates JTAG is enabled.

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9.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430i2xx Family User's Guide.
9.10.1 Clock System
The clock system consists of a fixed 16.384-MHz frequency internal DCO. The DCO can operate in internal
resistor mode or external resistor mode. The DCO clock accuracy is higher when operating in external resistor
mode especially upon variation in operating temperature. This feature can be useful in applications like utility
metering in which accurate clock is necessary under varying operating temperature. When external resistor
mode is selected by application, the resistor of recommended value must be connected to ROSC pin of thedevice. Refer to セクション 8.7.2.1 for the recommended value of the resistor at the ROSC pin. TI recommends
connecting the ROSC pin to AVSS when operating the DCO in internal resistor mode. When a resistor fault is
detected in the external resistor mode, the DCO automatically switches to the internal resistor mode as a failsafe mechanism to keep the system clocks active.
The DCO can be completely bypassed and the system clocks can be sourced by an external digital clock. The
clock system generates MCLK, SMCLK, and ACLK. MCLK is used by the CPU, while SMCLK and ACLK areused by the peripheral modules. There are programmable clock dividers for MCLK and SMCLK. ACLK runs at a
fixed 32-kHz frequency. The clock system supports active mode and four low-power modes.
9.10.2 Power-Management Module (PMM)
The PMM consists of voltage regulator that generates 1.8-V regulated core voltage. There is a brownout reset(BOR) circuit on the high-voltage domain, and a supply voltage supervisor (SVS) module on the low-voltage
domain. The BOR and SVS provide the proper internal reset signal to the device during power on and power off.
A built-in voltage reference is used by submodules of the PMM and by the analog modules on the device. A
temperature sensor is also available in the built-in voltage reference.
The voltage monitor (VMON) on the high-voltage domain can monitor external voltage on the VMONIN pin
against the internal reference voltage or by comparing the on-chip VCC to one of three programmable thresholdvoltages. During the LPM4.5 mode, the reference, voltage regulator, temperature sensor, and voltage monitor
are turned off, and only the high-side brownout circuit is active.

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9.10.3 Digital I/O
Two 8-bit I/O ports (P1 and P2) are implemented on the MSP430i204x, MSP430i203x, MSP430i202x devices.
On 32-pin RHB devices, ports P1 and P2 are complete, and 16 I/Os are available. On 28-pin PW devices, port
P2 is reduced to 4 bits, and 12 I/Os are available. On 28-pin PW devices, the unavailable pins (P2.4 to P2.7)
must be programmed to port function, output direction, and be driven with value 0.
•
•
•
•
•

All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt condition is possible.
Edge-selectable interrupt input capability for all 8 bits of port P1 and P2
LPM4.5 wake-up capability for Port pins P2.1 and P2.2
Read and write access to port-control registers is supported by all instructions.

9.10.4 Watchdog Timer (WDT)The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not neededin an application, the module can be disabled or configured as an interval timer and can generate interrupts atselected time intervals.
9.10.5 Timer TA0
Timer TA0 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA0 can support
multiple capture/compares, PWM outputs, and interval timing (see 表 9-9). TA0 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
表 9-9. TA0 Signal Connections
INPUT PORT PIN

DEVICE INPUTSIGNAL

MODULE INPUTSIGNAL

P1.3

TA0CLKTACLK

ACLK (internal)

ACLK

SMCLK (internal)

SMCLK

P1.3

TA0CLK

INCLK

P1.4

TA0.0

CCI0A

TA0.0

CCI0B

DVSS

GND

P2.5

P1.5

P1.6

46

VCC

VCC

TA0.1

CCI1A

ACLK (internal)

CCI1B

DVSS

GND

VCC

VCC

TA0.2

CCI2A

TA1 CCR2 output(internal)

CCI2B

DVSS

GND

VCC

VCC

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MODULE BLOCK

Timer

MODULEDEVICE OUTPUTOUTPUT SIGNAL
SIGNALNA

OUTPUT PORT
PIN

NA

P1.4
CCR0

TA0

TA0.0

P2.5

P1.5
CCR1

TA1

TA0.1

P2.6

P1.6
TA0.2
CCR2

TA2

P2.7

TA1 CCI2B input

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9.10.6 Timer TA1
Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support
multiple capture/compares, PWM outputs, and interval timing (see 表 9-10). TA1 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
表 9-10. TA1 Signal Connections
INPUT PORT PIN
P1.7

DEVICE INPUTSIGNAL

MODULE INPUTSIGNAL

TA1CLKTACLK

ACLK (internal)

ACLK

SMCLK (internal)

SMCLK

P1.7

TA1CLK

INCLK

P2.0

TA1.0

CCI0A

P2.4

TA1.0

CCI0B

DVSS

GND

VCC

VCC

P2.1

P2.2

TA1.1

CCI1A

ACLK (internal)

CCI1B

DVSS

GND

VCC

VCC

TA1.2

CCI2A

TA0 CCR2 output(internal)

CCI2B

DVSS

GND

VCC

VCC

MODULE BLOCK

Timer

MODULEDEVICE OUTPUTOUTPUT SIGNAL
SIGNALNA

OUTPUT PORT
PIN

NA

P2.0
CCR0

TA0

TA1.0

P2.4

P2.1
CCR1

TA1

TA1.1

P2.2
TA1.2
CCR2

TA2
TA0 CCI2B input

9.10.7 Enhanced Universal Serial Communication Interface (eUSCI)The eUSCI module is used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication protocols such
as UART, enhanced UART with automatic baudrate detection, and IrDA.
The eUSCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, and IrDA.
The eUSCI_Bn module provides support for SPI (3-pin or 4-pin) and I2C.
One eUSCI_A and one eUSCI_B module are implemented on MSP430i20xx devices.
9.10.8 Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16-bit,
16×8-bit, 8×16-bit, and 8×8-bit operations. The module supports signed and unsigned multiplication as well as
signed and unsigned multiply-and-accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.

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9.10.9 SD24
There are up to four independent 24-bit sigma-delta ADCs. Each converter is designed with a fully differential
analog input pair and programmable gain amplifier input stage. Also the converters are based on second-order
oversampling sigma-delta modulators and digital decimation filters. The decimation filters are comb-type filterswith selectable oversampling ratios of up to 256.
The SD24 converters can operate with internal reference (SD24REFS = 1) or with external reference(SD24REFS = 0). When SD24 operates with internal reference the VREF pin must not be loaded externally.
Connect only the recommended capacitor value (CVREF) at VREF pin to AVSS (see セクション 8.7.7.2).

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9.11 Input/Output Diagrams
9.11.1 Port P1, P1.0 to P1.3, Input/Output With Schmitt Trigger
図 9-8 shows the pin diagram. 表 9-11 summarizes the selection of the pin function.
JTAG enable
From JTAG
From JTAGPyDIR.x

00

From module 1

01
10

Direction
0: Input
1: Output

1

Pad Logic

0

11

PyOUT.x

00

From module 1

01

1

From module 2

10

0

DVSS

11

Py.x/Mod1/Mod2/JTAGPySEL1.x
PySEL0.x
PyIN.xEND

To modules
and JTAG

Functional representation only.

図 9-8. Py.x/Mod1/Mod2/JTAG Pin Diagram

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表 9-11. Port P1 (P1.0 to P1.3) Pin Functions
PIN NAME (P1.x)
P1.0/UCA0STE/MCLK/TCK

x0

FUNCTION

P1DIR.x

P1SEL1.x

P1SEL0.x

JTAG Enable

P1.0 (I/O)(2)

I: 0; O: 1

0

0

0

UCA0STE

X(3)

0

1

0

N/A

0

MCLK

1

1

0

0

N/A

0

DVSS

1

1

1

0

TCK(4)
P1.1/UCA0CLK/SMCLK/TMS

P1.2/UCA0RXD/UCA0SOMI/
ACLK/TDI/TCLK

P1.3/UCA0TXD/UCA0SIMO/
TA0CLK/TDO/TDI

1

2

3

CONTROL BITS OR SIGNALS(1)

X

X

X

1

P1.1 (I/O)(2)

I: 0; O: 1

0

0

0

UCA0CLK

X(3)

0

1

0

N/A

0

SMCLK

1

1

0

0

N/A

0

DVSS

1

1

1

0

TMS(4)

X

X

X

1

P1.2 (I/O)(2)

I: 0; O: 1

0

0

0

UCA0RXD/UCA0SOMI

X(3)

0

1

0

N/A

0

ACLK

1

1

0

0

N/A

0

DVSS

1

1

1

0

TDI/TCLK(4)

X

X

X

1

P1.3 (I/O)(2)

I: 0; O: 1

0

0

0

UCA0TXD/UCA0SIMO

X(3)

0

1

0

TA0CLK

0

DVSS

1

1

0

0

N/A

0

DVSS

1

1

1

0

TDO/TDI(4)

X

X

X

1

(1)
(2)
(3)
(4)

X = Don't care
Default condition
Direction is controlled by eUSCI_A0 module.
The pin direction is controlled by the JTAG module. The JTAG mode selection is made through the Spy-Bi-Wire 4-wire entry sequence.
Neither P1SEL0.x and P1SEL1.x nor P1DIR.x have an effect in these cases.

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9.11.2 Port P1, P1.4 to P1.7, Input/Output With Schmitt Trigger
図 9-9 shows the pin diagram. 表 9-12 summarizes the selection of the pin function.
Pad Logic
PyDIR.x

00

From module 1

01

Direction
0: Input
1: Output

10
11

PyOUT.x

00

From module 1

01

From module 2

10

DVSS

11

Py.x/Mod1/Mod2

PySEL1.x
PySEL0.x
PyIN.xEN
To module

D

Functional representation only.

図 9-9. Py.x/Mod1/Mod2 Pin Schematic

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表 9-12. Port P1 (P1.4 to P1.7) Pin Functions
PIN NAME (P1.x)
P1.4/UCB0STE/TA0.0

P1.5/UCB0CLK/TA0.1

P1.6/UCB0SCL/UCB0SOMI/
TA0.2

P1.7/UCB0SDA/UCB0SIMO/
TA1CLK

x
4

5

6

7

FUNCTIONCONTROL BITS OR SIGNALS(1)P1DIR.x

P1SEL1.x

P1SEL0.x

P1.4 (I/O)

I: 0; O: 100

UCB0STE

X(2)

0

1

TA0.CCI0A

0

TA0.0

1

1

0

N/A

0

DVSS

1

1

1

P1.5 (I/O)

I: 0; O: 100

UCB0CLK

X(2)

0

1

TA0.CCI1A

0

TA0.1

1

1

0

N/A

0

DVSS

1

1

1

P1.6 (I/O)

I: 0; O: 100

UCB0SCL/UCB0SOMI

X(2)

0

1

TA0.CCI2A

0

TA0.2

1

1

0

N/A

0

DVSS

1

1

1

P1.7 (I/O)

I: 0; O: 100

UCB0SDA/UCB0SIMO

X(2)

0

1

TA1CLK

0

DVSS

1

1

0

N/A

0

DVSS

1

1

1

(1)
(2)

X = Don't care
Direction is controlled by eUSCI_B0 module.

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9.11.3 Port P2, P2.0 to P2.2 and P2.4 to P2.7, Input/Output With Schmitt Trigger
図 9-10 shows the pin diagram. 表 9-13 summarizes the selection of the pin function.
Pad Logic
PyDIR.x

Direction
0: Input
1: Output

00
01
10
11

PyOUT.x

00

From module

01

DVSS

10

DVSS

11

Py.x/Mod1/Mod2

PySEL1.x
PySEL0.x
PyIN.xEND

To module

Functional representation only.

図 9-10. Py.x/Mod1/Mod2 Pin Schematic
表 9-13. Port P2 (P2.0 to P2.2 and P2.4 to P2.7) Pin Functions
PIN NAME (P2.x)
P2.0/TA1.0/CLKIN

P2.1/TA1.1

x0

1

FUNCTIONCONTROL BITS OR SIGNALSP2DIR.x

P2SEL1.x

P2SEL0.x

P2.0 (I/O)

I: 0; O: 10

0

TA1.CCI0A

0

TA1.0

1

0

1

CLKIN (DCO bypass clock)

0

DVSS

1

1

0

N/A

0

DVSS

1

1

1

0

0

0

1

1

0

1

1

P2.1 (I/O)

I: 0; O: 1

TA1.CCI1A

0

TA1.1

1

N/A

0

DVSS

1

N/A

0

DVSS

1

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表 9-13. Port P2 (P2.0 to P2.2 and P2.4 to P2.7) Pin Functions (continued)
PIN NAME (P2.x)
P2.2/TA1.2

P2.4/TA1.0(1)P2.5/TA0.0(1)P2.6/TA0.1(1)P2.7/TA0.2(1)

x
2

4

5

6

7

FUNCTIONCONTROL BITS OR SIGNALSP2DIR.x

P2SEL1.x

P2SEL0.x

P2.2 (I/O)

I: 0; O: 10

0

TA1.CCI2A

0

TA1.2

1

0

1

N/A

0

DVSS

1

1

0

N/A

0

DVSS

1

1

1

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

P2.4 (I/O)

I: 0; O: 1

TA1.CCI0B

0

TA1.0

1

N/A

0

DVSS

1

N/A

0

DVSS

1

P2.5 (I/O)

I: 0; O: 1

TA0.CCI0B

0

TA0.0

1

N/A

0

DVSS

1

N/A

0

DVSS

1

P2.6 (I/O)

I: 0; O: 1

N/A

0

TA0.1

1

N/A

0

DVSS

1

N/A

0

DVSS

1

P2.7 (I/O)

I: 0; O: 1

N/A

0

TA0.2

1

N/A

0

DVSS

1

N/A

0

DVSS

1

(1)

Available only on 32-pin RHB devices.

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9.11.4 Port P2, P2.3, Input/Output With Schmitt Trigger
図 9-11 shows the pin diagram. 表 9-14 summarizes the selection of the pin function.
Pad Logic
To VMON
From VMONPyDIR.x

Direction
0: Input
1: Output

00
01
10
11

PyOUT.x

00

DVSS

01

DVSS

10

DVSS

11

Py.x/VMONIN

PySEL1.x
PySEL0.x
PyIN.xBus
KeeperEN
D

No connect

Functional representation only.

図 9-11. Py.x/VMONIN Pin Schematic
表 9-14. Port P2 (P2.3) Pin Functions
PIN NAME (P2.x)
P2.3/VMONIN

(1)
(2)

x
3

FUNCTION
P2.3 (I/O)

CONTROL BITS OR SIGNALS(1)P2DIR.x

P2SEL1.x

P2SEL0.x

I: 0; O: 1

0

0

0

1

1

0

1

1

N/A

0

DVSS

1

N/A

0

DVSS

1

VMONIN(2)X

X = Don't care
Setting P2SEL1.3 and P2SEL0.3 disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying voltage at VMONIN pin. To enable the VMONIN function, VMONLVLx bits must be set to 3'b111 in the VMONCTL register.

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9.12 Device Descriptor
表 9-15 lists the contents of the tag-length-value (TLV) device descriptor structure for the MSP430i204x,
MSP430i203x, and MSP430i202x devices.
表 9-15. MSP430i204x, MSP430i203x, MSP430i202x TLVADDRESSSIZE(BYTES)VALUE

TLV checksum

013C0h2

Per unit

Die Record Tag

013C2h101h

Die Record Length

013C3h

10Ah

Lot/Wafer ID

013C4h4

Per unit

Die X position

013C8h2

Per unit

Die Y position

013CAh2

Per unit

Test results

013CCh2

Per unit

REF Calibration Tag

013CEh

1

02h

REF Calibration Length

013CFh102hCalibrate REF – for REFCAL1 register

013D0h1

Per unit

Calibrate REF – for REFCAL0 register

013D1h1

Per unit

DCO Calibration Tag

013D2h103h

DCO Calibration Length

013D3h104hCalibrate DCO – for CSIRFCAL register

013D4h1

Per unit

Calibrate DCO – for CSIRTCAL register

013D5h1

Per unit

Calibrate DCO – for CSERFCAL register

013D6h1

Per unit

Calibrate DCO – for CSERTCAL register

013D7h1

Per unit

SD24 Calibration Tag

013D8h104hSD24 Calibration Length

013D9h102hCalibrate SD24 – for SD24TRIM register

013DAh1

Per unit

Empty

013DBh1

FFh

Tag Empty

013DCh1

FEhEmpty Length013DDh

1

22h

Empty

013DEh34

FFh

DESCRIPTION
Checksum

Die Record

REF Calibration

DCO Calibration

SD24 Calibration

Empty

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9.13 Memory
表 9-16 lists the memory organization for the specified devices.
表 9-16. Memory Organization
MSP430i2040
MSP430i2030
MSP430i2020

MSP430i2041
MSP430i2031
MSP430i2021

Memory

Size

16KB

32KB

Main: interrupt vector

Flash

0xFFFF to 0xFFE0

0xFFFF to 0xFFE0

Main: code memory

Flash

0xFFFF to 0xC000

0xFFFF to 0x8000

Size

1KB

1KB

Flash

0x13FFh to 0x1000

0x13FFh to 0x1000

Size

1KB

2KB

Address

0x05FF to 0x0200

0x09FF to 0x0200

16-bit0x01FF to 0x0100

0x01FF to 0x0100

8-bit

0x00FF to 0x0010

0x00FF to 0x0010

8-bit SFR

0x000F to 0x0000

0x000F to 0x0000

Information memory
RAM

Peripherals

9.13.1 Peripheral File Map
表 9-17 lists the peripherals that support word access, and 表 9-18 lists the peripherals that support byte access.
Peripherals that support both access types are listed in both tables.
表 9-17. Peripherals With Word Access
MODULESYS

REGISTER DESCRIPTIONJTAG disable register

SYSJTAGDIS

0x01FE

TA1CCR2

0x0196

Capture/compare register 1

TA1CCR1

0x0194

Capture/compare register 0

TA1CCR00x0192

TA1R

0x0190Capture/compare control 2

TA1CCTL2

0x0186

Capture/compare control 1

TA1CCTL1

0x0184

Capture/compare control 0

TA1CCTL0

0x0182Timer_A control

TA1CTL

0x0180Timer_A interrupt vector

TA1IV

0x011E

Capture/compare register 2

TA0CCR2

0x0176

Capture/compare register 1

TA0CCR1

0x0174

Capture/compare register 0

TA0CCR00x0172TA0R

0x0170Capture/compare control 2

TA0CCTL2

0x0166

Capture/compare control 1

TA0CCTL1

0x0164

Capture/compare control 0

TA0CCTL0

0x0162Timer_A control

TA0CTL

0x0160Timer_A interrupt vector

TA0IV

0x012E

Timer_A register
Timer TA0

ADDRESS

Capture/compare register 2

Timer_A register
Timer TA1

ACRONYM

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表 9-17. Peripherals With Word Access (continued)
MODULEeUSCI_A0

REGISTER DESCRIPTIONACRONYM

ADDRESSUSCI_A control word 0

UCA0CTLW0

0x0140USCI _A control word 1

UCA0CTLW1

0x0142

USCI_A baud rate 0

UCA0BR00x0146

USCI_A baud rate 1

UCA0BR1

0x0147

USCI_A modulation control

UCA0MCTLW

0x0148USCI_A status

UCA0STAT

0x014AUSCI_A receive buffer

UCA0RXBUF

0x014CUSCI_A transmit buffer

UCA0TXBUF

0x014EUSCI_A LIN control

UCA0ABCTL

0x0150USCI_A IrDA transmit control

UCA0IRTCTL

0x0152

USCI_A IrDA receive control

UCA0IRRCTL

0x0153

USCI_A interrupt enable

UCA0IE

0x015AUSCI_A interrupt flags

UCA0IFG

0x015CUSCI_A interrupt vector word

eUSCI_B0

Hardware MultiplierFlash Memory
Watchdog Timer58

UCA0IV

0x015EUSCI_B control word 0

UCB0CTLW0

0x01C0USCI_B control word 1

UCB0CTLW1

0x01C2

USCI_B bit rate 0

UCB0BR0

0x01C6

USCI_B bit rate 1

UCB0BR1

0x01C7

USCI_B status word

UCB0STATW

0x01C8USCI_B byte counter threshold

UCB0TBCNT

0x01CAUSCI_B receive buffer

UCB0RXBUF

0x01CCUSCI_B transmit buffer

UCB0TXBUF

0x01CEUSCI_B I2C own address 0

UCB0I2COA0

0x01D4

USCI_B I2C own address 1

UCB0I2COA1

0x01D6

USCI_B I2C own address 2

UCB0I2COA2

0x01D8USCI_B I2C own address 3

UCB0I2COA3

0x01DAUSCI_B received address

UCB0ADDRX

0x01DCUSCI_B address mask

UCB0ADDMASK

0x01DEUSCI I2C slave address

UCB0I2CSA

0x01E0USCI interrupt enable

UCB0IE

0x01EAUSCI interrupt flags

UCB0IFG

0x01ECUSCI interrupt vector word

UCB0IV

0x01EESum extend

SUMEXT

0x013E

Result high word

RESHI

0x013C

Result low word

RESLO

0x013A

Second operandOP20x0138Multiply signed + accumulate/operand 1

MACS

0x0136

Multiply + accumulate/operand 1

MAC

0x0134Multiply signed/operand 1

MPYS

0x0132Multiply unsigned/operand 1

MPY

0x0130Flash control 3

FCTL3

0x012CFlash control 2

FCTL2

0x012A

Flash control 1

FCTL1

0x0128Watchdog/timer control

WDTCTL

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表 9-17. Peripherals With Word Access (continued)
MODULE

SD24(also see 表 9-18)

(1)
(2)

REGISTER DESCRIPTIONACRONYM

ADDRESS

SD24 interrupt vector word register

SD24IV

0x01F0Channel 3 conversion memory(1) (2)SD24MEM3

0x0116

Channel 2 conversion memory(2)SD24MEM2

0x0114Channel 1 conversion memory

SD24MEM1

0x0112Channel 0 conversion memory

SD24MEM00x0110Channel 3 control(1) (2)

SD24CCTL3

0x0108Channel 2 control(2)SD24CCTL2

0x0106

Channel 1 control

SD24CCTL1

0x0104Channel 0 control

SD24CCTL00x0102

General Control

SD24CTL

0x0100REGISTER NAME

ADDRESSNot available on MSP430i2031 and MSP430i2030 devices.
Not available on MSP430i2021 and MSP430i2020 devices.

表 9-18. Peripherals With Byte Access
MODULE

SD24(also see 表 9-17)

PMM

Clock System

REGISTER DESCRIPTION
SD24 trim

SD24TRIM

0x00BF

Channel 3 preload(1) (2)SD24PRE3

0x00BB

Channel 2 preload(2)SD24PRE2

0x00BA

Channel 1 preload

SD24PRE1

0x00B9Channel 0 preload

SD24PRE0

0x00B8Channel 3 input control(1) (2)

SD24INCTL3

0x00B3Channel 2 input control(2)SD24INCTL2

0x00B2Channel 1 input control

SD24INCTL1

0x00B1Channel 0 input control

SD24INCTL0

0x00B0

Reference calibration 1

REFCAL1

0x0063

Reference calibration 0

REFCAL00x0062

Voltage monitor control

VMONCTL

0x0061

LPM4.5 control

LPM45CTL

0x0060

Clock system external resistor temperature calibration

CSERTCAL

0x0055Clock system external resistor frequency calibration

CSERFCAL

0x0054Clock system internal resistor temperature calibration

CSIRTCAL

0x0053Clock system internal resistor frequency calibration

CSIRFCAL

0x0052Clock system control 1

CSCTL10x0051Clock system control 0

CSCTL00x0050Port P2 interrupt flag

P2IFG

0x002DPort P2 interrupt enable

P2IE

0x002B

Port P2 interrupt edge selectP2IES

0x0029Port P2 interrupt vector word
Port P2

P2IV

0x002EPort P2 selection 1

P2SEL10x001DPort P2 selection 0

P2SEL00x001B

Port P2 direction

P2DIR

0x0015

Port P2 output

P2OUT

0x0013

Port P2 input

P2IN

0x0011

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表 9-18. Peripherals With Byte Access (continued)
MODULEPort P1

Special Function(1)(2)

REGISTER DESCRIPTIONREGISTER NAME

ADDRESS

Port P1 interrupt flag

P1IFG

0x002CPort P1 interrupt enable

P1IE

0x002APort P1 interrupt edge select

P1IES

0x0028Port P1 interrupt vector word

P1IV

0x001EPort P1 selection 1

P1SEL10x001CPort P1 selection 0

P1SEL00x001APort P1 direction

P1DIR

0x0014

Port P1 output

P1OUT

0x0012

Port P1 input

P1IN

0x0010SFR interrupt flag 1

IFG10x0002

SFR interrupt enable 1

IE10x0000Not available on MSP430i2031 or MSP430i2030 devices.
Not available on MSP430i2021 or MSP430i2020 devices.

9.14 Identification
9.14.1 Device Identification
The device type can be identified from the top-side marking on the device package. See the packaging
information page or the device errata sheets listed in セクション 11.4 for help.
9.14.2 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in detail in
the MSP430 Programming With the JTAG Interface.

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10 Applications, Implementation, and Layout
注以下のアプリケーション情報は、TI の製品仕様に含まれるものではなく、TI ではその正確性または完全性を保証いたしません。個々の目的に対する製品の適合性については、お客様の責任で判断していただくことになります。また、お客様は自身の設計実装を検証しテストすることで、システムの機能を確認する必要があります。
The following resources provide application guidelines and best practices when designing with the MSP430i20xx
devices.
Implementation of a One- or Two-Phase Electronic Watt-Hour Meter Using MSP430i20xx application
reportThis application report describes the implementation of a low-cost 1- or 2-phase electronic electricity meter thatuses the TI MSP430i20xx metering processor. This application report includes information on metrology softwareand hardware procedures for this single-chip implementation.
Single-Phase and DC Embedded Metering Power Using MSP430i2040 application report
This application report describes an EVM that uses the MSP430i2040 microcontroller for embedded metering(submetering). In this application, the electricity measuring device is embedded in the end application and gives
the user information about the voltage, current, and power consumption of the device. In addition, the EVM cancompensate for line resistance and EMI filter capacitance.
Single Phase and DC Embedded Metering (Server Power Monitor) reference design
This reference design implements a high-accuracy single-phase embedded meter using an MSP430 MCU. This
EVM has built-in support to measure AC voltage, current, active power, reactive power, apparent power,
frequency, power factor, voltage THD, current THD, fundamental voltage, fundamental current, fundamental
power and DC voltage, DC current, DC active power. It can detect the input voltage to work in DC or AC mode. It
can also compensate for the effects of the wire resistance and the EMI filter capacitance so that the reading ofvoltage and power matches the reading of an external meter when EMI filter is connected to the input.
Three Output Smart Power Strip reference design
This reference design implements a high-accuracy single-phase embedded metering smart power strip using an
MSP430 MCU. This design supports measurement of AC voltage, current, active power, reactive power,
apparent power, frequency, and power factor with 3 sockets measured individually. Additional hardware is added
to provide futher development like relay control and wired or wireless communication.

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MSP430I2031, MSP430I2030
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11 Device and Documentation Support
11.1 Getting Started and Next Steps
For more information on the MSP430™ family of devices and the tools and libraries that are available to help withyour development, visit the MSP430™ ultra-low-power sensing & measurement MCUs overview.

11.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP
MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These
prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully
qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated
fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.
TI recommends that these devices not be used in any production system because their expected end-use failure
rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature
range, package type, and distribution format. 図 11-1 provides a legend for reading the complete device name.
MSP

430

i

2

041

T

PW

R
Tape and Reel

Processor Family

Packaging

MCU Platform
Device Type
SeriesProcessor Family

Temperature Range
Feature Set

MSP = Mixed-Signal Processor
XMS = Experimental Silicon

MCU Platform

430 = TI’s MSP430 Microcontroller Platform

Device TypeSpecialized Applicationi = Flash Industrial

Series2 = Flash 2 series up to 16.384 MHz

Feature Set

Various levels of integration within a series

Temperature Range

T = –40°C to 105°C

Packaging

http://www.ti.com/packaging

Tape and Reel

T = Small Reel
R = Large ReelNo markings = Tube or tray

図 11-1. Device Nomenclature

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11.3 Tools and Software
All MSP microcontrollers are supported by a wide variety of software and hardware development tools. Tools areavailable from TI and various third parties. See them all at MSP430 ultra-low-power MCUs – Design &development.
Design Kits and Evaluation Modules
32-pin target development board and MSP-FET programmer bundle for MSP430i2x MCUs
The MSP-FET430U32A is a stand-alone ZIF socket target board used to program and debug the MSP430 MCU
in-system through the JTAG interface or the Spy-Bi-Wire (2-wire JTAG) protocol.
MSP430 LaunchPad™ Value Line Development Kit
The MSP-EXP430G2 LaunchPad development kit is an easy-to-use microcontroller development board for the
low-power and low-cost MSP430G2x MCUs. It has on-board emulation for programming and debugging andfeatures a 14/20-pin DIP socket, on-board buttons and LEDs and BoosterPack plug-in module pinouts that
support a wide range of modules for added functionality such as wireless, displays, and more.
MSP430i2040 Submetering EVM
This embedded metering (sub-meter or e-meter) EVM is designed based on the MSP430i2040. The EVM can beconnected to the mains (or to DC) and the load directly. The EVM measures the electrical parameters of the load
and the result of measurement can be read from the UART port. This EVM provided with built-in power supply
and isolated serial connect to facilitate user quick start to the evaluation of the MSP430i2040 in embedded
metering application.
Software
MSP430Ware™ Software
MSP430Ware software is a collection of code examples, data sheets, and other design resources for all
MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 MCU design resources, MSP430Ware software also includes a high-level API called MSP Driver
Library. This library makes it easy to program MSP430 hardware. MSP430Ware software is available as acomponent of CCS or as a stand-alone package.
MSP430i20xx Code Examples
C code examples are available for every MSP device that configures each of the integrated peripherals forvarious application needs.
Floating Point Math Library for MSP430
Leveraging the intelligent peripherals of TI devices, this floating point math library of scalar functions brings you
up to 26x better performance. Mathlib is easy to integrate into your designs. This library is free and is integrated
in both Code Composer Studio and IAR IDEs.
Fixed Point Math Library for MSP
The TI MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical
functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and
MSP432 devices. These routines are typically used in computationally intensive real-time applications where
optimal execution speed, high accuracy and ultra-low energy are critical. By using the IQmath and Qmathlibraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably
lower than equivalent code written using floating-point math.

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English Data Sheet: SLAS887

MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
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Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code Composer Studio (CCS) integrated development environment (IDE) supports all MSP microcontroller
devices. CCS comprises a suite of embedded software utilities used to develop and debug embedded
applications. CCS includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features.
MSP Flasher - Command Line Programmer
MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET
programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary
files (.txt or .hex) directly to the MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger
The MSP-FET is a powerful emulation development tool – often called a debug probe – which lets users quickly
begin application development on MSP low-power MCUs. Creating MCU software usually requires downloading
the resulting binary program to the MSP device for validation and debugging.
MSP-GANG Production Programmer
The MSP Gang Programmer is an MSP430 or MSP432 device programmer that can program up to eight
identical MSP430 or MSP432 flash or FRAM devices at the same time. The MSP Gang Programmer connects toa host PC using a standard RS-232 or USB connection and provides flexible programming options that let theuser fully customize the process.

11.4 Documentation Support
The following documents describe the MSP430i20xx MCUs. Copies of these documents are available on theInternet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for yourdevice on ti.com (for example, MSP430i2041). In the upper right corner, click the "Alert me" button. This
registers you to receive a weekly digest of product information that has changed (if any). For change details,
check the revision history of any revised document.
Errata
MSP430i2041 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430i2040 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430i2031 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430i2031 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430i2021 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430i2021 Device Erratasheet
Describes the known exceptions to the functional specifications.

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MSP430I2021, MSP430I2020
JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

User's Guides
MSP430i2xx Family User's Guide
Detailed description of all modules and peripherals available in this device family.
MSP430™ Flash Device Bootloader (BSL) User's Guide
The MSP430 bootloader (BSL) lets users communicate with embedded memory in the MSP430 microcontroller
during the prototyping phase, final production, and in service. Both the programmable memory (flash memory)and the data memory (RAM) can be modified as required. Do not confuse the bootloader with the bootstrap
loader programs found in some digital signal processors (DSPs) that automatically load program code (and data)from external memory to the internal memory of the DSP.
MSP430 Programming With the JTAG Interface
This document describes the functions that are required to erase, program, and verify the memory module of the
MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition,
it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This
document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG
interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide
This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the
program development tool for the MSP430 ultra-low-power microcontroller. Both available interface types, theparallel port interface and the USB interface, are described.
Application Reports
MSP430 32-kHz Crystal Oscillators
Selection of the correct crystal, correct load circuit, and proper board layout are important for a stable crystal
oscillator. This application report summarizes crystal oscillator function and explains the parameters to select thecorrect crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout
are given. The document also contains detailed information on the possible oscillator tests to ensure stableoscillator operation in mass production.
MSP430 System-Level ESD Considerations
System-level ESD has become increasingly demanding with silicon technology scaling towards lower voltages
and the need for designing cost-effective and ultra-low-power components. This application report addresses
different ESD topics to help board designers and OEMs understand and design robust system-level designs.

11.5 サポート・リソース
TI E2E™ サポート ・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。
リンクされているコンテンツは、該当する貢献者により、現状のまま提供されるものです。これらは TI の仕様を構成するものではなく、必ずしも TI の見解を反映したものではありません。TI の使用条件を参照してください。

11.6 Trademarks
MSP430Ware™, MSP430™, Code Composer Studio™, TI E2E™, LaunchPad™, and are trademarks of Texas
Instruments.
すべての商標は、それぞれの所有者に帰属します。

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English Data Sheet: SLAS887

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MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020

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JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

11.7 静電気放電に関する注意事項
この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい ESD 対策をとらないと、デバイスを破損するおそれがあります。
ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。

11.8 用語集
TI 用語集

66

この用語集には、用語や略語の一覧および定義が記載されています。

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MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020
JAJSFD0C – SEPTEMBER 2014 – REVISED MARCH 2021

12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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English Data Sheet: SLAS887

PACKAGE OPTION ADDENDUM

www.ti.com

16-Mar-2021

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

(3)

(4/5)

(6)

MSP430I2020TPW

ACTIVE

TSSOP

PW

28

50

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2020TMSP430I2020TPWR

ACTIVE

TSSOP

PW

28

2000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2020TMSP430I2020TRHBR

ACTIVE

VQFN

RHB

32

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2020TMSP430I2020TRHBTACTIVE

VQFN

RHB

32

250

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2020TMSP430I2021TPW

ACTIVE

TSSOP

PW

28

50

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2021TMSP430I2021TPWR

ACTIVE

TSSOP

PW

28

2000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2021TMSP430I2021TRHBR

ACTIVE

VQFN

RHB

32

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2021TMSP430I2021TRHBTACTIVE

VQFN

RHB

32

250

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2021TMSP430I2030TPW

ACTIVE

TSSOP

PW

28

50

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2030TMSP430I2030TPWR

ACTIVE

TSSOP

PW

28

2000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2030TMSP430I2030TRHBR

ACTIVE

VQFN

RHB

32

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2030TMSP430I2030TRHBTACTIVE

VQFN

RHB

32

250

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2030TMSP430I2031TPW

ACTIVE

TSSOP

PW

28

50

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2031TMSP430I2031TPWR

ACTIVE

TSSOP

PW

28

2000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2031TMSP430I2031TRHBR

ACTIVE

VQFN

RHB

32

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2031TMSP430I2031TRHBTACTIVE

VQFN

RHB

32

250

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2031TMSP430I2040TPW

ACTIVE

TSSOP

PW

28

50

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2040TMSP430I2040TPWR

ACTIVE

TSSOP

PW

28

2000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2040TMSP430I2040TRHBR

ACTIVE

VQFN

RHB

32

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2040TMSP430I2040TRHBTACTIVE

VQFN

RHB

32

250

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2040T

Addendum-Page 1

SamplesPACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device

16-Mar-2021

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

(3)

(4/5)

(6)

MSP430I2041TPW

ACTIVE

TSSOP

PW

28

50

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2041TMSP430I2041TPWR

ACTIVE

TSSOP

PW

28

2000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2041TMSP430I2041TRHBR

ACTIVE

VQFN

RHB

32

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2041TMSP430I2041TRHBTACTIVE

VQFN

RHB

32

250

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

I2041T(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 2

SamplesPACKAGE OPTION ADDENDUM

www.ti.com

16-Mar-2021

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION
www.ti.com

23-Mar-2024

TAPE AND REEL INFORMATIONREEL DIMENSIONSTAPE DIMENSIONS
K0

P1

B0 W
Reel
DiameterCavity
A0
B0
K0
W
P1

A0

Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers

Reel Width (W1)QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes

Q1

Q2

Q1

Q2

Q3

Q4

Q3

Q4

User Direction of Feed

Pocket Quadrants*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

MSP430I2020TPWR

TSSOP

PW

28

2000

330.0

16.4

6.9

10.2

1.8

12.0

16.0

Q1

MSP430I2020TRHBR

VQFN

RHB

32

3000

330.0

MSP430I2020TRHBR

VQFN

RHB

32

3000

330.0

12.4

5.3

5.3

1.1

8.0

12.0

Q2

12.4

5.3

5.3

1.1

8.0

12.0

Q2

MSP430I2020TRHBT

VQFN

RHB

32

250

MSP430I2020TRHBT

VQFN

RHB

32

250

180.0

12.4

5.3

5.3

1.1

8.0

12.0

Q2

180.0

12.4

5.3

5.3

1.1

8.0

12.0

MSP430I2021TPWR

TSSOP

PW

28

Q2

2000

330.0

16.4

6.9

10.2

1.8

12.0

16.0

Q1

MSP430I2021TRHBR

VQFN

RHB

MSP430I2021TRHBR

VQFN

RHB

32

3000

330.0

12.4

5.3

5.3

1.1

8.0

12.0

Q2

32

3000

330.0

12.4

5.3

5.3

1.1

8.0

12.0

MSP430I2021TRHBT

VQFN

Q2

RHB

32

250

180.0

12.4

5.3

5.3

1.1

8.0

12.0

Q2

MSP430I2021TRHBTMSP430I2030TPWR

VQFN

RHB

32

250

180.0

12.4

5.3

5.3

1.1

8.0

12.0

Q2

TSSOP

PW

28

2000

330.0

16.4

6.9

10.2

1.8

12.0

16.0

Q1

MSP430I2030TRHBR
MSP430I2030TRHBR

VQFN

RHB

32

3000

330.0

12.4

5.3

5.3

1.1

8.0

12.0

Q2

VQFN

RHB

32

3000

330.0

12.4

5.3

5.3

1.1

8.0

12.0

MSP430I2030TRHBT

Q2

VQFN

RHB

32

250

180.0

12.4

5.3

5.3

1.1

8.0

12.0

Q2

MSP430I2030TRHBT

VQFN

RHB

32

250

180.0

12.4

5.3

5.3

1.1

8.0

12.0

Q2

MSP430I2031TPWR

TSSOP

PW

28

2000

330.0

16.4

6.9

10.2

1.8

12.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

23-Mar-2024

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

MSP430I2031TRHBR

VQFN

RHB

32

3000

330.0

12.4

MSP430I2031TRHBR

VQFN

RHB

32

3000

330.0

12.4

5.3

5.3

1.1

8.0

12.0

Q2

5.3

5.3

1.1

8.0

12.0

MSP430I2031TRHBT

VQFN

RHB

32

250

180.0

Q2

12.4

5.3

5.3

1.1

8.0

12.0

Q2

MSP430I2031TRHBT

VQFN

RHB

32

250

MSP430I2040TPWR

TSSOP

PW

28

2000

180.0

12.4

5.3

5.3

1.1

8.0

12.0

Q2

330.0

16.4

6.9

10.2

1.8

12.0

16.0

Q1

MSP430I2040TRHBR

VQFN

RHB

32

MSP430I2040TRHBR

VQFN

RHB

32

3000

330.0

12.4

5.3

5.3

1.1

8.0

12.0

Q2

3000

330.0

12.4

5.3

5.3

1.1

8.0

12.0

MSP430I2040TRHBT

VQFN

RHB

32

Q2

250

180.0

12.4

5.3

5.3

1.1

8.0

12.0

Q2

MSP430I2040TRHBT

VQFN

RHB

MSP430I2041TPWR

TSSOP

PW

32

250

180.0

12.4

5.3

5.3

1.1

8.0

12.0

Q2

28

2000

330.0

16.4

6.9

10.2

1.8

12.0

16.0

MSP430I2041TRHBR

VQFN

Q1

RHB

32

3000

330.0

12.4

5.3

5.3

1.1

8.0

12.0

Q2

MSP430I2041TRHBTMSP430I2041TRHBT

VQFN

RHB

32

250

180.0

12.4

5.3

5.3

1.1

8.0

12.0

Q2

VQFN

RHB

32

250

180.0

12.4

5.3

5.3

1.1

8.0

12.0

Q2

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

23-Mar-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)

W

L

H

*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)

MSP430I2020TPWR

TSSOP

PW

28

2000

350.0

350.0

43.0

MSP430I2020TRHBR

VQFN

RHB

32

3000

346.0

346.0

33.0

MSP430I2020TRHBR

VQFN

RHB

32

3000

367.0

367.0

35.0

MSP430I2020TRHBT

VQFN

RHB

32

250

210.0

185.0

35.0

MSP430I2020TRHBT

VQFN

RHB

32

250

210.0

185.0

35.0

MSP430I2021TPWR

TSSOP

PW

28

2000

367.0

367.0

38.0

MSP430I2021TRHBR

VQFN

RHB

32

3000

367.0

367.0

35.0

MSP430I2021TRHBR

VQFN

RHB

32

3000

346.0

346.0

33.0

MSP430I2021TRHBT

VQFN

RHB

32

250

210.0

185.0

35.0

MSP430I2021TRHBT

VQFN

RHB

32

250

210.0

185.0

35.0

MSP430I2030TPWR

TSSOP

PW

28

2000

350.0

350.0

43.0

MSP430I2030TRHBR

VQFN

RHB

32

3000

346.0

346.0

33.0

MSP430I2030TRHBR

VQFN

RHB

32

3000

367.0

367.0

35.0

MSP430I2030TRHBT

VQFN

RHB

32

250

210.0

185.0

35.0

MSP430I2030TRHBT

VQFN

RHB

32

250

210.0

185.0

35.0

MSP430I2031TPWR

TSSOP

PW

28

2000

350.0

350.0

43.0

MSP430I2031TRHBR

VQFN

RHB

32

3000

367.0

367.0

35.0

MSP430I2031TRHBR

VQFN

RHB

32

3000

346.0

346.0

33.0

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION
www.ti.com

23-Mar-2024

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)

MSP430I2031TRHBT

VQFN

RHB

32

250

210.0

185.0

35.0

MSP430I2031TRHBT

VQFN

RHB

32

250

210.0

185.0

35.0

MSP430I2040TPWR

TSSOP

PW

28

2000

350.0

350.0

43.0

MSP430I2040TRHBR

VQFN

RHB

32

3000

367.0

367.0

35.0

MSP430I2040TRHBR

VQFN

RHB

32

3000

367.0

367.0

35.0

MSP430I2040TRHBT

VQFN

RHB

32

250

210.0

185.0

35.0

MSP430I2040TRHBT

VQFN

RHB

32

250

210.0

185.0

35.0

MSP430I2041TPWR

TSSOP

PW

28

2000

350.0

350.0

43.0

MSP430I2041TRHBR

VQFN

RHB

32

3000

346.0

346.0

33.0

MSP430I2041TRHBT

VQFN

RHB

32

250

210.0

185.0

35.0

MSP430I2041TRHBT

VQFN

RHB

32

250

210.0

185.0

35.0

Pack Materials-Page 4

PACKAGE MATERIALS INFORMATION
www.ti.com

23-Mar-2024

TUBE
T - TubeheightL - Tube length

W - Tubewidth

B - Alignment groove width*All dimensions are nominal

DevicePackage Name

Package Type

Pins

SPQ

L (mm)W (mm)

T (µm)B (mm)MSP430I2020TPW

PW

TSSOP

28

50

530

10.2

3600

3.5

MSP430I2021TPW

PW

TSSOP

28

50

530

10.2

3600

3.5

MSP430I2030TPW

PW

TSSOP

28

50

530

10.2

3600

3.5

MSP430I2031TPW

PW

TSSOP

28

50

530

10.2

3600

3.5

MSP430I2040TPW

PW

TSSOP

28

50

530

10.2

3600

3.5

MSP430I2041TPW

PW

TSSOP

28

50

530

10.2

3600

3.5

Pack Materials-Page 5

GENERIC PACKAGE VIEW

RHB 32VQFN - 1 mm max height5 x 5, 0.5 mm pitch

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A

www.ti.com

PACKAGE OUTLINE
VQFN - 1 mm max height

RHB0032M

PLASTIC QUAD FLATPACK-NO LEAD

A

5.1
4.9

B

5.1
4.9

PIN 1 INDEX AREA

C

1 MAX

SEATING PLANE
0.08 C0.05
0.00

2X 3.5(0.2) TYP

9

16

28X 0.5
8

17

SYMM

33

2X
3.5

1
PIN 1 ID
(OPTIONAL)

24
32

25

SYMM
32X 0.5
0.3

32X 0.3
0.2
0.1
0.05

C A B
C

4223725/A 08/2017

NOTES:
1.
2.
3.

All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height

RHB0032M

PLASTIC QUAD FLATPACK-NO LEAD

(4.8)
(

2.1)

32

32X (0.6)

25

32X (0.25)
124

28X (0.5)

33

SYMM

(4.8)
2X
(0.8)

VIA TYP
8

17(R0.05) TYP
916
2X (0.8)
SYMM

LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 15X
0.07 MAXALL AROUND

0.07 MIN
ALL AROUNDMETALEXPOSEDMETALSOLDER MASKOPENINGSOLDER MASKOPENINGEXPOSEDMETALNON SOLDER MASKDEFINED(PREFERRED)METAL UNDERSOLDER MASKSOLDER MASKDEFINEDSOLDER MASK DETAILS
4223725/A 08/2017

NOTES: (continued)
4.
5.

This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shownon this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGNVQFN - 1 mm max height

RHB0032M

PLASTIC QUAD FLATPACK-NO LEAD

(4.8)
4X (

0.94)

32

32X (0.6)

25

32X (0.25)
124

28X (0.5)

33
SYMM
(4.8)
2X
(0.57)

METAL
TYP
8

17

(R0.05) TYP
916
2X (0.57)
SYMM

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCILEXPOSED PAD
80% PRINTED COVERAGE BY AREASCALE: 15X

4223725/A 08/2017

NOTES: (continued)
6.

Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com

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