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Table of Contents

Errata

MSP430F1610 Microcontroller

ABSTRACTThis document describes the known exceptions to the functional specifications (advisories).

Table of Contents
1 Functional Advisories............................................................................................................................................................ 2
2 Preprogrammed Software Advisories.................................................................................................................................. 2
3 Debug Only Advisories.......................................................................................................................................................... 2
4 Fixed by Compiler Advisories............................................................................................................................................... 2
5 Nomenclature, Package Symbolization, and Revision Identification................................................................................ 4
5.1 Device Nomenclature.........................................................................................................................................................4
5.2 Package Markings..............................................................................................................................................................4
5.3 Memory-Mapped Hardware Revision (TLV Structure)....................................................................................................... 5
6 Advisory Descriptions............................................................................................................................................................6
7 Revision History................................................................................................................................................................... 16

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Functional Advisories

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1 Functional Advisories
Advisories that affect the device's operation, function, or parametrics.

Rev B

Rev A

✓ The check mark indicates that the issue is present in the specified revision.

ADC18

✓

✓

ADC25

✓

✓

BCL5

✓

✓

CPU41

✓

✓

Errata Number

✓

DAC4
I2C7

✓

✓

I2C8

✓

✓

I2C9

✓

✓

I2C10

✓

✓

I2C11

✓

✓

I2C12

✓

✓

I2C13

✓

✓

I2C14

✓

✓

I2C15

✓

✓

I2C16

✓

✓

MPY2

✓

✓

TA12

✓

✓

TA16

✓

✓

TA21

✓

✓

TAB22

✓

✓

TB2

✓

✓

TB16

✓

✓

TB24

✓

✓
✓

US14
US15

✓

✓

WDG2

✓

✓

2 Preprogrammed Software Advisories
Advisories that affect factory-programmed software.
✓ The check mark indicates that the issue is present in the specified revision.
The device does not have any errata for this category.

3 Debug Only Advisories
Advisories that affect only debug operation.
✓ The check mark indicates that the issue is present in the specified revision.
The device does not have any errata for this category.

4 Fixed by Compiler Advisories
Advisories that are resolved by compiler workaround. Refer to each advisory for the IDE and compiler versions
with a workaround.
✓ The check mark indicates that the issue is present in the specified revision.

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CPU4

Rev A

Errata Number

Fixed by Compiler Advisories
Rev B

www.ti.com✓✓

Refer to the following MSP430 compiler documentation for more details about the CPU bugs workarounds.
TI MSP430 Compiler Tools (Code Composer Studio IDE)••

MSP430 Optimizing C/C++ Compiler: Check the --silicon_errata option
MSP430 Assembly Language Tools

MSP430 GNU Compiler (MSP430-GCC)••

MSP430 GCC Options: Check -msilicon-errata= and -msilicon-errata-warn= options
MSP430 GCC User's Guide

IAR Embedded Workbench•

IAR workarounds for msp430 hardware issues

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Nomenclature, Package Symbolization, and Revision Identification

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5 Nomenclature, Package Symbolization, and Revision Identification
The revision of the device can be identified by the revision letter on the Package Markings or by the HW_ID
located inside the TLV structure of the device.

5.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP
MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These
prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully
qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
MSP – Fully qualified production device
Support tool naming prefixes:
X: Development-support product that has not yet completed Texas Instruments internal qualification testing.
null: Fully-qualified development-support product.
XMS devices and X development-support tools are shipped against the following disclaimer:"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated
fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.
TI recommends that these devices not be used in any production system because their expected end-use failure
rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature
range, package type, and distribution format.

5.2 Package Markings
RTD64

QFN (RTD), 64 Pin

PM64

LQFP (PM), 64 Pin

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Nomenclature, Package Symbolization, and Revision Identification

5.3 Memory-Mapped Hardware Revision (TLV Structure)
This device does not support reading the hardware revision from memory.
Further guidance on how to locate the TLV structure and read out the HW_ID can be found in the device User's
Guide.

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Advisory Descriptions

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6 Advisory Descriptions
ADC18

ADC Module

Category

Functional

Function

Incorrect conversion result in extended sample mode

Description

The ADC12 conversion result can be incorrect if the extended sample mode is selected(SHP = 0), the conversion clock is not the internal ADC12 oscillator (ADC12SSEL > 0),and one of the following two conditions is true:- The extended sample input signal SHI is asynchronous to the clock source used for
ADC12CLK and the undivided ADC12 input clock frequency exceeds 3.15 MHz.
or
- The extended sample input signal SHI is synchronous to the clock source used for
ADC12CLK and the undivided ADC12 input clock frequency exceeds 6.3 MHz.

Workaround- Use the pulse sample mode (SHP = 1).
or- Use the ADC12 internal oscillator as the ADC12 clock source.
or- Limit the undivided ADC12 input clock frequency to 3.15 MHz.
or
- Use the same clock source (such as ACLK or SMCLK) to derive both SHI and
ADC12CLK, to achieve synchronous operation, and also limit the undivided ADC12 input
clock frequency to 6.3 MHz.

ADC25

ADC Module

Category

Functional

Function

Write to ADC12CTL0 triggers ADC12 when CONSEQ = 00

Description

If ADC conversions are triggered by the Timer_B module and the ADC12 is in singlechannel single-conversion mode (CONSEQ = 00), ADC sampling is enabled by write
access to any bit(s) in the ADC12CTL0 register. This is contrary to the expected behavior
that only the ADC12 enable conversion bit (ADC12ENC) triggers a new ADC12 sample.

Workaround

When operating the ADC12 in CONSEQ=00 and a Timer_B output is selected as the
sample and hold source, temporarily clear the ADC12ENC bit before writing to otherbits in the ADC12CTL0 register. The following capture trigger can then be re-enabled by
setting ADC12ENC = 1.

BCL5

BCL Module

Category

Functional

Function

RSELx bit modifications can generate high frequency spikes on MCLK

Description

When DIVMx = 00 or 01 the RSELx bits of the Basic Clock Module are incremented or
decremented in steps of 2 or greater, the DCO output may momentarily generate highfrequency spikes on MCLK, which may corrupt CPU operation. This is not an issue when
DIVMx = 10 or 11.

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Advisory Descriptions

Workaround

Set DIVMx = 10 or 11 to divide the MCLK input prior to modifying RSELx. After the RSELx
bits are configured as desired, the DIVMx setting can be changed back to the original
selection.

CPU4

CPU Module

Category

Compiler-Fixed

Function

PUSH #4, PUSH #8

Description

The single operand instruction PUSH cannot use the internal constants (CG) 4 and 8. The
other internal constants (0, 1, 2, -1) can be used. The number of clock cycles is different:
PUSH #CG uses address mode 00, requiring 3 cycles, 1 word instruction
PUSH #4/#8 uses address mode 11, requiring 5 cycles, 2 word instruction

Workaround

Refer to the table below for compiler-specific fix implementation information.
IDE/Compiler

Version Number

Notes

IAR Embedded Workbench

IAR EW430 v2.x until v6.20

User is required to add thecompiler flag option below. -hw_workaround=CPU4

IAR Embedded Workbench

IAR EW430 v6.20 or later

Workaround is automaticallyenabledTI MSP430 Compiler Tools (CodeComposer Studio)

v1.1 or later

MSP430 GNU Compiler (MSP430GCC)

MSP430-GCC 4.9 build 167 or later

CPU41

CPU Module

Category

Functional

Function

Incorrect address fetching during interrupt priority decoding

Description

The CPU might fetch a random address if the system clock is greater than 6 MHz and
two general maskable interrupts (GMI) with large priority difference are triggered within atime frame of 8 system clock cycles. In fail case, a race condition of the internal interrupt
priority chain is corrupting the address bus.
The issue can potentially occur if the priority delta between the two occurring interrupts isgreater than 8.

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Advisory Descriptions

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NOTE: This erratum supersedes the DMA9 erratum.
Workaround

1. Reduce the system frequency below 6MHz.
OR
2. Disable affected interrupts and poll the IFGs.

DAC4

DAC Module

Category

Functional

Function

DAC1 overwrites an input of the SVS comparator

Description

DAC1, when enabled (DAC12_1CTL.DAC12AMPx >0), overrides the input of the SVS
comparator if SVSCTL.VLDx = 1111 (comparing external input voltage SVSIN to 1.25
V.) This is caused by a conflict between SVS and DAC1 at Port 6.7. This behavior only
affects DAC output pins shared with SVSIN function.

Workaround

1) Do not enable DAC1 when SVS is used with VLDx = 1111
OR2) Use DAC output pin not shared with SVSIN function

I2C7

I2C Module

Category

Functional

Function

ARDYIFG Interrupt flag generation can fail in I2C slave mode.

Description

When the USART is configured for I2C mode (U0CTL.I2C, SYNC, and I2CEN are set)
and the module is configured as an I2C slave (U0CTL.MST=0), the ARDYIFG interrupt
flag generation can fail, even when both the I2C stop condition is received and the receive
buffer is empty.
This condition occurs when the I2C clock source selected by I2CSSELx is disabled by the
Status Register (SR) control signals OSCOFF or SCG1.
In this configuration, the hardware clock activation is enabled by the I2C module.
However, if RXRDYIFG is polled to determine data reception, the I2C hardware clock
activation may be disabled before the ARDYIFG is generated.

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Advisory Descriptions

Workaround(1)Use interrupt service routines using the I2C interrupt vector generator feature (I2CIV) tohandle all I2C interrupts.
OR(2)After detection of I2C Own Address (OAIFG), the selected I2C clock source is enabled
by clearing the OSCOFF or SCG1 Status Register (SR) bits. When the ARDYIFG isdetected, the OSCOFF or SCG1 in the Status Register (SR) can be set to disable theclock source and return to the desired low power mode operation.
OR(3)For slave only devices, it is normally not necessary to use ARDYIFG.

I2C8

I2C Module

Category

Functional

Function

Master Transmitter transmits 0FFh continuously.

Description

When the USART is configured for I2C mode (U0CTL.I2C, SYNC, and I2CEN areset) and the module is configured as an I2C master (U0CTL.MST=1) and I2CNDAT isused to control the number of bytes to transmit, the possibility exists that the masterstate-machine can become corrupted and start sending 0FFh as data on the I2C bus.
Specifically, this error can occur when a long delay occurs between the set of theI2CTXRDY interrupt flag and the loading of I2CDRB (I2CDRW).

Workaround

After detection of the I2CTXRDY interrupt flag, verify that the I2CTXUDF bit in I2CDCTL is
set before loading I2CDRB (I2CDRW).

I2C9

I2C Module

Category

Functional

Function

Master Transmitter Repeat Mode I2CSTP setting error.

Description

When the USART is configured for I2C mode (U0CTL.I2C, SYNC, and I2CEN are set)
and the module is configured as an I2C master (U0CTL.MST=1) and repeat mode
operation is selected (I2CTCTL.I2CRM=1), the timing of the I2CSTP bit can result in lost
data or extra requested transmitted bytes.
Specifically, if interrupts are active during the following two cases:
1) During the time between the setting of the I2CSTP bit and loading of I2CDRB(I2CDRW).
2) For transmitting slave address only, during the time between checking for I2CSTT
cleared and setting I2CSTP.
Note: In the second case, the SCL line will be held low until the I2CDRB (I2CDRW) is
loaded and then shifted out.

Workaround

Solution for case #1: disable all interrupts (DINT) before setting I2CSTP then re-enabling
after loading of I2CDRB.
Solution for case #2: disable all interrupts (DINT) before setting I2CSTT bit then reenabling after setting I2CSTP bit.

I2C10

I2C Module

Category

Functional

Function

Master stop bit SCL low phase does not match I2CSCLL setting.

Description

When the USART is configured for I2C mode (U0CTL.I2C, SYNC, and I2CEN are set)
and the module is configured as an I2C master (U0CTL.MST=1), the hardware control

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Advisory Descriptions

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of the SCL low phase before stop generation is equal to a single I2CCLK period. This isparticularly noticeable with large I2CSCLL settings or large I2CPSC settings.
Workaround

None.

I2C11

I2C Module

Category

Functional

Function

Master state machine requires reset before new sequence can proceed.

Description

When the USART is configured for I2C mode (U0CTL.I2C, SYNC, and I2CEN areset) and the module is configured as an I2C master (U0CTL.MST=1), the master statemachine does not properly reset between execution cycles.

Workaround

Before starting the new master sequence, clear and then re-set the I2CEN bit in the
U0CTL register.
bic.b #I2CEN,&U0CTL
bis.b #I2CEN,&U0CTL

I2C12

I2C Module

Category

Functional

Function

Master/Slave looses data on reception (lost RXRDYIFG).

Description

If the I2C data register I2CDRB (I2CDRW) is read at the same time that data is loaded
from the internal I2C shift register into I2CDRB (I2CDRW), then the received data islost and no corresponding receive ready interrupt (RXRDYIFG) is generated. Following
RXRDYIFG interrupts are processed but the missing byte cannot be recovered.

WorkaroundDo not read the I2CDRB(I2CDRW) register while data is being loaded into it. This canbe ensured by reading this register in a timely manner using any one of the following
methods:
1) Handle RXRDYIFG events with all other interrupt sources disabled.
2) Use the DMA for receiving incoming I2C data. The DMA interrupt or ARDYIFG interrupt
can be used to initiate further processing of received data.
3) Enable nested interrupts to allow immediate processing of RXRDYIFG interrupts. (Caremust be taken to avoid stack overflows).

I2C13

I2C Module

Category

Functional

Function

Glitch on SCL between I2C communication cycles can corrupt the state machine in I2C
master mode.

Description

When the USART is configured for I2C communication (U0CTL.I2C, SYNC, and I2CEN
are set) and the module is configured as an I2C master (U0CTL.MST=1), the I2C moduleis automatically switched to slave mode following the I2C master's generation of a stop
condition. If SCL is then pulled low and released again, the following device behavior canbe observed:
1) When SCL is pulled low after the stop condition is generated and while ARDYIFG is
not yet set, then ARDYIFG is not set as expected and ALIFG is set. SCL is released. See
workaround 1 for details on how to handle this condition.
2) When SCL is pulled low at the same time as ARDYIFG is being set, ALIFG is set
and SCL is released. Subsequent communication can result in an immediate ALIFG

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Advisory Descriptions

generation. See workaround 2 for details on how to handle this condition.
3) When SCL is pulled low after ARDYIFG is set but before ARDYIFG is cleared, ALIFG
is not set, but SCL is held low by the master. An SCL hang-up condition occurs. See
workaround 3 for details on how to handle this condition.
4) When SCL is pulled low after ARDYIFG is cleared, the module operates as intended.
The ALIFG flag is not set and SCL is released.
Workaround

1. ALIFG must be processed. Data bytes are not affected.
2. ALIFG must be processed. Data bytes are not affected. To avoid a second ALIFG, clear
I2CEN and re-set I2CEN before new communication begins.
3. Clear I2CEN and re-set I2CEN before new communication begins to clear the SCL
hang-up.

I2C14

I2C Module

Category

Functional

Function

Master SCL phases do not match I2CSCLx settings.

Description

When the USART is configured for I2C mode (U0CTL.I2C, SYNC, and I2CEN are set)
and the module is used as an I2C master (U0CTL.MST=1), the generated I2C shift clock(SCL) high and low phases may be one or more I2CIN clock periods longer than definedby I2CSCLH and I2CSCLL. High I2CIN frequencies, large external pull-up resistors, and alarge capacitive bus loading on SCL increase the likelihood for this to occur.

WorkaroundIf possible, use an I2CIN input frequency of 1MHz or less. Additionally, use lowimpedance I2C pull-up resistors, preferably in the lower single-digit k-Ohm range, andminimize capacitive load on SCL.

I2C15

I2C Module

Category

Functional

Function

I2CBUSY flag may clear before stop condition

Description

The I2CBUSY flag may already be cleared before the Stop condition on the bus is seen.

WorkaroundUse the I2CBB flag instead of the I2CBUSY flag.

I2C16

I2C Module

Category

Functional

Function

I2C Slave may not detect own address correctly

Description

When an interrupt occurs between ACK and stop conditions of a slave transmission, theslave may not acknowledge the slave address byte if all below conditions are fulfilled:- STT interrupt is enabled- Device is in LPMx during start condition.
If the failure occurs, the I2C state machine switches into IDLE state.

Workaround(1)Do not use the STT interrupt for slave transmission.
Or(2)Disable all interrupts between ACK and stop condition on I2C

MPY2

MPY Module

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Advisory Descriptions

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Category

Functional

Function

Multiplier Result register corruption

Description

Depending on the address of the write instruction, writing to the multiplier result registers(RESHI, RESLO, or SUMEXT) may corrupt the result registers. The address dependency
varies between a 2-word and a 3-word instructions.

Workaround

Ensure that a write instruction to an MPY result register (for example, mov.w #200,&RESHI) is not located at an address with the four least significant bits shown in Table 1:
Table 1. Sensitive Addresses for Write Access to MPY Result Registers MAB[3:0]TA12

TA Module

Category

Functional

FunctionInterrupt is lost (slow ACLK)

Description

Timer_A counter is running with slow clock (external TACLK or ACLK)compared to MCLK.
The compare mode is selected for the capture/compare channel and the CCRx register
is incremented by one with the occurring compare interrupt (if TAR = CCRx). Due to thefast MCLK the CCRx register increment (CCRx = CCRx+1) happens before the Timer_A
counter has incremented again. Therefore the next compare interrupt should happen atonce with the next Timer_A counter increment (if TAR = CCRx + 1). This interrupt gets
lost.

WorkaroundSwitch capture/compare mode to capture mode before the CCRx register increment.
Switch back to compare mode afterwards.

TA16

TA Module

Category

Functional

FunctionFirst increment of TAR erroneous when IDx > 00

Description

The first increment of TAR after any timer clear event (POR/TACLR) happens immediately
following the first positive edge of the selected clock source (INCLK, SMCLK, ACLK orTACLK). This is independent of the clock input divider settings (ID0, ID1). All following
TAR increments are performed correctly with the selected IDx settings.

Workaround

None

TA21

TA Module

Category

Functional

Function

TAIFG Flag is erroneously set after Timer A restarts in Up Mode

Description

In Up Mode, the TAIFG flag should only be set when the timer counts from TACCR0 to
zero. However, if the Timer A is stopped at TAR = TACCR0, then cleared (TAR=0) by

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Advisory Descriptions

setting the TACLR bit, and finally restarted in Up Mode, the next rising edge of the TACLK
will erroneously set the TAIFG flag.

Workaround

None.

TAB22

TAB Module

Category

Functional

Function

Timer_A/Timer_B register modification after Watchdog Timer PUC

Description

Unwanted modification of the Timer_A/Timer_B registers TACTL/TBCTL and TAIV/TBIV
can occur when a PUC is generated by the Watchdog Timer(WDT) in Watchdog
mode and any Timer_A/Timer_B counter register TACCRx/TBCCRx is incremented/
decremented (Timer_A/Timer_B does not need to be running).

Workaround

Initialize TACTL/TBCTL register after the reset occurs using a MOV instruction (BIS/BIC
may not fully initialize the register). TAIV/TBIV is automatically cleared following thisinitialization.
Example code:
MOV.W #VAL, &TACTL
orMOV.W #VAL, &TBCTL
Where, VAL=0, if Timer is not used in application otherwise, user defined per desired
function.

TB2

TB Module

Category

Functional

FunctionInterrupt is lost (slow ACLK)

Description

Timer_B counter is running with slow clock (external TBCLK or ACLK) compared to
MCLK. The compare mode is selected for the capture/compare channel and the CCRx
register is incremented by 1 with the occurring compare interrupt (if TBR = CCRx).
Due to the fast MCLK, the CCRx register increment (CCRx = CCRx + 1) happens before
the Timer_B counter has incremented again. Therefore, the next compare interrupt should
happen at once with the next Timer_B counter increment (if TBR = CCRx + 1). This
interrupt is lost.

WorkaroundSwitch capture/compare mode to capture mode before the CCRx register increment.
Switch back to compare mode afterward.

TB16

TB Module

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Advisory Descriptions

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Category

Functional

FunctionFirst increment of TBR erroneous when IDx > 00

Description

The first increment of TBR after any timer clear event (POR/TBCLR) happens
immediately following the first positive edge of the selected clock source (INCLK, SMCLK,ACLK, or TBCLK). This is independent of the clock input divider settings (ID0, ID1). Allfollowing TBR increments are performed correctly with the selected IDx settings.

Workaround

None

TB24

TB Module

Category

Functional

Function

TBIFG Flag is erroneously set after Timer B restarts in Up Mode

Description

In Up Mode, the TBIFG flag should only be set when the timer resets from TBCCR0 to
zero. However, if the Timer B is stopped at TBR = TBCCR0, then cleared (TBR=0) bysetting the TBCLR bit, and finally restarted in Up Mode, the next rising edge of the TBCLK
will erroneously set the TBIFG flag.

Workaround

None.

US14

USART Module

Category

Functional

FunctionStart edge of received characters may be ignored

Description

When using the USART in UART mode with UxBR0 = 0x03 and UxBR1 = 0x00, the startedge of received characters may be ignored due to internal timing conflicts within the
UART state machine. This condition does not apply when UxBR0 is > 0x03.

Workaround

None

US15

USART Module

Category

Functional

Function

UART receive with two stop bits

Description

USART hardware does not detect a missing second stop bit when SPB = 1.
The Framing Error Flag (FE) will not be set under this condition and erroneous data
reception may occur.

Workaround

None (Configure USART for a single stop bit, SPB = 0)

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Advisory Descriptions

WDG2

WDG Module

Category

Functional

Function

Incorrectly accessing a flash control register

Description

If a key violation is caused by incorrectly accessing a flash control register, the watchdog
interrupt flag is set in addition to the expected PUC.

Workaround

None

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Revision History

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7 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from May 12, 2021 to May 17, 2021
Page
• Changed the document format and structure; updated the numbering format for tables, figures, and crossreferences throughout the document..................................................................................................................6

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