APPLICATION NOTE
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Standard Gate-Driver Optocouplers
AN-3009/D
HOW DOES A STANDARD GATE−DRIVER
OPTOCOUPLER WORK?
The FOD31xx family of gate drivers functions as a power
buffer to control the gate of a power MOSFET or IGBT. It
is designed to supply the peak charging current required by
the MOSFET or IGBT’s gate input to turn the device ON. It
does this by providing a positive voltage (VOH) to the power
semiconductor’s gate. Turning the MOSFET or IGBT OFF
is accomplished by pulling the gate of the driven device tozero voltage (VOL) or lower.
Many power control applications use a “totem pole” high−and low−side connection of two or more series−connected
power semiconductors. The high−side N−channel MOSFET
drain is connected to a positive (+) terminal of a supply andits source is connected to the drain of the low−side transistor.
The source of the low−side transistor is connected to thenegative (−) side of the system supply. One side of the driven
load is connected at the common node of the high−side andlow−side transistors. Proper control of the high−side andlow−side transistors requires that neither transistor is ON or
conducting at the same time. The current through theseseries high−side and low−side devices is called “shoot−through” current. Shoot−through current wastes power andcan cause damage to the high− and low−side transistors.
The most common technique to eliminate shoot−throughcurrent is to add a delay or hold−off time between switchingon the high−side or low−side switch. The delay is introducedby controlling the timing of the signal supplied to the high−side and low−side gate drivers.
Figure 1 shows the gate drive internal block diagram.
Each section of the driver is supplied by a common poweror bias source. At initial power turn−on, there are circuit
delays due to the circuit’s complexity. This complexity can
introduce (during initial power−up) a situation where thegate’s output follows the rising edge of the applied VDD
supply until the supplies have stabilized. Once the bias
levels are correct, the gate drive output returns to its correctstate, controlled by the LED.
This application note discusses the key design criteria,
including LED driving, initial conditions, maximum
switching frequency, and power.

© Semiconductor Components Industries, LLC, 2012

August, 2022 − Rev. 2

Figure 1. FOD31xx Block Diagram

INITIAL CONDITIONS: DEVICE STARTUP
Operational Conditions
There are three power supplies in a typical inverter
application. The first is a logic supply (+3.3 V or +5 V or
+10 V). The second is an isolated low and high side driver
supply (+20 V FOD3182, +25 V FOD3120). The third is ahigh−voltage supply to power the MOSFETs / IGBTs. To
minimize any impact of the bias supply stabilization time, one
solution is to control the sequence of power supply activation:• First: logic supply − initial condition, LED current =0 mA, LED OFF.
• Second: isolated low− and high−side driver supply,
VO = VG = 0 V, power MOSFETs OFF.
• Third: high−voltage supply to power MOSFETS.
The turn−on sequence delay should accommodate
power−on reset for logic control and bootstrap charge time
for the driver isolated supply.
LED Drive
The peak forward current, IF(peak), is <1 A (1 ms, 300 pps).
The recommended operational current is 10 mA to 16 mA.
The rate of current rise is less than 250 ns. The fast rate ofLED−current rise minimizes propagation delay and output
switching jitter.
Power Supply Considerations
The FOD31xx products are high−gain (23 db),high−power−output, optical amplifiers. They require a
power supply with a low output impedance over the rangeof DC to 40 MHz. Using low−ESR bypass capacitors and asignal ground plane helps minimize self−induced
power−supply noise and degraded output rise and fall times.

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Publication Order Number:
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Propagation Delay on the FOD3182
Figure 2 shows that the propagation delay is independentof the load capacitance and that the typical pulse−width
distortion, PWD, is less than 40 ns.

Figure 5. Propagation Delay vs. Supply Voltage

Using a temperature−stable LED and temperature−compensated amplifiers and current sources, thepropagation delay changes by, typically, +0.2 ns/°C from
−40°C to 100°C, as shown in Figure 6.

Figure 2. Propagation Delay vs. Series Load
Capacitance

Figure 3 shows a propagation delay dependence on LED
current. The typical PWD is +4 ns/mA.

Figure 6. Propagation Delay vs. TA

The use of a P−channel MOSFET as the pull−up offers two
advantages over a bipolar transistor. First, the low RDS(ON)minimizes the internal voltage drop, providing a larger turn−on voltage for a given VCC – VEE. Second, the switching
delay is smaller than with a multi−stage PNP transistor.
Figure 7 shows the voltage drop curve for the FOD3120.

Figure 3. Propagation Delay vs. LED Forward Current

Figure 4 and Figure 5 illustrate independence of delay as
a function of series load and supply voltage.

Figure 4. Propagation Delay vs. Series Load Resistance

Figure 7. Output High Voltage Drop vs. TA

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AN−3009/D
GATE DRIVE CMTI (OR NOISE REJECTION)PERFORMANCE
Optically isolated MOSFET and IGBT drivers offer both
safety insulation and noise isolation between the load’s highvoltage and the applications control logic. The FOD31xx
family’s coplanar construction offers high dielectric
insulation and low input to output capacitance, which
optimizes safety and minimizes noise coupling. This
package construction results in safety compliance for both
US and European standards, with working voltage in excessof 800 V.
The interference caused by the electrical noise generated
by load switching is blocked through a coplanar optical
coupling technique and a special electro−optical shieldfurther reduces the capacitive coupling of the switchingtransients to the active circuits found in the gate driver.
A typical 240 VAC power converter generates 800 V
switching transients with slew rates greater than 6 kV/ms.
A transient of this magnitude results in a 3 mA peak current
flowing between input and output (when applied to an
isolation device with a CIO of only 0.5 pF) see Figure 8.

amplifier. The result is that the FOD31xx family rejects +/−common mode transient with peak amplitudes of 1.5 kV andslew rates in excess of 15 kV/ms.
The following summarizes the effects that Common
Mode Transients (CMT) have on the FOD31xx family:• Control current through LED, IF = 10 mA♦ Output of the driver is HIGH and sourcing current to
the load♦ Positive (+) dv/dt pulls current from the amplifier,aiding the photocurrent♦ Negative (−) dv/dt sources current into the amplifiercounter, acting on the photocurrent and potentiallycausing it to transition from HIGH to LOW• Control current through LED, IF = 0 mA
♦ Output of the driver is LOW and sinking current
from the load
♦ Positive (+) dv/dt pulls current from the amplifier,potentially causing it to transition from LOW to
HIGH♦ Negative (−) dv/dt sources current into the amplifier,helping keep the output in LOW state
Input Common Mode Transient Immunity

Figure 9 and Figure 10 show a half or “H” bridge using
two power MOSFETs in a totem−pole configuration.
Figure 9 shows the low−side switching, while Figure 10
illustrates high−side switching. Prior to the toggle action,
one side is ON and the other OFF. Just before the switching
toggle action occurs, both switches are deactivated, creatingan OFF dwell or “dead” time.

Figure 8. CMTI LED OFF

Figure 8 shows the capacitor that couples the noise current
between the input and output of the coupler. In this example,
the common−mode transient has a negative rate of voltage
swing, as referenced to the coupler’s output ground(GND2). This transient draws current from the coupler’s
output to the input. The package capacitance, CIO, provides
the dominant coupling impedance between the input tooutput. The LED is OFF, thus the output of the gate is in the
LOW state. The optical amplifier can be turned ON if
sufficient common−mode current, iCM, is drawn out of the
input of the amplifier. This noise current, iCM, is quite small
given the shield that blocks the effect of the electric fieldchange. This shield results in an effective common−modecoupling capacitance of less than 50 fF. This common−modeshield minimizes coupling into or out of the opticalFigure 9. Low−Side ON, High−Side OFF, Negative CMTFigure 9 shows the CMT being generated as the low−side
IGBT is turning ON. This load−switching action creates anegative dv/dt, as seen by both switches of the H−bridge. Itis essential that no load shoot−through current occurs during
this switching action. Note that input LEDs are connected inwww.onsemi.com3

AN−3009/D
Minimize Switching CMT with an LED Shunt Drive

the traditional “series” switching connection. A shoot−through fault can result if the high−side gate drive is
momentarily turned ON while the low−side switch is ON.
Figure 10 shows the CMT drawing current through thehigh−side’s LED. The magnitude of the LED current isdependent on: CMT’s dv/dt, assembly input−output
parasitic capacitance, and the impedances surrounding theLED. These impedances include the LED current−setting
resistor, R2, and the CCE of T1 driving the LED.
An inverter used to generate a 240 VAC power source may
create an LED current of 3 mApk with a pulse width ofapproximately 100 ns. This pulse is sufficient to activate thehigh−side driver and cause a shoot−through fault. The
susceptibility to this fault can be minimized by reducing theoff−state impedances surrounding the LED. These lower
impedances provide an alternative path for the CMT current
caused by the −dv/dt switching action.
The −dv/dt switching action, shown in Figure 9, creates a
CMT also seen by the low−side IGBT driver. This transient
attempts to draw current through the low−side LED. Thistransient has minimal effect. The LED is already ON, so
forcing more LED current only ensures the correct low−sideswitching action and the incremental CMT current isshunted to GND1 via transistor T2.

CMTI is essential when FOD31xx devices are used in
totem−pole half−bridge circuit applications. It is critical thatswitching transients developed during normal circuit
operation do not cause the OFF gate drive to turn ON. This
self−induced turn−ON due to half−bridge totem−poleoperation creates the need for an LED shunt drive to improve
operational noise immunity.
In the previous example, the LEDs were connected in the
traditional “series” drive configuration. The CMT can sinkor source current through the package, CIO, causing the OFF
LED to conduct. The normally off LED offers relatively
high impedance in OFF state. This potential problem can beeliminated by reducing the LED OFF state impedance. Thisis accomplished by providing a low impedance shunt patharound the LED when it is OFF. Figure 11 illustrates a shunt
LED drive circuit.
SHUNT LED DRIVE
To improve noise immunity, a shunt LED drive can beused. The advantages of a shunt LED drive are: 1) it
improves CMTI in a half−bridge drive, and 2) the load dv/dt
coupling via the package capacitance is coupled into a low−
impedance (either the conducting LED or the on resistanceof a conducting BJT or logic gate). The disadvantage is that
it is the least efficient (e.g., power is consumed when the
LED is ON or OFF).

Figure 11. FOD3182 with Shunt LED Drive

When the LED is connected in parallel with the driving
switch, this creates a current shunt drive. Figure 11 uses anopen−drain logic gate, U1, as the driver:• The LED current flows when the switch is OFF and
U1=HIGH.
• The LED offers low impedance to common mode
conducted currents.
• To turn the LED OFF, the gate is forced into LOW state.
This reduces the voltage across the LED to a value
significantly less than the required forward voltage. It
also offers a low impedance, reducing the influence that
common mode conducted currents have on the LED
operation.

Figure 10. Positive dv/dt − High−Side Switch
Turning ON

A positive dv/dt is created when the high−side switch
turns ON. Figure 10 shows the effect that this +dv/dt has on
the OFF low−side switch. The positive CMT can draw
current through the OFF LED in the low−side driver. If the
dv/dt is large enough, this CMT can momentarily force thelow−side IGBT driver to turn ON. This positive CMT is also
seen by the high−side switch. This dv/dt typically helps keep
the high−side driver ON.

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AN−3009/D
External or self−generated common−mode andnormal−mode noise can cause operational malfunction.
Minimizing the coupling capacitance between the control
logic and power semiconductor greatly reduces acommon−mode noise transient transition into anormal−mode noise pulse. Using low and balanced
impedances at the driving point improves the noise
immunity. Controlling power MOSFETs using galvanic
isolated drivers minimizes common−mode noise coupling.
The internal shield found in the FOD31xx family of
MOSFET drivers maximizes driver CMTI. Using a shunt
LED driver maximizes the input network’s CMTI, reducing
the risk of a common−mode noise pulse transitioning into anormal−mode LED drive signal.

The maximum allowable power dissipation in the output
transistor, POUT, is the difference between the maximum IC
power, PIC, and the static IC power, PSTATIC.
P OUT + P IC * P STATICP OUT + 210 mW * 1140 mW
P OUT + 96 mW(eq. 3)

At an ambient temperature of 100°C, the output transistor
can dissipate a steady−state power of 96 mW. The output
power is dissipated in the drain−to−source series resistance,RDS(ON), of the output P−channel and N−channeltransistors.
The output power equation is given below:
P OUT + I O

2R RDS(ON)(eq. 4)

HOW TO CALCULATE MAXIMUM SWITCHINGFREQUENCY FOR THE FOD3120 POWER
MOSFET / IGBT GATE−DRIVER OPTOCOUPLER
To calculate the maximum switching frequency for the
FOD3120, use the variables in Table 1.
Table 1. PERFORMANCE RATINGS
Maximum Junction Temperature

125°C

Thermal Resistance (Emitter), RthE

182 K/W

Thermal Resistance (Detector), RthD

141 K/W

Thermal Resistance (Between Emitter and
Detector), RthED

560 K/W

Output IC Power Dissipation at TA = 25°C

250 mW

Output IC Power Dissipation at TA = 100°C

210 mWICCL = ICCH

3.8 mARDS(ON)

3.5 W

VCC − VEE

30 V

Figure 12. FOD3120 – MOSFET Interface

FQA9N90C_F109
CGS2730 pF
25 W

ESR CGS

Analysis

The first step in calculating the maximum switchingfrequency is to determine the maximum power that can be
dissipated in the output driver MOSFET of the FOD3120 at
a maximum operation junction temperature of 125°C and an
ambient temperature of 100°C. The previous section
indicates the maximum power at TA = 100°C is 210 mW
based on the steady−state thermal resistance of the FOD3120.
The maximum power in the output IC is the sum of thesteady−state IC power and the power dissipated in the output
power−MOSFET transistors. The precise relationship isshown in Equation (1):P IC + P STATIC ) P OUT

Figure 13. Equivalent Circuit FOD3120 – MOSFETInterface

Figure 12 shows the interconnection between the
FOD3120 and an N−channel power MOSFET. Figure 13
provides the equivalent circuit to be used to calculate the
FOD3120’s output power. The P−channel transistor ismodeled as a switch with a series resistance of 3.5 W.
The input of the FQA9N90C_F109 is modeled as a series
RC circuit. The circuit elements are a gate−to−source
capacitance of 2730 pF in series with a 25 W equivalentcapacitor resistance (ESR).
The next section discusses the RMS power dissipated in
the output transistors given the charging and discharging
current of the MOSFET’s gate and the voltage drop acrossthe RDS(ON) of the FOD3120’s transistors.

(eq. 1)The static power is:
P STATIC + I CC

V CC

P STATIC + 3.8 mA
P STATIC + 114 mW

30 V(eq. 2)www.onsemi.com
5AN−3009/D

ǒVr @ exp ǒ* ttǓǓ @ Rdson
2

Po +(eq. 6)

The junction rise in the output is a product of the thermal
resistance and the output driver’s RMS power. The equation
for calculating the RMS power is given in Equation (7). The
variable, p, is the time period during which the power pulse
is averaged. Figure 14 illustrates that a drive current pulse ispresent at each LED transition. The frequency of operation
is defined as 1 / (2 x p). This definition is carried through thebalance of the analysis:
Figure 14. FOD3120 Output Current and Voltage
Po(RMS) +Figure 14 shows the output current waveform when the
FOD3120 is driving the gate of the power MOSFET.
Looking again at Figure 13, the initial charging transition isshown as a switch connected to the series of RGS, RDS(ON)and the input capacitance cGS. When the switch is thrown,
the current rises up to the peak value of VCC/rGS. The
charging current drops at an exponential rate determined by
the cGS and the resistors rGS and RDS(ON).
Assumptions:t = 2 x 10−9, 5 x 10−9…3 x 10−6
V = 30 V
c = 2730 x 10−12
r = 28.5
Tau = r x c
Tau = 7.781 x 10−8
a = 10 x 10−6i(t) +

ǒ

Ǔ

t
V
@ e*
t
r

Ǹ ŕǒ
p

ǒ ǓǓ @ Rdson dttV@ exp *
t
r

1
@
p

2

(eq. 7)0Equation (8) is the elementary calculus solution to thedefinite integral given in Equation (7), RDS = RDS(ON):
Po(RMS) +V 2 @ Rds
2 @ r2@Ǹ ǒǒǓǓ (eq. 8)*4@pt@ 1 * exptpWith the aid of Mathcad®, a graphical solution to theequation can be generated.
Assumptions:t = 3 x 10−6, 3.5 x 10−6…20 x 10−6
V = 30 V
c = 2730 x 10−12
r1 = 25
RDS = 3.5
R = r1 + RDS
Tau = r x c(eq. 5)

0.35
0.3
0.25
0.2

Po(p)

0.15
0.1
0.05

0

20

40

60

80 100 120 140 160 180 200f(p)Figure 16. Output Power Dissipation (W) vs.
Operations Frequency (kHz)

Figure 15. FOD3120 Output Current

Figure 16 indicates that the maximum permissible
frequency of operation when driving the FQA9N90C_F109
with an output power dissipation of 96 mW is less than
20 kHz. The major limiting factor is the worst−casespecification − RDS(ON) of the output drivers.
If the part’s maximum RDS(ON) is specified at a value
closer to its typical value of 1.0 W when operating at an IOof 1 A, the results shown in Figure 17 are possible.

The peak power dissipation in the FOD3120’s MOSFETs
is determined by the peak current and the exponential decay
time, t, where:
V = supply voltage;r = sum of ESR for Rs of the driven MOSFET and RDS(ON)of the FOD3120; andt = the time constant of the r and CISS of the driven
MOSFET.

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AN−3009/D
Figure 17 illustrates that if the RDS(ON) is equal to 1.0 W;
driving the FQA9N90C_F109 MOSFET at 100°C and
VCC = 30 V, a switching frequency of 150 kHz is possible.

Assumptions:
VCC = 30 V
Cgs = 2730 pF
Rds = 1.0 W
r = r1 + RDS(ON)r1 = RGS(cGS−ESR) = 25 W

CONCLUSION
This application note highlights some of the ways inwhich the reliability and performance of isolated gate drive
circuits can be optimized. The common equations used to
calculate the gate charge transfer power apply to the power
supplied to the driven MOSFET (FQA9N90C_F109).
However, this analysis does not describe the power
dissipation within the driver IC. Equation (8) calculates thepower dissipated in the FOD3120’s output power MOSFETs
as a function of RDS(ON), VCC, the driven MOSFET’s gate
capacitance, and the gate’s ESR.

0.11
0.1
0.09
Po(p)
0.08
0.07
0.06
60

75

90

105

120
f(p)

135

150

165

180

Figure 17. Output Power Dissipation (W) vs.
Operation Frequency (kHz)RELATED DATASHEETSFOD3120 − High Noise Immunity, 2.5 A Output Current, Gate Drive Optocoupler
FOD3182 − 3 A Output Current, High Speed MOSFET Gate Driver Optocoupler
FOD3184 − 3 A Output Current, High Speed MOSFET/IGBT Gate Driver Optocoupler
FOD8320 − High Noise Immunity, 2.5 A Output Current, Gate Drive Optocoupler in Optoplanar® Wide Body SOP 5−Pin

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