Multi-level storage in phase-change memory:from multi-layer to single layer
You Yin, and Sumio Hosaka
Graduate School of Engineering, Gunma University
1-5-1 Tenjin, Kiryu, Gunma 376-8515, JapanABSTRACT
In this paper, we report multi-level storage (MLS) in multi-layer (ML) and single-layer (SL) phase-change memories(PCM). For the former ML-PCM device, the active medium with two layers of chalcogenide consists of a top 30-nm
TiN/180-nm SbTeN/20-nm TiN/bottom 120-nm SbTeN stacked multi-layer. Three stable and distinct resistance states
are demonstrated in both static and dynamic switching characteristics of the multi-layer devices. For the latter SL-PCM
device, the active medium with only one layer of chalcogenide consists of a top 50-nm TiN/150-nm SbTeN. We
demonstrate that the number of distinguishable resistance levels can readily reach 16 and even higher. These levels inthis study result from the initial threshold switching and the subsequent current-controlled crystallization induced by
Joule heating. Therefore, the latter memory allows the creation of many distinct levels, thus enabling the low-cost
ultra-high-density non-volatile memory.
Keywords Multi-layer, Single-layer, Multi-level storage, Phase-change memory

INTRODUCTION
There is a rapidly increasing demand for ultra-high-density non-volatile memory (NVM) due to today’s explosive
proliferation of information. This type of memory can stably store information even if no power is supplied. An
extremely attractive characteristic of the future’s NVM is multi-level storage (MLS), which is data storage on more thantwo levels per memory cell; it makes possible a dramatic increase in memory capacity, i.e., much more information canbe saved without increasing the cell size. This leads to a decrease in the cost per bit.
Although MLS is very promising for post-flash phase-change memory (PCM) because of the huge available resistancechange, few reports on it have been found so far due to the difficulty in practically controlling resistance in PCM. 1-4) In
the past few years, researchers have demonstrated three- and four-level storage based on the layer-by-layer
crystallization of chalcogenide films in vertical PCM.1-2) However, there is a lack of literatures on MLS in lateral PCMs
although lateral PCMs were demonstrated to have many advantages. Here, we report MLS in both a multi-layer PCM
and a single-layer lateral PCM with a top heater.

EXPERIMENTAL METHODS
The current-voltage (I-V) characteristics of the device samples were measured by a semiconductor parameter analyzer(4155B, Agilent Technologies, Ltd.). A waveform generator (Model 2571, Tabor Electronics, Ltd.) was used to apply
single pulses to the devices to investigate the programming characteristics.

RESULTS AND DISCUSSIONSThe phase-change layer of SbTeN is adopted in these devices. SbTeN shows a gradual resistivity drop and good phasestability with increasing annealing temperature, a characteristic which makes it suitable for MLS applications.5)
We propose MLS based on multiple phase-change (PC) layers of different thicknesses as shown in Fig. 1. For two PC
layers, three levels are expected to be obtained due to the two switchings at two threshold voltages. A top 30-nm
TiN/180-nm SbTeN /20-nm TiN/bottom 120-nm SbTeN stacked structure is experimentally adopted as the active
medium in the multi-layer devices, as shown in Fig. 2. Three stable and distinct device resistance levels aredemonstrated in both static and dynamic switching characteristics of the multi-layer devices, as shown in Figs. 3 and 4.
Analysis reveals that two separate crystallization processes causing the two resistance drops could sequentially occur atthe steps from the bottom thin 120-nm SbTeN layer to the top thick 180-nm STN layer due to the electric field
confinement at the steps as shown in Fig. 5. From the principle and analysis of this ML-PCM, the available number ofresistance levels is strictly limited to be n+1 by the number of PC layers n.
To overcome the above limit, we propose SL-PCM to obtain much more resistance levels as shown in Fig. 6. The active
layers of a SL-PCM device consist of 150-nm-thick SbTeN layer with an additional top 50-nm-thick TiN layer.
Experimental results, as shown in Fig. 7, exhibit a number of levels up to 16 are distinct and stable, which are induced
by electric currents. From Fig. 6(a), the resistance level is dependent on the stop current (programming current), andfive levels (from “0” to “4”) are created. By reducing the programming current interval to 0.1 mA, up 16 resistancelevels can be readily created. In this case, the MLS results mainly from the gradual enlargement of crystalline region
between electrodes by Joule heating according to our analysis. These levels also exhibit good thermal stability as shownin Fig. 8.

CONCULTIONS
A lateral STN-based PCM with a stacked PC multi-layer was proposed for multi-state storage. Both static and dynamic
switching of the prototypical device exhibited three stable resistance states (HR, IR and LR). Analysis based on electricfield showed that two resistance switchings with increasing applied voltage successively took place at the lower andupper PC layers, respectively. In SL-PCM, we demonstrated ultra-multiple-level storage based on low-power
crystallization using a SbTeN single-layer PCM cell structure. The crystallization induced by Joule heating is
non-volatile, low-power and current-driven, and allows ultra-multiple-level storage. This phenomenon is expected to beemployed in practical applications to dramatically increase the memory capacity without increasing the cell size.

REFERENCES
1.

J. Feng, Y. F. Lai, B. W. Qiao, B. C. Cai, Y. Y. Lin, T. A. Tang, and B. Chen, Jpn. J. Appl. Phys. 46, 5724 (2007).

2.

Y. Yin, H. Sone, and S. Hosaka, Microelectron. Eng. 84, 2901 (2007).

3.

Y. Yin, N. Higano, H. Sone, and S. Hosaka, Appl. Phys. Lett. 92, 163509 (2008).

4.

Y. Yin, T. Noguchi, H. Ohno, and S. Hosaka, Appl. Phys. Lett. 95, 133503 (2009).

5.

Y. Yin, H. Sone, and S. Hosaka, J. Appl. Phys., 102, 064503 (2007).

(a)

(b)

PCM

Ith2th1

PC2

PC1IRL

“2”
“1”

UV“0”

Vt0-1 Vt1-2

Vt0-1= Et* th1

Vt1-2= Et* th2

Device resistance R ()5V

10

Gap parameters:
W=3 m, L=0.7 m
Stacked active multi-layers from top:
Top 30-nm TiN/180-nm STN/20-nm TiN/120-nm STN

"0"

"0"

Pulse width: 50 ns
Starting from a HR state
4"1"

10Pulse width: 20 ns
Starting from a LR stateFig. 1 (a) A proposed multi-level (e.g., three-state) PCM

0device with two PC layers (PC1 and PC2) of different

1234"2"5678910Pulse amplitude V (V)thicknesses (th1 and th2). (b) Schematic diagram of I-VFig. 4 Pulse-mode dynamic switching characteristics.

curves of the proposed device with three stable levels.

The HR (“0”), IR (“1”) and LR (“2”) levels are distinct

Two threshold voltages Vt0-1 and Vt1-2 are proportional toand stable in a large pulse amplitude window.

two thicknesses of th1 and th2, respectively.
(b)

(a)

Confinement due toAl
ZnS-SiO230-nm TiNstep coverage
180-nm STN
20-nm TiN
120-nm STNAl(a)2nd-STN: A
1st-STN: ASiN

I

REC +RSTN-A1 +RTiN1+ RSTN-A1+RECL
Si sub.

2rd-TiN
2nd-STN
1st-TiN
1st-STN“0”

SiO2 TiN EC(b)Fig. 2 (a) Schematic diagram of the fabricatedphase-change memory device with a stacked multi-layer“1”

2nd-STN: A
1st-STN: Locally C

of top 30-nm TiN/180-nm STN/20-nm TiN/120-nmREC

STN. Gap length and width are L and W. (b) Equivalent+REC+RSTN-C1+RTiN1+RSTN-C1structure of the fabricated device.
(c)1030 nm TiN/180 nm STN/
20 nm TiN/120 nm STN
4106REC + RSTN-C1 +R’ + RSTN-C1 +REC

R ()I (mA)

8“2”2nd-STN: Locally C
1st-STN: Locally C

4RSTN-C2 RTiN1 +RTiN2+2RSTN-C23

100R’=RTiN1//( RSTN-C2 +RTiN2+0246V (V)Fig. 3 Current sweeping and R-V characteristics inthe multi-layer device. 3 distinct resistance levels
were created for 2-layer device.

RSTN-C2)

Fig. 5 Analysis of resistance switchings from (a) “0” to(b) “1” and then to (c) “2” on the basis of crystallization
processes, which occurs at the steps due to electric field
confinement effect.

(b)Insulator
TiN heater
SbTeN

r1
rｈ

rｎ-2

r2(b)

2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.0

Wg=400 nm, Lg=1000 nm
17. 0-1.7 mA
9. 0-0.9 mA
16. 0-1.6 mA
8. 0-0.8 mA
15. 0-1.5 mA
7. 0-0.7 mA
14. 0-1.4 mA
6. 0-0.6 mA
13. 0-1.3 mA
5. 0-0.5 mA
12. 0-1.2 mA
4. 0-0.4 mA
11. 0-1.1 mA
3. 0-0.3 mA
10. 0-1.0 mA
2. 0-0.2 mA
17.

0.5

rh
r2

1.5
2.0
2.5
3.0
Device voltage V (V)

3.5

4.0

50

r1

rｎ-2
rｎ-1
Principle for MLS
r1→r1cfield)
r2 →r2c

1. 0-0.1 mA(c)
Device current @ 0.5 V (mA)

r1

1.
1.0

S-shapedoutline(Crystallization due to concentration of electric0.15(Crystallization via Joule heating- 1)

0.01

rn-2→rn-2c (Crystallization via Joule heating- n-3)
rn-1→rn-1c (Crystallization via Joule heating- n-2)

10

0.05

0.0

0.4
0.8
1.2
Programming current (mA)

Device resistance (k)rｎ-1

TiN electrode
Insulator
Si Sub.

Device current I (mA)

(a)

1.6

Fig. 7 (a) and (b) MLS programming by current sweepof the device for MLS at programming current intervals

Fig. 6 (a) Schematic cross-sectional diagram of ouroffabricated lateral PCM device with an additional topbetween resistance and programming current, showing

TiN heating layer. (b) Equivalent circuit and principle ofstaircase-like characteristics for MLS.

0.5-1.5 and 0.1 mA, respectively. (c) Relationship(a)Ｒ4、“4”

Ｒ3、“3”
Ｒ2、“2”

Current @ 0.5 V (A)the device for MLS.
110
1009080
7060
50
4030
20
10R3S3
R2

S2
R1

S1
R001000 2000 3000 4000 5000 6000
oＲ1、“1”

ＩＲＲ0、“0”ＶＲ

Annealing time @ 80 C (s)Fig. 8 Thermal stability at 80oC.