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Description

Design Guide: TIDA-010210

11-kW, Bidirectional, Three-Phase ANPC Based on GaN
Reference Design

Description

FeaturesThis reference design provides a design templatefor implementing a three-level, three-phase, gallium
nitride (GaN) based ANPC inverter power stage. The
use of fast switching power devices makes it possible
to switch at a higher frequency of 100 kHz, reducing
the size of magnetics for the filter and increasing
the power density of the power stage. The multilevel
topology allows the use of 600-V rated power devices
at higher DC bus voltages of up to 1000 V. The lower
switching voltage stress reduces switching losses,
resulting in a peak efficiency of 98.5%.

•

Resources
TIDA-010210

Design Folder

LMG3422R030

Product Folder

UCC21541

Product Folder

TMDSCNCD280049C

Tool Folder

TMS320F280049C

Product Folder

AMC3302, OPA4376

Product Folder

ISO7741, SN6501

Product Folder

TPS563200, LP5907

Product Folder

TLV9004, LMT87

Product Folder

Power stage for three-phase inverters and PFCs
using GaN switch
600-V rated switches in 800-V system (due tothree levels)
Novel onboard protection implemented using CLB
of C2000
Iso-quad channel driver supports high-frequency
operation (100 kHz)
Shunt-based current sense (high accuracy andlinearity over temperature)
Power module with up to 16-A current (on AC side)
High power density due to high switchingfrequency (100 kHz) and high efficiency (> 98%
at full load)
Bidirectional operation with < 1-ms directionchangeover
Low component stress helps improve system
reliability
Optimized control scheme needs only 6 PWMs
versus 9 PWMs for standard implementation
Reduced cost - four high frequency switches(versus six) per arm
Real-time safety operation with no extra cost

•
•
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•
•
•
•
•
•
•

Applications
Ask our TI E2E™ support experts•••

String inverter
DC wallbox charger
Power conversion system (PCS)+400 V

ISO7741

Driver

ISO7741

LMG3422R030

Driver

ISO7741

LMG3422R030

Driver+12 V+5 V
TPS563200

LP5907SN6501GATEDRIVES+5 V
DriverDriver

LMG3422R030+3.3 V

LMG3422R030

Driver

LMG3422R030

LMG3422R030

L1
N

L2
L3
AMC3302
DriverDriver

LMG3422R030

Driver

LMG3422R030
UCC2154

LMG3422R030
UCC2154

L1L2 L3

UCC2154

TLV9004

OPA4376
ISO7741

Driver

ISO7741

Driver

ISO7741

Driver

TMS320F28004
LMT87

LMG3422R030

LMG3422R030

TLV9004

LMG3422R030-400 V+400 V -400 V

LOGIC

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1 System Description
Modern commercial scale solar inverters are seeing innovation on multiple fronts, which lead to smaller, higher
efficiency products in the market:•••

The move to higher voltage solar arrays
Reducing the size of onboard magnetics
Inclusion of localized power storage requiring bidirectional power stages

By increasing the voltage to 1000-V or 1500-V DC from the array, the current can be reduced to maintain thesame power levels. The reduction in current reduces conduction losses and hence results in higher efficiency.
The reduction in di/dt also reduces the stress on electrical components. However, high DC bus voltages can limit
the choice of power components that can be used as devices with higher voltage withstand capability is needed.
To compensate for the voltage stresses generated by high-voltage solar arrays, new topologies of solar inverters
have been designed. Traditional half bridges block the full input voltage on each switching device. By adding
additional power components, the overall stress on the device can be significantly reduced. This reference
design shows how to implement a three-level ANPC converter that limits the voltage stress on all the powercomponents to only half the DC bus voltage, allowing use of more abundant and faster power components. This
design also demonstrates the use GaN devices in solar inverters which was not possible with other topologies
due to their limitation of voltage withstand capability.
Additional power density is also being enabled by moving to higher switching speeds in power converters. As
this design shows, a higher switching speed reduces the overall size requirement of the output filter stage—aprimary contributor to the design size.
Though multilevel topologies enable the use of lower voltage switching devices, they come with certain
limitations – the need to drive more switches and need to avoid overvoltage even during abnormal operation.
This design tries to demonstrate how to address all 18 power devices in the power stage with the limited numberof PWMs available from a common MCU and also how to implement hardware based interlocking protections
needed to avoid device overvoltage under all operating conditions without the use of additional components.
Another requirement that is becoming more prevalent for inverter power stages is the need for bidirectional
power transfer. This is important in storage ready inverters where there can be a need for the power fromthe grid to be stored in local power storage like a battery. The power conversion stage in an electronicenergy storage system also has the same requirement. The ANPC power stage demonstrated in this design
is inherently capable of bidirectional operation – only software is required for it to operate either as inverter or
power factor controller (PFC). Currently the design is tested in inverter mode operation and the testing in PFC
mode is in progress.

1.1 Key System Specifications
Table 1-1. Key System Specifications

2

PARAMETERSPECIFICATIONSDETAILS

Output power

11 kW

At 400-V AC

Nominal AC voltage

Three-phase 400-V AC

Output frequency

50 or 60 Hz

Output current

16 A

Nominal DC voltage

800-V DC

Inverter switching frequency

100 kHz

Efficiency

98.5%

Power density

2.57 kW/L

11-kW, Bidirectional, Three-Phase ANPC Based on GaN Reference Design
Copyright © 2022 Texas Instruments Incorporated

600-V to 800-V DC
At 400-V AC, 60% load

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System Overview

2 System Overview
2.1 Block Diagram+400 V

ISO7741

DriverDriver

ISO7741

LMG3422R030

ISO7741

LMG3422R030

Driver+12 V+5 V
TPS563200

LP5907SN6501GATEDRIVES+5 V
DriverDriver

LMG3422R030+3.3 V

LMG3422R030

Driver

LMG3422R030

LMG3422R030

L1
N

L2
L3
AMC3302
DriverDriver

LMG3422R030

Driver

LMG3422R030
UCC2154

LMG3422R030
UCC2154

L1L2 L3

UCC2154

TLV9004

OPA4376
ISO7741

Driver

ISO7741

Driver

ISO7741

Driver

TMS320F28004
LMT87

LMG3422R030

LMG3422R030

TLV9004

LMG3422R030-400 V+400 V -400 V

LOGIC

Figure 2-1. Block Diagram
This reference design is built in a modular construction to allow easy replacement of power switching devices toallow easy comparison between them. The following boards combine to form this three-phase inverter reference
design:••••A motherboard, comprising of the LCL filter, sensing electronics, bias power, switching relays and coolingfans.
A TMDSCNCD280049C Control Card to support the DSP.
Six power cards switching at 100 kHz containing GaN power switching devices and isolated bias power
supplies.
Three power cards switching at 100 Hz and 120 Hz containing Si power switching devices, gate drivers andisolated bias power supplies.

Though the board can accept 12-V bias power from an external power supply, it has provision to add an auxiliary
power supply that can run from the high voltage DC bus.

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2.2 Design Considerations
2.2.1 Three-Phase ANPC Inverter Architecture Overview
The basic architecture of the ANPC topology is shown in Figure 2-2.
V+

Q1A

Q5A

Q5C

Q5B
Q2A

Q1C

Q1B

Q2C

Q2B
A
B
C

Q6A

Q6C

Q6B

Q3C
Q3A

Q3B

Q4A

Q4B

Q4C

V-

Figure 2-2. ANPC Three-Phase Inverter Architecture
To simplify the analysis, a single leg can be separated out as shown in Figure 2-3.
V+

Q1

Q5

Q6

Q2

Q3

Q4

V-

Figure 2-3. ANPC Single-Phase Inverter Leg

4

11-kW, Bidirectional, Three-Phase ANPC Based on GaN Reference Design
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As can be seen, there are six switches in each phase. Though there can be various switching schemes tocontrol this power stage, we selected a relatively simpler scheme to reduce complexity. The upper half of thecircuit consisting of Q1, Q5 and Q2 is active during the positive half cycle and the lower half consisting of Q4,
Q6 and Q3 is active during the negative half cycle. Q2 and Q3 are slow switches that connect the inductor toeither the upper high frequency switching pair of Q1 & Q5 or Q4 & Q6 during positive and negative half cycles
respectively. Each of the high frequency switching pairs is operated as a synchronous buck converter during
their corresponding half cycles. The switching scheme is explained in detail in Figure 2-4 and Figure 2-5.
V+

V+

Q1

Q5

Q6

Q1

Q5

Q2

Q6

Q3

Q4

Q2

Q3

Q4

V-

Figure 2-4. Inductor connected to V+

V-

Figure 2-5. Inductor connected to N (+ve)

Figure 2-4 and Figure 2-5 show the operation of the circuit during the positive half cycle of this phase. The
components in red are the ones that are conducting and those in black are the ones that are off. As can be seen
Q2 remains on for the entire half cycle. When Q1 is on, the circuit is in active mode, establishing current flowfrom V+ to the inductor as in Figure 2-4. Since both Q1 and Q2 are on, the switching node of the inductor isconnected to V+. Now, the switches Q3 and Q4 together have to withstand the full bus voltage. To avoid unequal
distribution of the bus voltage among these devices (due to unequal device parasitics), Q6 also is kept on so thatthe central node gets connected to neutral, dividing the voltage equally between Q3 and Q4. When Q1 and Q6
are turned off together during the dead-time between the states shown in Figure 2-4 and Figure 2-5, the inductor
current can only flow through the body diode of Q5 and Q2 (which stays on). During the freewheeling modeshown in Figure 2-5, Q5 acts as a synchronous diode, connecting the switching node of the inductor to neutral.
Since the switches Q3 and Q4 have only half the bus voltage across them, it is not necessary to keep Q6 on forvoltage balancing.

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V+

V+

Q1

Q5

Q6

Q1

Q5

Q2

Q6

Q3

Q4

Q2

Q3

Q4

V-

V-

Figure 2-6. Inductor connected to V-

Figure 2-7. Inductor connected to N (-ve)

Similar to the operation during the positive half cycle, Figure 2-6 and Figure 2-7 illustrate the operation of the
ANPC power stage during the negative half cycle. Q3 remains on for the entire duration of the negative halfcycle.
Figure 2-6 shows the active mode operation in which the inductor gets connected to V- through Q4 and Q3.
Similar to the operation during positive half cycle, Q5 also is kept on in this active mode operation to balance
the voltage stress between Q1 and Q2. In freewheeling mode shown in Figure 2-7, the inductor current ismaintained through Q6 and Q3, connecting the inductor switch node to neutral.
2.2.2 LCL Filter Design
Any system of power transfer with the grid is required to meet certain output specifications for harmonic content.
In many rectifiers, a high-order LCL filter typically provides sufficient harmonic attenuation, along with reducing
the overall design size versus a simpler filter design. However, due to the higher order nature, take some care inits design to control resonance. Figure 2-8 shows a typical LCL filter.

iinv

igrid

Rd

Cf

Figure 2-8. LCL Filter Architecture
One of the key benefits of using GaN switching device (as this reference design does) is the ability to increase
the switching frequency of the power stage significantly versus traditional Si-based switching devices. This
increased switching frequency has a direct impact on the filter resonant design of the converter, which needs
to be accounted for. To ensure that the filter is designed correctly around this switching frequency, the known
mathematical model of this type of filter is used in this design.
The primary component is the switch side inductor, or Linv, which can be derived using Equation 1:

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V DC

L inv

8 u f SW u I grid _ rated u %ripple(1)

Using the system specifications, the primary inductor value can be calculated:

1000 V
8 u 100 kHz u 10 A u 30%

L inv

417 +

(2)

An inductor from Wurth Elektronik (750344413) with rated current of 15 A having zero bias inductance of 480
mH is used. With the high current bias during the operation, the inductance can reduce by 25% as per the data
sheet. This results in an effective inductance of 360 mH at 15 A, which is sufficient to ensure ripple current below
40%.
The sizing of the primary filter capacitor is handled in a similar fashion using Equation 3:%$ u 4 rated

Cf

2
2 u Œ u )grid u 9 grid

(3)

Make some design assumptions to finalize the value of Cf , limiting the total reactive power absorbed by thecapacitor to 3.5%. Scaling the total system power by the per phase power results in a primary capacitor value of:

6.6 kW
3
2§ 400 V ·+] u ¨¸© 3 ¹

3.5% uCf2uŒ u

4.59 )(4)

A standard value capacitor of 4.7 μF was selected.
For the remainder of the filter design, determine the values by defining the attenuation factor between theallowable ripple in grid inductor and the inverter inductor. This factor needs to be minimized while still
maintaining a stable and cost effective total filter. By assuming an attenuation factor, an r value, which defines
the ratio between the two inductors, is determined using Equation 5:

1

I att

2
1 r u ª1 L inv u C b u 2 u Œ u I SW u $ º
«¬
»¼

u 100
(5)

Where Cb is given by:

Cf

Cb

4.7 )

134 )

$

(6)

To obtain an attenuation factor of 5%, and using the earlier derived values, the value of r can be evaluated byrewriting Equation 5 to be:r1

360 + u1
1
5%
) u uŒu

N+]

2

2.85%
u
(7)

The resultant value for Lgrid is then:

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L gridwww.ti.com

r u L inv

2.85% u 360 ++(8)

A higher standard value of 15 μH was selected to ensure good attenuation.
The filter design can be validated by determining its resonant frequency (Fres). A good criteria for ensuring astable Fres is that it is an order of magnitude above the line frequency and less than half the switching frequency.
This criteria avoids issues in the upper and lower harmonic spectrums. The resonant frequency of the filter isgiven by Equation 9:

1
L grid u L inv
Fres

L grid L inv

u Cf

2u Œ

(9)

Using the derived filter values, the resonant frequency is:

1

Fres

15 + u15 ++u 4.7 )+
2uŒ19.35 kHz
(10)

This value for Fres meets the criteria listed earlier and validates the filter design.
The remaining value to determine is the passive damping that must be added to avoid oscillation. Generally, a
damping resistor at the same relative order of magnitude as the Cf impedance at resonance is suitable. This
impedance can be derived using Equation 11:

Rd

Rd

1
6 u Œ u )res u & f

(11)

1
6uŒu

0.58
N+] u

)

(12)

For the final implementation in hardware, use real values for all of these components based on productavailability and must be chosen to be appropriately close (±10% typically). When final values are determined,
recalculate the resonant frequency to ensure the filter is still stable.
2.2.3 Power Switching Devices Selection
As shown in the architecture overview, the main switching device needs to support only half the full switchingvoltage. To support the 800-V DC link voltage of this design, use 600-V rated devices. The switches Q1, Q5, Q4,
and Q6 are high-frequency switching and hence must be GaN devices. However, the switches Q2 and Q3 areonly switching at 100 Hz and 120 Hz and can use Si MOSFETs.
Conduction loss is mainly determined by the RDS(on) of the GaN MOSFET and the RDS(on) of the Si MOSFET.
At any instance, there are two devices conducting at the same time (one each of the GaN device and the Si
device). So the RDS(on) of these should be selected based on the conduction loss that can be allowed on them.
Switching loss is a function of the switching frequency and switching energy of each switching element; theswitching energy being related to the device current and voltage at the switching transient. Using the switchingenergy curve in the data sheet, the total switching loss can be estimated. Note that in inverter configuration, only
Q1 or Q4 experience switching loss, as Q5 and Q6 work as synchronous switches only and hence experiencezero voltage switching. However, since Q5 and Q6 body diodes conduct during dead-time, they can haveforward drop loss and reverse recovery loss. However, TI’s GaN devices do not have reverse recovery loss at

811-kW, Bidirectional, Three-Phase ANPC Based on GaN Reference Design
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all and SiC devices have only negligible reverse recovery. Q2 and Q3 switch only at a very low frequency andhence their switching loss can be neglected.
The conduction loss and switching loss can be estimated for all the devices and efficiency can be estimated as
explained. With the thermal impedance information of the thermal system design, the proper device rating canbe selected. 600-V, 30-mΩ GaN and 650-V, 40-mΩ Si MOSFET are good tradeoffs among thermal, efficiency
and cost.
2.2.4 GaN Power Stage
Unlike the Si power boards which are driven by isolated gate drivers as explained in Section 2.2.8, the TI GaN
device LMG3422R030 has built-in gate drive. So the power stage needs signal isolation to interface with the
MCU. Figure 2-9 shows the GaN power stage. The ISO7741 isolator used to isolate the PWM input has anotherchannel in the reverse direction that can transmit the fault signal back to the MCU side. As this is a negative
logic one, an AND gate is used to combine these signals to give a negative logic fault signal back to the MCU ifeither of these GaN devices generate a fault.
U1
5V_H

R1
49.9
C3
68pF

VCC1

VCC2

8

2

OUTA

INA

7

3

INB

OUTB

6

4

GND1

GND2

5

C4
1uF

R2

C1
0.22uF

R3
10.0k

49.9

VDD

25

LDO5V

C2
10uF

ISO_RET_H
IN_H

AGND

31

IN

32

FAULT

29

LPM

30

RDRV

ISO7721DWVRFAULT_H

AGND

27

5V_H
1

AGND

SW_H

28

BBSW

VM12V_H

26

VNEG

C9
2.2uF

17

SN74AHC1G08DBVR
C5
0.1uF

5V 12V

3

J1

C6
68pF
C7
22pF

AGND

C8
68pF

R4
15k

L1
10uH

U3

6 Top_FET
5 Bot_FET
4 GaN_Fault
3
2
1

HVBUS

ISO_12V_H

U2
5V

2
4

NC

DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN

1
2
3
4
5
6
7
8
9
10
11

SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE

12
13
14
15
16
18
19
20
21
22
23
24

PAD

33

LMG3410R050RWHT

1

C11
0.022µF

ISO_RET_H
5

ISO_RET_H

C12
0.1uF

C13
0.1uF

C14
0.1uF

C15
0.1uF

C16
0.1uF

C17
0.1uF

C18
0.1uF

C19
0.1uF

5V

U4

Aux Connector

ISO_12V_L

U5
C20
0.1uF

R5

AGND

TP3 TP4

2
3
4

AGND

C23
68pF

27

VDD

25

LDO5V

5V_L
1

49.9

TP1 TP2

5V_L

5V

AGND

VCC2

8

OUTA

INA

7

INB

OUTB

6

GND1

GND2

5

VCC1

R6

C21
0.22uF

R7
10.0k

49.9

ISO_RET_L

C24
1uF

AGND

C22
10uF

ISO_RET_L

IN_L

31

IN

32

FAULT

29

LPM

30

RDRV

28

BBSW

26

VNEG

ISO7721DWVRFAULT_L

AGND

ISO_RET_L
HVBUS
SW_L

C25
0.1uF
TP5 TP6

C26
68pF
C27
22pF

C28
68pF

R8
15k

L2
10uH

VM12V_L

C29
2.2uF

ISO_RET_H

17

NC

DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN

1
2
3
4
5
6
7
8
9
10
11

SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE

12
13
14
15
16
18
19
20
21
22
23
24

PAD

33

LMG3410R050RWHT
Power Connector
ISO_RET_L

ISO_RET_L

Figure 2-9. GaN Power Stage
2.2.5 Voltage Sensing
Voltage sensing happens at three points in the inverter signal path to aid in control: before and after the primary
output relay and at the positive and negative bus voltages. By enabling measurement on both sides of therelay, the control system can lock into the grid voltage and frequency before connecting, thus preventing any
mismatch issues. Similarly, sensing of the positive and negative bus voltages help in fine adjusting the duty cycle
separately during the positive and negative half cycle to prevent any bus voltage mismatch.
All three sensing topologies are similar. First, PGND is used as a virtual neutral using a resistor network. The
high voltage signal is attenuated using a series of large value resistances. An offset of 1.65 V is added to theattenuated neutral point to center the voltage signal in the middle of the input range of the TLV9004, and theattenuated value from the phase voltage is measured using the ADC within the C2000™ MCU. Figure 2-10
shows this sensing arrangement.

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R33
12.0k

R36

1.00M R37

1.00M R38

1.00M

VA_N

2

R48

1.00M R49

1.00M R50

1.00M

VA_P

3

1.65V_1

R57
12.0k

C14

U1A

470pF

A

1

R45

Vsen_A

Vinv_SEN_A

68.1

PGND

C17
0.01µFTP16

TLV9004IDR

GND

Figure 2-10. High-Voltage Sensing Signal Path2.2.6 Current Sensing
Critical to getting a closed loop control system is accurate current measurement of the inverter. In this design,
current measurement is done to sense the current through the inductor. Because the output is high voltage andthe controller needs to remain isolated, the AMC3302 reinforced isolated current sensor is used to measure theresistor voltage drop. To keep system losses low, the AMC3302 has a ±50-mV input range. When comparedto other devices with a typical input range of ±250 mV, the total power loss across the shunt is significantly
reduced.
Sizing the shunt resistor for this design is a trade-off between sensing accuracy and power dissipation. A 2-mΩshunt provides a ±50-mV output signal at the inverters approximate ±25-A output but also only generates 0.5
W of heat at full load. When choosing an actual device, select a high accuracy one to eliminate the need tocalibrate each sensor path.
The voltage across the shunt resistor is fed into the AMC3302 isolated current sensor with integrated isolated
bias power supply, which generates a differential output. This differential output is converted to a single ended
output with a 1.65-V offset using an OPA4376 amplifier for measurement using the ADC present on the C2000™
MCU. Figure 2-11 shows the current sensing circuit.
3.3V
R112

10.0

C36
R119 10nF
10.0

12

VDD

OUTN
OUTP

10
11

7
6

INN
INP

DCDCOUT

1

16

DCDCINHLDOOUT5HLDOINLDOOUT

13

HGND

8

DCDCGND
DCDCHGND

15
2

GND

9

3

C40
1µF
C43
1nF
C45
0.1uF

4
14

NU
NU

C47
1nF

L10

Isen_A_N
C35
3300pF

R117 49.9

R114

10.0k

2

Isen_A_P R118

10.0k

3

U5A
1

R116
Isen_A

499
OPA4376AIPW

R120
10.0k

C39
330pF

11

R115

Iind_A

3.3V_1

4U4
R113 49.9

Iind_A_Rtn

10.0k

3.3V

L11

C38
220pF

C37
0.1uF

1.65V_C
C42
330pF

C41
0.1uF
C44
1µF

GND

GND

GND

C46
0.1uF
C48
1nF

AMC3302DWER
GND

GND

GND

GND

GND

GND
Vsen_A

Figure 2-11. Isolated Current Sensing With AMC3302
2.2.7 System Power Supplies
This reference design uses multiple voltage domains across the system:
•
•
•

10

A primary bias power input to power the entire design (regulated 12 V). This is used to directly power relays
and fans used on the board. There is a connector provision on the main board to generate this 12-V supply
directly from the high-voltage DC bus.
A TPS563200 synchronous buck converter generates 5 V to power the control card and power cards from the
12 V main power. Each of the power cards generate its own isolated power supply for gate driving from this5-V power supply.
The 3.3-V supply for analog sensing and logic is generated by an LDO LP5907 from the 5 V.

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System Overview

Figure 2-12 shows the power tree for all of these domains.
12V_INT

U15

+12V

VIN

SW

2

5

EN

VBST

6

3
2
1

2
1

R144
56.2k

0.1uF

GND

U16

TP35

3.3uH

C83

J74

TP36

1

VIN

3

EN

4

N/C

VOUT

5

GND

2

3.3V

R143
820

J75
C87
35V
10uF

C88
35V
10uF

VFB

4

GND

1

LP5907MFX-3.3/NOPB

GND

GND

GND

R145
10.0k

TP37

TPS563200DDCR

GND

C89
10V
22uF

GND

GND

C90
10V
22uF

2

C86
25V
100uF

C91
2.2µF
16V

C92
2.2µF
16V

D7
1

12V_EXT

5V

L14

3

GND

GND

GND

GND

GND

GND

Figure 2-12. Power Tree
2.2.7.1 Isolated Bias Supplies
To generate the isolated bias supplies for each of the power cards, the SN6501 transformer driver is used todrive transformers suited for the power rails required to drive the specific power switching devices used in eachtype of board As each of the boards have two switching devices, there are two isolated bias power supplies per
board.
For the TI GaN device LMG3410R050, a 12-V output is needed. This is generated using the SN6501
transformer driver along with Würth Elektronik 750313638 transformer in a voltage doubler configuration asshown in Figure 2-13.
ISO_12V_L_B

T1

3
2

4
D2
VCC

2

D1

1

5V
5

2

6

1

D1
BAT54S-7-F

3

ISO_12V_L

GND

C30

U6

L3

1

4.7uF

750313638
C36

C35
10µF
10V

C32

D3

4.7uF

16V

3

C34
0.1uF

2

5

4

GND

3

1

4

4.7uF
ISO_RET_L_B

ISO_RET_L

AGND

Figure 2-13. SN6501 Bias Voltage Supply for GaN Power Board
For the slow switching Si power board, a +12-V, –5-V drive is used to drive the FCH040N65S3 Si MOSFET.
The SN6501 transformer driver along with Würth Elektronik 750342879 transformer in a push-pull configuration
is used to generate a 17-V supply. A TL431-based level-shifting circuit converts this to +12-V, –5-V supply. The
circuit is shown in Figure 2-14.
+12Va

U2

T1

R11
4.7k

4
1

3

C15
10uF

C16
10uF

3

D2

GND

D3

5

5V
2

GND

5

3

C13
4.7uF

4
1

SN6501QDBVRQ1

6

SW

R12
4.99k

750342879

U3

C17
0.1uF
R13
4.99k

3

GND

C14
4.7uF
2

VCC

1

D1

2

1
2

5V

C12
0.1uF

GND

-5Va

Figure 2-14. SN6501 Bias Voltage Supply for Si Power Board

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2.2.8 Si Gate Driver Circuit
Figure 2-15 shows the schematic of the isolated Si MOSFET gate driver. As the UCC21541 gate driver used has
two isolated gate drive outputs, it can drive both the devices in the half-bridge power stage of the power board.
The drive current is controlled separately for turn-on and turn-off with diode controlled separate drive paths. A
ferrite bead is used in the gate drive path to suppress ringing.
+12Va

C1
4.7uF
SW

U1

EN/Fault
PWM1A
PWM1B

C2
4.7uF

R4

100

1

R6

100

2
3

VDDA

16

INB

OUTA

15

VCCI

VSSA

14

4

GND

NC

13

5

DISABLE

NC

12

6

DT

VDDB

11

7

NC

OUTB

10

8

VCCI

VSSB

9

GND

5V

R10
10.0k
C7
0.1uF

C8
0.1uF

C4
100pF
50V

C5
100pF
50V

R3
10.0k

C6
2.2nF
50V

INA

C3
0.1uF
-5Va

L1

R5

G1H_P

D1

22.1

782853121
R7

DFLS240-7
D2

DFLS240-7
R9

22.1
R8
22.1
L2
G1L_P

22.1

782853121+12Vb

UCC21541DWR

C9
4.7uF

C10
0.1uF
SW-

C11
4.7uF
GND

-5Vb

Figure 2-15. UCC21541 Gate Drive Circuit

12

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Hardware, Software, Testing Requirements, and Test Results

3 Hardware, Software, Testing Requirements, and Test Results
3.1 Hardware and Software Requirements
3.1.1 Hardware
The DUT in this design is set up and operated in several pieces:
•

•
•
•

•
•

One TIDA-010210 mother board (TIDA-010210-MB-E2)– J75 Header : Jumper between pin 1 and pin 2– Change 750344413 with 750343810 (L2, L4, L6)
Six TIDA-010210 power cards based on GaN (TIDA-010210-GaN-E3)
Three TIDA-010210 power cards based on Si (TIDA-010210-Si-E2)
TMDSCNCD280049C Control Card:– S2 Switch : Change from the DOWN to the UP position– S3 Switch : Changed from the UP to the DOWN position
Mini USB cable
Laptop or other computer

The test equipment required to power and evaluate the design is as follows:
•
•
•
•
•
•

>12-V, 2-A bench style supply for primary board power>11-kW AC source>11 kW, 800-V DC load
> 1000-V, 10-A power supply for DC link input> 6.6-kW resistive AC load
Four-channel power quality analyzer

3.1.2 Software•

Code Composer Studio™ 9.3 or later versions with TI C2000 powerSUITE

3.2 Testing TIDA-010210 With AC Resistive LoadIn this test condition, the system is configured to operate in an open loop and close-loop control mode,
generating a static 50-Hz output. The power demand is then modulated by the resistive bank, together with
the MCU, to test the system at multiple load points. This operation allows the user to do preliminary testing
before going at high voltage and high power operation.
3.2.1 Test Setup

1000-V, 10-A
DC-SUPPLY

6.6-kW
AC-Resistive Load

TIDA-010210
DCAC

12 V, 2 A
Bench Power
SupplyFigure 3-1. Test Setup for Resistive AC LoadTo test the functionality of this reference design, use the following equipment:••••

One Magna-Power 1000-V, 10-A power supply to provide CV/CC adjustable input to the DUT
A 6.6-kW KWE load bank is used as a configurable load to test the design at various set points.
An oscilloscope
An external bench power supply is used to provide a 12-V input to power the DUT

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3.2.2 Experimental Results
The open loop test output waveforms in Figure 3-2 show clean sinusoidal waveforms with the new PWM
scheme, when DC bus is operating at 800 V. There is very little distortion even at zero crossing with CLB based
protection active.

Figure 3-2. Open Loop Output Waveforms (AC Load Voltage Waveforms)
The current loop stability of the circuit is demonstrated by the smooth transition in the current transient response.
Figure 3-3 shows the response when current is changed from 1 A to 6 A and Figure 3-4 shows the responsewhen current is changed from 6 A to 1 A.

Figure 3-3. Positive-Going Transient Response (AC Load Voltage Waveforms)
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Figure 3-4. Negative-Going Transient Response (AC Load Voltage Waveforms)

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3.3 Testing TIDA-010210 in PFC Operation
In this test condition, the system is configured to operate in an close-loop control mode. The TIDA-10210 design
is implementing a current control loop able to synchronize with the emulated grid voltages of the AC source. On
the DC link, the DC load is controlling directly the voltage, thus allowing the user to control the converter powerby changing the reference current of the d sequence. In this operating condition, efficiency versus power has
been measured.
3.3.1 Test Setup
To test the efficiency of this reference design, use the following equipment:••••

A 12-kW DC load able to regulate the load voltage from 50 V to 850 V
A 12-kVA AC supply able to regulate the voltage from 25 to 250 V
An AC power analyzer is connected to the DUT input and output to perform efficiency measurements
An external bench power supply is used to provide a 12-V input to power the DUT

Figure 3-5 shows the test setup for PFC operation.

Power Analyzer

1000-V, 10-A
DC-SUPPLY

6.6-kW
AC-Resistive Load

TIDA-010210
ACDC

12 V, 2 A
Bench Power
SupplyFigure 3-5. Test Setup for PFC Operation

16

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3.3.2 Experimental Results
Close loop test output waveforms in Figure 3-6 show clean sinusoidal waveforms at the nominal load. During theexperiments, no important zero crossing distortion was observed in the currents. Total harmonic distortion lessthan 4% was measured.
400
vL1

Voltage (V)

200

0

-200

-400
0

5

10

15

20
Time (ms)

25

30

35

40

25
iL1
iL2
iL3

Current (A)

15

5

-5

-15

-25
0

5

10

15

20
Time (ms)

25

30

35

40

Figure 3-6. Currents and Voltage Working at 11-kVA PFC full

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Table 3-1 and Table 3-2 collect the efficiencies of the PFC at 230 VRMS, respectively for two different DC bus
voltages: 600 V and 800 V. The results obtained from the power analyzer are taken from 2 kW to 11 kW. In mostof all the operating points, the power efficiency is higher than 98% by reaching a maximum of 98.62%.
Table 3-1. System Efficiency With GaN LMG3422R030 at 600-V DC
DC BUS VOLTAGE(V)

AC GRID
CURRENT (A)INPUT POWER(W)

OUTPUT POWER(W)EFFICIENCY

605.3

3

2045.7

1980.296.8

605.345.22

3559.53506.1

98.5

605.3874773.34707.4

98.62

605.2

8.9

6068.95978.598.51

605.2810.97432.77309.398.34

605.3413.05

8898.88731.5

98.12

605.5

15.2

10364.910148.3

97.91

605.8

16.5

11251.4

11006.1

97.82

Table 3-2. System Efficiency With GaN LMG3422R030 at 800-V DC

18

DC BUS VOLTAGE(V)

AC GRID
CURRENT (A)INPUT POWER(W)

OUTPUT POWER(W)EFFICIENCY

803.4

3.02

2070

1976.8

95.5

801.4

5.24

3601.83511.8

97.5

802.4

7.01

4830

4747.9

98.3

803.4

8.95

6141

6042.7

98.4

803.5

10.93

7521

7408.2

98.5

802.8

12.98

8970

8826.5

98.4

803.8

15.21

10488

10304.5

98.25

803.1

16.52

11385

11180.1

98.2

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All the data summarized in the tables have been collected and plotted as shown in Figure 3-7. At low power it isbetter to keep the PFC to work at lower DC bus voltage. Conversely, at a higher current keeping higher DC bus
voltage leads an important efficiency improvement of 0.4%.

100
99
98

Efficiency (%)

97
96
95
94
93
92
VDC = 600 V
VDC = 800 V

91
90
0

2

4

6
Power (kW)

8

10

12

Figure 3-7. PFC Efficiency vs Input PowerThe final design dimensions are outlined in Table 3-3 and show a total volume of 4.3 L. With a power rating of 11
kW, this results in a power density of 2.57 kW/L.
Table 3-3. TIDA-010210 Dimensions

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AXIS

DIMENSIONX

300 mmY

220 mmZ

65 mm

Volume4.29 liters

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Design and Documentation Support

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4 Design and Documentation Support
4.1 Design Files
4.1.1 Schematics
To download the schematics, see the design files at TIDA-010210.
4.1.2 BOM
To download the bill of materials (BOM), see the design files at TIDA-010210.
4.1.3 Altium Project
To download the Altium Designer® project files, see the design files at TIDA-010210.
4.1.4 Gerber Files
To download the Gerber files, see the design files at TIDA-010210.
4.1.5 Assembly Drawings
To download the assembly drawings, see the design files at TIDA-010210.

4.2 Tools and Software
Tools
ConciseDescription

TMDSCNCD280049C is an HSEC180 controlCARD based evaluation and development tool
for the C2000™ F28004x series of microcontroller products. controlCARDs are ideal to use
for initial evaluation and system prototyping. controlCARDs are complete board-level modules
that utilize one of two standard form factors (100-pin DIMM or 180-pin HSEC ) to provide a lowprofile single-board controller solution. For first evaluation controlCARDs are typically purchased
bundled with the TMDSHSECDOCK baseboard or bundled in an application kit.

SoftwareConcise Description

To download the software, see the software files at TIDA-010210.

4.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straightfrom the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

4.4 Trademarks
TI E2E™ and C2000™, and are trademarks of Texas Instruments.
Altium Designer® is a registered trademark of Altium LLC or its affiliated companies.
All trademarks are the property of their respective owners.

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About the Authors

5 About the Authors
RICCARDO RUFFO received the Ph.D. degree in Electric, Electronics and Communication Engineering from
Politecnico di Torino, Turin, Italy, in 2019. He is currently working at Texas Instruments Germany as System
Engineer in the area of Grid Infrastructure, Renewable Energy. His main work includes EV charging, inductive
wireless power transfer, photovoltaic, renewable energy, and energy storage applications.
SALIL CHELLAPPAN is a Systems Engineer at Texas Instruments working on leveraging TI's product portfolio
to solve system engineering problems related to Renewable Energy markets. After graduating from Kerala
University in 1990, Salil started his career at Bharat Electronics. Subsequently, he worked for companies forexample, Lucent Technologies, Power Integrations, and GE before joining Texas Instruments; where he has
worked in various roles as Lead Engineer, Systems Manager, and Systems Engineer for the past 13 years.

6 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (March 2021) to Revision A (March 2022)
Page• The TIDA-010210 is upgraded to run at 11 kW. Changes in revision A of this design guide support thisupgrade...............................................................................................................................................................1

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