TCAN1044A-Q1
SLLSFJ3D – AUGUST 2023 – REVISED OCTOBER 2024

TCAN1044A-Q1 Automotive Fault-Protected CAN FD Transceiver with Standby mode
1 Features

3 Description•

The TCAN1044A-Q1 is a high speed controller area
network (CAN) transceiver that meets the physicallayer requirements of the ISO 11898-2:2016 highspeed CAN specification.

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AEC-Q100 (Grade 1) Qualified for automotive
applications
Meets the requirements of ISO 11898-2:2016
physical layer standard
Functional Safety-Capable– Documentation available to aid in functionalsafety system design
Support of classical CAN and optimized CAN FD
performance at 2, 5, and 8Mbps– Short and symmetrical propagation delays forenhanced timing margin
TCAN1044AV I/O voltage range supports 1.7V to
5.5V
Support for 12V and 24V battery applications
Receiver common mode input voltage: ±12V
Protection features:– Bus fault protection: ±58V
– Undervoltage protection– TXD-dominant time-out (DTO)• Data rates down to 9.2kbps– Thermal-shutdown protection (TSD)
Operating modes:– Normal mode
– Low power standby mode supporting remotewake-up request
Optimized behavior when unpowered– Bus and logic pins are high impedance (no load
to operating bus or application)– Hot-plug capable: power up/down glitch-free
operation on bus and RXD output
8-Pin SOIC, small footprint SOT-23 and leadless
VSON-8 package with improved automated opticalinspection (AOI) capability

2 Applications

The transceivers have certified electromagnetic
compatibility (EMC) operation making it an ideal
choice for classical CAN and CAN FD networks up
to 5 megabits per second (Mbps). Up to 8Mbps
operation in simpler networks is possible with thesedevices. The TCAN1044AV-Q1 includes internal logic
level translation via the VIO pin to allow for interfacing
the transceiver I/O's directly to 1.8V, 2.5V, 3.3V, or
5V logic levels. The transceiver supports a low-power
standby mode and wake over CAN which is compliant
to the ISO 11898-2:2016 defined wake-up pattern(WUP).
The transceivers also include thermal-shutdown(TSD), TXD-dominant time-out (DTO), supply
undervoltage detection, and ±58V bus fault protection.
The devices have defined fail-safe behavior in
supply undervoltage or floating pin scenarios. Thesetransceivers are not only available in industrystandard SOIC-8 and VSON-8 packages, but also
have a space-saving small footprint SOT-23 package
option.
Package Information

TCAN1044A-Q1

(1)
(2)
VBAT

•

Automotive and transportation– Body control modules– Automotive gateway– Advanced driver assistance system (ADAS)– Infotainment

PACKAGE(1)PART NUMBER

PACKAGE SIZE(2)SOIC (D)

4.9mm x 6mm

VSON (DRB)

3mm x 3mm

SOT-23 (DDF)

2.9mm x 2.8mm

For more information, see Section 12.
The package size (length × width) is a nominal value andincludes pins, where applicable.
VIN

VOUT

5-V Voltage
Regula tor

3
VCC

VDD
Por t x

8

CANH

MCU

VIN

1.8 V / 2.5 V / 3.3 V
Regula tor

RXD
CAN FD
Controller
TXD

7

STB

TCA N1 044AV

4
RXD
1
TXD

VIO

GND

CANL

6

5

VOUT

Optiona l:
Terminating Node

Optiona l: Filte ring,Transient a nd ESD

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Device Comparison......................................................... 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 ESD Ratings - IEC Specifications .............................. 4
6.4 Recommended Operating Conditions ........................4
6.5 Thermal Characteristics ............................................. 5
6.6 Supply Characteristics ............................................... 5
6.7 Dissipation Ratings .................................................... 6
6.8 Electrical Characteristics ............................................6
6.9 Switching Characteristics ...........................................8
6.10 Typical Characteristics............................................ 10
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................14
8.1 Overview................................................................... 14

8.2 Functional Block Diagram......................................... 15
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................19
9 Application Information Disclaimer............................. 22
9.1 Application Information............................................. 22
9.2 Typical Application.................................................... 22
9.3 System Examples..................................................... 24
9.4 Power Supply Recommendations.............................24
9.5 Layout....................................................................... 25
10 Device and Documentation Support..........................26
10.1 Receiving Notification of Documentation Updates..26
10.2 Support Resources................................................. 26
10.3 Trademarks............................................................. 26
10.4 Electrostatic Discharge Caution..............................26
10.5 Glossary..................................................................26
11 Revision History.......................................................... 26
12 Mechanical, Packaging, and Orderable
Information.................................................................... 27

4 Device Comparison
Table 4-1. Device Comparison Table
Part Number

2

Low Voltage I/O Logic Support on Pin 5

TCAN1044A-Q1

No

TCAN1044AV-Q1

Yes

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Pin 8 Mode Selection
Low Power Standby Mode with Remote
Wake

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5 Pin Configuration and Functions

TX D

1

8

STB

TX D

1

8

STB

GND

2

7

CA NH

GND

2

7

CA NH

VCC

3

6

CA NL

VCC

3

6

CA NL

RX D

4

5

NC, VIO

RX D

4

5

NC, VIO

No t to scale

No t to scale

Figure 5-1. DDF Package, 8-Pin SOT (Top View)

TXD

1

GND

2

VCC

3

RXD

4

ThermalPad

Figure 5-2. D Package, 8-Pin SOIC (Top View)

8

STB

7

CANH

6

CANL

5

NC,VIO

Not to scale

Figure 5-3. DRB Package, 8-Pin VSON (Top View)
Table 5-1. Pin Functions
Pins

Type

Description

Name

No.

TXD

1

GND

2

GND

Ground connection

VCC

3

Supply5V supply voltage

RXD

4

NC
VIO

5

CANL

6

CANH

7

STB

8

Thermal Pad (VSON only)

Digital Input CAN transmit data input; integrated pull-up

Digital Output CAN receive data output, tri-stated when device powered off—

Not internally connected; Devices without VIO

SupplyI/O supply voltage for devices with suffix 'V'

Bus IO

Low-level CAN bus input/output line

Bus IO

High-level CAN bus input/output line

Digital Input Standby input for mode control; integrated pull-up—

Connect the thermal pad to any internal PCB ground plane using multiple vias for optimal
thermal performance.

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6 Specifications
6.1 Absolute Maximum Ratings(1) (2)

MIN

MAX

VCC

Supply voltage

–0.3

6

V

VIO

Supply voltage I/O level shifter

–0.3

6

V

VBUS

CAN Bus I/O voltage

–58

58

V

VDIFF

Max differential voltage between CANH and CANL

–45

45

V

VLogic_Input

Logic input terminal voltage

–0.3

6

V

VRXD

RXD output terminal voltage range

–0.3

6

V

IO(RXD)

RXD output current

–8

8

mA

TJ

Junction temperature

–40

165

°C

TSTG

Storage temperature

–65

150

°C

(1)

(2)

UNIT

Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
All voltage values, except differential I/O bus voltages, are with respect to ground terminal.

6.2 ESD Ratings

Human-body model (HBM), per AEC Q100-002(1)VESD

Electrostatic discharge

VALUE

UNIT

HBM classification level 3A forall pins±4000

V

HBM classification level 3B for
global pins CANH and CANL
with respect to GND±10000V±750

V

Charged-device model (CDM), per AEC Q100-011
CDM classification level C5 for all pins

(1)

AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 ESD Ratings - IEC Specifications
VALUE

UNIT

±8000

V

±8000

V

SAE J2962-2 per ISO 10605
Powered Air Discharge (2)±15000V

Pulse 1

–100

V

Pulse 2a75

V

Pulse 3a–150

V

Pulse 3b100

V

DCC slow transient pulse±30

V

Unpowered contact discharge
per ISO 10605 (1)VESD

SAE J2962-2 per ISO 10605
Powered Contact Discharge

System level Electrostatic discharge(2)

CAN bus terminals to GND

Transient voltage per ISO 7637-2(3)VTranTransient voltage per ISO 7637-3(4)

(1)
(2)
(3)
(4)

Tested according to IEC 62228-3:2019 CAN Transceivers.
Results given here are specific to the SAE J2962-2 Communication Transceivers Qualification Requirements - CAN. Testing performed
by OEM approved independent third party, EMC report available upon request.
Tested according to IEC 62228-3:2019 CAN Transceivers.
Tested according to SAE J2962-2.

6.4 Recommended Operating Conditions

4

MIN

NOM

MAX

UNIT

VCC

Supply voltage

4.5

5

5.5

V

VIO

Supply voltage for I/O level shifter

1.7

IOH(RXD)RXD terminal high-level output current, Devices with VIO–1.5

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5.5

V
mA

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6.4 Recommended Operating Conditions (continued)
MIN
IOL(RXD)RXD terminal low-level output current, Devices with VIOIOH(RXD)RXD terminal high-level output current, Devices without VIO

IOL(RXD)RXD terminal low-level output current, Devices without VIO

TJOperating junction temperature

NOM

MAX

UNIT

1.5

mA

–2

mA

-40

2

mA

150

℃

6.5 Thermal Characteristics
TCAN1044Ax-Q1

THERMAL METRIC(1)D (SOIC)DDF (SOT)UNIT

DRB (VSON)

RθJA

Junction-to-ambient thermal resistance

127.5

122

55.2

℃/W

RθJC(top)

Junction-to-case (top) thermal resistance

67.6

63

62.4

℃/W

RθJB

Junction-to-board thermal resistance

70.9

42.4

27.5

℃/W

ΨJT

Junction-to-top characterization parameter

19.3

2.4

2.3

℃/W

ΨJB

Junction-to-board characterization parameter

70.2

42.2

27.4

℃/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

--

--

11.5

℃/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.6 Supply Characteristics
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted)
PARAMETERTEST CONDITIONS

TYP

MAX

UNIT

STB = 0 V, TXD = 0 V
RL = 60 Ω, CL = open
See Figure 7-1

45

70

mA

STB = 0 V, TXD = 0 V
RL = 50 Ω, CL = open
See Figure 7-1

49

80

mA

Recessive

STB = 0 V, TXD = VCC or VIO
RL = 50 Ω, CL = open
See Figure 7-1

4.5

7.5

mA

Dominant withbus fault

STB = 0 V, TXD = 0 V
CANH = CANL = ±25 V
RL = open, CL = open
See Figure 7-1

130

mA

Supply current
Standby mode
Devices with VIO

STB = TXD = VIO
RL = 50 Ω, CL = open
See Figure 7-1

1.5

µA

Supply current
Standby mode
Devices without VIO

STB = TXD = VCC
RL = 50 Ω, CL = open
See Figure 7-1

15µA

Dominant

Supply current
Normal mode

ICC

IIO

I/O supply current
Normal mode

Dominant

STB = 0 V, TXD = 0 V
RXD floating

125

300

µA

I/O supply current
Normal mode

Recessive

STB = 0 V, TXD = 0 V
RXD floating

25

48

µA

STB = VIO, TXD = 0 V
RXD floating

8.5

14

µA

4.2

4.4

V

4

4.25

V

I/O supply current
Standby mode
UVCC
VHYS(UVCC)UVVIO
VHYS(UVIO)

MIN

Rising undervoltage detection on VCC for protected mode
Falling undervoltage detection on VCC for protected mode

3.5

Hysteresis voltage on UVCC

200

Rising undervoltage detection on VIO (Devices with VIO)

1.56

1.65

1.51

1.59

Falling undervoltage detection on VIO (Devices with VIO)
Hysteresis voltage on UVIO

1.4

40

mV
V
V
mV

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6.7 Dissipation Ratings
PARAMETERTEST CONDITIONS

Average power dissipation
Normal mode

PD

TTSD

Thermal shutdown temperature

TTSD(HYS)

Thermal shutdown hysteresis

MIN

TYP

MAX

UNIT

VCC = 5 V, VIO = 1.8 V, TJ = 27°C, RL = 60 Ω,
CL_RXD = 15 pF
TXD input = 250 kHz 50% duty cycle square
wave

95

mW

VCC = 5 V, VIO = 3.3 V, TJ = 27°C, RL = 60 Ω,
CL_RXD = 15 pF
TXD input = 250 kHz 50% duty cycle square
wave

95

mW

VCC = 5 V, VIO = 5 V, TJ = 27°C, RL = 60 Ω,
CL_RXD = 15 pF
TXD input = 250 kHz 50% duty cycle square
wave

95

mW

VCC = 5.5 V, VIO = 1.8 V, TJ = 150°C, RL = 60Ω,
CL_RXD = 15 pF
TXD input = 2.5 MHz 50% duty cycle square
wave

120

mW

VCC = 5.5 V, VIO = 3.3 V, TJ = 150°C, RL = 60 Ω,
CL_RXD = 15 pF
TXD input = 2.5 MHz 50% duty cycle square
wave

120

mW

VCC = 5.5 V, VIO = 5 V, TJ = 150°C, RL = 60 Ω,
CL_RXD = 15 pF
TXD input = 2.5 MHz 50% duty cycle square
wave

120

mW

175

195

210

°C

12

6.8 Electrical Characteristics
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX UNITSTB = 0 V, TXD = 0 V
50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open
See Figure 7-2 and Figure 8-3

2.75

4.5

V

0.5

2.25

V

3

V

0.9

1.1

V/V

Driver Electrical Characteristics
VO(DOM)

Dominant output voltage
Normal mode

VO(REC)

Recessive output voltage
Normal mode

CANL
CANH and CANLSTB = 0 V, TXD = VIO
RL = open (no load), RCM = open
See Figure 7-2 and Figure 8-3

2

0.5 VCC

VSYM

Driver symmetry(VO(CANH) + VO(CANL))/VCC

STB = 0 V, TXD = 250 kHz, 1 MHz, 2.5
MHz
RL = 60 Ω, CSPLIT = 4.7 nF, CL = open,
RCM = open
See Figure 7-2 and Figure 9-2

VSYM_DCDC output symmetry(VCC - VO(CANH) - VO(CANL))

STB = 0 V
RL = 60 Ω, CL = open
See Figure 7-2 and Figure 8-3

–400

400

mV

STB = 0 V, TXD = 0 V
50 Ω ≤ RL ≤ 65 Ω, CL = open
See Figure 7-2 and Figure 8-3

1.5

3

V

STB = 0 V, TXD = 0 V
45 Ω ≤ RL ≤ 70 Ω, CL = open
See Figure 7-2 and Figure 8-3

1.4

3.3

V

STB = 0 V, TXD = 0 V
RL = 2240 Ω, CL = open
See Figure 7-2 and Figure 8-3

1.5

5

V

STB = 0 V, TXD = VIO
RL = 60 Ω, CL = open
See Figure 7-2 and Figure 8-3

–120

12

mV

STB = 0 V, TXD = VIO
RL = open, CL = open
See Figure 7-2 and Figure 8-3

–50

50

mV

VOD(DOM)

VOD(REC)

6

CANH

Differential output voltage
Normal mode
Dominant

Differential output voltage
Normal mode
Recessive

CANH - CANLCANH - CANL

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6.8 Electrical Characteristics (continued)
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted)
PARAMETERTEST CONDITIONSCANHVO(STB)Bus output voltage
Standby mode

CANL
CANH - CANLIOS(SS_DOM)

IOS(SS_REC)

STB = VIO
RL = open
See Figure 7-2 and Figure 8-3
STB = 0 V, TXD = 0 V
V(CANH) = -15 V to 40 V, CANL = open
See Figure 7-7 and Figure 8-3

Short-circuit steady-state output current,
dominant
Normal mode

MIN

TYP

0.1

V

-0.1

0.1

V

-0.2

0.2

V

–115

mA

STB = 0 V, TXD = 0 V
V(CAN_L) = -15 V to 40 V, CANH = open
See Figure 7-7 and Figure 8-3

Short-circuit steady-state output current,
recessive
Normal mode

MAX UNIT

-0.1

115

mA

STB = 0 V, TXD = VIO–27 V ≤ VBUS ≤ 32 V, where VBUS = CANH
= CANL
See Figure 7-7 and Figure 8-3

–5

5

mA

Receiver Electrical Characteristics
VIT

Input threshold voltage
Normal mode

STB = 0 V
-12 V ≤ VCM ≤ 12 V
See Figure 7-3 and Table 8-6

500

900

mV

VIT(STB)

Input threshold
Standby mode

STB = VIO
-12 V ≤ VCM ≤ 12 V
See Figure 7-3 and Table 8-6

400

1150

mV

VDOM

Dominant state differential input voltage range
Normal mode

STB = 0 V
-12 V ≤ VCM ≤ 12 V
See Figure 7-3 and Table 8-6

0.9

9

V

VREC

Recessive state differential input voltage range
Normal mode

STB = 0 V
-12 V ≤ VCM ≤ 12 V
See Figure 7-3 and Table 8-6

-4

0.5

V

VDOM(STB)

Dominant state differential input voltage range
Standby mode

STB = VIO
-12 V ≤ VCM ≤ 12 V
See Figure 7-3 and Table 8-6

1.15

9

V

VREC(STB)

Recessive state differential input voltage range
Standby mode

STB = VIO
-12 V ≤ VCM ≤ 12 V
See Figure 7-3 and Table 8-6

-4

0.4

V

VHYS

Hysteresis voltage for input threshold
Normal mode

STB = 0 V
-12 V ≤ VCM ≤ 12 V
See Figure 7-3 and Table 8-6

VCM

Common-mode range
Normal and standby modes

See Figure 7-3 and Table 8-6

ILKG(IOFF)

Unpowered bus input leakage current

CANH = CANL = 5 V, VCC = VIO = GND

CIInput capacitance to ground (CANH or CANL)

CID

Differential input capacitance

RID

Differential input resistance

RIN

Single-ended input resistance(CANH or CANL)

RIN(M)

Input resistance matching[1 – (RIN(CANH) / RIN(CANL))] × 100 %

115

–12

TXD = VIO (1)STB = 0 V, TXD = VIO (1)-12 V ≤ VCM ≤ 12 V
V(CAN_H) = V(CAN_L) = 5 V

mV

12

V

5

µA

20

pF

10

pF

40

90

kΩ

20

45

kΩ

–1

1

%

TXD Terminal (CAN Transmit Data Input)
VIH

High-level input voltage

Devices without VIO

0.7 VCC

VIH

High-level input voltage

Devices with VIO

0.7 VIO

VIL

Low-level input voltage

Devices without VIO

0.3 VCC

VIL

Low-level input voltage

Devices with VIO

0.3 VIO

V

IIH

High-level input leakage current

TXD = VCC = VIO = 5.5 V

–2.5

0

1

µA

IIL

Low-level input leakage current

TXD = 0 V
VCC= VIO = 5.5 V

–200

-100

–20

µA

ILKG(OFF)

Unpowered leakage current

TXD = 5.5 V
VCC= VIO = 0 V

–1

0

1

µA

CI

Input capacitanceVIN= 0.4×sin(2×π×2×106×t)+2.5 V

V
V

5

V

pF

RXD Terminal (CAN Receive Data Output)

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6.8 Electrical Characteristics (continued)
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX UNIT

VOH

High-level output voltage

IO = –2 mA
Devices without VIO
See Figure 7-3

VOH

High-level output voltage

IO = –1.5 mA
Devices with VIO
See Figure 7-3

VOL

Low-level output voltage

IO = 2 mA
Devices without VIO
See Figure 7-3

0.2 VCC

V

VOL

Low-level output voltage

IO = 1.5mA
Devices with VIO
See Figure 7-3

0.2 VIOV

ILKG(OFF)

Unpowered leakage current

RXD = 5.5 V
VCC = VIO = 0 V

1µA

0.8 VCCV

0.8 VIOV–10

STB Terminal (Standby Mode Input)
VIH

High-level input voltage

Devices without VIO

0.7 VCC

VIH

High-level input voltage

Devices with VIO

0.7 VIO

VIL

Low-level input voltage

Devices without VIO

0.3 VCCV

VIL

Low-level input voltage

Devices with VIO

0.3 VIO

V

IIH

High-level input leakage current

VCC = VIO = STB = 5.5 V

–2

2

µA

IIL

Low-level input leakage current

STB = 0 V
VCC = VIO = 5.5 V,

–20

–2

µA

ILKG(OFF)

Unpowered leakage current

STB = 5.5V
VCC = VIO = 0 V

–1

1

µA

(1)

V
V

0

VIO = VCC in non-V variants of device

6.9 Switching Characteristics
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted).
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

Device Switching Characteristics
tPROP(LOOP1)

Total loop delay
Driver input (TXD) to receiver output (RXD),
recessive to dominant

STB = 0 V, VIO = 2.8 V to 5.5 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
See Figure 7-4

125

210

ns

tPROP(LOOP1)

Total loop delay
Driver input (TXD) to receiver output (RXD),
recessive to dominant

STB = 0 V, VIO = 1.7 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
See Figure 7-4

165

255

ns

tPROP(LOOP2)

Total loop delay
Driver input (TXD) to receiver output (RXD),
dominant to recessive

STB = 0 V, VIO = 2.8 V to 5.5 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
See Figure 7-4

150

210

ns

tPROP(LOOP2)

Total loop delay
Driver input (TXD) to receiver output (RXD),
dominant to recessive

STB = 0 V, VIO = 1.7 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
See Figure 7-4

180

255

ns

tMODE

Mode change time, from normal to standby or fromstandby to normal

See Figure 7-520µs

tWK_FILTER

Filter time for a valid wake-up pattern

0.5

1.8

µs

tWK_TIMEOUT

Bus wake-up timeout

0.8

6

ms

See Figure 8-5

Driver Switching Characteristics
Propagation delay time, high TXD to driverrecessive (dominant to recessive)

tpHR

ns

70

ns

tsk(p)

Propagation delay time, low TXD to driver dominant
STB = 0 V
(recessive to dominant)
RL = 60 Ω, CL = 100 pF
Pulse skew (|tpHR - tpLD|)
See Figure 7-2

14

ns

tR

Differential output signal rise time

28

ns

tF

Differential output signal fall time50

tTXD_DTO

Dominant timeout

tpLD

8

80

See Figure 7-6

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ns
4.0

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6.9 Switching Characteristics (continued)
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted).
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

Receiver Switching Characteristics
tpRH

Propagation delay time, bus recessive input to highoutput (dominant to recessive)

tpDL

Propagation delay time, bus dominant input to low
output (recessive to dominant)tR

RXD output signal rise timetF

RXD output signal fall time

STB = 0 V
CL(RXD) = 15 pF
See Figure 7-3

81

ns

66

ns

10

ns

10

ns

FD Timing CharacteristicstBIT(BUS)

Bit time on CAN bus output pinstBIT(TXD) = 500 ns

450

525

ns

Bit time on CAN bus output pinstBIT(TXD) = 200 ns

160

205

ns

Bit time on CAN bus output pinstBIT(TXD) = 125 ns(1)

85

130

ns

410

540

ns

130

210

ns

75

135

ns

Receiver timing symmetrytBIT(TXD) = 500 ns

-50

20

ns

Receiver timing symmetrytBIT(TXD) = 200 ns

-40

10

ns

Receiver timing symmetrytBIT(TXD) = 125 ns(1)

-40

10

ns

Bit time on RXD output pinstBIT(TXD) = 500 ns
tBIT(RXD)

Bit time on RXD output pinstBIT(TXD) = 200 ns
Bit time on RXD output pinstBIT(TXD) = 125 ns(1)

ΔtREC

(1)

STB = 0 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 7-4

Measured during characterization and not an ISO 11898-2:2016 parameter.

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6.10 Typical Characteristics
2.5

3

2.3

VOD(DOM) (V)VOD(DOM) (V)

2.5
2.1

1.9

2

1.5
1.7

1.5
-40

-20

0

VCC = 5 V

20

40
60
80 100Temperature (°C)

VIO = 3.3 V

120

140

160

RL = 60 Ω

1
4.5

4.6

VIO = 3.3 V

RL = 60 Ω

Figure 6-3. ICC Standby vs Temperature

10

4.8

4.9

5
5.1
VCC (V)

5.2

Temp = 25°C

Figure 6-1. VOD(DOM) vs Temperature

VCC = 5 V

4.7

5.3

5.4

5.5

RL = 60 Ω

Figure 6-2. VOD(DOM) vs VCC

VCC = 5 V

VIO = 3.3 V

RL = 60 Ω

Figure 6-4. IIO Standby vs Temperature

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7 Parameter Measurement Information
CANH

TXD
CL

RL

CANL

Figure 7-1. ICC Test Circuit
RCM

CANH

50%

TXD

50%

TXD
RL

CL

VOD

VCM

VCC

VO(CANH)

tpHR

tpLD

CANL

90%

RCM

0V

0.9V

VO(CANL)

VOD
0.5V

10%

tR

tF

Figure 7-2. Driver Test Circuit and Measurement
CANH

1.5V
0.9V
VID

IO

RXD

0.5V
0V

VID
tpD L

CANL

CL_ RXD

tpR H

VOH

VO

90%
VO(RXD )
50%
10%
VOL
tR

tF

Figure 7-3. Receiver Test Circuit and Measurement

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TXD

VI
70%
tLOOP1
30%

30%

CANH

0V
VI

TXD

RL

CL

tBIT(TXD)

5 x tBIT(TXD)

CANLtBIT(BUS)

0 V STB

900 mVRXD+

500 mVVDIFF
CL_RXD

VO

±

RXD

VOH
70%

30%
VOL

tBIT(RXD)tLOOP2

Figure 7-4. Transmitter and Receiver Timing Test Circuit and Measurement
CANH

0V

TXD

VIH
CL

RL

CANL
VI

STB

50%

STB
0V
tMODE

RXD
VOH

VO

CL_RXD

RXD

50%

VOL

Figure 7-5. tMODE Test Circuit and Measurement

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VIH

CANH
TXD
TXD

CL

RL

0V

VOD

VOD(D)

CANL
0.9V
VOD
0.5V

0V
tTXD_DTO

Figure 7-6. TXD Dominant Timeout Test Circuit and Measurement

CANH

200 s

IOS

TXD
VBUS

IOS
CANL

VBUS

VBUS

0V

or
0V
VBUS

VBUS

Figure 7-7. Driver Short-Circuit Current Test and Measurement

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8 Detailed Description
8.1 Overview
The TCAN1044A(V)-Q1 devices meet or exceed the specifications of the ISO 11898-2:2016 high speed CAN(Controller Area Network) physical layer standard. The devices have been certified to the requirements of ISO
11898-2:2016 physical layer requirements according to the GIFT/ICT high speed CAN test specification. The
transceivers provide a number of different protection features for the stringent automotive system requirements
while also supporting CAN FD data rates up to 8Mbps.
The TCAN1044A(V)-Q1 support the following CAN and CAN FD standards:
•

•

•

14

Physical layer:– ISO 11898-2:2016 High speed medium access unit
– ISO 11898-5:2007 High speed medium access unit with low-power mode
– SAE J2284-1: High Speed CAN (HSC) for Vehicle Applications at 125kbps– SAE J2284-2: High Speed CAN (HSC) for Vehicle Applications at 250kbps– SAE J2284-3: High Speed CAN (HSC) for Vehicle Applications at 500kbps– SAE J2284-4: High-Speed CAN (HSC) for Vehicle Applications at 500kbps with CAN FD Data at 2Mbps– SAE J2284-5: High-Speed CAN (HSC) for Vehicle Applications at 500kbps with CAN FD Data at 5Mbps
EMC Requirements– IEC 62228-3 EMC evaluation of transceivers - CAN transceivers– VeLIO (Vehicle LAN Interoperability and Optimization) CAN and CAN-FD Transceiver Requirements– SAE J2962-2 Communication Transceivers Qualification Requirements – CAN
Conformance test requirements:– ISO 16845-2 Road vehicles – Controller area network (CAN) conformance test plan Part 2: High-speed
medium access unit conformance test plan

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8.2 Functional Block Diagram

Figure 8-1. Block Diagram

8.3 Feature Description
8.3.1 Pin Description
8.3.1.1 TXDThe TXD input is a logic-level signal, referenced to either VCC or VIO from a CAN controller to the transceiver.
8.3.1.2 GND

GND is the ground pin of the transceiver. The pin must be connected to the PCB ground.
8.3.1.3 VCC

VCC provides the 5-V power supply to the CAN transceiver.
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8.3.1.4 RXD

RXD is the logic-level signal, referenced to either VCC or VIO, from the TCAN1044A-Q1 to a CAN controller. Thispin is only driven once VIO is present.
8.3.1.5 VIO

The VIO pin provides the digital I/O voltage to match the CAN controller voltage thus avoiding the requirement fora level shifter. It supports voltages from 1.7 V to 5.5 V providing the widest range of controller support.
8.3.1.6 CANH and CANLThe CANH and CANL pins are the CAN high and CAN low differential bus pins. These pins are internallyconnected to the CAN transmitter, receiver and the low-power wake-up receiver.
8.3.1.7 STB (Standby)

The STB pin is an input pin used for mode control of the transceiver. The STB pin can be supplied from either
the system processor or from a static system voltage source. If normal mode is the only intended mode ofoperation, the STB pin can be tied directly to GND.
8.3.2 CAN Bus States
The CAN bus has two logical states during operation: recessive and dominant. See Figure 8-2 and Figure 8-3.
A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD and
RXD pins. A recessive bus state occurs when the bus is biased to VCC/2 via the high-resistance internal input
resistors (RIN) of the receiver and corresponds to a logic high on the TXD and RXD pins.
A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting adominant bit at the same time during arbitration, and in this case the differential voltage of the bus is greater thanthe differential voltage of a single driver.
The TCAN1044A(V)-Q1 transceiver implements a low-power standby (STB) mode which enables a third bus
state where the bus pins are weakly biased to ground via the high resistance internal resistors of the receiver.
See Figure 8-2 and Figure 8-3.

Normal Mode

Standby Mode

Typical Bus Voltage

CANH

VDIFF

VDIFF
CANL

Recessive

Dominant

Recessive

Time, tFigure 8-2. Bus States

16

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CANH
2.5V

A
RXD

Bias
Unit

B
GND

CANL

A.

A - Normal Mode B - Standby Mode

Figure 8-3. Simplified Recessive Common Mode Bias Unit and Receiver
8.3.3 TXD Dominant Timeout (DTO)
During normal mode, the only mode where the CAN driver is active, the TXD DTO circuit prevents the local nodefrom blocking network communication in the event of a hardware or software failure where TXD is held dominant
longer than the timeout period tTXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If no risingedge is seen before the timeout period of the circuit, tTXD_DTO, the CAN driver is disabled. This frees the bus forcommunication between other nodes on the network. The CAN driver is reactivated when a recessive signal isseen on the TXD pin, thus clearing the dominant time out. The receiver remains active and biased to VCC/2 andthe RXD output reflects the activity on the CAN bus during the TXD DTO fault.
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted data
rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the
worst case, where five successive dominant bits are followed immediately by an error frame. The minimumtransmitted data rate may be calculated using Equation 1.
(1)

Minimum Data Rate = 11 bits / tTXD_DTO = 11 bits / 1.2 ms = 9.2 kbps
TXD fault stuck dominant: example PCB failure or bad softwaretTXD_DTO

TXD (driver)

Normal CAN communication

CAN Bus Signal

Fault is repaired & transmission capability
restored

Driver disabled freeing bus for other nodes%XV ZRXOG EH ³VWXFN GRPLQDQW´ EORFNLQJ FRPPXQLFDWLRQ IRU WKH ZKROH QHWZRUN EXW 7;' '72
prevents this and frees the bus for communication after the time tTXD_DTO.

tTXD_DTO

Communication from other bus node(s)Communication from repaired node

RXD (receiver)

Communication from local node

Communication from other bus node(s)Communication from repaired local node

Figure 8-4. Example Timing Diagram for TXD Dominant Timeout
8.3.4 CAN Bus short-circuit current limiting
The TCAN1044A(V)-Q1 has several protection features that limit the short-circuit current when a CAN bus line
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state timeout which prevents permanently having the higher short-circuit current of a dominant state in case ofa system fault. During CAN communication the bus switches between the dominant and recessive states, thus
the short-circuit current may be viewed as either the current during each bus state or as a DC average current.
When selecting termination resistors or a common-mode choke for the CAN design the average power rating,
IOS(AVG), should be used. The percentage dominant is limited by the TXD DTO and the CAN protocol which has
forced state changes and recessive bits due to bit stuffing, control fields, and interframe space. These ensure
there is a minimum amount of recessive time on the bus even if the data field contains a high percentage ofdominant bits.
The average short-circuit current of the bus depends on the ratio of recessive to dominant bits and theirrespective short-circuit currents. The average short-circuit current may be calculated using Equation 2.
IOS(AVG) = % Transmit x [(% REC_Bits x IOS(SS)_REC) + (% DOM_Bits x IOS(SS)_DOM)] + [% Receive x IOS(SS)_REC](2)

Where:• IOS(AVG) is the average short-circuit current• % Transmit is the percentage the node is transmitting CAN messages• % Receive is the percentage the node is receiving CAN messages• % REC_Bits is the percentage of recessive bits in the transmitted CAN messages• % DOM_Bits is the percentage of dominant bits in the transmitted CAN messages• IOS(SS)_REC is the recessive steady state short-circuit current• IOS(SS)_DOM is the dominant steady state short-circuit current
This short circuit current and the possible fault cases of the network should be taken into consideration whensizing the power supply used to generate the transceivers VCC supply.
8.3.5 Thermal Shutdown (TSD)
If the junction temperature of the TCAN1044A(V)-Q1 exceeds the thermal shutdown threshold, TTSD, the device
turns off the CAN driver circuitry and blocks the TXD to bus transmission path. The shutdown condition iscleared when the junction temperature of the device drops below TTSD. The CAN bus pins are biased to VCC/2
during a TSD fault and the receiver to RXD path remains operational. The TCAN1044A(V)-Q1 TSD circuit
includes hysteresis which prevents the CAN driver output from oscillating during a TSD fault.
8.3.6 Undervoltage Lockout
The supply pins, VCC and VIO, have undervoltage detection that places the device into a protected state. This
protects the bus during an undervoltage event on either supply pin.
Table 8-1. Undervoltage Lockout - TCAN1044A-Q1
VCC

DEVICE STATE

BUS

RXD PIN> UVVCC

NormalPer TXD

Mirrors bus< UVVCC

Protected

High impedanceHigh impedance

Table 8-2. Undervoltage Lockout - TCAN1044AV-Q1

18

VCC

VIO

DEVICE STATE

BUS

RXD PIN> UVVCC> UVVIO

NormalPer TXD

Mirrors bus< UVVCC> UVVIO

STB = High: Standby Mode

Weak biased to GND

VIO: Remote wake request
See Remote Wake Request via
Wake-Up Pattern (WUP) in Standby
Mode

STB =Low: Protected ModeHigh impedanceRecessive> UVVCC< UVVIO

Protected

High impedanceHigh impedance< UVVCC< UVVIO

Protected

High impedanceHigh impedance

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Once the undervoltage condition is cleared and tMODE has expired the TCAN1044A-Q1 will transition to normal
mode and the host controller can send and receive CAN traffic again
8.3.7 Unpowered Device
The TCAN1044A(V)-Q1 is designed to be a passive or no load to the CAN bus if the device is unpowered. The
bus pins were designed to have low leakage currents when the device is unpowered, so the pins do not load
the bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains
operational.
The logic pins also have low leakage currents when the device is unpowered, so the pins do not load othercircuits which may remain powered.
8.3.8 Floating pins
The TCAN1044A(V)-Q1 has internal pull-ups on critical pins which place the device into known states if thepin floats. This internal bias should not be relied upon by design though, especially in noisy environments, butinstead should be considered a failsafe protection feature.
When a CAN controller supporting open-drain outputs is used an adequate external pull-up resistor must be
chosen. This ensures that the TXD output of the CAN controller maintains acceptable bit time to the input of the
CAN transceiver. See Table 8-3 for details on pin bias conditions.
Table 8-3. Pin Bias
Pin

Pull-up or Pull-downComment

TXD

Pull-up

Weakly biases TXD towards recessive to prevent bus blockage or
TXD DTO triggering

STB

Pull-up

Weakly biases STB towards low-power standby mode to prevent
excessive system power

8.4 Device Functional Modes
8.4.1 Operating Modes
The TCAN1044A(V)-Q1 has two main operating modes; normal mode and standby mode. Operating mode
selection is made by applying a high or low level to the STB pin.
Table 8-4. Operating Modes
STB

Device Mode

DriverReceiverRXD PinHigh

Low current standby mode withbus wake-up

Disabled

Low-power receiver and bus
monitor enable

High (recessive) until valid WUP
is received
See Remote Wake Request
via Wake-Up Pattern (WUP) in
Standby Mode

Low

Normal Mode

EnabledEnabledMirrors bus state

8.4.2 Normal Mode
This is the normal operating mode of the TCAN1044A(V)-Q1. The CAN driver and receiver are fully operationaland CAN communication is bi-directional.
The driver is translating a digital input on the TXD input to a differential output on the CANH and CANL bus pins.
The receiver is translating the differential signal from CANH and CANL to a digital output on the RXD output.
8.4.3 Standby Mode
This is the low-power mode of the TCAN1044A(V)-Q1. The CAN driver and main receiver are switched off andbi-directional CAN communication is not possible. The low-power receiver and bus monitor circuits are enabled
to allow for RXD wake-up requests via the CAN bus. A wake-up request is output to RXD as shown in Figure8-5. The local CAN protocol controller should monitor RXD for transitions (high-to-low) and reactivate the device

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to normal mode by pulling the STB pin low. The CAN bus pins are weakly pulled to GND in this mode; see
Figure 8-2 and Figure 8-3.
In standby mode, only the VIO supply is required therefore the VCC may be switched off for additional systemlevel current savings.
8.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode

The TCAN1044A(V)-Q1 supports a remote wake-up request that is used to indicate to the host controller that thebus is active and the node should return to normal operation.
The device uses the multiple filtered dominant wake-up pattern (WUP) from the ISO 11898-2:2016 standard toqualify bus activity. Once a valid WUP has been received, the wake request is indicated to the controller by afalling edge and low period corresponding to a filtered dominant on the RXD output of the TCAN1044A(V)-Q1.
The WUP consists of a filtered dominant pulse, followed by a filtered recessive pulse, and finally by a second
filtered dominant pulse. The first filtered dominant initiates the WUP, and the bus monitor then waits on a filtered
recessive; other bus traffic does not reset the bus monitor. Once a filtered recessive is received the bus monitor
is waiting for a filtered dominant and again, other bus traffic does not reset the bus monitor. Immediately upon
reception of the second filtered dominant the bus monitor recognizes the WUP and drives the RXD output low
every time an additional filtered dominant signal is received from the bus.
For a dominant or recessive to be considered filtered, the bus must be in that state for more than thetWK_FILTER time. Due to variability in tWK_FILTER the following scenarios are applicable. Bus state times less thantWK_FILTER(MIN) are never detected as part of a WUP and thus no wake request is generated. Bus state times
between tWK_FILTER(MIN) and tWK_FILTER(MAX) may be detected as part of a WUP and a wake-up request may begenerated. Bus state times greater than tWK_FILTER(MAX) are always detected as part of a WUP, and thus a wakerequest is always generated. See Figure 8-5 for the timing diagram of the wake-up pattern.
The pattern and tWK_FILTER time used for the WUP prevents noise and bus stuck dominant faults from causing
false wake-up requests while allowing any valid message to initiate a wake-up request.
The ISO 11898-2:2016 standard has defined times for a short and long wake-up filter time. The tWK_FILTER timing
for the device has been picked to be within the minimum and maximum values of both filter ranges. This timing
has been chosen such that a single bit time at 500 kbps, or two back-to-back bit times at 1 Mbps triggers thefilter in either bus state. Any CAN frame at 500 kbps or less would contain a valid WUP.
For an additional layer of robustness and to prevent false wake-ups, the device implements a wake-up timeout
feature. For a remote wake-up event to successfully occur, the entire WUP must be received within the timeout
value t ≤ tWK_TIMEOUT. If not, the internal logic is reset and the transceiver remains in its current state without
waking up. The full pattern must then be transmitted again, conforming to the constraints mentioned in thissection. See Figure 8-5 for the timing diagram of the wake-up pattern with wake timeout feature.

20

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Bus Wake via RXD
RequestWake Up Pattern (WUP) received in t < tWK_Timeout
Filtered
Dominant

Filtered
Recessive

Waiting for
Filtered
Recessive

Filtered
Dominant

Waiting for
Filtered
DominantBusBus VDiff• tWK_FILTER• tWK_FILTER• tWK_FILTER• tWK_FILTER

RXD

Filtered Dominant RXD Output

Bus Wake Via RXD Requests

Figure 8-5. Wake-Up Pattern (WUP) with tWK_TIMEOUT
8.4.4 Driver and Receiver Function
The TCAN1044A-Q1 logic I/Os support CMOS levels with respect to either VCC for 5V systems (TCAN1044AQ1) or VIO for compatibility with MCUs that support 1.8V, 2.5V, 3.3V, or 5V systems (TCAN1044AV-Q1).
Table 8-5. Driver Function Table
Device Mode
NormalStandby(1)(2)

Bus Outputs

TXD Input(1)CANH

Driven Bus State(2)

CANL

Low

High

Low

Dominant

High or open

High impedanceHigh impedance

Biased recessive

X

High impedanceHigh impedance

Biased to ground

X = irrelevant
For bus state and bias see Figure 8-2 and Figure 8-3

Table 8-6. Receiver Function Table Normal and Standby Mode
Device ModeCAN Differential Inputs VID = VCANH – VCANLBus State

RXD Pin

VID ≥ 0.9V

Dominant

Low

0.5V < VID < 0.9V

Undefined

Undefined

VID ≤ 0.5V

RecessiveHigh

VID ≥ 1.15V

Dominant

NormalStandbyAny

0.4V < VID < 1.15V

Undefined

VID ≤ 0.4V

RecessiveHigh
Low if a remote wake event
occurredSee Figure 8-5Open (VID ≈ 0V)

Open

High

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9 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible fordetermining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information
9.2 Typical Application
The TCAN1044A(V)-Q1 transceiver can be used in applications with a host controller or FPGA that includes thelink layer portion of the CAN protocol. Figure 9-1 shows a typical configuration for 5V controller applications. The
bus termination is shown for illustrative purposes.
VIN

VIN

VOUT

5-V Voltage
Regulator

3

5

VCC

VDD
Port x

8

NC
CANH

7

STB

MCU

TCAN1044A

RXD
CAN FD
Controller
TXD

4
1

RXD
TXD

GND

CANL

6

Optional:
Terminating Node

Optional: Filtering,Transient and ESD

Figure 9-1. Transceiver Application Using 5V IO Connections
9.2.1 Design Requirements
9.2.1.1 CAN Termination

Termination may be a single 120Ω resistor at each end of the bus, either on the cable or in a terminating node.
If filtering and stabilization of the common-mode voltage of the bus is desired then split termination may be used,
see Figure 9-2. Split termination improves the electromagnetic emissions behavior of the network by filtering
higher-frequency common-mode noise that may be present on the differential signal lines.

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Standard Termination

Split Termination

CANH

CANH

RTERM/2

TCAN Transceiver

RTERM

TCAN Transceiver
CSPLIT
RTERM/2

CANL

CANL

Figure 9-2. CAN Bus Termination Concepts
9.2.2 Detailed Design Procedures
9.2.2.1 Bus Loading, Length and Number of Nodes

A typical CAN application may have a maximum bus length of 40 meters and maximum stub length of 0.3m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to abus. A high number of nodes requires a transceiver with high input impedance such as the TCAN1044A(V)-Q1
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2 standard. They made system level trade off decisions for data rate, cable length, and parasitic loadingof the bus. Examples of these CAN systems level specifications are ARINC 825, CANopen, DeviceNet, SAE
J2284, SAE J1939, and NMEA 2000.
A CAN network system design is a series of tradeoffs. In the ISO 11898-2:2016 specification the driverdifferential output is specified with a bus load that can range from 50Ω to 65Ω where the differential output
must be greater than 1.5V. The TCAN1044A(V)-Q1 family is specified to meet the 1.5V requirement down to50Ω and is specified to meet 1.4V differential output at 45Ω bus load. The differential input resistance of theTCAN1044A(V)-Q1 is a minimum of 40kΩ. If 100 TCAN1044A(V)-Q1 transceivers are in parallel on a bus, thisis equivalent to a 400-Ω differential load in parallel with the nominal 60Ω bus termination which gives a total bus
load of approximately 52Ω. Therefore, the TCAN1044A(V)-Q1 family theoretically supports over 100 transceivers
on a single bus segment. However, for a CAN network design margin must be given for signal loss across thesystem and cabling, parasitic loadings, timing, network imbalances, ground offsets, and signal integrity. Thusa practical maximum number of nodes is often lower. Bus length may also be extended beyond 40 meters
by careful system design and data rate tradeoffs. For example, CANopen network design guidelines allow the
network to be up to 1km with changes in the termination resistance, cabling, less than 64 nodes and significantly
lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. However, when using this flexibility
the CAN network system designer must take the responsibility of good network design to ensure robust network
operation.
Please refer to the application report SLLA270: Controller Area Network Physical layer requirements. This
document discusses in detail all system design physical layer parameters.

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Node 1

Node 2

Node 3

Node n(with termination)

System Controller

System Controller

System Controller

CAN FD
Controller

CAN FD
Controller

CAN FD
Controller

TCAN1044A-Q1

TCAN1044AV-Q1

TCAN1044A-Q1

System Controller

CAN FD
Controller

TCAN1043-Q1

RTERM

RTERM

Figure 9-3. Typical CAN Bus

9.3 System Examples
The TCAN1044AV-Q1 CAN transceiver is typically used in applications with a host controller or FPGA that
includes the link layer portion of the CAN protocol. A 1.8V, 2.5V, or 3.3V application is shown in Figure 9-4. The
bus termination is shown for illustrative purposes.
VBAT

VIN

VOUT

5-V Voltage
Regula tor

3
VCC

VDD
Por t x

8

CANH
STB

MCU

VIN

1.8 V / 2.5 V / 3.3 V
Regula tor

RXD
CAN FD
Controller
TXD

7

TCA N1 044AV

4
RXD
1
TXD

VIO

GND

CANL

6

5

VOUT

Optiona l:
Terminating Node

Optiona l: Filte ring,Transient a nd ESD

Figure 9-4. Typical Transceiver Application Using 1.8V, 2.5V, 3.3V IO Connections

9.4 Power Supply Recommendations
The TCAN1044A-Q1 transceiver is designed to operate with a main VCC input voltage supply range between
4.5V and 5.5V.
The TCAN1044AV-Q1 implements an IO level shifting supply input, VIO, designed for a range between 1.8V and
5.5V.
Both the VCC and VIO inputs must be well regulated. In addition to the power supply filtering a decoupling
capacitance, typically 100nF, should be placed near the CAN transceiver's main VCC and VIO supply pins.

24

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9.5 Layout
Robust and reliable CAN node design may require special layout techniques depending on the applicationand design requirements. Since transient disturbances have high frequency content and a wide bandwidth,
high-frequency layout techniques should be applied during PCB design.
9.5.1 Layout Guidelines
•

•
•
•

Place the protection and filtering circuitry close to the bus connector, J1, to prevent transients, ESD, andnoise from propagating onto the board. This layout example shows a optional transient voltage suppression(TVS) diode, D1, which may be implemented if the system-level requirements exceed the specified rating of
the transceiver. This example also shows optional bus filter capacitors C4 and C5.
Design the bus protection components in the direction of the signal path. Do not force the transient current todivert from the signal path to reach the protection device.
Decoupling capacitors should be placed as close as possible to the supply pins VCC and VIO of transceiver.
Use at least two vias for supply and ground connections of bypass capacitors and protection devices tominimize trace and via inductance.
Note
High-frequency current follows the path of least impedance and not the path of least resistance.

•

This layout example shows how split termination could be implemented on the CAN node. The terminationis split into two resistors, R2 and R3, with the center or split tap of the termination connected to groundvia capacitor C3. Split termination provides common mode filtering for the bus. See Section 9.2.1.1, Section
8.3.4, and Equation 2 for information on termination concepts and power ratings needed for the termination
resistor(s).

9.5.2 Layout Example
µC V

TXD

R1

STB

C4
STB

GND

CANH

VCC

CANL

RXD

VIO

R2

GND

C3
C1

VCC

GND

Choke

µC V
C2

D1

J1

R3
C5

Figure 9-5. Layout Example

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10 Device and Documentation Support
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For changedetails, review the revision history included in any revised document.

10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straightfrom the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.

10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handledwith appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.

10.5 Glossary
TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

11 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2021) to Revision D (October 2024)
Page• Deleted part number TCAN1044AV-Q1 from the data sheet title and header information................................. 1• Changed the Device Information table to the Package Information table.......................................................... 1

Changes from Revision B (October 2021) to Revision C (December 2021)
Page• Changed ICC (mA) to ICC (µA) in Figure 6-3 .................................................................................................... 10• Changed IIO (mA) to IIO (µA) in Figure 6-4 ...................................................................................................... 10

Changes from Revision A (July 2021) to Revision B (October 2021)
Page• Deleted Product Preview from the D and DDF packages in the Device Information table.................................1

Changes from Revision * (February 2021) to Revision A (July 2021)
Page• Changed the document status from: Advanced Information to: Production data............................................... 1

26

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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM
www.ti.com

17-Oct-2024

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking(3)

Samples

(4/5)

(6)

TCAN1044ADDFRQ1ACTIVE

SOT-23-THIN

DDF

8

3000

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 150

2HGF

Samples

TCAN1044ADRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 150

1044A

Samples

TCAN1044ADRQ1ACTIVE

SOIC

D

8

2500

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 150

1044A

Samples

TCAN1044AVDDFRQ1ACTIVE

SOT-23-THIN

DDF

8

3000

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 150

2HHF

Samples

TCAN1044AVDRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 150

1044AV

Samples

TCAN1044AVDRQ1ACTIVE

SOIC

D

8

2500

RoHS & Green

NIPDAU

Level-1-260C-UNLIM-40 to 150

1044AV

Samples(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Addendum-Page 1

PACKAGE OPTION ADDENDUM
www.ti.com

17-Oct-2024

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

18-Oct-2024

TAPE AND REEL INFORMATIONREEL DIMENSIONSTAPE DIMENSIONS
K0

P1

B0 W
Reel
DiameterCavity
A0
B0
K0
W
P1

A0

Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers

Reel Width (W1)QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes

Q1

Q2

Q1

Q2

Q3

Q4

Q3

Q4

User Direction of Feed

Pocket Quadrants*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

TCAN1044ADDFRQ1

SOT-23THIN

DDF

8

3000

180.0

8.4

3.2

3.2

1.4

4.0

8.0

Q3

TCAN1044ADRBRQ1

SON

DRB

8

3000

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q1

TCAN1044ADRQ1

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

TCAN1044AVDDFRQ1

SOT-23THIN

DDF

8

3000

180.0

8.4

3.2

3.2

1.4

4.0

8.0

Q3

TCAN1044AVDRBRQ1

SON

DRB

8

3000

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q1

TCAN1044AVDRQ1

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

18-Oct-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)

W

L

H

*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)TCAN1044ADDFRQ1
TCAN1044ADRBRQ1

SOT-23-THIN

DDF

8

3000

210.0

185.0

35.0

SON

DRB

8

3000

367.0

367.0

35.0

TCAN1044ADRQ1

SOIC

D

8

2500

356.0

356.0

35.0

TCAN1044AVDDFRQ1

SOT-23-THIN

DDF

8

3000

210.0

185.0

35.0

TCAN1044AVDRBRQ1

SON

DRB

8

3000

367.0

367.0

35.0

TCAN1044AVDRQ1

SOIC

D

8

2500

356.0

356.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

DDF0008A

SOT-23-THIN - 1.1 mm max height
SCALE 4.000

PLASTIC SMALL OUTLINE

C
2.95
TYP
2.65

SEATING PLANE

PIN 1 ID
AREA

A

0.1 C

6X 0.65
8

1

2.95
2.85
NOTE 32X
1.95

4X 0 -15

4
5

0.38
0.22
0.1
C A B
8X

B

1.65
1.55

1.1
MAX
4X 4 -15

0.20
TYP
0.08

SEE DETAIL A
0.25
GAGE PLANE

0 -8

0.1
0.0

0.6
0.3

DETAIL A
TYPICAL
4222047/E 07/2024

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DDF0008A

SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

8X (1.05)

SYMM
1
8

8X (0.45)
SYMM

6X (0.65)
5

4(R0.05)TYP(2.6)

LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:15X

SOLDER MASKOPENING

0.05 MAXALL AROUNDMETALEXPOSEDMETALMETAL UNDERSOLDER MASKSOLDER MASKOPENING

0.05 MIN
ALL AROUNDEXPOSEDMETALSOLDER MASKDEFINEDNON SOLDER MASKDEFINEDSOLDER MASK DETAILS

4222047/E 07/2024

NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DDF0008A

SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

8X (1.05)

SYMM(R0.05) TYP

1
8
8X (0.45)

SYMM

6X (0.65)
5

4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCILSCALE:15X

4222047/E 07/2024

NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

D0008ASOIC - 1.75 mm max height
SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUITCSEATING PLANE.228-.244 TYP[5.80-6.19]
A.004 [0.1] C

PIN 1 ID AREA
6X .050[1.27]
8

1

2X
.150
[3.81].189-.197[4.81-5.00]
NOTE 3

4X (0 -15 )4
5
B

8X .012-.020[0.31-0.51].010 [0.25]
C A B.150-.157[3.81-3.98]
NOTE 4.069 MAX[1.75].005-.010 TYP[0.13-0.25]

4X (0 -15 )SEE DETAIL A.010[0.25].004-.010[0.11-0.25]

0 -8.016-.050[0.41-1.27]

DETAIL A(.041)[1.04]TYPICAL

4214825/C 02/2019

NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008ASOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )[1.55]SYMM

SEE
DETAILS

1
8
8X (.024)[0.6]

6X (.050 )[1.27]

SYMM

5

4(R.002 ) TYP[0.05](.213)[5.4]

LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:8X

METAL

SOLDER MASKOPENINGEXPOSED
METAL.0028 MAX
[0.07]ALL AROUNDSOLDER MASKOPENINGMETAL UNDERSOLDER MASKEXPOSED
METAL.0028 MIN
[0.07]ALL AROUNDSOLDER MASKDEFINEDNON SOLDER MASKDEFINEDSOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008ASOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )[1.55]SYMM
1
88X (.024)[0.6]

6X (.050 )[1.27]

SYMM

5

4(R.002 ) TYP[0.05](.213)[5.4]

SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCILSCALE:8X

4214825/C 02/2019

NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE
VSON - 1 mm max height

DRB0008J

PLASTIC QUAD FLAT PACK- NO LEAD

3.1
2.9

B

A

PIN 1 INDEX AREA

3.1
2.9
0.1 MIN(0.13)SECTION A-A
TYPICAL

1 MAX

C
SEATING PLANE

0.05
0.00

0.08 C
1.75
1.55(0.2) TYP

6X 0.65(0.19)
5

4

SYMM

9

2.5
2.3

1
PIN 1 ID
(OPTIONAL)

8SYMM
8X 0.50.3

1.95

8X 0.36
0.26
0.1
0.05

C A B
C

4225036/A 06/2019

NOTES:
1.
2.
3.

All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT
VSON - 1 mm max height

DRB0008J

PLASTIC QUAD FLAT PACK- NO LEAD

(2.8)
(1.65)
8X (0.6)
8X (0.31)

SYMM
1

8

6X (0.65)
SYMM

9(1.95) (2.4)(0.95)(R0.05) TYP
45(Ø 0.2) VIA
TYP(0.575)LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 20X

0.07 MAXALL AROUNDMETALEXPOSED METAL

0.07 MIN
ALL AROUNDEXPOSED METALSOLDER MASKOPENINGNON- SOLDER MASKDEFINED(PREFERRED)SOLDER MASKOPENINGMETALSOLDER MASKDEFINEDSOLDER MASK DETAILS

4225036/A 06/2019

NOTES: (continued)
4.
5.

This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shownon this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGNVSON - 1 mm max height

DRB0008J

PLASTIC QUAD FLAT PACK- NO LEAD

(2.8)
2X
(1.51)

8X (0.6)
8X (0.31)

SYMM
1

8
2X
(1.06)

6X (0.65)
SYMM

9(R0.05) TYP
4(0.63)(1.95)

5

METAL
TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCILEXPOSED PAD
81% PRINTED COVERAGE BY AREASCALE: 20X

4225036/A 06/2019

NOTES: (continued)
6.

Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com

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