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LMG3410R070, LMG3411R070
SNOSD10F – APRIL 2016 – REVISED MAY 2020

LMG341xR070 600-V 70-mΩ GaN with Integrated Driver and Protection
1 Features

2 Applications

•

•

1

•

•

•

•

TI GaN Process Qualified Through Accelerated
Reliability In-application Hard-switching Mission
ProfilesEnables High Density Power Conversion Designs– Superior System Performance Over Cascodeor Stand-alone GaN FETs
– Low Inductance 8mm x 8mm QFN Package forEase of Design, and Layout– Adjustable Drive Strength for Switching
Performance and EMI Control– Digital Fault Status Output Signal– Only +12 V Unregulated Supply Needed
Integrated Gate Driver– Zero Common Source Inductance– 20 ns Propagation Delay for MHz Operation– Process-tuned Gate Bias Voltage for Reliability– 25 to 100V/ns User Adjustable Slew Rate
Robust Protection– Requires No External Protection Components– Over-current Protection with <100ns Response– >150V/ns Slew Rate Immunity– Transient Overvoltage Immunity– Overtemperature Protection– UVLO Protection on All Supply Rails
Device Options:– LMG3410R070: Latched Overcurrent
Protection– LMG3411R070: Cycle-by-cycle Overcurrent
Protection

•
•
•
•
•

High Density Industrial and Consumer Power
Supplies
Multi-level Converters
Solar Inverters
Industrial Motor Drives
Uninterruptable Power Supplies
High Voltage Battery Chargers

3 Description
The LMG341xR070 GaN power stage with integrated
driver and protection enables designers to achieve
new levels of power density and efficiency in powerelectronics systems. The LMG341x’s inherent
advantages over silicon MOSFETs include ultra-low
input and output capacitance, zero reverse recovery
to reduce switching losses by as much as 80%, andlow switch node ringing to reduce EMI. Theseadvantages enable dense and efficient topologies likethe totem-pole PFC.
The LMG341xR070 provides a smart alternative to
traditional cascode GaN and standalone GaN FETs
by integrating a unique set of features to simplify
design, maximize reliability and optimize theperformance of any power supply. Integrated gate
drive enables 100V/ns switching with near zero Vds
ringing, <100 ns current limiting self-protects against
unintended shoot-through events, Overtemperature
shutdown prevents thermal runaway, and systeminterface signals provide self-monitoring capability.
Device Information(1)PART NUMBER

PACKAGEBODY SIZE (NOM)

LMG341xR070

QFN (32)

8.00 mm × 8.00 mm(1) For all available packages, see the orderable addendum atthe end of the data sheet.

Simplified Block Diagram

Switching Performance at >100 V/ns
D

Direct-Drive
Slew Rate

600 V
GaN

S

RDRV
IN
VDD

5V

VNEG
LDO,
BB

OCP, OTP,UVLO

Current

FAULT

S

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

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SNOSD10F – APRIL 2016 – REVISED MAY 2020

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Table of Contents
1
2
3
4
5
6

Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions ......................... 4
Specifications......................................................... 5
6.1
6.2
6.3
6.4
6.5
6.6
6.7

Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Switching Characteristics .......................................... 7
Typical Characteristics .............................................. 8

7

Parameter Measurement Information ................ 10

8

Detailed Description ............................................ 13

7.1 Switching Parameters ............................................. 10
8.1
8.2
8.3
8.4

Overview ................................................................. 13
Functional Block Diagram ....................................... 13
Feature Description................................................. 14
Device Functional Modes........................................ 16

9

Application and Implementation ........................ 16
9.1
9.2
9.3
9.4

Application Information............................................ 16
Typical Application ................................................. 17
Paralleling GaN Devices ......................................... 20
Do's and Don'ts ...................................................... 20

10 Power Supply Recommendations ..................... 21
10.1 Using an Isolated Power Supply ........................... 21
10.2 Using a Bootstrap Diode ...................................... 21

11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 24

12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
12.6
12.7

Device Support...................................................... 26
Documentation Support ....................................... 26
Receiving Notification of Documentation Updates 26
Community Resources.......................................... 26
Trademarks ........................................................... 26
Electrostatic Discharge Caution ............................ 26
Glossary ................................................................ 26

13 Mechanical, Packaging, and Orderable
Information ........................................................... 26

4 Revision History
Changes from Revision E (October 2018) to Revision F

Page

•

Deleted max drain-source leakage current .......................................................................................................................... 6•

Added test condition for Itrip .................................................................................................................................................. 7

Changes from Revision D (August 2018) to Revision E

Page

•

Added LMG3411R070 to the LMG3410R070 datasheet ...................................................................................................... 1•

Added additional information in the overcurrent protection section...................................................................................... 14

Changes from Revision C (November 2017) to Revision D

Page

•

Changed data sheet status from: Advanced Information to: Production Data ...................................................................... 1•

Changed generic part number from: LMG3S10 to: LMG3410R070....................................................................................... 1

Changes from Revision B (March 2017) to Revision C•

Page

Changed front page ............................................................................................................................................................... 1

Changes from Revision A (June 2016) to Revision B
•

2

Page

Changed Gan Technology Preview to Advanced Information ............................................................................................... 1

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SNOSD10F – APRIL 2016 – REVISED MAY 2020

Changes from Original (April 2016) to Revision A

Page

•

Clarified part features list on front page ................................................................................................................................ 1•

Clarified definition of turn-on and turn-off energy ................................................................................................................ 12•

Corrected wording in Do's and Don'ts section ..................................................................................................................... 20•

Removed non-suitable isolated supply recommendation ..................................................................................................... 21

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SNOSD10F – APRIL 2016 – REVISED MAY 2020

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5 Pin Configuration and Functions
RWH (QFN) PACKAGE
32 PINS(Top View)

1

2

3

4

5

6

7

8

9

10

11

DRAIN

12

32 FAULT
31 IN
PAD

14

30 RDRVVDD 27

VNEG 26

SOURCELDO5V 25

24

23

21

20

28 BBSW
19

16
18

29 LPM

NC 17

15

22

SOURCE

13

Pin Functions
PIN
NAME

NO.

BBSW

28

DRAIN
FAULT

I/O (1)DESCRIPTIONPInternal buck-boost converter switch pin. Connect an inductor from this point to source

1-11

P

Power transistor drain

32

O

Fault output, push-pull, active low

IN

31

I

CMOS-compatible non-inverting gate drive input

LDO5V

25

P

5-V LDO output for external digital isolator.

LPM

29

I

Enables low-power-mode by connecting the pin to source

12-16, 18-24

PPower transistor source, die-attach pad, thermal sink, signal ground reference

RDRV

30

I

Drive strength selection pin. Connect a resistor from this pin to ground to set the turn-on drive
strength to control slew rate,

VDD

27

P

12-V power input, relative to source. Supplies 5-V rail and gate drive supply.

VNEG

26

P

Negative supply output, bypass to source with 2.2-µF capacitor

NC

17

—

Not connected, connect to source or leave floating.

PAD

—

P

Thermal Pad, tie to source with multiple vias.

SOURCE(1)

4

I = Input, O = Output, P = Power

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SNOSD10F – APRIL 2016 – REVISED MAY 2020

6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)MIN
V DS
VDS,trDrain-Source Voltage(2)

Transient Drain-Source Voltage

UNIT

600

V

800

V

20

V
A

V DD

Supply Voltage

I DS,pul (3)Drain-Source Current, Pulsed

100

Continous drain current @Tj=25℃

40

IDS (4)–0.3

MAXContinous drain current @Tj=100℃

30

A

5.5

V

V IN

IN, LPM Pin Voltage-0.3

V FAULTFAULT Pin Voltage

–0.3

5.5

V

T STG

Storage Temperature

–55

150

°C

TJ

Operating Temperature

–40

150

°C

(1)
(2)
(3)
(4)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
<1% duty cycle, <1us, for 1M pulses
Pulse current <100ns
The current is the drain current of GaN transistor only. Power stage current is clamped by integrated OCP. Please refer to the OCP
thresholds in Electrical Characteristics section.

6.2 ESD Ratings
VALUE
V(ESD)(1)(2)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)±1000

Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)

±250

UNIT
V

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN

MAX

UNIT

480

V

18

V

DC Drain-Source Current (Tj=125℃)

12A

IN, LPM Pin Voltage

5

V

I+5V

LDO External Load Current

5

mA

RDRV

Slew rate control resistor

LDCDC

DC-DC buck-boost converter output inductor

CDCDC

DC-DC buck/boost converter output capacitor

TJ

Operating Temperature

VDS

Drain-Source Voltage

VDD

Supply Voltage

IDS
VIN

9.5

NOM
12

15

150
22
2.2

-40

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kΩ
µH
µF

125

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6.4 Thermal Information
LMG3410R070
THERMAL METRIC (1)RWH (QFN)

UNIT

32 PINSR θJA

Junction-to-ambient thermal resistance

57

°C/W

R θJC(top)Junction-to-case (top) thermal resistance

5.3

°C/W

R θJC(bot)Junction-to-case (bottom) thermal resistance

0.5

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

6.5 Electrical Characteristics
over operating free-air temperature range, 9.5 V < VDD < 18 V, LPM = 5 V, VNEG = -14 V (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

GaN POWER
TRANSISTORRDS,ON

On-state Resistance

VSD

Third-quadrant mode source-drain
voltage

IDSS

Drain Leakage Current

Coss

TJ = 25°C

70

TJ = 125°C

110

IN = 0 V, ISD = 0.1 A

5IN = 0 V, ISD = 10 A

7.8

mΩ
V

VDS = 600 V, TJ = 25°C

1

VDS = 600 V, TJ = 125°C

10

GaN output capacitanceIN = 0 V, VDS = 400 V, fSW = 250 kHz

71

pF

Coss,er

Effective output capacitance, energy
relatedIN = 0 V, VDS =0-400 V

95

pF

Coss,tr

Effective output capacitance, time
relatedID = 5 A, IN = 0 V, VDS = 0-400 V

145

pF

Qrr

Reverse recovery charge

VR = 400 V, ISD = 5 A, dISD/dt = 1 A/ns

0nC

VLPM = 0 V, VDD = 12 V

80

Transistor held off

0.5

transistor held on

0.5
43

µA

DRIVER SUPPLY
IVDD,LPM

Quiescent current, ultra-low-power
mode

IVDD,Q

Quiescent current (average)

IVDD,op

Operating current

VDD = 12 V, fSW = 1 MHz, RDRV=40
kΩ, 50% duty cycle

V+5V

5V LDO output voltage

VDD = 12 V

VNEG

Negative Supply

30-mA load current

4.7

95

µA
mA
mA

5.3
-13.9

V
V

BUCK BOOSTCONVERTER
fSW,GANFET switching frequency

1

IDCDC,PK

Peak inductor current

IOUT = 20 mA, VIN = 12 V, VOUT = -14
V

ΔVNEG

DC-DC output ripple voltage, pk-pk

CNEG = 2.2 µF, IOUT = 20 mA

250
50

MHz
350

mA
mV

DRIVER INPUT
VIH

Input pin, LPM pin, logic highthreshold

VIL

Input pin, LPM pin, low threshold

VHYST

Input pin, LPM pin, hysteresis

0.8

V

RIN,L

Input pull-down resistance

150

kΩ

RLPM

LPM pin pull-down resistance

150

kΩ

6

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2.5
0.8

V
V

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SNOSD10F – APRIL 2016 – REVISED MAY 2020

Electrical Characteristics (continued)
over operating free-air temperature range, 9.5 V < VDD < 18 V, LPM = 5 V, VNEG = -14 V (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

UNDERVOLTAGE LOCKOUT
VDD,(ON)VDD turnon threshold

Turn-on voltage

9.1

V

VDD,(OFF)VDD turnoff threshold

Turn-off voltage

8.5

V

ΔVDD,UVLO

UVLO Hysteresis

550

mV

FAULT
-40℃ ≤ Tj ≤125℃

Itrip

Current Fault Trip Point

Ttrip

Temperature Trip Point

TtripHys

Temperature Trip Hysteresis

22

trip point

36

50

A

165

°C

20

°C

6.6 Switching Characteristics
over operating free-air temperature range, 9.5 V < VDD < 18 V, VNEG = -14 V, VBUS = 400 V (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

GaN FETRDRV = 15 kΩ

100

RDRV = 40 kΩ

50

RDRV = 100 kΩ

25

Slew Rate Variation

turn on, IL = 5 A, RDRV = 40 kΩ

25%Edge Rate Immunity

Drain dv/dt, device remains off
inductor-fed, max di/dt = 10 A/ns

150

V/ns

Startup Time, VIN rising above UVLO

Time until gate responds to IN CNEG
= 2.2 µF, CLDO = 1 µF

1ms

tpd,onPropagation delay, turn on

IN rising to IDS > 1 A, VDS = 400 V
RDRV = 40 kΩ, VNEG = -14 V

20

nstdelay,onTurn on delay time

IDS > 1 A to VDS < 320 V, RDRV = 40
kΩ

12

ns

tVDS,ft

VDS fall time

VDS = 320 V to VDS = 80 V, ID = 5 A

4.2

ns

tpd,off

Propagation delay, turn off

IN falling to VDS > 10 V; ID = 5 A

36

nstdelay,offTurn off delay time

VDS = 10 V to VDS = 80 V, ID = 5 A

10nstVDS,rtVDS rise time

VDS = 80 V to VDS = 320 V, ID = 5 A

15

nsCurrent Fault Delay

IDS > ITH to FAULT low

50nstblankCurrent Fault Blanking Time

VIN>VIH to end of blanking,
RDRV=15kΩ

55

nstresetFault reset time

IN held low

dv/dt
Δdv/dtdv/dt

Turn-on Drain Slew Rate

V/ns

STARTUPtSTART
DRIVER

FAULT
tcurr

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250

350

500

µs

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6.7 Typical Characteristics
100

50
Propagation delay (turn on)
Turn on delay
Rise time

40

90
Drain Slew Rate (V/ns)

45

Delay (ns)35 I = 5 A
D
30
25
20
15

70
60
50
40

10

30

5

20
10

0
0

20

40

60

80
100
RDRV (k:)

120

140

0

160

20

40
60
80
100
120
Drive Strength Resistor (k:)

D010

Figure 1. Turn-on Delays vs Drive-Strength Resistor

140

160
D001

Figure 2. Drain Slew Rate vs Drive-Strength Resistor
8

180
25 qC
125 qCOCP limit

160

7.8

Source-Drain Voltage (V)

140
120

IDS (A)

80

100
80
60
40

7.6
7.4
7.2
7
6.8

20

IN = 0 V
0

6.6
0

3

6

9

12

15
18
VDS (V)

21

24

27

30

0

1

2

IV

3
4
5
6
7
Source-Drain Current (A)

8

9

10
D004

Figure 4. Source-Drain Voltage in 3rd Quadrant Operation

Figure 3. IDS - VDS curve
2

50
30

1.8

Supply Current (mA)

Normalized RDS,on

20
1.6
1.4
1.2
1
0.8
0.6
-40

-20

0

20

40
60
80 100Temperature (qC)

120

140

160
D011

Figure 5. Normalized On Resistance vs Temperature

8

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10
7
5
3
2
1
0.7
0.5
10

VDS = 400 V
VDS = 50 V
VDS = 0 V
20

30 40 50 70 100
200 300
Switching Frequency (kHz)500 700 1000
D001

Figure 6. VDD Supply Current vs Switching Frequency

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Typical Characteristics (continued)
1000

500
400

Switching Energy (PJ)

Output Capacitance (pF)

700

300
200

100
70
50
0

50 100 150 200 250 300 350 400 450 500 550 600
Drain-Source Voltage (V)
D001

115
110
105
100
95
90
85
80
75
70
65
60
55
50
45
40

7

8

9

10
D008

Figure 8. Hard-switched Half-Bridge Turn-on and Turn-off
Switching Energy vs Drain Current
180
160

Blanking time (ns)Turn-on Energy (PJ)

Figure 7. Output Capacitance80
Turn-on Energy
75
Turn-off Energy
70
65
60 RDRV = 40 k:
55
50
45
40
35
30
25
20
15
10
5
0
1
2
3
4
5
6
Drain Current (A)

140
120
100
80
60

ID = 5 A
40

0

20

40

60
80
100
RDRV Value (k:)

120

140

160

0

20

40

D009

Figure 9. Hard-switched Half-Bridge Turn-On Switching
Energy vs Slew Rate Resistor

60

80
100
RDRV (k:)

120

140

160
RDRV

Figure 10. RDRV vs Blanking Time

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7 Parameter Measurement Information
7.1 Switching Parameters
The circuit used to measure most switching parameters is shown in Figure 11. The top LMG341xR070 in thiscircuit is used to re-circulate the inductor current and functions in third-quadrant mode only. The bottom device isthe active device; it is turned on to increase the inductor current to the desired test current. The bottom device isthen turned off and on to create switching waveforms at a specific inductor current. Both the drain current (at thesource) and the drain-source voltage is measured. The specific timing measurement is shown in Figure 12. It is
recommended to use the half-bridge as double pulse tester. Excessive 3rd quadrant operation may over heat the
top LMG341xR070.

D
RDRV

Slew
Rate

Direct-Drive
S

600 V
GaN

IN
VDD

VNEG
LDO,
BB

5V

OCP, OTP,
UVLO

500 µH
Current

FAULT
S
DC
CPCB

D
RDRV

Slew
Rate

Direct-Drive
S

600 V
GaN

+

IN
VDD
5V

VBUS
480 V

VNEG
LDO,
BB

OCP, OTP,UVLO

Current

VDS
_

FAULT
PWM input
S

Figure 11. Circuit Used to Determine Switching Parameters

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Switching Parameters (continued)

IN

50%

50%

tpd,off

tpd,onID
1A
tdelay,ontdelay,offtVDS,rttVDS,ft
80%

80%

VDS
20%

20%

Figure 12. Measurement to Determine Propagation Delays and Slew Rates
7.1.1 Turn-on Delays
The timing of the turn-on transition has three components: propagation delay, turn-on delay and rise time. The
first component is the propagation delay of the driver from when the input goes high to when the GaN FET starts
turning on (represented by 1 A drain current). The turn-on delay is the delay from when the FET starts turning on
to when the drain voltage swings down by 20 percent. Finally, the VDS fall time is the time it takes the drain
voltage to slew between 80 percent and 20 percent of the bus voltage. The drive-strength resistor value has alarge effect on turn-on delay and VDS fall time but does not affect the propagation delay significantly.
7.1.2 Turn-off Delays
The timing of the turn-off transition has three components: propagation delay, turn-off delay and fall time. The
first component is the propagation delay of the driver from when the input goes low to when the GaN FET starts
turning off. The turn-off delay is the delay from when the FET starts turning of (represented by the drain rising
above 10 V) to when the drain voltage swings up by 20 percent. Finally, the VDS rise time is the time it takes thedrain voltage to slew between 20 percent and 80 percent of the bus voltage. The turn-off delays of the
LMG341xR070 are independent of the drive-strength resistor but the turn-off delay and the VDS rise time areheavily dependent on the load current.
7.1.3 Drain Slew Rate
The slew rate, measured in volts per nanosecond, is measured on the turn-on edge of the LMG341xR070. The
slew rate is considered over the VDS fall time, where the drain falls from 80 percent to 20 percent of the bus
voltage. The drain slew rate is thus given by 60 percent of the bus voltage divided by the VDS fall time. This drainslew rate is dependent on the RDRV value and is only slightly affected by drain current. Please refer to Figure 2
for the RDRV that is matched with the needed slew rate.

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Switching Parameters (continued)
7.1.4 Turn-on and Turn-off Energy
The turn-on and turn-off energy, shown in Figure 8, represent the energy absorbed by the low-side device during
the turn-on and turn-off transients of the circuit in Figure 11, respectively. As this circuit represents a
synchronous buck converter, with input shorted to output, the switching energy is dissipated in the low-side
device. The turn-on transition is lossy, while the turn-off transition is essentially lossless; the output capacitanceof the devices is charged by the inductor current. The turn-on and turn-off losses have been calculated fromexperimental waveforms by integrating the product of the drain current with the drain-source voltage over theturn-on and turn-off times, respectively. The skew of probes for voltage and current are very important for
accurate measurement of turn-on and turn-off energy.
The switching loss of the converter can be determined by adding the turn-on and turn-off energy in Figure 8,
adjusting for the RDRV value (shown in Figure 9). To obtain the switching loss, multiply this value by the switchingfrequency. The obtained loss is a sum of the V-I overlap loss (due to hard switching) and the loss caused bycharging and discharging the COSS of both devices. Additional test-fixture capacitance, including PCB andinductor intra-winding capacitance, has not been removed from these measurements.

12

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8 Detailed Description
8.1 Overview
LMG341xR070 is a high-performance 600-V GaN transistor with integrated gate driver. The GaN transistor
provides ultra-low input and output capacitance and zero reverse recovery. The lack of reverse recovery enables
efficient operation in half-bridge and bridge-based topologies.
TI utilizes a Direct Drive architecture to control the GaN FET within the LMG341xR070. When the driver ispowered up, the GaN FET is controlled directly with the integrated gate driver. This architecture provides
superior switching performance compared with the traditional cascode approach.
The integrated driver solves a number of challenges using GaN devices. The LMG341xR070 contains a driver
specifically tuned to the GaN device for fast driving without ringing on the gate. The driver ensures the device
stays off for high drain slew rates up to 150 V/ns. In addition, the integrated driver protects against faults byproviding over-current and over-temperature protection. This feature can protect the system in case of a device
failure, or prevent a device failure in the case of a controller error or malfunction. LMG3410R070 and
LMG3411R070 have the same design and features, except the handling of OCP events. LMG3410R070 adopts
a latch-off strategy at OCP events, while LMG3411R070 can realize cycle-by-cycle current limit function. Pleaserefer to Fault Detection for more details.
Unlike silicon MOSFETs, there is no p-n junction from source to drain in GaN devices. That is why GaN devices
have no reverse recovery losses. However, the GaN device can still conduct from source to drain in 3rd quadrantof operation similar to a body diode but with higher voltage drop and higher conduction loss. 3rd quadrant
operation can be defined as follows; when the GaN device is turned off and negative current pulls the drain node
voltage to be lower than its source. The voltage drop across GaN device during 3rd quadrant operation is high;therefore, it is recommended to operate with synchronous switching and keep the duration of 3rd quadrant
operation at minimum.

8.2 Functional Block Diagram
DRAIN

VDD

GaN
LDO
UVLO

LDO5V

(+5 V, VDD, VNEG)

FAULT

IN
OCP
OTP

Level Shift
BBSW
LPM

Buck-Boost
Controller

VNEG
RDRV

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8.3 Feature Description
The LMG341xR070 includes numerous features to provide increased switching performance and efficiency incustomers' applications while providing an easy-to-use solution.
8.3.1 Direct-Drive GaN Architecture
The LMG341xR070 utilizes a series FET to ensure the GaN module stays off when VDD is not applied. When thisFET is off, the gate of the GaN transistor is held within a volt of the FET's source. As the silicon FET blocks thedrain voltage, the VGS of the GaN transistor decreases until it passes its threshold voltage. Then, the GaN
transistor turns off and blocks the remaining drain voltage.
When the LMG341xR070 is powered up, the internal buck-boost converter generates a negative voltage (VNEG)
that is sufficient to directly turn off the GaN transistor. In this case, the silicon FET is held on and the GaN
transistor is gated directly with the negative voltage. During operation, this removes the switching loss of silicon
FET.
8.3.2 Internal Buck-Boost DC-DC Converter
An internal inverting buck-boost converter generates a regulated negative rail for the turn-off supply of the GaN
device. The buck-boost converter is controlled by a peak current mode, hysteretic controller. In normal operation,
the converter remains in discontinuous-conduction mode, but may enter continuous-conduction mode during
startup and overload conditions. The converter is controlled internally and requires only a single surface-mountinductor and output bypass capacitor. For recommendations on the required passives, see Buck-Boost Converter
Design.
8.3.3 Internal Auxiliary LDO
An internal low-dropout regulator is provided to supply external loads, such as digital isolators for the high-side
drive signal. It is capable of delivering up to 5 mA to an external load. A bypass capacitor with 1 µF typical isrequired for stability.
8.3.4 Fault Detection
The GaN driver includes built-in over-current protection (OCP), over-temperature protection (OTP) and undervoltage lockout (UVLO).
8.3.4.1 Over-current Protection
The OCP circuit monitors the LMG341xR070's drain current and compares that current signal with an internallyset limit. Upon detection of the over-current, the family of GaN FETs has two optional protection actions: 1)
latched overcurrent protection; and 2) cycle-by-cycle overcurrent protection.
LMG3410R070 provides 1) latched OCP option, by which the FET is shut off and held off until the fault is resetby either holding the IN pin low for more than 350 microseconds or removing power from VDD.
LMG3411R070 provides 2) cycle-by-cycle cycle-by-cycle OCP option. In this mode, the FET is also shut off whenovercurrent happens, but the output fault signal will clear after the input PWM goes low. In the next cycle, theFET can turn on as normal. The cycle-by-cycle function can be used in cases where steady state operation
current is below the OCP level but transient response can still reach high current, while the circuit operation
cannot be paused. It also prevents the power stage from overheating by having overcurrent induced conduction
loss.
During cycle-by-cycle operation, after the current reaches the upper limit but the PWM input is still high, the load
current can flow through the third quadrant of the other FET of a half-bridge with no synchronous rectification.
The extra high negative voltage drop (–6V to –8V) from drain to source could lead to high third quadrant loss,
similar to dead time loss but with much longer time. An operation scheme of cycle-by-cycle current limitation isshown as Figure 13. Therefore, it is critical to design the control scheme to make sure the number of switchingcycles in cycle-by-cycle mode is limited, or to change PWM input based on the fault signal to shorten the time inthird quadrant conduction mode of the power stage.
OCP circuit has a 20ns typical blanking time at slew rate of 100V/ns to prevent false triggering during switch
node transitions. The blanking time increases with respect to lower slew rates accordingly since lower slew rates
results in longer switching transition time. This fast response OCP circuit protects the GaN device even under ahard short-circuit condition.
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Feature Description (continued)

Current limit

Inductor
current

VSW

Input PWM

FAULT

Figure 13. Cycle-by-cycle OCP Operation
8.3.4.2 Over-Temperature Protection and UVLO
The over-temperature protection circuit measures the temperature of the driver die and trips if the temperature
exceeds the over-temperature threshold (typically 165 °C). Upon an over-temperature condition, the GaN device
is held off until temperature falls below the hysteresis limit, typically 15 degrees below the turn-off threshold.
The FAULT output is a push-pull output indicating the readiness and fault status of the driver. It is held low whenstarting up until the safety FET is turned on. In an OCP or OTP fault condition, it is held low until the fault latches
are reset or fault is cleared. If the power supplies go below the UVLO thresholds, power transistor switching is
disabled and FAULT is held low until the power supplies recover.
8.3.5 Drive Strength Adjustment
To allow for an adjustable slew rate to control stability and ringing in the circuit, as well as an adjustment to passelectro-magnetic compliance (EMC) standards, LMG341xR070 allows the user to adjust its drive strength. A
resistor is connected the RDRV pin and ground. The value of the resistor determines the slew rate of the device
during turn-on between 30V/ns and 100V/ns; see Figure 2 for the relationship between RDRV and the drain slew
rate. The propagation delays vary with RDRV; consult Figure 1 for more details. The turn-off slew rate isdependent on the load current; therefore, it is not controlled.

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8.4 Device Functional Modes
8.4.1 Low-Power ModeIn some applications, it is important to reduce quiescent current during low power mode such as start up or burst.
The LMP pins reduces the quiescent current to support low power modes. When LPM is pulled low, the supply
current in the low-power mode is typically 80 µA. Once this pin is pulled high, the buck-boost converter will startup and LMG341xR070 will be ready to operate within 1 ms.

9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information
The LMG341xR070 is a single-channel GaN power stage targeting high-voltage applications. It targets hardswitched and soft-switched applications running from a 350 V to 480 V bus such as power-factor correction(PFC) applications. As GaN devices such as the LMG341xR070 have zero reverse-recovery charge, they are
well-suited for hard-switched half-bridge applications, such as the totem-pole bridgeless PFC circuit. It is also
well-suited for resonant DC-DC converters, such as the LLC and phase-shifted full-bridge. As both of theseconverters utilize the half-bridge building block, this section will describe how to use the LMG341xR070 in a halfbridge configuration.

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9.2 Typical Application
ISO_12V_L
5V
D1
UFM15PL-TP

C1
1µF

U1
5V_H
1

R3 AGND

PWM_H

3

49.9
68pF
C2

FauLT_H

AGND

4

VCC1

VCC2

INA

OUTA

0.1µF

OUTB

OUTC

INC

6

NC

NC

11 ISONC1

7

EN1

EN2

10 ISONC3

2
8

GND1
GND1

GND2
GND2

R4

27

VDD

25

LDO5V

C5
0.22µF

ISO_RET_H
ISO_RET_H
C6
68pF

5V_H

R7

15
9

IN_H

31

FAULT_H

32
29

10.0k

ISO7831FDWR
AGND

ISO_RET_H
15k 100V/ns
40.2k 50V/ns

R5
15k

L1

30

SW_H
BRC2518T220K
VM12V_H

28
26

IN
FAULT
LPM
RDRV
BBSW
VNEG

C9
2.2uF

5V

17

C16
1µF

NC

DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
PAD
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
33

C10
0.01µF1206

C29
0.01µF1206

C120.01µF1206

C13
0.01µF
1206

C14
0.1µF

C15
0.1µF

24

LMG3410R070
ISO_RET_H
U2

12V

AGND

5V_L
1
3

PWM_L

HVBUS

0

C8
47µF

12

VHV
i

Q1

R2

5V_H

C4
22pF

ISO_RET_H

49.9

13 ISONC2

INB

5

C3

16
14

ISO_12V_H

R1
20

R11

4

FAULT_L5

C17
68pF 6

VCC1

VCC2

INA

OUTA

INB

OUTB

OUTC

INC

C18

16
14

R18

ISO_RET_H

27

0

C23
10µF

0.1µF

5V_L
25

ISO_RET_L
C19
22pF

13

R12

12

NC

EN1

EN2

10

2
8

GND1
GND1

GND2
GND2

15
9

AGND

R6
17.8k

17.8k 100V/ns

IN_L

31

IN

FAULT_L

32

FAULT

R8

29

5V_L

15k 100v/ns

ISO7831FDWR
ISO_RET_L

LDO5V

ISO_RET_L

C11
68pF

AGND

VDD

C7
0.22µF

ISO_RET_L

49.9

11

NC

7

10.0k

R9
100k

30

SW_L
BRC2518T220K

28

BBSW

26

VNEG

VM12V_L

ISO_RET_LQ3
MGSF1N02LT1G

RDRV

C26
2.2uF

2

1

LPM

L2

3

68.1k 50V/ns

VSWNET i

Q2

ISO_12V_L

17

NC

LMG3410R070

ISO_RET_L
ISO_RET_L

DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
PAD
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
33
24

ISO_RET_L

ISO_RET_L

Figure 14. Typical Half-Bridge Application

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9.2.1 Design Requirements
This design example is for a hard-switched boost converter which is representative of PFC applications. The
system parameters considered are as follows.
Table 1. Design Parameters
DESIGN PARAMETER

EXAMPLE VALUE

Input Voltage

200 VDC

Output Voltage

400 VDC

Input (Inductor) Current

5A

Switching Frequency

100 kHz

9.2.2 Detailed Design Procedure
In high-voltage power converters, correct circuit design and PCB layout is essential to obtaining a highperformance and even functional power converter. While the general procedure for designing a power converter
is out of the scope of this document, this datasheet describes how to utilize the LMG341xR070 to build efficient,well-behaved power converters.
9.2.2.1 Slew Rate Selection
The LMG341xR070 supports slew rate adjustment through connecting a resistor from RDRV to source. The
choice of RDRV will control the slew rate of the drain voltage of the device between approximately 25 V/ns and
100 V/ns. The slew rate adjustment is used to control the following aspects of the power stage:• Switching loss in a hard-switched converter• Radiated and conducted EMI generated by the switching stage• Interference elsewhere in the circuit coupled from the switch node
• Voltage overshoot and ringing on the switch node due to power loop inductance and other parasitics
When increasing the slew rate, the switching power loss will decrease, as the portion of the switching period
where the switch simultaneous conducts high current while blocking high voltage is decreased. However, byincreasing the slew rate of the device, the other three aspects of the power stage get worse. Following thedesign recommendations in this datasheet will help mitigate the system-related challenges related to high slew
rate. Ultimately, it is up to the power designer to ensure the chosen slew rate provides the best performance in
his or her end application.
9.2.2.1.1 Startup and Slew Rate with Bootstrap High-Side Supply

Using a bootstrap supply for the high-side LMG341xR070 places additional constraints on the startup of thecircuit. Before the high-side LMG341xR070 functions correctly, its VDD, LDO5V and VNEG power supplies must
start up and be functional. Prior to the device powering up, the GaN device operates in cascode mode with
reduced performance. In particular, under high drain slew rate (dv/dt), the transistor can conduct to a small extent
and cause additional power dissipation. The correct startup procedure for a bootstrap-supplied half-bridge
depends on the circuit used.
In a buck converter without pre-bias, where the initial output voltage is zero, the startup procedure isstraightforward. In this case, before switching begins, turn on the low-side device to allow the high-side bootstrap
transistor to charge up. When the FAULT signal goes high, the high-side device has powered up completely, andnormal switching can begin.
In a boost converter or a buck converter with a pre-biased output, it is necessary to operate the circuit inswitching PWM mode while the high-side LMG341xR070 is powering up. With a boost converter, if the low-side
device is held on, the power inductor current will likely run away and the inductor will saturate. To start up a
boost converter, the duty cycle has to be very low and gradually increase to charge the output to the desired
value without the inductor current reaching saturation. This pulse sequence can be performed open-loop or using
a current-mode controller. This startup mode is standard for boost-type converters.

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However, with the LMG341xR070, during the boost converter startup, significant shoot-through current can occur
for high drain slew rates while starting up. This shoot-through current is approximately 1.25 µC per switching
event at 50 V/ns, and is comparable to a reverse-recovery event. If this shoot-through current is undesirable, thedrain slew rate of the low-side device must be reduced during startup. In Figure 14, the FAULT output from thehigh-side device is used to gate MOSFET Q1. When FAULT from the high-side is high, once the device ispowered up, Q1 turns on and reduces the effective resistance connected to RDRV on the low-side
LMG341xR070. With this circuit, the dv/dt of the low-side device can be held low to reduce power dissipation andreduce ringing during high-side startup, but then increase to reduce switching loss during normal operation.
9.2.2.2 Signal Level-Shifting
As the LMG341xR070 is a single-channel power stage, two devices are used to construct a half-bridge
converter, such as the one shown in Figure 14. A high-voltage level shifter or digital isolator must be used toprovide signals to the high-side device. Using an isolator for the low-side device is optional but will equalize
propagation delays between the high-side and low-side signal path, as well as providing the ability to use
different grounds for the power stage and the controller. If an isolator is not used on the low-side device, thecontrol ground and the power ground must be connected at the LMG341xR070, as described in Layout
Guidelines, and nowhere else on the board. With the high current slew rate of the fast-switching GaN device, any
ground-plane inductance common with the power path may cause oscillation or instability in the power stage
without the use of an isolator.
Choosing a digital isolator for level-shifting is an important consideration for fault-free operation. Because GaN
switches very quickly, exceeding 50 V/ns in hard-switching applications, isolators with high common-mode
transient immunity (CMTI) are required. If an isolator suffers from a CMTI issue, it can output a false pulse orsignal which can cause shoot-through. In addition, choosing an isolator that is not edge-triggered can improve
circuit robustness. In an edge-triggered isolator, a high dv/dt event can cause the isolator to flip states and cause
circuit malfunctioning.
On/off keyed isolators are preferred, such as the TI ISO78xxF series, as a high CMTI event would only cause ashort (few nanosecond) false pulse, which can be filtered out. To allow for filtering of these false pulses, an R-C
filter at the driver input is recommended to ensure these false pulses can be filtered. If issues are observed,
values of 1 kΩ and 22 pF can be used to filter out any false pulses.
9.2.2.3 Buck-Boost Converter Design
The Buck-boost converter generates the negative voltage necessary to turn off the direct-drive GaN FET. While it
is controlled internally, it requires an external power inductor and output capacitor. The converter is designed touse a 22 µH inductor and a 2.2 µF output capacitor. As the peak current of the buck-boost is limited to less than
350 mA, the inductor chosen must have a saturation current above 350 mA. A Taiyo-Yuden BRC2518T220K 22µH SMT inductor in a 0806 package is recommended. This inductor is connected between the BBSW pin andground. A 2.2 µF, 25V 0805 bypass capacitor is required between VNEG and ground. Due to the voltage
coefficient of X7R capacitors, a 2.2 µF capacitor will provide the required minimum 1.0 µF capacitance when
operating.

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9.2.3 Application Curves
VDS (50 V/div)
ID (2.5 A/div)

VDS (50 V/div)
ID (1.25 A/div)

VOUT = 400V
IL = 5 A
RDRV = 40 k:

VBUS = 400 V
IL = 5 A
RDRV = 40 k:

Time (5 ns/div)

Time (5 ns/div)
D006

Figure 15. Turn-on Waveform in Application Example

D007

Figure 16. Turn-off Waveform in Application Example

9.3 Paralleling GaN Devices
LMG341xR070s can be paralleled directly in soft-switching applications. As for hard-switching applications, small
decoupling inductors should be utilized to parallel the two half-bridge LMG341xR070s. This type of setup
prevents current and thermal unbalances among the parallel devices due to any propagation delay and gatesource threshold voltage mismatches, and other factors.

9.4 Do's and Don'ts
The successful use of GaN devices in general and the LMG341xR070 in particular depends on proper use of thedevice. When using the LMG341xR070, DO:• Read and fully understand the datasheet, including the application notes and layout recommendations• Use a four-layer board and place the return power path on an inner layer to minimize power-loop inductance• Use small, surface-mount bypass and bus capacitors to minimize parasitic inductance• Use the proper size decoupling capacitors and locate them close to the IC as described in the Layout
Guidelines section• Use a signal isolator to supply the input signal for the low side device. If not, ensure the signal source isconnected to the signal GND plane which is tied to the power source only at the LMG341xR070 IC• Use the FAULT pin to determine power-up state and to detect over-current and over-temperature events andsafely shut off the converter.
To avoid issues in your system when using the LMG341xR070, DON'T:• Use a single-layer or two-layer PCB for the LMG341xR070 as the power-loop and bypass capacitor
inductances will be excessive and prevent proper operation of the IC• Reduce the bypass capacitor values below the recommended values• Allow the device to experience drain transients above 600 V as they may damage the device• Allow significant third-quadrant conduction when the device is OFF or unpowered, which may cause
overheating. Self-protection feature cannot protect the device in this mode of operation• Ignore the FAULT pin output.

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10 Power Supply Recommendations
The LMG341xR070 requires an unregulated 12-V supply to power its internal driver and fault protection circuitry.
The low-side supply can be supplied from the local controller supply. The high-side device's supply must comefrom an isolated supply or bootstrap supply.

10.1 Using an Isolated Power Supply
Using an isolated power supply to power the high-side device has the advantage that it will work regardless ofcontinued power-stage switching or duty cycle. It can also power the high-side device before power-stage
switching begins, eliminating the power-loss concern of switching with an unpowered LMG341xR070 (seeStartup and Slew Rate with Bootstrap High-Side Supply for details). Finally, a properly-selected isolated supply
will contribute fewer parasitics to the switching power stage, increasing power-stage efficiency. However, theisolated power supply solution is larger and more expensive than the bootstrap solution.
The isolated supply can be constructed from an output of a flyback or FlyBuck™ converter, or using an isolated
power module. When using an unregulated supply, ensure that the input to the LMG341xR070 does not exceed
the maximum supply voltage. If necessary, a 18 V zener to clamp the VDD voltage supplied by the isolated
power converter. Minimizing the inter-winding capacitance of the isolated power supply or transformer isnecessary to reduce switching loss in hard-switched applications.

10.2 Using a Bootstrap Diode
When used in a half-bridge configuration, a floating supply is necessary for the top-side switch. Due to theswitching performance of LMG341xR070, a transformer-isolated power supply is recommended. With caution, abootstrap supply can be used with the recommendations in this section.
10.2.1 Diode Selection
LMG341xR070 has no reverse-recovery charge and little output charge. Hard-switched circuits using
LMG341xR070 also exhibit high voltage slew rates. A compatible bootstrap diode must exhibit low output charge
and, if used in a hard-switching circuit, very low reverse-recovery charge.
For soft-switching applications, the MCC UFM15PL ultra-fast silicon diode can be used. The output charge of 2.7
nC is small in comparison with the switching transistors, so it will have little influence on switching performance.
In a hard-switching application, the reverse recovery charge of the silicon diode may contribute an additional loss
to the circuit.
For hard-switched applications, a silicon carbide diode can be used to avoid reverse-recovery effects. The Cree
C3D1P7060Q SiC diode has an output charge of 4.5 nC and a reverse recovery charge of about 5 nC. There will
be some losses using this diode due to the output charge, but these will not dominate the switching stage’s
losses.
10.2.2 Managing the Bootstrap Voltage
In a synchronous buck, totem-pole PFC, or other converter where the low-side switch occasionally operates inthird-quadrant mode, it is important to consider the bootstrap supply. During the dead time, the bootstrap supply
charges through a path that includes the third-quadrant voltage drop of the low-side LMG341xR070. This thirdquadrant drop can be large, which may over-charge the bootstrap supply in certain conditions. The VDD supply of
LMG341xR070 must not exceed 18 V in bootstrap operation.

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Using a Bootstrap Diode (continued)
VDD

DRAIN
VF

SOURCE

+
±
VDD

DRAIN
VF

SOURCE

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Figure 17. Charging Path for Bootstrap DiodeThe recommended bootstrap supply connection includes a bootstrap diode and a series resistor with an optional
zener as shown in Figure 18. The series resistor limits the charging current at startup and when the low-side
device is operating in third-quadrant mode. This resistor must be chosen to allow sufficient current to power the
LMG341xR070 at the desired operating frequency. At 100 kHz operation, a value of approximately 5.1 ohms is
recommended. At higher frequencies, this resistor value should be reduced or the resistor omitted entirely toensure sufficient supply current.
VDD

+12 V

DRAIN
VF

SOURCE

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Figure 18. Suggested Bootstrap Regulation Circuit
Using a series resistor with the bootstrap supply will create a charging time constant in conjunction with thebypass capacitance on the order of a microsecond. When the dead time, or third-quadrant conduction time, ismuch lower than this time constant, the bootstrap voltage will be well-controlled and the optional zener clamp in
Figure 18 will not be necessary. If a large deadtime is needed, a 14-V zener diode can be used in parallel with
the VDD bypass capacitor to prevent damaging the high-side LMG341xR070.
10.2.3 Reliable Bootstrap Start-up
In some applications such as boost converter, the low side LMG341xR070 may need to start switching at highfrequency while high side LMG341xR070 is not fully biased. If low side GaN device turn-on speed is adjusted toachieve high slew rate, the high side GaN device can turn-on unintentionally as high dv/dt can charge high side
GaN device drain to source capacitance. For reliable operation, the slew rate should be slowed down to 30 V/ns
by changing the resistance of RDRV pin of the low side LMG341xR070 until high side LMG341xR070's bias isfully settled. This can be monitored through the FAULT output of high side LMG341xR070 as given in Figure 14.

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LMG3410R070, LMG3411R070
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SNOSD10F – APRIL 2016 – REVISED MAY 2020

11 Layout11.1 Layout Guidelines
The layout of the LMG341xR070 is critical to its performance and functionality. Because the half-bridge
configuration is typically used with these GaN devices, layout recommendations will be considered with thisconfiguration. A four-layer or higher layer count board is required to reduce the parasitic inductances of thelayout to achieve suitable performance.
11.1.1 Power Loop Inductance
The power loop, comprising the two devices in the half bridge and the high-voltage bus capacitance, undergoes
large di/dt during switching events. By minimizing the inductance of this loop, ringing and electro-magnetic
interference (EMI) can be reduced, as well as reducing voltage stress on the devices.
This loop inductance is minimized by locating the power devices as close together as possible. The bus
capacitance is positioned in line with the two devices, either below the low-side device or above the high-side
device, on the same side of the PCB. The return path (PGND in this case) is located on the second layer on the
PCB in close proximity to the top layer. By using an inner layer and not the bottom layer, the vertical dimensionof the loop is reduced, thus minimizing inductance. A large number of vias near both the device terminal and bus
capacitance carries the high-frequency switching current to the inner layer while minimizing impedance.
11.1.2 Signal Ground Connection
The LMG341xR070's SOURCE pin is also signal ground reference. The signal GND plane should be connectedto SOURCE with low impedance kelvin connection. In addition, the return path for the passives associated to thedriver (e.g. bypass capacitance) must be connected to the GND plane. In Figure 19, local signal GND planes arelocated on the second copper layer to act as the return for the local circuitry. The local signal GND planes are
isolated from the high-current SOURCE plane except the kelvin connection at the source pin through enough low
impedance vias.
11.1.3 Bypass Capacitors
The gate drive loop impedance must also be minimized to yield strong performance. Although the gate driver is
integrated on package, the bypass capacitance for the driver is placed externally on the PCB board. As the GaN
device is turned off to a negative voltage, the impedance of the negative source is included in the crucial turn-off
path. As the critical hold-off path passes through this external bypass capacitor attached to VNEG, this capacitor
must be located close to the LMG341xR070. In the Figure 19, VNEG bypass capacitors C9 and C26 are locatedimmediately adjacent to the pins on the IC with a direct connection to the SOURCE pin.
The bypass capacitors for the input supply (C8 and C23) and the 5V regulator (C5 and C7) must also be locatedimmediately next to the IC with a close connection to the ground plane.
11.1.4 Switch-Node CapacitanceGaN devices have very low output capacitance and switch quickly with a high dv/dt, yielding very low switchingloss. To preserve this low switching loss, additional capacitance added to the output node must be minimized.
The PCB capacitance at the switch node can be minimized by following these guidelines:• Minimize overlap between the switch-node plane and other power and ground planes• Thin the GND return path under the high-side device somewhat while still maintaining a low-inductance path
• Choose high-side isolator ICs and bootstrap diodes with low capacitance• Locate the power inductor as close to the power stage as possible• Power inductors should be constructed with a single-layer winding to minimize intra-winding capacitance• If a single-layer inductor is not possible, consider placing a small inductor between the primary inductor andthe power stage to effectively shield the power stage from the additional capacitance• If a back-side heat-sink is used, restrict the switch-node copper coverage on the bottom copper layer to theminimum area necessary to extract the needed heat

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Layout Guidelines (continued)
11.1.5 Signal Integrity
The control signals to the LMG341xR070 must be protected from the high dv/dt that the GaN power stage
produces. Coupling between the control signals and the drain may cause circuit instability and potential
destruction. Route the control signals (IN, FAULT and LPM) over a ground plane located on an adjacent layer.
For example, in the layout in Figure 19, all the signals are routed on the top layer directly over the signal GND
plane on the first inner copper layer.
The signals for the high-side device are often particularly vulnerable. Coupling between these signals and system
ground planes could cause issues in the circuit. Keep the traces associated with the control signals away fromdrain copper. For the high-side level shifter, ensure no copper from either the input or output side extends
beneath the isolator or the device's CMTI may be compromised.
11.1.6 High-Voltage Spacing
Circuits using the LMG341xR070 involve high voltage, potentially up to 600V. When laying out circuits using the
LMG341xR070, understand the creepage and clearance requirements in your application and how they apply tothe power stage. Functional (or working) isolation is required between the source and drain of each transistor,and between the high-voltage power supply and ground. Functional isolation or perhaps stronger isolation (suchas reinforced isolation) may be required between the input circuitry to the LMG341xR070 and the power
controller. Choose signal isolators and PCB spacing (creepage and clearance) distances which meet yourisolation requirements.
If a heatsink is used to manage thermal dissipation of the LMG341xR070, ensure necessary electrical isolationand mechanical spacing is maintained between the heatsink and the PCB.
11.1.7 Thermal Recommendations
The LMG341xR070 is a lateral transistor grown on a Si substrate. The thermal pad is connected to the Source
node. The LMG341xR070 may be used in applications with significant power dissipation, for example, hardswitched power converters. In these converters, cooling using just the PCB may not be sufficient to keep the partat a reasonable temperature. To improve the thermal dissipation of the part, TI recommends a heatsink isconnected to the back of the PCB to extract additional heat. Using power planes and numerous thermal vias, theheat dissipated in the LMG341xR070(s) can be spread out in the PCB and effectively passed to the other side of
the PCB. A heat sink can be applied to bare areas on the back of the PCB using an adhesive thermal interface
material (TIM). The soldermask from the back of the board underneath the heatsink can be removed for more
effective heat removal.
Please refer to the High Voltage Half Bridge Design Guide for LMG341x Smart GaN FET application note formore recommendations and performance data on thermal layouts.

11.2 Layout Example
Correct layout of the LMG341xR070 and its surrounding components is essential for correct operation. The
layout shown here reflects the power stage schematic in Figure 14. It may be possible to obtain acceptableperformance with alternate layout schemes, however this layout has been shown to produce good results and isintended as a guideline.

24

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LMG3410R070, LMG3411R070
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SNOSD10F – APRIL 2016 – REVISED MAY 2020

Layout Example (continued)

Figure 19. Example Half-Bridge Layout

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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOTCONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHERALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support
12.2.1 Related Documentation
High Voltage Half Bridge Design Guide for LMG3410 Smart GaN FET application note.

12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.

12.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straightfrom the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks
FlyBuck, E2E are trademarks of Texas Instruments.

12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM
www.ti.com

8-Jul-2022

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking(3)

Samples

(4/5)

(6)

LMG3410R070RWHR

ACTIVE

VQFN

RWH

32

2000

RoHS-Exempt& GreenNIPDAU

Level-3-260C-168HRS-40 to 150

LMG3410R070

Samples

LMG3410R070RWHT

ACTIVE

VQFN

RWH

32

250

RoHS-Exempt& GreenNIPDAU

Level-3-260C-168HRS-40 to 150

LMG3410R070

Samples

LMG3411R070RWHR

ACTIVE

VQFN

RWH

32

2000

RoHS-Exempt& GreenNIPDAU

Level-3-260C-168HRS-40 to 150

LMG3411
R070

Samples

LMG3411R070RWHT

ACTIVE

VQFN

RWH

32

250

RoHS-Exempt& GreenNIPDAU

Level-3-260C-168HRS-40 to 150

LMG3411
R070

Samples(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1

PACKAGE OPTION ADDENDUM
www.ti.com

8-Jul-2022

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

4-Oct-2024

TAPE AND REEL INFORMATIONREEL DIMENSIONSTAPE DIMENSIONS
K0

P1

B0 W
Reel
DiameterCavity
A0
B0
K0
W
P1

A0

Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers

Reel Width (W1)QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes

Q1

Q2

Q1

Q2

Q3

Q4

Q3

Q4

User Direction of Feed

Pocket Quadrants*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)LMG3410R070RWHR

VQFN

RWH

32

2000

330.0

16.4

LMG3411R070RWHR

VQFN

RWH

32

2000

330.0

16.4

Pack Materials-Page 1

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

8.3

8.3

2.25

12.0

16.0

Q2

8.3

8.3

2.25

12.0

16.0

Q2

PACKAGE MATERIALS INFORMATION
www.ti.com

4-Oct-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)

W

L

H

*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)LMG3410R070RWHR

VQFN

RWH

32

2000

350.0

350.0

43.0

LMG3411R070RWHR

VQFN

RWH

32

2000

350.0

350.0

43.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

4-Oct-2024

TRAY
L - Outer tray length without tabs

KO Outertray
height

WOuter
tray
width
Text

P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

DevicePackage
Name

Package
Type

Pins

SPQ

Unit arrayMax
L (mm) W
matrix temperature
(mm)
(°C)

K0
(µm)

P1
(mm)

CL
(mm)

CW
(mm)

LMG3410R070RWHR

RWH

VQFN

32

2000

10 x 26

150

315

135.9

7620

11.8

10

10.35

LMG3410R070RWHT

RWH

VQFN

32

250

10 x 26

150

315

135.9

7620

11.8

10

10.35

LMG3411R070RWHR

RWH

VQFN

32

2000

10 x 26

150

315

135.9

7620

11.8

10

10.35

LMG3411R070RWHT

RWH

VQFN

32

250

10 x 26

150

315

135.9

7620

11.8

10

10.35

Pack Materials-Page 3

PACKAGE OUTLINE

RWH0032A

VQFN - 1 mm max height
SCALE 2.000

PLASTIC QUAD FLATPACK - NO LEAD
8.1
7.9

B

A

PIN 1 INDEX AREA
8.1
7.9

1.0
0.8

(0.2) TYPCSEATING PLANE

0.05
0.00

(2.75)

3.75 0.1
PKG

0.08 C(0.65)
4X 0.85

32X
12

0.65
0.55

16

11

17
4X

2X

6.2 0.1

5.2

0.85
0.75
0.1
0.05

C A B
C

33

PKG SYMM
16X 0.65

PIN 1 ID

0.45
0.35
0.1
C A B
0.05
C

24X
27

1
32

28
4X

4X 0.65
2X 1.3

0.65
0.55
0.1
0.05

C A B
C

4X 0.75
2X 2.85
4221569/D 08/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RWH0032A

VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.75)(0.8) TYP

(1.875)28

32
4X (0.8)

27

1

2X (1.05)
24X (0.4)
22X ( 0.2)
VIA

(7.6)
33

PKG SYMM(6.2)(0.595)(1.19)TYP

20X (0.65)(0.4)
4X (0.85)(0.8) TYP
17

11
(R0.05) TYP

16

12(1.225)

4X (0.6)
PKG

PAD
4X (0.75)
2X (2.85)(7.6)

LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:12X
0.05 MAXALL AROUNDEXPOSED METAL

0.05 MIN
ALL AROUNDMETALSOLDER MASKOPENINGNON SOLDER MASKDEFINED(PREFERRED)EXPOSED METALMETAL UNDERSOLDER MASKSOLDER MASKOPENINGSOLDER MASK DEFINEDSOLDER MASK DETAILS
4221569/D 08/2021

NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

www.ti.com

EXAMPLE STENCIL DESIGN

RWH0032A

VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

PKG
(0.314)5X(1.8)

SEE DETAIL A
28
32
27

1

24X (0.4)

(0.2)
TYP

4X (1.19)

PKG SYMM(7.6)(R0.05) TYP

33

20X (0.65)

10X (0.99)
4X (0.85)
17

11
16

12
10X (1.6)

4X (0.6)
4X (0.75)
2X (2.85)(0.76)(7.6)

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCILEXPOSED PAD 33:
68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGESCALE:10X
METAL
PASTE

DETAIL A
4X, SCALE: 30X
4221569/D 08/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com

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