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MSP430F5342, MSP430F5341, MSP430F5340
JAJSG78F – JULY 2011 – REVISED SEPTEMBER 2018

MSP430F534x ミクスト・シグナル・マイクロコントローラ
1 デバイスの概要
1.1

特長

1

• 低い電源電圧範囲: 3.6Vから最低1.8Vまで• 超低消費電力– アクティブ・モード(AM)：すべてのシステム・クロック
がアクティブ– 290µA/MHz (8MHz、3V)、フラッシュ・プログラム
実行時（標準値）– 150µA/MHz (8MHz、3V)、RAMプログラム実行
時（標準値）– スタンバイ・モード(LPM3)– リアルタイム・クロック(RTC)（水晶振動子を使用）、ウォッチドッグ、および電源スーパーバイザ
が動作、RAMデータ完全保持、高速ウェークアッ
プ：
1.9µA (2.2V)、2.1µA (3V)（標準値）– 低消費電力発振器(VLO)、汎用カウンタ、ウォッ
チドッグ、および電源スーパーバイザが動作、RAMデータ完全保持、高速ウェークアップ：
1.4µA (3V)（標準値）– オフ・モード(LPM4)– RAMデータ完全保持、電源スーパーバイザが動作、高速ウェークアップ：
1.1µA (3V)（標準値）– シャットダウン・モード(LPM4.5)– 0.18µA (3V)（標準値）• スタンバイ・モードから3.5µsでウェークアップ(標準値)• 16ビットRISCアーキテクチャ、拡張メモリ、最大25MHzのシステム・クロック• 柔軟な電力管理システム– プログラム可能な、レギュレートされたコア電源電圧を持つ、完全に統合されたLDO– 電源電圧の管理、監視、およびブラウンアウト• 統合クロック・システム

1.2
•
•

•
•

データ・ロギング
汎用アプリケーション

•
•
•
•
•

•
•
•
•

アプリケーション

アナログ・センサ・システム
デジタル・センサ・システム

1.3

•
•
•

– FLL制御ループによる周波数安定化– 低電力、低周波数の内部クロック・ソース(VLO)– 低周波数のトリムされた内部基準ソース(REFO)– 32kHzの時計用水晶振動子(XT1)– 最高32MHzの高周波数水晶振動子(XT2)
16ビット・タイマ TA0：5個のキャプチャ/コンペア・レジスタを備えたTimer_A
16ビット・タイマ TA1：3個のキャプチャ/コンペア・レジスタを備えたTimer_A
16ビット・タイマ TA2：3個のキャプチャ/コンペア・レジスタを備えたTimer_A
16ビット・タイマTB0：7個のキャプチャ/コンペア・シャド
ウ・レジスタを備えたTimer_B
2つのユニバーサル・シリアル通信インターフェイス(USCI)– USCI_A0、USCI_A1がそれぞれ次の機能をサ
ポート– 自動ボーレート検出機能付きの拡張UART– IrDAエンコーダおよびデコーダ– 同期SPI– USCI_B0、USCI_B1がそれぞれ次の機能をサ
ポート
– I2C
– 同期SPI
内部リファレンス、サンプル・アンド・ホールド、オートス
キャン機能搭載の12ビットのA/Dコンバータ(ADC)
コンパレータハードウェア乗算器で32ビットの演算をサポート
シリアルのオンボード・プログラミング、外部からのプロ
グラミング電圧は不要
3チャネルの内蔵DMA
RTC機能付き基本タイマ
デバイスの比較 に、供給中の製品ファミリを掲載

概要
TIのMSP超低消費電力マイクロコントローラ・ファミリは、各種アプリケーションを対象とするそれぞれ異なるペリフェ
ラルを備えた複数のデバイスで構成されています。アーキテクチャに多様な低消費電力モードを組み合わせ、携帯型測定機器で長いバッテリ駆動時間を実現するように最適化しています。強力な16ビットRISC CPU、16ビット・レ
ジスタ、および定数ジェネレータが搭載されているため、最高水準のコード効率を実現できます。デジタル制御発振器(DCO)により、低消費電力モードからアクティブ・モードへ3.5µs (標準値)でウェークアップできます。
MSP430F534x MCUは、4つの16ビット・タイマ、高性能の12ビットADC、2つのUSCI、ハードウェア乗算器、DMA、アラーム機能付きのRTCモジュール、38本のI/Oピンを搭載しています。

1

英語版のTI製品についての情報を翻訳したこの資料は、製品の概要を確認する目的で便宜的に提供しているものです。該当する正式な英語版の最新情報は、www.ti.comで閲覧でき、その内容が常に優先されます。TIでは翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、必ず最新版の英語版をご参照くださいますようお願いいたします。
English Data Sheet: SLAS706

MSP430F5342, MSP430F5341, MSP430F5340
JAJSG78F – JULY 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

モジュールの完全な説明については、『MSP430FR5xxおよびMSP430FR6xxファミリ ユーザー・ガイド』を参照してください。
製品情報 (1)型番

パッケージ

本体サイズ (2)

MSP430F5342IRGZ

VQFN (48)7mm×7mm

MSP430F5341IRGZVQFN (48)7mm×7mm

MSP430F5340IRGZ

VQFN (48)7mm×7mm

(1)
(2)

1.4

最新の製品、パッケージ、および注文情報については、 8の「付録：パッケージ・オプション」、または
www.ti.comのTI Webサイトを参照してください。
ここに記載されているサイズは概略です。許容公差を含めたパッケージの寸法については、 8の「メカニカル・データ」を参照してください。

機能ブロック図
機能ブロック図を、図 1-1に示します。
XIN XOUT RST/NMI DVCC DVSS VCORE

AVCC AVSS
P1.x

XT2IN
XT2OUT

Unified
Clock
System

ACLK
SMCLK

MCLK

CPUXV2andWorking
Registers

128KB
96KB
64KB

10KB
8KB
6KB

Flash

RAM

Power
Management

SYS
Watchdog

LDO,
SVM, SVS,
Brownout

Port Map
Control
(P4)

PA
P2.x

P3.x

PB
P4.x

P5.x

PC
P6.x

I/O Ports
P1, P2
1×8 I/Os
1x1 I/OsI/O Ports
P3, P4
1×5 I/Os
1×8 I/OsI/O Ports
P5, P6
1×7 I/Os
1×5 I/OsInterrupt& WakeupPA
1×9 I/Os

PB
1×13 I/Os

PC
1×12 I/Os

USCI0,1
USCI_Ax:UART,
IrDA, SPIUSCI_Bx:
SPI, I2C

MAB

DMA

MDB

3 Channel

EEM(L: 8+2)
ADC12_AJTAG,
SBWInterface

MPY32

TA0

TA1

TA2

TB0

Timer_A
5 CC
Registers

Timer_A
3 CC
Registers

Timer_A
3 CC
Registers

Timer_B
7 CC
Registers

RTC_A

CRC16

12 bit200 ksps
9 channels(7 ext, 2 int)
Autoscan

COMP_BREF
5 Channels

Copyright © 2016, Texas Instruments Incorporated

図 1-1. MSP430F534xののブロック図2

デバイスの概要

Copyright © 2011–2018, Texas Instruments Incorporated

MSP430F5342, MSP430F5341, MSP430F5340
www.tij.co.jp

JAJSG78F – JULY 2011 – REVISED SEPTEMBER 2018

Table of Contents
1

2
3

デバイスの概要 ............................................. 1

5.24

PMM, SVS Low Side ................................ 24

1.1

特長 ................................................... 1

1.2

アプリケーション ........................................ 1

5.25
5.26

1.3

概要 ................................................... 1

PMM, SVM Low Side ............................... 24
Wake-up Times From Low-Power Modes andReset ................................................ 25

1.4

機能ブロック図 ......................................... 2

5.27

Timer_A ............................................. 25

改訂履歴 .................................................... 4
Device Comparison ..................................... 5

5.28

Timer_B ............................................. 25

5.29

USCI (UART Mode) Clock Frequency .............. 26

Related Products ..................................... 55.30

USCI (UART Mode) ................................. 26

Terminal Configuration and Functions .............. 6

5.31

USCI (SPI Master Mode) Clock Frequency ......... 26

Pin Diagram .......................................... 6

5.32

USCI (SPI Master Mode)............................ 26

Signal Descriptions ................................... 7

5.33

USCI (SPI Slave Mode) ............................. 28

Specifications ........................................... 11

5.34
5.35

USCI (I2C Mode) .................................... 30
12-Bit ADC, Power Supply and Input Range
Conditions ........................................... 31

5.36
5.37

12-Bit ADC, Timing Parameters .................... 31
12-Bit ADC, Linearity Parameters Using an External
Reference Voltage or AVCC as Reference Voltage 32
12-Bit ADC, Linearity Parameters Using the Internal
Reference Voltage .................................. 32

3.1

4

4.1
4.2

5

5.1

Absolute Maximum Ratings ........................ 11

5.2

ESD Ratings ........................................ 11

Recommended Operating Conditions ...............
Active Mode Supply Current Into VCC Excluding
External Current .....................................
5.5
Low-Power Mode Supply Currents (Into VCC)
Excluding External Current..........................
5.6
Thermal Resistance Characteristics, VQFN (RGZ)
Package .............................................
5.7
Schmitt-Trigger Inputs – General-Purpose I/O(P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7)
5.3
5.4

11
12

5.38

13
13

(P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI) 14
5.8
Inputs – Ports P1 and P2(P1.0 to P1.7, P2.0 to P2.7) ................................ 14
5.9
Leakage Current – General-Purpose I/O(P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7)

6(P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI) 14
5.10 Outputs – General-Purpose I/O (Full Drive Strength)(P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7)(P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3) ........... 15
5.11 Outputs – General-Purpose I/O (Reduced Drive
Strength)(P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7)(P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3) ........... 15
5.12 Output Frequency – General-Purpose I/O(P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7)(P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3) ........... 15
5.13 Typical Characteristics – Outputs, Reduced Drive
Strength (PxDS.y = 0) ............................... 16
5.14 Typical Characteristics – Outputs, Full Drive
Strength (PxDS.y = 1) ............................... 17
5.15

Crystal Oscillator, XT1, Low-Frequency Mode ..... 18

5.16
5.17

Crystal Oscillator, XT2 .............................. 19
Internal Very-Low-Power Low-Frequency Oscillator(VLO) ................................................ 20
Internal Reference, Low-Frequency Oscillator(REFO) .............................................. 20

5.18
5.19

DCO Frequency ..................................... 21

5.20

PMM, Brownout Reset (BOR)....................... 22

5.21

PMM, Core Voltage ................................. 22

5.22

PMM, SVS High Side ............................... 23

5.23

PMM, SVM High Side ............................... 24

Copyright © 2011–2018, Texas Instruments Incorporated

7

5.39

12-Bit ADC, Temperature Sensor and Built-In VMID

5.40

REF, External Reference ........................... 34

5.41

REF, Built-In Reference ............................. 35

5.42

Comparator_B ....................................... 36

5.43Flash Memory ....................................... 37

5.44

JTAG and Spy-Bi-Wire Interface .................... 37

Detailed Description ................................... 38
6.1

CPU ................................................. 38

6.2

Operating Modes .................................... 39

6.3

Interrupt Vector Addresses.......................... 40

6.4

Memory Organization ............................... 41

6.5

Bootloader (BSL) .................................... 42

6.6

JTAG Operation ..................................... 42

6.7Flash Memory ....................................... 43

6.8

RAM ................................................. 43

6.9

Peripherals .......................................... 43

6.10

Input/Output Diagrams .............................. 65

6.11

Device Descriptors .................................. 81

デバイスおよびドキュメントのサポート .................... 84
7.1

8

33

はじめに .............................................. 84

7.2

Device Nomenclature ............................... 84

7.3

ツールとソフトウェア ................................... 86

7.4

ドキュメントのサポート ................................. 88

7.5

関連リンク ............................................ 89

7.6

Community Resources .............................. 89

7.7

商標.................................................. 89

7.8

静電気放電に関する注意事項 ........................ 89

7.9

Export Control Notice ............................... 89

7.10

Glossary ............................................. 89

メカニカル、パッケージ、および注文情報................ 90

Table of Contents

3

MSP430F5342, MSP430F5341, MSP430F5340
JAJSG78F – JULY 2011 – REVISED SEPTEMBER 2018www.ti.com

2 改訂履歴
資料番号末尾の英字は改訂を表しています。その改訂履歴は英語版に準じています。
2013年
年10月
月1日
日発行分から2018年
年09月
月26日
日発行分への変更
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

4

Page

全体を通してドキュメントのフォーマットと構成を変更、セクションの番号追加も含む .............................................. 1「製品情報」表を追加 .................................................................................................................. 2
機能ブロック図を 1.4に移動........................................................................................................... 2
Added Section 3.1, Related Products ............................................................................................. 5
Added typical conditions statements at the beginning of Section 5, Specifications ........................................ 11
Added Section 5.2, ESD Ratings.................................................................................................. 11
Added note to CVCORE in Section 5.3, Recommended Operating Conditions ............................................... 11
Moved Section 5.6, Thermal Resistance Characteristics ..................................................................... 13
Changed the TYP value of the CL,eff parameter with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF
in Section 5.15, Crystal Oscillator, XT1, Low-Frequency Mode............................................................... 18
Changed the MIN value of V(DVCC_BOR_hys) from 60 mV to 50 mV in Section 5.20, PMM, Brownout Reset (BOR) ..... 22
Updated notes (1) and (2) and added note (3) in Section 5.26, Wake-up Times From Low-Power Modes andReset ................................................................................................................................. 25
Removed ADC12DIV from the formula for the TYP value in the second row of the tCONVERT parameter in
Section 5.36, 12-Bit ADC, Timing Parameters, because ADC12CLK is after division ..................................... 31
Added second row for the tEN_CMP parameter with Test Conditions of "CBPWRMD = 10" and MAX value of
100 µs and removed option for "CBPWRMD = 10" from first row of Test Conditions in Section 5.42, Comparator_B 36
Changed all instances of "bootstrap loader" to "bootloader" throughout document ........................................ 427を追加して、「ツールのサポート」、「デバイスの項目表記」、「静電気放電に関する注意事項」、「商標」セクションをそこに移動 ................................................................................................................................. 84
従来の「ツールのサポート」を 7.3「ツールとソフトウェア」に置き換え ............................................................. 86
8「メカニカル、パッケージ、および注文情報」を追加 .............................................................................. 90

改訂履歴Copyright © 2011–2018, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: MSP430F5342 MSP430F5341 MSP430F5340

MSP430F5342, MSP430F5341, MSP430F5340
www.ti.com

JAJSG78F – JULY 2011 – REVISED SEPTEMBER 2018

3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Device Comparison (1) (2)USCIDEVICE

FLASH
(KB)

SRAM
(KB)

Timer_A (3)Timer_B (4)CHANNEL A:
UART, IrDA,
SPI

CHANNEL B:
SPI, I2C

ADC12_A(Ch)

Comp_B(Ch)

I/Os

PACKAGEMSP430F5342

128

10

5, 3 (5), 3 (6)

7

2

2

7 ext, 2 int

538

48 RGZMSP430F5341

96

8

5, 3 (5), 3 (6)

7

2

2

7 ext, 2 int

538

48 RGZMSP430F5340

64

65, 3 (5), 3 (6)

7

2

2

7 ext, 2 int

538

48 RGZ

(1)
(2)
(3)
(4)
(5)
(6)

3.1

For the most current package and ordering information, see the Package Option Addendum in 8, or see the TI website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/packaging.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Only one PWM output and one external capture input available at pin.
No PWM outputs or external capture inputs available at pins.

Related Products
For information about other devices in this family of products or related products, see the following links.
Products for TI Microcontrollers TI's low-power and high-performance MCUs, with wired and wirelessconnectivity options, are optimized for a broad range of applications.
Products for MSP430 Ultra-Low-Power Microcontrollers One platform. One ecosystem. Endlesspossibilities. Enabling the connected world with innovations in ultra-low-power
microcontrollers with advanced peripherals for precise sensing and measurement.
Companion Products for MSP430F5342 Review products that are frequently purchased or used inconjunction with this product.
TI Reference Designs Find reference designs that leverage the best in TI technology to solve yoursystem-level challenges.

Copyright © 2011–2018, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: MSP430F5342 MSP430F5341 MSP430F5340

Device Comparison

5

MSP430F5342, MSP430F5341, MSP430F5340
JAJSG78F – JULY 2011 – REVISED SEPTEMBER 2018www.ti.com

4 Terminal Configuration and Functions
4.1

Pin Diagram

P5.7/TB0.1

DVSS3

P5.2/XT2IN

P5.3/XT2OUTTEST/SBWTCK

PJ.0/TDO

PJ.1/TDI/TCLK

PJ.2/TMS

PJ.3/TCK

RST/NMI/SBWTDIO

P6.1/CB1/A1

P6.2/CB2/A2

Figure 4-1 shows the pinout of the 48-pin RGZ package.

48 47 46 45 44 43 42 41 40 39 38 37
P6.3/CB3/A3

1

36

P4.7/PM_NONE

P6.4/CB4/A4

2

35

P4.6/PM_NONE

P6.5/CB5/A5

3

34

P4.5/PM_UCA1RXD/PM_UCA1SOMI

P5.0/VREF+/VeREF+/A8

4

33

P4.4/PM_UCA1TXD/PM_UCA1SIMO

P5.1/VREF-/VeREF-/A9

5

32

DVCC2

AVCC1

6

31

DVSS2

MSP430F5342IRGZMSP430F5341IRGZMSP430F5340IRGZ

26

P3.4/UCA0RXD/UCA0SOMI

VCORE

12
25
13 14 15 16 17 18 19 20 21 22 23 24

P3.3/UCA0TXD/UCA0SIMO

P3.2/UCB0CLK/UCA0STE

11

P3.1/UCB0SOMI/UCB0SCL

P4.0/PM_UCB1STE/PM_UCA1CLK

DVSS1

P2.7/UCB0STE/UCA0CLK

27

P3.0/UCB0SIMO/UCB0SDA

10

P1.7/TA1.0

P4.1/PM_UCB1SIMO/PM_UCB1SDA

DVCC1

P1.6/TA1CLK/CBOUT

28

P1.5/TA0.4

9P1.4/TA0.3

P4.2/PM_UCB1SOMI/PM_UCB1SCL

AVSS1

P1.3/TA0.2

P4.3/PM_UCB1CLK/PM_UCA1STE

29

P1.2/TA0.1

30

8P1.1/TA0.0

7P1.0/TA0CLK/ACLK

P5.4/XIN
P5.5/XOUTNOTE: TI recommends connecting the exposed thermal pad connection to VSS.

Figure 4-1. 48-Pin RGZ Package (Top View)

6

Terminal Configuration and Functions

Copyright © 2011–2018, Texas Instruments Incorporated

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Product Folder Links: MSP430F5342 MSP430F5341 MSP430F5340

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4.2

JAJSG78F – JULY 2011 – REVISED SEPTEMBER 2018

Signal Descriptions
Table 4-1 describes the signals.
Table 4-1. Signal Descriptions
TERMINAL
NAME

NO.

I/O (1)DESCRIPTION
General-purpose digital I/O

P6.3/CB3/A3

1

I/O

Comparator_B input CB3
Analog input A3 for the ADC
General-purpose digital I/O

P6.4/CB4/A4

2

I/O

Comparator_B input CB4
Analog input A4 for the ADC
General-purpose digital I/O

P6.5/CB5/A5

3

I/O

Comparator_B input CB5
Analog input A5 for the ADC
General-purpose digital I/O
Analog input A8 for the ADC

P5.0/A8/VREF+/VeREF+

4

I/O
Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
General-purpose digital I/O

P5.1/A9/VREF-/VeREF-

5

I/O

Analog input A9 for the ADC
Negative terminal for the ADC reference voltage for both sources, the internal reference
voltage, or an external applied reference voltage

AVCC1

6

P5.4/XIN

7

Analog power supply
General-purpose digital I/O
I/O
Input terminal for crystal oscillator XT1General-purpose digital I/O

P5.5/XOUT

8

I/O

AVSS1

9

Analog ground supply

DVCC1

10

Digital power supply

DVSS1

11

Digital ground supply

VCORE (2)12Regulated core power supply output (internal use only, no external current loading)

Output terminal of crystal oscillator XT1General-purpose digital I/O with port interrupt
P1.0/TA0CLK/ACLK

13

I/O

TA0 clock signal TA0CLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O with port interrupt

P1.1/TA0.0

14

I/O

TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
General-purpose digital I/O with port interrupt

P1.2/TA0.1

15

I/O

TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
General-purpose digital I/O with port interrupt

P1.3/TA0.2

16

I/O
TA0 CCR2 capture: CCI2A input, compare: Out2 output

(1)
(2)

I = input, O = output, N/A = not available
VCORE is for internal use only. No external current loading is possible. VCORE should be connected to only the recommended
capacitor value, CVCORE.
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME

NO.

I/O (1)DESCRIPTION
General-purpose digital I/O with port interrupt

P1.4/TA0.3

17

I/O
TA0 CCR3 capture: CCI3A input compare: Out3 output
General-purpose digital I/O with port interrupt

P1.5/TA0.4

18

I/O
TA0 CCR4 capture: CCI4A input, compare: Out4 output
General-purpose digital I/O with port interrupt

P1.6/TA1CLK/CBOUT

19

I/O

TA1 clock signal TA1CLK input
Comparator_B output
General-purpose digital I/O with port interrupt

P1.7/TA1.0

20

I/O
TA1 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O with port interrupt
Slave transmit enable for USCI_B0 SPI mode

P2.7/UCB0STE/UCA0CLK21

I/O
Clock signal input for USCI_A0 SPI slave mode
Clock signal output for USCI_A0 SPI master mode
General-purpose digital I/O

P3.0/UCB0SIMO/UCB0SDA

22

I/O

Slave in, master out for USCI_B0 SPI modeI2C data for USCI_B0 I2C mode
General-purpose digital I/O

P3.1/UCB0SOMI/UCB0SCL

23

I/O

Slave out, master in for USCI_B0 SPI modeI2C clock for USCI_B0 I2C mode
General-purpose digital I/O
Clock signal input for USCI_B0 SPI slave mode

P3.2/UCB0CLK/UCA0STE

24

I/O
Clock signal output for USCI_B0 SPI master mode
Slave transmit enable for USCI_A0 SPI mode
General-purpose digital I/O

P3.3/UCA0TXD/UCA0SIMO

25

I/O

Transmit data for USCI_A0 UART mode
Slave in, master out for USCI_A0 SPI mode
General-purpose digital I/O

P3.4/UCA0RXD/UCA0SOMI

26

I/O

Receive data for USCI_A0 UART mode
Slave out, master in for USCI_A0 SPI mode
General-purpose digital I/O with reconfigurable port mapping secondary function

P4.0/PM_UCB1STE/
PM_UCA1CLKDefault mapping: Slave transmit enable for USCI_B1 SPI mode
27

I/O
Default mapping: Clock signal input for USCI_A1 SPI slave mode
Default mapping: Clock signal output for USCI_A1 SPI master mode
General-purpose digital I/O with reconfigurable port mapping secondary function

P4.1/PM_UCB1SIMO/
PM_UCB1SDA

28

I/O

Default mapping: Slave in, master out for USCI_B1 SPI mode
Default mapping: I2C data for USCI_B1 I2C mode
General-purpose digital I/O with reconfigurable port mapping secondary function

P4.2/PM_UCB1SOMI/
PM_UCB1SCL

29

I/O

Default mapping: Slave out, master in for USCI_B1 SPI mode
Default mapping: I2C clock for USCI_B1 I2C mode

8

Terminal Configuration and Functions

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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME

NO.

I/O (1)DESCRIPTION
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Clock signal input for USCI_B1 SPI slave mode

P4.3/PM_UCB1CLK/PM_UCA1STE

30

DVSS2

31

Digital ground supply

DVCC2

32

Digital power supply

I/O
Default mapping: Clock signal output for USCI_B1 SPI master mode
Default mapping: Slave transmit enable for USCI_A1 SPI mode

General-purpose digital I/O with reconfigurable port mapping secondary function
P4.4/PM_UCA1TXD/
PM_UCA1SIMO

33

I/O

Default mapping: Transmit data for USCI_A1 UART mode
Default mapping: Slave in, master out for USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping secondary function

P4.5/PM_UCA1RXD/
PM_UCA1SOMI

34

I/O

Default mapping: Receive data for USCI_A1 UART mode
Default mapping: Slave out, master in for USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping secondary function

P4.6/PM_NONE

35

I/O
Default mapping: no secondary function.
General-purpose digital I/O with reconfigurable port mapping secondary function

P4.7/PM_NONE

36

I/O
Default mapping: no secondary function.
General-purpose digital I/O

P5.7/TB0.1

37

I/O
TB0 CCR1 capture: CCI1A input, compare: Out1 output

DVSS3

38

P5.2/XT2IN

39

Digital ground supply
General-purpose digital I/O
I/O
Input terminal for crystal oscillator XT2General-purpose digital I/O

P5.3/XT2OUT

40

I/O
Output terminal of crystal oscillator XT2

TEST/SBWTCK (3)Test mode pin – Selects 4-wire JTAG operation.
41

I
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activatedPJ.0/TDO (4)General-purpose digital I/O
42

I/O
JTAG test data output port

PJ.1/TDI/TCLK (4)General-purpose digital I/O
43

I/O
JTAG test data input or test clock input

PJ.2/TMS (4)General-purpose digital I/O
44

I/O
JTAG test mode selectPJ.3/TCK (4)General-purpose digital I/O
45

I/O
JTAG test clock
Reset input active low (5)RST/NMI/SBWTDIO (3)

46

I/O

Nonmaskable interrupt input
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated.
General-purpose digital I/O

P6.1/CB1/A1

47

I/O

Comparator_B input CB1
Analog input A1 for the ADC

(3)
(4)
(5)

See Section 6.5 and Section 6.6 for use with BSL and JTAG functions
See Section 6.6 for use with JTAG function.
When this pin is configured as reset, the internal pullup resistor is enabled by default.
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME

NO.

I/O (1)DESCRIPTION
General-purpose digital I/O

P6.2/CB2/A2

48

I/O

Comparator_B input CB2
Analog input A2 for the ADC

Thermal Pad

10

QFN package pad. TI recommends connecting to VSS.

Terminal Configuration and Functions

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5 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.

Absolute Maximum Ratings (1)5.1

over operating free-air temperature range (unless otherwise noted)
Voltage applied at VCC to VSS
Voltage applied to any pin (excluding VCORE)

(2)

MIN

MAX

UNIT

–0.3

4.1

V

–0.3

VCC + 0.3

V

±2

mA

150

°C

Diode current at any device pin
Storage temperature, Tstg (3)
(1)
(2)
(3)

–55

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2

ESD Ratings
VALUE

V(ESD)(1)(2)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)±1000

Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)±250

Recommended Operating Conditions
MIN

VCC

Supply voltage during program execution and flash
programming (AVCCx = DVCCx = VCC) (1) (2)

VSS

Supply voltage (AVSSx = DVSSx = VSS)TA

Operating free-air temperature

TJ

Operating junction temperature

CVCORE

Recommended capacitor at VCORECDVCC/CVCORE

Capacitor ratio of DVCC to VCORE

fSYSTEM

(2)
(3)
(4)

V

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.

5.3

(1)

UNIT

MAX

PMMCOREVx = 0

1.8

3.6

PMMCOREVx = 0, 1

2.0

3.6

PMMCOREVx = 0, 1, 2

2.2

3.6

PMMCOREVx = 0, 1, 2, 3

2.4

UNIT

V

3.6
0

V

–40

85

°C

–40

85

°C

(3)

Processor frequency (maximum MCLK frequency) (4)(see Figure 5-1)

NOM

470

nF

10
PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V(default condition)0

8.0

PMMCOREVx = 1,
2.0 V ≤ VCC ≤ 3.6 V

0

12.0

PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V

0

20.0

PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V

0

25.0

MHz

TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.22 threshold parameters forthe exact values and further details.
A capacitor tolerance of ±20% or better is required.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

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Specifications

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25

System Frequency - MHz

3
20
2

2, 3

1

1, 2

1, 2, 30, 1

0, 1, 20, 1, 2, 3

12

8

0

0
1.8

2.0

2.2

2.4

3.6

Supply Voltage - V
NOTE: The numbers within the fields denote the supported PMMCOREVx settings.

Figure 5-1. Maximum System Frequency

5.4

Active Mode Supply Current Into VCC Excluding External Current

over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3)FREQUENCY (fDCO = fMCLK = fSMCLK)PARAMETER

IAM, FlashIAM, RAM

(1)
(2)
(3)

12

EXECUTIONMEMORY

Flash

RAM

VCC

3V

3V

PMMCOREVx

1 MHz

8 MHz

12 MHz20 MHz25 MHz

TYP

MAX

TYP

MAX

TYP

2.65

4.0

4.4

2.90

4.3

7.1

7.7

4.6

7.6

TYP

MAX

TYP

MAX

0

0.36

0.47

2.32

2.60

1

0.40

2

0.44

3

0.46

0

0.20

1

0.22

1.35

2.0

2

0.24

1.50

2.2

3.7

3

0.26

1.60

2.4

3.9

3.10
0.24

1.20

UNIT

MAX

mA
10.1

11.0

1.30
2.2

mA

4.2
5.3

6.2

All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.

Specifications

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5.5

JAJSG78F – JULY 2011 – REVISED SEPTEMBER 2018

Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
TEMPERATURE (TA)PARAMETER

VCC

PMMCOREVx

–40°C
TYP

ILPM0,1MHz

Low-power mode 0 (3) (4)

ILPM2

Low-power mode 2 (5) (4)

77

85

80

85

97

83

92

88

95

105

2.2 V

0

6.5

6.5

12

10

11

17

3V

3

7.0

7.0

13

11

12

18

0

1.60

1.90

2.6

5.6

1

1.65

2.00

2.7

5.9

2

1.75

2.15

2.9

6.1

0

1.8

2.1

2.8

5.8

1

1.9

2.3

2.9

6.1

2

2.0

2.4

3.0

6.3

3

2.0

2.5

3.9

3.1

6.4

9.3

0

1.1

1.4

2.7

1.9

4.9

7.4

1

1.1

1.4

2.0

5.2

2

1.2

1.5

2.1

5.3

3

1.3

1.6

3.0

2.2

5.4

8.5

0

0.9

1.1

1.5

1.8

4.8

7.3

1

1.1

1.2

2.0

5.1

2

1.2

1.2

2.1

5.2

3V

ILPM4.5

Low-power mode 4.5 (9)

3V

3

(5)
(6)
(7)
(8)
(9)

UNIT
MAX

79

3V

(4)

85°C
TYP

73

Low-power mode 4 (8) (4)

(3)

MAX

3

ILPM4

(1)
(2)

TYP

0

Low-power mode 3,
crystal mode (6) (4)Low-power mode 3,
VLO mode (7) (4)

MAX

3V

3V

ILPM3,VLO

60°C

TYP

2.2 V

2.2 V
ILPM3,XT1LF

25°C

MAX

2.9

µA
µA

8.3

µA

µA

µA

1.3

1.3

1.6

2.2

5.3

8.1

0.15

0.18

0.35

0.26

0.5

1.0

µA

All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO setting = 1MHz operation, DCO bias generator enabled.)
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz

5.6

Thermal Resistance Characteristics, VQFN (RGZ) Package

RθJA

Junction-to-ambient thermal resistance, still air

RθJC
RθJB

THERMAL METRIC

VALUE

UNIT

27.8

°C/W

Junction-to-case thermal resistance

13.6

°C/W

Junction-to-board thermal resistance

4.7

°C/W

High-K board (JESD51-7)

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Schmitt-Trigger Inputs – General-Purpose I/O (1)(P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7)(P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI)

5.7

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VIT+

Positive-going input threshold voltage

VIT–

Negative-going input threshold voltage

Vhys

Input voltage hysteresis (VIT+ – VIT–)

RPull

Pullup/pulldown resistor (2)For pullup: VIN = VSS
For pulldown: VIN = VCC

CI

Input capacitance

VIN = VSS or VCC

(1)
(2)

VCC

MIN

1.8 V

0.80

1.40

3V

1.50

2.10

1.8 V

0.45

1.00

3V

0.75

1.65

1.8 V

0.3

0.8

3V

0.4

1.0

20

TYP

35

MAX

50

5

UNIT
V
V
V
kΩ
pF

Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
Also applies to RST pin when pullup or pulldown resistor is enabled.

Inputs – Ports P1 and P2 (1)(P1.0 to P1.7, P2.0 to P2.7)

5.8

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER(1)(2)

TEST CONDITIONS

External interrupt timing (2)t(int)

External trigger pulse duration to set interrupt flag

VCC

MIN

2.2 V, 3 V

20

MAX

UNIT
ns

Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).

5.9

Leakage Current – General-Purpose I/O(P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7)(P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)

14

High-impedance leakage current

TEST CONDITIONS(1) (2)VCC
1.8 V, 3 V

MIN

MAX

UNIT

±50

nA

The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor isdisabled.

Specifications

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JAJSG78F – JULY 2011 – REVISED SEPTEMBER 20185.10 Outputs – General-Purpose I/O (Full Drive Strength)(P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7)(P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Section 5.14)
PARAMETERTEST CONDITIONS
I(OHmax) = –3 mA (1)

VOH

1.8 V

I(OHmax) = –10 mA (2)High-level output voltage

I(OHmax) = –5 mA

(1)

3V

I(OHmax) = –15 mA (2)I(OLmax) = 3 mA (1)VOL

I(OLmax) = 5 mA (1)

(2)

MAX
VCC

VCC – 0.60

VCC

VCC – 0.25

VCC

VCC – 0.60

VCC

VSS

VSS + 0.25

VSS

VSS + 0.60

VSS

VSS + 0.25

VSS

VSS + 0.60

3V

I(OLmax) = 15 mA (2)(1)

MIN
VCC – 0.25

1.8 V

I(OLmax) = 10 mA (2)Low-level output voltage

VCC

UNIT

V

V

The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.

5.11 Outputs – General-Purpose I/O (Reduced Drive Strength)(P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7)(P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (seeSection 5.13)
PARAMETERTEST CONDITIONS
I(OHmax) = –1 mA

VOH

1.8 V

I(OHmax) = –3 mA (3)High-level output voltage

I(OHmax) = –2 mA (2)3V

I(OHmax) = –6 mA (3)I(OLmax) = 1 mA (2)VOL

I(OLmax) = 2 mA

(3)

MAX

VCC – 0.25

VCC

VCC – 0.60

VCC

VCC – 0.25

VCC

VCC – 0.60

VCC

VSS

VSS + 0.25

VSS

VSS + 0.60

VSS

VSS + 0.25

VSS

VSS + 0.60

(2)

3V

I(OLmax) = 6 mA (3)
(1)
(2)

MIN

1.8 V

I(OLmax) = 3 mA (3)Low-level output voltage

VCC

(2)

UNIT

V

V

Selecting reduced drive strength may reduce EMI.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.

5.12 Output Frequency – General-Purpose I/O(P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7)(P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

fPx.y

Port output frequency (with load)

See (1) (2)fPort_CLKClock output frequency

ACLK, SMCLK, or MCLK ,CL = 20 pF (2)

(1)
(2)

MIN

MAX

VCC = 1.8 V, PMMCOREVx = 0

16

VCC = 3 V, PMMCOREVx = 3

25

VCC = 1.8 V, PMMCOREVx = 0

16

VCC = 3 V, PMMCOREVx = 3

25

UNIT
MHz
MHz

A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For fulldrive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

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5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
8.0

VCC = 3.0 V
Px.y

IOL – Typical Low-Level Output Current – mA

IOL – Typical Low-Level Output Current – mA

25.0

TA = 25°C

20.0

TA = 85°C

15.0

10.0

5.0

0.0
0.0

0.5

1.0

1.5

2.0

2.5

3.0

IOH – Typical High-Level Output Current – mA

IOH – Typical High-Level Output Current – mA

−10.0

−20.0

−25.0
0.0

TA = 85°C

TA = 25°C

0.5

1.0

1.5

2.0

2.5

3.0

3.5

VOH – High-Level Output Voltage – V
Figure 5-4. Typical High-Level Output Current vs High-Level
Output Voltage

16

4.0
3.0
2.0
1.0

0.0

−5.0

−15.0

5.0

Specifications

0.5

1.0

1.5

2.0

VOL – Low-Level Output Voltage – V
Figure 5-3. Typical Low-Level Output Current vs Low-Level
Output Voltage

0.0
VCC = 3.0 V
Px.y

TA = 85°C

6.0

0.0
0.0

3.5

VOL – Low-Level Output Voltage – V
Figure 5-2. Typical Low-Level Output Current vs Low-Level
Output Voltage

7.0

TA = 25°C

VCC = 1.8 V
Px.y

−1.0

VCC = 1.8 V
Px.y

−2.0
−3.0
−4.0
−5.0
−6.0

TA = 85°C

TA = 25°C

−7.0
−8.0
0.0

0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
Figure 5-5. Typical High-Level Output Current vs High-Level
Output Voltage

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JAJSG78F – JULY 2011 – REVISED SEPTEMBER 20185.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

55.0

24

TA = 25°C

VCC = 3.0 V
Px.y

50.0

IOL – Typical Low-Level Output Current – mA

IOL – Typical Low-Level Output Current – mA

60.0

TA = 85°C

45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0

TA = 25°C

20
TA = 85°C

16

12

8

4

5.0
0.0
0.0

0.5

1.0

1.5

2.0

2.5

3.0

0
0.0

3.5

VOL – Low-Level Output Voltage – V
Figure 5-6. Typical Low-Level Output Current vs Low-Level
Output Voltage

−10.0
−15.0
−20.0
−25.0
−30.0
−35.0
−40.0
−45.0
−50.0

TA = 85°C

−55.0
−60.0
0.0

1.0

1.5

2.0

0

VCC = 3.0 V
Px.y

IOH – Typical High-Level Output Current – mA

−5.0

0.5

VOL – Low-Level Output Voltage – V
Figure 5-7. Typical Low-Level Output Current vs Low-Level
Output Voltage

0.0

IOH – Typical High-Level Output Current – mA

VCC = 1.8 V
Px.y

TA = 25°C
0.5

1.0

1.5

2.0

2.5

3.0

3.5

VOH – High-Level Output Voltage – V
Figure 5-8. Typical High-Level Output Current vs High-Level
Output Voltage

VCC = 1.8 V
Px.y
−4

−8

−12
TA = 85°C−16
TA = 25°C
−20
0.0

0.5

1.0

1.5

2.0

VOH – High-Level Output Voltage – V
Figure 5-9. Typical High-Level Output Current vs High-Level
Output Voltage

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5.15 Crystal Oscillator, XT1, Low-Frequency Mode (1)over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCC

MIN

fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
ΔIDVCC.LF

Differential XT1 oscillator crystal
current consumption from lowest
drive setting, LF mode

fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C

fXT1,LF,SW

XT1 oscillator logic-level squarewave input frequency, LF mode

XTS = 0, XT1BYPASS = 1 (2) (3)Integrated effective load
capacitance, LF mode (5)CL,eff

fFault,LF

tSTART,LF

(1)

(2)
(3)
(4)

(5)
(6)
(7)
(8)

18

10

32.768

XTS = 0,XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF

210

XTS = 0,XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF

300
1

XTS = 0, XCAPx = 1

5.5

XTS = 0, XCAPx = 2

8.5

XTS = 0, XCAPx = 3

12.0

Duty cycle, LF mode
Oscillator fault frequency,
LF mode (7)XTS = 0 (8)fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 6 pF
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C, CL,eff = 12 pF

UNIT

µA

Hz
50

kHz

kΩ

XTS = 0, XCAPx = 0 (6)XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz

Start-up time, LF mode

0.170

32768

XTS = 0, XT1BYPASS = 0

OALF

3V

0.290

XT1 oscillator crystal frequency,
LF mode

MAX

0.075

fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
fXT1,LF0

Oscillation allowance for
LF crystals (4)

TYP

pF

30%

70%

10

10000

Hz

1000
3V

ms
500

To improve EMI on the XT1 oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:• For XT1DRIVEx = 0, CL,eff ≤ 6 pF.
• For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF.
• For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF.
• For XT1DRIVEx = 3, CL,eff ≥ 6 pF.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, theeffective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.

Specifications

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JAJSG78F – JULY 2011 – REVISED SEPTEMBER 20185.16 Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)PARAMETERTEST CONDITIONS

VCC

MIN

fOSC = 4 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 0, TA = 25°C

IDVCC.XT2

XT2 oscillator crystal current
consumption

fOSC = 12 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 1, TA = 25°C
fOSC = 20 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 2, TA = 25°C

TYP

MAX

UNIT

200
260
3V

µA
325

fOSC = 32 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 3, TA = 25°C

450

fXT2,HF0

XT2 oscillator crystal
frequency, mode 0

XT2DRIVEx = 0, XT2BYPASS = 0 (3)

4

8

MHz

fXT2,HF1

XT2 oscillator crystal
frequency, mode 1

XT2DRIVEx = 1, XT2BYPASS = 0 (3)

8

16

MHz

fXT2,HF2

XT2 oscillator crystal
frequency, mode 2

XT2DRIVEx = 2, XT2BYPASS = 0 (3)

16

24

MHz

fXT2,HF3

XT2 oscillator crystal
frequency, mode 3

XT2DRIVEx = 3, XT2BYPASS = 0 (3)

24

32

MHz

fXT2,HF,SW

XT2 oscillator logic-levelsquare-wave input frequency, XT2BYPASS = 1 (4) (3)bypass mode

0.7

32

MHz

OAHF

tSTART,HF

CL,eff

fFault,HF
(1)
(2)

(3)
(4)
(5)
(6)
(7)
(8)

Oscillation allowance for
HF crystals (5)Start-up time

XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 pF

450

XT2DRIVEx = 1, XT2BYPASS = 0,
fXT2,HF1 = 12 MHz, CL,eff = 15 pF

320

XT2DRIVEx = 2, XT2BYPASS = 0,
fXT2,HF2 = 20 MHz, CL,eff = 15 pF

200

XT2DRIVEx = 3, XT2BYPASS = 0,
fXT2,HF3 = 32 MHz, CL,eff = 15 pF

200

fOSC = 6 MHz,XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF

0.5

fOSC = 20 MHz,XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C, CL,eff = 15 pF

Ω

3V

ms
0.3

Integrated effective load
capacitance, HF mode (6) (1)1Duty cycle

Measured at ACLK, fXT2,HF2 = 20 MHz

Oscillator fault frequency (7)XT2BYPASS = 1 (8)

40%
30

50%

pF
60%
300

kHz

Requires external capacitors at both terminals. Values are specified by crystal manufacturers. In general, an effective load capacitanceof up to 18 pF can be supported.
To improve EMI on the XT2 oscillator the following guidelines should be observed.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
• Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics definedin the Schmitt-trigger Inputs section of this data sheet.
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, theeffective load capacitance should always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.

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5.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCC

MIN

TYP

MAX

6

9.4

14

fVLO

VLO frequency

Measured at ACLK

1.8 V to 3.6 V

dfVLO/dT

VLO frequency temperature drift

Measured at ACLK (1)1.8 V to 3.6 V

Measured at ACLK (2)1.8 V to 3.6 V

Measured at ACLK

1.8 V to 3.6 V

dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
(1)
(2)

0.5
50%

kHz
%/°C

4
40%

UNIT

%/V
60%

Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

5.18 Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IREFO
fREFO

TEST CONDITIONS

VCC

MIN

TYP

TA = 25°C

1.8 V to 3.6 V

3REFO frequency calibrated

Measured at ACLK

1.8 V to 3.6 V

32768

Full temperature range

1.8 V to 3.6 V

±3.5%

3V

±1.5%

REFO absolute tolerance calibrated

TA = 25°C(1)

dfREFO/dT

REFO frequency temperature drift

Measured at ACLK

1.8 V to 3.6 V

0.01

dfREFO/dVCC

REFO frequency supply voltage drift

Measured at ACLK (2)1.8 V to 3.6 V

1.0

Duty cycle

Measured at ACLK

1.8 V to 3.6 V

REFO start-up time

40%/60% duty cycle

1.8 V to 3.6 V

tSTART
(1)
(2)

20

MAX

REFO oscillator current consumption

40%

50%
25

UNIT
µA
Hz

%/°C
%/V
60%
µs

Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

Specifications

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JAJSG78F – JULY 2011 – REVISED SEPTEMBER 20185.19 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS
(1)

MIN

TYP

MAX

UNIT

fDCO(0,0)

DCO frequency (0, 0)

DCORSELx = 0, DCOx = 0, MODx = 0

0.07

0.20

MHz

fDCO(0,31)

DCO frequency (0, 31) (1)

DCORSELx = 0, DCOx = 31, MODx = 0

0.70

1.70

MHz

fDCO(1,0)

DCO frequency (1, 0) (1)

DCORSELx = 1, DCOx = 0, MODx = 0

0.15

0.36

MHz

fDCO(1,31)

DCO frequency (1, 31) (1)

DCORSELx = 1, DCOx = 31, MODx = 0

1.47

3.45

MHz

(1)

fDCO(2,0)

DCO frequency (2, 0)

DCORSELx = 2, DCOx = 0, MODx = 0

0.32

0.75

MHz

fDCO(2,31)

DCO frequency (2, 31) (1)

DCORSELx = 2, DCOx = 31, MODx = 0

3.17

7.38

MHz

fDCO(3,0)

DCO frequency (3, 0) (1)

DCORSELx = 3, DCOx = 0, MODx = 0

0.64

1.51

MHz

(1)

fDCO(3,31)

DCO frequency (3, 31)

DCORSELx = 3, DCOx = 31, MODx = 0

6.07

14.0

MHz

fDCO(4,0)

DCO frequency (4, 0) (1)

DCORSELx = 4, DCOx = 0, MODx = 0

1.3

3.2

MHz

fDCO(4,31)

DCO frequency (4, 31) (1)

DCORSELx = 4, DCOx = 31, MODx = 0

12.3

28.2

MHz

(1)

fDCO(5,0)

DCO frequency (5, 0)

DCORSELx = 5, DCOx = 0, MODx = 0

2.5

6.0

MHz

fDCO(5,31)

DCO frequency (5, 31) (1)

DCORSELx = 5, DCOx = 31, MODx = 0

23.7

54.1

MHz

fDCO(6,0)

DCO frequency (6, 0) (1)

DCORSELx = 6, DCOx = 0, MODx = 0

4.6

10.7

MHz

fDCO(6,31)

DCO frequency (6, 31) (1)

DCORSELx = 6, DCOx = 31, MODx = 0

39.0

88.0

MHz

(1)

fDCO(7,0)

DCO frequency (7, 0)

DCORSELx = 7, DCOx = 0, MODx = 0

8.5

19.6

MHz

fDCO(7,31)

DCO frequency (7, 31) (1)

DCORSELx = 7, DCOx = 31, MODx = 0

60

135

MHz

SDCORSEL

Frequency step (ratio) between
range DCORSEL and
DCORSEL + 1

SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)

1.2

2.3

SDCO

Frequency step (ratio) between
tap DCO and DCO + 1

SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)

1.02

1.12

Duty cycle

Measured at SMCLK

40%

dfDCO/dT

DCO frequency temperaturedrift (2)fDCO = 1 MHz

0.1

%/°C

dfDCO/dVCC

DCO frequency voltage drift (3)fDCO = 1 MHz

1.9

%/V

(1)

(2)
(3)

50%

60%

When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within therange of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. If the actual fDCO frequency for the selected
range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the selected range is at its minimum
or maximum tap setting.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
100
VCC = 3.0 V
TA = 25°C

fDCO – MHz

10

DCOx = 311

0.1

DCOx = 0

0

1

2

3

4

5

6

7

DCORSEL

Figure 5-10. Typical DCO Frequency
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5.20 PMM, Brownout Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

0.80

1.30

V(DVCC_BOR_IT–)BORH on voltage, DVCC falling level| dDVCC/dt | < 3 V/s

V(DVCC_BOR_IT+)BORH off voltage, DVCC rising level| dDVCC/dt | < 3 V/s

V(DVCC_BOR_hys)

BORH hysteresis

50

tRESET

Pulse duration required at the RST/NMI pin to accept a
reset

2

MAX

UNIT

1.45

V

1.50

V

250

mV
µs

5.21 PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

VCORE3(AM)Core voltage, active mode, PMMCOREV = 3

2.4 V ≤ DVCC ≤ 3.6 V

1.90

V

VCORE2(AM)Core voltage, active mode, PMMCOREV = 2

2.2 V ≤ DVCC ≤ 3.6 V

1.80

V

VCORE1(AM)Core voltage, active mode, PMMCOREV = 1

2.0 V ≤ DVCC ≤ 3.6 V

1.60

V

VCORE0(AM)Core voltage, active mode, PMMCOREV = 0

1.8 V ≤ DVCC ≤ 3.6 V

1.40

V

VCORE3(LPM)

Core voltage, low-current mode, PMMCOREV = 3

2.4 V ≤ DVCC ≤ 3.6 V

1.94

V

VCORE2(LPM)

Core voltage, low-current mode, PMMCOREV = 2

2.2 V ≤ DVCC ≤ 3.6 V

1.84

V

VCORE1(LPM)

Core voltage, low-current mode, PMMCOREV = 1

2.0 V ≤ DVCC ≤ 3.6 V

1.64

V

VCORE0(LPM)

Core voltage, low-current mode, PMMCOREV = 0

1.8 V ≤ DVCC ≤ 3.6 V

1.44

V

22

Specifications

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JAJSG78F – JULY 2011 – REVISED SEPTEMBER 20185.22 PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSMINSVSHE = 0, DVCC = 3.6 V
I(SVSH)SVS current consumption

V(SVSH_IT+)SVSH on voltage level (1)SVSH off voltage level (1)tpd(SVSH)

SVSH propagation delayt(SVSH)SVSH on or off delay timedVDVCC/dt

DVCC rise time

(1)

MAX

0

SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0

1.5

µA

SVSHE = 1, SVSHRVL = 0

1.57

1.68

1.78

SVSHE = 1, SVSHRVL = 1

1.79

1.88

1.98

SVSHE = 1, SVSHRVL = 2

1.98

2.08

2.21

SVSHE = 1, SVSHRVL = 3

2.10

2.18

2.31

SVSHE = 1, SVSMHRRL = 0

1.62

1.74

1.85

SVSHE = 1, SVSMHRRL = 1

1.88

1.94

2.07

SVSHE = 1, SVSMHRRL = 2

2.07

2.14

2.28

SVSHE = 1, SVSMHRRL = 3

2.20

2.30

2.42

SVSHE = 1, SVSMHRRL = 4

2.32

2.40

2.55

SVSHE = 1, SVSMHRRL = 5

2.52

2.70

2.88

SVSHE = 1, SVSMHRRL = 6

2.90

3.10

3.23

SVSHE = 1, SVSMHRRL = 7

2.90

3.10

3.23

SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1

2.5

SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0

20

SVSHE = 0 → 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1

12.5

SVSHE = 0 → 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0

100
0

UNIT
nA

200

SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1

V(SVSH_IT–)

TYP

V

V

µs
µs
1000

V/s

The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and use.

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5.23 PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSMINSVMHE = 0, DVCC = 3.6 V
I(SVMH)

SVMH current consumption

SVMH on or off voltage level

tpd(SVMH)

SVMH propagation delayt(SVMH)

SVMH on or off delay time

(1)

1.5

µA

SVMHE = 1, SVSMHRRL = 0

1.62

1.74

1.85

SVMHE = 1, SVSMHRRL = 1

1.88

1.94

2.07

SVMHE = 1, SVSMHRRL = 2

2.07

2.14

2.28

SVMHE = 1, SVSMHRRL = 3

2.20

2.30

2.42

SVMHE = 1, SVSMHRRL = 4

2.32

2.40

2.55

SVMHE = 1, SVSMHRRL = 5

2.52

2.70

2.88

SVMHE = 1, SVSMHRRL = 6

2.90

3.10

3.23

SVMHE = 1, SVSMHRRL = 7

2.90

3.10

3.23

SVMHE = 1, SVMHOVPE = 1

3.75

SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1

2.5

SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0

20

SVMHE = 0 → 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1

12.5

SVMHE = 0 → 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0

100

UNIT
nA

200

SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1

V(SVMH)MAX

0SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0

(1)

TYP

V

µs
µs

The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and use.

5.24 PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSMINSVSLE = 0, PMMCOREV = 2
I(SVSL)SVSL current consumption

tpd(SVSL)SVSL propagation delayt(SVSL)SVSL on or off delay time

TYP

MAX

0

SVSLE = 1, PMMCOREV = 2, SVSLFP = 0

200

SVSLE = 1, PMMCOREV = 2, SVSLFP = 1

1.5

SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1

2.5

SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0

20

SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1

12.5

SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0

100

UNIT
nA
µA
µs
µs

5.25 PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSMINSVMLE = 0, PMMCOREV = 2
I(SVML)

SVML current consumption

tpd(SVML)

SVML propagation delayt(SVML)

SVML on or off delay time

24

Specifications

TYP
0

SVMLE= 1, PMMCOREV = 2, SVMLFP = 0

200

SVMLE= 1, PMMCOREV = 2, SVMLFP = 1

1.5

SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1

2.5

SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0

20

SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1

12.5

SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0

100

MAX

UNIT
nA
µA
µs
µs

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JAJSG78F – JULY 2011 – REVISED SEPTEMBER 20185.26 Wake-up Times From Low-Power Modes and Resetover recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

fMCLK ≥ 4.0 MHz

3.5

7.5

1.0 MHz < fMCLK< 4.0 MHz

4.5

9

150

165

µs

tWAKE-UP-FAST

Wake-up time from LPM2,
LPM3, or LPM4 to activemode (1)

PMMCOREV = SVSMLRRL = n(where n = 0, 1, 2, or 3),
SVSLFP = 1

tWAKE-UP-SLOW

Wake-up time from LPM2,
LPM3, or LPM4 to activemode (2) (3)

PMMCOREV = SVSMLRRL = n(where n = 0, 1, 2, or 3),
SVSLFP = 0

tWAKE-UP-LPM5

Wake-up time from LPM4.5 toactive mode (4)

2

3

ms

tWAKE-UP-RESET

Wake-up time from RST or
BOR event to active mode (4)

2

3

ms

(1)

(2)

(3)
(4)

µs

This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performancemode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in full performancemode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in
the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx Family User's Guide.
This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performancemode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in normal mode (lowcurrent mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in thePower Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx Family User's Guide.
The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by theperformance mode settings as for LPM2, LPM3, and LPM4.
This value represents the time from the wake-up event to the reset vector execution.

5.27 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

fTA

Timer_A input clock frequency

Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%tTA,cap

Timer_A capture timing

All capture inputs, minimum pulse
duration required for capture

VCC
1.8 V, 3 V
1.8 V, 3 V

MIN

MAX

UNIT

25

MHz

20

ns

5.28 Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

fTBTimer_B input clock frequency

Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%tTB,cap

Timer_B capture timing

All capture inputs, minimum pulse
duration required for capture

VCC
1.8 V, 3 V
1.8 V, 3 V

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MIN

MAX

UNIT

25

MHz

20

Specificationsns

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5.29 USCI (UART Mode) Clock Frequency
PARAMETER
fUSCITEST CONDITIONSMINInternal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%

USCI input clock frequency

fBITCLK BITCLK clock frequency (equals baud rate in MBaud)

MAX

UNIT

fSYSTEM

MHz

1

MHz

UNIT

5.30 USCI (UART Mode)over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER

VCC

MIN

MAX

2.2 V

50

600

3V

50

600

tτ

UART receive deglitch time (1)(1)

Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses arecorrectly recognized, their duration should exceed the maximum specification of the deglitch time.

ns

5.31 USCI (SPI Master Mode) Clock Frequency
PARAMETER
fUSCI

USCI input clock frequency

TEST CONDITIONSMINInternal: SMCLK or ACLK,
Duty cycle = 50% ±10%

MAX

UNIT

fSYSTEM

MHz

MAX

UNIT

fSYSTEMMHz

5.32 USCI (SPI Master Mode)over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)(see Figure 5-11 and Figure 5-12)
PARAMETER
fUSCI

USCI input clock frequency

TEST CONDITIONSVCCPMMCOREV = 0
tSU,MISOMI input data setup time
PMMCOREV = 3
PMMCOREV = 0

tHD,MISOMI input data hold time
PMMCOREV = 3

tVALID,MO

SIMO output data valid time (2)

(2)
(3)

26

55

3V

38

2.4 V

30

3V

25

1.8 V

0

3V

0

2.4 V

0

3V

0

ns

ns

UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 0

20

3V

18

UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3

2.4 V

16

SIMO output data hold time (3)CL = 20 pF, PMMCOREV = 3

(1)

1.8 V

1.8 V

CL = 20 pF, PMMCOREV = 0
tHD,MOMIN

SMCLK or ACLK,
Duty cycle = 50% ±10%

3V
1.8 V

ns

15
–10

3V

–8

2.4 V

–10

3V

–8

ns

fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagramsin Figure 5-11 and Figure 5-12.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the dataon the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 511 and Figure 5-12.

Specifications

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1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLO/HItLO/HI

tSU,MI
tHD,MI

SOMI
tHD,MOtVALID,MO
SIMO

Figure 5-11. SPI Master Mode, CKPH = 0
1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLO/HItLO/HI
tSU,MI

tHD,MI

SOMI
tHD,MOtVALID,MO
SIMO

Figure 5-12. SPI Master Mode, CKPH = 1

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5.33 USCI (SPI Slave Mode)over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)(see Figure 5-13 and Figure 5-14)
PARAMETERTEST CONDITIONSPMMCOREV = 0

tSTE,LEAD

STE lead time, STE low to clock
PMMCOREV = 3
PMMCOREV = 0

tSTE,LAG

STE lag time, last clock to STE high
PMMCOREV = 3
PMMCOREV = 0

tSTE,ACC

STE access time, STE low to SOMI data out
PMMCOREV = 3
PMMCOREV = 0
STE disable time, STE high to SOMI highimpedancetSTE,DISPMMCOREV = 3

SIMO input data setup time
PMMCOREV = 3
PMMCOREV = 0

tHD,SISIMO input data hold time
PMMCOREV = 3

tVALID,SO

SOMI output data valid time (2)

(2)
(3)

28

3V

8

2.4 V

7

3V

6

1.8 V

3

3V

3

2.4 V

3

3V

3

MAX

ns

1.8 V

66

3V

50

2.4 V

36

3V

30

1.8 V

30

3V

23

2.4 V

16

ns

ns

13

1.8 V

5

3V

5

2.4 V

2

3V

2

1.8 V

5

3V

5

2.4 V

5

3V

5

ns

ns

76

3V

60

UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 3

2.4 V

44

3V

40

SOMI output data hold time (3)

UNIT

ns

UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 0

CL = 20 pF, PMMCOREV = 3
(1)

11

1.8 V

CL = 20 pF, PMMCOREV = 0
tHD,SO

MIN

3V

PMMCOREV = 0
tSU,SI

VCC
1.8 V

1.8 V

18

3V

12

2.4 V

10

3V

8

ns

ns

fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagramsin Figure 5-13 and Figure 5-14.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13
and Figure 5-14.

Specifications

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tSTE,LEAD

tSTE,LAG

STE
1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLO/HItSU,SItLO/HI

tHD,SI
SIMO
tHD,SOtVALID,SOtSTE,ACC

tSTE,DIS

SOMI

Figure 5-13. SPI Slave Mode, CKPH = 0
tSTE,LAG

tSTE,LEAD
STE
1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLO/HItLO/HI
tHD,SItSU,SISIMO

tSTE,ACC

tHD,MOtVALID,SOtSTE,DIS

SOMI

Figure 5-14. SPI Slave Mode, CKPH = 1

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5.34 USCI (I2C Mode)over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-15)
PARAMETERTEST CONDITIONS

VCC

MIN

Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%

MAX

UNIT

fSYSTEM

MHz

400

kHz

fUSCI

USCI input clock frequencyfSCL

SCL clock frequency

tHD,STA

Hold time (repeated) STARTtSU,STA

Setup time for a repeated STARTtHD,DAT

Data hold time

2.2 V, 3 V

0nstSU,DAT

Data setup time

2.2 V, 3 V

250

ns

2.2 V, 3 V
fSCL ≤ 100 kHz
fSCL ≤ 100 kHz

fSCL ≤ 100 kHz

tSP

Pulse duration of spikes suppressed by input filter

tSU,STAtHD,STA

4.7

µs

0.6

4.0

2.2 V, 3 V

fSCL > 100 kHz

µs

0.6

2.2 V, 3 V

fSCL > 100 kHz

Setup time for STOP

4.0

2.2 V, 3 V

fSCL > 100 kHz

tSU,STO

0

µs

0.6

2.2 V

50

600

3V

50

600

tHD,STA

ns

tBUF

SDA
tLOW

tHIGH

tSP

SCL

tSU,DATtSU,STOtHD,DAT

Figure 5-15. I2C Mode Timing

30

Specifications

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JAJSG78F – JULY 2011 – REVISED SEPTEMBER 20185.35 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETERTEST CONDITIONS

VCC

AVCC

Analog supply voltage

AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V

V(Ax)Analog input voltage range (2)All ADC12 analog input pins Ax

IADC12_A

Operating supply current into
AVCC terminal (3)fADC12CLK = 5.0 MHz (4)CI

Input capacitance

Only one terminal Ax can be selected at one
time

Input MUX ON resistance0 V ≤ VAx ≤ AVCC

RI
(1)
(2)
(3)
(4)

MIN

TYP

MAX

UNIT

2.2

3.6

V

0

AVCC

V

2.2 V

125

155

3V

150

220

2.2 V

20

25

pF

200

1900

Ω

10

µA

The leakage current is specified by the digital I/O input leakage.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If thereference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling
capacitors are required. See Section 5.40 and Section 5.41.
The internal reference supply current is not included in current consumption parameter IADC12_A.
ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0.

5.36 12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCCFor specified performance of ADC12 linearity
parameters using an external reference
voltage or AVCC as reference (1)fADC12CLKADC conversion clock

For specified performance of ADC12 linearity
parameters using the internal reference (2)2.2 V, 3 V

For specified performance of ADC12 linearity
parameters using the internal reference (3)fADC12OSC

tCONVERTtSample
(1)
(2)
(3)
(4)
(5)

Internal ADC12
oscillator (4)Conversion time

Sampling time

MIN

TYP

MAX

0.45

4.8

5.0

0.45

2.4

4.0

0.45

2.4

2.7

4.8

5.4

ADC12DIV = 0, fADC12CLK = fADC12OSC

2.2 V, 3 V

4.2

REFON = 0, Internal oscillator,
ADC12OSC used for ADC conversion clock

2.2 V, 3 V

2.4

External fADC12CLK from ACLK, MCLK, or
SMCLK, ADC12SSEL ≠ 0
RS = 400 Ω, RI = 1000 Ω, CI = 20 pF,
τ = (RS + RI) × CI (5)

UNIT

MHz

MHz

3.1
13 ×

µs

1 / fADC12CLK
2.2 V, 3 V

1000

ns

REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,
SREF0 = 0. The performance of the ADC12 linearity is specified when using the ADC12OSC. For other clock sources, the performanceof the ADC12 linearity is specified with fADC12CLK maximum of 5.0 MHz.
SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1
SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured whenusing the ADC12OSC divided by 2.
The ADC12OSC is sourced directly from MODOSC inside the UCS.
Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) × (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance

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5.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as
Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS
1.4 V ≤ dVREF ≤ 1.6 V (2)EIIntegral linearity error (1)ED

Differential linearity error (1)EO

Offset error (3)EG

Gain error (3)

ET
(1)
(2)

(3)

Total unadjusted error

1.6 V < dVREF (2)

VCC

MIN

TYP

MAX
±2.0

2.2 V, 3 V±1.7

See (2)

2.2 V, 3 V

dVREF ≤ 2.2 V (2)2.2 V, 3 V

±1.0

±2.0

dVREF > 2.2 V (2)2.2 V, 3 V

±1.0

±2.0

See (2)

2.2 V, 3 V

±1.0

±2.0

dVREF ≤ 2.2 V (2)2.2 V, 3 V

±1.4

±3.5

dVREF > 2.2 V (2)2.2 V, 3 V

±1.4

±3.5

±1.0

UNIT
LSB
LSB
LSB
LSB
LSB

Parameters are derived using the histogram method.
The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ – VR-, VR+ < AVCC, VR- > AVSS.
Unless otherwise noted, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω and two decoupling capacitors, 10 µF
and 100 nF, should be connected to VREF to decouple the dynamic current. Also see the MSP430F5xx and MSP430F6xx Family User's
Guide.
Parameters are derived using a best fit curve.

5.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
EI

Integral linearity
error (2)ED

Differential linearity
error (2)TEST CONDITIONS (1)ADC12SR = 0, REFOUT = 1, fADC12CLK ≤ 4.0 MHz
ADC12SR = 0, REFOUT = 0, fADC12CLK ≤ 2.7 MHz

VCC

2.2 V, 3 V

ADC12SR = 0, REFOUT = 0, fADC12CLK ≤ 2.7 MHz
EO

Offset error (3)EG

Gain error (3)ADC12SR = 0, REFOUT = 1, fADC12CLK ≤ 4.0 MHz
ADC12SR = 0, REFOUT = 0, fADC12CLK ≤ 2.7 MHz
ADC12SR = 0, REFOUT = 1, fADC12CLK ≤ 4.0 MHz
ADC12SR = 0, REFOUT = 0, fADC12CLK ≤ 2.7 MHz
ADC12SR = 0, REFOUT = 1, fADC12CLK ≤ 4.0 MHz

TYP

2.2 V, 3 V
2.2 V, 3 V

±2.5
–1.0

+2.0

–1.0

+1.5

–1.0

+2.5

UNIT
LSB

LSB

±1.0

±2.0

±1.0

±2.0

±1.0

±2.0

LSB

(4)

VREF

±3.5

LSB

±1.5%
±1.4

LSB

ET

Total unadjusted error

(1)
(2)
(3)
(4)

The internal reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 1. dVREF = VR+ - VR-.
Parameters are derived using the histogram method.
Parameters are derived using a best fit curve.
The gain error and total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In thismode, the reference voltage used by the ADC12_A is not available on a pin.

32

Specifications

ADC12SR = 0, REFOUT = 0, fADC12CLK ≤ 2.7 MHz

2.2 V, 3 V

MAX
±1.7

2.2 V, 3 V

ADC12SR = 0, REFOUT = 1, fADC12CLK ≤ 4.0 MHz
ADC12SR = 0, REFOUT = 1, fADC12CLK ≤ 2.7 MHz

MIN±1.5% (4) VREF

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JAJSG78F – JULY 2011 – REVISED SEPTEMBER 20185.39 12-Bit ADC, Temperature Sensor and Built-In VMID (1)over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERVSENSORSee (2) and Figure 5-16

TCSENSORtSENSOR(sample)

TEST CONDITIONSVCCADC12ON = 1, INCH = 0Ah,
TA = 0°C

2.2 V

680

3V

680

2.2 V

2.25

3V

2.25

ADC12ON = 1, INCH = 0Ah
Sample time required ifchannel 10 is selected (3)ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤1 LSB

AVCC divider at channel 11,
VAVCC factor

ADC12ON = 1, INCH = 0Bh

AVCC divider at channel 11

ADC12ON = 1, INCH = 0Bh

Sample time required ifchannel 11 is selected (4)ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤1 LSB

VMID

tVMID(sample)
(1)
(2)

(3)
(4)

MIN

2.2 V

100

3V

100

TYP

MAX

UNIT
mV
mV/°C
µs

0.48

0.5

0.52 VAVCC

2.2 V

1.06

1.1

1.14

3V

1.44

1.5

1.56

2.2 V, 3 V

1000

V
ns

The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current consumption of
the temperature sensor.
The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor. The TLV structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference
voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature,°C) + VSENSOR, where TCSENSOR andVSENSOR can be computed from the calibration values for higher accuracy. Also see the MSP430F5xx and MSP430F6xx Family User's
Guide.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor on-time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.

Typical Temperature Sensor Voltage (mV)

1000
950
900
850
800
750
700
650
600
550
500
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Ambient Temperature (°C)

Figure 5-16. Typical Temperature Sensor Voltage

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5.40 REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETERTEST CONDITIONS

VCC

MIN

MAX

UNIT

VeREF+

Positive external reference voltage
input

VeREF+ > VREF-/VeREF- (2)

1.4

AVCC

V

VREF-/VeREF-

Negative external reference voltage
input

VeREF+ > VREF-/VeREF- (3)

0

1.2

V

(VeREF+ –VREF-/VeREF-)

Differential external reference
voltage input

VeREF+ > VREF-/VeREF- (4)

1.4

AVCC

V

–26

26

IVeREF+,
IVREF-/VeREF-

CVREF+/(1)
(2)
(3)
(4)
(5)

34

Static input current

1.4 V ≤ VeREF+ ≤ VAVCC,
VeREF- = 0 V, fADC12CLK = 5 MHz,ADC12SHTx = 1h,
Conversion rate 200 ksps

2.2 V, 3 V

1.4 V ≤ VeREF+ ≤ VAVCC,
VeREF- = 0 V, fADC12CLK = 5 MHz,ADC12SHTx = 8h,
Conversion rate 20 ksps

2.2 V, 3 VµA

Capacitance at VREF+ or VREFterminal

–1

(5)

10

1

µF

The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow therecommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an externalreference source if it is used for the ADC12_A. Also see the MSP430F5xx and MSP430F6xx Family User's Guide.

Specifications

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JAJSG78F – JULY 2011 – REVISED SEPTEMBER 20185.41 REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER

VREF+

AVCC(min)TEST CONDITIONS

Positive built-in reference
voltage output

AVCC minimum voltage,
Positive built-in reference
activeVCC

MIN

REFVSEL = {2} for 2.5 V,
REFON = REFOUT = 1, IVREF+= 0 A

3V

2.46252.50 2.5375

REFVSEL = {1} for 2.0 V,
REFON = REFOUT = 1, IVREF+= 0 A

3V

1.9503

1.98 2.0097

REFVSEL = {0} for 1.5 V,
REFON = REFOUT = 1, IVREF+= 0 A

2.2 V, 3 V

1.4677

1.49 1.5124

REFVSEL = {0} for 1.5 V

2.2

REFVSEL = {1} for 2.0 V

2.3

REFVSEL = {2} for 2.5 V

2.8

ADC12SR = 1 (4), REFON = 1,
REFOUT = 0, REFBURST = 0

IREF+

Operating supply current into
AVCC terminal (2) (3)ADC12SR = 1 (4), REFON = 1,
REFOUT = 1, REFBURST = 0(4)

ADC12SR = 0 , REFON = 1,
REFOUT = 0, REFBURST = 0

IL(VREF+)REFVSEL = {0, 1, 2},
IVREF+ = +10 µA or –1000 µA,
AVCC = AVCC(min) for each reference level,
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1

CVREF+

Capacitance at VREF+
terminals

REFON = REFOUT = 1

TCREF+

Temperature coefficient ofbuilt-in reference (6)IVREF+ = 0 A,
REFVSEL = {0, 1, 2}, REFON = 1,
REFOUT = 0 or 1

PSRR_DCPower supply rejection ratio(DC)

PSRR_ACPower supply rejection ratio(AC)tSETTLE

(1)

(2)
(3)
(4)
(5)
(6)
(7)

Settling time of reference
voltage (7)

MAX

UNIT

V

V

70

100

µA

0.45

0.75

mA

210

310

µA

0.95

1.7

mA

3V

ADC12SR = 0 (4), REFON = 1,
REFOUT = 1, REFBURST = 0
Load-current regulation,
VREF+ terminal (5)TYP2500 µV/mA

100

pF

30

50

ppm/
°C

AVCC = AVCC(min) to AVCC(max),
TA = 25°C, REFVSEL = {0, 1, 2},
REFON = 1, REFOUT = 0 or 1

120

300

µV/V

AVCC = AVCC(min) to AVCC(max),
TA = 25°C, f = 1 kHz, ΔVpp = 100 mV,REFVSEL = {0, 1, 2}, REFON = 1,
REFOUT = 0 or 1

6.4

AVCC = AVCC(min) to AVCC(max),
REFVSEL = {0, 1, 2}, REFOUT = 0,
REFON = 0 → 1

75

AVCC = AVCC(min) to AVCC(max),
CVREF = CVREF(max),
REFVSEL = {0, 1, 2}, REFOUT = 1,
REFON = 0 → 1

20

mV/V

µs
75

The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one
smaller and one larger, for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal and isused as the reference for the conversion and uses the larger buffer. When REFOUT = 0, the reference is only used as the reference forthe conversion and uses the smaller buffer.
The internal reference current is supplied from the AVCC terminal. Consumption is independent of the ADC12ON control bit, unless aconversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current
contribution of the larger buffer without external load.
The temperature sensor is provided by the REF module. Its current is supplied from the AVCC terminal and is equivalent to IREF+ with
REFON =1 and REFOUT = 0.
For devices without the ADC12, the parametric with ADC12SR = 0 are applicable.
Contribution only due to the reference and buffer including package. This does not include resistance due to factors such as PCB
traces.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load when REFOUT = 1.

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5.42 Comparator_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERVCCTEST CONDITIONS

VCCSupply voltage

MIN

TYP

1.8
1.8 V
CBPWRMD = 00

IAVCC_COMP

Comparator operating supply current into
AVCC, Excludes reference resistor ladder

IAVCC_REF

Quiescent current of local reference
voltage amplifier into AVCC

VIC

Common mode input range

VOFFSET

Input offset voltage

CIN

Input capacitance

RSIN

Propagation delay, response time

tPD,filter

Propagation delay with filter active

tEN_CMPtEN_REF

36

Comparator enable time

Resistor reference enable time

VCB_REF

Reference voltage for a given tap

Specifications

UNIT

3.6

V

40

2.2 V

30

50

3V

40

65

CBPWRMD = 01

2.2 V, 3 V

1030

CBPWRMD = 10

2.2 V, 3 V

0.1

0.5

CBREFACC = 1, CBREFLx = 01
0

µA

VCC
–1

V

CBPWRMD = 00

±20

CBPWRMD = 01, 10±10

ON, switch closed

3

OFF, switch opened

µA

22

5

Series input resistance

tPD

MAX

mV
pF

4

30

kΩ
MΩ

CBPWRMD = 00, CBF = 0450

CBPWRMD = 01, CBF = 0600

CBPWRMD = 10, CBF = 050

CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 00

0.35

0.6

1.0

CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 01

0.6

1.0

1.8

CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 10

1.0

1.8

3.4

CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 11

1.8

3.4

6.5

1

2

ns
µs

µs

CBON = 0 to CBON = 1,
CBPWRMD = 00, 01µs

CBON = 0 to CBON = 1,
CBPWRMD = 10

100

CBON = 0 to CBON = 1

1
VIN ×(n + 1)/ 32

VIN = reference into resistor
ladder (n = 0 to 31)

1.5

µs
V

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JAJSG78F – JULY 2011 – REVISED SEPTEMBER 20185.43 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER

TJ

DVCC(PGM/ERASE) Program or erase supply voltage

MIN

TYP

UNIT

3.6

V

IPGM

Average supply current from DVCC during program

3

5

mA

IERASE

Average supply current from DVCC during erase

6

11

mA

IMERASE, IBANK

Average supply current from DVCC during mass erase or bank erase

6

11

mA

tCPT

Cumulative program time

1.8

MAX

(1)

16
104

Program and erase endurancetRetention

Data retention duration

25°C
(2)

105

ms
cycles

100

years

tWord

Word or byte program time

64

85

µs

tBlock, 0

Block program time for first byte or word (2)

49

65

µs

tBlock, 1–(N–1)

Block program time for each additional byte or word, except for last byte orword (2)

37

49

µs

tBlock, N

Block program time for last byte or word (2)

55

73

µs

tEraseErase time for segment, mass erase, and bank erase (when available) (2)

23

32

ms

fMCLK,MGR

MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)

0

1

MHz

(1)
(2)

The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
These values are hardwired into the state machine of the flash controller.

5.44 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER

VCC

MIN

TYP

MAX

UNIT

fSBW

Spy-Bi-Wire input frequency

2.2 V, 3 V

0

20

MHz

tSBW,Low

Spy-Bi-Wire low clock pulse duration

2.2 V, 3 V

0.025

15

µs

tSBW, En

Spy-Bi-Wire enable time, TEST high to acceptance of first clock edge (1)2.2 V, 3 V

1µstSBW,Rst

Spy-Bi-Wire return to normal operation time

µs

fTCK

TCK input frequency, 4-wire JTAG (2)Rinternal

Internal pulldown resistance on TEST

(1)
(2)

15

100

2.2 V

0

5

3V

0

10

2.2 V, 3 V

45

60

80

MHz
kΩ

Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying thefirst SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.

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6 Detailed Description
6.1

CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction withseven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, arededicated as program counter, stack pointer, status register, and constant generator, respectively. The
remaining registers are general-purpose registers (see Figure 6-1).
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be
managed with all instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word andbyte data.
Program Counter

PC/R0

Stack Pointer

SP/R1

Status Register

SR/CG1/R2

Constant Generator

CG2/R3General-Purpose Register

R4

General-Purpose Register

R5

General-Purpose Register

R6

General-Purpose Register

R7

General-Purpose Register

R8

General-Purpose Register

R9

General-Purpose Register

R10

General-Purpose Register

R11

General-Purpose Register

R12

General-Purpose Register

R13

General-Purpose Register

R14

General-Purpose Register

R15

Figure 6-1. CPU Registers

38

Detailed Description

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6.2

JAJSG78F – JULY 2011 – REVISED SEPTEMBER 2018

Operating Modes
These microcontrollers have one active mode and six software-selectable low-power modes of operation.
An interrupt event can wake the device from any of the low-power modes, service the request, and restore
back to the low-power mode on return from the interrupt program.
Software can configure the following operating modes:
•
•

•

•

•

•

•

Active mode (AM)– All clocks are active
Low-power mode 0 (LPM0)– CPU is disabled– ACLK and SMCLK remain active– MCLK is disabled– FLL loop control remains active
Low-power mode 1 (LPM1)– CPU is disabled– FLL loop control is disabled– ACLK and SMCLK remain active– MCLK is disabled
Low-power mode 2 (LPM2)– CPU is disabled– MCLK, FLL loop control, and DCOCLK are disabled– DC generator of the DCO remains enabled– ACLK remains active
Low-power mode 3 (LPM3)– CPU is disabled– MCLK, FLL loop control, and DCOCLK are disabled– DC generator of the DCO is disabled– ACLK remains active
Low-power mode 4 (LPM4)– CPU is disabled– ACLK is disabled– MCLK, FLL loop control, and DCOCLK are disabled– DC generator of the DCO is disabled– Crystal oscillator is stopped– Complete data retention
Low-power mode 4.5 (LPM4.5)– Internal regulator disabled– No data retention– Wake-up input from RST/NMI, P1, and P2

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Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (seeTable 6-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
Table 6-1. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCEINTERRUPT FLAGSYSTEM
INTERRUPT

WORD
ADDRESSPRIORITY

System Reset
Power upExternal reset
Watchdog time-out, password violation
Flash memory password violation
PMM password violation

WDTIFG, KEYV (SYSRSTIV) (1) (2)Reset

0FFFEh63, highest

System NMI
PMM
Vacant memory access
JTAG mailbox

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,VLRLIFG, VLRHIFG, VMAIFG, JMBINIFG,JMBOUTIFG (SYSSNIV) (1)(Non)maskable

0FFFCh62

User NMI
NMI
Oscillator fault
Flash memory access violation

NMIIFG, OFIFG, ACCVIFG, BUSIFG(SYSUNIV) (1) (2)(Non)maskable

0FFFAh61

Comp_B

Comparator B interrupt flags (CBIV) (1) (3)Maskable

0FFF8h60

TB0

TB0CCR0 CCIFG0 (3)Maskable

0FFF6h59

TB0

TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TB0IV) (1) (3)Maskable

0FFF4h58

Watchdog Timer_A interval timer
mode

WDTIFG

Maskable

0FFF2h57

USCI_A0 receive or transmit

UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) (3)Maskable

0FFF0h56

USCI_B0 receive or transmit

UCB0RXIFG, UCB0TXIFG (UCB0IV) (1) (3)Maskable

0FFEEh55

ADC12_A

ADC12IFG0 to ADC12IFG15 (ADC12IV) (1) (3) (4)Maskable

0FFECh54

TA0

TA0CCR0 CCIFG0

Maskable

0FFEAh53

TA0

TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV) (1) (3)Maskable

0FFE8h52

Reserved

Reserved

Maskable

0FFE6h

51

DMA

(1)
(2)
(3)
(4)
40

(3)

DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1) (3)Maskable

0FFE4h50

TA1

TA1CCR0 CCIFG0 (3)Maskable

0FFE2h49

TA1

TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV) (1) (3)Maskable

0FFE0h48

I/O port P1

P1IFG.0 to P1IFG.7 (P1IV) (1) (3)Maskable

0FFDEh47

USCI_A1 receive or transmit

UCA1RXIFG, UCA1TXIFG (UCA1IV) (1) (3)Maskable

0FFDCh46

USCI_B1 receive or transmit

UCB1RXIFG, UCB1TXIFG (UCB1IV) (1) (3)Maskable0FFDAh

45

(3)

TA2

TA2CCR0 CCIFG0

Maskable

0FFD8h44

TA2

TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV) (1) (3)Maskable

0FFD6h43

I/O port P2

P2IFG.0 to P2IFG.7 (P2IV) (1) (3)Maskable

0FFD4h42

RTC_A

RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG (RTCIV) (1) (3)Maskable

0FFD2h41

Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.
Interrupt flags are in the module.
Only on devices with ADC, otherwise reserved.
Detailed Description

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Table 6-1. Interrupt Sources, Flags, and Vectors (continued)(5)

INTERRUPT SOURCEINTERRUPT FLAG

Reserved

Reserved (5)SYSTEM
INTERRUPT

WORD
ADDRESSPRIORITY

0FFD0h40⋮⋮

0FF80h0, lowest

Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintaincompatibility with other devices, TI recommends reserving these locations.

6.4

Memory Organization
Table 6-2 summarizes the memory map for all device variants.
Table 6-2. Memory Organization (1)Memory (flash)
Main: interrupt vector

MSP430F5340

MSP430F5341

MSP430F5342

Total Size

64KB
00FFFFh to 00FF80h

96KB
00FFFFh to 00FF80h

128KB
00FFFFh to 00FF80h

Bank D

N/A

N/A

32KB
0243FFh to 01C400h

Bank C

N/A

32KB
01C3FFh to 014400h

32KB
01C3FFh to 014400h

Bank B

32KB
0143FFh to 00C400h

32KB
0143FFh to 00C400h

32KB
0143FFh to 00C400h

Bank A

32KB
00C3FFh to 004400h

32KB
00C3FFh to 004400h

32KB
00C3FFh to 004400h

Sector 3

N/A

N/A

2 KB
0043FFh to 003C00h

Sector 2

N/A

2KB
003BFFh to 003400h

2KB
003BFFh to 003400h

Sector 1

2KB
0033FFh to 002C00h

2KB0033FFh to 002C00h

2KB0033FFh to 002C00h

Sector 0

2KB
002BFFh to 002400h

2KB
002BFFh to 002400h

2KB
002BFFh to 002400h

Sector 7

2KB
0023FFh to 001C00h

2KB
0023FFh to 001C00h

2KB
0023FFh to 001C00h

Info A

128 B
0019FFh to 001980h

128 B
0019FFh to 001980h

128 B
0019FFh to 001980hInfo B

128 B
00197Fh to 001900h

128 B
00197Fh to 001900h

128 B
00197Fh to 001900h

Info C

128 B
0018FFh to 001880h

128 B
0018FFh to 001880h

128 B
0018FFh to 001880hInfo D

128 B
00187Fh to 001800h

128 B
00187Fh to 001800h

128 B
00187Fh to 001800h

BSL 3

512 B
0017FFh to 001600h

512 B
0017FFh to 001600h

512 B
0017FFh to 001600h

BSL 2

512 B
0015FFh to 001400h

512 B
0015FFh to 001400h

512 B
0015FFh to 001400h

BSL 1

512 B
0013FFh to 001200h

512 B
0013FFh to 001200h

512 B
0013FFh to 001200h

BSL 0

512 B
0011FFh to 001000h

512 B
0011FFh to 001000h

512 B
0011FFh to 001000h

Size

4KB
000FFFh to 0h

4KB
000FFFh to 0h

4KB
000FFFh to 0h

Main: code memory

RAM

Information memory (flash)

Bootloader (BSL) memory(flash)Peripherals(1)

N/A = Not available

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Bootloader (BSL)
The BSL lets users program the flash memory or RAM using a UART serial interface. Access to thedevice memory through the BSL is protected by an user-defined password. Table 6-3 lists the pins thatare required to use the BSL. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO andTEST/SBWTCK pins. For further details on interfacing to development tools and device programmers, see
the MSP430 Hardware Tools User's Guide. For complete description of the features of the BSL and its
implementation, see MSP430 Flash Device Bootloader (BSL) User's Guide.
Table 6-3. BSL Pin Requirements and Functions
DEVICE SIGNALBSL FUNCTION

RST/NMI/SBWTDIO

Entry sequence signal

TEST/SBWTCK

Entry sequence signal

P1.1

Data transmit

6.6

JTAG Operation

6.6.1

JTAG Standard Interface

P1.2

Data receive

VCC

Power supply

VSS

Ground supply

The MSP430 family supports the standard JTAG interface which requires four signals for sending andreceiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used toenable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. Table 6-4 lists the JTAG pin requirements. For
further details on interfacing to development tools and device programmers, see the MSP430 Hardware
Tools User's Guide. For a complete description of the features of the JTAG interface and its
implementation, see MSP430 Programming With the JTAG Interface.
Table 6-4. JTAG Pin Requirements and Functions

6.6.2

DEVICE SIGNAL

DIRECTIONFUNCTION

PJ.3/TCKIN

JTAG clock input

PJ.2/TMSIN

JTAG state control

PJ.1/TDI/TCLKIN

JTAG data input, TCLK input

PJ.0/TDOOUTJTAG data output

TEST/SBWTCKIN

Enable JTAG pins

RST/NMI/SBWTDIO

IN

External reset

VCC

Power supply

VSS

Ground supply

Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wireinterface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers.
Table 6-5 lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing todevelopment tools and device programmers, see the MSP430 Hardware Tools User's Guide. For acomplete description of the features of the JTAG interface and its implementation, see MSP430
Programming With the JTAG Interface.

42

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Table 6-5. Spy-Bi-Wire Pin Requirements and Functions

6.7

DEVICE SIGNAL

DIRECTIONFUNCTION

TEST/SBWTCKIN

Spy-Bi-Wire clock input

RST/NMI/SBWTDIO

IN, OUT

Spy-Bi-Wire data input/output

VCC

Power supply

VSS

Ground supply

Flash Memory
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-systemby the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
Features of the flash memory include:•

Flash memory has n segments of main memory and four segments of information memory (A to D) of 128 bytes
each. Each segment in main memory is 512 bytes in size.
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually. Segments A to D are also called information memory.
Segment A can be locked separately.

•
•
•

6.8

RAM
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage;
however, all data are lost. Features of the RAM include:
•
•
•

6.9

RAM has n sectors. See Section 6.4 for the size of a sector.
Each sector 0 to n can be complete disabled; however, data retention is lost.
Each sector 0 to n automatically enters low power retention mode when possible.

Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430F5xx and
MSP430F6xx Family User's Guide.

6.9.1

Digital I/O
Up to eight 8-bit I/O ports are implemented. For 80-pin options, P1, P2, P3, P4, P5, P6, and P7 arecomplete, and P8 is reduced to 3-bit I/O. For 64-pin options, P3 and P5 are reduced to 5-bit I/O and 6-bit
I/O, respectively, and P7 and P8 are completely removed. Port PJ contains four individual I/O ports,
common to all devices.
•
•
•
•
•
•
•

6.9.2

All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Pullup or pulldown on all ports is programmable.
Drive strength on all ports is programmable.
Edge-selectable interrupt and LPM4.5 wake-up input capability available for all bits of ports P1 and P2.
Read and write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise (P1 through P8) or word-wise in pairs (PA through PD).

Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4(see Table 6-6). Table 6-7 lists the default settings for all pins that support port mapping.
Table 6-6. Port Mapping Mnemonics and Functions

VALUE

PxMAPy MNEMONICINPUT PIN FUNCTIONOUTPUT PIN FUNCTION0

PM_NONE

None

DVSS

PM_CBOUT0–Comparator_B output

PM_TB0CLK

TB0 clock input–

1

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Table 6-6. Port Mapping Mnemonics and Functions (continued)
VALUE
2

INPUT PIN FUNCTIONOUTPUT PIN FUNCTION

PM_ADC12CLK–ADC12CLK

PM_DMAE0

DMAE0 input–

PM_SVMOUT–

SVM output

PM_TB0OUTH

TB0 high-impedance input TB0OUTH–

4

PM_TB0CCR0A

TB0 CCR0 capture input CCI0A

TB0 CCR0 compare output Out05

PM_TB0CCR1A

TB0 CCR1 capture input CCI1A

TB0 CCR1 compare output Out1

6

PM_TB0CCR2A

TB0 CCR2 capture input CCI2A

TB0 CCR2 compare output Out2

7

PM_TB0CCR3A

TB0 CCR3 capture input CCI3A

TB0 CCR3 compare output Out3

8

PM_TB0CCR4A

TB0 CCR4 capture input CCI4A

TB0 CCR4 compare output Out4

9

PM_TB0CCR5A

TB0 CCR5 capture input CCI5A

TB0 CCR5 compare output Out5

10

PM_TB0CCR6A

TB0 CCR6 capture input CCI6A

TB0 CCR6 compare output Out6

3

11
12
13
14
15
16

PM_UCA1RXD

USCI_A1 UART RXD (Direction controlled by USCI – input)

PM_UCA1SOMIUSCI_A1 SPI slave out master in (direction controlled by USCI)PM_UCA1TXDUSCI_A1 UART TXD (Direction controlled by USCI – output)

PM_UCA1SIMO

USCI_A1 SPI slave in master out (direction controlled by USCI)PM_UCA1CLKUSCI_A1 clock input/output (direction controlled by USCI)PM_UCB1STE

USCI_B1 SPI slave transmit enable (direction controlled by USCI)PM_UCB1SOMIUSCI_B1 SPI slave out master in (direction controlled by USCI)PM_UCB1SCLUSCI_B1 I2C clock (open drain and direction controlled by USCI)PM_UCB1SIMO

USCI_B1 SPI slave in master out (direction controlled by USCI)PM_UCB1SDAUSCI_B1 I2C data (open drain and direction controlled by USCI)PM_UCB1CLKUSCI_B1 clock input/output (direction controlled by USCI)PM_UCA1STE

USCI_A1 SPI slave transmit enable (direction controlled by USCI)17

PM_CBOUT1

None

Comparator_B output

18

PM_MCLK

None

MCLK

19-30

Reserved

None

DVSS

31 (0FFh) (1)(1)

PxMAPy MNEMONIC

Disables the output driver and the input Schmitt-trigger to prevent parasitic
cross currents when applying analog signals.

PM_ANALOG

The value of the PM_ANALOG mnemonic is 0FFh. The port mapping registers are 5 bits wide, and the upper bits are ignored, which
results in a read out value of 31.

Table 6-7. Default Mapping

44

PIN

PxMAPy MNEMONIC

P4.0/P4MAP0

PM_UCB1STE/PM_UCA1CLKUSCI_B1 SPI slave transmit enable (direction controlled by USCI)USCI_A1 clock input/output (direction controlled by USCI)

P4.1/P4MAP1

PM_UCB1SIMO/PM_UCB1SDAUSCI_B1 SPI slave in master out (direction controlled by USCI)USCI_B1 I2C data (open drain and direction controlled by USCI)

P4.2/P4MAP2

PM_UCB1SOMI/PM_UCB1SCLUSCI_B1 SPI slave out master in (direction controlled by USCI)USCI_B1 I2C clock (open drain and direction controlled by USCI)

P4.3/P4MAP3

PM_UCB1CLK/PM_UCA1STE

USCI_A1 SPI slave transmit enable (direction controlled by USCI)USCI_B1 clock input/output (direction controlled by USCI)

P4.4/P4MAP4PM_UCA1TXD/PM_UCA1SIMO

USCI_A1 UART TXD (Direction controlled by USCI – output)
USCI_A1 SPI slave in master out (direction controlled by USCI)

P4.5/P4MAP5

PM_UCA1RXD/PM_UCA1SOMIUSCI_A1 UART RXD (Direction controlled by USCI – input)
USCI_A1 SPI slave out master in (direction controlled by USCI)

P4.6/P4MAP6

PM_NONE

None

DVSS

P4.7/P4MAP7

PM_NONE

None

DVSS

Detailed Description

INPUT PIN FUNCTIONOUTPUT PIN FUNCTION

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6.9.3

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Oscillator and System Clock
The clock system is supported by the Unified Clock System (UCS) module that includes support for a 32kHz watch crystal oscillator (XT1 LF mode; XT1 HF mode not supported), an internal very-low-power lowfrequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal
digitally controlled oscillator (DCO), and a high-frequency crystal oscillator (XT2). The UCS module isdesigned to meet the requirements of both low system cost and low power consumption. The UCS modulefeatures a digital frequency-locked loop (FLL) that, in conjunction with a digital modulator, stabilizes the
DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal DCO
provides a fast turnon clock source and stabilizes in 3.5 µs (typical). The UCS module provides thefollowing clock signals:
•

•
•
•

6.9.4

Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the internal
low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally controlled
oscillator (DCO).
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by the same sources madeavailable to ACLK.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by thesame sources made available to ACLK.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device andcontains programmable output levels to provide for power optimization. The PMM also includes supply
voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection.
The brownout circuit is implemented to provide the proper internal reset signal to the device during poweron and power-off. The SVS and SVM circuitry detects if the supply voltage drops below a user-selectablelevel and supports both supply voltage supervision (the device is automatically reset) and supply voltage
monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary
supply and core supply.

6.9.5

Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication
as well as signed and unsigned multiply-and-accumulate operations.

6.9.6

Real-Time Clock (RTC_A)
The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated
real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit
timers that can be cascaded to form a 16-bit timer or counter. Both timers can be read and written bysoftware. Calendar mode integrates an internal calendar that compensates for months with less than
31 days and includes leap year correction. The RTC_A also supports flexible alarm functions and offsetcalibration hardware.

6.9.7

Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the module can be configured as an interval timer and can generateinterrupts at selected time intervals.

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System Module (SYS)The SYS module handles many of the system functions within the device. These include power on resetand power up clear handling, NMI source selection and management, reset interrupt vector generators,
bootloader entry mechanisms, as well as configuration management (device descriptors). The SYS
module also includes a data exchange mechanism through JTAG called a JTAG mailbox that can be usedin the application. Table 6-8 lists the interrupt vector registers of the SYS module.
Table 6-8. System Module Interrupt Vector Registers

INTERRUPT VECTOR REGISTERSYSRSTIV, System ResetSYSSNIV, System NMISYSUNIV, User NMI

46

Detailed Description

ADDRESS

019Eh

019Ch

019Ah

INTERRUPT EVENT

VALUE

No interrupt pending

00h

Brownout (BOR)02h

RST/NMI (POR)

04h

PMMSWBOR (BOR)

06h

Wakeup from LPMx.5

08h

Security violation (BOR)

0Ah

SVSL (POR)

0Ch

SVSH (POR)

0Eh

SVML_OVP (POR)10h

SVMH_OVP (POR)

12h

PMMSWPOR (POR)

14h

WDT time-out (PUC)16h

WDT password violation (PUC)18h

KEYV flash password violation (PUC)

1Ah

Reserved

1Ch

Peripheral area fetch (PUC)

1Eh

PMM password violation (PUC)

20h

Reserved

22h to 3Eh

No interrupt pending

00h

SVMLIFG02h

SVMHIFG04h

SVSMLDLYIFG

06h

SVSMHDLYIFG

08h

VMAIFG0Ah

JMBINIFG

0Ch

JMBOUTIFG

0Eh

SVMLVLRIFG

10h

SVMHVLRIFG

12h

Reserved

14h to 1Eh

No interrupt pending

00h

NMIIFG

02h

OFIFG

04h

ACCVIFG

06h

Reserved

08h

Reserved

0Ah to 1Eh

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DMA Controller
The DMA controller allows movement of data from one memory address to another without CPUintervention. For example, the DMA controller can move data from the ADC12_A conversion memory toRAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller
reduces system power consumption by allowing the CPU to remain in sleep mode, without having toawaken to move data to or from a peripheral. Table 6-9 lists the available DMA triggers.
Table 6-9. DMA Trigger Assignments (1)TRIGGER(1)

CHANNEL01

2

0

DMAREQDMAREQDMAREQ

1

TA0CCR0 CCIFG

TA0CCR0 CCIFG

TA0CCR0 CCIFG

2

TA0CCR2 CCIFG

TA0CCR2 CCIFG

TA0CCR2 CCIFG

3

TA1CCR0 CCIFG

TA1CCR0 CCIFG

TA1CCR0 CCIFG

4

TA1CCR2 CCIFG

TA1CCR2 CCIFG

TA1CCR2 CCIFG

5

TA2CCR0 CCIFG

TA2CCR0 CCIFG

TA2CCR0 CCIFG

6

TA2CCR2 CCIFG

TA2CCR2 CCIFG

TA2CCR2 CCIFG

7

TB0CCR0 CCIFG

TB0CCR0 CCIFG

TB0CCR0 CCIFG

8

TB0CCR2 CCIFG

TB0CCR2 CCIFG

TB0CCR2 CCIFG

9

Reserved

Reserved

Reserved

10

Reserved

Reserved

Reserved

11

Reserved

Reserved

Reserved

12

Reserved

Reserved

Reserved

13

Reserved

Reserved

Reserved

14

Reserved

Reserved

Reserved

15

Reserved

Reserved

Reserved

16

UCA0RXIFGUCA0RXIFGUCA0RXIFG

17

UCA0TXIFGUCA0TXIFGUCA0TXIFG

18

UCB0RXIFGUCB0RXIFGUCB0RXIFG

19

UCB0TXIFGUCB0TXIFGUCB0TXIFG

20

UCA1RXIFGUCA1RXIFGUCA1RXIFG

21

UCA1TXIFGUCA1TXIFGUCA1TXIFG

22

UCB1RXIFGUCB1RXIFGUCB1RXIFG

23

UCB1TXIFGUCB1TXIFGUCB1TXIFG24

ADC12IFGx

ADC12IFGx

ADC12IFGx

25

Reserved

Reserved

Reserved

26

Reserved

Reserved

Reserved

27

Reserved

Reserved

Reserved

28

Reserved

Reserved

Reserved

29

MPY ready

MPY ready

MPY ready30

DMA2IFGDMA0IFGDMA1IFG

31

DMAE0

DMAE0

DMAE0

If a reserved trigger source is selected, no trigger is generated.

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6.9.10 Universal Serial Communication Interface (USCI)The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3- or 4-pin) and I2C, and asynchronous communication protocols
such as UART, enhanced UART with automatic baud-rate detection, and IrDA. Each USCI module
contains two portions, A and B.
The USCI_An module provides support for SPI (3- or 4-pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3- or 4-pin) or I2C.
The MSP430F534x MCUs include two complete USCI modules (n = 0, 1).

6.9.11 TA0
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple
captures or compares, PWM outputs, and interval timing (see Table 6-10). TA0 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from eachof the capture/compare registers.
Table 6-10. TA0 Signal Connections
INPUT PINNUMBER

DEVICE INPUTSIGNAL

MODULEINPUT SIGNAL

13-P1.0

TA0CLKTACLK

ACLK (internal)

ACLK

SMCLK
(internal)

SMCLK

13-P1.0

TA0CLK

TACLK

14-P1.1

TA0.0

CCI0A

DVSS

CCI0B

DVSS

GND

15-P1.2

16-P1.3

17-P1.4

18-P1.5

48

MODULEBLOCK

MODULEOUTPUT
SIGNALDEVICEOUTPUT
SIGNAL

Timer

N/A

N/A

OUTPUT PIN NUMBER

14-P1.1
CCR0

TA0

TA0.0

DVCC

VCC

TA0.1

CCI1A

15-P1.2

CBOUT(internal)

CCI1B

ADC12 (internal)
ADC12SHSx = {1}

DVSS

GND

DVCC

VCC

TA0.2

CCI2A

ACLK (internal)

CCI2B

DVSS

GND

DVCC

VCC

TA0.3

CCI3A

DVSS

CCI3B

DVSS

GND

DVCC

VCC

TA0.4

CCI4A

DVSS

CCI4B

DVSS

GND

DVCC

VCC

Detailed Description

CCR1

TA1

TA0.1

16-P1.3
CCR2

TA2

TA0.2

17-P1.4
CCR3

TA3

TA0.3

18-P1.5
CCR4

TA4

TA0.4

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6.9.12 TA1
TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support
multiple captures or compares, PWM outputs, and interval timing (see Table 6-11). TA1 also has
extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions andfrom each of the capture/compare registers.
Table 6-11. TA1 Signal Connections
INPUT PINNUMBER

DEVICE INPUTSIGNAL

MODULE INPUTSIGNAL19-P1.6

TA1CLKTACLK

ACLK (internal)

ACLK

SMCLK (internal)

SMCLK

19-P1.6

TA1CLK

TACLK

20-P1.7

TA1.0

CCI0A

DVSS

CCI0B

DVSS

GND

DVCC

VCC

Not available

Not available

TA1.1

CCI1A

CBOUT (internal)

CCI1B

DVSS

GND

DVCC

VCC

TA1.2

CCI2A

ACLK (internal)

CCI2B

DVSS

GND

DVCC

VCC

MODULE BLOCK

Timer

MODULEDEVICE OUTPUTOUTPUT SIGNAL
SIGNALN/A

OUTPUT PIN
NUMBER

N/A

20-P1.7
CCR0

TA0

TA1.0

Not available
CCR1

TA1

TA1.1

Not available
CCR2

TA2

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6.9.13 TA2
TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA2 can support
multiple captures or compares, PWM outputs, and interval timing (see Table 6-12). TA2 also has
extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions andfrom each of the capture/compare registers.
Table 6-12. TA2 Signal Connections
INPUT PINNUMBER

DEVICE INPUTSIGNAL

MODULE INPUTSIGNALNot available

TA2CLKTACLK

ACLK (internal)

ACLK

SMCLK (internal)

SMCLK

Not available

TA2CLK

TACLK

Not available

TA2.0

CCI0A

DVSS

CCI0B

DVSS

GND

DVCC

VCC

Not available

Not available

50

TA2.1

CCI1A

CBOUT (internal)

CCI1B

DVSS

GND

DVCC

VCC

TA2.2

CCI2A

ACLK (internal)

CCI2B

DVSS

GND

DVCC

VCC

Detailed Description

MODULE BLOCK

Timer

MODULEDEVICE OUTPUTOUTPUT SIGNAL
SIGNALN/A

OUTPUT PIN
NUMBER

N/A

Not available
CCR0

TA0

TA2.0

Not available
CCR1

TA1

TA2.1

Not available
CCR2

TA2

TA2.2

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6.9.14 TB0
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 can support
multiple captures or compares, PWM outputs, and interval timing (see Table 6-13). TB0 also has
extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions andfrom each of the capture/compare registers.
Table 6-13. TB0 Signal Connections
INPUT PINNUMBER (1)37-P5.7(1)

DEVICE INPUTSIGNAL

MODULEINPUT SIGNAL

TB0CLKTBCLKACLK (internal)

ACLK

SMCLK
(internal)

SMCLK

TB0CLK

TBCLK

TB0.0

CCI0A

TB0.0

CCI0B

DVSS

GND

DVCC

VCC

TB0.1

CCI1A

CBOUT
(internal)

CCI1B

DVSS

GND

DVCC

VCC

TB0.2

CCI2A

TB0.2

CCI2B

DVSS

GND

DVCC

VCC

TB0.3

CCI3A

TB0.3

CCI3B

DVSS

GND

DVCC

VCC

TB0.4

CCI4A

TB0.4

CCI4B

DVSS

GND

DVCC

VCC

TB0.5

CCI5A

TB0.5

CCI5B

DVSS

GND

DVCC

VCC

TB0.6

CCI6A

ACLK (internal)

CCI6B

DVSS

GND

DVCC

VCC

MODULEBLOCK

MODULEOUTPUT
SIGNALDEVICEOUTPUT
SIGNAL

Timer

N/A

N/A

CCR0

TB0

TB0.0

OUTPUT PIN
NUMBER (1)ADC12 (internal)
ADC12SHSx = {2}37-P5.7
CCR1

TB1

TB0.1

CCR2

TB2

TB0.2

CCR3

TB3

TB0.3

CCR4

TB4

TB0.4

CCR5

TB5

TB0.5

CCR6

TB6

TB0.6

ADC12 (internal)
ADC12SHSx = {3}Timer functions selectable through the port mapping controller.

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6.9.15 Comparator_B
The primary function of the Comparator_B module is to support precision slope analog-to-digitalconversions, battery voltage supervision, and monitoring of external analog signals.

6.9.16 ADC12_A
The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit
SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored
without any CPU intervention.

6.9.17 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

6.9.18 Reference (REF) Module Voltage Reference
The REF module generates all critical reference voltages that can be used by the various analog
peripherals in the device.

6.9.19 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The L version of the EEM has the following features:• Eight hardware triggers or breakpoints on memory access• Two hardware trigger or breakpoint on CPU register write access• Up to 10 hardware triggers can be combined to form complex triggers or breakpoints• Two cycle counters• Sequencer• State storage• Clock control on module level

52

Detailed Description

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6.9.20 Peripheral File Map
Table 6-14 lists the base address for all of the peripherals that are available. Table 6-15 through Table 641 list the registers available in each peripheral.
Table 6-14. Peripherals
MODULE NAMEBASE ADDRESSOFFSET ADDRESSRANGESpecial Functions (see Table 6-15)

0100h

000h to 01Fh

PMM (see Table 6-16)0120h000h to 010h

Flash Control (see Table 6-17)0140h000h to 00Fh

CRC16 (see Table 6-18)0150h000h to 007h

RAM Control (see Table 6-19)0158h

000h to 001h

Watchdog (see Table 6-20)015Ch000h to 001h

UCS (see Table 6-21)0160h000h to 01Fh

SYS (see Table 6-22)0180h000h to 01Fh

Shared Reference (see Table 6-23)01B0h000h to 001h

Port Mapping Control (see Table 6-24)

01C0h

000h to 002h

Port Mapping Port P4 (see Table 6-24)01E0h000h to 007h

Port P1 and P2 (see Table 6-25)0200h

000h to 01Fh

Port P3 and P4 (see Table 6-26)0220h000h to 00Bh

Port P5 and P6 (see Table 6-27)0240h000h to 00Bh

Port PJ (see Table 6-28)0320h000h to 01Fh

TA0 (see Table 6-29)0340h000h to 02Eh

TA1 (see Table 6-30)0380h000h to 02Eh

TB0 (see Table 6-31)

03C0h

000h to 02Eh

TA2 (see Table 6-32)

0400h

000h to 02Eh

Real-Time Clock (RTC_A) (see Table 6-33)

04A0h

000h to 01Bh

32-Bit Hardware Multiplier (see Table 6-34)04C0h

000h to 02Fh

DMA General Control (see Table 6-35)0500h

000h to 00FhDMA Channel 0 (see Table 6-35)

0510h000h to 00Ah

DMA Channel 1 (see Table 6-35)0520h000h to 00Ah

DMA Channel 2 (see Table 6-35)0530h000h to 00Ah

USCI_A0 (see Table 6-36)

05C0h

000h to 01Fh

USCI_B0 (see Table 6-37)05E0h000h to 01Fh

USCI_A1 (see Table 6-38)

0600h

000h to 01Fh

USCI_B1 (see Table 6-39)0620h

000h to 01Fh

ADC12_A (see Table 6-40)

0700h

000h to 03Eh

Comparator_B (see Table 6-41)08C0h

000h to 00Fh

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Table 6-15. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTIONREGISTEROFFSETSFR interrupt enable

SFRIE100h

SFR interrupt flag

SFRIFG102h

SFR reset pin control

SFRRPCR

04h

Table 6-16. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTIONREGISTEROFFSET

PMM control 0

PMMCTL000h

PMM control 1

PMMCTL102h

SVS high-side control

SVSMHCTL

04h

SVS low-side control

SVSMLCTL

06h

PMM interrupt flags

PMMIFG0Ch

PMM interrupt enable

PMMIE

0Eh

PMM power mode 5 control

PM5CTL010h

Table 6-17. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTIONREGISTEROFFSET

Flash control 1

FCTL1

00h

Flash control 3

FCTL3

04h

Flash control 4

FCTL4

06h

Table 6-18. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTIONREGISTEROFFSET

CRC data input

CRC16DI00h

CRC data input reverse byte

CRCDIRB

02h

CRC initialization and result

CRCINIRES

04h

CRC result reverse byte

CRCRESR

06h

Table 6-19. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM control 0

REGISTERRCCTL0OFFSET
00h

Table 6-20. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control

54

Detailed Description

REGISTERWDTCTLOFFSET
00h

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Table 6-21. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTIONREGISTEROFFSETUCS control 0

UCSCTL000h

UCS control 1

UCSCTL102h

UCS control 2

UCSCTL204h

UCS control 3

UCSCTL306h

UCS control 4

UCSCTL408h

UCS control 5

UCSCTL50Ah

UCS control 6

UCSCTL60Ch

UCS control 7

UCSCTL70Eh

UCS control 8

UCSCTL8

10h

Table 6-22. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTIONREGISTEROFFSET

System control

SYSCTL00h

Bootloader configuration area

SYSBSLC

02h

JTAG mailbox control

SYSJMBC

06h

JTAG mailbox input 0

SYSJMBI008h

JTAG mailbox input 1

SYSJMBI1

0Ah

JTAG mailbox output 0

SYSJMBO00Ch

JTAG mailbox output 1

SYSJMBO1

0Eh

Bus error vector generator

SYSBERRIV

18h

User NMI vector generator

SYSUNIV

1Ah

System NMI vector generator

SYSSNIV

1Ch

Reset vector generator

SYSRSTIV

1Eh

Table 6-23. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control

REGISTEROFFSET

REFCTL

00h

Table 6-24. Port Mapping Registers(Base Address of Port Mapping Control: 01C0h, Port P4: 01E0h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port mapping key/ID

PMAPKEYID

00h

Port mapping control

PMAPCTL

02h

Port P4.0 mapping

P4MAP000h

Port P4.1 mapping

P4MAP101h

Port P4.2 mapping

P4MAP202h

Port P4.3 mapping

P4MAP303hPort P4.4 mapping

P4MAP404h

Port P4.5 mapping

P4MAP505h

Port P4.6 mapping

P4MAP606h

Port P4.7 mapping

P4MAP707h

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Table 6-25. Port P1 and P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P1 input

P1IN

00h

Port P1 output

P1OUT

02h

Port P1 direction

P1DIR

04h

Port P1 resistor enable

P1REN

06h

Port P1 drive strength

P1DS

08h

Port P1 selection

P1SEL

0Ah

Port P1 interrupt vector word

P1IV

0Eh

Port P1 interrupt edge select

P1IES

18h

Port P1 interrupt enable

P1IE

1Ah

Port P1 interrupt flag

P1IFG

1Ch

Port P2 input

P2IN

01h

Port P2 output

P2OUT

03h

Port P2 direction

P2DIR

05h

Port P2 resistor enable

P2REN

07h

Port P2 drive strength

P2DS

09h

Port P2 selection

P2SEL

0Bh

Port P2 interrupt vector word

P2IV

1Eh

Port P2 interrupt edge select

P2IES

19h

Port P2 interrupt enable

P2IE

1Bh

Port P2 interrupt flag

P2IFG

1Dh

Table 6-26. Port P3 and P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P3 input

P3IN

00h

Port P3 output

P3OUT

02h

Port P3 direction

P3DIR

04h

Port P3 resistor enable

P3REN

06h

Port P3 drive strength

P3DS

08h

Port P3 selection

P3SEL

0Ah

Port P4 input

P4IN

01h

Port P4 output

P4OUT

03h

Port P4 direction

P4DIR

05h

Port P4 resistor enable

P4REN

07h

Port P4 drive strength

P4DS

09h

Port P4 selection

P4SEL

0Bh

56

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Table 6-27. Port P5 and P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P5 input

P5IN

00h

Port P5 output

P5OUT

02h

Port P5 direction

P5DIR

04h

Port P5 resistor enable

P5REN

06h

Port P5 drive strength

P5DS

08h

Port P5 selection

P5SEL

0Ah

Port P6 input

P6IN

01h

Port P6 output

P6OUT

03h

Port P6 direction

P6DIR

05h

Port P6 resistor enable

P6REN

07h

Port P6 drive strength

P6DS

09h

Port P6 selection

P6SEL

0Bh

Table 6-28. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port PJ input

PJIN

00h

Port PJ output

PJOUT

02h

Port PJ direction

PJDIR

04h

Port PJ resistor enable

PJREN

06h

Port PJ drive strength

PJDS

08h

Table 6-29. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTIONREGISTEROFFSETTA0 control

TA0CTL00h

Capture/compare control 0

TA0CCTL002h

Capture/compare control 1

TA0CCTL1

04h

Capture/compare control 2

TA0CCTL2

06h

Capture/compare control 3

TA0CCTL3

08h

Capture/compare control 4

TA0CCTL4

0Ah

TA0 counter

TA0R

10h

Capture/compare 0

TA0CCR012h

Capture/compare 1

TA0CCR1

14h

Capture/compare 2

TA0CCR2

16h

Capture/compare 3

TA0CCR3

18h

Capture/compare 4

TA0CCR4

1Ah

TA0 expansion 0

TA0EX020h

TA0 interrupt vector

TA0IV

2Eh

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Table 6-30. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTIONREGISTEROFFSETTA1 control

TA1CTL00h

Capture/compare control 0

TA1CCTL002h

Capture/compare control 1

TA1CCTL1

04h

Capture/compare control 2

TA1CCTL2

06h

TA1 counter

TA1R

10h

Capture/compare 0

TA1CCR012h

Capture/compare 1

TA1CCR1

14h

Capture/compare 2

TA1CCR216h

TA1 expansion 0

TA1EX020h

TA1 interrupt vector

TA1IV

2Eh

Table 6-31. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTIONREGISTEROFFSET

TB0 control

TB0CTL00h

Capture/compare control 0

TB0CCTL002h

Capture/compare control 1

TB0CCTL1

04h

Capture/compare control 2

TB0CCTL2

06h

Capture/compare control 3

TB0CCTL3

08h

Capture/compare control 4

TB0CCTL4

0Ah

Capture/compare control 5

TB0CCTL5

0Ch

Capture/compare control 6

TB0CCTL60Eh

TB0 counter

TB0R

10h

Capture/compare 0

TB0CCR012h

Capture/compare 1

TB0CCR1

14h

Capture/compare 2

TB0CCR2

16h

Capture/compare 3

TB0CCR3

18h

Capture/compare 4

TB0CCR4

1Ah

Capture/compare 5

TB0CCR5

1Ch

Capture/compare 6

TB0CCR6

1Eh

TB0 expansion 0

TB0EX020h

TB0 interrupt vector

TB0IV

2Eh

Table 6-32. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTIONREGISTEROFFSETTA2 control

TA2CTL00h

Capture/compare control 0

TA2CCTL002h

Capture/compare control 1

TA2CCTL1

04h

Capture/compare control 2

TA2CCTL2

06h

TA2 counter

TA2R

10h

Capture/compare 0

TA2CCR012h

Capture/compare 1

TA2CCR1

14h

Capture/compare 2

TA2CCR216h

TA2 expansion 0

TA2EX020h

TA2 interrupt vector

TA2IV

2Eh

58

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Table 6-33. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTIONREGISTEROFFSET

RTC control 0

RTCCTL000h

RTC control 1

RTCCTL101h

RTC control 2

RTCCTL202h

RTC control 3

RTCCTL303h

RTC prescaler 0 control

RTCPS0CTL

08h

RTC prescaler 1 control

RTCPS1CTL

0Ah

RTC prescaler 0

RTCPS00Ch

RTC prescaler 1

RTCPS10Dh

RTC interrupt vector word

RTCIV

0Eh

RTC seconds, RTC counter 1

RTCSEC, RTCNT1

10h

RTC minutes, RTC counter 2

RTCMIN, RTCNT2

11h

RTC hours, RTC counter 3

RTCHOUR, RTCNT3

12h

RTC day of week, RTC counter 4

RTCDOW, RTCNT4

13h

RTC days

RTCDAY

14h

RTC month

RTCMON15h

RTC year low

RTCYEARL

16h

RTC year high

RTCYEARH

17h

RTC alarm minutes

RTCAMIN

18h

RTC alarm hours

RTCAHOUR

19h

RTC alarm day of week

RTCADOW

1Ah

RTC alarm days

RTCADAY

1Bh

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Table 6-34. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTIONREGISTEROFFSET

16-bit operand 1 – multiply

MPY

00h

16-bit operand 1 – signed multiply

MPYS

02h

16-bit operand 1 – multiply accumulate

MAC

04h

16-bit operand 1 – signed multiply accumulate

MACS

06h

16-bit operand 2

OP2

08h

16 × 16 result low word

RESLO

0Ah

16 × 16 result high word

RESHI

0Ch

16 × 16 sum extension

SUMEXT0Eh

32-bit operand 1 – multiply low word

MPY32L10h

32-bit operand 1 – multiply high word

MPY32H12h32-bit operand 1 – signed multiply low word

MPYS32L

14h

32-bit operand 1 – signed multiply high word

MPYS32H

16h32-bit operand 1 – multiply accumulate low word

MAC32L18h

32-bit operand 1 – multiply accumulate high word

MAC32H1Ah

32-bit operand 1 – signed multiply accumulate low word

MACS32L

1Ch

32-bit operand 1 – signed multiply accumulate high word

MACS32H

1Eh32-bit operand 2 – low word

OP2L

20h

32-bit operand 2 – high word

OP2H

22h

32 × 32 result 0 – least significant word

RES0

24h

32 × 32 result 1

RES1

26h

32 × 32 result 2

RES2

28h

32 × 32 result 3 – most significant word

RES3

2Ah

MPY32 control 0

MPY32CTL02Ch60Detailed Description

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Table 6-35. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTIONREGISTEROFFSET

DMA channel 0 control

DMA0CTL

00h

DMA channel 0 source address low

DMA0SAL

02h

DMA channel 0 source address high

DMA0SAH04h

DMA channel 0 destination address low

DMA0DAL

06h

DMA channel 0 destination address high

DMA0DAH08h

DMA channel 0 transfer size

DMA0SZ

0Ah

DMA channel 1 control

DMA1CTL

00h

DMA channel 1 source address low

DMA1SAL

02h

DMA channel 1 source address high

DMA1SAH04h

DMA channel 1 destination address low

DMA1DAL

06h

DMA channel 1 destination address high

DMA1DAH08h

DMA channel 1 transfer size

DMA1SZ

0Ah

DMA channel 2 control

DMA2CTL

00h

DMA channel 2 source address low

DMA2SAL

02h

DMA channel 2 source address high

DMA2SAH04h

DMA channel 2 destination address low

DMA2DAL

06h

DMA channel 2 destination address high

DMA2DAH08h

DMA channel 2 transfer size

DMA2SZ

0Ah

DMA module control 0

DMACTL000h

DMA module control 1

DMACTL102h

DMA module control 2

DMACTL204h

DMA module control 3

DMACTL306h

DMA module control 4

DMACTL408h

DMA interrupt vector

DMAIV

0Eh

Table 6-36. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTIONREGISTEROFFSETUSCI control 1

UCA0CTL100h

USCI control 0

UCA0CTL0

01h

USCI baud rate 0

UCA0BR006h

USCI baud rate 1

UCA0BR107h

USCI modulation control

UCA0MCTL

08h

USCI status

UCA0STAT

0Ah

USCI receive buffer

UCA0RXBUF

0Ch

USCI transmit buffer

UCA0TXBUF

0Eh

USCI LIN control

UCA0ABCTL

10h

USCI IrDA transmit control

UCA0IRTCTL

12h

USCI IrDA receive control

UCA0IRRCTL

13h

USCI interrupt enable

UCA0IE1Ch

USCI interrupt flags

UCA0IFG

1Dh

USCI interrupt vector word

UCA0IV

1Eh

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Table 6-37. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTIONREGISTEROFFSETUSCI synchronous control 1

UCB0CTL100h

USCI synchronous control 0

UCB0CTL0

01h

USCI synchronous bit rate 0

UCB0BR006h

USCI synchronous bit rate 1

UCB0BR107h

USCI synchronous status

UCB0STAT

0Ah

USCI synchronous receive buffer

UCB0RXBUF

0Ch

USCI synchronous transmit buffer

UCB0TXBUF

0Eh

USCI I2C own address

UCB0I2COA

10h

USCI I2C slave address

UCB0I2CSA

12h

USCI interrupt enable

UCB0IE1Ch

USCI interrupt flags

UCB0IFG

1Dh

USCI interrupt vector word

UCB0IV

1Eh

Table 6-38. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTIONREGISTEROFFSETUSCI control 1

UCA1CTL100h

USCI control 0

UCA1CTL0

01h

USCI baud rate 0

UCA1BR006h

USCI baud rate 1

UCA1BR107h

USCI modulation control

UCA1MCTL

08h

USCI status

UCA1STAT

0Ah

USCI receive buffer

UCA1RXBUF

0Ch

USCI transmit buffer

UCA1TXBUF

0Eh

USCI LIN control

UCA1ABCTL

10h

USCI IrDA transmit control

UCA1IRTCTL

12h

USCI IrDA receive control

UCA1IRRCTL

13h

USCI interrupt enable

UCA1IE1Ch

USCI interrupt flags

UCA1IFG

1Dh

USCI interrupt vector word

UCA1IV

1Eh

Table 6-39. USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTIONREGISTEROFFSETUSCI synchronous control 1

UCB1CTL100h

USCI synchronous control 0

UCB1CTL0

01h

USCI synchronous bit rate 0

UCB1BR006h

USCI synchronous bit rate 1

UCB1BR107h

USCI synchronous status

UCB1STAT

0Ah

USCI synchronous receive buffer

UCB1RXBUF

0Ch

USCI synchronous transmit buffer

UCB1TXBUF

0Eh

USCI I2C own address

UCB1I2COA

10h

USCI I2C slave address

UCB1I2CSA

12h

USCI interrupt enable

UCB1IE1Ch

USCI interrupt flags

UCB1IFG

1Dh

USCI interrupt vector word

UCB1IV

1Eh

62

Detailed Description

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Table 6-40. ADC12_A Registers (Base Address: 0700h)
REGISTER DESCRIPTIONREGISTEROFFSET

ADC control 0

ADC12CTL000h

ADC control 1

ADC12CTL102h

ADC control 2

ADC12CTL204h

ADC interrupt flag

ADC12IFG

0Ah

ADC interrupt enable

ADC12IE

0Ch

ADC interrupt vector word

ADC12IV

0Eh

ADC memory control 0

ADC12MCTL010h

ADC memory control 1

ADC12MCTL111h

ADC memory control 2

ADC12MCTL212h

ADC memory control 3

ADC12MCTL313h

ADC memory control 4

ADC12MCTL414h

ADC memory control 5

ADC12MCTL515h

ADC memory control 6

ADC12MCTL616h

ADC memory control 7

ADC12MCTL717h

ADC memory control 8

ADC12MCTL818h

ADC memory control 9

ADC12MCTL919h

ADC memory control 10

ADC12MCTL10

1Ah

ADC memory control 11

ADC12MCTL11

1Bh

ADC memory control 12

ADC12MCTL12

1Ch

ADC memory control 13

ADC12MCTL13

1Dh

ADC memory control 14

ADC12MCTL14

1Eh

ADC memory control 15

ADC12MCTL15

1FhConversion memory 0

ADC12MEM020h

Conversion memory 1

ADC12MEM1

22h

Conversion memory 2

ADC12MEM2

24h

Conversion memory 3

ADC12MEM3

26h

Conversion memory 4

ADC12MEM428h

Conversion memory 5

ADC12MEM5

2AhConversion memory 6

ADC12MEM6

2Ch

Conversion memory 7

ADC12MEM7

2EhConversion memory 8

ADC12MEM830hConversion memory 9

ADC12MEM932h

Conversion memory 10

ADC12MEM1034h

Conversion memory 11

ADC12MEM11

36h

Conversion memory 12

ADC12MEM1238h

Conversion memory 13

ADC12MEM13

3Ah

Conversion memory 14

ADC12MEM14

3Ch

Conversion memory 15

ADC12MEM15

3Eh

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Table 6-41. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTIONREGISTEROFFSET

Comp_B control 0

CBCTL000hComp_B control 1

CBCTL102h

Comp_B control 2

CBCTL204h

Comp_B control 3

CBCTL306h

Comp_B interrupt

CBINT

0Ch

Comp_B interrupt vector word

CBIV

0Eh

64

Detailed Description

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JAJSG78F – JULY 2011 – REVISED SEPTEMBER 20186.10 Input/Output Diagrams
6.10.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
Figure 6-2 shows the port diagram. Table 6-42 summarizes the selection of the pin functions.
Pad Logic

P1REN.x

P1DIR.x0

From module

1

P1OUT.x0

From module

1

DVSS

0

DVCC

1

Direction
0: Input
1: Output

P1DS.x0: Low drive
1: High drive

P1SEL.x
P1IN.xEN
To module

1

P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0

D

P1IE.xEN

P1IRQ.x

Q
P1IFG.x

Set

P1SEL.xInterrupt
Edge
SelectP1IES.x

Figure 6-2. Port P1 (P1.0 to P1.7) Diagram

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Table 6-42. Port P1 (P1.0 to P1.7) Pin Functions
PIN NAME (P1.x)

P1.0/TA0CLK/ACLK

x

0

CONTROL BITS OR SIGNALSFUNCTION

P1DIR.x

P1SEL.x

P1.0 (I/O)

I: 0; O: 10

TA0CLK

01

ACLK
P1.1/TA0.0

1

1

1

P1.1 (I/O)

I: 0; O: 10

TA0.CCI0A

0

1

TA0.0
P1.2/TA0.1

2

1

1

P1.2 (I/O)

I: 0; O: 10

TA0.CCI1A

0

1

TA0.1
P1.3/TA0.2

P1.4/TA0.3

P1.5/TA0.4

P1.6/TA1CLK/CBOUT

P1.7/TA1.0

66

Detailed Description

3

4

5

6

7

1

1

P1.3 (I/O)

I: 0; O: 10

TA0.CCI2A

0

1

TA0.2

1

1

P1.4 (I/O)

I: 0; O: 10

TA0.CCI3A

0

1

TA0.3

1

1

P1.5 (I/O)

I: 0; O: 10

TA0.CCI4A

0

1

TA0.4

1

1

P1.6 (I/O)

I: 0; O: 10

TA1CLK

0

1

CBOUT comparator B

1

1

P1.7 (I/O)

I: 0; O: 10

TA1.CCI0A

0

1

TA1.0

1

1

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6.10.2 Port P2 (P2.7) Input/Output With Schmitt Trigger
Figure 6-3 shows the port diagram. Table 6-43 summarizes the selection of the pin functions.
Pad Logic

P2REN.x

P2DIR.x0

From module

1

P2OUT.x0

From module

1

DVSS

0

DVCC

1

1

Direction
0: Input
1: Output

P2.7/UB0STE/UCA0CLK

P2DS.x0: Low drive
1: High drive

P2SEL.x
P2IN.xEND

To module

P2IE.xEN

To moduleQ
P2IFG.x

Set

P2SEL.xInterrupt
Edge
SelectP2IES.x

Figure 6-3. Port P2 (P2.7) Diagram
Table 6-43. Port P2 (P2.7) Pin Functions
PIN NAME (P2.x)
P2.7/UCB0STE/UCA0CLK
(1)
(2)
(3)

x
7

FUNCTION
P2.7 (I/O)
UCB0STE/UCA0CLK(2) (3)

CONTROL BITS OR SIGNALS (1)P2DIR.x

P2SEL.x

I: 0; O: 1

0

X

1

X = Don't care
The pin direction is controlled by the USCI module.
UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.

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6.10.3 Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
Figure 6-4 shows the port diagram. Table 6-44 summarizes the selection of the pin functions.
Pad Logic

P3REN.x

P3DIR.x0

From module

1

P3OUT.x0

From module

1

DVSS

0

DVCC

1

1

Direction
0: Input
1: Output

P3DS.x0: Low drive
1: High drive

P3SEL.x
P3IN.xP3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
P3.4/UCA0RXD/UCA0SOMIEN
To module

D

Figure 6-4. Port P3 (P3.0 to P3.4) Diagram
Table 6-44. Port P3 (P3.0 to P3.4) Pin Functions
PIN NAME (P3.x)
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE

x
0
1
2

P3.3/UCA0TXD/UCA0SIMO

3

P3.4/UCA0RXD/UCA0SOMI

4

(1)
(2)
(3)
(4)

68

CONTROL BITS OR SIGNALS (1)FUNCTION
P3.0 (I/O)
UCB0SIMO/UCB0SDA(2) (3)P3.1 (I/O)
UCB0SOMI/UCB0SCL (2) (3)P3.2 (I/O)
UCB0CLK/UCA0STE(2) (4)P3.3 (I/O)
UCA0TXD/UCA0SIMO (2)P3.4 (I/O)
UCA0RXD/UCA0SOMI (2)P3DIR.x

P3SEL.x

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

X = Don't care
The pin direction is controlled by the USCI module.
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.

Detailed Description

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6.10.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
Figure 6-5 shows the port diagram. Table 6-45 summarizes the selection of the pin functions.
Pad Logic

P4REN.x

P4DIR.x0

From Port Mapping Control

1

P4OUT.x0

From Port Mapping Control

1

DVSS

0

DVCC

1

1

Direction
0: Input
1: Output

P4.0/P4MAP0
P4.1/P4MAP1
P4.2/P4MAP2
P4.3/P4MAP3
P4.4/P4MAP4
P4.5/P4MAP5
P4.6/P4MAP6
P4.7/P4MAP7

P4DS.x0: Low drive
1: High drive

P4SEL.x
P4IN.xEN
D

To Port Mapping Control

Figure 6-5. Port P4 (P4.0 to P4.7) Diagram
Table 6-45. Port P4 (P4.0 to P4.7) Pin Functions
PIN NAME (P4.x)

x

P4.0/P4MAP00P4.1/P4MAP1

1

P4.2/P4MAP2

2

P4.3/P4MAP3

3

P4.4/P4MAP4

4

P4.5/P4MAP5

5

P4.6/P4MAP6

6

P4.7/P4MAP7
(1)
(2)

7

FUNCTION
P4.0 (I/O)
Mapped secondary digital function
P4.1 (I/O)
Mapped secondary digital function
P4.2 (I/O)
Mapped secondary digital function
P4.3 (I/O)
Mapped secondary digital function
P4.4 (I/O)
Mapped secondary digital function
P4.5 (I/O)
Mapped secondary digital function
P4.6 (I/O)
Mapped secondary digital function
P4.7 (I/O)
Mapped secondary digital function

CONTROL BITS OR SIGNALS (1)P4DIR.x (2)P4SEL.x

I: 0; O: 1

0

X

X

1

≤ 30

I: 0; O: 1

0

X
≤ 30

P4MAPxX

1

I: 0; O: 1

0

X

X

1

≤ 30

I: 0; O: 1

0

X

X

1

≤ 30

I: 0; O: 1

0

X

X

1

≤ 30

I: 0; O: 1

0

X

X

1

≤ 30

I: 0; O: 1

0

X
≤ 30

X

1

I: 0; O: 1

0

X

X

1

≤ 30

X = Don't care
The direction of some mapped secondary functions are controlled directly by the module. See Table 6-6 for specific direction control
information of mapped secondary functions.

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6.10.5 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
Figure 6-6 shows the port diagram. Table 6-46 summarizes the selection of the pin functions.
Pad Logic

To or from
Reference
to ADC12INCHx = x

P5REN.x

P5DIR.x

DVSS

0

DVCC

1

1

0
1

P5OUT.x0

From module1
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF–/VeREF–

P5DS.x0: Low drive
1: High drive

P5SEL.x
P5IN.xBus
KeeperEN
To module

D

Figure 6-6. Port P5 (P5.0 and P5.1) Diagram
Table 6-46. Port P5 (P5.0 and P5.1) Pin Functions
PIN NAME (P5.x)x

FUNCTION
P5.0 (I/O)

P5.0/A8/VREF+/VeREF+

(1)
(2)
(3)
(4)

70

0

(2)

CONTROL BITS OR SIGNALS (1)P5DIR.x

P5SEL.x

REFOUT

I: 0; O: 1

0

X

A8/VeREF+ (3)

X

1

0

A8/VREF+ (4)

X

1

1

X = Don't care
Default condition
Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A. Channel A8, when selected with
the INCHx bits, is connected to the VREF+/VeREF+ pin.
Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. The VREF+ reference is available at the pin. Channel A8, when selected with the INCHx bits, is connected to the
VREF+/VeREF+ pin.
Detailed Description

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Table 6-46. Port P5 (P5.0 and P5.1) Pin Functions (continued)
PIN NAME (P5.x)x

FUNCTION
P5.1 (I/O)

P5.1/A9/VREF-/VeREF-

(5)
(6)

1

(2)

CONTROL BITS OR SIGNALS (1)P5DIR.x

P5SEL.x

REFOUT

I: 0; O: 1

0

X

A9/VeREF- (5)

X

1

0

A9/VREF- (6)

X

1

1

Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A. Channel A9, when selected with the
INCHx bits, is connected to the VREF-/VeREF- pin.
Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. The VREF- reference is available at the pin. Channel A9, when selected with the INCHx bits, is connected to the VREF/VeREF- pin.

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6.10.6 Port P5 (P5.2) Input/Output With Schmitt Trigger
Figure 6-7 shows the port diagram. Table 6-47 summarizes the selection of the pin functions.
Pad Logic
To XT2P5REN.2

P5DIR.2

DVSS

0

DVCC

1

1

0
1

P5OUT.20Module X OUT

1
P5DS.20: Low drive
1: High drive

P5SEL.2

P5.2/XT2IN

P5IN.2EN
Module X IN

Bus
KeeperD

Figure 6-7. Port P5 (P5.2) Diagram

72

Detailed Description

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6.10.7 Port P5 (P5.3) Input/Output With Schmitt Trigger
Figure 6-8 shows the port diagram. Table 6-47 summarizes the selection of the pin functions.
Pad Logic
To XT2P5REN.3

P5DIR.3

DVSS

0

DVCC

1

1

0
1

P5OUT.30Module X OUT

1
P5.3/XT2OUT

P5DS.30: Low drive
1: High drive

P5SEL.3
P5IN.3Bus
KeeperEN
Module X IN

D

Figure 6-8. Port P5 (P5.3) Diagram
Table 6-47. Port P5 (P5.2 and 5.3) Pin Functions
PIN NAME (P5.x)x

FUNCTION
P5.2 (I/O)

P5.2/XT2IN

2

(1)
(2)
(3)

3

P5DIR.x

P5SEL.2

P5SEL.3

XT2BYPASS

I: 0; O: 1

0

X

X

XT2IN crystal mode (2)

X

1

X

0

XT2IN bypass mode (2)

X

1

X

1

I: 0; O: 1

0

X

X

XT2OUT crystal mode (3)

X

1

X

0

P5.3 (I/O) (3)

X

1

X

1

P5.3 (I/O)
P5.3/XT2OUTCONTROL BITS OR SIGNALS (1)X = Don't care
Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal
mode or bypass mode.
Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as
general-purpose I/O.

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6.10.8 Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
Figure 6-9 and Figure 6-10 show the port diagrams. Table 6-48 summarizes the selection of the pinfunctions.
Pad Logic
to XT1P5REN.4

P5DIR.4

DVSS

0

DVCC

1

1

0
1

P5OUT.40Module X OUT

1
P5DS.40: Low drive
1: High drive

P5SEL.4

P5.4/XIN

P5IN.4EN
Module X IN

Bus
KeeperD

Figure 6-9. Port P5 (P5.4) Diagram

74

Detailed Description

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Pad Logic
To XT1P5REN.5

P5DIR.5

DVSS

0

DVCC

1

1

0
1

P5OUT.50Module X OUT

1
P5.5/XOUT

P5DS.50: Low drive
1: High drive

P5SEL.5
XT1BYPASS
P5IN.5Bus
KeeperEN
D

Module X IN

Figure 6-10. Port P5 (P5.5) Diagram
Table 6-48. Port P5 (P5.4 and P5.5) Pin Functions
PIN NAME (P5.x)x

FUNCTION

P5DIR.x

P5SEL.4

P5SEL.5

XT1BYPASS

I: 0; O: 1

0

X

X

(2)

X

1

X

0

XIN bypass mode (2)

X

1

X

1

I: 0; O: 1

0

X

X

XOUT crystal mode (3)

X

1

X

0

(3)

X

1

X

1

P5.4 (I/O)
P5.4/XIN4

XIN crystal mode
P5.5 (I/O)

P5.5/XOUT

5

P5.5 (I/O)
(1)
(2)
(3)

CONTROL BITS OR SIGNALS (1)X = Don't care
Setting P5SEL.4 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.4 is configured for crystal
mode or bypass mode.
Setting P5SEL.4 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.5 can be used as
general-purpose I/O.

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6.10.9 Port P5 (P5.7) Input/Output With Schmitt Trigger
Figure 6-11 shows the port diagram. Table 6-49 summarizes the selection of the pin functions.
Pad Logic

P5REN.x

P5DIR.x0

From Module

1

P5OUT.x

0

DVSS

0

DVCC

1

1

Direction
0: Input
1: Output

1
P5.7/TB0.1

P5DS.x0: Low drive
1: High drive

P5SEL.x
P5IN.xEND

To module

Figure 6-11. Port P5 (P5.7) Diagram
Table 6-49. Port P5 (P5.7) Pin Functions
PIN NAME (P5.x)
P5.7/TB0.1

76

Detailed Descriptionx
7

CONTROL BITS OR SIGNALSFUNCTION

P5DIR.x

P5SEL.x

TB0.CCI1A

0

1

TB0.1

1

1

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6.10.10 Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
Figure 6-12 shows the port diagram. Table 6-50 summarizes the selection of the pin functions.
Pad Logic

to ADC12INCHx = x
to Comparator_B
from Comparator_B
CBPD.xP6REN.x

P6DIR.x00From module

1

0

DVCC

1

P6DS.x0: Low drive
1: High drive

P6SEL.x
P6IN.xP6.1/CB1/A1
P6.2/CB2/A2
P6.3/CB3/A3
P6.4/CB4/A4
P6.5/CB5/A5

Bus
KeeperEN
To module

1

Direction
0: Input
1: Output

1

P6OUT.x

DVSS

D

Figure 6-12. Port P6 (P6.1 to P6.5) Diagram

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Table 6-50. Port P6 (P6.1 to P6.5) Pin Functions
PIN NAME (P6.x)x

FUNCTION
P6.1 (I/O)

P6.1/CB1/A1

1A1
CB1 (2)
P6.2 (I/O)

P6.2/CB2/A2

2A2
CB2 (2)
P6.3 (I/O)

P6.3/CB3/A3

3A3
CB3 (2)

4

(1)
(2)

78

5

P6SEL.x
0

CBPDx
0

X

1

X
1

X

X

I: 0; O: 1

0

0

X

1

X
1

X

X

I: 0; O: 1

0

0

X

1

X
1

X

X
0

0

A4

X

1

X

CB4 (2)

XX

1

P6.5 (I/O)
P6.5/CB5/A5

P6DIR.x
I: 0; O: 1

I: 0; O: 1

P6.4 (I/O)
P6.4/CB4/A4

CONTROL BITS OR SIGNALS (1)I: 0; O: 1

0

0

A5

X

1

X

CB5 (2)

XX

1

X = Don't care
Setting the CBPDx bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input buffer
for that pin, regardless of the state of the associated CBPDx bit.

Detailed Description

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6.10.11 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
Figure 6-13 shows the port diagram. Table 6-51 summarizes the selection of the pin functions.
Pad Logic

PJREN.0

PJDIR.0

0

DVCC

1

PJOUT.00

From JTAG

1

DVSS

0

DVCC

1

PJDS.0
0: Low drive
1: High drive

From JTAG

1

PJ.0/TDO

PJIN.0EN
D

Figure 6-13. Port PJ (PJ.0) Diagram

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6.10.12 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt
Trigger or Output
Figure 6-14 shows the port diagram. Table 6-51 summarizes the selection of the pin functions.
Pad Logic

PJREN.x

PJDIR.x

0

DVSS

1

PJOUT.x0

From JTAG

1

DVSS

0

DVCC

1

PJDS.x0: Low drive
1: High drive

From JTAG1

PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK

PJIN.xEN
D

To JTAG

Figure 6-14. Port PJ (PJ.1 to PJ.3) Diagram
Table 6-51. Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)

x

CONTROL BITS OR
SIGNALS (1)FUNCTIONPJDIR.x
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
(1)
(2)
(3)
(4)

80

0
1
2
3

PJ.0 (I/O) (2)I: 0; O: 1

TDO (3)
PJ.1 (I/O)X(2)

I: 0; O: 1

TDI/TCLK (3) (4)X

PJ.2 (I/O) (2)I: 0; O: 1

TMS (3) (4)X

PJ.3 (I/O) (2)I: 0; O: 1

TCK (3) (4)X

X = Don't care
Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.

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JAJSG78F – JULY 2011 – REVISED SEPTEMBER 20186.11 Device Descriptors
Table 6-52 lists the complete contents of the device descriptor tag-length-value (TLV) structure for eachdevice type.
Table 6-52. Device Descriptor Table (1)Info Block

Die Record

ADC12 Calibration

REF Calibration

(1)

VALUE

ADDRESS

SIZE(bytes)

F5342

F5341

F5340

Info length

01A00h

1

06h

06h

06h

CRC length

01A01h

1

06h

06h

06h

CRC value

01A02h2

Per unit

Per unit

Per unit

Device ID

01A04h

1

1Eh

1Dh

1Ch

DESCRIPTION

Device ID

01A05h

1

81h

81h

81h

Hardware revision

01A06h1

Per unit

Per unit

Per unit

Firmware revision

01A07h1

Per unit

Per unit

Per unit

Die record tag

01A08h

1

08h

08h

08h

Die record length

01A09h

1

0Ah

0Ah

0Ah

Lot/wafer ID

01A0Ah4

Per unit

Per unit

Per unit

Die X position

01A0Eh2

Per unit

Per unit

Per unit

Die Y position

01A10h2

Per unit

Per unit

Per unit

Test results

01A12h2

Per unit

Per unit

Per unit

ADC12 calibration tag

01A14h

1

11h

11h

11h

ADC12 calibration length

01A15h

1

10h

10h

10h

ADC gain factor

01A16h2

Per unit

Per unit

Per unit

ADC offset

01A18h2

Per unit

Per unit

Per unit

ADC 1.5-V reference
temperature sensor 30°C

01A1Ah2

Per unit

Per unit

Per unit

ADC 1.5-V reference
temperature sensor 85°C

01A1Ch2

Per unit

Per unit

Per unit

ADC 2.0-V reference
temperature sensor 30°C

01A1Eh2

Per unit

Per unit

Per unit

ADC 2.0-V reference
temperature sensor 85°C

01A20h2

Per unit

Per unit

Per unit

ADC 2.5-V reference
temperature sensor 30°C

01A22h2

Per unit

Per unit

Per unit

ADC 2.5-V reference
temperature sensor 85°C

01A24h2

Per unit

Per unit

Per unit
12h

REF calibration tag

01A26h

1

12h

12h

REF calibration length

01A27h

1

06h

06h

06h

REF 1.5-V reference factor

01A28h2

Per unit

Per unit

Per unit

REF 2.0-V reference factor

01A2Ah2

Per unit

Per unit

Per unit

REF 2.5-V reference factor

01A2Ch2

Per unit

Per unit

Per unit

N/A = Not applicable, blank = unused and reads FFh

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Table 6-52. Device Descriptor Table(1) (continued)
SIZE(bytes)

Peripheral descriptor tag

01A2Eh

1

02h

02h

02h

Peripheral descriptor length

01A2Fh

1

5Eh

5Eh

5Eh

Memory 1

2

08h
8Ah

08h
8Ah

08h
8Ah

Memory 2

2

0Ch
86h

0Ch
86h

0Ch
86h

Memory 3

2

0Eh
2Fh

0Eh
2Eh

0Eh
2Dh

Memory 4

2

2Ah
22h

22h
95h

2Ah
22h

Memory 5

1

96h

92h

94h

Delimiter

1

00h

00h

00h

Peripheral count

1

1Fh

1Fh

1Fh

MSP430CPUXV2

2

00h
23h

00h
23h

00h
23h

JTAG

2

00h
09h

00h
09h

00h
09h

SBW

2

00h
0Fh

00h
0Fh

00h
0Fh

EEM-L

2

00h
05h

00h
05h

00h
05h

TI BSL

2

00h
FCh

00h
FCh

00h
FCh

SFR

2

10h
41h

10h
41h

10h
41h

PMM

2

02h
30h

02h
30h

02h
30h

FCTL

2

02h
38h

02h
38h

02h
38h

CRC16

2

01h
3Ch

01h
3Ch

01h
3Ch

CRC16_RB

2

00h
3Dh

00h
3Dh

00h
3Dh

RAMCTL

2

00h
44h

00h
44h

00h
44h

WDT_A

2

00h
40h

00h
40h

00h
40h

UCS

2

01h
48h

01h
48h

01h
48h

SYS

2

02h
42h

02h
42h

02h
42h

REF

2

03h
A0h

03h
A0h

03h
A0h

Port Mapping

2

01h
10h

01h
10h

01h
10h

Port 1 and 2

2

04h
51h

04h
51h

04h
51h

Port 3 and 4

2

02h
52h

02h
52h

02h
52h

Port 5 and 6

2

02h
53h

02h
53h

02h
53h

Peripheral Descriptor

82

Detailed Description

VALUE

ADDRESSDESCRIPTION

F5342

F5341

F5340

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Table 6-52. Device Descriptor Table(1) (continued)
DESCRIPTION

Peripheral Descriptor(continued)

Interrupts

ADDRESS

SIZE(bytes)

VALUE
F5342

F5341

F5340

JTAG

2

0Eh
5Fh

0Eh
5Fh

0Eh
5Fh

TA0

2

02h
62h

02h
62h

02h
62h

TA1

2

04h
61h

04h
61h

04h
61h

TB0

2

04h
67h

04h
67h

04h
67h

TA2

2

04h
61h

04h
61h

04h
61h

RTC

2

0Ah
68h

0Ah
68h

0Ah
68h

MPY32

2

02h
85h

02h
85h

02h
85h

DMA-3

2

04h
47h

04h
47h

04h
47h

USCI_A, USCI_B

2

0Ch
90h

0Ch
90h

0Ch
90h

USCI_A, USCI_B

2

04h
90h

04h
90h

04h
90h

ADC12_A

2

10h
D1h

10h
D1h

10h
D1h

COMP_B

2

1Ch
A8h

1Ch
A8h

1Ch
A8h

COMP_B

1

A8h

A8h

A8h

TB0.CCIFG0

1

64h

64h

64h

TB0.CCIFG1..6

1

65h

65h

65h

WDTIFG

1

40h

40h

40h

USCI_A0

1

90h

90h

90h

USCI_B0

1

91h

91h

91h

ADC12_A

1

D0h

D0h

D0h

TA0.CCIFG0

1

60h

60h

60h

TA0.CCIFG1..4

1

61h

61h

61h

Reserved

1

01h

01h

01h

DMA

1

46h

46h

46h

TA1.CCIFG0

1

62h

62h

62h

TA1.CCIFG1..2

1

63h

63h

63h

P1

1

50h

50h

50h

USCI_A1

1

92h

92h

92h

USCI_B1

1

93h

93h

93h

TA1.CCIFG0

1

66h

66h

66h

TA1.CCIFG1..2

1

67h

67h

67h

P2

1

51h

51h

51h

RTC_A

1

68h

68h

68h

Delimiter

1

00h

00h

00h

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7 デバイスおよびドキュメントのサポート
7.1

はじめに
MSP430™ファミリのデバイス、および開発に役立つツールやライブラリの詳細については、「MSP430超低消費電力センシング/測定マイコンの概要」を参照してください。

7.2

Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS.
These prefixes represent evolutionary stages of product development from engineering prototypes (XMS)
through fully qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates thetemperature range, package type, and distribution format. 図 7-1 provides a legend for reading thecomplete device name.

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MSP 430 F 5 438 A I ZQW T -EP
Processor Family

Optional: Additional Features

MCU Platform

Optional: Tape and Reel

Device Type

Packaging

SeriesFeature Set
Processor Family

Optional: Temperature Range
Optional: A = Revision

CC = Embedded RF RadioMSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 = MSP430 low-power microcontroller platform

MCU Platform
Device Type

Memory TypeC = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory

Specialized Application
AFE = Analog Front End
BQ = Contactless PowerCG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter

Series

1 = Up to 8 MHz
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD

5 = Up to 25 MHz
6 = Up to 25 MHz with LCD
0 = Low-Voltage Series

Feature Set

Various levels of integration within a series

Optional: A = Revision

N/A

Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging

http://www.ti.com/packaging

Optional: Tape and Reel

T = Small reel
R = Large reel
No markings = Tube or tray

Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)-HT = Extreme Temperature Parts (–55°C to 150°C)-Q1 = Automotive Q100 Qualified

図 7-1. Device Nomenclature

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ツールとソフトウェア
すべてのMSPマイクロコントローラは、広範なソフトウェアおよびハードウェア開発ツールによりサポートされています。ツールは、TIおよびさまざまなサードパーティーから入手できます。すべての一覧は「MSP430 超低消費電力
マイコン – ツールとソフトウェア」で参照できます。
MSP430F532x
MCUのデバッグ機能の一覧を、表7-1に示します。利用可能な機能の詳細については、『MSP430用Code Composer Studio ユーザー・ガイド』を参照してください。
表 7-1. ハードウェアのデバッグ機能

MSP430ののアーキテク4線
線式JTAGチャ
MSP430Xv2

2線
線式JTAG

ブレーク・ポ
イント
(N)

範囲ブレー
ク・ポイント

クロック制御状態シーケンサ

トレース・バッファ

LPMx.5デデバッ
グ・サポート

○

8

○

○

○

○

×

○

設計キットと評価モジュール
MSP430F534x 48ピ
ピン・ターゲット・ボードのみ MSP-TS430RGZ48Bはスタンドアロンの48ピンZIFソケット・ター
ゲット・ボードで、これによりJTAGインターフェイスまたはSpy Bi-Wire（2線式JTAG）プロトコルを使用
して、MSP430 MCUをインシステムでプログラミングおよびデバッグできます。
MSP430F5x MCU用
用の48ピ
ピン・ターゲット開発基板とMSP-FETプ
プログラマ・バンドル MSP-FET430U48Bは強力なフラッシュ・エミュレーション・ツールで、MSP430 MCUによるアプリケーションの開発をすぐに開始できます。USBデバッグ・インターフェイスにより、JTAGインターフェイスまたは省ピンSpy Bi-Wire（2線式JTAG）プロトコルを使用してMSP430をインシステムでプログラミングおよびデバッグできます。
MSP430のフラッシュ・メモリは、数回のキー操作により、数秒で消去およびプログラミングできます。
また、極めて低消費電力であるため、外部電源は不要です。
ソフトウェアMSP430Ware™ソ
ソフトウェア MSP430Wareソフトウェアは、すべてのMSP430デバイス向けのサンプル・コード、
データシート、その他の設計リソースを、1つの便利なパッケージとしてまとめたものです。既存のMSP430 MCU 設計リソースの完全なコレクションに加えて、MSP430Ware ソフトウェアには、MSP
ドライバ・ライブラリという高レベルのAPIも含まれています。このライブラリにより、MSP430ハードウェ
アを簡単にプログラムできます。MSP430WareソフトウェアはCCSのコンポーネントとして、またはスタンドアロンのパッケージとして入手できます。
MSP430F534xサ
サンプル・コード 各種のアプリケーションの要求に応じて、各内蔵ペリフェラルを設定するCコード・
サンプルです。
MSPド
ドライバ・ライブラリ
ドライバ・ライブラリの抽象化APIで、使いやすい関数呼び出しが用意されており、MSP430ハードウェアのビットやバイトのレベルを意識せずに、より高水準の開発作業に集中できます。使いやすいAPIガイドにより包括的な技術資料が参照でき、それぞれの関数呼び出しと、認識されるパラメータの詳細が記載されています。開発者は、ドライバ・ライブラリの関数を使用して、最小限のオーバーヘッドで完全なプロジェクトを作成できます。
MSP EnergyTrace™テ
テクノロジ MSP430マイクロコントローラ用のEnergyTraceテクノロジは、エネルギーを基準としたコード解析ツールで、アプリケーションのエネルギー・プロファイルを測定して表示し、消費電力が極めて低くなるよう最適化するため役立ちます。
ULP (超超低消費電力) Advisor ULP Advisor™ソフトウェアは、MSPおよびMSP432マイクロコントローラ独自の超低消費電力機能を十分に活用できる、最も効率的なコードを開発者が作成できるよう手引きするツー
ルです。ULP Advisorは、マイクロコントローラの熟練した開発者でも、新しい開発者でも使用でき、
包括的なULPチェックリストと照らし合わせてコードのチェックを行い、アプリケーションの性能を最大限まで発揮できるようにします。ビルド時に、消費電力低減のためさらに最適化が可能なコードの部
分を明らかにするため通知と注釈を出力します。
IEC60730ソ
ソフトウェア・パッケージ IEC60730 MSP430ソフトウェア・パッケージは、クラスBまでの製品について、
お客様がIEC 60730-1:2010 (家庭および同様な用途に使用される自動電気制御 – 第1部: 一般的な要件)に準拠するため役立つよう開発されています。この分類には家電機器、アーク検出器、電力コンバータ、電動工具、電動アシスト自転車、その他多くの製品が含まれます。IEC60730 MSP430
ソフトウェア・パッケージは、MSP430で実行するお客様のアプリケーションに組み込むことができるため、消費者向けデバイスがIEC 60730-1:2010クラスBの機能安全性に準拠していることの認定作業を簡素化できます。

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MSP用用の固定小数点算術ライブラリ MSP IQmathおよびQmathライブラリは、Cプログラマ向けの高度に最適化された高精度の算術関数のコレクションで、浮動小数点アルゴリズムをMSP430およびMSP432デバイ
スの固定小数点コードへシームレスに移行できます。これらのルーチンは通常、最適な実行速度、高精度、超低消費電力が重視される、演算集中型のリアルタイム・アプリケーションで使用されます。
IQmathライブラリとQmathライブラリを使用すると、浮動小数点演算を使用して記述した同等のコードに比べて、実行速度を大幅に高速化するとともに、消費電力の大幅な削減が可能です。
MSP430用
用の浮動小数点算術ライブラリ 低消費電力かつ低コストのマイクロコントローラ分野で継続的な革新を行うため、TIはMSPMATHLIBを提供しています。このスカラー関数の浮動小数点数値演算ライブラリ
は、弊社デバイスのインテリジェントなペリフェラルを活用し、最高26倍の性能を実現します。Mathlib
は、設計へ簡単に組み入れることができます。このライブラリは無償で、Code Composer Studio とIAR IDE の両方に組み込まれています。数値演算ライブラリと関連ベンチマークの詳細について
は、ユーザー・ガイドを参照してください。
開発ツール
Code Composer Studio™: MSPマ
マイクロコントローラ用の統合開発環境 Code Composer Studioは、すべてのMSPマイクロコントローラ・デバイスをサポートする統合開発環境(IDE)です。CodeComposer
Studioは、組み込みアプリケーションの開発とデバッグに使用される、組み込み用ソフトウェア・ユー
ティリティのスイートです。最適化C/C++コンパイラ、ソース・コード・エディタ、プロジェクト・ビルド環
境、デバッガ、プロファイラなど、多数の機能が含まれています。IDEは直感的で、アプリケーションの開発フローの各段階を、すべて同一のユーザー・インターフェイスで実行できます。使い慣れたユー
ティリティとインターフェイスにより、ユーザーは従来より迅速に作業を開始できます。CodeComposer Studioは、Eclipseソフトウェア・フレームワークの利点と、TIの先進的な組み込みデバッ
グ機能の利点を組み合わせ、組み込み製品の開発者向けの魅力的な、豊富な機能を持つ開発環
境を実現します。Code Composer Studio IDEをMSP MCUとともに使用すると、MSPマイクロコント
ローラを最大限に活用するための、ユニークで強力な一連のプラグインや組み込みソフトウェア・ユー
ティリティを利用できます。
コマンドライン・プログラマ MSP Flasher は、FETプログラマまたは eZ430 を経由し、JTAG または Spy-Bi-Wire(SBW) 通信を使用して MSP マイクロコントローラをプログラムするための、オープン・ソースでシェ
ル・ベースのインターフェイスです。MSP Flasher は、IDE を使用せずにバイナリ・ファイル (.txtまたは.hex) をMSPマイクロコントローラへ直接ダウンロードできます。
MSP MCUプ
プログラマおよびデバッガ MSP-FETは強力なエミュレーション開発ツールで、多くの場合、デバッグ・プローブと呼ばれています。ユーザーはこのツールを使用して、MSP低消費電力マイクロコントローラ(MCU)のアプリケーション開発を迅速に開始できます。MCUのソフトウェアを作成する場合は通常、結果として得られたバイナリ・プログラムをMSPデバイスにダウンロードし、検証とデバッグを行う
必要があります。MSP-FETは、ホスト・コンピュータとターゲットMSPの間で、デバッグ通信経路を提供します。さらに、MSP-FETはコンピュータのUSBインターフェイスとMSP UARTの間で、バックチャ
ネルUART接続も提供します。これにより、MSPプログラマは、コンピュータ上で動作している端末ソフトウェアとMSPとの間で、シリアル通信を簡単に実行できます。また、UARTやI2C通信プロトコルを経由するBSL (ブートローダー) を使用して、プログラム (多くの場合、ファームウェアと呼ばれます)
をMSPターゲットにロードできます。
MSP-GANG量
量産プログラマ MSP Gang ProgrammerはMSP430またはMSP432用のデバイス・プログラマで、8つまでの同一のMSP430またはMSP432フラッシュまたはFRAMデバイスを同時にプログラムできます。MSP Gang Programmerは、標準のRS-232またはUSB接続を使用してホストPCに接続でき、柔軟なプログラミング・オプションにより、プロセスを完全にカスタマイズ可能です。MSP
Gang
Programmerには、Gang
Splitterと呼ばれる拡張ボードが付属しており、MSP
Gang
Programmerと複数のターゲット・デバイスとの間で相互接続機能を実装します。拡張ボードと、8つのターゲット・デバイスとを接続するため、8本のケーブルが付属しています(JTAGまたはSpy-BiWireコネクタ経由)。PCを使用してプログラムすることも、スタンドアロンのデバイスとしてプログラムすることもできます。PC側のグラフィカル・ユーザー・インターフェイスも用意されており、DLLベースです。

デバイスおよびドキュメントのサポート
Submit Documentation Feedback
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Copyright © 2011–2018, Texas Instruments Incorporated

87

MSP430F5342, MSP430F5341, MSP430F5340
JAJSG78F – JULY 2011 – REVISED SEPTEMBER 20187.4

www.tij.co.jp

ドキュメントのサポート
以下のドキュメントには、MSP430F532x
www.ti.comで入手できます。

MCUについて記載されています。これらのドキュメントのコピーは、ドキュメントの更新通知を受け取る方法
ドキュメント更新の通知を、シリコンの正誤表も含めて受け取るには、ti.comでお使いの製品のフォルダへ移動します(プロダクト・フォルダへのリンクについては、 7.5を参照してください)。右上の隅にある「通知を受け取る」ボタンをクリックします。これによって登録が行われ、変更された製品情報の概要を毎週受け取ることができます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。
正誤表『MSP430F5342デ
デバイス正誤表』 このデバイスにおけるすべてのシリコンのリビジョンについて、機能仕様に関する既知の例外が記載されています。
『MSP430F5341デ
デバイス正誤表』 このデバイスにおけるすべてのシリコンのリビジョンについて、機能仕様に関する既知の例外が記載されています。
『MSP430F5340デ
デバイス正誤表』 このデバイスにおけるすべてのシリコンのリビジョンについて、機能仕様に関する既知の例外が記載されています。
ユーザー・ガイド『MSP430x5xxおおよびMSP430x6xxフ
ファミリ・ユーザー・ガイド』
ペリフェラルについての詳細情報です。

このデバイス・ファミリで利用可能なモジュールと『MSP430 フラッシュ・デバイス・ブートローダ(BSL)ユ
ユーザー・ガイド』 MSP430ブートローダ(BSL)を使用すると、プロトタイプ作成フェーズ、最終的な量産、およびサービス中に、MSP430マイクロコントローラの組
み込みメモリと通信を行うことができます。必要に応じて、プログラム可能メモリ(フラッシュ・メモリ)とデータ・メモリ(RAM)の両方を変更できます。このブートローダは、一部のデジタル・シグナル・プロ
セッサ(DSP)に見られる、外部メモリからDSPの内部メモリへプログラム・コード(およびデータ)を自動的にロードする、ブートストラップ・ローダ・プログラムとは異なることに注意してください。
『JTAGイインターフェイスによるMSP430ののプログラミング』
このドキュメントでは、JTAG通信ポートを使用してMSP430のフラッシュ・ベースおよびFRAMベースのマイクロコントローラ・ファミリのメモリ・モジュールを消去、プログラム、検証するために必要な機能について解説しています。さらに、すべてのMSP430デバイスで利用可能なJTAGアクセス・セキュリティ・ヒューズのプログラム方法についても解説しています。このドキュメントには、標準の4線式JTAGインターフェイスと2線式JTAGインターフェイスの両方を使用してデバイスにアクセスする方法が解説されています。2線式JTAGインターフェイス
はSpy-Bi-Wire (SBW)とも呼ばれます。
『MSP430ハ
ハードウェア・ツール ユーザー・ガイド』 このマニュアルには、TI MSP-FET430フラッシュ・エミュレー
ション・ツール(FET)のハードウェアについて解説されています。このFETは、MSP430 超低消費電力マイクロコントローラ用のプログラム開発ツールです。利用可能なインターフェイスとして、パラレル・
ポート・インターフェイスとUSBインターフェイスの両方について解説されています。
アプリケーション・レポート『MSP430 32kHz水水晶発振器』
適切な水晶、正しい負荷回路、および適切な基板レイアウトの選択は、安定した水晶発振器のために重要です。このアプリケーション・レポートでは、水晶発振器の機能について要約し、MSP430の超低消費電力動作用の適切な水晶を選択するためのパラメータについて説明しま
す。また、正しい基板レイアウトについてのヒントや例も紹介しています。このドキュメントには、量産時の安定した発振器の動作を保証するために行うことができる、発振器のテストについての詳細情報も記載されています。
『MSP430 システム・レベルESDのの考慮事項』
シリコン・テクノロジがますます低電圧化し、コスト効率の優れた非
常に消費電力の低いコンポーネントを設計する必要性が高まっていくにつれ、システム・レベルESDの要求はますます高くなりつつあります。このアプリケーション・レポートでは、基板の設計者およびOEMが強固なシステム・レベルの設計を理解して実行するため役立つよう、3つのESDトピックが扱
われています。(1)部品レベルのESDテストとシステム・レベルのESDテスト、(2)システム・レベルのESD保護の一般的な設計ガイドライン、(3)システムの高効率ESD設計(SEED)の概要と、オンボード
およびオンチップESD保護のコデザイン手法。現実世界でのシステム・レベルのESD保護を設計する例のいくつかと、その結果についても解説します。

88

デバイスおよびドキュメントのサポート

Copyright © 2011–2018, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: MSP430F5342 MSP430F5341 MSP430F5340

MSP430F5342, MSP430F5341, MSP430F5340
www.tij.co.jp

7.5

JAJSG78F – JULY 2011 – REVISED SEPTEMBER 2018

関連リンク
表 7-2 に、クイック・アクセス・リンクの一覧を示します。カテゴリには、技術資料、サポートおよびコミュニティ・リソー
ス、ツールとソフトウェア、およびサンプル注文またはご購入へのクイック・アクセスが含まれます。
表 7-2. 関連リンク

7.6

製品

プロダクト・フォルダ

ご注文はこちら

技術資料

ツールとソフトウェア

サポートとコミュニティ

MSP430F5342

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

MSP430F5341

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

MSP430F5340

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by therespective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.

7.7

商標
MSP430, MSP430Ware, EnergyTrace, ULP Advisor, Code Composer Studio, E2E are trademarks ofTexas Instruments.

7.8

静電気放電に関する注意事項
すべての集積回路は、適切なESD保護方法を用いて、取扱いと保存を行うようにして下さい。
静電気放電はわずかな性能の低下から完全なデバイスの故障に至るまで、様々な損傷を与えます。高精度の集積回路は、損傷に対して敏感であり、極めてわずかなパラメータの変化により、デバイスに規定された仕様に適合しなくなる場合があります。

7.9

Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to whichsuch export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining priorauthorization from U.S. Department of Commerce and other competent Government authorities to theextent required by those laws.

7.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

デバイスおよびドキュメントのサポート
Submit Documentation Feedback
Product Folder Links: MSP430F5342 MSP430F5341 MSP430F5340

Copyright © 2011–2018, Texas Instruments Incorporated

89

MSP430F5342, MSP430F5341, MSP430F5340
JAJSG78F – JULY 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

8 メカニカル、パッケージ、および注文情報
以降のページには、メカニカル、パッケージ、および注文に関する情報が記載されています。これらの情報は、指定のデバイスに対して提供されている最新のデータです。このデータは予告なく変更されることがあり、ドキュメントが改訂される場合もあります。本データシートのブラウザ版を使用されている場合は、画面左側の説明をご覧ください。

90

メカニカル、パッケージ、および注文情報

Copyright © 2011–2018, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: MSP430F5342 MSP430F5341 MSP430F5340

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

(3)

(4/5)

(6)

MSP430F5340IRGZR

ACTIVE

VQFN

RGZ

48

2500

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430
F5340

MSP430F5340IRGZT

ACTIVE

VQFN

RGZ

48

250

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430
F5340

MSP430F5341IRGZR

ACTIVE

VQFN

RGZ

48

2500

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430
F5341

MSP430F5341IRGZT

ACTIVE

VQFN

RGZ

48

250

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430
F5341

MSP430F5342IRGZR

ACTIVE

VQFN

RGZ

48

2500

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430
F5342

MSP430F5342IRGZT

ACTIVE

VQFN

RGZ

48

250

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430
F5342

(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

SamplesPACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

26-Sep-2018

TAPE AND REEL INFORMATION*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)

MSP430F5340IRGZR

VQFN

RGZ

48

2500

330.0

16.4

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

7.3

7.3

1.1

12.0

16.0

Q2

MSP430F5340IRGZT

VQFN

RGZ

48

250

180.0

16.4

7.3

7.3

1.1

12.0

16.0

Q2

MSP430F5341IRGZR

VQFN

RGZ

48

2500

330.0

16.4

7.3

7.3

1.1

12.0

16.0

Q2

MSP430F5341IRGZT

VQFN

RGZ

48

250

180.0

16.4

7.3

7.3

1.1

12.0

16.0

Q2

MSP430F5342IRGZR

VQFN

RGZ

48

2500

330.0

16.4

7.3

7.3

1.1

12.0

16.0

Q2

MSP430F5342IRGZT

VQFN

RGZ

48

250

180.0

16.4

7.3

7.3

1.1

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

26-Sep-2018*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)

MSP430F5340IRGZR

VQFN

RGZ

48

2500

367.0

367.0

38.0

MSP430F5340IRGZT

VQFN

RGZ

48

250

210.0

185.0

35.0

MSP430F5341IRGZR

VQFN

RGZ

48

2500

367.0

367.0

38.0

MSP430F5341IRGZT

VQFN

RGZ

48

250

210.0

185.0

35.0

MSP430F5342IRGZR

VQFN

RGZ

48

2500

367.0

367.0

38.0

MSP430F5342IRGZT

VQFN

RGZ

48

250

210.0

185.0

35.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RGZ 48VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD

7 x 7, 0.5 mm pitch

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A

www.ti.com

PACKAGE OUTLINE

RGZ0048A

VQFN - 1 mm max height

PLASTIC QUADFLAT PACK- NO LEAD
A

7.1
6.9

B

(0.1) TYP
7.1
6.9

PIN 1 INDEX AREA

SIDE WALL DETAILOPTIONAL METAL THICKNESS(0.45) TYP

CHAMFERED LEADCORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.05
0.00

0.08 C
2X 5.55.15±0.1(0.2) TYP
24

13

44X 0.5
12

25

SYMM

2X
5.5

1

PIN1 ID(OPTIONAL)
SEE LEAD OPTIONSEE SIDE WALL
DETAIL

36
48

SYMM

37

48X 0.5
0.3

48X 0.30
0.18
0.1
0.05

C A B
C

4219044/D 02/2022

NOTES:
1.
2.
3.

All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGZ0048A

VQFN - 1 mm max height

PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)( 5.15)SYMM
48X (0.6)

37

48

48X (0.24)
1

44X (0.5)

2X
(5.5)

36

SYMM

2X
(6.8)
2X
(1.26)

2X(1.065)(R0.05)TYP

25

12
21X (Ø0.2) VIA
TYP
13

24

2X (1.26)

2X (1.065)

2X (5.5)

LAND PATTERN EXAMPLESCALE: 15X

0.07 MIN
ALL AROUND

0.07 MAXALL AROUNDEXPOSED METALSOLDER MASKOPENINGEXPOSED METALMETALNON SOLDER MASKDEFINED(PREFERRED)SOLDER MASKOPENINGSOLDER MASKDEFINEDSOLDER MASK DETAILSMETAL UNDERSOLDER MASK

4219044/D 02/2022

NOTES: (continued)
4.
5.

This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shownon this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGNRGZ0048A

VQFN - 1 mm max height

PLASTIC QUADFLAT PACK- NO LEAD

2X (6.8)
SYMM
48X (0.6)( 1.06)37

48

48X (0.24)
1

44X (0.5)

2X
(5.5)

36

SYMM

2X

2X (6.8)(0.63)

2X(1.26)(R0.05)
TYP

25

12

13

2X (0.63)

2X(1.26)

24

2X (5.5)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCILEXPOSED PAD
67% PRINTED COVERAGE BY AREASCALE: 15X

4219044/D 02/2022

NOTES: (continued)
6.

Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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