TPS746-Q1
SBVS358C – JUNE 2018 – REVISED MAY 2022

TPS746-Q1 Automotive, 1-A LDO With Power-Good in Small Wettable Flank WSON
Packages
1 Features

3 Description•

The TPS746-Q1 is a 1-A, ultra-low-dropout regulator(LDO) with power-good functionality. This device isavailable in a small 6-pin, 2-mm × 2-mm WSON
package and a small 8-pin, 3-mm × 3-mm VSON
package with wettable flanks to facilitate opticalinspection. The TPS746-Q1 consumes low quiescentcurrent and provides fast line and load transient
performance.

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AEC-Q100 qualified for automotive applications:– Temperature grade 1: –40°C to +125°C, TA
Device operating junction temperature range:– –40°C to +150°C
Package:– 2-mm × 2-mm wettable flank WSON
– 3-mm × 3-mm wettable flank VSON
Input voltage range: 1.5 V to 6.0 V
Output voltage range:– Fixed option: 0.65 V to 5.0 V– Adjustable option: 0.55 V to 5.5 V
High PSRR: 38 dB at 100 kHz
Output accuracy: ±0.85% typical, ±1.5% maximum
Power-good output options:– Open-drain or push-pull
Ultra-low dropout:– 265 mV (max) at 1 A (3.3 VOUT)
Stable with a 1-µF or larger capacitor
Low IQ: 25 μA (typical)
Active output discharge
Functional Safety-Capable– Documentation available to aid functional safetysystem design
Low thermal resistance:– DRV (6-pin WSON), RθJA = 80.3°C/W– DRB (8-pin VSON), RθJA = 55.5°C/W

2 Applications
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The TPS746-Q1 is a flexible device for post-regulation
by supporting an input voltage range from 1.5 V to
6.0 V and an externally adjustable output range of
0.55 V to 5.5 V. The device also features fixed output
voltages for powering common voltage rails.
The TPS746-Q1 has a power-good (PG) output thatmonitors the voltage at the feedback pin to indicate
the status of the output voltage. The EN input andPG output can be used for sequencing multiple power
supplies in the system.
The TPS746-Q1 is stable with small ceramic output
capacitors, allowing for a small overall solution size. A
precision band-gap and error amplifier provides highaccuracy of ±0.85% (max) at 25°C and ±1.5% (max)over temperature. This device includes integrated
thermal shutdown, current limit, and undervoltage
lockout (UVLO) features. The TPS746-Q1 has aninternal foldback current limit that helps reduce thethermal dissipation during short-circuit events.
Device Information(1)Automotive head units
Front and rear cameras
Automotive cluster displays
Telematics control units
Medium, short range radar

PART NUMBER

VIN

VOUT

EN

GND

Wettable flank VSON
3.00 mm × 3.00 mm
(8)

VIN

VOUT

OUT

IN

Cff

RPG*

TPS746-Q1

CIN

2.00 mm × 2.00 mm

For all available packages, see the orderable addendum atthe end of the data sheet.

OUT

IN

BODY SIZE (NOM)

Wettable flank
WSON (6)

TPS746-Q1(1)

PACKAGE

COUT

PG*Pull-up resistor not requiredfor push-pull option

Typical Application: Fixed Voltage Version

TPS746-Q1

CIN

EN

FB

GND

PG

COUT

R1
RPG*
R2

*Pull-up resistor not requiredfor push-pull option

Typical Application: Adjustable Voltage Version

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements.................................................. 6
6.7 Typical Characteristics................................................ 7
7 Detailed Description......................................................15
7.1 Overview................................................................... 15
7.2 Functional Block Diagrams....................................... 15
7.3 Feature Description...................................................17

7.4 Device Functional Modes..........................................19
8 Application and Implementation.................................. 20
8.1 Application Information............................................. 20
8.2 Typical Application.................................................... 27
9 Power Supply Recommendations................................28
10 Layout...........................................................................29
10.1 Layout Guidelines................................................... 29
10.2 Layout Examples.................................................... 29
11 Device and Documentation Support..........................30
11.1 Device Support........................................................30
11.2 Documentation Support.......................................... 30
11.3 Receiving Notification of Documentation Updates.. 30
11.4 Support Resources................................................. 30
11.5 Trademarks............................................................. 30
11.6 Electrostatic Discharge Caution.............................. 30
11.7 Glossary.................................................................. 31

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2021) to Revision C (May 2022)
Page• Changed DRB RθJA from 62.0°C/W to 55.5°C/W and added Functional Safety Bullet...................................... 1• Changed WSON to VSON for DRB package throughout document.................................................................. 1• Updated thermal table to reflect correct values and package name...................................................................5
Changes from Revision A (October 2019) to Revision B (January 2021)
Page• Changed DRB package from preview to production data...................................................................................1• Added limits to ISC and tSTR in Electrical Charactertistics table.......................................................................... 4• Changed VDO and VOL(PG) conditions to correct values in Electrical Charactertistics table............................... 4

2

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5 Pin Configuration and Functions

OUT

1

FB
GND

6

IN

OUT

1

6

IN

2 Thermal 5
Pad

PG

NC

2 Thermal 5
Pad

PG

3

EN

GND

3

EN

4

Not to scale

Not to scale

Figure 5-1. DRV Package, 6-Pin Adjustable WSON(Top View)

OUT

1

NC

2

FB

3

GND

4

4

ThermalPad

Figure 5-2. DRV Package, 6-Pin Fixed WSON(Top View)

8

IN

OUT

1

7

NC

NC

2

6

PG

NC

3

5

EN

GND

4

Not to scale

Thermal
Pad

8

IN

7

NC

6

PG

5

EN

Not to scale

Figure 5-3. DRB Package, 8-Pin Adjustable VSON(Top View)

Figure 5-4. DRB Package, 8-Pin Fixed VSON(Top View)

Table 5-1. Pin Functions
PIN
DRV(Fixed)DRV(Adjust)DRB(Fixed)DRB(Adjust)I/O

DESCRIPTION

EN

4

4

5

5

Input

Enable pin. Drive EN greater than VEN(HI) to turn on the regulator. Drive EN lessthan VEN(LO) to put the low-dropout regulator (LDO) into shutdown mode.

FB

—

2

—

3

—

This pin is used as an input to the control loop error amplifier and is used to set
the output voltage of the LDO.

GND

3

3

4

4

—

Ground pin.

NAME

IN

6

6

8

8

Input

Input pin. For best transient response and to minimize input impedance, use
the recommended value or larger ceramic capacitor from IN to ground as listed
in the Recommended Operating Conditions table and the Input and Output
Capacitor Selection section. Place the input capacitor as close to the output ofthe device as possible.

NC

2

—

2, 3, 72, 7—

No internal connection. Ground this pin for better thermal performance.

OUT

PG

1

5

1

5

1

6

Thermal Pad

1

6

OutputRegulated output voltage pin. A capacitor is required from OUT to ground forstability. For best transient response, use the nominal recommended value orlarger ceramic capacitor from OUT to ground; see the Recommended Operating
Conditions table and the Input and Output Capacitor Selection section. Placethe output capacitor as close to the output of the device as possible.

OutputPower-good output. Available in open-drain and push-pull topologies. A pullup
resistor is required for the open-drain version. For the open-drain version, if thepower-good functionality is not being used, ground this pin or leave floating. For
the push-pull version, if the power-good functionality is not being used, leavethis pin floating.

—

The thermal pad is electrically connected to the GND node. Connect to the GND
plane for improved thermal performance.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)Voltage

6.5

Enable, VEN

–0.3

6.5

Feedback, VFB

–0.3

2.0

Power-good, VPG

–0.3

6.5

Output, VOUT

–0.3

VIN + 0.3(2)

UNIT

V

Internally limited

Power-good, IPG

Temperature

(2)

MAX

–0.3

Output, IOUT

Current(1)

MIN
Supply, VIN±10Operating junction, TJ

–40

150

Storage, Tstg

–65

150

mA
°C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stressratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated underRecommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The absolute maximum rating is VIN + 0.3 V or 6.0 V, whichever is smaller.

6.2 ESD Ratings
VALUE

V(ESD)(1)

Electrostatic discharge

Human-body model (HBM), per AEC Q100-002(1)±2000

Charged-device model (CDM), per AEC Q100-011, corner pins

±750

Charged-device model (CDM), per AEC Q100-011, other pins

±500

UNIT

V

AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN

MAX

UNIT

1.5

6.0

V

Adjustable version

0.55

5.5

Fixed version

0.65

5.0
1

Input voltage

VOUT

Output voltage

IOUT

Output current

0

CIN

Input capacitor

1

COUT

Output capacitor(1)1

CFF

Feed-forward capacitor

VEN

Enable voltage

fEN

Enable toggle frequency

VPG

PG voltage

TJ

Junction temperature

NOM

(1)

Minimum derated capacitance of 0.47 µF is required for stability.

4

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A
µF

220
10

0

V

µF
nF

6.0

V

10

kHz

0

6.0

V

–40

150

°C

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6.4 Thermal Information
TPS746-Q1
THERMAL METRIC(1)DRV (WSON)DRB (VSON)

6 PINS

8 PINS

UNIT

RθJA

Junction-to-ambient thermal resistance

80.3

55.5

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

98.7

70.7

°C/W

RθJB

Junction-to-board thermal resistance

44.8

28.0

°C/W

ψJT

Junction-to-top characterization parameter

6.1

4.3

°C/W

ψJB

Junction-to-board characterization parameter

45.0

28.0

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

20.8

10.2

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics
at operating temperature range (TJ = –40°C to +150°C), VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values at TJ = 25°C
PARAMETERVFBTEST CONDITIONS

Feedback voltage
Output accuracy(1)0.55-40°C ≤ TJ ≤ 85°C

–1.00%

1.00%-40°C ≤ TJ ≤ 150°C–1.50%

VOUT(NOM) + 0.5 V(2) ≤ VI N ≤ 6.0 V

Load regulation

0.1 mA ≤ IOUT ≤ 1 A, VIN ≥ 2.0 V
IOUT = 0 mA

ISHDN

Shutdown current

VEN ≤ 0.3 V,
1.5 V ≤ VIN ≤ 6.0 V

IFB

Feedback pin current

Adjustable only

ICL

Output current limit

PSRR

VN

Dropout voltage

Power-supply rejection ratio

Output noise voltage

VUVLO

Undervoltage lockout

VUVLO,HYSTUndervoltage lockout
hysteresis

0.030

mV
V/A

32

-40°C ≤ TJ ≤ 150°C

25

36-40°C ≤ TJ ≤ 125°C

0.1

1-40°C ≤ TJ ≤ 150°C

0.1

1.55

0.01

0.1

µA

1.22

1.5

1.83

A

500

680

850

mA

0.65 V ≤ VOUT < 0.8 V(3)

895

1090

0.8 V ≤ VOUT < 0.9 V

765

960

0.9 V ≤ VOUT < 1.0 V

700

890

1.0 V ≤ VOUT < 1.2 V

600

790

1.2 V ≤ VOUT < 1.5 V

465

625

1.5 V ≤ VOUT < 1.8 V

335

480

1.8 V ≤ VOUT < 2.5 V

265

400

2.5 V ≤ VOUT < 3.3 V

195

310

3.3 V ≤ VOUT ≤ 5.5 V

160

265

f = 1 kHz53

f = 100 kHz

38

f = 1 MHz30

VOUT(NOM) < 1 V,
VIN = 2.0 V
VOUT(NOM) ≥ 1 V,
VIN = VOUT(NOM) + 1.0 V

VOUT = 1.8 V,
VIN = 2.8 V,
IOUT = 1 A,
COUT = 2.2 µF

7.5

25

VOUT(NOM) ≥ 1 V,
VOUT = VOUT(NOM) × 0.85, VIN = VOUT(NOM) + 1.0 V

IOUT = 1 A,
VOUT = 0.95 x VOUT(NOM)

1.50%
2

TJ = 25°C

VOUT(NOM) < 1 V,
VOUT = VOUT(NOM) - 0.2 V, VIN = 2.0 V

VOUT = 0 V

UNIT
V

0.85%

Ground current

VDO

MAX

–0.85%

Line regulation

Short-circuit current limit

TYP

TJ = 25°C

IGND

ISC

MIN

BW = 10 Hz to 100 kHz, VOUT = 0.9 V, VIN = 1.9 V

53

mV

µVRMS

1.21

1.33

1.47

VIN falling

1.17

1.29

1.42

40

µA

dB

VIN rising

VIN hysteresis

µA

V
mV

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6.5 Electrical Characteristics (continued)
at operating temperature range (TJ = –40°C to +150°C), VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values at TJ = 25°C
PARAMETERTEST CONDITIONS
From EN low-to-high transition to VOUT = VOUT(NOM) x
95%

MIN

TYP

MAX

UNIT

200

500

650

µs

tSTR

Startup time

VHI

EN pin high voltage(enabled)

VLO

EN pin low voltage(disabled)

IEN

Enable pin current

VIN = VEN = 6.0 V

RPULLDOWN

Pulldown resistance

VIN = 6.0 V

PGHTH

PG high threshold

VOUT increasing

89

92

96

%VOUT

PGLTH

PG low threshold

VOUT decreasing

86

90

93

%VOUT

PGHYSTPG hysteresis

1.0

V
0.3
10

nA

95

Ω

2

VOL(PG)PG pin low-level output
voltage

VOH(PG)PG pin high-level output
voltage(4)Ilkg(PG)

PG pin leakage current(5)TSD

Thermal shutdown

V

%VOUT

VIN ≥ 1.5 V, ISINK = 1 mA300

VIN ≥ 2.75 V, ISINK = 2 mA

mV

VOUT ≥ 1.0 V, ISOURCE = 0.04 mA
VOUT ≥ 1.4 V, ISOURCE = 0.2 mA

0.8 × VOUT

VOUT ≥ 2.5 V, ISOURCE = 0.5 mA

V

VOUT ≥ 4.5 V, ISOURCE = 1.0 mA

(1)
(2)
(3)
(4)
(5)

VOUT > PGHTH, VPG = 6.0 V

7Shutdown, temperature increasing

170

Reset, temperature decreasing

155

50

nA
°C

When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.
VIN = 1.5V for VOUT < 1.0 V
Dropout is not tested for nominal output voltages below 0.65 V since the input voltage may be below UVLO.
Push-pull version only. The push-pull option is supported only for VOUT ≥ 1.0 V.
Open-drain version only.

6.6 Timing Requirements
PARAMETER

MIN

NOM

MAX

tPGDH

PG delay time rising, time from 92% VOUT to 20%
of PG(1)

135

165

178

µs

4.5

5

5.5

ms

tPGDL

PG delay time falling, time from 90% VOUT to 80% of PG(1)

1.5

7

10

µs

'B' version(2)

(1)
(2)

Output overdrive = 10%.
See the Device Nomenclature table for more information on available PG timings.

6

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6.7 Typical Characteristics

0.6

0.6

0.45

0.45

Output Voltage Accuracy (%)

Output Voltage Accuracy (%)

at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN,
and CIN = COUT = 1 μF (unless otherwise noted)

0.3
0.15
0
-0.15
-0.3
-0.45
-0.6
3.8

4

4.2

TJ
± qC
0qC

±
±

qC
qC

4.4

4.6

4.8

5

25qC
85qC
5.2

5.4

125qC
150qC
5.6

5.8

0.3
0.15
0
-0.15
-0.3
-0.45

±
±

-0.6
1.5

6

2

2.5

3

Input Voltage (V)

3.5

4

25qC
85qC
4.5

125qC
150qC
5

5.5

6

0.9

1

0.9

1

Input Voltage (V)VOUT = 3.3 V, IOUT = 1 mA

VOUT = 0.55 V, IOUT = 1 mA

Figure 6-1. 3.3-V Line Regulation vs VIN

Figure 6-2. 0.55-V Line Regulation vs VIN
320

0.3

±
±

qC
qC

0.1

0.2

280

0.2

Dropout Voltage (mV)

Output Voltage Accuracy (%)

TJ
± qC
0qC

qC
qC

0.1
0
-0.1
TJ
± qC
0qC

-0.2
±
±
-0.3
5.5

qC
qC

25qC
85qC

TJ
± qC
0qC

25qC
85qC

125qC
150qC

240
200
160
120
80
40

125qC
150qC

0
5.6

5.7

5.8

5.9

6

0

0.3

Input Voltage (V)

0.4

0.5

0.6

0.7

0.8

Output Current (A)VOUT = 5.5 V, IOUT = 1 mA
Figure 6-3. 5.5-V Line Regulation vs VIN

Figure 6-4. 3.3-V Dropout Voltage vs IOUT
320

1,280
±
±

qC
qC

25qC
85qC

125qC
150qC

±
±

qC
qC

0.1

0.2

280

Dropout Voltage (mV)

Dropout Voltage (mV)

1,200

TJ
± qC
0qC

1,120
1,040
960
880
800
720

TJ
± qC
0qC

25qC
85qC

125qC
150qC

240
200
160
120
80
40

640
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Output Current (A)

0.9

1

0
0

0.3

0.4

0.5

0.6

0.7

0.8

Output Current (A)Figure 6-5. 0.55-V Dropout Voltage vs IOUT

Figure 6-6. 5.5-V Dropout Voltage vs IOUT

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6.7 Typical Characteristics (continued)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN,
and CIN = COUT = 1 μF (unless otherwise noted)
1,200

1,100
±
±

Dropout Voltage (mV)

900

TJ
± qC
0qC

qC
qC

25qC
85qC

125qC
150qC

1,050

Ground Pin Current (PA)

1,000

800
700
600
500
400
300
200

900
750
600
450
300
150

100
0
0.5

±
±

qC
qC

TJ
± qC
0qC

25qC
85qC

0.5

0.7

125qC
150qC

0
1

1.5

2

2.5

3

3.5

4

4.5

5

0

0.1

0.2

0.3

Output Voltage (V)

0.4

0.6

0.8

0.9

1

Output Current (A)IOUT = 1 A
Figure 6-7. VDO vs VOUT

Figure 6-8. IGND vs IOUT
560

2,100

Shutdown Current (nA)

TJ
± qC
0qC

qC
qC

25qC
85qC

125qC
150qC

±
±

480

Ground Pin Current (PA)

±
±

1,800
1,500
1,200
900
600
300
0

0

25qC
85qC

3

4.2

125qC
150qC

400
320
240
160
80

0.6

1.2

1.8

2.4

3

3.6

4.2

4.8

5.4

-80

6

0

Input Voltage (V)

0.6

1.2

1.8

2.4

3.6

4.8

5.4

6

Input Voltage (V)VEN = 0 V

VOUT = 3.3 V, IOUT = 0 mA

Figure 6-9. ISHDN vs VIN

Figure 6-10. IGND vs VIN

1.6

0.8
±
±

1.2

TJ
± qC
0qC

qC
qC

25qC
85qC

125qC
150qC

±
±

0.6

0.8

Change in VOUT (%)

Change in VOUT (%)

TJ
± qC
0qC

0

-300

0.4
0
-0.4
-0.8
-1.2

qC
qC

TJ
± qC
0qC

25qC
85qC

0.5

0.7

125qC
150qC

0.4
0.2
0
-0.2
-0.4
-0.6

-1.6

-0.8
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0

0.1

Output Current (A)

0.2

0.3

0.4

0.6

0.8

0.9

1

Output Current (A)VIN = 3.8 V, VOUT = 3.3 V

VIN = 2 V, VOUT = 0.55 V

Figure 6-11. 3.3-V Load Regulation vs IOUT

8

qC
qC

Figure 6-12. 0.55-V Load Regulation vs IOUT

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6.7 Typical Characteristics (continued)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN,
and CIN = COUT = 1 μF (unless otherwise noted)
1.2

640

±
±

qC
qC

25qC
85qC

125qC
150qC

±
±

qC
qC

0.5

1

560

0.6

Output Voltage (mV)

Change in VOUT (%)

0.9

TJ
± qC
0qC

0.3
0
-0.3
-0.6

TJ
± qC
0qC

25qC
85qC

125qC
150qC

480
400
320
240
160
80

-0.9

0

-1.2
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0

1

1.5

2

2.5

3

3.5

4

4.5

5

Pulldown Current (mA)

Output Current (A)VIN = 6 V, VOUT = 5 V
Figure 6-14. VOUT vs IOUT Pulldown Resistor

92.5
92.25
92
91.75
91.5
91.25
91
90.75
90.5
90.25
90
89.75
89.5
89.25
89
-50

40
35

PG Leakage Current (nA)PG Pin Thresholds (%)

Figure 6-13. 5-V Load Regulation vs IOUT

PGLTH
-30

-10

10

30

50

70

90

110

25
20
15
10
5
0

PGHTH

-5

130

-10
-50

150

Temperature (qC)

PG = 3.3 V
-25

0

25

50

75

PG = 5.5 V
100

125

150

Temperature (qC)

Figure 6-15. PGLTH and PGHTH vs Temperature

Figure 6-16. IIkg(PG) vs Temperature and PG Pin Voltage

300

166

±
±

240

TJ
± qC
0qC

qC
qC

tPGDH

25qC
85qC

125qC
150qC

PG Delay Time Rising (Ps)270

PG Pin Voltage Low (mV)

30

210
180
150
120
90
60

164
162
160
158
156
154
152

30
0
0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

150
-50

PG Pin Sink Current (mA)

-25

0

25

50

75

100

125

150

Temperature (qC)

VIN = 3.8 V, VOUT = 3.3 V
Figure 6-17. VOL(PG) vs PG Pin Sink Current

Figure 6-18. tPGDH vs Temperature

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6.7 Typical Characteristics (continued)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN,
and CIN = COUT = 1 μF (unless otherwise noted)
6.5

4.96
tPGDH

PG Delay Time Falling (Ps)PG Delay Time Rising (ms)

4.92
4.9
4.88
4.86
4.84
4.82
4.8
-50

tPGDL

6.1

4.94

5.7
5.3
4.9
4.5
4.1
3.7
3.3
2.9

-25

0

25

50

75

100

125

2.5
-50

150

Temperature (qC)

-25

50

75

100

125

150

Figure 6-20. tPGDL vs Temperature

840

300
VEN(LO)

800

VEN(HI)

±
±

250

760

Enable Pin Current (PA)

Enable Threshold (mV)25

Temperature (qC)

Figure 6-19. tPGDH vs Temperature (For TPS746B Only)

720
680
640
600
560
520

TJ
± qC
0qC

qC
qC

125qC
85qC

125qC
150qC

200
150
100
50
0

480
440
-50

0

-50
-25

0

25

50

75

100

125

150

0

0.5

1

1.5

Temperature (qC)

2

2.5

3

3.5

4

4.5

5

5.5

Input Voltage (V)VEN = 5.5 V
Figure 6-21. VEN(HI) and VEN(LO) vs Temperature
5
4.5

-50qC
-40qC

25qC
85qC

1

1.4

125qC
Input Voltage (V)Output Voltage (V)

4

TJ
-20qC
0qC

3.5
3
2.5
2
1.5
1
0.5

0

0
0

0.2

0.4

0.6

0.8

1.2

1.6

1.8

Output Current (A)

2

0.5

1.5

VOUT = 0.55 V, IOUT = 1 mA, VIN slew rate = 1 V/µs

Figure 6-23. 3.3-V Foldback Current Limit vs IOUT

10

1Time (ms)

25
Vin
20
Vout 15
10
5
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
2

AC-coupled Output Voltage (mV)

Figure 6-22. IEN vs VIN
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

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Figure 6-24. 0.55-V Line Transient

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6.7 Typical Characteristics (continued)

0.2

0.4

0.6

0.8
1
1.2
Time (ms)

1.4

1.6

200
Iout
Vout 150
100

4
3.5
3

50

2.5

0

2

-50

1.5

-100

1

-150

0.5

-200

0

-250

-0.5

-300
500

0

Output Current (A)

3.5

240

4.5

160

4

80

3

0

2.5

-80

2

-160

1.5

-240

1

-320

0.5

-400

0

-480

-0.5

-560
500

100

150

200 250 300
Time (us)

350

400

200 250 300
Time (us)

350

400

450

450

240
Iout
Vout

160

3.5

Output Current (A)

Iout
Vout

AC-coupled Output Voltage (mV)

4.5

50

150

Figure 6-26. 1-mA to 1-A Load Transient (0.55 V)

Figure 6-25. 3.3-V Line Transient

0100

VOUT = 0.55 V, VIN = 2 V, IOUT slew rate = 1 A/µs

VOUT = 3.3 V, IOUT = 1 mA, VIN slew rate = 1 V/µs

450

AC-coupled Output Voltage (mV)

4.5

80

3

0

2.5

-80

2

-160

1.5

-240

1

-320

0.5

-400

0

-480

-0.5

-560
600

0

VOUT = 5 V, VIN = 5.5 V, IOUT slew rate = 1 A/µs

60

120

180

240 300 360
Time (us)

420

480

540

AC-coupled Output Voltage (mV)

0

120
Vin
100
Vout 80
60
40
20
0
-20
-40
-60
-80
-100
-120
-140
-160
1.8
2

Output Current (A)

10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3

AC-coupled Output Voltage (mV)

Input Voltage (V)at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN,
and CIN = COUT = 1 μF (unless otherwise noted)

VOUT = 3.3 V, VIN = 3.8 V, IOUT slew rate = 1 A/µs

Figure 6-27. 1-mA to 1-A Load Transient (5 V)

Figure 6-28. 1-mA to 1-A Load Transient (3.3 V)
5

5
4.5
4

4

3.5

3

Voltage (V)Voltage (V)

3
2.5
2
1.5
1

2
1

0.5
0

Vout
Vin

-0.5
-1
0

200

400
600
Time (us)

800

1,000

Vout
Venable
Vin

0
-1
0

VIN = 3.8 V, VOUT = 3.3 V, IOUT = 1 mA
Figure 6-29. VIN Power-Up

200

400
600
Time (us)

800

1,000

VIN = 3.8 V, VOUT = 3.3 V, IOUT = 1 mA
Figure 6-30. Startup With EN

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6.7 Typical Characteristics (continued)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN,
and CIN = COUT = 1 μF (unless otherwise noted)
90
VIN = 3.5 V
VIN = 3.6 V
VIN = 3.7 V
VIN = 3.8 V

80
70

Power-Supply Rejection Ratio (dB)

Power-Supply Rejection Ratio (dB)

90

60
50
40
30
20
10
0
10

100

1k

10k
100k
Frequency (Hz)

1M

80
70
60
50
40
30
20
10
0
10

10M

80
70
60
50
40
30
20
10
100

1k

10k
100k
Frequency (Hz)1MPower-Supply Rejection Ratio (dB)

Power-Supply Rejection Ratio (dB)

1M

10M

90
VIN = 3.5 V
VIN = 3.6 V
VIN = 3.7 V
VIN = 3.8 V

80
70
60
50
40
30
20
10

VIN = 3.9 V
VIN = 4.0 V
VIN = 4.1 V
VIN = 4.2 V
VIN = 4.3 V

0
10

10M

VOUT = 3.3 V, IOUT = 250 mA, COUT = 2.2 µF

100

1k

10k
100k
Frequency (Hz)

1M

10M

VOUT = 3.3 V, IOUT = 250 mA, COUT = 2.2 µF

Figure 6-33. PSRR vs Frequency and VIN

Figure 6-34. PSRR vs Frequency and VIN90

VIN = 1.9 V, VOUT = 0.9 V
VIN = 2.8 V, VOUT = 1.8 V
VIN = 4.3 V, VOUT = 3.3 V

80
70
60
50
40
30
20
10
100

1k

10k
100k
Frequency (Hz)

1M

10M

Power-Supply Rejection Ratio (dB)90Power-Supply Rejection Ratio (dB)

10k
100k
Frequency (Hz)Figure 6-32. PSRR vs Frequency and VIN90

VIN = 2.3 V, VOUT = 1.8 V
VIN = 2.8 V, VOUT = 1.8 V
VIN = 3.8 V, VOUT = 3.3 V
VIN = 4.3 V, VOUT = 3.3 V

80
70
60
50
40
30
20
10
0
10

IOUT = 500 mA, COUT = 2.2 µF

100

1k

10k
100k
Frequency (Hz)

1M

10M

IOUT = 1 A, COUT = 2.2 µF

Figure 6-35. PSRR vs Frequency

12

1k

VOUT = 3.3 V, IOUT = 500 mA, COUT = 2.2 µF

Figure 6-31. PSRR vs Frequency and VIN

0
10

100

D001

VOUT = 3.3 V, IOUT = 500 mA, COUT = 2.2 µF

010

VIN = 3.9 V
VIN = 4.0 V
VIN = 4.1 V
VIN = 4.2 V
VIN = 4.3 V

Figure 6-36. PSRR vs Frequency

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6.7 Typical Characteristics (continued)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN,
and CIN = COUT = 1 μF (unless otherwise noted)
90
COUT = 1 PF
COUT = 2.2 PF
COUT = 4.7 PF
COUT = 47 PF

80
70
60
50
40
30
20
10
0
10

100

1k

10k
100k
Frequency (Hz)

1M

70
60
50
40
30
20
10
100

1k

10k
100k
Frequency (Hz)1M

VIN = 3.8 V, VOUT = 3.3 V, IOUT = 500 mA

VIN = 3.8 V, VOUT = 3.3 V, IOUT = 500 mA

Figure 6-37. PSRR vs Frequency and COUT

Figure 6-38. PSRR vs Frequency and CFF

90

20

80

10

10M

IOUT= 100mA, 170PVRMSIOUT= 500mA, 169PVRMSIOUT= 1A, 160PVRMS

5

70

2

60
50
40
30
ILOAD = 10 mA
ILOAD = 100 mA
ILOAD = 250 mA
ILOAD = 500 mA
ILOAD = 1 A

20
10
0
-10
10

100

1k

1
0.5
0.2
0.1
0.05
0.02
0.01

10k
100k
Frequency (Hz)

1M

0.005
10

10M

100

1k

10k
100k
Frequency (Hz)

1M

10M

VIN = 3.8 V, VOUT = 3.3 V, COUT = 2.2 µF

VIN = 3.8 V, VOUT = 3.3 V, COUT = 4.7 µF, VRMS BW = 10 Hz to
100 kHz

Figure 6-39. PSRR vs Frequency and ILOAD

Figure 6-40. Output Spectral Noise Density vs Frequency and
IOUT

20

20
IOUT= 10mA, 159PVRMSIOUT= 100mA, 160PVRMSIOUT= 500mA, 160PVRMS

105CFF = 0 nF, 160 PVRMS
CFF = 1 nF, 108 PVRMS
CFF = 10 nF, 74 PVRMS
CFF = 100 nF, 44 PVRMS

1052Noise (PV/—Hz)2

Noise (PV/—Hz)CFF = 0 nF
CFF = 1 nF
CFF = 10 nF
CFF = 100 nF

80

0
10

10M

Noise (PV/—Hz)Power-Supply Rejection Ratio (dB)

Power-Supply Rejection Ratio (dB)

Power-Supply Rejection Ratio (dB)

90

1
0.5
0.2
0.1

1
0.5
0.2
0.1

0.05

0.05

0.02

0.02

0.01

0.01

0.005
10

0.005
10

100

1k

10k
100k
Frequency (Hz)

1M

10M

100

1k

10k
100k
Frequency (Hz)

1M

10M

VIN = 3.8 V, VOUT = 3.3 V, COUT = 2.2 µF, VRMS BW = 10 Hz to
100 kHzVIN = 3.8 V, VOUT = 3.3 V, IOUT = 500 mA, COUT = 2.2 µF, VRMS
BW = 10 Hz to 100 kHz

Figure 6-41. Output Spectral Noise Density vs Frequency and
IOUT

Figure 6-42. Output Spectral Noise Density vs Frequency and
CFF

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6.7 Typical Characteristics (continued)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN,
and CIN = COUT = 1 μF (unless otherwise noted)
20

20
COUT = 2.2PF, 160 PVRMS
COUT = 4.7PF, 170 PVRMS
COUT = 47PF, 138 PVRMS

10
5

5
2

Noise (PV/—Hz)

Noise (PV/—Hz)

2
1
0.5
0.2
0.1

1
0.5
0.2
0.1

0.05

0.05

0.02

0.02

0.01

0.01

0.005
10

0.005
10

100

1k

10k
100k
Frequency (Hz)

1M

10M

VIN = 3.8 V, VOUT = 3.3 V, IOUT = 100 mA, CFF = 0 µF, VRMS
BW = 10 Hz to 100 kHz
Figure 6-43. Output Spectral Noise Density vs Frequency and
COUT

14

VIN=1.9V, VOUT=0.9V, 53PVRMS
VIN=2.8V, VOUT=1.8V, 96PVRMS
VIN=3.8V, VOUT=3.3V, 160PVRMS

10

100

1k

10k
100k
Frequency (Hz)

1M

10M

IOUT = 500 mA, COUT = 2.2 µF, VRMS BW = 10 Hz to 100 kHz
Figure 6-44. Output Spectral Noise Density vs Frequency

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7 Detailed Description
7.1 Overview
The TPS746-Q1 is a low-dropout regulator (LDO) that consumes low quiescent current and delivers excellent
line and load transient performance. These characteristics, combined with low noise and good PSRR with low
dropout voltage, make this device ideal for portable consumer applications.
This regulator offers foldback current limit, shutdown, and thermal protection. The operating junction temperature
for this device is –40°C to +150°C.

7.2 Functional Block Diagrams

IN

OUT
Current
Limit

±

+

ThermalShutdown

95 Ÿ
FB

UVLO

PG
±
0.90 x VREF
EN+

Band Gap

GND
Logic

Figure 7-1. Adjustable Version With Open-Drain Power-GoodIN

OUT
Current
Limit

±

+

ThermalShutdown

95 Ÿ
FB

UVLO

PG
±
0.90 x VREF
EN+

Band Gap

GND
Logic

Figure 7-2. Adjustable Version With Push-Pull Power-Good

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IN

OUT
Current
Limit

±

+

ThermalShutdown

95 Ÿ

UVLO
PG
±
0.90 x VREF
EN+

Band Gap

GND
Logic

Figure 7-3. Fixed Voltage Version With Open-Drain Power-GoodIN

OUT
Current
Limit

±

+

ThermalShutdown

95 Ÿ

UVLO
PG
±
0.90 x VREF
EN+

Band Gap

GND
Logic

Figure 7-4. Fixed Voltage Version With Push-Pull Power-Good

16

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7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)The TPS746-Q1 uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage
is greater than the rising UVLO voltage (VUVLO). This circuit ensures that the device does not exhibit any
unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry.
When VIN is less than VUVLO, the output is connected to ground with a pulldown resistor (RPULLDOWN).
7.3.2 Shutdown
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(HI). Turn off the device
by forcing the EN pin to drop below VEN(LO). If shutdown capability is not required, connect EN to IN.
The TPS746-Q1 has an internal pulldown MOSFET that connects an RPULLDOWN resistor to ground when thedevice is disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load
resistance (RL) in parallel with the pulldown resistor (RPULLDOWN). Equation 1 calculates the time constant:τ = ( RPULLDOWN × RL) / (RPULLDOWN + RL)(1)

7.3.3 Foldback Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brick-wall-foldback scheme. The current limit transitions from abrick-wall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault withthe output voltage above VFOLDBACK, the brick-wall scheme limits the output current to the current limit (ICL).
When the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as theoutput voltage approaches GND. When the output is shorted, the device supplies a typical current called theshort-circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
For this device, VFOLDBACK = 0.4 × VOUT(NOM).
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, thedevice begins to heat up because of the increase in power dissipation. When the device is in brick-wall current
limit, the pass transistor dissipates power [(VIN – V OUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered,the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.
If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For
more information on current limits, see the Know Your Limits application report.

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Figure 7-5 shows a diagram of the foldback current limit.

VOUT
Brickwall
VOUT(NOM)

VFOLDBACKFoldback

IOUT

0V
0 mA

ISC

IRATED

ICL

Figure 7-5. Foldback Current Limit
7.3.4 Thermal Shutdown
Thermal shutdown protection disables the output when the junction temperature rises to approximately 170°C.
Disabling the device eliminates the power dissipated by the device, allowing the device to cool. When thejunction temperature cools to approximately 155°C, the output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off.
This cycling limits regulator dissipation, protecting the LDO from damage as a result of overheating.
Activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the productof the (VIN – VOUT) voltage and the load current. For reliable operation limit junction temperature to 125°C,
maximum. To estimate the margin of safety in a complete design, increase the ambient temperature until thethermal protection is triggered; use worst-case loads and signal conditions.
The TPS746-Q1 internal protection circuitry protects against overload conditions but is not intended to be
activated in normal operation. Continuously running the TPS746-Q1 into thermal shutdown degrades device
reliability.

18

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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
The Device Functional Mode Comparison table shows the conditions that lead to the different modes ofoperation. See the Electrical Characteristics table for parameter values.
Table 7-1. Device Functional Mode Comparison
PARAMETER

OPERATING MODE

VIN

VEN

IOUT

TJ

Normal operation

VIN > VOUT(nom) + VDO and VIN > VIN(min)VEN > VEN(HI)IOUT < IOUT(max)

TJ < TSD(shutdown)

Dropout operation

VIN(min) < VIN < VOUT(nom) + VDO

VEN > VEN(HI)IOUT < IOUT(max)

TJ < TSD(shutdown)

Disabled(any true condition
disables the device)

VIN < VUVLO

VEN < VEN(LOW)

Not applicable

TJ > TSD(shutdown)

7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:•••

The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)•

The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased
to less than the enable falling threshold

7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all otherconditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or loadtransients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into theohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum
EN pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor isturned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal
discharge circuit from the output to ground.

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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible fordetermining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information
8.1.1 Adjustable Device Feedback Resistors
Figure 8-1 shows that the output voltage of the TPS746P-Q1 can be adjusted from 0.55 V to 5.5 V by using a
resistor divider network.
VIN

VOUT

OUT

IN

Cff

TPS746-Q1

CIN

EN

FB

GND

PG

COUT

R1
RPG*
R2

*Pull-up resistor not requiredfor push-pull option

Figure 8-1. Adjustable Operation
The adjustable-version device requires external feedback divider resistors to set the output voltage. VOUT is set
using the feedback divider resistors, R1 and R2, according to the following equation:
VOUT = VFB × (1 + R1 / R2)(2)

To ignore the FB pin current error term in the VOUT equation, set the feedback divider current to 100x the FB pin
current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider series
resistance, as shown in the following equation:
R1 + R2 ≤ VOUT / (IFB × 100)(3)

8.1.2 Input and Output Capacitor Selection
The TPS746-Q1 requires an output capacitance of 0.47 µF or larger for stability. Use X5R- and X7R-type
ceramic capacitors because these capacitors have minimal variation in value and equivalent series resistance(ESR) over temperature. When choosing a capacitor for a specific application, pay attention to the dc bias
characteristics for the capacitor. Higher output voltages cause a significant derating of the capacitor. For best
performance, the maximum recommended output capacitance is 220 µF.
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input
supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improvestransient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of
frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use ahigher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several
inches from the input power source.

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8.1.3 Dropout Voltage
The TPS746-Q1 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the
dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output
resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because
the PMOS device behaves like a resistor in dropout mode. As with any linear regulator, PSRR and transient
response degrade as (VIN – VOUT) approaches dropout operation.
8.1.4 Exiting Dropout
Some applications have transients that place the LDO into dropout, such as slower ramps on VIN during start-up.
As with other LDOs, the output may overshoot on recovery from these conditions. A ramping input supply
causes an LDO to overshoot on start-up, as shown in Figure 8-2, when the slew rate and voltage levels are in
the correct range. Use an enable signal to avoid this condition.
Input Voltage
Response time for
LDO to get back into
regulation.

Load current discharges
output voltage.

VIN = VOUT(nom) + VDO

Voltage

Output Voltage
Dropout
VOUT = VIN - VDO

Output Voltage innormal regulation.

Time

Figure 8-2. Start-Up Into Dropout
Line transients out of dropout can also cause overshoot on the output of the regulator. These overshoots arecaused by the error amplifier having to drive the gate capacitance of the pass element and bring the gate back to
the correct voltage for proper regulation. Figure 8-3 illustrates what is happening internally with the gate voltage
and how overshoot can be caused during operation. When the LDO is placed in dropout, the gate voltage (VGS)
is pulled all the way down to ground to give the pass device the lowest on-resistance as possible. However, if
a line transient occurs when the device is in dropout, the loop is not in regulation and can cause the output toovershoot until the loop responds and the output current pulls the output voltage back down into regulation. If
these transients are not acceptable, then continue to add input capacitance in the system until the transient isslow enough to reduce the overshoot.

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Figure 8-3. Line Transients From Dropout
8.1.5 Reverse Current
As with most LDOs, excessive reverse current can damage this device.
Reverse current flows through the body diode on the pass element instead of the normal conducting channel.
At high magnitudes, this current flow degrades the long-term reliability of the device, as a result of one of thefollowing conditions:• Degradation caused by electromigration• Excessive heat dissipation• Potential for a latch-up condition
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT > VIN + 0.3 V:• If the device has a large COUT and the input supply collapses with little or no load current• The output is biased when the input supply is not established• The output is biased above the input supply
22

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If reverse current flow is expected in the application, external protection must be used to protect the device.
Figure 8-4 shows one approach of protecting the device.
Schottky Diode

IN

CIN

Internal Body Diode

OUT

DeviceCOUT

GND

Figure 8-4. Example Circuit for Reverse Current Protection Using a Schottky Diode8.1.6 Power Dissipation (PD)Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. Equation 4 calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT

(4)

Note
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage
required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain anarray of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to Equation 5, power dissipation and junction temperature are most often related by the junction-toambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambientair (TA).
TJ = TA + (RθJA × PD)(5)Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.

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Figure 8-5 and Figure 8-6 show the functions of RθJA and ψJB versus copper area and thickness. These plots
are generated with a 101.6-mm × 101.6-mm × 1.6-mm PCB of two and four layers. For the four layer board, theinner planes use 1-oz copper thickness. Outer layers are simulated with both 1-oz and 2-oz copper thickness. A
2 x 1 array of thermal vias of 300-µm drill diameter and 25-µm copper (Cu) plating is located beneath the thermal
pad of the device. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board,the first inner GND plane. Each of the layers has a copper plane of equal area, as shown in Figure 8-7.
140
2 layer PCB, 1 oz copper
2 layer PCB, 2 oz copper
4 layer PCB, 1 oz copper
4 layer PCB, 2 oz copper

130

Thermal Resistance - RTJA (qC/W)

120
110
100
90
80
70
60
50
40
30
0

10

20

30

40
50
60
Cu Area Per Layer (cm2)

70

80

90

100
thet

Figure 8-5. RθJA versus Cu Area for the WSON (DRV) Package
36
2 layer PCB, 1 oz copper
2 layer PCB, 2 oz copper
4 layer PCB, 1 oz copper
4 layer PCB, 2 oz copper

Thermal Resistance - <JB (qC/W)

34
32
30
28
26
24
22
20
0

10

20

30

40
50
60
Cu Area Per Layer (cm2)

70

80

90

100
psyJ

Figure 8-6. ψJB versus Cu Area for the WSON (DRV) Package

24

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As shown in Figure 8-7, each of the layers has a copper plane of equal area.

A

2-mm
A

1-mm

Buried plane and bottom layer Cu groundplanes are modeled with Area = A×A

Figure 8-7. Board Parameters Used for Simulation
For a more comprehensive study of how thermal resistance varies with copper area and thickness, see the An
Empirical Analysis of the Impact of Board Layout on LDO Thermal Performance application report. As shown in
Figure 8-8, modifying board layout to be more thermally enhanced can lower the RθJA value from 80.3°C/W to
46.8°C/W or better.

Figure 8-8. TPS746-Q1 (WSON) RθJA vs Board Layout
8.1.7 Power-Good Function
The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage.
When the output voltage falls below the PG threshold voltage (PGLTH), the PG pin open-drain output engages
and pulls the PG pin close to GND. When the output voltage exceeds PGHTH, the PG pin becomes highimpedance. The open-drain output requires a pullup resistor. By connecting a pullup resistor to an external
supply, any downstream device can receive power-good as a logic signal that can be used for sequencing.
Additionally, the open-drain output can be tied to other open-drain outputs to implement AND logic. Make sure
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that the external pullup supply voltage results in a valid logic signal for the receiving device. Using a pullup
resistor from 10 kΩ to 100 kΩ is recommended. The push-pull power-good output option does not require thepullup resistor and instead has a high logic signal that correlates with the output voltage of the device. The
push-pull option is supported only for VOUT ≥ 1.0 V. Do not tie the push-pull output to other logic outputs.
When using a feed-forward capacitor (CFF), the time constant for the LDO startup is increased whereas thepower-good output time constant stays the same, possibly resulting in an invalid status of the power-good
output. To avoid this issue, and to receive a valid PG output, make sure that the time constant of both the
LDO startup and the power-good output match, which can be done by adding a capacitor in parallel with thepower-good pullup resistor. For more information, see the Pros and Cons of Using a Feedforward Capacitor witha Low-Dropout Regulator application report.
The state of PG is only valid when the device operates above the minimum input voltage of the device andpower-good is asserted, regardless of the output voltage state when the input voltage falls below the UVLO
threshold minus the UVLO hysteresis. When the input voltage falls below approximately 0.8 V, there is notenough gate drive voltage to keep the open-drain, power-good device turned on and the power-good output
pulled high. Connecting the power-good pullup resistor to the output voltage can help minimize this effect.
8.1.8 Feed-Forward Capacitor (CFF)
For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin
to the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability.
Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance
CFF can be used; however, the startup time increases. For a detailed description of CFF tradeoffs, see the Pros
and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.
8.1.9 Start-Up Sequencing
If VEN is greater than VUVLO rising (min), the input pin (IN) must sink 1 mA of current to avoid the device being
turned on with a floating input pin.

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8.2 Typical Application
Figure 8-9 shows the typical application circuit for the TPS746P-Q1. Input and output capacitances must be atleast 1 µF.
VIN

VOUT

OUT

IN

Cff

TPS746-Q1

CIN

EN

FB

GND

PG

COUT

R1
RPG*
R2

*Pull-up resistor not requiredfor push-pull option

Figure 8-9. TPS746-Q1 Typical Application
8.2.1 Design Requirements
Use the parameters listed in Table 8-1 for typical linear regulator applications.
Table 8-1. Design Parameters
PARAMETERDESIGN REQUIREMENT

Input voltage

3.8 V

Output voltage

3.3 V, ±1%

Input current

1.2 A (maximum)

Output load

1-A DC

Maximum ambient temperature

70°C

8.2.2 Detailed Design Procedure
Input and output capacitors are required to achieve the output voltage transient requirements. Capacitancevalues of 2.2 µF are selected to give the maximum output capacitance in a small, low-cost package; see theInput and Output Capacitor Selection section for details.
Figure 8-1 illustrates the output voltage of the TPS746-Q1. Set the output voltage using the resistor divider; see
the Adjustable Device Feedback Resistors section for details.
8.2.2.1 Input Current
During normal operation, the input current to the LDO is approximately equal to the output current of the LDO.
During startup, the input current is higher as a result of the inrush current charging the output capacitor. Use
Equation 6 to calculate the current through the input.
IOUT(t) =COUT ´ dVOUT(t)dt+

VOUT(t)RLOAD(6)where:•••

VOUT(t) is the instantaneous output voltage of the turn-on ramp
dVOUT(t) / dt is the slope of the VOUT ramp
RLOAD is the resistive load impedance

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8.2.2.2 Thermal Dissipation
The junction temperature can be determined using the junction-to-ambient thermal resistance (RθJA) and thetotal power dissipation (PD). Use Equation 7 to calculate the power dissipation. Multiply PD by RθJA as Equation
8 shows and add the ambient temperature (TA) to calculate the junction temperature (TJ).
PD = (IGND+ IOUT) × (VIN – VOUT)(7)

TJ = RθJA × PD + TA

(8)

Calculate the maximum ambient temperature as Equation 9 shows if the (TJ(MAX)) value does not exceed 125°C.
Equation 10 calculates the maximum ambient temperature with a value of 109.85°C.
TA(MAX) = TJ(MAX) – RθJA × PD

(9)

TA(MAX) = 150°C – 80.3°C/W × (3.8 V – 3.3 V) × (1 A) = 109.85°C(10)8.2.3 Application Curve

Power-Supply Rejection Ratio (dB)

90
80
70
60
50
40
30
20
10
0
-10
10

ILOAD = 10 mA
ILOAD = 100 mA
ILOAD = 250 mA
ILOAD = 500 mA
ILOAD = 1 A
100

1k

10k
100k
Frequency (Hz)

1M

10M

VIN = 3.8 V, VOUT = 3.3 V, COUT = 2.2 µF

Figure 8-10. PSRR vs Frequency and ILOAD

9 Power Supply Recommendations
The TPS745-Q1 is designed to operate from an input voltage supply range from 1.5 V to 6.0 V. The input voltage
range provides adequate headroom in order for the device to have a regulated output. This input supply must
be well regulated. If the input supply is noisy, additional input capacitors with low ESR may help improve output
noise performance. Connect a low output impedance power supply directly to the IN pin of the TPS746-Q1.

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10 Layout10.1 Layout Guidelines••••

Place input and output capacitors as close to the device as possible.
Use copper planes for device connections in order to optimize thermal performance.
Place thermal vias around the device to distribute heat.
Place a tented thermal via directly beneath the thermal pad of the DRV or DRB package. An untented via
can wick solder or solder paste away from the thermal pad joint during the soldering process, leading to acompromised solder joint on the thermal pad.

10.2 Layout Examples

COUT

Cff

R1

R2

CIN

1

6

2

5

3

4

RPG*

GND PLANE
Signal via to Pin1

*Pull-up resistor not required for push-pull option

Figure 10-1. Layout Example for the DRV Package

CIN

COUT

Cff

R1

1

8

2

7

3

6

4

5

RPG*

R2
GND PLANE
Signal via to Pin1

*Pull-up resistor not required for push-pull option

Figure 10-2. Layout Example for the DRB package

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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 11-1. Device Nomenclature(1) (2)PRODUCTVOUT
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are usedin the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V; 01 =adjustable).
P indicates an active output discharge feature. All members of the TPS746 family will actively discharge
the output when the device is disabled.
v indicates the topology of the power-good output and the timing associated with the power-good delay.

TPS746)xx(x)PvQWyyyzQ1•••

If unused, indicates an open-drain power-good output with a 150-µs delay.
If B, indicates an open-drain, power-good output with a 5-ms delay.
If C, indicates a push-pull, power-good output with a 150-µs delay.

Q indicates that this device is a Grade-1 device in accordance with the AEC-Q100 standard.
W indicates the package has wettable flanks.
yyy is the package designator.
z is the package quantity. R is for reel (3000 pieces).
Q1 indicates that this device is an automotive grade (AEC-Q100) device.
(1)(2)

For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit thedevice product folder on www.ti.com.
Output voltages from 0.65 V to 5.0 V in 50-mV increments are available. Contact the factory for details and availability.

11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:• Texas Instruments, Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator
application report• Texas Instruments, An Empirical Analysis of the Impact of Board Layout on LDO Thermal Performance
application report

11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. Forchange details, review the revision history included in any revised document.

11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straightfrom the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handledwith appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.

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11.7 Glossary
TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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23-Jun-2023

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking(3)

Samples

(4/5)

(6)

TPS74601PBQWDRVRQ1

ACTIVE

WSON

DRV

6

3000

RoHS & Green

Call TI

Level-1-260C-UNLIM-40 to 125

1S46

Samples

TPS74601PCQWDRVRQ1

ACTIVE

WSON

DRV

6

3000

RoHS & Green

Call TI

Level-1-260C-UNLIM-40 to 125

1OZ6

Samples

TPS74601PQWDRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

74601P

Samples

TPS74601PQWDRVRQ1

ACTIVE

WSON

DRV

6

3000

RoHS & GreenSN

Level-1-260C-UNLIM-40 to 125

1OW6

Samples

TPS74607PQWDRBRQ1

PREVIEW

SON

DRB

8

3000

TBD

Call TI

Call TI-40 to 125

TPS74610PQWDRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

74610P

Samples

TPS74610PQWDRVRQ1

ACTIVE

WSON

DRV

6

3000

RoHS & GreenSN

Level-1-260C-UNLIM-40 to 125

1SG6

Samples

TPS746115PQWDRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

746115

Samples

TPS74611PQWDRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

74611P

Samples

TPS74611PQWDRVRQ1

ACTIVE

WSON

DRV

6

3000

RoHS & GreenSN

Level-1-260C-UNLIM-40 to 125

1SH6

Samples

TPS746125PQWDRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

746125

Samples

TPS74612PQWDRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

74612P

Samples

TPS74612PQWDRVRQ1

ACTIVE

WSON

DRV

6

3000

RoHS & GreenSN

Level-1-260C-UNLIM-40 to 125

1SI6

Samples

TPS746135PQWDRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

746135

Samples

TPS74613PQWDRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

74613P

Samples

TPS74615PQWDRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

74615P

Samples

TPS74615PQWDRVRQ1

ACTIVE

WSON

DRV

6

3000

RoHS & GreenSN

Level-1-260C-UNLIM-40 to 125

1SJ6

Samples

TPS74617PQWDRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

74617P

Samples

TPS74618PQWDRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

74618P

Samples

TPS74618PQWDRVRQ1

ACTIVE

WSON

DRV

6

3000

RoHS & GreenSN

Level-1-260C-UNLIM-40 to 125

1SK6

Samples

Addendum-Page 1

PACKAGE OPTION ADDENDUM
www.ti.com

Orderable Device

23-Jun-2023

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking(3)

Samples

(4/5)

(6)

TPS74625PQWDRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

74625P

Samples

TPS74625PQWDRVRQ1

ACTIVE

WSON

DRV

6

3000

RoHS & GreenSN

Level-1-260C-UNLIM-40 to 125

1SL6

Samples

TPS74628PQWDRBRQ1

PREVIEW

SON

DRB

8

3000

TBD

Call TI

Call TI-40 to 125

TPS74628PQWDRVRQ1

ACTIVE

WSON

DRV

6

3000

RoHS & GreenSN

Level-1-260C-UNLIM-40 to 125

1SM6

Samples

TPS74629PQWDRBRQ1

PREVIEW

SON

DRB

8

3000

TBD

Call TI

Call TI-40 to 125

TPS74629PQWDRVRQ1

ACTIVE

WSON

DRV

6

3000

RoHS & GreenSN

Level-1-260C-UNLIM-40 to 125

1SN6

Samples

TPS74630PQWDRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

74630P

Samples

TPS74633PCQWDRVRQ1

ACTIVE

WSON

DRV

6

3000

RoHS & Green

Call TI

Level-1-260C-UNLIM-40 to 125

1P16

Samples

TPS74633PQWDRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

74633P

Samples

TPS74633PQWDRVRQ1

ACTIVE

WSON

DRV

6

3000

RoHS & GreenSN

Level-1-260C-UNLIM-40 to 125

1OX6

Samples

TPS74634PQWDRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

74634P

Samples

TPS74650PQWDRBRQ1

ACTIVE

SON

DRB

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

74650P

Samples(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 2

PACKAGE OPTION ADDENDUM
www.ti.com

23-Jun-2023(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS746-Q1 :• Catalog : TPS746
NOTE: Qualified Version Definitions:• Catalog - TI's standard catalog product

Addendum-Page 3

PACKAGE MATERIALS INFORMATION
www.ti.com

23-Jun-2023

TAPE AND REEL INFORMATIONREEL DIMENSIONSTAPE DIMENSIONS
K0

P1

B0 W
Reel
DiameterCavity
A0
B0
K0
W
P1

A0

Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers

Reel Width (W1)QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes

Q1

Q2

Q1

Q2

Q3

Q4

Q3

Q4

User Direction of Feed

Pocket Quadrants*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)TPS74601PBQWDRVRQ1 WSON

DRV

6

3000

180.0

TPS74601PCQWDRVRQ1 WSON

DRV

6

3000

TPS74601PQWDRBRQ1

SON

DRB

8

3000

TPS74601PQWDRVRQ1

WSON

DRV

6

3000

TPS74610PQWDRBRQ1

SON

DRB

8

3000

TPS74610PQWDRVRQ1

WSON

DRV

6

TPS746115PQWDRBRQ1

SON

DRB

TPS74611PQWDRBRQ1

SON

DRB

TPS74611PQWDRVRQ1

WSON

TPS746125PQWDRBRQ1
TPS74612PQWDRBRQ1

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant
8.0

Q2

8.4

2.2

2.2

1.2

4.0

180.0

8.4

2.2

2.2

1.2

4.0

8.0

Q2

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

180.0

8.4

2.2

2.2

1.2

4.0

8.0

Q2

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

3000

180.0

8.4

2.2

2.2

1.2

4.0

8.0

Q2

8

3000

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

8

3000

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

DRV

6

3000

180.0

8.4

2.2

2.2

1.2

4.0

8.0

Q2

SON

DRB

8

3000

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

SON

DRB

8

3000

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

TPS74612PQWDRVRQ1

WSON

DRV

6

3000

180.0

8.4

2.2

2.2

1.2

4.0

8.0

Q2

TPS746135PQWDRBRQ1

SON

DRB

8

3000

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

TPS74613PQWDRBRQ1

SON

DRB

8

3000

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

TPS74615PQWDRBRQ1

SON

DRB

8

3000

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

TPS74615PQWDRVRQ1

WSON

DRV

6

3000

180.0

8.4

2.2

2.2

1.2

4.0

8.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

23-Jun-2023

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

TPS74617PQWDRBRQ1

SON

DRB

8

3000

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

TPS74618PQWDRBRQ1

SON

DRB

8

3000

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

TPS74618PQWDRVRQ1

WSON

DRV

6

3000

180.0

8.4

2.2

2.2

1.2

4.0

8.0

Q2

TPS74625PQWDRBRQ1

SON

DRB

8

3000

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

TPS74625PQWDRVRQ1

WSON

DRV

6

3000

180.0

8.4

2.2

2.2

1.2

4.0

8.0

Q2

TPS74628PQWDRVRQ1

WSON

DRV

6

3000

180.0

8.4

2.2

2.2

1.2

4.0

8.0

Q2

TPS74629PQWDRVRQ1

WSON

DRV

6

3000

180.0

8.4

2.2

2.2

1.2

4.0

8.0

Q2

TPS74630PQWDRBRQ1

SON

DRB

8

3000

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

TPS74633PCQWDRVRQ1 WSON

DRV

6

3000

180.0

8.4

2.2

2.2

1.2

4.0

8.0

Q2

TPS74633PQWDRBRQ1

SON

DRB

8

3000

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

TPS74633PQWDRVRQ1

WSON

DRV

6

3000

180.0

8.4

2.2

2.2

1.2

4.0

8.0

Q2

TPS74634PQWDRBRQ1

SON

DRB

8

3000

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

TPS74650PQWDRBRQ1

SON

DRB

8

3000

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

23-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

W

L

H

*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)TPS74601PBQWDRVRQ1

WSON

DRV

6

3000

200.0

183.0

25.0

TPS74601PCQWDRVRQ1

WSON

DRV

6

3000

200.0

183.0

25.0

TPS74601PQWDRBRQ1

SON

DRB

8

3000

367.0

367.0

35.0

TPS74601PQWDRVRQ1

WSON

DRV

6

3000

200.0

183.0

25.0

TPS74610PQWDRBRQ1

SON

DRB

8

3000

367.0

367.0

35.0

TPS74610PQWDRVRQ1

WSON

DRV

6

3000

200.0

183.0

25.0

TPS746115PQWDRBRQ1

SON

DRB

8

3000

367.0

367.0

35.0

TPS74611PQWDRBRQ1

SON

DRB

8

3000

367.0

367.0

35.0

TPS74611PQWDRVRQ1

WSON

DRV

6

3000

200.0

183.0

25.0

TPS746125PQWDRBRQ1

SON

DRB

8

3000

367.0

367.0

35.0

TPS74612PQWDRBRQ1

SON

DRB

8

3000

367.0

367.0

35.0

TPS74612PQWDRVRQ1

WSON

DRV

6

3000

200.0

183.0

25.0

TPS746135PQWDRBRQ1

SON

DRB

8

3000

367.0

367.0

35.0

TPS74613PQWDRBRQ1

SON

DRB

8

3000

367.0

367.0

35.0

TPS74615PQWDRBRQ1

SON

DRB

8

3000

367.0

367.0

35.0

TPS74615PQWDRVRQ1

WSON

DRV

6

3000

200.0

183.0

25.0

TPS74617PQWDRBRQ1

SON

DRB

8

3000

367.0

367.0

35.0

TPS74618PQWDRBRQ1

SON

DRB

8

3000

367.0

367.0

35.0

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION
www.ti.com

23-Jun-2023

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)TPS74618PQWDRVRQ1

WSON

DRV

6

3000

200.0

183.0

25.0

TPS74625PQWDRBRQ1

SON

DRB

8

3000

367.0

367.0

35.0

TPS74625PQWDRVRQ1

WSON

DRV

6

3000

200.0

183.0

25.0

TPS74628PQWDRVRQ1

WSON

DRV

6

3000

200.0

183.0

25.0

TPS74629PQWDRVRQ1

WSON

DRV

6

3000

200.0

183.0

25.0

TPS74630PQWDRBRQ1

SON

DRB

8

3000

367.0

367.0

35.0

TPS74633PCQWDRVRQ1

WSON

DRV

6

3000

200.0

183.0

25.0

TPS74633PQWDRBRQ1

SON

DRB

8

3000

367.0

367.0

35.0

TPS74633PQWDRVRQ1

WSON

DRV

6

3000

200.0

183.0

25.0

TPS74634PQWDRBRQ1

SON

DRB

8

3000

367.0

367.0

35.0

TPS74650PQWDRBRQ1

SON

DRB

8

3000

367.0

367.0

35.0

Pack Materials-Page 4

GENERIC PACKAGE VIEW

DRV 6

WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F

PACKAGE OUTLINE

DRV0006C

WSON - 0.8 mm max height
SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1
1.9

B

A

PIN 1 INDEX AREA
2.1
1.9
0.1 MIN(0.05)SECTION A-A
A-A 40.000

TYPICAL

0.8 MAXCSEATING PLANE
0.08 C(0.2) TYP
0.05
0.00

0.9 0.1

EXPOSEDTHERMAL PAD
3

4
2X
1.3

7

A

A
1.6 0.1

6

1
4X 0.65
PIN 1 ID
(OPTIONAL)

6X

6X

0.35
0.25

0.35
0.25
0.1
0.05

C A B
C
4223939/A 09/2017

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

DRV0006C

WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

6X (0.5)(0.9)
1
6

6X (0.3)

(1.6)

SYMM

7

(1.1)

4X (0.65)
4

3
SYMM

(R0.05) TYP( 0.2) TYP
VIA

(1.9)

LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:25X

0.07 MIN
ALL AROUND

0.07 MAXALL AROUNDEXPOSEDMETALEXPOSEDMETALSOLDER MASKOPENINGMETALMETAL UNDERSOLDER MASKNON SOLDER MASKDEFINED(PREFERRED)SOLDER MASKOPENINGSOLDER MASKDEFINEDSOLDER MASK DETAILS

4223939/A 09/2017
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shownon this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DRV0006C

WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

6X (0.5)

SYMM

METAL

1
6

6X (0.3)(0.45)SYMM
7
4X (0.65)
(0.7)
4

3
(R0.05) TYP
(0.9)
(1.9)

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCILEXPOSED PAD #7:
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGESCALE:30X

4223939/A 09/2017

NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com

PACKAGE OUTLINE
VSON - 1 mm max height

DRB0008J

PLASTIC QUAD FLAT PACK- NO LEAD

3.1
2.9

B

A

PIN 1 INDEX AREA

3.1
2.9
0.1 MIN(0.13)SECTION A-A
TYPICAL

1 MAX

C
SEATING PLANE

0.05
0.00

0.08 C
1.75
1.55(0.2) TYP

6X 0.65(0.19)
5

4

SYMM

9

2.5
2.3

1
PIN 1 ID
(OPTIONAL)

8SYMM
8X 0.50.3

1.95

8X 0.36
0.26
0.1
0.05

C A B
C

4225036/A 06/2019

NOTES:
1.
2.
3.

All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT
VSON - 1 mm max height

DRB0008J

PLASTIC QUAD FLAT PACK- NO LEAD

(2.8)
(1.65)
8X (0.6)
8X (0.31)

SYMM
1

8

6X (0.65)
SYMM

9(1.95) (2.4)(0.95)(R0.05) TYP
45(Ø 0.2) VIA
TYP(0.575)LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 20X

0.07 MAXALL AROUNDMETALEXPOSED METAL

0.07 MIN
ALL AROUNDEXPOSED METALSOLDER MASKOPENINGNON- SOLDER MASKDEFINED(PREFERRED)SOLDER MASKOPENINGMETALSOLDER MASKDEFINEDSOLDER MASK DETAILS

4225036/A 06/2019

NOTES: (continued)
4.
5.

This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shownon this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGNVSON - 1 mm max height

DRB0008J

PLASTIC QUAD FLAT PACK- NO LEAD

(2.8)
2X
(1.51)

8X (0.6)
8X (0.31)

SYMM
1

8
2X
(1.06)

6X (0.65)
SYMM

9(R0.05) TYP
4(0.63)(1.95)

5

METAL
TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCILEXPOSED PAD
81% PRINTED COVERAGE BY AREASCALE: 20X

4225036/A 06/2019

NOTES: (continued)
6.

Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCEDESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicablestandards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction withsuch TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
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