参考資料
MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630
JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

MSP430F563x ミクスト・シグナル・マイクロコントローラ
1 特長
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低い電源電圧範囲：1.8V～3.6V
超低消費電力– アクティブ・モード (AM)：すべてのシステム・クロックがアクティブ：
270µA/MHz (8MHz、3.0V)、フラッシュ・プログラム
実行時 (標準値)– スタンバイ・モード(LPM3)：
ウォッチドッグ (水晶振動子を使用)、電源スーパー
バイザが動作、すべての RAM を保持、高速ウェー
クアップ：
1.8µA (2.2V)、2.1µA (3.0V) (標準値)– シャットダウン・リアルタイム・クロック（ RTC ）モード
(LPM3.5) ：シャットダウン・モード、RTC (水晶振動子を使用)が動作：
1.1µA (3.0V) (標準値)– シャットダウン・モード (LPM4.5)：
0.3µA (3.0V) (標準値)
スタンバイ・モードから 3µs (標準値) でウェークアップ
16 ビット RISC アーキテクチャ、拡張メモリ、最大20MHz のシステム・クロック
柔軟な電力管理システム– プログラム可能な、レギュレートされたコア電源電圧を持つ、完全に統合された LDO– 電源電圧の管理、監視、およびブラウンアウト
統合クロック・システム– FLL 制御ループによる周波数安定化– 低電力、低周波数の内部クロック・ソース (VLO)– 調整済みの低周波数内部基準源 (REFO)– 32kHz の水晶振動子 (XT1)– 最高 32MHz の高周波数水晶振動子( XT2)
4 個の 16 ビット・タイマと 3、5、または 7 個のキャプチ
ャ/ 比較レジスタ2 つのユニバーサル・シリアル通信インターフェイス(USCI)

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– USCI_A0、USCI_A1 がそれぞれ次の機能をサポート：• 自動ボーレート検出機能付きの拡張 UART
• IrDA エンコーダおよびデコーダ• 同期 SPI– USCI_B0、USCI_B1 がそれぞれ次の機能をサポ
ート：
• I2C
• 同期 SPI
フルスピード・ユニバーサル・シリアル・バス(USB)– USB-PHY 内蔵– 3.3V/1.8V USB 電源システム内蔵– USB-PLL 内蔵– 8 入力 / 8 出力のエンドポイント
共有基準電圧、サンプル・アンド・ホールド、自動スキャン機能を内蔵した 12 ビット A/D コンバータ(ADC)
同期機能付きの 2 つの 12 ビット D/A コンバータ(DAC)
電圧コンパレータ
ハードウェア乗算器で 32 ビットの演算をサポート
シリアルのオンボード・プログラミング、外部のプログラミ
ング電圧不要6 チャネルの内蔵 DMA
電源電圧バックアップ・スイッチ付きの RTC モジュール
「デバイスの比較」に、提供しているファミリ製品をまとめています。

2 アプリケーション
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アナログおよびデジタル・センサ・システム
デジタル・モーター制御
リモート・コントロール
サーモスタット
デジタル・タイマ
ハンドヘルド・メータ

3 概要
TI MSP 430™ ファミリの超低消費電力マイクロコントローラは複数のデバイスで構成され、それぞれが各種のアプリケー
ションを対象とする異なるペリフェラルを搭載しています。このアーキテクチャは 5 つの低消費電力モードを持ち、携帯用測定器用途でバッテリ駆動時間を延長するよう最適化されています。このデバイスには、強力な 16 ビット RISC CPU、16
ビット・レジスタ、および定数ジェネレータが搭載されており、コード効率が最大限に発揮されます。デジタル制御発振器(DCO) により、低消費電力モードからアクティブ・モードへ 3µs (標準値) でウェークアップできます。
MSP430F563x は、高性能 12 ビット ADC、コンパレータ、2 つの USCI、USB 2.0、ハードウェア乗算器、DMA、4 つの
16 ビット・タイマ、アラーム機能付き RTC モジュール、最大 74 本の I/O ピンを搭載したマイクロコントローラです。
モジュールの完全な説明については、『MSP430F5xx および MSP430F6xx ファミリ・ユーザー・ガイド』を参照してください。
英語版の TI 製品についての情報を翻訳したこの資料は、製品の概要を確認する目的で便宜的に提供しているものです。該当する正式な英語版の最新情報は、
www.ti.com で閲覧でき、その内容が常に優先されます。TI では翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、必ず最新版の英語版をご参照くださいますようお願いいたします。

English Data Sheet: SLAS650

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.tij.co.jp

JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

製品情報
部品番号(1)パッケージ

本体サイズ(2)LQFP (100)14mm × 14mm

MSP430F5638IZCAnFBGA (113)7mm × 7mm

MSP430F5638IZQW(3)MicroStar Junior™ BGA (113)7mm × 7mm

MSP430F5638IPZ

(1)
(2)
(3)

2

最新のデバイス、パッケージ、および注文情報については、セクション 11 の「付録：パッケージ・オプション」
または、www.tij.co.jp の TI Web サイトを参照してください。
ここに記載されているサイズは概略です。許容公差を含めたパッケージの寸法については、セクション 11の「メカニカル・データ」を参照してください。
ZQW (MicroStar Junior BGA) パッケージのすべての注文可能な部品番号が「最終購入」のステータスに変更されました。このステータスの詳細については、製品ライフサイクルのページを参照してください。

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Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634
MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.tij.co.jp

JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

4 機能ブロック図
図 4-1 に MSP430F5638、MSP430F5637、MSP430F5636 の機能ブロック図を示します。
XIN XOUT

DVCC

DVSS

AVCC

AVSS

RST/NMI
P1.x

XT2IN
XT2OUT

Unified
Clock
System

16KB
RAM

ACLK
SMCLK

256KB
192KB
128KB

Power
Management+2KB RAMUSB Buffer

LDO,
SVM, SVS,
Brownout

Flash

MCLK

SYS
Watchdog+8B Backup
RAM

P2 Port
Mapping
Controller

PA
P2.x

I/O Ports
P1, P2
2×8 I/OsInterrupt
Capability
PA
1×16 I/Os

P3.x

PB
P4.x

I/O Ports
P3, P42×8 I/OsInterrupt
Capability
PB
1×16 I/Os

P5.x

PC
P6.x

P7.x

I/O Ports
P5, P62×8 I/OsPD
P8.x

I/O Ports
P7, P81×6 I/Os
1×8 I/Os

PC
1×16 I/Os

PD
1×14 I/Os

P9.x

I/O Ports
P9
1×8 I/Os

USCI0,
USCI1

USB
Full-speed

Ax: UART,
IrDA, SPIPE
1×8 I/Os

Bx: SPI, I2C

CPUXV2andWorking
Registers

EEM(L: 8+2)TA1 and
TA2

TA0
JTAG,
SBW
Interface

MPY32

Timer_A
5 CC
Registers

Port PJ

2 Timer_A
each with
3 CC
Registers

ADC12_A

DMA

RTC_B
TB0
Timer_B
7 CC
Registers

CRC16

12 bit200 ksps

Comp_B

Battery
BackupSystem16 channels(12 ext, 4 int)
Autoscan

DAC12_AREF

12 bit2 channels
voltage out

Reference
1.5 V, 2.0 V,
2.5 V

6 Channel

PJ.x

図 4-1. 機能ブロック図 – MSP430F5638、MSP430F5637、MSP430F5636
図 4-2 に MSP430F5635、MSP430F5634、MSP430F5633 の機能ブロック図を示します。
XIN XOUT

DVCC

DVSS

AVCC

AVSS

RST/NMI
P1.x

XT2IN
XT2OUT

Unified
Clock
System

MCLK

ACLK
SMCLK

256KB
192KB
128KB
Flash

16KB
RAM

Power
Management

SYS
Watchdog+2KB RAMUSB Buffer+8B Backup
RAM

LDO,
SVM, SVS,
Brownout

P2 Port
Mapping
Controller

PA
P2.x

I/O Ports
P1, P2
2×8 I/OsInterrupt
Capability
PA
1×16 I/Os

P3.x

PB
P4.x

I/O Ports
P3, P42×8 I/OsInterrupt
Capability
PB
1×16 I/Os

P5.x

PC
P6.x

P7.x

I/O Ports
P5, P62×8 I/Os

PC
1×16 I/Os

PD
P8.x

I/O Ports
P7, P81×6 I/Os
1×8 I/Os
PD
1×14 I/Os

P9.x

I/O Ports
P9
1×8 I/Os

USCI0,
USCI1

USB
Full-speed

Ax: UART,
IrDA, SPIPE
1×8 I/Os

Bx: SPI, I2C

CPUXV2andWorking
Registers

EEM(L: 8+2)
TA0
JTAG,
SBW
Interface

MPY32

Timer_A
5 CC
Registers

Port PJ

TA1 andTA2
2 Timer_A
each with
3 CC
Registers

ADC12_A
RTC_B
TB0
Timer_B
7 CC
Registers

CRC16
Battery
BackupSystemComp_B

12 bit200 ksps
16 channels(12 ext, 4 int)
AutoscanDMA
REF

6 Channel

Reference
1.5 V, 2.0 V,
2.5 V

PJ.x

図 4-2. 機能ブロック図 – MSP430F5635、MSP430F5634、MSP430F5633

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3

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.tij.co.jp

JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

図 4-3 に MSP430F5632、MSP430F5631、MSP430F5630 の機能ブロック図を示します。
XIN XOUT

DVCC

DVSS

AVCC

AVSS

RST/NMI
P1.x

XT2IN
XT2OUT

Unified
Clock
System

MCLK

ACLK
SMCLK

256KB
192KB
128KB
Flash

16KB
RAM

Power
Management

SYS
Watchdog+2KB RAMUSB Buffer

LDO,
SVM, SVS,
Brownout+8B Backup
RAM

P2 Port
Mapping
Controller

PA
P2.x

P3.x

PB
P4.x

P5.x

PC
P6.x

I/O Ports
P1, P2
2×8 I/OsInterrupt
Capability

I/O Ports
P3, P42×8 I/OsInterrupt
Capability

I/O Ports
P5, P62×8 I/Os

PA
1×16 I/Os

PB
1×16 I/Os

PC
1×16 I/Os

P7.x

PD
P8.x

I/O Ports
P7, P81×6 I/Os
1×8 I/Os
PD
1×14 I/Os

P9.x

I/O Ports
P9
1×8 I/Os

USCI0,
USCI1

USB
Full-speed

Ax: UART,
IrDA, SPIPE
1×8 I/Os

Bx: SPI, I2C

CPUXV2andWorking
Registers

EEM(L: 8+2)
TA0
JTAG,
SBW
Interface

MPY32

Port PJ

Timer_A
5 CC
Registers

TA1 andTA2
2 Timer_A
each with
3 CC
Registers

DMA

RTC_B
REF

TB0
Timer_B
7 CC
Registers

CRC16
Battery
BackupSystemComp_B

6 Channel

Reference
1.5 V, 2.0 V,
2.5 V

PJ.x

図 4-3. 機能ブロック図 – MSP430F5632、MSP430F5631、MSP430F5630

4

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

Table of Contents
1 特長................................................................................... 1
2 アプリケーション...................................................................1
3 概要................................................................................... 1
4 機能ブロック図.................................................................... 3
5 Revision History.............................................................. 6
6 Device Comparison......................................................... 8
6.1 Related Products........................................................ 8
7 Terminal Configuration and Functions..........................9
7.1 Pin Diagrams.............................................................. 9
7.2 Signal Descriptions................................................... 13
8 Specifications................................................................ 18
8.1 Absolute Maximum Ratings...................................... 18
8.2 ESD Ratings............................................................. 18
8.3 Recommended Operating Conditions.......................18
8.4 Active Mode Supply Current Into VCC Excluding
External Current.......................................................... 20
8.5 Low-Power Mode Supply Currents (Into VCC)
Excluding External Current..........................................20
8.6 Thermal Resistance Characteristics......................... 21
8.7 Schmitt-Trigger Inputs – General-Purpose I/O..........22
8.8 Inputs – Ports P1, P2, P3, and P4............................ 22
8.9 Leakage Current – General-Purpose I/O.................. 228.10 Outputs – General-Purpose I/O (Full Drive
Strength)......................................................................22
8.11 Outputs – General-Purpose I/O (Reduced Drive
Strength)......................................................................23
8.12 Output Frequency – Ports P1, P2, and P3..............23
8.13 Typical Characteristics – Outputs, Reduced
Drive Strength (PxDS.y = 0)........................................ 24
8.14 Typical Characteristics – Outputs, Full Drive
Strength (PxDS.y = 1)................................................. 25
8.15 Crystal Oscillator, XT1, Low-Frequency Mode........26
8.16 Crystal Oscillator, XT2............................................ 27
8.17 Internal Very-Low-Power Low-Frequency
Oscillator (VLO)...........................................................28
8.18 Internal Reference, Low-Frequency Oscillator(REFO)........................................................................ 28
8.19 DCO Frequency...................................................... 29
8.20 PMM, Brownout Reset (BOR).................................30
8.21 PMM, Core Voltage.................................................30
8.22 PMM, SVS High Side..............................................31
8.23 PMM, SVM High Side............................................. 31
8.24 PMM, SVS Low Side...............................................32
8.25 PMM, SVM Low Side.............................................. 32
8.26 Wake-up Times From Low-Power Modes andReset........................................................................... 32
8.27 Timer_A, Timers TA0, TA1, and TA2.......................33
8.28 Timer_B, Timer TB0................................................33
8.29 Battery Backup........................................................34
8.30 USCI (UART Mode)................................................ 35
8.31 USCI (SPI Master Mode)........................................ 35
8.32 USCI (SPI Slave Mode).......................................... 37
8.33 USCI (I2C Mode)..................................................... 39
8.34 12-Bit ADC, Power Supply and Input Range
Conditions................................................................... 40

Copyright © 2021 Texas Instruments Incorporated

8.35 12-Bit ADC, Timing Parameters..............................40
8.36 12-Bit ADC, Linearity Parameters Using anExternal Reference Voltage.........................................41
8.37 12-Bit ADC, Linearity Parameters Using AVCC
as Reference Voltage.................................................. 41
8.38 12-Bit ADC, Linearity Parameters Using theInternal Reference Voltage..........................................41
8.39 12-Bit ADC, Temperature Sensor and Built-In
VMID ............................................................................ 42
8.40 REF, External Reference........................................ 43
8.41 REF, Built-In Reference.......................................... 44
8.42 12-Bit DAC, Supply Specifications..........................45
8.43 12-Bit DAC, Linearity Specifications....................... 46
8.44 12-Bit DAC, Output Specifications.......................... 47
8.45 12-Bit DAC, Reference Input Specifications........... 48
8.46 12-Bit DAC, Dynamic Specifications.......................48
8.47 12-Bit DAC, Dynamic Specifications (Continued)... 49
8.48 Comparator_B.........................................................50
8.49 Ports PU.0 and PU.1...............................................51
8.50 USB Output Ports DP and DM................................51
8.51 USB Input Ports DP and DM...................................51
8.52 USB-PWR (USB Power System)............................ 52
8.53 USB-PLL (USB Phase-Locked Loop)..................... 52
8.54 Flash Memory......................................................... 53
8.55 JTAG and Spy-Bi-Wire Interface.............................53
9 Detailed Description......................................................54
9.1 Overview................................................................... 54
9.2 CPU.......................................................................... 54
9.3 Instruction Set........................................................... 55
9.4 Operating Modes...................................................... 56
9.5 Interrupt Vector Addresses....................................... 57
9.6 Memory..................................................................... 58
9.7 Bootloader (BSL)...................................................... 59
9.8 JTAG Operation........................................................ 59
9.9 Flash Memory .......................................................... 60
9.10 RAM ....................................................................... 60
9.11 Backup RAM........................................................... 60
9.12 Peripherals..............................................................61
9.13 Input/Output Diagrams............................................83
9.14 Device Descriptors................................................104
10 Device and Documentation Support........................105
10.1 Getting Started and Next Steps............................ 105
10.2 Device Nomenclature............................................10510.3 Tools and Software............................................... 107
10.4 Documentation Support........................................ 109
10.5 Related Links.........................................................111
10.6 サポート・リソース.....................................................111
10.7 Trademarks........................................................... 111
10.8 静電気放電に関する注意事項.................................111
10.9 Export Control Notice............................................ 111
10.10 用語集..................................................................111
11 Mechanical, Packaging, and Orderable
Information.................................................................. 112

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5

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.tij.co.jp

JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

5 Revision History
資料番号末尾の英字は改訂を表しています。その改訂履歴は英語版に準じています。
Changes from revision F to revision G
Changes from September 18, 2018 to September 10, 2020
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Page

文書全体にわたってセクション、表、図、相互参照の採番方法を更新......................................................................1
文書全体にわたって nFBGA パッケージ (ZCA) の情報を追加...............................................................................1
Removed package options that are no longer available in 表 6-1, Device Comparison (MSP430F5637 and
MSP430F5631 in ZQW) .................................................................................................................................... 8
Updated the list of devices available in the 113-Pin ZQW package in the caption of 図 7-4 ............................. 9
Changed the MAX value of the IERASE and IMERASE, IBANK parameters in セクション 8.54, Flash Memory .......53
Corrected the connection of the P7SEL.x signal in 図 9-11, Port P7 (P7.4 to P7.7) Diagram ......................... 97

Changes from revision E to revision F
Changes from December 9, 2015 to September 17, 2018
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Page

Added セクション 6.1, Related Products ............................................................................................................. 8
Added typical conditions statements at the beginning of セクション 8, Specifications ...................................... 18
Changed the MIN value of the V(DVCC_BOR_hys) parameter from 60 mV to 50 mV in セクション 8.20, PMM,
Brownout Reset (BOR) .................................................................................................................................... 30
Updated notes (1) and (2) and added note (3) in セクション 8.26, Wake-up Times From Low-Power Modes andReset ............................................................................................................................................................... 32
Removed ADC12DIV from the formula for the TYP value in the second row of the tCONVERT parameter in セク
ション 8.35, 12-Bit ADC, Timing Parameters, because ADC12CLK is after division......................................... 40
Removed the note that started "This impedance depends on..." from the "Reference input resistance"parameter in セクション 8.45, 12-Bit DAC, Reference Input Specifications ...................................................... 48
Added second row for tEN_CMP with Test Conditions of "CBPWRMD = 10" and MAX value of 100 µs in セクショ
ン 8.48, Comparator_B .................................................................................................................................... 50
Renamed FCTL4.MGR0 and MGR1 in the fMCLK,MGR parameter in セクション 8.54, Flash Memory to beconsistent with header files ..............................................................................................................................53
Replaced former section Development Tools Support with セクション 10.3, Tools and Software ................... 107

Changes from revision D to revision E
Changes from August 6, 2013 to December 8, 2015
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Page

全体を通してドキュメントのフォーマットと編成を変更、セクションの番号追加も含む.................................................. 1
すべての機能ブロック図をセクション 4「機能ブロック図」に移動 ............................................................................. 3
Added USB column to 表 6-1, Family Members ................................................................................................ 8
Added セクション 6, Device Comparison, and moved 表 6-1 to it........................................................................ 8
Added "Port U is supplied by the LDOO rail" to the PU.0 and PU.1 descriptions in セクション 7.2, Signal
Descriptions ..................................................................................................................................................... 13
Added セクション 8.2, ESD Ratings .................................................................................................................. 18
Added note to CVCORE ..................................................................................................................................... 18
Added note to RPull .......................................................................................................................................... 22
Changed TYP value of CL,eff with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF.......................26
In VBAT3 parameter description, changed from "VBAT3 ≠ VBAT/3" to "VBAT3 = VBAT/3"....................................... 34
Changed from fDAC12_0OUT to fDAC12_1OUT in the first row of the Test Conditions for the "Channel-to-channel
crosstalk" parameter......................................................................................................................................... 49
Changed the value of DAC12_xDAT from 7F7h to F7Fh and changed the x-axis label from fToggle to 1/fToggle in
図 8-22, Crosstalk Test Conditions .................................................................................................................. 49
Added note to RPUR ......................................................................................................................................... 52
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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.tij.co.jp

•
•
•
•
•
•
•
•
•
•
•

JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

Corrected the spelling of the MRG bits in the fMCLK,MRG parameter in セクション 8.54, Flash Memory ............ 53
Removed RTC_B from LPM4.5 wake-up options.............................................................................................56
Throughout document, changed all instances of "bootstrap loader" to "bootloader" ....................................... 59
Added the paragraph that starts "Using the MSP430 RTC_B Module With Battery Backup Supply describes
how..." .............................................................................................................................................................. 63
Corrected names of interrupt events PMMSWBOR (BOR) and PMMSWPOR (POR) in 表 9-11, System
Module Interrupt Vector Registers ................................................................................................................... 64
Corrected spelling of NMIIFG (added missing "I") in 表 9-11, System Module Interrupt Vector Registers ...... 64
Corrected register acronyms (added "USB" prefix as required) in 表 9-50, USB Control Registers ............... 71
Added P7SEL.2 and XT2BYPASS inputs with AND and OR gates in 図 9-10, Port P7 (P7.3) Diagram .........96
Changed P7SEL.3 column from X to 0 for "P7.3 (I/O)" rows............................................................................96
Added セクション 10 and moved Development Tools Support, Device and Development Tool Nomenclature,
Trademarks, and Electrostatic Discharge Caution sections to it.....................................................................105
Added セクション 11, Mechanical, Packaging, and Orderable Information ..................................................... 112

The following table lists the changes to this data sheet from the original release through revision D.
REVISIONCOMMENTS
Signal Descriptions, Added note regarding pullup resistor to RST/NMI/SBWTDIO pin.
Added Applications, Development Tools Support, and Device and Development Tool Nomenclature

SLAS650D
August 2013

セクション 9.12.1, Changed the description of the number of I/Os in each port.
表 9-19, Added PM5CTL0 register.
セクション 8.42, Fixed typo in IDD Test Conditions (changed from DAC12IOG to DAC12OG).
セクション 8.51, Corrected VIL and VIH limits.
セクション 8.54, Changed IERASE and IMERASE, IBANK limits.
Changed description of ACLK and PUR in Signal Descriptions.
Changed typos to Interrupt Flag names on Timer TA2 rows in 表 9-3.
Changed SYSRSTIV, System Reset offset 1Ch to Reserved in 表 9-11.
Corrected names of SVMLVLRIFG and SVMHVLRIFG bits in 表 9-11.

SLAS650C
August 2012

Corrected right-most column in 表 9-4.
Added note regarding evaluation of PUR in セクション 9.7.1.
Changed notes on セクション 8.41.
Changed tSENSOR(sample) MIN to 100 µs in セクション 8.39.
Changed note (2) in セクション 8.39.
Editorial changes throughout.

SLAS650B
August 2011

Production Data release

SLAS650A
July 2010

Updated Product Preview including electrical specifications

SLAS650
May 2010

Product Preview release

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7

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

6 Device Comparison
表 6-1 summarizes the available family members.
表 6-1. Device Comparison
USCI_A:
UART,
IrDA, SPIUSCI_B:
SPI, I2C

ADC12_A(Ch)

DAC12_A(Ch)

Comp_B
(Ch)

USB

I/O

PACKAGE

7

2

2

12 ext, 4 int

2

12

Yes

74

100 PZ,
113 ZCA,113 ZQW

5, 3, 372

2

12 ext, 4 int

2

12

Yes

74

100 PZ

16 + 25, 3, 372

2

12 ext, 4 int

2

12

Yes

74

100 PZ,
113 ZCA,113 ZQW

256

16 + 25, 3, 372

2

12 ext, 4 int

–

12

Yes

74

100 PZ,
113 ZCA,113 ZQWMSP430F5634

192

16 + 25, 3, 372

2

12 ext, 4 int

–

12

Yes

74

100 PZ,
113 ZCA,113 ZQWMSP430F5633

128

16 + 25, 3, 372

2

12 ext, 4 int

–

12

Yes

74

100 PZ,
113 ZCA,113 ZQWMSP430F5632

256

16 + 25, 3, 3

7

2

2

–

–

12

Yes

74

100 PZ,
113 ZCA,113 ZQWMSP430F5631

192

16 + 25, 3, 3

7

2

2

–

–

12

Yes

74

100 PZ

74

100 PZ,
113 ZCA,113 ZQWDEVICE(1) (2)

FLASH
(KB)

SRAM
(KB)(5)

MSP430F5638

256

16 + 25, 3, 3

MSP430F5637

192

16 + 2

MSP430F5636

128

MSP430F5635

MSP430F5630

(1)
(2)
(3)
(4)
(5)

128

Timer_A(3) Timer_B(4)16 + 25, 3, 3

7

2

2

–

–

12

Yes

For the most current package and ordering information, see the Package Option Addendum in セクション 11, or see the TI website at
www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/
packaging.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and
PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and
PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
The additional 2KB of USB SRAM that is listed can be used as general-purpose SRAM when USB is not in use.

6.1 Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers
High-performance, low-power solutions to enable the autonomous future
Products for MSP430 ultra-low-power sensing & measurement MCUs
One platform. One ecosystem. Endless possibilities.
Companion products for MSP430F5638
Review products that are frequently purchased or used in conjunction with this product.
Reference designs
Find reference designs leveraging the best in TI technology to solve your system-level challenges

8

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.tij.co.jp

JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

7 Terminal Configuration and Functions
7.1 Pin Diagrams

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

MSP430F5638
MSP430F5637
MSP430F5636

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

P9.7
P9.6
P9.5
P9.4
P9.3
P9.2
P9.1
P9.0
P8.7
P8.6/UCB1SOMI/UCB1SCL
P8.5/UCB1SIMO/UCB1SDA
DVCC2
DVSS2
P8.4/UCB1CLK/UCA1STE
P8.3/UCA1RXD/UCA1SOMI
P8.2/UCA1TXD/UCA1SIMO
P8.1/UCB1STE/UCA1CLK
P8.0/TB0CLK
P4.7/TB0OUTH/SVMOUT
P4.6/TB0.6
P4.5/TB0.5
P4.4/TB0.4
P4.3/TB0.3
P4.2/TB0.2
P4.1/TB0.1

DVSS1
VCORE
P5.2
DVSS
DNC
P5.3
P5.4
P5.5
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA0.1
P1.7/TA0.2
P3.0/TA1CLK/CBOUT
P3.1/TA1.0
P3.2/TA1.1
P3.3/TA1.2
P3.4/TA2CLK/SMCLK
P3.5/TA2.0
P3.6/TA2.1
P3.7/TA2.2
P4.0/TB0.0

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6/DAC0
P6.7/CB7/A7/DAC1
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14/DAC0
P7.7/CB11/A15/DAC1
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
AVSS1
XIN
XOUT
AVSS2
P5.6/ADC12CLK/DMAE0
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6
P2.7/P2MAP7
DVCC1

100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76

P6.3/CB3/A3
P6.2/CB2/A2
P6.1/CB1/A1
P6.0/CB0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
DVSS3
DVCC3
P5.7/RTCCLK
VBAT
VBAK
P7.3/XT2OUT
P7.2/XT2IN
AVSS3
V18
VUSB
VBUS
PU.1/DM
PUR
PU.0/DPVSSU

図 7-1 shows the pinout for the MSP430F5638, MSP430F5637, and MSP430F5636 devices in the 100-pin PZ
package.

NOTE: DNC = Do not connect

図 7-1. 100-Pin PZ Package (Top View) – MSP430F5638, MSP430F5637, MSP430F5636

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

9

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.tij.co.jp

JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

MSP430F5635
MSP430F5634
MSP430F5633

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

P9.7
P9.6
P9.5
P9.4
P9.3
P9.2
P9.1
P9.0
P8.7
P8.6/UCB1SOMI/UCB1SCL
P8.5/UCB1SIMO/UCB1SDA
DVCC2
DVSS2
P8.4/UCB1CLK/UCA1STE
P8.3/UCA1RXD/UCA1SOMI
P8.2/UCA1TXD/UCA1SIMO
P8.1/UCB1STE/UCA1CLK
P8.0/TB0CLK
P4.7/TB0OUTH/SVMOUT
P4.6/TB0.6
P4.5/TB0.5
P4.4/TB0.4
P4.3/TB0.3
P4.2/TB0.2
P4.1/TB0.1

DVSS1
VCORE
P5.2
DVSS
DNC
P5.3
P5.4
P5.5
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA0.1
P1.7/TA0.2
P3.0/TA1CLK/CBOUT
P3.1/TA1.0
P3.2/TA1.1
P3.3/TA1.2
P3.4/TA2CLK/SMCLK
P3.5/TA2.0
P3.6/TA2.1
P3.7/TA2.2
P4.0/TB0.0

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14
P7.7/CB11/A15
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
AVSS1
XIN
XOUT
AVSS2
P5.6/ADC12CLK/DMAE0
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6
P2.7/P2MAP7
DVCC1

100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76

P6.3/CB3/A3
P6.2/CB2/A2
P6.1/CB1/A1
P6.0/CB0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
DVSS3
DVCC3
P5.7/RTCCLK
VBAT
VBAK
P7.3/XT2OUT
P7.2/XT2IN
AVSS3
V18
VUSB
VBUS
PU.1/DM
PUR
PU.0/DPVSSU

図 7-2 shows the pinout for the MSP430F5635, MSP430F5634, and MSP430F5633 devices in the 100-pin PZ
package.

NOTE: DNC = Do not connect

図 7-2. 100-Pin PZ Package (Top View) – MSP430F5635, MSP430F5634, MSP430F5633

10

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.tij.co.jp

JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

MSP430F5632
MSP430F5631
MSP430F5630

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

P9.7
P9.6
P9.5
P9.4
P9.3
P9.2
P9.1
P9.0
P8.7
P8.6/UCB1SOMI/UCB1SCL
P8.5/UCB1SIMO/UCB1SDA
DVCC2
DVSS2
P8.4/UCB1CLK/UCA1STE
P8.3/UCA1RXD/UCA1SOMI
P8.2/UCA1TXD/UCA1SIMO
P8.1/UCB1STE/UCA1CLK
P8.0/TB0CLK
P4.7/TB0OUTH/SVMOUT
P4.6/TB0.6
P4.5/TB0.5
P4.4/TB0.4
P4.3/TB0.3
P4.2/TB0.2
P4.1/TB0.1

DVSS1
VCORE
P5.2
DVSS
DNC
P5.3
P5.4
P5.5
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA0.1
P1.7/TA0.2
P3.0/TA1CLK/CBOUT
P3.1/TA1.0
P3.2/TA1.1
P3.3/TA1.2
P3.4/TA2CLK/SMCLK
P3.5/TA2.0
P3.6/TA2.1
P3.7/TA2.2
P4.0/TB0.0

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

P6.4/CB4
P6.5/CB5
P6.6/CB6
P6.7/CB7P7.4/CB8P7.5/CB9P7.6/CB10
P7.7/CB11
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
AVSS1
XIN
XOUT
AVSS2
P5.6/DMAE0
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6
P2.7/P2MAP7
DVCC1

100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76

P6.3/CB3
P6.2/CB2
P6.1/CB1
P6.0/CB0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
DVSS3
DVCC3
P5.7/RTCCLK
VBAT
VBAK
P7.3/XT2OUT
P7.2/XT2IN
AVSS3
V18
VUSB
VBUS
PU.1/DM
PUR
PU.0/DP
VSSU

図 7-3 shows the pinout for the MSP430F5632, MSP430F5631, and MSP430F5630 devices in the 100-pin PZ
package.

NOTE: DNC = Do not connect

図 7-3. 100-Pin PZ Package (Top View) – MSP430F5632, MSP430F5631, MSP430F5630

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

11

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.tij.co.jp

JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

図 7-4 shows the pinout for all devices in the 113-pin ZCA or ZQW package. See 表 7-1 for pin assignments anddescriptions.
A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

C1

C2

C3

C11

C12

D1

D2

D4

D5

D6

D7

D8

D9

D11

D12

E1

E2

E4

E5

E6

E7

E8

E9

E11

E12

F1

F2

F4

F5

F8

F9

F11

F12

G1

G2

G4

G5

G8

G9

G11

G12

H1

H2

H4

H5

H6

H7

H8

H9

H11

H12

J1

J2

J4

J5

J6

J7

J8

J9

J11

J12

K1

K2

K11

K12

L1

L2

L3

L4

L5

L6

L7

L8

L9

L10

L11

L12

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

NOTE: For terminal assignments, see 表 7-1.

図 7-4. 113-Pin ZCA or ZQW Package (Top View) – MSP430F5638, MSP430F5636, MSP430F5635,
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5630

12

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Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634
MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.tij.co.jp

JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

7.2 Signal Descriptions
表 7-1 describes the signals for all device variants and packages.
表 7-1. Signal Descriptions
TERMINAL
NO.(4)NAME

I/O(1)DESCRIPTION

PZ

ZCA,
ZQW

P6.4/CB4/A4

1

A1

I/O

General-purpose digital I/O
Comparator_B input CB4
Analog input A4 – ADC (not available on F5632, F5631, and F5630 devices)

P6.5/CB5/A5

2

B2

I/O

General-purpose digital I/O
Comparator_B input CB5
Analog input A5 – ADC (not available on F5632, F5631, and F5630 devices)

I/O

General-purpose digital I/O
Comparator_B input CB6
Analog input A6 – ADC (not available on F5632, F5631, and F5630 devices)
DAC12.0 output (not available on F5635, F5634, F5633, F5632, F5631, and F5630
devices)P6.6/CB6/A6/DAC03

B1

P6.7/CB7/A7/DAC1

4

C2

I/O

General-purpose digital I/O
Comparator_B input CB7
Analog input A7 – ADC (not available on F5632, F5631, and F5630 devices)
DAC12.1 output (not available on F5635, F5634, F5633, F5632, F5631, and F5630
devices)P7.4/CB8/A12

5

C1

I/O

General-purpose digital I/O
Comparator_B input CB8
Analog input A12 –ADC (not available on F5632, F5631, and F5630 devices)

P7.5/CB9/A13

6

C3

I/O

General-purpose digital I/O
Comparator_B input CB9
Analog input A13 – ADC (not available on F5632, F5631, and F5630 devices)

I/O

General-purpose digital I/O
Comparator_B input CB10
Analog input A14 – ADC (not available on F5632, F5631, and F5630 devices)
DAC12.0 output (not available on F5635, F5634, F5633, F5632, F5631, and F5630
devices)P7.6/CB10/A14/DAC07

D2

P7.7/CB11/A15/DAC1

8

D1

I/O

General-purpose digital I/O
Comparator_B input CB11
Analog input A15 – ADC (not available on F5632, F5631, and F5630 devices)
DAC12.1 output (not available on F5635, F5634, F5633, F5632, F5631, and F5630
devices)P5.0/VREF+/VeREF+

9

D4

I/O

General-purpose digital I/O
Output of reference voltage to the ADC
Input for an external reference voltage to the ADC

P5.1/VREF-/VeREF-

10

E4

I/O

General-purpose digital I/O
Negative terminal for the reference voltage of the ADC for both sources, theinternal reference voltage, or an external applied reference voltage

AVCC1

11

E1,
E2

Analog power supply

AVSS1

12

F2

Analog ground supply

XIN

13

F1

I

Input terminal for crystal oscillator XT1

XOUT

14

G1

O

Output terminal of crystal oscillator XT1

AVSS2

15

G2

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Analog ground supply
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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

表 7-1. Signal Descriptions (continued)
TERMINAL
NO.(4)NAME

I/O(1)DESCRIPTION

PZ

ZCA,
ZQW

P5.6/ADC12CLK/DMAE0

16

H1

I/O

General-purpose digital I/O
Conversion clock output ADC (not available on F5632, F5631, and F5630 devices)
DMA external trigger input

P2.0/P2MAP0

17

G4

I/O

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output

P2.1/P2MAP1

18

H2

I/O

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data

P2.2/P2MAP2

19

J1

I/O

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock

P2.3/P2MAP3

20

H4

I/O

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable

P2.4/P2MAP4

21

J2

I/O

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out

P2.5/P2MAP5

22

K1

I/O

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master inP2.6/P2MAP6

23

K2

I/O

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: no secondary function

P2.7/P2MAP7

24

L2

I/O

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: no secondary function

DVCC1

25

L1

Digital power supply

DVSS1

26

M1

Digital ground supply

VCORE(2)27

M2Regulated core power supply (internal use only, no external current loading)

P5.2

28

L3

DVSS

29

M3

DNC

30

J4

P5.3

31

L4

I/O

General-purpose digital I/O

P5.4

32

M4

I/O

General-purpose digital I/O

P5.5

33

J5

I/O

General-purpose digital I/O

P1.0/TA0CLK/ACLK

34

L5

I/O

General-purpose digital I/O with port interrupt
Timer TA0 clock signal TACLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)

P1.1/TA0.0

35

M5

I/O

General-purpose digital I/O with port interrupt
Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output

P1.2/TA0.1

36

J6

I/O

General-purpose digital I/O with port interrupt
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input

P1.3/TA0.2

37

H6

I/O

General-purpose digital I/O with port interrupt
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output

P1.4/TA0.3

38

M6

I/O

General-purpose digital I/O with port interrupt
Timer TA0 CCR3 capture: CCI3A input compare: Out3 output

P1.5/TA0.4

39

L6

I/O

General-purpose digital I/O with port interrupt
Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output

P1.6/TA0.1

40

J7

I/O

General-purpose digital I/O with port interrupt
Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output

14

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I/O

General-purpose digital I/O
Digital ground supply
Do not connect. It is strongly recommended to leave this terminal open.

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表 7-1. Signal Descriptions (continued)
TERMINAL
NO.(4)NAME

I/O(1)DESCRIPTION

PZ

ZCA,
ZQW

P1.7/TA0.2

41

M7

I/O

General-purpose digital I/O with port interrupt
Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output

P3.0/TA1CLK/CBOUT

42

L7

I/O

General-purpose digital I/O with port interrupt
Timer TA1 clock input
Comparator_B output

P3.1/TA1.0

43

H7

I/O

General-purpose digital I/O with port interrupt
Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

P3.2/TA1.1

44

M8

I/O

General-purpose digital I/O with port interrupt
Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

P3.3/TA1.2

45

L8

I/O

General-purpose digital I/O with port interrupt
Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

P3.4/TA2CLK/SMCLK

46

J8

I/O

General-purpose digital I/O with port interrupt
Timer TA2 clock input
SMCLK output

P3.5/TA2.0

47

M9

I/O

General-purpose digital I/O with port interrupt
Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

P3.6/TA2.1

48

L9

I/O

General-purpose digital I/O with port interrupt
Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

P3.7/TA2.2

49

M10

I/O

General-purpose digital I/O with port interrupt
Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

P4.0/TB0.0

50

J9

I/O

General-purpose digital I/O with port interrupt
Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

P4.1/TB0.1

51

M11

I/O

General-purpose digital I/O with port interrupt
Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

P4.2/TB0.2

52

L10

I/O

General-purpose digital I/O with port interrupt
Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

P4.3/TB0.3

53

M12

I/O

General-purpose digital I/O with port interrupt
Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output

P4.4/TB0.4

54

L12

I/O

General-purpose digital I/O with port interrupt
Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output

P4.5/TB0.5

55

L11

I/O

General-purpose digital I/O with port interrupt
Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output

P4.6/TB0.6

56

K11

I/O

General-purpose digital I/O with port interrupt
Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output

P4.7/TB0OUTH/SVMOUT

57

K12

I/O

General-purpose digital I/O with port interrupt
Timer TB0: Switch all PWM outputs high impedance
SVM output

P8.0/TB0CLK

58

J11

I/O

General-purpose digital I/OTimer TB0 clock input

P8.1/UCB1STE/UCA1CLK

59

J12

I/O

General-purpose digital I/O
USCI_B1 SPI slave transmit enable; USCI_A1 clock input/output

P8.2/UCA1TXD/UCA1SIMO

60

H11

I/O

General-purpose digital I/O
USCI_A1 UART transmit data; USCI_A1 SPI slave in/master out

P8.3/UCA1RXD/UCA1SOMI

61

H12

I/O

General-purpose digital I/O
USCI_A1 UART receive data; USCI_A1 SPI slave out/master in

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表 7-1. Signal Descriptions (continued)
TERMINAL
NO.(4)NAME

I/O(1)DESCRIPTION

PZ

ZCA,
ZQW

P8.4/UCB1CLK/UCA1STE

62

G11

DVSS2

63

G12

Digital ground supply

DVCC2

64

F12

Digital power supply

P8.5/UCB1SIMO/UCB1SDA

65

F11

I/O

General-purpose digital I/O
USCI_B1 SPI slave in/master out; USCI_B1 I2C data

P8.6/UCB1SOMI/UCB1SCL

66

G9

I/O

General-purpose digital I/O
USCI_B1 SPI slave out/master in; USCI_B1 I2C clock

P8.7

67

E12

I/O

General-purpose digital I/O

P9.0

68

E11

I/O

General-purpose digital I/O

P9.1

69

F9

I/O

General-purpose digital I/O

P9.2

70

D12

I/O

General-purpose digital I/O

P9.3

71

D11

I/O

General-purpose digital I/O

P9.4

72

E9

I/O

General-purpose digital I/O

P9.5

73

C12

I/O

General-purpose digital I/O

P9.6

74

C11

I/O

General-purpose digital I/O

P9.7

75

D9

I/O

General-purpose digital I/O

VSSU

76

B11,
B12

PU.0/DP

77

A12

I/O

General-purpose digital I/O, controlled by USB control register. Port U is suppliedby the LDOO rail.
USB data terminal DP

PUR

78

B10

I/O

USB pullup resistor pin (open drain). The voltage level at the PUR pin is used to
invoke the default USB BSL. TI recommends a 1-MΩ resistor to ground. See セクシ
ョン 9.7.1 for more information.

PU.1/DM

79

A11

I/O

General-purpose digital I/O, controlled by USB control register. Port U is suppliedby the LDOO rail.
USB data terminal DM

VBUS

80

A10

USB LDO input (connect to USB power source)

VUSB

81

A9

USB LDO output

V18

82

B9

USB regulated power (internal use only, no external current loading)

AVSS3

83

A8

Analog ground supply

P7.2/XT2IN

84

B8

I/O

General-purpose digital I/O
Input terminal for crystal oscillator XT2

P7.3/XT2OUT

85

B7

I/O

General-purpose digital I/O
Output terminal of crystal oscillator XT2

VBAK

86

A7

Capacitor for backup subsystem. Do not load this pin externally. For capacitor
values, see CBAK in セクション 8.3.

VBAT

87

D8

Backup or secondary supply voltage. If backup voltage is not supplied, connect to
DVCC externally.

P5.7/RTCCLK

88

D7

DVCC3

89

A6

Digital power supply

DVSS3

90

A5

Digital ground supply

TEST/SBWTCK

91

B6

16

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I/O

General-purpose digital I/O
USCI_B1 clock input/output; USCI_A1 SPI slave transmit enable

USB PHY ground supply

I/O

I

General-purpose digital I/O
RTCCLK output

Test mode pin; selects digital I/O on JTAG pins
Spy-Bi-Wire input clock
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表 7-1. Signal Descriptions (continued)
TERMINAL
NO.(4)NAME

I/O(1)DESCRIPTION

PZ

ZCA,
ZQW

PJ.0/TDO

92

B5

I/O

General-purpose digital I/O
Test data output port

PJ.1/TDI/TCLK

93

A4

I/O

General-purpose digital I/O
Test data input or test clock input

PJ.2/TMS

94

E7

I/O

General-purpose digital I/O
Test mode selectPJ.3/TCK

95

D6

I/O

General-purpose digital I/O
Test clock

RST/NMI/SBWTDIO

96

A3

I/O

Reset input (active low)(3)Nonmaskable interrupt input
Spy-Bi-Wire data input/output

P6.0/CB0/A0

97

B4

I/O

General-purpose digital I/O
Comparator_B input CB0
Analog input A0 – ADC (not available on F5632, F5631, and F5630 devices)

P6.1/CB1/A1

98

B3

I/O

General-purpose digital I/O
Comparator_B input CB1
Analog input A1 – ADC (not available on F5632, F5631, and F5630 devices)

P6.2/CB2/A2

99

A2

I/O

General-purpose digital I/O
Comparator_B input CB2
Analog input A2 – ADC (not available on F5632, F5631, and F5630 devices)

P6.3/CB3/A3

100

D5

I/O

General-purpose digital I/O
Comparator_B input CB3
Analog input A3 – ADC (not available on F5632, F5631, and F5630 devices)

N/A

E5,
E6,
E8,
F4,
F5,
F8,
G5,
G8,
H5,
H8,
H9

Reserved

(1)
(2)
(3)
(4)

Reserved. TI recommends connecting to ground (DVSS, AVSS).

I = input, O = output, N/A = not available on this package offering
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
When this pin is configured as reset, the internal pullup resistor is enabled by default.
See the Package Option Addendum in セクション 11 to determine which devices are available in each package.

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8 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.

8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN

MAX

UNIT

Voltage applied at VCC to VSS

–0.3

4.1

V

Voltage applied to any pin (excluding VCORE, VBUS, V18)(2)–0.3

VCC + 0.3

V

Diode current at any device pin±2mA

Maximum junction temperature, TJ

95

°C

150

°C

Storage temperature, Tstg
(1)
(2)
(3)

(3)

–55

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.

8.2 ESD Ratings
VALUE
V(ESD)(1)(2)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±1000

Charged-device model (CDM), per JEDEC specification JESD22-C101(2)

±250

UNIT
V

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as±250 V may actually have higher performance.

8.3 Recommended Operating Conditions
MIN
Supply voltage during program execution and flash
programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 =DVCC = VCC)(1) (2)

VCC

Supply voltage during USB operation, USB PLL disabled(USB_EN = 1, UPLLEN = 0)
VCC,USBVSS
VBAT,RTC

Backup-supply voltage with RTC operational

VBAT,MEM

MAX

1.8

3.6

PMMCOREVx = 0, 1

2.0

3.6

PMMCOREVx = 0, 1, 2

2.2

3.6

PMMCOREVx = 0, 1, 2, 3

2.4

3.6

PMMCOREVx = 0

1.8

3.6

PMMCOREVx = 0, 1

2.0

3.6

PMMCOREVx = 0, 1, 2

2.2

3.6

PMMCOREVx = 0, 1, 2, 3

2.4

3.6

2.2

3.6

2.4

3.6

Supply voltage during USB operation, USB PLL enabled(6) PMMCOREVx = 2(USB_EN = 1, UPLLEN = 1)
PMMCOREVx = 2, 3
Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 =DVSS2 = DVSS3 = VSS)NOM

PMMCOREVx = 0

0

UNIT

V

V

V

TA = 0°C to 85°C

1.55

3.6

TA = –40°C to +85°C

1.70

3.6

Backup-supply voltage with backup memory retained

TA = –40°C to +85°C

1.20

3.6

V

TA

Operating free-air temperature

I version

–40

85

°C

TJ

Operating junction temperature

I version

–40

85

°C

CBAK

Capacitance at pin VBAK10nF

CVCORE

Capacitor at VCORE(4)18

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1

4.7
470

V

nF

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8.3 Recommended Operating Conditions (continued)
MIN
CDVCC/CVCOREfSYSTEMCapacitor ratio of DVCC to VCORE

Processor frequency (maximum MCLK frequency)(3) (5)(see 図 8-1)

Minimum processor frequency for USB operation

USB_wait

Wait state cycles during USB operation

(2)
(3)
(4)
(5)
(6)

MAX

UNIT

10

fSYSTEM_USB

(1)

NOM

PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V(default condition)0

8.0

PMMCOREVx = 1,
2 V ≤ VCC ≤ 3.6 V

0

12.0

PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V

0

16.0

PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V

0

20.0

1.5

MHz

MHz
16

cyclesTI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the threshold parameters in セクション
8.22 for the exact values and more details.
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of thespecified maximum frequency.
A capacitor tolerance of ±20% or better is required.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
USB operation with USB PLL enabled requires PMMCOREVx ≥ 2 for proper operation.

25

System Frequency - MHz

20
3
16
2

2, 3

1

1, 2

1, 2, 30, 1

0, 1, 20, 1, 2, 3

12

8
0

0
1.8

2.0

2.2

2.4

3.6

Supply Voltage - V
NOTE: The numbers within the fields denote the supported PMMCOREVx settings.

図 8-1. Frequency vs Supply Voltage

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8.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)(1) (2) (3)PARAMETER

IAM, FlashIAM, RAM

(1)
(2)
(3)

EXECUTIONMEMORYFlashRAM

FREQUENCY (fDCO = fMCLK = fSMCLK)
VCC

3V

3V

PMMCOREVx

1 MHz

8 MHz

12 MHz20 MHz

TYP

MAX

TYP

2.4

3.6

4.0

2.5

3.8

TYP

MAX

TYP

MAX

0

0.32

0.36

2.1

2.4

1

0.36

2

0.37

3

0.39

0

0.18

2.7

1

0.20

1.2

1.7

2

0.22

1.3

2.0

3

0.23

1.4

2.1

0.21

1.0

4.0

UNIT

MAX

mA
6.6

1.2
1.9

mA
3.6

All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and externalload capacitance are chosen to closely match the required 12.5 pF.
Characterized with program executing typical data processing. USB disabled (VUSBEN = 0, SLDOEN = 0).
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.

8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
TEMPERATURE (TA)PARAMETER

VCC

PMMCOREVx

–40°C
TYP

ILPM0,1MHz

Low-power mode 0(3) (9)ILPM2

Low-power mode 2(4) (9)ILPM3,

Low-power mode 4(7) (9)ILPM4

ILPM3.5,
RTC,VCC20

Low-power mode 3.5(LPM3.5) current withactive RTC into primary
supply pin DVCC (10)Submit Document Feedback

TYP

85°C
MAX

TYP

UNIT
MAX

0

71

75

87

81

85

99

3

78

83

98

89

94

108

2.2 V

0

6.3

6.7

9.9

9.0

11

16

3V

3

6.6

7.0

11

10

12

18

0

1.6

1.8

2.4

4.7

6.5

10.5

1

1.6

1.9

4.8

6.6

2

1.7

2.0

4.9

6.7

0

1.9

2.1

5.0

6.8

1

1.9

2.1

5.1

7.0

2

2.0

2.2

5.2

7.1

3

2.0

2.2

2.9

5.4

7.3

12.6

0

0.9

1.2

1.9

4.0

5.9

10.3

1

0.9

1.2

4.1

6.0

2

1.0

1.3

4.2

6.1

3

1.0

1.3

2.2

4.3

6.3

11.3

0

0.9

1.1

1.8

3.9

5.8

10

1

0.9

1.1

4.0

5.9

2

1.0

1.2

4.1

6.1

3

1.0

1.2

4.2

6.2

11

0.8

1.4

3V

VLO,WDT

60°C
MAX

3V

Low-power mode 3,
crystal mode(5) (9)Low-power mode 3,
VLO mode, Watchdog
enabled(6) (9)

25°C
TYP

2.2 V

2.2 V
ILPM3,XT1LF

MAX

3V

3V

3V

0.5

2.7

2.1

10.8

µA
µA

µA

µA

µA

µA

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8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
TEMPERATURE (TA)PARAMETER

VCC

PMMCOREVx

–40°C
TYP

ILPM3.5,
RTC,VBATILPM3.5,
RTC,TOTILPM4.5

MAX

25°C
TYP

Low-power mode 3.5(LPM3.5) current withactive RTC into backup
supply pin VBAT(11)3V

Total low-power mode 3.5(LPM3.5) current withactive RTC(12)

3V

1.0

1.1

Low-power mode 4.5(LPM4.5)(8)

3V

0.2

0.3

60°C
MAX

TYP

MAX

UNIT

TYP

MAX

0.8

1.4

µA

1.3

1.6

2.8

µA

0.7

0.9

1.4

µA

0.6

0.6

85°C

(1)
(2)

All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and externalload capacitance are chosen to closely match the required 9 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0).
(4) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO
setting = 1 MHz operation, DCO bias generator enabled.
USB disabled (VUSBEN = 0, SLDOEN = 0).
(5) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0).
(6) Current for watchdog timer clocked by VLO included.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fMCLK = fSMCLK = fDCO = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0).
(7) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0).
(8) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz(9) Current for brownout included. Low-side supervisor (SVSL) and low-side monitor (SVML) disabled. High-side supervisor (SVSH) andhigh-side monitor (SVMH) disabled. RAM retention enabled.
(10) VVBAT = VCC – 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active(11) VVBAT = VCC – 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, nocurrent drawn on VBAK(12) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK

8.6 Thermal Resistance Characteristics
PARAMETER
RθJA

Junction-to-ambient thermal resistance, still air(1)RθJC(TOP)

Junction-to-case (top) thermal resistance(2)RθJB

Junction-to-board thermal resistance(3)

(1)
(2)
(3)

VALUE
LQFP (PZ)

122

BGA (ZQW)108

LQFP (PZ)

83

BGA (ZQW)

72

LQFP (PZ)

98

BGA (ZQW)

76

UNIT
°C/W
°C/W
°C/W

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board,as specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

8.7 Schmitt-Trigger Inputs – General-Purpose I/Oover recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETERTEST CONDITIONS

VIT+

Positive-going input threshold voltage

VIT–

Negative-going input threshold voltage

Vhys

Input voltage hysteresis (VIT+ – VIT–)

RPull

Pullup or pulldown resistor(2)For pullup: VIN = VSS
For pulldown: VIN = VCC

CI

Input capacitance

VIN = VSS or VCC

(1)
(2)

VCC

MIN

TYP

1.8 V

0.80

1.40

3V

1.50

2.10

1.8 V

0.45

1.00

3V

0.75

1.65

1.8 V

0.3

0.8

3V

0.4

1.0

20

35

MAX

50

5

UNIT
V
V
V
kΩ
pF

Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
Also applies to RST pin when pullup or pulldown resistor is enabled.

8.8 Inputs – Ports P1, P2, P3, and P4
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
External interrupt timing(2)t(int)(1)(2)

TEST CONDITIONSPort P1, P2, P3, P4: P1.x to P4.x,
External trigger pulse duration to set interrupt flag

VCC

MIN

2.2 V, 3 V

20

MAX

UNIT
ns

Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).

8.9 Leakage Current – General-Purpose I/Oover recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.x)(1)(2)

TEST CONDITIONS

VCC

See (1) (2)High-impedance leakage current

MIN

1.8 V, 3 V

MAX

UNIT

±50

nA

The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor isdisabled.

8.10 Outputs – General-Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS
I(OHmax)

VOH

High-level output voltage= –3 mA(1)I(OHmax) = –10 mA(2)I(OHmax)= –5 mA(1)I(OHmax) = –15 mA(2)I(OLmax)VOL

Low-level output voltage= 3 mA(1)

I(OLmax) = 10 mA(2)I(OLmax)= 5 mA(1)

I(OLmax) = 15 mA(2)
(1)
(2)

22

VCC
1.8 V
3V
1.8 V
3V

MIN

MAX

VCC – 0.25

VCC

VCC – 0.60

VCC

VCC – 0.25

VCC

VCC – 0.60

VCC

VSS

VSS + 0.25

VSS

VSS + 0.60

VSS

VSS + 0.25

VSS

VSS + 0.60

UNIT

V

V

The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage
drop specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.

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8.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(3)PARAMETERTEST CONDITIONS
I(OHmax)

VOH

High-level output voltage= –1 mA(1)1.8 V

I(OHmax) = –3 mA(2)I(OHmax)= –2 mA(1)3V

I(OHmax) = –6 mA(2)I(OLmax) = 1 mA(1)VOL

Low-level output voltage

(2)
(3)

MIN

MAX

VCC – 0.25

VCC

VCC – 0.60

VCC

VCC – 0.25

VCC

VCC – 0.60

VCC

VSS

VSS + 0.25

VSS

VSS + 0.60

VSS

VSS + 0.25

VSS

VSS + 0.60

1.8 V

I(OLmax) = 3 mA(2)I(OLmax) = 2 mA(1)3V

I(OLmax) = 6 mA(2)
(1)

VCC

UNIT

V

V

The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
Selecting reduced drive strength may reduce EMI.

8.12 Output Frequency – Ports P1, P2, and P3
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER

fPx.y

fPort_CLK

(1)
(2)
(3)

TEST CONDITIONSPort output frequency(with load)

P3.4/TA2CLK/SMCLK/S27,
CL = 20 pF, RL = 1 kΩ(1) or 3.2 kΩ(2) (3)Clock output frequency

P1.0/TA0CLK/ACLK/S39,
P3.4/TA2CLK/SMCLK/S27,
P2.0/P2MAP0 (P2MAP0 = PM_MCLK ),CL = 20 pF(3)

MIN

MAX

VCC = 1.8 V,
PMMCOREVx = 0

8

VCC = 3 V,
PMMCOREVx = 3

20

VCC = 1.8 V,
PMMCOREVx = 0

8

VCC = 3 V,
PMMCOREVx = 3

20

UNIT

MHz

MHz

Full drive strength of port: A resistive divider with 2 × 0.5 kΩ between VCC and VSS is used as load. The output is connected to thecenter tap of the divider.
Reduced drive strength of port: A resistive divider with 2 × 1.6 kΩ between VCC and VSS is used as load. The output is connected tothe center tap of the divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

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8.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
8.0
VCC = 3.0 V
P3.2

IOL – Typical Low-Level Output Current – mA

IOL – Typical Low-Level Output Current – mA

25.0

TA = 25°C

20.0

TA = 85°C

15.0

10.0

5.0

0.0
0.0

0.5

1.0

1.5

2.0

2.5

3.0

VOL – Low-Level Output Voltage – V−10.0

TA = 85°C

TA = 25°C

0.5

1.0

1.5

2.0

2.5

3.0

VOH – High-Level Output Voltage – V

3.5

図 8-4. Typical High-Level Output Current vs HighLevel Output Voltage

24

4.0
3.0
2.0
1.0

0.5

1.0

1.5

2.0

図 8-3. Typical Low-Level Output Current vs LowLevel Output Voltage

IOH – Typical High-Level Output Current – mA

IOH – Typical High-Level Output Current – mA

−5.0

−25.0
0.0

TA = 85°C

5.0

0.0
VCC = 3.0 V
P3.2

−20.0

TA = 25°C

VOL – Low-Level Output Voltage – V

0.0

−15.0

VCC = 1.8 V
P3.2

6.0

0.0
0.0

3.5

図 8-2. Typical Low-Level Output Current vs LowLevel Output Voltage

7.0

Submit Document Feedback−1.0

VCC = 1.8 V
P3.2

−2.0
−3.0
−4.0
−5.0

TA = 85°C−6.0
TA = 25°C
−7.0
−8.0
0.0

0.5
1.0
1.5
VOH – High-Level Output Voltage – V

2.0

図 8-5. Typical High-Level Output Current vs HighLevel Output Voltage

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8.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

55.0

24

VCC = 3.0 V
P3.2

TA = 25°C

IOL – Typical Low-Level Output Current – mA

IOL – Typical Low-Level Output Current – mA

60.0

50.0
TA = 85°C

45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
0.0
0.0

0.5

1.0

1.5

2.0

2.5

3.0

VOL – Low-Level Output Voltage – V

図 8-6. Typical Low-Level Output Current vs LowLevel Output Voltage

12

8

4

0.5

1.0

1.5

2.0

図 8-7. Typical Low-Level Output Current vs LowLevel Output Voltage

IOH – Typical High-Level Output Current – mA

IOH – Typical High-Level Output Current – mA

−15.0
−20.0
−25.0
−30.0
−35.0
−40.0
−45.0
TA = 85°C

−55.0
−60.0
0.0

TA = 85°C

0
VCC = 3.0 V
P3.2

−10.0

−50.0

16

VOL – Low-Level Output Voltage – V

0.0
−5.0

TA = 25°C

20

0
0.0

3.5

VCC = 1.8 V
P3.2

VCC = 1.8 V
P3.2
−4

−8

−12
TA = 85°C−16
TA = 25°C

TA = 25°C
0.5

1.0

1.5

2.0

2.5

3.0

VOH – High-Level Output Voltage – V

3.5

図 8-8. Typical High-Level Output Current vs HighLevel Output Voltage

Copyright © 2021 Texas Instruments Incorporated

−20
0.0

0.5

1.0

1.5

2.0

VOH – High-Level Output Voltage – V

図 8-9. Typical High-Level Output Current vs HighLevel Output Voltage

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8.15 Crystal Oscillator, XT1, Low-Frequency Modeover recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(5)PARAMETERTEST CONDITIONS

VCC

MIN

fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
ΔIDVCC,LF

Differential XT1 oscillator crystal
current consumption from lowest
drive setting, LF mode

fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C

fXT1,LF,SW

XT1 oscillator logic-level squarewave input frequency, LF mode

XTS = 0, XT1BYPASS = 1(6) (7)Integrated effective load
capacitance, LF mode(1)CL,eff

fFault,LF

tSTART,LF

(1)
(2)
(3)
(4)
(5)

10

32.768

XTS = 0,XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF

210

XTS = 0,XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF

300
1

XTS = 0, XCAPx = 1

5.5

XTS = 0, XCAPx = 2

8.5

XTS = 0, XCAPx = 3

12.0

XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz

Oscillator fault frequency,
LF mode(4)XTS = 0(3)fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C,
CL,eff = 6 pF
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C,
CL,eff = 12 pF

UNIT

µA

Hz
50

kHz

kΩ

XTS = 0, XCAPx = 0(2)Duty cycle, LF mode

Start-up time, LF mode

0.170

32768

XTS = 0, XT1BYPASS = 0

OALF

3V

0.290

XT1 oscillator crystal frequency,
LF mode

MAX

0.075

fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
fXT1,LF0

Oscillation allowance for
LF crystals(8)

TYP

pF

30%

70%

10

10000

Hz

1000
3V

ms
500

Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For acorrect setup, the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Measured with logic-level input frequency but also applies to operation with crystals.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
To improve EMI on the XT1 oscillator, the following guidelines should be observed.

(7)• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this datasheet.
Maximum frequency of operation of the entire device cannot be exceeded.

26

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Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:••••

For XT1DRIVEx = 0, CL,eff ≤ 6 pF.
For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF.
For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF.
For XT1DRIVEx = 3, CL,eff ≥ 6 pF.

8.16 Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(2) (5)PARAMETERIDVCC,XT2

XT2 oscillator crystal current
consumption

TEST CONDITIONS

VCC

MIN

TYP

fOSC = 4 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C

200

fOSC = 12 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 1,
TA = 25°C

260

fOSC = 20 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C

MAX

3V

UNIT

µA
325

fOSC = 32 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 3,
TA = 25°C

450

fXT2,HF0

XT2 oscillator crystal frequency,mode 0

XT2DRIVEx = 0, XT2BYPASS = 0(7)

4

8

MHz

fXT2,HF1

XT2 oscillator crystal frequency,mode 1

XT2DRIVEx = 1, XT2BYPASS = 0(7)

8

16

MHz

fXT2,HF2

XT2 oscillator crystal frequency,mode 2

XT2DRIVEx = 2, XT2BYPASS = 0(7)

16

24

MHz

fXT2,HF3

XT2 oscillator crystal frequency,mode 3

XT2DRIVEx = 3, XT2BYPASS = 0(7)

24

32

MHz

fXT2,HF,SW

XT2 oscillator logic-level squarewave input frequency

XT2BYPASS = 1(6) (7)

0.7

32

MHz

OAHF

tSTART,HF

fFault,HF(2)(3)

Start-up time450

XT2DRIVEx = 1, XT2BYPASS = 0,
fXT2,HF1 = 12 MHz, CL,eff = 15 pF

320

XT2DRIVEx = 2, XT2BYPASS = 0,
fXT2,HF2 = 20 MHz, CL,eff = 15 pF

200

XT2DRIVEx = 3, XT2BYPASS = 0,
fXT2,HF3 = 32 MHz, CL,eff = 15 pF

200

fOSC = 6 MHz
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF

0.5

fOSC = 20 MHz
XT2BYPASS = 0, XT2DRIVEx = 3,
TA = 25°C, CL,eff = 15 pF

Ω

3V

ms
0.3

Integrated effective load
capacitance, HF mode(1) (2)CL,eff(1)

Oscillation allowance for
HF crystals(8)XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 pF

1

Duty cycle

Measured at ACLK, fXT2,HF2 = 20 MHz

Oscillator fault frequency(4)XT2BYPASS = 1(3)

40%

50%

30

pF
60%
300

kHz

Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For acorrect setup, the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Measured with logic-level input frequency but also applies to operation with crystals.

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(4)
(5)

Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
To improve EMI on the XT2 oscillator the following guidelines should be observed.

(6)
(7)
(8)

• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
• Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When XT2BYPASS is set, the XT2 circuit is automatically powered down.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals.

8.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fVLO
dfVLO/dT

VCC

MIN

TYP

MAX

UNIT

VLO frequency

Measured at ACLK

1.8 V to 3.6 V

6

9.4

14

kHz

VLO frequency temperature drift

Measured at ACLK(1)1.8 V to 3.6 V

0.5

%/°C

Measured at ACLK(2)1.8 V to 3.6 V

4%/V

Measured at ACLK

1.8 V to 3.6 V

dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle(1)(2)

TEST CONDITIONS

40%

50%

60%

Calculated using the box method: (MAX(–40°C to +85°C) – MIN(–40°C to +85°C)) / MIN(–40°C to +85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

8.18 Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERIREFOTEST CONDITIONS

VCC

MIN

TYP

REFO oscillator current
consumption

TA = 25°C

1.8 V to 3.6 V

3
32768

MAX

UNIT
µA

REFO frequency calibrated

Measured at ACLK

1.8 V to 3.6 V

fREFO

REFO absolute tolerance
calibrated

Full temperature range

1.8 V to 3.6 V

dfREFO/dT

REFO frequency temperature drift Measured at ACLK(1)1.8 V to 3.6 V

0.01

%/°C

dfREFO/dVCC

REFO frequency supply voltage
drift

Measured at ACLK(2)1.8 V to 3.6 V

1.0

%/V

Duty cycle

Measured at ACLK

1.8 V to 3.6 V

REFO start-up time

40%/60% duty cycle

1.8 V to 3.6 V

tSTARTTA = 25°C

Hz
±3.5%

3V

±1.5%

40%

50%

60%

25

(1)
(2)

Calculated using the box method: (MAX(–40°C to +85°C) – MIN(–40°C to +85°C)) / MIN(–40°C to +85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

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8.19 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

fDCO(0,0)

DCO frequency (0, 0)

DCORSELx = 0, DCOx = 0, MODx = 0

0.07

0.20

MHz

fDCO(0,31)

DCO frequency (0, 31)

DCORSELx = 0, DCOx = 31, MODx = 0

0.70

1.70

MHz

fDCO(1,0)

DCO frequency (1, 0)

DCORSELx = 1, DCOx = 0, MODx = 0

0.15

0.36

MHz

fDCO(1,31)

DCO frequency (1, 31)

DCORSELx = 1, DCOx = 31, MODx = 0

1.47

3.45

MHz

fDCO(2,0)

DCO frequency (2, 0)

DCORSELx = 2, DCOx = 0, MODx = 0

0.32

0.75

MHz

fDCO(2,31)

DCO frequency (2, 31)

DCORSELx = 2, DCOx = 31, MODx = 0

3.17

7.38

MHz

fDCO(3,0)

DCO frequency (3, 0)

DCORSELx = 3, DCOx = 0, MODx = 0

0.64

1.51

MHz

fDCO(3,31)

DCO frequency (3, 31)

DCORSELx = 3, DCOx = 31, MODx = 0

6.07

14.0

MHz

fDCO(4,0)

DCO frequency (4, 0)

DCORSELx = 4, DCOx = 0, MODx = 0

1.3

3.2

MHz

fDCO(4,31)

DCO frequency (4, 31)

DCORSELx = 4, DCOx = 31, MODx = 0

12.3

28.2

MHz

fDCO(5,0)

DCO frequency (5, 0)

DCORSELx = 5, DCOx = 0, MODx = 0

2.5

6.0

MHz

fDCO(5,31)

DCO frequency (5, 31)

DCORSELx = 5, DCOx = 31, MODx = 0

23.7

54.1

MHz

fDCO(6,0)

DCO frequency (6, 0)

DCORSELx = 6, DCOx = 0, MODx = 0

4.6

10.7

MHz

fDCO(6,31)

DCO frequency (6, 31)

DCORSELx = 6, DCOx = 31, MODx = 0

39.0

88.0

MHz

fDCO(7,0)

DCO frequency (7, 0)

DCORSELx = 7, DCOx = 0, MODx = 0

8.5

19.6

MHz

fDCO(7,31)

DCO frequency (7, 31)

DCORSELx = 7, DCOx = 31, MODx = 0

60

135

MHz

SDCORSEL

Frequency step between range
DCORSEL and DCORSEL + 1

SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)

1.2

2.3

ratio

SDCO

Frequency step between tap
DCO and DCO + 1

SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)

1.02

1.12

ratio

Duty cycle

Measured at SMCLK

40%

dfDCO/dT

DCO frequency temperature drift

fDCO = 1 MHz

0.1

%/°C

dfDCO/dVCC

DCO frequency voltage drift

fDCO = 1 MHz

1.9

%/V

50%

60%

100
VCC = 3.0 V
TA = 25°C

fDCO – MHz

10

DCOx = 311

0.1

DCOx = 0

0

1

2

3

4

5

6

7

DCORSEL

図 8-10. Typical DCO Frequency

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8.20 PMM, Brownout Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSMIN

V(DVCC_BOR_IT–)BORH on voltage,
DVCC falling level| dDVCC/dt | < 3 V/s

V(DVCC_BOR_IT+)BORH off voltage,
DVCC rising level| dDVCC/dt | < 3 V/s

V(DVCC_BOR_hys)

BORH hysteresis

50

tRESET

Pulse duration required at RST/NMI pin to accept
a reset

2

0.80

TYP

1.30

MAX

UNIT

1.45

V

1.50

V

250

mV
µs

8.21 PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

VCORE3(AM)Core voltage, active mode,
PMMCOREV = 3

2.4 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA

1.90

V

VCORE2(AM)Core voltage, active mode,
PMMCOREV = 2

2.2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA

1.80

V

VCORE1(AM)Core voltage, active mode,
PMMCOREV = 1

2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 17 mA

1.60

V

VCORE0(AM)Core voltage, active mode,
PMMCOREV = 0

1.8 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 13 mA

1.40

V

VCORE3(LPM)

Core voltage, low-current
mode, PMMCOREV = 3

2.4 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA

1.94

V

VCORE2(LPM)

Core voltage, low-current
mode, PMMCOREV = 2

2.2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA

1.84

V

VCORE1(LPM)

Core voltage, low-current
mode, PMMCOREV = 1

2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA

1.64

V

VCORE0(LPM)

Core voltage, low-current
mode, PMMCOREV = 0

1.8 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA

1.44

V

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8.22 PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

SVSHE = 0, DVCC = 3.6 V
I(SVSH)

V(SVSH_IT–)

V(SVSH_IT+)SVS current consumption

SVSH on voltage level(1)SVSH off voltage level(1)tpd(SVSH)

SVSH propagation delayt(SVSH)SVSH on or off delay timedVDVCC/dt

DVCC rise time

(1)

MAX

0

SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0

200

SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1

2.0

nA
µA

SVSHE = 1, SVSHRVL = 0

1.59

1.64

1.69

SVSHE = 1, SVSHRVL = 1

1.79

1.84

1.91

SVSHE = 1, SVSHRVL = 2

1.98

2.04

2.11

SVSHE = 1, SVSHRVL = 3

2.10

2.16

2.23

SVSHE = 1, SVSMHRRL = 0

1.62

1.74

1.81

SVSHE = 1, SVSMHRRL = 1

1.88

1.94

2.01

SVSHE = 1, SVSMHRRL = 2

2.07

2.14

2.21

SVSHE = 1, SVSMHRRL = 3

2.20

2.26

2.33

SVSHE = 1, SVSMHRRL = 4

2.32

2.40

2.48

SVSHE = 1, SVSMHRRL = 5

2.56

2.70

2.84

SVSHE = 1, SVSMHRRL = 6

2.85

3.00

3.15

SVSHE = 1, SVSMHRRL = 7

2.85

3.00

3.15

SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1

2.5

SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0

20

SVSHE = 0→1, SVSHFP = 1

12.5

SVSHE = 0→1, SVSHFP = 0

100
0

UNIT

V

V

µs

µs
1000

V/s

The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and usage.

8.23 PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

SVMHE = 0, DVCC = 3.6 V
I(SVMH)

SVMH current consumption

SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0

SVMH on or off voltage level(1)tpd(SVMH)

SVMH propagation delayt(SVMH)

SVMH on or off delay time

(1)

2.0

µA

SVMHE = 1, SVSMHRRL = 0

1.65

1.74

1.86

SVMHE = 1, SVSMHRRL = 1

1.85

1.94

2.02

SVMHE = 1, SVSMHRRL = 2

2.02

2.14

2.22

SVMHE = 1, SVSMHRRL = 3

2.18

2.26

2.35

SVMHE = 1, SVSMHRRL = 4

2.32

2.40

2.48

SVMHE = 1, SVSMHRRL = 5

2.56

2.70

2.84

SVMHE = 1, SVSMHRRL = 6

2.85

3.00

3.15

SVMHE = 1, SVSMHRRL = 7

2.85

3.00

3.15

SVMHE = 1, SVMHOVPE = 1

3.75

SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1

2.5

SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0

20

SVMHE = 0→1, SVSMFP = 1

12.5

SVMHE = 0→1, SVMHFP = 0

100

UNIT
nA

200

SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1

V(SVMH)

MAX

0

V

µs

µs

The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and usage.

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8.24 PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

SVSLE = 0, PMMCOREV = 2
I(SVSL)SVSL current consumption

tpd(SVSL)SVSL propagation delayt(SVSL)SVSL on or off delay timeMAX

0

SVSLE = 1, PMMCOREV = 2, SVSLFP = 0

200

SVSLE = 1, PMMCOREV = 2, SVSLFP = 1

2.0

SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1

2.5

SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0

20

SVSLE = 0→1, SVSLFP = 1

12.5

SVSLE = 0→1, SVSLFP = 0

100

UNIT
nA
µA
µs
µs

8.25 PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

SVMLE = 0, PMMCOREV = 2
I(SVML)

SVML current consumption

tpd(SVML)

SVML propagation delayt(SVML)

SVML on or off delay timeMAX

0

SVMLE = 1, PMMCOREV = 2, SVMLFP = 0

200

SVMLE = 1, PMMCOREV = 2, SVMLFP = 1

2.0

SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1

2.5

SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0

20

SVMLE = 0→1, SVMLFP = 1

12.5

SVMLE = 0→1, SVMLFP = 0

100

UNIT
nA
µA
µs
µs

8.26 Wake-up Times From Low-Power Modes and Resetover recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

TYP

MAX

fMCLK ≥ 4 MHz

MIN

3

6.5

UNIT

1 MHz < fMCLK <
4 MHz

4

8.0

150

165

µs

tWAKE-UP-FAST

Wake-up time from LPM2,
LPM3, or LPM4 to activemode(1)

PMMCOREV = SVSMLRRL = n(where n = 0, 1, 2, or 3),
SVSLFP = 1

tWAKE-UP-SLOW

Wake-up time from LPM2,
LPM3, or LPM4 to activemode(2) (3)

PMMCOREV = SVSMLRRL = n(where n = 0, 1, 2, or 3),
SVSLFP = 0

tWAKE-UP-LPM5

Wake-up time from LPM3.5 orLPM4.5 to active mode(4)

2

3

ms

tWAKE-UP-RESET

Wake-up time from RST or
BOR event to active mode(4)

2

3

ms

(1)

µs

(4)

This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on theperformance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in
full performance mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode
Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx
Family User's Guide.
This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on theperformance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in
normal mode (low current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode
Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx
Family User's Guide.
The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by
the performance mode settings as for LPM2, LPM3, and LPM4.
This value represents the time from the wake-up event to the reset vector execution.

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8.27 Timer_A, Timers TA0, TA1, and TA2over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCC

MIN

fTA

Timer_A input clock frequency

Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%

1.8 V, 3 V

tTA,cap

Timer_A capture timing

All capture inputs, Minimum pulse
duration required for capture

1.8 V, 3 V

MAX UNIT
20

MHz

20

ns

MIN

MAX UNIT

8.28 Timer_B, Timer TB0
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCC

fTB

Timer_B input clock frequency

Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%

1.8 V, 3 V

tTB,cap

Timer_B capture timing

All capture inputs, Minimum pulse
duration required for capture

1.8 V, 3 V

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20
20

MHz
ns

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8.29 Battery Backup
over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSVBAT = 1.7 V,
DVCC not connected,
RTC running

Current into VBAT terminal if noprimary battery is connected

IVBAT

VBAT = 2.2 V,
DVCC not connected,
RTC running

VBAT = 3 V,
DVCC not connected,
RTC running

VCC

MIN

TA = –40°C

0.43

TA = 25°C

0.52

TA = 60°C

0.58

TA = 85°C

0.64

TA = –40°C

0.50

TA = 25°C

0.59

TA = 60°C

0.64

TA = 85°C

0.71

TA = –40°C

0.68

TA = 25°C

0.75

TA = 60°C

0.79

TA = 85°C

Switch-over level (VCC to VBAT)CVCC = 4.7 µF

RON_VBAT

ON-resistance of switch between
VBAT = 1.8 V
VBAT and VBAKVBAT3VBAT to ADC input channel 12:
VBAT divided, VBAT3 = VBAT/3

tSample,µA

SVSHRL = 0

1.59

1.69

SVSHRL = 1

1.79

1.91

SVSHRL = 2

1.98

2.11

SVSHRL = 3

2.10

2.23

0V

0.35

1

1.8 V

0.6

±5%

3V

1.0

±5%

3.6 V

1.2

±5%

VBAT3

ADC12ON = 1,
Error of conversion result ≤ 1 LSB

1000

VCHVx

Charger end voltage

CHVx = 2

2.65

RCHARGE

Charge limiting resistor

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UNIT

VSVSH_IT-VBAT to ADC: Sampling timerequired if VBAT3 selected

34

MAX

0.86

GeneralVSWITCH

TYP

V

kΩ

V

ns
2.7

2.9

CHCx = 1

5

CHCx = 2

10

CHCx = 320VkΩ

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8.30 USCI (UART Mode)over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fUSCI

USCI input clock frequency

fBITCLKBITCLK clock frequency(equals baud rate in MBaud)tτ

UART receive deglitch time(1)(1)

TEST CONDITIONS

VCC

MIN

Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%

MAX

UNIT

fSYSTEM

MHz

1

MHz

2.2 V

50

600

3V

50

600

ns

Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses arecorrectly recognized their width should exceed the maximum specification of the deglitch time.

8.31 USCI (SPI Master Mode)over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(see 図 8-11 and 図 8-12)
PARAMETER
fUSCI

USCI input clock frequency

TEST CONDITIONSPMMCOREV = 0
tSU,MISOMI input data setup time
PMMCOREV = 3
PMMCOREV = 0

tHD,MISOMI input data hold time
PMMCOREV = 3

tVALID,MO

SIMO output data valid time(2)

(2)
(3)

1.8 V

55

3V

38

2.4 V

30

3V

25

1.8 V

0

3V

0

2.4 V

0

3V

0

MAX

UNIT

fSYSTEM

MHz

ns

ns

1.8 V

20

3V

18

UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3

2.4 V

16

3V

15

SIMO output data hold time(3)CL = 20 pF, PMMCOREV = 3

(1)

MIN

UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 0

CL = 20 pF, PMMCOREV = 0
tHD,MOVCC

SMCLK or ACLK,
Duty cycle = 50% ±10%

1.8 V

–10

3V

–8

2.4 V

–10

3V

–8

ns

ns

fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagramsin 図 8-11 and 図 8-12.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the dataon the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in 図 8-11
and 図 8-12.

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1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLO/HItLO/HI

tSU,MI
tHD,MI

SOMI
tHD,MOtVALID,MOSIMO

図 8-11. SPI Master Mode, CKPH = 0
1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLO/HItLO/HI
tSU,MI

tHD,MI

SOMI
tHD,MOtVALID,MOSIMO

図 8-12. SPI Master Mode, CKPH = 1

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8.32 USCI (SPI Slave Mode)over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(see 図 8-13 and 図 8-14)
PARAMETERTEST CONDITIONSPMMCOREV = 0

tSTE,LEAD

STE lead time, STE low to clock
PMMCOREV = 3
PMMCOREV = 0

tSTE,LAG

STE lag time, Last clock to STE high
PMMCOREV = 3
PMMCOREV = 0

tSTE,ACC

STE access time, STE low to SOMI data out
PMMCOREV = 3
PMMCOREV = 0

tSTE,DIS

STE disable time, STE high to SOMI high impedance
PMMCOREV = 3
PMMCOREV = 0

tSU,SISIMO input data setup time
PMMCOREV = 3
PMMCOREV = 0

tHD,SISIMO input data hold time
PMMCOREV = 3

tVALID,SO

tHD,SO

(1)
(2)
(3)

SOMI output data valid time(2)SOMI output data hold time(3)

VCC

MIN

1.8 V

11

3V

8

2.4 V

7

3V

6

1.8 V

3

3V

3

2.4 V

3

3V

3

MAX

ns

ns

1.8 V

66

3V

50

2.4 V

36

3V

30

1.8 V

30

3V

23

2.4 V

16

3V

UNIT

ns

ns

13

1.8 V

5

3V

5

2.4 V

2

3V

2

1.8 V

5

3V

5

2.4 V

5

3V

5

ns

ns

UCLK edge to SOMI valid,
CL = 20 pF,
PMMCOREV = 0

1.8 V

76

3V

60

UCLK edge to SOMI valid,
CL = 20 pF,
PMMCOREV = 3

2.4 V

44

3V

40

CL = 20 pF,
PMMCOREV = 0

1.8 V

18

3V

12

CL = 20 pF,
PMMCOREV = 3

2.4 V

10

3V

8

ns

ns

fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagramsin 図 8-13 and 図 8-14.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in 図 8-13
and 図 8-14.

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tSTE,LEAD

tSTE,LAG

STE
1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLO/HItSU,SItLO/HI

tHD,SI
SIMO
tHD,SOtVALID,SOtSTE,ACC

tSTE,DISSOMI

図 8-13. SPI Slave Mode, CKPH = 0
tSTE,LAG

tSTE,LEAD
STE
1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLO/HItLO/HI
tHD,SItSU,SISIMO

tSTE,ACC

tHD,MOtVALID,SOtSTE,DISSOMI

図 8-14. SPI Slave Mode, CKPH = 1

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8.33 USCI (I2C Mode)over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 図 8-15)
PARAMETERTEST CONDITIONS

fUSCIUSCI input clock frequencyfSCL

SCL clock frequency

tHD,STA

Hold time (repeated) STARTtSU,STA

Setup time for a repeated STARTtHD,DAT

Data hold time

tSU,DAT

Data setup time

VCC

MIN

Internal: SMCLK or ACLK,
External: UCLK
Duty cycle = 50% ±10%
2.2 V, 3 V
fSCL ≤ 100 kHz
fSCL ≤ 100 kHz

Setup time for STOPtSP

Pulse duration of spikes suppressed by
input filter

tSU,STAtHD,STA

MHz

400

kHz
µs

4.7

µs

0.6

2.2 V, 3 V

0ns

2.2 V, 3 V

250

ns

4.0

2.2 V, 3 V

fSCL > 100 kHz

fSYSTEM

0.6

2.2 V, 3 V

fSCL > 100 kHz

UNIT

4.0

2.2 V, 3 V

fSCL > 100 kHz

fSCL ≤ 100 kHz

tSU,STO

0

MAX

µs

0.6

2.2 V

50

600

3V

50

600

tHD,STA

ns

tBUF

SDA
tLOW

tHIGH

tSP

SCL

tSU,DATtSU,STOtHD,DAT

図 8-15. I2C Mode Timing

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8.34 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(2)PARAMETERTEST CONDITIONS

VCC

AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V

AVCC

Analog supply voltage

V(Ax)Analog input voltage range(3) All ADC12 analog input pins Ax

0Operating supply current into
fADC12CLK = 5 MHz(1)AVCC terminal(4)CI

Input capacitance

Only one terminal Ax can be selected at one
time

RI

Input MUX ON resistance0 V ≤ VIN ≤ V(AVCC)

(4)

TYP

2.2

IADC12_A

(1)
(2)
(3)

MIN

MAX

UNIT

3.6

V

AVCC

V

2.2 V

150

200

3V

150

250

2.2 V

20

25

pF

200

1900

Ω

10

µA

ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0
The leakage current is specified by the digital I/O input leakage.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If thereference voltage is supplied by an external source or if the internal voltage is used and REFOUT = 1, then decoupling capacitors are
required. See セクション 8.40 and セクション 8.41.
The internal reference supply current is not included in current consumption parameter IADC12.

8.35 12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCCFor specified performance of ADC12 linearity
parameters using an external reference
voltage or AVCC as reference(1)fADC12CLKADC conversion clock

For specified performance of ADC12 linearity
parameters using the internal reference(2)2.2 V, 3 V

For specified performance of ADC12 linearity
parameters using the internal reference(3)fADC12OSC

tCONVERTtSample(1)

Internal ADC12
oscillator(5)Conversion time

Sampling time

MIN

TYP

MAX

0.45

4.8

5.0

0.45

2.4

4.0

0.45

2.4

2.7

4.8

5.4

ADC12DIV = 0, fADC12CLK = fADC12OSC

2.2 V, 3 V

4.2

REFON = 0, Internal oscillator,
ADC12OSC used for ADC conversion clock

2.2 V, 3 V

2.4

External fADC12CLK from ACLK, MCLK or
SMCLK, ADC12SSEL ≠ 0
RS = 400 Ω, RI = 200 Ω, CI = 20 pF,
τ = (RS + RI) × CI (4)

UNIT

MHz

MHz

3.1
13 ×

µs

1 / fADC12CLK
2.2 V, 3 V

1000

ns

(5)

REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,
SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, thespecified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5 MHz.
SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1
SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured whenusing the ADC12OSC divided by 2.
Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
The ADC12OSC is sourced directly from MODOSC inside the UCS.

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(2)
(3)
(4)

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8.36 12-Bit ADC, Linearity Parameters Using an External Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS
1.4 V ≤ dVREF ≤ 1.6 V(1)EI

Integral linearity error(2)ED

Differential linearity error(2)EO

Offset error(3)EG

Gain error(3)

ET

(1)

(2)
(3)

1.6 V < dVREF (1)Total unadjusted error

VCC

MIN

TYP

MAX
±2

2.2 V, 3 V±1.7

See (1)

2.2 V, 3 V

dVREF ≤ 2.2 V(1)2.2 V, 3 V

±3

±5.6

dVREF > 2.2 V(1)2.2 V, 3 V

±1.5

±3.5

See (1)

2.2 V, 3 V

±1

±2.5

dVREF ≤ 2.2 V(1)2.2 V, 3 V

±3.5

±7.1

dVREF > 2.2 V(1)2.2 V, 3 V

±2

±5

±1

UNIT
LSB
LSB
LSB
LSB
LSB

The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ - VR-. VR+ < AVCC. VR- > AVSS.
Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω, and two decoupling capacitors,
10 µF and 100 nF, should be connected to VREF+/VREF- to decouple the dynamic current. See also the MSP430F5xx and
MSP430F6xx Family User's Guide.
Parameters are derived using the histogram method.
Parameters are derived using a best fit curve.

8.37 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

±1.7

LSB

±1

LSB

±2

LSB

±2

±4

LSB

±2

±5

LSB

TYP

MAX

UNIT

EI

Integral linearity error(2)See (1)

2.2 V, 3 VED

Differential linearity error(2)See (1)

2.2 V, 3 V

EO

Offset error(3)See (1)

2.2 V, 3 V±1EGGain error(3)See (1)

2.2 V, 3 V

ETTotal unadjusted error

See (1)

2.2 V, 3 V

(1)
(2)
(3)

AVCC as reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 0.
Parameters are derived using the histogram method.
Parameters are derived using a best fit curve.

8.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST CONDITIONS(1)PARAMETER
EI

Integral linearity error(2)ED

Differential
linearity error(2)EO

Offset error(3)EG

Gain error(3)

ET

(1)
(2)
(3)
(4)

Total unadjusted error

ADC12SR = 0, REFOUT = 1

fADC12CLK ≤ 4.0 MHz

ADC12SR = 0, REFOUT = 0

fADC12CLK ≤ 2.7 MHz

ADC12SR = 0, REFOUT = 1

fADC12CLK ≤ 4.0 MHz

ADC12SR = 0, REFOUT = 1

fADC12CLK ≤ 2.7 MHz

ADC12SR = 0, REFOUT = 0

fADC12CLK ≤ 2.7 MHz

ADC12SR = 0, REFOUT = 1

fADC12CLK ≤ 4.0 MHz

ADC12SR = 0, REFOUT = 0

fADC12CLK ≤ 2.7 MHz

ADC12SR = 0, REFOUT = 1

fADC12CLK ≤ 4.0 MHz

ADC12SR = 0, REFOUT = 0

fADC12CLK ≤ 2.7 MHz

ADC12SR = 0, REFOUT = 1

fADC12CLK ≤ 4.0 MHz

ADC12SR = 0, REFOUT = 0

fADC12CLK ≤ 2.7 MHz

VCC

MIN

±1.7

2.2 V, 3 V

±2.5
–1

+1.5

–1

+2.5

2.2 V, 3 V±1

2.2 V, 3 V

2.2 V, 3 V

LSB

±2

±4

±2

±4

±1

±2.5

LSB

±1%(4)VREF±2

2.2 V, 3 V

LSB

LSB

±5

LSB

±1%(4)VREF

The external reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 1. dVREF = VR+ - VR-.
Parameters are derived using the histogram method.
Parameters are derived using a best fit curve.
The gain error and the total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In
this mode the reference voltage used by the ADC12_A is not available on a pin.

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8.39 12-Bit ADC, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETERVSENSOR

Temperature sensor voltage(2)(see )図 8-16

TEST CONDITIONS

VCC

MIN

TYP

ADC12ON = 1, INCH = 0Ah,
TA = 0°C

2.2 V

680

3V

680

2.2 V

2.25

3V

2.25

MAX

mV

TCSENSOR

Temperature coefficient ofsensor(2)ADC12ON = 1, INCH = 0Ah

tSENSOR(sample)

Sample time required ifchannel 10 is selected(3)ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB

2.2 V

100

3V

100

VMID

AVCC divider at channel 11

ADC12ON = 1, INCH = 0Bh,
VMID ≈ 0.5 × VAVCC

2.2 V

1.06

1.1

1.14

3V

1.46

1.5

1.54

tVMID(sample)

Sample time required ifchannel 11 is selected(4)ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB

2.2 V, 3 V

1000

(1)
(2)

(3)
(4)

UNIT

mV/°C
µs
V
ns

The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current consumption of
the temperature sensor.
The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor. The TLV structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference
voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature,°C) + VSENSOR, where TCSENSOR andVSENSOR can be computed from the calibration values for higher accuracy. See also the MSP430F5xx and MSP430F6xx Family User's
Guide.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.

Typical Temperature Sensor Voltage (mV)

1000
950
900
850
800
750
700
650
600
550
500
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Ambient Temperature (°C)

図 8-16. Typical Temperature Sensor Voltage

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

8.40 REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETERTEST CONDITIONS

VCC

MIN

MAX

UNIT

1.4

AVCC

V

VeREF+

Positive external reference
VeREF+ > VREF-/VeREF- (2)voltage input

VREF-/VeREF-

Negative externalreference voltage input

VeREF+ > VREF-/VeREF- (3)

0

1.2

V

VeREF+ –VREF-/VeREF-

Differential externalreference voltage input

VeREF+ > VREF-/VeREF- (4)

1.4

AVCC

V

–26

26

IVeREF+, IVREF-/
VeREF-

CVREF+/(1)
(2)
(3)
(4)
(5)

Static input current

Capacitance at VREF+ or
VREF- terminal(5)1.4 V ≤ VeREF+ ≤ VAVCC , VeREF- = 0 V,
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
Conversion rate 200 ksps

2.2 V, 3 V

1.4 V ≤ VeREF+ ≤ VAVCC , VeREF- = 0 V,
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
Conversion rate 20 ksps

2.2 V, 3 V

µA
–1.2
10

+1.2
µF

The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, isalso the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow therecommendations on analog-source impedance to let the charge settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Connect two decoupling capacitors, 10 µF and 100 nF, to VREF to decouple the dynamic current required for an external reference
source if it is used for the ADC12_A. Also see the MSP430F5xx and MSP430F6xx Family User's Guide.

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8.41 REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER

VREF+TEST CONDITIONSVCCREFVSEL = {2} for 2.5 V,
REFON = REFOUT = 1 , IVREF+ = 0 A
Positive built-in
REFVSEL = {1} for 2 V,
reference voltage output REFON = REFOUT = 1, IVREF+ = 0 A
REFVSEL = {0} for 1.5 V,
REFON = REFOUT = 1, IVREF+ = 0 A
AVCC(min)

TYP

MAX

3V

2.5

±1%

3V

2.0

±1%

2.2 V, 3 V

1.5

±1%

REFVSEL = {0} for 1.5 V
AVCC minimum voltage,
Positive built-in
REFVSEL = {1} for 2 V
reference active
REFVSEL = {2} for 2.5 V

MIN

UNIT

V

2.2
2.3

V

2.8

ADC12SR = 1(8), REFON = 1, REFOUT = 0,
REFBURST = 0

70

100

µA

0.45

0.75

mA

210

310

µA

ADC12SR = 0(8), REFON = 1, REFOUT = 1,
REFBURST = 0

0.95

1.7

mA

IL(VREF+)

Load-current regulation,
VREF+ terminal(3)REFVSEL = {0, 1, 2},
IVREF+ = +10 µA , –1000 µA,
AVCC = AVCC(min) for each reference level,
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1

1500

CVREF+

Capacitance at VREF+
terminal

REFON = REFOUT = 1(6),0 mA ≤ IVREF+ ≤ IVREF+(max)

TCREF+

Temperature coefficientof built-in reference(4)IVREF+ is a constant in the rangeof 0 mA ≤ IVREF+ ≤ –1 mA

REFOUT = 0

2.2 V, 3 V

20

TCREF+

Temperature coefficientof built-in reference(4)IVREF+ is a constant in the rangeof 0 mA ≤ IVREF+ ≤ –1 mA

REFOUT = 1

2.2 V, 3 V

20

50

ppm/
°C

PSRR_DCPower supply rejection
ratio (DC)

AVCC = AVCC(min) to AVCC(max),
TA = 25°C, REFVSEL = {0, 1, 2}, REFON = 1,
REFOUT = 0 or 1

120

300

µV/V

PSRR_ACPower supply rejection
ratio (AC)AVCC = AVCC(min) to AVCC(max),
TA = 25°C, REFVSEL = {0, 1, 2}, REFON = 1,
REFOUT = 0 or 1

1

tSETTLEAVCC = AVCC(min) to AVCC(max),
REFVSEL = {0, 1, 2}, REFOUT = 0,
Settling time of reference REFON = 0 → 1
voltage(5)AVCC = AVCC(min) to AVCC(max),
CVREF = CVREF(max), REFVSEL = {0, 1, 2},
REFOUT = 1, REFON = 0 → 1

ADC12SR = 1(8), REFON = 1, REFOUT = 1,
Operating supply current REFBURST = 0
into AVCC terminal (2) (7) ADC12SR = 0(8), REFON = 1, REFOUT = 0,
REFBURST = 0

IREF+

(1)

(2)
(3)
(4)
(5)
(6)

44

3V

2.2 V, 3 V

202500 µV/mA

100

pF
ppm/
°C

mV/V

75
µs
75

The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers,
one smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal, as wellas, used as the reference for the conversion and uses the larger buffer. When REFOUT = 0, the reference is only used as thereference for the conversion and uses the smaller buffer.
The internal reference current is supplied by the AVCC terminal. Consumption is independent of the ADC12ON control bit, unless aconversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current
contribution of the larger buffer without external load.
Contribution only due to the reference and buffer including package. This does not include resistance due to PCB traces or otherexternal factors.
Calculated using the box method: (MAX(–40°C to +85°C) – MIN(–40°C to +85°C)) / MIN(–40°C to +85°C)/(85°C – (–40°C)).
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load when REFOUT = 1.
Connect two decoupling capacitors, 10 µF and 100 nF, to VREF to decouple the dynamic current required for an external reference
source if it is used for the ADC12_A. Also see the MSP430F5xx and MSP430F6xx Family User's Guide.

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

The temperature sensor is provided by the REF module. Its current is supplied by terminal AVCC and is equivalent to IREF+ with
REFON = 1 and REFOUT = 0.
For devices without the ADC12, the parametric with ADC12SR = 0 are applicable.

8.42 12-Bit DAC, Supply Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
AVCC

Analog supply voltage

TEST CONDITIONSAVCC = DVCC, AVSS = DVSS = 0 V
DAC12AMPx = 2, DAC12IR = 0,
DAC12OG = 1, DAC12_xDAT = 0800h,
VeREF+ = VREF+ = 1.5 V

Supply current, single DAC
channel(1) (2)

IDD

VCC

3V

PSRR

(1)
(2)
(3)
(4)

MAX

UNIT

3.60

V

65

110

125

165
µA

2.2 V, 3 V

DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREF+ = AVCC
Power supply rejection ratio(3) (4)

TYP

2.20

DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREF+ = AVCC
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREF+ = AVCC

MIN

250

350

750

1100

DAC12_xDAT = 800h,
VeREF+ = 1.5 V, ΔAVCC = 100 mV

2.2 V

70

DAC12_xDAT = 800h,
VeREF+ = 1.5 V or 2.5 V, ΔAVCC = 100 mV

3V

70

dB

No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
PSRR = 20 log (ΔAVCC / ΔVDAC12_xOUT)
The internal reference is not used.

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

8.43 12-Bit DAC, Linearity Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 図 8-17)
PARAMETER
Resolution

TEST CONDITIONS

MIN

12-bit monotonic

INL

Integral nonlinearity(2)DNL

Differential nonlinearity(2)12EGGain errordE(G)/dT

Gain temperature
coefficient(2)tOffset_Cal

Time for offset
calibration(4)±4(1)

VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1

3V

±2

±4

VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1

2.2 V

±0.4

±1(1)

VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1

3V

±0.4

±1

VeREF+ = 1.5 V,
DAC12AMPx = 7,
DAC12IR = 1

2.2 V±21(1)

VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1

3V

±21

VeREF+ = 1.5 V,
DAC12AMPx = 7,
DAC12IR = 1

2.2 V±1.5(1)

VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1

3V

±1.5

With calibration

2.2 V, 3 V±10

VeREF+ = 1.5 V

2.2 V

±2.5

VeREF+ = 2.5 V

3V

±2.5

2.2 V, 3 V

LSB

µV/°C
%FSR
ppm of
FSR/
°C

10
165

DAC12AMPx = 3, 5

2.2 V, 3 V

66

DAC12AMPx = 4, 6, 7

(3)
(4)

LSB

mV

DAC12AMPx = 2

(1)
(2)

UNIT
bits

±2

With calibration(2) (3)Offset error temperature
coefficient(2)

MAX

2.2 V

Offset voltage

dE(O)/dT

TYP

VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1

Without calibration(2) (3)

EO

VCC

ms

16.5

This parameter is not production tested.
Parameters calculated from the best-fit curve from 0x0F to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b"of the first-order equation: y = a + bx. VDAC12_xOUT = EO + (1 + EG) × (VeREF+ / 4095) × DAC12_xDAT, DAC12IR = 1.
The offset calibration works on the output operational amplifier. Offset calibration is triggered by setting the DAC12CALON bit.
The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx= {0, 1}. TI recommends configuring the DAC12 module before initiating calibration. Port activity during calibration may effect accuracy
and is not recommended.

DAC VOUTDAC Output

VR+

RLoad = ¥Ideal transfer
function

AVCC
2
CLoad = 100 pF

Offset Error
Positive
Negative

Gain Error
DAC Code

図 8-17. Linearity Test Load Conditions and Gain and Offset Definitions

46

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

8.44 12-Bit DAC, Output Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCC

MIN

No load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7

Output voltage range(1)VO(see 図 8-18)

No load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7

Maximum DAC12 load
capacitance

IL(DAC12)

Maximum DAC12 load
current

Output resistance (see
図 8-18)00.005

AVCC –0.05

AVCC

DAC12AMPx = 2, DAC12_xDAT = 0FFFh,
VO/P(DAC12) > AVCC – 0.3
DAC12AMPx = 2, DAC12_xDAT = 0h,
VO/P(DAC12) < 0.3 V

00.1

AVCC –
0.13

AVCC
100

pF

–1
2.2 V, 3 V

mA
1RLoad = 3 kΩ, VO/P(DAC12) > AVCC – 0.3 V,
DAC12_xDAT = 0FFFh

2.2 V, 3 V

150

250

150

250

RLoad = 3 kΩ,
0.3 V ≤ VO/P(DAC12) ≤ AVCC – 0.3 V
(1)

UNIT

V

2.2 V, 3 V

RLoad = 3 kΩ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 2, DAC12_xDAT = 0h
RO/P(DAC12)MAX

2.2 V, 3 V

RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
CL(DAC12)

TYP

Ω

6

Data is valid after the offset calibration of the output amplifier.

RO/P(DAC12_x)
Max

RLoad

ILoad

AVCC

DAC12

2
O/P(DAC12_x)

CLoad = 100 pF

Min
0.3

AVCC – 0.3 V

VOUT

AVCC

図 8-18. DAC12_x Output Resistance Tests

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8.45 12-Bit DAC, Reference Input Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

Reference input voltage
range

VeREF+VCC

DAC12IR = 0(1) (2)

MIN

20

V
MΩ

DAC12_0 IR = 1, DAC12_1 IR = 0

48

Reference input resistance DAC12_0 IR = 0, DAC12_1 IR = 1

2.2 V, 3 V

48

DAC12_0 IR = DAC12_1 IR = 1,
DAC12_0 SREFx = DAC12_1 SREFx(5)
(1)
(2)
(3)
(4)
(5)

UNIT

AVCC AVCC + 0.2

DAC12_0 IR = DAC12_1 IR = 0
Ri(VREF+),
Ri(VeREF+)

MAX

AVCC / 3 AVCC + 0.2

2.2 V, 3 V

DAC12IR = 1(3) (4)

TYP

kΩ

24

For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = (AVCC – VE(O)) / (3 × (1 + EG)).
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = (AVCC – VE(O)) / (1 + EG).
When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.

8.46 12-Bit DAC, Dynamic Specifications
VREF = VCC, DAC12IR = 1 (see 図 8-19 and 図 8-20), over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER

tON

VCC

DAC12AMPx = 0 → {5, 6}

2.2 V, 3 V

TYP

MAX

60

120

15

30

6

12

100

200

40

80

15

30

DAC12AMPx = 0 → 7
DAC12AMPx = 2
DAC12AMPx = 3, 5

DAC12_xDAT =3F8h → 408h → 3F8h,
BF8h → C08h → BF8h

DAC12AMPx = 3, 5

Slew rate

DAC12_xDAT =80h → F7Fh → 80h(2)DAC12AMPx = 3, 5

Glitch energy

DAC12_xDAT =800h → 7FFh → 800h

DAC12AMPx = 7

Settling time, code to
code

MIN

DAC12AMPx = 0 → {2, 3, 4}

DAC12_xDAT =80h → F7Fh → 80h

Settling time, full scaletS(C-C)(1)(2)

DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB(1)(see 図 8-19)

DAC12 on timetS(FS)SR

TEST CONDITIONS

2.2 V, 3 V

DAC12AMPx = 4, 6, 7
DAC12AMPx = 2

UNIT

µs

µs

5
2.2 V, 3 V

2

DAC12AMPx = 4, 6, 7

µs

1

DAC12AMPx = 2
2.2 V, 3 V

DAC12AMPx = 4, 6, 7

0.05

0.35

0.35

1.10

1.50

5.20

2.2 V, 3 V

35

V/µs

nV-s

RLoad and CLoad connected to AVSS (not AVCC/2) in 図 8-19.
Slew rate applies to output voltage steps ≥ 200 mV.

Conversion 1
VOUT

DAC Output
ILoad

RLoad = 3 kW

Conversion 2

Conversion 3±1/2 LSB

GlitchEnergyAVCC
2
RO/P(DAC12.x)±1/2 LSB

CLoad = 100 pF

tsettleLH

tsettleHL

図 8-19. Settling Time and Glitch Energy Testing48

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Conversion 1

Conversion 2

Conversion 3

90%

90%

VOUT

10%

10%

tSRLH

tSRHL

図 8-20. Slew Rate Testing

8.47 12-Bit DAC, Dynamic Specifications (Continued)
over recommended ranges of supply voltage and TA = 25°C (unless otherwise noted)
PARAMETER

BW–3dBTEST CONDITIONS

VCC

3-dB bandwidth,
VDC = 1.5 V,
VAC = 0.1 VPP(see 図 8-21)

DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h

TYP

MAX

UNIT

40
180

2.2 V, 3 V

DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h

kHz

550

DAC12_0DAT = 800h, No load,
DAC12_1DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
fDAC12_1OUT = 10 kHz at 50/50 duty cycle

Channel-to-channel
crosstalk(1) (see 図 8-22) DAC12_0DAT = 80h ↔ F7Fh, R
Load = 3 kΩ,
DAC12_1DAT = 800h, No load,
fDAC12_0OUT = 10 kHz at 50/50 duty cycle
(1)

MIN

DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h

–80
2.2 V, 3 V

dB–80

RLoad = 3 kΩ, CLoad = 100 pF
RLoad = 3 kW
ILoad

VeREF+AVCC

DAC12_x

2

DACx

AC

CLoad = 100 pF

DC

図 8-21. Test Conditions for 3-dB Bandwidth Specification
RLoad
ILoad
AVCC

DAC12_02

DAC0

DAC12_xDAT 080h

F7Fh

080h

F7Fh

080h

VOUT

CLoad = 100 pF

VREF+

VDAC12_yOUT

RLoad
ILoad
AVCC

DAC12_1

VDAC12_xOUT

2

DAC1

1/fToggle

CLoad = 100 pF

図 8-22. Crosstalk Test Conditions

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8.48 Comparator_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERVCCTEST CONDITIONS

VCC

MIN

Supply voltage

TYP

1.8

3.6

1.8 V
Comparator operating supply current
IAVCC_COMP into AVCC terminal, excludes
reference resistor ladder

IAVCC_REF

Quiescent current of local reference
voltage amplifier into AVCC terminal

VIC

Common-mode input range

VOFFSET

Input offset voltage

CIN

Input capacitance

RSIN

Series input resistancetPD

Propagation delay, response time

tPD,filter

tEN_CMPPropagation delay with filter active

Comparator enable time, settling time

CBPWRMD = 00

30

50

3V

40

65

CBPWRMD = 01

2.2 V, 3 V

1030

CBPWRMD = 10

2.2 V, 3 V

0.1

0.5

CBREFACC = 1, CBREFLx = 01
0

VCC – 1

V

±20
±10
5
3
50

CBPWRMD = 01, CBF = 0600

CBPWRMD = 10, CBF = 050

CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 00

0.35

0.6

1.0

CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 01

0.6

1.0

1.8

CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 10

1.0

1.8

3.4

CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 11

1.8

3.4

6.5

1

2

VIN = reference into resistor
ladder, n = 0 to 31µsµs

CBON = 0 to CBON = 1,
CBPWRMD = 10

Reference voltage for a given tap

nsµs

CBON = 0 to CBON = 1,
CBPWRMD = 00, 01

VCB_REF

kΩ
MΩ

450

CBON = 0 to CBON = 1

mV
pF

4

CBPWRMD = 00, CBF = 0

Resistor reference enable time

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CBPWRMD = 01, 10
On (switch closed)µA

22

CBPWRMD = 00

Off (switch open)

V

40

2.2 V

tEN_REF50

MAX UNIT

100
0.3
VIN ×
(n + 0.5)
/ 32

1.5

µs

VIN ×
VIN ×
(n + 1) (n + 1.5)
/ 32
/ 32

V

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8.49 Ports PU.0 and PU.1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

VOH

High-level output voltage

VUSB = 3.3 V ±10%, IOH = –25 mA

2.4

VOL

Low-level output voltage

VUSB = 3.3 V ±10%, IOL = 25 mA

VIH

High-level input voltage

VUSB = 3.3 V ±10%

VIL

Low-level input voltage

VUSB = 3.3 V ±10%

MAX

UNIT
V

0.4
2.0

V
V

0.8

V

MIN

MAX

UNIT
V

8.50 USB Output Ports DP and DM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VOH

D+, D– single ended

USB 2.0 load conditions

2.8

3.6

VOL

D+, D– single ended

USB 2.0 load conditions

0

0.3

V

Z(DRV)

D+, D– impedance

Including external series resistor of 27 Ω

28

44

Ω

tRISE

Rise time

Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+

4

20

ns

tFALL

Fall time

Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+

4

20

ns

MIN

MAX UNIT

8.51 USB Input Ports DP and DM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(CM)

Differential input common-mode range

0.8

Z(IN)

Input impedance

300

VCRS

Crossover voltage

1.3

VIL

Static SE input logic low level

VIH

Static SE input logic high level

VDI

Differential input voltage

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2.5

V
kΩ

2.0

V

0.8

V

2.0

V
0.2

V

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8.52 USB-PWR (USB Power System)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

VLAUNCH

VBUS detection threshold

VBUS

USB bus voltage

VUSB

USB LDO output voltage

3.3

V18

Internal USB voltage(1)1.8IUSB_EXT

Maximum external current from VUSB terminal(2)IDET

USB LDO current overload detection(3)Normal operation

3.76

USB LDO is on
60
USB LDO is on,
USB PLL disabled

MAX

UNIT

3.75

V

5.5

V

±9%

V

12

mA

100

mA

250

µA

V

ISUSPEND

Operating supply current into VBUS terminal.(4)CBUS

VBUS terminal recommended capacitance

4.7

µF

CUSB

VUSB terminal recommended capacitance

220

nF

C18

V18 terminal recommended capacitance

220

nF

tENABLE

Settling time VUSB and V18

RPUR

Pullup resistance of PUR terminal(5)

(1)
(2)
(3)
(4)
(5)

Within 2%,
recommended capacitances
70

110

2

ms

150

Ω

This voltage is for internal use only. No external DC loading should be applied.
This represents additional current that can be supplied to the application from the VUSB terminal beyond the needs of the USB
operation.
A current overload is detected when the total current supplied from the USB LDO, including IUSB_EXT, exceeds this value.
Does not include current contribution of Rpu and Rpd as outlined in the USB specification.
This value, in series with an external resistor between PUR and D+, produces the Rpu as outlined in the USB specification.

8.53 USB-PLL (USB Phase-Locked Loop)over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IPLL

Operating supply current

fPLL

PLL frequency

fUPD

PLL reference frequencytLOCK

PLL lock time

tJitter

PLL jitter

52

MIN

TYP

UNIT

7

mA

48
1.5
1000

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MAX

MHz
3

MHz

2

ms
ps

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8.54 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER

TJ

DVCC(PGM/ERASE) Program and erase supply voltage

MIN

TYP

1.8

MAX

UNIT

3.6

V

IPGM

Average supply current from DVCC during program

3

5

mA

IERASE

Average supply current from DVCC during erase

6

15

mA

IMERASE, IBANK

Average supply current from DVCC during mass erase or bank erase

6

15

mA

tCPT

Cumulative program time(1)

16

ms

104

Program and erase endurance

cyclestRetention

Data retention duration

tWord

Word or byte program time(2)

64

85

µs

tBlock, 0

Block program time for first byte or word(2)

49

65

µs

tBlock, 1–(N–1)

Block program time for each additional byte or word, except for last byte
or word(2)

37

49

µs

tBlock, N

Block program time for last byte or word(2)

55

73

µs

tSeg Erase

Erase time for segment, mass erase, and bank erase when available(2)

23

32

ms

fMCLK,MGR

MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4.MGR1 = 1)

0

1

MHz

(1)
(2)

25°C

105

100

years

The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
These values are hardwired into the state machine of the flash controller.

8.55 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTESTCONDITIONS

MIN

TYP

MAX

UNIT

fSBW

Spy-Bi-Wire input frequency

2.2 V, 3 V

0

20

MHz

tSBW,Low

Spy-Bi-Wire low clock pulse duration

2.2 V, 3 V

0.025

15

µs

tSBW, En

Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)(1)2.2 V, 3 V

1µstSBW,Rst

Spy-Bi-Wire return to normal operation time

fTCK

TCK input frequency (4-wire JTAG)(2)Rinternal

Internal pulldown resistance on TEST

(1)
(2)

15

100

µs

2.2 V

0

5

MHz

3V

0

10

MHz

2.2 V, 3 V

45

80

kΩ

60

Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying thefirst SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.

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9 Detailed Description
9.1 Overview
The MSP430F563x devices include a high-performance 12-bit ADC, a comparator, two USCIs, USB 2.0, a
hardware multiplier, DMA, four 16-bit timers, an RTC module with alarm capabilities, and up to 74 I/O pins.

9.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constantgenerator, respectively. The remaining registers are general-purpose registers (see 図 9-1).
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be managed withall instructions.
Program Counter

PC/R0

Stack Pointer

SP/R1

Status Register

SR/CG1/R2

Constant Generator

CG2/R3General-Purpose Register

R4

General-Purpose Register

R5

General-Purpose Register

R6

General-Purpose Register

R7

General-Purpose Register

R8

General-Purpose Register

R9

General-Purpose Register

R10

General-Purpose Register

R11

General-Purpose Register

R12

General-Purpose Register

R13

General-Purpose Register

R14

General-Purpose RegisterR15

図 9-1. Integrated CPU Registers

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9.3 Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes andadditional instructions for the expanded address range. Each instruction can operate on word and byte data. 表
9-1 lists examples of the three types of instruction formats; 表 9-2 lists the address modes.
表 9-1. Instruction Word Formats
INSTRUCTION WORD FORMAT

EXAMPLEOPERATION

Dual operands, source-destination

ADD

R4,R5

R4 + R5 → R5

Single operands, destination only

CALL

R8

PC → (TOS), R8 → PC

Relative jump, un/conditional

JNE

Jump-on-equal bit = 0

表 9-2. Address Mode Descriptions(1)

ADDRESS MODE

S(1)

D(1)

SYNTAX

EXAMPLE

Register++

MOV Rs,Rd

MOV R10,R11

R10 → R11

Indexed++MOV X(Rn),Y(Rm)

MOV 2(R5),6(R6)M(2+R5) → M(6+R6)

Symbolic (PC relative)++

MOV EDE,TONI

Absolute++

MOV &MEM, &TCDAT

Indirect+

MOV @Rn,Y(Rm)

MOV @R10,Tab(R6)

M(R10) → M(Tab+R6)

Indirect auto-increment+

MOV @Rn+,Rm

MOV @R10+,R11

M(R10) → R11
R10 + 2 → R10

Immediate+

MOV #X,TONI

MOV #45,TONI#45 → M(TONI)OPERATION

M(EDE) → M(TONI)
M(MEM) → M(TCDAT)

S = source, D = destination

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9.4 Operating Modes
These devices have one active mode and seven software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
Software can configure the following operating modes:
•
•

•

•

•

•

•

•

56

Active mode (AM)– All clocks are active
Low-power mode 0 (LPM0)– CPU is disabled– ACLK and SMCLK remain active, MCLK is disabled– FLL loop control remains active
Low-power mode 1 (LPM1)– CPU is disabled– FLL loop control is disabled– ACLK and SMCLK remain active, MCLK is disabled
Low-power mode 2 (LPM2)– CPU is disabled– MCLK, FLL loop control, and DCOCLK are disabled– DC generator of the DCO remains enabled– ACLK remains active
Low-power mode 3 (LPM3)– CPU is disabled– MCLK, FLL loop control, and DCOCLK are disabled– DC generator of the DCO is disabled– ACLK remains active
Low-power mode 4 (LPM4)– CPU is disabled– ACLK is disabled– MCLK, FLL loop control, and DCOCLK are disabled– DC generator of the DCO is disabled– Crystal oscillator is stopped– Complete data retention
Low-power mode 3.5 (LPM3.5)– Internal regulator disabled– No data retention– RTC enabled and clocked by low-frequency oscillator– Wake-up signal from RST/NMI, RTC_B, P1, P2, P3, and P4
Low-power mode 4.5 (LPM4.5)– Internal regulator disabled– No data retention– Wake-up signal from RST/NMI, P1, P2, P3, and P4

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9.5 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see 表 9-3).
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
表 9-3. Interrupt Sources, Flags, and Vectors of MSP430F563x Configurations
INTERRUPT SOURCEINTERRUPT FLAGSYSTEM INTERRUPTWORDADDRESSPRIORITY

System Reset
Power-Up, External Reset
Watchdog Time-out, Key Violation
Flash Memory Key Violation

WDTIFG, KEYV (SYSRSTIV)(1) (3)Reset

0FFFEh63, highest

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG,VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV)(Non)maskable

0FFFCh62

User NMI
NMI
Oscillator Fault
Flash Memory Access Violation

NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV)(1) (3)(Non)maskable

0FFFAh61

Comp_B

Comparator B interrupt flags (CBIV)(1) (2)Maskable

0FFF8h60

Timer TB0

TB0CCR0 CCIFG0(2)Maskable

0FFF6h59

Timer TB0

TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TBIV)(1) (2)Maskable

0FFF4h58

Watchdog Interval Timer Mode

WDTIFG

Maskable

0FFF2h57

USCI_A0 Receive or Transmit

UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (2)Maskable

0FFF0h56

USCI_B0 Receive or Transmit

UCB0RXIFG, UCB0TXIFG (UCB0IV)(1) (2)Maskable

0FFEEh55

ADC12_A(5)ADC12IFG0 to ADC12IFG15 (ADC12IV)(1) (2)Maskable

0FFECh54

Timer TA0

TA0CCR0 CCIFG0(2)Maskable

0FFEAh53

Timer TA0

TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV)(1) (2)Maskable

0FFE8h52

USB_UBMUSB interrupts (USBIV)(1) (2)Maskable

0FFE6h51

DMA

DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG, DMA4IFG,DMA5IFG (DMAIV)(1) (2)Maskable

0FFE4h50

Timer TA1

TA1CCR0 CCIFG0(2)Maskable

0FFE2h49

Timer TA1

TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV)(1) (2)Maskable

0FFE0h48

I/O Port P1

P1IFG.0 to P1IFG.7 (P1IV)(1) (2)Maskable

0FFDEh47

USCI_A1 Receive or Transmit

UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (2)Maskable

0FFDCh46

USCI_B1 Receive or Transmit

UCB1RXIFG, UCB1TXIFG (UCB1IV)(1) (2)Maskable0FFDAh45

I/O Port P2

P2IFG.0 to P2IFG.7 (P2IV)(1) (2)Maskable

0FFD8h44

Reserved

Reserved

Maskable

0FFD6h43

RTC_B

RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG,
RT1PSIFG, RTCOFIFG (RTCIV)(1) (2)Maskable

0FFD4h42

DAC12_A(6)DAC12_0IFG, DAC12_1IFG(1) (2)Maskable

0FFD2h41

Timer TA2

TA2CCR0 CCIFG0(2)Maskable

0FFD0h40

Timer TA2

TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV)(1) (2)Maskable

0FFCEh39

I/O Port P3

P3IFG.0 to P3IFG.7 (P3IV)(1) (2)Maskable

0FFCCh38

I/O Port P4

P4IFG.0 to P4IFG.7 (P4IV)(1) (2)Maskable

0FFCAh37

0FFC8h36

System NMI
PMM
Vacant Memory Access
JTAG Mailbox(1)

Reserved

(1)
(2)
(3)
(4)

Reserved(4)⋮⋮0FF80h0, lowest

Multiple source flags
Interrupt flags are in the module.
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To
maintain compatibility with other devices, TI recommends reserving these locations.

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(5)
(6)

Only on devices with peripheral module ADC12_A, otherwise reserved.
Only on devices with peripheral module DAC12_A, otherwise reserved.

9.6 Memory
表 9-4 summarizes the memory map for all device variants.
表 9-4. Memory Organization
MSP430F5636
MSP430F5633
MSP430F5630

MSP430F5637
MSP430F5634
MSP430F5631

MSP430F5638
MSP430F5635
MSP430F5632

Total Size

128KB
00FFFFh to 00FF80h

192KB
00FFFFh to 00FF80h

256KB
00FFFFh to 00FF80h

Bank 3

N/A

N/A

64KB
047FFFh to 038000h

Bank 2

N/A

64KB
037FFFh to 028000h

64KB
037FFFh to 028000h

Bank 164KB
027FFFh to 018000h

64KB
027FFFh to 018000h

64KB
027FFFh to 018000h

Bank 064KB017FFFh to 008000h

64KB
017FFFh to 008000h

64KB
017FFFh to 008000h

Sector 3

4KB
0063FFh to 005400h

4KB
0063FFh to 005400h

4KB
0063FFh to 005400h

Sector 2

4KB
0053FFh to 004400h

4KB
0053FFh to 004400h

4KB
0053FFh to 004400h

Sector 1

4KB
0043FFh to 003400h

4KB
0043FFh to 003400h

4KB
0043FFh to 003400h

Sector 0

4KB
0033FFh to 002400h

4KB
0033FFh to 002400h

4KB
0033FFh to 002400h

Size
RAM

2KB
0023FFh to 001C00h

2KB
0023FFh to 001C00h

2KB
0023FFh to 001C00h

Info A128 bytes
0019FFh to 001980h

128 bytes
0019FFh to 001980h

128 bytes
0019FFh to 001980hInfo B

128 bytes
00197Fh to 001900h

128 bytes
00197Fh to 001900h

128 bytes
00197Fh to 001900h

Info C

128 bytes
0018FFh to 001880h

128 bytes
0018FFh to 001880h

128 bytes
0018FFh to 001880hInfo D

128 bytes
00187Fh to 001800h

128 bytes
00187Fh to 001800h

128 bytes
00187Fh to 001800h

BSL 3

512 bytes
0017FFh to 001600h

512 bytes
0017FFh to 001600h

512 bytes
0017FFh to 001600h

BSL 2

512 bytes
0015FFh to 001400h

512 bytes
0015FFh to 001400h

512 bytes
0015FFh to 001400h

BSL 1

512 bytes
0013FFh to 001200h

512 bytes
0013FFh to 001200h

512 bytes
0013FFh to 001200h

BSL 0

512 bytes
0011FFh to 001000h

512 bytes
0011FFh to 001000h

512 bytes
0011FFh to 001000h

Size

4KB
000FFFh to 000000h

4KB
000FFFh to 000000h

4KB
000FFFh to 000000h(1) (3)

Memory (flash)
Main: interrupt vector

Main: code memory

RAM

USB RAM(2)Information memory(flash)Bootloader (BSL)
memory (flash)

Peripherals
(1)
(2)
(3)

N/A = Not available.
USB RAM can be used as general-purpose RAM when not used for USB operation.
Backup RAM is accessed through the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.

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9.7 Bootloader (BSL)
The BSL lets users program the flash memory or RAM using various serial interfaces. Access to the device
memory by the BSL is protected by an user-defined password. For complete description of the features of the
BSL and its implementation, see MSP430™ Flash Devices Bootloader (BSL) User's Guide.
9.7.1 USB BSL
All devices come preprogrammed with the USB BSL. Use of the USB BSL requires external access to six pins(see 表 9-5). In addition to these pins, the application must support external components necessary for normal
USB operation; for example, the proper crystal on XT2IN and XT2OUT or proper decoupling.
表 9-5. USB BSL Pin Requirements and Functions
DEVICE SIGNALBSL FUNCTION

RST/NMI/SBWTDIO

Entry sequence signal

PU.0/DPUSB data terminal DP

PU.1/DM

USB data terminal DM

PUR

USB pullup resistor terminal

VBUS

USB bus power supply

VSSU

USB ground supply

Note
The default USB BSL evaluates the logic level of the PUR pin after a BOR reset. If the PUR pin ispulled high externally, the BSL is invoked. Therefore, unless the application is invoking the BSL, it isimportant to keep PUR pulled low after a BOR reset, even if BSL or USB is never used. TI
recommends applying a 1-MΩ resistor to ground.
9.7.2 UART BSL
A UART BSL is also available that can be programmed by the user into the BSL memory by replacing the
preprogrammed, factory supplied, USB BSL. Use of the UART BSL requires external access to six pins (see 表9-6).
表 9-6. UART BSL Pin Requirements and Functions
DEVICE SIGNALBSL FUNCTION

RST/NMI/SBWTDIO

Entry sequence signal

TEST/SBWTCK

Entry sequence signal

P1.1

Data transmit

P1.2

Data receive

VCC

Power supply

VSS

Ground supply

9.8 JTAG Operation
9.8.1 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. 表 9-7 lists the JTAG pin requirements. For further details oninterfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For acomplete description of the features of the JTAG interface and its implementation, see MSP430 Programming
With the JTAG Interface.

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表 9-7. JTAG Pin Requirements and Functions
DEVICE SIGNAL

DIRECTIONFUNCTION

PJ.3/TCKIN

JTAG clock input

PJ.2/TMSIN

JTAG state control

PJ.1/TDI/TCLKIN

JTAG data input, TCLK input

PJ.0/TDOOUTJTAG data output

TEST/SBWTCKIN

Enable JTAG pins

RST/NMI/SBWTDIO

IN

External reset

VCC

Power supply

VSS

Ground supply

9.8.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. SpyBi-Wire can be used to interface with MSP430 development tools and device programmers. 表 9-8 lists the SpyBi-Wire interface pin requirements. For further details on interfacing to development tools and device
programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the
JTAG interface and its implementation, see MSP430 Programming With the JTAG Interface.
表 9-8. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL

DIRECTIONFUNCTION

TEST/SBWTCKIN

Spy-Bi-Wire clock input

RST/NMI/SBWTDIO

IN, OUT

Spy-Bi-Wire data input/output

VCC

Power supply

VSS

Ground supply

9.9 Flash Memory
The flash memory can be programmed by the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by theCPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:••••

Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also
called information memory.
Segment A can be locked separately.

9.10 RAMThe RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however, alldata is lost. Features of the RAM include:••••

RAM has n sectors. The size of a sector can be found in セクション 9.6.
Each sector 0 to n can be complete disabled; however, data retention is lost.
Each sector 0 to n automatically enters low power retention mode when possible.
For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.

9.11 Backup RAM
The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during
operation from a backup supply if the Battery Backup System module is implemented.
Eight bytes of backup RAM are available. The backup RAM can be wordwise accessed by the control registers
BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.

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9.12 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be managed
using all instructions. For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's
Guide.
9.12.1 Digital I/O
Up to nine 8-bit I/O ports are implemented: P1 through P6, P8, and P9 are complete, P7 contains six individual
I/O ports, and PJ contains four individual I/O ports.
•
•
•
•
•
•
•

All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown on all ports.
Programmable drive strength on all ports.
All eight bits of ports P1, P2, P3, and P4 support edge-selectable interrupt input.
All instructions support read and write access to port-control registers.
Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PD).

9.12.2 Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2. 表 9-9
lists the mnemonic for each function that can be assigned.
表 9-9. Port Mapping Mnemonics and Functions
VALUE

PxMAPy MNEMONICINPUT PIN FUNCTIONOUTPUT PIN FUNCTION0

PM_NONE

None

DVSS

PM_CBOUT–

Comparator_B output

PM_TB0CLK

Timer TB0 clock input–

PM_ADC12CLK–ADC12CLK

PM_DMAE0

DMAE0 Input–

PM_SVMOUT–

SVM output

PM_TB0OUTH

Timer TB0 high-impedance input
TB0OUTH–

4

PM_TB0CCR0B

Timer TB0 CCR0 capture input CCI0B

Timer TB0: TB0.0 compare output Out05

PM_TB0CCR1B

Timer TB0 CCR1 capture input CCI1B

Timer TB0: TB0.1 compare output Out1

6

PM_TB0CCR2B

Timer TB0 CCR2 capture input CCI2B

Timer TB0: TB0.2 compare output Out2

7

PM_TB0CCR3B

Timer TB0 CCR3 capture input CCI3B

Timer TB0: TB0.3 compare output Out3

8

PM_TB0CCR4B

Timer TB0 CCR4 capture input CCI4B

Timer TB0: TB0.4 compare output Out4

9

PM_TB0CCR5B

Timer TB0 CCR5 capture input CCI5B

Timer TB0: TB0.5 compare output Out5

10

PM_TB0CCR6B

Timer TB0 CCR6 capture input CCI6B

Timer TB0: TB0.6 compare output Out6

1
2

3

11
12
13
14
15
16
17

PM_UCA0RXD

USCI_A0 UART RXD (Direction controlled by USCI – input)

PM_UCA0SOMIUSCI_A0 SPI slave out master in (direction controlled by USCI)PM_UCA0TXD

USCI_A0 UART TXD (Direction controlled by USCI – output)

PM_UCA0SIMO

USCI_A0 SPI slave in master out (direction controlled by USCI)PM_UCA0CLKUSCI_A0 clock input/output (direction controlled by USCI)PM_UCB0STE

USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)

PM_UCB0SOMIUSCI_B0 SPI slave out master in (direction controlled by USCI)PM_UCB0SCLUSCI_B0 I2C clock (open drain and direction controlled by USCI)PM_UCB0SIMO

USCI_B0 SPI slave in master out (direction controlled by USCI)PM_UCB0SDA

USCI_B0 I2C data (open drain and direction controlled by USCI)PM_UCB0CLKUSCI_B0 clock input/output (direction controlled by USCI)PM_UCA0STE

USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)

PM_MCLK

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表 9-9. Port Mapping Mnemonics and Functions (continued)
VALUE

PxMAPy MNEMONIC

18

Reserved

Reserved for test purposes. Do not use this setting.

19

Reserved

Reserved for test purposes. Do not use this setting.

20–30

Reserved

31 (0FFh)(1)(1)

INPUT PIN FUNCTIONNone

OUTPUT PIN FUNCTIONDVSSDisables the output driver and the input Schmitt-trigger to prevent parasitic cross currents
when applying analog signals.

PM_ANALOG

The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are 5 bits wide, and the upper bits are ignored,
which results in a maximum value of 31.

表 9-10 lists the default values for all pins that support port mapping.
表 9-10. Default Mapping
PIN

PxMAPyMNEMONIC

P2.0/P2MAP0

PM_UCB0STE,
PM_UCA0CLKUSCI_B0 SPI slave transmit enable (direction controlled by USCI – input),
USCI_A0 clock input/output (direction controlled by USCI)

P2.1/P2MAP1

PM_UCB0SIMO,
PM_UCB0SDA

USCI_B0 SPI slave in master out (direction controlled by USCI),USCI_B0 I2C data (open drain and direction controlled by USCI)

P2.2/P2MAP2

PM_UCB0SOMI,
PM_UCB0SCLUSCI_B0 SPI slave out master in (direction controlled by USCI),USCI_B0 I2C clock (open drain and direction controlled by USCI)

P2.3/P2MAP3

PM_UCB0CLK,
PM_UCA0STE

USCI_B0 clock input/output (direction controlled by USCI),USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)

P2.4/P2MAP4

PM_UCA0TXD,
PM_UCA0SIMO

USCI_A0 UART TXD (direction controlled by USCI – output),
USCI_A0 SPI slave in master out (direction controlled by USCI)

P2.5/P2MAP5

PM_UCA0RXD,
PM_UCA0SOMIUSCI_A0 UART RXD (direction controlled by USCI – input),
USCI_A0 SPI slave out master in (direction controlled by USCI)

P2.6/P2MAP6

PM_NONE–

DVSS

P2.7/P2MAP7

PM_NONE–DVSSINPUT PIN FUNCTIONOUTPUT PIN FUNCTION

9.12.3 Oscillator and System Clock
The clock system is supported by the Unified Clock System (UCS) module that includes support for a 32-kHz
watch crystal oscillator (in XT1 LF mode; XT1 HF mode is not supported), an internal very-low-power lowfrequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitallycontrolled oscillator (DCO), and a high-frequency crystal oscillator XT2. The UCS module is designed to meetthe requirements of both low system cost and low power consumption. The UCS module features digitalfrequency-locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency
to a programmable multiple of the watch-crystal frequency. The internal DCO provides a fast turnon clock sourceand stabilizes in 3 µs (typical). The UCS module provides the following clock signals:••••

Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), theinternal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitallycontrolled oscillator DCO.
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources available to
ACLK.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced bysame sources available to ACLK.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

9.12.4 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS
and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
9.12.5 Hardware Multiplier (MPY) (Link to User's Guide)The multiplication operation is supported by a dedicated peripheral module. The module performs operations
with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed
and unsigned multiply-and-accumulate operations.
9.12.6 Real-Time Clock (RTC_B)
The RTC_B module can be configured for real-time clock (RTC) or calendar mode providing seconds, minutes,
hours, day of week, day of month, month, and year. Calendar mode integrates an internal calendar which
compensates for months with less than 31 days and includes leap year correction. The RTC_B also supports
flexible alarm functions and offset-calibration hardware. The implementation on this device supports operation in
LPM3.5 mode and operation from a backup supply.
Using the MSP430 RTC_B Module With Battery Backup Supply describes how to use the RTC_B with battery
backup supply functionality to retain the time and keep the RTC counting through loss of main power supply, andhow to perform correct reinitialization when the main power supply is restored.
9.12.7 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not neededin an application, the module can be configured as an interval timer and can generate interrupts at selected timeintervals.

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9.12.8 System Module (SYS)The SYS module handles many of the system functions within the device. These include power-on reset andpower-up clear handling, NMI source selection and management, reset interrupt vector generators, bootloader
entry mechanisms, and configuration management (device descriptors). SYS also includes a data exchangemechanism through JTAG called a JTAG mailbox that can be used in the application.
表 9-11 lists the SYS interrupt vector registers.
表 9-11. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTERSYSRSTIV, System Reset

INTERRUPT EVENT

WORD ADDRESS

00hBrownout (BOR)02h

RST/NMI (BOR)

04h

PMMSWBOR (BOR)

06h

LPM3.5 or LPM4.5 wakeup (BOR)

08h

Security violation (BOR)

0Ah

SVSL (POR)

0Ch

SVSH (POR)

0Eh

SVML_OVP (POR)
SVMH_OVP (POR)

019Eh

SYSUNIV, User NMI

14h
16h

WDT key violation (PUC)18h

KEYV flash key violation (PUC)

1Ah

Reserved

1Ch

Peripheral area fetch (PUC)

1Eh

PMM key violation (PUC)

20h

Reserved

22h to 3Eh

No interrupt pending

00h

SVMLIFG02h

SVMHIFG04h

DLYLIFG

06h

SYSBERRIV, Bus Error

0Ch
0Eh

SVMLVLRIFG

10h

SVMHVLRIFG

12h

Reserved

14h to 1Eh

No interrupt pending

00h

NMIIFG

02h

OFIFG

04h

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019Ah

08h

Reserved

0Ah to 1Eh

No interrupt pending

00h
0198h

LowestHighest06h

BUSIFG

Reserved

Highest0Ah

JMBINIFG

USB wait state time-out

Lowest08h
019Ch

JMBOUTIFGACCVIFG

Highest12h

PMMSWPOR (POR)

VMAIFGPRIORITY

10h

WDT time-out (PUC)DLYHIFGSYSSNIV, System NMI

OFFSETNo interrupt pending

Lowest02hHighest04h to 1Eh

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9.12.9 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM.
Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces
system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to movedata to or from a peripheral. 表 9-12 lists the trigger assignments for each DMA channel.
The USB timestamp generator also uses the channel 0, 1, and 2 DMA trigger assignments.
表 9-12. DMA Trigger Assignments
TRIGGER(1)CHANNEL
0

1

DMAREQ

1

TA0CCR0 CCIFG

2

TA0CCR2 CCIFG

3

TA1CCR0 CCIFG

4

TA1CCR2 CCIFG

5

TA2CCR0 CCIFG

6

TA2CCR2 CCIFG

7

TBCCR0 CCIFG

8

TBCCR2 CCIFG

9

Reserved

10

Reserved

11

Reserved

12

Reserved

13

Reserved

14

Reserved

15

Reserved

16

UCA0RXIFG

17

UCA0TXIFG

18

UCB0RXIFG

19

UCB0TXIFG

20

UCA1RXIFG

21

UCA1TXIFG

22

UCB1RXIFG

23

UCB1TXIFG24

ADC12IFGx(2)25

DAC12_0IFG(3)26DAC12_1IFG(3)27

USB FNRXD

28

USB ready

30

4

5

DMA3IFGDMA4IFGMPY ready
DMA5IFG

31

(2)
(3)

3

0

29

(1)

2

DMA0IFGDMA1IFGDMA2IFGDMAE0Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers will notcause any DMA trigger event when selected.
Only on devices with peripheral module ADC12_A. Reserved on devices without ADC.
Only on devices with peripheral module DAC12_A. Reserved on devices without DAC.

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9.12.10 Universal Serial Communication Interface (USCI)The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions,
A and B.
The USCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3 or 4 pin) or I2C.
The MSP430F563x series includes two complete USCI modules (n = 0 or 1).
9.12.11 Timer TA0
Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple
capture/compares, PWM outputs, and interval timing (see 表 9-13). TA0 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each capture/compare register.
表 9-13. Timer TA0 Signal Connections
INPUT PIN NUMBER
PZ

ZCA, ZQWDEVICE
INPUT
SIGNAL

MODULE
INPUT
SIGNAL34-P1.0

L5-P1.0

TA0CLK

TACLK

ACLK

ACLK

SMCLK

SMCLK

34-P1.0

L5-P1.0

TA0CLK

TACLK

35-P1.1

M5-P1.1

TA0.0

CCI0A

DVSS

CCI0B

DVSS

GND

DVCC

VCC

MODULEBLOCK

MODULEOUTPUT
SIGNALDEVICEOUTPUT
SIGNAL

Timer

NA

NA

CCR0

TA0

OUTPUT PIN NUMBER
PZ

ZCA, ZQW

35-P1.1

M5-P1.1

TA0.0

36-P1.2

J6-P1.2

TA0.1

CCI1A

36-P1.2

J6-P1.2

40-P1.6

J7-P1.6

TA0.1

CCI1B

40-P1.6

J7-P1.6

DVSS

GND

DVCC

VCC

37-P1.3

H6-P1.3

TA0.2

CCI2A

41-P1.7

M7-P1.7

TA0.2

CCI2B

DVSS

GND

38-P1.4

39-P1.5

M6-P1.4

L6-P1.5

DVCC

VCC

TA0.3

CCI3A

DVSS

CCI3B

DVSS

GND

DVCC

VCC

TA0.4

CCI4A

DVSS

CCI4B

DVSS

GND

DVCC

VCC

(1)

Only on devices with peripheral module ADC12_A.

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CCR1

CCR2

CCR3

CCR4

TA1

TA2

TA3

TA4

TA0.1

TA0.2

ADC12_A (internal)(1)
ADC12SHSx = {1}37-P1.3

H6-P1.3

41-P1.7

M7-P1.7

38-P1.4

M6-P1.4

39-P1.5

L6-P1.5

TA0.3

TA0.4

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9.12.12 Timer TA1
Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 supports multiple
capture/compares, PWM outputs, and interval timing (see 表 9-14). TA1 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each capture/compare register.
表 9-14. Timer TA1 Signal Connections
INPUT PIN NUMBER
PZ

ZCA, ZQWDEVICE
INPUT
SIGNAL42-P3.0

L7-P3.0

TA1CLK

TACLK

ACLK

ACLK

SMCLK

SMCLK

42-P3.0

L7-P3.0

TA1CLKTACLK

43-P3.1

H7-P3.1

TA1.0

CCI0A

DVSS

CCI0B

DVSS

GND

44-P3.2

45-P3.3(1)

MODULE
INPUT
SIGNAL

M8-P3.2

L8-P3.3

MODULEBLOCK

MODULEOUTPUT
SIGNALDEVICEOUTPUT
SIGNAL

Timer

NA

NA

CCR0

TA0

OUTPUT PIN NUMBER
PZ

ZCA, ZQW

43-P3.1

H7-P3.1

M8-P3.2

TA1.0

DVCC

VCC

TA1.1

CCI1A

44-P3.2

CBOUT(internal)

CCI1B

DAC12_A(1)DAC12_0, DAC12_1(internal)

DVSS

GND

DVCC

VCC

TA1.2

CCI2A

ACLK
(internal)

CCI2B

DVSS

GND

DVCC

VCC

CCR1

TA1

TA1.1

45-P3.3
CCR2

TA2

L8-P3.3

TA1.2

Only on devices with peripheral module DAC12_A.

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9.12.13 Timer TA2
Timer TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA2 supports multiple
capture/compares, PWM outputs, and interval timing (see 表 9-15). TA2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each capture/compare register.
表 9-15. Timer TA2 Signal Connections
INPUT PIN NUMBER
PZ

ZCA, ZQWDEVICE
INPUT
SIGNAL46-P3.4

J8-P3.4

TA2CLK

TACLK

ACLK

ACLK

SMCLK

SMCLK

46-P3.4

J8-P3.4

TA2CLK

TACLK

47-P3.5

M9-P3.5

TA2.0

CCI0A

DVSS

CCI0B

DVSS

GND

48-P3.6

49-P3.7

68

MODULE
INPUT
SIGNAL

DVCC

VCC

TA2.1

CCI1A

CBOUT
(internal)

CCI1B

DVSS

GND

DVCC

VCC

L9-P3.6

M10-P3.7

TA2.2

CCI2A

ACLK
(internal)

CCI2B

DVSS

GND

DVCC

VCC

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MODULEBLOCK

MODULEOUTPUT
SIGNALDEVICEOUTPUT
SIGNAL

Timer

NA

NA

CCR0

CCR1

CCR2

TA0

TA1

TA2

OUTPUT PIN NUMBER
PZ

ZCA, ZQW

47-P3.5

M9-P3.5

48-P3.6

L9-P3.6

49-P3.7

M10-P3.7

TA2.0

TA2.1

TA2.2

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

9.12.14 Timer TB0
Timer TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 supports multiple
capture/compares, PWM outputs, and interval timing (see 表 9-16). TB0 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each capture/compare register.
表 9-16. Timer TB0 Signal Connections
INPUT PIN NUMBER
PZ

ZCA, ZQW

58-P8.0
P2MAPx(3)J11-P8.0
P2MAPx(3)DEVICE
INPUT
SIGNAL

MODULE
INPUT
SIGNAL

TB0CLK

TB0CLK

ACLK

ACLK

SMCLK

SMCLK

MODULEBLOCK

MODULEOUTPUT
SIGNALDEVICEOUTPUT
SIGNAL

Timer

NA

NA

OUTPUT PIN NUMBER
PZ

ZCA, ZQW

58-P8.0
P2MAPx(3)J11-P8.0
P2MAPx(3)TB0CLK

TB0CLK

50-P4.0

J9-P4.0

TB0.0

CCI0A

50-P4.0

J9-P4.0

P2MAPx(3)P2MAPx(3)

TB0.0

CCI0B

P2MAPx(3)P2MAPx(3)

DVSS

GND

51-P4.1

M11-P4.1

P2MAPx(3)P2MAPx(3)

CCR0

TB0

TB0.0

ADC12 (internal) (1)
ADC12SHSx = {2}

DVCC

VCC

TB0.1

CCI1A

51-P4.1

M11-P4.1

TB0.1

CCI1B

P2MAPx(3)P2MAPx(3)

DVSS

GND

DVCC

VCC

CCR1

TB1

TB0.1

ADC12 (internal) (1)
ADC12SHSx = {3}52-P4.2

L10-P4.2

TB0.2

CCI2A

52-P4.2

L10-P4.2

P2MAPx(3)P2MAPx(3)

TB0.2

CCI2B

P2MAPx(3)P2MAPx(3)

DVSS

GND

53-P4.3

M12-P4.3

P2MAPx(3)P2MAPx(3)54-P4.4

L12-P4.4

P2MAPx(3)P2MAPx(3)55-P4.5

L11-P4.5

P2MAPx(3)P2MAPx(3)56-P4.6

K11-P4.6

P2MAPx(3)P2MAPx(3)

(1)
(2)
(3)

CCR2

TB2

TB0.2

DAC12_A(2) (internal)
DAC12_0, DAC12_1

DVCC

VCC

TB0.3

CCI3A

53-P4.3

M12-P4.3

TB0.3

CCI3B

P2MAPx(3)P2MAPx(3)

DVSS

GND

CCR3

TB3

TB0.3

DVCC

VCC

TB0.4

CCI4A

54-P4.4

L12-P4.4

TB0.4

CCI4B

P2MAPx(3)P2MAPx(3)

DVSS

GND

CCR4

TB4

TB0.4

DVCC

VCC

TB0.5

CCI5A

55-P4.5

L11-P4.5

TB0.5

CCI5B

P2MAPx(3)P2MAPx(3)

DVSS

GND

CCR5

TB5

TB0.5

DVCC

VCC

TB0.6

CCI6A

56-P4.6

K11-P4.6

TB0.6

CCI6B

P2MAPx(3)P2MAPx(3)

DVSS

GND

DVCC

VCC

CCR6

TB6

TB0.6

Only on devices with peripheral module ADC12_A.
Only on devices with peripheral module DAC12_A.
Timer functions selectable by the port mapping controller.

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

9.12.15 Comparator_B
The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,battery voltage supervision, and monitoring of external analog signals.
9.12.16 ADC12_A
The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversionand-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPUintervention.
The DAC12_A module is a 12-bit R-ladder voltage-output DAC. The DAC12_A may be used in 8-bit or 12-bit
mode, and may be used with the DMA controller. When multiple DAC12_A modules are present, they may begrouped together for synchronous operation.
9.12.18 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
9.12.19 Voltage Reference (REF) Module
The REF module generates all of the critical reference voltages that can be used by the various analog
peripherals in the device.
9.12.20 USB Universal Serial Bus
The USB module is a fully integrated USB interface that is compliant with the USB 2.0 specification. The module
supports full-speed operation of control, interrupt, and bulk transfers. The module includes an integrated LDO,
PHY, and PLL. The PLL is highly flexible and can support a wide range of input clock frequencies. USB RAM,
when not used for USB communication, can be used by the system.
9.12.21 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The L version of the EEM has the following features:
•
•
•
•
•
•
•

70

Eight hardware triggers or breakpoints on memory accessTwo hardware triggers or breakpoints on CPU register write access
Up to 10 hardware triggers can be combined to form complex triggers or breakpoints
Two cycle counters
Sequencer
State storage
Clock control on module level

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

9.12.22 Peripheral File Map
表 9-17 lists the register base address for all of the available peripheral modules.
表 9-17. Peripherals(1)

MODULE NAMEBASE ADDRESSOFFSET ADDRESS RANGE(1)Special Functions (see 表 9-18)0100h

000h to 01Fh

PMM (see 表 9-19)0120h000h to 010h

Flash Control (see 表 9-20)0140h000h to 00Fh

CRC16 (see 表 9-21)0150h000h to 007h

RAM Control (see 表 9-22)0158h000h to 001h

Watchdog (see 表 9-23)015Ch000h to 001h

UCS (see 表 9-24)0160h000h to 01Fh

SYS (see 表 9-25)0180h000h to 01Fh

Shared Reference (see 表 9-26)01B0h000h to 001h

Port Mapping Control (see 表 9-27)01C0h000h to 003h

Port Mapping Port P2 (see 表 9-27)

01D0h

000h to 007h

Port P1, P2 (see 表 9-28)0200h

000h to 01Fh

Port P3, P4 (see 表 9-29)0220h000h to 01Fh

Port P5, P6 (see 表 9-30)0240h000h to 00Bh

Port P7, P8 (see 表 9-31)0260h000h to 00Bh

Port P9 (see 表 9-32)0280h000h to 00Bh

Port PJ (see 表 9-33)

0320h

000h to 01Fh

Timer TA0 (see 表 9-34)0340h000h to 02Eh

Timer TA1 (see 表 9-35)0380h000h to 02Eh

Timer TB0 (see 表 9-36)

03C0h

000h to 02Eh

Timer TA2 (see 表 9-37)0400h

000h to 02Eh

Battery Backup (see 表 9-38)0480h000h to 01Fh

RTC_B (see 表 9-39)04A0h

000h to 01Fh

32-bit Hardware Multiplier (see 表 9-40)

04C0h

000h to 02Fh

DMA General Control (see 表 9-41)0500h

000h to 00FhDMA Channel 0 (see 表 9-41)0510h

000h to 00Ah

DMA Channel 1 (see 表 9-41)0520h

000h to 00Ah

DMA Channel 2 (see 表 9-41)0530h000h to 00Ah

DMA Channel 3 (see 表 9-41)0540h000h to 00Ah

DMA Channel 4 (see 表 9-41)0550h

000h to 00Ah

DMA Channel 5 (see 表 9-41)0560h

000h to 00Ah

USCI_A0 (see 表 9-42)05C0h000h to 01Fh

USCI_B0 (see 表 9-43)05E0h000h to 01Fh

USCI_A1 (see 表 9-44)0600h

000h to 01Fh

USCI_B1 (see 表 9-45)0620h

000h to 01Fh

ADC12_A (see 表 9-46)0700h

000h to 03Fh

DAC12_A (see 表 9-47)0780h000h to 01Fh
000h to 00Fh

Comparator_B (see 表 9-48)

08C0h

USB configuration (see 表 9-49)

0900h

000h to 014h

USB control (see 表 9-50)

0920h000h to 01Fh

For a detailed description of the individual control register offset addresses, see the MSP430F5xx and MSP430F6xx Family User's
Guide.

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

表 9-18. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTIONREGISTEROFFSETSFR interrupt enable

SFRIE100h

SFR interrupt flag

SFRIFG102h

SFR reset pin control

SFRRPCR04h

表 9-19. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTIONREGISTEROFFSET

PMM control 0

PMMCTL000h

PMM control 1

PMMCTL102h

SVS high-side control

SVSMHCTL

04h

SVS low-side control

SVSMLCTL

06h

PMM interrupt flags

PMMIFG0Ch

PMM interrupt enable

PMMIE

0Eh

PMM power mode 5 control

PM5CTL010h

表 9-20. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTIONREGISTEROFFSET

Flash control 1

FCTL1

00h

Flash control 3

FCTL3

04h

Flash control 4

FCTL4

06h

表 9-21. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTIONREGISTEROFFSET

CRC data input

CRC16DI00h

CRC result

CRC16INIRES04h

表 9-22. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM control 0

REGISTERRCCTL0OFFSET00h

表 9-23. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control

REGISTERWDTCTLOFFSET00h

表 9-24. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTIONREGISTEROFFSETUCS control 0

UCSCTL000h

UCS control 1

UCSCTL102h

UCS control 2

UCSCTL204h

UCS control 3

UCSCTL306h

UCS control 4

UCSCTL408h

UCS control 5

UCSCTL50Ah

UCS control 6

UCSCTL60Ch

UCS control 7

UCSCTL70Eh

UCS control 8

UCSCTL810h

表 9-25. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
System control
72

REGISTERSYSCTL

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OFFSET
00h

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

表 9-25. SYS Registers (Base Address: 0180h) (continued)
REGISTER DESCRIPTIONREGISTEROFFSET

Bootloader configuration area

SYSBSLC

02h

JTAG mailbox control

SYSJMBC

06h

JTAG mailbox input 0

SYSJMBI008h

JTAG mailbox input 1

SYSJMBI1

0Ah

JTAG mailbox output 0

SYSJMBO00Ch

JTAG mailbox output 1

SYSJMBO1

0Eh

Bus error vector generator

SYSBERRIV

18h

User NMI vector generator

SYSUNIV

1Ah

System NMI vector generator

SYSSNIV

1Ch

Reset vector generator

SYSRSTIV1Eh

表 9-26. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control

REGISTEROFFSET

REFCTL00h

表 9-27. Port Mapping Registers(Base Address of Port Mapping Control: 01C0h, Port P2: 01D0h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port mapping password

PMAPPWD

00h

Port mapping control

PMAPCTL

02h

Port P2.0 mapping

P2MAP000h

Port P2.1 mapping

P2MAP101h

Port P2.2 mapping

P2MAP202h

Port P2.3 mapping

P2MAP303hPort P2.4 mapping

P2MAP404h

Port P2.5 mapping

P2MAP505h

Port P2.6 mapping

P2MAP606h

Port P2.7 mapping

P2MAP707h

表 9-28. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P1 input

P1IN

00h

Port P1 output

P1OUT

02h

Port P1 direction

P1DIR

04h

Port P1 pullup/pulldown enable

P1REN

06h

Port P1 drive strength

P1DS

08h

Port P1 selection

P1SEL

0Ah

Port P1 interrupt vector word

P1IV

0Eh

Port P1 interrupt edge select

P1IES

18h

Port P1 interrupt enable

P1IE

1Ah

Port P1 interrupt flag

P1IFG

1Ch

Port P2 input

P2IN

01h

Port P2 output

P2OUT

03h

Port P2 direction

P2DIR

05h

Port P2 pullup/pulldown enable

P2REN

07h

Port P2 drive strength

P2DS

09h

Port P2 selection

P2SEL

0Bh

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

表 9-28. Port P1, P2 Registers (Base Address: 0200h) (continued)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P2 interrupt vector word

P2IV

1Eh

Port P2 interrupt edge select

P2IES

19h

Port P2 interrupt enable

P2IE

1Bh

Port P2 interrupt flag

P2IFG

1Dh

表 9-29. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P3 input

P3IN

00h

Port P3 output

P3OUT

02h

Port P3 direction

P3DIR

04h

Port P3 pullup/pulldown enable

P3REN

06h

Port P3 drive strength

P3DS

08h

Port P3 selection

P3SEL

0Ah

Port P3 interrupt vector word

P3IV

0Eh

Port P3 interrupt edge select

P3IES

18h

Port P3 interrupt enable

P3IE

1Ah

Port P3 interrupt flag

P3IFG

1Ch

Port P4 input

P4IN

01h

Port P4 output

P4OUT

03h

Port P4 direction

P4DIR

05h

Port P4 pullup/pulldown enable

P4REN

07h

Port P4 drive strength

P4DS

09h

Port P4 selection

P4SEL

0Bh

Port P4 interrupt vector word

P4IV

1Eh

Port P4 interrupt edge select

P4IES

19h

Port P4 interrupt enable

P4IE

1Bh

Port P4 interrupt flag

P4IFG

1Dh

表 9-30. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P5 input

P5IN

00h

Port P5 output

P5OUT

02h

Port P5 direction

P5DIR

04h

Port P5 pullup/pulldown enable

P5REN

06h

Port P5 drive strength

P5DS

08h

Port P5 selection

P5SEL

0Ah

Port P6 input

P6IN

01h

Port P6 output

P6OUT

03h

Port P6 direction

P6DIR

05h

Port P6 pullup/pulldown enable

P6REN

07h

Port P6 drive strength

P6DS

09h

Port P6 selection

P6SEL

0Bh

表 9-31. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTIONPort P7 input

74

REGISTER
P7IN

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OFFSET
00h

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表 9-31. Port P7, P8 Registers (Base Address: 0260h) (continued)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P7 output

P7OUT

02h

Port P7 direction

P7DIR

04h

Port P7 pullup/pulldown enable

P7REN

06h

Port P7 drive strength

P7DS

08h

Port P7 selection

P7SEL

0Ah

Port P8 input

P8IN

01h

Port P8 output

P8OUT

03h

Port P8 direction

P8DIR

05h

Port P8 pullup/pulldown enable

P8REN

07h

Port P8 drive strength

P8DS

09h

Port P8 selection

P8SEL

0Bh

表 9-32. Port P9 Register (Base Address: 0280h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P9 input

P9IN

00h

Port P9 output

P9OUT

02h

Port P9 direction

P9DIR

04h

Port P9 pullup/pulldown enable

P9REN

06h

Port P9 drive strength

P9DS

08h

Port P9 selection

P9SEL

0Ah

表 9-33. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port PJ input

PJIN

00h

Port PJ output

PJOUT

02h

Port PJ direction

PJDIR

04h

Port PJ pullup/pulldown enable

PJREN

06h

Port PJ drive strength

PJDS

08h

表 9-34. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTIONREGISTEROFFSETTA0 control

TA0CTL00h

Capture/compare control 0

TA0CCTL002h

Capture/compare control 1

TA0CCTL1

04h

Capture/compare control 2

TA0CCTL2

06h

Capture/compare control 3

TA0CCTL3

08h

Capture/compare control 4

TA0CCTL4

0Ah

TA0 counter

TA0R

10h

Capture/compare 0

TA0CCR012h

Capture/compare 1

TA0CCR1

14h

Capture/compare 2

TA0CCR2

16h

Capture/compare 3

TA0CCR3

18h

Capture/compare 4

TA0CCR4

1Ah

TA0 expansion 0

TA0EX020h

TA0 interrupt vector

TA0IV

2Eh

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

表 9-35. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTIONREGISTEROFFSETTA1 control

TA1CTL00h

Capture/compare control 0

TA1CCTL002h

Capture/compare control 1

TA1CCTL1

04h

Capture/compare control 2

TA1CCTL2

06h

TA1 counter

TA1R

10h

Capture/compare 0

TA1CCR012h

Capture/compare 1

TA1CCR1

14h

Capture/compare 2

TA1CCR216h

TA1 expansion 0

TA1EX020h

TA1 interrupt vector

TA1IV

2Eh

表 9-36. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTIONREGISTEROFFSET

TB0 control

TB0CTL00h

Capture/compare control 0

TB0CCTL002h

Capture/compare control 1

TB0CCTL1

04h

Capture/compare control 2

TB0CCTL2

06h

Capture/compare control 3

TB0CCTL3

08h

Capture/compare control 4

TB0CCTL4

0Ah

Capture/compare control 5

TB0CCTL5

0Ch

Capture/compare control 6

TB0CCTL60Eh

TB0 counter

TB0R

10h

Capture/compare 0

TB0CCR012h

Capture/compare 1

TB0CCR1

14h

Capture/compare 2

TB0CCR2

16h

Capture/compare 3

TB0CCR3

18h

Capture/compare 4

TB0CCR4

1Ah

Capture/compare 5

TB0CCR5

1Ch

Capture/compare 6

TB0CCR6

1Eh

TB0 expansion 0

TB0EX020h

TB0 interrupt vector

TB0IV

2Eh

表 9-37. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTIONREGISTEROFFSETTA2 control

TA2CTL00h

Capture/compare control 0

TA2CCTL002h

Capture/compare control 1

TA2CCTL1

04h

Capture/compare control 2

TA2CCTL2

06h

TA2 counter

TA2R

10h

Capture/compare 0

TA2CCR012h

Capture/compare 1

TA2CCR1

14h

Capture/compare 2

TA2CCR216h

TA2 expansion 0

TA2EX020h

TA2 interrupt vector

TA2IV

2Eh

76

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表 9-38. Battery Backup Registers (Base Address: 0480h)
REGISTER DESCRIPTIONREGISTEROFFSET

Battery backup memory 0

BAKMEM000h

Battery backup memory 1

BAKMEM1

02h

Battery backup memory 2

BAKMEM2

04h

Battery backup memory 3

BAKMEM3

06h

Battery backup control

BAKCTL

1Ch

Battery charger control

BAKCHCTL

1Eh

表 9-39. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTIONREGISTEROFFSET

RTC control 0

RTCCTL000h

RTC control 1

RTCCTL101h

RTC control 2

RTCCTL202h

RTC control 3

RTCCTL303h

RTC prescaler 0 control

RTCPS0CTL

08h

RTC prescaler 1 control

RTCPS1CTL

0Ah

RTC prescaler 0

RTCPS00Ch

RTC prescaler 1

RTCPS10Dh

RTC interrupt vector word

RTCIV

0Eh

RTC seconds

RTCSEC10h

RTC minutes

RTCMIN11h

RTC hours

RTCHOUR12h

RTC day of week

RTCDOW

13h

RTC days

RTCDAY

14h

RTC month

RTCMON15h

RTC year low

RTCYEARL

16h

RTC year high

RTCYEARH

17h

RTC alarm minutes

RTCAMIN

18h

RTC alarm hours

RTCAHOUR

19h

RTC alarm day of week

RTCADOW

1Ah

RTC alarm days

RTCADAY

1Bh

Binary-to-BCD conversion

BIN2BCD

1Ch

BCD-to-binary conversion

BCD2BIN1Eh

表 9-40. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTIONREGISTEROFFSET

16-bit operand 1 – multiply

MPY

00h

16-bit operand 1 – signed multiply

MPYS

02h

16-bit operand 1 – multiply accumulate

MAC

04h

16-bit operand 1 – signed multiply accumulate

MACS

06h

16-bit operand 2

OP2

08h

16 × 16 result low word

RESLO

0Ah

16 × 16 result high word

RESHI

0Ch

16 × 16 sum extension

SUMEXT0Eh

32-bit operand 1 – multiply low word

MPY32L10h

32-bit operand 1 – multiply high word

MPY32H12h32-bit operand 1 – signed multiply low word

MPYS32L

14h

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表 9-40. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h) (continued)
REGISTER DESCRIPTIONREGISTEROFFSET

32-bit operand 1 – signed multiply high word

MPYS32H

16h32-bit operand 1 – multiply accumulate low word

MAC32L18h

32-bit operand 1 – multiply accumulate high word

MAC32H1Ah

32-bit operand 1 – signed multiply accumulate low word

MACS32L

1Ch

32-bit operand 1 – signed multiply accumulate high word

MACS32H

1Eh32-bit operand 2 – low word

OP2L

20h

32-bit operand 2 – high word

OP2H

22h

32 × 32 result 0 – least significant word

RES0

24h

32 × 32 result 1

RES1

26h

32 × 32 result 2

RES2

28h

32 × 32 result 3 – most significant word

RES3

2Ah

MPY32 control 0

MPY32CTL02Ch

表 9-41. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h)
REGISTER DESCRIPTIONREGISTEROFFSET

DMA general control: DMA module control 0

DMACTL000h

DMA general control: DMA module control 1

DMACTL102h

DMA general control: DMA module control 2

DMACTL204h

DMA general control: DMA module control 3

DMACTL306h

DMA general control: DMA module control 4

DMACTL408h

DMA general control: DMA interrupt vector

DMAIV

0Ah

DMA channel 0 control

DMA0CTL

00h

DMA channel 0 source address low

DMA0SAL

02h

DMA channel 0 source address high

DMA0SAH04h

DMA channel 0 destination address low

DMA0DAL

06h

DMA channel 0 destination address high

DMA0DAH08h

DMA channel 0 transfer size

DMA0SZ

0Ah

DMA channel 1 control

DMA1CTL

00h

DMA channel 1 source address low

DMA1SAL

02h

DMA channel 1 source address high

DMA1SAH04h

DMA channel 1 destination address low

DMA1DAL

06h

DMA channel 1 destination address high

DMA1DAH08h

DMA channel 1 transfer size

DMA1SZ

0Ah

DMA channel 2 control

DMA2CTL

00h

DMA channel 2 source address low

DMA2SAL

02h

DMA channel 2 source address high

DMA2SAH04h

DMA channel 2 destination address low

DMA2DAL

06h

DMA channel 2 destination address high

DMA2DAH08h

DMA channel 2 transfer size

DMA2SZ

0Ah

DMA channel 3 control

DMA3CTL

00h

DMA channel 3 source address low

DMA3SAL

02h

DMA channel 3 source address high

DMA3SAH04h

DMA channel 3 destination address low

DMA3DAL

06h

DMA channel 3 destination address high

DMA3DAH

08h

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表 9-41. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h) (continued)
REGISTER DESCRIPTIONREGISTEROFFSET

DMA channel 3 transfer size

DMA3SZ

0Ah

DMA channel 4 control

DMA4CTL

00h

DMA channel 4 source address low

DMA4SAL

02h

DMA channel 4 source address high

DMA4SAH04h

DMA channel 4 destination address low

DMA4DAL

06h

DMA channel 4 destination address high

DMA4DAH08h

DMA channel 4 transfer size

DMA4SZ

0Ah

DMA channel 5 control

DMA5CTL

00h

DMA channel 5 source address low

DMA5SAL

02h

DMA channel 5 source address high

DMA5SAH04h

DMA channel 5 destination address low

DMA5DAL

06h

DMA channel 5 destination address high

DMA5DAH08h

DMA channel 5 transfer size

DMA5SZ0Ah

表 9-42. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTIONREGISTEROFFSETUSCI control 0

UCA0CTL000h

USCI control 1

UCA0CTL1

01h

USCI baud rate 0

UCA0BR006h

USCI baud rate 1

UCA0BR107h

USCI modulation control

UCA0MCTL

08h

USCI status

UCA0STAT

0Ah

USCI receive buffer

UCA0RXBUF

0Ch

USCI transmit buffer

UCA0TXBUF

0Eh

USCI LIN control

UCA0ABCTL

10h

USCI IrDA transmit control

UCA0IRTCTL

12h

USCI IrDA receive control

UCA0IRRCTL

13h

USCI interrupt enable

UCA0IE1Ch

USCI interrupt flags

UCA0IFG

1Dh

USCI interrupt vector word

UCA0IV1Eh

表 9-43. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTIONREGISTEROFFSETUSCI synchronous control 0

UCB0CTL000h

USCI synchronous control 1

UCB0CTL1

01h

USCI synchronous bit rate 0

UCB0BR006h

USCI synchronous bit rate 1

UCB0BR107h

USCI synchronous status

UCB0STAT

0Ah

USCI synchronous receive buffer

UCB0RXBUF

0Ch

USCI synchronous transmit buffer

UCB0TXBUF

0Eh

USCI I2C own address

UCB0I2COA

10h

USCI I2C slave address

UCB0I2CSA

12h

USCI interrupt enable

UCB0IE1Ch

USCI interrupt flags

UCB0IFG

1Dh

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

表 9-43. USCI_B0 Registers (Base Address: 05E0h) (continued)
REGISTER DESCRIPTIONUSCI interrupt vector word

REGISTERUCB0IVOFFSET1Eh

表 9-44. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTIONREGISTEROFFSETUSCI control 0

UCA1CTL000h

USCI control 1

UCA1CTL1

01h

USCI baud rate 0

UCA1BR006h

USCI baud rate 1

UCA1BR107h

USCI modulation control

UCA1MCTL

08h

USCI status

UCA1STAT

0Ah

USCI receive buffer

UCA1RXBUF

0Ch

USCI transmit buffer

UCA1TXBUF

0Eh

USCI LIN control

UCA1ABCTL

10h

USCI IrDA transmit control

UCA1IRTCTL

12h

USCI IrDA receive control

UCA1IRRCTL

13h

USCI interrupt enable

UCA1IE1Ch

USCI interrupt flags

UCA1IFG

1Dh

USCI interrupt vector word

UCA1IV1Eh

表 9-45. USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTIONREGISTEROFFSETUSCI synchronous control 0

UCB1CTL000h

USCI synchronous control 1

UCB1CTL1

01h

USCI synchronous bit rate 0

UCB1BR006h

USCI synchronous bit rate 1

UCB1BR107h

USCI synchronous status

UCB1STAT

0Ah

USCI synchronous receive buffer

UCB1RXBUF

0Ch

USCI synchronous transmit buffer

UCB1TXBUF

0Eh

USCI I2C own address

UCB1I2COA

10h

USCI I2C slave address

UCB1I2CSA

12h

USCI interrupt enable

UCB1IE1Ch

USCI interrupt flags

UCB1IFG

1Dh

USCI interrupt vector word

UCB1IV1Eh

表 9-46. ADC12_A Registers (Base Address: 0700h)
REGISTER DESCRIPTIONREGISTEROFFSET

ADC12 control 0

ADC12CTL000h

ADC12 control 1

ADC12CTL102h

ADC12 control 2

ADC12CTL2

04h

Interrupt flag

ADC12IFG

0Ah

Interrupt enable

ADC12IE

0Ch

Interrupt vector word

ADC12IV

0Eh

ADC memory control 0

ADC12MCTL010h

ADC memory control 1

ADC12MCTL111h

ADC memory control 2

ADC12MCTL212h

ADC memory control 3

ADC12MCTL3

13h

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表 9-46. ADC12_A Registers (Base Address: 0700h) (continued)
REGISTER DESCRIPTIONREGISTEROFFSET

ADC memory control 4

ADC12MCTL414h

ADC memory control 5

ADC12MCTL515h

ADC memory control 6

ADC12MCTL616h

ADC memory control 7

ADC12MCTL717h

ADC memory control 8

ADC12MCTL818h

ADC memory control 9

ADC12MCTL919h

ADC memory control 10

ADC12MCTL10

1Ah

ADC memory control 11

ADC12MCTL11

1Bh

ADC memory control 12

ADC12MCTL12

1Ch

ADC memory control 13

ADC12MCTL13

1Dh

ADC memory control 14

ADC12MCTL14

1Eh

ADC memory control 15

ADC12MCTL15

1FhConversion memory 0

ADC12MEM020h

Conversion memory 1

ADC12MEM1

22h

Conversion memory 2

ADC12MEM2

24h

Conversion memory 3

ADC12MEM3

26h

Conversion memory 4

ADC12MEM428h

Conversion memory 5

ADC12MEM5

2AhConversion memory 6

ADC12MEM6

2Ch

Conversion memory 7

ADC12MEM7

2EhConversion memory 8

ADC12MEM830hConversion memory 9

ADC12MEM932h

Conversion memory 10

ADC12MEM1034h

Conversion memory 11

ADC12MEM11

36h

Conversion memory 12

ADC12MEM1238h

Conversion memory 13

ADC12MEM13

3Ah

Conversion memory 14

ADC12MEM14

3Ch

Conversion memory 15

ADC12MEM153Eh

表 9-47. DAC12_A Registers (Base Address: 0780h)
REGISTER DESCRIPTIONREGISTEROFFSET

DAC12_A channel 0 control 0

DAC12_0CTL000h

DAC12_A channel 0 control 1

DAC12_0CTL102h

DAC12_A channel 0 data

DAC12_0DAT

04h

DAC12_A channel 0 calibration control

DAC12_0CALCTL

06h

DAC12_A channel 0 calibration data

DAC12_0CALDAT08h

DAC12_A channel 1 control 0

DAC12_1CTL010h

DAC12_A channel 1 control 1

DAC12_1CTL1

12h

DAC12_A channel 1 data

DAC12_1DAT14h

DAC12_A channel 1 calibration control

DAC12_1CALCTL

16h

DAC12_A channel 1 calibration data

DAC12_1CALDAT18h

DAC12_A interrupt vector word

DAC12IV1Eh

表 9-48. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
Comp_B control 0

REGISTERCBCTL0

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OFFSET
00h

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

表 9-48. Comparator_B Registers (Base Address: 08C0h) (continued)
REGISTER DESCRIPTIONREGISTEROFFSET

Comp_B control 1

CBCTL102h

Comp_B control 2

CBCTL204h

Comp_B control 3

CBCTL306h

Comp_B interrupt

CBINT

0Ch

Comp_B interrupt vector word

CBIV

0Eh

表 9-49. USB Configuration Registers (Base Address: 0900h)
REGISTER DESCRIPTIONREGISTEROFFSETUSB key/ID

USBKEYID

00h

USB module configuration

USBCNF

02h

USB PHY control

USBPHYCTL

04h

USB power control

USBPWRCTL

08h

USB power voltage setting

USBPWRVSR

0Ah

USB PLL control

USBPLLCTL

10h

USB PLL divider

USBPLLDIV

12h

USB PLL interrupts

USBPLLIR14h

表 9-50. USB Control Registers (Base Address: 0920h)
REGISTER DESCRIPTIONREGISTEROFFSET

Input endpoint_0 configuration

USBIEPCNF_0

00h

Input endpoint_0 byte count

USBIEPCNT_001h

Output endpoint_0 configuration

USBOEPCNF_0

02h

Output endpoint_0 byte count

USBOEPCNT_0

03h

Input endpoint interrupt enables

USBIEPIE

0Eh

Output endpoint interrupt enables

USBOEPIE

0Fh

Input endpoint interrupt flags

USBIEPIFG

10h

Output endpoint interrupt flags

USBOEPIFG

11h

USB interrupt vector

USBIV

12h

USB maintenance

USBMAINT

16h

Timestamp

USBTSREG

18h

USB frame number

USBFN

1Ah

USB control

USBCTL1Ch

USB interrupt enables

USBIE

1Dh

USB interrupt flags

USBIFG

1Eh

Function address

USBFUNADR

1Fh

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9.13 Input/Output Diagrams
9.13.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
図 9-2 shows the pin diagram. 表 9-51 summarizes how to select the pin function.
Pad Logic

P1REN.x

DVSS

0

DVCC

1

1

Direction
0: Input
1: Output

P1DIR.x

P1OUT.x0Module X OUT

1
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA0.1
P1.7/TA0.2

P1DS.x0: Low drive
1: High drive

P1SEL.x
P1IN.xEN
Module X IN

D

P1IE.xEN

P1IRQ.x

Q
P1IFG.x

Set

P1SEL.xInterrupt
Edge
SelectP1IES.x

図 9-2. Port P1 (P1.0 to P1.7) Diagram

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表 9-51. Port P1 (P1.0 to P1.7) Pin Functions
PIN NAME (P1.x)

x

FUNCTION
P1.0 (I/O)

P1.0/TA0CLK/ACLK

0 Timer TA0.TA0CLK
ACLK
P1.1 (I/O)

P1.1/TA0.0

1 Timer TA0.CCI0A capture input
Timer TA0.0 output
P1.2 (I/O)

P1.2/TA0.1

2 Timer TA0.CCI1A capture input
Timer TA0.1 output
P1.3 (I/O)

P1.3/TA0.2

3 Timer TA0.CCI2A capture input
Timer TA0.2 output
P1.4 (I/O)

P1.4/TA0.3

4 Timer TA0.CCI3A capture input
Timer TA0.3 output
P1.5 (I/O)

P1.5/TA0.4

5 Timer TA0.CCI4A capture input
Timer TA0.4 output
P1.6 (I/O)

P1.6/TA0.1

6 Timer TA0.CCI1B capture input
Timer TA0.1 output
P1.7 (I/O)

P1.7/TA0.2

7 Timer TA0.CCI2B capture input
Timer TA0.2 output

84

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CONTROL BITS OR SIGNALSP1DIR.x

P1SEL.x

I: 0; O: 1

0

0

1

1

1

I: 0; O: 1

0

0

1

1

1

I: 0; O: 1

0

0

1

1

1

I: 0; O: 1

0

0

1

1

1

I: 0; O: 1

0

0

1

1

1

I: 0; O: 1

0

0

1

1

1

I: 0; O: 1

0

0

1

1

1

I: 0; O: 1

0

0

1

1

1

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

9.13.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
図 9-3 shows the pin diagram. 表 9-52 summarizes how to select the pin function.
Pad Logic

P2REN.x

P2DIR.x0

From Port Mapping

1

P2OUT.x0

From Port Mapping

1

DVSS

0

DVCC

1

1

Direction
0: Input
1: Output

P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6
P2.7/P2MAP7

P2DS.x0: Low drive
1: High drive

P2SEL.x
P2IN.xEN
To Port Mapping

D

P2IE.xEN

P2IRQ.x

Q
P2IFG.x

Set

P2SEL.xInterrupt
Edge
SelectP2IES.x

図 9-3. Port P2 (P2.0 to P2.7) Diagram

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

表 9-52. Port P2 (P2.0 to P2.7) Pin Functions
PIN NAME (P2.x)
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2

x
0
1
2

P2.3/P2MAP3

3

P2.4/P2MAP4

4

P2.5/P2MAP5

5

P2.6/P2MAP6

6

P2.7/P2MAP7786FUNCTION
P2.0 (I/O)
Mapped secondary digital function
P2.1 (I/O)
Mapped secondary digital function
P2.2 (I/O)
Mapped secondary digital function
P2.3 (I/O)
Mapped secondary digital function
P2.4 (I/O)
Mapped secondary digital function
P2.5 (I/O
Mapped secondary digital function
P2.6 (I/O)
Mapped secondary digital function
P2.7 (I/O)
Mapped secondary digital function

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CONTROL BITS OR SIGNALS(1)P2DIR.x

P2SEL.x

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

P2MAPx
≤ 19
≤ 19
≤ 19
≤ 19
≤ 19
≤ 19
≤ 19
≤ 19

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

9.13.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
図 9-4 shows the pin diagram. 表 9-53 summarizes how to select the pin function.
Pad Logic

P3REN.x

DVSS

0

DVCC

1

Direction
0: Input
1: Output

P3DIR.x

P3OUT.x0Module X OUT

1
P3DS.x0: Low drive
1: High drive

P3SEL.x
P3IN.xEN
Module X IN

1

P3.0/TA1CLK/CBOUT
P3.1/TA1.0
P3.2/TA1.1
P3.3/TA1.2
P3.4/TA2CLK/SMCLK
P3.5/TA2.0
P3.6/TA2.1
P3.7/TA2.2

D
P3IE.xEN

P3IRQ.x

Q
P3IFG.x

Set

P3SEL.xInterrupt
Edge
SelectP3IES.x

図 9-4. Port P3 (P3.0 to P3.7) Diagram

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

表 9-53. Port P3 (P3.0 to P3.7) Pin Functions
PIN NAME (P3.x)x

FUNCTION
P3.0 (I/O)

P3.0/TA1CLK/CBOUT

P3.1/TA1.0

0 Timer TA1.TA1CLK

1
1

P3.1 (I/O)

I: 0; O: 1

0

0

1

2 Timer TA1.CCI1A capture input
Timer TA1.1 output

1
0

0

1

1

1

I: 0; O: 1

0

0

1

SMCLK

1

1

P3.5 (I/O)

I: 0; O: 1

0

0

1

1

1

I: 0; O: 1

0

0

1

3 Timer TA1.CCI2A capture input

4 Timer TA2.TA2CLK

5 Timer TA2.CCI0A capture input
Timer TA2.0 output
P3.6 (I/O)
6 Timer TA2.CCI1A capture input
Timer TA2.1 output
P3.7 (I/O)
7 Timer TA2.CCI2A capture input
Timer TA2.2 output

88

0

0

1

P3.4 (I/O)

P3.7/TA2.2

1

1

Timer TA1.2 output

P3.6/TA2.1

1
I: 0; O: 1

I: 0; O: 1

P3.3 (I/O)

P3.5/TA2.0

01

P3.2 (I/O)

P3.4/TA2CLK/SMCLKP3SEL.x0Timer TA1.0 output

P3.3/TA1.2

P3DIR.x
I: 0; O: 1

CBOUT
1 Timer TA1.CCI0A capture input

P3.2/TA1.1

CONTROL BITS OR SIGNALS

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I: 0; O: 1

0

0

1

1

1

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

9.13.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
図 9-5 shows the pin diagram. 表 9-54 summarizes how to select the pin function.
Pad Logic

P4REN.x

DVSS

0

DVCC

1

Direction
0: Input
1: Output

P4DIR.x

P4OUT.x0Module X OUT

1
P4DS.x0: Low drive
1: High drive

P4SEL.x
P4IN.xEN
Module X IN

1

P4.0/TB0.0
P4.1/TB0.1
P4.2/TB0.2
P4.3/TB0.3
P4.4/TB0.4
P4.5/TB0.5
P4.6/TB0.6
P4.7/TB0OUTH/SVMOUT

D
P4IE.xEN

P4IRQ.x

Q
P4IFG.x

Set

P4SEL.xInterrupt
Edge
SelectP4IES.x

図 9-5. Port P4 (P4.0 to P4.7) Diagram

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

表 9-54. Port P4 (P4.0 to P4.7) Pin Functions
PIN NAME (P4.x)

x

FUNCTION
P4.0 (I/O)

P4.0/TB0.0

0 Timer TB0.CCI0A capture input
Timer TB0.0 output(1)P4.1 (I/O)

P4.1/TB0.1

1 Timer TB0.CCI1A capture input
Timer TB0.1 output(1)P4.2 (I/O)

P4.2/TB0.2

2 Timer TB0.CCI2A capture input
Timer TB0.2 output(1)P4.3 (I/O)

P4.3/TB0.3

3 Timer TB0.CCI3A capture input
Timer TB0.3 output(1)P4.4 (I/O)

P4.4/TB0.4

4 Timer TB0.CCI4A capture input
Timer TB0.4 output(1)P4.5 (I/O)

P4.5/TB0.5

5 Timer TB0.CCI5A capture input
Timer TB0.5 output(1)P4.6 (I/O)

P4.6/TB0.6

6 Timer TB0.CCI6A capture input
Timer TB0.6 output(1)P4.7 (I/O)

P4.7/TB0OUTH/ SVMOUT

7 Timer TB0.TB0OUTH
SVMOUT(1)

Setting TB0OUTH causes all Timer_B configured outputs to be set to high impedance.

90

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CONTROL BITS OR SIGNALSP4DIR.x

P4SEL.x

I: 0; O: 1

0

0

1

1

1

I: 0; O: 1

0

0

1

1

1

I: 0; O: 1

0

0

1

1

1

I: 0; O: 1

0

0

1

1

1

I: 0; O: 1

0

0

1

1

1

I: 0; O: 1

0

0

1

1

1

I: 0; O: 1

0

0

1

1

1

I: 0; O: 1

0

0

1

1

1

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

9.13.5 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
図 9-6 shows the pin diagram. 表 9-55 summarizes how to select the pin function.
Pad Logic
To/From
Reference

P5REN.x

P5DIR.x

DVSS

0

DVCC

1

1

0
1

P5OUT.x0Module X OUT

1
P5.0/VREF+/VeREF+
P5.1/VREF–/VeREF–

P5DS.x0: Low drive
1: High drive

P5SEL.x
P5IN.xBus
KeeperEN
Module X IND

図 9-6. Port P5 (P5.0 and P5.1) Diagram
表 9-55. Port P5 (P5.0 and P5.1) Pin Functions
PIN NAME (P5.x)x

FUNCTION

P5DIR.x

P5SEL.x

REFOUT

I: 0; O: 1

0

X

X

1

0

VREF+(4)X

1

1

P5.1 (I/O)(2)

I: 0; O: 10

X

1 VeREF-(5)

X

1

0

VREF-(6)X

1

1

P5.0 (I/O)(2)P5.0/VREF+/VeREF+

P5.1/VREF-/VeREF-

(1)
(2)
(3)
(4)
(5)
(6)

CONTROL BITS OR SIGNALS(1)0 VeREF+(3)X = Don't care
Default condition
Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A, Comparator_B, or
DAC12_A.
Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. The ADC12_A VREF+ reference is available at the pin.
Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A, Comparator_B, or
DAC12_A.
Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. The ADC12_A VREF- reference is available at the pin.

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

9.13.6 Port P5 (P5.2 to P5.7) Input/Output With Schmitt Trigger
図 9-7 shows the pin diagram. 表 9-56 summarizes how to select the pin function.
Pad Logic

P5REN.x

DVSS

0

DVCC

1

1

Direction
0: Input
1: Output

P5DIR.x

P5OUT.x0Module X OUT

1
P5.2
P5.3
P5.4
P5.5
P5.6/ADC12CLK/DMAE0
P5.7/RTCCLK

P5DS.x0: Low drive
1: High drive

P5SEL.x
P5IN.xEN
Module X IND

図 9-7. Port P5 (P5.2 to P5.7) Diagram
表 9-56. Port P5 (P5.2 to P5.7) Pin Functions
PIN NAME (P5.x)

x

CONTROL BITS OR SIGNALSFUNCTION

P5DIR.x

P5SEL.x

P5.2

2

P5.2 (I/O)

I: 0; O: 1

0

P5.3

3

P5.3 (I/O)

I: 0; O: 1

0

P5.4

4

P5.4 (I/O)

I: 0; O: 1

0

P5.5

5

P5.5 (I/O)

I: 0; O: 1

0

P5.6 (I/O)

I: 0; O: 1

0

ADC12CLK

1

1

DMAE0

0

1

P5.7 (I/O)

I: 0; O: 10

RTCCLK

1

1

P5.6/ADC12CLK/DMAE0

P5.7/RTCCLK

6

7

9.13.7 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
図 9-8 shows the pin diagram. 表 9-57 summarizes how to select the pin function.

92

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

Pad Logic
To ADC12INCHx = y
0
Dvss

1

From DAC12_A

2

0 if DAC12AMPx=0
1 if DAC12AMPx=1
2 if DAC12AMPx>1

To Comparator_B
From Comparator_B
CBPD.xDAC12AMPx>0
DAC12OPS
P6REN.x

DVSS

0

DVCC

1

1

P6DIR.x

P6OUT.xP6.0/CB0/A0
P6.1/CB1/A1
P6.2/CB2/A2
P6.3/CB3/A3
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6/DAC0
P6.7/CB7/A7/DAC1

P6DS.x0: Low drive
1: High drive

P6SEL.x
P6IN.xBus
Keeper

図 9-8. Port P6 (P6.0 to P6.7) Diagram

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

表 9-57. Port P6 (P6.0 to P6.7) Pin Functions
PIN NAME (P6.x)x

FUNCTION

P6DIR.x

P6SEL.x

CBPD.xDAC12OPSDAC12AMPx

I: 0; O: 1

0

0

n/a

n/a

CB0

X

X

1

n/a

n/a

A0(1) (2)

X

1

X

n/a

n/a

P6.1 (I/O)

I: 0; O: 1

0

0

n/a

n/a

X

X

1

n/a

n/a

A1(1) (2)

X

1

X

n/a

n/a

P6.2 (I/O)

I: 0; O: 1

0

0

n/a

n/a

X

X

1

n/a

n/a

A2(1) (2)

X

1

X

n/a

n/a

P6.3 (I/O)

I: 0; O: 1

0

0

n/a

n/a

CB3

X

X

1

n/a

n/a

A3(1) (2)

X

1

X

n/a

n/a

P6.4 (I/O)

I: 0; O: 1

0

0

n/a

n/a

X

X

1

n/a

n/a

A4(1) (2)

X

1

X

n/a

n/a

P6.5 (I/O)

I: 0; O: 1

0

0

n/a

n/a

CB5

X

X

1

n/a

n/a

A5 (1) (2)

X

1

X

n/a

n/a

P6.6 (I/O)

P6.0 (I/O)
P6.0/CB0/A0

P6.1/CB1/A1

P6.2/CB2/A2

P6.3/CB3/A3

P6.4/CB4/A4

P6.5/CB5/A5

P6.6/CB6/A6/DAC0

0

1

2

3

4

5

6

CB1

CB2

CB4

I: 0; O: 1

0

0

X

0

CB6

X

X

1

X

0

A6(1) (2)

X

1

X

X

0

DAC0

X

X

X

0

>1

P6.7 (I/O)
P6.7/CB7/A7/DAC1(1)

7

CONTROL BITS OR SIGNALS(1)I: 0; O: 1

0

0

X

0

CB7

X

X

1

X

0

A7(1) (2)

X

1

X

X

0

DAC1

X

X

X

0

>1

(2)

Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
The ADC12_A channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.

94

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

9.13.8 Port P7 (P7.2) Input/Output With Schmitt Trigger
図 9-9 shows the pin diagram. 表 9-58 summarizes how to select the pin function.
Pad Logic
To XT2P7REN.2

P7DIR.2

DVSS

0

DVCC

1

1

0
1

P7OUT.2
P7.2/XT2IN

P7DS.20: Low drive
1: High drive

P7SEL.2
P7IN.2Bus
Keeper

図 9-9. Port P7 (P7.2) Diagram

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

9.13.9 Port P7 (P7.3) Input/Output With Schmitt Trigger
図 9-10 shows the pin diagram. 表 9-58 summarizes how to select the pin function.
Pad Logic
To XT2P7REN.3

P7DIR.3

DVSS

0

DVCC

1

1

0
1

P7OUT.3
P7SEL.2

P7.3/XT2OUT

P7DS.30: Low drive
1: High drive

XT2BYPASS
P7SEL.3
P7IN.3Bus
Keeper

図 9-10. Port P7 (P7.3) Diagram
表 9-58. Port P7 (P7.2 and P7.3) Pin Functions
PIN NAME (P5.x)x

FUNCTION

P7DIR.x

P7SEL.2

P7SEL.3

XT2BYPASS

I: 0; O: 1

0

X

X

XT2IN crystal mode(1)

X

1

X

0

XT2IN bypass mode(1)

X

1

X

1

I: 0; O: 1

0

0

X

X

1

X

0

X

1

0

1

P7.2 (I/O)
P7.2/XT2IN

2

P7.3 (I/O)
P7.3/XT2OUT

3 XT2OUT crystal mode(2)P7.3 (I/O)(2)

(1)
(2)

96

CONTROL BITS OR SIGNALS(1)Setting P7SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P7.2 is configured for crystal
mode or bypass mode.
Setting P7SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.3 can be used as
general-purpose I/O.

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

9.13.10 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
図 9-11 shows the pin diagram. 表 9-59 summarizes how to select the pin function.
0
DVSS

1

From DAC12_A

2

Pad Logic
0 if DAC12AMPx = 0
1 if DAC12AMPx = 1
2 if DAC12AMPx > 1

To ADC12INCHx = y

To Comparator_B
From Comparator_B
CBPD.xDAC12AMPx>0
DAC12OPS
P7REN.x
P7SEL.x

DVSS

0

DVCC

1

1

P7DIR.x

P7OUT.x
P7DS.x0: Low drive
1: High drive

P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14/DAC0
P7.7/CB11/A15/DAC1

P7IN.xBus
Keeper

図 9-11. Port P7 (P7.4 to P7.7) Diagram

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

表 9-59. Port P7 (P7.4 to P7.7) Pin Functions
PIN NAME (P7.x)

x

FUNCTION

P7DIR.x

P7SEL.x

CBPD.xDAC12OPSDAC12AMPx

I: 0; O: 1

0

0

n/a

n/a

Comparator_B input CB8

X

X

1

n/a

n/a

A12(1) (2)

X

1

X

n/a

n/a

P7.5 (I/O)

I: 0; O: 1

0

0

n/a

n/a

X

X

1

n/a

n/a

A13(1) (2)

X

1

X

n/a

n/a

P7.6 (I/O)

I: 0; O: 1

0

0

X

0

Comparator_B input CB10

X

X

1

X

0

A14(1) (2)

X

1

X

X

0

DAC12_A output DAC0

X

X

X

1

>1

P7.4 (I/O)
P7.4/CB8/A12

4

P7.5/CB9/A13

5

P7.6/CB10/A14/DAC0

6

Comparator_B input CB9P7.7 (I/O)
P7.7/CB11/A15/DAC1(1)

7

CONTROL BITS OR SIGNALS(1)I: 0; O: 1

0

0

X

0

Comparator_B input CB11

X

X

1

X

0

A15(1) (2)

X

1

X

X

0

DAC12_A output DAC1

X

X

X

1

>1

(2)

Setting the P7SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
The ADC12_A channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.

98

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JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

9.13.11 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
図 9-12 shows the pin diagram. 表 9-60 summarizes how to select the pin function.
Pad Logic

P8REN.x

P8DIR.x0

From module

1

P8OUT.x0Module X OUT

1

DVSS

0

DVCC

1

Direction
0: Input
1: Output

P8DS.x0: Low drive
1: High drive

P8SEL.x
P8IN.xEN
Module X IN

1

P8.0/TB0CLK
P8.1/UCB1STE/UCA1CLK
P8.2/UCA1TXD/UCA1SIMO
P8.3/UCA1RXD/UCA1SOMI
P8.4/UCB1CLK/UCA1STE
P8.5/UCB1SIMO//UCB1SDA
P8.6/UCB1SOMI/UCB1SCL
P8.7

D

図 9-12. Port P8 (P8.0 to P8.7) Diagram
表 9-60. Port P8 (P8.0 to P8.7) Pin Functions
PIN NAME (P9.x)x

P8.0/TB0CLK

0

P8.1/UCB1STE/UCA1CLK

1

P8.2/UCA1TXD/UCA1SIMO
P8.3/UCA1RXD/UCA1SOMI
P8.4/UCB1CLK/UCA1STE
P8.5/UCB1SIMO/UCB1SDA

2
3
4
5

FUNCTION
P8.0 (I/O)
Timer TB0.TB0CLK clock input
P8.1 (I/O)
UCB1STE/UCA1CLK
P8.2 (I/O)
UCA1TXD/UCA1SIMO
P8.3 (I/O)
UCA1RXD/UCA1SOMI
P8.4 (I/O)
UCB1CLK/UCA1STE
P8.5 (I/O)
UCB1SIMO/UCB1SDA
P8.6 (I/O)

P8.6/UCB1SOMI/UCB1SCL

6

P8.7

7 P8.7 (I/O)

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UCB1SOMI/UCB1SCL

CONTROL BITS OR
SIGNALS(1)P8DIR.x

P8SEL.x

I: 0; O: 1

0

0

1

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

I: 0; O: 10

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9.13.12 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
図 9-13 shows the pin diagram. 表 9-61 summarizes how to select the pin function.
Pad Logic

P9REN.x

DVSS

0

DVCC

1

1

Direction
0: Input
1: Output

P9DIR.x

P9OUT.x
P9.0
P9.1
P9.2
P9.3
P9.4
P9.5
P9.6
P9.7

P9DS.x0: Low drive
1: High drive
P9IN.x

図 9-13. Port P9 (P9.0 to P9.7) Diagram
表 9-61. Port P9 (P9.0 to P9.7) Pin Functions
PIN NAME (P9.x)

x

FUNCTIONCONTROL BITS OR SIGNALSP9DIR.x

P9SEL.x

P9.0

0

P9.0 (I/O)

I: 0; O: 1

0

P9.1

1

P9.1 (I/O)

I: 0; O: 1

0

P9.2

2

P9.2 (I/O)

I: 0; O: 1

0

P9.3

3

P9.3 (I/O)

I: 0; O: 1

0

P9.4

4

P9.4 (I/O)

I: 0; O: 1

0

P9.5

5

P9.5 (I/O)

I: 0; O: 1

0

P9.6

6

P9.6 (I/O)

I: 0; O: 1

0

P9.7

7

P9.7 (I/O)

I: 0; O: 10100

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9.13.13 Port PU (PU.0/DP, PU.1/DM, PUR) USB Ports
図 9-14 shows the pin diagram. 表 9-62 summarizes how to select the pin function.
PUSEL
PUOPE

0

USB output enable

1

PUOUT00

USB DP output

1

VUSB

VSSU
Pad Logic

PU.0/DPPUIN0
USB DP input
PUIPE

PUIN1
USB DM input
PUOUT1

0

USB DM output

1

PU.1/DM

VUSB

VSSU
Pad Logic

PUREN

PUR

“1 ”
PUSEL
PURIN

図 9-14. Port PU (PU.0 and PU.1) Diagram
表 9-62. Port PU.0/DP and PU.1/DM Output Functions
CONTROL BITSPIN NAME

FUNCTION

PUSEL

PUDIR

PUOUT1PUOUT0PU.1/DM

PU.0/DP

0

0

X

X

Hi-Z

Hi-Z

Outputs off

0

1

0

0

0

0

Outputs enabled

0

1

0

1

0

1

Outputs enabled

0

1

1

0

1

0

Outputs enabled

0

1

1

1

1

1

Outputs enabled

1

X

X

X

DM

DP

Direction set by USB module

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表 9-63. Port PUR Input Functions
CONTROL BITS

FUNCTION

PUSEL

PUREN

0

0

Input disabled
Pullup disabled

01

Input disabled
Pullup enabled

10Input enabled
Pullup disabled

1

1

Input enabled
Pullup enabled

9.13.14 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
図 9-15 shows the pin diagram. 表 9-64 summarizes how to select the pin function.
Pad Logic

PJREN.0

PJDIR.0

0

DVCC

1

PJOUT.00

From JTAG

1

DVSS

0

DVCC

1

1

PJDS.0
0: Low drive
1: High drive

From JTAG

PJ.0/TDO

PJIN.0END

図 9-15. Port J (PJ.0) Diagram

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9.13.15 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or
Output
図 9-16 shows the pin diagram. 表 9-64 summarizes how to select the pin function.
Pad Logic

PJREN.x

PJDIR.x

0

DVSS

1

PJOUT.x0

From JTAG

1

DVSS

0

DVCC

1

1

PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCKPJDS.x0: Low drive
1: High drive

From JTAG
PJIN.xEN
D

To JTAG

図 9-16. Port PJ (PJ.1 to PJ.3) Diagram
表 9-64. Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)

x

CONTROL BITS
OR SIGNALS(1)FUNCTIONPJDIR.x
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
(1)
(2)
(3)

0
1
2
3

PJ.0 (I/O)(1)

I: 0; O: 1

TDO(2)

X

PJ.1 (I/O)(1)

I: 0; O: 1

TDI/TCLK(2) (3)X

PJ.2 (I/O)(1)

I: 0; O: 1

TMS(2) (3)X

PJ.3 (I/O)(1)

I: 0; O: 1

TCK(2) (3)X

Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.

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9.14 Device Descriptors
表 9-65 list the contents of the device descriptor tag-length-value (TLV) structure.
表 9-65. MSP430F563x Device Descriptor Table
DESCRIPTION(1)Info Block

Die Record

ADC12
Calibration

VALUE

ADDRESS

SIZE(bytes)

F5638

F5637

F5636

F5635

F5634

F5633

F5632

F5631

F5630
06h

Info length

01A00h

1

06h

06h

06h

06h

06h

06h

06h

06h

CRC length

01A01h

1

06h

06h

06h

06h

06h

06h

06h

06h

06h

CRC value

01A02h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Device ID

01A04h

2

8014h

8012h

8010h

800Eh

8044h

8042h

8040h

803Eh

803Ch

Hardware revision

01A06h1

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Firmware revision

01A07h1

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Die record tag

01A08h

1

08h

08h

08h

08h

08h

08h

08h

08h

08h

Die record length

01A09h

1

0Ah

0Ah

0Ah

0Ah

0Ah

0Ah

0Ah

0Ah

0Ah

Lot/wafer ID

01A0Ah4

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Die X position

01A0Eh2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Die Y position

01A10h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit
Per unit

Test results

01A12h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC12 calibration tag

01A14h

1

11h

11h

11h

11h

11h

11h

11h

11h

11h

ADC12 calibration length

01A15h

1

10h

10h

10h

10h

10h

10h

10h

10h

10h

ADC gain factor

01A16h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC offset

01A18h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 1.5-V reference
temp. l 30°C

01A1Ah2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 1.5-V reference
Temperature sensor 85°C

01A1Ch2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 2.0-V reference
Temperature sensor 30°C

01A1Eh2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 2.0-V reference
Temperature sensor 85°C

01A20h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 2.5-V reference
Temperature sensor 30°C

01A22h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 2.5-V reference
Temperature sensor 85°C

01A24h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit(1)

NA = Not applicable104

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10 Device and Documentation Support
10.1 Getting Started and Next Steps
For more information on the MSP430™ family of devices and the tools and libraries that are available to help withyour development, visit the MSP430 ultra-low-power sensing & measurement MCUs overview.

10.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP
MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These
prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully
qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated
fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.
TI recommends that these devices not be used in any production system because their expected end-use failure
rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature
range, package type, and distribution format. 図 10-1 provides a legend for reading the complete device name.

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MSP 430 F 5 438 A I PM T -EP
Processor Family

Optional: Additional Features

MCU Platform

Optional: Tape and Reel

Device Type

Packaging

SeriesFeature Set
Processor Family

MCU Platform

Optional: Temperature Range
Optional: Revision

CC = Embedded RF RadioMSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 = MSP430 low-power microcontroller platform

Device Type

Memory TypeC = ROM
F = Flash
FR = FRAM
G = Flash
L = No nonvolatile memory

Specialized Application
AFE = Analog front end
BQ = Contactless power
CG = ROM medical
FE = Flash energy meter
FG = Flash medical
FW = Flash electronic flow meter

Series

1 = Up to 8 MHz
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD driver

5 = Up to 25 MHz
6 = Up to 25 MHz with LCD driver
0 = Low-voltage series

Feature Set

Various levels of integration within a series

Optional: Revision

Updated version of the base part number

Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging

http://www.ti.com/packaging

Optional: Tape and Reel

T = Small reel
R = Large reel
No markings = Tube or tray

Optional: Additional Features -EP = Enhanced product (–40°C to 105°C)-HT = Extreme temperature parts (–55°C to 150°C)-Q1 = Automotive Q100 qualified

図 10-1. Device Nomenclature

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10.3 Tools and Software
All MSP microcontrollers are supported by a wide variety of software and hardware development tools. Tools areavailable from TI and various third parties. See them all at MSP430 ultra-low-power MCUs – Design &development.
表 10-1 lists the debug features of the MSP430F563x MCUs. See the Code Composer Studio™ IDE for MSP430™ MCUs User's Guide for details on the available features.
表 10-1. Hardware Debug Features
MSP430
ARCHITECTURE

4-WIRE
JTAG

2-WIREJTAG

BREAKPOINTS
(N)

RANGE
BREAKPOINTSCLOCK
CONTROLSTATESEQUENCER

TRACE
BUFFER

LPMx.5DEBUGGINGSUPPORT

MSP430Xv2

Yes

Yes

8

Yes

Yes

Yes

Yes

No

Design Kits and Evaluation Modules
MSP-TS430PZ100USB - 100-pin Target Development Board for MSP430F5x and MSP430F6x MCUs
The MSP-TS430PZ100USB is a stand-alone 100-pin ZIF socket target board used to program and debug the
MSP430 MCU in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol.
100-pin Target Development Board and MSP-FET Programmer Bundle for MSP430F5x and MSP430F6x MCUs
The MSP-FET is a powerful flash emulation tool to quickly begin application development on the MSP430 MCU.
It includes USB debugging interface used to program and debug the MSP430 in-system through the JTAG
interface or the pin saving Spy Bi-Wire (2-wire JTAG) protocol. The flash memory can be erased andprogrammed in seconds with only a few keystrokes, and because the MSP430 flash is ultra-low power, no
external power supply is required.
Software
MSP430Ware™ Software
MSP430Ware software is a collection of code examples, data sheets, and other design resources for all
MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 design resources, MSP430Ware software also includes a high-level API called MSP430 Driver Library.
This library makes it easy to program MSP430 hardware. MSP430Ware software is available as a component of
CCS or as a stand-alone package.
MSP430F563x, MSP430F663x Code Examples
C code examples are available for every MSP device that configures each of the integrated peripherals forvarious application needs.
MSP Driver Library
Driver Library's abstracted API keeps you above the bits and bytes of the MSP430 hardware by providing easyto-use function calls. Thorough documentation is delivered through a helpful API Guide, which includes details
on each function call and the recognized parameters. Developers can use Driver Library functions to write
complete projects with minimal overhead.
MSP EnergyTrace™ Technology
EnergyTrace technology for MSP430 microcontrollers is an energy-based code analysis tool that measures anddisplays the application's energy profile and helps to optimize it for ultra-low-power consumption.

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ULP (Ultra-Low Power) Advisor
ULP Advisor ™ software is a tool for guiding developers to write more efficient code to fully utilize the uniqueultra-low power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new
microcontroller developers, ULP Advisor checks your code against a thorough ULP checklist to squeeze every
last nano amp out of your application. At build time, ULP Advisor will provide notifications and remarks tohighlight areas of your code that can be further optimized for lower power.
IEC 60730 Software Package
The IEC 60730 MSP430 software package was developed to be useful in assisting customers in complying withIEC 60730-1:2010 (Automatic Electrical Controls for Household and Similar Use – Part 1: General
Requirements) for up to Class B products, which includes home appliances, arc detectors, power converters,
power tools, e-bikes, and many others. The IEC 60730 MSP430 software package can be embedded incustomer applications running on MSP430s to help simplify the customer’s certification efforts of functionalsafety-compliant consumer devices to IEC 60730-1:2010 Class B.
Fixed Point Math Library for MSP
The MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical
functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430
MCUs. These routines are typically used in computationally intensive real-time applications where optimal
execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmath libraries, it ispossible to achieve execution speeds considerably faster and energy consumption considerably lower thanequivalent code written using floating-point math.
Floating Point Math Library for MSP430
Continuing to innovate in the low-power and low-cost microcontroller space, TI brings you MSPMATHLIB.
Leveraging the intelligent peripherals of our devices, this floating point math library of scalar functions brings you
up to 26x better performance. Mathlib is easy to integrate into your designs. This library is free and is integrated
in both Code Composer Studio and IAR IDEs. Read the user’s guide for an in depth look at the math library andrelevant benchmarks.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
The Code Composer Studio integrated development environment (IDE) supports all MSP microcontroller
devices. The Code Composer Studio IDE comprises a suite of embedded software utilities used to develop anddebug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build
environment, debugger, profiler, and many other features. The intuitive IDE provides a single user interface
taking you through each step of the application development flow. Familiar utilities and interfaces allow users to
get started faster than ever before. The Code Composer Studio IDE combines the advantages of the Eclipse
software framework with advanced embedded debug capabilities from TI resulting in a compelling feature-richdevelopment environment for embedded developers. When using the Code Composer Studio IDE with an
MSP430 MCU, a unique and powerful set of plugins and embedded software utilities are made available to fully
leverage the MSP430 microcontroller.
Command-Line Programmer
MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET
programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary
files (.txt or .hex) files directly to the MSP microcontroller without an IDE.

108

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MSP MCU Programmer and Debugger
The MSP-FET is a powerful emulation development tool – often called a debug probe – that lets users quickly
begin application development on MSP low-power microcontrollers (MCU). Creating MCU software usuallyrequires downloading the resulting binary program to the MSP device for validation and debugging. The MSPFET provides a debug communication pathway between a host computer and the target MSP. Furthermore, the
MSP-FET also provides a Backchannel UART connection between the computer's USB interface and the MSP
UART. This gives the MSP programmer a convenient method to communicate serially between the MSP and aterminal running on the computer. It also supports loading programs (often called firmware) to the MSP target
using the BSL (bootloader) through the UART and I2C communication protocols.
MSP-GANG Production Programmer
The MSP Gang Programmer is a device programmer that can program up to eight identical MSP430 or MSP432
flash or FRAM devices at the same time. The MSP Gang Programmer connects to a host PC using a standard
RS-232 or USB connection and provides flexible programming options that allow the user to fully customize theprocess. The MSP Gang Programmer is provided with an expansion board, called the Gang Splitter, that
implements the interconnections between the MSP Gang Programmer and multiple target devices. Eight cables
are provided that connect the expansion board to eight target devices (through JTAG or Spy-Bi-Wireconnectors). The programming can be done with a PC or as a stand-alone device. A PC-side graphical userinterface is also available and is DLL-based.

10.4 Documentation Support
The following documents describe the MSP430F563x MCUs. Copies of these documents are available on theInternet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for yourdevice on ti.com (for links to the product folders, see セクション 10.5). In the upper right corner, click the "Alertme" button. This registers you to receive a weekly digest of product information that has changed (if any). Forchange details, check the revision history of any revised document.
Errata
MSP430F5638 Device Erratasheet
Describes the known exceptions to the functional specifications for this device.
MSP430F5637 Device Erratasheet
Describes the known exceptions to the functional specifications for this device.
MSP430F5636 Device Erratasheet
Describes the known exceptions to the functional specifications for this device.
MSP430F5635 Device Erratasheet
Describes the known exceptions to the functional specifications for this device.
MSP430F5634 Device Erratasheet
Describes the known exceptions to the functional specifications for this device.
MSP430F5633 Device Erratasheet
Describes the known exceptions to the functional specifications for this device.
MSP430F5632 Device Erratasheet
Describes the known exceptions to the functional specifications for this device.

Copyright © 2021 Texas Instruments Incorporated

Submit Document Feedback

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MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

109

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.tij.co.jp

JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

MSP430F5631 Device Erratasheet
Describes the known exceptions to the functional specifications for this device.
MSP430F5630 Device Erratasheet
Describes the known exceptions to the functional specifications for this device.
User's Guides
MSP430x5xx and MSP430x6xx Family User's Guide
Detailed information on the modules and peripherals available in this device family.
IAR Embedded Workbench IDE for MSP430 MCUs User's Guide
This manual describes the use of IAR Embedded Workbench (EW430) with the MSP430 ultra-low-power
microcontrollers.
MSP430™ Flash Devices Bootloader (BSL) User's Guide
The MSP430 BSL lets users communicate with embedded memory in the MSP430 microcontroller during theprototyping phase, final production, and in service. Both the programmable memory (flash memory) and the data
memory (RAM) can be modified as required. Do not confuse the bootloader with the bootstrap loader programs
found in some digital signal processors (DSPs) that automatically load program code (and data) from external
memory to the internal memory of the DSP.
MSP430 Programming With the JTAG Interface
This document describes the functions that are required to erase, program, and verify the memory module of the
MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition,
it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This
document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG
interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide
This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the
program development tool for the MSP430 ultra-low-power microcontroller. Both available interface types, theparallel port interface and the USB interface, are described.
Application Reports
MSP430 32-kHz Crystal Oscillators
Selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal
oscillator. This application report summarizes crystal oscillator function and explains the parameters to select thecorrect crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout
are given. The document also contains detailed information on the possible oscillator tests to ensure stableoscillator operation in mass production.
MSP430 System-Level ESD Considerations
System-level ESD has become increasingly demanding with silicon technology scaling towards lower voltages
and the need for designing cost-effective and ultra-low-power components. This application report addresses
three different ESD topics to help board designers and OEMs understand and design robust system-level
designs.

110

Submit Document Feedback

Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634
MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.tij.co.jp

JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

10.5 Related Links
表 10-2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
表 10-2. Related LinksPARTS

PRODUCT FOLDER

ORDER NOWTECHNICALDOCUMENTS

TOOLS &SOFTWARE

SUPPORT &COMMUNITY

MSP430F5638

Click here

Click here

Click here

Click here

Click here

MSP430F5637

Click here

Click here

Click here

Click here

Click here

MSP430F5636

Click here

Click here

Click here

Click here

Click here

MSP430F5635

Click here

Click here

Click here

Click here

Click here

MSP430F5634

Click here

Click here

Click here

Click here

Click here

MSP430F5633

Click here

Click here

Click here

Click here

Click here

MSP430F5632

Click here

Click here

Click here

Click here

Click here

MSP430F5631

Click here

Click here

Click here

Click here

Click here

MSP430F5630

Click here

Click here

Click here

Click here

Click here

10.6 サポート・リソース
TI E2E™ サポート ・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。
リンクされているコンテンツは、該当する貢献者により、現状のまま提供されるものです。これらは TI の仕様を構成するものではなく、必ずしも TI の見解を反映したものではありません。TI の使用条件を参照してください。

10.7 Trademarks
MSP 430™, MicroStar Junior™, MSP430™, MSP430Ware™, EnergyTrace™, ULP Advisor™, Code Composer
Studio™, and TI E2E™ are trademarks of Texas Instruments.
すべての商標は、それぞれの所有者に帰属します。

10.8 静電気放電に関する注意事項

この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい ESD 対策をとらないと、デバイスを破損するおそれがあります。
ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。

10.9 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (asdefined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.

10.10 用語集
TI 用語集

この用語集には、用語や略語の一覧および定義が記載されています。

Copyright © 2021 Texas Instruments Incorporated

Submit Document Feedback

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634
MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

111

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

www.tij.co.jp

JAJSG45G – MAY 2010 – REVISED SEPTEMBER 2020

11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

112

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Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634
MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

PACKAGE OPTION ADDENDUM
www.ti.com

28-Aug-2024

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking(3)

Samples

(4/5)

(6)

MSP430F5630IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430F5630

Samples

MSP430F5631IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430F5631

Samples

MSP430F5632IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430F5632

Samples

MSP430F5632IPZR

ACTIVE

LQFP

PZ

100

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430F5632

Samples

MSP430F5632IZCARACTIVE

NFBGA

ZCA

113

2500

RoHS & GreenSNAGCU

Level-3-260C-168 HR-40 to 85

F5632

Samples

MSP430F5633IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430F5633

Samples

MSP430F5633IPZR

ACTIVE

LQFP

PZ

100

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430F5633

Samples

MSP430F5634IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430F5634

Samples

MSP430F5635IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430F5635

Samples

MSP430F5635IPZR

ACTIVE

LQFP

PZ

100

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430F5635

Samples

MSP430F5635IZCARACTIVE

NFBGA

ZCA

113

2500

RoHS & GreenSNAGCU

Level-3-260C-168 HR-40 to 85

F5635

Samples

MSP430F5635IZCATACTIVE

NFBGA

ZCA

113

250

RoHS & GreenSNAGCU

Level-3-260C-168 HR-40 to 85

F5635

Samples

MSP430F5636IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430F5636

Samples

MSP430F5636IPZRACTIVE

LQFP

PZ

100

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430F5636

Samples

MSP430F5636IZQWROBSOLETE

BGA
MICROSTARJUNIOR

ZQW

113

TBD

Call TI

Call TI

MSP430F5637IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430F5637

Samples

MSP430F5637IPZR

ACTIVE

LQFP

PZ

100

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430F5637

Samples

MSP430F5638IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430F5638

Samples

MSP430F5638IPZR

ACTIVE

LQFP

PZ

100

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

M430F5638

Samples

Addendum-Page 1

M430F5636

PACKAGE OPTION ADDENDUM
www.ti.com

Orderable Device

28-Aug-2024

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking(3)

Samples

(4/5)

(6)

MSP430F5638IZCARACTIVE

NFBGA

ZCA

113

2500

RoHS & GreenSNAGCU

Level-3-260C-168 HR-40 to 85

F5638

Samples

MSP430F5638IZCATACTIVE

NFBGA

ZCA

113

250

RoHS & GreenSNAGCU

Level-3-260C-168 HR-40 to 85

F5638

Samples

MSP430F5638IZQWROBSOLETE

BGA
MICROSTARJUNIOR

ZQW

113

TBD

Call TI

Call TI-40 to 85

M430F5638

MSP430F5638IZQWTOBSOLETE

BGA
MICROSTARJUNIOR

ZQW

113

TBD

Call TI

Call TI-40 to 85

M430F5638(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 2

PACKAGE OPTION ADDENDUM
www.ti.com

28-Aug-2024

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION
www.ti.com

5-Dec-2023

TAPE AND REEL INFORMATIONREEL DIMENSIONSTAPE DIMENSIONS
K0

P1

B0 W
Reel
DiameterCavity
A0
B0
K0
W
P1

A0

Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers

Reel Width (W1)QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes

Q1

Q2

Q1

Q2

Q3

Q4

Q3

Q4

User Direction of Feed

Pocket Quadrants*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)
17.0

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

17.0

2.1

20.0

24.0

Q2

MSP430F5632IPZR

LQFP

PZ

100

1000

330.0

24.4

MSP430F5632IZCAR

NFBGA

ZCA

113

2500

330.0

16.4

7.3

7.3

1.5

12.0

16.0

Q1

MSP430F5633IPZR

LQFP

PZ

100

1000

330.0

24.4

17.0

17.0

2.1

20.0

24.0

Q2

MSP430F5635IPZR

LQFP

PZ

100

1000

330.0

24.4

17.0

17.0

2.1

20.0

24.0

Q2

MSP430F5635IZCAR

NFBGA

ZCA

113

2500

330.0

16.4

7.3

7.3

1.5

12.0

16.0

Q1

MSP430F5637IPZR

LQFP

PZ

100

1000

330.0

24.4

17.0

17.0

2.1

20.0

24.0

Q2

MSP430F5638IZCAR

NFBGA

ZCA

113

2500

330.0

16.4

7.3

7.3

1.5

12.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

5-Dec-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

W

L

H

*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)

MSP430F5632IPZR

LQFP

PZ

100

1000

350.0

350.0

43.0

MSP430F5632IZCAR

NFBGA

ZCA

113

2500

350.0

350.0

43.0

MSP430F5633IPZR

LQFP

PZ

100

1000

350.0

350.0

43.0

MSP430F5635IPZR

LQFP

PZ

100

1000

350.0

350.0

43.0

MSP430F5635IZCAR

NFBGA

ZCA

113

2500

350.0

350.0

43.0

MSP430F5637IPZR

LQFP

PZ

100

1000

350.0

350.0

43.0

MSP430F5638IZCAR

NFBGA

ZCA

113

2500

350.0

350.0

43.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

5-Dec-2023

TRAY
L - Outer tray length without tabs

KO Outertray
height

WOuter
tray
width
Text

P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

DevicePackage
Name

Package
Type

Pins

SPQ

Unit arrayMax
L (mm) W
matrix temperature
(mm)
(°C)

K0
(µm)

P1
(mm)

CL
(mm)

CW
(mm)

MSP430F5630IPZ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

MSP430F5631IPZ

PZ

LQFP

100

90

6 x 15150

MSP430F5632IPZ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

315

135.9

7620

20.3

15.4

MSP430F5632IZCAR

ZCA

NFBGA

113

2500

10 x 26

15.45

150

315

135.9

7620

11.8

10

10.35

MSP430F5633IPZ

PZ

LQFP

100

90

MSP430F5634IPZ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

MSP430F5635IPZ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

MSP430F5635IZCAR

ZCA

NFBGA

113

2500

10 x 26

150

315

135.9

7620

11.8

10

10.35

MSP430F5635IZCAT

ZCA

NFBGA

113

250

10 x 26

150

315

135.9

7620

11.8

10

10.35

MSP430F5636IPZ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

MSP430F5637IPZ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

MSP430F5638IPZ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

MSP430F5638IZCAR

ZCA

NFBGA

113

2500

10 x 26

150

315

135.9

7620

11.8

10

10.35

MSP430F5638IZCAT

ZCA

NFBGA

113

250

10 x 26

150

315

135.9

7620

11.8

10

10.35

Pack Materials-Page 3

MECHANICAL DATAMTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996

PZ (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27
0,17

0,50
75

0,08 M

51

76

50

100

26

1

0,13 NOM

25
12,00 TYP

Gage Plane

14,20
SQ
13,80
16,20
SQ
15,80

0,05 MIN

1,45
1,35

0,25
0°– 7°

0,75
0,45
Seating Plane
0,08

1,60 MAX

4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026

POST OFFICE BOX 655303• DALLAS, TEXAS 75265

1

PACKAGE OUTLINENFBGA - 1 mm max height

ZCA0113A

PLASTIC BALL GRID ARRAY
A

7.1
6.9

B

BALL A1 CORNER
7.1
6.9

1 MAX

C

0.25
0.15

SEATING PLANE
0.08 CBALL TYP

5.5
TYP
SYMM

(0.75) TYP

M(0.75) TYP

L
K
J
H

5.5
TYP

SYMM

G
F
E
D

113X Ø0.35
0.25

C
B
A

0.5 TYP

1

2

3

4

5

6

7

8

9 10 11 12

0.15
0.05

C A B
C

0.5 TYP

4225149/A 08/2019

NOTES:
1.
2.

NanoFree is a trademark of Texas Instruments.

All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUTNFBGA - 1 mm max height

ZCA0113A

PLASTIC BALL GRID ARRAY(0.5) TYP
(0.5) TYP

A

1

2

3

4

5

6

7

8

9

10 11 12B
C
DE

113X (Ø0.25)
SYMM

F
G
H
J
K
L
M

SYMM

LAND PATTERN EXAMPLESCALE: 10X

0.05 MAXALL AROUNDEXPOSED
METAL(Ø 0.25)METAL
SOLDER MASKOPENINGNON- SOLDER MASKDEFINED(PREFERRED)

0.05 MIN
ALL AROUNDMETAL UNDERSOLDER MASK(Ø 0.25)
SOLDER MASKOPENINGEXPOSEDMETALSOLDER MASKDEFINEDSOLDER MASK DETAILSNOT TO SCALE

4225149/A 08/2019

NOTES: (continued)
3.

Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGNNFBGA - 1 mm max height

ZCA0113A

PLASTIC BALL GRID ARRAY(0.5) TYP
(0.5) TYP

A

1

2

3

4

5

6

7

8

9

10 11 12B
C

(R0.05)

D
E

SYMM

F
G
H
J

METAL TYP

K
L
M

113X ( 0.25)
SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.100 mm THICK STENCILSCALE: 10X

4225149/A 08/2019

NOTES: (continued)
4.

Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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