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参考資料

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

MSP430F673x、、MSP430F672x ミクスト・シグナル・マイクロコントローラ
1 デバイスの概要
1.1

特長

1

• 低い電源電圧範囲: 3.6Vから最低1.8Vまで• 超低消費電力– アクティブ・モード(AM)：すべてのシステム・クロックがアクティブ：
265µA/MHz (8MHz、3.0V)、フラッシュ・プログラム
実行時（標準値）
140µA/MHz (8MHz、3.0V)、RAMプログラム実行
時（標準値）– スタンバイ・モード(LPM3)：
リアルタイム・クロック(RTC)（水晶振動子を使用）、ウォッチドッグ、および電源スーパーバイザが動作、RAMデータ完全保持、高速ウェークアップ：
1.7µA (2.2V)、2.5µA (3.0V)（標準値）– オフ・モード(LPM4)：RAMデータ完全保持、電源スーパーバイザが動作、高速ウェークアップ：
1.6µA (3.0V)（標準値）– シャットダウンRTCモード(LPM3.5)：
シャットダウン・モード、リアルタイム・クロック(RTC)（水晶振動子を使用）が動作：
1.24µA (3.0V)（標準値）– シャットダウン・モード(LPM4.5)：0.78µA (3.0V)（標準値）• スタンバイ・モードから3µsでウェークアップ(標準値)• 16ビットRISCアーキテクチャ、拡張メモリ、最大25MHzのシステム・クロック• 柔軟な電源管理システム– プログラム可能な、レギュレートされたコア電源電圧を持つ、完全に統合されたLDO– 電源電圧の管理、監視、およびブラウンアウト– 最大2つの補助電源からのシステム動作• 統合クロック・システム– FLL制御ループによる周波数安定化– 低電力、低周波数の内部クロック・ソース(VLO)– 低周波数のトリムされた内部基準ソース(REFO)– 32kHzの水晶振動子(XT1)• 3つのキャプチャ/比較レジスタを搭載した16ビット・タイ
マ×1• 2つのキャプチャ/比較レジスタを搭載した16ビット・タイ
マ×3• 拡張ユニバーサル・シリアル通信インターフェイス– eUSCI_A0、eUSCI_A1、eUSCI_A2– 自動ボーレート検出機能付きの拡張UART– IrDAエンコーダおよびデコーダ– 同期SPI– eUSCI_B0– 複数のスレーブ・アドレシングを持つI2C– 同期SPI• パスワードで保護されたRTC、水晶振動子オフセット
較正および温度補償機能付き• バックアップ・サブシステム用の独立した電圧源– 32kHzの低周波数発振器(XT1)– リアルタイム・クロック– バックアップ・メモリ(4×16ビット)• 3つの24ビット・シグマ・デルタA/Dコンバータ(ADC)、
差動PGA入力付き• コントラスト制御を搭載し、8マルチプレクサ・モードで最大320セグメントに対応の内蔵LCDドライバ• ハードウェア乗算器で32ビットの演算をサポート• 10ビット、200kspsのADC– 内部基準– サンプル・アンド・ホールドおよび自動スキャン機能– 最大6つの外部チャネルと2つの内部チャネル、温度センサを含む• 3チャネルの内蔵DMA• シリアル・プログラミング機能を搭載、外部からのプロ
グラミング電圧は不要• 単相電子電力量計開発ツール（「 ツールとソフトウェ
ア」も参照）– EVM430-F6736 - MSP430F6736 EVM、メーター
用– MSP430™マイコン向けエネルギー測定デザイン・センター• デバイスの比較 に、供給中の製品ファミリを掲載• 100ピンと80ピンのLQFPパッケージで供給

1

英語版のTI製品についての情報を翻訳したこの資料は、製品の概要を確認する目的で便宜的に提供しているものです。該当する正式な英語版の最新情報は、www.ti.comで閲覧でき、その内容が常に優先されます。TIでは翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、必ず最新版の英語版をご参照くださいますようお願いいたします。
English Data Sheet: SLAS731

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

1.2
•
•

アプリケーション

2線式の単相メータ
3線式の単相メータ

1.3

www.tij.co.jp•

改ざん防止メータ

概要
TI MSPファミリの超低消費電力マイクロコントローラは複数のデバイスで構成され、それぞれが各種のアプリケー
ションを対象とする異なるペリフェラルを搭載しています。アーキテクチャに多様な低消費電力モードを組み合わ
せ、携帯型測定機器で長いバッテリ駆動時間を実現するように最適化しています。強力な16ビットRISC CPU、16
ビット・レジスタ、および定数ジェネレータが搭載されているため、最高水準のコード効率を実現できます。デジタル
制御発振器(DCO)により、低消費電力モードからアクティブ・モードへ3µs (標準値)でウェークアップできます。
MSP430F673xおよびMSP430F672xマイクロコントローラには、最大3つの高性能24ビット・シグマ・デルタADC、10ビットADC、4つの拡張ユニバーサル・シリアル通信インターフェイス（3つのeUSCI_Aモジュールと1つの
eUSCI_Bモジュール）、4つの16ビット・タイマ、ハードウェア乗算器、DMAモジュール、アラーム機能付きのRTC
モジュール、コントラスト制御を内蔵したLCDドライバ、補助電源システム、および100ピンのデバイスでは最大72本、80ピンのデバイスでは最大52本のI/Oピンが搭載されています。
モジュールの完全な説明については、『MSP430FR5xxおよびMSP430FR6xxファミリ ユーザー・ガイド』を参照してください。
製品情報 (1)型番

パッケージ

本体サイズ (2)

MSP430F6736IPZ

LQFP (100)14mm×14mm

MSP430F6736IPN

LQFP (80)12mm×12mm

(1)
(2)

2

最新の製品、パッケージ、および注文情報については、 8の「付録：パッケージ・オプション」、または
www.ti.comのTI Webサイトを参照してください。
ここに記載されているサイズは概略です。許容公差を含めたパッケージの寸法については、 8の「メカニカル・データ」を参照してください。

デバイスの概要

Copyright © 2011–2018, Texas Instruments Incorporated

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

機能ブロック図

1.4

DVCC DVSSAVCC AVSSAUXVCC3XOUT

AUXVCC2XIN

AUXVCC1

デバイスのすべてのバリエーションについて、PZパッケージでの機能ブロック図を、図 1-1に示します。

RST/NMIPA
P1.x P2.x

PB
P3.x P4.x

PC
P5.x P6.x

PD
P7.x P8.x

PE
P9.x

I/O Ports
P1, P2
2×8 I/OsInterrupt andWakeupI/O Ports
P3, P42×8 I/OsI/O Ports
P5, P62×8 I/OsI/O Ports
P7, P82×8 I/OsI/O Ports
P9
1×4 I/O

PA
1×16 I/Os

PB
1×16 I/Os

PC
1×16 I/Os

PD
1×16 I/Os

PE
1×4 I/O

TA0

TA1
TA2
TA3

eUSCI_A0
eUSCI_A1
eUSCI_A2

eUSCI_B0(32kHz)ACLK
Unified
Clock
System
SMCLK

SYS

128KB
96KB
64KB
32KB
16KB

8KB
4KB
2KB
1KB

Flash

RAM

PMM
Auxiliary
Supplies

SD24_B

ADC10_A

LCD_C

REF

3 channel
2 channel

10 bit200 ksps

8-mux
Up to 320
Segments

Reference
1.5 V, 2.0 V,
2.5 V

MCLK

Watchdog
MPY32

CRC16

Port
Mapping
Controller

CPUXV2andWorking
Registers(25 MHz)EEM(S: 3+1)

JTAG,
SBWInterface

LDO
SVM, SVSBORPort PJ

RTC_C

PJ.x

(UART,
IrDA,SPI)

Timer_A
2 CC
Registers

Timer_A
3 CC
Registers

2(SPI, I C)

DMA
3 channel

Copyright © 2018, Texas Instruments Incorporated

図 1-1. 機能ブロック図 - MSP430F673xIPZおおよびMSP430F672xIPZ

DVCC DVSSAVCC AVSSAUXVCC3XOUT

AUXVCC2XIN

AUXVCC1

デバイスのすべてのバリエーションについて、PNパッケージでの機能ブロック図を、図 1-2に示します。

RST/NMIPA
P1.x P2.x

PB
P3.x P4.x

PC
P5.x P6.x

I/O Ports
P1, P2
2×8 I/OsInterrupt andWakeupI/O Ports
P3, P42×8 I/OsI/O Ports
P5, P62×8 I/Os

PA
1×16 I/Os

PB
1×16 I/Os

PC
1×16 I/Os

TA0

TA1
TA2
TA3

eUSCI_A0
eUSCI_A1
eUSCI_A2

Timer_A
3 CC
Registers

Timer_A
2 CC
Registers(UART,
IrDA, SPI)

(32 kHz)

ACLK
Unified
Clock
System
SMCLK
MCLK

SYS

128KB
96KB
64KB
32KB
16KB

8KB
4KB
2KB
1KB

Flash

RAM

PMM
Auxiliary
Supplies

SD24_B

ADC10_A

LCD_C

REF

3 channel
2 channel

10 bit200 ksps

8-mux
Up to 320segments

Reference
1.5 V, 2.0 V,
2.5 V

DMA

Watchdog

3 Channel

Port
Mapping
Controller

CRC16

MPY32

CPUXV2andWorking
Registers(25 MHz)EEM(S: 3+1)

JTAG,
SBWInterface
Port PJ

LDO
SVM, SVS
BOR

RTC_C

eUSCI_B0(SPI, I2C)

PJ.x

Copyright © 2018, Texas Instruments Incorporated

図 1-2. 機能ブロック図 - MSP430F673xIPNおおよびMSP430F672xIPN

Copyright © 2011–2018, Texas Instruments Incorporated

デバイスの概要

3

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

Table of Contents
1

2
3

デバイスの概要 ............................................. 1

5.16

ADC10_A ............................................ 59

1.1

特長 ................................................... 1

5.17

REF.................................................. 61

1.2

アプリケーション ........................................ 2

5.18

Flash Memory ....................................... 62

1.3

概要 ................................................... 2

5.19

Emulation and Debug ............................... 62

1.4

機能ブロック図 ......................................... 3

5

6.1

CPU ................................................. 63

6.2

Instruction Set ....................................... 64

Related Products ..................................... 7

6.3

Operating Modes .................................... 65

Terminal Configuration and Functions .............. 8

6.4

Interrupt Vector Addresses.......................... 66

4.1

Pin Diagrams ......................................... 8

6.5

Memory Organization ............................... 67

4.2

Signal Descriptions .................................. 12

6.6

Bootloader (BSL) .................................... 69

Specifications ........................................... 24

6.7

JTAG Operation ..................................... 69

5.1

Absolute Maximum Ratings ......................... 24

6.8

Flash Memory ....................................... 70

5.2

ESD Ratings ........................................ 24

6.9

RAM ................................................. 70

5.3
5.4

Recommended Operating Conditions ...............
Active Mode Supply Current Into VCC Excluding
External Current .....................................
Low-Power Mode Supply Currents (Into VCC)
Excluding External Current..........................
Low-Power Mode With LCD Supply Currents (Into
VCC) Excluding External Current ....................

6.10

Backup RAM ........................................ 70

6.11

Peripherals .......................................... 71

6.12

Input/Output Diagrams .............................. 95

6.13

Device Descriptors (TLV) .......................... 127

5.5
5.6

24
26
27

7

デバイスおよびドキュメントのサポート .................. 129
使い始めと次の手順................................. 129

28

7.1

5.7

Thermal Resistance Characteristics ................ 29

7.2

Device Nomenclature .............................. 129

5.8

Digital I/O Ports ..................................... 30

7.3

ツールとソフトウェア ................................. 131

5.9

Clock Specifications ................................. 35

7.4

ドキュメントのサポート ................................ 133

5.10

Power-Management Module (PMM) ................ 38

7.5

関連リンク ........................................... 134

5.11

Auxiliary Supplies ................................... 41

7.6

Community Resources............................. 134

5.12

Timer_A ............................................. 44

7.7

商標 ................................................ 134

5.13

eUSCI ............................................... 44

7.8

静電気放電に関する注意事項 ...................... 135

5.14

LCD Controller ...................................... 50

7.9

Export Control Notice .............................. 135

5.15

SD24_B ............................................. 52

7.10

Glossary............................................ 135

84

Detailed Description ................................... 63

改訂履歴 .................................................... 5
Device Comparison ..................................... 6
3.1

4

6

Table of Contents

メカニカル、パッケージ、および注文情報 .............. 136

Copyright © 2011–2018, Texas Instruments Incorporated

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.ti.com

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

2 改訂履歴
資料番号末尾の英字は改訂を表しています。その改訂履歴は英語版に準じています。
2013年
年2月
月28日
日発行分から2018年
年09月
月28日
日発行分への変更
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•

Page

全体を通してドキュメントのフォーマットと編成を変更、セクションの番号追加も含む ............................................. 1「特長」に、開発ツールとデザイン・センターへのリンクを追加................................................................................................................................... 1「製品情報」表を追加 .................................................................................................................. 2
1.4「機能ブロック図」で、AUXVCC1、AUXVCC2、AUXVCC3ピンの名前を訂正................................................ 3
Added Section 3 and moved Table 3-1 to it ....................................................................................... 6
Added Section 3.1, Related Products ............................................................................................. 7
Added note to RST/NMI/SBWTDIO pin in Table 4-3, Terminal Functions, PZ Package .................................. 17
Added note to RST/NMI/SBWTDIO pin in Table 4-4, Terminal Functions, PN Package .................................. 22
Added typical conditions statements at the beginning of Section 5, Specifications ........................................ 24
Moved all electrical specifications to Section 5, Specifications ............................................................... 24
Added SD24_B input pins and AUXVCCx pins to exception list on "Voltage applied to pins" parameter, andadded SD24_B input pin limits in "Diode current at pins" parameter in Section 5.1, Absolute Maximum Ratings ..... 24
Added Section 5.2, ESD Ratings.................................................................................................. 24
Added note on CVCORE in Section 5.3, Recommended Operating Conditions ............................................... 24
Added Section 5.7, Thermal Resistance Characteristics ...................................................................... 29
Added note to RPull in Table 5-1, Schmitt-Trigger Inputs – General-Purpose I/O ........................................... 30
Changed TYP value of CL,eff with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF in Table 5-7,
Crystal Oscillator, XT1, Low-Frequency Mode .................................................................................. 35
Corrected the formula in note (1) [added "/ (85ºC – (–40ºC)"] in Table 5-8, Internal Very-Low-Power LowFrequency Oscillator (VLO) ........................................................................................................ 36
Corrected the formula in note (1) [added "/ (85ºC – (–40ºC)"] in Table 5-9, Internal Reference, Low-Frequency
Oscillator (REFO) ................................................................................................................... 36
Changed the MIN value of the V(DVCC_BOR_hys) parameter from 60 mV to 50 mV in Table 5-11, PMM, Brownout
Reset (BOR) ........................................................................................................................ 38
Updated notes (1) and (2) and added note (3) in Table 5-17, Wake-up Times From Low-Power Modes andReset ................................................................................................................................. 40
Corrected the names of the AUXVCC1, AUXVCC2, and AUXVCC3 pins in Auxiliary Supplies section ................ 41
Corrected the name of the AUXCHCx bit in the Test Conditions of Table 5-25, Auxiliary Supplies, Charge
Limiting Resistor ..................................................................................................................... 43
Replaced fFrame parameter with fLCD, fFRAME,4mux, and fFRAME,8mux parameters in Table 5-33, LCD_C
Recommended Operating Conditions ............................................................................................ 50
Removed ADC10DIV from the formula for the TYP value in the second row of the tCONVERT parameter in Table 544, 10-Bit ADC, Timing Parameters, because ADC10CLK is after division ................................................. 59
Updated Test Conditions for all parameters in Table 5-45, 10-Bit ADC, Linearity Parameters: Changed from"CVREF+ = 20 pF" to "CVeREF+ = 20 pF"; Changed from "(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–)" to"1.4 V ≤ (VeREF+ – VeREF–)"; Added "CVeREF+ = 20 pF" to EI Test Conditions ................................................. 60
Added "ADC10SREFx = 11b" to Test Conditions for EG and ET in Table 5-45 ............................................. 60
Throughout document, changed all instances of "bootstrap loader" to "bootloader" ....................................... 69
Corrected spelling of NMIIFG in 表 6-11, System Module Interrupt Vector Registers ..................................... 75
Removed mention of real-time clock mode (also called counter mode) in 6.11.21, Real-Time Clock (RTC_C)(feature is not supported in this device) .......................................................................................... 80
Removed SD24BTRGCTL, SD24BTRGOSR, and SD24BTRGPRE registers (not supported) in 表 6-55, SD24_B
Registers ............................................................................................................................. 93
7「デバイスおよびドキュメントのサポート」セクションを追加し、「デバイスおよび開発ツールの表記規則」および「商標」セ
クションを、そのセクションに移動 .................................................................................................. 129
従来の「開発ツールのサポート」セクションを 7.3「ツールとソフトウェア」セクションに入れ替え ................................ 131
8「メカニカル、パッケージ、および注文情報」を追加 ............................................................................. 136

改訂履歴Submit Documentation Feedback
Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730
MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

Copyright © 2011–2018, Texas Instruments Incorporated

5

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.ti.com

3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Family Members (1) (2)
DEVICE

FLASH
(KB)

SRAM
(KB)

SD24_BCONVERTERS

ADC10_ACHANNELS

Timer_A (3)eUSCI_A:
UART, IrDA,
SPI

eUSCI_B:
SPI, I2C

I/Os

PACKAGEMSP430F6736IPZ

128

8

3

6 ext, 2 int

3, 2, 2, 2

3

1

72

100 PZMSP430F6735IPZ

128

4

3

6 ext, 2 int

3, 2, 2, 2

3

1

72

100 PZMSP430F6734IPZ

96

4

3

6 ext, 2 int

3, 2, 2, 2

3

1

72

100 PZMSP430F6733IPZ

64

4

3

6 ext, 2 int

3, 2, 2, 2

3

1

72

100 PZMSP430F6731IPZ

32

2

3

6 ext, 2 int

3, 2, 2, 2

3

1

72

100 PZMSP430F6730IPZ

16

1

3

6 ext, 2 int

3, 2, 2, 2

3

1

72

100 PZMSP430F6726IPZ

128

8

2

6 ext, 2 int

3, 2, 2, 2

3

1

72

100 PZMSP430F6725IPZ

128

4

2

6 ext, 2 int

3, 2, 2, 2

3

1

72

100 PZMSP430F6724IPZ

96

4

2

6 ext, 2 int

3, 2, 2, 2

3

1

72

100 PZMSP430F6723IPZ

64

4

2

6 ext, 2 int

3, 2, 2, 2

3

1

72

100 PZMSP430F6721IPZ

32

2

2

6 ext, 2 int

3, 2, 2, 2

3

1

72

100 PZMSP430F6720IPZ

16

1

2

6 ext, 2 int

3, 2, 2, 2

3

1

72

100 PZMSP430F6736IPN

128

8

3

3 ext, 2 int

3, 2, 2, 2

3

1

52

80 PN

MSP430F6735IPN

128

4

3

3 ext, 2 int

3, 2, 2, 2

3

1

52

80 PN

MSP430F6734IPN

96

4

3

3 ext, 2 int

3, 2, 2, 2

3

1

52

80 PN

MSP430F6733IPN

64

4

3

3 ext, 2 int

3, 2, 2, 2

3

1

52

80 PN

MSP430F6731IPN

32

2

3

3 ext, 2 int

3, 2, 2, 2

3

1

52

80 PN

MSP430F6730IPN

16

1

3

3 ext, 2 int

3, 2, 2, 2

3

1

52

80 PN

MSP430F6726IPN

128

8

2

3 ext, 2 int

3, 2, 2, 2

3

1

52

80 PN

MSP430F6725IPN

128

4

2

3 ext, 2 int

3, 2, 2, 2

3

1

52

80 PN

MSP430F6724IPN

96

4

2

3 ext, 2 int

3, 2, 2, 2

3

1

52

80 PN

MSP430F6723IPN

64

4

2

3 ext, 2 int

3, 2, 2, 2

3

1

52

80 PN

MSP430F6721IPN

32

2

2

3 ext, 2 int

3, 2, 2, 2

3

1

52

80 PN

MSP430F6720IPN

16

1

2

3 ext, 2 int

3, 2, 2, 2

3

1

52

80 PN

(1)
(2)
(3)

6

For the most current package and ordering information, see the Package Option Addendum in 8, or see the TI website at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

Device Comparison

Copyright © 2011–2018, Texas Instruments Incorporated

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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.ti.com

3.1

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Related Products
For information about other devices in this family of products or related products, see the following links.
Products for TI Microcontrollers TI's low-power and high-performance MCUs, with wired and wirelessconnectivity options, are optimized for a broad range of applications.
Products for MSP430 Ultra-Low-Power Microcontrollers One platform. One ecosystem. Endlesspossibilities. Enabling the connected world with innovations in ultra-low-power
microcontrollers with advanced peripherals for precise sensing and measurement.
Companion Products for MSP430F6736 Review products that are frequently purchased or used withthis product.
Reference Designs for MSP430F6736 The TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.

Device Comparison
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

Copyright © 2011–2018, Texas Instruments Incorporated

7

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.ti.com

4 Terminal Configuration and Functions
4.1

Pin Diagrams

P6.1/S18

P6.2/S17

P6.3/S16

P6.4/S15

P6.5/S14

P6.6/S13

P6.7/S12

P7.0/S11

P7.1/S10

P7.2/S9

P7.3/S8

P7.4/S7P7.5/S6

P7.6/S5

P7.7/S4

P8.0/S3

P8.1/S2

P8.2/S1

P8.3/S0

TEST/SBWTCK

PJ.0/SMCLK/TDO

PJ.1/MCLK/TDI/TCLK

PJ.2/ADC10CLK/TMS

PJ.3/ACLK/TCK

RST/NMI/SBWTDIO

Figure 4-1 shows the pinout for the 100-pin PZ package. See Table 4-1 for differences between the
MSP430F673x and MSP430F672x devices in this package.

SD0P0

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75

DVSS

SD0N0

2

74

DVSYS

SD1P0

3

73

P6.0/S19

SD1N0

4

72

P5.7/S20

SD2P0

5

71

P5.6/S21

SD2N0

6

70

P5.5/S22

VREF

7

69

P5.4/S23

AVSS

8

68

P5.3/S24

AVCC

9

67

P5.2/S25

VASYS

10

66

P5.1/S26

P9.1/A5

11

65

P5.0/S27

P9.2/A4

12

64

P4.7/S28

P9.3/A3

13

63

P4.6/S29

P1.0/PM_TA0.0/VeREF-/A2

14

62

P4.5/S30

P1.1/PM_TA0.1/VeREF+/A1

15

61

P4.4/S31

P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0

1660

P4.3/S32

P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03

17

59

P4.2/S33

AUXVCC2

18

58

P4.1/S34

AUXVCC1

19

57

P4.0/S35

VDSYS

20

56

P3.7/PM_SD2DIO/S36

DVCC

21

55

P3.6/PM_SD1DIO/S37

DVSS

22

54

P3.5/PM_SD0DIO/S38

VCORE

23

53

P3.4/PM_SDCLK/S39

XIN

24

52

P3.3/PM_TA0.2
P3.2/PM_TACLK/PM_RTCCLK

P3.1/PM_TA2.1/BSL_RX

P3.0/PM_TA2.0/BSL_TX

P2.7/PM_TA1.1

P2.6/PM_TA1.0

P2.5/PM_UCA2CLK

P2.4/PM_UCA1CLK

P2.3/PM_UCA2TXD/PM_UCA2SIMO

P2.2/PM_UCA2RXD/PM_UCA2SOMI

P9.0/TACLK/RTCCLK

P8.7/TA2.1

P8.6/TA2.0

P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7

P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6

P1.7/PM_UCB0CLK/COM5

P1.6/PM_UCA0CLK/COM4

COM3

COM2

COM1

COM0

P8.5/TA1.1

P8.4/TA1.0

LCDCAP/R33

P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23

AUXVCC325
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13

XOUT

NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. This pinout shows the default mapping.
See 表 6-9 for details.
NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.

Figure 4-1. 100-Pin PZ Package (Top View)
8

Terminal Configuration and Functions

Copyright © 2011–2018, Texas Instruments Incorporated

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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.ti.com

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Table 4-1. Pinout Differences Between MSP430F673xIPZ and MSP430F672xIPZ (1)PIN NUMBER(1)

PIN NAME
MSP430F673xIPZ

MSP430F672xIPZ

1

SD0P0

SD0P0

2

SD0N0

SD0N0

3

SD1P0

SD1P0

4

SD1N0

SD1N0

5

SD2P0

NC

6

SD2N0

NC

7

VREF

VREF

53

P3.4/PM_SDCLK/S39

P3.4/PM_SDCLK/S39

54

P3.5/PM_SD0DIO/S38

P3.5/PM_SD0DIO/S38

55

P3.6/PM_SD1DIO/S37

P3.6/PM_SD1DIO/S37

56

P3.7/PM_SD2DIO/S36

P3.7/PM_NONE/S36

Signal names that differ between devices are indicated by italic typeface.

Terminal Configuration and Functions
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Copyright © 2011–2018, Texas Instruments Incorporated

9

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.ti.com

P5.2/S13

P5.3/S12

P5.4/S11

P5.5/S10

P5.6/S9

P5.7/S8

P6.0/S7

P6.1/S6

P6.2/S5

P6.3/S4

P6.4/S3

P6.5/S2

P6.6/S1

P6.7/S0

TEST/SBWTCK

PJ.0/SMCLK/TDO

PJ.1/MCLK/TDI/TCLK

PJ.2/ADC10CLK/TMS

PJ.3/ACLK/TCK

RST/NMI/SBWTDIO

Figure 4-2 shows the pinout for the 80-pin PN package. See Table 4-2 for differences between the
MSP430F673x and MSP430F672x devices in this package.

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

54

P4.5/S18

AVSS

8

53

P4.4/S19

AVCC

9

52

P4.3/S20

VASYS

10

51

P4.2/S21

P1.0/PM_TA0.0/VeREF-/A2

1150

P4.1/S22

P1.1/PM_TA0.1/VeREF+/A1

12

49

P4.0/S23

P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0

1348

P3.7/PM_SD2DIO/S24

P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03

14

47

P3.6/PM_SD1DIO/S25

AUXVCC2

15

46

P3.5/PM_SD0DIO/S26

AUXVCC1

16

45

P3.4/PM_SDCLK/S27

VDSYS

17

44

P3.3/PM_TA0.2/S28

DVCC

18

43

P3.2/PM_TACLK/PM_RTCCLK/S29

DVSS

19

42

P3.1/PM_TA2.1/S30/BSL_RX

41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

P3.0/PM_TA2.0/S31/BSL_TX

XIN

VCORE

P2.7/PM_TA1.1/S32

7

P2.6/PM_TA1.0/S33

P4.6/S17

VREF

P2.5/PM_UCA2CLK/S34

55

P2.4/PM_UCA1CLK/S35

6

P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36

P4.7/S16

SD2N0

P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37

56

P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38

5P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39

P5.0/S15

SD2P0

P1.7/PM_UCB0CLK/COM5

57

P1.6/PM_UCA0CLK/COM4

4

COM3

P5.1/S14

SD1N0

COM2

58

COM1

3

COM0

DVSYS

SD1P0

LCDCAP/R33

59

P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23

DVSS

2

P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13

60

SD0N0

AUXVCC3

1

XOUT

SD0P0

NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. This pinout shows the default mapping.
See 表 6-9 for details.
NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.

Figure 4-2. 80-Pin PN Package (Top View)

10

Terminal Configuration and Functions

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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.ti.com

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Table 4-2. Pinout Differences Between MSP430F673xIPN and
MSP430F672xIPN (1)PIN NUMBER(1)

PIN NAME
MSP430F673xIPN

MSP430F672xIPN

1

SD0P0

SD0P0

2

SD0N0

SD0N0

3

SD1P0

SD1P0

4

SD1N0

SD1N0

5

SD2P0

NC

6

SD2N0

NC

7

VREF

VREF

45

P3.4/PM_SDCLK/S27

P3.4/PM_SDCLK/S27

46

P3.5/PM_SD0DIO/S26

P3.5/PM_SD0DIO/S26

47

P3.6/PM_SD1DIO/S25

P3.6/PM_SD1DIO/S25

48

P3.7/PM_SD2DIO/S24

P3.7/PM_NONE/S24

Signal names that differ between devices are indicated by italic typeface.

Terminal Configuration and Functions
Submit Documentation Feedback
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

Copyright © 2011–2018, Texas Instruments Incorporated

11

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 20184.2

www.ti.com

Signal Descriptions
Table 4-3 describes the signals for all device variants in the PZ package. See Table 4-4 for signal
descriptions in the PN package.
Table 4-3. Terminal Functions, PZ Package
TERMINAL
NAME

NO.

I/O (1)DESCRIPTION

PZ

SD0P0

1

I

SD24_B positive analog input for converter 0 (2)

SD0N0

2

I

SD24_B negative analog input for converter 0 (2)

SD1P0

3

I

SD24_B positive analog input for converter 1 (2)

SD1N0

4

I

SD24_B negative analog input for converter 1 (2)

SD2P0

5

I

SD24_B positive analog input for converter 2 (2) (not available on F672x devices)

SD2N0

6

I

SD24_B negative analog input for converter 2 (2) (not available on F672x devices)

VREF

7

I

SD24_B external reference voltage

AVSS

8

Analog ground supply

AVCC

9

Analog power supply

VASYS

10

Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect
recommended capacitor value of CVSYS (see Table 5-18).

P9.1/A5

11

I/O

General-purpose digital I/O
Analog input A5 for 10-bit ADC

P9.2/A4

12

I/O

General-purpose digital I/O
Analog input A4 for 10-bit ADC

P9.3/A3

13

I/O

General-purpose digital I/O
Analog input A3 for 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output

P1.0/PM_TA0.0/VeREF-/A2

14

I/O

Negative terminal for the ADC reference voltage for an external applied reference
voltage
Analog input A2 for 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function

P1.1/PM_TA0.1/VeREF+/A1

15

I/O

Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
Positive terminal for the ADC reference voltage for an external applied reference voltage
Analog input A1 for 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function

P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0

16

I/O

Default mapping: eUSCI_A0 UART receive data; eUSCI_A0 SPI slave out/master in
Analog input A0 for 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function

P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03

17

AUXVCC2

18

Auxiliary power supply AUXVCC2AUXVCC1

19

Auxiliary power supply AUXVCC1

I/O

Default mapping: eUSCI_A0 UART transmit data; eUSCI_A0 SPI slave in/master out
Input/output port of lowest analog LCD voltage (V5)

(1)
(2)
12

I = input, O = output
Short unused analog input pairs and connect them to analog ground.
Terminal Configuration and Functions

Copyright © 2011–2018, Texas Instruments Incorporated

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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.ti.com

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Table 4-3. Terminal Functions, PZ Package (continued)
TERMINAL
NAME

NO.

I/O (1)DESCRIPTION

PZ
20Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect
recommended capacitor value of CVSYS (see Table 5-18).

DVCC

21

Digital power supply

DVSS

22

Digital ground supply

VCORE (4)

23

XIN

24

I

Input terminal for crystal oscillator

XOUT

25

O

Output terminal for crystal oscillator

AUXVCC3

26

VDSYS

(3)

Regulated core power supply (internal use only, no external current loading)

Auxiliary power supply AUXVCC3 for back up subsystem
General-purpose digital I/O with port interrupt and mappable secondary function

P1.4/PM_UCA1RXD/
PM_UCA1SOMI/LCDREF/R13

27

I/O

Default mapping: eUSCI_A1 UART receive data; eUSCI_A1 SPI slave out/master inExternal reference voltage input for regulated LCD voltage
Input/output port of third most positive analog LCD voltage (V3 or V4)
General-purpose digital I/O with port interrupt and mappable secondary function

P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23

28

I/O

Default mapping: eUSCI_A1 UART transmit data; eUSCI_A1 SPI slave in/master out
Input/output port of second most positive analog LCD voltage (V2)
LCD capacitor connection

LCDCAP/R33

29

I/O

Input/output port of most positive analog LCD voltage (V1)
CAUTION: This pin must be connected to DVSS if not used.

P8.4/TA1.0

30

I/O

General-purpose digital I/OTimer TA1 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O

P8.5/TA1.1

31

I/O

COM0

32

O

LCD common output COM0 for LCD backplane

COM1

33

O

LCD common output COM1 for LCD backplane

COM2

34

O

LCD common output COM2 for LCD backplane

COM3

35

O

LCD common output COM3 for LCD backplane

P1.6/PM_UCA0CLK/COM4

36

I/O

Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A0 clock input/output
LCD common output COM4 for LCD backplane
General-purpose digital I/O with port interrupt and mappable secondary function
P1.7/PM_UCB0CLK/COM5

37

I/O

Default mapping: eUSCI_B0 clock input/output
LCD common output COM5 for LCD backplane
General-purpose digital I/O with port interrupt and mappable secondary function

P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6

38

I/O

Default mapping: eUSCI_B0 SPI slave out/master in; eUSCI_B0 I2C clock
LCD common output COM6 for LCD backplane

(3)
(4)

The pins VDSYS and DVSYS must be connected externally on the board for proper device operation.
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
Terminal Configuration and Functions
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Copyright © 2011–2018, Texas Instruments Incorporated

13

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.ti.com

Table 4-3. Terminal Functions, PZ Package (continued)
TERMINAL
NAME

NO.

I/O (1)DESCRIPTIONPZ
General-purpose digital I/O with port interrupt and mappable secondary function

P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7

39

I/O

Default mapping: eUSCI_B0 SPI slave in/master out; eUSCI_B0 I2C data
LCD common output COM7 for LCD backplane

P8.6/TA2.0

40

I/O

General-purpose digital I/OTimer TA2 CCR0 capture: CCI0A input, compare: Out0 output

P8.7/TA2.1

41

I/O

General-purpose digital I/OTimer TA2 CCR1 capture: CCI1A input, compare: Out1 output
General-purpose digital I/O

P9.0/TACLK/RTCCLK

42

I/O

Timer clock input TACLK for TA0, TA1, TA2, TA3
RTCCLK clock output

P2.2/PM_UCA2RXD/
PM_UCA2SOMI

43

P2.3/PM_UCA2TXD/
PM_UCA2SIMO

44

P2.4/PM_UCA1CLK

45

I/O

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A2 UART receive data; eUSCI_A2 SPI slave out/master in

I/O

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A2 UART transmit data; eUSCI_A2 SPI slave in/master out

I/O

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A1 clock input/output

P2.5/PM_UCA2CLK

46

I/O

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A2 clock input/output

P2.6/PM_TA1.0

47

I/O

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output

P2.7/PM_TA1.1

48

I/O

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA1 capture CCR1: CCI1A input, compare: Out1 output
General-purpose digital I/O with mappable secondary function

P3.0/PM_TA2.0/BSL_TX

49

I/O

Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output
Bootloader: Data transmit
General-purpose digital I/O with mappable secondary function

P3.1/PM_TA2.1/BSL_RX

50

I/O

Default mapping: Timer TA2 capture CCR1: CCI1A input, compare: Out1 output
Bootloader: Data receive
General-purpose digital I/O with mappable secondary function

P3.2/PM_TACLK/PM_RTCCLK

51

I/O

P3.3/PM_TA0.2

52

I/O

Default mapping: Timer clock input TACLK for TA0, TA1, TA2, TA3; RTCCLK clock
outputGeneral-purpose digital I/O with mappable secondary function
Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output
General-purpose digital I/O with mappable secondary function

P3.4/PM_SDCLK/S39

53

I/O

Default mapping: SD24_B bitstream clock input/output
LCD segment output S39

14

Terminal Configuration and Functions

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.ti.com

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Table 4-3. Terminal Functions, PZ Package (continued)
TERMINAL
NAME

NO.

I/O (1)DESCRIPTIONPZ
General-purpose digital I/O with mappable secondary function

P3.5/PM_SD0DIO/S38

54

I/O

Default mapping: SD24_B converter-0 bitstream data input/output
LCD segment output S38
General-purpose digital I/O with mappable secondary function

P3.6/PM_SD1DIO/S37

55

I/O

Default mapping: SD24_B converter-1 bitstream data input/output
LCD segment output S37
General-purpose digital I/O with mappable secondary function

P3.7/PM_SD2DIO/S36

56

I/O

Default mapping: SD24_B converter-2 bitstream data input/output (not available on
F672x devices)
LCD segment output S36

P4.0/S35

57

I/O

General-purpose digital I/O
LCD segment output S35

P4.1/S34

58

I/O

General-purpose digital I/O
LCD segment output S34

P4.2/S33

59

I/O

General-purpose digital I/O
LCD segment output S33

P4.3/S32

60

I/O

General-purpose digital I/O
LCD segment output S32

P4.4/S31

61

I/O

General-purpose digital I/O
LCD segment output S31

P4.5/S30

62

I/O

General-purpose digital I/O
LCD segment output S30

P4.6/S29

63

I/O

General-purpose digital I/O
LCD segment output S29

P4.7/S28

64

I/O

General-purpose digital I/O
LCD segment output S28

P5.0/S27

65

I/O

General-purpose digital I/O
LCD segment output S27

P5.1/S26

66

I/O

General-purpose digital I/O
LCD segment output S26

P5.2/S25

67

I/O

General-purpose digital I/O
LCD segment output S25

P5.3/S24

68

I/O

General-purpose digital I/O
LCD segment output S24

P5.4/S23

69

I/O

General-purpose digital I/O
LCD segment output S23

Terminal Configuration and Functions
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Copyright © 2011–2018, Texas Instruments Incorporated

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.ti.com

Table 4-3. Terminal Functions, PZ Package (continued)
TERMINAL
NAME

P5.5/S22NO.

I/O (1)DESCRIPTION

PZ
70

I/O

General-purpose digital I/O
LCD segment output S22

P5.6/S21

71

I/O

General-purpose digital I/O
LCD segment output S21

P5.7/S20

72

I/O

General-purpose digital I/O
LCD segment output S20

I/O

General-purpose digital I/O

P6.0/S1973

DVSYS (3)74

Digital power supply for I/Os

DVSS

75

Digital ground supply

P6.1/S18

76

LCD segment output S19

I/O

General-purpose digital I/O
LCD segment output S18

P6.2/S17

77

I/O

General-purpose digital I/O
LCD segment output S17

P6.3/S16

78

I/O

General-purpose digital I/O
LCD segment output S16

P6.4/S15

79

I/O

General-purpose digital I/O
LCD segment output S15

P6.5/S1480

I/O

General-purpose digital I/O
LCD segment output S14

P6.6/S13

81

I/O

General-purpose digital I/O
LCD segment output S13

P6.7/S1282

I/O

General-purpose digital I/O
LCD segment output S12

P7.0/S11

83

I/O

General-purpose digital I/O
LCD segment output S11

P7.1/S1084

I/O

General-purpose digital I/O
LCD segment output S10

P7.2/S985

I/O

General-purpose digital I/O
LCD segment output S9

P7.3/S8

86

I/O

General-purpose digital I/O
LCD segment output S8

P7.4/S7

87

I/O

General-purpose digital I/O
LCD segment output S7

16

Terminal Configuration and Functions

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Table 4-3. Terminal Functions, PZ Package (continued)
TERMINAL
NAME

P7.5/S6NO.

I/O (1)DESCRIPTION

PZ
88

I/O

General-purpose digital I/O
LCD segment output S6

P7.6/S589

I/O

General-purpose digital I/O
LCD segment output S5

P7.7/S490

I/O

General-purpose digital I/O
LCD segment output S4

P8.0/S391

I/O

General-purpose digital I/O
LCD segment output S3

P8.1/S2

92

I/O

General-purpose digital I/O
LCD segment output S2

P8.2/S1

93

I/O

General-purpose digital I/O
LCD segment output S1

P8.3/S094

I/O

General-purpose digital I/O
LCD segment output S0

TEST/SBWTCK95

I

Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
General-purpose digital I/O

PJ.0/SMCLK/TDO

96

I/O

SMCLK clock output
Test data output
General-purpose digital I/O

PJ.1/MCLK/TDI/TCLK

97

I/O

MCLK clock output
Test data input or Test clock input
General-purpose digital I/O

PJ.2/ADC10CLK/TMS

98

I/O

ADC10_A clock output
Test mode selectGeneral-purpose digital I/O

PJ.3/ACLK/TCK

99

I/O

ACLK clock output
Test clock
Reset input active low (5)RST/NMI/SBWTDIO

100

I/O

Nonmaskable interrupt input
Spy-Bi-Wire data input/output(5)

When this pin is configured as reset, the internal pullup resistor is enabled by default.

Terminal Configuration and Functions
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Copyright © 2011–2018, Texas Instruments Incorporated

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.ti.com

Table 4-4 describes the signals for all device variants in the PN package. See Table 4-3 for signal
descriptions in the PZ package.
Table 4-4. Terminal Functions, PN Package
TERMINAL
NAME

NO.

I/O (1)DESCRIPTION

PN

SD0P0

1

I

SD24_B positive analog input for converter 0 (2)

SD0N0

2

I

SD24_B negative analog input for converter 0 (2)

SD1P0

3

I

SD24_B positive analog input for converter 1 (2)

SD1N0

4

I

SD24_B negative analog input for converter 1 (2)

SD2P0

5

I

SD24_B positive analog input for converter 2 (2) (not available on F672x devices)

SD2N0

6

I

SD24_B negative analog input for converter 2 (2) (not available on F672x devices)

VREF

7

I

SD24_B external reference voltage

AVSS

8

Analog ground supply

AVCC

9

Analog power supply

VASYS

10

Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect
recommended capacitor value of CVSYS (see Table 5-18).
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output

P1.0/PM_TA0.0/VeREF-/A2

11

I/O

Negative terminal for the ADC reference voltage for an external applied reference
voltage
Analog input A2 for 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function

P1.1/PM_TA0.1/VeREF+/A1

12

I/O

Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
Positive terminal for the ADC reference voltage for an external applied reference voltage
Analog input A1 for 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function

P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0

13

I/O

Default mapping: eUSCI_A0 UART receive data; eUSCI_A0 SPI slave out/master in
Analog input A0 for 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function

P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03

14

AUXVCC2

15

Auxiliary power supply AUXVCC2AUXVCC1

16

Auxiliary power supply AUXVCC1VDSYS (3)17

Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect
recommended capacitor value of CVSYS (see Table 5-18).

DVCC

18

Digital power supply

DVSS

19

Digital ground supply

I/O

Default mapping: eUSCI_A0 UART transmit data; eUSCI_A0 SPI slave in/master out
Input/output port of lowest analog LCD voltage (V5)

VCORE

(4)

20

Regulated core power supply (internal use only, no external current loading)

XIN

21

I

Input terminal for crystal oscillator

XOUT

22

O

Output terminal for crystal oscillator

AUXVCC3

23

(1)
(2)
(3)
(4)
18

Auxiliary power supply AUXVCC3 for back up subsystem

I = input, O = output
Short unused analog input pairs and connect them to analog ground.
The pins VDSYS and DVSYS must be connected externally on the board for proper device operation.
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
Terminal Configuration and Functions

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.ti.com

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Table 4-4. Terminal Functions, PN Package (continued)
TERMINAL
NAME

NO.

I/O (1)DESCRIPTIONPN
General-purpose digital I/O with port interrupt and mappable secondary function

P1.4/PM_UCA1RXD/
PM_UCA1SOMI/LCDREF/R13

24

I/O

Default mapping: eUSCI_A1 UART receive data; eUSCI_A1 SPI slave out/master inExternal reference voltage input for regulated LCD voltage
Input/output port of third most positive analog LCD voltage (V3 or V4)
General-purpose digital I/O with port interrupt and mappable secondary function

P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23

25

I/O

Default mapping: eUSCI_A1 UART transmit data; eUSCI_A1 SPI slave in/master out
Input/output port of second most positive analog LCD voltage (V2)
LCD capacitor connection

LCDCAP/R33

26

I/O

Input/output port of most positive analog LCD voltage (V1)
CAUTION: This pin must be connected to DVSS if not used.

COM0

27

O

LCD common output COM0 for LCD backplane

COM1

28

O

LCD common output COM1 for LCD backplane

COM2

29

O

LCD common output COM2 for LCD backplane

COM3

30

O

LCD common output COM3 for LCD backplane

P1.6/PM_UCA0CLK/COM4

31

I/O

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A0 clock input/output
LCD common output COM4 for LCD backplane
General-purpose digital I/O with port interrupt and mappable secondary function
P1.7/PM_UCB0CLK/COM5

32

I/O

Default mapping: eUSCI_B0 clock input/output
LCD common output COM5 for LCD backplane
General-purpose digital I/O with port interrupt and mappable secondary function

P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6/S39

33

I/O

Default mapping: eUSCI_B0 SPI slave out/master in; eUSCI_B0 I2C clock
LCD common output COM6 for LCD backplane
LCD segment output S39
General-purpose digital I/O with port interrupt and mappable secondary function

P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7/S38

34

I/O

Default mapping: eUSCI_B0 SPI slave in/master out; eUSCI_B0 I2C data
LCD common output COM7 for LCD backplane
LCD segment output S38
General-purpose digital I/O with port interrupt and mappable secondary function

P2.2/PM_UCA2RXD/
PM_UCA2SOMI/S37

35

I/O

Default mapping: eUSCI_A2 UART receive data; eUSCI_A2 SPI slave out/master in
LCD segment output S37
General-purpose digital I/O with port interrupt and mappable secondary function

P2.3/PM_UCA2TXD/
PM_UCA2SIMO/S36

36

I/O

Default mapping: eUSCI_A2 UART transmit data; eUSCI_A2 SPI slave in/master out
LCD segment output S36
General-purpose digital I/O with port interrupt and mappable secondary function

P2.4/PM_UCA1CLK/S35

37

I/O

Default mapping: eUSCI_A1 clock input/output
LCD segment output S35

Terminal Configuration and Functions
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Copyright © 2011–2018, Texas Instruments Incorporated

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.ti.com

Table 4-4. Terminal Functions, PN Package (continued)
TERMINAL
NAME

NO.

I/O (1)DESCRIPTIONPN
General-purpose digital I/O with port interrupt and mappable secondary function

P2.5/PM_UCA2CLK/S34

38

I/O

Default mapping: eUSCI_A2 clock input/output
LCD segment output S34
General-purpose digital I/O with port interrupt and mappable secondary function

P2.6/PM_TA1.0/S33

39

I/O

Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
LCD segment output S33
General-purpose digital I/O with port interrupt and mappable secondary function

P2.7/PM_TA1.1/S32

40

I/O

Default mapping: Timer TA1 capture CCR1: CCI1A input, compare: Out1 output
LCD segment output S32
General-purpose digital I/O with mappable secondary function

P3.0/PM_TA2.0/S31/BSL_TX

41

I/O

Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output
LCD segment output S31
Bootloader: Data transmit
General-purpose digital I/O with mappable secondary function

P3.1/PM_TA2.1/S30/BSL_RX

42

I/O

Default mapping: Timer TA2 capture CCR1: CCI1A input, compare: Out1 output
LCD segment output S30
Bootloader: Data receive
General-purpose digital I/O with mappable secondary function

P3.2/PM_TACLK/PM_RTCCLK/
S29

43

I/O

Default mapping: Timer clock input TACLK for TA0, TA1, TA2, TA3; RTCCLK clock
outputLCD segment output S29
General-purpose digital I/O with mappable secondary function

P3.3/PM_TA0.2/S28

44

I/O

Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output
LCD segment output S28
General-purpose digital I/O with mappable secondary function

P3.4/PM_SDCLK/S27

45

I/O

Default mapping: SD24_B bitstream clock input/output
LCD segment output S27
General-purpose digital I/O with mappable secondary function

P3.5/PM_SD0DIO/S26

46

I/O

Default mapping: SD24_B converter-0 bitstream data input/output
LCD segment output S26
General-purpose digital I/O with mappable secondary function

P3.6/PM_SD1DIO/S25

47

I/O

Default mapping: SD24_B converter-1 bitstream data input/output
LCD segment output S25
General-purpose digital I/O with mappable secondary function

P3.7/PM_SD2DIO/S24

48

I/O

Default mapping: SD24_B converter-2 bitstream data input/output (not available on
F672x devices)
LCD segment output S24

20

Terminal Configuration and Functions

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.ti.com

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Table 4-4. Terminal Functions, PN Package (continued)
TERMINAL
NAME

P4.0/S23NO.

I/O (1)DESCRIPTION

PN
49

I/O

General-purpose digital I/O
LCD segment output S23

P4.1/S22

50

I/O

General-purpose digital I/O
LCD segment output S22

P4.2/S21

51

I/O

General-purpose digital I/O
LCD segment output S21

P4.3/S20

52

I/O

General-purpose digital I/O
LCD segment output S20

P4.4/S19

53

I/O

General-purpose digital I/O
LCD segment output S19

P4.5/S18

54

I/O

General-purpose digital I/O
LCD segment output S18

P4.6/S17

55

I/O

General-purpose digital I/O
LCD segment output S17

P4.7/S16

56

I/O

General-purpose digital I/O
LCD segment output S16

P5.0/S15

57

I/O

General-purpose digital I/O
LCD segment output S15

P5.1/S14

58

I/O

General-purpose digital I/O
LCD segment output S14

DVSYS

(3)

59

Digital power supply for I/Os

DVSS

60

Digital ground supply

P5.2/S13

61

I/O

General-purpose digital I/O
LCD segment output S13

P5.3/S1262

I/O

General-purpose digital I/O
LCD segment output S12

P5.4/S11

63

I/O

General-purpose digital I/O
LCD segment output S11

P5.5/S1064

I/O

General-purpose digital I/O
LCD segment output S10

P5.6/S965

I/O

General-purpose digital I/O
LCD segment output S9

P5.7/S8

66

I/O

General-purpose digital I/O
LCD segment output S8

Terminal Configuration and Functions
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Copyright © 2011–2018, Texas Instruments Incorporated

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.ti.com

Table 4-4. Terminal Functions, PN Package (continued)
TERMINAL
NAME

P6.0/S7NO.

I/O (1)DESCRIPTION

PN
67

I/O

General-purpose digital I/O
LCD segment output S7

P6.1/S6

68

I/O

General-purpose digital I/O
LCD segment output S6

P6.2/S5

69

I/O

General-purpose digital I/O
LCD segment output S5

P6.3/S470

I/O

General-purpose digital I/O
LCD segment output S4

P6.4/S3

71

I/O

General-purpose digital I/O
LCD segment output S3

P6.5/S2

72

I/O

General-purpose digital I/O
LCD segment output S2

P6.6/S1

73

I/O

General-purpose digital I/O
LCD segment output S1

P6.7/S074

I/O

General-purpose digital I/O
LCD segment output S0

TEST/SBWTCK

75

I

Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
General-purpose digital I/O

PJ.0/SMCLK/TDO

76

I/O

SMCLK clock output
Test data output
General-purpose digital I/O

PJ.1/MCLK/TDI/TCLK

77

I/O

MCLK clock output
Test data input or Test clock input
General-purpose digital I/O

PJ.2/ADC10CLK/TMS

78

I/O

ADC10_A clock output
Test mode selectGeneral-purpose digital I/O

PJ.3/ACLK/TCK

79

I/O

ACLK clock output
Test clock
Reset input active low (5)RST/NMI/SBWTDIO

80

I/O

Nonmaskable interrupt input
Spy-Bi-Wire data input/output

(5)

22

When this pin is configured as reset, the internal pullup resistor is enabled by default.

Terminal Configuration and Functions

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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Terminal Configuration and Functions
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5 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.

5.1

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
Voltage applied at DVCC to DVSS

MIN

MAX

UNIT

–0.3

4.1

V

–0.3

VCC + 0.3

V(3)

All pins except VCORE , SD24_B input pins (SD0N0, SD0P0,
SD1N0, SD1P0, SD2N0, SD2P0) (4), AUXVCC1, AUXVCC2, and
AUXVCC3 (5)Voltage applied to pins (2)Diode current at pins

All pins except SD24_B input pins (SD0N0, SD0P0, SD1N0,
SD1P0, SD2N0, SD2P0)±2

SD0N0, SD0P0, SD1N0, SD1P0, SD2N0, SD2P0 (6)2Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
(6)
(7)

(7)

–55

mA

95

°C

150

°C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS = V(DVSS) = V(AVSS).
VCORE is for internal device use only. Do not apply external DC loading or voltage.
See Table 5-35 for SD24_B specifications.
See Table 5-18 for AUX specifications.
A protection diode is connected to VCC for the SD24_B input pins. No protection diode is connected to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2

ESD Ratings
VALUE

V(ESD)
(1)
(2)

5.3

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)±1000

Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)±250

Recommended Operating Conditions

Supply voltage during program execution and flash
programming, V(AVCC) = V(DVCC) = VCC (1) (2)

VCC

VSS

Supply voltage V(AVSS) = V(DVSS) = VSSTAOperating free-air temperature

TJ

Operating junction temperature

CVCORE

Recommended capacitor at VCORECDVCC/CVCORE

Capacitor ratio of DVCC to VCORE

(2)
(3)
24

V

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.

MIN

(1)

UNIT

NOM

MAX

PMMCOREVx = 0

1.8

3.6

PMMCOREVx = 0, 1

2.0

3.6

PMMCOREVx = 0, 1, 2

2.2

3.6

PMMCOREVx = 0, 1, 2, 3

2.4

3.6
0

UNIT

V

V

–40

85

°C

–40

85

°C

(3)

470

nF

10

TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC) can be
tolerated during power up and operation.
The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Table 5-13 threshold parameters forthe exact values and further details.
A capacitor tolerance of ±20% or better is required.
Specifications

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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Recommended Operating Conditions (continued)
MIN
PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V(default condition)
PMMCOREVx = 1,
Processor frequency (maximum MCLK frequency) (4) (5) 2.0 V ≤ VCC ≤ 3.6 V(see Figure 5-1)
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V

fSYSTEM

PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V

NOM

MAX

0

8.0

0

12.0

0

20.0

0

25.0

UNIT

MHz

ILOAD, DVCCD

Maximum load current that can be drawn from DVCC for core and IO(ILOAD = ICORE + IIO)

20mA

ILOAD, AUX1D

Maximum load current that can be drawn from AUXVCC1 for core and IO(ILOAD = ICORE + IIO)

20mA

ILOAD, AUX2D

Maximum load current that can be drawn from AUXVCC2 for core and IO(ILOAD = ICORE + IIO)

20mA

ILOAD, AVCCA

Maximum load current that can be drawn from AVCC for analog modules(ILOAD = IModules)

10

mA

ILOAD, AUX1A

Maximum load current that can be drawn from AUXVCC1 for analog modules(ILOAD = IModules)

5

mA

ILOAD, AUX2A

Maximum load current that can be drawn from AUXVCC2 for analog modules(ILOAD = IModules)

5

mA

(4)
(5)

The MSP430 CPU is clocked directly with MCLK. Both the high and low phases of MCLK must not exceed the pulse duration of thespecified maximum frequency.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

25

System Frequency - MHz

3
20
2

2, 3

1

1, 2

1, 2, 30, 1

0, 1, 20, 1, 2, 3

12

8

0

0
1.8

2.0

2.2

2.4

3.6

Supply Voltage - V
The numbers within the fields denote the supported PMMCOREVx settings.

Figure 5-1. Maximum System Frequency

Specifications
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Active Mode Supply Current Into VCC Excluding External Current

over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3)FREQUENCY (fDCO = fMCLK = fSMCLK)PARAMETER

IAM, Flash (4)IAM, RAM (5)

(1)
(2)
(3)
(4)
(5)

26

EXECUTIONMEMORY

Flash

RAM

VCC

3.0 V

3.0 V

PMMCOREVx

1 MHz

8 MHz

12 MHz20 MHz25 MHz

TYP

MAX

TYP

MAX

TYP

2.39

3.54

3.90

2.65

3.94

6.54

7.23

4.20

6.96

TYP

MAX

TYP

MAX

0

0.32

0.36

2.10

2.30

1

0.36

2

0.39

3

0.42

0

0.20

1

0.22

1.30

1.90

2

0.24

1.45

2.15

3.55

3

0.26

1.55

2.30

3.80

2.82
0.22

1.10

UNIT

MAX

mA
8.65

9.54

1.22
2.10

mA

4.0
4.70

5.30

All inputs are tied to 0 or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
Active mode supply current when program executes in flash at a nominal supply voltage of 3 V.
Active mode supply current when program executes in RAM at a nominal supply voltage of 3 V.

Specifications

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5.5

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
TEMPERATURE (TA)PARAMETER

VCC

PMMCOREVx

–40°C
TYP

ILPM0,1MHz

Low-power mode 0 (3) (4)

ILPM2

Low-power mode 2 (5) (4)

ILPM3,XT1LF

Low-power mode 3, crystal
mode (6) (4)

ILPM3,XT1LF

ILPM3,VLO

ILPM4

Low-power mode 3, crystal
mode (6) (4)Low-power mode 3,
VLO mode (7) (4)

ILPM4.5

MAX

MAX

TYP

TYP

UNIT
MAX

0

75

78

87

81

84

96

3

85

89

99

93

98

110

2.2 V

0

5.9

6.2

9

6.9

9.4

17

3.0 V

3

6.9

7.4

10

8.4

11

19

0

1.4

1.7

2.5

4.9

1

1.5

1.9

2.7

5.2

2

1.7

2.0

2.9

5.5

0

2.2

2.5

3.3

5.5

1

2.3

2.7

3.5

5.8

2

2.5

2.9

3.7

6.1

3

2.5

2.9

3.5

3.7

6.1

14.0

0

1.4

1.7

2.2

2.4

4.5

11.5

1

1.5

1.8

2.5

4.7

2

1.6

1.9

2.7

4.9

3

1.6

1.9

2.4

2.7

5.0

12.7

0

1.3

1.6

2.0

2.3

4.4

11.1

1

1.4

1.6

2.4

4.5

2

1.4

1.7

2.5

4.8

2.2 V

3.0 V

Low-power mode 4 (8) (4)

3.0 V

1.4

1.7

Low-power mode 3.5, RTC
active on AUXVCC3 (9)

2.2 V

0.65

0.80

3.0 V

1.16

1.24

3.0 V

0.70

0.78

Low-power mode 4.5

85°C
MAX

3.0 V

3.0 V

(10)

60°C

TYP

2.2 V

3
ILPM3.5

25°C

3.1

2.2

µA

µA

µA

12.7
µA

µA

µA

2.5

4.8

0.90

1.30

12.2

2.05

1.43

1.87

2.71

1.05

0.90

1.20

1.85

µA
µA

(1)
(2)

All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz(4) Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
(5) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low-frequency crystal operation (XTS = 0,
XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO setting= 1-MHz operation, DCO bias generator enabled.
(6) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low-frequency crystal operation (XTS = 0,
XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz(7) Current for watchdog timer clocked by ACLK included. RTC is disabled (RTCHOLD = 1). ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz(9) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC active on AUXVCC3 supply(10) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, PMMREGOFF = 1

Specifications
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Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
TEMPERATURE (TA)PARAMETER

VCC

PMMCOREVx

–40°C
TYP

ILPM3
LCD,
int. bias

Low-power mode 3(LPM3) current, LCD 4mux mode, internalbiasing, charge pumpdisabled (3) (4)

ILPM3
LCD,
int. bias

Low-power mode 3(LPM3) current, LCD 4mux mode, internalbiasing, charge pumpdisabled (3) (4)

2.2 V

3.0 V

2.2 V
ILPM3
LCD,CP

(1)
(2)
(3)

(4)
(5)

28

Low-power mode 3(LPM3) current, LCD 4mux mode, internalbiasing, charge pumpenabled (3) (5)

3.0 V

MAX

25°C

60°C

TYP

MAX

TYP

3.6

85°C
MAX

UNIT

TYP

MAX

3.8

5.8

12.2

4.0

6.0

0

2.4

2.9

1

2.5

3.1

2

2.6

3.3

3.9

4.2

6.3

13.4

0

2.8

3.2

3.9

4.1

6.4

13.3

1

2.9

3.4

4.3

6.7

2

3.1

3.6

4.5

7.0

3

3.1

3.6

4.5

7.0

0

3.8

1

3.9

2

4.0

0

4.0

1

4.1

2

4.2

3

4.2

4.5

µA

µA
14.7

µA

All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low-frequency crystal operation (XTS = 0,
XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pumpdisabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2, ... = 0 and odd segments S1, S3, ... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pumpenabled), VLCDx = 1000 (VLCD = 3 V, typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2, ... = 0 and odd segments S1, S3, ... = 1. No LCD panel load.

Specifications

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5.7

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Thermal Resistance Characteristics
THERMAL METRIC (1) (2)RθJA

Junction-to-ambient thermal resistance, still air

RθJC(TOP)

Junction-to-case (top) thermal resistanceRθJC(BOTTOM)

Junction-to-case (bottom) thermal resistanceRθJB

Junction-to-board thermal resistanceΨJT

Junction-to-package-top thermal characterization parameter

ΨJB

Junction-to-board thermal characterization parameter

(1)
(2)

(3)

VALUE
LQFP 80 (PN)

46.3

LQFP 100 (PZ)

45.6

LQFP 80 (PN)

11.5

LQFP 100 (PZ)

11.0

LQFP 80 (PN)

N/A (3)

LQFP 100 (PZ)

N/A

LQFP 80 (PN)

21.9

LQFP 100 (PZ)

23.4

LQFP 80 (PN)

0.5

LQFP 100 (PZ)

0.4

LQFP 80 (PN)

21.6

LQFP 100 (PZ)

23.0

UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W

For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
N/A = not applicableSpecifications
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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 20185.8

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Digital I/O Ports
Table 5-1 lists the characteristics of the schmitt-trigger Inputs.
Table 5-1. Schmitt-Trigger Inputs – General-Purpose I/Oover recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VIT+

Positive-going input threshold voltage

VIT–

Negative-going input threshold voltage

Vhys

Input voltage hysteresis (VIT+ – VIT–)

RPull

Pullup or pulldown resistor (1)For pullup: VIN = VSS
For pulldown: VIN = VCC

CI

Input capacitance

VIN = VSS or VCC

(1)

VCC

MIN

TYP

1.8 V

0.80

1.40

3V

1.50

2.10

1.8 V

0.45

1.00

3V

0.75

1.65

1.8 V

0.3

0.85

3V

0.4

1.0

20

35

MAX

UNIT
V
V
V

50

kΩ

5

pF

Also applies to RST pin when pullup or pulldown resistor is enabled.

Table 5-2 lists the characteristics of the P1 and P2 inputs.
Table 5-2. Inputs – Ports P1 and P2 (1)over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)t(int)(1)(2)

PARAMETERTEST CONDITIONS

VCC

MIN

External interrupt timing (2)Port P1, P2: P1.x to P2.x, External trigger pulse duration
to set interrupt flag

2.2 V, 3 V

20

MAX

UNIT
ns

Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It might be set by trigger signals
shorter than t(int).

Table 5-3 lists the characteristics of the GPIO leakage current.
Table 5-3. Leakage Current – General-Purpose I/Oover recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)(1)(2)

TEST CONDITIONS

VCC

See (1) (2)High-impedance leakage current

MIN

1.8 V, 3 V

MAX

UNIT

±50

nA

The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor isdisabled.

Table 5-4 lists the characteristics of the full drive strength GPIO output.
Table 5-4. Outputs – General-Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS
I(OHmax) = –3 mA (1)VOH

High-level output voltage

I(OHmax) = –10 mA (1)
I(OHmax) = –5 mA (1)
I(OHmax) = –15 mA (1)I(OLmax) = 3 mA (2)VOL

Low-level output voltage

I(OLmax) = 10 mA (3)I(OLmax) = 5 mA

(2)
(3)
30

1.8 V
3V
1.8 V

(2)

I(OLmax) = 15 mA (3)
(1)

VCC

3V

MIN

MAX

VCC – 0.25

VCC

VCC – 0.60

VCC

VCC – 0.25

VCC

VCC – 0.60

VCC

VSS

VSS + 0.25

VSS

VSS + 0.60

VSS

VSS + 0.25

VSS

VSS + 0.60

UNIT

V

V

The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.
See Section 5.3 for more details.
The maximum total current, I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.
The maximum total current, I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified.
Specifications

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5.8.1

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Typical Characteristics – General-Purpose I/O (Full Drive Strength)
0

-10

-5

IOH – High-Level Output Current – mA

IOH – High-Level Output Current – mA

0

-10

-15
TA = 85°C

-20

-20

-30

-40
TA = 85°C-50

TA = 25°C

TA = 25°C
-60

-25
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0

1.8

0.5

VCC = 1.8 V

Full Drive Strength

Figure 5-2. High-Level Output Current vs High-Level Output
Voltage

1.5

2

VCC = 3 V

2.5

3Full Drive Strength

Figure 5-3. High-Level Output Current vs High-Level Output
Voltage
60

25

50

20

IOL – Low-Level Output Current – mA

IOL – Low-Level Output Current – mA

1

VOH – High-Level Output Voltage – V

VOH – High-Level Output Voltage – V

TA = 25°C
TA = 85°C
15

10

5

TA = 25°C
TA = 85°C
40

30

20

10

0

0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

0

0.5

VCC = 1.8 V

Full Drive Strength

Figure 5-4. Low-Level Output Current vs Low-Level Output
Voltage

1

1.5

2

2.5

VCC = 3 V

Full Drive Strength

Figure 5-5. Low-Level Output Current vs Low-Level Output
VoltageSpecifications
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VOL – Low-Level Output Voltage – V

VOL – Low-Level Output Voltage – V

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Table 5-5 lists the characteristics of the reduced drive strength GPIO output.
Table 5-5. Outputs – General-Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETERTEST CONDITIONS
I(OHmax) = –1 mA (2)VOH

High-level output voltage

I(OHmax) = –3 mA (2)I(OHmax) = –2 mA (2)I(OHmax) = –6 mA (2)I(OLmax) = 1 mA (3)VOL

Low-level output voltage

I(OLmax) = 3 mA (4)I(OLmax) = 2 mA (3)I(OLmax) = 6 mA (4)

(1)
(2)
(3)
(4)

32

VCC
1.8 V
3.0 V
1.8 V
3.0 V

MIN

MAX

VCC – 0.25

VCC

VCC – 0.60

VCC

VCC – 0.25

VCC

VCC – 0.60

VCC

VSS

VSS + 0.25

VSS

VSS + 0.60

VSS

VSS + 0.25

VSS

VSS + 0.60

UNIT

V

V

Selecting reduced drive strength may reduce EMI.
The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.
See Section 5.3 for more details.
The maximum total current, I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified.
The maximum total current, I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified.

Specifications

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5.8.2

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Typical Characteristics – General-Purpose I/O (Reduced Drive Strength)00

IOH – High-Level Output Current – mA

IOH – High-Level Output Current – mA

-1
-2
-3
-4
-5
TA = 85°C
-6

-5

-10

-15
TA = 85°C-20
TA = 25°C-7
TA = 25°C
-8

-25

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

0

0.5

VOH – High-Level Output Voltage – V

VCC = 1.8 V

Reduced Drive Strength

Figure 5-6. High-Level Output Current vs High-Level Output
Voltage

1.5

VCC = 3 V

2

2.5

3

Reduced Drive Strength

Figure 5-7. High-Level Output Current vs High-Level Output
Voltage

8

20
18

7

TA = 25°C
TA = 25°C

IOL – Low-Level Output Current – mA

IOL – Low-Level Output Current – mA

1

VOH – High-Level Output Voltage – V

6
TA = 85°C
5
4
3
2
1

16
TA = 85°C
14
12
10
8
6
4
2

0

0
0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

0

0.5

VCC = 1.8 V

Reduced Drive Strength

Figure 5-8. Low-Level Output Current vs Low-Level Output
Voltage

1

1.5

2

2.5

VCC = 3 V

Reduced Drive Strength

Figure 5-9. Low-Level Output Current vs Low-Level Output
VoltageSpecifications
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VOL – Low-Level Output Voltage – V

VOL – Low-Level Output Voltage – V

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Table 5-6 lists the characteristics of the GPIO output frequency.
Table 5-6. Output Frequency – General-Purpose I/Oover recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER

fPx.y

Port output frequency (with load)

fPort_CLK

(1)
(2)

34

Clock output frequency

TEST CONDITIONS
See (1) (2)

ACLK, SMCLK, MCLK,
CL = 20 pF (2)

MIN

MAX

VCC = 1.8 V,
PMMCOREVx = 0

16

VCC = 3 V,
PMMCOREVx = 3

25

VCC = 1.8 V,
PMMCOREVx = 0

16

VCC = 3 V,
PMMCOREVx = 3

25

UNIT

MHz

MHz

A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For fulldrive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

Specifications

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5.9

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Clock Specifications
Table 5-7 lists the characteristics of the XT1 oscillator in low-frequency mode.
Table 5-7. Crystal Oscillator, XT1, Low-Frequency Mode (1)over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERΔIDVCC.LF

Differential XT1 oscillator
crystal current consumption
from lowest drive setting, LF
mode

TEST CONDITIONSfOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 2, TA = 25°C

Oscillation allowance for
LF crystals (4)

(1)

(2)
(3)
(4)

(5)
(6)
(7)
(8)

10

32.768

XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF

210

XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF

300
1

XTS = 0, XCAPx = 1

5.5

XTS = 0, XCAPx = 2

8.5

XTS = 0, XCAPx = 3

12.0

Duty cycle, LF mode
Oscillator fault frequency,
LF mode (7)XTS = 0 (8)fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 0, TA = 25°C, CL,eff = 6 pF
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 3, TA = 25°C, CL,eff = 12 pF

UNIT

µA

Hz
50

kHz

kΩ

XTS = 0, XCAPx = 0 (6)XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz

Start-up time, LF mode

0.170

32768

OALF

tSTART,LF

3.0 V

XTS = 0, XT1BYPASS = 0

XT1 oscillator logic-levelsquare-wave input frequency, XTS = 0, XT1BYPASS = 1 (2) (3)LF mode

MAX

0.075

0.290

fXT1,LF,SW

fFault,LF

TYP

fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 3, TA = 25°C

XT1 oscillator crystal
frequency, LF mode

CL,effMIN

fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 1, TA = 25°C

fXT1,LF0

Integrated effective load
capacitance, LF mode (5)

VCC

pF

30%

70%

10

10000

Hz

1000
3.0 V

ms
500

To improve EMI on the XT1 oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger inputs section of this data sheet.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:• For XT1DRIVEx = 0, CL,eff ≤ 6 pF.
• For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF.
• For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF.
• For XT1DRIVEx = 3, CL,eff ≥ 6 pF.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For acorrect setup, the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.

Specifications
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Table 5-8 lists the characteristics of the VLO.
Table 5-8. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERfVLO

VLO frequency

dfVLO/dT

VLO frequency temperature drift

dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle(1)(2)

TEST CONDITIONS
Measured at ACLK

VCC

MIN

TYP

MAX

UNIT

1.8 V to 3.6 V

6

9.4

15

kHz

(1)

1.8 V to 3.6 V

0.5

Measured at ACLK (2)1.8 V to 3.6 V

4Measured at ACLK

1.8 V to 3.6 V

Measured at ACLK

30%

%/°C
%/V
70%

Calculated using the box method: (MAX(–40°C to 85ºC) – MIN(–40°C to 85ºC)) / MIN(–40°C to 85ºC) / (85ºC – (–40ºC))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

Table 5-9 lists the characteristics of the REFO.
Table 5-9. Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IREFO

fREFO

TEST CONDITIONS

VCC

MIN

TYP

TA = 25°C

1.8 V to 3.6 V

3REFO frequency calibrated

Measured at ACLK

1.8 V to 3.6 V

32768

Full temperature range

1.8 V to 3.6 V

±3.5%

3V

±1.5%

REFO absolute tolerance calibrated

TA = 25°C

dfREFO/dT

REFO frequency temperature drift(1)

1.8 V to 3.6 V

0.01

dfREFO/dVCC

REFO frequency supply voltage drift Measured at ACLK (2)1.8 V to 3.6 V

1.0

Duty cycle

Measured at ACLK

1.8 V to 3.6 V

REFO start-up time

40%/60% duty cycle

1.8 V to 3.6 V

tSTART
(1)
(2)

36

MAX

REFO oscillator current
consumption

Measured at ACLK

40%

50%

UNIT
µA
Hz

%/°C
%/V
60%

25

µs

Calculated using the box method: (MAX(–40°C to 85ºC) – MIN(–40°C to 85ºC)) / MIN(–40°C to 85ºC) / (85ºC – (–40ºC))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

Specifications

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Table 5-10 lists the frequency characteristics of the DCO.
Table 5-10. DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

DCO frequency (0, 0) (1)fDCO(0,0)

(1)

MAX

UNIT

DCORSELx = 0, DCOx = 0, MODx = 0

0.07

MIN

TYP

0.20

MHz

fDCO(0,31)

DCO frequency (0, 31)

DCORSELx = 0, DCOx = 31, MODx = 0

0.70

1.70

MHz

fDCO(1,0)

DCO frequency (1, 0) (1)

DCORSELx = 1, DCOx = 0, MODx = 0

0.15

0.36

MHz

fDCO(1,31)

DCO frequency (1, 31) (1)

DCORSELx = 1, DCOx = 31, MODx = 0

1.47

3.45

MHz

fDCO(2,0)

DCO frequency (2, 0) (1)

DCORSELx = 2, DCOx = 0, MODx = 0

0.32

0.75

MHz

(1)

fDCO(2,31)

DCO frequency (2, 31)

DCORSELx = 2, DCOx = 31, MODx = 0

3.17

7.38

MHz

fDCO(3,0)

DCO frequency (3, 0) (1)

DCORSELx = 3, DCOx = 0, MODx = 0

0.64

1.51

MHz

fDCO(3,31)

DCO frequency (3, 31) (1)

DCORSELx = 3, DCOx = 31, MODx = 0

6.07

14.0

MHz

(1)

fDCO(4,0)

DCO frequency (4, 0)

DCORSELx = 4, DCOx = 0, MODx = 0

1.3

3.2

MHz

fDCO(4,31)

DCO frequency (4, 31) (1)

DCORSELx = 4, DCOx = 31, MODx = 0

12.3

28.2

MHz

fDCO(5,0)

DCO frequency (5, 0) (1)

DCORSELx = 5, DCOx = 0, MODx = 0

2.5

6.0

MHz

(1)

fDCO(5,31)

DCO frequency (5, 31)

DCORSELx = 5, DCOx = 31, MODx = 0

23.7

54.1

MHz

fDCO(6,0)

DCO frequency (6, 0) (1)

DCORSELx = 6, DCOx = 0, MODx = 0

4.6

10.7

MHz

fDCO(6,31)

DCO frequency (6, 31) (1)

DCORSELx = 6, DCOx = 31, MODx = 0

39.0

88.0

MHz

fDCO(7,0)

DCO frequency (7, 0) (1)

DCORSELx = 7, DCOx = 0, MODx = 0

8.5

19.6

MHz

(1)

fDCO(7,31)

DCO frequency (7, 31)

DCORSELx = 7, DCOx = 31, MODx = 0

60

135

MHz

SDCORSEL

Frequency step between range
DCORSEL and DCORSEL + 1

SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)

1.2

2.3

ratio

SDCO

Frequency step between tap
DCO and DCO + 1

SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)

1.02

1.12

ratio

40%

Duty cycle

Measured at SMCLK

dfDCO/dT

DCO frequency temperature drift

fDCO = 1 MHz

0.1

%/°C

dfDCO/dVCORE

DCO frequency voltage drift

fDCO = 1 MHz

1.9

%/V

(1)

50%

60%

When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within therange of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. If the actual fDCO frequency for the selected
range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the selected range is at its minimum
or maximum tap setting.
100
VCC = 3.0 V
TA = 25°C

fDCO – MHz

10

DCOx = 311

0.1

DCOx = 0

0

1

2

3

4

5

6

7

DCORSEL

Figure 5-10. Typical DCO Frequency

Specifications
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5.10 Power-Management Module (PMM)
Table 5-11 lists the brownout characteristics of the PMM.
Table 5-11. PMM, Brownout Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

0.80

1.30

V(DVCC_BOR_IT–)BORH on voltage, DVCC falling level| dDVCC/dt | < 3 V/s

V(DVCC_BOR_IT+)BORH off voltage, DVCC rising level| dDVCC/dt | < 3 V/s

V(DVCC_BOR_hys)

BORH hysteresis

50

tRESET (1)Pulse duration required at RST/NMI pin to accept
a reset

2

(1)

MAX

UNIT

1.45

V

1.50

V

250

mV
µs

Pulse much shorter than 2 µs might trigger reset.

Table 5-12 lists the core voltage characteristics of the PMM.
Table 5-12. PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

VCORE3(AM)Core voltage, active mode, PMMCOREV = 3

2.4 V ≤ DVCC ≤ 3.6 V

1.93

V

VCORE2(AM)Core voltage, active mode, PMMCOREV = 2

2.2 V ≤ DVCC ≤ 3.6 V

1.83

V

VCORE1(AM)Core voltage, active mode, PMMCOREV = 1

2.0 V ≤ DVCC ≤ 3.6 V

1.62

V

VCORE0(AM)Core voltage, active mode, PMMCOREV = 0

1.8 V ≤ DVCC ≤ 3.6 V

1.42

V

VCORE3(LPM)

Core voltage, low-current mode, PMMCOREV = 3

2.4 V ≤ DVCC ≤ 3.6 V

1.96

V

VCORE2(LPM)

Core voltage, low-current mode, PMMCOREV = 2

2.2 V ≤ DVCC ≤ 3.6 V

1.94

V

VCORE1(LPM)

Core voltage, low-current mode, PMMCOREV = 1

2.0 V ≤ DVCC ≤ 3.6 V

1.74

V

VCORE0(LPM)

Core voltage, low-current mode, PMMCOREV = 0

1.8 V ≤ DVCC ≤ 3.6 V

1.54

V

38

Specifications

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Table 5-13 lists the characteristics of the high-side SVS.
Table 5-13. PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSMINSVSHE = 0, DVCC = 3.6 V
I(SVSH)SVS current consumption

SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0

SVSH on voltage level (1)V(SVSH_IT+)SVSH off voltage level (1)tpd(SVSH)

SVSH propagation delayt(SVSH)SVSH on or off delay timedVDVCC/dt

DVCC rise time

(1)

MAX

UNIT

0

nA

200

SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1

V(SVSH_IT–)

TYP

1.5

µA

SVSHE = 1, SVSHRVL = 0

1.60

1.65

1.70

SVSHE = 1, SVSHRVL = 1

1.77

1.84

1.90

SVSHE = 1, SVSHRVL = 2

1.97

2.04

2.10

SVSHE = 1, SVSHRVL = 3

2.09

2.16

2.23

SVSHE = 1, SVSMHRRL = 0

1.68

1.74

1.80

SVSHE = 1, SVSMHRRL = 1

1.89

1.95

2.01

SVSHE = 1, SVSMHRRL = 2

2.08

2.14

2.21

SVSHE = 1, SVSMHRRL = 3

2.21

2.27

2.34

SVSHE = 1, SVSMHRRL = 4

2.35

2.41

2.49

SVSHE = 1, SVSMHRRL = 5

2.65

2.72

2.80

SVSHE = 1, SVSMHRRL = 6

2.96

3.04

3.13

SVSHE = 1, SVSMHRRL = 7

2.96

3.04

3.13

SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1

2.5

SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0

20

SVSHE = 0 → 1, SVSHFP = 1

12.5

SVSHE = 0 → 1, SVSHFP = 0

100
0

V

V

µs
µs
1000

V/s

The SVSH settings available depend on the VCORE (PMMCOREVx) setting. Refer to the Power Management Module and Supply
Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide on recommended settings and usage.

Table 5-14 lists the characteristics of the high-side SVM.
Table 5-14. PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSMINSVMHE = 0, DVCC = 3.6 V
I(SVMH)

SVMH current consumption

SVMH on or off voltage level (1)tpd(SVMH)

SVMH propagation delayt(SVMH)

SVMH on or off delay time

(1)

MAX

UNIT

0

SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0

nA

200

SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1

V(SVMH)

TYP

1.5

µA

SVMHE = 1, SVSMHRRL = 0

1.68

1.74

1.80

SVMHE = 1, SVSMHRRL = 1

1.89

1.95

2.01

SVMHE = 1, SVSMHRRL = 2

2.08

2.14

2.21

SVMHE = 1, SVSMHRRL = 3

2.21

2.27

2.34

SVMHE = 1, SVSMHRRL = 4

2.35

2.41

2.49

SVMHE = 1, SVSMHRRL = 5

2.65

2.72

2.80

SVMHE = 1, SVSMHRRL = 6

2.96

3.04

3.13

SVMHE = 1, SVSMHRRL = 7

2.96

3.04

3.13

SVMHE = 1, SVMHOVPE = 1

3.79

SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1

2.5

SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0

20

SVMHE = 0 → 1, SVMHFP = 1

12.5

SVMHE = 0 → 1, SVMHFP = 0

100

V

µs
µs

The SVMH settings available depend on the VCORE (PMMCOREVx) setting. Refer to the Power Management Module and Supply
Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide on recommended settings and usage.
Specifications
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Table 5-15 lists the characteristics of the low-side SVS.
Table 5-15. PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSMINSVSLE = 0, PMMCOREV = 2
I(SVSL)SVSL current consumption

tpd(SVSL)SVSL propagation delayt(SVSL)SVSL on or off delay time

TYP

MAX

0

SVSLE = 1, PMMCOREV = 2, SVSLFP = 0

200

SVSLE = 1, PMMCOREV = 2, SVSLFP = 1

1.5

SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1

2.5

SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0

20

SVSLE = 0 → 1, SVSLFP = 1

12.5

SVSLE = 0 → 1, SVSLFP = 0

100

UNIT
nA
µA
µs
µs

Table 5-16 lists the characteristics of the low-side SVM.
Table 5-16. PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSMINSVMLE = 0, PMMCOREV = 2
I(SVML)

SVML current consumption

tpd(SVML)

SVML propagation delayt(SVML)

SVML on or off delay time

TYP

MAX

0

SVMLE = 1, PMMCOREV = 2, SVMLFP = 0

200

SVMLE = 1, PMMCOREV = 2, SVMLFP = 1

1.5

SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1

2.5

SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0

20

SVMLE = 0 → 1, SVMLFP = 1

12.5

SVMLE = 0 → 1, SVMLFP = 0

100

UNIT
nA
µA
µs
µs

Table 5-17 lists the wake-up times.
Table 5-17. Wake-up Times From Low-Power Modes and Resetover recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP MAXUNIT

fMCLK ≥ 4 MHz

3

5

1 MHz < fMCLK <
4 MHz

4

6

150

160

µs

tWAKE-UP-FAST

Wake-up time from LPM2,
LPM3, or LPM4 to activemode (1)

PMMCOREV = SVSMLRRL = n(where n = 0, 1, 2, or 3),
SVSLFP = 1

tWAKE-UP-SLOW

Wake-up time from LPM2,
LPM3, or LPM4 to activemode (2) (3)

PMMCOREV = SVSMLRRL = n(where n = 0, 1, 2, or 3),
SVSLFP = 0

tWAKE-UP-LPM4.5

Wake-up time from LPM4.5 toactive mode (4)

2

3

ms

tWAKE-UP-RESET

Wake-up time from RST or BOR
event to active mode (4)

2

3

ms

(1)

(2)

(3)
(4)

40

µs

This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performancemode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in full performancemode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in
the Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx Family User's Guide.
This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performancemode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in normal mode (lowcurrent mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in thePower Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx Family User's Guide.
The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by theperformance mode settings as for LPM2, LPM3, and LPM4.
This value represents the time from the wake-up event to the reset vector execution.

Specifications

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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 20185.11 Auxiliary Supplies
Table 5-18 lists the operating conditions of the auxiliary supplies.
Table 5-18. Auxiliary Supplies, Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC

MAX

UNIT
V

Supply voltage range for all supplies at pins DVCC, AVCC, AUXVCC1, AUXVCC2,AUXVCC3

1.8

3.6

PMMCOREVx = 0

1.8

3.6

PMMCOREVx = 1

2.0

3.6

PMMCOREVx = 2

2.2

3.6

PMMCOREVx = 3

2.4

3.6

Digital system supply voltage range,
VDSYS = VCC – RON × ILOAD

VDSYS

NOM

See module
specifications

V

VASYS

Analog system supply voltage range, VASYS = VCC – RON × ILOAD

V

CVCC,
CAUX1/2

Recommended capacitor at pins DVCC, AVCC, AUXVCC1, AUXVCC2

4.7

µF

CVSYS

Recommended capacitor at pins VDSYS and VASYS

4.7

µF

CVCORE

Recommended capacitance at VCORE pin

0.47

µF

CAUX3

Recommended capacitor at pin AUXVCC3

0.47

µF

Table 5-19 lists the current consumption of AUX3.
Table 5-19. Auxiliary Supplies, AUXVCC3 (Backup Subsystem) Currents
over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCC

IAUX3,RTCon

AUXVCC3 current with
RTC enabled

RTC and 32-kHz oscillator in
backup subsystem enabled

3V

IAUX3,RTCoff

AUXVCC3 current with
RTC disabled

RTC and 32-kHz oscillator in
backup subsystem disabled

3V

TA

MIN

TYP

MAX

25°C

0.83

85°C

0.95

25°C

110

85°C

165

UNIT
µA
nA

Table 5-20 lists the characteristics of the auxiliary supply monitor.
Table 5-20. Auxiliary Supplies, Auxiliary Supply Monitor
over operating free-air temperature range (unless otherwise noted)
PARAMETER

ICC,Monitor

Average supply current formonitoring circuitry drawn from
VDSYS

Average current drawn from
IMeas,Monitor monitored supply during
measurement cycle

VMonitor

Auxiliary supply threshold level

TEST CONDITIONSLOCKAUX = 0, AUXMRx = 0,
AUX0MD = 0, AUX1MD = 0, AUX2MD = 1,
VDSYS = DVCC, VASYS = AVCC,
Current measured at VDSYS pin (also see
Figure 5-11)

VCC

MIN

TYP

3V

LOCKAUX = 0, AUXMRx = 0,
AUX0MD = 0, AUX1MD = 0, AUX2MD = 1,
VDSYS = DVCC, VASYS = AVCC,AUXVCC1 = 3 V,
Current measured at AUXVCC1 pin (also see
Figure 5-12)

MAX

UNIT

0.70

µA

0.11

µA

AUXLVLx = 0

1.67

1.74

1.80

AUXLVLx = 1

1.87

1.95

2.01

AUXLVLx = 2

2.06

2.14

2.21

AUXLVLx = 3

2.19

2.27

2.33

AUXLVLx = 4

2.33

2.41

2.48

AUXLVLx = 5

2.63

2.72

2.79

AUXLVLx = 6

2.91

3.02

3.10

AUXLVLx = 7

2.91

3.02

3.10

Specifications
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0.7
0.6

ICC, monitor – µA

0.5
0.4
0.3
0.2
0.1
0
1.8

2

2.2

2.4

2.6
2.8
VDSYS Voltage – V

3

3.2

3.4

3.6

3.2

3.4

3.6

TYP

MAX

Figure 5-11. VDSYS Voltage vs ICC,Monitor
120

Imeas, monitor – nA

100
80
60
40
20
0
1.8

2.0

2.2

2.4

2.6
2.8
AUXVCC1 Voltage – V

3.0

Figure 5-12. AUXVCC1 Voltage vs IMeas,Monitor
Table 5-21 lists the ON-resistance characteristics of the auxiliary supplies.
Table 5-21. Auxiliary Supplies, Switch ON-Resistanceover operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

UNIT

RON,DVCC

ON-resistance of switch
between DVCC and VDSYSILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA

5Ω

RON,DAUX1

ON-resistance of switch
between AUXVCC1 andVDSYS

ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA

5Ω

RON,DAUX2

ON-resistance of switch
between AUXVCC2 andVDSYS

ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA

5Ω

RON,AVCC

ON-resistance of switch
between AVCC and VASYSILOAD = IModules = 10 mA

5Ω

RON,AAUX1

ON-resistance of switch
between AUXVCC1 and VASYSILOAD = IModules = 5 mA

20Ω

RON,AAUX2

ON-resistance of switch
between AUXVCC2 and VASYSILOAD = IModules = 5 mA

20

Ω

42

Specifications

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Table 5-22 lists the switching times of the auxiliary supplies.
Table 5-22. Auxiliary Supplies, Switching Timeover operating free-air temperature range (unless otherwise noted)
PARAMETERMIN

tSwitchTime from occurence of trigger (SVM or software) to "new" supply connected to system supplies

tRecover"Recovery time" after a switch over took place; during this time, no further switching takes place

MAX

UNIT

100

ns

200

450

µs

TYP

MAX

UNIT

50

100

nA

450

730

nA

UNIT

Table 5-23 lists the switch leakage of the auxiliary supplies.
Table 5-23. Auxiliary Supplies, Switch Leakage
over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSISW,Lkg

Current into DVCC, AVCC, AUXVCC1, or
AUXVCC2 if not selected

IVmax

Current drawn from highest supply

MIN

Per supply (but not the highest supply)

Table 5-24 lists the characteristics of the auxiliary supplies to ADC10_A.
Table 5-24. Auxiliary Supplies, Auxiliary Supplies to ADC10_A
over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONS

Supply voltage divider
V3 = VSupply/3

V3

RV3

Load resistance

tSample,V3

Sampling time required if
V3 selected

VCC

MIN

TYP

MAX

1.8 V

0.58

0.60

0.62

3.0 V

0.98

1.00

1.02

3.6 V

1.18

1.20

1.22

AUXADCRx = 0

18

AUXADCRx = 1

1.5

AUXADCRx = 2

0.6

AUXADC = 1, ADC10ON = 1,
INCH = 0Ch,
Error of conversion result≤ 1 LSB

AUXADCRx = 0

1000

AUXADCRx = 1

1000

AUXADCRx = 2

1000

V

kΩ

ns

Table 5-25 lists the charge limiting resistor characteristics of the auxiliary supplies.
Table 5-25. Auxiliary Supplies, Charge Limiting Resistor
over operating free-air temperature range (unless otherwise noted)
PARAMETER
RCHARGE

Charge limiting resistor

TEST CONDITIONS

VCC

MIN

TYP

MAX

AUXCHCx = 1

3V

5

AUXCHCx = 2

3V

10

AUXCHCx = 3

3V

20

Specifications
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UNIT
kΩ

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5.12 Timer_A
Table 5-26 lists the characteristics of the Timer_A.
Table 5-26. Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCC

MIN

fTA

Timer_A input clock frequency

Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%

1.8 V, 3 V

tTA,cap

Timer_A capture timing

All capture inputs, minimum pulse duration
required for capture

1.8 V, 3 V

MAX

UNIT

25

MHz

20

ns

5.13 eUSCI
Table 5-27. eUSCI (UART Mode) Clock Frequency
PARAMETERCONDITIONS

feUSCIeUSCI input clock frequency

fBITCLKBITCLK clock frequency(equals baud rate in MBaud)

VCC

MIN

Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%

MAX

UNIT

fSYSTEM

MHz

5

MHz

UNIT

Table 5-28 lists the switching characteristics of the eUSCI in UART mode.
Table 5-28. eUSCI (UART Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER

tt

UART receive deglitch time (1)TEST CONDITIONS

MIN

TYP

MAX

UCGLITx = 0

10

15

25

UCGLITx = 1

30

50

85

50

80

150

70

120

200

UCGLITx = 2
UCGLITx = 3

(1)

44

VCC

2 V, 3 V

ns

Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses arecorrectly recognized their duration should exceed the maximum specification of the deglitch time.

Specifications

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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Table 5-29 lists the supported clock frequencies of the eUSCI in SPI master mode.
Table 5-29. eUSCI (SPI Master Mode) Clock Frequency
PARAMETER
feUSCIeUSCI input clock frequency

CONDITIONS

VCC

MIN

Internal: SMCLK or ACLK,
Duty cycle = 50% ±10%

MAX

UNIT

fSYSTEM

MHz

MAX

UNIT

Table 5-30 lists the switching characteristics of the eUSCI in SPI master mode.
Table 5-30. eUSCI (SPI Master Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
tSTE,LEAD

STE lead time, STE active to clocktSTE,LAG

STE lag time, Last clock to STE
inactive

TEST CONDITIONS

VCC

MIN

UCSTEM = 0, UCMODEx = 01 or 10

2 V, 3 V

150

UCSTEM = 1, UCMODEx = 01 or 10

2 V, 3 V

150

UCSTEM = 0, UCMODEx = 01 or 10

2 V, 3 V

200

UCSTEM = 1, UCMODEx = 01 or 10

2 V, 3 V

200

UCSTEM = 0, UCMODEx = 01 or 10
tSTE,ACC

STE access time, STE active to SIMO
data out
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10

tSTE,DIS

STE disable time, STE inactive to
SIMO high impedance
UCSTEM = 1, UCMODEx = 01 or 10

tSU,MISOMI input data setup time

tHD,MISOMI input data hold timetVALID,MO

SIMO output data valid time (2)UCLK edge to SIMO valid, CL = 20 pF

tHD,MOSIMO output data hold time (3)CL = 20 pF

(1)
(2)
(3)

ns
ns

2V

50

3V

30

2V

50

3V

30

2V

40

3V

25

2V

40

3V

ns

ns

25

2V

50

3V

30

2V

0

3V

0

ns
ns

2V

9

3V

5

2V

0

3V

0

ns
ns

fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagramsin Figure 5-13 and Figure 5-14.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the dataon the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 513 and Figure 5-14.

Specifications
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1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLOW/HIGHtLOW/HIGH

tSU,MI
tHD,MISOMI

tVALID,MO
SIMO

Figure 5-13. SPI Master Mode, CKPH = 0
1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLOW/HIGHtLOW/HIGH

tHD,MI

tSU,MISOMI

tVALID,MO
SIMO

Figure 5-14. SPI Master Mode, CKPH = 1

46

Specifications

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Table 5-31 lists the switching characteristics of the eUSCI in SPI slave mode.
Table 5-31. eUSCI (SPI Slave Mode)over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETERTEST CONDITIONStSTE,LEAD

STE lead time, STE active to clocktSTE,LAG

STE lag time, Last clock to STE inactivetSTE,ACC

STE access time, STE active to SOMI data outtSTE,DIS

STE disable time, STE inactive to SOMI highimpedancetSU,SISIMO input data setup time

tHD,SISIMO input data hold timetVALID,SO

SOMI output data valid time (2)UCLK edge to SOMI valid,
CL = 20 pF

tHD,SOSOMI output data hold time (3)CL = 20 pF

(1)
(2)
(3)

VCC

MIN

2.0 V

4

3.0 V

3

2.0 V

0

3.0 V

0

TYP

MAX

ns
ns

2.0 V

46

3.0 V

24

2.0 V

38

3.0 V

25

2.0 V

2

3.0 V

1

2.0 V

2

3.0 V

2
55
32

3.0 V

16

ns

ns

3.0 V
24

ns

ns

2.0 V
2.0 V

UNIT

ns
ns

fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagramsin Figure 5-15 and Figure 5-16.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams inFigure 5-15
and Figure 5-16.

UCMODEx = 01
tSTE,LEAD

STEtSTE,LAGUCMODEx = 10
1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLOW/HIGHtSU,SIMOtLOW/HIGHtHD,SIMO
SIMO

tACC

tVALID,SOMI

tDIS

SOMI

Figure 5-15. SPI Slave Mode, CKPH = 0

Specifications
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tSTE,LAG

tSTE,LEAD
STE
1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLOW/HIGHtLOW/HIGHtHD,SItSU,SI

SIMO

tACC

tDIS

tVALID,SO

SOMI

Figure 5-16. SPI Slave Mode, CKPH = 1

48

Specifications

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Table 5-32 lists the switching characteristics of the eUSCI in I2C mode.
Table 5-32. eUSCI (I2C Mode)over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17)
PARAMETERTEST CONDITIONS

feUSCIeUSCI input clock frequencyfSCL

SCL clock frequency
Hold time (repeated) STARTtSU,STA

Setup time for a repeated STARTtHD,DAT

Data hold time
Data setup time

tSU,STO

Setup time for STOPfSCL = 100 kHz

2 V, 3 V

fSCL > 100 kHz
fSCL = 100 kHz

2 V, 3 V

fSCL > 100 kHz

TYP

0

400

kHz
µs
µs

5.0

fSCL > 100 kHz

2 V, 3 V

1.3

µs
µs

5.2

µs

1.7

UCGLITx = 0

75

220

UCGLITx = 1

35

120

30

60

2 V, 3 V

UCGLITx = 2

20
30

UCCLTOx = 2

2 V, 3 V

33

UCCLTOx = 3
tSU,STAtHD,STA

ns

35

UCCLTOx = 1
Clock low time-out

MHz

1.4
0.4

UCGLITx = 3
tTIMEOUT

fSYSTEM

5.1

2 V, 3 V

fSCL > 100 kHz

UNIT

1.5

2 V, 3 V

2 V, 3 V

MAX

5.1

fSCL = 100 kHz
fSCL = 100 kHz

Pulse duration of spikes suppressed by
input filter

tSP

MIN

2 V, 3 V

tHD,STAtSU,DAT

VCC

Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%ms

37
tHD,STA

tBUF

SDA
tLOW

tHIGH

tSP

SCL

tSU,DATtSU,STOtHD,DAT

Figure 5-17. I2C Mode Timing

Specifications
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5.14 LCD Controller
Table 5-33 lists the recommended operating conditions of the LCD_C.
Table 5-33. LCD_C Recommended Operating Conditions
MIN

MAX

UNIT

2.2

3.6

V

LCDCPEN = 1, 0000 < VLCDx ≤ 1100
(charge pump enabled, VLCD ≤ 3.3 V)

2.0

3.6

V

Supply voltage range, internalbiasing, charge pump disabled

LCDCPEN = 0, VLCDEXT = 0

2.4

3.6

V

VCC,LCD_C,ext. bias

Supply voltage range, externalbiasing, charge pump disabled

LCDCPEN = 0, VLCDEXT = 0

2.4

3.6

V

VCC,LCD_C,VLCDEXT

Supply voltage range, external
LCD voltage, internal or externalbiasing, charge pump disabled

LCDCPEN = 0, VLCDEXT = 1

2.0

3.6

V

VLCDCAP/R33

External LCD voltage at
LCDCAP/R33, internal or externalbiasing, charge pump disabled

LCDCPEN = 0, VLCDEXT = 1

2.4

3.6

V

CLCDCAP

Capacitor on LCDCAP whencharge pump enabled

LCDCPEN = 1, VLCDx > 0000
(charge pump enabled)

10

µF

fLCD

LCD frequency range

fFRAME = 1/(2 × mux) × fLCD
with mux = 1 (static) to 8

1024

Hz

fFRAME,4mux

LCD frame frequency range

fFRAME,4mux(MAX) = 1/(2 × 4) ×
fLCD(MAX) = 1/(2 × 4) × 1024 Hz

128

Hz

fFRAME,8mux

LCD frame frequency range

fFRAME,8mux(MAX) = 1/(2 × 4) ×
fLCD(MAX) = 1/(2 × 8) × 1024 Hz

64

Hz

fACLK,in

ACLK input frequency range

40

kHz

CPanelPanel capacitance

100-Hz frame frequency

10000

pF

VCC
+ 0.2

V

VCC,LCD_C,CP en,3.6

Supply voltage range, charge
pump enabled, VLCD ≤ 3.6 V

LCDCPEN = 1, 0000 < VLCDx ≤ 1111
(charge pump enabled, VLCD ≤ 3.6 V)

VCC,LCD_C,CP en,3.3

Supply voltage range, charge
pump enabled, VLCD ≤ 3.3 V

VCC,LCD_C,int. bias

NOM

4.7
0

30

32

VR33

Analog input voltage at R33

LCDCPEN = 0, VLCDEXT = 1

2.4

VR23,1/3bias

Analog input voltage at R23

LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0

VR13

VR03 + 2/3 ×(VR33-VR03)

VR33

V

VR13,1/3bias

Analog input voltage at R13 with
1/3 biasing

LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0

VR03

VR03 + 1/3 ×(VR33-VR03)

VR23

V

VR13,1/2bias

Analog input voltage at R13 with
1/2 biasing

LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1

VR03

VR03 + 1/2 ×(VR33-VR03)

VR33

V

VR03

Analog input voltage at R03

R0EXT = 1

VSS

VLCD–VR03

Voltage difference between VLCD
and R03

LCDCPEN = 0, R0EXT = 1

2.4

VLCDREF/R13

External LCD reference voltage
applied at LCDREF/R13

VLCDREFx = 01

0.8

50

Specifications

V

1.2

VCC
+ 0.2

V

1.5

V

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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Table 5-34 lists the characteristics of the LCD_C.
Table 5-34. LCD_C Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER

VLCD

LCD voltage

TEST CONDITIONS

VCC

MIN

TYP

VLCDx = 0000, VLCDEXT = 0

2.4 V to 3.6 V

VCC

LCDCPEN = 1, VLCDx = 0001

2 V to 3.6 V

2.58

LCDCPEN = 1, VLCDx = 0010

2 V to 3.6 V

2.64

LCDCPEN = 1, VLCDx = 0011

2 V to 3.6 V

2.71

LCDCPEN = 1, VLCDx = 0100

2 V to 3.6 V

2.78

LCDCPEN = 1, VLCDx = 0101

2 V to 3.6 V

2.83

LCDCPEN = 1, VLCDx = 0110

2 V to 3.6 V

2.90

LCDCPEN = 1, VLCDx = 0111

2 V to 3.6 V

2.96

LCDCPEN = 1, VLCDx = 1000

2 V to 3.6 V

3.02

LCDCPEN = 1, VLCDx = 1001

2 V to 3.6 V

3.07

LCDCPEN = 1, VLCDx = 1010

2 V to 3.6 V

3.14

LCDCPEN = 1, VLCDx = 1011

2 V to 3.6 V

3.21

LCDCPEN = 1, VLCDx = 1100

2 V to 3.6 V

3.27

LCDCPEN = 1, VLCDx = 1101

2.2 V to 3.6 V

3.32

LCDCPEN = 1, VLCDx = 1110

2.2 V to 3.6 V

3.38

MAX

UNIT

V

LCDCPEN = 1, VLCDx = 1111

2.2 V to 3.6 V

3.44

ICC,Peak,CP

Peak supply currents due tocharge pump activities

3.6

LCDCPEN = 1, VLCDx = 1111

2.2 V

400

tLCD,CP,on

Time to charge CLCD when
discharged

CLCD = 4.7µF, LCDCPEN = 0→1,
VLCDx = 1111

2.2 V

150

ICP,Load

Maximum charge pump load
current

LCDCPEN = 1, VLCDx = 1111

2.2 V

RLCD,Seg

LCD driver output impedance,
segment lines

LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA

2.2 V

10

kΩ

RLCD,COMLCD driver output impedance,
common lines

LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA

2.2 V

10

kΩ

µA
500

50

µA

Specifications
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5.15 SD24_B
Table 5-35 lists the power supply and recommended operating conditions of the SD24_B.
Table 5-35. SD24_B Power Supply and Recommended Operating Conditions
MIN
AVCC

Analog supply voltage

AVCC = DVCC, AVSS = DVSS = 0 V

TYP

2.4

MAX

UNIT

3.6

V

fSD

Modulator clock frequency

(1)

0.03

2.3

MHz

VI

Absolute input voltage range

AVSS – 1

AVCC

V

VIC

Common-mode input voltage range

AVSS – 1

AVCC

V

VID,FS

Differential full-scale input voltage

Differential input voltage for specified
performance (2)

VID

CREF
(1)
(2)
(3)

VID = VI,A+ – VI,A–

SD24REFS = 1

VREF load capacitance (3)–VREF/GAIN+VREF/GAIN

SD24GAINx = 1

±910

±920

SD24GAINx = 2

±455

±460

SD24GAINx = 4

±227

±230

SD24GAINx = 8

±113

±115

SD24GAINx = 16

±57

±58

SD24GAINx = 32

±28

±29

SD24GAINx = 64

±14

±14.5

SD24GAINx = 128

±7

±7.2

SD24REFS = 1

mV

100

nF

Modulator clock frequency: MIN = 32.768 kHz – 10% ≈ 30 kHz. MAX = 32.768 kHz × 64 + 10% ≈ 2.3 MHz
The full-scale range (FSR) is defined by VFS+ = +VREF/GAIN and VFS– = –VREF/GAIN: FSR = VFS+ – VFS– = 2 × VREF / GAIN. If VREF issourced externally, the analog input range should not exceed 80% of VFS+ or VFS–; that is, VID = 0.8 VFS– to 0.8 VFS+. If VREF is sourced
internally, the given VID ranges apply.
There is no capacitance required on VREF. However, a capacitance of 100 nF is recommended to reduce any reference voltage noise.

Table 5-36 lists the analog input characteristics of the SD24_B.
Table 5-36. SD24_B Analog Input (1)PARAMETERCI

Input capacitance

TEST CONDITIONS

VCC

MIN

5

SD24GAINx = 2

5

SD24GAINx = 4

5

SD24GAINx = 8

5

SD24GAINx = 16

5

SD24GAINx = 32, 64, 128
ZI

ZID
(1)

52

Input impedance(Pin A+ or A- to AVSS)

Differential input impedance(Pin A+ to pin A-)

TYP

SD24GAINx = 1

fSD24 = 1 MHz

fSD24 = 1 MHz

MAX

UNIT

pF

5
SD24GAINx = 1

3V

200

SD24GAINx = 8

3V

200

SD24GAINx = 32

3V

SD24GAINx = 1

3V

SD24GAINx = 83V

SD24GAINx = 32

3V

kΩ

200
300

400
400

300

kΩ

400

All parameters pertain to each SD24_B converter.

Specifications

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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 20181600

Input Leakage Current – nA

1400
1200
1000
800
600
400
200
0
-200
-1

-0.5

0

0.5

1
Input Voltage – V

1.5

2

2.5

3

Figure 5-18. Input Leakage Current vs Input Voltage(Modulator OFF)
Table 5-37 lists the supply current of the SD24_B.
Table 5-37. SD24_B Supply Currents
PARAMETER

ISD,256

ISD,512TEST CONDITIONS

Analog plus digital supply current perconverter (reference not included)

fSD24 = 1 MHz,SD24OSR = 256

Analog plus digital supply current perconverter (reference not included)

fSD24 = 2 MHz,SD24OSR = 512

VCC

MIN

TYP

MAX

SD24GAIN: 1

3V

600

675

SD24GAIN: 2

3V

600

675

SD24GAIN: 4

3V

600

675

SD24GAIN: 8

3V

700

750

SD24GAIN: 16

3V

700

750

SD24GAIN: 32

3V

775

850

SD24GAIN: 64

3V

775

850

SD24GAIN: 128

3V

775

850

SD24GAIN: 1

3V

750

800

SD24GAIN: 8

3V

825

900

SD24GAIN: 32

3V

900

1000

TYP

MAX

UNIT

µA

µA

Table 5-38 lists the performance characteristics of the SD24_B.
Table 5-38. SD24_B Performance
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER
INL

Gnom

Integral nonlinearity, endpoint fit

Nominal gain

VCC

MIN

SD24GAIN: 1

TEST CONDITIONS

3V

–0.01

0.01

SD24GAIN: 8

3V

–0.01

0.01

SD24GAIN: 32

3V

–0.01

0.01

SD24GAIN: 1

3V

1

SD24GAIN: 23V

2

SD24GAIN: 43V

4

SD24GAIN: 83V

8

SD24GAIN: 163V

16

SD24GAIN: 32

3V

31.7

SD24GAIN: 64

3V

63.4

SD24GAIN: 128

3V

126.8

Specifications
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UNIT
% of
FSR

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Table 5-38. SD24_B Performance (continued)
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETERTEST CONDITIONSEGGain error (1)ΔEG/ΔT

Gain error temperature
coefficient (2), internalreference

ΔEG/ΔVCC

Gain error vs VCC (3)Offset error (4)EOS[V]

Offset error (4)EOS[FS]

Offset error temperature
coefficient (5)ΔEOS/ΔT

ΔEOS/ΔVCC

CMRR,DC

(1)
(2)

(3)

(4)
(5)

(6)

(7)

54

Offset error vs VCC(6)Common-mode rejection at
DC (7)VCC

MIN

SD24GAIN: 1, with external reference (1.2 V)

3V

–1%

TYP

MAX
+1%

SD24GAIN: 8, with external reference (1.2 V)

3V

–2%

+2%

SD24GAIN: 32, with external reference (1.2 V)

3V

–2%

+2%

SD24GAIN: 1, 8, or 32 (with internal reference)

3V

50

SD24GAIN: 1

0.15

SD24GAIN: 8

0.15

SD24GAIN: 32

0.4
3V

2.3

SD24GAIN: 8

3V

0.73

SD24GAIN: 32

3V

0.18

SD24GAIN: 1 (with Vdiff = 0 V)

3V

–0.2

0.2

SD24GAIN: 8

3V

–0.5

0.5

SD24GAIN: 32

3V

–0.5

0.5

SD24GAIN: 1

3V

1

SD24GAIN: 8

3V

0.15

SD24GAIN: 32

3V

0.1
600

SD24GAIN: 8100

SD24GAIN: 32

50

SD24GAIN: 1

3V

–110

SD24GAIN: 8

3V

–110

SD24GAIN: 32

3V

–110

ppm/
°C

%/V

SD24GAIN: 1 (with Vdiff = 0 V)

SD24GAIN: 1

UNIT

mV

% FS

µV/°C

µV/V

dB

The gain error EG specifies the deviation of the actual gain Gact from the nominal gain Gnom: EG = (Gact – Gnom)/Gnom. It covers process,temperature and supply voltage variations.
The gain error temperature coefficient ΔEG / ΔT specifies the variation of the gain error EG over temperature (EG(T) = (Gact(T) –Gnom)/Gnom) using the box method (that is, MIN and MAX values):
ΔEG/ ΔT = (MAX(EG(T)) – MIN(EG(T) ) / (MAX(T) – MIN(T)) = (MAX(Gact(T)) – MIN(Gact(T)) / Gnom / (MAX(T) – MIN(T))
with T ranging from –40°C to +85°C.
The gain error vs VCC coefficient ΔEG/ ΔVCC specifies the variation of the gain error EG over supply voltage (EG(VCC) = (Gact(VCC) –Gnom)/Gnom) using the box method (that is, MIN and MAX values):
ΔEG/ ΔVCC = (MAX(EG(VCC)) – MIN(EG(VCC) ) / (MAX(VCC) – MIN(VCC)) = (MAX(Gact(VCC)) – MIN(Gact(VCC)) / Gnom / (MAX(VCC) –MIN(VCC))
with VCC ranging from 2.4 V to 3.6 V.
The offset error EOS is measured with shorted inputs in 2s-complement mode with +100% FS = VREF / G and –100% FS = –VREF / G.
Conversion between EOS [FS] and EOS [V] is as follows: EOS [FS] = EOS [V]×G/VREF; EOS [V] = EOS [FS]×VREF/G.
The offset error temperature coefficient ΔEOS / ΔT specifies the variation of the offset error EOS over temperature using the box method(that is, MIN and MAX values):
ΔEOS / ΔT = (MAX(EOS(T)) – MIN(EOS(T) ) / (MAX(T) – MIN(T))
with T ranging from –40°C to +85°C.
The offset error vs VCC ΔEOS / ΔVCC specifies the variation of the offset error EOS over supply voltage using the box method (that is,
MIN and MAX values):
ΔEOS / ΔVCC = (MAX(EOS(VCC)) – MIN(EOS(VCC) ) / (MAX(VCC) – MIN(VCC))
with VCC ranging from 2.4 V to 3.6 V.
The DC CMRR specifies the change in the measured differential input voltage value when the common-mode voltage varies:
DC CMRR = –20log(ΔMAX/FSR) with ΔMAX being the difference between the minium value and the maximum value measured whensweeping the common-mode voltage (for example, calculating with 16-bit FSR = 65536, a maximum change by 1 LSB results in–20log(1/65536) ≈ –96 dB) .
The DC CMRR is measured with both inputs connected to the common-mode voltage (that is, no differential input signal is applied), andthe common-mode voltage is swept from –1 V to VCC.
Specifications

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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Table 5-38. SD24_B Performance (continued)
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER
CMRR,50Hz

AC PSRR,ext

AC PSRR,int

XT

Common-mode rejection at
50 Hz (8)AC power supply rejection
ratio, external reference (9)AC power supply rejection
ratio, internal reference (9)Crosstalk between
converters (10)TEST CONDITIONS

VCC

MIN

TYP

SD24GAIN: 1, fCM = 50 Hz, VCM = 930 mV

3V

–110

SD24GAIN: 8, fCM = 50 Hz, VCM = 120 mV

3V

–110

SD24GAIN: 32, fCM = 50 Hz, VCM = 30 mV

3V

–110

SD24GAIN: 1,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz–61

SD24GAIN: 8,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz–77

SD24GAIN: 32,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz–79

SD24GAIN: 1,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz–61

SD24GAIN: 8,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz–77

SD24GAIN: 32,
VCC = 3 V + 50 mV × sin(2π × fVcc × t),
fVcc = 50 Hz–79

Crosstalk source: SD24GAIN: 1,
Sine wave with maximum possible Vpp,
fIN = 50 Hz or 100 Hz,
Converter under test: SD24GAIN: 1

3V

–120

Crosstalk source: SD24GAIN: 1,
Sine wave with maximum possible Vpp,
fIN = 50 Hz or 100 Hz,
Converter under test: SD24GAIN: 8

3V

–115

Crosstalk source: SD24GAIN: 1,
Sine wave with maximum possible Vpp,
fIN = 50 Hz or 100 Hz,
Converter under test: SD24GAIN: 32

3V

–100

MAX

UNIT
dB

dB

dB

dB

(8)

The AC CMRR is the difference between a hypothetical signal with the amplitude and frequency of the applied common-mode ripple
applied to the inputs of the ADC and the actual common-mode signal spur visible in the FFT spectrum:
AC CMRR = Error Spur [dBFS] – 20log(VCM / 1.2 V / G) [dBFS] with a common-mode signal of VCM × sin(2π × fCM × t) applied to theanalog inputs.
The AC CMRR is measured with the both inputs connected to the common-mode signal (that is, no differential input signal is applied).
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).
(9) The AC PSRR is the difference between a hypothetical signal with the amplitude and frequency of the applied supply voltage ripple
applied to the inputs of the ADC and the actual supply ripple spur visible in the FFT spectrum:
AC PSRR = Error Spur [dBFS] – 20log(50 mV / 1.2 V / G) [dBFS] with a signal of 50 mV × sin(2π × fVcc × t) added to VCC.
The AC PSRR is measured with the inputs grounded (that is, no analog input signal is applied).
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).
SD24GAIN: 1 → Hypothetical signal: 20log(50 mV / 1.2 V / 1) = –27.6 dBFS
SD24GAIN: 8 → Hypothetical signal: 20log(50 mV / 1.2 V / 8) = –9.5 dBFS
SD24GAIN: 32 → Hypothetical signal: 20log(50 mV / 1.2 V / 32) = 2.5 dBFS(10) The crosstalk (XT) is specified as the tone level of the signal applied to the crosstalk source seen in the spectrum of the converter under
test. It is measured with the inputs of the converter under test being grounded.

Specifications
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Table 5-39 lists the AC performance characteristics of the SD24_B.
Table 5-39. SD24_B AC Performance
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER

SINAD

Signal-to-noise + distortion ratio

VCC

MIN

TYP

SD24GAIN: 1

TEST CONDITIONS

3V

85

87

SD24GAIN: 2

3V

SD24GAIN: 43V

SD24GAIN: 8

3V

SD24GAIN: 16

fIN = 50 Hz (1)Total harmonic distortion

84

3V
3V

68

SD24GAIN: 128

3V

62

3V

100

3V

90

3V

80

fIN = 50 Hz (1)dB

80

SD24GAIN: 64

SD24GAIN: 32
(1)

85
82

SD24GAIN: 32

SD24GAIN: 8

UNIT

86

3V

SD24GAIN: 1
THD

MAX

73

74

dB

The following voltages were applied to the SD24_B inputs:
VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t)
VI,A-(t) = 0 V – VPP / 2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24_B recommended operating conditions).

Table 5-40 lists the AC performance characteristics of the SD24_B.
Table 5-40. SD24_B AC Performance
fSD24 = 2 MHz, SD24OSRx = 512, SD24REFS = 1
PARAMETER

SINAD

(1)

56

Signal-to-noise + distortion ratio

TEST CONDITIONS

VCC

MIN

TYP

SD24GAIN: 1

3V

87

SD24GAIN: 2

3V

86

SD24GAIN: 43V

85

SD24GAIN: 8

3V

84

3V

81

SD24GAIN: 32

3V

76

SD24GAIN: 64

3V

71

SD24GAIN: 128

3V

65

SD24GAIN: 16

fIN = 50 Hz (1)

MAX

UNIT

dB

The following voltages were applied to the SD24_B inputs:
VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t)
VI,A-(t) = 0 V – VPP / 2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24_B recommended operating conditions).

Specifications

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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Table 5-41 lists the AC performance characteristics of the SD24_B.
Table 5-41. SD24_B AC Performance
fSD24 = 32 kHz, SD24OSRx = 512, SD24REFS = 1
PARAMETER

SINAD

(1)

TEST CONDITIONS

Signal-to-noise + distortion ratio

VCC

MIN

TYP

SD24GAIN: 1

3V

89

SD24GAIN: 2

3V

85

SD24GAIN: 43V

84

SD24GAIN: 8

3V

86

3V

80

SD24GAIN: 32

3V

76

SD24GAIN: 64

3V

67

SD24GAIN: 128

3V

61

SD24GAIN: 16

fIN = 12 Hz (1)

MAX

UNIT

dB

The following voltages were applied to the SD24_B inputs:
VI,A+(t) = 0 V + VPP / 2 × sin(2π × fIN × t)
VI,A-(t) = 0 V – VPP / 2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VI,A+(t) – VI,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24_B recommended operating conditions).
95
90

SINAD – dB

85
80
75
70
65
60
55
32

64

128

256

512

1024

SD24OSRx

Figure 5-19. SINAD vs OSR(fSD24 = 1 MHz, SD24REFS = 1, SD24GAIN = 1)

Specifications
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9085

SINAD – dB

80

75

70

65

60
0.1

0.2

0.3

0.4

0.5
0.6
Vpp/Vref/Gain

0.7

0.8

0.9

1

Figure 5-20. SINAD vs VPP
Table 5-42 lists the external reference input requirements of the SD24_B.
Table 5-42. SD24_B External Reference Input
ensure correct input voltage range according to VREF
PARAMETERTEST CONDITIONS

VCC

MIN

TYP

MAX

1.0

1.20

1.5

V

50

nA

VREF(I)

Input voltage

SD24REFS = 0

3V

IREF(I)

Input current

SD24REFS = 0

3V58

Specifications

UNIT

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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 20185.16 ADC10_A
Table 5-43 lists the power supply and input range conditions of the ADC10_A.
Table 5-43. 10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC
AVCC

Analog supply voltage

AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V

V(Ax)Analog input voltage range (1)All ADC10_A pins

Operating supply current into
AVCC terminal, REF moduleand reference buffer off

fADC10CLK = 5 MHz, ADC10ON =1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 00

Operating supply current into
AVCC terminal, REF module
on, reference buffer on

fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 01

Operating supply current into
AVCC terminal, REF module
off, reference buffer on

MIN

TYP

MAX

UNIT

1.8

3.6

V

0

AVCC

V

2.2 V

70

105

3V

80

115

3V

130

185

fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 10, VEREF = 2.5 V

3V

108

160

Operating supply current into
AVCC terminal, REF module
off, reference buffer off

fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 11, VEREF = 2.5 V

3V

74

105

CI

Input capacitance

Only one terminal Ax can be selected at one timefrom the pad to the ADC10_A capacitor arrayincluding wiring and pad.

2.2 V

3.5

RI

Input MUX ON resistance

IADC10_A

(1)

µA

pF

AVCC > 2 V, 0 V ≤ VAx ≤ AVCC

36

1.8 V < AVCC < 2 V, 0 V ≤ VAx ≤ AVCC

96kΩ

The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The externalreference voltage requires decoupling capacitors. Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to
decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430x5xx and
MSP430x6xx Family User's Guide.

Table 5-44 lists the timing parameters of the ADC10_A.
Table 5-44. 10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER

VCC

MIN

TYP

MAX

UNIT

For specified performance of ADC10_A
linearity parameters

2.2 V, 3 V

0.45

5

5.5

MHz

Internal ADC10_A
oscillator (1)ADC10DIV = 0, fADC10CLK = fADC10OSC

2.2 V, 3 V

4.4

5.0

5.6

MHz

2.2 V, 3 V

2.4

Conversion time

REFON = 0, Internal oscillator,
12 ADC10CLK cycles, 10-bit modefADC10OSC = 4 MHz to 5 MHz

fADC10CLK
fADC10OSC

tCONVERTTEST CONDITIONSµs

External fADC10CLK from ACLK, MCLK or
SMCLK, ADC10SSEL ≠ 0
tADC10ON

Turnon settling time of
the ADCtSampleSampling time

(1)
(2)
(3)

See

3.0
12 ×
1 / fADC10CLK

(2)

100

RS = 1000 Ω, RI = 96 kΩ, CI = 3.5 pF (3)

1.8 V

3

RS = 1000 Ω, RI = 36 kΩ, CI = 3.5 pF (3)

3V

1

ns
µs

The ADC10OSC is sourced directly from MODOSC inside the UCS.
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are alreadysettled.
Approximately ei8ght Tau (t) are needed to get an error of less than ±0.5 LSB

Specifications
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Table 5-45. 10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCC

1.4 V ≤ (VeREF+ – VeREF–) ≤ 1.6 V, CVeREF+ = 20 pF

MIN

TYP

MAX
±1.0

UNIT

EI

Integrallinearity errorED

Differential
linearity error

1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF

2.2 V, 3 V

±1.0

LSB

EO

Offset error

1.4 V ≤ (VeREF+ – VeREF–), CVREF+ = 20 pF,
Internal impedance of source RS < 100 Ω

2.2 V, 3 V

±1.0

LSB

EG

Gain error

1.4 V ≤ (VeREF+ – VeREF–),
CVeREF+ = 20 pF, ADC10SREFx = 11b

2.2 V, 3 V

±1.0

LSB

ET

Total unadjusted
error

1.4 V ≤ (VeREF+ – VeREF–),
CVeREF+ = 20 pF, ADC10SREFx = 11b

2.2 V, 3 V

±2.0

LSB

MAX

UNIT

1.4

AVCC

V

2.2 V, 3 V

1.6 V < (VeREF+ – VeREF–) ≤ VAVCC, CVeREF+ = 20 pF

±1.0

±1.0

LSB

Table 5-46 lists the external reference requirements of the ADC10_A.
Table 5-46. 10-Bit ADC, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETERTEST CONDITIONS

VCC

MIN

TYP

VeREF+

Positive external reference
VeREF+ > VeREF– (2)voltage input

VeREF–

Negative externalreference voltage input

VeREF+ > VeREF– (3)

0

1.2

V

(VeREF+ –VeREF–)

Differential externalreference voltage input

VeREF+ > VeREF– (4)

1.4

AVCC

V

±26

µA

±1

µA

IVeREF+,
IVeREF–

CVeREF+/(1)
(2)
(3)
(4)
(5)

60

Static input current

Capacitance at VeREF+
or VeREF- terminal

1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTx = 0x0001,
Conversion rate 200 ksps

2.2 V, 3 V

1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTX = 0x1000,
Conversion rate 20 ksps

2.2 V, 3 V

See (5)

±8.5

10

µF

The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow therecommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VeREF to decouple the dynamic current required for an externalreference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide.

Specifications

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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 20185.17 REF
Table 5-47 lists the characteristics of the REF.
Table 5-47. REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Positive built-in reference
voltage

VREF+

AVCC minimum voltage,
Positive built-in reference
active

AVCC(min)Operating supply current
into AVCC terminal (1)IREF+

TEST CONDITIONS

VCC

MIN

TYP

MAX

REFVSEL = {2} for 2.5 V, REFON = 1

3V

2.47

2.51

2.55

REFVSEL = {1} for 2.0 V, REFON = 1

3V

1.95

1.99

2.03

REFVSEL = {0} for 1.5 V, REFON = 1

2.2 V, 3 V

1.46

1.50

1.54

REFVSEL = {0} for 1.5 V

1.8

REFVSEL = {1} for 2.0 V

2.2

REFVSEL = {2} for 2.5 V

2.7

UNIT
V

V

fADC10CLK = 5 MHz,REFON = 1, REFBURST = 0,
REFVSEL = {2} for 2.5 V

3V

23

30

fADC10CLK = 5 MHz,REFON = 1, REFBURST = 0,
REFVSEL = {1} for 2.0 V

3V

21

27

fADC10CLK = 5 MHz,REFON = 1, REFBURST = 0,
REFVSEL = {0} for 1.5 V

3V

19

25

10

50

µA

TCREF+

Temperature coefficient ofbuilt-in reference (2)REFVSEL = {0, 1, 2}, REFON = 1

ISENSOROperating supply current
into AVCC terminal

REFON = 1, ADC10ON = 1,
INCH = 0Ah, TA = 30°C

2.2 V

145

220

3V

170

245

VSENSORSee (3)

REFON = 1, ADC10ON = 1,
INCH = 0Ah, TA = 30°C

2.2 V

780

3V

780

VMID

AVCC divider at channel 11

ADC10ON = 1, INCH = 0Bh,
VMID is ~0.5 × VAVCC

2.2 V

1.08

1.1

1.12

3V

1.48

1.5

1.52

tSENSOR(sample)

Sample time required ifchannel 10 is selected (4)REFON = 1, ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB30µstVMID(sample)

Sample time required ifchannel 11 is selected (5)ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB

1µs

PSRR_DCPower supply rejection ratio(DC)

AVCC = AVCC (min) to AVCC(max),
TA = 25°C,
REFVSEL = {0, 1, 2}, REFON = 1

120

PSRR_ACPower supply rejection ratio(AC)

AVCC = AVCC (min) to AVCC(max),
TA = 25°C,
f = 1 kHz, ΔVpp = 100 mVREFVSEL = {0, 1, 2}, REFON = 1

1

mV/V

tSETTLE

Settling time of reference
voltage (6)AVCC = AVCC (min) to AVCC(max),
REFVSEL = {0, 1, 2}, REFON = 0→175µs

VSD24REF

SD24_B internal reference
voltage

SD24REFS = 1

3V

tON

SD24_B internal reference
turnon time (7)SD24REFS = 0→1, CREF = 100 nF

3V

(1)
(2)
(3)
(4)
(5)
(6)
(7)

1.137

1.151

ppm/
°C
µA
mV

300

1.165

200

V

µV/V

V
µs

The internal reference current is supplied through the AVCC terminal. Consumption is independent of the ADC10ON control bit, unless aconversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
The condition is that the error in a conversion started after tREFON is ≤ 1 LSB.
The condition is that SD24_B conversion started after tON should guarantee specified SINAD values for the selected Gain, OSR andfSD24.

Specifications
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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5.18 Flash Memory
Table 5-48 lists the characteristics of the flash memory.
Table 5-48. Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER

TJ

MIN

TYP

UNIT

DVCC(PGM/ERASE)

Program and erase supply voltage

3.6

V

IPGM

Average supply current from DVCC during program

3

5

mA

IERASE

Average supply current from DVCC during erase

6

11

mA

IMERASE, IBANK

Average supply current from DVCC during mass erase or bank erase

6

11

mA

tCPT

Cumulative program time

1.8

MAX

(1)

16
104

Program and erase endurancetRetention

Data retention duration

25°C
(2)

105

ms
cycles

100

years

tWord

Word or byte program time

64

85

µs

tBlock, 0

Block program time for first byte or word (2)

49

65

µs

tBlock, 1–(N–1)

Block program time for each additional byte or word, except for lastbyte or word (2)

37

49

µs

tBlock, N

Block program time for last byte or word (2)

55

73

µs

tEraseErase time for segment erase, mass erase, and bank erase whenavailable (2)

23

32

ms

fMCLK,MGR

MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)

0

1

MHz

(1)
(2)

The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word- or byte-write and block-write modes.
These values are hardwired into the state machine of the flash controller.

5.19 Emulation and Debug
Table 5-49 lists the characteristics of the JTAG and Spy-Bi-Wire interface.
Table 5-49. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER

VCC

MIN

TYP

MAX

UNIT

fSBW

Spy-Bi-Wire input frequency

2.2 V, 3 V

0

20

MHz

tSBW,Low

Spy-Bi-Wire low clock pulse duration

2.2 V, 3 V

0.025

15

µs

tSBW, En

Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1)2.2 V, 3 V

1µstSBW,Rst

Spy-Bi-Wire return to normal operation time

100

µs

fTCK

TCK input frequency for 4-wire JTAG (2)Rinternal

Internal pulldown resistance on TEST

(1)
(2)

62

15
2.2 V

0

5

3V

0

10

2.2 V, 3 V

45

60

80

MHz
kΩ

Tools that access the Spy-Bi-Wire interface must wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.

Specifications

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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

6 Detailed Description
6.1

CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction withseven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, arededicated as program counter, stack pointer, status register, and constant generator, respectively. The
remaining registers are general-purpose registers (see 図 6-1).
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be
managed with all instructions.
Program Counter

PC/R0

Stack Pointer

SP/R1

Status Register

SR/CG1/R2

Constant Generator

CG2/R3General-Purpose Register

R4

General-Purpose Register

R5

General-Purpose Register

R6

General-Purpose Register

R7

General-Purpose Register

R8

General-Purpose Register

R9

General-Purpose Register

R10

General-Purpose Register

R11

General-Purpose Register

R12

General-Purpose Register

R13

General-Purpose Register

R14

General-Purpose RegisterR15

図 6-1. Integrated CPU Registers

Detailed Description
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Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word andbyte data. 表 6-1 lists examples of the three types of instruction formats. 表 6-2 lists the address modes.
表 6-1. Instruction Word Formats
INSTRUCTION WORD FORMAT

EXAMPLEOPERATION

Dual operands, source and destination

ADD R4,R5

R4 + R5 → R5

Single operands, destination only

CALL R8

PC → (TOS), R8 → PC

Relative jump, unconditional or conditional

JNE

Jump-on-equal bit = 0

表 6-2. Address Mode Descriptions
ADDRESS MODE

S (1)

D (1)

SYNTAX

EXAMPLE

Register++

MOV Rs,Rd

MOV R10,R11

R10 → R11

Indexed++MOV X(Rn),Y(Rm)

MOV 2(R5),6(R6)M(2+R5) → M(6+R6)

Symbolic (PC relative)++

MOV EDE,TONI

Absolute++

MOV & MEM, & TCDAT

Indirect+

MOV @Rn,Y(Rm)

MOV @R10,Tab(R6)

M(R10) → M(Tab+R6)

Indirect autoincrement+

MOV @Rn+,Rm

MOV @R10+,R11

M(R10) → R11
R10 + 2 → R10

Immediate+

MOV #X,TONI

MOV #45,TONI#45 → M(TONI)(1)

S = source, D = destination

64

Detailed Description

OPERATION

M(EDE) → M(TONI)
M(MEM) → M(TCDAT)

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6.3

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Operating Modes
These microcontrollers have one active mode and seven software-selectable low-power modes ofoperation. An interrupt event can wake up the device from any of the low-power modes, service therequest, and restore back to the low-power mode on return from the interrupt program.
Software can configure the following operating modes:
•
•

•

•

•

•

•

•

Active mode (AM)– All clocks are active
Low-power mode 0 (LPM0)– CPU is disabled– ACLK and SMCLK remain active, MCLK is disabled– FLL loop control remains active
Low-power mode 1 (LPM1)– CPU is disabled– FLL loop control is disabled– ACLK and SMCLK remain active, MCLK is disabled
Low-power mode 2 (LPM2)– CPU is disabled– MCLK and FLL loop control and DCOCLK are disabled– DC generator of the DCO remains enabled– ACLK remains active
Low-power mode 3 (LPM3)– CPU is disabled– MCLK, FLL loop control, and DCOCLK are disabled– DC generator of the DCO is disabled– ACLK remains active
Low-power mode 4 (LPM4)– CPU is disabled– ACLK is disabled– MCLK, FLL loop control, and DCOCLK are disabled– DC generator of the DCO is disabled– Crystal oscillator is stopped– Complete data retention
Low-power mode 3.5 (LPM3.5)– Internal regulator disabled– No RAM retention, Backup RAM retained– I/O pad state retention– RTC clocked by low-frequency oscillator– Wake-up input from RST/NMI, RTC_C events, Ports P1 and P2
Low-power mode 4.5 (LPM4.5)– Internal regulator disabled– No RAM retention, Backup RAM retained– RTC is disabled– I/O pad state retention– Wake-up input from RST/NMI, Ports P1 and P2

Detailed Description
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Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see 表
6-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
表 6-3. Interrupt Sources, Flags, and Vectors of MSP430F67xx Configurations
INTERRUPT SOURCEINTERRUPT FLAGSYSTEM
INTERRUPT

WORD
ADDRESSPRIORITY

System Reset
Power upExternal reset
Watchdog time-out, key violation
Flash memory key violation

WDTIFG, KEYV (SYSRSTIV) (1) (2)Reset

0FFFEh63, highest

System NMI
PMM
Vacant memory access
JTAG mailbox

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,JMBOUTIFG (SYSSNIV) (1) (3)(Non)maskable

0FFFCh62

User NMI
NMI
Oscillator fault
Flash memory access violation
Supply switch

NMIIFG, OFIFG, ACCVIFG, AUXSWNMIFG(SYSUNIV) (1) (3)(Non)maskable

0FFFAh61

Watchdog Timer_A interval timer
mode

WDTIFG

Maskable

0FFF8h60

eUSCI_A0 receive or transmit

UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) (4)Maskable

0FFF6h59

eUSCI_B0 receive or transmit

UCB0RXIFG, UCB0TXIFG (UCB0IV) (1) (4)Maskable

0FFF4h58

ADC10_A

ADC10IFG0, ADC10INIFG, ADC10LOIFG,
ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG(ADC10IV) (1) (4)Maskable

0FFF2h57

SD24_B

SD24_B Interrupt Flags (SD24IV) (1) (4)Maskable

0FFF0h56

Timer TA0

TA0CCR0 CCIFG0 (4)Maskable

0FFEEh55

Timer TA0

TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,
TA0IFG (TA0IV) (1) (4)Maskable

0FFECh54

eUSCI_A1 receive or transmit

UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (4)Maskable

0FFEAh53

eUSCI_A2 receive or transmit

UCA2RXIFG, UCA2TXIFG (UCA2IV) (1) (4)Maskable

0FFE8h52(1) (4)Maskable

0FFE6h51

DMA

DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1) (4)Maskable

0FFE4h50

Timer TA1

TA1CCR0 CCIFG0 (4)Maskable

0FFE2h49

Timer TA1

TA1CCR1 CCIFG1,
TA1IFG (TA1IV) (1) (4)Maskable

0FFE0h48

Maskable

0FFDEh47

Maskable

0FFDCh46

Maskable0FFDAh45

Auxiliary supplies

(1)
(2)
(3)
(4)
66

Auxiliary Supplies Interrupt Flags (AUXIV)

I/O port P1

P1IFG.0 to P1IFG.7 (P1IV)

Timer TA2

TA2CCR0 CCIFG0 (4)Timer TA2

TA2CCR1 CCIFG1,TA2IFG (TA2IV) (1) (4)(1) (4)(1) (4)I/O port P2

P2IFG.0 to P2IFG.7 (P2IV)

Maskable

0FFD8h44

Timer TA3

TA3CCR0 CCIFG0(4)

Maskable

0FFD6h43

Timer TA3

TA3CCR1 CCIFG1,
TA3IFG (TA3IV) (1) (4)Maskable

0FFD4h42

LCD_C

LCD_C Interrupt Flags (LCDCIV) (1) (4)Maskable

0FFD2h41

RTC_C

RTCOFIFG, RTCRDYIFG, RTCTEVIFG,
RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV) (1) (4)Maskable

0FFD0h40

Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.
Interrupt flags are in the module.
Detailed Description

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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

表 6-3. Interrupt Sources, Flags, and Vectors of MSP430F67xx Configurations (continued)(5)

INTERRUPT SOURCEINTERRUPT FLAG

Reserved

Reserved (5)SYSTEM
INTERRUPT

WORD
ADDRESSPRIORITY

0FFCEh39⋮⋮

0FF80h0, lowest

Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintaincompatibility with other devices, TI recommends reserving these locations.

6.5

Memory Organization
表 6-4 and 表 6-5 summarize the memory map for the devices.
表 6-4. Memory Organization

Main Memory(flash)MSP430F6730
MSP430F6720

MSP430F6731
MSP430F6721

MSP430F6733
MSP430F6723

16KB

32KB

64KB

00FFFFh to 00FF80h

00FFFFh to 00FF80h

00FFFFh to 00FF80h

Bank 3

not available

not available

not available

Bank 2

not available

not available

not available

Bank 1

not available

16KB
00FFFFh to 00C000h

32KB
013FFFh to 00C000h

Bank 0

16KB
00FFFFh to 00C000h

16KB
00BFFFh to 008000h

32KB
00BFFFh to 004000h

Total Size

Main: Interrupt
vectorMain: code
memoryTotal Size

1KB

2KB

4KB

Sector 3

not available

not available

not available

Sector 2

not available

not available

not available

Sector 1

not available

not available

2KB
002BFFh to 002400h

Sector 0

1KB
001FFFh to 001C00h

2KB
0023FFh to 001C00h

2KB
0023FFh to 001C00h

Info A

128 B
0019FFh to 001980h

128 B
0019FFh to 001980h

128 B
0019FFh to 001980hInfo B

128 B
00197Fh to 001900h

128 B
00197Fh to 001900h

128 B
00197Fh to 001900h

Info C

128 B
0018FFh to 001880h

128 B
0018FFh to 001880h

128 B
0018FFh to 001880hInfo D

128 B
00187Fh to 001800h

128 B
00187Fh to 001800h

128 B
00187Fh to 001800h

BSL 3

512 B
0017FFh to 001600h

512 B
0017FFh to 001600h

512 B
0017FFh to 001600h

BSL 2

512 B
0015FFh to 001400h

512 B
0015FFh to 001400h

512 B
0015FFh to 001400h

BSL 1

512 B
0013FFh to 001200h

512 B
0013FFh to 001200h

512 B
0013FFh to 001200h

BSL 0

512 B
0011FFh to 001000h

512 B
0011FFh to 001000h

512 B
0011FFh to 001000h

4KB
000FFFh to 0h

4KB
000FFFh to 0h

4KB
000FFFh to 0h

RAM

Information
memory (flash)

Bootloader (BSL)
memory (flash)

Peripherals

Detailed Description
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表 6-5. Memory Organization
MSP430F6734
MSP430F6724

MSP430F6735
MSP430F6725

MSP430F6736
MSP430F6726

96KB

128KB

128KB

00FFFFh to 00FF80h

00FFFFh to 00FF80h

00FFFFh to 00FF80h

Bank 3

not available

32KB
023FFFh to 01C000h

32KB
023FFFh to 01C000h

Bank 232KB
01BFFFh to 014000h

32KB
01BFFFh to 014000h

32KB
01BFFFh to 014000h

Bank 132KB
013FFFh to 00C000h

32KB
013FFFh to 00C000h

32KB
013FFFh to 00C000h

Bank 032KB
00BFFFh to 004000h

32KB
00BFFFh to 004000h

32KB
00BFFFh to 004000h

Total
Size

4KB

4KB

8KB

Sector 3

not available

not available

2KB
003BFFh to 003400h

Sector 2

not available

not available

2KB
0033FFh to 002C00h

Sector 1

2KB
002BFFh to 002400h

2KB
002BFFh to 002400h

2KB
002BFFh to 002400h

Sector 0

2KB
0023FFh to 001C00h

2KB
0023FFh to 001C00h

2KB
0023FFh to 001C00h

Info A

128 B
0019FFh to 001980h

128 B
0019FFh to 001980h

128 B
0019FFh to 001980hInfo B

128 B
00197Fh to 001900h

128 B
00197Fh to 001900h

128 B
00197Fh to 001900h

Info C

128 B
0018FFh to 001880h

128 B
0018FFh to 001880h

128 B
0018FFh to 001880hInfo D

128 B
00187Fh to 001800h

128 B
00187Fh to 001800h

128 B
00187Fh to 001800h

BSL 3

512 B
0017FFh to 001600h

512 B
0017FFh to 001600h

512 B
0017FFh to 001600h

BSL 2

512 B
0015FFh to 001400h

512 B
0015FFh to 001400h

512 B
0015FFh to 001400h

BSL 1

512 B
0013FFh to 001200h

512 B
0013FFh to 001200h

512 B
0013FFh to 001200h

BSL 0

512 B
0011FFh to 001000h

512 B
0011FFh to 001000h

512 B
0011FFh to 001000h

4KB
000FFFh to 0h

4KB
000FFFh to 0h

4KB
000FFFh to 0h

Total
Size

Main Memory (flash)
Main: Interrupt vector

Main: code memory

RAM

Information memory(flash)Bootloader (BSL)
memory (flash)

Peripherals

68

Detailed Description

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6.6

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

Bootloader (BSL)
The BSL enables users to program the flash memory or RAM using various serial interfaces. Access tothe device memory through the BSL is protected by an user-defined password. BSL entry requires a
specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of
the features of the BSL and its implementation, see MSP430™ Flash Device Bootloader (BSL) User's
Guide. 表 6-6 lists the BSL pin requirements.
表 6-6. UART BSL Pin Requirements and Functions
DEVICE SIGNALBSL FUNCTION

RST/NMI/SBWTDIO

Entry sequence signal

TEST/SBWTCK

Entry sequence signal

P3.0

Data transmit

6.7

JTAG Operation

6.7.1

JTAG Standard Interface

P3.1

Data receive

DVCC

Power supply

DVSS

Ground supply

The MSP430 family supports the standard JTAG interface, which requires four signals for sending andreceiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used toenable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. 表 6-7 lists the JTAG pin requirements. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools
User's Guide and MSP430 Programming With the JTAG Interface.
表 6-7. JTAG Pin Requirements and Functions
DEVICE SIGNAL

DIRECTIONFUNCTION

PJ.3/ACLK/TCKIN

JTAG clock input

PJ.2/ADC10CLK/TMS

IN

JTAG state control

PJ.1/MCLK/TDI/TCLKIN

JTAG data input and TCLK input

PJ.0/SMCLK/TDO

OUT

JTAG data output

TEST/SBWTCKIN

Enable JTAG pins

RST/NMI/SBWTDIO

IN

External reset

DVCC

Power supply

DVSS

Ground supply

Detailed Description
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MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

6.7.2

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Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the 2-wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. 表 6-8
lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools anddevice programmers, see the MSP430 Hardware Tools User's Guide and MSP430 Programming With the
JTAG Interface.
表 6-8. Spy-Bi-Wire Pin Requirements and Functions

6.8

DEVICE SIGNAL

DIRECTIONFUNCTION

TEST/SBWTCKIN

Spy-Bi-Wire clock input

RST/NMI/SBWTDIO

IN, OUT

Spy-Bi-Wire data input and output

DVCC

Power supply

DVSS

Ground supply

Flash Memory
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-systemby the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
Features of the flash memory include:
•
•
•
•

6.9

Flash memory has n segments of main memory and four segments of information memory (A to D) of 128 bytes
each. Each segment in main memory is 512 bytes in size.
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called
information memory.
Segment A can be locked separately.

RAM
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage;
however, all data are lost. Features of the RAM include:•••

RAM has n sectors of 2KB each.
Each sector 0 to n can be complete disabled; however, data retention is lost.
Each sector 0 to n automatically enters low-power retention mode when possible.

6.10 Backup RAM
The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5. This
backup RAM is part of the Backup subsystem in MSP430F67xx that operates on dedicated power supply
AUXVCC3. There are 8 bytes of backup RAM available in this device. The backup RAM can be word-wiseaccessed through the registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3. The backup RAM
registers cannot be accessed by the CPU when the high-side SVS is disabled by the user.

70

Detailed Description

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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 20186.11 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx
Family User's Guide.

6.11.1 Oscillator and System Clock
The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, aninternal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator(REFO), and an integrated internal digitally controlled oscillator (DCO). The UCS module is designed tomeet the requirements of both low system cost and low power consumption. The UCS module features
digital frequency-locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the
DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal DCO
provides a fast turnon clock source and stabilizes in 3 µs (typical). The UCS module provides the following
clock signals:••••

Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, the internal low-frequency oscillator (VLO), or thetrimmed low-frequency oscillator (REFO).
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made available
to ACLK.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by same
sources made available to ACLK.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

6.11.2 Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device andcontains programmable output levels to provide for power optimization. The PMM also includes supply
voltage supervisor (SVS) and supply voltage monitor (SVM) circuitry, as well as brownout protection. The
brownout circuit is implemented to provide the proper internal reset signal to the device during power onand power off. The SVS and SVM circuitry detects if the supply voltage drops below a user-selectablelevel and supports both supply voltage supervision (the device is automatically reset) and supply voltage
monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary
supply and core supply.

6.11.3 Auxiliary Supply System
The auxiliary supply system provides the possibility to operate the device from auxiliary supplies when the
primary supply fails.There are two auxililary supplies AUXVCC1 and AUXVCC2 supported in
MSP430F67xx. This module supports automatic and manual switching from primary supply to auxiliary
suppllies while maintaining full functionality. It allows threshold based monitoring of primary and auxiliary
supplies. The device can be started from primary supply or from AUXVCC1, whichever is higher. The
auxiliary supply system enables internal monitoring of voltage levels on the primary and auxiliary supplies
using ADC10_A. This module also implements a simple charger for the backup supplies.

6.11.4 Backup Subsystem
The backup subsystem operates on a dedicated power supply, AUXVCC3. This subsystem includes lowfrequency oscillator (XT1), RTC module, and backup RAM. The functionality of backup subsystem isretained during LPM3.5. The backup subsystem module registers cannot be accessed by CPU when thehigh-side SVS is disabled by the user. Keep the high-side SVS enabled (SVSHMD = 1 and SVSMHACE =0) to turn off the low-frequency oscillator (XT1) in LPM4.

Detailed Description
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6.11.5 Digital I/O
Up to nine 8-bit I/O ports are implemented. For 100-pin options, Ports P1 to P8 are complete, and P9 isreduced to 4-bit I/O. For 80-pin options, Ports P1 to P6 are complete, and P7, P8, and P9 are completely
removed. Port PJ contains four individual I/O pins, common to all devices. All I/O bits are individuallyprogrammable.
•
•
•
•
•
•

Any combination of input, output, and interrupt conditions is possible.
Pullup or pulldown on all ports is programmable.
Programmable drive strength on all ports.
Edge-selectable interrupt and LPM3.5 or LPM4.5 wake-up input are available for all bits of ports P1 and P2.
Read and write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PE).

6.11.6 Port Mapping Controller
The port mapping controller allows flexible and reconfigurable mapping of digital functions to P1, P2, andP3 (see 表 6-9). 表 6-10 lists the default settings for all pins that support port mapping.
表 6-9. Port Mapping Mnemonics and Functions
VALUE

PxMAPy MNEMONICINPUT PIN FUNCTIONOUTPUT PIN FUNCTION0

PM_NONE

None

DVSS

1
2
3
4
5
6

eUSCI_A0 UART RXD (direction controlled by eUSCI – Input)

PM_UCA0SOMI

eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)PM_UCA0TXD

eUSCI_A0 UART TXD (direction controlled by eUSCI – Output)

PM_UCA0SIMO

eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)PM_UCA0CLK

eUSCI_A0 clock input/output (direction controlled by eUSCI)PM_UCA0STE

eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI)PM_UCA1RXD

eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)

PM_UCA1SOMI

eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)PM_UCA1TXD

eUSCI_A1 UART TXD (direction controlled by eUSCI – Output)

PM_UCA1SIMO

eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)7

PM_UCA1CLK

eUSCI_A1 clock input/output (direction controlled by eUSCI)8

PM_UCA1STE

eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)910

PM_UCA2RXD

eUSCI_A2 UART RXD (direction controlled by eUSCI – Input)

PM_UCA2SOMI

eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)PM_UCA2TXD

eUSCI_A2 UART TXD (direction controlled by eUSCI – Output)

PM_ UCA2SIMO

eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)11

PM_UCA2CLK

eUSCI_A2 clock input/output (direction controlled by eUSCI)12

PM_UCA2STE

eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)

13
14

72

PM_UCA0RXD

PM_UCB0SIMO

eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)PM_UCB0SDA

eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)PM_UCB0SOMI

eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)PM_UCB0SCL

eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)15

PM_UCB0CLK

eUSCI_B0 clock input/output (direction controlled by eUSCI)16

PM_UCB0STE

eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI)17

PM_TA0.0

TA0 CCR0 capture input CCI0A

TA0 CCR0 compare output Out018

PM_TA0.1

TA0 CCR1 capture input CCI1A

TA0 CCR1 compare output Out1

19

PM_TA0.2

TA0 CCR2 capture input CCI2A

TA0 CCR2 compare output Out220

PM_TA1.0

TA1 CCR0 capture input CCI0A

TA1 CCR0 compare output Out021

PM_TA1.1

TA1 CCR1 capture input CCI1A

TA1 CCR1 compare output Out1

22

PM_TA2.0

TA2 CCR0 capture input CCI0A

TA2 CCR0 compare output Out023

PM_TA2.1

TA2 CCR1 capture input CCI1A

TA2 CCR1 compare output Out1

Detailed Description

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

表 6-9. Port Mapping Mnemonics and Functions (continued)
VALUE

PxMAPy MNEMONICINPUT PIN FUNCTIONOUTPUT PIN FUNCTION24

PM_TA3.0

TA3 CCR0 capture input CCI0A

TA3 CCR0 compare output Out025

PM_TA3.1

TA3 CCR1 capture input CCI1A

TA3 CCR1 compare output Out1

PM_TACLK

Timer_A clock input toTA0, TA1, TA2, TA3

None

None

RTC_C clock output

26

PM_RTCCLK27

PM_SDCLK

SD24_B bitstream clock input/output (direction controlled by SD24_B)

28

PM_SD0DIO

SD24_B converter-0 bitstream data input/output (direction controlled by SD24_B)

29

PM_SD1DIO

SD24_B converter-1 bitstream data input/output (direction controlled by SD24_B)

30
31 (0FFh)(1)(1)

PM_SD2DIO

SD24_B converter-2 bitstream data input/output (direction controlled by SD24_B)

PM_ANALOG

Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents
when applying analog signals.

The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are
ignored, which results in a read value of 31.

表 6-10. Default Mapping
PIN NAME

PxMAPy MNEMONICINPUT PIN FUNCTIONOUTPUT PIN FUNCTION

P1.0/PM_TA0.0/
VeREF-/A2

PM_TA0.0

TA0 CCR0 capture input CCI0A

TA0 CCR0 compare output Out0

P1.1/PM_TA0.1/
VeREF+/A1

P1.1/PM_TA0.1/
VeREF+/A1

PM_TA0.1

TA0 CCR1 capture input CCI1A

TA0 CCR1 compare output Out1

P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0

P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0

PM_UCA0RXD,
PM_UCA0SOMI

eUSCI_A0 UART RXD(direction controlled by eUSCI – input),eUSCI_A0 SPI slave out master in(direction controlled by eUSCI)

P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03

P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03

PM_UCA0TXD,
PM_UCA0SIMO

eUSCI_A0 UART TXD(direction controlled by eUSCI – output),eUSCI_A0 SPI slave in master out(direction controlled by eUSCI)

P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13

P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13

PM_UCA1RXD,
PM_UCA1SOMI

eUSCI_A1 UART RXD(direction controlled by eUSCI – input),eUSCI_A1 SPI slave out master in(direction controlled by eUSCI)

P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23

P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23

PM_UCA1TXD,
PM_UCA1SIMO

eUSCI_A1 UART TXD(direction controlled by eUSCI – output),eUSCI_A1 SPI slave in master out(direction controlled by eUSCI)

P1.6/PM_UCA0CLK/
COM4

P1.6/PM_UCA0CLK/
COM4

PM_UCA0CLK

eUSCI_A0 clock input/output (direction controlled by eUSCI)

P1.7/PM_UCB0CLK/
COM5

P1.7/PM_UCB0CLK/
COM5

PM_UCB0CLK

eUSCI_B0 clock input/output (direction controlled by eUSCI)

P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6

P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6/S39

PM_UCB0SOMI,
PM_UCB0SCL

eUSCI_B0 SPI slave out master in(direction controlled by eUSCI),
eUSCI_B0 I2C clock(open drain and direction controlled by eUSCI)

P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7

P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7/S38

PM_UCB0SIMO,
PM_UCB0SDA

eUSCI_B0 SPI slave in master out(direction controlled by eUSCI),
eUSCI_B0 I2C data
(open drain and direction controlled by eUSCI)

P2.2/PM_UCA2RXD/
PM_UCA2SOMI

P2.2/PM_UCA2RXD/
PM_UCA2SOMI/S37

PM_UCA2RXD,
PM_UCA2SOMI

eUSCI_A2 UART RXD(direction controlled by eUSCI – input),eUSCI_A2 SPI slave out master in(direction controlled by eUSCI)

P2.3/PM_UCA2TXD/
PM_UCA2SIMO

P2.3/PM_UCA2TXD/
PM_UCA2SIMO/S36

PM_UCA2TXD,
PM_UCA2SIMO

eUSCI_A2 UART TXD(direction controlled by eUSCI – output),eUSCI_A2 SPI slave in master out(direction controlled by eUSCI)

P2.4/PM_UCA1CLK

P2.4/PM_UCA1CLK/S35

PM_UCA1CLK

eUSCI_A1 clock input/output (direction controlled by eUSCI)

P2.5/PM_UCA2CLK

P2.5/PM_UCA2CLK/S34

PM_UCA2CLK

P2.6/PM_TA1.0

P2.6/PM_TA1.0/S33

PZ

PN

P1.0/PM_TA0.0/
VeREF-/A2

PM_TA1.0

eUSCI_A2 clock input/output (direction controlled by eUSCI)TA1 CCR0 capture input CCI0A

TA1 CCR0 compare output Out0

Detailed Description
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表 6-10. Default Mapping (continued)
PIN NAME
PZ

PN

PxMAPy MNEMONICINPUT PIN FUNCTIONOUTPUT PIN FUNCTION

P2.7/PM_TA1.1

P2.7/PM_TA1.1/S32

PM_TA1.1

TA1 CCR1 capture input CCI1A

TA1 CCR1 compare output Out1

P3.0/PM_TA2.0

P3.0/PM_TA2.0/S31

PM_TA2.0

TA2 CCR0 capture input CCI0A

TA2 CCR0 compare output Out0

P3.1/PM_TA2.1

P3.1/PM_TA2.1/S30

PM_TA2.1

TA2 CCR1 capture input CCI1A

TA2 CCR1 compare output Out1

P3.2/PM_TACLK/
PM_RTCCLK

P3.2/PM_TACLK/
PM_RTCCLK/S29

PM_TACLK,
PM_RTCCLK

Timer_A clock input toTA0, TA1, TA2, TA3

RTC_C clock output

P3.3/PM_TA0.2

P3.3/PM_TA0.2/S28

PM_TA0.2

TA0 CCR2 capture input CCI2A

TA0 CCR2 compare output Out2

P3.4/PM_SDCLK/S39

P3.4/PM_SDCLK/S27

PM_SDCLK

SD24_B bitstream clock input/output(direction controlled by SD24_B)

P3.5/PM_SD0DIO/S38

P3.5/PM_SD0DIO/S26

PM_SD0DIO

SD24_B converter-0 bitstream data input/output(direction controlled by SD24_B)

P3.6/PM_SD1DIO/S37

P3.6/PM_SD1DIO/S25

PM_SD1DIO

SD24_B converter-1 bitstream data input/output(direction controlled by SD24_B)

P3.7/PM_SD2DIO/S36

P3.7/PM_SD2DIO/S24

PM_SD2DIO

SD24_B converter-2 bitstream data input/output(direction controlled by SD24_B)

6.11.7 System Module (SYS)The SYS module handles many of the system functions within the device. These include power-on reset(POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector
generators, bootloader entry mechanisms, as well as, configuration management (device descriptors). It
also includes a data exchange mechanism through JTAG called a JTAG mailbox that can be used in theapplication. 表 6-11 lists the SYS module interrupt vector registers.
表 6-11. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTERSYSRSTIV, System Reset74

Detailed Description

INTERRUPT EVENT

WORD
ADDRESSOFFSETNo interrupt pending

00h

Brownout (BOR)02h

RST/NMI (POR)

04h

DoBOR (BOR)

06h

Wakeup from LPMx.5 (BOR)

08h

Security violation (BOR)

0Ah

SVSL (POR)

0Ch

SVSH (POR)

0Eh

SVML_OVP (POR)
SVMH_OVP (POR)

019Eh

PRIORITY

Highest10h
12h

DoPOR (POR)

14h

WDT time-out (PUC)16h

WDT key violation (PUC)18h

KEYV flash key violation (PUC)

1Ah

Reserved

1Ch

Peripheral area fetch (PUC)

1Eh

PMM key violation (PUC)

20h

Reserved

22h to 3Eh

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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

表 6-11. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR REGISTERINTERRUPT EVENT

WORD
ADDRESSOFFSETNo interrupt pending

00h

SVMLIFG02h

SVMHIFG04h

DLYLIFG

06h

DLYHIFGSYSSNIV, System NMI

Highest08h

VMAIFG

019Ch

0Ah

JMBINIFG

0Ch

JMBOUTIFG

0Eh

VLRLIFG10h

VLRHIFG

12h

Reserved

14h to 1Eh

No interrupt pending

00h

NMIIFG02h

OFIFG

SYSUNIV, User NMI

PRIORITY

019Ah

ACCVIFG

LowestHighest

04h
06h

AUXSWNMIFG

08h

Reserved

0Ah to 1Eh

Lowest6.11.8 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the timer can be configured as an interval timer and can generateinterrupts at selected time intervals.

6.11.9 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPUintervention. For example, the DMA controller can be used to move data from the ADC10_A conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral. 表 6-12 lists the triggers that are available to start
DMA transfer.
表 6-12. DMA Trigger Assignments (1)TRIGGER(1)

CHANNEL0

1

0

DMAREQ

1

TA0CCR0 CCIFG

2

TA0CCR2 CCIFG

3

TA1CCR0 CCIFG

4

Reserved

5

TA2CCR0 CCIFG

6

Reserved

7

TA3CCR0 CCIFG

8

Reserved

2

Reserved DMA triggers may be used by other devices in the family.
Reserved DMA triggers do not cause a DMA trigger event whenselected.

Detailed Description
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表 6-12. DMA Trigger Assignments(1) (continued)
TRIGGERCHANNEL
0

1

9

Reserved

10

Reserved

11

Reserved

12

Reserved

13

SD24IFG

14

Reserved

15

Reserved

16

UCA0RXIFG

17

UCA0TXIFG

18

UCA1RXIFG

19

UCA1TXIFG

20

UCA2RXIFG

21

UCA2TXIFG

22

UCB0RXIFG023

UCB0TXIFG024

ADC10IFG025

Reserved

26

Reserved

27

Reserved

28

Reserved

29
30
31

2

MPY readyDMA2IFGDMA0IFGDMA1IFG

Reserved

6.11.10 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

6.11.11 Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication
as well as signed and unsigned multiply-and-accumulate operations.

6.11.12 Enhanced Universal Serial Communication Interface (eUSCI)The eUSCI module is used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3- or 4-pin) and I2C, and asynchronous communication protocols
such as UART, enhanced UART with automatic baudrate detection, and IrDA.
The eUSCI_An module supports for SPI (3- or 4-pin), UART, enhanced UART, or IrDA.
The eUSCI_Bn module supports for SPI (3- or 4-pin) or I2C.
Three eUSCI_A and one eUSCI_B modules are implemented in MSP430F67xx devices.

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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

6.11.13 ADC10_A
The ADC10_A module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit
SAR core, sample select control, reference generator, and a conversion results buffer. A window
comparator with a lower and upper limits allows CPU-independent result monitoring with three window
comparator interrupt flags.

6.11.14 SD24_B
The SD24_B module integrates up to three independent 24-bit sigma-delta analog-to-digital converters.
Each converter is designed with a fully differential analog input pair and programmable gain amplifier input
stage. The converters are based on second-order over-sampling sigma-delta modulators and digitaldecimation filters. The decimation filters are comb type filters with selectable oversampling ratios of up to1024.

Detailed Description
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6.11.15 TA0
TA0 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA0 can support
multiple capture/compares, PWM outputs, and interval timing (see 表 6-13). TA0 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from eachof the capture/compare registers.
表 6-13. TA0 Signal Connections
DEVICE INPUT SIGNAL

MODULE INPUT NAME

PM_TACLKTACLKMODULE BLOCKMODULE OUTPUT
SIGNALDEVICE OUTPUT
SIGNAL

Timer

NA

NA

ACLK (internal)

ACLK

SMCLK (internal)

SMCLK

PM_TACLKINCLK

PM_TA0.0

CCI0A

DVSS

CCI0B

DVSS

GND

DVCC

VCC

PM_TA0.1

CCI1A

PM_TA0.1

ACLK (internal)

CCI1B

ADC10_A (internal)
ADC10SHSx = {1}

DVSS

GND

PM_TA0.0
CCR0

TA0

CCR1

DVCC

VCC

PM_TA0.2

CCI2A

DVSS

CCI2B

DVSS

GND

DVCC

VCC

TA1

SD24_B (internal)
SD24SCSx = {1}PM_TA0.2

CCR2

TA2

6.11.16 TA1
TA1 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA1 can support multiple
capture/compares, PWM outputs, and interval timing (see 表 6-14). TA1 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of thecapture/compare registers.
表 6-14. TA1 Signal Connections
DEVICE INPUT SIGNAL

MODULE INPUT NAME

PM_TACLK

TACLK

78

ACLK (internal)

ACLK

SMCLK (internal)

SMCLK

PM_TACLKINCLK

PM_TA1.0

CCI0A

DVSS

CCI0B

DVSS

GND

DVCC

VCC

PM_TA1.1

CCI1A

ACLK (internal)

CCI1B

DVSS

GND

DVCC

VCC

Detailed Description

MODULE BLOCK

Timer

MODULE OUTPUT
SIGNALNA

DEVICE OUTPUT
SIGNALPZ

NA

PM_TA1.0
CCR0

TA0

PM_TA1.1
CCR1

TA1

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6.11.17 TA2TA2 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA2 can support multiple
capture/compares, PWM outputs, and interval timing (see 表 6-15). TA2 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of thecapture/compare registers.
表 6-15. TA2 Signal Connections
DEVICE INPUT SIGNAL

MODULE INPUT NAME

PM_TACLKTACLKMODULE BLOCKMODULE OUTPUT
SIGNALDEVICE OUTPUT
SIGNAL

Timer

NA

NA

ACLK (internal)

ACLK

SMCLK (internal)

SMCLK

PM_TACLKINCLK

PM_TA2.0

CCI0A

DVSS

CCI0B

DVSS

GND

DVCC

VCC

PM_TA2.1

CCI1A

PM_TA2.1

ACLK (internal)

CCI1B

SD24_B (internal)
SD24SCSx = {2}

DVSS

GND

DVCC

VCC

PM_TA2.0
CCR0

TA0

CCR1

TA1

6.11.18 TA3
TA3 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA3 can support multiple
capture/compares, PWM outputs, and interval timing (see 表 6-16). TA3 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of thecapture/compare registers.
表 6-16. TA3 Signal Connections
DEVICE INPUT SIGNAL

MODULE INPUT NAME

PM_TACLKTACLKMODULE BLOCKMODULE OUTPUT
SIGNAL

Timer

NA

DEVICE OUTPUT
SIGNALACLK (internal)

ACLK

SMCLK (internal)

SMCLK

PM_TACLKINCLK

PM_TA3.0

CCI0A

PM_TA3.0

DVSS

CCI0B

TA0

ADC10_A (internal)
ADC10SHSx = {2}

DVSS

GND

TA1

CCR0

DVCC

VCC

PM_TA3.1

CCI1A

PM_TA3.1

ACLK (internal)

CCI1B

SD24_B (internal)
SD24SCSx = {3}

DVSS

GND

DVCC

VCC

CCR1

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6.11.19 SD24_B Triggers
表 6-17 lists the input trigger connections to SD24_B converters from Timer_A modules and output trigger
pulse connection from SD24_B to ADC10_A.
表 6-17. SD24_B Input/Output Trigger Connections
DEVICE INPUT SIGNAL MODULE INPUT SIGNAL
TA0.1 (internal)

SD24_B
SD24SCSx = {1}TA2.1 (internal)

SD24_B
SD24SCSx = {2}TA3.1 (internal)

SD24_B
SD24SCSx = {3}MODULE BLOCKMODULE OUTPUT
SIGNALDEVICE OUTPUT
SIGNAL

Trigger Pulse

ADC10_A (internal)
ADC10SHSx = {3}SD24_B

6.11.20 ADC10_A Triggers
表 6-18 lists the input trigger connections to ADC10_A from Timer_A modules and SD24_B.
表 6-18. ADC10_A Input Trigger Connections
DEVICE INPUT SIGNAL

MODULE INPUT SIGNAL

TA0.1 (internal)

ADC10_A
ADC10SHSx = {1}TA3.0 (internal)

ADC10_A
ADC10SHSx = {2}SD24_B
trigger pulse (internal)

ADC10_A
ADC10SHSx = {3}MODULE BLOCK

ADC10_A

6.11.21 Real-Time Clock (RTC_C)
The RTC_C module can be configured for calendar mode providing seconds, hours, day of week, day ofmonth, month, and year. The RTC_C control and configuration registers are password protected to ensure
clock integrity against runaway code. Calendar mode integrates an internal calendar that compensates formonths with less than 31 days and includes leap year correction. The RTC_C also supports flexible alarmfunctions, offset calibration, and temperature compensation. The RTC_C on this device operates on
dedicated AUXVCC3 supply and supports operation in LPM3.5.

6.11.22 Reference (REF) Module Voltage Reference
The REF module generates all critical reference voltages that can be used by the various analog
peripherals in the device. These include the ADC10_A, LCD_C, and SD24_B modules.

6.11.23 LCD_C
The LCD_C driver generates the segment and common signals required to drive a liquid crystal display(LCD). The LCD_C controller has dedicated data memories to hold segment drive information. Commonand segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, 4-mux, up to 8-mux
LCDs are supported. The module can provide a LCD voltage independent of the supply voltage with its
integrated charge pump. It is possible to control the level of the LCD voltage, and thus contrast, bysoftware. The module also provides an automatic blinking capability for individual segments in static,
2‑mux, 3-mux, and 4-mux modes.

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6.11.24 Embedded Emulation Module (EEM) (S Version)
The EEM supports real-time in-system debugging. The S version of the EEM has the following features:• Three hardware triggers or breakpoints on memory access• One hardware trigger or breakpoint on CPU register write access• Up to four hardware triggers can be combined to form complex triggers or breakpoints• One cycle counter• Clock control on module level

Detailed Description
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6.11.25 Peripheral File Map
表 6-19 lists the base address for the registers of each supported peripheral.
表 6-19. Peripherals
BASE ADDRESSOFFSET ADDRESSRANGESpecial Functions (see 表 6-20)

0100h

000h to 01Fh

PMM (see 表 6-21)0120h000h to 01Fh

Flash Control (see 表 6-22)0140h000h to 00Fh

CRC16 (see 表 6-23)0150h000h to 007h

RAM Control (see 表 6-24)0158h000h to 001h

Watchdog (see 表 6-25)015Ch000h to 001h

UCS (see 表 6-26)0160h000h to 01Fh

SYS (see 表 6-27)0180h000h to 01Fh

Shared Reference (see 表 6-28)01B0h000h to 001h

Port Mapping Control (see 表 6-29)

01C0h

000h to 007h

Port Mapping Port P1 (see 表 6-30)

01C8h000h to 007h

Port Mapping Port P2 (see 表 6-31)

01D0h

000h to 007h

Port Mapping Port P3 (see 表 6-32)

01D8h000h to 007h

Port P1 and P2 (see 表 6-33)

0200h

000h to 01Fh

Port P3 and P4 (see 表 6-34)0220h000h to 00Bh

Port P5 and P6 (see 表 6-35)0240h000h to 00Bh

Port P7 and P8 (see 表 6-36)(Port P7 and P8 not available in MSP430F67xxIPN)

0260h000h to 00Bh

Port P9 (Port P9 not available in MSP430F67xxIPN)(see 表 6-37)0280h000h to 00Bh

Port PJ (refer to表 6-38)

0320h

000h to 01Fh

Timer TA0 (see 表 6-39)0340h000h to 03Fh

Timer TA1 (see 表 6-40)0380h000h to 03Fh

Timer TA2 (see 表 6-41)0400h

000h to 03Fh

Timer TA3 (see 表 6-42)0440h000h to 03Fh

Backup Memory (see 表 6-43)0480h000h to 00Fh

RTC_C (see 表 6-44)04A0h

000h to 01Fh

32-Bit Hardware Multiplier (see 表 6-45)

04C0h

000h to 02Fh

DMA General Control (see 表 6-46)0500h

000h to 00FhDMA Channel 0 (see 表 6-47)0500h

010h to 01FhDMA Channel 1 (see 表 6-48)0500h

020h to 02FhDMA Channel 2 (see 表 6-49)0500h

030h to 03Fh

eUSCI_A0 (see 表 6-50)

05C0h

000h to 01Fh

eUSCI_A1 (see 表 6-51)05E0h000h to 01Fh

eUSCI_A2 (see 表 6-52)0600h

000h to 01Fh

eUSCI_B0 (see 表 6-53)0640h

000h to 02Fh

ADC10_A (see 表 6-54)0740h

000h to 01Fh

SD24_B(see 表 6-55)

0800h

000h to 06Fh

Auxiliary Supply (see 表 6-49)

09E0h

000h to 01Fh

LCD_C (see 表 6-57)

0A00h

000h to 05Fh

MODULE NAME

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表 6-20. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTIONREGISTEROFFSETSFR interrupt enable

SFRIE100h

SFR interrupt flag

SFRIFG102h

SFR reset pin control

SFRRPCR04h

表 6-21. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTIONREGISTEROFFSET

PMM control 0

PMMCTL000h

PMM control 1

PMMCTL102h

SVS high-side control

SVSMHCTL

04h

SVS low-side control

SVSMLCTL

06h

PMM interrupt flags

PMMIFG0Ch

PMM interrupt enable

PMMIE

0Eh

PMM power mode 5 control 0

PM5CTL010h

表 6-22. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTIONREGISTEROFFSET

Flash control 1

FCTL1

00h

Flash control 3

FCTL3

04h

Flash control 4

FCTL4

06h

表 6-23. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTIONREGISTEROFFSET

CRC data input

CRC16DI00h

CRC data input reverse byte

CRC16DIRB

02h

CRC result

CRCINIRES

04h

CRC result reverse byte

CRCRESR06h

表 6-24. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM control 0

REGISTERRCCTL0OFFSET00h

表 6-25. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control

REGISTERWDTCTLOFFSET00h

表 6-26. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTIONREGISTEROFFSETUCS control 0

UCSCTL000h

UCS control 1

UCSCTL102h

UCS control 2

UCSCTL204h

UCS control 3

UCSCTL306h

UCS control 4

UCSCTL408h

UCS control 5

UCSCTL50Ah

UCS control 6

UCSCTL60Ch

UCS control 7

UCSCTL7

0Eh

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表 6-26. UCS Registers (Base Address: 0160h) (continued)
REGISTER DESCRIPTIONUCS control 8

REGISTERUCSCTL8OFFSET10h

表 6-27. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTIONREGISTEROFFSET

System control

SYSCTL00h

Bootloader configuration area

SYSBSLC

02h

JTAG mailbox control

SYSJMBC

06h

JTAG mailbox input 0

SYSJMBI008h

JTAG mailbox input 1

SYSJMBI1

0Ah

JTAG mailbox output 0

SYSJMBO00Ch

JTAG mailbox output 1

SYSJMBO1

0Eh

Bus error vector generator

SYSBERRIV

18h

User NMI vector generator

SYSUNIV

1Ah

System NMI vector generator

SYSSNIV

1Ch

Reset vector generator

SYSRSTIV1Eh

表 6-28. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control

REGISTERREFCTLOFFSET00h

表 6-29. Port Mapping Controller (Base Address: 01C0h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port mapping password

PMAPPWD

00h

Port mapping control

PMAPCTL02h

表 6-30. Port Mapping for Port P1 (Base Address: 01C8h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P1.0 mapping

P1MAP000h

Port P1.1 mapping

P1MAP101h

Port P1.2 mapping

P1MAP202h

Port P1.3 mapping

P1MAP303hPort P1.4 mapping

P1MAP404h

Port P1.5 mapping

P1MAP505h

Port P1.6 mapping

P1MAP606h

Port P1.7 mapping

P1MAP707h

表 6-31. Port Mapping for Port P2 (Base Address: 01D0h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P2.0 mapping

P2MAP000h

Port P2.1 mapping

P2MAP201h

Port P2.2 mapping

P2MAP202h

Port P2.3 mapping

P2MAP303hPort P2.4 mapping

P2MAP404h

Port P2.5 mapping

P2MAP505h

Port P2.6 mapping

P2MAP606h

Port P2.7 mapping

P2MAP707h84

Detailed Description

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表 6-32. Port Mapping for Port P3 (Base Address: 01D8h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P3.0 mapping

P3MAP000h

Port P3.1 mapping

P3MAP301h

Port P3.2 mapping

P3MAP202h

Port P3.3 mapping

P3MAP303hPort P3.4 mapping

P3MAP404h

Port P3.5 mapping

P3MAP505h

Port P3.6 mapping

P3MAP606h

Port P3.7 mapping

P3MAP707h

表 6-33. Port P1 and P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P1 input

P1IN

00h

Port P1 output

P1OUT

02h

Port P1 direction

P1DIR

04h

Port P1 resistor enable

P1REN

06h

Port P1 drive strength

P1DS

08h

Port P1 selection

P1SEL

0Ah

Port P1 interrupt vector word

P1IV

0Eh

Port P1 interrupt edge select

P1IES

18h

Port P1 interrupt enable

P1IE

1Ah

Port P1 interrupt flag

P1IFG

1Ch

Port P2 input

P2IN

01h

Port P2 output

P2OUT

03h

Port P2 direction

P2DIR

05h

Port P2 resistor enable

P2REN

07h

Port P2 drive strength

P2DS

09h

Port P2 selection

P2SEL

0Bh

Port P2 interrupt vector word

P2IV

1Eh

Port P2 interrupt edge select

P2IES

19h

Port P2 interrupt enable

P2IE

1Bh

Port P2 interrupt flag

P2IFG

1Dh

表 6-34. Port P3 and P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P3 input

P3IN

00h

Port P3 output

P3OUT

02h

Port P3 direction

P3DIR

04h

Port P3 resistor enable

P3REN

06h

Port P3 drive strength

P3DS

08h

Port P3 selection

P3SEL

0Ah

Port P4 input

P4IN

01h

Port P4 output

P4OUT

03h

Port P4 direction

P4DIR

05h

Port P4 resistor enable

P4REN

07h

Port P4 drive strength

P4DS

09h

Port P4 selection

P4SEL

0Bh

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表 6-35. Port P5 and P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P5 input

P5IN

00h

Port P5 output

P5OUT

02h

Port P5 direction

P5DIR

04h

Port P5 resistor enable

P5REN

06h

Port P5 drive strength

P5DS

08h

Port P5 selection

P5SEL

0Ah

Port P6 input

P6IN

01h

Port P6 output

P6OUT

03h

Port P6 direction

P6DIR

05h

Port P6 resistor enable

P6REN

07h

Port P6 drive strength

P6DS

09h

Port P6 selection

P6SEL

0Bh

表 6-36. Port P7 and P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P7 input

P7IN

00h

Port P7 output

P7OUT

02h

Port P7 direction

P7DIR

04h

Port P7 resistor enable

P7REN

06h

Port P7 drive strength

P7DS

08h

Port P7 selection

P7SEL

0Ah

Port P8 input

P8IN

01h

Port P8 output

P8OUT

03h

Port P8 direction

P8DIR

05h

Port P8 resistor enable

P8REN

07h

Port P8 drive strength

P8DS

09h

Port P8 selection

P8SEL

0Bh

表 6-37. Port P9 Registers (Base Address: 0280h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P9 input

P9IN

00h

Port P9 output

P9OUT

02h

Port P9 direction

P9DIR

04h

Port P9 resistor enable

P9REN

06h

Port P9 drive strength

P9DS

08h

Port P9 selection

P9SEL

0Ah

表 6-38. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port PJ input

PJIN

00h

Port PJ output

PJOUT

02h

Port PJ direction

PJDIR

04h

Port PJ resistor enable

PJREN

06h

Port PJ drive strength

PJDS

08h

Port PJ selection

PJSEL

0Ah

86

Detailed Description

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

表 6-39. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTIONREGISTEROFFSETTA0 control

TA0CTL00h

Capture/compare control 0

TA0CCTL002h

Capture/compare control 1

TA0CCTL1

04h

Capture/compare control 2

TA0CCTL2

06h

TA0 counter

TA0R

10h

Capture/compare 0

TA0CCR012h

Capture/compare 1

TA0CCR1

14h

Capture/compare 2

TA0CCR216h

TA0 expansion 0

TA0EX020h

TA0 interrupt vector

TA0IV

2Eh

表 6-40. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTIONREGISTEROFFSETTA1 control

TA1CTL00h

Capture/compare control 0

TA1CCTL002h

Capture/compare control 1

TA1CCTL1

04h

TA1 counter

TA1R

10h

Capture/compare 0

TA1CCR012h

Capture/compare 1

TA1CCR114h

TA1 expansion 0

TA1EX020h

TA1 interrupt vector

TA1IV

2Eh

表 6-41. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTIONREGISTEROFFSETTA2 control

TA2CTL00h

Capture/compare control 0

TA2CCTL002h

Capture/compare control 1

TA2CCTL104h

TA2 counter

TA2R

10h

Capture/compare 0

TA2CCR012h

Capture/compare 1

TA2CCR114h

TA2 expansion 0

TA2EX020h

TA2 interrupt vector

TA2IV

2Eh

表 6-42. TA3 Registers (Base Address: 0440h)
REGISTER DESCRIPTIONREGISTEROFFSETTA3 control

TA3CTL00h

Capture/compare control 0

TA3CCTL002h

Capture/compare control 1

TA3CCTL1

04h

TA3 counter

TA3R

10h

Capture/compare 0

TA3CCR012h

Capture/compare 1

TA3CCR114h

TA3 expansion 0

TA3EX020h

TA3 interrupt vector

TA3IV

2Eh

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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表 6-43. Backup Memory Registers (Base Address: 0480h)
REGISTER DESCRIPTIONREGISTEROFFSET

Backup memory 0

BAKMEM000h

Backup memory 1

BAKMEM1

02h

Backup memory 2

BAKMEM2

04h

Backup memory 3

BAKMEM306h

表 6-44. RTC_C Registers (Base Address: 04A0h)
REGISTER DESCRIPTIONREGISTEROFFSET

RTC control 0

RTCCTL000h

RTC password

RTCPWD01h

RTC control 1

RTCCTL102h

RTC control 3

RTCCTL303h

RTC offset calibration

RTCOCAL04h

RTC temperature compensation

RTCTCMP06h

RTC prescaler 0 control

RTCPS0CTL

08h

RTC prescaler 1 control

RTCPS1CTL

0Ah

RTC prescaler 0

RTCPS00Ch

RTC prescaler 1

RTCPS10Dh

RTC interrupt vector word

RTCIV

0Eh

RTC seconds

RTCSEC10h

RTC minutes

RTCMIN11h

RTC hours

RTCHOUR12h

RTC day of week

RTCDOW

13h

RTC days

RTCDAY

14h

RTC month

RTCMON15h

RTC year

RTCYEAR16h

RTC alarm minutes

RTCAMIN

18h

RTC alarm hours

RTCAHOUR

19h

RTC alarm day of week

RTCADOW

1Ah

RTC alarm days

RTCADAY

1Bh

Binary-to-BCD conversion

BIN2BCD

1Ch

BCD-to-binary conversion

BCD2BIN

1Eh

88

Detailed Description

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

表 6-45. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTIONREGISTEROFFSET

16-bit operand 1 – multiply

MPY

00h

16-bit operand 1 – signed multiply

MPYS

02h

16-bit operand 1 – multiply accumulate

MAC

04h

16-bit operand 1 – signed multiply accumulate

MACS

06h

16-bit operand 2

OP2

08h

16 × 16 result low word

RESLO

0Ah

16 × 16 result high word

RESHI

0Ch

16 × 16 sum extension

SUMEXT0Eh

32-bit operand 1 – multiply low word

MPY32L10h

32-bit operand 1 – multiply high word

MPY32H12h32-bit operand 1 – signed multiply low word

MPYS32L

14h

32-bit operand 1 – signed multiply high word

MPYS32H

16h32-bit operand 1 – multiply accumulate low word

MAC32L18h

32-bit operand 1 – multiply accumulate high word

MAC32H1Ah

32-bit operand 1 – signed multiply accumulate low word

MACS32L

1Ch

32-bit operand 1 – signed multiply accumulate high word

MACS32H

1Eh32-bit operand 2 – low word

OP2L

20h

32-bit operand 2 – high word

OP2H

22h

32 × 32 result 0 – least significant word

RES0

24h

32 × 32 result 1

RES1

26h

32 × 32 result 2

RES2

28h

32 × 32 result 3 – most significant word

RES3

2Ah

MPY32 control 0

MPY32CTL02Ch

表 6-46. DMA General Control Registers (Base Address: 0500h)
REGISTER DESCRIPTIONREGISTEROFFSET

DMA module control 0

DMACTL000h

DMA module control 1

DMACTL102h

DMA module control 2

DMACTL204h

DMA module control 3

DMACTL306h

DMA module control 4

DMACTL408h

DMA interrupt vector

DMAIV

0Eh

表 6-47. DMA Channel 0 Registers (Base Address: 0500h)
REGISTER DESCRIPTIONREGISTEROFFSET

DMA channel 0 control

DMA0CTL

10h

DMA channel 0 source address low

DMA0SAL

12h

DMA channel 0 source address high

DMA0SAH14h

DMA channel 0 destination address low

DMA0DAL

16h

DMA channel 0 destination address high

DMA0DAH18h

DMA channel 0 transfer size

DMA0SZ

1Ah

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

表 6-48. DMA Channel 1 Registers (Base Address: 0500h)
REGISTER DESCRIPTIONREGISTEROFFSET

DMA channel 1 control

DMA1CTL

20h

DMA channel 1 source address low

DMA1SAL

22h

DMA channel 1 source address high

DMA1SAH24h

DMA channel 1 destination address low

DMA1DAL

26h

DMA channel 1 destination address high

DMA1DAH28h

DMA channel 1 transfer size

DMA1SZ2Ah

表 6-49. DMA Channel 2 Registers (Base Address: 0500h)
REGISTER DESCRIPTIONREGISTEROFFSET

DMA channel 2 control

DMA2CTL

30h

DMA channel 2 source address low

DMA2SAL

32h

DMA channel 2 source address high

DMA2SAH34h

DMA channel 2 destination address low

DMA2DAL36h

DMA channel 2 destination address high

DMA2DAH38h

DMA channel 2 transfer size

DMA2SZ3Ah

表 6-50. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTIONREGISTEROFFSET

eUSCI_A control word 0

UCA0CTLW000h

eUSCI _A control word 1

UCA0CTLW1

02h

eUSCI_A baud rate 0

UCA0BR006h

eUSCI_A baud rate 1

UCA0BR1

07h

eUSCI_A modulation control

UCA0MCTLW

08h

eUSCI_A status

UCA0STAT

0Ah

eUSCI_A receive buffer

UCA0RXBUF

0Ch

eUSCI_A transmit buffer

UCA0TXBUF

0Eh

eUSCI_A LIN control

UCA0ABCTL

10h

eUSCI_A IrDA transmit control

UCA0IRTCTL

12h

eUSCI_A IrDA receive control

UCA0IRRCTL

13h

eUSCI_A interrupt enable

UCA0IE

1Ah

eUSCI_A interrupt flags

UCA0IFG

1Ch

eUSCI_A interrupt vector word

UCA0IV

1Eh

90

Detailed Description

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

表 6-51. eUSCI_A1 Registers (Base Address:05E0h)
REGISTER DESCRIPTIONREGISTEROFFSET

eUSCI_A control word 0

UCA1CTLW000h

eUSCI _A control word 1

UCA1CTLW1

02h

eUSCI_A baud rate 0

UCA1BR006h

eUSCI_A baud rate 1

UCA1BR1

07h

eUSCI_A modulation control

UCA1MCTLW

08h

eUSCI_A status

UCA1STAT

0Ah

eUSCI_A receive buffer

UCA1RXBUF

0Ch

eUSCI_A transmit buffer

UCA1TXBUF

0Eh

eUSCI_A LIN control

UCA1ABCTL

10h

eUSCI_A IrDA transmit control

UCA1IRTCTL

12h

eUSCI_A IrDA receive control

UCA1IRRCTL

13h

eUSCI_A interrupt enable

UCA1IE

1Ah

eUSCI_A interrupt flags

UCA1IFG

1Ch

eUSCI_A interrupt vector word

UCA1IV1Eh

表 6-52. eUSCI_A2 Registers (Base Address:0600h)
REGISTER DESCRIPTIONREGISTEROFFSET

eUSCI_A control word 0

UCA2CTLW000h

eUSCI _A control word 1

UCA2CTLW1

02h

eUSCI_A baud rate 0

UCA2BR006h

eUSCI_A baud rate 1UCA2BR1

07h

eUSCI_A modulation control

UCA2MCTLW

08h

eUSCI_A status

UCA2STAT

0Ah

eUSCI_A receive buffer

UCA2RXBUF

0Ch

eUSCI_A transmit buffer

UCA2TXBUF

0Eh

eUSCI_A LIN control

UCA2ABCTL

10h

eUSCI_A IrDA transmit control

UCA2IRTCTL

12h

eUSCI_A IrDA receive control

UCA2IRRCTL

13h

eUSCI_A interrupt enable

UCA2IE

1Ah

eUSCI_A interrupt flags

UCA2IFG

1Ch

eUSCI_A interrupt vector word

UCA2IV

1Eh

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

表 6-53. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTIONREGISTEROFFSET

eUSCI_B control word 0

UCB0CTLW000h

eUSCI_B control word 1

UCB0CTLW1

02h

eUSCI_B bit rate 0

UCB0BR006h

eUSCI_B bit rate 1

UCB0BR1

07h

eUSCI_B status word

UCB0STATW

08h

eUSCI_B byte counter threshold

UCB0TBCNT

0Ah

eUSCI_B receive buffer

UCB0RXBUF

0Ch

eUSCI_B transmit buffer

UCB0TXBUF

0Eh

eUSCI_B I2C own address 0

UCB0I2COA014h

eUSCI_B I2C own address 1

UCB0I2COA1

16h

eUSCI_B I2C own address 2

UCB0I2COA218h

eUSCI_B I2C own address 3

UCB0I2COA3

1Ah

eUSCI_B received address

UCB0ADDRX

1Ch

eUSCI_B address mask

UCB0ADDMASK

1Eh

eUSCI I2C slave address

UCB0I2CSA

20h

eUSCI interrupt enable

UCB0IE

2Ah

eUSCI interrupt flags

UCB0IFG

2Ch

eUSCI interrupt vector word

UCB0IV2Eh

表 6-54. ADC10_A Registers (Base Address: 0740h)
REGISTER DESCRIPTIONREGISTEROFFSET

ADC10_A control 0

ADC10CTL000h

ADC10_A control 1

ADC10CTL102h

ADC10_A control 2

ADC10CTL204h

ADC10_A window comparator low threshold

ADC10LO06h

ADC10_A window comparator high threshold

ADC10HI08h

ADC10_A memory control 0

ADC10MCTL00Ah

ADC10_A conversion memory

ADC10MCTL012h

ADC10_A interrupt enable

ADC10IE

1Ah

ADC10_A interrupt flags

ADC10IGH

1Ch

ADC10_A interrupt vector word

ADC10IV

1Eh

92

Detailed Description

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

表 6-55. SD24_B Registers (Base Address: 0800h)
REGISTER DESCRIPTIONREGISTEROFFSET

SD24_B control 0

SD24BCTL000h

SD24_B control 1

SD24BCTL102h

SD24_B interrupt flag

SD24BIFG

0Ah

SD24_B interrupt enable

SD24BIE

0Ch

SD24_B interrupt vector

SD24BIV

0Eh

SD24_B converter 0 control

SD24BCCTL010h

SD24_B converter 0 input control

SD24BINCTL0

12h

SD24_B converter 0 OSR control

SD24BOSR014h

SD24_B converter 0 preload

SD24BPRE016h

SD24_B converter 1 control

SD24BCCTL1

18h

SD24_B converter 1 input control

SD24BINCTL1

1Ah

SD24_B converter 1 OSR control

SD24BOSR1

1Ch

SD24_B converter 1 preload

SD24BPRE1

1Eh

SD24_B converter 2 control

SD24BCCTL2

20h

SD24_B converter 2 input control

SD24BINCTL2

22h

SD24_B converter 2 OSR control

SD24BOSR2

24h

SD24_B converter 2 preload

SD24BPRE226h

SD24_B converter 0 conversion memory low word

SD24BMEML050h

SD24_B converter 0 conversion memory high word

SD24BMEMH052hSD24_B converter 1 conversion memory low word

SD24BMEML1

54h

SD24_B converter 1 conversion memory high word

SD24BMEMH156h

SD24_B converter 2 conversion memory low word

SD24BMEML258h

SD24_B converter 2 conversion memory high word

SD24BMEMH25Ah

表 6-56. Auxiliary Supplies Registers (Base Address: 09E0h)
REGISTER DESCRIPTIONREGISTEROFFSET

Auxiliary supply control 0

AUXCTL000h

Auxiliary supply control 1

AUXCTL1

02h

Auxiliary supply control 2

AUXCTL2

04h

AUX2 charger control

AUX2CHCTL

12h

AUX3 charger control

AUX3CHCTL

14h

AUX ADC control

AUXADCCTL

16h

AUX interrupt flag

AUXIFG1Ah

AUX interrupt enable

AUXIE

1Ch

AUX interrupt vector word

AUXIV

1Eh

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

表 6-57. LCD_C Registers (Base Address: 0A00h)
REGISTER DESCRIPTIONREGISTEROFFSETLCD_C control 0

LCDCCTL0000h

LCD_C control 1

LCDCCTL1

002h

LCD_C blinking control

LCDCBLKCTL

004h

LCD_C memory control

LCDCMEMCTL

006h

LCD_C voltage control

LCDCVCTL

008h

LCD_C port control 0

LCDCPCTL0

00Ah

LCD_C port control 1

LCDCPCTL1

00Ch

LCD_C port control 2

LCDCPCTL2

00Eh

LCD_C charge pump control

LCDCCPCTL

012h

LCD_C interrupt vector

LCDCIV

01Eh

LCD_C memory 1

LCDM1

020h

LCD_C memory 2

LCDM2

021h

Static and 2- to 4-mux modes

⋮

⋮

⋮

LCD_C memory 20

LCDM20033h

LCD_C blinking memory 1

LCDBM1040h

LCD_C blinking memory 2

LCDBM2041h⋮⋮

LCD_C blinking memory 20⋮

LCDBM20053h

LCD_C memory 1

LCDM1

020h

LCD_C memory 2

LCDM2

021h

5- to 8-mux modes⋮⋮

LCD_C memory 40

94

Detailed Description⋮

LCDM40047h

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 20186.12 Input/Output Diagrams
6.12.1 Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger (MSP430F67xxIPZ and
MSP430F67xxIPN)
図 6-2 shows the port diagram. 表 6-58 summarizes the selection of the pin functions.
Pad Logic
To and from Reference

To ADC10_A
INCHx = y

P1REN.x
P1MAP.x = PMAP_ANALOG

P1DIR.x0

From Port Mapping

1

P1OUT.x0

From Port Mapping

1

DVSS

0

DVCC

1

1

Direction
0: Input
1: Output

P1DS.x0: Low drive
1: High drive

P1SEL.x

P1.0/PM_TA0.0/VeREF-/A2
P1.1/PM_TA0.1/VeREF+/A1

P1IN.xBus
KeeperEN
To Port Mapping

D

P1IE.xEN

P1IRQ.x

Q
P1IFG.x

Set

P1SEL.xInterrupt
Edge
SelectP1IES.x

図 6-2. Port P1 (P1.0 and P1.1) Diagram (MSP430F67xxIPZ and MSP430F67xxIPN)

Detailed Description
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Copyright © 2011–2018, Texas Instruments Incorporated

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

表 6-58. Port P1 (P1.0 and P1.1) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
PIN NAME (P1.x)

P1.0/PM_TA0.0/
VeREF-/A2

P1.1/PM_TA0.1/
VeREF+/A1

(1)
(2)

96

x

0

1

FUNCTIONCONTROL BITS OR SIGNALS (1)P1DIR.x

P1SEL.x

P1.0 (I/O)

I: 0; O: 10

P1MAPxX

TA0.CCI0A

01

default

TA0.TA01

1

default

VeREF-/A2 (2)

X

1

= 31

P1.1 (I/O)

I: 0; O: 10

X

TA0.CCI1A0

1

default

TA0.TA1

1

1

default

VeREF+/A1 (2)

X

1

= 31

X = Don't care
Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.

Detailed Description

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

6.12.2 Port P1 (P1.2) Input/Output With Schmitt Trigger (MSP430F67xxIPZ and
MSP430F67xxIPN)
図 6-3 shows the port diagram. 表 6-59 summarizes the selection of the pin functions.
Pad Logic
To ADC10_A
INCHx = y

P1REN.x
P1MAP.x = PMAP_ANALOG

P1DIR.x0

From Port Mapping

1

P1OUT.x0

From Port Mapping

1

DVSS

0

DVCC

1

1

Direction
0: Input
1: Output

P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0

P1DS.x0: Low drive
1: High drive

P1SEL.x
P1IN.xBus
KeeperEN
To Port Mapping

D

P1IE.xEN

P1IRQ.x

Q
P1IFG.x

Set

P1SEL.xInterrupt
Edge
SelectP1IES.x

図 6-3. Port P1 (P1.2) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
表 6-59. Port P1 (P1.2) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
PIN NAME (P1.x)

x

FUNCTION

P1DIR.x

P1SEL.x

P1MAPxI: 0; O: 10

X

UCA0RXD/UCA0SOMI

X

1default

A0 (2)X1= 31

P1.2 (I/O)
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
(1)
(2)

2

CONTROL BITS OR SIGNALS (1)X = Don't care
Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

6.12.3 Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger (MSP430F67xxIPZ and
MSP430F67xxIPN)
図 6-4 shows the port diagram. 表 6-60 summarizes the selection of the pin functions.
To LCD_C

Pad Logic
P1REN.x
P1MAP.x = PMAP_ANALOG

P1DIR.x0

From Port Mapping

1

P1OUT.x0

From Port Mapping

1

DVSS

0

DVCC

1

1

Direction
0: Input
1: Output

P1DS.x0: Low drive
1: High drive

P1SEL.x

P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13
P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23

P1IN.xBus
KeeperEN
To Port Mapping

D
P1IE.xEN

P1IRQ.x

Q
P1IFG.x

Set

P1SEL.xInterrupt
Edge
SelectP1IES.x

図 6-4. Port P1 (P1.3 to P1.5) Diagram (MSP430F67xxIPZ and MSP430F67xxIPN)
表 6-60. Port P1 (P1.3 to P1.5) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
PIN NAME (P1.x)

x

P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03

3

FUNCTION
P1.3 (I/O)

P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13

(1)
(2)

98

P1MAPx

0XX

1

default

R03 (2)

X

1

= 31

I: 0; O: 1

0

X

X

1

default

UCA1RXD/UCA1SOMILCDREF/R13 (2)5P1SEL.x

I: 0; O: 1

X

1

= 31

I: 0; O: 10

X

UCA1TXD/UCA1SIMO

X

1default

R23 (2)

X

1

= 31

P1.5 (I/O)
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23

P1DIR.x

UCA0TXD/UCA0SIMO
P1.4 (I/O)

4

CONTROL BITS OR SIGNALS (1)X = Don't care
Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.

Detailed Description

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

6.12.4 Port P1 (P1.6 and P1.7) (MSP430F67xxIPZ and MSP430F67xxIPN),Port P2 (P2.0 and P2.1) (MSP430F67xxIPZ Only) Input/Output With Schmitt Trigger
図 6-5 shows the port diagram. 表 6-61 and 表 6-62 summarize the selection of the pin functions.

COM4 to COM7
From LCD_C
Pad Logic
PyREN.x
PyMAP.x = PMAP_ANALOG

PyDIR.x0

From Port Mapping

1

PyOUT.x0

From Port Mapping

1

DVSS

0

DVCC

1

Direction
0: Input
1: Output

PyDS.x0: Low drive
1: High drive

PySEL.x
PyIN.xP1.6/PM_UCA0CLK/COM4
P1.7/PM_UCB0CLK/COM5
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7

Bus
KeeperEN
To Port Mapping

1

D
PyIE.xEN

PyIRQ.x

Q
PyIFG.x

Set

PySEL.xInterrupt
Edge
SelectPyIES.x

図 6-5. Port P1 (P1.6 and P1.7) (MSP430F67xxIPZ and MSP430F67xxIPN), Port P2 (P2.0 and P2.1)(MSP430F67xxIPZ Only) Diagram

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

表 6-61. Port P1 (P1.6 and P1.7) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
CONTROL BITS OR SIGNALS (1)PIN NAME (P1.x)

P1.6/PM_UCA0CLK/COM4x

6

FUNCTION

P1DIR.x

P1SEL.x

P1MAPxCOM4, COM5
Enable Signal

P1.6 (I/O)

I: 0; O: 1

0

X

0

UCA0CLKX

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

COM4

P1.7/PM_UCB0CLK/COM5

(1)

7

X

X

X

1

P1.7 (I/O)

I: 0; O: 1

0

X

0

UCB0CLKX

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

COM5

X

X

X

1

X = Don't care

表 6-62. Port P2 (P2.0 and P2.1) Pin Functions (MSP430F67xxIPZ Only)
CONTROL BITS OR SIGNALS (1)PIN NAME (P2.x)x

FUNCTIONP2DIR.x

P2SEL.x

P2MAPxCOM6, COM7
Enable Signal

I: 0; O: 1

0

X

0

UCB0SOMI/UCB0SCL

X

1default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

P2.0 (I/O)
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6

0

COM6

X

X

X

1

I: 0; O: 1

0

X

0

UCB0SIMO/UCB0SDA

X

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

COM7

X

X

X

1

P2.1 (I/O)
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7

(1)

100

1

X = Don't care

Detailed Description

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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

6.12.5 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
図 6-6 shows the port diagram. 表 6-63 summarizes the selection of the pin functions.
Pad Logic
P2REN.x
P2MAP.x = PMAP_ANALOG

P2DIR.x0

From Port Mapping

1

P2OUT.x0

From Port Mapping

1

DVSS

0

DVCC

1

Direction
0: Input
1: Output

P2DS.x0: Low drive
1: High drive

P2SEL.x
P2IN.xBus
KeeperEN
To Port Mapping1

P2.2/PM_UCA2RXD/PM_UCA2SOMI
P2.3/PM_UCA2TXD/PM_UCA2SIMO
P2.4/PM_UCA1CLK
P2.5/PM_UCA2CLK
P2.6/PM_TA1.0
P2.7/PM_TA1.1

D
P2IE.xEN

P2IRQ.x

Q
P2IFG.x

Set

P2SEL.xInterrupt
Edge
SelectP2IES.x

図 6-6. Port P2 (P2.2 to P2.7) Diagram (MSP430F67xxIPZ Only)

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

表 6-63. Port P2 (P2.2 to P2.7) Pin Functions (MSP430F67xxIPZ Only)PIN NAME (P2.x)x

FUNCTION
P2.2 (I/O)

P2.2/PM_UCA2RXD/
PM_UCA2SOMI

2

UCA2RXD/UCA2SOMI
Output driver and input Schmitt trigger disabledP2.3 (I/O)

P2.3/PM_UCA2TXD/
PM_UCA2SIMO

3

UCA2TXD/UCA2SIMO
Output driver and input Schmitt trigger disabled

P2.4/PM_UCA1CLK

4

P2.6/PM_TA1.0

5

6

(1)

102

7

P2SEL.x
0

P2MAPxX

X

1default= 31

X

1

I: 0; O: 1

0

X

X

1

default= 31

X

1

I: 0; O: 10

X

UCA1CLKX

1

default= 31

X

1

P2.5 (I/O)

I: 0; O: 10

X

UCA2CLKX

1

default

Output driver and input Schmitt trigger disabled

X

1

= 31

P2.6 (I/O)

I: 0; O: 10

X

TA1.CC10A

0

1

default

TA1.TA01

1

default= 31

Output driver and input Schmitt trigger disabled

P2.7/PM_TA1.1

P2DIR.x
I: 0; O: 1

P2.4 (I/O)
Output driver and input Schmitt trigger disabled
P2.5/PM_UCA2CLKCONTROL BITS OR SIGNALS (1)X

1

P2.7 (I/O)

I: 0; O: 10

X

TA1.CCI1A0

1

default

TA1.TA1

1

1

default

Output driver and input Schmitt trigger disabled

X

1

= 31

X = Don't care

Detailed Description

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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

6.12.6 Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
図 6-7 shows the port diagram. 表 6-64 summarizes the selection of the pin functions.
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG

P3DIR.x0

From Port Mapping

1

P3OUT.x0

From Port Mapping

1

DVSS

0

DVCC

1

1

Direction
0: Input
1: Output

P3.0/PM_TA2.0
P3.1/PM_TA2.1
P3.2/PM_TACLK/PM_RTCCLK
P3.3/PM_TA0.2

P3DS.x0: Low drive
1: High drive

P3SEL.x
P3IN.xBus
KeeperEN
To Port MappingD

図 6-7. Port P3 (P3.0 to P3.3) Diagram (MSP430F67xxIPZ Only)
表 6-64. Port P3 (P3.0 to P3.3) Pin Functions (MSP430F67xxIPZ Only)PIN NAME (P3.x)

P3.0/PM_TA2.0

x0

FUNCTION

P3DIR.x

P3SEL.x

P3.0 (I/O)

I: 0; O: 10

X

TA2.CC10A

0

1

default

TA2.TA01

1

default= 31

Output driver and input Schmitt trigger disabled

P3.1/PM_TA2.1

P3.2/PM_TACLK/
PM_RTCCLK

P3.3/PM_TA0.2

(1)

1

2

3

CONTROL BITS OR SIGNALS (1)P3MAPxX

1

P3.1 (I/O)

I: 0; O: 10

X

TA2.CCI1A0

1

default

TA2.TA1

1

1

default

Output driver and input Schmitt trigger disabled

X

1

= 31

P3.2 (I/O)

I: 0; O: 1

0

X

TACLK

0

1

default

RTCCLK1

1

default

Output driver and input Schmitt trigger disabled

X

1

= 31

P3.3 (I/O)

I: 0; O: 10

X

TA0.CCI2A

0

1

default

TA0.TA2

1

1

default

Output driver and input Schmitt trigger disabled

X

1

= 31

X = Don't care

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

6.12.7 Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
図 6-8 shows the port diagram. 表 6-65 summarizes the selection of the pin functions.

S39 to S37
LCDS39 to LCDS37
Pad Logic

P3REN.x
P3MAP.x = PMAP_ANALOG

P3DIR.x0

From Port Mapping

1

P3OUT.x0

From Port Mapping

1

DVSS

0

DVCC

1

1

Direction
0: Input
1: Output

P3DS.x0: Low drive
1: High drive

P3SEL.x

P3.4/PM_SDCLK/S39
P3.5/PM_SD0DIO/S38
P3.6/PM_SD1DIO/S37
P3.7/PM_SD2DIO/S36

P3IN.xEN
To Port MappingBus
KeeperD

図 6-8. Port P3 (P3.4 to P3.7) Diagram (MSP430F67xxIPZ Only)

104

Detailed Description

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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

表 6-65. Port P3 (P3.4 to P3.7) Pin Functions (MSP430F67xxIPZ Only)
CONTROL BITS OR SIGNALS (1)PIN NAME (P3.x)

P3.4/PM_SDCLK/S39

x

4

FUNCTION

P3DIR.x

P3SEL.x

P3MAPxLCDS39...
LCDS36

P3.4 (I/O)

I: 0; O: 1

0

X

0

SDCLK

X

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

S39

P3.5/PM_SD0DIO/S38

5

X

X

X

1

P3.5 (I/O)

I: 0; O: 1

0

X

0

SD0DIOX

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

S38

P3.6/PM_SD1DIO/S37

P3.7/PM_SD2DIO/S36

(1)

6

7

X

X

X

1

P3.6 (I/O)

I: 0; O: 1

0

X

0

SD1DIOX

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

S37

X

X

X

1

P3.7 (I/O)

I: 0; O: 1

0

X

0

SD2DIOX

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

S36

X

X

X

1

X = Don't care

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

6.12.8 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 toP7.7), Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
図 6-9 shows the port diagram. 表 6-66 through 表 6-70 summarize the selection of the pin functions.

Sz
LCDSz
Pad Logic

PyREN.x

PyDIR.x

0

0

DVSS

1

0

DVCC

1

1

Direction
0: Input
1: Output

1

PyOUT.x

DVSS

PyDS.x0: Low drive
1: High drive

PySEL.x

Py.x/Sz

PyIN.xEN
Not UsedBus
KeeperD

図 6-9. Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to P7.7), Port P8(P8.0 to P8.3) Diagram (MSP430F67xxIPZ Only)

106

Detailed Description

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

表 6-66. Port P4 (P4.0 to P4.7) Pin Functions (MSP430F67xxIPZ Only)
CONTROL BITS OR SIGNALS (1)PIN NAME (P4.x)

x

FUNCTION

P4DIR.x

P4SEL.x

LCDS35...
LCDS28

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S35

X

X

1

P4.0 (I/O)
P4.0/S35

0

P4.1 (I/O)
P4.1/S34

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S34

X

X

1

P4.2 (I/O)
P4.2/S33

2

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S33
P4.3 (I/O)
P4.3/S32

3

N/A

4

5

6

(1)

7

1

0

1

1

0

X

1

I: 0; O: 1

0

0

0

1

0

N/A
DVSS

1

1

0

S31

X

X

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S30

X

X

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S29

X

X

1

P4.7 (I/O)
P4.7/S28

00X

P4.6 (I/O)
P4.6/S29

1

0

S32

P4.5 (I/O)
P4.5/S30

X

DVSS
P4.4 (I/O)

P4.4/S31

X
I: 0; O: 1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S28

X

X

1

X = Don't care

Detailed Description
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

表 6-67. Port P5 (P5.0 to P5.7) Pin Functions (MSP430F67xxIPZ Only)
CONTROL BITS OR SIGNALS (1)PIN NAME (P5.x)x

FUNCTION

P5DIR.x

P5SEL.x

LCDS27...
LCDS20

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S27

X

X

1

P5.0 (I/O)
P5.0/S27

0

P5.1 (I/O)
P5.1/S26

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S26

X

X

1

P5.2 (I/O)
P5.2/S25

2

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S25
P5.3 (I/O)
P5.3/S24

3

N/A

4

5

6

(1)

108

7

1

0

1

1

0

X

1

I: 0; O: 1

0

0

0

1

0

N/A
DVSS

1

1

0

S23

X

X

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S22

X

X

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S21

X

X

1

P5.7 (I/O)
P5.7/S20

00X

P5.6 (I/O)
P5.6/S21

1

0

S24

P5.5 (I/O)
P5.5/S22

X

DVSS
P5.4 (I/O)

P5.4/S23

X
I: 0; O: 1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S20

X

X

1

X = Don't care

Detailed Description

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
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JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

表 6-68. Port P6 (P6.0 to P6.7) Pin Functions (MSP430F67xxIPZ Only)
CONTROL BITS OR SIGNALS (1)PIN NAME (P6.x)x

FUNCTION

P6DIR.x

P6SEL.x

LCDS19...
LCDS12

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S19

X

X

1

P6.0 (I/O)
P6.0/S19

0

P6.1 (I/O)
P6.1/S18

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S18

X

X

1

P6.2 (I/O)
P6.2/S172

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S17
P6.3 (I/O)
P6.3/S16

3

N/A

4

5

6

(1)

7

1

0

1

1

0

X

1

I: 0; O: 1

0

0

0

1

0

N/A
DVSS

1

1

0

S15

X

X

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S14

X

X

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S13

X

X

1

P6.7 (I/O)
P6.7/S12

00X

P6.6 (I/O)
P6.6/S13

1

0

S16

P6.5 (I/O)
P6.5/S14X

DVSS
P6.4 (I/O)

P6.4/S15

X
I: 0; O: 1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S12

X

X

1

X = Don't care

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

表 6-69. Port P7 (P7.0 to P7.7) Pin Functions (MSP430F67xxIPZ Only)
CONTROL BITS OR SIGNALS (1)PIN NAME (P7.x)

x

FUNCTION

P7DIR.x

P7SEL.x

LCDS11...
LCDS4

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S11

X

X

1

P7.0 (I/O)
P7.0/S11

0

P7.1 (I/O)
P7.1/S101

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S10

X

X

1

P7.2 (I/O)
P7.2/S92

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S9
P7.3 (I/O)
P7.3/S8

3

N/A

4

5

6

(1)

110

7

1

0

1

1

0

X

1

I: 0; O: 1

0

0

0

1

0

N/A
DVSS

1

1

0

S7

X

X

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S6

X

X

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S5

X

X

1

P7.7 (I/O)
P7.7/S4

00
X

P7.6 (I/O)
P7.6/S5

1

0

S8

P7.5 (I/O)
P7.5/S6X

DVSS
P7.4 (I/O)

P7.4/S7

X
I: 0; O: 1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S4

X

X

1

X = Don't care

Detailed Description

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

表 6-70. Port P8 (P8.0 to P8.3) Pin Functions (MSP430F67xxIPZ Only)
CONTROL BITS OR SIGNALS (1)PIN NAME (P8.x)x

FUNCTION

P8DIR.x

P8SEL.x

LCDS3...
LCDS0

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S3

X

X

1

P8.0 (I/O)
P8.0/S3

0

P8.1 (I/O)
P8.1/S2

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S2

X

X

1

P8.2 (I/O)
P8.2/S1

2

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S1
P8.3 (I/O)
P8.3/S0

(1)

3

N/A

X

X

1

I: 0; O: 1

0

0

0

1

0

DVSS

1

1

0

S0

X

X

1

X = Don't care

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

6.12.9 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
図 6-10 shows the port diagram. 表 6-71 summarizes the selection of the pin functions.
Pad Logic

P8REN.x

P8DIR.x00Module X OUT

1

0

DVCC

1

1

Direction
0: Input
1: Output

1

P8OUT.x

DVSS

P8.4/TA1.0
P8.5/TA1.1
P8.6/TA2.0
P8.7/TA2.1

P8DS.x0: Low drive
1: High drive

P8SEL.x
P8IN.xEN
Module X IND

図 6-10. Port P8 (P8.4 to P8.7) Diagram (MSP430F67xxIPZ Only)
表 6-71. Port P8 (P8.4 to P8.7) Pin Functions (MSP430F67xxIPZ Only)PIN NAME (P8.x)

P8.4/TA1.0

P8.5/TA1.1

P8.6/TA2.0

P8.7/TA2.1

112

Detailed Description

x

4

5

6

7

FUNCTIONCONTROL BITS OR SIGNALSP8DIR.x

P8SEL.xP8.4 (I/O)

I: 0; O: 10

TA1.CCI0A

01

TA1.TA0

1

1

P8.5 (I/O)

I: 0; O: 10

TA1.CCI1A

0

1

TA1.TA1

1

1

P8.6 (I/O)

I: 0; O: 10

TA2.CCI0A

0

1

TA2.TA0

1

1

P8.7 (I/O)

I: 0; O: 10

TA2.CCI1A

0

1

TA2.TA1

1

1

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

6.12.10 Port P9 (P9.0) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
図 6-11 shows the port diagram. 表 6-72 summarizes the selection of the pin functions.
Pad Logic

P9REN.x

P9DIR.x00Module X OUT

1

0

DVCC

1

1

Direction
0: Input
1: Output

1

P9OUT.x

DVSS

P9.0/TACLK/RTCCLK

P9DS.x0: Low drive
1: High drive

P9SEL.x
P9IN.xEN

Module X IND

図 6-11. Port P9 (P9.0) Diagram (MSP430F67xxIPZ Only)
表 6-72. Port P9 (P9.0) Pin Functions (MSP430F67xxIPZ Only)PIN NAME (P9.x)x

P9.0/TACLK/RTCCLK0

FUNCTIONCONTROL BITS OR SIGNALSP9DIR.x

P9SEL.xP9.0 (I/O)

I: 0; O: 1

0

TACLK

0

1

RTCCLK

1

1

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

6.12.11 Port P9 (P9.1 to P9.3) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
図 6-12 shows the port diagram. 表 6-73 summarizes the selection of the pin functions.
Pad Logic
To ADC10
INCHx = y

P9REN.x

DVSS

0

DVCC

1

1

P9DIR.x

P9OUT.xP9.1/A5
P9.2/A4
P9.3/A3

P9DS.x0: Low drive
1: High drive

P9SEL.x
P9IN.xBus
Keeper

図 6-12. Port P9 (P9.1 to P9.3) Diagram (MSP430F67xxIPZ Only)
表 6-73. Port P9 (P9.1 to P9.3) Pin Functions (MSP430F67xxIPZ Only)PIN NAME (P9.x)
P9.1/A5

x1

P9.2/A4

2

P9.3/A3

3

(1)
(2)

114

FUNCTION
P9.1 (I/O)
A5 (2)
P9.2 (I/O)
A4 (2)
P9.3 (I/O)
A3 (2)

CONTROL BITS OR SIGNALS (1)P9DIR.x

P9SEL.x

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

X = Don't care
Setting P9SEL.x bit disables the output driver and the input Schmitt trigger.

Detailed Description

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

6.12.12 Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
図 6-13 shows the port diagram. 表 6-74 summarizes the selection of the pin functions.

S39, S38
LCDS39, LCDS38

COM6, COM7
From LCD_C
Pad Logic
P2REN.x
P2MAP.x = PMAP_ANALOG

P2DIR.x0

From Port Mapping

1

P2OUT.x0

From Port Mapping

1

DVSS

0

DVCC

1

1

Direction
0: Input
1: Output

P2DS.x0: Low drive
1: High drive

P2SEL.x

P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38

P2IN.xBus
KeeperEN
To Port Mapping

D
P2IE.xEN

P2IRQ.x

Q
P2IFG.x

Set

P2SEL.xInterrupt
Edge
SelectP2IES.x

図 6-13. Port P2 (P2.0 and P2.1) Diagram (MSP430F67xxIPN Only)

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

表 6-74. Port P2 (P2.0 and P2.1) Pin Functions (MSP430F67xxIPN Only)
CONTROL BITS OR SIGNALS (1)PIN NAME (P2.x)x

FUNCTION

P2.0 (I/O)
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6/
S39

0

(1)

116

1

P2SEL.x

P2MAPxLCDS39,LCDS38COM6,
COM7EnableSignal

I: 0; O: 1

0

X

0

0

UCB0SOMI/UCB0SCL

X

1default

00

Output driver and input
Schmitt trigger disabled

X

1

= 31

0

0

COM6

X

X

X

X

1

S39

X

X

X

1

0

P2.1 (I/O)
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7/
S38

P2DIR.x

I: 0; O: 1

0

X

0

0

UCB0SIMO/UCB0SDA

X

1

default

00

Output driver and input
Schmitt trigger disabled

X

1

= 31

0

0

COM7

X

X

X

X

1

S38

X

X

X

1

0

X = Don't care

Detailed Description

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

6.12.13 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
図 6-14 shows the port diagram. 表 6-75 summarizes the selection of the pin functions.

S37...S32
LCDS37...LCDS32
Pad Logic
P2REN.x
P2MAP.x = PMAP_ANALOG

P2DIR.x0

From Port Mapping

1

P2OUT.x0

From Port Mapping

1

DVSS

0

DVCC

1

Direction
0: Input
1: Output

P2DS.x0: Low drive
1: High drive

P2SEL.x
P2IN.xBus
KeeperEN
To Port Mapping1

P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37
P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36
P2.4/PM_UCA1CLK/S35
P2.5/PM_UCA2CLK/S34
P2.6/PM_TA1.0/S33
P2.7/PM_TA1.1/S32

D
P2IE.xEN

P2IRQ.x

Q
P2IFG.x

Set

P2SEL.xInterrupt
Edge
SelectP2IES.x

図 6-14. Port P2 (P2.2 to P2.7) Diagram (MSP430F67xxIPN Only)

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

表 6-75. Port P2 (P2.2 to P2.7) Pin Functions (MSP430F67xxIPN Only)
CONTROL BITS OR SIGNALS (1)PIN NAME (P2.x)x

FUNCTIONP2DIR.x

P2SEL.x

P2MAPxLCDS37...
LCDS32

I: 0; O: 1

0

X

0

UCA2RXD/UCA2SOMIX

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

P2.2 (I/O)
P2.2/PM_UCA2RXD/
PM_UCA2SOMI/S37

2

S37

X

X

X

1

I: 0; O: 1

0

X

0

UCA2TXD/UCA2SIMO

X

1default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

P2.3 (I/O)
P2.3/PM_UCA2TXD/
PM_UCA2SIMO/S36

3

S36

P2.4/PM_UCA1CLK/S35

P2.5/PM_UCA2CLK/S34

4

5

X

X

X

1

P2.4 (I/O)

I: 0; O: 1

0

X

0

UCA1CLKX

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

S35

X

X

X

1

P2.5 (I/O)

I: 0; O: 1

0

X

0

UCA2CLKX

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

S34

P2.6/PM_TA1.0/S33

6

X

X

X

1

P2.6 (I/O)

I: 0; O: 1

0

X

0

TA1.CCI0A

01

default

0

TA1.TA01

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

S33

P2.7/PM_TA1.1/S32

(1)

118

7

X

X

X

1

P2.7 (I/O)

I: 0; O: 1

0

X

0

TA1.CCI1A0

1

default

0

TA1.TA1

1

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

S32

X

X

X

1

X = Don't care

Detailed Description

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

6.12.14 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
図 6-15 shows the port diagram. 表 6-76 summarizes the selection of the pin functions.

S31 to S24
LCDS31 to LCDS24
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG

P3DIR.x0

From Port Mapping

1

P3OUT.x0

From Port Mapping

1

DVSS

0

DVCC

1

Direction
0: Input
1: Output

P3DS.x0: Low drive
1: High drive

P3SEL.x
P3IN.xEN
To Port Mapping

1

Bus
Keeper

P3.0/PM_TA2.0/S31
P3.1/PM_TA2.1/S30
P3.2/PM_TACLK/PM_RTCCLK/S29
P3.3/PM_TA0.2/S28
P3.4/PM_SDCLK/S27
P3.5/PM_SD0DIO/S26
P3.6/PM_SD1DIO/S25
P3.7/PM_SD2DIO/S24

D

図 6-15. Port P3 (P3.0 to P3.7) Diagram (MSP430F67xxIPN Only)

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

表 6-76. Port P3 (P3.0 to P3.7) Pin Functions (MSP430F67xxIPN Only)
CONTROL BITS OR SIGNALS (1)PIN NAME (P3.x)

P3.0/PM_TA2.0/S31

x

0

FUNCTION

P3DIR.x

P3SEL.x

P3MAPxLCDS31...
LCDS24P3.0 (I/O)

I: 0; O: 1

0

X

0

TA2.CCI0A

01

default

0

TA2.TA01

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

S31

P3.1/PM_TA2.1/S30

1

X

X

X

1

P3.1 (I/O)

I: 0; O: 1

0

X

0

TA2.CCI1A0

1

default

0

TA2.TA1

1

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

S30

P3.2/PM_TACLK/
PM_RTCCLK/S29

P3.3/PM_TA0.2/S28

2

3

X

X

X

1

P3.2 (I/O)

I: 0; O: 1

0

X

0

TACLK

0

1

default

0

RTCCLK1

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

S29

X

X

X

1

P3.3 (I/O)

I: 0; O: 1

0

X

0

TA0.CCI2A

0

1

default

0TA0.TA2

1

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

S28

P3.4/PM_SDCLK/S27

4

X

X

X

1

P3.4 (I/O)

I: 0; O: 1

0

X

0

SDCLK

X

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

S27

P3.5/PM_SD0DIO/S26

5

X

X

X

1

P3.5 (I/O)

I: 0; O: 1

0

X

0

SD0DIOX

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

S26

P3.6/PM_SD1DIO/S25

P3.7/PM_SD2DIO/S24

(1)

120

6

7

X

X

X

1

P3.6 (I/O)

I: 0; O: 1

0

X

0

SD1DIOX

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

S25

X

X

X

1

P3.7 (I/O)

I: 0; O: 1

0

X

0

SD2DIOX

1

default0

Output driver and input Schmitt
trigger disabled

X

1

= 31

0

S24

X

X

X

1

X = Don't care

Detailed Description

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

6.12.15 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Input/Output
With Schmitt Trigger (MSP430F67xxIPN Only)
図 6-16 shows the port diagram. 表 6-77 through 表 6-79 summarize the selection of the pin functions.

Sz
LCDSz
Pad Logic

PyREN.x

PyDIR.x

0

0

DVSS

1

0

DVCC

1

1

Direction
0: Input
1: Output

1

PyOUT.x

DVSS

PyDS.x0: Low drive
1: High drive

PySEL.x

Py.x/Sz

PyIN.xEN
Not UsedBus
KeeperD

図 6-16. Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Diagram (MSP430F67xxIPN
Only)

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

表 6-77. Port P4 (P4.0 to P4.7) Pin Functions (MSP430F67xxIPN Only)
CONTROL BITS OR SIGNALS (1)PIN NAME (P4.x)

x

FUNCTION

P4DIR.x

P4SEL.x

LCDS23...
LCDS16

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S23

X

X

1

P4.0 (I/O)
P4.0/S23

0

P4.1 (I/O)
P4.1/S22

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S22

X

X

1

P4.2 (I/O)
P4.2/S212

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S21
P4.3 (I/O)
P4.3/S20

3

N/A

4

5

6

(1)

122

7

1

0

1

1

0

X

1

I: 0; O: 1

0

0

0

1

0

N/A
DVSS

1

1

0

S19

X

X

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S18

X

X

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S17

X

X

1

P4.7 (I/O)
P4.7/S16

00
X

P4.6 (I/O)
P4.6/S17

1

0

S20

P4.5 (I/O)
P4.5/S18

X

DVSS
P4.4 (I/O)

P4.4/S19

X
I: 0; O: 1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S16

X

X

1

X = Don't care

Detailed Description

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

表 6-78. Port P5 (P5.0 to P5.7) Pin Functions (MSP430F67xxIPN Only)
CONTROL BITS OR SIGNALS (1)PIN NAME (P5.x)x

FUNCTION

P5DIR.x

P5SEL.x

LCDS15...
LCDS8

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S15

X

X

1

P5.0 (I/O)
P5.0/S15

0

P5.1 (I/O)
P5.1/S141

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S14

X

X

1

P5.2 (I/O)
P5.2/S132

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S13
P5.3 (I/O)
P5.3/S12

3

N/A

4

5

6

(1)

7

1

0

1

1

0

X

1

I: 0; O: 1

0

0

0

1

0

N/A
DVSS

1

1

0

S11

X

X

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S10

X

X

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S9

X

X

1

P5.7 (I/O)
P5.7/S8

00X

P5.6 (I/O)
P5.6/S91

0

S12

P5.5 (I/O)
P5.5/S10X

DVSS
P5.4 (I/O)

P5.4/S11

X
I: 0; O: 1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S8

X

X

1

X = Don't care

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

表 6-79. Port P6 (P6.0 to P6.7) Pin Functions (MSP430F67xxIPN Only)
CONTROL BITS OR SIGNALS (1)PIN NAME (P6.x)x

FUNCTION

P6DIR.x

P6SEL.x

LCDS7...
LCDS0

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S7

X

X

1

P6.0 (I/O)
P6.0/S7

0

P6.1 (I/O)
P6.1/S6

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S6

X

X

1

P6.2 (I/O)
P6.2/S5

2

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S5
P6.3 (I/O)
P6.3/S4

3

N/A

4

5

6

(1)

124

7

1

0

1

1

0

X

1

I: 0; O: 1

0

0

0

1

0

N/A
DVSS

1

1

0

S3

X

X

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S2

X

X

1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S1

X

X

1

P6.7 (I/O)
P6.7/S00

0X

P6.6 (I/O)
P6.6/S1

1

0

S4

P6.5 (I/O)
P6.5/S2X

DVSS
P6.4 (I/O)

P6.4/S3

X
I: 0; O: 1

I: 0; O: 1

0

0

N/A

0

1

0

DVSS

1

1

0

S0

X

X

1

X = Don't care

Detailed Description

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

6.12.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
図 6-17 shows the port diagram. 表 6-80 summarizes the selection of the pin functions.
Pad Logic
PJREN.x

PJDIR.x

0

DVCC

1

PJOUT.x

00

From JTAG

01

SMCLK

10

DVSS

0

DVCC

1

PJDS.0
0: Low drive
1: High drive

111

PJ.0/SMCLK/TDO

PJSEL.x
From JTAG
PJIN.xEN

Bus
HolderD

図 6-17. Port PJ (PJ.0) Diagram

Detailed Description
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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

6.12.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt
Trigger or Output
図 6-18 shows the port diagram. 表 6-80 summarizes the selection of the pin functions.
Pad Logic
PJREN.x

PJDIR.x

0

DVSS

1

PJOUT.x

00

From JTAG01

MCLK/ADC10CLK/ACLK

10

DVSS

0

DVCC

1

1

PJ.1/MCLK/TDI/TCLK
PJ.2/ADC10CLK/TMS
PJ.3/ACLK/TCK

PJDS.x0: Low drive
1: High drive

11
PJSEL.x
From JTAG
PJIN.xBus
HolderEN
D

To JTAG

図 6-18. Port PJ (PJ.1 to PJ.3) Diagram
表 6-80. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS OR SIGNALS (1)PIN NAME (PJ.x)x

FUNCTION
PJ.0 (I/O) (2)PJ.0/SMCLK/TDO

0

1

2

0

0

1

1

0

TDO (3)

X

X

1

(1)
(2)
(3)
(4)

126

3

(2)

I: 0; O: 1

0

0

MCLK

1

1

0

TDI/TCLK (3) (4)

X

X

1

(2)

I: 0; O: 10

0

ADC10CLK1

1

0

TMS (3) (4)

X

X

1

PJ.3 (I/O)
PJ.3/ACLK/TCK

JTAG
Mode
Signal

I: 0; O: 1

PJ.2 (I/O)
PJ.2/ADC10CLK/TMS

PJSEL.x

SMCLK
PJ.1 (I/O)

PJ.1/MCLK/TDI/TCLKPJDIR.x(2)

I: 0; O: 1

0

0

ACLK

1

1

0

TCK (3) (4)

X

X

1

X = Don't care
Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.

Detailed Description

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MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 20186.13 Device Descriptors (TLV)
表 6-81 and 表 6-82 list the contents of the device descriptor tag-length-value (TLV) structure for eachdevice type.
表 6-81. MSP430F673x Device Descriptors
DESCRIPTION

Info Block

Die Record

ADC10
Calibration

ADDRESS

SIZE(bytes)

VALUE
F6736PZ
F6736PN

F6735PZ
F6735PN

F6734PZ
F6734PN

F6733PZ
F6733PN

F6731PZ
F6731PN

F6730PZ
F6730PN
06h

Info length

01A00h

1

06h

06h

06h

06h

06h

CRC length

01A01h

1

06h

06h

06h

06h

06h

06h

CRC value

01A02h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Device ID

01A04h

1

6Ch

6Bh

6Ah

65h

63h

62h

Device ID

01A05h

1

81h

81h

81h

80h

80h

80h

Hardware revision

01A06h1

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Firmware revision

01A07h1

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Die record tag

01A08h

1

08h

08h

08h

08h

08h

08h

Die record length

01A09h

1

0Ah

0Ah

0Ah

0Ah

0Ah

0Ah

Lot/wafer ID

01A0Ah4

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Die X position

01A0Eh2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Die Y position

01A10h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Test results

01A12h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC10 calibration tag

01A14h

1

13h

13h

13h

13h

13h

13h

ADC10 calibration length

01A15h

1

10h

10h

10h

10h

10h

10h

ADC gain factor

01A16h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC offset

01A18h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 1.5-V reference
Temperature sensor 30°C

01A1Ah2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 1.5-V reference
Temperature sensor 85°C

01A1Ch2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 2.0-V reference
Temperature sensor 30°C

01A1Eh2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 2.0-V reference
Temperature sensor 85°C

01A20h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 2.5-V reference
Temperature sensor 30°C

01A22h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 2.5-V reference
Temperature sensor 85°C

01A24h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Detailed Description
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Copyright © 2011–2018, Texas Instruments Incorporated

127

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

表 6-82. MSP430F672x Device Descriptors
DESCRIPTION

Info Block

Die Record

ADC10
Calibration

128

ADDRESS

SIZE(bytes)

VALUE
F6726PZ
F6726PN

F6725PZ
F6725PN

F6724PZ
F6724PN

F6723PZ
F6723PN

F6721PZ
F6721PN

F6720PZ
F6720PN
06h

Info length

01A00h

1

06h

06h

06h

06h

06h

CRC length

01A01h

1

06h

06h

06h

06h

06h

06h

CRC value

01A02h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Device ID

01A04h

1

6Fh

6Eh

6Dh

61h

59h

58h

Device ID

01A05h

1

81h

81h

81h

80h

80h

80h

Hardware revision

01A06h1

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Firmware revision

01A07h1

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Die record tag

01A08h

1

08h

08h

08h

08h

08h

08h

Die record length

01A09h

1

0Ah

0Ah

0Ah

0Ah

0Ah

0Ah

Lot/wafer ID

01A0Ah4

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Die X position

01A0Eh2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Die Y position

01A10h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Test results

01A12h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC10 calibration tag

01A14h

1

13h

13h

13h

13h

13h

13h

ADC10 calibration length

01A15h

1

10h

10h

10h

10h

10h

10h

ADC gain factor

01A16h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC offset

01A18h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 1.5-V reference
Temperature sensor 30°C

01A1Ah2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 1.5-V reference
Temperature sensor 85°C

01A1Ch2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 2.0-V reference
Temperature sensor 30°C

01A1Eh2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 2.0-V reference
Temperature sensor 85°C

01A20h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 2.5-V reference
Temperature sensor 30°C

01A22h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

ADC 2.5-V reference
Temperature sensor 85°C

01A24h2

Per unit

Per unit

Per unit

Per unit

Per unit

Per unit

Detailed Description

Copyright © 2011–2018, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730
MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

7 デバイスおよびドキュメントのサポート
7.1

使い始めと次の手順
MSP430™ファミリのデバイス、および開発に役立つツールやライブラリの詳細については、「Getting Started」ページを参照してください。

7.2

Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS.
These prefixes represent evolutionary stages of product development from engineering prototypes (XMS)
through fully qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates thetemperature range, package type, and distribution format. 図 7-1 provides a legend for reading thecomplete device name.

デバイスおよびドキュメントのサポート
Submit Documentation Feedback
Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730
MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

Copyright © 2011–2018, Texas Instruments Incorporated

129

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

MSP 430 F 5 438 A I ZQW T -EP
Processor Family

Optional: Additional Features

MCU Platform

Optional: Tape and Reel

Device Type

Packaging

SeriesFeature Set
Processor Family

MCU Platform

Optional: Temperature Range
Optional: A = Revision

CC = Embedded RF RadioMSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 = MSP430 low-power microcontroller platform

Device Type

Memory TypeC = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory

Specialized Application
AFE = Analog Front End
BQ = Contactless PowerCG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter

Series

1 = Up to 8 MHz
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD

5 = Up to 25 MHz
6 = Up to 25 MHz with LCD
0 = Low-Voltage Series

Feature Set

Various levels of integration within a series

Optional: A = Revision

N/A

Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging

http://www.ti.com/packaging

Optional: Tape and Reel

T = Small reel
R = Large reel
No markings = Tube or tray

Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)-HT = Extreme Temperature Parts (–55°C to 150°C)-Q1 = Automotive Q100 Qualified

図 7-1. Device Nomenclature

130

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Submit Documentation Feedback
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MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

7.3

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

ツールとソフトウェア
すべてのMSPマイクロコントローラは、広範なソフトウェアおよびハードウェア開発ツールによりサポートされています。ツールは、TIおよびさまざまなサードパーティーから入手できます。詳細については、「MSP430超低消費電力
マイコン – ツールとソフトウェア」を参照してください。
MSP430F673xおよびMSP430F672x MCUのデバッグ機能の一覧を、表 7-1に示します。利用可能な機能の詳細については、『MSP430用Code Composer Studio ユーザー・ガイド』を参照してください。
表 7-1. ハードウェアのデバッグ機能

MSP430ののアーキテク4線
線式JTAGチャ
MSP430Xv2

2線
線式JTAG

ブレーク・ポ
イント
(N)

範囲ブレー
ク・ポイント

クロック制御状態シーケンサ

トレース・バッファ

LPMX.5デデバッ
グ・サポート

○

3

○

○

×

×

×

○

設計キットと評価モジュール
MSP-TS430PZ100B - MSP430F6x MCU用用の100ピピン・ターゲット開発ボード
MSP-TS430PZ100Bはスタンド
アロンの100ピンZIFソケット・ターゲット・ボードで、JTAGインターフェイスまたはSpy Bi-Wire（2線式のJTAG）プロトコルによる、MSP430 MCUのイン・システムでのプログラムとデバッグに使用できます。
MSP430F6x MCU用用の100ピピン・ターゲット開発ボードとMSP-FETプ
プログラマ・バンドル MSP-FETは強力なフラッシュ・エミュレーション・ツールで、MSP430 MCUによるアプリケーションの開発をすぐに開始できます。USBデバッグ・インターフェイスにより、JTAGインターフェイスまたは省ピンSpy Bi-Wire（2線式JTAG）プロトコルを使用してMSP430をインシステムでプログラミングおよびデバッグできます。
EVM430-F6736 - MSP430F6736 EVM、
、メーター用 EVM430-F6736 は、MSP430F6736 デバイスをベースにした単相電力量計の評価モジュールです。この電力量計は、主電力線に接続可能で、電圧と電流の入力端子と、さらに改ざん防止設定用の接続端子があります。
ソフトウェアMSP430Ware™ソ
ソフトウェア MSP430Wareソフトウェアは、すべてのMSP430デバイス向けのサンプル・コード、
データシート、その他の設計リソースを、1つの便利なパッケージとしてまとめたものです。既存のMSP430用設計リソースの完全なコレクションに加えて、MSP430WareソフトウェアにはMSPドライ
バ・ライブラリという高レベルのAPIも含まれています。このライブラリにより、MSP430ハードウェアを簡
単にプログラムできます。MSP430WareソフトウェアはCCSのコンポーネントとして、またはスタンドア
ロンのパッケージとして入手できます。
MSP430マ
マイコン向けエネルギー測定デザイン・センター
エネルギー測定デザイン・センターは、TI
MSP430i20xxおよびMSP430F67xxフラッシュ・ベース・マイクロコントローラ(MCU)を使用したエネ
ルギー測定システムを短期間で開発できるツールです。グラフィカル・ユーザー・インターフェイス(GUI)、ドキュメント、ソフトウェア・ライブラリ、およびサンプルが含まれているため、スマート・グリッドやビルディング・オートメーションなどを含む、広範な電力監視およびエネルギー測定アプリケーション
を簡単に開発でき、設計時間を短縮できます。デザイン・センターを利用すれば、コードを1行も書かずに構成や較正を行い、結果を確認できます。
MSPド
ドライバ・ライブラリ MSPドライバ・ライブラリの抽象化されたAPIには、使いやすい関数呼び出しが含まれているため、MSP430ハードウェアのビットやバイトを直接操作する煩雑さから解放されます。使いやすい
APIガイドにより包括的な技術資料が参照でき、それぞれの関数呼び出しと、認識されるパラメータの詳細が記載されています。開発者は、ドライバ・ライブラリの関数を使用して、最小限のオーバーヘッ
ドで完全なプロジェクトを作成できます。
IEC60730ソ
ソフトウェア・パッケージ IEC60730 MSP430ソフトウェア・パッケージは、クラスBまでの製品について、
お客様がIEC 60730-1:2010 (家庭および同様な用途に使用される自動電気制御 – 第1部: 一般的な要件)に準拠するため役立つよう開発されています。この分類には家電機器、アーク検出器、電力コンバータ、電動工具、電動アシスト自転車、その他多くの製品が含まれます。IEC60730 MSP430
ソフトウェア・パッケージは、MSP430で実行するお客様のアプリケーションに組み込むことができるため、消費者向けデバイスがIEC 60730-1:2010クラスBの機能安全性に準拠していることの認定作業を簡素化できます。
MSP430F673x、、MSP430F672xののコード・サンプル すべてのMSPデバイス用に、内蔵する各ペリフェラルをさま
ざまな用途のニーズに合わせて構成するためのCコード・サンプルが用意されています。

デバイスおよびドキュメントのサポート
Submit Documentation Feedback
Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730
MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

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131

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

静電容量式タッチ・ソフトウェア・ライブラリ MSP430 MCU で静電容量式タッチ機能を有効にするための、無償のCライブラリです。MSP430 MCU バージョンのライブラリには、ROおよびRC方式を含む、いくつかの
静電容量式タッチ機能の実装が含まれています。
MSP EnergyTrace™テ
テクノロジ MSP430マイクロコントローラ用のEnergyTraceテクノロジは、エネルギーを基準としたコード解析ツールで、アプリケーションのエネルギー・プロファイルを測定して表示し、消費電力が極めて低くなるよう最適化するため役立ちます。
ULP (超超低消費電力) Advisor ULP Advisor™ソフトウェアは、MSPおよびMSP432マイクロコントローラの超低消費電力機能を十分に活用できる、最も効率的なコードを開発者が作成できるよう手引きするツールです。ULP
Advisorはマイクロコントローラに熟練した開発者と、新しい開発者の両方を対象としており、包括的なULPチェックリストを使用してコードをチェックし、アプリケーションのエネルギー消費を最小化するため役立ちます。ビルド時に、消費電力低減のためさらに最適化が可能なコードの部分を明らかにするため通知と注釈を出力します。
MSP用用の固定小数点算術ライブラリ MSP IQmathおよびQmathライブラリは、Cプログラマ向けの高度に最適化された高精度の算術関数のコレクションで、浮動小数点アルゴリズムをMSP430およびMSP432デバイ
スの固定小数点コードへシームレスに移行できます。これらのルーチンは通常、最適な実行速度、高精度、超低消費電力が重視される、演算集中型のリアルタイム・アプリケーションで使用されます。
IQmathライブラリとQmathライブラリを使用すると、浮動小数点演算を使用して記述した同等のコードに比べて、実行速度を大幅に高速化するとともに、消費電力の大幅な削減が可能です。
MSP430用
用の浮動小数点算術ライブラリ 低消費電力で低コストのマイクロコントローラ分野にさらなる革新を引き起こすため、TIはMSPMATHLIBを提供します。この浮動小数点算術ライブラリは、弊社デバイスのイン
テリジェントなペリフェラルを活用し、標準のMSP430算術関数よりも最高で26倍も高速なスカラー関
数です。Mathlibは、設計へ簡単に組み入れることができます。このライブラリは無償で、CodeComposer Studio IDEとIAR Embedded Workbench IDEの両方に組み込まれています。
開発ツール
Code Composer Studio™: MSPマ
マイクロコントローラ用の統合開発環境 Code Composer Studio (CCS)は、
すべてのMSPマイクロコントローラ・デバイスをサポートする統合開発環境(IDE)です。CCSは、組み込みアプリケーションの開発とデバッグに使用される、組み込み用ソフトウェア・ユーティリティのス
イートです。最適化C/C++コンパイラ、ソース・コード・エディタ、プロジェクト・ビルド環境、デバッガ、
プロファイラなど、多数の機能が含まれています。
コマンドライン・プログラマ MSP Flasher は、FETプログラマまたは eZ430 を経由し、JTAG または Spy-Bi-Wire(SBW) 通信を使用して MSP マイクロコントローラをプログラムするための、オープン・ソースでシェ
ル・ベースのインターフェイスです。MSP Flasher は、IDE を使用せずにバイナリ・ファイル (.txt または .hex) を MSP マイクロコントローラへ直接ダウンロードできます。
MSP MCUプ
プログラマおよびデバッガ MSP-FETは強力なエミュレーション開発ツールで、多くの場合にデバッグ・プローブと呼ばれます。ユーザーはこのツールを使用して、MSP低消費電力MCUのアプリケーショ
ン開発をすぐに始めることができます。MCUのソフトウェアを作成する場合は通常、結果として得られたバイナリ・プログラムをMSPデバイスにダウンロードし、検証とデバッグを行う必要があります。
MSP-GANG量
量産プログラマ MSP Gang プログラマは MSP430 または MSP432 用のデバイス・プログラマで、8つまでの同一の MSP430 または MSP432 のフラッシュまたは FRAM デバイスを同時にプログラム
できます。MSP Gang プログラマは、標準の RS-232 または USB 接続を使用してホスト PC と接続
し、柔軟なプログラミング・オプションが用意されているため、ユーザーはプロセスを完全にカスタマイ
ズ可能です。

132

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Copyright © 2011–2018, Texas Instruments Incorporated

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Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730
MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

7.4

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

ドキュメントのサポート
以下のドキュメントには、MSP430F673xおよびMSP430F672x MCUについて記載されています。これらのドキュメ
ントのコピーは、www.ti.comで入手できます。
ドキュメントの更新通知を受け取る方法
ドキュメント更新の通知を、シリコンの正誤表も含めて受け取るには、ti.comでお使いの製品のフォルダへ移動します(プロダクト・フォルダへのリンクについては、 7.5を参照してください)。右上の隅にある「通知を受け取る」ボタンをクリックします。これによって登録が行われ、変更された製品情報の概要を毎週受け取ることができます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。
正誤表『MSP430F6736デ
デバイス正誤表』 には、機能仕様に対する既知の例外が記載されています。
『MSP430F6735デ
デバイス正誤表』 には、機能仕様に対する既知の例外が記載されています。
『MSP430F6734デ
デバイス正誤表』 には、機能仕様に対する既知の例外が記載されています。
『MSP430F6733デ
デバイス正誤表』 には、機能仕様に対する既知の例外が記載されています。
『MSP430F6731デ
デバイス正誤表』 には、機能仕様に対する既知の例外が記載されています。
『MSP430F6730デ
デバイス正誤表』 には、機能仕様に対する既知の例外が記載されています。
『MSP430F6726デ
デバイス正誤表』 には、機能仕様に対する既知の例外が記載されています。
『MSP430F6725デ
デバイス正誤表』 には、機能仕様に対する既知の例外が記載されています。
『MSP430F6724デ
デバイス正誤表』 には、機能仕様に対する既知の例外が記載されています。
『MSP430F6723デ
デバイス正誤表』 には、機能仕様に対する既知の例外が記載されています。
『MSP430F6721デ
デバイス正誤表』 には、機能仕様に対する既知の例外が記載されています。
『MSP430F6720デ
デバイス正誤表』 には、機能仕様に対する既知の例外が記載されています。
ユーザー・ガイド『MSP430x5xxおおよびMSP430x6xxフ
ファミリ・ユーザー・ガイド』
ペリフェラルについての詳細情報です。

このデバイス・ファミリで利用可能なモジュールと『MSP430 フラッシュ・デバイス・ブートローダ(BSL)ユ
ユーザー・ガイド』 MSP430ブートローダ(BSL) (旧ブートスト
ラップ・ローダ)を使用すると、プロトタイプ作成、最終的な量産、および使用時に、MSP430マイクロコ
ントローラの組み込みメモリと通信を行うことができます。必要に応じて、プログラム可能メモリ(フラッシュ・メモリ)とデータ・メモリ(RAM)の両方を変更できます。このブートローダは、一部のデジタル・シグ
ナル・プロセッサ(DSP)に見られる、外部メモリからDSPの内部メモリへプログラム・コード(およびデー
タ)を自動的にロードする、ブートストラップ・ローダ・プログラムとは異なることに注意してください。
『JTAGイインターフェイスによるMSP430ののプログラミング』
このドキュメントでは、JTAG通信ポートを使用してMSP430のフラッシュ・ベースおよびFRAMベースのマイクロコントローラ・ファミリのメモリ・モジュールを消去、プログラム、検証するために必要な機能について解説しています。さらに、すべてのMSP430デバイスで利用可能なJTAGアクセス・セキュリティ・ヒューズのプログラム方法についても解説しています。このドキュメントには、標準の4線式JTAGインターフェイスと2線式JTAGインターフェイスの両方を使用してデバイスにアクセスする方法が解説されています。2線式JTAGインターフェイス
はSpy-Bi-Wire (SBW)とも呼ばれます。
『MSP430ハ
ハードウェア・ツール ユーザー・ガイド』 このマニュアルには、TI MSP-FET430フラッシュ・エミュレー
ション・ツール(FET)のハードウェアについて解説されています。このFETは、MSP430 超低消費電力マイクロコントローラ用のプログラム開発ツールです。利用可能なインターフェイスとして、パラレル・
ポート・インターフェイスとUSBインターフェイスの両方について解説されています。
アプリケーション・レポート『MSP430 32kHz水水晶発振器』 適切な水晶振動子、正しい負荷回路、および適切な基板レイアウトの選択は、安定した水晶発振器に重要です。このアプリケーション・レポートでは、水晶発振器の機能について要約し、MSP430の超低消費電力動作用の適切な水晶を選択するためのパラメータについて説明しま
す。また、正しい基板レイアウトについてのヒントや例も紹介しています。このドキュメントには、量産時の安定した発振器の動作を保証するために行うことができる、発振器のテストについての詳細情報も記載されています。

デバイスおよびドキュメントのサポート
Submit Documentation Feedback
Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730
MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

Copyright © 2011–2018, Texas Instruments Incorporated

133

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp『MSP430 システム・レベルESDのの考慮事項』
シリコン・テクノロジがますます低電圧化し、コスト効率に優れ非常に消費電力の低いコンポーネントを設計する必要性が高まっていくにつれ、システム・レベルESDの要求はますます高くなりつつあります。このアプリケーション・レポートでは、基板設計者とOEMが堅牢なシステム・レベルのデザインを理解し設計できるよう、3種類の異なるESDトピックについて扱います。
『MSP430ととセグメントLCDをを使用する設計』 セグメント液晶ディスプレイ(LCD)は、スマート・メーターから電子棚札(ESL)、医療機器に至る広範なアプリケーションで、ユーザーに情報を提供するために必要です。
MSP430マイクロコントローラ・ファミリの中には、低電力のLCDドライバ回路を内蔵し、MSP430
MCUでセグメントLCDガラスを直接制御できるものもあります。このアプリケーション・ノートには、セグ
メントLCDの動作原理、MSP430 MCUファミリ全体にわたる各種LCDモジュールの各種機能、LCD
ハードウェアのレイアウト設計のヒント、効率的で使いやすいLCDドライバ・ソフトウェアを作成するための指針、およびデバイス選択に役立つ各種LCD機能を含むMSP430デバイス・ポートフォリオの概要が記載されています。

7.5

関連リンク
表 7-2 に、クイック・アクセス・リンクの一覧を示します。カテゴリには、技術資料、サポートおよびコミュニティ・リソー
ス、ツールとソフトウェア、およびサンプル注文またはご購入へのクイック・アクセスが含まれます。
表 7-2. 関連リンク

7.6

製品

プロダクト・フォルダ

ご注文はこちら

技術資料

ツールとソフトウェア

サポートとコミュニティ

MSP430F6736

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

MSP430F6735

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

MSP430F6734

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

MSP430F6733

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

MSP430F6731

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

MSP430F6730

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

MSP430F6726

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

MSP430F6725

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

MSP430F6724

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

MSP430F6723

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

MSP430F6721

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

MSP430F6720

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by therespective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.

7.7

商標
MSP430, MSP430Ware, EnergyTrace, ULP Advisor, Code Composer Studio, E2E are trademarks ofTexas Instruments.
All other trademarks are the property of their respective owners.

134

デバイスおよびドキュメントのサポート

Copyright © 2011–2018, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730
MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
www.tij.co.jp

7.8

JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018

静電気放電に関する注意事項
すべての集積回路は、適切なESD保護方法を用いて、取扱いと保存を行うようにして下さい。
静電気放電はわずかな性能の低下から完全なデバイスの故障に至るまで、様々な損傷を与えます。高精度の集積回路は、損傷に対して敏感であり、極めてわずかなパラメータの変化により、デバイスに規定された仕様に適合しなくなる場合があります。

7.9

Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to whichsuch export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining priorauthorization from U.S. Department of Commerce and other competent Government authorities to theextent required by those laws.

7.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

デバイスおよびドキュメントのサポート
Submit Documentation Feedback
Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730
MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

Copyright © 2011–2018, Texas Instruments Incorporated

135

MSP430F6736, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730
MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720
JAJSG92D – DECEMBER 2011 – REVISED SEPTEMBER 2018www.tij.co.jp

8 メカニカル、パッケージ、および注文情報
以降のページには、メカニカル、パッケージ、および注文に関する情報が記載されています。これらの情報は、指定のデバイスに対して提供されている最新のデータです。このデータは予告なく変更されることがあり、ドキュメントが改訂される場合もあります。本データシートのブラウザ版を使用されている場合は、画面左側の説明をご覧ください。

136

メカニカル、パッケージ、および注文情報

Copyright © 2011–2018, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730
MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720

PACKAGE OPTION ADDENDUM
www.ti.com

16-Aug-2023

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking(3)

Samples

(4/5)

(6)

MSP430F6720IPN

ACTIVE

LQFP

PN

80

119

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6720

Samples

MSP430F6720IPNR

ACTIVE

LQFP

PN

80

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6720

Samples

MSP430F6720IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6720

Samples

MSP430F6720IPZR

ACTIVE

LQFP

PZ

100

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6720

Samples

MSP430F6721IPN

ACTIVE

LQFP

PN

80

119

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6721

Samples

MSP430F6721IPNR

ACTIVE

LQFP

PN

80

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6721

Samples

MSP430F6721IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6721

Samples

MSP430F6721IPZR

ACTIVE

LQFP

PZ

100

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6721

Samples

MSP430F6723IPN

ACTIVE

LQFP

PN

80

119

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6723

Samples

MSP430F6723IPNR

ACTIVE

LQFP

PN

80

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6723

Samples

MSP430F6723IPNR-S

ACTIVE

LQFP

PN

80

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6723

Samples

MSP430F6723IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6723

Samples

MSP430F6723IPZR

ACTIVE

LQFP

PZ

100

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6723

Samples

MSP430F6724IPN

ACTIVE

LQFP

PN

80

119

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6724

Samples

MSP430F6724IPNR

ACTIVE

LQFP

PN

80

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6724

Samples

MSP430F6724IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6724

Samples

MSP430F6724IPZR

ACTIVE

LQFP

PZ

100

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6724

Samples

MSP430F6725IPN

ACTIVE

LQFP

PN

80

119

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6725

Samples

MSP430F6725IPNR

ACTIVE

LQFP

PN

80

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6725

Samples

MSP430F6725IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6725

Samples

Addendum-Page 1

PACKAGE OPTION ADDENDUM
www.ti.com

Orderable Device

16-Aug-2023

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking(3)

Samples

(4/5)

(6)

MSP430F6725IPZR

ACTIVE

LQFP

PZ

100

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6725

Samples

MSP430F6726IPN

ACTIVE

LQFP

PN

80

119

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6726

Samples

MSP430F6726IPNR

ACTIVE

LQFP

PN

80

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6726

Samples

MSP430F6726IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6726

Samples

MSP430F6726IPZRACTIVE

LQFP

PZ

100

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6726

Samples

MSP430F6730IPN

ACTIVE

LQFP

PN

80

119

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6730

Samples

MSP430F6730IPNR

ACTIVE

LQFP

PN

80

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6730

Samples

MSP430F6730IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6730

Samples

MSP430F6731IPN

ACTIVE

LQFP

PN

80

119

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6731

Samples

MSP430F6731IPNR

ACTIVE

LQFP

PN

80

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6731

Samples

MSP430F6731IPZOBSOLETE

LQFP

PZ

100

TBD

Call TI

Call TI

F6731

MSP430F6731IPZROBSOLETE

LQFP

PZ

100

TBD

Call TI

Call TI

F6731

MSP430F6733IPN

ACTIVE

LQFP

PN

80

119

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6733

Samples

MSP430F6733IPNR

ACTIVE

LQFP

PN

80

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6733

Samples

MSP430F6733IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR

F6733

Samples

MSP430F6733IPZR

ACTIVE

LQFP

PZ

100

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR

F6733

Samples

MSP430F6734IPN

ACTIVE

LQFP

PN

80

119

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6734

Samples

MSP430F6734IPNR

ACTIVE

LQFP

PN

80

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6734

Samples

MSP430F6734IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6734

Samples

MSP430F6734IPZR

ACTIVE

LQFP

PZ

100

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6734

Samples

MSP430F6735IPN

ACTIVE

LQFP

PN

80

119

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6735

Samples

MSP430F6735IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6735

Samples

Addendum-Page 2

PACKAGE OPTION ADDENDUM
www.ti.com

Orderable Device

16-Aug-2023

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking(3)

Samples

(4/5)

(6)

MSP430F6736IPN

ACTIVE

LQFP

PN

80

119

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6736

Samples

MSP430F6736IPNR

ACTIVE

LQFP

PN

80

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6736

Samples

MSP430F6736IPZ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6736

Samples

MSP430F6736IPZRACTIVE

LQFP

PZ

100

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6736

Samples

SN0806723IPNR

ACTIVE

LQFP

PN

80

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

F6723

Samples(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 3

PACKAGE OPTION ADDENDUM
www.ti.com

16-Aug-2023

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 4

PACKAGE MATERIALS INFORMATION
www.ti.com

28-Mar-2024

TAPE AND REEL INFORMATIONREEL DIMENSIONSTAPE DIMENSIONS
K0

P1

B0 W
Reel
DiameterCavity
A0
B0
K0
W
P1

A0

Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers

Reel Width (W1)QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes

Q1

Q2

Q1

Q2

Q3

Q4

Q3

Q4

User Direction of Feed

Pocket Quadrants*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

MSP430F6720IPNR

LQFP

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

PN

80

1000

330.0

24.4

15.0

15.0

2.1

20.0

24.0

Q2

MSP430F6720IPZR

LQFP

PZ

100

1000

330.0

24.4

17.0

17.0

2.1

20.0

24.0

Q2

MSP430F6721IPNR

LQFP

PN

80

1000

330.0

24.4

15.0

15.0

2.1

20.0

24.0

Q2

MSP430F6721IPZR

LQFP

PZ

100

1000

330.0

24.4

17.0

17.0

2.1

20.0

24.0

Q2

MSP430F6723IPNR

LQFP

PN

80

1000

330.0

24.4

15.0

15.0

2.1

20.0

24.0

Q2

MSP430F6723IPZR

LQFP

PZ

100

1000

330.0

24.4

17.0

17.0

2.1

20.0

24.0

Q2

MSP430F6724IPNR

LQFP

PN

80

1000

330.0

24.4

15.0

15.0

2.1

20.0

24.0

Q2

MSP430F6725IPNR

LQFP

PN

80

1000

330.0

24.4

15.0

15.0

2.1

20.0

24.0

Q2

MSP430F6725IPZR

LQFP

PZ

100

1000

330.0

24.4

17.0

17.0

2.1

20.0

24.0

Q2

MSP430F6726IPNR

LQFP

PN

80

1000

330.0

24.4

15.0

15.0

2.1

20.0

24.0

Q2

MSP430F6726IPZR

LQFP

PZ

100

1000

330.0

24.4

17.0

17.0

2.1

20.0

24.0

Q2

MSP430F6730IPNR

LQFP

PN

80

1000

330.0

24.4

15.0

15.0

2.1

20.0

24.0

Q2

MSP430F6731IPNR

LQFP

PN

80

1000

330.0

24.4

15.0

15.0

2.1

20.0

24.0

Q2

MSP430F6733IPNR

LQFP

PN

80

1000

330.0

24.4

15.0

15.0

2.1

20.0

24.0

Q2

MSP430F6733IPZR

LQFP

PZ

100

1000

330.0

24.4

17.0

17.0

2.1

20.0

24.0

Q2

MSP430F6734IPNR

LQFP

PN

80

1000

330.0

24.4

15.0

15.0

2.1

20.0

24.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

28-Mar-2024

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

MSP430F6734IPZR

LQFP

PZ

100

1000

330.0

24.4

17.0

17.0

2.1

20.0

24.0

Q2

MSP430F6736IPNR

LQFP

PN

80

1000

330.0

24.4

15.0

15.0

2.1

20.0

24.0

Q2

MSP430F6736IPZR

LQFP

PZ

100

1000

330.0

24.4

17.0

17.0

2.1

20.0

24.0

Q2

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

28-Mar-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)

W

L

H

*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)

MSP430F6720IPNR

LQFP

MSP430F6720IPZR

LQFP

PN

80

1000

350.0

350.0

43.0

PZ

100

1000

350.0

350.0

43.0

MSP430F6721IPNR

LQFP

MSP430F6721IPZR

LQFP

PN

80

1000

350.0

350.0

43.0

PZ

100

1000

350.0

350.0

43.0

MSP430F6723IPNR

LQFP

MSP430F6723IPZR

LQFP

PN

80

1000

350.0

350.0

43.0

PZ

100

1000

350.0

350.0

MSP430F6724IPNR

43.0

LQFP

PN

80

1000

350.0

350.0

43.0

MSP430F6725IPNR

LQFP

PN

80

1000

350.0

350.0

43.0

MSP430F6725IPZR

LQFP

PZ

100

1000

350.0

350.0

43.0

MSP430F6726IPNR

LQFP

PN

80

1000

350.0

350.0

43.0

MSP430F6726IPZR

LQFP

PZ

100

1000

350.0

350.0

43.0

MSP430F6730IPNR

LQFP

PN

80

1000

350.0

350.0

43.0

MSP430F6731IPNR

LQFP

PN

80

1000

350.0

350.0

43.0

MSP430F6733IPNR

LQFP

PN

80

1000

367.0

367.0

45.0

MSP430F6733IPZR

LQFP

PZ

100

1000

350.0

350.0

43.0

MSP430F6734IPNR

LQFP

PN

80

1000

350.0

350.0

43.0

MSP430F6734IPZR

LQFP

PZ

100

1000

350.0

350.0

43.0

MSP430F6736IPNR

LQFP

PN

80

1000

350.0

350.0

43.0

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION
www.ti.com

28-Mar-2024

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)

MSP430F6736IPZR

LQFP

PZ

100

1000

350.0

350.0

43.0

Pack Materials-Page 4

PACKAGE MATERIALS INFORMATION
www.ti.com

28-Mar-2024

TRAY
L - Outer tray length without tabs

KO Outertray
height

WOuter
tray
width
Text

P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

DevicePackage
Name

Package
Type

Pins

SPQ

Unit arrayMax
L (mm) W
matrix temperature
(mm)
(°C)

MSP430F6720IPN

PN

LQFP

80

119

7 x 17

150

315

K0
(µm)

P1
(mm)

CL
(mm)

CW
(mm)

135.9

7620

17.9

14.3

13.95

MSP430F6720IPZ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

MSP430F6721IPN

PN

LQFP

80

119

7 x 17

150

315

135.9

7620

17.9

14.3

13.95

MSP430F6721IPZ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

MSP430F6723IPN

PN

LQFP

80

119

7 x 17

150

315

135.9

7620

17.9

14.3

13.95

MSP430F6723IPZ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

MSP430F6724IPN

PN

LQFP

80

119

7 x 17

150

315

135.9

7620

17.9

14.3

13.95

MSP430F6724IPZ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

MSP430F6725IPN

PN

LQFP

80

119

7 x 17

150

315

135.9

7620

17.9

14.3

13.95

MSP430F6725IPZ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

MSP430F6726IPN

PN

LQFP

80

119

7 x 17

150

315

135.9

7620

17.9

14.3

13.95

MSP430F6726IPZ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

MSP430F6730IPN

PN

LQFP

80

119

7 x 17

150

315

135.9

7620

17.9

14.3

13.95

MSP430F6730IPZ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

MSP430F6731IPN

PN

LQFP

80

119

7 x 17

150

315

135.9

7620

17.9

14.3

13.95

MSP430F6733IPN

PN

LQFP

80

119

7 x 17

150

315

135.9

7620

17.9

14.3

13.95

MSP430F6733IPZ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

Pack Materials-Page 5

PACKAGE MATERIALS INFORMATION
www.ti.com

28-Mar-2024

DevicePackage
Name

Package
Type

Pins

SPQ

MSP430F6734IPN

PN

MSP430F6734IPZ

PZ

MSP430F6735IPN

Unit arrayMax
L (mm) W
matrix temperature
(mm)
(°C)

K0
(µm)

P1
(mm)

CL
(mm)

CW
(mm)

LQFP

80

119

7 x 17

150

315

LQFP

100

90

6 x 15

150

315

135.9

7620

17.9

14.3

13.95

135.9

7620

20.3

15.4

PN

LQFP

80

119

7 x 17

150

15.45

315

135.9

7620

17.9

14.3

13.95

MSP430F6735IPZ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

MSP430F6736IPN

PN

LQFP

80

119

7 x 17

150

315

135.9

7620

17.9

14.3

13.95

MSP430F6736IPZ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.45

Pack Materials-Page 6

PACKAGE OUTLINE

PN0080A

LQFP - 1.6 mm max height
SCALE 1.250

PLASTIC QUAD FLATPACK

12.2
11.8

PIN 1 ID

B

80

A

61

1

60

12.2
11.8

14.2
TYP
13.8

20
41
40

21
76X 0.5

80X

4X 9.5

0.27
0.17
0.08

C A B

1.6 MAXC(0.13) TYP

SEATING PLANE
0.08

SEE DETAIL A

0.25
GAGE PLANE

0 -7

(1.4)

0.05 MIN

0.75
0.45

DETAIL A
DETAIL A
SCALE: 14

TYPICAL
4215166/A 08/2022

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.

www.ti.com

EXAMPLE BOARD LAYOUT

PN0080A

LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

SYMM
61

80
80X (1.5)
160
80X (0.3)

SYMM

76X (0.5)(13.4)(R0.05) TYP

41

20

21

40
(13.4)LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:6X

0.05 MAXALL AROUNDEXPOSED METALMETALSOLDER MASKOPENINGEXPOSED METALMETAL UNDERSOLDER MASKSOLDER MASKNON SOLDER MASKDEFINED

0.05 MIN
ALL AROUNDSOLDER MASKDEFINEDSOLDER MASK DETAILS
4215166/A 08/2022

NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
6. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).

www.ti.com

EXAMPLE STENCIL DESIGN

PN0080A

LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

SYMM
80

61

80X (1.5)
160
80X (0.3)

SYMM

76X (0.5)(13.4)(R0.05) TYP

41

20

21

40
(13.4)SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCILSCALE:6X

4215166/A 08/2022

NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com

MECHANICAL DATAMTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996

PZ (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27
0,17

0,50
75

0,08 M

51

76

50

100

26

1

0,13 NOM

25
12,00 TYP

Gage Plane

14,20
SQ
13,80
16,20
SQ
15,80

0,05 MIN

1,45
1,35

0,25
0°– 7°

0,75
0,45
Seating Plane
0,08

1,60 MAX

4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026

POST OFFICE BOX 655303• DALLAS, TEXAS 75265

1

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