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参考資料

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

TMS320F280x、、TMS320C280x、、TMS320F2801x デジタル・シグナル・プロ
セッサ
1 デバイスの概要
1.1

特長

1

• 高性能スタティック CMOS テクノロジ– 100MHz (サイクル・タイム 10ns)– 60MHz (サイクル・タイム 16.67ns)– 低消費電力 (コア 1.8V、I/O 3.3V) の設計• JTAG バウンダリ・スキャンのサポート– IEEE標準 1149.1-1990 標準テスト・アクセス・ポー
トおよびバウンダリ・スキャン・アーキテクチャ• 高性能の 32 ビット CPU (TMS320C28x)– 16 ビット × 16 ビットおよび 32 ビット × 32 ビットのMAC 演算– 16 ビット × 16 ビットのデュアル MAC– ハーバード・バス・アーキテクチャ– アトミック処理– 高速な割り込み応答とプロセッシング– 統合メモリ・プログラミング・ツール– 高いコード効率 (C/C++ およびアセンブリ)• オンチップ・メモリ– F2809：128K × 16 フラッシュ、18K × 16 SARAM
F2808：64K × 16 フラッシュ、18K × 16 SARAM
F2806：32K × 16 フラッシュ、10K × 16 SARAM
F2802：32K × 16 フラッシュ、6K × 16 SARAM
F2801：16K × 16 フラッシュ、6K × 16 SARAM
F2801x：16K × 16 フラッシュ、6K × 16 SARAM– 1K × 16 OTP ROM (フラッシュ・デバイスのみ)– C2802：32K × 16 ROM、6K × 16 SARAM
C2801：16K × 16 ROM、6K × 16 SARAM• ブート ROM (4K × 16)– ソフトウェア・ブート・モード搭載 (SCI、SPI、CAN、
I2C、パラレル I/O 経由)– 標準演算テーブル• クロックおよびシステム制御– オンチップ発振器– ウォッチドッグ・タイマ・モジュール• 任意の GPIO A ピンを、3 つの外部コア割り込みのい
ずれかに接続可能• 43 のペリフェラル割り込みすべてをサポートする、ペリ
フェラル割り込み拡張 (PIE) ブロック• リトル・エンディアン• 128 ビットのセキュリティ・キー/ロック– フラッシュ/OTP/L0/L1 ブロックを保護– ファームウェアのリバース・エンジニアリングを防止• 3 つの 32 ビット CPU タイマ• 拡張制御ペリフェラル– 最大 16 の PWM 出力– 150ps MEP 分解能を持つ、最大 6 つの HRPWM
出力– 最大 4 つのキャプチャ入力– 最大 2 つの直交エンコーダ・インターフェイス– 最大 6 つの 32 ビット / 6 つの 16 ビット・タイマ• シリアル・ポート・ペリフェラル– 最大 4 つの SPI モジュール– 最大 2 つの SCI (UART) モジュール– 最大 2 つの CAN モジュール– 1 つの I2C (Inter-Integrated-Circuit) バス• 12 ビット ADC、16 チャネル
– 2 × 8 チャネルの入力マルチプレクサ– 2 つのサンプル・アンド・ホールド– 単独/同時変換– 高い変換速度：
80ns - 12.5MSPS (F2809 のみ)
160ns - 6.25MSPS (280x)
267ns - 3.75MSPS (F2801x)– 内部または外部のリファレンス• 最大 35 の個別にプログラム可能な、多重化された、入力フィルタリング付き GPIO ピン• 高度なエミュレーション機能– 分析およびブレークポイント機能– ハードウェアによるリアルタイム・デバッグ• 開発サポート– ANSI C/C++ コンパイラ/アセンブラ/リンカ– Code Composer Studio™IDE– SYS/BIOS– デジタル・モータ制御およびデジタル電源のソフト
ウェア・ライブラリ• 低消費電力モードとパワー・セービング– IDLE、STANDBY、HALT モードをサポート– 個別のペリフェラル・クロックの無効化• パッケージ・オプション– 薄型クワッド・フラットパック (PZ)
– MicroStar BGA™(GGM、ZGM)• 温度オプション– A：-40°C～85°C (PZ、GGM、ZGM)– S：-40°C～125°C (PZ、GGM、ZGM)– Q：-40°C～125°C (PZ)
(車載アプリケーション向けに AEC-Q100 認定)

1

英語版のTI製品についての情報を翻訳したこの資料は、製品の概要を確認する目的で便宜的に提供しているものです。該当する正式な英語版の最新情報は、www.ti.comで閲覧でき、その内容が常に優先されます。TIでは翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、必ず最新版の英語版をご参照くださいますようお願いいたします。
English Data Sheet: SPRS230

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 20191.2•

アプリケーション

モータ駆動/制御

1.3

www.tij.co.jp•

デジタル電源概要
TMS320C28x DSP 世代の TMS320F2809、TMS320F2808、TMS320F2806、TMS320F2802、
TMS320F2801、TMS320F28015、TMS320F28016、TMS320C2802、TMS320C2801 デバイスは、要求の厳しい制御アプリケーション向けの高集積高性能ソリューションです。
このドキュメント全体を通して、TMS320F2809、TMS320F2808、TMS320F2806、TMS320F2802、
TMS320F2801、TMS320C2802、TMS320C2801、TMS320F28015、TMS320F28016 を、それぞれ F2809、F2808、F2806、F2802、F2801、C2802、C2801、F28015、F28016 と略記します。TMS320F28015 およびTMS320F28016 を、F2801x と略記します。各デバイスの特長の要約を、「 デバイス比較 (100MHz のデバイス)」と「 デバイス比較 (60MHz のデバイス)」に示します。
製品情報 (1)
パッケージ

本体サイズ

TMS320F2809ZGM

型番

BGA MicroStar (100)10.0mm×10.0mm

TMS320F2808ZGMBGA MicroStar (100)10.0mm×10.0mm

TMS320F2806ZGMBGA MicroStar (100)10.0mm×10.0mm

TMS320F2802ZGMBGA MicroStar (100)10.0mm×10.0mm

TMS320F2801ZGMBGA MicroStar (100)10.0mm×10.0mm

TMS320C2802ZGMBGA MicroStar (100)10.0mm×10.0mm

TMS320C2801ZGMBGA MicroStar (100)10.0mm×10.0mm

TMS320F28016ZGMBGA MicroStar (100)10.0mm×10.0mm

TMS320F28015ZGMBGA MicroStar (100)10.0mm×10.0mm

TMS320F2809GGM

BGA MicroStar (100)10.0mm×10.0mm

TMS320F2808GGM

BGA MicroStar (100)10.0mm×10.0mm

TMS320F2806GGM

BGA MicroStar (100)10.0mm×10.0mm

TMS320F2802GGM

BGA MicroStar (100)10.0mm×10.0mm

TMS320F2801GGM

BGA MicroStar (100)10.0mm×10.0mm

TMS320C2802GGM

BGA MicroStar (100)10.0mm×10.0mm

TMS320C2801GGM

BGA MicroStar (100)10.0mm×10.0mm

TMS320F28016GGMBGA MicroStar (100)10.0mm×10.0mm

TMS320F28015GGMBGA MicroStar (100)10.0mm×10.0mm

TMS320F2809PZ

LQFP (100)14.0mm×14.0mm

TMS320F2808PZ

LQFP (100)14.0mm×14.0mm

TMS320F2806PZ

LQFP (100)14.0mm×14.0mm

TMS320F2802PZ

LQFP (100)14.0mm×14.0mm

TMS320F2801PZ

LQFP (100)14.0mm×14.0mm

TMS320C2802PZ

LQFP (100)14.0mm×14.0mm

TMS320C2801PZ

LQFP (100)14.0mm×14.0mm

TMS320F28016PZ

LQFP (100)14.0mm×14.0mm

TMS320F28015PZ

LQFP (100)14.0mm×14.0mm(1)2

これらのデバイスの詳細については、「メカニカル、パッケージ、および注文情報」を参照してください。

デバイスの概要

Copyright © 2003–2019, Texas Instruments Incorporated

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
www.tij.co.jp

1.4

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

機能ブロック図Memory Bus
TINT032-bit CPU TIMER 0

TINT1

7

32-bit CPU TIMER 1
TINT2

32-bit CPU TIMER 2
INT14
PIE
(96 Interrupts)(A)

INT[12:1]

External Interrupt
Control

32

NMI, INT13

4
16

SCI-A/B

FIFO

SPI-A/B/C/D

FIFO

I2C-A

FIFO

GPIO MUX

GPIOs
(35)

M0 SARAM
1K x 16
M1 SARAM
1K x 16

L0 SARAM
4K x 16(0-wait)
L1 SARAM
4K x 16(0-wait)2
4

Real-Time JTAG
(TDI, TDO, TRST, TCK,
TMS, EMU0, EMU1)(B)

H0 SARAM
8K x 16(0-wait)(C)

eCAN-A/B (32 mbox)

8
eQEP1/2
4

C28x CPU(100 MHz)eCAP1/2/3/4(4 32-bit Timers)

12ROM
32K x 16 (C2802)
16K x 16 (C2801)

ePWM1/2/3/4/5/6(12 PWM Outputs,
6 Trip Zones,
6 16-bit Timers)

6

SYSCLKOUT

32
System Control

FLASH
128K x 16 (F2809)
64K x 16 (F2808)
32K x 16 (F2806)
32K x 16 (F2802)
16K x 16 (F2801)
16K x 16 (F2801x)

RS

XCLKOUTXRSXCLKIN
X1
X2(Oscillator, PLL,
Peripheral Clocking,
Low-Power Modes,
Watchdog)

CLKIN
(D)

OTP
1K x 16

ADCSOCA/B
Boot ROM
4K x 16(1-wait state)

SOCA/B
12-Bit ADC
16 Channels

Protected by the code-security module.

Peripheral Bus

Copyright © 2016, Texas Instruments Incorporated

A.
B.
C.
D.

使用可能な 96 の割り込みのうち 43 が本デバイスで使用されています。
F2802、F2801、C2802、C2801 では使用できません。
F2806、F2802、F2801、C2802、C2801 では使用できません。
C280x デバイスでは、1K × 16 OTP が 1K × 16 ROM に置き換えられています。

図 1-1. 機能ブロック図
Copyright © 2003–2019, Texas Instruments Incorporated

デバイスの概要

3

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.tij.co.jp

Table of Contents
1

デバイスの概要 ............................................. 1

Pin PZ Package ..................................... 33

1.1

特長 ................................................... 1

5.13

Thermal Design Considerations .................... 33

1.2

アプリケーション ........................................ 2

5.14

Timing and Switching Characteristics ............... 34

1.3

概要 ................................................... 2

5.15

On-Chip Analog-to-Digital Converter ................ 60

1.4

機能ブロック図 ......................................... 3

5.16

Migrating From F280x Devices to C280x Devices .. 6623

改訂履歴 .................................................... 5
Device Comparison ..................................... 7

5.17

ROM Timing (C280x only) .......................... 67

Related Products ..................................... 9

6.1

Brief Descriptions.................................... 68

4

Terminal Configuration and Functions ............ 10

6.2

Peripherals .......................................... 75

4.1

Pin Diagrams ........................................ 10

6.3

Memory Maps ...................................... 109

4.2

3.1

5

Detailed Description ................................... 68

Signal Descriptions .................................. 15

6.4

Register Map ....................................... 117

Specifications ........................................... 21

6.5Interrupts ........................................... 120

5.1

Absolute Maximum Ratings ........................ 21

6.6

System Control..................................... 125

5.2

ESD Ratings – Automotive ......................... 22

6.7

Low-Power Modes Block .......................... 131

5.3

ESD Ratings – Commercial ......................... 22

5.4

Recommended Operating Conditions ............... 225.5Power Consumption Summary ..................... 23

5.6
5.7

Electrical Characteristics ...........................
Thermal Resistance Characteristics for F280x 100Ball GGM Package ..................................
Thermal Resistance Characteristics for F280x 100Pin PZ Package .....................................
Thermal Resistance Characteristics for C280x 100Ball GGM Package ..................................
Thermal Resistance Characteristics for C280x 100Pin PZ Package .....................................
Thermal Resistance Characteristics for F2809 100Ball GGM Package ..................................
Thermal Resistance Characteristics for F2809 100-

5.8
5.9
5.10
5.11
5.12

4

6

Table of Contents

7

Applications, Implementation, and Layout ...... 132

8

デバイスおよびドキュメントのサポート .................. 133

7.1

30
31
31
32
32
33

9

TI Design or Reference Design .................... 132

8.1

はじめに ............................................ 133

8.2

デバイスおよび開発ツールの項目表記 .............. 134

8.3

ツールとソフトウェア ................................. 136

8.4

ドキュメントのサポート ................................ 137

8.5

関連リンク ........................................... 139

8.6

Community Resources............................. 139

8.7

商標 ................................................ 139

8.8

静電気放電に関する注意事項 ...................... 139

8.9

Glossary............................................ 140

メカニカル、パッケージ、および注文情報 .............. 141
9.1

パッケージ情報 ..................................... 141

Copyright © 2003–2019, Texas Instruments Incorporated

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

2 改訂履歴
2012年
年5月
月31日
日発行分から2019年
年03月
月11日
日発行分への変更 (from N Revision (May 2012) to O Revision)
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Page

グローバル: ドキュメントを再構成。 ................................................................................................... 1
グローバル：「DSP/BIOS」を「SYS/BIOS」に置き換え。............................................................................. 1
グローバル：「CAN 2.0B」を「ISO 11898-1 (CAN 2.0B)」に変更。................................................................. 1
グローバル：『Reliability Data for TMS320LF24xx and TMS320F28xx Devices Application Report』 (SPRA963) への参照を削除。............................................................................................................................... 1
1 (デバイスの概要)：セクションのタイトルを「F280x、F2801x、C280x DSP」から「デバイスの概要」に変更。 ................. 1
1.1 (特長)：「動的なPLL比率変更をサポート」の特長を削除。...................................................................... 1
1.1：Q 温度オプションに、「(車載アプリケーション用に AEC-Q100 認定)」を追加。 .............................................. 1
1.2 (アプリケーション): セクションを追加。 ........................................................................................... 2
1.3 (概要)：セクションを追加。......................................................................................................... 2
1.4 (機能ブロック図)：セクションを追加。 ............................................................................................ 3
Section 3 (Device Comparison): Added section. ................................................................................ 7
Table 3-1 (Device Comparison (100-MHz Devices)): Changed title from "Hardware Features (100-MHz
Devices)" to "Device Comparison (100-MHz Devices)". ........................................................................ 7
Table 3-1: Changed "PWM outputs" to "PWM channels". ...................................................................... 7
Table 3-1: Added "(AEC-Q100 Qualification)" after Q temperature range. .................................................. 7
Table 3-1: Removed "Product status" row. ....................................................................................... 7
Table 3-2 (Device Comparison (60-MHz Devices)): Changed title from "Hardware Features (60-MHz Devices)"to "Device Comparison (60-MHz Devices)". ...................................................................................... 8
Table 3-2: Changed "PWM outputs" to "PWM channels". ...................................................................... 8
Table 3-2: Added "(AEC-Q100 Qualification)" after Q temperature range. .................................................. 8
Table 3-2: Removed "Product status" row. ....................................................................................... 8
Section 3.1 (Related Products): Added section. ................................................................................. 9
Section 4 (Terminal Configuration and Functions): Added section. ......................................................... 10
Section 4.1 (Pin Diagrams): Changed section title from "Pin Assignments" to "Pin Diagrams". ......................... 10
Table 4-1 (Signal Descriptions): Updated DESCRIPTION of XRS. .......................................................... 15
Section 5.2 (ESD Ratings – Automotive): Added section. ..................................................................... 22
Section 5.3 (ESD Ratings – Commercial): Added section. ................................................................... 22
Section 5.4 (Recommended Operating Conditions): Changed "Q version (Q100 Qualification)" to "Q version(AEC-Q100 Qualification)". ........................................................................................................ 22
Section 5.5 (Power Consumption Summary): Changed section title from "Current Consumption" to "Power
Consumption Summary". .......................................................................................................... 23
Section 5.13 (Thermal Design Considerations): Added section. ............................................................. 33
Section 5.14 (Timing and Switching Characteristics): Added section. ...................................................... 34
Section 5.14.2 (Power Sequencing): Updated "No voltage larger than a diode drop ..." paragraph. ................... 36
Section 5.14.2: Removed "Power Management and Supervisory Circuit Solutions" section. ............................ 36
Figure 5-12 (General-Purpose Input Timing): Changed XCLKOUT to SYSCLK. .......................................... 44
Figure 5-16 (PWM Hi-Z Characteristics): Changed XCLKOUT to SYSCLK. ............................................... 48
Table 5-24 (High-Resolution PWM Characteristics at SYSCLKOUT = 60–100 MHz): Updated footnote. ............. 49
Section 5.14.4.5.1 (SPI Master Mode Timing): Updated section. ............................................................ 52
Section 5.14.4.5.2 (SPI Slave Mode Timing): Updated section. ............................................................. 55
Table 5-39 (Flash Parameters at 100-MHz SYSCLKOUT): Added MAX Program Time values and MAX Erase
Time values. Updated and added footnotes. .................................................................................... 58
Table 5-41 (Flash Data Retention Duration): Added table. ................................................................... 59
Section 5.16.1 (Migration Issues): Added NOTE about ROM versions of F280x device not being accepted by TI
anymore. ............................................................................................................................. 66
Section 6 (Detailed Description): Changed section title from "Functional Overview" to "Detailed Description". ....... 68
Section 6.1.6 (ROM): Added NOTE. ............................................................................................. 69
Section 6.2.6 (Enhanced Analog-to-Digital Converter (ADC) Module): Updated equations by which the digitalvalue of the input analog voltage is derived. .................................................................................... 85
Section 6.2.9 (Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)): Updated "Rising edge
with phase delay" clockng scheme ............................................................................................... 99
Table 6-27 (Device Emulation Registers): Updated REVID: Added Silicon rev. A for F2809 only. .................... 119
Table 6-28 (PIE Peripheral Interrupts): Added footnote about ADCINT. .................................................. 122
Figure 6-30 (Watchdog Module): Updated figure. ............................................................................ 130
改訂履歴Submit Documentation Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

Copyright © 2003–2019, Texas Instruments Incorporated

5

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

•
•
•
•
•
•

6

www.ti.com

Section 7 (Applications, Implementation, and Layout): Added section. .................................................... 132
8 (デバイスおよびドキュメントのサポート): セクションを追加。 .................................................................. 133
図 8-1 (TMS320x280x/2801x デバイスの項目表記例)：「(Q100 認定)」を「(AEC-Q100 認定)」に変更。 .................. 135
8.3 (ツールとソフトウェア)：セクションを追加。 ................................................................................... 136
8.4 (ドキュメントのサポート): セクションを更新。 ................................................................................. 137
8.5 (関連リンク)：セクションを追加。 .............................................................................................. 139

改訂履歴

Copyright © 2003–2019, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

3 Device Comparison
Table 3-1. Device Comparison (100-MHz Devices)
TYPE (1)

F2809

F2808

F2806

F2802

F2801

C2802

C2801

–

10 ns

10 ns

10 ns

10 ns

10 ns

10 ns

10 ns

Single-access RAM (SARAM) (16-bit word)–

18K(L0, L1, M0, M1,
H0)

18K(L0, L1, M0, M1,
H0)

10K(L0, L1, M0, M1)

6K(L0, M0, M1)

6K(L0, M0, M1)

6K(L0, M0, M1)

6K(L0, M0, M1)

3.3-V on-chip flash (16-bit word)

–

128K

64K

32K

32K

16K

–

–

On-chip ROM (16-bit word)

–

–

–

–

–

–

32K

16K

Code security for on-chip flash/SARAM/OTP blocks

–

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Boot ROM (4K x 16)

–

Yes

Yes

Yes

Yes

Yes

Yes

Yes

One-time programmable (OTP) ROM(16-bit word)

–

1K

1K

1K

1K

1K

–

–

PWM channels

0

ePWM1/2/3/4/5/6

ePWM1/2/3/4/5/6

ePWM1/2/3/4/5/6

ePWM1/2/3

ePWM1/2/3

ePWM1/2/3

ePWM1/2/3

HRPWM channels

0

ePWM1A/2A/3A/
4A/5A/6A

ePWM1A/2A/
3A/4A

ePWM1A/2A/
3A/4A

ePWM1A/2A/3A

ePWM1A/2A/3A

ePWM1A/2A/3A

ePWM1A/2A/3A

32-bit CAPTURE inputs or auxiliary PWM outputs

0

eCAP1/2/3/4

eCAP1/2/3/4

eCAP1/2/3/4

eCAP1/2

eCAP1/2

eCAP1/2

eCAP1/2

32-bit QEP channels (four inputs/channel)0

eQEP1/2

eQEP1/2

eQEP1/2

eQEP1

eQEP1

eQEP1

eQEP1

Watchdog timer

–

Yes

Yes

Yes

Yes

Yes

Yes

Yes

12-Bit, 16-channel ADC conversion time

1

80 ns

160 ns160 ns160 ns160 ns160 ns160 ns32-Bit CPU timers

–

3

3

3

3

3

3

3

Serial Peripheral Interface (SPI)0

SPI-A/B/C/D

SPI-A/B/C/D

SPI-A/B/C/D

SPI-A/B

SPI-A/B

SPI-A/B

SPI-A/B

Serial Communications Interface (SCI)0

SCI-A/B

SCI-A/B

SCI-A/B

SCI-A

SCI-A

SCI-A

SCI-A

Enhanced Controller Area Network (eCAN)

0

eCAN-A/B

eCAN-A/B

eCAN-AeCAN-AeCAN-AeCAN-AeCAN-A

Inter-Integrated Circuit (I2C)

0

I2C-A

I2C-A

I2C-A

I2C-A

I2C-A

I2C-A

I2C-A

Digital I/O pins (shared)

–

35

35

35

35

35

35

35

External interrupts

–

3

3

3

3

3

3

3

1.8-V Core, 3.3-V I/O

–

Yes

Yes

Yes

Yes

Yes

Yes

Yes

100-Pin PZ

–

Yes

Yes

Yes

Yes

Yes

Yes

Yes

100-Ball GGM, ZGM

–

Yes

Yes

Yes

Yes

Yes

Yes

Yes

A: –40°C to 85°C–

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

S: –40°C to 125°C–(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

Q: –40°C to 125°C(AEC-Q100 Qualification)

–

(PZ)

(PZ)

(PZ)

(PZ)

(PZ)

(PZ)

(PZ)

FEATURE
Instruction cycle (at 100 MHz)

Supply voltage
PackagingTemperature options(1)

A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect thebasic functionality of the module. These device-specific differences are listed in the C2000 real-time control peripherals reference guide and in the peripheral reference guides.

Copyright © 2003–2019, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

Device Comparison

7

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

Table 3-2. Device Comparison (60-MHz Devices)
TYPE (1)F2802-60

F2801-60

F28016

F28015

Instruction cycle (at 60 MHz)–

16.67 ns

16.67 ns

16.67 ns

16.67 ns

Single-access RAM (SARAM) (16-bit word)–

6K(L0, M0, M1)

6K(L0, M0, M1)

6K(L0, M0, M1)

6K(L0, M0, M1)

3.3-V on-chip flash (16-bit word)

–

32K

16K

16K

16K

On-chip ROM (16-bit word)

–

–

–

–

–

Code security for on-chip flash/SARAM/OTP blocks

–

Yes

Yes

Yes

Yes

Boot ROM (4K x 16)

–

Yes

Yes

Yes

Yes

One-time programmable (OTP) ROM(16-bit word)

–

1K

1K

1K

1K

PWM channels

0

ePWM1/2/3

ePWM1/2/3

ePWM1/2/3/4

ePWM1/2/3/4

HRPWM channels

0

ePWM1A/2A/3A

ePWM1A/2A/3A

ePWM1A/2A/3A/4A

ePWM1A/2A/3A/4A

32-bit CAPTURE inputs or auxiliary PWM outputs

0

eCAP1/2

eCAP1/2

eCAP1/2

eCAP1/2

32-bit QEP channels (four inputs/channel)

0

eQEP1

eQEP1

-

-

Watchdog timer

–

Yes

Yes

Yes

Yes

16

16

16

16

1

3.75

3.75

3.75

3.75
267 nsFEATURE

No. of channels
12-Bit ADC

MSPS

267 ns267 ns267 ns32-Bit CPU timers

Conversion time
–

3

3

3

3

Serial Peripheral Interface (SPI)0

SPI-A/B

SPI-A/B

SPI-A

SPI-A

Serial Communications Interface (SCI)

0

SCI-A

SCI-A

SCI-A

SCI-A

Enhanced Controller Area Network (eCAN)

0

eCAN-AeCAN-AeCAN-A-

Inter-Integrated Circuit (I2C)

0

I2C-A

I2C-A

I2C-A

I2C-A

Digital I/O pins (shared)

–

35

35

35

35

External interrupts

–

3

3

3

3

–

1.8-V Core,
3.3-V I/O

1.8-V Core,
3.3-V I/O

1.8-V Core,
3.3-V I/O

1.8-V Core,
3.3-V I/O

100-Pin PZ

–

Yes

Yes

Yes

Yes

100-Ball GGM, ZGM

–

Yes

Yes

Yes

Yes

A: –40°C to 85°C–

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

S: –40°C to 125°C–(PZ GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

Q: –40°C to 125°C(AEC-Q100 Qualification)

–

(PZ)

(PZ)

(PZ)

(PZ)

Supply voltage
PackagingTemperature options(1)

8

A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect thebasic functionality of the module. These device-specific differences are listed in the C2000 real-time control peripherals reference guide and in the peripheral reference guides.

Device Comparison

Copyright © 2003–2019, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com

3.1

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Related Products
For information about other devices in this family of products, see the following links:
TMS320F2837xS Delfino™ Microcontrollers
The Delfino™ TMS320F2837xS is a powerful 32-bit floating-point microcontroller unit (MCU) designed foradvanced closed-loop control applications such as industrial drives and servo motor control; solar
inverters and converters; digital power; transportation; and power line communications. Complete
development packages for digital power and industrial drives are available as part of the powerSUITE andDesignDRIVE initiatives.

Device Comparison
Submit Documentation Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

Copyright © 2003–2019, Texas Instruments Incorporated

9

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

4 Terminal Configuration and Functions
4.1

Pin Diagrams

GPIO18/SPICLKA/SCITXDBGPIO5/EPWM3B/SPICLKD/ECAP1

GPIO17/SPISOMIA/CANRXB/TZ6

GPIO4/EPWM3A

54

53

52

51

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
VSS
56

55

GPIO7/EPWM4B/SPISTED/ECAP2

GPIO19/SPISTEA/SCIRXDB
57

59

58

GPIO9/EPWM5B/SCITXDB/ECAP3

GPIO8/EPWM5A/CANTXB/ADCSOCAO
VDD

61

62

60

GPIO10/EPWM6A/CANRXB/ADCSOCBO
GPIO20/EQEP1A/SPISIMOC/CANTXB
VSS
64

63

XCLKOUT
VDDIO
66

65

VDD

GPIO21/EQEP1B/SPISOMIC/CANRXB
67

69

68

GPIO22/EQEP1S/SPICLKC/SCITXDBGPIO11/EPWM6B/SCIRXDB/ECAP4
VSS

71

72

70

TMS

TDI
GPIO23/EQEP1I/SPISTEC/SCIRXDB73

XRSGPIO27/ECAP4/EQEP2S/SPISTEB

TCK
76

75

TDO
VSS

74

The TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28015, and TMS320F28016 100-pin PZ low-profile quad flatpack (LQFP) pin
assignments are shown in Figure 4-1, Figure 4-2, Figure 4-3, and Figure 4-4. The 100-ball GGM and ZGM
ball grid array (BGA) terminal assignments are shown in Figure 4-5. Table 4-1 describes the function(s) ofeach pin.

50
49

GPIO16/SPISIMOA/CANTXB/TZ5
VSS

78

48

GPIO3/EPWM2B/SPISOMID

79

47

EMU0

80

46

GPIO0/EPWM1A
VDDIO

EMU1
VDDIO

81

45

GPIO2/EPWM2A

82

44

GPIO1/EPWM1B/SPISIMOD

GPIO24/ECAP1/EQEP2A/SPISIMOB

83

43

TRST
VDD

84

42

GPIO34
VDD

85

41

VSS

X2
VSS

86

40

VDD2A18

87

39

VSS2AGND

X1
VSS

88

38

ADCRESEXT

89

37

ADCREFPXCLKINGPIO25/ECAP2/EQEP2B/SPISOMIB

9036

ADCREFM

91

35

ADCREFIN

GPIO28/SCIRXDA/TZ5
VDD

92

34

ADCINB79333

ADCINB6

VSS

94

32

ADCINB5

GPIO13/TZ2/CANRXB/SPISOMIB
VDD3VFL

95

31

ADCINB49630

ADCINB3

TEST1

97

29

ADCINB2

TEST2
GPIO26/ECAP3/EQEP2I/SPICLKB9828ADCINB1

99

27

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

100

26

ADCINB0
VDDAIO24ADCLO
VSSAIO25

22

23

ADCINA1

ADCINA020

21
ADCINA219ADCINA4ADCINA31718

ADCINA6

16ADCINA7ADCINA5

14

15

VSSA2

VDDA2

12

13

10

11
VSS

VDD1A18

9GPIO15/TZ4/SCIRXDB/SPISTEBVDD

VSS1AGND

7

8

GPIO31/CANTXAGPIO14/TZ3/SCITXDB/SPICLKB

6

4

5

GPIO29/SCITXDA//TZ6

3
VDDIO

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO30/CANRXA

2

1

GPIO12/TZ1/CANTXB/SPISIMOB
VSS

77

Figure 4-1. TMS320F2809, TMS320F2808 100-Pin PZ LQFP (Top View)

10

Terminal Configuration and Functions

Copyright © 2003–2019, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015

GPIO18/SPICLKA/SCITXDBGPIO5/EPWM3B/SPICLKD/ECAP1

GPIO17/SPISOMIA/TZ6

GPIO4/EPWM3A

54

53

52

51

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
VSS
56

55

GPIO7/EPWM4B/SPISTED/ECAP2

GPIO19/SPISTEA/SCIRXDB
57

59

58

GPIO9/EPWM5B/SCITXDB/ECAP3

GPIO8/EPWM5A/ADCSOCAO
VDD

61

62

60

GPIO10/EPWM6A/ADCSOCBO
GPIO20/EQEP1A/SPISIMOC
VSS
64

63

XCLKOUT
VDDIO
66

65

VDD

GPIO21/EQEP1B/SPISOMIC
67

69

68

GPIO22/EQEP1S/SPICLKC/SCITXDBGPIO11/EPWM6B/SCIRXDB/ECAP4
VSS

71

72

70

TMS

TDI
GPIO23/EQEP1I/SPISTEC/SCIRXDBXRSGPIO27/ECAP4/EQEP2S/SPISTEB

73

76

TCK
TDO
VSS

75

JAJS280O – OCTOBER 2003 – REVISED MARCH 201974

www.ti.com

50
49

GPIO16/SPISIMOA/TZ5
VSS

78

48

GPIO3/EPWM2B/SPISOMID

79

47

EMU0

80

46

GPIO0/EPWM1A
VDDIO

EMU1
VDDIO

81

45

GPIO2/EPWM2A

82

44

GPIO1/EPWM1B/SPISIMOD

GPIO24/ECAP1/EQEP2A/SPISIMOB

83

43

TRST
VDD

84

42

GPIO34
VDD

85

41

VSS

X2
VSS

86

40

VDD2A18

87

39

VSS2AGND

X1
VSS

88

38

ADCRESEXT

89

37

ADCREFPXCLKINGPIO25/ECAP2/EQEP2B/SPISOMIB

9036

ADCREFM

91

35

ADCREFIN

GPIO28/SCIRXDA/TZ5
VDD

92

34

ADCINB79333

ADCINB6

VSS

94

32

ADCINB5

GPIO13/TZ2/SPISOMIB
VDD3VFL

95

31

ADCINB49630

ADCINB3

TEST1

97

29

ADCINB2

TEST2
GPIO26/ECAP3/EQEP2I/SPICLKB9828ADCINB1

99

27

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

100

26

ADCINB0
VDDAIO24ADCLO
VSSAIO25

22

23

ADCINA1

ADCINA020

21
ADCINA219ADCINA4ADCINA31718

ADCINA6

16ADCINA7ADCINA5

14

15

VSSA2

VDDA2

12

13

10

11
VSS

VDD1A18

9GPIO15/TZ4/SCIRXDB/SPISTEBVDD

VSS1AGND

7

8

GPIO31/CANTXAGPIO14/TZ3/SCITXDB/SPICLKB

6

4

5

GPIO29/SCITXDA//TZ6

3
VDDIO

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO30/CANRXA

2

1

GPIO12/TZ1/SPISIMOB
VSS

77

Figure 4-2. TMS320F2806 100-Pin PZ LQFP (Top View)

Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

Copyright © 2003–2019, Texas Instruments Incorporated

11

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015

GPIO18/SPICLKA

GPIO5/EPWM3B/ECAP1

GPIO17/SPISOMIA/TZ6

GPIO4/EPWM3A

54

53

52

51

GPIO6/EPWMSYNCI/EPWMSYNCO
VSS
56

55

GPIO7/ECAP2

GPIO19/SPISTEA
57

59

58

GPIO9

GPIO8/ADCSOCAO
VDD

61

62

60

GPIO10/ADCSOCBO
GPIO20/EQEP1A
VSS
64

63

XCLKOUT
VDDIO
66

65

VDD

GPIO21/EQEP1B
67

69

68

GPIO22/EQEP1SGPIO11
VSS

71

72

70

TMS

TDI
GPIO23/EQEP1I

50
49

GPIO16/SPISIMOA/TZ5
VSS

78

48

GPIO3/EPWM2B

79

47

EMU0

80

46

GPIO0/EPWM1A
VDDIO

EMU1
VDDIO

81

45

GPIO2/EPWM2A

82

44

GPIO1/EPWM1B

SPISIMOB/GPIO24/ECAP1

83

43

TRST
VDD

84

42

GPIO34
VDD

85

41

VSS

X2
VSS

86

40

VDD2A18

87

39

VSS2AGND

X1
VSS

88

38

ADCRESEXT

89

37

ADCREFPXCLKINGPIO25/ECAP2/SPISOMIB

9036

ADCREFM

91

35

ADCREFIN

GPIO28/SCIRXDA/TZ5
VDD

92

34

ADCINB79333

ADCINB6

VSS

94

32

ADCINB5SPISOMIB/GPIO13/TZ2

95

31

ADCINB4VDD3VFL
TEST1

96

30

ADCINB3

9729

ADCINB2TEST2SPICLKB/GPIO26

98

28

ADCINB1

99

27

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

100

26

ADCINB0
VDDAIO24ADCLO
VSSAIO25

22

23

ADCINA1

ADCINA2

ADCINA020

21

ADCINA31718

ADCINA6ADCINA519

16
ADCINA7ADCINA4

14

15

VSSA2

VDDA2

12

13

10

11
VSS

VDD1A18

9

SPISTEB/GPIO15/TZ4VDD

VSS1AGND

7

8

GPIO31/CANTXA6SPICLKB/GPIO14/TZ3

4

5

GPIO29/SCITXDA//TZ6

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO30/CANRXA

3
VDDIO

1

2

77

SPISIMOB/GPIO12/TZ1
VSS

(A)

A.

73

XRS
SPISTEB/GPIO27

TCK
76

75

TDO
VSS

www.ti.com

74

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

On the C280x devices, the VDD3VFL pin is VDDIO.

Figure 4-3. TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP (Top View)

12

Terminal Configuration and Functions

Copyright © 2003–2019, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015

GPIO18/SPICLKA

GPIO5/EPWM3B/ECAP1

GPIO17/SPISOMIA/TZ6

GPIO4/EPWM3A

54

53

52

51

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
VSS
56

55

GPIO7/EPWM4B/ECAP2

GPIO19/SPISTEA
57

59

58

GPIO9

GPIO8/ADCSOCAO
VDD

61

62

60

GPIO10/ADCSOCBO
GPIO20VSS
64

63

XCLKOUT
VDDIO
66

65

VDD

GPIO21
67

69

68

GPIO22

GPIO11
VSS

71

72

70

TMS

50
49

GPIO16/SPISIMOA/TZ5
VSS

78

48

GPIO3/EPWM2B

79

47

EMU0

80

46

GPIO0/EPWM1A
VDDIO

EMU1
VDDIO

81

45

GPIO2/EPWM2A

82

44

GPIO1/EPWM1B

GPIO24/ECAP1

83

43

TRST
VDD

84

42

GPIO34
VDD

85

41

VSS

X2
VSS

86

40

VDD2A18

87

39

VSS2AGND

X1
VSS

88

38

ADCRESEXT

89

37

ADCREFPXCLKINGPIO25/ECAP290

36

ADCREFM

91

35

ADCREFIN

GPIO28/SCIRXDA/TZ5
VDD

92

34

ADCINB79333

ADCINB6

VSS

94

32

ADCINB5

GPIO13/TZ2

95

31

ADCINB4VDD3VFL
TEST1

96

30

ADCINB3

9729

ADCINB2

TEST2

98

28

ADCINB1

GPIO26

99

27

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

100

26

ADCINB0
VDDAIO24ADCLO
VSSAIO25

22

23

ADCINA1

ADCINA020

21
ADCINA219ADCINA4ADCINA31718

ADCINA6

16ADCINA7ADCINA5

14

15

VSSA2

VDDA2

12

13

VDD1A18

VSS1AGND

10

11
VSS

9

GPIO15/TZ4
VDD

7

8

(A)

GPIO31/CANTXAGPIO14/TZ3

6(A)

GPIO30/CANRXA

4

5

GPIO29/SCITXDA//TZ6

3
VDDIO

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

2

GPIO12/TZ1
VSS

77

1

A.

TDI
GPIO23XRS
GPIO27

73

76

TCK
TDO
VSS

75

JAJS280O – OCTOBER 2003 – REVISED MARCH 201974

www.ti.com

CANTXA (pin 7) and CANRXA (pin 6) pins are not applicable for the TMS320F28015.

Figure 4-4. TMS320F2801x 100-Pin PZ LQFP (Top View)

Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

Copyright © 2003–2019, Texas Instruments Incorporated

13

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

K

VSSAIOADCINB0

ADCINB3

ADCINB5ADCINB7

VSS2AGND

GPIO1

GPIO0

VSS

GPIO16JADCLO

VDDAIOADCINB1

ADCINB4

ADCREFIN

VDD2A18

GPIO2

GPIO3

GPIO4

GPIO17H

ADCINA1

ADCINA0

ADCINB2

ADCINB6

ADCREFM

VSS

VDDIO

GPIO18

GPIO5

VSS

G

ADCINA4ADCINA3ADCINA2

ADCINA5

ADCREFPVDD

GPIO34

GPIO7

GPIO6

GPIO19

F

VSSA2

VDDA2

ADCINA7ADCINA6

ADCRESEXTGPIO20

VSS

GPIO9

GPIO8

VDD

E

GPIO15VDD

VSS

VDD1A18

VSS1AGND

X1

GPIO21XCLKOUTVDDIOGPIO10D

GPIO31

GPIO30

GPIO14VDD

GPIO28VSS

VDD

GPIO22

GPIO11VSSC

GPIO33

VDDIO

GPIO29VDD3VFLGPIO25X2

GPIO24

GPIO27TDI

GPIO23B

VSS

GPIO12TEST2GPIO13XCLKIN

VDD

EMU1

XRS

TDO

TMS

A

GPIO32

GPIO26

TEST1

VSS

VSS

TRST

VDDIO

EMU0

VSS

TCK

1

2

3

4

5

6

7

8

9

10

Bottom View

Figure 4-5. TMS320F2809, TMS320F2808, TMS320F2806,TMS320F2802, TMS320F2801,
TMS320F28016, TMS320F28015, TMS320C2802, TMS320C2801
100-Ball GGM and ZGM MicroStar BGA™ (Bottom View)

14

Terminal Configuration and Functions

Copyright © 2003–2019, Texas Instruments Incorporated

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com

4.2

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Signal Descriptions
Table 4-1 describes the signals. All digital inputs are TTL-compatible. All outputs are 3.3 V with CMOS
levels. Inputs are not 5-V tolerant.
Table 4-1. Signal Descriptions
PIN NO.
NAME

PZ
PIN #

GGM/
ZGM
BALL #DESCRIPTION (1)

JTAG

TRST

84

A6

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of
the operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an active
high test pin and must be maintained low at all times during normal device operation. An external
pulldown resistor is required on this pin. The value of this resistor should be based on drive strengthof the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate
protection. Since this is application-specific, it is recommended that each target board be validated
for proper operation of the debugger and the application. (I, ↓)

TCK

75

A10

JTAG test clock with internal pullup (I, ↑)

TMS

74

B10

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
controller on the rising edge of TCK. (I, ↑)

TDI

73

C9

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction
or data) on a rising edge of TCK. (I, ↑)

TDO

76

B9

JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)
are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)

A8

Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put thedevice into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at alogic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
(I/O/Z, 8 mA drive ↑)NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should bebased on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.

B7

Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put thedevice into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at alogic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
(I/O/Z, 8 mA drive ↑)NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should bebased on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.

EMU0

EMU1

80

81

FLASH
VDD3VFL

96

C4

3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times. On the ROM
parts (C280x), this pin should be connected to VDDIO.

TEST1

97

A3

Test Pin. Reserved for TI. Must be left unconnected. (I/O)

TEST2

98

B3

Test Pin. Reserved for TI. Must be left unconnected. (I/O)
CLOCK

XCLKOUT

66

E8

Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half thefrequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0
(XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal
can be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is notplaced in high-impedance state during a reset. (O/Z, 8 mA drive).

XCLKIN90

B5

External Oscillator Input. This pin is used to feed a clock from an external 3.3-V oscillator. In thiscase, tie the X1 pin to GND. Alternately, when a crystal/resonator is used (or if an external 1.8-V
oscillator is fed into the X1 pin), tie the XCLKIN pin to GND. (I)(1)

I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown
Terminal Configuration and Functions
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Copyright © 2003–2019, Texas Instruments Incorporated

15

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

Table 4-1. Signal Descriptions (continued)
PIN NO.
NAME

PZ
PIN #

GGM/
ZGM
BALL #DESCRIPTION (1)

X1

88

E6

Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic
resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital
power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN
pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 mustbe tied to GND. (I)

X2

86

C6

Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 andX2. If X2 is not used it must be left unconnected. (O)B8

Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the addresscontained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at thelocation pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs.
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD, ↑)The output buffer of this pin is an open-drain with an internal pullup. If this pin is driven by an
external device, it should be done using an open-drain device.

RESET

XRS

78

ADC SIGNALSADCINA716F3

ADC Group A, Channel 7 input (I)

ADCINA617F4ADC Group A, Channel 6 input (I)

ADCINA518

G4ADC Group A, Channel 5 input (I)

ADCINA419G1

ADC Group A, Channel 4 input (I)

ADCINA320G2

ADC Group A, Channel 3 input (I)

ADCINA221

G3

ADC Group A, Channel 2 input (I)

ADCINA1

22

H1

ADC Group A, Channel 1 input (I)

ADCINA023

H2

ADC Group A, Channel 0 input (I)

ADCINB734K5ADC Group B, Channel 7 input (I)

ADCINB633

H4ADC Group B, Channel 6 input (I)

ADCINB532

K4ADC Group B, Channel 5 input (I)

ADCINB431

J4ADC Group B, Channel 4 input (I)

ADCINB330

K3ADC Group B, Channel 3 input (I)

ADCINB229

H3

ADC Group B, Channel 2 input (I)

ADCINB128J3ADC Group B, Channel 1 input (I)

ADCINB027

K2

ADC Group B, Channel 0 input (I)

ADCLO

24

J1

Low Reference (connect to analog ground) (I)

ADCRESEXT38

F5ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.

ADCREFIN

35

J5External reference input (I)G5Internal Reference Positive Output. Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of
2.2 μF to analog ground. (O)NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that isused in the system.

H5Internal Reference Medium Output. Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of
2.2 μF to analog ground. (O)NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that isused in the system.

ADCREFPADCREFM

16

37

36

Terminal Configuration and Functions

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Table 4-1. Signal Descriptions (continued)
PIN NO.
NAME

PZ
PIN #

GGM/
ZGM
BALL #DESCRIPTION (1)CPU AND I/O POWER PINS
VDDA2

15

F2

ADC Analog Power Pin (3.3 V)

VSSA2

14

F1

ADC Analog Ground Pin

VDDAIO26

J2

ADC Analog I/O Power Pin (3.3 V)

VSSAIO

25

K1

ADC Analog I/O Ground Pin

VDD1A1812E4ADC Analog Power Pin (1.8 V)

VSS1AGND

13

E5

ADC Analog Ground Pin

VDD2A1840J6ADC Analog Power Pin (1.8 V)

VSS2AGND

39

K6

ADC Analog Ground Pin

VDD

10

E2

VDD

42

G6

VDD

59

F10

VDD

68

D7

VDD

85

B6

VDD

93

D4

VDDIO

3

C2

VDDIO

46

H7

VDDIO

65

E9

VDDIO

82

A7

VSS

2

B1

VSS

11

E3

VSS

41

H6

VSS

49

K9

VSS

55

H10

VSS

62

F7

VSS

69

D10

VSS

77

A9

VSS

87

D6

VSS

89

A5

VSS

94

A4

CPU and Logic Digital Power Pins (1.8 V)

Digital I/O Power Pin (3.3 V)

Digital Ground Pins

GPIOA AND PERIPHERAL SIGNALS (2) (3)GPIO0
EPWM1AGPIO1
EPWM1BSPISIMODGPIO2
EPWM2A
(2)
(3)
(4)

47

44

45

K8

General-purpose input/output 0 (I/O/Z) (4)Enhanced PWM1 Output A and HRPWM channel (O)-K7

General-purpose input/output 1 (I/O/Z) (4)Enhanced PWM1 Output B (O)SPI-D slave in, master out (I/O) (not available on 2801, 2802)-

J7

General-purpose input/output 2 (I/O/Z) (4)Enhanced PWM2 Output A and HRPWM channel (O)-Some peripheral functions may not be available in TMS320F2801x devices. See Table 3-2 for details.
All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively
enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at
reset. The peripheral signals that are listed under them are alternate functions.
The pullups on GPIO0-GPIO11 pins are not enabled at reset.

Terminal Configuration and Functions
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Copyright © 2003–2019, Texas Instruments Incorporated

17

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

Table 4-1. Signal Descriptions (continued)
PIN NO.
NAME

GPIO3
EPWM2BSPISOMID
-

48

GPIO4
EPWM3A-51

GPIO5
EPWM3BSPICLKD
ECAP1

53

GPIO6
EPWM4AEPWMSYNCIEPWMSYNCO
GPIO7
EPWM4BSPISTED
ECAP2

GPIO9
EPWM5BSCITXDBECAP3

GPIO13TZ2CANRXBSPISOMIBGPIO14TZ3SCITXDBSPICLKB
GPIO15TZ4SCIRXDBSPISTEB
GPIO16SPISIMOACANTXB
TZ5
(5)

18

60

61

GPIO10EPWM6ACANRXB
ADCSOCBO

GPIO12TZ1CANTXBSPISIMOB

56

58

GPIO8
EPWM5ACANTXB
ADCSOCAO

GPIO11EPWM6BSCIRXDB
ECAP4

PZ
PIN #

64

70

1

95

8

9

50

GGM/
ZGM
BALL #DESCRIPTION (1)J8General-purpose input/output 3 (I/O/Z) (4)Enhanced PWM2 Output B (O)SPI-D slave out, master in (I/O) (not available on 2801, 2802)-

J9

General-purpose input/output 4 (I/O/Z) (4)Enhanced PWM3 output A and HRPWM channel (O)-H9General-purpose input/output 5 (I/O/Z) (4)Enhanced PWM3 output B (O)SPI-D clock (I/O) (not available on 2801, 2802)
Enhanced capture input/output 1 (I/O)

G9General-purpose input/output 6 (I/O/Z) (4)Enhanced PWM4 output A and HRPWM channel (O) (not available on 2801, 2802)
External ePWM sync pulse input (I)External ePWM sync pulse output (O)G8General-purpose input/output 7 (I/O/Z) (4)Enhanced PWM4 output B (O) (not available on 2801, 2802)
SPI-D slave transmit enable (I/O) (not available on 2801, 2802)
Enhanced capture input/output 2 (I/O)

F9General-purpose input/output 8 (I/O/Z) (4)Enhanced PWM5 output A and HRPWM channel (O) (not available on 2801, 2802)
Enhanced CAN-B transmit (O) (not available on 2801, 2802, F2806)
ADC start-of-conversion A (O)F8General-purpose input/output 9 (I/O/Z) (4)Enhanced PWM5 output B (O) (not available on 2801, 2802)
SCI-B transmit data (O) (not available on 2801, 2802)
Enhanced capture input/output 3 (I/O) (not available on 2801, 2802)

E10

General-purpose input/output 10 (I/O/Z) (4)Enhanced PWM6 output A and HRPWM channel (O) (not available on 2801, 2802)
Enhanced CAN-B receive (I) (not available on 2801, 2802, F2806)
ADC start-of-conversion B (O)D9General-purpose input/output 11 (I/O/Z) (4)Enhanced PWM6 output B (O) (not available on 2801, 2802)
SCI-B receive data (I) (not available on 2801, 2802)
Enhanced CAP Input/Output 4 (I/O) (not available on 2801, 2802)

B2

General-purpose input/output 12 (I/O/Z) (5)Trip Zone input 1 (I)Enhanced CAN-B transmit (O) (not available on 2801, 2802, F2806)
SPI-B Slave in, Master out (I/O)

B4

General-purpose input/output 13 (I/O/Z) (5)Trip zone input 2 (I)Enhanced CAN-B receive (I) (not available on 2801, 2802, F2806)
SPI-B slave out, master in (I/O)

D3

General-purpose input/output 14 (I/O/Z) (5)Trip zone input 3 (I)SCI-B transmit (O) (not available on 2801, 2802)
SPI-B clock input/output (I/O)

E1

General-purpose input/output 15 (I/O/Z) (5)Trip zone input 4 (I)SCI-B receive (I) (not available on 2801, 2802)
SPI-B slave transmit enable (I/O)

K10

General-purpose input/output 16 (I/O/Z) (5)SPI-A slave in, master out (I/O)
Enhanced CAN-B transmit (O) (not available on 2801, 2802, F2806)
Trip zone input 5 (I)The pullups on GPIO12-GPIO34 are enabled upon reset.

Terminal Configuration and Functions

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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www.ti.com

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Table 4-1. Signal Descriptions (continued)
PIN NO.
NAME

GPIO17SPISOMIACANRXB
TZ6
GPIO18SPICLKASCITXDB
GPIO19SPISTEASCIRXDBGPIO20
EQEP1ASPISIMOCCANTXBGPIO21
EQEP1BSPISOMICCANRXBGPIO22
EQEP1SSPICLKCSCITXDBGPIO23
EQEP1ISPISTECSCIRXDBGPIO24
ECAP1
EQEP2ASPISIMOBGPIO25
ECAP2
EQEP2BSPISOMIBGPIO26
ECAP3
EQEP2ISPICLKB
GPIO27
ECAP4
EQEP2SSPISTEB
GPIO28SCIRXDA
TZ5
GPIO29SCITXDA
TZ6

PZ
PIN #

52

54

57

63

67

71

72

83

91

99

79

92

4

GGM/
ZGM
BALL #DESCRIPTION (1)J10General-purpose input/output 17 (I/O/Z) (5)SPI-A slave out, master in (I/O)
Enhanced CAN-B receive (I) (not available on 2801, 2802, F2806)
Trip zone input 6 (I)H8General-purpose input/output 18 (I/O/Z) (5)SPI-A clock input/output (I/O)
SCI-B transmit (O) (not available on 2801, 2802)-

G10

General-purpose input/output 19 (I/O/Z) (5)SPI-A slave transmit enable input/output (I/O)
SCI-B receive (I) (not available on 2801, 2802)-

F6

General-purpose input/output 20 (I/O/Z) (5)Enhanced QEP1 input A (I)SPI-C slave in, master out (I/O) (not available on 2801, 2802)
Enhanced CAN-B transmit (O) (not available on 2801, 2802, F2806)

E7

General-purpose input/output 21 (I/O/Z) (5)Enhanced QEP1 input A (I)SPI-C master in, slave out (I/O) (not available on 2801, 2802)
Enhanced CAN-B receive (I) (not available on 2801, 2802, F2806)

D8

General-purpose input/output 22 (I/O/Z) (5)Enhanced QEP1 strobe (I/O)
SPI-C clock (I/O) (not available on 2801, 2802)
SCI-B transmit (O) (not available on 2801, 2802)

C10

General-purpose input/output 23 (I/O/Z) (5)Enhanced QEP1 index (I/O)
SPI-C slave transmit enable (I/O) (not available on 2801, 2802)
SCI-B receive (I) (not available on 2801, 2802)

C7

General-purpose input/output 24 (I/O/Z) (5)Enhanced capture 1 (I/O)
Enhanced QEP2 input A (I) (not available on 2801, 2802)
SPI-B slave in, master out (I/O)

C5General-purpose input/output 25 (I/O/Z) (5)Enhanced capture 2 (I/O)
Enhanced QEP2 input B (I) (not available on 2801, 2802)
SPI-B master in, slave out (I/O)

A2

General-purpose input/output 26 (I/O/Z) (5)Enhanced capture 3 (I/O) (not available on 2801, 2802)
Enhanced QEP2 index (I/O) (not available on 2801, 2802)
SPI-B clock (I/O)

C8General-purpose input/output 27 (I/O/Z) (5)Enhanced capture 4 (I/O) (not available on 2801, 2802)
Enhanced QEP2 strobe (I/O) (not available on 2801, 2802)
SPI-B slave transmit enable (I/O)

D5

General-purpose input/output 28. This pin has an 8-mA (typical) output buffer. (I/O/Z) (5)SCI receive data (I)Trip zone input 5 (I)C3General-purpose input/output 29. This pin has an 8-mA (typical) output buffer. (I/O/Z) (5)SCI transmit data (O)Trip zone 6 input (I)Terminal Configuration and Functions
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Copyright © 2003–2019, Texas Instruments Incorporated

19

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

Table 4-1. Signal Descriptions (continued)
PIN NO.
NAME

GPIO30CANRXA-

6

GPIO31CANTXA-

7

GPIO32SDAA
EPWMSYNCIADCSOCAO
GPIO33SCLAEPWMSYNCO
ADCSOCBO
GPIO34
-

PZ
PIN #

100

5

43

GGM/
ZGM
BALL #DESCRIPTION (1)D2

General-purpose input/output 30. This pin has an 8-mA (typical) output buffer. (I/O/Z) (5)Enhanced CAN-A receive data (I)-D1General-purpose input/output 31. This pin has an 8-mA (typical) output buffer. (I/O/Z) (5)Enhanced CAN-A transmit data (O)-A1General-purpose input/output 32 (I/O/Z) (5)I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)ADC start-of-conversion (O)C1General-Purpose Input/Output 33 (I/O/Z) (5)I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)ADC start-of-conversion (O)G7General-Purpose Input/Output 34 (I/O/Z) (5)-NOTE
Some peripheral functions may not be available in TMS320F2801x devices. See Table 3-2
for details.

20

Terminal Configuration and Functions

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

5 Specifications
This section provides the absolute maximum ratings and the recommended operating conditions.

5.1

Absolute Maximum Ratings (1) (2)Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges.
MIN

MAX

VDDIO, VDD3VFL with respect to VSS

–0.3

4.6

VDDA2, VDDAIO with respect to VSSA

–0.3

4.6

VDD with respect to VSS

–0.3

2.5

VDD1A18, VDD2A18 with respect to VSSA

–0.3

2.5

VSSA2, VSSAIO, VSS1AGND, VSS2AGND with respect
to VSS–0.3

0.3

Input voltage

VIN

–0.3

4.6

Output voltage

VO

–0.3

4.6

V

Input clamp current

IIK (VIN < 0 or VIN > VDDIO) (3)

–20

20

mA

Output clamp current

IOK (VO < 0 or VO > VDDIO)

–20

20

mA

Supply voltage

UNIT

V

V

(4)

–40

85

S version (GGM, ZGM, PZ) (4)

–40

125

Q version (PZ) (4)

–40

125

Junction temperature

TJ (4)

–40

150

°C

Storage temperature

Tstg (4)

–65

150

°C

A version (GGM, ZGM, PZ)
Operating ambient temperature, TA

(1)
(2)
(3)
(4)

°C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
Continuous clamp current per pin is ±2 mA. This includes the analog inputs which have an internal clamping circuit that clamps thevoltage to a diode drop above VDDA2 or below VSSA2.
Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see Semiconductor and IC package thermal metrics.

Specifications
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TMS320C2801 TMS320F28016 TMS320F28015

Copyright © 2003–2019, Texas Instruments Incorporated

21

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 20195.2

www.ti.com

ESD Ratings – Automotive
VALUE

UNIT

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801, TMS320F28016, andTMS320F28015 in 100-pin PZ package

V(ESD)(1)

Electrostatic discharge

Human body model (HBM), per AEC-Q100-002 (1)±2000

Charged device model (CDM),
per AEC-Q100-011

All pins±500

Corner pins on 100-pin PZ:
1, 25, 26, 50, 51, 75, 76, 100

±750

V

AEC-Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5.3

ESD Ratings – Commercial
VALUE

UNIT

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801, TMS320F28016, andTMS320F28015 in 100-ball ZGM package
V(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)±2000

Charged-device model (CDM), per JEDEC specification JESD22C101 (2)

±500

V

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801, TMS320F28016, andTMS320F28015 in 100-ball GGM package
V(ESD)
(1)
(2)

5.4

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)±2000

Charged-device model (CDM), per JEDEC specification JESD22C101 (2)

±500

V

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN

NOM

MAX

UNIT

Device supply voltage, I/O, VDDIO

3.14

3.3

3.47

V

Device supply voltage CPU, VDD

1.71

1.8

1.89

V

Supply ground, VSS, VSSIO

0V

ADC supply voltage (3.3 V), VDDA2, VDDAIO

3.14

3.3

3.47

V

ADC supply voltage (1.8 V), VDD1A18, VDD2A18

1.71

1.8

1.89

V

Flash supply voltage, VDD3VFL

3.14

3.3

3.47

V

Device clock frequency (system clock),
fSYSCLKOUT

100-MHz devices

2

100

MHz

60-MHz devices

2

60

MHz

High-level input voltage, VIH

All inputs except X1

2

VDDIO + 0.3

0.7 * VDD – 0.05

VDD

X1
Low-level input voltage, VIL

All inputs except X1

VSS – 0.3

X1

0.8

All I/Os except Group 2

Low-level output sink current,
VOL = VOL MAX, IOL

All I/Os except Group 2

4Group 2 (1)8Ambient temperature, TA

(1)

22

V

0.3 * VDD + 0.05

High-level output source current,
VOH = 2.4 V, IOHGroup 2

V

–4

(1)

mA

–8

A version–40

85

S version

–40

125

Q version(AEC-Q100
Qualification)

–40

125

mA
°C

Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, and EMU1

Specifications

Copyright © 2003–2019, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com

5.5

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Power Consumption Summary
Table 5-1. TMS320F2809, TMS320F2808 Current Consumption by Power-Supply Pins at 100-MHz
SYSCLKOUT
IDDIO (1)

IDD

MODE

TEST CONDITIONS

Operational(Flash)The following peripheral
clocks are enabled:•ePWM1/2/3/4/5/6•
eCAP1/2/3/4•
eQEP1/2•
eCAN-A•
SCI-A/B
•
SPI-A
•
ADC
•
I2C
All PWM pins are toggled
at 100 kHz.
All I/O pins are left
unconnected.
Data is continuouslytransmitted out of the
SCI-A, SCI-B, andeCAN-A ports. The
hardware multiplier is
exercised.
Code is running out offlash with 3 wait-states.
XCLKOUT is turned off.

195 mA

230 mA

IDLE

Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:•eCAN-A
•
SCI-A
•
SPI-A
•
I2C

75 mA

STANDBY

Flash is powered down.
Peripheral clocks are off.

6 mA

HALT

Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.

70 μA

(1)
(2)
(3)
(4)
(5)
(6)

TYP

(5)

IDDA18 (3)

TYP

MAX

15 mA

27 mA

35 mA

40 mA

30 mA

90 mA

500 μA

2 mA

2 μA

10 μA

12 mA

100 μA

500 μA

2 μA

60 μA

120 μA

2 μA

TYP

(5)

IDD3VFL (2)
(6)

MAX

(6)

MAX

(6)

IDDA33 (4)(5)

MAX (6)38 mA

1.5 mA

2 mA

5 μA

50 μA

15 μA

30 μA

10 μA

5 μA

50 μA

15 μA

30 μA

10 μA

5 μA

50 μA

15 μA

30 μA

TYP

(5)

MAX

(6)

TYP

IDDIO current is dependent on the electrical loading on the I/O pins.
The IDD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Table 5-39. If the user application
involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.
IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
IDDA33 includes current into VDDA2 and VDDAIO pins.
TYP numbers are applicable over room temperature and nominal voltage.
MAX numbers are at 125°C and MAX voltage.

NOTE
The peripheral - I/O multiplexing implemented in the 280x devices prevents all available
peripherals from being used at the same time. This is because more than one peripheral
function may share an I/O pin. It is, however, possible to turn on the clocks to all the
peripherals at the same time, although such a configuration is not useful. If this is done, thecurrent drawn by the device will be more than the numbers specified in the current
consumption tables.

Specifications
Submit Documentation Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

Copyright © 2003–2019, Texas Instruments Incorporated

23

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

Table 5-2. TMS320F2806 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUTIDDIO (1)IDD

IDD3VFL (2)IDDA18 (3)MODE

TEST CONDITIONS

Operational(Flash)The following peripheral
clocks are enabled:•ePWM1/2/3/4/5/6•
eCAP1/2/3/4•
eQEP1/2•
eCAN-A•
SCI-A/B
•
SPI-A
•
ADC
•
I2C
All PWM pins are toggled at
100 kHz.
All I/O pins are left
unconnected.
Data is continuouslytransmitted out of the SCIA, SCI-B, and eCAN-A
ports. The hardware
multiplier is exercised.
Code is running out of flash
with 3 wait-states.
XCLKOUT is turned off

195 mA

230 mA

15 mA

27 mA

35 mA

40 mA

30 mA

IDLE

Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:•eCAN-A
•
SCI-A
•
SPI-A
•
I2C

75 mA

90 mA

500 μA

2 mA

2 μA

10 μA

STANDBY

Flash is powered down.
Peripheral clocks are off.

6 mA

12 mA

100 μA

500 μA

2 μA

HALT

Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.

70 μA

60 μA

120 μA

2 μA

(1)
(2)
(3)
(4)
(5)
(6)

TYP

(5)

MAX

(6)

TYP

(5)

MAX

(6)

TYP

(5)

MAX (6)38 mA

1.5 mA

2 mA

5 μA

50 μA

15 μA

30 μA

10 μA

5 μA

50 μA

15 μA

30 μA

10 μA

5 μA

50 μA

15 μA

30 μA

TYP

(5)

IDDA33 (4)
(5)

MAX

(6)

MAX

(6)

TYP

IDDIO current is dependent on the electrical loading on the I/O pins.
The IDD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Table 5-39. If the user application
involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.
IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
IDDA33 includes current into VDDA2 and VDDAIO pins.
TYP numbers are applicable over room temperature and nominal voltage.
MAX numbers are at 125°C and MAX voltage.

NOTE
The peripheral - I/O multiplexing implemented in the 280x devices prevents all available
peripherals from being used at the same time. This is because more than one peripheral
function may share an I/O pin. It is, however, possible to turn on the clocks to all the
peripherals at the same time, although such a configuration is not useful. If this is done, thecurrent drawn by the device will be more than the numbers specified in the current
consumption tables.

24

Specifications

Copyright © 2003–2019, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Table 5-3. TMS320F2802, TMS320F2801 Current Consumption by Power-Supply Pins at 100-MHz
SYSCLKOUT
IDDIO (1)IDD

IDD3VFL (2)IDDA18 (3)IDDA33 (4)MODE

TEST CONDITIONSTYP (5)

MAX (6)

TYP (5)

MAX (6)

TYP (5)

MAX (6)

TYP (5)

MAX (6)

TYP (5)

MAX (6)

Operational(Flash)The following peripheral
clocks are enabled:•ePWM1/2/3•
eCAP1/2•
eQEP1•
eCAN-A
•
SCI-A
•
SPI-A
•
ADC
•
I2C
All PWM pins are toggled at
100 kHz.
All I/O pins are left
unconnected.
Data is continuouslytransmitted out of the SCI-A,
SCI-B, and eCAN-A ports.
The hardware multiplier is
exercised.
Code is running out of flash
with 3 wait-states.
XCLKOUT is turned off.

180 mA

210 mA

15 mA

27 mA

35 mA

40 mA

30 mA

38 mA

1.5 mA

2 mA

IDLE

Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:•eCAN-A
•
SCI-A
•
SPI-A
•
I2C

75 mA

90 mA

500 μA

2 mA

2 μA

10 μA

5 μA

50 μA

15 μA

30 μA

STANDBY

Flash is powered down.
Peripheral clocks are off.

6 mA

12 mA

100 μA

500 μA

2 μA

10 μA

5 μA

50 μA

15 μA

30 μA

HALT

Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.

70 μA

60 μA

120 μA

2 μA

10 μA

5 μA

50 μA

15 μA

30 μA

(1)
(2)
(3)
(4)
(5)
(6)

IDDIO current is dependent on the electrical loading on the I/O pins.
The IDD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Table 5-39. If the user application
involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.
IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
IDDA33 includes current into VDDA2 and VDDAIO pins.
TYP numbers are applicable over room temperature and nominal voltage.
MAX numbers are at 125°C and MAX voltage.

NOTE
The peripheral - I/O multiplexing implemented in the 280x devices prevents all available
peripherals from being used at the same time. This is because more than one peripheral
function may share an I/O pin. It is, however, possible to turn on the clocks to all the
peripherals at the same time, although such a configuration is not useful. If this is done, thecurrent drawn by the device will be more than the numbers specified in the current
consumption tables.

Specifications
Submit Documentation Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

Copyright © 2003–2019, Texas Instruments Incorporated25

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

Table 5-4. TMS320C2802, TMS320C2801 Current Consumption by Power-Supply Pins at
100-MHz SYSCLKOUT
MODE

TEST CONDITIONSIDDIO (1)IDD

IDDA18 (2)IDDA33 (3)TYP (4)

MAX (5)

TYP (4)

MAX (5)

TYP (4)

MAX (5)

TYP (4)

MAX (5)

Operational(ROM)

The following peripheral clocks
are enabled:•ePWM1/2/3•
eCAP1/2•
eQEP1•
eCAN-A
•
SCI-A
•
SPI-A
•
ADC
•
I2C
All PWM pins are toggled at
100 kHz.
All I/O pins are left unconnected.
Data is continuously transmitted
out of the SCI-A, SCI-B, andeCAN-A ports. The hardware
multiplier is exercised.
Code is running out of ROM with
3 wait-states.
XCLKOUT is turned off.

150 mA

165 mA

5 mA

10 mA

30 mA

38 mA

1.5 mA

2 mA

IDLE

XCLKOUT is turned off.
The following peripheral clocks
are enabled:•eCAN-A
•
SCI-A
•
SPI-A
•
I2C

75 mA

90 mA

500 μA

2 mA

5 μA

50 μA

15 μA

30 μA

STANDBY

Peripheral clocks are off.

6 mA

12 mA

100 μA

500 μA

5 μA

50 μA

15 μA

30 μA

HALT

Peripheral clocks are off.
Input clock is disabled.

70 μA

80 μA

120 μA

5 μA

50 μA

15 μA

30 μA

(1)
(2)
(3)
(4)
(5)

IDDIO current is dependent on the electrical loading on the I/O pins.
IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
IDDA33 includes current into VDDA2 and VDDAIO pins.
TYP numbers are applicable over room temperature and nominal voltage.
MAX numbers are at 125°C and MAX voltage.

NOTE
The peripheral - I/O multiplexing implemented in the 280x devices prevents all available
peripherals from being used at the same time. This is because more than one peripheral
function may share an I/O pin. It is, however, possible to turn on the clocks to all the
peripherals at the same time, although such a configuration is not useful. If this is done, thecurrent drawn by the device will be more than the numbers specified in the current
consumption tables.

26

Specifications

Copyright © 2003–2019, Texas Instruments Incorporated

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com

5.5.1

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Reducing Current Consumption
280x devices have a richer peripheral mix compared to the 281x family. While the McBSP has been
removed, the following new peripherals have been added on the 280x:• 3 SPI modules• 1 CAN module• 1 I2C module
The two event manager modules of the 281x have been enhanced and replaced with separate ePWM (6),eCAP (4) and eQEP (2) modules, providing tremendous flexibility in applications. Like 281x, 280x DSPs
incorporate a unique method to reduce the device current consumption. Since each peripheral unit has anindividual clock-enable bit, significant reduction in current consumption can be achieved by turning off theclock to any peripheral module that is not used in a given application. Furthermore, any one of the three
low-power modes could be taken advantage of to reduce the current consumption even further. Table 5-5
indicates the typical reduction in current consumption achieved by turning off the clocks.
Table 5-5. Typical Current Consumption by Various
Peripherals (at 100 MHz) (1)

(1)
(2)
(3)

PERIPHERALMODULEIDD CURRENT
REDUCTION (mA) (2)

ADC

8 (3)

I2C

5

eQEP

5

ePWM

5

eCAP

2

SCI

4

SPI

5

eCAN

11

All peripheral clocks are disabled upon reset. Writing to/reading fromperipheral registers is possible only after the peripheral clocks areturned on.
For peripherals with multiple instances, the current quoted is per
module. For example, the 5 mA number quoted for ePWM is for one
ePWM module.
This number represents the current drawn by the digital portion of
the ADC module. Turning off the clock to the ADC module results inthe elimination of the current drawn by the analog portion of the ADC(IDDA18) as well.

NOTE
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.

NOTE
The baseline IDD current (current when the core is executing a dummy loop with noperipherals enabled) is 110 mA, typical. To arrive at the IDD current for a given application,
the current-drawn by the peripherals (enabled by that application) must be added to thebaseline IDD current.

Specifications
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TMS320C2801 TMS320F28016 TMS320F28015

Copyright © 2003–2019, Texas Instruments Incorporated27

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

5.5.2

www.ti.com

Current Consumption Graphs
250.0

Current (mA)

200.0
150.0
100.0
50.0
0.0
10

20

30

40

50

60

70

80

90

100

SYSCLKOUT (MHz)IDD

IDDA18

1.8-V current

IDDIO

IDD3VFL

3.3-V current

Figure 5-1. Typical Operational Current Versus Frequency (F2808)
600.0
500.0

Device Power (mW)

400.0
300.0
200.0
100.0
0.0
10

20

30

40

50

60

70

80

90

100

SYSCLKOUT (MHz)TOTAL POWER

Figure 5-2. Typical Operational Power Versus Frequency (F2808)
NOTE
Typical operational current for 60-MHz devices can be estimated from Figure 5-1. For IDD
current alone, subtract the current contribution of non-existent peripherals after scaling theperipheral currents for 60 MHz. For example, to compute the current of F2801-60 device, thecontribution by the following peripherals must be subtracted from IDD: ePWM4/5/6, eCAP3/4,
eQEP2, SCI-B.

28

Specifications

Copyright © 2003–2019, Texas Instruments Incorporated

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Current Vs SYSCLKOUT
200
180

Current (mA)

160
140
120
100
80
60
40
20
0
10

20

30

40

50

60

70

80

90

10

SYSCLKOUT (MHz)IDD

IDDA181.8v current

IDDIO

IDD3VFL

3.3v current

Figure 5-3. Typical Operational Current Versus Frequency (C280x)

Device Power (mW)

Device Power Vs SYSCLKOUT
400.0
300.0
200.0
100.0
0.0
10

20

30

40

50

60

70

80

90

100

SYSCLKOUT (MHz)TOTAL POWER

Figure 5-4. Typical Operational Power Versus Frequency (C280x)

Specifications
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TMS320C2801 TMS320F28016 TMS320F28015

Copyright © 2003–2019, Texas Instruments Incorporated

29

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 20195.6

www.ti.com

Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER
VOH

High-level output voltage

VOL

Low-level output voltage

IIL

IIH

Input current(low level)

Input current(high level)

TEST CONDITIONSMINIOH = IOH MAX

TYP

MAX

2.4

IOH = 50 μA

V

VDDIO – 0.2

IOL = IOL MAX

0.4

Pin with pullup
enabledVDDIO = 3.3 V, VIN = 0 V

Pin with pulldown
enabledVDDIO = 3.3 V, VIN = 0 V±2

Pin with pullup
enabledVDDIO = 3.3 V, VIN = VDDIO±2

Pin with pulldown
enabledVDDIO = 3.3 V, VIN = VDDIO (F280x)

28

50

80

Pin with pulldown
enabledVDDIO = 3.3 V, VIN = VDDIO (C280x)

80

140

190

IOZ

Output current, pullup or
pulldown disabled

CI

Input capacitance

30

Specifications

All I/Os (including XRS)

–80

UNIT

–140

V

–190
μA

VO = VDDIO or 0 V

±2
2

μA

μA
pF

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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5.7

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Thermal Resistance Characteristics for F280x 100-Ball GGM Package°C/W (1)

AIR FLOW (lfm) (2)RΘJC

Junction-to-case thermal resistance

12.08

N/A

RΘJB

Junction-to-board thermal resistance

16.46

N/A

RΘJA
(High k PCB)

PsiJT

(1)

(2)

Junction-to-free air thermal resistanceJunction-to-package top

30.58

0

29.31

150

28.09

250

26.62

500

0.4184

0

0.32

150

0.3725250

0.4887500

These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute

5.8

Thermal Resistance Characteristics for F280x 100-Pin PZ Package°C/W (1)

AIR FLOW (lfm) (2)RΘJC

Junction-to-case thermal resistance

12.89

N/A

RΘJB

Junction-to-board thermal resistance

29.58

N/A

RΘJA
(High k PCB)

PsiJT

(1)

(2)

Junction-to-free air thermal resistanceJunction-to-package top

48.16

0

40.06

150

37.96

250

35.17

500

0.3425

0

0.85

150

1.0575

250

1.410

500

These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minuteSpecifications
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31

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 20195.9

www.ti.com

Thermal Resistance Characteristics for C280x 100-Ball GGM Package°C/W (1)

AIR FLOW (lfm) (2)RΘJC

Junction-to-case thermal resistance

14.18

N/A

RΘJB

Junction-to-board thermal resistance

21.36

N/A

RΘJA
(High k PCB)

PsiJT

(1)

(2)

Junction-to-free air thermal resistanceJunction-to-package top

36.33

0

35.01

150

33.81

250

32.31

500

0.57

0

0.43

150

0.52

250

0.67

500

These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute

5.10 Thermal Resistance Characteristics for C280x 100-Pin PZ Package°C/W (1)

AIR FLOW (lfm) (2)RΘJC

Junction-to-case thermal resistance

13.52

N/A

RΘJB

Junction-to-board thermal resistance

54.78

N/A

RΘJA
(High k PCB)

PsiJT

(1)

(2)

32

Junction-to-free air thermal resistanceJunction-to-package top

69.81

0

60.34

150

57.46

250

53.63

500

0.42

0

1.23

150

1.54

250

2.11

500

These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minuteSpecifications

Copyright © 2003–2019, Texas Instruments Incorporated

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com

JAJS280O – OCTOBER 2003 – REVISED MARCH 20195.11 Thermal Resistance Characteristics for F2809 100-Ball GGM Package
RΘJC

Junction-to-case thermal resistanceRΘJB

Junction-to-board thermal resistance

RΘJA(High k PCB)

PsiJT

(1)

(2)

Junction-to-free air thermal resistanceJunction-to-package top°C/W (1)

AIR FLOW (lfm) (2)

10.36

N/A

13.3

N/A

28.15

0

26.89

150

25.68

250

24.22

500

0.38

0

0.35

150

0.33

250

0.44

500

These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute

5.12 Thermal Resistance Characteristics for F2809 100-Pin PZ Package°C/W (1)

AIR FLOW (lfm) (2)RΘJC

Junction-to-case thermal resistance

7.06

N/A

RΘJB

Junction-to-board thermal resistance

28.76

N/A

RΘJA
(High k PCB)

PsiJT

(1)

(2)

Junction-to-free air thermal resistanceJunction-to-package top

44.02

0

28.34

150

36.28

250

33.68

500

0.2

0

0.56

150

0.7

250

0.95

500

These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute

5.13 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary.
Systems with more than 1 Watt power dissipation may require a product level thermal design. Care should
be taken to keep Tj within specified limits. In the end applications, Tcase should be measured to estimate
the operating junction temperature Tj. Tcase is normally measured at the center of the package top sidesurface. The thermal application note Semiconductor and IC package thermal metrics helps to understandthe thermal metrics and definitions.

Specifications
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Copyright © 2003–2019, Texas Instruments Incorporated

33

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

5.14 Timing and Switching Characteristics
5.14.1 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten thesymbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:

Letters and symbols and their
meanings:

aaccess time

H

High

c

cycle time (period)

L

Low

d

delay time

V

Valid

f

fall timeX

Unknown, changing, or don't care
level

h

hold time

Z

High impedancerrise timesu

setup timettransition timevvalid timew

pulse duration (width)

5.14.1.1 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
5.14.1.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.

Tester Pin Electronics

42 W

Data Sheet Timing Reference Point

3.5 nH

OutputUnder
Test

Transmission Line(A)

Z0 = 50 W
4.0 pF

A.
B.

Device Pin

1.85 pF(B)

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at thedevice pin.
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.

Figure 5-5. 3.3-V Test Load Circuit

34

Specifications

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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www.ti.com

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

5.14.1.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the 280x DSPs. Table 5-6 and Table 5-7 list the cycle times of various clocks.
Table 5-6. TMS320x280x Clock Table and Nomenclature (100-MHz Devices)
MIN
On-chip oscillator
clock
XCLKIN (1)SYSCLKOUTXCLKOUTHSPCLK (2)tc(OSC), Cycle time

ns
MHz

20

35

10

250

ns

Frequency

4

100

MHz

tc(SCO), Cycle time

10

500

ns
MHz

Frequency

2100

tc(XCO), Cycle time

10

2000

ns

Frequency

0.5

100

MHz

tc(HCO), Cycle time

10

100

MHz

20 (3)
50 (3)

10

Frequencytc(ADCCLK), Cycle time (All devices except F2809)

25

(3)

ns
100

MHz

12.5

MHz

80

ns

Frequency (All devices except F2809)
tc(ADCCLK), Cycle time (F2809)

ns

40 (3)

40ns

Frequency (F2809)
(1)
(2)
(3)

UNIT

50

tc(CI), Cycle timetc(LCO), Cycle time

ADC clockMAX

Frequency

Frequency

LSPCLK (2)

NOM

28.6

25

MHz

MAX

UNIT

This also applies to the X1 pin if a 1.8-V oscillator is used.
Lower LSPCLK and HSPCLK will reduce device power consumption.
This is the default reset value if SYSCLKOUT = 100 MHz.

Table 5-7. TMS320x280x/2801x Clock Table and Nomenclature (60-MHz Devices)
MIN
On-chip oscillator
clock

Frequency

SYSCLKOUT

Frequency
Frequency

HSPCLK (2)

(1)
(2)
(3)

tc(SCO), Cycle timetc(XCO), Cycle timeXCLKOUTADC clock

Frequencytc(CI), Cycle time

XCLKIN (1)LSPCLK (2)tc(OSC), Cycle timetc(HCO), Cycle time

28.6

50

ns

20

35

MHz

16.67

250

ns

4

60

MHz

16.67

500

ns

2

60

MHz

16.67

2000

ns

60

MHz

60

MHz

60

MHz

7.5

MHz

0.5
16.67
16.67

Frequency

ns

66.7 (3)
15 (3)

Frequencytc(ADCCLK), Cycle time

33.3 (3)30 (3)

Frequencytc(LCO), Cycle time

NOM

ns

133.33ns

This also applies to the X1 pin if a 1.8-V oscillator is used.
Lower LSPCLK and HSPCLK will reduce device power consumption.
This is the default reset value if SYSCLKOUT = 60 MHz.

Specifications
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

5.14.2 Power Sequencing
No requirements are placed on the power up/down sequence of the various power pins to ensure thecorrect reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffersof the I/O pins are powered prior to the 1.8-V transistors, it is possible for the output buffers to turn on,
causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD (core voltage)pins prior to or simultaneously with the VDDIO (input/output voltage) pins, ensuring that the VDD pins havereached 0.7 V before the VDDIO pins reach 0.7 V.
There are some requirements on the XRS pin:
1. During power up, the XRS pin must be held low for tw(RSL1) after the input clock is stable (see Table 58). This is to enable the entire device to start from a known condition.
2. During power down, the XRS pin must be pulled low at least 8 μs prior to VDD reaching 1.5 V. This is toenhance flash reliability.
No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin (for analog
pins, it is 0.7 V above VDDA) prior to powering up the device. Voltages applied to pins on an unpowered
device can bias internal p-n junctions in unintended ways and produce unpredictable results.

36

Specifications

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

VDDIO, VDD3VFL
VDDA2, VDDAIO(3.3 V)
VDD, VDD1A18,
VDD2A18(1.8 V)XCLKIN

X1/X2

OSCCLK/8(A)XCLKOUT

User-Code DependenttOSCST

tw(RSL1)

XRS
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/Data/
Control(Internal)td(EX)th(boot-mode)(B)

Boot-Mode
Pins

User-Code Execution Phase
User-Code Dependent

GPIO Pins as Input
Peripheral/GPIO Function
Based on Boot CodeBoot-ROM Execution Starts
I/O Pins(C)GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent

A.

B.

C.

Upon power up, SYSCLKOUT is OSCCLK/2. Since the XCLKOUTDIV bits in the XCLK register come up with a reset
state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT =OSCCLK/8 during this phase.
After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (indebugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.
See Section 5.14.2 for requirements to ensure a high-impedance state for GPIO pins during power-up.

Figure 5-6. Power-on Reset

Specifications
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Copyright © 2003–2019, Texas Instruments Incorporated37

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

Table 5-8. Reset (XRS) Timing Requirements
MIN

NOM

MAX

UNIT

tw(RSL1) (1)Pulse duration, stable XCLKIN to XRS hightw(RSL2)

Pulse duration, XRS lowtw(WDRS)

Pulse duration, reset pulse generated bywatchdog

512tc(OSCCLK)

cyclestd(EX)

Delay time, address/data valid after XRS high32tc(OSCCLK)

cyclestOSCST(2)

cycles8tc(OSCCLK)

cyclesOscillator start-up timeth(boot-mode)(1)(2)

Warm reset

8tc(OSCCLK)

1

Hold time for boot-mode pins

10200tc(OSCCLK)

ms
cyclesIn addition to the tw(RSL1) requirement, XRS has to be low at least for 1 ms after VDD reaches 1.5 V.
Dependent on crystal/resonator and board design.
XCLKIN

X1/X2

OSCCLK/8

XCLKOUT

User-Code Dependent

OSCCLK * 5
tw(RSL2)
XRS
Address/Data/
Control(Internal)td(EX)
User-Code Execution(Don’t Care)

Boot-ROM Execution Starts
Boot-Mode
Pins

Peripheral/GPIO Function

User-Code Execution Phase

GPIO Pins as Inputth(boot-mode)(A)Peripheral/GPIO Function
User-Code Execution Starts

I/O Pins

User-Code Dependent

GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code DependentA.

After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (indebugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.

Figure 5-7. Warm Reset

38

Specifications

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Figure 5-8 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the
PLL lock-up is complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating
frequency, OSCCLK x 4.
OSCCLK
Write to PLLCRSYSCLKOUTOSCCLK * 2

OSCCLK/2

OSCCLK * 4(Current CPU
Frequency)(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period(PLL Lock-up Time, tp) is131072 OSCCLK Cycles Long.)(Changed CPU Frequency)

Figure 5-8. Example of Effect of Writing Into PLLCR Register

Specifications
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39

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

5.14.3 Clock Requirements and Characteristics
Table 5-9. Input Clock Frequency
PARAMETER

fx

Input clock frequency

MIN

MAX UNIT

20

Crystal (X1/X2)

20

35

100-MHz device

4100

60-MHz device

4

External oscillator/clock
source (XCLKIN or X1 pin)fl

TYP

Resonator (X1/X2)

Limp mode SYSCLKOUT frequency range (with /2 enabled)

35
MHz

60
1–5

MHz

Table 5-10. XCLKIN (1) Timing Requirements - PLL Enabled
NO.

MIN

MAX

UNIT

33.3

C8

tc(CI)

Cycle time, XCLKIN

200

ns

C9

tf(CI)

Fall time, XCLKIN

6

ns

C10

tr(CI)

Rise time, XCLKIN

6

ns

C11

tw(CIL)

Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)

45%

55%

C12

tw(CIH)

Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)

45%

55%

(1)

This applies to the X1 pin also.

Table 5-11. XCLKIN (1) Timing Requirements - PLL DisabledNO.
C8tc(CI)

Cycle time, XCLKIN

C9tf(CI)

Fall time, XCLKIN

MIN

MAX

100-MHz device

10

250

60-MHz device

16.67

250

ns

Up to 20 MHz

6ns

20 MHz to 100 MHz

2ns

Up to 20 MHz

6

ns

2

ns

C10

tr(CI)

Rise time, XCLKIN

C11tw(CIL)

Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)

45%

55%

C12

tw(CIH)

Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)

45%

55%

(1)

UNIT

20 MHz to 100 MHz

This applies to the X1 pin also.

The possible configuration modes are shown in Table 6-33.
Table 5-12. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2)
NO.

(1)
(2)
(3)

40

PARAMETER

MIN
100-MHz device

1060-MHz device

16.67

TYP

C1

tc(XCO)

Cycle time, XCLKOUT

C3

tf(XCO)

Fall time, XCLKOUT

2

C4

tr(XCO)

Rise time, XCLKOUT

2

C5

tw(XCOL)

Pulse duration, XCLKOUT low

H–2

C6

tw(XCOH)

Pulse duration, XCLKOUT high

H–2

tp

PLL lock time

MAX

UNIT
ns
ns
ns

H+2
H+2
131072tc(OSCCLK) (3)nsns
cycles

A load of 40 pF is assumed for these parameters.
H = 0.5tc(XCO)
OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.

Specifications

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

C10
C9

C8
XCLKIN(A)

C1

C6

C3
C4

C5

XCLKOUT(B)A.
B.

The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown isintended to illustrate the timing parameters only and may differ based on actual configuration.
XCLKOUT configured to reflect SYSCLKOUT.

Figure 5-9. Clock Timing

Specifications
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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5.14.4 Peripherals
5.14.4.1 General-Purpose Input/Output (GPIO)
5.14.4.1.1

GPIO - Output Timing
Table 5-13. General-Purpose Output Switching Characteristics
MAX

UNIT

tr(GPO)

Rise time, GPIO switching low to high

PARAMETERAll GPIOs

MIN

8

ns

tf(GPO)

Fall time, GPIO switching high to low

All GPIOs

8

ns

tfGPO

Toggling frequency, GPO pins

25

MHz

GPIO
tr(GPO)tf(GPO)

Figure 5-10. General-Purpose Output Timing
5.14.4.1.2

GPIO - Input Timing
Table 5-14. General-Purpose Input Timing Requirements
MIN

tw(SP)

Sampling periodtw(IQSW)

Input qualifier sampling window

tw(GPI) (2)
(1)
(2)

42

Pulse duration, GPIO low/high

MAX

UNIT

QUALPRD = 0

1tc(SCO)cyclesQUALPRD ≠ 0

2tc(SCO) * QUALPRD

cyclestw(SP) * (n (1) – 1)

cyclesSynchronous mode

2tc(SCO)cyclesWith input qualifiertw(IQSW) + tw(SP) + 1tc(SCO)

cycles"n" represents the number of qualification samples as defined by GPxQSELn register.
For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.

Specifications

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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

(A)

GPIO Signal

GPxQSELn = 1,0 (6 samples)

1

1

0

0

0

0

0

0

0

1

tw(SP)

0

0

0

1

1

1

1

1

1

1

1

1

Sampling Period determinedby GPxCTRL[QUALPRD](B)tw(IQSW)(SYSCLKOUT cycle * 2 * QUALPRD) * 5(C))

Sampling Window
SYSCLKOUTQUALPRD = 1(SYSCLKOUT/2)(D)

Output From
Qualifier
A.

B.
C.
D.

This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value"n", the qualification sampling period in 2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO
pin will be sampled).
The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode isused.
In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles orgreater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure
5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide
pulse ensures reliable recognition.

Figure 5-11. Sampling Mode

Specifications
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5.14.4.1.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity ofthe signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0
SYSCLK

GPIOxntw(GPI)

Figure 5-12. General-Purpose Input Timing
NOTE
The pulse-width requirement for general-purpose input is applicable for the XINT2_ADCSOC
signal as well.

44

Specifications

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5.14.4.1.4 Low-Power Mode Wakeup Timing
Table 5-15 shows the timing requirements, Table 5-16 shows the switching characteristics, and Figure 513 shows the timing diagram for IDLE mode.
Table 5-15. IDLE Mode Timing Requirements (1)MIN
tw(WAKE-INT)(1)

Pulse duration, external wake-up signal

Without input qualifierMAX

2tc(SCO)With input qualifier

UNIT
cycles5tc(SCO) + tw(IQSW)

For an explanation of the input qualifier parameters, see Table 5-14.

Table 5-16. IDLE Mode Switching Characteristics (1)PARAMETERTEST CONDITIONS

MIN

MAX

UNIT

Delay time, external wake signal to program
execution resume (2)•td(WAKE-IDLE)••

Wake-up from Flash– Flash module in active state

Without input qualifier

Wake-up from Flash– Flash module in sleep state

Without input qualifier

Wake-up from SARAM

Without input qualifier

With input qualifier
With input qualifier
With input qualifier

(1)
(2)

20tc(SCO)
20tc(SCO) + tw(IQSW)
1050tc(SCO)
1050tc(SCO) + tw(IQSW)
20tc(SCO)
20tc(SCO) + tw(IQSW)

cyclescyclescyclesFor an explanation of the input qualifier parameters, see Table 5-14.
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggeredby the wake up) signal involves additional latency.
td(WAKE−IDLE)

Address/Data(internal)
XCLKOUT
tw(WAKE−INT)WAKE INT(A)A.

WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.

Figure 5-13. IDLE Entry and Exit Timing

Specifications
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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Table 5-17. STANDBY Mode Timing Requirements
TEST CONDITIONS
tw(WAKE-INT)(1)

Pulse duration, external
wake-up signal

MIN

Without input qualification

3tc(OSCCLK)With input qualification (1)(2 + QUALSTDBY) * tc(OSCCLK)

MAX

UNIT
cyclesQUALSTDBY is a 6-bit field in the LPMCR0 register.

Table 5-18. STANDBY Mode Switching Characteristics
PARAMETER
td(IDLE-XCOL)TEST CONDITIONSDelay time, IDLE instruction
executed to XCLKOUT low

MIN

MAX

UNIT

32tc(SCO)

45tc(SCO)

cyclesDelay time, external wake signal toprogram execution resume (1)•td(WAKE-STBY)•

Without input qualifier
Wake up from flash– Flash module in active state With input qualifier
Wake up from flash– Flash module in sleep state

100tc(SCO)
100tc(SCO) + tw(WAKE-INT)

Without input qualifier

1125tc(SCO)

With input qualifier

1125tc(SCO) + tw(WAKE-INT)

Without input qualifier•(1)

Wake up from SARAM

100tc(SCO)

With input qualifier

100tc(SCO) + tw(WAKE-INT)

cyclescyclescyclesThis is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggeredby the wake up signal) involves additional latency.
(A)

(C)
(B)

DeviceStatusSTANDBY

(E)
(D)

(F)

STANDBY

Normal Execution

Flushing Pipeline
Wake−up
Signaltw(WAKE-INT)
td(WAKE-STBY)X1/X2 or
X1 or
XCLKINXCLKOUT
td(IDLE−XCOL)
A.
B.

C.
D.
E.
F.

IDLE instruction is executed to put the device into STANDBY mode.
The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles (if CLKINDIV = 0)
or 64 cycles (if CLKINDIV = 1) before being turned off. This delay enables the CPU pipe and any other pending
operations to flush properly.
Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
The external wake-up signal is driven active.
After a latency period, the STANDBY mode is exited.
Normal execution resumes. The device will respond to the interrupt (if enabled).

Figure 5-14. STANDBY Entry and Exit Timing Diagram

46

Specifications

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Table 5-19. HALT Mode Timing Requirements
MIN

MAX

UNIT

tw(WAKE-GPIO)

Pulse duration, GPIO wake-up signal

toscst + 2tc(OSCCLK) (1)cyclestw(WAKE-XRS)

Pulse duration, XRS wakeup signal

toscst + 8tc(OSCCLK)

cycles

(1)

See Table 5-8 for an explanation of toscst.

Table 5-20. HALT Mode Switching Characteristics
PARAMETER
td(IDLE-XCOL)Delay time, IDLE instruction executed to XCLKOUT low

tp

PLL lock-up timetd(WAKE-HALT)

Delay time, PLL lock to program execution resume•
Wake up from flash– Flash module in sleep state
•

MIN

MAX

UNIT

32tc(SCO)

45tc(SCO)

cycles131072tc(OSCCLK)

cycles1125tc(SCO)

cycles35tc(SCO)

cyclesWake up from SARAM

(A)

(C)

DeviceStatus(D)
HALT

Flushing Pipeline

(G)

(E)

(B)

(F)

HALT
PLL Lock-up Time
Wake-up Latency

NormalExecution

GPIOn
td(WAKE−HALT)
tw(WAKE-GPIO)

tp

X1/X2
or XCLKIN
Oscillator Start-up TimeXCLKOUT
td(IDLE−XCOL)
A.
B.

C.

D.

E.

F.
G.

IDLE instruction is executed to put the device into HALT mode.
The PLL block responds to the HALT signal. SYSCLKOUT is held for approximately 32 cycles (if CLKINDIV = 0) or
64 cycles (if CLKINDIV = 1) before the oscillator is turned off and the CLKIN to the core is stopped. This delay
enables the CPU pipe and any other pending operations to flush properly.
Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power.
When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator
wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This
enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin
asynchronously begins the wakeup process, care should be taken to maintain a low noise environment prior toentering and during HALT mode.
Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 131,072 OSCCLK (X1/X2 or X1 or
XCLKIN) cycles. Note that these 131,072 clock cycles are applicable even when the PLL is disabled (that is, code
execution will be delayed by this duration even when the PLL is disabled).
Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to theinterrupt (if enabled), after a latency.
Normal operation resumes.

Figure 5-15. HALT Wake-Up Using GPIOn

Specifications
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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5.14.4.2 Enhanced Control Peripherals
5.14.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
PWM refers to PWM outputs on ePWM1–6. Table 5-21 shows the PWM timing requirements and Table 522, switching characteristics.
Table 5-21. ePWM Timing Requirements (1)TEST CONDITIONStw(SYCIN)

Sync input pulse width

MAX

UNIT

Asynchronous

2tc(SCO)cyclesSynchronous

2tc(SCO)cycles1tc(SCO) + tw(IQSW)

cyclesWith input qualifier
(1)

MIN

For an explanation of the input qualifier parameters, see Table 5-14.

Table 5-22. ePWM Switching Characteristics
PARAMETER
tw(PWM)

Pulse duration, PWMx output high/lowtw(SYNCOUT)

Sync output pulse widthtd(PWM)tza

Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced lowtd(TZ-PWM)HZ

Delay time, trip input active to PWM Hi-Z

TEST CONDITIONS

MIN

MAX

20

UNIT
ns

8tc(SCO)cyclesno pin load

25

ns

20

ns

5.14.4.2.2 Trip-Zone Input Timing
Table 5-23. Trip-Zone input Timing Requirements (1)MIN
Asynchronous
tw(TZ)

Pulse duration, TZx input low

(1)

UNIT
cycles2tc(SCO)cycles1tc(SCO) + tw(IQSW)

cyclesSynchronous
With input qualifierMAX

1tc(SCO)For an explanation of the input qualifier parameters, see Table 5-14.

SYSCLK

tw(TZ)(A)

TZ

td(TZ-PWM)HZ
(B)

PWM

A.
B.

TZ: TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.

Figure 5-16. PWM Hi-Z Characteristics

48

Specifications

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5.14.4.2.3 High-Resolution PWM Timing
Table 5-24 shows the high-resolution PWM switching characteristics.
Table 5-24. High-Resolution PWM Characteristics at SYSCLKOUT = 60–100 MHz
MIN

TYP

MAX

UNIT

150

310

ps

Micro Edge Positioning (MEP) step size (1)(1)

The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.

5.14.4.2.4 Enhanced Capture (eCAP) Timing
Table 5-25 shows the eCAP timing requirement and Table 5-26 shows the eCAP switching characteristics.
Table 5-25. Enhanced Capture (eCAP) Timing Requirement (1)TEST CONDITIONSMINAsynchronous
tw(CAP)

Capture input pulse width

UNIT

2tc(SCO)

Synchronous

2tc(SCO)With input qualifier
(1)

MAX

cycles1tc(SCO) + tw(IQSW)

For an explanation of the input qualifier parameters, see Table 5-14.

Table 5-26. eCAP Switching Characteristics
PARAMETER
tw(APWM)TEST CONDITIONS

MIN

Pulse duration, APWMx output high/low

MAX

UNIT

20

ns

5.14.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
Table 5-27 shows the eQEP timing requirement and Table 5-28 shows the eQEP switching
characteristics.
Table 5-27. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements (1)TEST CONDITIONS
tw(QEPP)QEP input period

tw(INDEXH)QEP Index Input High timetw(INDEXL)QEP Index Input Low timetw(STROBH)QEP Strobe High timetw(STROBL)QEP Strobe Input Low time

(1)
(2)

MIN

Asynchronous (2)/synchronous
With input qualifierMAX

2tc(SCO)cycles2[1tc(SCO) + tw(IQSW)]Asynchronous (2)/synchronous

2tc(SCO)With input qualifier

cycles2tc(SCO) +tw(IQSW)Asynchronous (2)/synchronous
With input qualifier2tc(SCO)cycles2tc(SCO) + tw(IQSW)Asynchronous (2)/synchronous
With input qualifier2tc(SCO)cycles2tc(SCO) + tw(IQSW)Asynchronous (2)/synchronous
With input qualifier

UNIT

2tc(SCO)cycles2tc(SCO) +tw(IQSW)

For an explanation of the input qualifier parameters, see Table 5-14.
Refer to the TMS320F280x, TMS320C280x, TMS320F2801x DSPs silicon errata for limitations in the asynchronous mode.

Table 5-28. eQEP Switching Characteristics
MAX

UNIT

td(CNTR)xin

Delay time, external clock to counter increment

PARAMETERTEST CONDITIONS

MIN

4tc(SCO)cyclestd(PCS-OUT)QEP

Delay time, QEP input edge to position compare sync output

6tc(SCO)cyclesSpecifications
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5.14.4.2.6 ADC Start-of-Conversion Timing
Table 5-29. External ADC Start-of-Conversion Switching Characteristics
PARAMETER
tw(ADCSOCAL)

MIN

Pulse duration, ADCSOCAO low

MAX

32tc(HCO )UNIT
cyclestw(ADCSOCAL)ADCSOCAOorADCSOCBO

Figure 5-17. ADCSOCAO or ADCSOCBO Timing
5.14.4.3 External Interrupt Timing
Table 5-30. External Interrupt Timing Requirements (1)MIN
tw(INT) (2)(1)(2)

Pulse duration, INT input low/highSynchronous

1tc(SCO)With qualifier

1tc(SCO) + tw(IQSW)

MAX

UNIT
cyclesFor an explanation of the input qualifier parameters, see Table 5-14.
This timing is applicable to any GPIO pin configured for ADCSOC functionality.

Table 5-31. External Interrupt Switching Characteristics (1)PARAMETER
td(INT)(1)

MIN

Delay time, INT low/high to interrupt-vector fetch

MAX

UNIT

tw(IQSW) + 12tc(SCO)

cyclesFor an explanation of the input qualifier parameters, see Table 5-14.
tw(INT)
XNMI, XINT1, XINT2
td(INT)
Address bus(internal)

Interrupt Vector

Figure 5-18. External Interrupt Timing

50

Specifications

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5.14.4.4 I2C Electrical Specification and Timing
Table 5-32. I2C Timing
TEST CONDITIONSMIN

I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler andclock divider registers are configured
appropriately

MAX

UNIT

400

kHz

0.3 VDDIOVfSCL

SCL clock frequency

Vil

Low level input voltage

VihHigh level input voltage

0.7 VDDIOV

Vhys

Input hysteresis

0.05 VDDIOV

Vol

Low level output voltage

3 mA sink current

tLOW

Low period of SCL clock

I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler andclock divider registers are configured
appropriately

1.3

μs

tHIGH

High period of SCL clock

I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler andclock divider registers are configured
appropriately

0.6

μs

lI

Input current with an input voltage
between 0.1 VDDIO and 0.9 VDDIO MAX

0

–10

0.4

10

Specifications
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V

μA

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5.14.4.5 Serial Peripheral Interface (SPI) TimingThis section contains both Master Mode and Slave Mode timing data.
5.14.4.5.1 SPI Master Mode Timing
Table 5-33 lists the master mode timing (clock phase = 0) and Table 5-34 lists the master mode timing(clock phase = 1). Figure 5-19 and Figure 5-20 show the timing waveforms.
Table 5-33. SPI Master Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5)
NO.
1

(1)
(2)
(3)
(4)
(5)

52

PARAMETER

BRR EVENBRR ODD

MIN

MAX

4tc(LSPCLK)

UNIT

MIN

MAX

128tc(LSPCLK)

5tc(LSPCLK)

127tc(LSPCLK)

ns

0.5tc(SPC)M +0.5tc(LSPCLK) + 10

ns

0.5tc(SPC)M –0.5tc(LSPCLK) + 10

ns

10

ns

tc(SPC)M

Cycle time, SPICLK

2

tw(SPC1)M

Pulse duration, SPICLK first
pulse

0.5tc(SPC)M – 10

0.5tc(SPC)M + 10

0.5tc(SPC)M +0.5tc(LSPCLK) – 10

3

tw(SPC2)M

Pulse duration, SPICLK second
pulse

0.5tc(SPC)M – 10

0.5tc(SPC)M + 10

0.5tc(SPC)M –0.5tc(LSPCLK) – 10

4td(SIMO)M

Delay time, SPICLK to
SPISIMO valid

5

tv(SIMO)M

Valid time, SPISIMO valid after
SPICLK

8

tsu(SOMI)M

9

10
0.5tc(SPC)M – 10

0.5tc(SPC)M –0.5tc(LSPCLK) – 10

ns

Setup time, SPISOMI before
SPICLK

35

35

nsth(SOMI)M

Hold time, SPISOMI valid after
SPICLK

0

0

ns

23

td(SPC)M

Delay time, SPISTE active to
SPICLK

1.5tc(SPC)M –3tc(SYSCLK) – 10

1.5tc(SPC)M –3tc(SYSCLK) – 10

ns

24

td(STE)M

Delay time, SPICLK to SPISTE
inactive

0.5tc(SPC)M – 10

0.5tc(SPC)M –0.5tc(LSPCLK) – 10ns

The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
tc(LCO) = LSPCLK cycle time
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).

Specifications

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

1
SPICLK(clock polarity = 0)2
3
SPICLK(clock polarity = 1)
4
5
SPISIMO

Master Out Data Is Valid89Master In Data
Must Be Valid

SPISOMI

23

24

SPISTE

Figure 5-19. SPI Master Mode External Timing (Clock Phase = 0)

Specifications
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Copyright © 2003–2019, Texas Instruments Incorporated53

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

Table 5-34. SPI Master Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) (5)
NO.
1

(1)
(2)
(3)
(4)
(5)

BRR EVEN

PARAMETERBRR ODD

MIN

MAX

4tc(LSPCLK)

UNIT

MIN

MAX

128tc(LSPCLK)

5tc(LSPCLK)

127tc(LSPCLK)

ns

0.5tc(SPC)M –0.5tc(LSPCLK) + 10

ns

0.5tc(SPC)M +0.5tc(LSPCLK) + 10

nstc(SPC)M

Cycle time, SPICLK

2

tw(SPC1)M

Pulse duration, SPICLK first
pulse

0.5tc(SPC)M – 10

0.5tc(SPC)M + 10

0.5tc(SPC)M –0.5tc(LSPCLK) – 10

3

tw(SPC2)M

Pulse duration, SPICLK second
pulse

0.5tc(SPC)M – 10

0.5tc(SPC)M + 10

0.5tc(SPC)M +0.5tc(LSPCLK) – 10

6td(SIMO)M

Delay time, SPISIMO valid to
SPICLK

0.5tc(SPC)M – 10

0.5tc(SPC)M +0.5tc(LSPCLK) – 10ns7tv(SIMO)M

Valid time, SPISIMO valid after
SPICLK

0.5tc(SPC)M – 10

0.5tc(SPC)M –0.5tc(LSPCLK) – 10ns

10

tsu(SOMI)M

Setup time, SPISOMI before
SPICLK

35

35

ns

11

th(SOMI)M

Hold time, SPISOMI valid after
SPICLK

0

0

ns

23

td(SPC)M

Delay time, SPISTE active to
SPICLK

2tc(SPC)M –3tc(SYSCLK) – 10

2tc(SPC)M –3tc(SYSCLK) – 10

ns

24

td(STE)M

Delay time, SPICLK to SPISTE
inactive

0.5tc(SPC) – 10

0.5tc(SPC) –0.5tc(LSPCLK) – 10ns

The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
1

SPICLK(clock polarity = 0)2
3
SPICLK(clock polarity = 1)
67
Master Out Data Is ValidSPISIMO

10
11
Master In Data Must
Be Valid

SPISOMI

24

23
SPISTE

Figure 5-20. SPI Master Mode External Timing (Clock Phase = 1)

54

Specifications

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

5.14.4.5.2 SPI Slave Mode Timing
Table 5-35 lists the slave mode timing (clock phase = 0) and Table 5-36 lists the slave mode timing (clockphase = 1). Figure 5-21 and Figure 5-22 show the timing waveforms.
Table 5-35. SPI Slave Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5)NO.

PARAMETER

MIN

12tc(SPC)SCycle time, SPICLK

13

tw(SPC1)S

14

tw(SPC2)S15

td(SOMI)S

Delay time, SPICLK to SPISOMI valid

16

tv(SOMI)S

Valid time, SPISOMI data valid after SPICLK

19

tsu(SIMO)S

20

th(SIMO)S

25
26
(1)
(2)
(3)
(4)
(5)

MAX

UNIT

4tc(SYSCLK)

ns

Pulse duration, SPICLK first pulse

2tc(SYSCLK) – 1

ns

Pulse duration, SPICLK second pulse

2tc(SYSCLK) – 1

ns
35

ns

0

ns

Setup time, SPISIMO valid before SPICLK

1.5tc(SYSCLK)

ns

Hold time, SPISIMO data valid after SPICLK

1.5tc(SYSCLK)

nstsu(STE)S

Setup time, SPISTE active before SPICLK

1.5tc(SYSCLK)

nsth(STE)S

Hold time, SPISTE inactive after SPICLK

1.5tc(SYSCLK)ns

The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK(clock polarity = 0)13
14
SPICLK(clock polarity = 1)
15

SPISOMI

16

SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be ValidSPISIMO
25

26

SPISTE

Figure 5-21. SPI Slave Mode External Timing (Clock Phase = 0)

Specifications
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Copyright © 2003–2019, Texas Instruments Incorporated55

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

Table 5-36. SPI Slave Mode External Timing (Clock Phase = 1) (1) (2) (3) (4)NO.

PARAMETER

MIN

12tc(SPC)SCycle time, SPICLK

13

tw(SPC1)S

14

tw(SPC2)S17

td(SOMI)S

Delay time, SPICLK to SPISOMI valid

18

tv(SOMI)S

Valid time, SPISOMI data valid after SPICLK

21

tsu(SIMO)S

22

th(SIMO)S

25
26
(1)
(2)
(3)
(4)

MAX

UNIT

4tc(SYSCLK)

ns

Pulse duration, SPICLK first pulse

2tc(SYSCLK) – 1

ns

Pulse duration, SPICLK second pulse

2tc(SYSCLK) – 1

ns
35

ns

0

ns

Setup time, SPISIMO valid before SPICLK

1.5tc(SYSCLK)

ns

Hold time, SPISIMO data valid after SPICLK

1.5tc(SYSCLK)

nstsu(STE)S

Setup time, SPISTE active before SPICLK

1.5tc(SYSCLK)

nsth(STE)S

Hold time, SPISTE inactive after SPICLK

1.5tc(SYSCLK)ns

The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12

SPICLK(clock polarity = 0)13

14

SPICLK(clock polarity = 1)

17
SPISOMI

Data Valid

SPISOMI Data Is Valid

Data Valid

18

21
22
SPISIMO Data
Must Be ValidSPISIMO

26

25
SPISTE

Figure 5-22. SPI Slave Mode External Timing (Clock Phase = 1)

56

Specifications

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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www.ti.com

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

5.14.5 Emulator Connection Without Signal Buffering for the DSP
Figure 5-23 shows the connection between the DSP and JTAG header for a single-processor
configuration. If the distance between the JTAG header and the DSP is greater than 6 inches, theemulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed.
Figure 5-23 shows the simpler, no-buffering situation. For the pullup/pulldown resistor values, see
Section 4.2.
6 inches or less
VDDIO

EMU0
EMU1
TRST
TMS
TDI
TDO
TCK

VDDIO

13
14
2
1
3
7
11
9

EMU0

PD

5

EMU1
TRST

GND

TMS

GND

TDI

GND

TDO

GND

TCK

GND

4
6
8
10
12

TCK_RETDSPJTAG Header

Figure 5-23. Emulator Connection Without Signal Buffering for the DSP

Specifications
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Copyright © 2003–2019, Texas Instruments Incorporated

57

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

5.14.6 Flash Timing
Table 5-37. Flash Endurance for A and S Temperature Material (1)ERASE/PROGRAMTEMPERATURE

MIN

TYP

20000

50000

Nf

Flash endurance for the array (write/erase cycles)

0°C to 85°C (ambient)NOTP

OTP endurance for the array (write cycles)

0°C to 85°C (ambient)

(1)

MAX

UNIT
cycles1

write

Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.

Table 5-38. Flash Endurance for Q Temperature Material (1)ERASE/PROGRAMTEMPERATURE

MIN

TYP

20000

50000

Nf

Flash endurance for the array (write/erase cycles)–40°C to 125°C (ambient)NOTP

OTP endurance for the array (write cycles)–40°C to 125°C (ambient)

(1)

MAX

UNIT
cycles1

write

Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.

Table 5-39. Flash Parameters at 100-MHz SYSCLKOUT
PARAMETER

Program
Time (1)EraseTime (3)TEST CONDITIONS

MIN

TYP

MAX

UNIT

16-Bit Word

50

16K Sector

5002000 (2)ms

8K Sector

250

2000 (2)ms

4K Sector

125

(2)

ms

16K Sector2

15 (2)s

8K Sector2

15 (2)

s

4K Sector2

15 (2)

s

μs

2000

Erase

75

mA

Program

35

mA

IDDP (4)VDD current consumption during
Erase/Program cycle

140

mA

IDDIOP (4)VDDIO current consumption during
Erase/Program cycle

20mA

IDD3VFLP (4)VDD3VFL current consumption during theErase/Program cycle

(1)

(2)
(3)
(4)

Program time is at the maximum device frequency. The programming time indicated in this table is applicable only when all the required
code/data is available in the device RAM, ready for programming. Program time includes overhead of the flash state machine but does
not include the time to transfer the following into RAM:• the code that uses flash API to program the flash• the Flash API itself• Flash data to be programmed
The parameters mentioned in the MAX column are for the first 100 Erase/Program cycles.
The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
before programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain astable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brownout or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during
flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed
during the programming process.

Table 5-40. Flash/OTP Access Timing
PARAMETER

MIN

MAX

UNIT

ta(fp)

Paged flash access time36

nsta(fr)

Random flash access time36

nsta(OTP)OTP access time

60

ns

58

Specifications

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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www.ti.com

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Table 5-41. Flash Data Retention Duration
PARAMETER
tretention

TEST CONDITIONS

Data retention duration

MIN

TJ = 55°C

MAX

15

UNIT
years

Table 5-42. Minimum Required Flash/OTP Wait-States at Different Frequencies
SYSCLKOUT
(MHz)

(1)

SYSCLKOUT (ns)FLASH PAGE
WAIT-STATEFLASH RANDOM
WAIT-STATE (1)OTP WAIT-STATE

100

10

3

3

5

75

13.33

2

2

4

60

16.67

2

2

3

50

20

1

1

2

30

33.33

1

1

1

25

40

0

1

1

15

66.67

0

1

1

4

250

0

1

1

Random wait-state must be greater than or equal to 1.

Equations to compute the Flash page wait-state and random wait-state in Table 5-42 are as follows:
Flash Page Wait-State +ƪǒ Ǔ ƫƪǒ Ǔ ƫ
ta(fp)*1t c(SCO)Flash Random Wait-State +ta(fr)t c(SCO)(round up to the next highest integer) or 0, whichever is larger* 1 (round up to the next highest integer) or 1, whichever is larger

Equation to compute the OTP wait-state in Table 5-42 is as follows:
OTP Wait-State +ƪǒta(OTP)t c(SCO)Ǔ ƫ* 1 (round up to the next highest integer) or 1, whichever is larger

Specifications
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59

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

5.15 On-Chip Analog-to-Digital Converter
Table 5-43. ADC Electrical Characteristics (1) (2)over recommended operating conditions
PARAMETER

MIN

TYP

MAX

UNIT

DC SPECIFICATIONSResolution

12

ADC clockBits

60-MHz device

0.001

7.5

100-MHz device

0.001

12.5

100-MHz device (F2809 only)

0.001

25

MHz

ACCURACY
INL (Integral nonlinearity)

1–12.5 MHz ADC clock (6.25 MSPS)±1.5

12.5–25 MHz ADC clock (12.5 MSPS)±2

DNL (Differential nonlinearity) (3)Offset error

(4)

–60

Offset error with hardware trimming

±1

LSB

+60

LSB

±4

Overall gain error with internal reference (5)–60Overall gain error with external reference

–60

LSB

LSB
+60

LSB

+60

LSB

Channel-to-channel offset variation

±4

LSB

Channel-to-channel gain variation

±4

LSB

ANALOG INPUT
Analog input voltage (ADCINx to ADCLO) (6)

0

ADCLO

–5

Input capacitance

0

3

V

5

mV

10

Input leakage current

pF
±5

μA

INTERNAL VOLTAGE REFERENCE (5)VADCREFP - ADCREFP output voltage at the pin
based on internal reference

1.275

V

VADCREFM - ADCREFM output voltage at the pin
based on internal reference

0.525

V

Voltage difference, ADCREFP - ADCREFM

0.75

V

50

PPM/°CADCREFSEL[15:14] = 11b

1.024

V

ADCREFSEL[15:14] = 10b

1.500

V

ADCREFSEL[15:14] = 01b

2.048

V

67.5

dB

SNR (100 kHz) Signal-to-noise ratio

68dB

THD (100 kHz) Total harmonic distortion

–79

dB

ENOB (100 kHz) Effective number of bits

10.9

Bits

83

dB

Temperature coefficient
EXTERNAL VOLTAGE REFERENCE (5) (7)VADCREFIN - External reference voltage input on
ADCREFIN pin 0.2% or better accurate
reference recommended
AC SPECIFICATIONSSINAD (100 kHz) Signal-to-noise ratio +distortion

SFDR (100 kHz) Spurious free dynamic range
(1)
(2)
(3)
(4)
(5)

(6)
(7)
60

Tested at 12.5 MHz ADCCLK.
All voltages listed in this table are with respect to VSSA2.
TI specifies that the ADC will have no missing codes.
1 LSB has the weighted value of 3.0/4096 = 0.732 mV.
A single internal/external band gap reference sources both ADCREFP and ADCREFM signals, and hence, these voltages track
together. The ADC converter uses the difference between these two as its reference. The total gain error listed for the internal reference
is inclusive of the movement of the internal bandgap over temperature. Gain error over temperature for the external reference option will
depend on the temperature profile of the source used.
Voltages above VDDA + 0.3 V or below VSS - 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin.
To avoid this, the analog inputs should be kept within these limits.
TI recommends using high precision external reference TI part REF3020/3120 or equivalent for 2.048-V reference.
Specifications

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

5.15.1 ADC Power-Up Control Bit Timing
ADC Power Up Delay

ADC Ready for ConversionsPWDNBGPWDNREFtd(BGR)PWDNADC
td(PWD)

Request for
ADC
Conversion

Figure 5-24. ADC Power-Up Control Bit Timing
Table 5-44. ADC Power-Up Delays
PARAMETER (1)td(BGR)

Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3
register (ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled.

td(PWD)

Delay time for power-down control to be stable. Bit delay time for band-gap
reference to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0)
must be set to 1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3
register (PWDNADC)must be set to 1 before any ADC conversions are initiated.

(1)

MIN

20

TYP

MAX

UNIT

5

ms

50

μs
1

ms

Timings maintain compatibility to the 281x ADC module. The 280x ADC also supports driving all 3 bits at the same time and waitingtd(BGR) ms before first conversion.

Table 5-45. Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK) (1) (2)ADC OPERATING MODE

CONDITIONSVDDA18VDDA3.3

UNIT

Mode A (Operational Mode):••

BG and REF enabled
PWD disabled

30

2

mA

Mode B:•••ADC clock enabled
BG and REF enabled
PWD enabled

9

0.5

mA

Mode C:•••ADC clock enabled
BG and REF disabled
PWD enabled

5

20

μA

Mode D:•••ADC clock disabled
BG and REF disabled
PWD enabled

5

15

μA

(1)

(2)

Test Conditions:
SYSCLKOUT = 100 MHz
ADC module clock = 12.5 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
VDDA18 includes current into VDD1A18 and VDD2A18. VDDA3.3 includes current into VDDA2 and VDDAIO.

Specifications
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Rs

SourceSignalwww.ti.com

ADCIN0Ron
1 kΩ

Switch

Cp
10 pF

ac

Ch
1.64 pF

28x DSP

Typical Values of the Input Circuit Components:
Switch Resistance (Ron):
Sampling Capacitor (Ch):
Parasitic Capacitance (Cp):
Source Resistance (Rs):

1 kΩ
1.64 pF
10 pF
50 Ω

Figure 5-25. ADC Analog Input Impedance Model

5.15.2 Definitions
Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC.
Analog Inputs
The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at
a time. These inputs are software-selectable.
Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate withlow power consumption.
Conversion Modes
The conversion can be performed in two different conversion modes:• Sequential sampling mode (SMODE = 0)
• Simultaneous sampling mode (SMODE = 1)

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5.15.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Axto Bx). The ADC can start conversions on event triggers from the ePWM, software trigger, or from anexternal ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel on
every Sample/Hold pulse. The conversion time and latency of the Result register update are explained
below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The
selected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse
width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
Sample n+2
Sample n+1
Analog Input on
Channel Ax or Bx

Sample n

ADC ClockSample and HoldSH Pulse
SMODE Bittd(SH)

tdschx_n+1
tdschx_n

ADC Event Trigger fromePWM or Other SourcestSH

Figure 5-26. Sequential Sampling Mode (Single-Channel) Timing
Table 5-46. Sequential Sampling Mode Timing
SAMPLE n

SAMPLE n + 1

AT 12.5 MHz
ADC CLOCK,tc(ADCCLK) = 80 ns

td(SH)

Delay time from event trigger tosampling

2.5tc(ADCCLK)tSH

Sample/Hold width/Acquisition
Width(1 + Acqps) *tc(ADCCLK)

80 ns with Acqps = 0

td(schx_n)

Delay time for first result to appear
in Result register

4tc(ADCCLK)

320 nstd(schx_n+1)

Delay time for successive results toappear in Result register(2 + Acqps) *tc(ADCCLK)REMARKS

Acqps value = 0–15
ADCTRL1[8:11]

160 nsSpecifications
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5.15.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the ePWM, software trigger, orfrom an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selectedchannels on every Sample/Hold pulse. The conversion time and latency of the result register update are
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register
update. The selected channels will be sampled simultaneously at the falling edge of the Sample/Holdpulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC
clocks wide (maximum).
NOTE
In simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7,
and not in other combinations (such as A1/B3, and so forth).

Sample n

Sample n+2

Sample n+1

Analog Input on
Channel Ax
Analog Input on
Channel Bx
ADC ClockSample and HoldSH Pulse
SMODE Bittd(SH)

tdschA0_n+1

tSH

ADC Event Trigger fromePWM or Other SourcestdschA0_ntdschB0_n+1

tdschB0_n

Figure 5-27. Simultaneous Sampling Mode Timing
Table 5-47. Simultaneous Sampling Mode Timing
SAMPLE n

SAMPLE n + 1

AT 12.5 MHz
ADC CLOCK,tc(ADCCLK) = 80 ns

td(SH)

Delay time from event trigger tosampling

2.5tc(ADCCLK)tSH

Sample/Hold width/Acquisition
Width(1 + Acqps) *tc(ADCCLK)

80 ns with Acqps = 0

td(schA0_n)

Delay time for first result toappear in Result register

4tc(ADCCLK)

320 nstd(schB0_n )Delay time for first result toappear in Result register

5tc(ADCCLK)

400 nstd(schA0_n+1)

Delay time for successive results
to appear in Result register(3 + Acqps) * tc(ADCCLK)

240 nstd(schB0_n+1 )Delay time for successive results
to appear in Result register(3 + Acqps) * tc(ADCCLK)

240 ns64

Specifications

REMARKS

Acqps value = 0–15
ADCTRL1[8:11]

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5.15.5 Detailed Descriptions
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through fullscale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point isdefined as level one-half LSB beyond the last code transition. The deviation is measured from the centerof each particular code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal
value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as thedeviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The lasttransition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error isthe deviation of the actual difference between first and last code transitions and the ideal difference
between first and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral
components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD isexpressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,(SINAD * 1.76)
N+
6.02
it is possible to get a measure of performance expressed as N, the effective numberof bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can becalculated directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured
input signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.

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5.16 Migrating From F280x Devices to C280x Devices
5.16.1 Migration Issues
The migration issues to be considered while migrating from the F280x devices to C280x devices are as
follows:• The 1K OTP memory available in F280x devices has been replaced by 1K ROM C280x devices.
• Current consumption differs for F280x and C280x devices for all four possible modes. See theappropriate electrical section for exact numbers.
• The VDD3VFL pin is the 3.3-V Flash core power pin in F280x devices but is a VDDIO pin in C280x
devices.
• F280x and C280x devices are pin-compatible and code-compatible; however, they are electricallydifferent with different EMI/ESD profiles. Before ramping production with C280x devices, evaluate
performance of the hardware design with both devices.
• Addresses 0x3D 7BFC through 0x3D 7BFF in the OTP and addresses 0x3F 7FF0 through 0x3F 7FF5in the main ROM array are reserved for ROM part-specific information and are not available for user
applications.
• The paged and random wait-state specifications for the Flash and ROM parts are different. Whilemigrating from Flash to ROM parts, the same wait-state values must be used for best-performancecompatibility (for example, in applications that use software delay loops or where precise interrupt
latencies are critical).
• The analog input switch resistance is smaller in C280x devices compared to F280x devices. Whilemigrating from a Flash to a ROM device care should be taken to design the analog input circuits tomeet the application performance required by the sampling network.
• The PART-ID register value is different for Flash and ROM parts.
• From a silicon functionality/errata standpoint, rev A ROM devices are equivalent to rev C flash devices.
See the errata applicable to 280x devices for details.
• As part of the ROM code generation process, all unused memory locations in the customer application
are automatically filled with 0xFFFF. Unused locations should not be manually filled with any other
data.
NOTE
Requests for ROM versions of the F280x device are not accepted by TI anymore.

For errata applicable to 280x devices, see the TMS320F280x, TMS320C280x, TMS320F2801x DSPs
silicon errata.

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JAJS280O – OCTOBER 2003 – REVISED MARCH 20195.17 ROM Timing (C280x only)
Table 5-48. ROM/OTP Access Timing
PARAMETER

MIN

MAX

UNIT

ta(rp)

Paged ROM access time19

nsta(rr)

Random ROM access time

19

ns

60

ns

ta(ROM)(1)(1)

ROM (OTP area) access timeIn C280x devices, a 1K X 16 ROM block replaces the OTP block found in Flash devices.

Table 5-49. ROM/ROM (OTP area) Minimum Required
Wait-States at Different Frequencies
SYSCLKOUT(MHz)SYSCLKOUT(ns)

PAGE WAITSTATERANDOM WAITSTATE (1)

100

10

1

1

75

13.33

1

1

50

20

0

1

30

33.33

0

1

25

40

0

1

15

66.67

0

1

4

250

0

1

(1)

Random wait-state must be greater than or equal to 1.

Equations to compute the page wait-state and random wait-state in Table 5-49 are as follows:
ROM Page Wait-State +ƪǒROM Random Wait-State +t a(rp)t c(SCO)

ƪǒ

Ǔ ƫ
*1

t a(rr)t c(SCO)(round up to the next highest integer) or 0, whichever is largerǓ ƫ* 1 (round up to the next highest integer) or 1, whichever is larger

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6 Detailed Description
6.1

Brief Descriptions

6.1.1

C28x CPU
The C28x DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is avery efficient C/C++ engine, enabling users to develop not only their system control software in a highlevel language, but also enables math algorithms to be developed using C/C++. The C28x is as efficient in
DSP math tasks as it is in system control tasks that typically are handled by microcontroller devices. Thisefficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC capabilities of
the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher numericalresolution problems that would otherwise demand a more expensive floating-point processor solution. Add
to this the fast interrupt response with automatic context save of critical registers, resulting in a device thatis capable of servicing many asynchronous events with minimal latency. The C28x has an 8-level-deep
protected pipeline with pipelined memory accesses. This pipelining enables the C28x to execute at highspeeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware
minimizes the latency for conditional discontinuities. Special store conditional operations further improve
performance.

6.1.2

Memory Bus (Harvard Bus Architecture)
As with many DSP type devices, multiple busses are used to move data between the memories andperipherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables theC28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals andmemories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory
bus accesses can be summarized as follows:
Highest:Data Writes(Simultaneous data and program writes cannot occur on thememory bus.)

Program Writes (Simultaneous data and program writes cannot occur on thememory bus.)
Data Reads

Lowest:6.1.3

Program
Reads(Simultaneous program reads and fetches cannot occur on thememory bus.)

Fetches(Simultaneous program reads and fetches cannot occur on thememory bus.)

Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the280x devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge
multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of
16 address lines and 16 or 32 data lines and associated control signals. Two versions of the peripheralbus are supported on the 280x. One version only supports 16-bit accesses (called peripheral frame 2).
The other version supports both 16- and 32-bit accesses (called peripheral frame 1).

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6.1.4

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Real-Time JTAG and Analysis
The 280x implements the standard IEEE 1149.1 JTAG interface. Additionally, the 280x supports real-timemode of operation whereby the contents of memory, peripheral and register locations can be modified
while the processor is running and executing code and servicing interrupts. The user can also single step
through non-time critical code while enabling time-critical interrupts to be serviced without interference.
The 280x implements the real-time mode in hardware within the CPU. This is a unique feature to the
280x, no software monitor is required. Additionally, special analysis hardware is provided which allows theuser to set hardware breakpoint or data/address watch-points and generate various user-selectable break
events when a match occurs.

6.1.5

Flash
The F2809 contains 128K x 16 of embedded flash memory, segregated into eight 16K x 16 sectors. The
F2808 contains 64K x 16 of embedded flash memory, segregated into four 16K x 16 sectors. The F2806
and F2802 have 32K x 16 of embedded flash, segregated into four 8K x 16 sectors. The F2801 device
contains 16K x 16 of embedded flash, segregated into four 4K x 16 sectors. All five devices also contain asingle 1K x 16 of OTP memory at address range 0x3D 7800 – 0x3D 7BFF. The user can individuallyerase, program, and validate a flash sector while leaving other sectors untouched. However, it is notpossible to use one sector of the flash or the OTP to execute flash algorithms that erase/program othersectors. Special memory pipelining is provided to enable the flash module to achieve higher performance.
The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code orstore data information. Note that addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data variables andshould not contain program code.
NOTE
The F2809/F2808/F2806/F2802/F2801 Flash and OTP wait-states can be configured by theapplication. This allows applications running at slower frequencies to configure the flash touse fewer wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in theFlash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait-state
configuration alone. The exact performance gain when using the Flash pipeline mode isapplication-dependent.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers,
see the TMS320x280x, 2801x, 2804x DSP system control and interrupts reference guide.

6.1.6

ROM
The C2802 contains 32K x 16 of ROM, while the C2801 contains 16K x 16 of ROM.
NOTE
Requests for ROM devices are not accepted by TI anymore.

6.1.7

M0, M1 SARAMs
All 280x devices contain these two blocks of single-access memory, each 1K x 16 in size. The stack
pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks
on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 toexecute code or for data variables. The partitioning is performed within the linker. The C28x device
presents a unified memory map to the programmer. This makes for easier programming in high-level
languages.

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6.1.8

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L0, L1, H0 SARAMs
The F2809 and F2808 each contain an additional 16K x 16 of single-access RAM, divided into threeblocks (L0-4K, L1-4K, H0-8K). The F2806 contains an additional 8K x 16 of single-access RAM, divided
into two blocks (L0-4K, L1-4K). The F2802, F2801, C2802, and C2801 each contain an additional 4K x 16
of single-access RAM (L0-4K). Each block can be independently accessed to minimize CPU pipeline
stalls. Each block is mapped to both program and data space.

6.1.9

Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell
the bootloader software what boot mode to use on power up. The user can select to boot normally or to
download new software from an external connection or to select boot software that is programmed in theinternal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use
in math related algorithms.
Table 6-1. Boot Mode Selection
DESCRIPTIONGPIO18SPICLKASCITXDBGPIO29SCITXDAGPIO34

Boot to Flash/ROM

Jump to Flash/ROM address 0x3F 7FF6
You must have programmed a branch instruction here prior
to reset to redirect code execution as desired.

1

1

1

SCI-A Boot

Load a data stream from SCI-A

1

1

0

SPI-A Boot

Load from an external serial SPI EEPROM on SPI-A

1

0

1

I2C Boot

Load data from an external EEPROM at address 0x50 on
the I2C bus

1

0

0

eCAN-A Boot

Call CAN_Boot to load from eCAN-A mailbox 1.

0

1

1

Boot to M0 SARAM

Jump to M0 SARAM address 0x00 0000.

0

1

0

Boot to OTP

Jump to OTP address 0x3D 7800

0

0

1

Parallel I/O Boot

Load data from GPIO0 - GPIO15

0

0

0

MODE

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6.1.10 Security
The 280x devices support high levels of security to protect the user firmware from being reverse
engineered. The security features a 128-bit password (hardcoded for 16 wait-states), which the user
programs into the flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1
SARAM blocks. The security feature prevents unauthorized users from examining the memory contents
via the JTAG port, executing code from external memory or trying to boot-load some undesirable softwarethat would export the secure memory contents. To enable access to the secure blocks, the user must
write the correct 128-bit KEY value, which matches the value stored in the password locations within theFlash.
NOTE
The 128-bit password (at 0x3F 7FF8 – 0x3F 7FFF) must not be programmed to zeros. Doingso would permanently lock the device.

DISCLAIMER
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNEDTO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY(EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN
ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO
TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR
THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BECOMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATEDMEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPTAS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONSCONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIEDWARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAYOUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE,
BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR
INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

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6.1.11 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the 280x, 43 of the possible 96 interrupts areused by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of
12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a
dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU
on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.
Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in
hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.

6.1.12 External Interrupts (XINT1, XINT2, XNMI)The 280x supports three masked external interrupts (XINT1, XINT2, XNMI). XNMI can be connected to
the INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, orboth negative and positive edge triggering and can also be enabled/disabled (including the XNMI). The
masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a validinterrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike the281x devices, there are no dedicated pins for the external interrupts. Rather, any Port A GPIO pin can be
configured to trigger any external interrupt.

6.1.13 Oscillator and PLL
The 280x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit.
A PLL is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly
in software, enabling the user to scale back on operating frequency if lower power operation is desired.
See Section 5 for timing details. The PLL block can be set in bypass mode.

6.1.14 Watchdog
The 280x devices contain a watchdog timer. The user software must regularly reset the watchdog counter
within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog
can be disabled if necessary.

6.1.15 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption
when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C and eCAN)
and the ADC blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be
decoupled from increasing CPU clock speeds.

6.1.16 Low-Power Modes
The 280x devices are full static CMOS devices. Three low-power modes are provided:
IDLE:

Place CPU into low-power mode. Peripheral clocks may be turned off selectively andonly those peripherals that need to function during IDLE are left operating. An
enabled interrupt from an active peripheral or the watchdog timer will wake theprocessor from IDLE mode.

STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL
functional. An external interrupt event will wake the processor and the peripherals.
Execution begins on the next valid cycle after detection of the interrupt event
HALT:

72

Detailed Description

Turns off the internal oscillator. This mode basically shuts down the device andplaces it in the lowest possible power consumption mode. A reset or external signal
can wake the device from this mode.

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

6.1.17 Peripheral Frames 0, 1, 2 (PFn)
The 280x segregate peripherals into three sections. The mapping of peripherals is as follows:
PF0:

PF1:

PF2:

PIE:

PIE Interrupt Enable and Control Registers Plus PIE Vector Table

Flash:

Flash Control, Programming, Erase, Verify Registers

Timers:CPU-Timers 0, 1, 2 Registers

CSM:

Code Security Module KEY Registers

ADC:

ADC Result Registers (dual-mapped)

eCAN:

eCAN Mailbox and Control Registers

GPIO:

GPIO MUX Configuration and Control Registers

ePWM:

Enhanced Pulse Width Modulator Module and Registers

eCAP:

Enhanced Capture Module and Registers

eQEP:

Enhanced Quadrature Encoder Pulse Module and Registers

SYS:

System Control Registers

SCI:

Serial Communications Interface (SCI) Control and RX/TX Registers

SPI:

Serial Port Interface (SPI) Control and RX/TX Registers

ADC:

ADC Status, Control, and Result Register

I2C:

Inter-Integrated Circuit Module and Registers

6.1.18 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pinsare configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power
modes.

6.1.19 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clockprescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counterreaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 isreserved for the SYS/BIOS Real-Time OS, and is connected to INT14 of the CPU. If SYS/BIOS is not
being used, CPU-Timer 2 is available for general use. CPU-Timer 1 is for general use and can beconnected to INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block.

Detailed Description
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

6.1.20 Control Peripherals
The 280x devices support the following peripherals which are used for embedded control andcommunication:ePWM:

The enhanced PWM peripheral supports independent/complementary PWM
generation, adjustable dead-band generation for leading/trailing edges,
latched/cycle-by-cycle trip mechanism. Some of the PWM pins support HRPWM
features.

eCAP:The enhanced capture peripheral uses a 32-bit time base and registers up to four
programmable events in continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.

eQEP:

The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed
measurement using capture unit and high-speed measurement using a 32-bit unit
timer.
This peripheral has a watchdog timer to detect motor stall and input error detection
logic to identify simultaneous edge transition in QEP signals.

ADC:

The ADC block is a 12-bit converter, single-ended, 16-channels. It contains two
sample-and-hold units for simultaneous sampling.

6.1.21 Serial Port Peripherals
The 280x devices support the following serial communication peripherals:

74

eCAN:

This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, timestamping of messages, and is compliant with ISO11898-1 (CAN 2.0B).

SPI:

The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream ofprogrammed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications
between the DSP controller and external peripherals or another processor. Typicalapplications include external I/O or peripheral expansion through devices such as
shift registers, display drivers, and ADCs. Multi-device communications aresupported by the master/slave operation of the SPI. On the 280x, the SPI contains a
16-level receive and transmit FIFO for reducing interrupt servicing overhead.

SCI:

The serial communications interface is a two-wire asynchronous serial port,
commonly known as UART. On the 280x, the SCI contains a 16-level receive andtransmit FIFO for reducing interrupt servicing overhead.

I2C:

The inter-integrated circuit (I2C) module provides an interface between a DSP andother devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus)
specification version 2.1 and connected by way of an I2C-bus. External components
attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the
DSP through the I2C module. On the 280x, the I2C contains a 16-level receive andtransmit FIFO for reducing interrupt servicing overhead.

Detailed Description

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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6.2

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Peripherals
The integrated peripherals of the 280x are described in the following subsections:• Three 32-bit CPU-Timers• Up to six enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6)• Up to four enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4)• Up to two enhanced QEP modules (eQEP1, eQEP2)• Enhanced analog-to-digital converter (ADC) module• Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B)• Up to two serial communications interface modules (SCI-A, SCI-B)• Up to four serial peripheral interface (SPI) modules (SPI-A, SPI-B, SPI-C, SPI-D)• Inter-integrated circuit module (I2C)• Digital I/O and shared pin functions

6.2.1

32-Bit CPU-Timers 0/1/2
There are three 32-bit CPU-timers on the 280x devices (CPU-TIMER0/1/2).
CPU-Timer 0 and CPU-Timer 1 can be used in user applications. Timer 2 is reserved for SYS/BIOS.
These timers are different from the timers that are present in the ePWM modules.
NOTE
If the application is not using SYS/BIOS, then CPU-Timer 2 can be used in the application.

Reset
Timer Reload

16-Bit Timer Divide-Down
TDDRH:TDDRSYSCLKOUT
TCR.4(Timer Start Status)

32-Bit Timer Period
PRDH:PRD

16-Bit Prescale Counter
PSCH:PSC
Borrow

32-Bit Counter
TIMH:TIM
Borrow

TINT

Figure 6-1. CPU-Timers

Detailed Description
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

In the 280x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in
Figure 6-2.

INT1
to
INT12

PIE

TINT0

CPU-TIMER 0

C28x
TINT1

INT13

CPU-TIMER 1

XINT13A.
B.

CPU-TIMER 2(Reserved for
SYS/BIOS)

TINT2

INT14

The timer registers are connected to the memory bus of the C28x processor.
The timing of the timers is synchronized to SYSCLKOUT of the processor clock.

Figure 6-2. CPU-Timer Interrupt Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with thevalue in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of theC28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The
registers listed in Table 6-2 are used to configure the timers. For more information, see the TMS320x280x,
2801x, 2804x DSP system control and interrupts reference guide.
Table 6-2. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME

ADDRESSSIZE (x16)

TIMER0TIM

0x0C001

CPU-Timer 0, Counter Register

TIMER0TIMH

0x0C01

1

CPU-Timer 0, Counter Register HighTIMER0PRD

0x0C02

1

CPU-Timer 0, Period Register

TIMER0PRDH

0x0C03

1

CPU-Timer 0, Period Register HighTIMER0TCR

0x0C04

1

CPU-Timer 0, Control Register

Reserved

0x0C05

1

Reserved

TIMER0TPR

0x0C06

1

CPU-Timer 0, Prescale Register

TIMER0TPRH

0x0C07

1

CPU-Timer 0, Prescale Register HighTIMER1TIM

0x0C081

CPU-Timer 1, Counter Register

TIMER1TIMH

0x0C091

CPU-Timer 1, Counter Register HighTIMER1PRD

0x0C0A

1

CPU-Timer 1, Period Register

TIMER1PRDH

0x0C0B

1

CPU-Timer 1, Period Register HighTIMER1TCR

0x0C0C

1

CPU-Timer 1, Control Register

Reserved

0x0C0D

1

Reserved

TIMER1TPR

0x0C0E

1

CPU-Timer 1, Prescale Register

TIMER1TPRH

0x0C0F

1

CPU-Timer 1, Prescale Register HighTIMER2TIM

0x0C101

CPU-Timer 2, Counter Register

TIMER2TIMH

0x0C11

1

CPU-Timer 2, Counter Register HighTIMER2PRD

0x0C12

1

CPU-Timer 2, Period Register

TIMER2PRDH

0x0C13

1

CPU-Timer 2, Period Register HighTIMER2TCR

0x0C14

1

CPU-Timer 2, Control Register

Reserved

0x0C15

1

Reserved

76

Detailed Description

DESCRIPTION

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Table 6-2. CPU-Timers 0, 1, 2 Configuration and Control Registers (continued)
NAME

ADDRESSSIZE (x16)0x0C16

1

CPU-Timer 2, Prescale Register

TIMER2TPRH

0x0C17

1

CPU-Timer 2, Prescale Register High

Reserved

0x0C18 –0x0C3F

40

Reserved

TIMER2TPR

6.2.2

DESCRIPTION

Enhanced PWM Modules (ePWM1/2/3/4/5/6)
The 280x device contains up to six enhanced PWM modules (ePWM). Figure 6-3 shows a block diagramof multiple ePWM modules. Figure 6-4 shows the signal interconnections with the ePWM. See the
TMS320x280x, 2801x, 2804x Enhanced Pulse Width Modulator (ePWM) module reference guide for moredetails.
EPWM1SYNCIEPWM1SYNCIEPWM1INT
EPWM1SOC

EPWM1AePWM1 Module

EPWM1BTZ1 to TZ6

To eCAP1
Module(Sync in)

EPWM1SYNCO

EPWM1SYNCO

EPWM2SYNCIEPWM2INT
EPWM2SOCPIE

EPWM2AePWM2 Module

EPWM2BTZ1 to TZ6

EPWM2SYNCO

GPIO
MUX

EPWMxSYNCIEPWMxINT
EPWMxSOC

EPWMxAePWMx Module

EPWMxBTZ1 to TZ6

EPWMxSYNCO

ADCSOCx0
Peripheral Bus

ADC

Copyright © 2016, Texas Instruments Incorporated

Figure 6-3. Multiple PWM Modules in a 280x System
Table 6-3 shows the complete ePWM register set per module.

Detailed Description
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

Table 6-3. ePWM Control and Status Registers
ePWM1

ePWM2

ePWM3

ePWM4

ePWM5

ePWM6

SIZE (x16) /#SHADOW

TBCTL

0x68000x68400x68800x68C00x69000x69401/0Time Base Control Register

TBSTS

0x68010x68410x6881

0x68C10x69010x6941

1/0Time Base Status Register

TBPHSHR

0x68020x68420x68820x68C2

N/A

N/A

1/0

Time Base Phase HRPWM Register

TBPHS

0x68030x68430x68830x68C30x69030x6943

1/0Time Base Phase Register

TBCTR

0x68040x68440x68840x68C40x69040x6944

1/0Time Base Counter Register

TBPRD

0x68050x68450x68850x68C50x69050x6945

1/1Time Base Period Register Set

CMPCTL0x68070x68470x68870x68C70x69070x6947

1/0Counter Compare Control Register

CMPAHR

0x68080x68480x68880x68C8

N/A

N/A

1/1

Time Base Compare A HRPWM RegisterNAME

DESCRIPTION

CMPA

0x68090x68490x68890x68C90x69090x6949

1/1Counter Compare A Register Set

CMPB

0x680A0x684A

0x688A

0x68CA

0x690A

0x694A

1/1

Counter Compare B Register Set

AQCTLA

0x680B

0x684B

0x688B

0x68CB

0x690B

0x694B

1/0

Action Qualifier Control Register For Output A

AQCTLB

0x680C0x684C0x688C

0x68CC0x690C0x694C

1/0

Action Qualifier Control Register For Output B

AQSFRC0x680D

0x684D

0x688D

0x68CD

0x690D

0x694D

1/0

Action Qualifier Software Force Register

AQCSFRC

0x680E0x684E0x688E

0x68CE

0x690E0x694E

1/1

Action Qualifier Continuous S/W Force Register Set

DBCTL

0x680F0x684F0x688F

0x68CF0x690F0x694F

1/1

Dead-Band Generator Control Register

DBRED

0x68100x68500x68900x68D00x69100x69501/0

Dead-Band Generator Rising Edge Delay Count Register

DBFED

0x68110x68510x6891

0x68D10x69110x6951

1/0

Dead-Band Generator Falling Edge Delay Count Register

TZSEL

0x68120x68520x68920x68D20x69120x6952

1/0

Trip Zone Select Register (1)TZCTL

0x68140x68540x68940x68D40x69140x6954

1/0

Trip Zone Control Register (1)TZEINT

0x68150x68550x68950x68D50x69150x6955

1/0

Trip Zone Enable Interrupt Register (1)TZFLG

0x68160x68560x6896

0x68D60x69160x6956

1/0

Trip Zone Flag Register

TZCLR

0x68170x68570x6897

0x68D70x69170x6957

1/0

Trip Zone Clear Register (1)TZFRC

0x68180x68580x68980x68D80x69180x6958

1/0

Trip Zone Force Register (1)ETSEL

0x68190x68590x68990x68D90x69190x69591/0

Event Trigger Selection Register

ETPS

0x681A0x685A

0x689A

0x68DA

0x691A

0x695A

1/0

Event Trigger Prescale Register

ETFLG

0x681B

0x685B

0x689B

0x68DB

0x691B

0x695B

1/0

Event Trigger Flag Register

ETCLR

0x681C0x685C0x689C

0x68DC0x691C0x695C

1/0

Event Trigger Clear Register

ETFRC

0x681D

0x685D

0x689D

0x68DD

0x691D

0x695D

1/0

Event Trigger Force Register

PCCTL

0x681E0x685E0x689E

0x68DE

0x691E

0x695E

1/0

PWM Chopper Control Register

HRCNFG

0x68200x68600x68A00x68E00x6920 (2)0x6960 (2)1/0

HRPWM Configuration Register (1)

(1)
(2)

78

Registers that are EALLOW protected.
Applicable to F2809 only

Detailed Description

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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Time-Base (TB)
CTR = ZEROTBPRD Shadow (16)CTR = CMPBTBPRD Active (16)Disabled
CTR = PRD

Sync
In/OutSelectMux

EPWMxSYNCOTBCTL[SYNCOSEL]TBCTL[PHSEN]
EPWMxSYNCICounter
Up/Down(16-Bit)TBCTL[SWFSYNC](Software-Forced Sync)
CTR = ZEROTBCNTActive (16)

CTR_Dir
TBPHSHR (8)168TBPHS Active (24)

CTR = PRD

Phase
Control

CTR = ZERO
CTR = CMPACounter Compare (CC)CTR = CMPA
CMPAHR (8)16CTR = CMPBCTR_Dir

Event
TriggerandInterrupt(ET)

EPWMxINT
EPWMxSOCA
EPWMxSOCB

ActionQualifier(AQ)

8

HiRes PWM (HRPWM)

CMPA Active (24)EPWMxAO

EPWMA
CMPA Shadow (24)
Dead
Band
(DB)

CTR = CMPB

PWM
Chopper(PC)

16

EPWMxBOEPWMB
CMPB Active (16)
CMPB Shadow (16)

Trip
Zone
(TZ)

EPWMxTZINTCTR = ZEROTZ1 to TZ6

Copyright © 2016, Texas Instruments Incorporated

Figure 6-4. ePWM Sub-Modules Showing Critical Internal Signal Interconnections

Copyright © 2003–2019, Texas Instruments Incorporated

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Detailed Description

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

6.2.3

www.ti.com

Hi-Resolution PWM (HRPWM)
The HRPWM module offers PWM resolution (time granularity) which is significantly better than what canbe achieved using conventionally derived digital PWM methods. The key points for the HRPWM moduleare:• Significantly extends the time resolution capabilities of conventionally derived digital PWM• Typically used when effective PWM resolution falls below ~ 9–10 bits. This occurs at PWM frequencies
greater than ~200 kHz when using a CPU/System clock of 100 MHz.
• This capability can be utilized in both duty cycle and phase-shift control methods.
• Finer time granularity control or edge positioning is controlled via extensions to the Compare A andPhase registers of the ePWM module.
• HRPWM capabilities are offered only on the A signal path of an ePWM module (that is, on the
EPWMxA output). EPWMxB output has conventional PWM capabilities.

80

Detailed Description

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6.2.4

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Enhanced CAP Modules (eCAP1/2/3/4)
The 280x device contains up to four enhanced capture (eCAP) modules. Figure 6-5 shows a functional
block diagram of a module. See the TMS320x280x, 2801x, 2804x Enhanced Capture (eCAP) module
reference guide for more details.

SYNC

CTRPHS(Phase Register - 32-bit)
SYNCInSYNCOut

TSCTR(Counter - 32-bit)

APWM Mode
CTR_OVFOVF
RSTDelta Mode

CTR [0-31]

PWM
CompareLogic

PRD [0-31]
CMP [0-31]

32
CTR=PRD

CTR [0-31]

CTR=CMP32

CAP1(APRD Active)
APRD
Shadow
32

32

32

LD1

Polarity
Select

CMP [0-31]

CAP2(ACMP Active)

32

LD

MODE SELECT

32

PRD [0-31]

LD

32

CAP3
(APRD Shadow)

LD

32

CAP4
(ACMP Shadow)LD

Polarity
SelectLD2

Event
Qualifier

ACMP
Shadow

eCAPx

Event
Prescale

LD3

Polarity
SelectLD4Polarity
Select4
Capture Events

4

CEVT[1:4]

to PIEInterrupt
Trigger
andFlag
Control

CTR_OVF

Continuous/
One-Shot
Capture Control

CTR=PRD
CTR=CMPCopyright © 2016, Texas Instruments Incorporated

Figure 6-5. eCAP Functional Block Diagram

Detailed Description
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

The eCAP modules are clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1/2/3/4ENCLK) in the PCLKCR1 register are used to turn off the eCAP
modules individually (for low power operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK,ECAP3ENCLK, and ECAP4ENCLK are set to low, indicating that the peripheral clock is off.
Table 6-4. eCAP Control and Status Registers
eCAP1

eCAP2

eCAP3

eCAP4

SIZE
(x16)

TSCTR

0x6A00

0x6A20

0x6A400x6A602Time-Stamp Counter

CTRPHS

0x6A02

0x6A22

0x6A42

0x6A62

2

Counter Phase Offset Value Register

CAP1

0x6A04

0x6A24

0x6A44

0x6A642

Capture 1 Register

CAP2

0x6A06

0x6A26

0x6A46

0x6A662

Capture 2 RegisterNAME

DESCRIPTION

CAP3

0x6A08

0x6A28

0x6A48

0x6A682

Capture 3 Register

CAP4

0x6A0A

0x6A2A

0x6A4A

0x6A6A

2

Capture 4 Register

Reserved

0x6A0C –0x6A12

0x6A2C –0x6A32

0x6A4C –0x6A52

0x6A6C –0x6A72

8

Reserved

ECCTL1

0x6A14

0x6A34

0x6A54

0x6A741

Capture Control Register 1

ECCTL2

0x6A15

0x6A35

0x6A55

0x6A751

Capture Control Register 2

ECEINT

0x6A16

0x6A36

0x6A56

0x6A761

Capture Interrupt Enable Register

ECFLG

0x6A17

0x6A37

0x6A57

0x6A771

Capture Interrupt Flag Register

ECCLR

0x6A18

0x6A38

0x6A58

0x6A781

Capture Interrupt Clear Register

ECFRC

0x6A19

0x6A39

0x6A59

0x6A791

Capture Interrupt Force Register

Reserved

0x6A1A –0x6A1F

0x6A3A –0x6A3F

0x6A5A –0x6A5F

0x6A7A –0x6A7F

6

Reserved

82

Detailed Description

Copyright © 2003–2019, Texas Instruments Incorporated

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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6.2.5

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Enhanced QEP Modules (eQEP1/2)
The 280x device contains up to two enhanced quadrature encoder (eQEP) modules. See the
TMS320x280x, 2801x, 2804x Enhanced Quadrature Encoder Pulse (eQEP) module reference guide formore details.
System Control
Registers
To CPU
EQEPxENCLK

Data BusSYSCLKOUTQCPRDQCAPCTL

QCTMR

16

16

16

Quadrature
CaptureUnit(QCAP)QCTMRLATQCPRDLAT

Registers
Used byMultiple Units

QUTMR

QWDTMRQUPRD

QWDPRD32

16

QEPCTLQEPSTS

UTIME

QFLG

UTOUT

QWDOG

QDECCTL
16

WDTOUTPIE

EQEPxAINQCLK

EQEPxINT16QPOSLATEQEPxIIN

QI

Position Counter/
Control Unit
(PCCU)

EQEPxIOE
EQEPxSIN
EQEPxSOUTQPOSILAT

EQEPxSOE
32

32

QPOSCNTQPOSCMP

EQEPxB/XDIR

EQEPxIOUTQS Quadrature
Decoder
PHE(QDU)
PCSOUTQPOSSLAT

EQEPxA/XCLK

EQEPxBIN

QDIR

GPIO
MUX

EQEPxI
EQEPxS16QEINT

QPOSINITQFRCQPOSMAXQCLRQPOSCTL

Enhanced QEP (eQEP) Peripheral
Copyright © 2016, Texas Instruments Incorporated

Figure 6-6. eQEP Functional Block Diagram

Detailed Description
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

Table 6-5 provides a summary of the eQEP registers.
Table 6-5. eQEP Control and Status Registers
eQEP1
ADDRESSeQEP2
ADDRESSeQEP1
SIZE(x16)/#SHADOWQPOSCNT

0x6B000x6B402/0eQEP Position CounterQPOSINIT

0x6B02

0x6B422/0

eQEP Initialization Position CountQPOSMAX

0x6B04

0x6B442/0

eQEP Maximum Position CountQPOSCMP0x6B060x6B462/1

eQEP Position-compare

NAME

REGISTER DESCRIPTIONQPOSILAT

0x6B08

0x6B482/0

eQEP Index Position Latch

QPOSSLAT

0x6B0A

0x6B4A

2/0

eQEP Strobe Position LatchQPOSLAT

0x6B0C

0x6B4C

2/0

eQEP Position Latch

QUTMR

0x6B0E

0x6B4E

2/0

eQEP Unit Timer

QUPRD

0x6B100x6B502/0eQEP Unit Period Register

QWDTMR

0x6B12

0x6B52

1/0

eQEP Watchdog Timer

QWDPRD

0x6B13

0x6B53

1/0

eQEP Watchdog Period Register

QDECCTL

0x6B14

0x6B541/0

eQEP Decoder Control Register

QEPCTL

0x6B15

0x6B551/0

eQEP Control Register

QCAPCTL

0x6B160x6B561/0

eQEP Capture Control Register

QPOSCTL

0x6B17

0x6B571/0

eQEP Position-compare Control Register

QEINT

0x6B18

0x6B581/0

eQEP Interrupt Enable Register

QFLG

0x6B190x6B591/0

eQEP Interrupt Flag Register

QCLR

0x6B1A

0x6B5A

1/0

eQEP Interrupt Clear Register

QFRC

0x6B1B

0x6B5B

1/0

eQEP Interrupt Force Register

QEPSTS

0x6B1C

0x6B5C

1/0

eQEP Status Register

QCTMR

0x6B1D

0x6B5D

1/0

eQEP Capture Timer

QCPRD

0x6B1E

0x6B5E

1/0

eQEP Capture Period Register

QCTMRLAT

0x6B1F

0x6B5F

1/0

eQEP Capture Timer Latch

QCPRDLAT

0x6B200x6B601/0eQEP Capture Period Latch

Reserved

0x6B21–
0x6B3F

0x6B61 –0x6B7F

31/0

Reserved

84

Detailed Description

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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6.2.6

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Enhanced Analog-to-Digital Converter (ADC) Module
A simplified functional block diagram of the ADC module is shown in Figure 6-7. The ADC module
consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module
include:• 12-bit ADC core with built-in S/H• Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)• Fast conversion rate: Up to 80 ns at 25-MHz ADC clock, 12.5 MSPS
• 16-channel, MUXed inputs• Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion
can be programmed to select anyone of 16 input channels• Sequencer can be operated as two independent 8-channel sequencers or as one large 16-channel
sequencer (that is, two cascaded 8-channel sequencers)• Sixteen result registers (individually addressable) to store conversion values– The digital value of the input analog voltage is derived by:, when ADCIN £ ADCLO

Digital Value = 0(

Digital Value = floor 4096 ´
Digital Value = 4095
A.

•

•
•
•
•

ADCIN - ADCLO
3(, when ADCLO < ADCIN < 3 V, when ADCIN ³ 3 V

All fractional values are truncated.

Multiple triggers as sources for the start-of-conversion (SOC) sequence– S/W - software immediate start– ePWM start of conversion– XINT2 ADC start of conversion
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS.
Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" tosynchronize conversions.
SOCA and SOCB triggers can operate independently in dual-sequencer mode.
Sample-and-hold (S/H) acquisition time window has separate prescale control.

The ADC module in the 280x has been enhanced to provide flexible interface to ePWM peripherals. The
ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of up to 80 ns at 25MHz ADC clock. The ADC module has a 16-channel sequencer, configurable as two independent 8channel sequencers. The two independent 8-channel sequencers can be cascaded to form a 16-channel
sequencer. Although there are multiple input channels and two sequencers, there is only one converter inthe ADC module. Figure 6-7 shows the block diagram of the ADC module.
The two 8-channel sequencer modules have the capability to autosequence a series of conversions, each
module has the choice of selecting any one of the respective eight channels available through an analog
MUX. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On eachsequencer, once the conversion is complete, the selected channel value is stored in its respective
RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing
the user to perform oversampling algorithms. This gives increased resolution over traditional singlesampled conversion results.

Detailed Description
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

SystemControl BlockADCENCLKSYSCLKOUT

High-Speed
Prescaler

DSP

HSPCLK

HALT

AnalogMUXResult Registers
Result Reg 0

ADCINA070A8h

Result Reg 1

S/H
ADCINA7
12-BitADC
ModuleResult Reg 7

70AFh

Result Reg 8

70B0h

Result Reg 15

70B7h

ADCINB0
S/H
ADCINB7ADC Control Registers
S/W
EPWMSOCA

SOC

Sequencer 1

Sequencer 2

SOC

GPIO/XINT2_
ADCSOC

S/W
EPWMSOCB

Figure 6-7. Block Diagram of the ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent
possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths.
This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs.
Furthermore, proper isolation techniques must be used to isolate the ADC module power pins (VDD1A18,
VDD2A18, VDDA2, VDDAIO) from the digital supply. Figure 6-8 and Figure 6-9 show the ADC pin connections
for the 280x devices.
NOTE
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the
ADC module is controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT
signals is as follows:
–

–

86

Detailed Description

ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) theclock to the register will still function. This is necessary to make sure all registers andmodes go into their default reset state. The analog module, however, will be in a lowpower inactive state. As soon as reset goes high, then the clock to the registers will
be disabled. When the user sets the ADCENCLK signal high, then the clocks to theregisters will be enabled and the analog module will be enabled. There will be acertain time delay (ms range) before the ADC is stable and can be used.
HALT: This mode only affects the analog module. It does not affect the registers. In
this mode, the ADC module goes into low-power mode. This mode also will stop theclock to the CPU, which will stop the HSPCLK; therefore, the ADC register logic will
be turned off indirectly.

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Figure 6-8 shows the ADC pin-biasing for internal reference and Figure 6-9 shows the ADC pin-biasing forexternal reference.
ADC 16-Channel Analog Inputs

ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADCREFIN

ADC External Current Bias Resistor

ADCRESEXTADC Reference Positive Output

ADCREFPADC Reference Medium Output

ADCREFM

Analog input 0-3 V with respect to ADCLO
Connect to analog ground
Float or ground if internal reference is used
22 k
(A)

ADC Power

ADC Analog and Reference I/O Power

A.
B.
C.

2.2 μF(A)

2.2 μF

ADCREFP and ADCREFM should not
be loaded by external circuitry

VDD1A18
VDD2A18

VSS1AGNDVSS2AGNDADC Analog Power Pin (1.8 V)
ADC Analog Power Pin (1.8 V)
ADC Analog Ground Pin
ADC Analog Ground Pin

VDDA2

ADC Analog Power Pin (3.3 V)

VSSA2ADC Analog Ground Pin

VDDAIOVSSAIOADC Analog Power Pin (3.3 V)
ADC Analog I/O Ground Pin

TAIYO YUDEN LMK212BJ225MG-T or equivalent
External decoupling capacitors are recommended on all power pins.
Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.

Figure 6-8. ADC Pin Connections With Internal Reference

Detailed Description
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

ADC 16-Channel Analog Inputs

ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADCREFIN

ADC External Current Bias Resistor

ADCRESEXTADC Reference Positive Output

ADCREFPADC Reference Medium Output

ADCREFMADC Analog PowerADC Analog and Reference I/O Power

A.
B.
C.
D.

www.ti.com

Analog input 0-3 V with respect to ADCLO
Connect to Analog Ground(D)
Connect to 1.500, 1.024, or 2.048-V precision source
22 k
(A)

2.2 μF(A)

2.2 μF

ADCREFP and ADCREFM should not
be loaded by external circuitry

VDD1A18
VDD2A18

VSS1AGNDVSS2AGNDADC Analog Power Pin (1.8 V)
ADC Analog Power Pin (1.8 V)
ADC Analog Ground Pin
ADC Analog Ground Pin

VDDA2
VSSA2

ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin

VDDAIOVSSAIOADC Analog Power Pin (3.3 V)
ADC Analog I/O Ground Pin

TAIYO YUDEN LMK212BJ225MG-T or equivalent
External decoupling capacitors are recommended on all power pins.
Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
External voltage on ADCREFIN is enabled by changing bits 15:14 in the ADC Reference Select register depending on
the voltage used on this pin. TI recommends TI part REF3020 or equivalent for 2.048-V generation. Overall gain
accuracy will be determined by accuracy of this voltage source.

Figure 6-9. ADC Pin Connections With External Reference
NOTE
The temperature rating of any recommended component must match the rating of the end
product.

88

Detailed Description

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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www.ti.com

6.2.6.1

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

ADC Connections if the ADC Is Not Used

It is recommended to keep the connections for the analog power pins, even if the ADC is not used.
Following is a summary of how the ADC pins should be connected, if the ADC is not used in an
application:• VDD1A18/VDD2A18 – Connect to VDD• VDDA2, VDDAIO – Connect to VDDIO• VSS1AGND/VSS2AGND, VSSA2, VSSAIO – Connect to VSS• ADCLO – Connect to VSS• ADCREFIN – Connect to VSS• ADCREFP/ADCREFM – Connect a 100-nF cap to VSS• ADCRESEXT – Connect a 20-kΩ resistor (very loose tolerance) to VSS.
• ADCINAn, ADCINBn - Connect to VSS
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize powersavings.
When the ADC module is used in an application, unused ADC input pins should be connected to analog
ground (VSS1AGND/VSS2AGND)

Detailed Description
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Copyright © 2003–2019, Texas Instruments Incorporated

89

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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

6.2.6.2

www.ti.com

ADC Registers

The ADC operation is configured, controlled, and monitored by the registers listed in Table 6-6.
Table 6-6. ADC Registers (1)NAME

ADDRESS (1)ADDRESS (2)ADCTRL1

0x71001

ADC Control Register 1

SIZE (x16)

DESCRIPTIONADCTRL20x7101

1

ADC Control Register 2

ADCMAXCONV

0x7102

1

ADC Maximum Conversion Channels Register

ADCCHSELSEQ1

0x7103

1

ADC Channel Select Sequencing Control Register 1

ADCCHSELSEQ20x71041

ADC Channel Select Sequencing Control Register 2

ADCCHSELSEQ30x71051

ADC Channel Select Sequencing Control Register 3

ADCCHSELSEQ40x71061

ADC Channel Select Sequencing Control Register 4

ADCASEQSR

0x7107

1

ADC Auto-Sequence Status Register

ADCRESULT00x71080x0B001

ADC Conversion Result Buffer Register 0

ADCRESULT1

0x71090x0B01

1

ADC Conversion Result Buffer Register 1

ADCRESULT2

0x710A

0x0B02

1

ADC Conversion Result Buffer Register 2

ADCRESULT3

0x710B

0x0B03

1

ADC Conversion Result Buffer Register 3

ADCRESULT40x710C

0x0B041

ADC Conversion Result Buffer Register 4

ADCRESULT50x710D

0x0B051

ADC Conversion Result Buffer Register 5

ADCRESULT6

0x710E

0x0B061

ADC Conversion Result Buffer Register 6

ADCRESULT7

0x710F

0x0B071

ADC Conversion Result Buffer Register 7

ADCRESULT8

0x7110

0x0B081

ADC Conversion Result Buffer Register 8

ADCRESULT90x7111

0x0B091

ADC Conversion Result Buffer Register 9

ADCRESULT10

0x71120x0B0A1

ADC Conversion Result Buffer Register 10

ADCRESULT11

0x71130x0B0B1

ADC Conversion Result Buffer Register 11

ADCRESULT12

0x71140x0B0C1ADC Conversion Result Buffer Register 12

ADCRESULT13

0x7115

0x0B0D1

ADC Conversion Result Buffer Register 13

ADCRESULT14

0x7116

0x0B0E1

ADC Conversion Result Buffer Register 14

ADCRESULT15

0x71170x0B0F1

ADC Conversion Result Buffer Register 15

ADCTRL30x71181

ADC Control Register 3

ADCST

0x71191

ADC Status Register

Reserved

0x711A –0x711B

2

Reserved

(1)
(2)

90

ADCREFSEL

0x711C1

ADC Reference Select Register

ADCOFFTRIM

0x711D1

ADC Offset Trim Register

Reserved

0x711E –0x711F

2

Reserved

The registers in this column are Peripheral Frame 2 Registers.
The ADC result registers are dual mapped in the 280x DSP. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait-states and left
justified. Locations in Peripheral frame 0 space (0x0B00-0x0B0F) are 0 wait sates and right justified. During high-speed/continuous
conversion use of the ADC, use the 0 wait-state locations for fast transfer of ADC results to user memory.

Detailed Description

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6.2.7

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
The CAN module has the following features:• Fully compliant with CAN protocol, version 2.0B
• Supports data rates up to 1 Mbps
• Thirty-two mailboxes, each with the following properties:– Configurable as receive or transmit– Configurable with standard or extended identifier– Has a programmable receive mask
– Supports data and remote frame– Composed of 0 to 8 bytes of data
– Uses a 32-bit time stamp on receive and transmit message– Protects against reception of new message– Holds the dynamically programmable priority of transmit message– Employs a programmable interrupt scheme with two interrupt levels– Employs a programmable alarm on transmission or reception time-out• Low-power mode
• Programmable wake-up on bus activity• Automatic reply to a remote request message• Automatic retransmission of a frame in case of loss of arbitration or error• 32-bit local network time counter synchronized by a specific message (communication in conjunction
with mailbox 16)• Self-test mode
– Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided,
thereby eliminating the need for another node to provide the acknowledge bit.
NOTE
For a SYSCLKOUT of 100 MHz, the smallest bit rate possible is 15.625 kbps.
For a SYSCLKOUT of 60 MHz, the smallest bit rate possible is 9.375 kbps.

Detailed Description
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

eCAN0INT

www.ti.com

eCAN1INT

Controls Address

Data

Enhanced CAN Controller

32

Message Controller
Mailbox RAM(512 Bytes)
32-Message Mailboxof 4 x 32-Bit Words

Memory Management
Unit
32

CPU Interface,
Receive Control Unit,
Timer Management Unit

32

eCAN Memory(512 Bytes)
Registers andMessage Objects Control

32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer

SN65HVD23x
3.3-V CAN Transceiver

CAN BusFigure 6-10. eCAN Block Diagram and Interface Circuit
Table 6-7. 3.3-V eCAN Transceivers

92

PART NUMBER

SUPPLYVOLTAGE

LOW-POWER
MODE

SLOPE
CONTROL

VREF

OTHER

TA

SN65HVD230

3.3 V

StandbyAdjustable

Yes––40°C to 85°C

SN65HVD230Q

3.3 V

StandbyAdjustable

Yes––40°C to 125°C

SN65HVD231

3.3 V

Sleep

Adjustable

Yes––40°C to 85°C

SN65HVD231Q

3.3 V

Sleep

Adjustable

Yes––40°C to 125°C

SN65HVD232

3.3 V

None

None

None

–

–40°C to 85°C

SN65HVD232Q

3.3 V

None

None

None

–

–40°C to 125°C

SN65HVD233

3.3 V

StandbyAdjustable

None

Diagnostic
Loopback–40°C to 125°C

SN65HVD234

3.3 V

Standby & Sleep

Adjustable

None

–

–40°C to 125°C

SN65HVD235

3.3 V

StandbyAdjustable

None

Autobaud
Loopback–40°C to 125°C

Detailed Description

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

eCAN-A Control and Status Registers
Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
Abort Acknowledge - CANAA

eCAN-A Memory (512 Bytes)
6000h

Received Message Pending - CANRMP
Control and Status Registers

603Fh
6040h
607Fh
6080h
60BFh
60C0h
60FFh

Received Message Lost - CANRML
Remote Frame Pending - CANRFP

Local Acceptance Masks (LAM)(32 x 32-Bit RAM)

Global Acceptance Mask - CANGAM

Message Object Time Stamps (MOTS)(32 x 32-Bit RAM)

Bit-Timing Configuration - CANBTC

Message Object Time-Out (MOTO)(32 x 32-Bit RAM)

Transmit Error Counter - CANTEC

Master Control - CANMC
Error and Status - CANES
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1

eCAN-A Memory RAM (512 Bytes)
6100h-6107h

Mailbox 06108h-610Fh

Mailbox 1

6110h-6117h

Mailbox 26118h-611Fh

Mailbox 36120h-6127h

Mailbox 4

Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMILOverwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Time Stamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS

61E0h-61E7h

Mailbox 28

61E8h-61EFh

Mailbox 29

61F0h-61F7h

Mailbox 30

61F8h-61FFh

Mailbox 31

Reserved

Message Mailbox (16 Bytes)
61E8h-61E9h

Message Identifier - MSGID

61EAh-61EBh

Message Control - MSGCTRL

61ECh-61EDh

Message Data Low - MDL

61EEh-61EFh

Message Data High - MDH

Figure 6-11. eCAN-A Memory Map
NOTE
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO,
and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should beenabled for this.

Detailed Description
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

eCAN-B Control and Status Registers
Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
Abort Acknowledge - CANAA

eCAN-B Memory (512 Bytes)
6200h

Received Message Pending - CANRMP
Control and Status Registers

623Fh
6240h
627Fh
6280h
62BFh
62C0h
62FFh

Received Message Lost - CANRML
Remote Frame Pending - CANRFP

Local Acceptance Masks (LAM)(32 x 32-Bit RAM)

Global Acceptance Mask - CANGAM

Message Object Time Stamps (MOTS)(32 x 32-Bit RAM)

Bit-Timing Configuration - CANBTC

Message Object Time-Out (MOTO)(32 x 32-Bit RAM)

Transmit Error Counter - CANTEC

Master Control - CANMC
Error and Status - CANES
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1

eCAN-B Memory RAM (512 Bytes)
6300h-6307h

Mailbox 06308h-630Fh

Mailbox 1

6310h-6317h

Mailbox 26318h-631Fh

Mailbox 36320h-6327h

Mailbox 4

Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMILOverwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Time Stamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS

63E0h-63E7h

Mailbox 28

63E8h-63EFh

Mailbox 29

63F0h-63F7h

Mailbox 30

63F8h-63FFh

Mailbox 31

Reserved

Message Mailbox (16 Bytes)
63E8h-63E9h

Message Identifier - MSGID

63EAh-63EBh

Message Control - MSGCTRL

63ECh-63EDh

Message Data Low - MDL

63EEh-63EFh

Message Data High - MDH

Figure 6-12. eCAN-B Memory Map

94

Detailed Description

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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

The CAN registers listed in Table 6-8 are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 6-8. CAN Register Map (1)REGISTER NAME

eCAN-A
ADDRESSeCAN-BADDRESS

SIZE
(x32)

(1)

DESCRIPTION

CANME

0x60000x62001

Mailbox enable

CANMD

0x60020x6202

1

Mailbox direction

CANTRS

0x60040x6204

1

Transmit request set

CANTRR

0x60060x6206

1

Transmit request reset

CANTA

0x60080x62081

Transmission acknowledge

CANAA

0x600A

0x620A

1

Abort acknowledge

CANRMP

0x600C0x620C

1

Receive message pending

CANRML

0x600E0x620E

1

Receive message lost

CANRFP

0x60100x62101

Remote frame pending

CANGAM

0x60120x6212

1

Global acceptance mask

CANMC

0x60140x6214

1

Master control

CANBTC

0x60160x6216

1

Bit-timing configuration

CANES

0x60180x62181

Error and status

CANTEC

0x601A

0x621A

1

Transmit error counter

CANREC

0x601C

0x621C

1

Receive error counter

CANGIF00x601E0x621E

1

Global interrupt flag 0

CANGIM

0x60200x62201

Global interrupt mask

CANGIF10x60220x6222

1

Global interrupt flag 1

CANMIM

0x60240x62241

Mailbox interrupt mask

CANMIL

0x60260x62261

Mailbox interrupt level

CANOPC

0x60280x62281

Overwrite protection control

CANTIOC

0x602A

0x622A1

TX I/O control

CANRIOC

0x602C

0x622C1

RX I/O control

CANTSC

0x602E0x622E

1Time stamp counter (Reserved in SCC mode)

CANTOC

0x60300x62301Time-out control (Reserved in SCC mode)

CANTOS

0x60320x6232

1

Time-out status (Reserved in SCC mode)

These registers are mapped to Peripheral Frame 1.

Detailed Description
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

6.2.8

www.ti.com

Serial Communications Interface (SCI) Modules (SCI-A, SCI-B)
The 280x devices include two serial communications interface (SCI) modules. The SCI modules support
digital communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own
separate enable and interrupt bits. Both can be operated independently or simultaneously in the fullduplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun,and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baudselect register.
Features of each SCI module include:• Two external pins:– SCITXD: SCI transmit-output pin– SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates:

•

•
•
•
•
•

•
•

•
•

Baud rate =LSPCLK(BRR + 1) * 8

when BRR ¹ 0

Baud rate =LSPCLK
16

when BRR = 0

Data-word format– One start bit– Data-word length programmable from one to eight bits
– Optional even/odd/no parity bit– One or two stop bits
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
100 MHzMax bit rate == 6.25 ´ 106 b/s (for 100 - MHz devices)
16
60 MHzMax bit rate == 3.75 ´ 106 b/s (for 60 - MHz devices)16
NRZ (non-return-to-zero) format
Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTE
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7–0), and the upper byte
(15–8) is read as zeros. Writing to the upper byte has no effect.

96

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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Enhanced features:• Auto baud-detect hardware logic• 16-level transmit/receive FIFOThe SCI port operation is configured and controlled by the registers listed in Table 6-9 and Table 6-10.
Table 6-9. SCI-A Registers (1)NAME

ADDRESSSIZE (x16)

SCICCRA0x70501

SCI-A Communications Control Register

SCICTL1A

0x7051

1

SCI-A Control Register 1

SCIHBAUDA

0x7052

1

SCI-A Baud Register, High Bits

SCILBAUDA

0x7053

1

SCI-A Baud Register, Low Bits

SCICTL2A

0x7054

1

SCI-A Control Register 2

SCIRXSTA

0x7055

1

SCI-A Receive Status Register

SCIRXEMUA

0x7056

1

SCI-A Receive Emulation Data Buffer Register

SCIRXBUFA

0x7057

1

SCI-A Receive Data Buffer Register

SCITXBUFA

0x70591

SCI-A Transmit Data Buffer Register

SCIFFTXA (2)0x705A

1

SCI-A FIFO Transmit Register(2)0x705B

1

SCI-A FIFO Receive Register

SCIFFCTA (2)0x705C1

SCI-A FIFO Control Register

SCIPRIA0x705F

1

SCI-A Priority Control Register

SCIFFRXA(1)(2)

DESCRIPTION

Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
These registers are new registers for the FIFO mode.

Table 6-10. SCI-B Registers (1) (2)NAME

ADDRESSSIZE (x16)

SCICCRB

0x77501

SCI-B Communications Control Register

SCICTL1B

0x7751

1

SCI-B Control Register 1

SCIHBAUDB

0x7752

1

SCI-B Baud Register, High Bits

SCILBAUDB

0x7753

1

SCI-B Baud Register, Low Bits

SCICTL2B

0x7754

1

SCI-B Control Register 2

SCIRXSTB

0x7755

1

SCI-B Receive Status Register

SCIRXEMUB

0x7756

1

SCI-B Receive Emulation Data Buffer Register

SCIRXBUFB

0x7757

1

SCI-B Receive Data Buffer Register

SCITXBUFB

0x77591

SCI-B Transmit Data Buffer Register

SCIFFTXB (2)0x775A

1

SCI-B FIFO Transmit Register(2)0x775B

1

SCI-B FIFO Receive Register

SCIFFCTB (2)0x775C

1

SCI-B FIFO Control Register

SCIPRIB

0x775F

1

SCI-B Priority Control Register

SCIFFRXB(1)(2)

DESCRIPTION

Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
These registers are new registers for the FIFO mode.

Detailed Description
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

Figure 6-13 shows the SCI module block diagram.

SCICTL1.1
Frame Format and Mode

SCITXD

TXSHFRegister

ParityEven/Odd
EnableTX EMPTYSCICTL2.6

8

SCICCR.6 SCICCR.5

TXRDY
SCICTL2.7

Transmitter-Data
Buffer Register
TXWAKESCICTL1.3

WUT

SCICTL2.0
TXINT

TX FIFO _0

TX Interrupt Logic-----

TX FIFO _15

TX
FIFOInterrupts

SCITXBUF.7-0
TX FIFO Registers
SCIFFENASCIHBAUD. 15 - 8
Baud Rate
MSbyteRegister

LSPCLKTX INT ENA

8
TX FIFO _1

1

SCITXDTXENA

To CPUSCI TX Interrupt Select Logic

AutoBaud Detect Logic

SCIFFTX.14
SCIRXDSCIRXDRXSHF Register
RXWAKESCIRXST.1

SCILBAUD. 7 - 0
Baud Rate
LSbyteRegister

RXENA
8SCICTL1.0
SCICTL2.1
RXRDY

Receive-Data
Buffer Register
SCIRXBUF.7-0

RX/BK INT ENASCIRXST.6
BRKDT8SCIRXST.5

RX FIFO _15-----

RX FIFO _1
RX FIFO _0

RX
FIFOInterrupts

RX Interrupt Logic

To CPUSCIRXBUF.7-0
RX FIFO Registers
RXFFOVFSCIRXST.7

SCIRXST.4 - 2

RX Error

FE OE PERXINT

SCIFFRX.15

RX Error
RX ERR INT ENASCI RX Interrupt Select Logic

SCICTL1.6

Figure 6-13. Serial Communications Interface (SCI) Module Block Diagram98

Detailed Description

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6.2.9

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)The 280x devices include the four-pin serial peripheral interface (SPI) module. Up to four SPI modules(SPI-A, SPI-B, SPI-C, and SPI-D) are available. The SPI is a high-speed, synchronous serial I/O port thatallows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of thedevice at a programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include external I/O orperipheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice
communications are supported by the master/slave operation of the SPI.
The SPI module features include:• Four external pins:– SPISOMI: SPI slave-output/master-input pin– SPISIMO: SPI slave-input/master-output pin– SPISTE: SPI slave transmit-enable pin– SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
•

•
•

•
•
•

Two operational modes: master and slave
Baud rate: 125 different programmable rates.
Baud rate =LSPCLK(SPIBRR + 1)

when SPIBRR = 3 to 127

Baud rate =LSPCLK
4

when SPIBRR = 0, 1, 2

Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of thefalling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of therising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7–0), and the upper byte
(15–8) is read as zeros. Writing to the upper byte has no effect.

Enhanced feature:• 16-level transmit/receive FIFO
• Delayed transmit control

Detailed Description
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

The SPI port operation is configured and controlled by the registers listed in Table 6-11 through Table 614.
Table 6-11. SPI-A Registers(1)

DESCRIPTION (1)NAME

ADDRESSSIZE (x16)

SPICCR

0x70401

SPI-A Configuration Control Register

SPICTL0x70411

SPI-A Operation Control Register

SPISTS0x7042

1

SPI-A Status Register

SPIBRR

0x7044

1

SPI-A Baud Rate Register

SPIRXEMU

0x7046

1

SPI-A Receive Emulation Buffer Register

SPIRXBUF

0x7047

1

SPI-A Serial Input Buffer Register

SPITXBUF

0x7048

1

SPI-A Serial Output Buffer Register

SPIDAT

0x70491

SPI-A Serial Data Register

SPIFFTX

0x704A

1

SPI-A FIFO Transmit Register

SPIFFRX0x704B

1

SPI-A FIFO Receive Register

SPIFFCT

0x704C1

SPI-A FIFO Control Register

SPIPRI

0x704F

1

SPI-A Priority Control Register

Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.

Table 6-12. SPI-B Registers

(1)

100

DESCRIPTION (1)NAME

ADDRESSSIZE (x16)

SPICCR

0x77401

SPI-B Configuration Control Register

SPICTL

0x7741

1

SPI-B Operation Control Register

SPISTS0x7742

1

SPI-B Status Register

SPIBRR

0x7744

1

SPI-B Baud Rate Register

SPIRXEMU

0x7746

1

SPI-B Receive Emulation Buffer Register

SPIRXBUF

0x7747

1

SPI-B Serial Input Buffer Register

SPITXBUF

0x7748

1

SPI-B Serial Output Buffer Register

SPIDAT0x77491

SPI-B Serial Data Register

SPIFFTX

0x774A

1

SPI-B FIFO Transmit Register

SPIFFRX0x774B

1

SPI-B FIFO Receive Register

SPIFFCT

0x774C

1

SPI-B FIFO Control Register

SPIPRI

0x774F

1

SPI-B Priority Control Register

Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.

Detailed Description

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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Table 6-13. SPI-C Registers(1)

DESCRIPTION (1)NAME

ADDRESSSIZE (x16)

SPICCR

0x77601

SPI-C Configuration Control Register

SPICTL

0x7761

1

SPI-C Operation Control Register

SPISTS

0x7762

1

SPI-C Status Register

SPIBRR

0x7764

1

SPI-C Baud Rate Register

SPIRXEMU

0x7766

1

SPI-C Receive Emulation Buffer Register

SPIRXBUF

0x7767

1

SPI-C Serial Input Buffer Register

SPITXBUF

0x7768

1

SPI-C Serial Output Buffer Register

SPIDAT

0x77691

SPI-C Serial Data Register

SPIFFTX

0x776A

1

SPI-C FIFO Transmit Register

SPIFFRX0x776B

1

SPI-C FIFO Receive Register

SPIFFCT

0x776C1

SPI-C FIFO Control Register

SPIPRI

0x776F

1

SPI-C Priority Control Register

Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.

Table 6-14. SPI-D Registers(1)

DESCRIPTION (1)NAME

ADDRESSSIZE (x16)

SPICCR

0x7780

1

SPI-D Configuration Control Register

SPICTL

0x7781

1

SPI-D Operation Control Register

SPISTS

0x7782

1

SPI-D Status Register

SPIBRR

0x7784

1

SPI-D Baud Rate Register

SPIRXEMU

0x7786

1

SPI-D Receive Emulation Buffer Register

SPIRXBUF

0x7787

1

SPI-D Serial Input Buffer Register

SPITXBUF

0x7788

1

SPI-D Serial Output Buffer Register

SPIDAT

0x7789

1

SPI-D Serial Data Register

SPIFFTX

0x778A

1

SPI-D FIFO Transmit Register

SPIFFRX0x778B

1

SPI-D FIFO Receive Register

SPIFFCT

0x778C1

SPI-D FIFO Control Register

SPIPRI

0x778F

1

SPI-D Priority Control Register

Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.

Detailed Description
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

Figure 6-14 is a block diagram of the SPI in slave mode.

SPIFFENASPIFFTX.14
OverrunINT ENA

ReceiverOverrun Flag

RX FIFO Registers
SPIRXBUF
RX FIFO _0
RX FIFO _1----RX FIFO _15

SPISTS.7
SPICTL.4
RX
FIFO
Interrupt

RX Interrupt
Logic

16

SPIINT/SPIRXINT

SPIFFOVFFLAGSPIRXBUF Buffer Register

To CPUSPIFFRX.15
TX FIFO Registers
SPITXBUF

TX
FIFO
Interrupt

TX Interrupt
Logic

TX FIFO _15----TX FIFO _1
TX FIFO _0

16

SPI
INT FLAGSPITXINTSPIINT ENASPISTS.6
SPICTL.0

16
SPITXBUF Buffer Register
16

M

M
S

SPIDAT Data RegisterS

SW1

SPISIMO
M

M

SPIDAT.15 - 0

S

S
SW2

SPISOMITalk
SPICTL.1(A)

SPISTE
State Control
Master/Slave
SPI Char

SPICCR.3 - 0
3

2

1

SW3
M

SPI Bit Rate
LSPCLKSPIBRR.6 - 0
6

A.

5

4

3

SPICTL.2

S

0

2

1

0

S

Clock
Polarity
SPICCR.6

Clock
Phase
SPICTL.3

SPICLKM

SPISTE is driven low by the master for a slave device.

Figure 6-14. SPI Module Block Diagram (Slave Mode)

102

Detailed Description

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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

6.2.10 Inter-Integrated Circuit (I2C)
The 280x device contains one I2C Serial Port. Figure 6-15 shows how the I2C peripheral moduleinterfaces within the 280x device.
The I2C module has the following features:• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):– Support for 1-bit to 8-bit format transfers– 7-bit and 10-bit addressing modes– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers– Support for multiple slave-transmitters and master-receivers– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)• One 16-word receive FIFO and one 16-word transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of thefollowing conditions:– Transmit-data ready– Receive-data ready– Register-access ready– No-acknowledgment received– Arbitration lost
– Stop condition detected– Addressed as slave• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable/disable capability• Free data format mode

Detailed Description
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

System Control Block

C28x CPUI2CAENCLKSYSRSControl
Data[16]
SDAA
GPIO
MUX

Peripheral Bus

SYSCLKOUT

Data[16]
I2C-A

Addr[16]SCLA
I2CINT1AI2CINT2A

A.
B.

PIE
Block

The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port arealso at the SYSCLKOUT rate.
The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power
operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.

Figure 6-15. I2C Peripheral Module Interfaces
The registers in Table 6-15 configure and control the I2C port operation.
Table 6-15. I2C-A Registers

104

NAME

ADDRESSI2COAR

0x7900I2C own address register

DESCRIPTION

I2CIER

0x7901I2C interrupt enable register

I2CSTR

0x7902I2C status register

I2CCLKL

0x7903

I2C clock low-time divider register

I2CCLKH

0x7904I2C clock high-time divider register

I2CCNT

0x7905I2C data count register

I2CDRR

0x7906

I2C data receive register

I2CSAR

0x7907

I2C slave address register

I2CDXR

0x7908I2C data transmit register

I2CMDR

0x7909I2C mode register

I2CISRC

0x790AI2C interrupt source register

I2CPSC

0x790CI2C prescaler register

I2CFFTX

0x7920I2C FIFO transmit register

I2CFFRX0x7921I2C FIFO receive register

I2CRSR-I2C receive shift register (not accessible to the CPU)I2CXSR-I2C transmit shift register (not accessible to the CPU)

Detailed Description

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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

6.2.11 GPIO MUXOn the 280x, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO
pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin
is shown in Figure 6-16. Because of the open-drain capabilities of the I2C pins, the GPIO MUX block
diagram for these pins differ. See the TMS320x280x, 2801x, 2804x DSP system control and interrupts
reference guide for details.
GPIOXINT1SELGPIOLMPSELGPIOXINT2SELLPMCR0GPIOXNMISEL

Low-Power
Modes Block

External Interrupt
MUX

PIE

GPxDAT (read)

Asynchronouspath
GPxQSEL1/2
GPxCTRLGPxPUD
Input
Qualification

Internal
Pullup

00

N/C

01

Peripheral 1 Input

10

Peripheral 2 Input

11

Peripheral 3 Input

Asynchronous path

GPxTOGGLE
GPxCLEARGPxSET

GPIOx pin00

GPxDAT (latch)

01

Peripheral 1 Output

10

Peripheral 2 Output

11

Peripheral 3 Output

00

GPxDIR (latch)

High-Impedance
Output Control

0 = Input, 1 = Output
XRS= Default at Reset

A.
B.

01

Peripheral 1 Output Enable

10

Peripheral 2 Output Enable

11

Peripheral 3 Output Enable

GPxMUX1/2

x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
GPxDAT latch/read are accessed at the same memory location.

Figure 6-16. GPIO MUX Block Diagram

Detailed Description
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The 280x supports 34 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1
to enable 32-bit operations on the registers (along with 16-bit operations). Table 6-16 shows the GPIO
register mapping.
Table 6-16. GPIO Registers
NAME

ADDRESSSIZE (x16)

DESCRIPTIONGPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL

0x6F802

GPIO A Control Register (GPIO0 to 31)

GPAQSEL1

0x6F82

2

GPIO A Qualifier Select 1 Register (GPIO0 to 15)

GPAQSEL2

0x6F84

2

GPIO A Qualifier Select 2 Register (GPIO16 to 31)

GPAMUX1

0x6F862

GPIO A MUX 1 Register (GPIO0 to 15)

GPAMUX2

0x6F882

GPIO A MUX 2 Register (GPIO16 to 31)

GPADIR

0x6F8A

2

GPIO A Direction Register (GPIO0 to 31)

GPAPUD

0x6F8C

2

GPIO A Pull Up Disable Register (GPIO0 to 31)

Reserved

0x6F8E –0x6F8F

2

Reserved

GPBCTRL

0x6F902

GPIO B Control Register (GPIO32 to 35)

GPBQSEL1

0x6F92

2

GPIO B Qualifier Select 1 Register (GPIO32 to 35)

GPBQSEL2

0x6F94

2

Reserved

GPBMUX1

0x6F962

GPIO B MUX 1 Register (GPIO32 to 35)

GPBMUX2

0x6F98

2

Reserved

GPBDIR

0x6F9A

2

GPIO B Direction Register (GPIO32 to 35)

GPBPUD

0x6F9C

2

GPIO B Pull Up Disable Register (GPIO32 to 35)

Reserved

0x6F9E –0x6F9F

2

Reserved

Reserved

0x6FA0 –0x6FBF

32

Reserved

GPADAT

0x6FC02

GPIO Data Register (GPIO0 to 31)

GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPASET

0x6FC2

2

GPIO Data Set Register (GPIO0 to 31)

GPACLEAR

0x6FC4

2

GPIO Data Clear Register (GPIO0 to 31)

GPATOGGLE

0x6FC62

GPIO Data Toggle Register (GPIO0 to 31)

GPBDAT

0x6FC82

GPIO Data Register (GPIO32 to 35)

GPBSET

0x6FCA

2

GPIO Data Set Register (GPIO32 to 35)

GPBCLEAR

0x6FCC

2

GPIO Data Clear Register (GPIO32 to 35)

GPBTOGGLE

0x6FCE

2

GPIO Data Toggle Register (GPIO32 to 35)

Reserved

0x6FD0 –0x6FDF

16

Reserved

GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)106

GPIOXINT1SEL

0x6FE01

XINT1 GPIO Input Select Register (GPIO0 to 31)

GPIOXINT2SEL

0x6FE1

1

XINT2 GPIO Input Select Register (GPIO0 to 31)

GPIOXNMISEL

0x6FE2

1

XNMI GPIO Input Select Register (GPIO0 to 31)

Reserved

0x6FE3 –0x6FE7

5

Reserved

GPIOLPMSEL

0x6FE8

2

LPM GPIO Select Register (GPIO0 to 31)

Reserved

0x6FEA –0x6FFF

22

Reserved

Detailed Description

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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Table 6-17. F2808 GPIO MUX Table
GPAMUX1/2 (1)REGISTER
BITS

DEFAULT AT RESETPRIMARY I/O
FUNCTION(GPxMUX1/2
BITS = 0,0)

PERIPHERALSELECTION 1 (2)(GPxMUX1/2 BITS = 0,1)

1–0

GPIO0

3–2

GPIO1

PERIPHERALSELECTION 2(GPxMUX1/2 BITS = 1,0)

PERIPHERALSELECTION 3(GPxMUX1/2 BITS = 1,1)

EPWM1A (O)Reserved (3)Reserved (3)EPWM1B (O)SPISIMOD (I/O)

Reserved (3)GPAMUX1(3)

Reserved (3)

5–4

GPIO2

EPWM2A (O)Reserved

7–6

GPIO3

EPWM2B (O)SPISOMID (I/O)

Reserved (3)

9–8

GPIO4

EPWM3A (O)Reserved (3)Reserved (3)

11–10

GPIO5

EPWM3B (O)SPICLKD (I/O)

ECAP1 (I/O)

13–12

GPIO6

EPWM4A (O)EPWMSYNCI (I)EPWMSYNCO (O)

15–14

GPIO7

EPWM4B (O)SPISTED (I/O)

ECAP2 (I/O)

17–16

GPIO8

EPWM5A (O)CANTXB (O)ADCSOCAO (O)

19–18

GPIO9

EPWM5B (O)SCITXDB (O)ECAP3 (I/O)

21–20

GPIO10EPWM6A (O)CANRXB (I)

ADCSOCBO (O)

23–22

GPIO11EPWM6B (O)SCIRXDB (I)ECAP4 (I/O)

25–24

GPIO12TZ1 (I)CANTXB (O)SPISIMOB (I/O)

27–26

GPIO13TZ2 (I)CANRXB (I)

SPISOMIB (I/O)

29–28

GPIO14TZ3 (I)SCITXDB (O)SPICLKB (I/O)

31–30

GPIO15TZ4 (I)SCIRXDB (I)SPISTEB (I/O)

CANTXB (O)TZ5 (I)GPAMUX2
1–0

GPIO16SPISIMOA (I/O)

3–2

GPIO17SPISOMIA (I/O)

CANRXB (I)TZ6 (I)

5–4

GPIO18SPICLKA (I/O)

SCITXDB (O)Reserved (3)

7–6

GPIO19SPISTEA (I/O)

SCIRXDB (I)

Reserved (3)

9–8

GPIO20

EQEP1A (I)SPISIMOC (I/O)

CANTXB (O)

11–10

GPIO21

EQEP1B (I)

SPISOMIC (I/O)

CANRXB (I)

13–12

GPIO22

EQEP1S (I/O)

SPICLKC (I/O)

SCITXDB (O)

15–14

GPIO23

EQEP1I (I/O)

SPISTEC (I/O)

SCIRXDB (I)

17–16

GPIO24

ECAP1 (I/O)

EQEP2A (I)SPISIMOB (I/O)

19–18

GPIO25

ECAP2 (I/O)

EQEP2B (I)

SPISOMIB (I/O)

21–20

GPIO26

ECAP3 (I/O)

EQEP2I (I/O)

SPICLKB (I/O)

23–22

GPIO27

ECAP4 (I/O)

EQEP2S (I/O)

SPISTEB (I/O)

25–24

GPIO28SCIRXDA (I)

Reserved (3)TZ5 (I)

27–26

GPIO29SCITXDA (O)Reserved (3)TZ6 (I)

29–28

GPIO30CANRXA (I)

Reserved (3)Reserved (3)31–30

GPIO31CANTXA (O)Reserved (3)Reserved (3)1–0

GPIO32SDAA (I/OC)

EPWMSYNCI (I)ADCSOCAO (O)

3–2

GPIO33SCLA (I/OC)

EPWMSYNCO (O)ADCSOCBO (O)

5–4

GPIO34

Reserved (3)Reserved (3)Reserved (3)GPBMUX1

(1)
(2)
(3)

GPxMUX1/2 refers to the appropriate MUX register for the pin; GPAMUX1, GPAMUX2 or GPBMUX1.
This table pertains to the 2808 device. Some peripherals may not be available in the 2809, 2806, 2802, or 2801 devices. See the pin
descriptions for more detail.
The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of
the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.

Detailed Description
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers fromfour choices:• Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0,0): This is the default mode of all GPIO pinsat reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
• Qualification Using Sampling Window (GPxQSEL1/2 = 0,1 and 1,0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before
the input is allowed to change.
Time Between Samples
GPyCTRL Reg

GPIOx

SYNC

Qualification

Input Signal
Qualified by
3 or 6 Samples

GPxQSELSYSCLKOUT
Number of Samples••

Figure 6-17. Qualification Using Sampling Window
The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable ingroups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The
sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL
samples are the same (all 0s or all 1s) as shown in Figure 5-11 (for 6-sample mode).
No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is
not required (synchronization is performed within the peripheral).

Due to the multi-level multiplexing that is required on the 280x device, there may be cases where aperipheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is notselected, the input signal will default to either a 0 or 1 state, depending on the peripheral.

108

Detailed Description

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6.3

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Memory Maps
Block Start
Address

Prog Space

Data Space

0x00 0000

M0 Vector − RAM (32 x 32)(Enabled if VMAP = 0)

ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ

0x00 0040

0x00 0400

M0 SARAM (1K y 16)

M1 SARAM (1K y 16)

0x00 0800
Low 64K [0000 − FFFF](24x/240x equivalent data space)

Peripheral Frame 00x00 0D00

PIE Vector − RAM(256 x 16)(Enabled if ENPIE = 1)

Reserved

0x00 0E00

Reserved

0x00 6000

0x00 7000

Peripheral Frame 1(protected)

Reserved

Peripheral Frame 2(protected)

0x00 8000

L0 SARAM (0-wait)(4K y 16, Secure Zone, Dual-Mapped)

0x00 9000

0x00 A000

L1 SARAM (0-wait)(4K y 16, Secure Zone, Dual-Mapped)
H0 SARAM (0-wait)(8K y 16, Dual-Mapped)

0x00 C000

Reserved

0x3D 7800

0x3D 7C00

OTP(1K y 16, Secure Zone)
Reserved

0x3D 8000

FLASH(128K y 16, Secure Zone)

High 64K [3F0000 − 3FFFFF](24x/240x equivalent program space)

0x3F 7FF8

A.
B.
C.
D.

128-bit Password

0x3F 8000
L0 SARAM (0-wait)(4K y 16, Secure Zone, Dual-Mapped)ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ

0x3F 9000

0x3F A000
0x3F C000

L1 SARAM (0-wait)(4K y 16, Secure Zone, Dual-Mapped)
H0 SARAM (0-wait)(8K y 16, Dual-Mapped)
Reserved

0x3F F000

Boot ROM (4K y 16)

0x3F FFC0

Vectors (32 y 32)(enabled if VMAP = 1, ENPIE = 0)

Memory blocks are not to scale.
Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
Certain memory ranges are EALLOW protected against spurious writes after configuration.

Figure 6-18. F2809 Memory Map

Detailed Description
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.ti.com

Block Start
Address

Prog Space

Data Space

0x00 0000

ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
M0 Vector − RAM (32 x 32)(Enabled if VMAP = 0)0x00 0040

M0 SARAM (1K y 16)

0x00 0400

M1 SARAM (1K y 16)

0x00 0800
Low 64K [0000 − FFFF](24x/240x equivalent data space)

Peripheral Frame 00x00 0D00

PIE Vector − RAM(256 x 16)(Enabled if ENPIE = 1)

Reserved

0x00 0E00

Reserved

0x00 6000

0x00 7000

Peripheral Frame 1(protected)

Reserved

Peripheral Frame 2(protected)

0x00 8000

L0 SARAM (0-wait)(4K y 16, Secure Zone, Dual-Mapped)

0x00 9000

0x00 A000

L1 SARAM (0-wait)(4K y 16, Secure Zone, Dual-Mapped)
H0 SARAM (0-wait)(8K y 16, Dual-Mapped)

0x00 C000

Reserved

0x3D 7800

OTP(1K y 16, Secure Zone)

0x3D 7C00

Reserved

0x3E 8000

High 64K [3F0000 − 3FFFFF](24x/240x equivalent program space)

FLASH(64K y 16, Secure Zone)

A.
B.
C.
D.

0x3F 7FF8128-bit Password

0x3F 8000
L0 SARAM (0-wait)(4K y 16, Secure Zone, Dual-Mapped)ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ

0x3F 9000

0x3F A000

0x3F C000

L1 SARAM (0-wait)(4K y 16, Secure Zone, Dual-Mapped)
H0 SARAM (0-wait)(8K y 16, Dual-Mapped)
Reserved

0x3F F000

Boot ROM (4K y 16)

0x3F FFC0

Vectors (32 y 32)(enabled if VMAP = 1, ENPIE = 0)

Memory blocks are not to scale.
Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
Certain memory ranges are EALLOW protected against spurious writes after configuration.

Figure 6-19. F2808 Memory Map

110

Detailed Description

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Block Start
Address
0x00 0000

Prog Space

Data Space

M0 Vector − RAM (32 x 32)(Enabled if VMAP = 0)

ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ

0x00 0040

M0 SARAM (1K y 16)

0x00 0400

M1 SARAM (1K y 16)

0x00 0800
Low 64K [0000−FFFF](24x/240x equivalent data space)

Peripheral Frame 00x00 0D00

0x00 0E00

PIE Vector − RAM(256 x 16)(Enabled if ENPIE = 1)

Reserved

Reserved

0x00 6000

Peripheral Frame 1(protected)

0x00 7000

Peripheral Frame 2(protected)

0x00 8000

0x00 9000
0x00 A000

Reserved

L0 SARAM (0-wait)(4K y 16, Secure Zone, Dual-Mapped)

L1 SARAM (0-wait)(4K y 16, Secure Zone, Dual-Mapped)

Reserved

0x3D 7800

OTP(1K y 16, Secure Zone)

0x3D 7C00

Reserved

High 64K [3F0000 −3FFFF](24x/240x equivalent program space)

0x3F 0000

0x3F 7FF8C.
D.

128-bit Password

0x3F 8000

L0 SARAM (0-wait)(4K y 16, Secure Zone, Dual-Mapped)

0x3F 9000

L1 SARAM (0-wait)(4K y 16, Secure Zone, Dual-Mapped)

0x3F A000

Reserved

0x3F F000

Boot ROM (4K y 16)

0x3F FFC0

A.
B.

FLASH
(32K y 16, Secure Zone)

Vectors (32 y 32)(enabled if VMAP = 1, ENPIE = 0)

Memory blocks are not to scale.
Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
Certain memory ranges are EALLOW protected against spurious writes after configuration.

Figure 6-20. F2806 Memory Map

Detailed Description
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Block Start
Address
0x00 0000

Data Space

Prog Space

ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
M0 Vector − RAM (32 x 32)(Enabled if VMAP = 0)0x00 0040

M0 SARAM (1K y 16)

Low 64K [0000−FFFF](24x/240x equivalent data space)

0x00 0400
0x00 0800

M1 SARAM (1K y 16)

Peripheral Frame 00x00 0D00

0x00 0E00

PIE Vector − RAM(256 x 16)(Enabled if ENPIE = 1)

Reserved

Reserved

0x00 6000

Peripheral Frame 1(protected)

0x00 7000

0x00 8000

0x00 9000

Reserved

Peripheral Frame 2(protected)

L0 SARAM (0-wait)(4K y 16, Secure Zone, Dual-Mapped)

Reserved

0x3D 7800
0x3D 7C00

OTP (F2802 Only)(A)(1K y 16, Secure Zone)

Reserved

High 64K [3F0000 −3FFFF](24x/240x equivalent program space)

0x3F 0000
0x3F 7FF8
0x3F 8000

D.
E.
F.

128-bit Password

L0 (0-wait)(4K y 16, Secure Zone, Dual-Mapped)

0x3F 9000

Reserved

0x3F F000
0x3F FFC0

A.
B.
C.

FLASH (F2802) or ROM (C2802)(32K y 16, Secure Zone)

Boot ROM (4K y 16)

Vectors (32 y 32)(enabled if VMAP = 1, ENPIE = 0)

The 1K x 16 OTP has been replaced with 1K x 16 ROM in C2802.
Memory blocks are not to scale.
Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
Certain memory ranges are EALLOW protected against spurious writes after configuration.
Some locations in ROM are reserved for TI. See Table 6-22 for more information.

Figure 6-21. F2802, C2802 Memory Map

112

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Block Start
Address
0x00 0000

Data Space

Prog Space

ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
M0 Vector − RAM (32 x 32)(Enabled if VMAP = 0)0x00 0040

Low 64K [0000−FFFF](24x/240x equivalent data space)

0x00 0400
0x00 0800

M0 SARAM (1K y 16)

M1 SARAM (1K y 16)

Peripheral Frame 00x00 0D00

0x00 0E00

PIE Vector − RAM(256 x 16)(Enabled if ENPIE = 1)

Reserved

Reserved

0x00 6000

Peripheral Frame 1(protected)

0x00 7000

0x00 8000

0x00 9000

Peripheral Frame 2(protected)

Reserved

L0 SARAM (0-wait)(4K y 16, Secure Zone, Dual-Mapped)

Reserved

0x3D 7800

0x3D 7C00

OTP (F2801/F2801x Only)(A)(1K y 16, Secure Zone)

Reserved

High 64K [3F0000 −3FFFF](24x/240x equivalent program space)

0x3F 4000
0x3F 7FF8
0x3F 8000

D.
E.
F.

128-bit Password

L0 (0-wait)(4K y 16, Secure Zone, Dual-Mapped)

0x3F 9000

Reserved

0x3F F000
0x3F FFC0

A.
B.
C.

FLASH (F2801) or ROM (C2801)(16K y 16, Secure Zone)

Boot ROM (4K y 16)

Vectors (32 y 32)(enabled if VMAP = 1, ENPIE = 0)

The 1K x 16 OTP has been replaced with 1K x 16 ROM in C2801.
Memory blocks are not to scale.
Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
Certain memory ranges are EALLOW protected against spurious writes after configuration.
Some locations in ROM are reserved for TI. See Table 6-22 for more information.

Figure 6-22. F2801, F28015, F28016, C2801 Memory Map

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Table 6-18. Addresses of Flash Sectors in F2809
ADDRESS RANGEPROGRAM AND DATA SPACE

0x3D 8000 – 0x3D BFFF

Sector H (16K x 16)

0x3D C000 – 0x3D FFFF

Sector G (16K x 16)

0x3E 0000 – 0x3E 3FFF

Sector F (16K x 16)

0x3E 4000 – 0x3E 7FFF

Sector E (16K x 16)

0x3E 8000 – 0x3E BFFF

Sector D (16K x 16)

0x3E C000 – 0x3E FFFF

Sector C (16K x 16)

0x3F 0000 – 0x3F 3FFF

Sector B (16K x 16)

0x3F 4000 – 0x3F 7F7F

Sector A (16K x 16)

0x3F 7F80 – 0x3F 7FF5

Program to 0x0000 when using theCode Security Module

0x3F 7FF6 – 0x3F 7FF7

Boot-to-Flash Entry Point(program branch instruction here)

0x3F 7FF8 – 0x3F 7FFF

Security Password (128-Bit)(Do not program to all zeros)

Table 6-19. Addresses of Flash Sectors in F2808
ADDRESS RANGEPROGRAM AND DATA SPACE

0x3E 8000 – 0x3E BFFF

Sector D (16K x 16)

0x3E C000 – 0x3E FFFF

Sector C (16K x 16)

0x3F 0000 – 0x3F 3FFF

Sector B (16K x 16)

0x3F 4000 – 0x3F 7F7F

Sector A (16K x 16)

0x3F 7F80 – 0x3F 7FF5

Program to 0x0000 when using theCode Security Module

0x3F 7FF6 – 0x3F 7FF7

Boot-to-Flash Entry Point(program branch instruction here)

0x3F 7FF8 – 0x3F 7FFF

Security Password (128-Bit)(Do not program to all zeros)

Table 6-20. Addresses of Flash Sectors in F2806, F2802

114

Detailed Description

ADDRESS RANGEPROGRAM AND DATA SPACE

0x3F 0000 – 0x3F 1FFF

Sector D (8K x 16)

0x3F 2000 – 0x3F 3FFF

Sector C (8K x 16)

0x3F 4000 – 0x3F 5FFF

Sector B (8K x 16)

0x3F 6000 – 0x3F 7F7F

Sector A (8K x 16)

0x3F 7F80 – 0x3F 7FF5

Program to 0x0000 when using theCode Security Module

0x3F 7FF6 – 0x3F 7FF7

Boot-to-Flash Entry Point(program branch instruction here)

0x3F 7FF8 – 0x3F 7FFF

Security Password (128-Bit)(Do not program to all zeros)

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Table 6-21. Addresses of Flash Sectors in F2801, F28015, F28016
ADDRESS RANGEPROGRAM AND DATA SPACE

0x3F 4000 – 0x3F 4FFF

Sector D (4K x 16)

0x3F 5000 – 0x3F 5FFF

Sector C (4K x 16)

0x3F 6000 – 0x3F 6FFF

Sector B (4K x 16)

0x3F 7000 – 0x3F 7F7F

Sector A (4K x 16)

0x3F 7F80 – 0x3F 7FF5

Program to 0x0000 when using theCode Security Module

0x3F 7FF6 – 0x3F 7FF7

Boot-to-Flash Entry Point(program branch instruction here)

0x3F 7FF8 – 0x3F 7FFF

Security Password (128-Bit)(Do not program to all zeros)

NOTE•

When the code-security passwords are programmed, all addresses between 0x3F7F80
and 0x3F7FF5 cannot be used as program code or data. These locations must be
programmed to 0x0000.
• If the code security feature is not used, addresses 0x3F7F80 through 0x3F7FEF may be
used for code or data. Addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data andshould not contain program code.
• On ROM devices, addresses 0x3F7FF0 – 0x3F7FF5 and 0x3D7BFC – 0x3D7BFF arereserved for TI, irrespective of whether code security has been used or not. User
application should not use these locations in any way.
Table 6-22 shows how to handle these memory locations.

Table 6-22. Impact of Using the Code Security Module
ADDRESS
0x3F 7F80 – 0x3F 7FEF
0x3F 7FF0 – 0x3F 7FF5
0x3D 7BFC – 0x3D 7BFF

FLASH
Code security enabled
Fill with 0x0000

ROM

Code security disabled

Code security enabled

Code security disabled

Application code and data

Fill with 0x0000

Application code and data

Reserved for data only

Application code and data

Reserved for TI. Do not use.

Peripheral Frame 1 and Peripheral Frame 2 are grouped together so as to enable these blocks to bewrite/read peripheral block protected. The protected mode ensures that all accesses to these blocks
happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different
memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems
in certain peripheral applications where the user expected the write to occur first (as written). The C28x
CPU supports a block protection mode where a region of memory can be protected so as to make surethat operations occur as written (the penalty is extra cycles are added to align the operations). This modeis programmable and by default, it will protect the selected zones.

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The wait-states for the various spaces in the memory map area are listed in Table 6-23.
Table 6-23. Wait-states

116

AREA

WAIT-STATES

M0 and M1 SARAMs

0-waitFixedCOMMENTS

Peripheral Frame 00-waitFixed

Peripheral Frame 1

0-wait (writes)
2-wait (reads)

Fixed. The eCAN peripheral can extend a cycle as needed.
Back-to-back writes will introduce a 1-cycle delay.

Peripheral Frame 20-wait (writes)
2-wait (reads)

Fixed

L0 and L1 SARAMs

0-wait

OTP

Programmed via the Flash registers. 1-wait-state operation
Programmable,
is possible at a reduced CPU frequency. See Section 6.1.5
1-wait minimum
for more information.

Flash

Programmed via the Flash registers. 0-wait-state operation
Programmable, is possible at reduced CPU frequency. The CSM password
0-wait minimum locations are hardwired for 16 wait-states. See
Section 6.1.5 for more information.

H0 SARAM

0-waitFixed

Boot-ROM

1-waitFixed

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6.4

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Register Map
The 280x devices contain three peripheral register spaces. The spaces are categorized as follows:
Peripheral
Frame 0:

These are peripherals that are mapped directly to the CPU memory bus.
See Table 6-24.

Peripheral
Frame 1

These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 6-25.

Peripheral
Frame 2:

These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 6-26.
Table 6-24. Peripheral Frame 0 Registers (1) (2)NAME

ACCESS TYPE (3)ADDRESS RANGESIZE (x16)

Device Emulation Registers

0x0880 – 0x09FF

384

EALLOW protected

FLASH Registers (4)0x0A80 – 0x0ADF

96

EALLOW protected
CSM Protected

Code Security Module Registers

0x0AE0 – 0x0AEF

16

EALLOW protected

ADC Result Registers (dual-mapped)

0x0B00 – 0x0B0F

16

Not EALLOW protected

CPU-TIMER0/1/2 Registers

0x0C00 – 0x0C3F

64

Not EALLOW protected

PIE Registers

0x0CE0 – 0x0CFF

32

Not EALLOW protected

PIE Vector Table

0x0D00 – 0x0DFF

256

EALLOW protected

(1)
(2)
(3)
(4)

Registers in Frame 0 support 16-bit and 32-bit accesses.
Missing segments of memory space are reserved and should not be used in applications.
If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
The Flash Registers are also protected by the Code Security Module (CSM).

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Table 6-25. Peripheral Frame 1 Registers (1) (2)NAME

ADDRESS RANGESIZE (x16)

ACCESS TYPE

eCANA Registers

0x6000 – 0x60FF

256

Some eCAN control registers (and selected
bits in other eCAN control registers) are
EALLOW-protected.

eCANA Mailbox RAM

0x6100 – 0x61FF

256

Not EALLOW-protected

eCANB Registers

0x6200 – 0x62FF

256

Some eCAN control registers (and selected
bits in other eCAN control registers) are
EALLOW-protected.

eCANB Mailbox RAM

0x6300 – 0x63FF

256

Not EALLOW-protected

ePWM1 Registers

0x6800 – 0x683F

64

ePWM2 Registers

0x6840 – 0x687F

64

ePWM3 Registers

0x6880 – 0x68BF

64

ePWM4 Registers

0x68C0 – 0x68FF

64

ePWM5 Registers

0x6900 – 0x693F

64

ePWM6 Registers

0x6940 – 0x697F

64

eCAP1 Registers

0x6A00 – 0x6A1F

32

eCAP2 Registers

0x6A20 – 0x6A3F

32

eCAP3 Registers

0x6A40 – 0x6A5F

32

eCAP4 Registers

0x6A60 – 0x6A7F

32

eQEP1 Registers

0x6B00 – 0x6B3F

64

eQEP2 Registers

0x6B40 – 0x6B7F

64

GPIO Control Registers

0x6F80 – 0x6FBF

128

EALLOW protected

GPIO Data Registers

0x6FC0 – 0x6FDF

32

Not EALLOW protected

GPIO Interrupt and LPM Select Registers

0x6FE0 – 0x6FFF

32

EALLOW protected

(1)
(2)

Some ePWM registers are EALLOW
protected. See Table 6-3.

Not EALLOW protected

The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
Missing segments of memory space are reserved and should not be used in applications.

Table 6-26. Peripheral Frame 2 Registers (1) (2)
ADDRESS RANGESIZE (x16)System Control Registers

NAME

0x7010 – 0x702F

32

SPI-A Registers

0x7040 – 0x704F

16

SCI-A Registers

0x7050 – 0x705F

16

External Interrupt Registers

0x7070 – 0x707F

16

ADC Registers

0x7100 – 0x711F

32

SPI-B Registers

0x7740 – 0x774F

16

SCI-B Registers

0x7750 – 0x775F

16

SPI-C Registers

0x7760 – 0x776F

16

SPI-D Registers

0x7780 – 0x778F

16

I2C Registers

0x7900 – 0x792F

48

(1)
(2)

118

ACCESS TYPE
EALLOW Protected

Not EALLOW Protected

Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
Missing segments of memory space are reserved and should not be used in applications.

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6.4.1

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some criticaldevice signals. The registers are defined in Table 6-27.
Table 6-27. Device Emulation Registers
ADDRESSRANGE

SIZE (x16)

DEVICECNF

0x08800x0881

2

Device Configuration Register

PARTID

0x0882

1

Part ID Register

0x002C (1) - F2801
0x0024 – F2802
0x0034 – F2806
0x003C – F2808
0x00FE – F2809
0x0014 – F28016
0x001C – F28015
0xFF2C – C2801
0xFF24 – C2802

REVID

0x0883

1

Revision ID Register

0x0000 – Silicon Rev. 0 – TMX
0x0001 – Silicon Rev. A – TMX
0x0002 – Silicon Rev. B – TMS
0x0003 – Silicon Rev. C – TMS

Revision ID Register

0x0000 – Silicon rev. 0 – TMS (F2809 only)
0x0001 – Silicon rev. A – TMS (F2809 only)NAME

DESCRIPTIONPROTSTART

0x0884

1

Block Protection Start Address Register

PROTRANGE

0x0885

1

Block Protection Range Address Register(1)

The first byte (00) denotes flash devices. FF denotes ROM devices. Other values are reserved for future devices.

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Interrupts
Figure 6-23 shows how the various interrupt sources are multiplexed within the 280x devices.
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with
8 interrupts per group equals 96 possible interrupts. On the 280x, 43 of these are used by peripherals asshown in Table 6-28.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine
corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address
pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore,
TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service
routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector
from INT1.1, TRAP #2 fetches the vector from INT2.1 and so forth.

120

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Peripherals(SPI, SCI, I2C, eCAN, ePWM, eCAP, eQEP, ADC)WDINT

WAKEINT

XINT1

XINT1

Interrupt Control

Watchdog
Low-Power ModesMUX

LPMINT

96 Interrupts

XINT1CTR(15:0)
GPIOXINT1SEL(4:0)

ADC
XINT2

XINT2SOC
XINT2Interrupt Control

MUX

INT1
to
INT12

PIE

XINT1CR(15:0)

XINT2CR(15:0)

C28x
CPU

XINT2CTR(15:0)
GPIOXINT2SEL(4:0)

TINT0
CPU TIMER 0
TINT2

INT14

CPU TIMER 2 (Reserved for SYS/BIOS)

TINT1

MUX

INT13

CPU TIMER 1

int13_select
GPIO0.int
XNMI_XINT13

MUX

NMI

Interrupt Control

MUX

nmi_selectXNMICR(15:0)

GPIO
MUX
GPIO31.int

1
XNMICTR(15:0)
GPIOXNMISEL(4:0)

Figure 6-23. External and PIE Interrupt Sources

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IFR[12:1]

INTM

IER[12:1]

INT1
INT2
1
MUX
INT11
INT12
(Flag)

INTx

GlobalEnable(Enable)INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8MUXPIEACKx(Enable/Flag)(Enable)(Flag)

PIEIERx[8:1]

PIEIFRx[8:1]

CPU
0

From
PeripheralsorExternal
Interrupts

Figure 6-24. Multiplexing of Interrupts Using the PIE Block
Table 6-28. PIE Peripheral Interrupts (1)CPU
INTERRUPTS

(1)

(2)

122

PIE INTERRUPTS
INTx.8

INTx.7

INTx.6

INTx.5

INT1

WAKEINT(LPM/WD)

TINT0(TIMER 0)

ADCINT (2)
(ADC)

INT2

Reserved

Reserved

EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT(ePWM6)(ePWM5)(ePWM4)(ePWM3)(ePWM2)(ePWM1)

INT3

Reserved

Reserved

EPWM6_INT(ePWM6)EPWM5_INT(ePWM5)EPWM4_INT(ePWM4)EPWM3_INT(ePWM3)EPWM2_INT(ePWM2)EPWM1_INT(ePWM1)

INT4

Reserved

Reserved

Reserved

Reserved

ECAP4_INT(eCAP4)

ECAP3_INT(eCAP3)

ECAP2_INT(eCAP2)

ECAP1_INT(eCAP1)

INT5

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

EQEP2_INT(eQEP2)

EQEP1_INT(eQEP1)INT6SPITXINTD(SPI-D)SPIRXINTD(SPI-D)SPITXINTC(SPI-C)SPIRXINTC(SPI-C)SPITXINTB(SPI-B)SPIRXINTB(SPI-B)SPITXINTA(SPI-A)SPIRXINTA(SPI-A)

INT7

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved
I2CINT1A(I2C-A)XINT2

INTx.4
XINT1

INTx.3

INTx.2

INTx.1

Reserved

SEQ2INT(ADC)

SEQ1INT
(ADC)

INT8

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

I2CINT2A(I2C-A)

INT9

ECAN1_INTB(CAN-B)

ECAN0_INTB(CAN-B)ECAN1_INTA(CAN-A)

ECAN0_INTA(CAN-A)SCITXINTB(SCI-B)SCIRXINTB(SCI-B)SCITXINTA(SCI-A)SCIRXINTA(SCI-A)

INT10

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

INT11

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

INT12

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Out of the 96 possible interrupts, 43 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 12).
ADCINT is sourced as a logical "OR" of both the SEQ1INT and SEQ2INT signals. This is to support backward compatibility with theimplementation found on the TMS320F281x series of devices, where SEQ1INT and SEQ2INT did not exist, only ADCINT. For new
implementations, TI recommends using SEQ1INT and SEQ2INT and not enabling ADCINT in the PIEIER register.

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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Table 6-29. PIE Configuration and Control RegistersNAME

DESCRIPTION (1)ADDRESSSIZE (x16)PIECTRL

0x0CE01

PIE, Control Register

PIEACK

0x0CE1

1

PIE, Acknowledge Register

PIEIER1

0x0CE2

1

PIE, INT1 Group Enable Register

PIEIFR1

0x0CE3

1

PIE, INT1 Group Flag Register

PIEIER2

0x0CE4

1

PIE, INT2 Group Enable Register

PIEIFR2

0x0CE5

1

PIE, INT2 Group Flag Register

PIEIER3

0x0CE6

1

PIE, INT3 Group Enable Register

PIEIFR3

0x0CE7

1

PIE, INT3 Group Flag Register

PIEIER4

0x0CE8

1

PIE, INT4 Group Enable Register

PIEIFR4

0x0CE91

PIE, INT4 Group Flag Register

PIEIER5

0x0CEA

1

PIE, INT5 Group Enable Register

PIEIFR5

0x0CEB

1

PIE, INT5 Group Flag Register

PIEIER6

0x0CEC

1

PIE, INT6 Group Enable Register

PIEIFR6

0x0CED

1

PIE, INT6 Group Flag Register

PIEIER7

0x0CEE

1

PIE, INT7 Group Enable Register

PIEIFR7

0x0CEF

1

PIE, INT7 Group Flag Register

PIEIER8

0x0CF01

PIE, INT8 Group Enable Register

PIEIFR8

0x0CF1

1

PIE, INT8 Group Flag Register

PIEIER90x0CF2

1

PIE, INT9 Group Enable Register

PIEIFR90x0CF3

1

PIE, INT9 Group Flag Register

PIEIER10

0x0CF4

1

PIE, INT10 Group Enable Register

PIEIFR10

0x0CF5

1

PIE, INT10 Group Flag Register

PIEIER11

0x0CF6

1

PIE, INT11 Group Enable Register

PIEIFR11

0x0CF7

1

PIE, INT11 Group Flag Register

PIEIER12

0x0CF8

1

PIE, INT12 Group Enable Register

PIEIFR12

0x0CF91

PIE, INT12 Group Flag Register

Reserved

0x0CFA –0x0CFF

6

Reserved(1)

The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector tableis protected.

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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

6.5.1

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External Interrupts

Table 6-30. External Interrupt Registers
NAME

ADDRESSSIZE (x16)0x70701

XINT1 control register

XINT2CR

0x7071

1

XINT2 control register

Reserved

0x7072 – 0x7076

5

ReservedXNMICR

0x7077

1

XNMI control register

XINT1CTR

0x7078

1

XINT1 counter register

XINT2CTR

0x70791

XINT2 counter register

Reserved

0x707A – 0x707E

5ReservedXNMICTR0x707F1

XNMI counter register

XINT1CRDESCRIPTION

Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive andnegative edge. For more information, see the TMS320x280x, 2801x, 2804x DSP system control andinterrupts reference guide.

124

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6.6

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

System Control
This section describes the 280x oscillator, PLL and clocking mechanisms, the watchdog function and thelow power modes. Figure 6-25 shows the various clock and reset domains in the 280x devices that will be
discussed.
Reset
XRS

Watchdog
Block

(A)

SYSCLKOUT

Peripheral Reset
CLKIN

X1

(A)

Peripheral Bus

28x
CPU

PLL

OSC

Power
Modes
Control

Peripheral
Registers

CPU
TimersSystemControl
Registers

Clock Enables

Peripheral
Registers

ePWM 1/2/3/4/5/6
eCAP 1/2/3/4 eQEP 1/2

I/O

Peripheral
Registers

eCAN-A/B
I2C-A

I/O

X2

XCLKIN

GPIO
MUX

GPIOs

Low-Speed Prescaler
LSPCLK
Peripheral
Registers

Low-Speed Peripherals
SCI-A/B, SPI-A/B/C/D

I/O

High-Speed Prescaler
HSPCLK
ADC
RegistersA.

12-Bit ADC

16 ADC Inputs

CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT).

Figure 6-25. Clock and Reset Domains

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The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 6-31.
Table 6-31. PLL, Clocking, Watchdog, and Low-Power Mode Registers (1)NAME

ADDRESSSIZE (x16)0x7010

1

XCLKOUT Pin Control, X1 and XCLKIN Status Register

PLLSTS

0x7011

1

PLL Status Register

Reserved

0x7012 – 0x7019

8

Reserved

HISPCP

0x701A

1

High-Speed Peripheral Clock Prescaler Register (for HSPCLK)LOSPCP

0x701B

1

Low-Speed Peripheral Clock Prescaler Register (for LSPCLK)PCLKCR00x701C

1

Peripheral Clock Control Register 0

PCLKCR10x701D

1

Peripheral Clock Control Register 1

LPMCR00x701E

1

Low-Power Mode Control Register 0

Reserved

0x701F – 0x7020

1

Reserved

PLLCR

0x7021

1

PLL Control Register

SCSR

0x7022

1

System Control and Status Register

WDCNTR

0x7023

1

Watchdog Counter Register

Reserved

0x7024

1

Reserved

WDKEY

0x7025

1

Watchdog Reset Key Register

Reserved

0x7026 – 0x7028

3

Reserved

WDCR

0x70291

Watchdog Control Register

Reserved

0x702A – 0x702F

6

Reserved

XCLK

(1)

126

DESCRIPTION

All of the registers in this table are EALLOW protected.

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6.6.1

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

OSC and PLL Block
Figure 6-26 shows the OSC and PLL block on the 280x.

XCLKIN
(3.3-V Clock Input)

OSCCLKOSCCLKXOR
PLLSTS[OSCOFF]PLLVCOCLKOSCCLKor
VCOCLK0nn0

PLLSTS[PLLOFF]

CLKIN

/2

PLLSTS[CLKINDIV]

X1
On-Chip
Oscillator

4-bit PLL Select(PLLCR)

X2

Figure 6-26. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the 280x devices using the X1
and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of thefollowing configurations:
1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied low. The logic-high level in this case should not exceed VDDIO.
2. A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left
unconnected and the XCLKIN pin tied low. The logic-high level in this case should not exceed VDD.
The three possible input-clock configurations are shown in Figure 6-27 through Figure 6-29.
XCLKIN

X1

X2

NC

External Clock Signal(Toggling 0-VDDIO)

Figure 6-27. Using a 3.3-V External Oscillator
XCLKIN

X1

X2

External Clock Signal(Toggling 0-VDD)

NC

Figure 6-28. Using a 1.8-V External Oscillator
XCLKIN

X1

X2

CL1

CL2
CrystalFigure 6-29. Using the Internal Oscillator

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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

6.6.1.1

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External Reference Oscillator Clock Option

The typical specifications for the external quartz crystal for a frequency of 20 MHz are listed below:• Fundamental mode, parallel resonant• CL (load capacitance) = 12 pF• CL1 = CL2 = 24 pF• Cshunt = 6 pF
• ESR range = 30 to 60 Ω
TI recommends that customers have the resonator/crystal vendor characterize the operation of theirdevice with the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tankcircuit. The vendor can also advise the customer regarding the proper tank component values that willproduce proper start up and stability over the entire operating range.
6.6.1.2

PLL-Based Clock Module

The 280x devices have an on-chip, PLL-based clock module. This module provides all the necessary
clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio
control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before
writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, whichtakes 131072 OSCCLK cycles.
Table 6-32. PLLCR Register Bit Definitions
SYSCLKOUT(CLKIN) (2)

PLLCR[DIV] (1)

(1)
(2)

0000 (PLL bypass)

OSCCLK/n

0001(OSCCLK*1)/n0010(OSCCLK*2)/n0011(OSCCLK*3)/n0100(OSCCLK*4)/n

0101(OSCCLK*5)/n0110(OSCCLK*6)/n0111(OSCCLK*7)/n

1000(OSCCLK*8)/n

1001(OSCCLK*9)/n1010(OSCCLK*10)/n1011–1111

Reserved

This register is EALLOW protected.
CLKIN is the input clock to the CPU. SYSCLKOUT is the output
clock from the CPU. The frequency of SYSCLKOUT is the same as
CLKIN. If CLKINDIV = 0, n = 2; if CLKINDIV = 1, n = 1.

NOTE
PLLSTS[CLKINDIV] enables or bypasses the divide-by-two block before the clock is fed tothe core. This bit must be 0 before writing to the PLLCR and must only be set after
PLLSTS[PLLLOCKS] = 1.

128

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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

The PLL-based clock module provides two modes of operation:• Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time baseto the device.
• External clock source operation - This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1 or the XCLKIN pin.
Table 6-33. Possible PLL Configuration Modes
REMARKSPLLSTS[CLKINDIV]SYSCLKOUT(CLKIN)0OSCCLK/2

PLL Off

Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL blockis disabled in this mode. This can be useful to reduce system noise and for low
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.

1

OSCCLK

PLL Bypass is the default PLL configuration upon power-up or after an external
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.

0

OSCCLK/2

PLL Bypass

1

OSCCLKPLL Enable

Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.

0

OSCCLK*n/2

PLL MODE

6.6.1.3

Loss of Input ClockIn PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still
issue a limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typicalfrequency of 1–5 MHz. Limp mode is not specified to work from power-up, only after input clocks havebeen present initially. In PLL bypass mode, the limp mode clock from the PLL is automatically routed to
the CPU if the input clock is removed or absent.
Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog
reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter stops
decrementing (that is, the watchdog counter does not change with the limp-mode clock). In addition tothis, the device will be reset and the “Missing Clock Status” (MCLKSTS) bit will be set. These conditions
could be used by the application firmware to detect the input clock failure and initiate necessary shut-down
procedure for the system.
NOTE
Applications in which the correct CPU operating frequency is absolutely critical should
implement a mechanism by which the DSP will be held in reset, should the input clocks everfail. For example, an R-C circuit may be used to trigger the XRS pin of the DSP, should thecapacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on aperiodic basis to prevent it from getting fully charged. Such a circuit would also help in
detecting failure of the flash memory and the VDD3VFL rail.

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Watchdog Block
The watchdog block on the 280x is similar to the one used on the 240x and 281x devices. The watchdog
module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up
counter has reached its maximum value. To prevent this, the user disables the counter or the softwaremust periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset thewatchdog counter. Figure 6-30 shows the various functional blocks within the watchdog module.
WDCR (WDPS[2:0])

WDCR (WDDIS)
WDCNTR[7:0]

OSCCLK

Watchdog
Prescaler

/512

WDCLK

8-Bit
Watchdog
Counter
CLR
Clear Counter

Internal
Pullup
WDKEY[7:0]
Watchdog
55 + AAKey Detector

Generate
Output Pulse(512 OSCCLKs)

Good Key

WDRST
WDINT

XRS
Core-reset

Bad
WDCHK
Key

SCSR (WDENINT)WDCR (WDCHK[2:0])

(A)

WDRST

A.

1

0

1

The WDRST signal is driven low for 512 OSCCLK cycles.

Figure 6-30. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the
LPM block so that it can wake the device from STANDBY (if enabled). See Section 6.7, Low-Power
Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence sois the WATCHDOG.

130

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6.7

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

Low-Power Modes Block
The low-power modes on the 280x are similar to the 240x devices. Table 6-34 summarizes the various
modes.
Table 6-34. Low-Power Modes

MODE

LPMCR0(1:0)

OSCCLK

CLKIN

SYSCLKOUT

EXIT (1)

IDLE

00

On

On

On (2)XRS, Watchdog interrupt, any enabledinterrupt, XNMISTANDBY

01

On(watchdog still running)

Off

Off

XRS, Watchdog interrupt, GPIO Port A
signal, debugger (3), XNMI

HALT

1X

Off
(oscillator and PLL turned off,
watchdog not functional)

Off

Off

XRS, GPIO Port A signal, XNMI,
debugger (3)

(1)
(2)
(3)

The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, willexit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the
IDLE mode will not be exited and the device will go back into the indicated low power mode.
The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is
still functional while on the 24x/240x the clock is turned off.
On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.

The various low-power modes operate as follows:
IDLE Mode:

This mode is exited by any enabled interrupt or an XNMI that is recognizedby the processor. The LPM block performs no tasks during this mode aslong as the LPMCR0(LPM) bits are set to 0,0.

STANDBY Mode:

Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY
mode. The user must select which signal(s) will wake the device in the
GPIOLPMSEL register. The selected signal(s) are also qualified by the
OSCCLK before waking the device. The number of OSCCLKs is specified in
the LPMCR0 register.

HALT Mode:

Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake thedevice from HALT mode. The user selects the signal in the GPIOLPMSEL
register.
NOTE

The low-power modes do not affect the state of the output pins (PWM pins included). They
will be in whatever state the code left them in when the IDLE instruction was executed. See
the TMS320x280x, 2801x, 2804x DSP system control and interrupts reference guide formore details.

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7 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

7.1

TI Design or Reference Design
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processor, and connectivity. Created by TI experts to help you jump start your system design, all TI
Designs include schematic or block diagrams, BOMs, and design files to speed your time to market.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
www.tij.co.jp

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

8 デバイスおよびドキュメントのサポート
8.1

はじめに
このセクションでは、C28xデバイス用の開発を最初に行うときの手順について、概要を簡単に説明します。各手順の詳細については、次の資料を参照してください。
• 「C2000 リアルタイム制御MCU - はじめに」• 「C2000 リアルタイム制御MCU - ツールおよびソフトウェア」
ステップ 1.適適切な開発ツールの入手
C28x デバイスを使い始めるための一番の近道は、初期開発用の eZdsp™キットを入手することです。このパッケー
ジには、次のものが含まれています。
• USB またはパラレル・ポート経由のオンポート JTAG エミュレーション• 適切なエミュレーション・ドライバ• Code Composer Studio™ IDE for eZdsp
デバイスをよく理解し、独自ハードウェアの開発を始めた後で、ソフトウェア開発用の Code Composer Studio™
IDE と JTAG エミュレーション・ツールを別に購入し、プロジェクトを開始できます。
ステップ 2.ススタータ・ソフトウェアのダウンロード
C28x デバイスのプログラミングを簡素化するため、C/C++ ヘッダー・ファイルとサンプルをダウンロードし、それらを使って C28x デバイスと各種ペリフェラルのソフトウェア開発を始めることを推奨します。
デバイスに対して適切なヘッダー・ファイル・パッケージをダウンロードした後で、次の資料に記載されている詳細手順に従い、ペリフェラルのサンプルを実行し、ヘッダー・ファイルの構造を自分のソフトウェアに使用します。
• /doc ディレクトリにある Quick Start Readme を参照して、最初のアプリケーションを実行します。
• 『C/C++でのTMS320x28xxおよび28xxxペリフェラルのプログラミング』アプリケーション・レポート
ステップ 3.フフラッシュ・プログラミング・ソフトウェアのダウンロード
多くの C28x デバイスにはフラッシュ・メモリが内蔵され、ユーザーのソフトウェア IP をフラッシュにプログラムするためのツールが付属しています。
• フラッシュ・ツール：C28x フラッシュ・ツール
• 『TMS320F281x™ フラッシュ・プログラミング・ソリューション』• 『TMS320F28xxx DSP の内部フラッシュ・メモリからアプリケーションを実行する』
ステップ 4.よより高度なトピックへの移行
アプリケーション・ソフトウェアや、他の高度なトピックについては、「C2000 リアルタイム制御マイコン – ツールとソフ
トウェア」を参照してください。

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133

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
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JAJS280O – OCTOBER 2003 – REVISED MARCH 20198.2

www.tij.co.jp

デバイスおよび開発ツールの項目表記
製品開発サイクルの段階を示すために、TIでは TMS320™ DSP デバイスおよびサポート・ツールの型番に接頭辞を使用しています。それぞれの TMS320™ DSP の民生用ファミリの各製品には、TMX、TMP、TMS のいずれかの接頭辞があります (たとえば、TMS320F2808)。テキサス・インスツルメンツでは、サポート・ツールに使用可能な3つの接頭辞のうち、TMDXおよびTMDSの2つを推奨しています。これらの接頭辞は、製品開発の進展段階を表します。段階には、エンジニアリング・プロトタイプ(TMX/TMDX)から、認定済み製品デバイス/ツール(TMS/TMDS)があります。
デバイス開発の段階は次のとおりです。
TMX

実験的デバイスで、最終デバイスの電気的特性を必ずしも表しません。

TMP

最終的なシリコン・ダイで、デバイスの電気的特性に適合しますが、品質および信頼性の検証は完了していません。

TMS

完全に認定済みの量産版デバイスです。

サポート・ツール開発の段階は次のとおりです。
TMDX 開発サポート製品で、テキサス・インスツルメンツの社内認定試験はまだ完了していません。
TMDS 完全に認定済みの開発サポート製品です。
TMXおよびTMPデバイスと、TMDX開発サポート・ツールは、以下の免責事項の下で出荷されます。
「開発段階の製品は、社内での評価を目的としたものです」
TMSデバイスとTMDS開発サポート・ツールの特性は完全に明確化されており、デバイスの品質と信頼性が十分に示されてきました。TIの標準保証が適用されます。
プロトタイプ・デバイス(TMXまたはTMP)の方が標準的な製品版デバイスに比べて故障率が大きいと予測されます。
これらのデバイスは予測される最終使用時の故障率が未定義であるため、テキサス・インスツルメンツではそれらのデバイスを量産システムで使用しないよう推奨しています。認定された量産デバイスのみを使用する必要があります。
TIデバイスの項目表記には、デバイス・ファミリ名の接尾辞も含まれます。この接尾辞は、パッケージの種類(例：PZ) と温度範囲 (例：S) を示しています。図 8-1に、任意のファミリ・メンバについて、完全なデバイス名を読み取るための凡例を示します。
デバイスの型番、および注文情報の詳細については、このデータシートにあるパッケージ・オプションについての付録や、TI Webサイト(www.ti.com)を参照するか、またはお近くのTI販売代理店にお問い合わせください。
ダイのデバイス項目表記マーキングの詳細説明については、『TMS320F280x、TMS320C280x、TMS320F2801x
DSP シリコン正誤表』を参照してください。

134

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TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
www.tij.co.jp

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

TMS

320

F

28015

PREFIX
TMX = experimental device
TMP = prototype device
TMS = qualified device

PZ

A

-60

Indicates 60-MHz device.
Absence of “-60” indicates 100-MHz device.
TEMPERATURE RANGE
A = −40°C to 85°C
S = −40°C to 125°C
Q = −40°C to 125°C(Q refers to AEC-Q100 qualification for automotive applications.)

DEVICE FAMILY
320 = TMS320 DSP Family

TECHNOLOGYF = Flash EEPROM (1.8-V Core/3.3-V I/O)
C = ROM (1.8-V Core/3.3-V I/O)

DEVICE
2809
2808
2806
2802
2801
28015
28016

PACKAGE TYPE
100-Pin PZ Low-Profile Quad Flatpack (LQFP)
100-Ball GGM Ball Grid Array (BGA)
100-Ball ZGM Lead-Free BGA

図 8-1. TMS320x280x/2801x デバイスの項目表記の例

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135

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 20198.3

www.tij.co.jp

ツールとソフトウェア
TIでは、幅広い開発ツールを提供しています。ツールおよびソフトウェアの一部は、デバイスの性能評価や、コードの生成に使用され、以下に示すようなソリューションの開発が行われます。利用可能なすべてのツールとソフトウェア
については、表 8-1 に記載されている各デバイスの「ツールとソフトウェア」ページを参照してください。
ソフトウェアC28x IQMath ライブラリ - 仮想浮動小数点エンジン
テキサス・インスツルメンツの TMS320C28x IQ Math ライブラリは、C/C++ プログラマ向けの高度に最適化された
高精度の数学関数ライブラリであり、TMS320C28x デバイス上で浮動小数点アルゴリズムを固定小数点コードにシームレスに変換できます。これらのルーチンは通常、最適な実行速度と高精度が重視される、演算集中型のリア
ルタイム・アプリケーションで使用されます。これらのルーチンを使用することにより、標準 ANSI C 言語で作成された同等のコードよりも大幅に処理速度を向上できます。さらに、TI の IQ Math ライブラリには、すぐに使用できる高精度の関数が含まれているので、DSP アプリケーションの開発期間を大幅に短縮できます(ファイルを抽出し、インストールしたら、/docs フォルダに含まれる『IQ Math User's Guide』を参照してください)。
C280x、C2801x C/C++ ヘッダー・ファイル/ペリフェラル例
このユーティリティには、TMS320x280x および TMS320x280xx DSP デバイス用のハードウェア抽象化レイヤ(HAL) が含まれています。この HAL により、C言語を使用したペリフェラル構成が簡単に行えます。また、各ペリフェラルで HAL を使用してオンチップ・ペリフェラルの制御と構成を行う方法の例となる、簡単なテスト・プログラムも付属しています。
開発ツール
C2000 Gang Programmer
C2000 Gang Programmerは、8つまでの同一なC2000デバイスを同時にプログラムできるC2000デバイス・プログ
ラマです。C2000 Gang Programmerでは、標準のRS-232またはUSB接続を使用してホストPCに接続できるほか、柔軟なプログラミング・オプションにより、ユーザーがプロセスを完全にカスタマイズできます。
C2000マイクロコントローラ用の Code Composer Studio™ (CCS)統合開発環境(IDE)
Code Composer Studioは、TIのマイクロコントローラおよび組み込みプロセッサ・ポートフォリオをサポートする統合開発環境(IDE)です。Code Composer Studioは、組み込みアプリケーションの開発およびデバッグに必要な一連のツールで構成されています。最適化C/C++コンパイラ、ソース・コード・エディタ、プロジェクト・ビルド環境、デバッガ、プロファイラなど、多数の機能が含まれています。IDEは直感的で、アプリケーションの開発フローの各段階
を、すべて同一のユーザー・インターフェイスで実行できます。使い慣れたツールとインターフェイスにより、ユーザーは従来より迅速に作業を開始できます。Code Composer Studioは、Eclipseソフトウェア・フレームワークの利点と、TIの先進的な組み込みデバッグ機能の利点を組み合わせ、組み込み製品の開発者向けの魅力的な、豊富な機能を持つ開発環境を実現します。
Uniflashスタンドアロン・フラッシュ・ツールCCS Uniflash は、TI 製 MCU のオンチップ・フラッシュ・メモリのプログラムに使用される、スタンドアロンのツールです。
モデル
製品の｢ツールとソフトウェア」ページでは、各種のモデルをダウンロードできます。これらのモデルには、I/Oバッファ
情報仕様(IBIS)モデルや、バウンダリ・スキャン記述言語(BSDL)モデルが含まれます。利用可能なモデルすべてを参照するには、表 8-1にある各デバイスの「ツールとソフトウェア」ページの「モデル」セクションをご覧ください。

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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
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8.4

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

ドキュメントのサポート
ドキュメントの更新についての通知を受け取るには、ti.comのデバイス製品フォルダを開いてください。右上の「アラートを受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。
プロセッサおよび関連ペリフェラルに関する最新ドキュメント、その他の技術資料を以下に示します。
正誤表『TMS320F280x、TMS320C280x、TMS320F2801x DSP シリコン正誤表』では、シリコンの各バージョンについての勧告事項と使用上の注意を説明しています。
CPU ユーザー・ガイド『TMS320C28x CPU および命令セット・リファレンス・ガイド』では、TMS320C28x 固定小数点デジタル信号プロ
セッサ (DSP) の CPU (Central Processing Unit) およびアセンブリ言語命令について説明しています。これらのDSPで利用可能なエミュレーション機能についても解説しています。
『TMS320x280x、2801x、2804x DSP システム制御および割り込みリファレンス・ガイド』では、280x デジタル信号
プロセッサ (DSP) の各種の割り込みおよびシステム制御機能について説明しています。
ペリフェラル・ガイド『C2000 リアルタイム制御ペリフェラル・リファレンス・ガイド』では、28x デジタル信号プロセッサ (DSP) のペリフェラ
ル・リファレンス・ガイドについて説明しています。
『TMS320x280x、2801x、2804x DSP アナログ/デジタル・コンバータ (ADC) モジュール・リファレンス・ガイド』では、オンチップの 12 ビット・パイプライン ADC モジュールの構成および使用方法を説明しています。
『TMS320x280x、2801x、2804x 拡張パルス幅変調器(ePWM)モジュール・リファレンス・ガイド』では、拡張パルス
幅変調器の主要な分野として、デジタル・モータ制御、スイッチ・モード電源制御、無停電電源 (UPS)、その他の電力変換形式について説明しています。
『TMS320x280x、2801x、2804x 拡張直交エンコーダ・パルス (eQEP) モジュール・リファレンス・ガイド』では、
eQEP モジュールについて説明しています。このモジュールは、リニアまたはロータリー増分エンコーダに接続し、高性能のモーションおよび位置制御システムにおいて、回転している機械の位置、方向、速度情報を収集するために使用されます。モジュールの説明とレジスタも含まれています。
『TMS320x280x、2801x、2804x 拡張キャプチャ (eCAP) モジュール・リファレンス・ガイド』では、拡張キャプチャ・
モジュールについて説明しています。モジュールの説明とレジスタも含まれています。
『TMS320x280x、2801x、2804x 高分解能パルス幅変調器 (HRPWM) リファレンス・ガイド』では、パルス幅変調器 (HRPWM) の高分解能拡張機能の動作について説明しています。
『TMS320x280x/2801x 拡張コントローラ・エリア・ネットワーク(eCAN)リファレンス・ガイド』では、x280x
x2801x デバイスの eCAN (拡張コントローラ・エリア・ネットワーク) について説明しています。

および『TMS320x280x、2801x、2804x シリアル通信インターフェイス (SCI) リファレンス・ガイド』では、TMS320x280x、
2801x、2804x デバイスで利用可能なシリアル通信インターフェイス (SCI) モジュールの機能と動作について説明
しています。
『TMS320x280x、2801x、2804x シリアル・ペリフェラル・インターフェイス・リファレンス・ガイド』では、シリアル・ペリ
フェラル・インターフェイスの動作について説明しています。
『TMS320x280x、2801x、2804x IC相互接続 (I2C) モジュール・リファレンス・ガイド』では、I2C (IC相互接続) モ
ジュールの機能と動作について説明しています。
『TMS320x280x、2801x、2804x ブートROMリファレンス・ガイド』では、ブートローダー (出荷時にプログラムされる
ブート・ローディング・ソフトウェア)の目的と機能について説明しています。また、デバイスのオンチップ・ブート
ROM の他の内容についても記述されており、すべての情報について、メモリ内の位置が明記されています。

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JAJS280O – OCTOBER 2003 – REVISED MARCH 2019www.tij.co.jp

ツール・ガイド『TMS320C28x アセンブリ言語ツール v18.12.0.LTS ユーザー・ガイド』では、TMS320C28x デバイス用のアセンブリ言語ツール (アセンブリ言語コードを開発するためのアセンブラや他のツール)、アセンブラのディレクティブ、マクロ、一般的なオブジェクト・ファイル・フォーマット、シンボリック・デバッグ・ディレクティブについて説明しています。
『TMS320C28x 最適化 C/C++ コンパイラ v18.12.0.LTS ユーザー・ガイド』では、TMS320C28x C/C++ コンパイ
ラについて説明しています。このコンパイラは、ANSI標準のC/C++ソースコードから、TMS320C28xデバイス用のTMS320 DSPアセンブリ言語ソースコードを生成します。
『TMS320C28x DSP/BIOS 5.x アプリケーション・プログラミング・インターフェイス (API) リファレンス・ガイド』では、
DSP/BIOS を使用する開発について説明しています。
アプリケーション・レポート『『TMS320x281xからTMS320x2833xまたは2823xへの移行の概要』では、281x デバイスの設計から 2833x または 2823x の設計に移行する方法について説明しています。
『TMS320x280xからTMS320x2833xまたは2823xへの移行の概要』では、280x デバイスの設計から 2833x または 2823x の設計に移行する方法について説明しています。
『TMS320C28x FPU 入門』では、C2000™ Delfino マイクロコントローラ・デバイスの浮動小数点ユニット (FPU) の概要を説明しています。
『TMS320F28xxx DSPの内部フラッシュ・メモリからアプリケーションを実行する』では、オンチップのフラッシュ・メモ
リからアプリケーションを実行するよう正しく構成するための要件を説明しています。DSP/BIOSのプロジェクトとそれ以外のプロジェクトの両方についての要件が説明されています。サンプル・コード・プロジェクトも含まれています。
『C/C++ での TMS320x28xx および 28xxx ペリフェラルのプログラミング』では、28x DSP 用の C/C++ コーディン
グを簡単に行うための、ハードウェア抽象化レイヤの実装について説明しています。この方法が従来の#defineマクロと比較され、コード効率や、特別な場合のレジスタについても触れられています。
『TMS320F280x デジタル信号コントローラで PWM 出力をデジタル/アナログ・コンバータとして使用する』では、TMS320F280x ファミリのデジタル信号コントローラに実装されている、オンチップのパルス幅変調 (PWM) 信号
ジェネレータを、デジタル/アナログ・コンバータ (DAC) として使用する方法を紹介しています。
『TUSB3410 USB-to-UART ブリッジ・チップを使用する TMS320F280x デジタル信号コントローラの USB 接続性』では、単純な通信エコー・プログラムを使用する開発システムのハードウェア接続や、ソフトウェアの準備と動作について説明しています。
『TMS320x280x、28xxx の拡張直交エンコーダ・パルス (eQEP) モジュールを専用キャプチャとして使用する』では、eQEP
モジュールを専用のキャプチャ・ユニットとして使用する方法を紹介しており、TMS320x280x、28xxx
ファミリのプロセッサに適用可能です。
『ePWM モジュールによる 0%～100% のデューティ・サイクル制御』では、ePWM モジュールを使用して0%～100% のデューティ・サイクル制御を行う方法の指針を説明しており、TMS320x280x ファミリのプロセッサに適用可能です。
『TMS320x280x および TMS320F2801x ADC の較正』では、TMS320x280x および TMS320F2801x デバイスに搭載されている 12 ビット ADC の絶対精度を向上させる方法について説明しています。固有のゲインおよびオフ
セット誤差は、ADCの絶対精度に影響を及ぼします。このレポートに記載されている方法により、ADCの絶対精度を0.5%以内のレベルに向上できます。このアプリケーション・レポートには、F2808 EzDSP上のRAMから実行される
サンプル・プログラムをダウンロードするオプションがあります。
『TMS320C28x DSPのオンライン・スタック・オーバーフローの検出』では、TMS320C28x DSP のオンライン・ス
タック・オーバーフロー検出の手法を説明しています。DSP/BIOSアプリケーションとそれ以外のアプリケーションの両方について、オーバーフロー検出を実装するための機能を含むCソース・コードが紹介されています。
『TMS320281x から TMS320x280x への移行の概要』では、アプリケーションの移行を支援するため、テキサス・イ
ンスツルメンツ製の TMS320x281x と TMS320x280x/2801x/2804x DSP との相違点について説明しています。
『半導体のパッキング手法』では、半導体デバイスをエンド・ユーザーへの配送用に準備するためのパッキング手法について説明しています。
138

デバイスおよびドキュメントのサポート

Copyright © 2003–2019, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
www.tij.co.jp

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

『IBIS (I/O バッファ情報仕様) モデル作成の概要』では、IBIS について歴史、利点、互換性、モデルの生成フ
ロー、入力/出力構造のモデル作成におけるデータの要件、将来の動向など、各種の側面から解説しています。
『組み込みプロセッサの有効寿命の計算』では、TI の組み込みプロセッサ (EP) を電子機器システムで、電力を供給して使用したときの有効寿命を計算するための手法を説明しています。これは、TI EPの信頼性が最終システムの信頼性要件を満たすかどうかを判定したい一般的なエンジニアを対象としています。
『半導体とICパッケージの熱指標』では、従来型と新型の熱指標について記述され、システム・レベルの接合部温度推定に関して、それぞれの用途を説明しています。
『ミッション・プロファイルの FIT の計算』では、TI の信頼性ディレーティング・ツールを使用して、システムのミッショ
ン・プロファイルについて電源オン状態でのコンポーネント・レベル FIT を計算する方法を説明しています。
『C2000™ マイクロコントローラのシリアル・フラッシュ・プログラミング』では、フラッシュ・カーネルおよび ROM ロー
ダーを使用したデバイスのシリアル・プログラミングについて説明しています。

8.5

関連リンク
次の表に、クイック・アクセス・リンクを示します。カテゴリには、技術資料、サポートおよびコミュニティ・リソース、ツー
ルとソフトウェア、およびご注文へのクイック・アクセスが含まれます。
表 8-1. 関連リンク
製品

プロダクト・フォルダ

ご注文はこちら

技術資料

ツールとソフトウェア

サポートとコミュニティ

TMS320F2809

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

TMS320F2808

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

TMS320F2806

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

TMS320F2802

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

TMS320F2801

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

TMS320C2802

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

TMS320C2801

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

TMS320F28016

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

TMS320F28015

ここをクリック

ここをクリック

ここをクリック

ここをクリック

ここをクリック

8.6

Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by therespective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Established to help developers get started with Embedded Processors
from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.

8.7

商標
Code Composer Studio, MicroStar BGA, Delfino, TMS320C2000, TMS320, E2E are trademarks of Texas
Instruments.
eZdsp is a trademark of Spectrum Digital.
All other trademarks are the property of their respective owners.

8.8

静電気放電に関する注意事項
すべての集積回路は、適切なESD保護方法を用いて、取扱いと保存を行うようにして下さい。
静電気放電はわずかな性能の低下から完全なデバイスの故障に至るまで、様々な損傷を与えます。高精度の集積回路は、損傷に対して敏感であり、極めてわずかなパラメータの変化により、デバイスに規定された仕様に適合しなくなる場合があります。

デバイスおよびドキュメントのサポート
Submit Documentation Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

Copyright © 2003–2019, Texas Instruments Incorporated

139

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
JAJS280O – OCTOBER 2003 – REVISED MARCH 20198.9

www.tij.co.jp

Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

140

デバイスおよびドキュメントのサポート

Copyright © 2003–2019, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015
www.tij.co.jp

JAJS280O – OCTOBER 2003 – REVISED MARCH 2019

9 メカニカル、パッケージ、および注文情報
9.1

パッケージ情報以降のページには、メカニカル、パッケージ、および注文に関する情報が記載されています。この情報は、そのデバイスについて利用可能な最新のデータです。このデータは予告なく変更されることがあり、ドキュメントが改訂される場合もあります。本データシートのブラウザ版を使用されている場合は、画面左側の説明をご覧ください。

メカニカル、パッケージ、および注文情報
Submit Documentation Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015

Copyright © 2003–2019, Texas Instruments Incorporated

141

PACKAGE OPTION ADDENDUM
www.ti.com

10-May-2024

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)(3)

Device Marking

Samples

(4/5)

(6)

TMS320F28015NMFAACTIVE

NFBGA

NMF

100

184

RoHS & GreenSNAGCU

Level-3-260C-168 HR-40 to 85

TMS320F28015NMFA

Samples

TMS320F28015PZA

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

320F28015PZA
TMS

Samples

TMS320F28015PZSACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

320F28015PZS
TMS

Samples

TMS320F28015PZSR

ACTIVE

LQFP

PZ

100

1000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

320F28015PZS
TMS

Samples

TMS320F28016PZA

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

320F28016PZA
TMS

Samples

TMS320F28016PZQACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

320F28016PZQ
TMS

Samples

TMS320F28016PZSACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

320F28016PZS
TMS

Samples

TMS320F2801NMFAACTIVE

NFBGA

NMF

100

184

RoHS & GreenSNAGCU

Level-3-260C-168 HR-40 to 85

TMS320F2801NMFA

Samples

TMS320F2801PZA

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

320F2801PZA
TMS

Samples

TMS320F2801PZA-60

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

320F2801PZA-60
TMS

Samples

TMS320F2801PZQ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

320F2801PZQ
TMS

Samples

TMS320F2801PZSACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

320F2801PZS
TMS

Samples

TMS320F2801PZS-60

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

320F2801PZS-60
TMS

Samples

TMS320F2802PZA

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

320F2802PZA
TMS

Samples

TMS320F2802PZA-60

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

320F2802PZA-60
TMS

Samples

TMS320F2802PZQ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

320F2802PZQ
TMS

Samples

TMS320F2802PZSACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

320F2802PZS

Samples

Addendum-Page 1

PACKAGE OPTION ADDENDUM
www.ti.com

Orderable Device

10-May-2024

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking(3)

Samples

(4/5)

(6)

TMS
TMS320F2802PZS-60

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

320F2802PZS-60
TMS

Samples

TMS320F2806NMFAACTIVE

NFBGA

NMF

100

184

RoHS & GreenSNAGCU

Level-3-260C-168 HR-40 to 85

TMS320F2806NMFA

Samples

TMS320F2806NMFARACTIVE

NFBGA

NMF

100

1000

RoHS & GreenSNAGCU

Level-3-260C-168 HR-40 to 85

TMS320F2806NMFA

Samples

TMS320F2806NMFSACTIVE

NFBGA

NMF

100

184

RoHS & GreenSNAGCU

Level-3-260C-168 HR-40 to 125

TMS320F2806NMFS

Samples

TMS320F2806PZA

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

320F2806PZA
TMS

Samples

TMS320F2806PZQ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

320F2806PZQ
TMS

Samples

TMS320F2806PZSACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

320F2806PZS
TMS

Samples

TMS320F2808GBAAACTIVE

NFBGA

GBA

100

184

Non-RoHS& Green

SNPB

Level-3-220C-168 HR-40 to 85

TMS320F2808GBAA

Samples

TMS320F2808GBAS

ACTIVE

NFBGA

GBA

100

184

Non-RoHS& Green

SNPB

Level-3-220C-168 HR-40 to 125

TMS320F2808GBAS

Samples

TMS320F2808NMFAACTIVE

NFBGA

NMF

100

184

RoHS & GreenSNAGCU

Level-3-260C-168 HR-40 to 85

TMS320F2808NMFA

Samples

TMS320F2808NMFSACTIVE

NFBGA

NMF

100

184

RoHS & GreenSNAGCU

Level-3-260C-168 HR-40 to 125

TMS320F2808NMFS

Samples

TMS320F2808PZA

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

320F2808PZA
TMS

Samples

TMS320F2808PZAR

ACTIVE

LQFP

PZ

100

1000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

320F2808PZA
TMS

Samples

TMS320F2808PZQ

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

320F2808PZQ
TMS

Samples

TMS320F2808PZSACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

320F2808PZS
TMS

Samples

TMS320F2809NMFAACTIVE

NFBGA

NMF

100

184

RoHS & GreenSNAGCU

Level-3-260C-168 HR-40 to 85

TMS320F2809NMFA

Samples

TMS320F2809PZA

ACTIVE

LQFP

PZ

100

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

320F2809PZA
TMS

Samples

Addendum-Page 2

PACKAGE OPTION ADDENDUM
www.ti.com

Orderable Device

10-May-2024

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

RoHS & Green

NIPDAUMSL Peak Temp

Op Temp (°C)

Device Marking(3)

Samples

(4/5)

(6)

TMS320F2809PZSACTIVE

LQFP

PZ

100

90

Level-2-260C-1 YEAR

-40 to 125

320F2809PZS
TMS

(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMS320F2801, TMS320F2801-Q1, TMS320F28016, TMS320F28016-Q1, TMS320F2802, TMS320F2802-Q1, TMS320F2806, TMS320F2806Q1, TMS320F2808, TMS320F2808-Q1, TMS320F2809 :Addendum-Page 3

SamplesPACKAGE OPTION ADDENDUM
www.ti.com

10-May-2024• Catalog : TMS320F2801, TMS320F28016, TMS320F2802, TMS320F2806, TMS320F2808• Automotive : TMS320F2801-Q1, TMS320F28016-Q1, TMS320F2802-Q1, TMS320F2806-Q1, TMS320F2808-Q1, TMS320F2809-Q1
NOTE: Qualified Version Definitions:• Catalog - TI's standard catalog product• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 4

PACKAGE MATERIALS INFORMATION
www.ti.com

22-Feb-2023

TRAY
L - Outer tray length without tabs

KO Outertray
height

WOuter
tray
width
Text

P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

DevicePackage
Name

Package
Type

Pins

SPQ

Unit arrayMax
L (mm) W
matrix temperature
(mm)
(°C)

K0
(µm)

P1
(mm)

CL
(mm)

CW
(mm)

TMS320F28015NMFA

NMF

NFBGA

100

184

8 x 23

150

315

135.9

7620

13.4

10.1

19.65

TMS320F28015PZA

PZ

LQFP

100

90

6 x 15150

TMS320F28015PZS

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

315

135.9

7620

20.3

15.4

TMS320F28016PZA

PZ

LQFP

100

90

6 x 15

15.4

150

315

135.9

7620

20.3

15.4

15.4

TMS320F28016PZQ

PZ

LQFP

100

90

TMS320F28016PZS

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

TMS320F2801NMFA

NMF

NFBGA

100

TMS320F2801PZA

PZ

LQFP

100

184

8 x 23

150

315

135.9

7620

13.4

10.1

19.65

90

6 x 15

150

315

135.9

7620

20.3

15.4

TMS320F2801PZA-60

PZ

LQFP

15.4

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

TMS320F2801PZQ

PZ

TMS320F2801PZS

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

TMS320F2801PZS-60

15.4

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

TMS320F2802PZA

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

TMS320F2802PZA-60

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

TMS320F2802PZQ

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

TMS320F2802PZS

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

TMS320F2802PZS-60

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

22-Feb-2023

DevicePackage
Name

Package
Type

Pins

SPQ

Unit arrayMax
L (mm) W
matrix temperature
(mm)
(°C)

K0
(µm)

P1
(mm)

CL
(mm)

CW
(mm)

TMS320F2806NMFA

NMF

NFBGA

100

184

8 x 23150

315

TMS320F2806NMFS

NMF

NFBGA

100

184

8 x 23

150

315

135.9

7620

13.4

10.1

19.65

135.9

7620

13.4

10.1

TMS320F2806PZA

PZ

LQFP

100

90

6 x 15

150

19.65

315

135.9

7620

20.3

15.4

15.4

TMS320F2806PZQ

PZ

LQFP

100

90

6 x 15

TMS320F2806PZS

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

150

315

135.9

7620

20.3

15.4

15.4

TMS320F2808GBAA

GBA

NFBGA

100

184

TMS320F2808GBAS

GBA

NFBGA

100

184

8 x 23

150

315

135.9

7620

13.4

10.1

19.65

8 x 23

150

315

135.9

7620

13.4

10.1

TMS320F2808NMFA

NMF

NFBGA

100

19.65

184

8 x 23

150

315

135.9

7620

13.4

10.1

19.65

TMS320F2808NMFS

NMF

NFBGA

TMS320F2808PZA

PZ

LQFP

100

184

8 x 23

150

315

135.9

7620

13.4

10.1

19.65

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

TMS320F2808PZQ

PZ

15.4

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

TMS320F2808PZS

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

TMS320F2809NMFA

NMF

NFBGA

100

184

8 x 23

150

315

135.9

7620

13.4

10.1

19.65

TMS320F2809PZA

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

TMS320F2809PZS

PZ

LQFP

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

Pack Materials-Page 2

MECHANICAL DATAMPBG028B FEBRUARY 1997 – REVISED MAY 2002

GGM (S–PBGA–N100)

PLASTIC BALL GRID ARRAY

10,10
SQ
9,90

7,20 TYP
0,80
0,40

K
0,80

J
H
G
F
E
0,40

D
C
B
A

A1 Corner

1

2

3

4

5

6

7

8

9

10

Bottom View

0,95
0,85

1,40 MAX

Seating Plane
0,55
0,45

0,08

0,45
0,35

0,10

4145257–3/C 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice
C. MicroStar BGA configuration.

POST OFFICE BOX 655303• DALLAS, TEXAS 75265

1

MECHANICAL DATAMTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996

PZ (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27
0,17

0,50
75

0,08 M

51

76

50

100

26

1

0,13 NOM

25
12,00 TYP

Gage Plane

14,20
SQ
13,80
16,20
SQ
15,80

0,05 MIN

1,45
1,35

0,25
0°– 7°

0,75
0,45
Seating Plane
0,08

1,60 MAX

4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026

POST OFFICE BOX 655303• DALLAS, TEXAS 75265

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