TMS570LS04x/03x 16/32-Bit RISC Flash
Microcontroller

Technical Reference Manual

Literature Number: SPNU517C
March 2018

Contents
Preface....................................................................................................................................... 55
1

Introduction ....................................................................................................................... 57
1.1
1.2
1.3

2

2.2

2.3

2.4

2.5

Introduction ................................................................................................................. 63
2.1.1 Architecture Block Diagram ..................................................................................... 63
2.1.2 Definitions of Terms .............................................................................................. 64
2.1.3 Bus Master / Slave Access Privileges ......................................................................... 65
Memory Organization ..................................................................................................... 66
2.2.1 Memory-Map Overview .......................................................................................... 66
2.2.2 Memory-Map Table ............................................................................................... 67
2.2.3 Flash on Microcontrollers ........................................................................................ 70
2.2.4 On-Chip SRAM ................................................................................................... 72
Exceptions................................................................................................................... 76
2.3.1 Resets .............................................................................................................. 76
2.3.2 Aborts .............................................................................................................. 76
2.3.3 System Software Interrupts ..................................................................................... 78
Clocks ........................................................................................................................ 79
2.4.1 Clock Sources ..................................................................................................... 79
2.4.2 Clock Domains .................................................................................................... 80
2.4.3 Low-Power Modes ................................................................................................ 81
2.4.4 Clock Test Mode .................................................................................................. 83
2.4.5 Safety Considerations for Clocks ............................................................................... 84
System and Peripheral Control Registers .............................................................................. 86
2.5.1 Primary System Control Registers (SYS) ..................................................................... 86
2.5.2 Secondary System Control Registers (SYS2) ............................................................... 139
2.5.3 Peripheral Central Resource (PCR) Control Registers .................................................... 144

I/O Multiplexing and Control Module (IOMM) ........................................................................ 159
3.1
3.2
3.3

3.4

3.5

2

58
58
61
61

Architecture ...................................................................................................................... 62
2.1

3

Designed for Safety Applications .........................................................................................
Family Description..........................................................................................................
Endianism Considerations ................................................................................................
1.3.1 Big Endian (BE32) ................................................................................................

Overview ..................................................................................................................
Main Features of I/O Multiplexing Module (IOMM) ..................................................................
Control of Multiplexed Functions .......................................................................................
3.3.1 Control of Multiplexed Outputs ................................................................................
3.3.2 Inputs .............................................................................................................
3.3.3 Control of Special Multiplexed Options ......................................................................
Safety Features ..........................................................................................................
3.4.1 Locking Mechanism for Memory-Mapped Registers .......................................................
3.4.2 Error Conditions ..................................................................................................
IOMM Registers ...........................................................................................................
3.5.1 REVISION_REG: Revision Register ..........................................................................
3.5.2 BOOT_REG: Boot Mode Register .............................................................................
3.5.3 KICK_REG0: Kicker Register 0 ................................................................................
3.5.4 KICK_REG1: Kicker Register 1 ................................................................................

Contents

160
160
160
160
161
162
163
163
163
164
164
165
165
165

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

3.5.5 ERR_RAW_STATUS_REG: Error Raw Status / Set Register .............................................
3.5.6 ERR_ENABLED_STATUS_REG: Error Enabled Status / Clear Register ................................
3.5.7 ERR_ENABLE_REG: Error Signaling Enable Register.....................................................
3.5.8 ERR_ENABLE_CLR_REG: Error Signaling Enable Clear Register ......................................
3.5.9 FAULT_ADDRESS_REG: Fault Address Register ..........................................................
3.5.10 FAULT_STATUS_REG: Fault Status Register .............................................................
3.5.11 FAULT_CLEAR_REG: Fault Clear Register ................................................................
3.5.12 PINMMRn: Pin Multiplexing Control Registers..............................................................

4

166
167
168
169
169
170
171
172

F021 Flash Module Controller............................................................................................. 173
4.1

4.2
4.3

4.4

4.5

4.6

4.7

Overview ..................................................................................................................
4.1.1 Features ..........................................................................................................
4.1.2 Definition of Terms ..............................................................................................
4.1.3 F021 Flash Tools ................................................................................................
Default Flash Configuration .............................................................................................
SECDED ..................................................................................................................
4.3.1 SECDED Initialization ...........................................................................................
4.3.2 ECC Encoding....................................................................................................
4.3.3 Syndrome Table: Decode to Bit in Error ......................................................................
4.3.4 Syndrome Table: An Alternate Method .......................................................................
Memory Map ..............................................................................................................
4.4.1 Location of Flash ECC Bits .....................................................................................
4.4.2 OTP Memory .....................................................................................................
Power On, Power Off Considerations .................................................................................
4.5.1 Error Checking at Power On ...................................................................................
4.5.2 Flash Integrity at Power Off ....................................................................................
Emulation and SIL3 Diagnostic Modes ................................................................................
4.6.1 System Emulation ...............................................................................................
4.6.2 Diagnostic Mode .................................................................................................
4.6.3 Diagnostic Mode Summary .....................................................................................
4.6.4 Read Margin ......................................................................................................
Control Registers .........................................................................................................
4.7.1 Flash Option Control Register (FRDCNTL) ..................................................................
4.7.2 Flash Error Detection and Correction Control Register 1 (FEDACCTRL1) .............................
4.7.3 Flash Error Correction and Correction Control Register 2 (FEDACCTRL2) ............................
4.7.4 Flash Correctable Error Count Register (FCOR_ERR_CNT) .............................................
4.7.5 Flash Correctable Error Address Register (FCOR_ERR_ADD) ..........................................
4.7.6 Flash Correctable Error Position Register (FCOR_ERR_POS) ..........................................
4.7.7 Flash Error Detection and Correction Status Register (FEDACSTATUS) ...............................
4.7.8 Flash Uncorrectable Error Address Register (FUNC_ERR_ADD) .......................................
4.7.9 Flash Error Detection and Correction Sector Disable Register (FEDACSDIS) .........................
4.7.10 Primary Address Tag Register (FPRIM_ADD_TAG) ......................................................
4.7.11 Duplicate Address Tag Register (FDUP_ADD_TAG) .....................................................
4.7.12 Flash Bank Protection Register (FBPROT) ................................................................
4.7.13 Flash Bank Sector Enable Register (FBSE) ................................................................
4.7.14 Flash Bank Busy Register (FBBUSY) .......................................................................
4.7.15 Flash Bank Access Control Register (FBAC) ..............................................................
4.7.16 Flash Bank Fallback Power Register (FBFALLBACK) ....................................................
4.7.17 Flash Bank/Pump Ready Register (FBPRDY) .............................................................
4.7.18 Flash Pump Access Control Register 1 (FPAC1) ..........................................................
4.7.19 Flash Pump Access Control Register 2 (FPAC2) ..........................................................
4.7.20 Flash Module Access Control Register (FMAC) ............................................................
4.7.21 Flash Module Status Register (FMSTAT) ..................................................................
4.7.22 EEPROM Emulation Data MSW Register (FEMU_DMSW) ...............................................

SPNU517C – March 2018
Submit Documentation Feedback

Contents
Copyright © 2018, Texas Instruments Incorporated

174
174
174
175
175
176
176
177
178
179
180
180
181
183
183
183
184
184
184
187
189
189
191
192
194
194
195
196
197
200
201
203
203
204
204
205
206
207
208
209
209
210
211
213
3

www.ti.com

4.7.234.7.244.7.254.7.264.7.274.7.284.7.294.7.304.7.31
4.7.324.7.334.7.344.7.354.7.364.7.374.7.384.7.394.7.404.7.41
4.7.42

5

Tightly-Coupled RAM (TCRAM) Module ............................................................................... 232
5.1

5.2
5.3

5.4
5.5
5.6

6

Overview ................................................................................................................... 233
5.1.1 B0TCM and B1TCM Connection Diagram ................................................................... 233
5.1.2 Main Features .................................................................................................... 233
RAM Memory Map ........................................................................................................ 234
Safety Features ........................................................................................................... 235
5.3.1 Support for Cortex-R4 CPU's Single-Error-Correction Double-Error-Detection (SECDED) ........... 235
5.3.2 Support for Cortex-R4 CPU's Address and Control Bus Parity Checking ................................ 236
5.3.3 Redundant Address Decode ................................................................................... 236
TCRAM Auto-Initialization ............................................................................................... 236
Emulation / Debug Mode Behavior ..................................................................................... 237
TCRAM Control and Status Registers ................................................................................. 237
5.6.1 TCRAM Module Control Register (RAMCTRL) .............................................................. 238
5.6.2 TCRAM Module Single-Bit Error Correction Threshold Register (RAMTHRESHOLD) ................. 239
5.6.3 TCRAM Module Single-Bit Error Occurrences Counter Register (RAMOCCUR) ....................... 240
5.6.4 TCRAM Module Interrupt Control Register (RAMINTCTRL) ............................................... 240
5.6.5 TCRAM Module Error Status Register (RAMERRSTATUS) ............................................... 241
5.6.6 TCRAM Module Single-Bit Error Address Register (RAMSERRADDR).................................. 242
5.6.7 TCRAM Module Uncorrectable Error Address Register (RAMUERRADDR) ............................ 243
5.6.8 TCRAM Module Test Mode Control Register (RAMTEST)................................................. 244
5.6.9 TCRAM Module Test Mode Vector Register (RAMADDRDECVECT) .................................... 245
5.6.10 TCRAM Module Parity Error Address Register (RAMPERRADDR) ..................................... 245

Programmable Built-In Self-Test (PBIST) Module ................................................................. 246
6.1

6.2
6.3
6.4
6.5

4

EEPROM Emulation Data LSW Register (FEMU_DLSW) ................................................ 213
EEPROM Emulation ECC Register (FEMU_ECC) ......................................................... 214
EEPROM Emulation Address Register (FEMU_ADDR) ................................................... 215
Diagnostic Control Register (FDIAGCTRL) ................................................................. 216
Uncorrected Raw Data High Register (FRAW_DATAH) .................................................. 218
Uncorrected Raw Data Low Register (FRAW_DATAL) ................................................... 218
Uncorrected Raw ECC Register (FRAW_ECC) ............................................................ 219
Parity Override Register (FPAR_OVR) ...................................................................... 220
Flash Error Detection and Correction Sector Disable Register (FEDACSDIS2) ...................... 221
FSM Register Write Enable (FSM_WR_ENA) ............................................................. 223
FSM Sector Register (FSM_SECTOR) ..................................................................... 223
EEPROM Emulation Configuration Register (EEPROM_CONFIG) ..................................... 224
EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1) .............. 225
EEPROM Emulation Error Correction and Correction Control Register 2 (EE_CTRL2) ............. 226
EEPROM Emulation Correctable Error Count Register (EE_COR_ERR_CNT) ....................... 227
EEPROM Emulation Correctable Error Address Register (EE_COR_ERR_ADD) .................... 227
EEPROM Emulation Correctable Error Position Register (EE_COR_ERR_POS) .................... 228
EEPROM Emulation Error Status Register (EE_STATUS) .............................................. 229
EEPROM Emulation Uncorrectable Error Address Register (EE_UNC_ERR_ADD) ................. 230
Flash Bank Configuration Register (FCFG_BANK) ....................................................... 231

Overview ..................................................................................................................
6.1.1 Features of PBIST ..............................................................................................
6.1.2 PBIST versus Application Software-Based Testing .........................................................
6.1.3 PBIST Block Diagram ..........................................................................................
RAM Grouping and Algorithm ..........................................................................................
PBIST Flow ...............................................................................................................
6.3.1 PBIST Sequence ................................................................................................
Memory Test Algorithms on the On-chip ROM ......................................................................
PBIST Control Registers ................................................................................................
6.5.1 RAM Configuration Register (RAMT) .........................................................................

Contents

247
247
247
247
248
249
250
251
253
254

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

6.6

7

CPU Self-Test Controller (STC) Module .............................................................................. 267
7.1

7.2

7.3
7.4

7.5

8

General Description ......................................................................................................
7.1.1 CPU Self-Test Controller Features ...........................................................................
7.1.2 STC Block Diagram .............................................................................................
Application Self-Test Flow ..............................................................................................
7.2.1 STC Module Configuration .....................................................................................
7.2.2 Context Saving ..................................................................................................
7.2.3 Entering CPU Idle Mode .......................................................................................
7.2.4 Self-Test Completion and Error Generation .................................................................
STC Test Coverage and Duration .....................................................................................
STC Control Registers ..................................................................................................
7.4.1 STC Global Control Register 0 (STCGCR0) .................................................................
7.4.2 STC Global Control Register 1 (STCGCR1) .................................................................
7.4.3 Self-Test Run Timeout Counter Preload Register (STCTPR) .............................................
7.4.4 STC Current ROM Address Register (STC_CADDR) ......................................................
7.4.5 STC Current Interval Count Register (STCCICR) ...........................................................
7.4.6 Self-Test Global Status Register (STCGSTAT)..............................................................
7.4.7 Self-Test Fail Status Register (STCFSTAT) .................................................................
7.4.8 CPU1 Current MISR Registers (CPU1_CURMISR3-CPU1_CURMISR0) ...............................
7.4.9 CPU2 Current MISR Registers (CPU2_CURMISR3-CPU2_CURMISR0) ...............................
7.4.10 Signature Compare Self Check Register (STCSCSCR)...................................................
STC Configuration Example ............................................................................................
7.5.1 Example 1: Self-Test Run for 24 Interval ....................................................................

268
268
268
270
270
270
270
271
272
273
274
274
275
275
276
277
278
279
280
281
282
282

CPU Compare Module for Cortex™-R4 (CCM-R4) ................................................................. 283
8.1
8.2
8.3

8.4

9

6.5.2 Datalogger Register (DLR) ..................................................................................... 255
6.5.3 Program Control Register (PCR) .............................................................................. 256
6.5.4 PBIST Activate/Clock Enable Register (PACT) .............................................................. 257
6.5.5 PBIST ID Register (PBISTID) .................................................................................. 257
6.5.6 Override Register (OVER) ...................................................................................... 258
6.5.7 Fail Status Fail Register (FSRF0) ............................................................................. 259
6.5.8 Fail Status Count Registers (FSRC0 and FSRC1) .......................................................... 260
6.5.9 Fail Status Address Registers (FSRA0 and FSRA1) ....................................................... 261
6.5.10 Fail Status Data Registers (FSRDL0 and FSRDL1) ....................................................... 262
6.5.11 ROM Mask Register (ROM) ................................................................................... 263
6.5.12 ROM Algorithm Mask Register (ALGO) ..................................................................... 263
6.5.13 RAM Info Mask Lower Register (RINFOL) .................................................................. 264
6.5.14 RAM Info Mask Upper Register (RINFOU) .................................................................. 264
PBIST Configuration Examples ......................................................................................... 265
6.6.1 Example 1 : Configuration of PBIST Controller to Run Self-Test on DCAN1 RAM ..................... 265
6.6.2 Example 2 : Configuration of PBIST Controller to Run Self-Test on ALL RAM Groups ................ 266

Main Features .............................................................................................................
Block Diagram .............................................................................................................
Module Operation .........................................................................................................
8.3.1 1oo1D Lock Step Mode .........................................................................................
8.3.2 Self-Test Mode ...................................................................................................
8.3.3 Error Forcing Mode ..............................................................................................
8.3.4 Self-Test Error Forcing Mode ..................................................................................
8.3.5 Operation During CPU Debug Mode ..........................................................................
CCM-R4 Control Registers ..............................................................................................
8.4.1 CCM-R4 Status Register (CCMSR) ...........................................................................
8.4.2 CCM-R4 Key Register (CCMKEYR) ..........................................................................

284
284
285
285
285
288
288
288
288
289
290

Oscillator, PLL, and Clock Monitoring ................................................................................. 291
9.1

Introduction ................................................................................................................ 292

SPNU517C – March 2018
Submit Documentation Feedback

Contents
Copyright © 2018, Texas Instruments Incorporated

5

www.ti.com

9.2
9.3

9.4

9.5

9.6

9.7

9.8

10

10.2

10.3
10.4

Introduction ...............................................................................................................
10.1.1 Main Features ..................................................................................................
10.1.2 Block Diagram ..................................................................................................
Module Operation ........................................................................................................
10.2.1 Error Conditions ................................................................................................
10.2.2 Single-Shot Operation Mode .................................................................................
Clock Source Selection for Counter0 and Counter1 ................................................................
DCC Control Registers ..................................................................................................
10.4.1 DCC Global Control Register (DCCGCTRL) ...............................................................
10.4.2 DCC Revision ID Register (DCCREV) ......................................................................
10.4.3 DCC Counter0 Seed Register (DCCCNT0SEED) .........................................................
10.4.4 DCC Valid0 Seed Register (DCCVALID0SEED) ..........................................................
10.4.5 DCC Counter1 Seed Register (DCCCNT1SEED) .........................................................
10.4.6 DCC Status Register (DCCSTAT) ...........................................................................
10.4.7 DCC Counter0 Value Register (DCCCNT0) ................................................................
10.4.8 DCC Valid0 Value Register (DCCVALID0) .................................................................
10.4.9 DCC Counter1 Value Register (DCCCNT1) ................................................................
10.4.10 DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) ..............................
10.4.11 DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) ..............................

318
318
318
319
319
322
322
323
324
325
325
326
326
327
328
329
329
330
330

Error Signaling Module (ESM) ........................................................................................... 331
11.1

6

292
293
294
295
295
295
296
296
297
297
298
299
299
300
302
303
306
307
307
308
309
310
311
312
313
313
314
314
315
315

Dual-Clock Comparator (DCC) Module ................................................................................ 317
10.1

11

9.1.1 Features ...........................................................................................................
Quick Start .................................................................................................................
Oscillator ...................................................................................................................
9.3.1 Oscillator Implementation .......................................................................................
9.3.2 Oscillator Enable .................................................................................................
9.3.3 Oscillator Disable ................................................................................................
Low-Power Oscillator and Clock Detect (LPOCLKDET) .............................................................
9.4.1 Clock Detect ......................................................................................................
9.4.2 Behavior on Oscillator Failure ..................................................................................
9.4.3 Recovery from Oscillator Failure...............................................................................
9.4.4 LPOCLKDET Enable ............................................................................................
9.4.5 LPOCLKDET Disable ...........................................................................................
9.4.6 Trimming the HF LPO Oscillator ...............................................................................
PLL .........................................................................................................................
9.5.1 Modulation ........................................................................................................
9.5.2 PLL Output Control ..............................................................................................
9.5.3 Behavior on PLL Fail ............................................................................................
9.5.4 Recovery from a PLL Failure ...................................................................................
9.5.5 PLL Modulation Depth Measurement .........................................................................
9.5.6 PLL Frequency Measurement Circuit .........................................................................
PLL Control Registers ....................................................................................................
9.6.1 PLL Modulation Depth Measurement Control Register (SSWPLL1) ......................................
9.6.2 SSW PLL BIST Control Register 2 (SSWPLL2) .............................................................
9.6.3 SSW PLL BIST Control Register 3 (SSWPLL3) .............................................................
Phase-Locked Loop Theory of Operation .............................................................................
9.7.1 Phase-Frequency Detector .....................................................................................
9.7.2 Charge Pump and Loop Filter ..................................................................................
9.7.3 Voltage-Controlled Oscillator ...................................................................................
9.7.4 Frequency Modulation...........................................................................................
Programming Example ...................................................................................................

Overview .................................................................................................................. 332
11.1.1 Features.......................................................................................................... 332

Contents

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

11.2

11.3
11.4

12

11.1.2 Block Diagram ..................................................................................................
Module Operation ........................................................................................................
11.2.1 Reset Behavior .................................................................................................
11.2.2 ERROR Pin Timing ............................................................................................
11.2.3 Forcing an Error Condition ....................................................................................
Recommended Programming Procedure .............................................................................
Control Registers .........................................................................................................
11.4.1 ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1) ...............................
11.4.2 ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1) ..............................
11.4.3 ESM Interrupt Enable Set Register 1 (ESMIESR1) ........................................................
11.4.4 ESM Interrupt Enable Clear Register 1 (ESMIECR1) .....................................................
11.4.5 ESM Interrupt Level Set Register 1 (ESMILSR1) ..........................................................
11.4.6 ESM Interrupt Level Clear Register 1 (ESMILCR1) ........................................................
11.4.7 ESM Status Register 1 (ESMSR1) ...........................................................................
11.4.8 ESM Status Register 2 (ESMSR2) ...........................................................................
11.4.9 ESM Status Register 3 (ESMSR3) ...........................................................................
11.4.10 ESM ERROR Pin Status Register (ESMEPSR) ..........................................................
11.4.11 ESM Interrupt Offset High Register (ESMIOFFHR) ......................................................
11.4.12 ESM Interrupt Offset Low Register (ESMIOFFLR) .......................................................
11.4.13 ESM Low-Time Counter Register (ESMLTCR) ...........................................................
11.4.14 ESM Low-Time Counter Preload Register (ESMLTCPR)................................................
11.4.15 ESM Error Key Register (ESMEKR) ........................................................................
11.4.16 ESM Status Shadow Register 2 (ESMSSR2) .............................................................
11.4.17 ESM Influence ERROR Pin Set Register 4 (ESMIEPSR4) .............................................
11.4.18 ESM Influence ERROR Pin Clear Register 4 (ESMIEPCR4) ..........................................
11.4.19 ESM Interrupt Enable Set Register 4 (ESMIESR4) ......................................................
11.4.20 ESM Interrupt Enable Clear Register 4 (ESMIECR4) ...................................................
11.4.21 ESM Interrupt Level Set Register 4 (ESMILSR4) ........................................................
11.4.22 ESM Interrupt Level Clear Register 4 (ESMILCR4) .....................................................
11.4.23 ESM Status Register 4 (ESMSR4) .........................................................................

332
334
334
335
337
338
339
340
340
341
341
342
342
343
343
344
344
345
346
347
347
348
348
349
349
350
350
351
351
352

Real-Time Interrupt (RTI) Module ........................................................................................ 353
12.1

12.2

12.3

Overview ...................................................................................................................
12.1.1 Features..........................................................................................................
12.1.2 Industry Standard Compliance Statement ...................................................................
Module Operation .........................................................................................................
12.2.1 Counter Operation ..............................................................................................
12.2.2 Interrupt Requests ..............................................................................................
12.2.3 RTI Clocking .....................................................................................................
12.2.4 Digital Watchdog (DWD) .......................................................................................
12.2.5 Low Power Modes ..............................................................................................
12.2.6 Halting Debug Mode Behaviour...............................................................................
RTI Control Registers ....................................................................................................
12.3.1 RTI Global Control Register (RTIGCTRL) ...................................................................
12.3.2 RTI Capture Control Register (RTICAPCTRL)..............................................................
12.3.3 RTI Compare Control Register (RTICOMPCTRL) .........................................................
12.3.4 RTI Free Running Counter 0 Register (RTIFRC0) .........................................................
12.3.5 RTI Up Counter 0 Register (RTIUC0) ........................................................................
12.3.6 RTI Compare Up Counter 0 Register (RTICPUC0) ........................................................
12.3.7 RTI Capture Free Running Counter 0 Register (RTICAFRC0) ...........................................
12.3.8 RTI Capture Up Counter 0 Register (RTICAUC0)..........................................................
12.3.9 RTI Free Running Counter 1 Register (RTIFRC1) .........................................................
12.3.10 RTI Up Counter 1 Register (RTIUC1) ......................................................................
12.3.11 RTI Compare Up Counter 1 Register (RTICPUC1).......................................................

SPNU517C – March 2018
Submit Documentation Feedback

Contents
Copyright © 2018, Texas Instruments Incorporated

354
354
354
355
355
357
358
358
361
361
362
363
364
365
366
366
367
367
368
368
369
370
7

www.ti.com

12.3.1212.3.1312.3.1412.3.15
12.3.1612.3.1712.3.18
12.3.1912.3.20
12.3.2112.3.2212.3.23
12.3.24
12.3.25
12.3.26
12.3.2712.3.28
12.3.2912.3.30
12.3.3112.3.32
12.3.33
12.3.34
12.3.35
12.3.36

13

371
371
372
372
373
373
374
374
375
375
376
378
380
381
382
383
384
385
385
386
387
388
388
389
389

Cyclic Redundancy Check (CRC) Controller Module ............................................................ 390
13.1

13.2

13.3
13.4

8

RTI Capture Free Running Counter 1 Register (RTICAFRC1) .........................................
RTI Capture Up Counter 1 Register (RTICAUC1) ........................................................
RTI Compare 0 Register (RTICOMP0) .....................................................................
RTI Update Compare 0 Register (RTIUDCP0) ............................................................
RTI Compare 1 Register (RTICOMP1) .....................................................................
RTI Update Compare 1 Register (RTIUDCP1) ............................................................
RTI Compare 2 Register (RTICOMP2) .....................................................................
RTI Update Compare 2 Register (RTIUDCP2) ............................................................
RTI Compare 3 Register (RTICOMP3) .....................................................................
RTI Update Compare 3 Register (RTIUDCP3) ............................................................
RTI Set Interrupt Enable Register (RTISETINTENA) ....................................................
RTI Clear Interrupt Enable Register (RTICLEARINTENA) ..............................................
RTI Interrupt Flag Register (RTIINTFLAG) ................................................................
Digital Watchdog Control Register (RTIDWDCTRL) .....................................................
Digital Watchdog Preload Register (RTIDWDPRLD) .....................................................
Watchdog Status Register (RTIWDSTATUS) .............................................................
RTI Watchdog Key Register (RTIWDKEY) ................................................................
RTI Digital Watchdog Down Counter (RTIDWDCNTR) ..................................................
Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) .................................
Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) ............................
RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE) .................................
RTI Compare 0 Clear Register (RTICMP0CLR) ..........................................................
RTI Compare 1 Clear Register (RTICMP1CLR) ..........................................................
RTI Compare 2 Clear Register (RTICMP2CLR) ..........................................................
RTI Compare 3 Clear Register (RTICMP3CLR) ..........................................................

Overview ..................................................................................................................
13.1.1 Features .........................................................................................................
13.1.2 Block Diagram ...................................................................................................
Module Operation ........................................................................................................
13.2.1 General Operation .............................................................................................
13.2.2 CRC Modes of Operation ......................................................................................
13.2.3 PSA Signature Register........................................................................................
13.2.4 Raw Data Register .............................................................................................
13.2.5 CPU Data Trace ................................................................................................
13.2.6 Power Down Mode .............................................................................................
13.2.7 Emulation .......................................................................................................
13.2.8 Peripheral Bus Interface .......................................................................................
Example/Hints: Full-CPU Mode ........................................................................................
13.3.1 CRC Setup ......................................................................................................
CRC Control Registers ...................................................................................................
13.4.1 CRC Global Control Register 0 (CRC_CTRL0).............................................................
13.4.2 CRC Global Control Register (CRC_CTRL1) ...............................................................
13.4.3 CRC Global Control Register 2 (CRC_CTRL2).............................................................
13.4.4 Channel 1 PSA Signature Low Register (PSA_SIGREGL1) ..............................................
13.4.5 Channel 1 PSA Signature High Register (PSA_SIGREGH1) .............................................
13.4.6 Channel 1 Raw Data Low Register (RAW_DATAREGL1) ................................................
13.4.7 Channel 1 Raw Data High Register (RAW_DATAREGH1) ...............................................
13.4.8 Channel 2 PSA Signature Low Register (PSA_SIGREGL2) ..............................................
13.4.9 Channel 2 PSA Signature High Register (PSA_SIGREGH2) .............................................
13.4.10 Channel 2 Raw Data Low Register (RAW_DATAREGL2)...............................................
13.4.11 Channel 2 Raw Data High Register (RAW_DATAREGH2)..............................................
13.4.12 Data Bus Selection Register (CRC_TRACE_BUS_SEL) ................................................

Contents

391
391
391
392
392
392
392
393
394
394
394
394
394
395
395
396
396
397
398
398
399
399
400
400
401
401
402

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

14

Vectored Interrupt Manager (VIM) Module ............................................................................ 403
14.1
14.2

14.3

14.4

14.5
14.6
14.7

14.8

15

Overview ...................................................................................................................
Device Level Interrupt Management ...................................................................................
14.2.1 Interrupt Generation at the Peripheral .......................................................................
14.2.2 Interrupt Handling at the CPU.................................................................................
14.2.3 Software Interrupt Handling Options .........................................................................
Interrupt Handling Inside VIM ...........................................................................................
14.3.1 VIM Interrupt Channel Mapping...............................................................................
14.3.2 VIM Input Channel Management .............................................................................
Interrupt Vector Table (VIM RAM) ......................................................................................
14.4.1 Interrupt Vector Table Operation .............................................................................
14.4.2 Enabling and Controlling the VIM Parity .....................................................................
14.4.3 Interrupt Vector Table Initialization ...........................................................................
14.4.4 Interrupt Vector Table Parity Testing .........................................................................
VIM Wakeup Interrupt ....................................................................................................
Capture Event Sources ..................................................................................................
Examples ..................................................................................................................
14.7.1 Examples - Configure CPU To Receive Interrupts .........................................................
14.7.2 Examples - Register Vector Interrupt and Index Interrupt Handling .....................................
VIM Control Registers ....................................................................................................
14.8.1 Interrupt Vector Table Parity Flag Register (PARFLG) ...................................................
14.8.2 Interrupt Vector Table Parity Control Register (PARCTL) .................................................
14.8.3 Address Parity Error Register (ADDERR) ...................................................................
14.8.4 Fall-Back Address Parity Error Register (FBPARERR)....................................................
14.8.5 VIM Offset Vector Registers...................................................................................
14.8.6 IRQ Index Offset Vector Register (IRQINDEX) .............................................................
14.8.7 FIQ Index Offset Vector Registers (FIQINDEX) ............................................................
14.8.8 FIQ/IRQ Program Control Registers (FIRQPR[0:2]) .......................................................
14.8.9 Pending Interrupt Read Location Registers (INTREQ[0:2]) ...............................................
14.8.10 Interrupt Enable Set Registers (REQENASET[0:2]) ......................................................
14.8.11 Interrupt Enable Clear Registers (REQENACLR[0:2]) ...................................................
14.8.12 Wake-Up Enable Set Registers (WAKEENASET[0:2])...................................................
14.8.13 Wake-Up Enable Clear Registers (WAKEENACLR[0:2]) ................................................
14.8.14 IRQ Interrupt Vector Register (IRQVECREG) .............................................................
14.8.15 FIQ Interrupt Vector Register (FIQVECREG) .............................................................
14.8.16 Capture Event Register (CAPEVT) .........................................................................
14.8.17 VIM Interrupt Control Registers (CHANCTRL[0:23]) .....................................................

404
404
405
405
406
407
408
410
411
411
412
412
413
414
415
415
415
416
418
419
419
420
420
421
422
422
423
424
425
426
427
428
429
429
430
431

Enhanced Quadrature Encoder Pulse (eQEP) Module ........................................................... 433
15.1
15.2

15.3

15.4

15.5

Introduction ................................................................................................................
Description .................................................................................................................
15.2.1 eQEP Inputs .....................................................................................................
15.2.2 Functional Description .........................................................................................
15.2.3 eQEP Memory Map ............................................................................................
Quadrature Decoder Unit (QDU) .......................................................................................
15.3.1 Position Counter Input Modes ................................................................................
15.3.2 eQEP Input Polarity Selection ................................................................................
15.3.3 Position-Compare Sync Output ...............................................................................
Position Counter and Control Unit (PCCU) ............................................................................
15.4.1 Position Counter Operating Modes ...........................................................................
15.4.2 Position Counter Latch .........................................................................................
15.4.3 Position Counter Initialization .................................................................................
15.4.4 eQEP Position-compare Unit ..................................................................................
eQEP Edge Capture Unit ................................................................................................

SPNU517C – March 2018
Submit Documentation Feedback

Contents
Copyright © 2018, Texas Instruments Incorporated

434
436
436
437
438
439
439
442
442
442
442
445
447
447
449
9

www.ti.com

15.6
15.7
15.8
15.9

16

452
452
453
454
454
455
455
455
456
456
456
457
457
457
458
459
460
462
463
464
465
466
467
468
469
469
470
470

Analog To Digital Converter (ADC) Module .......................................................................... 471
16.1
16.2

16.3

16.4

10

eQEP Watchdog ..........................................................................................................
Unit Timer Base ...........................................................................................................
eQEP Interrupt Structure ................................................................................................
eQEP Registers ...........................................................................................................
15.9.1 eQEP Position Counter Register (QPOSCNT) .............................................................
15.9.2 eQEP Position Counter Initialization Register (QPOSINIT) ...............................................
15.9.3 eQEP Maximum Position Count Register (QPOSMAX) ...................................................
15.9.4 eQEP Position-Compare Register (QPOSCMP) ...........................................................
15.9.5 eQEP Index Position Latch Register (QPOSILAT) .........................................................
15.9.6 eQEP Strobe Position Latch Register (QPOSSLAT) ......................................................
15.9.7 eQEP Position Counter Latch Register (QPOSLAT).......................................................
15.9.8 eQEP Unit Timer Register (QUTMR) ........................................................................
15.9.9 eQEP Register Unit Period Register (QUPRD) .............................................................
15.9.10 eQEP Watchdog Timer Register (QWDTMR) .............................................................
15.9.11 eQEP Watchdog Period Register (QWDPRD) ............................................................
15.9.12 eQEP Decoder Control Register (QDECCTL) .............................................................
15.9.13 eQEP Control Register (QEPCTL) ..........................................................................
15.9.14 eQEP Capture Control Register (QCAPCTL) .............................................................
15.9.15 eQEP Position-Compare Control Register (QPOSCTL) .................................................
15.9.16 eQEP Interrupt Enable Register (QEINT) ..................................................................
15.9.17 eQEP Interrupt Flag Register (QFLG) ......................................................................
15.9.18 eQEP Interrupt Clear Register (QCLR) ....................................................................
15.9.19 eQEP Interrupt Force Register (QFRC) ....................................................................
15.9.20 eQEP Status Register (QEPSTS) ...........................................................................
15.9.21 eQEP Capture Timer Register (QCTMR) ..................................................................
15.9.22 eQEP Capture Period Register (QCPRD) .................................................................
15.9.23 eQEP Capture Timer Latch Register (QCTMRLAT) ......................................................
15.9.24 eQEP Capture Period Latch Register (QCPRDLAT) .....................................................

Overview ................................................................................................................... 472
Introduction ................................................................................................................ 472
16.2.1 Input Multiplexor ................................................................................................ 472
16.2.2 Self-Test and Calibration Cell ................................................................................. 472
16.2.3 Analog-to-Digital Converter Core ............................................................................. 474
16.2.4 Sequencer ....................................................................................................... 474
16.2.5 Conversion Groups ............................................................................................. 475
Basic Features and Usage of the ADC ................................................................................ 475
16.3.1 How to Select Between 12-bit and 10-bit Resolutions ..................................................... 475
16.3.2 How to Set Up the ADCLK Speed ............................................................................ 475
16.3.3 How to Set Up the Input Channel Acquisition Time ........................................................ 475
16.3.4 How to Select an Input Channel for Conversion............................................................ 476
16.3.5 How to Select Between Single Conversion Sequence or Continuous Conversions ................... 476
16.3.6 How to Start a Conversion .................................................................................... 476
16.3.7 How to Know When the Group Conversion is Completed ................................................ 476
16.3.8 How Results are Stored in the Results’ Memory ........................................................... 477
16.3.9 How to Read the Results from the Results’ Memory ...................................................... 477
16.3.10 How to Stop a Conversion ................................................................................... 480
16.3.11 Example Sequence for Basic Configuration of ADC Module ............................................ 481
Advanced Conversion Group Configuration Options................................................................. 482
16.4.1 Group Trigger Options ......................................................................................... 483
16.4.2 Analog Input Channel Selection Mode Options............................................................. 483
16.4.3 Single or Continuous Conversion Modes .................................................................... 484
16.4.4 Conversion Group Freeze Capability ........................................................................ 485

Contents

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

16.4.5 Conversion Group Memory Overrun Option ................................................................ 486
16.4.6 Response on Writing Non-Zero Value to Conversion Group’s Channel Select Register ............. 486
16.4.7 Conversion Result Size on Reading: 8-bit, 10-bit, or 12-bit ............................................... 487
16.4.8 Option to Read Group Channel ID Along With Conversion Result ...................................... 487
16.5 ADC Module Basic Interrupts ........................................................................................... 488
16.5.1 Group Conversion End Interrupt .............................................................................. 488
16.5.2 Group Memory Threshold Interrupt .......................................................................... 488
16.5.3 Group Memory Overrun Interrupt ............................................................................. 488
16.6 ADC Magnitude Threshold Interrupts .................................................................................. 489
16.6.1 Magnitude Threshold Interrupt Configuration ............................................................... 489
16.6.2 Magnitude Threshold Interrupt Comparison Mask Configuration ........................................ 489
16.6.3 Magnitude Threshold Interrupt Enable / Disable Control .................................................. 489
16.6.4 Magnitude Threshold Interrupt Flags......................................................................... 489
16.6.5 Magnitude Threshold Interrupt Offset Register ............................................................. 489
16.7 ADC Special Modes ...................................................................................................... 490
16.7.1 ADC Error Calibration Mode .................................................................................. 490
16.7.2 ADC Self-Test Mode ........................................................................................... 494
16.7.3 ADC Power-Down Mode ....................................................................................... 495
16.7.4 ADC Sample Capacitor Discharge Mode .................................................................... 496
16.8 ADC Results’ RAM Special Features .................................................................................. 497
16.8.1 ADC Results’ RAM Auto-Initialization ........................................................................ 497
16.8.2 ADC Results’ RAM Test Mode ................................................................................ 497
16.8.3 ADC Results’ RAM Parity...................................................................................... 497
16.9 ADEVT Pin General Purpose I/O Functionality ....................................................................... 498
16.9.1 GPIO Functionality ............................................................................................. 498
16.9.2 Summary ......................................................................................................... 499
16.10 ADC Registers ............................................................................................................ 500
16.10.1 ADC Reset Control Register (ADRSTCR) ................................................................. 502
16.10.2 ADC Operating Mode Control Register (ADOPMODECR) .............................................. 503
16.10.3 ADC Clock Control Register (ADCLOCKCR).............................................................. 504
16.10.4 ADC Calibration Mode Control Register (ADCALCR) .................................................... 505
16.10.5 ADC Event Group Operating Mode Control Register (ADEVMODECR) .............................. 507
16.10.6 ADC Group1 Operating Mode Control Register (ADG1MODECR) ..................................... 510
16.10.7 ADC Group2 Operating Mode Control Register (ADG2MODECR) ..................................... 513
16.10.8 ADC Event Group Trigger Source Select Register (ADEVSRC) ....................................... 516
16.10.9 ADC Group1 Trigger Source Select Register (ADG1SRC) .............................................. 517
16.10.10 ADC Group2 Trigger Source Select Register (ADG2SRC) ............................................ 518
16.10.11 ADC Event Interrupt Enable Control Register (ADEVINTENA)........................................ 519
16.10.12 ADC Group1 Interrupt Enable Control Register (ADG1INTENA) ..................................... 520
16.10.13 ADC Group2 Interrupt Enable Control Register (ADG2INTENA) ..................................... 521
16.10.14 ADC Event Group Interrupt Flag Register (ADEVINTFLG) ............................................ 522
16.10.15 ADC Group1 Interrupt Flag Register (ADG1INTFLG) .................................................. 523
16.10.16 ADC Group2 Interrupt Flag Register (ADG2INTFLG) .................................................. 524
16.10.17 ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) ........................ 525
16.10.18 ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR) .............................. 525
16.10.19 ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) .............................. 526
16.10.20 ADC Results Memory Configuration Register (ADBNDCR) ........................................... 527
16.10.21 ADC Results Memory Size Configuration Register (ADBNDEND) .................................... 528
16.10.22 ADC Event Group Sampling Time Configuration Register (ADEVSAMP) ........................... 529
16.10.23 ADC Group1 Sampling Time Configuration Register (ADG1SAMP).................................. 529
16.10.24 ADC Group2 Sampling Time Configuration Register (ADG2SAMP).................................. 530
16.10.25 ADC Event Group Status Register (ADEVSR) .......................................................... 531
16.10.26 ADC Group1 Status Register (ADG1SR) ................................................................. 532
SPNU517C – March 2018
Submit Documentation Feedback

Contents
Copyright © 2018, Texas Instruments Incorporated

11

www.ti.com

16.10.27
16.10.28
16.10.29
16.10.30
16.10.31
16.10.32
16.10.33
16.10.34
16.10.35
16.10.36
16.10.37
16.10.38
16.10.39
16.10.40
16.10.41
16.10.42
16.10.43
16.10.44
16.10.45
16.10.46
16.10.47
16.10.48
16.10.49
16.10.50
16.10.51
16.10.52
16.10.53
16.10.54
16.10.55
16.10.56
16.10.57
16.10.58
16.10.59
16.10.60
16.10.61
16.10.62
16.10.63
16.10.64
16.10.65
16.10.66
16.10.67
16.10.68
16.10.69
16.10.70
16.10.71
16.10.72
16.10.73
16.10.74

17

High-End Timer (N2HET) Module ........................................................................................ 566
17.1

17.2
12

ADC Group2 Status Register (ADG2SR) ................................................................. 533
ADC Event Group Channel Select Register (ADEVSEL) .............................................. 534
ADC Group1 Channel Select Register (ADG1SEL) ..................................................... 535
ADC Group2 Channel Select Register (ADG2SEL) ..................................................... 536
ADC Calibration and Error Offset Correction Register (ADCALR) .................................... 537
ADC State Machine Status Register (ADSMSTATE) ................................................... 537
ADC Channel Last Conversion Value Register (ADLASTCONV) ..................................... 538
ADC Event Group Results' FIFO Register (ADEVBUFFER) ........................................... 539
ADC Group1 Results FIFO Register (ADG1BUFFER) ................................................. 540
ADC Group2 Results FIFO Register (ADG2BUFFER) ................................................. 541
ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER) ........................ 542
ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER)............................... 543
ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER)............................... 544
ADC ADEVT Pin Direction Control Register (ADEVTDIR) ............................................. 545
ADC ADEVT Pin Output Value Control Register (ADEVTOUT) ....................................... 546
ADC ADEVT Pin Input Value Register (ADEVTIN) ..................................................... 546
ADC ADEVT Pin Set Register (ADEVTSET) ............................................................ 547
ADC ADEVT Pin Clear Register (ADEVTCLR) .......................................................... 547
ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) ......................................... 548
ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) ........................................ 548
ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL)......................................... 549
ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN) ................. 549
ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) ....................... 550
ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) ....................... 551
ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR) ......................... 552
ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK).............................. 554
ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) ................... 555
ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR) ................ 555
ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG) ................................ 556
ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF) .............................. 556
ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR) ........................... 557
ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR).................................. 557
ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR).................................. 558
ADC Event Group RAM Write Address Register (ADEVRAMWRADDR) ............................ 558
ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) .................................. 559
ADC Group2 RAM Write Address Register (ADG2RAMWRADDR) .................................. 559
ADC Parity Control Register (ADPARCR) ................................................................ 560
ADC Parity Error Address Register (ADPARADDR) .................................................... 560
ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL) ...................................... 561
ADC Event Group Channel Selection Mode Control Register (ADEVCHNSELMODECTRL) ..... 561
ADC Group1 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL) ........... 562
ADC Group2 Channel Selection Mode Control Register (ADG2CHNSELMODECTRL) ........... 562
ADC Event Group Current Count Register (ADEVCURRCOUNT) ................................... 563
ADC Event Group Maximum Count Register (ADEVMAXCOUNT) ................................... 563
ADC Group1 Current Count Register (ADG1CURRCOUNT) .......................................... 564
ADC Group1 Maximum Count Register (ADG1MAXCOUNT) ......................................... 564
ADC Group2 Current Count Register (ADG2CURRCOUNT) .......................................... 565
ADC Group2 Maximum Count Register (ADG2MAXCOUNT) ......................................... 565

Features ....................................................................................................................
17.1.1 Overview .........................................................................................................
17.1.2 Block Diagram ...................................................................................................
N2HET Functional Description ..........................................................................................

Contents

567
567
570
572

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

17.3
17.4

17.5

18

17.2.1 Specialized Timer Micromachine .............................................................................
17.2.2 N2HET RAM Organization ....................................................................................
17.2.3 Time Base .......................................................................................................
17.2.4 Host Interface ...................................................................................................
17.2.5 I/O Control .......................................................................................................
17.2.6 Suppression Filters .............................................................................................
17.2.7 Interrupts and Exceptions .....................................................................................
17.2.8 Hardware Priority Scheme: ....................................................................................
17.2.9 N2HET Requests to the HTU .................................................................................
Angle Functions ...........................................................................................................
17.3.1 Software Angle Generator .....................................................................................
N2HET Control Registers ................................................................................................
17.4.1 Global Configuration Register (HETGCR) ...................................................................
17.4.2 Prescale Factor Register (HETPFR) .........................................................................
17.4.3 N2HET Current Address Register (HETADDR) ............................................................
17.4.4 Offset Index Priority Level 1 Register (HETOFF1) .........................................................
17.4.5 Offset Index Priority Level 2 Register (HETOFF2) .........................................................
17.4.6 Interrupt Enable Set Register (HETINTENAS)..............................................................
17.4.7 Interrupt Enable Clear Register (HETINTENAC) ...........................................................
17.4.8 Exception Control Register 1 (HETEXC1) ...................................................................
17.4.9 Exception Control Register 2 (HETEXC2) ...................................................................
17.4.10 Interrupt Priority Register (HETPRY) .......................................................................
17.4.11 Interrupt Flag Register (HETFLG) ..........................................................................
17.4.12 AND Share Control Register (HETAND) ..................................................................
17.4.13 HR Share Control Register (HETHRSH) ...................................................................
17.4.14 XOR Share Control Register (HETXOR) ...................................................................
17.4.15 Request Enable Set Register (HETREQENS) ............................................................
17.4.16 Request Enable Clear Register (HETREQENC) ..........................................................
17.4.17 NHET Direction Register (HETDIR) ........................................................................
17.4.18 N2HET Data Input Register (HETDIN) .....................................................................
17.4.19 N2HET Data Output Register (HETDOUT) ................................................................
17.4.20 NHET Data Set Register (HETDSET) ......................................................................
17.4.21 N2HET Data Clear Register (HETDCLR) ..................................................................
17.4.22 N2HET Open Drain Register (HETPDR) ...................................................................
17.4.23 N2HET Pull Disable Register (HETPULDIS) ..............................................................
17.4.24 N2HET Pull Select Register (HETPSL) ....................................................................
17.4.25 Parity Control Register (HETPCR) ..........................................................................
17.4.26 Parity Address Register (HETPAR) .........................................................................
17.4.27 Parity Pin Register (HETPPR) ...............................................................................
17.4.28 Suppression Filter Preload Register (HETSFPRLD) .....................................................
17.4.29 Suppression Filter Enable Register (HETSFENA) ........................................................
17.4.30 Loop Back Pair Select Register (HETLBPSEL) ...........................................................
17.4.31 Loop Back Pair Direction Register (HETLBPDIR) ........................................................
17.4.32 N2HET Pin Disable Register (HETPINDIS) ...............................................................
Instruction Set .............................................................................................................
17.5.1 Instruction Summary ...........................................................................................
17.5.2 Abbreviations, Encoding Formats and Bits ..................................................................
17.5.3 Instruction Description .........................................................................................

572
576
579
582
583
598
599
600
601
601
601
605
606
608
609
610
611
612
612
613
614
615
615
616
617
618
619
619
620
621
621
622
622
623
623
624
625
626
627
628
628
629
630
631
632
632
634
637

High-End Timer Transfer Unit (HTU) Module ........................................................................ 703
18.1
18.2

Overview ...................................................................................................................
18.1.1 Features..........................................................................................................
Module Operation .........................................................................................................
18.2.1 Data Transfers Between Main RAM and N2HET RAM ....................................................

SPNU517C – March 2018
Submit Documentation Feedback

Contents
Copyright © 2018, Texas Instruments Incorporated

704
704
704
706
13

www.ti.com

18.3

18.4

18.5

18.6

19

General-Purpose Input/Output (GIO) Module ........................................................................ 755
19.1
19.2

14

18.2.2 Arbitration of HTU Elements and Frames ................................................................... 711
18.2.3 Conditions for Frame Transfer Interruption.................................................................. 712
18.2.4 HTU Overload and Request Lost Detection ................................................................. 712
18.2.5 Memory Protection ............................................................................................. 714
18.2.6 Control Packet RAM Parity Checking ........................................................................ 715
Use Cases ................................................................................................................. 717
18.3.1 Example: Single Element Transfer with One Trigger Request ........................................... 717
18.3.2 Example: Multiple Element Transfer with One Trigger Request.......................................... 717
18.3.3 Example: 64-Bit-Transfer of Control Field and Data Fields ............................................... 719
Control Registers ......................................................................................................... 720
18.4.1 Global Control Register (HTU GC) ........................................................................... 721
18.4.2 Control Packet Enable Register (HTU CPENA) ............................................................ 722
18.4.3 Control Packet (CP) Busy Register 0 (HTU BUSY0) ...................................................... 723
18.4.4 Control Packet (CP) Busy Register 1 (HTU BUSY1) ...................................................... 724
18.4.5 Control Packet (CP) Busy Register 2 (HTU BUSY2) ...................................................... 724
18.4.6 Control Packet (CP) Busy Register 3 (HTU BUSY3) ...................................................... 725
18.4.7 Active Control Packet and Error Register (HTU ACPE) ................................................... 725
18.4.8 Request Lost and Bus Error Control Register (HTU RLBECTRL) ....................................... 727
18.4.9 Buffer Full Interrupt Enable Set Register (HTU BFINTS).................................................. 728
18.4.10 Buffer Full Interrupt Enable Clear Register (HTU BFINTC) ............................................. 728
18.4.11 Interrupt Mapping Register (HTU INTMAP) ............................................................... 729
18.4.12 Interrupt Offset Register 0 (HTU INTOFF0) ............................................................... 730
18.4.13 Interrupt Offset Register 1 (HTU INTOFF1) ............................................................... 731
18.4.14 Buffer Initialization Mode Register (HTU BIM) ............................................................ 732
18.4.15 Request Lost Flag Register (HTU RLOSTFL) ............................................................. 734
18.4.16 Buffer Full Interrupt Flag Register (HTU BFINTFL) ....................................................... 734
18.4.17 BER Interrupt Flag Register (HTU BERINTFL) ........................................................... 735
18.4.18 Memory Protection 1 Start Address Register (HTU MP1S) ............................................. 736
18.4.19 Memory Protection 1 End Address Register (HTU MP1E) .............................................. 736
18.4.20 Debug Control Register (HTU DCTRL) .................................................................... 737
18.4.21 Watch Point Register (HTU WPR) .......................................................................... 738
18.4.22 Watch Mask Register (HTU WMR) ......................................................................... 738
18.4.23 Module Identification Register (HTU ID) ................................................................... 739
18.4.24 Parity Control Register (HTU PCR) ......................................................................... 740
18.4.25 Parity Address Register (HTU PAR) ........................................................................ 741
18.4.26 Memory Protection Control and Status Register (HTU MPCS) ......................................... 742
18.4.27 Memory Protection Start Address Register 0 (HTU MP0S) ............................................. 745
18.4.28 Memory Protection End Address Register (HTU MP0E)................................................. 745
Double Control Packet Configuration Memory ........................................................................ 746
18.5.1 Initial Full Address A Register (HTU IFADDRA) ............................................................ 747
18.5.2 Initial Full Address B Register (HTU IFADDRB) ............................................................ 747
18.5.3 Initial N2HET Address and Control Register (HTU IHADDRCT) ......................................... 748
18.5.4 Initial Transfer Count Register (HTU ITCOUNT) ........................................................... 749
18.5.5 Current Full Address A Register (HTU CFADDRA) ........................................................ 750
18.5.6 Current Full Address B Register (HTU CFADDRB) ........................................................ 751
18.5.7 Current Frame Count Register (HTU CFCOUNT).......................................................... 752
Examples .................................................................................................................. 753
18.6.1 Application Examples for Setting the Transfer Modes of CP A and B of a DCP ....................... 753
18.6.2 Software Example Sequence Assuming Circular Mode for Both CP A and B.......................... 753
18.6.3 Example of an Interrupt Dispatch Flow for a Request Lost Interrupt .................................... 754
Overview ................................................................................................................... 756
Quick Start Guide ......................................................................................................... 757

Contents

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

19.3

19.4

19.5

19.6

20

Functional Description of GIO Module .................................................................................
19.3.1 I/O Functions ....................................................................................................
19.3.2 Interrupt Function ...............................................................................................
19.3.3 GIO Block Diagram .............................................................................................
Device Modes of Operation .............................................................................................
19.4.1 Emulation Mode .................................................................................................
19.4.2 Power-Down Mode (Low-Power Mode)......................................................................
GIO Control Registers ....................................................................................................
19.5.1 GIO Global Control Register (GIOGCR0) ...................................................................
19.5.2 GIO Interrupt Detect Register (GIOINTDET) ................................................................
19.5.3 GIO Interrupt Polarity Register (GIOPOL) ...................................................................
19.5.4 GIO Interrupt Enable Registers (GIOENASET and GIOENACLR) .......................................
19.5.5 GIO Interrupt Priority Registers (GIOLVLSET and GIOLVLCLR) ........................................
19.5.6 GIO Interrupt Flag Register (GIOFLG) .......................................................................
19.5.7 GIO Offset Register 1 (GIOOFF1) ............................................................................
19.5.8 GIO Offset B Register (GIOOFF2) ...........................................................................
19.5.9 GIO Emulation A Register (GIOEMU1) ......................................................................
19.5.10 GIO Emulation B Register (GIOEMU2) ....................................................................
19.5.11 GIO Data Direction Registers (GIODIR[A-B]) .............................................................
19.5.12 GIO Data Input Registers (GIODIN[A-B]) ..................................................................
19.5.13 GIO Data Output Registers (GIODOUT[A-B]) .............................................................
19.5.14 GIO Data Set Registers (GIODSET[A-B]) .................................................................
19.5.15 GIO Data Clear Registers (GIODCLR[A-B]) ...............................................................
19.5.16 GIO Open Drain Registers (GIOPDR[A-B]) ................................................................
19.5.17 GIO Pull Disable Registers (GIOPULDIS[A-B]) ...........................................................
19.5.18 GIO Pull Select Registers (GIOPSL[A-B]) .................................................................
I/O Control Summary .....................................................................................................

759
759
760
760
762
762
762
763
764
765
766
767
769
772
773
774
775
776
777
777
778
778
779
779
780
780
781

Controller Area Network (DCAN) Module ............................................................................ 782
20.1
20.2

20.3

Overview ..................................................................................................................
20.1.1 Features .........................................................................................................
Module Operation .........................................................................................................
20.2.1 Functional Description .........................................................................................
20.2.2 CAN Blocks .....................................................................................................
20.2.3 CAN Bit Timing .................................................................................................
20.2.4 CAN Module Configuration ...................................................................................
20.2.5 Message RAM ..................................................................................................
20.2.6 Message Interface Register Sets ............................................................................
20.2.7 Message Object Configurations ..............................................................................
20.2.8 Message Handling .............................................................................................
20.2.9 CAN Message Transfer .......................................................................................
20.2.10 Interrupt Functionality ........................................................................................
20.2.11 Global Power-Down Mode ..................................................................................
20.2.12 Local Power-Down Mode ....................................................................................
20.2.13 GIO Support ...................................................................................................
20.2.14 Test Modes ....................................................................................................
20.2.15 Parity Check Mechanism ....................................................................................
20.2.16 Debug/Suspend Mode .......................................................................................
DCAN Control Registers ................................................................................................
20.3.1 CAN Control Register (DCAN CTL) ..........................................................................
20.3.2 Error and Status Register (DCAN ES) .......................................................................
20.3.3 Error Counter Register (DCAN ERRC) ......................................................................
20.3.4 Bit Timing Register (DCAN BTR) .............................................................................
20.3.5 Interrupt Register (DCAN INT) ................................................................................

SPNU517C – March 2018
Submit Documentation Feedback

Contents
Copyright © 2018, Texas Instruments Incorporated

783
783
783
783
784
786
790
793
797
800
802
807
808
810
811
813
813
817
818
818
820
822
824
825
826
15

www.ti.com

20.3.6 Test Register (DCAN TEST) ..................................................................................
20.3.7 Parity Error Code Register (DCAN PERR) ..................................................................
20.3.8 Core Release Register (DCAN REL) ........................................................................
20.3.9 Auto-Bus-On Time Register (DCAN ABOTR)...............................................................
20.3.10 Transmission Request X Register (DCAN TXRQ X) .....................................................
20.3.11 Transmission Request Registers (DCAN TXRQ12 to DCAN TXRQ78) ...............................
20.3.12 New Data X Register (DCAN NWDAT X) ..................................................................
20.3.13 New Data Registers (DCAN NWDAT12 to DCAN NWDAT78) .........................................
20.3.14 Interrupt Pending X Register (DCAN INTPND X) .........................................................
20.3.15 Interrupt Pending Registers (DCAN INTPND12 to DCAN INTPND78) ................................
20.3.16 Message Valid X Register (DCAN MSGVAL X)...........................................................
20.3.17 Message Valid Registers (DCAN MSGVAL12 to DCAN MSGVAL78) .................................
20.3.18 Interrupt Multiplexer Registers (DCAN INTMUX12 to DCAN INTMUX78).............................
20.3.19 IF1/IF2 Command Registers (DCAN IF1CMD, DCAN IF2CMD)........................................
20.3.20 IF1/IF2 Mask Registers (DCAN IF1MSK, DCAN IF2MSK) ..............................................
20.3.21 IF1/IF2 Arbitration Registers (DCAN IF1ARB, DCAN IF2ARB) .........................................
20.3.22 IF1/IF2 Message Control Registers (DCAN IF1MCTL, DCAN IF2MCTL) .............................
20.3.23 IF1/IF2 Data A and Data B Registers (DCAN IF1DATA/DATB, DCAN IF2DATA/DATB) ...........
20.3.24 IF3 Observation Register (DCAN IF3OBS) ................................................................
20.3.25 IF3 Mask Register (DCAN IF3MSK) ........................................................................
20.3.26 IF3 Arbitration Register (DCAN IF3ARB) ..................................................................
20.3.27 IF3 Message Control Register (DCAN IF3MCTL) ........................................................
20.3.28 IF3 Data A and Data B Registers (DCAN IF3DATA/DATB) .............................................
20.3.29 IF3 Update Enable Registers (DCAN IF3UPD12 to IF3UPD78) ........................................
20.3.30 CAN TX IO Control Register (DCAN TIOC) ...............................................................
20.3.31 CAN RX IO Control Register (DCAN RIOC) ...............................................................

21

Multi-Buffered Serial Peripheral Interface Module (MibSPI) .................................................... 856
21.1

21.2

21.3

21.4
21.5
16

827
828
828
829
829
830
831
832
833
834
835
836
837
838
841
842
843
845
846
848
849
850
851
852
853
854

Overview ...................................................................................................................
21.1.1 Word Format Options ..........................................................................................
21.1.2 Multi-buffering (Mib) Support ..................................................................................
21.1.3 Transmission Lock (Multi-Buffer Mode Master Only) ......................................................
Operating Modes..........................................................................................................
21.2.1 Pin Configurations ..............................................................................................
21.2.2 Data Handling ...................................................................................................
21.2.3 Operation with SPICS ..........................................................................................
21.2.4 Operation with SPIENA ........................................................................................
21.2.5 Five-Pin Operation (Hardware Handshaking) ...............................................................
21.2.6 Data Formats ....................................................................................................
21.2.7 Clocking Modes .................................................................................................
21.2.8 Data Transfer Example ........................................................................................
21.2.9 Decoded and Encoded Chip Select (Master Only) .........................................................
21.2.10 Variable Chip Select Setup and Hold Timing (Master Only).............................................
21.2.11 Hold Chip-Select Active ......................................................................................
21.2.12 Detection of Slave Desynchronization (Master Only) ....................................................
21.2.13 ENA Signal Time-Out (Master Only)........................................................................
21.2.14 Data-Length Error .............................................................................................
21.2.15 Continuous Self-Test (Master/Slave) .......................................................................
21.2.16 Half Duplex Mode .............................................................................................
Test Features..............................................................................................................
21.3.1 Internal Loop-Back Test Mode (Master Only) ...............................................................
21.3.2 Input/Output Loopback Test Mode ...........................................................................
General-Purpose I/O .....................................................................................................
Low-Power Mode .........................................................................................................

Contents

857
857
858
858
858
858
859
862
863
864
865
866
868
869
869
869
871
871
871
872
872
872
872
873
874
874

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

Interrupts ................................................................................................................... 875
21.6.1 Interrupts in Multi-Buffer Mode ................................................................................ 875
21.7 Module Configuration..................................................................................................... 877
21.7.1 Compatibility (SPI) Mode Configuration ..................................................................... 877
21.7.2 MibSPI Mode Configuration ................................................................................... 878
21.8 Control Registers ......................................................................................................... 879
21.8.1 SPI Global Control Register 0 (SPIGCR0) .................................................................. 880
21.8.2 SPI Global Control Register 1 (SPIGCR1) .................................................................. 881
21.8.3 SPI Interrupt Register (SPIINT0) ............................................................................. 882
21.8.4 SPI Interrupt Level Register (SPILVL) ....................................................................... 884
21.8.5 SPI Flag Register (SPIFLG) ................................................................................... 885
21.8.6 SPI Pin Control Register 0 (SPIPC0) ........................................................................ 888
21.8.7 SPI Pin Control Register 1 (SPIPC1) ........................................................................ 889
21.8.8 SPI Pin Control Register 2 (SPIPC2) ........................................................................ 891
21.8.9 SPI Pin Control Register 3 (SPIPC3) ........................................................................ 892
21.8.10 SPI Pin Control Register 4 (SPIPC4) ....................................................................... 893
21.8.11 SPI Pin Control Register 5 (SPIPC5) ....................................................................... 895
21.8.12 SPI Pin Control Register 6 (SPIPC6) ....................................................................... 896
21.8.13 SPI Pin Control Register 7 (SPIPC7) ....................................................................... 898
21.8.14 SPI Pin Control Register 8 (SPIPC8) ....................................................................... 899
21.8.15 SPI Transmit Data Register 0 (SPIDAT0).................................................................. 900
21.8.16 SPI Transmit Data Register 1 (SPIDAT1).................................................................. 901
21.8.17 SPI Receive Buffer Register (SPIBUF)..................................................................... 904
21.8.18 SPI Emulation Register (SPIEMU) .......................................................................... 906
21.8.19 SPI Delay Register (SPIDELAY) ............................................................................ 906
21.8.20 SPI Default Chip Select Register (SPIDEF) ............................................................... 909
21.8.21 SPI Data Format Registers (SPIFMT) ...................................................................... 910
21.8.22 Interrupt Vector 0 (INTVECT0) .............................................................................. 912
21.8.23 Interrupt Vector 1 (INTVECT1) .............................................................................. 913
21.8.24 SPI Pin Control Register 9 (SPIPC9) ....................................................................... 915
21.8.25 Multi-buffer Mode Enable Register (MIBSPIE) ............................................................ 916
21.8.26 TG Interrupt Enable Set Register (TGITENST) ........................................................... 917
21.8.27 TG Interrupt Enable Clear Register (TGITENCR) ........................................................ 918
21.8.28 Transfer Group Interrupt Level Set Register (TGITLVST) ............................................... 919
21.8.29 Transfer Group Interrupt Level Clear Register (TGITLVCR) ............................................ 920
21.8.30 Transfer Group Interrupt Flag Register (TGINTFLAG) ................................................... 921
21.8.31 Tick Count Register (TICKCNT) ............................................................................. 922
21.8.32 Last TG End Pointer (LTGPEND) ........................................................................... 923
21.8.33 TGx Control Registers (TGxCTRL) ......................................................................... 924
21.8.34 Multi-buffer RAM Uncorrectable Parity Error Control Register (UERRCTRL) ......................... 927
21.8.35 Multi-buffer RAM Uncorrectable Parity Error Status Register (UERRSTAT) .......................... 928
21.8.36 RXRAM Uncorrectable Parity Error Address Register (UERRADDR1) ................................ 929
21.8.37 TXRAM Uncorrectable Parity Error Address Register (UERRADDR0) ................................ 930
21.8.38 RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) ................................... 931
21.8.39 I/O-Loopback Test Control Register (IOLPBKTSTCR) ................................................... 932
21.8.40 SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) ..... 934
21.8.41 SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) ..... 936
21.9 Multi-Buffer RAM .......................................................................................................... 938
21.9.1 Multi-Buffer RAM Auto Initialization .......................................................................... 939
21.9.2 Multi-buffer RAM Register Summary ......................................................................... 939
21.9.3 Multi-buffer RAM Transmit Data Register (TXRAM) ....................................................... 940
21.9.4 Multi-buffer RAM Receive Buffer Register (RXRAM) ...................................................... 943
21.10 Parity Memory ............................................................................................................ 945
21.6

SPNU517C – March 2018
Submit Documentation Feedback

Contents
Copyright © 2018, Texas Instruments Incorporated

17

www.ti.com

21.10.1 Example of Parity Memory Organization ...................................................................
21.11 MibSPI Pin Timing Parameters .........................................................................................
21.11.1 Master Mode Timings for SPI/MibSPI ......................................................................
21.11.2 Slave Mode Timings for SPI/MibSPI........................................................................
21.11.3 Master Mode Timing Parameter Details....................................................................
21.11.4 Slave Mode Timing Parameter Details .....................................................................

22

947
948
948
950
951
951

Serial Communication Interface (SCI)/Local Interconnect Network (LIN) Module ...................... 952
Introduction and Features ............................................................................................... 953
22.1.1 SCI Features .................................................................................................... 953
22.1.2 LIN Features..................................................................................................... 954
22.1.3 Block Diagram ................................................................................................... 955
22.2 SCI Communication Formats............................................................................................ 958
22.2.1 SCI Frame Formats ............................................................................................ 958
22.2.2 SCI Timing Mode ............................................................................................... 959
22.2.3 SCI Baud Rate .................................................................................................. 959
22.2.4 SCI Multiprocessor Communication Modes ................................................................. 962
22.2.5 SCI Multi-Buffered Mode....................................................................................... 964
22.3 SCI Interrupts.............................................................................................................. 966
22.3.1 Transmit Interrupt ............................................................................................... 967
22.3.2 Receive Interrupt ................................................................................................ 967
22.3.3 WakeUp Interrupt ............................................................................................... 967
22.3.4 Error Interrupts .................................................................................................. 968
22.4 SCI Configurations........................................................................................................ 969
22.4.1 Receiving Data .................................................................................................. 969
22.4.2 Transmitting Data ............................................................................................... 970
22.5 SCI Low-Power Mode .................................................................................................... 971
22.5.1 Sleep Mode for Multiprocessor Communication ............................................................ 971
22.6 LIN Communication Formats ............................................................................................ 972
22.6.1 LIN Standards ................................................................................................... 972
22.6.2 Message Frame ................................................................................................. 973
22.6.3 Synchronizer .................................................................................................... 975
22.6.4 Baud Rate ....................................................................................................... 975
22.6.5 Header Generation ............................................................................................. 977
22.6.6 Extended Frames Handling ................................................................................... 981
22.6.7 Timeout Control ................................................................................................. 982
22.6.8 TXRX Error Detector (TED) ................................................................................... 983
22.6.9 Message Filtering and Validation ............................................................................. 986
22.6.10 Receive Buffers ................................................................................................ 988
22.6.11 Transmit Buffers .............................................................................................. 988
22.7 LIN Interrupts .............................................................................................................. 989
22.8 LIN Configurations ........................................................................................................ 990
22.8.1 Receiving Data .................................................................................................. 990
22.8.2 Transmitting Data ............................................................................................... 991
22.9 Low-Power Mode ......................................................................................................... 992
22.9.1 Entering Sleep Mode ........................................................................................... 992
22.9.2 Wakeup .......................................................................................................... 993
22.9.3 Wakeup Timeouts .............................................................................................. 994
22.10 Emulation Mode .......................................................................................................... 994
22.11 SCI/LIN Control Registers ............................................................................................... 995
22.11.1 SCI Global Control Register 0 (SCIGCR0) ................................................................ 996
22.11.2 SCI Global Control Register 1 (SCIGCR1) ................................................................ 997
22.11.3 SCI Global Control Register 2 (SCIGCR2) ............................................................... 1001
22.11.4 SCI Set Interrupt Register (SCISETINT) ................................................................. 1002
22.1

18

Contents

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

22.11.5 SCI Clear Interrupt Register (SCICLEARINT) ...........................................................
22.11.6 SCI Set Interrupt Level Register (SCISETINTLVL) .....................................................
22.11.7 SCI Clear Interrupt Level Register (SCICLEARINTLVL) ...............................................
22.11.8 SCI Flags Register (SCIFLR) ..............................................................................
22.11.9 SCI Interrupt Vector Offset 0 (SCIINTVECT0) ...........................................................
22.11.10 SCI Interrupt Vector Offset 1 (SCIINTVECT1) .........................................................
22.11.11 SCI Format Control Register (SCIFORMAT) ...........................................................
22.11.12 Baud Rate Selection Register (BRS) ....................................................................
22.11.13 SCI Data Buffers (SCIED, SCIRD, SCITD) .............................................................
22.11.14 SCI Pin I/O Control Register 0 (SCIPIO0) ..............................................................
22.11.15 SCI Pin I/O Control Register 1 (SCIPIO1) ..............................................................
22.11.16 SCI Pin I/O Control Register 2 (SCIPIO2) ..............................................................
22.11.17 SCI Pin I/O Control Register 3 (SCIPIO3) ..............................................................
22.11.18 SCI Pin I/O Control Register 4 (SCIPIO4) ..............................................................
22.11.19 SCI Pin I/O Control Register 5 (SCIPIO5) ..............................................................
22.11.20 SCI Pin I/O Control Register 6 (SCIPIO6) ..............................................................
22.11.21 SCI Pin I/O Control Register 7 (SCIPIO7) ..............................................................
22.11.22 SCI Pin I/O Control Register 8 (SCIPIO8) ..............................................................
22.11.23 LIN Compare Register (LINCOMPARE) ................................................................
22.11.24 LIN Receive Buffer 0 Register (LINRD0)................................................................
22.11.25 LIN Receive Buffer 1 Register (LINRD1)................................................................
22.11.26 LIN Mask Register (LINMASK) ...........................................................................
22.11.27 LIN Identification Register (LINID) .......................................................................
22.11.28 LIN Transmit Buffer 0 Register (LINTD0) ...............................................................
22.11.29 LIN Transmit Buffer 1 Register (LINTD1) ...............................................................
22.11.30 Maximum Baud Rate Selection Register (MBRS) .....................................................
22.11.31 Input/Output Error Enable Register (IODFTCTRL) ....................................................
22.12 GPIO Functionality ......................................................................................................
22.12.1 GPIO Functionality ..........................................................................................
22.12.2 Under Reset ..................................................................................................
22.12.3 Out of Reset ..................................................................................................
22.12.4 Open-Drain Feature Enabled on a Pin ....................................................................
22.12.5 Summary ......................................................................................................

23

1005
1008
1010
1013
1020
1020
1021
1022
1023
1025
1026
1027
1028
1029
1030
1031
1032
1032
1033
1034
1034
1035
1036
1037
1037
1038
1039
1041
1041
1041
1042
1042
1042

eFuse Controller ............................................................................................................. 1043
23.1
23.2
23.3

23.4

Overview..................................................................................................................
Introduction ...............................................................................................................
eFuse Controller Testing ...............................................................................................
23.3.1 eFuse Controller Connections to ESM .....................................................................
23.3.2 Checking for eFuse Errors After Power Up ................................................................
eFuse Controller Registers.............................................................................................
23.4.1 EFC Boundary Control Register (EFCBOUND) ...........................................................
23.4.2 EFC Pins Register (EFCPINS) ..............................................................................
23.4.3 EFC Error Status Register (EFCERRSTAT)...............................................................
23.4.4 EFC Self Test Cycles Register (EFCSTCY) ...............................................................
23.4.5 EFC Self Test Signature Register (EFCSTSIG) ..........................................................

1044
1044
1044
1044
1044
1047
1047
1049
1050
1050
1051

Revision History ...................................................................................................................... 1052

SPNU517C – March 2018
Submit Documentation Feedback

Contents
Copyright © 2018, Texas Instruments Incorporated

19

www.ti.com

List of Figures

20

1-1.

Block Diagram .............................................................................................................. 60

1-2.

Example: SPIDELAY – FFF7 F448h .................................................................................... 61

2-1.

Architectural Block Diagram .............................................................................................. 63

2-2.

Memory-Map ............................................................................................................... 66

2-3.

Hardware Memory Initialization Protocol ............................................................................... 74

2-4.

SYS Pin Control Register 1 (SYSPC1) (offset = 00h) ................................................................. 87

2-5.

SYS Pin Control Register 2 (SYSPC2) (offset = 04h) ................................................................. 88

2-6.

SYS Pin Control Register 3 (SYSPC3) (offset = 08h) ................................................................. 88

2-7.

SYS Pin Control Register 4 (SYSPC4) (offset = 0Ch) ................................................................ 89

2-8.

SYS Pin Control Register 5 (SYSPC5) (offset = 10h) ................................................................. 89

2-9.

SYS Pin Control Register 6 (SYSPC6) (offset = 14h) ................................................................. 90

2-10.

SYS Pin Control Register 7 (SYSPC7) (offset = 18h) ................................................................. 90

2-11.

SYS Pin Control Register 8 (SYSPC8) (offset = 1Ch) ................................................................ 91

2-12.

SYS Pin Control Register 9 (SYSPC9) (offset = 20h) ................................................................. 91

2-13.

Clock Source Disable Register (CSDIS) (offset = 30h) ............................................................... 92

2-14.

Clock Source Disable Set Register (CSDISSET) (offset = 34h) ..................................................... 93

2-15.

Clock Source Disable Clear Register (CSDISCLR) (offset = 38h) ................................................... 94

2-16.

Clock Domain Disable Register (CDDIS) (offset = 3Ch) ............................................................. 95

2-17.

Clock Domain Disable Set Register (CDDISSET) (offset = 40h) .................................................... 97

2-18.

Clock Domain Disable Clear Register (CDDISCLR) (offset = 44h) .................................................. 98

2-19.

GCLK, HCLK, VCLK, and VCLK2 Source Register (GHVSRC) (offset = 48h) .................................... 99

2-20.

Peripheral Asynchronous Clock Source Register (VCLKASRC) (offset = 4Ch) .................................. 101

2-21.

RTI Clock Source Register (RCLKSRC) (offset = 50h) .............................................................. 102

2-22.

Clock Source Valid Status Register (CSVSTAT) (offset = 54h) .................................................... 103

2-23.

Memory Self-Test Global Control Register (MSTGCR) (offset = 58h) ............................................. 104

2-24.

Memory Hardware Initialization Global Control Register (MINITGCR) (offset = 5Ch) ........................... 105

2-25.

PBIST Controller/Memory Initialization Enable Register (MSINENA) (offset = 60h) ............................. 106

2-26.

Memory Self-Test Fail Status Register (MSTFAIL) (offset = 64h).................................................. 107

2-27.

MSTC Global Status Register (MSTCGSTAT) (offset = 68h)....................................................... 108

2-28.

Memory Hardware Initialization Status Register (MINISTAT) (offset = 6Ch) ..................................... 109

2-29.

PLL Control Register 1 (PLLCTL1) (offset = 70h) .................................................................... 110

2-30.

PLL Control Register 2 (PLLCTL2) (offset = 74h) .................................................................... 112

2-31.

SYS Pin Control Register 10 (SYSPC10) (offset = 78h) ............................................................ 113

2-32.

Die Identification Register, Lower Word (DIEIDL) [offset = 7Ch] ................................................... 114

2-33.

Die Identification Register, Upper Word (DIEIDH) [offset = 80h] ................................................... 114

2-34.

LPO/Clock Monitor Control Register (LPOMONCTL) [offset = 88h] ............................................... 115

2-35.

Clock Test Register (CLKTEST) (offset = 8Ch)....................................................................... 118

2-36.

DFT Control Register (DFTCTRLREG) (offset = 90h) .............................................................. 120

2-37.

DFT Control Register 2 (DFTCTRLREG2) (offset = 94h) .......................................................... 121

2-38.

General Purpose Register (GPREG1) (offset = A0h) ............................................................... 122

2-39.

Imprecise Fault Status Register (IMPFASTS) (offset = A8h) ....................................................... 123

2-40.

Imprecise Fault Write Address Register (IMPFTADD) (offset = ACh) ............................................. 124

2-41.

System Software Interrupt Request 1 Register (SSIR1) (offset = B0h) ........................................... 125

2-42.

System Software Interrupt Request 2 Register (SSIR2) (offset = B4h) ........................................... 125

2-43.

System Software Interrupt Request 3 Register (SSIR3) (offset = B8h) ........................................... 126

2-44.

System Software Interrupt Request 4 Register (SSIR4) (offset = BCh) ........................................... 126

2-45.

RAM Control Register (RAMGCR) (offset = C0h) .................................................................... 127

List of Figures

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

2-46.

Bus Matrix Module Control Register 1 (BMMCR) (offset = C4h) ................................................... 128

2-47.

CPU Reset Control Register (CPURSTCR) (offset = CCh) ........................................................ 129

2-48.

Clock Control Register (CLKCNTRL) (offset = D0h) ................................................................. 130

2-49.

ECP Control Register (ECPCNTL) (offset = D4h) .................................................................... 131

2-50.

DEV Parity Control Register 1 (DEVCR1) (offset = DCh) ........................................................... 132

2-51.

System Exception Control Register (SYSECR) (offset = E0h) ..................................................... 132

2-52.

System Exception Status Register (SYSESR) (offset = E4h) ...................................................... 133

2-53.

System Test Abort Status Register (SYSTASR) (offset = E8h) ................................................... 134

2-54.

Global Status Register (GLBSTAT) [offset = ECh] ................................................................... 135

2-55.

Device Identification Register (DEVID) (offset = F0h) ............................................................... 136

2-56.

Software Interrupt Vector Register (SSIVEC) (offset = F4h) ........................................................ 137

2-57.

System Software Interrupt Flag Register (SSIF) (offset = F8h) .................................................... 138

2-58.

CPU Logic BIST Clock Prescaler (STCLKDIV) (offset = 08h) ...................................................... 139

2-59.

Clock Slip Register (CLKSLIP) (offset = 70h) ........................................................................ 140

2-60.

EFUSE Controller Control Register (EFC_CTLREG) (offset = ECh) .............................................. 141

2-61.

Die Identification Register, Lower Word (DIEIDL_REG0) [offset = F0h] .......................................... 141

2-62.

Die Identification Register, Upper Word (DIEIDH_REG1) [offset = F4h] .......................................... 142

2-63.

Die Identification Register, Lower Word (DIEIDL_REG2) [offset = F8h] .......................................... 142

2-64.

Die Identification Register, Upper Word (DIEIDH_REG3) [offset = FCh] ......................................... 143

2-65.

Peripheral Memory Protection Set Register 0 (PMPROTSET0) (offset = 00h) ................................... 145

2-66.

Peripheral Memory Protection Set Register 1 (PMPROTSET1) (offset = 04h) ................................... 145

2-67.

Peripheral Memory Protection Clear Register 0 (PMPROTCLR0) (offset = 10h) ................................ 146

2-68.

Peripheral Memory Protection Clear Register 1 (PMPROTCLR1) (offset = 14h) ................................ 146

2-69.

Peripheral Protection Set Register 0 (PPROTSET0) (offset = 20h) ............................................... 147

2-70.

Peripheral Protection Set Register 1 (PPROTSET1) (offset = 24h) ............................................... 148

2-71.

Peripheral Protection Set Register 2 (PPROTSET2) (offset = 28h) ............................................... 148

2-72.

Peripheral Protection Set Register 3 (PPROTSET3) (offset = 2Ch) ............................................... 149

2-73.

Peripheral Protection Clear Register 0 (PPROTCLR0) (offset = 40h) ............................................. 149

2-74.

Peripheral Protection Clear Register 1 (PPROTCLR1) (offset = 44h) ............................................. 150

2-75.

Peripheral Protection Clear Register 2 (PPROTCLR2) (offset = 48h) ............................................. 150

2-76.

Peripheral Protection Clear Register 3 (PPROTCLR3) (offset = 4Ch) ............................................ 151

2-77.

Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0) (offset = 60h) ......................... 152

2-78.

Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1) (offset = 64h) ......................... 152

2-79.

Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0) (offset = 70h) ...................... 153

2-80.

Peripheral Memory Power-Down Clear Register 1 (PCSPWRDWNCLR1) (offset = 74h) ...................... 153

2-81.

Peripheral Power-Down Set Register 0 (PSPWRDWNSET0) (offset = 80h) ..................................... 154

2-82.

Peripheral Power-Down Set Register 1 (PSPWRDWNSET1) (offset = 84h) ..................................... 155

2-83.

Peripheral Power-Down Set Register 2 (PSPWRDWNSET2) (offset = 88h) ..................................... 155

2-84.

Peripheral Power-Down Set Register 3 (PSPWRDWNSET3) (offset = 8Ch) ..................................... 156

2-85.

Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0) (offset = A0h) .................................. 156

2-86.

Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1) (offset = A4h) .................................. 157

2-87.

Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2) (offset = A8h) .................................. 157

2-88.

Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR) (offset = ACh) ................................... 158

3-1.

PINMMR1 Control Register ............................................................................................. 160

3-2.

Output Multiplexing Example ........................................................................................... 161

3-3.

REVISION_REG: Revision Register (Offset = 00h) .................................................................. 164

3-4.

BOOT_REG: Boot Mode Register (Offset = 20h) .................................................................... 165

3-5.

KICK_REG0: Kicker Register 0 (Offset = 38h) ....................................................................... 165

3-6.

KICK_REG1: Kicker Register 1 (Offset = 3Ch) ....................................................................... 165

SPNU517C – March 2018
Submit Documentation Feedback

List of Figures
Copyright © 2018, Texas Instruments Incorporated

21

www.ti.com

22

3-7.

ERR_RAW_STATUS_REG: Error Raw Status / Set Register (Offset = E0h) .................................... 166

3-8.

ERR_ENABLED_STATUS_REG: Error Enabled Status / Clear Register (Offset = E4h) ....................... 167

3-9.

ERR_ENABLE_REG: Error Signaling Enable Register (Offset = E8h) ............................................ 168

3-10.

ERR_ENABLE_CLR_REG: Error Signaling Enable Clear Register (Offset = ECh) ............................. 169

3-11.

FAULT_ADDRESS_REG: Fault Address Register (Offset = F4h) ................................................. 169

3-12.

FAULT_STATUS_REG: Fault Status Register (Offset = F8h) ...................................................... 170

3-13.

FAULT_CLEAR_REG: Fault Clear Register (Offset = FCh) ........................................................ 171

3-14.

PINMMRn: Pin Multiplexing Control Registers (Offset = 110h-138h) .............................................. 172

4-1.

ECC Organization for Program Flash (144-Bits Wide) .............................................................. 180

4-2.

ECC Organization for Bank 7 (72-Bits Wide) ......................................................................... 180

4-3.

TI OTP Bank 0 Sector Information ..................................................................................... 181

4-4.

TI OTP Bank 0 Package and Memory Size Information (F008 015Ch) ........................................... 182

4-5.

TI OTP Bank 0 LPO Trim and Max HCLK Information (F008 01B4h) ............................................. 182

4-6.

TI OTP Bank 0 Symbolization Information (F008 01E0h-F008 01FFh) ........................................... 183

4-7.

TI OTP Bank 0 Deliberate ECC Error Information (F008 03F0h-F008 03FFh) ................................... 183

4-8.

Flash Option Control Register (FRDCNTL) [offset = 00h] ........................................................... 191

4-9.

Flash Error Detection and Correction Control Register 1 (FEDACCTRL1) [offset = 08h]....................... 192

4-10.

Flash Error Correction and Correction Control Register 2 (FEDACCTRL2) [offset = 0Ch] ..................... 194

4-11.

Flash Corectable Error Count Register (FCOR_ERR_CNT) [offset = 10h] ....................................... 194

4-12.

Flash Correctable Error Address Register (FCOR_ERR_ADD) [offset = 14h] ................................... 195

4-13.

Flash Correctable Error Position Register (FCOR_ERR_POS) [offset = 18h] .................................... 196

4-14.

Flash Error Detection and Correction Status Register (FEDACSTATUS) [offset = 1Ch] ....................... 197

4-15.

Flash Uncorrectable Error Address Register (FUNC_ERR_ADD) [offset = 20h] ................................. 200

4-16.

Flash Error Detection and Correction Sector Disable Register (FEDACSDIS) [offset = 24h] .................. 201

4-17.

Primary Address Tag Register (FPRIM_ADD_TAG) [offset = 28h] ................................................ 203

4-18.

Duplicate Address Tag Register (FDUP_ADD_TAG) [offset = 2Ch] ............................................... 203

4-19.

Flash Bank Protection Register (FBPROT) [offset = 30h] ........................................................... 204

4-20.

Flash Bank Sector Enable Register (FBSE) [offset = 34h] .......................................................... 204

4-21.

Flash Bank Busy Register (FBBUSY) [offset = 38h] ................................................................. 205

4-22.

Flash Bank Access Control Register (FBAC) [offset = 3Ch] ........................................................ 206

4-23.

Flash Bank Fallback Power Register (FBFALLBACK) [offset = 40h] .............................................. 207

4-24.

Flash Bank/Pump Ready Register (FBPRDY) [offset = 44h] ....................................................... 208

4-25.

Flash Pump Access Control Register 1 (FPAC1) [offset = 48h] .................................................... 209

4-26.

Flash Pump Access Control Register 2 (FPAC2) [offset = 4Ch] ................................................... 209

4-27.

Flash Module Access Control Register (FMAC) [offset = 50h] ..................................................... 210

4-28.

Flash Module Status Register (FMSTAT) [offset = 54h] ............................................................. 211

4-29.

EEPROM Emulation Data MSW Register (FEMU_DMSW) [offset = 58h] ........................................ 213

4-30.

EEPROM Emulation Data LSW Register (FEMU_DLSW) [offset = 5Ch] ......................................... 213

4-31.

EEPROM Emulation ECC Register (FEMU_ECC) [offset = 60h] .................................................. 214

4-32.

EEPROM Emulation Address Register (FEMU_ADDR) [offset = 68h] ............................................ 215

4-33.

Diagnostic Control Register (FDIAGCTRL) [offset = 6Ch] .......................................................... 216

4-34.

Uncorrected Raw Data High Register (FRAW_DATAH) [offset = 70h] ............................................ 218

4-35.

Uncorrected Raw Data Low Register (FRAW_DATAL) [offset = 74h] ............................................. 218

4-36.

Uncorrected Raw ECC Register (FRAW_ECC) [offset = 78h] ...................................................... 219

4-37.

Parity Override Register (FPAR_OVR) [offset = 7Ch] ............................................................... 220

4-38.

Flash Error Detection and Correction Sector Disable Register (FEDACSDIS2) [offset = C0h] ................ 221

4-39.

FSM Register Write Enable (FSM_WR_ENA) [offset = 288h] ...................................................... 223

4-40.

FSM Sector Register (FSM_SECTOR) [offset = 2A4h] .............................................................. 223

4-41.

EEPROM Emulation Configuration Register (EEPROM_CONFIG) [offset = 2B8h] ............................. 224

List of Figures

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

4-42.

EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1) [offset = 308h] ....... 225

4-43.

EEPROM Emulation Error Correction and Correction Control Register 2 (EE_CTRL2) [offset = 30Ch] ...... 226

4-44.

EEPROM Emulation Error Corectable Error Count Register (EE_COR_ERR_CNT) [offset = 310h] ......... 227

4-45.

EEPROM Emulation Correctable Error Address Register (EE_COR_ERR_ADD) [offset = 314h] ............ 227

4-46.

EEPROM Emulation Correctable Error Position Register (EE_COR_ERR_POS) [offset = 318h] ............. 228

4-47.

EEPROM Emulation Error Status Register (EE_STATUS) [offset = 31Ch] ....................................... 229

4-48.

EEPROM Emulation Uncorrectable Error Address Register (EE_UNC_ERR_ADD) [offset = 320h] .......... 230

4-49.

Flash Bank Configuration Register (FCFG_BANK) [offset = 400h] ................................................ 231

5-1.

TCRAM Module Connections ........................................................................................... 233

5-2.

RAM Memory Map ........................................................................................................ 234

5-3.

TCRAM Module Control Register (RAMCTRL) (offset = 00h) ...................................................... 238

5-4.

TCRAM Module Single-Bit Error Correction Threshold Register (RAMTHRESHOLD) (offset = 04h) ......... 239

5-5.

TCRAM Module Single-Bit Error Occurrences Counter Register (RAMOCCUR) (offset = 08h) ............... 240

5-6.

TCRAM Module Interrupt Control Register (RAMINTCTRL) (offset = 0Ch) ...................................... 240

5-7.

TCRAM Module Error Status Register (RAMERRSTATUS) (offset = 10h) ....................................... 241

5-8.

TCRAM Module Single-Bit Error Address Register (RAMSERRADDR) (offset = 14h) .......................... 242

5-9.

TCRAM Module Uncorrectable Error Address Register (RAMUERRADDR) (offset = 1Ch) .................... 243

5-10.

TCRAM Module Test Mode Control Register (RAMTEST) (offset = 30h) ......................................... 244

5-11.

TCRAM Module Test Mode Vector Register (RAMADDRDECVECT) (offset = 38h) ............................ 245

5-12.

TCRAM Module Parity Error Address Register (RAMPERRADDR) (offset = 3Ch) .............................. 245

6-1.

PBIST Block Diagram ................................................................................................... 247

6-2.

PBIST Memory Self-Test Flow Diagram .............................................................................. 249

6-3.

RAM Configuration Register (RAMT) (offset = 160h) ................................................................ 254

6-4.

Datalogger Register (DLR) (offset = 164h) ............................................................................ 255

6-5.

Program Control Register (PCR) (offset = 16Ch) .................................................................... 256

6-6.

PBIST Activate/Clock Enable Register (PACT) (offset = 180h) .................................................... 257

6-7.

PBIST ID Register (PBISTID) (offset = 184h) ......................................................................... 257

6-8.

Override Register (OVER) (offset = 188h) ............................................................................ 258

6-9.

Fail Status Fail Register 0 (FSRF0) (offset = 190h) .................................................................. 259

6-10.

Fail Status Count 0 Register (FSRC0) (offset = 198h) .............................................................. 260

6-11.

Fail Status Count Register 1 (FSRC1) (offset = 19Ch) .............................................................. 260

6-12.

Fail Status Address 0 Register (FSRA0) (offset = 1A0h) ............................................................ 261

6-13.

Fail Status Address 1 Register (FSRA1) (offset = 1A4h) ............................................................ 261

6-14.

Fail Status Data Register 0 (FSRDL0) (offset = 1A8h) .............................................................. 262

6-15.

Fail Status Data Register 1 (FSRDL1) (offset = 1B0h) .............................................................. 262

6-16.

ROM Mask Register (ROM) (offset = 1C0h) .......................................................................... 263

6-17.

ROM Algorithm Mask Register (ALGO) (offset = 1C4h) ............................................................. 263

6-18.

RAM Info Mask Lower Register (RINFOL) (offset = 1C8h) ......................................................... 264

6-19.

RAM Info Mask Upper Register (RINFOU) (offset = 1CCh) ........................................................ 264

7-1.

STC Block Diagram ...................................................................................................... 269

7-2.

Application Self-Test Flow Chart ....................................................................................... 271

7-3.

STC Global Control Register 0 (STCGCR0) (offset = 00h) ......................................................... 274

7-4.

STC Global Control Register 1 (STCGCR1) (offset = 04h) ......................................................... 274

7-5.

Self-Test Run Timeout Counter Preload Register (STCTPR) (offset = 08h) ..................................... 275

7-6.

STC Current ROM Address Register (STC_CADDR) (offset = 0Ch) .............................................. 275

7-7.

STC Current Interval Count Register (STCCICR) (offset = 10h) ................................................... 276

7-8.

Self-Test Global Status Register (STCGSTAT) (offset = 14h) ...................................................... 277

7-9.

Self-Test Fail Status Register (STCFSTAT) (offset = 18h).......................................................... 278

7-10.

CPU1 Current MISR Register 3 (CPU1_CURMISR3) (offset = 1Ch) .............................................. 279

SPNU517C – March 2018
Submit Documentation Feedback

List of Figures
Copyright © 2018, Texas Instruments Incorporated

23

www.ti.com

7-11.

CPU1 Current MISR Register 2 (CPU1_CURMISR2) (offset = 20h) .............................................. 279

7-12.

CPU1 Current MISR Register 1 (CPU1_CURMISR1) (offset = 24h) .............................................. 279

7-13.

CPU1 Current MISR Register 0 (CPU1_CURMISR0) (offset = 28h) .............................................. 279

7-14.

CPU2 Current MISR Register 3 (CPU2_CURMISR3) (offset = 2Ch) .............................................. 280

7-15.

CPU2 Current MISR Register 2 (CPU2_CURMISR2) (offset = 30h) .............................................. 280

7-16.

CPU2 Current MISR Register 1 (CPU2_CURMISR1) (offset = 34h) .............................................. 280

7-17.

CPU2 Current MISR Register 0 (CPU2_CURMISR0) (offset = 38h) .............................................. 280

7-18.

Signature Compare Self Check Register (STCSCSCR) (offset = 3Ch) ........................................... 281

8-1.

Block Diagram ............................................................................................................. 284

8-2.

CCM-R4 Status Register (CCMSR) (offset = FFFF F600h)......................................................... 289

8-3.

CCM-R4 Key Register (CCMKEYR) (offset = FFFF F604h) ........................................................ 290

9-1.

Clock Path From Oscillator Through PLL To Device................................................................. 293

9-2.

Clock Generation Path ................................................................................................... 294

9-3.

Oscillator Implementation ................................................................................................ 295

9-4.

Operation of the FM-PLL Module ....................................................................................... 300

9-5.

PLL Slip Detection and Reset/Bypass Block Diagram ............................................................... 306

9-6.

SSW PLL BIST Control Register 1 (SSWPLL1) (offset = 24h) ..................................................... 310

9-7.

SSW PLL BIST Control Register 2 (SSWPLL2) (offset = 28h) ..................................................... 311

9-8.

SSW PLL BIST Control Register 3 (SSWPLL3) (offset = 2Ch) ..................................................... 312

9-9.

Basic PLL Circuit .......................................................................................................... 313

9-10.

PFD Timing ................................................................................................................ 313

9-11.

PLL Modulation Block Diagram ......................................................................................... 314

9-12.

Frequency versus Time .................................................................................................. 315

10-1.

DCC Block Diagram ..................................................................................................... 318

10-2.

Counter Relationship .................................................................................................... 319

10-3.

Clock1 Slower Than Clock0 - Results in an Error and Stops Counting .......................................... 320

10-4.

Clock1 Faster Than Clock0 - Results in an Error and Stops Counting ........................................... 320

10-5.

Clock1 Not Present - Results in an Error and Stops Counting .................................................... 321

10-6.

Clock0 Not Present - Results in an Error and Stops Counting .................................................... 321

10-7.

DCC Global Control Register (DCCGCTRL) (offset = 00h) ........................................................ 324

10-8.

DCC Revision ID Register (DCCREV) (offset = 04h) ............................................................... 325

10-9.

DCC Counter0 Seed Register (DCCCNT0SEED) (offset = 08h) .................................................. 325

10-10. DCC Valid0 Seed Register (DCCVALID0SEED) (offset = 0Ch) ................................................... 326
10-11. DCC Counter1 Seed Register (DCCCNT1SEED) (offset = 10h) .................................................. 326
10-12. DCC Status Register (DCCSTAT) (offset = 14h) .................................................................... 327
10-13. DCC Counter0 Value Register (DCCCNT0) (offset = 18h) ......................................................... 328
10-14. DCC Valid0 Value Register (DCCVALID0) (offset = 1Ch) .......................................................... 329
10-15. DCC Counter1 Value Register (DCCCNT1) (offset = 20h) ......................................................... 329
10-16. DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) (offset = 24h) ......................... 330
10-17. DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) (offset = 28h) ......................... 330

24

11-1.

Block Diagram ............................................................................................................. 332

11-2.

Interrupt Response Handling ........................................................................................... 333

11-3.

ERROR Pin Response Handling ....................................................................................... 333

11-4.

ERROR Pin Timing - Example 1 ........................................................................................ 335

11-5.

ERROR Pin Timing - Example 2 ....................................................................................... 335

11-6.

ERROR Pin Timing - Example 3 ....................................................................................... 335

11-7.

ERROR Pin Timing - Example 4 ....................................................................................... 336

11-8.

ERROR Pin Timing - Example 5 ....................................................................................... 336

11-9.

ERROR Pin Timing - Example 7 ........................................................................................ 337

List of Figures

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

11-10. ESM Initialization ......................................................................................................... 338
11-11. ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1) [address = FFFF F500h]........... 340
11-12. ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1) [address = FFFF F504h] .......... 340
11-13. ESM Interrupt Enable Set Register 1 (ESMIESR1) [address = FFFF F508h] .................................... 341
11-14. ESM Interrupt Enable Clear Register 1 (ESMIECR1) [address = FFFF F50Ch] ................................. 341
11-15. ESM Interrupt Level Set Register 1 (ESMILSR1) [address = FFFF F510h] ...................................... 342
11-16. ESM Interrupt Level Clear Register 1 (ESMILCR1) [address = FFFF F514h] .................................... 342
11-17. ESM Status Register 1 (ESMSR1) [address = FFFF F518h] ....................................................... 343
11-18. ESM Status Register 2 (ESMSR2) [address = FFFF F51Ch] ...................................................... 343
11-19. ESM Status Register 3 (ESMSR3) [address = FFFF F520h] ....................................................... 344
11-20. ESM ERROR Pin Status Register (ESMEPSR) [address = FFFF F524h] ........................................ 344
11-21. ESM Interrupt Offset High Register (ESMIOFFHR) [address = FFFF F528h] .................................... 345
11-22. ESM Interrupt Offset Low Register (ESMIOFFLR) [address = FFFF F52Ch] .................................... 346
11-23. ESM Low-Time Counter Register (ESMLTCR) [address = FFFF F530h] ......................................... 347
11-24. ESM Low-Time Counter Preload Register (ESMLTCPR) [address = FFFF F534h] ............................. 347
11-25. ESM Error Key Register (ESMEKR) [address = FFFF F538h] ..................................................... 348
11-26. ESM Status Shadow Register 2 (ESMSSR2) [address = FFFF F53Ch] .......................................... 348
11-27. ESM Influence ERROR Pin Set Register 4 (ESMIEPSR4) [address = FFFF F540h] ........................... 349
11-28. ESM Influence ERROR Pin Clear Register 4 (ESMIEPCR4) [address = FFFF F544h] ......................... 349
11-29. ESM Interrupt Enable Set Register 4 (ESMIESR4) [address = FFFF F548h] .................................... 350
11-30. ESM Interrupt Enable Clear Register 4 (ESMIECR4) [address = FFFF F54Ch] ................................. 350
11-31. ESM Interrupt Level Set Register 4 (ESMILSR4) [address = FFFF F550h] ...................................... 351
11-32. ESM Interrupt Level Clear Register 4 (ESMILCR4) [address = FFFF F554h] .................................... 351
11-33. ESM Status Register 4 (ESMSR4) [address = FFFF F558h] ....................................................... 352
12-1.

RTI Block Diagram........................................................................................................ 355

12-2.

Counter Block Diagram .................................................................................................. 356

12-3.

Compare Unit Block Diagram (shows only 1 of 4 blocks for simplification) ....................................... 358

12-4.

Digital Watchdog .......................................................................................................... 358

12-5.

DWD Operation ........................................................................................................... 359

12-6.

Digital Windowed Watchdog Timing Example ........................................................................ 360

12-7.

Digital Windowed Watchdog Operation Example (25% Window) .................................................. 360

12-8.

RTI Global Control Register (RTIGCTRL) [offset = 00] .............................................................. 363

12-9.

RTI Capture Control Register (RTICAPCTRL) [offset = 08h] ....................................................... 364

12-10. RTI Compare Control Register (RTICOMPCTRL) [offset = 0Ch]................................................... 365
12-11. RTI Free Running Counter 0 Register (RTIFRC0) [offset = 10h]................................................... 366
12-12. RTI Up Counter 0 Register (RTIUC0) [offset = 14h] ................................................................. 366
12-13. RTI Compare Up Counter 0 Register (RTICPUC0) [offset = 18h] ................................................. 367
12-14. RTI Capture Free Running Counter 0 Register (RTICAFRC0) [offset = 20h] .................................... 367
12-15. RTI Capture Up Counter 0 Register (RTICAUC0) [offset = 24] .................................................... 368
12-16. RTI Free Running Counter 1 Register (RTIFRC1) [offset = 30h]................................................... 368
12-17. RTI Up Counter 1 Register (RTIUC1) [offset = 34h] ................................................................. 369
12-18. RTI Compare Up Counter 1 Register (RTICPUC1) [offset = 38h] ................................................. 370
12-19. RTI Capture Free Running Counter 1 Register (RTICAFRC1) [offset = 40h] .................................... 371
12-20. RTI Capture Up Counter 1 Register (RTICAUC1) [offset = 44h] ................................................... 371
12-21. RTI Compare 0 Register (RTICOMP0) [offset = 50h] ................................................................ 372
12-22. RTI Update Compare 0 Register (RTIUDCP0) [offset = 54h] ....................................................... 372
12-23. RTI Compare 1 Register (RTICOMP1) [offset = 58h] ................................................................ 373
12-24. RTI Update Compare 1 Register (RTIUDCP1) [offset = 5Ch] ...................................................... 373
12-25. RTI Compare 2 Register (RTICOMP2) [offset = 60h] ................................................................ 374
SPNU517C – March 2018
Submit Documentation Feedback

List of Figures
Copyright © 2018, Texas Instruments Incorporated25

www.ti.com

12-26. RTI Update Compare 2 Register (RTIUDCP2) [offset = 64h] ....................................................... 374
12-27. RTI Compare 3 Register (RTICOMP3) [offset = 68h] ................................................................ 375
12-28. RTI Update Compare 3 Register (RTIUDCP3) [offset = 6Ch] ...................................................... 375
12-29. RTI Set Interrupt Control Register (RTISETINTENA) [offset = 80h] ............................................... 376
12-30. RTI Clear Interrupt Control Register (RTICLEARINTENA) [offset = 84h] ......................................... 378
12-31. RTI Interrupt Flag Register (RTIINTFLAG) [offset = 88h] ........................................................... 380
12-32. Digital Watchdog Control Register (RTIDWDCTRL) [offset = 90h] ................................................ 381
12-33. Digital Watchdog Preload Register (RTIDWDPRLD) [offset = 94h] ................................................ 382
12-34. Watchdog Status Register (RTIWDSTATUS) [offset = 98h] ........................................................ 383
12-35. RTI Watchdog Key Register (RTIDWDKEY) [offset = 9Ch] ......................................................... 384
12-36. RTI Watchdog Down Counter Register (RTIDWDCNTR) [offset = A0h] .......................................... 385
12-37. Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) [offset = A4h] ............................ 385
12-38. Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) [offset = A8h]....................... 386
12-39. RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE) [offset = ACh] ........................... 387
12-40. RTI Compare 0 Clear Register (RTICMP0CLR) [offset = B0h] ..................................................... 388
12-41. RTI Compare 1 Clear Register (RTICMP1CLR) [offset = B4h] ..................................................... 388
12-42. RTI Compare 2 Clear Register (RTICMP2CLR) [offset = B8h] ..................................................... 389
12-43. RTI Compare 3 Clear Register (RTICMP3CLR) [offset = BCh] .................................................... 389
13-1.

CRC Controller Block Diagram For One Channel ................................................................... 391

13-2.

Linear Feedback Shift Register (LFSR) ............................................................................... 392

13-3.

CRC Global Control Register 0 (CRC_CTRL0) [offset = 00h] ...................................................... 396

13-4.

CRC Global Control Register 1 (CRC_CTRL1) [offset = 08h] ...................................................... 396

13-5.

CRC Global Control Register 2 (CRC_CTRL2) [offset = 10h] ...................................................... 397

13-6.

Channel 1 PSA Signature Low Register (PSA_SIGREGL1) [offset = 60h] ....................................... 398

13-7.

Channel 1 PSA Signature High Register (PSA_SIGREGH1) [offset = 64h] ...................................... 398

13-8.

Channel 1 Raw Data Low Register (RAW_DATAREGL1) [offset = 78h].......................................... 399

13-9.

Channel 1 Raw Data High Register (RAW_DATAREGH1) [offset = 7Ch] ........................................ 399

13-10. Channel 2 PSA Signature Low Register (PSA_SIGREGL2) [offset = A0h] ....................................... 400
13-11. Channel 2 PSA Signature High Register (PSA_SIGREGH2) [offset = A4h] ...................................... 400
13-12. Channel 2 Raw Data Low Register (RAW_DATAREGL2) [offset = B8h] ......................................... 401
13-13. Channel 2 Raw Data High Register (RAW_DATAREGH2) [offset = BCh] ........................................ 401
13-14. Data Bus Selection Register (CRC_TRACE_BUS_SEL) [offset = 140h].......................................... 402
14-1.

Device Level Interrupt Block Diagram ................................................................................. 404

14-2.

VIM Interrupt Handling Block Diagram ................................................................................. 407

14-3.

VIM Channel Mapping ................................................................................................... 408

14-4.

VIM in Default State ...................................................................................................... 409

14-5.

VIM in a Programmed State ............................................................................................. 409

14-6.

Interrupt Channel Management ......................................................................................... 410

14-7.

VIM Interrupt Address Memory Map ................................................................................... 411

14-8.

Parity Bit Mapping ........................................................................................................ 413

14-9.

Detail of the IRQ Input ................................................................................................... 414

14-10. Capture Event Sources .................................................................................................. 415
14-11. Interrupt Vector Table Parity Flag Register (PARFLG) [offset = ECh] ............................................. 419
14-12. Interrupt Vector Table Parity Control Register (PARCTL) [offset = F0h] .......................................... 419
14-13. Address Parity Error Register (ADDERR) [offset = F4h] ............................................................ 420
14-14. Fall-Back Address Parity Error Register (FBPARERR) [offset = F8h] ............................................. 420
14-15. IRQ Index Offset Vector Register (IRQINDEX) [offset = 00h] ...................................................... 422
14-16. FIQ Index Offset Vector Register (FIQINDEX) [offset = 04h] ....................................................... 422
14-17. FIQ/IRQ Program Control Register 0 (FIRQPR0) [offset = 10h] ................................................... 423
26

List of Figures

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

14-18. FIQ/IRQ Program Control Register 1 (FIRQPR1) [offset = 14h] ................................................... 423
14-19. FIQ/IRQ Program Control Register 2 (FIRQPR2) [offset = 18h] ................................................... 423
14-20. Pending Interrupt Read Location Register 0 (INTREQ0) [offset = 20h] ........................................... 424
14-21. Pending Interrupt Read Location Register 1 (INTREQ1) Register [offset = 24h] ................................ 424
14-22. Pending Interrupt Read Location Register 2 (INTREQ2) Register [offset = 28h] ................................ 424
14-23. Interrupt Enable Set Register 0 (REQENASET0) [offset = 30h] .................................................... 425
14-24. Interrupt Enable Set Register 1 (REQENASET1) [offset = 34h] .................................................... 425
14-25. Interrupt Enable Set Register 2 (REQENASET2) [offset = 38h] .................................................... 425
14-26. Interrupt Enable Clear Register 0 (REQENACLR0) [offset = 40h] ................................................. 426
14-27. Interrupt Enable Clear Register 1 (REQENACLR1) [offset = 44h] ................................................. 426
14-28. Interrupt Enable Clear Register 2 (REQENACLR2) [offset = 48h] ................................................. 426
14-29. Wake-Up Enable Set Register 0 (WAKEENASET0) [offset = 50h] ................................................ 427
14-30. Wake-Up Enable Set Register 1 (WAKEENASET1) [offset = 54h] ................................................ 427
14-31. Wake-Up Enable Set Register 2 (WAKEENASET2) [offset = 58h] ................................................ 427
14-32. Wake-Up Enable Clear Register 0 (WAKEENACLR0) [offset = 60h] .............................................. 428
14-33. Wake-Up Enable Clear Register 1 (WAKEENACLR1) [offset = 64h] .............................................. 428
14-34. Wake-Up Enable Clear Register 2 (WAKEENACLR2) [offset = 68h] .............................................. 428
14-35. IRQ Interrupt Vector Register (IRQVECREG) [offset = 70h] ........................................................ 429
14-36. IRQ Interrupt Vector Register (FIQVECREG) [offset = 74h] ........................................................ 429
14-37. Capture Event Register (CAPEVT) [offset = 78h] .................................................................... 430
14-38. Interrupt Control Registers (CHANCTRL[0:23]) [offset = 80h-DCh]................................................ 431
15-1.

Optical Encoder Disk ..................................................................................................... 434

15-2.

QEP Encoder Output Signal for Forward/Reverse Movement ...................................................... 434

15-3.

Index Pulse Example ..................................................................................................... 435

15-4.

Functional Block Diagram of the eQEP Peripheral ................................................................... 437

15-5.

Functional Block Diagram of Decoder Unit ............................................................................ 439

15-6.

Quadrature Decoder State Machine.................................................................................... 440

15-7.

Quadrature-clock and Direction Decoding ............................................................................. 441

15-8.

Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or F9Fh) ................ 443

15-9.

Position Counter Underflow/Overflow (QPOSMAX = 4) ............................................................. 444

15-10. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1) ................................................. 446
15-11. Strobe Event Latch (QEPCTL[SEL] = 1)............................................................................... 446
15-12. eQEP Position-compare Unit ............................................................................................ 447
15-13. eQEP Position-compare Event Generation Points ................................................................... 448
15-14. eQEP Position-compare Sync Output Pulse Stretcher .............................................................. 448
15-15. eQEP Edge Capture Unit ................................................................................................ 450
15-16. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010) .................................. 450
15-17. eQEP Edge Capture Unit - Timing Details ............................................................................ 451
15-18. eQEP Watchdog Timer .................................................................................................. 452
15-19. eQEP Unit Time Base .................................................................................................... 452
15-20. EQEP Interrupt Generation .............................................................................................. 453
15-21. eQEP Position Counter (QPOSCNT) Register (offset = 00h)....................................................... 454
15-22. eQEP Position Counter Initialization (QPOSINIT) Register (offset = 04h) ........................................ 455
15-23. eQEP Maximum Position Count Register (QPOSMAX) Register (offset = 08h) ................................. 455
15-24. eQEP Position-Compare (QPOSCMP) Register (offset = 0Ch) .................................................... 455
15-25. eQEP Index Position Latch (QPOSILAT) Register (offset = 10h) .................................................. 456
15-26. eQEP Strobe Position Latch (QPOSSLAT) Register (offset = 14h) ................................................ 456
15-27. eQEP Position Counter Latch (QPOSLAT) Register (offset = 18h) ................................................ 456
15-28. eQEP Unit Timer (QUTMR) Register (offset = 1Ch) ................................................................. 457
SPNU517C – March 2018
Submit Documentation Feedback

List of Figures
Copyright © 2018, Texas Instruments Incorporated

27

www.ti.com

15-29. eQEP Register Unit Period (QUPRD) Register (offset = 20h) ...................................................... 457
15-30. eQEP Watchdog Timer (QWDTMR) Register (offset = 26h) ........................................................ 457
15-31. eQEP Watchdog Period (QWDPRD) Register (offset = 24h) ....................................................... 458
15-32. eQEP Decoder Control (QDECCTL) Register (offset = 2Ah) ....................................................... 459
15-33. eQEP Control (QEPCTL) Register (offset = 28h) .................................................................... 460
15-34. eQEP Capture Control (QCAPCTL) Register (offset = 2Eh) ........................................................ 462
15-35. eQEP Position-compare Control (QPOSCTL) Register (offset = 2Ch) ............................................ 463
15-36. eQEP Interrupt Enable (QEINT) Register (offset = 32h) ............................................................ 464
15-37. eQEP Interrupt Flag (QFLG) Register (offset = 30h) ................................................................ 465
15-38. eQEP Interrupt Clear (QCLR) Register (offset = 36h) ............................................................... 466
15-39. eQEP Interrupt Force (QFRC) Register (offset = 34h)............................................................... 467
15-40. eQEP Status (QEPSTS) Register (offset = 3Ah) ..................................................................... 468
15-41. eQEP Capture Timer (QCTMR) Register (offset = 38h) ............................................................. 469
15-42. eQEP Capture Period (QCPRD) Register (offset = 3Eh) ............................................................ 469
15-43. eQEP Capture Timer Latch (QCTMRLAT) Register (offset = 3Ch) ................................................ 470
15-44. eQEP Capture Period Latch (QCPRDLAT) Register (offset = 42h) ................................................ 470
16-1.

ADC Block Diagram ...................................................................................................... 473

16-2.

FIFO Implementation ..................................................................................................... 477

16-3.

Format of Conversion Result Read from FIFO, 12-bit ADC......................................................... 478

16-4.

Format of Conversion Result Read from FIFO, 10-bit ADC......................................................... 478

16-5.

ADC Memory-Mapping ................................................................................................... 479

16-6.

Format of Conversion Result Directly Read from ADC RAM, 12-bit ADC ........................................ 479

16-7.

Format of Conversion Result Directly Read from ADC RAM, 10-bit ADC ........................................ 479

16-8.

Conversion Results Storage............................................................................................. 480

16-9.

ADC Groups’ Operating Mode Control and Status Registers ....................................................... 482

16-10. Example Look-Up Table Entry .......................................................................................... 484
16-11. Self-Test and Calibration Logic ......................................................................................... 490
16-12. Mid-point Value Calculation ............................................................................................. 493
16-13. Self-Test and Calibration Logic ......................................................................................... 494
16-14. Timing for Self-Test Mode ............................................................................................... 495
16-15. Timing for Sample Capacitor Discharge Mode ....................................................................... 496
16-16. ADC Memory Map in Parity Test Mode ................................................................................ 498
16-17. GPIO Functionality of ADEVT ........................................................................................... 498
16-18. ADC Reset Control Register (ADRSTCR) [offset = 00h] ............................................................ 502
16-19. ADC Operating Mode Control Register (ADOPMODECR) [offset = 04h] ......................................... 503
16-20. ADC Clock Control Register (ADCLOCKCR) [offset = 08h]......................................................... 504
16-21. ADC Calibration Mode Control Register (ADCALCR) [offset = 0Ch] .............................................. 505
16-22. 12-bit ADC Event Group Operating Mode Control Register (ADEVMODECR) [offset = 10h] .................. 507
16-23. 10-bit ADC Event Group Operating Mode Control Register (ADEVMODECR) [offset = 10h] .................. 507
16-24. 12-bit ADC Group1 Operating Mode Control Register (ADG1MODECR) [offset = 14h] ........................ 510
16-25. 10-bit ADC Group1 Operating Mode Control Register (ADG1MODECR) [offset = 14h] ........................ 510
16-26. 12-bit ADC Group2 Operating Mode Control Register (ADG2MODECR) [offset = 18h] ........................ 513
16-27. 10-bit ADC Group2 Operating Mode Control Register (ADG2MODECR) [offset = 18h] ........................ 513
16-28. ADC Event Group Trigger Source Select Register (ADEVSRC) [offset = 1Ch] .................................. 516
16-29. ADC Group1 Trigger Source Select Register (ADG1SRC) [offset = 20h] ......................................... 517
16-30. ADC Group2 Trigger Source Select Register (ADG2SRC) [offset = 24h] ......................................... 518
16-31. ADC Event Group Interrupt Enable Control Register (ADEVINTENA) [offset = 28h] ............................ 519
16-32. ADC Group1 Interrupt Enable Control Register (ADG1INTENA) [offset = 2Ch] ................................. 520
16-33. ADC Group2 Interrupt Enable Control Register (ADG2INTENA) [offset = 30h] .................................. 521
28

List of Figures

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

16-34. ADC Event Group Interrupt Flag Register (ADEVINTFLG) [offset = 34h] ......................................... 522
16-35. ADC Group1 Interrupt Flag Register (ADG1INTFLG) [offset = 38h] ............................................... 523
16-36. ADC Group2 Interrupt Flag Register (ADG2INTFLG) [offset = 3Ch] .............................................. 524
16-37. ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) [offset = 40h] .................... 525
16-38. ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR) [offset = 44h] .......................... 525
16-39. ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) [offset = 48h] .......................... 526
16-40. ADC Results Memory Configuration Register (ADBNDCR) [offset = 58h] ........................................ 527
16-41. ADC Results Memory Size Configuration Register (ADBNDEND) [offset = 5Ch] ................................ 528
16-42. ADC Event Group Sampling Time Configuration Register (ADEVSAMP) [offset = 60h] ........................ 529
16-43. ADC Group1 Sampling Time Configuration Register (ADG1SAMP) [offset = 64h] .............................. 529
16-44. ADC Group2 Sampling Time Configuration Register (ADG2SAMP) [offset = 68h] .............................. 530
16-45. ADC Event Group Status Register (ADEVSR) [offset = 6Ch] ...................................................... 531
16-46. ADC Group1 Status Register (ADG1SR) [offset = 70h] ............................................................. 532
16-47. ADC Group2 Status Register (ADG2SR) [offset = 74h] ............................................................. 533
16-48. ADC Event Group Channel Select Register (ADEVSEL) [offset = 78h] ........................................... 534
16-49. ADC Group1 Channel Select Register (ADG1SEL) [offset = 7Ch] ................................................. 535
16-50. ADC Group2 Channel Select Register (ADG2SEL) [offset = 80h] ................................................. 536
16-51. 12-bit ADC Calibration and Error Offset Correction Register (ADCALR) [offset = 84h] ......................... 537
16-52. 10-bit ADC Calibration and Error Offset Correction Register (ADCALR) [offset = 84h] ......................... 537
16-53. ADC State Machine Status Register (ADSMSTATE) [offset = 88h] ............................................... 537
16-54. ADC Channel Last Conversion Value Register (ADLASTCONV) [offset = 8Ch] ................................. 538
16-55. 12-bit ADC Event Group Results' FIFO Register (ADEVBUFFER) [offset = 90h-AFh] .......................... 539
16-56. 10-bit ADC Event Group Results' FIFO Register (ADEVBUFFER) [offset = 90h-AFh] .......................... 539
16-57. 12-bit ADC Group1 Results FIFO Register (ADG1BUFFER) [offset = B0h-CFh] ................................ 540
16-58. 10-bit ADC Group1 Results' FIFO Register (ADG1BUFFER) [offset = B0h-CFh] ............................... 540
16-59. 12-bit ADC Group2 Results FIFO Register (ADG2BUFFER) [offset = D0h-EFh] ................................ 541
16-60. 10-bit ADC Group2 Results' FIFO Register (ADG2BUFFER) [offset = D0h-EFh] ............................... 541
16-61. 12-bit ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER) [offset = F0h] ............. 542
16-62. 10-bit ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER) [offset = F0h] ............. 542
16-63. 12-bit ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) [offset = F4h] ................... 543
16-64. 10-bit ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) [offset = F4h] ................... 543
16-65. 12-bit ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) [offset = F8h] ................... 544
16-66. 10-bit ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) [offset = F8h] ................... 544
16-67. ADC ADEVT Pin Direction Control Register (ADEVTDIR) [offset = FCh] ......................................... 545
16-68. ADC ADEVT Pin Output Value Control Register (ADEVTOUT) [offset = 100h] .................................. 546
16-69. ADC ADEVT Pin Input Value Register (ADEVTIN) [offset = 104h] ................................................ 546
16-70. ADC ADEVT Pin Set Register (ADEVTSET) [offset = 108h] ....................................................... 547
16-71. ADC ADEVT Pin Clear Register (ADEVTCLR) [offset = 10Ch] .................................................... 547
16-72. ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) [offset = 110h] .................................... 548
16-73. ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) [offset = 114h]................................... 548
16-74. ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) [offset = 118h] ................................... 549
16-75. ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN) [offset = 11Ch] ........... 549
16-76. ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) [offset = 120h] .................. 550
16-77. ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) [offset = 124h] .................. 551
16-78. 12-bit ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR) [offset = 128h-138h] ...... 552
16-79. 10-bit ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR) [offset = 128h-138h] ...... 552
16-80. 12-bit ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK) [offset = 12Ch-13Ch] ......... 554
16-81. 10-bit ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK) [offset = 12Ch-13Ch] ......... 554
16-82. ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) [offset = 158h] .............. 555
SPNU517C – March 2018
Submit Documentation Feedback

List of Figures
Copyright © 2018, Texas Instruments Incorporated

29

www.ti.com

16-83. ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR) [offset = 15Ch] ........... 555
16-84. ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG) [offset = 160h] ........................... 556
16-85. ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF) [offset = 164h] ......................... 556
16-86. ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR) [offset = 168h] ...................... 557
16-87. ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) [offset = 16Ch] ............................ 557
16-88. ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) [offset = 170h]............................. 558
16-89. ADC Event Group RAM Write Address Register (ADEVRAMWRADDR) [offset = 174h] ....................... 558
16-90. ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) [offset = 178h] ............................. 559
16-91. ADC Group2 RAM Write Address Register (ADG2RAMWRADDR) [offset = 17Ch] ............................. 559
16-92. ADC Parity Control Register (ADPARCR) [offset = 180h] ........................................................... 560
16-93. ADC Parity Error Address Register (ADPARADDR) [offset = 184h] ............................................... 560
16-94. ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL) [offset = 188h] ................................. 561
16-95. ADC Event Group Channel Selection Mode Control Register (ADEVCHNSELMODECTRL) [offset = 190h] 561
16-96. ADC Group1 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL) [offset = 194h] ...... 562
16-97. ADC Group2 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL) [offset = 198h] ...... 562
16-98. ADC Event Group Current Count Register (ADEVCURRCOUNT) [offset = 19Ch] .............................. 563
16-99. ADC Event Group Maximum Count Register (ADEVMAXCOUNT) [offset = 1A0h] ............................. 563
16-100. ADC Group1 Current Count Register (ADG1CURRCOUNT) [offset = 1A4h] ................................... 564
16-101. ADC Group1 Maximum Count Register (ADG1MAXCOUNT) [offset = 1A8h] .................................. 564
16-102. ADC Group2 Current Count Register (ADG2CURRCOUNT) [offset = 1ACh]................................... 565
16-103. ADC Group2 Maximum Count Register (ADG2MAXCOUNT) [offset = 1B0h] .................................. 565
17-1.

N2HET Block Diagram ................................................................................................... 571

17-2.

Specialized Timer Micromachine ....................................................................................... 572

17-3.

Program Flow Timings ................................................................................................... 573

17-4.

Use of the Overflow Interrupt Flag (HETEXC2) ...................................................................... 574

17-5.

Multi-Resolution Operation Flow Example ............................................................................ 575

17-6.

Debug Control Configuration ............................................................................................ 576

17-7.

Prescaler Configuration .................................................................................................. 580

17-8.

I/O Control ................................................................................................................. 583

17-9.

N2HET Loop Resolution Structure for Each Bit ...................................................................... 584

17-10. Loop Resolution Instruction Execution Example ..................................................................... 585
17-11. HR I/O Architecture ....................................................................................................... 586
17-12. Example of HR Structure Sharing for N2HET Pins 0/1 .............................................................. 586
17-13. XOR-shared HR I/O ...................................................................................................... 587
17-14. Symmetrical PWM with XOR-sharing Output ......................................................................... 588
17-15. AND-shared HR I/O ...................................................................................................... 588
17-16. HR0 to HR1 Digital Loopback Logic: LBTYPE[0] = 0 ................................................................ 589
17-17. HR0 to HR1 Analog Loop Back Logic: LBTYPE[0] = 1 .............................................................. 590
17-18. N2HET Input Edge Detection ........................................................................................... 591
17-19. ECMP Execution Timings................................................................................................ 592
17-20. High/Low Resolution Modes for ECMP and PWCNT ................................................................ 593
17-21. PCNT Instruction Timing (With Capture Edge After HR Counter Overflow) ...................................... 594
17-22. PCNT Instruction Timing (With Capture Edge Before HR Counter Overflow) .................................... 594
17-23. WCAP Instruction Timing ................................................................................................ 595
17-24. I/O Block Diagram Including Pull Control Logic....................................................................... 596
17-25. N2HET Pin Disable Feature Diagram .................................................................................. 597
17-26. Suppression Filter Counter Operation ................................................................................. 598
17-27. Interrupt Functionality on Instruction Level ............................................................................ 599
17-28. Interrupt Flag/Priority Level Architecture............................................................................... 600
30

List of Figures

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

17-29. Request Line Assignment Example .................................................................................... 601
17-30. Operation of N2HET Count Instructions ............................................................................... 602
17-31. SCNT Count Operation .................................................................................................. 602
17-32. ACNT Period Variation Compensations ............................................................................... 603
17-33. N2HET Timings Associated with the Gap Flag (ACNT Deceleration) ............................................. 604
17-34. N2HET Timings Associated with the Gap Flag (ACNT Acceleration) ............................................. 604
17-35. Global Configuration Register (HETGCR) [offset = 00h] ............................................................ 606
17-36. Prescale Factor Register (HETPFR) [offset = 04h] .................................................................. 608
17-37. N2HET Current Address (HETADDR) [offset = 08h] ................................................................. 609
17-38. Offset Index Priority Level 1 Register (HETOFF1) [offset = 0Ch] .................................................. 610
17-39. Offset Index Priority Level 2 Register (HETOFF2) [offset = 10h]................................................... 611
17-40. Interrupt Enable Set Register (HETINTENAS) [offset = 14h] ....................................................... 612
17-41. Interrupt Enable Clear (HETINTENAC) [offset = 18h] ............................................................... 612
17-42. Exception Control Register (HETEXC1) ............................................................................... 613
17-43. Exception Control Register 2 (HETEXC2) ............................................................................. 614
17-44. Interrupt Priority Register (HETPRY) [offset = 24h] .................................................................. 615
17-45. Interrupt Flag Register (HETFLG) [offset = 28h] ..................................................................... 615
17-46. AND Share Control Register (HETAND) [offset = 2Ch] ............................................................. 616
17-47. HR Share Control Register (HETHRSH) [offset = 34h] .............................................................. 617
17-48. XOR Share Control Register (HETXOR) [offset = 38h] .............................................................. 618
17-49. Request Enable Set Register (HETREQENS) [offset = 3Ch] ....................................................... 619
17-50. Request Enable Clear Register (HETREQENC) [offset = 40h] ..................................................... 619
17-51. N2HET Direction Register (HETDIR) [offset = 4Ch] ................................................................. 620
17-52. N2HET Data Input Register (HETDIN) [offset = 50h] ................................................................ 621
17-53. N2HET Data Output Register (HETDOUT) [offset = 54h] ........................................................... 621
17-54. N2HET Data Set Register (HETDSET) [offset = 58h] ............................................................... 622
17-55. N2HET Data Clear Register (HETDCLR) [offset = 5Ch] ............................................................ 622
17-56. N2HET Open Drain Register (HETPDR) [offset = 60h] .............................................................. 623
17-57. N2HET Pull Disable Register (HETPULDIS) [offset = 64h] ......................................................... 623
17-58. N2HET Pull Select Register (HETPSL) [offset = 68h] ............................................................... 624
17-59. Parity Control Register (HETPCR) [offset = 74h] ..................................................................... 625
17-60. Parity Address Register (HETPAR) [offset = 78h] .................................................................... 626
17-61. Parity Pin Register (HETPPR) [offset = 7Ch] ......................................................................... 627
17-62. Suppression Filter Preload Register (HETSFPRLD) [offset = 80h] ................................................ 628
17-63. Suppression Filter Enable Register (HETSFENA) [offset = 84h] ................................................... 628
17-64. Loop Back Pair Select Register (HETLBPSEL) [offset = 8Ch] ..................................................... 629
17-65. Loop Back Pair Direction Register (HETLBPDIR) [offset = 90h] ................................................... 630
17-66. N2HET Pin Disable Register (HETPINDIS) [offset = 94h] .......................................................... 631
17-67. ACMP Program Field (P31:P0) ......................................................................................... 637
17-68. ACMP Control Field (C31:C0)........................................................................................... 637
17-69. ACMP Data Field (D31:D0).............................................................................................. 637
17-70. ACNT Program Field (P31:P0) .......................................................................................... 639
17-71. ACNT Control Field (C31:C0) ........................................................................................... 639
17-72. ACNT Data Field (D31:D0) .............................................................................................. 639
17-73. ADCNST Program Field (P31:P0) ...................................................................................... 642
17-74. ADCNST Control Field (C31:C0) ....................................................................................... 642
17-75. ADCNST Data Field (D31:D0) .......................................................................................... 642
17-76. ADCNST Operation If Remote Data Field[31:7] Is Not Zero ........................................................ 643
17-77. ADCNST Operation if Remote Data Field [31:7] Is Zero ............................................................ 643
SPNU517C – March 2018
Submit Documentation Feedback

List of Figures
Copyright © 2018, Texas Instruments Incorporated31

www.ti.com

17-78. ADC, ADD, AND, OR, SBB, SUB, XOR Program Field (P31:P0) .................................................. 644
17-79. ADC, ADD, AND, OR, SBB, SUB, XOR Control Field (C31:C0) ................................................... 644
17-80. ADC, ADD, AND, OR, SBB, SUB, XOR Data Field (D31:D0) ...................................................... 644
17-81. ADM32 Program Field (P31:P0) ........................................................................................ 650
17-82. ADM32 Control Field (C31:C0) ......................................................................................... 650
17-83. ADM32 Data Field (D31:D0) ............................................................................................ 650
17-84. ADM32 Add and Move Operation for IM&REGTOREG (Case 00)................................................. 652
17-85. ADM32 Add and Move Operation for REM&REGTOREG (Case 01).............................................. 652
17-86. APCNT Program Field (P31:P0) ........................................................................................ 653
17-87. APCNT Control Field (C31:C0) ......................................................................................... 653
17-88. APCNT Data Field (D31:D0) ............................................................................................ 653
17-89. BR Program Field (P31:P0) ............................................................................................. 656
17-90. BR Control Field (C31:C0) ............................................................................................... 656
17-91. BR Data Field (D31:D0) .................................................................................................. 656
17-92. CNT Program Field (P31:P0) ........................................................................................... 658
17-93. CNT Control Field (C31:C0) ............................................................................................. 658
17-94. CNT Data Field (D31:D0) ................................................................................................ 658
17-95. DADM64 Program Field (P31:P0) ...................................................................................... 662
17-96. DADM64 Control Field (C31:C0) ....................................................................................... 662
17-97. DADM64 Data Field (D31:D0) .......................................................................................... 662
17-98. DADM64 Add and Move Operation .................................................................................... 662
17-99. DJZ Program Field (P31:P0) ............................................................................................ 664
17-100. DJZ Control Field (C31:C0) ............................................................................................ 664
17-101. DJZ Data Field (D31:D0) ............................................................................................... 664
17-102. ECMP Program Field (P31:P0) ........................................................................................ 666
17-103. ECMP Control Field (C31:C0) ......................................................................................... 666
17-104. ECMP Data Field (D31:D0) ............................................................................................ 666
17-105. ECNT Program Field (P31:P0) ........................................................................................ 669
17-106. ECNT Control Field (C31:C0) .......................................................................................... 669
17-107. ECNT Data Field (D31:D0) ............................................................................................. 669
17-108. MCMP Program Field (P31:P0) ....................................................................................... 671
17-109. MCMP Control Field (C31:C0) ......................................................................................... 671
17-110. MCMP Data Field (D31:D0) ............................................................................................ 671
17-111. MOV32 Program Field (P31:P0) ...................................................................................... 674
17-112. MOV32 Control Field (C31:C0) ........................................................................................ 674
17-113. MOV32 Data Field (D31:D0) ........................................................................................... 674
17-114. MOV32 Move Operation for IMTOREG (Case 00) .................................................................. 675
17-115. MOV32 Move Operation for IMTOREG&REM (Case 01) .......................................................... 676
17-116. MOV32 Move Operation for REGTOREM (Case 10) ............................................................... 676
17-117. MOV32 Move Operation for REMTOREG (Case 11) ............................................................... 676
17-118. MOV64 Program Field (P31:P0) ...................................................................................... 679
17-119. MOV64 Control Field (C31:C0) ........................................................................................ 679
17-120. MOV64 Data Field (D31:D0) ........................................................................................... 679
17-121. MOV64 Move Operation ................................................................................................ 679
17-122. PCNT Program Field (P31:P0) ........................................................................................ 681
17-123. PCNT Control Field (C31:C0) .......................................................................................... 681
17-124. PCNT Data Field (D31:D0) ............................................................................................. 681
17-125. PWCNT Program Field (P31:P0) ...................................................................................... 684
17-126. PWCNT Control Field (C31:C0) ....................................................................................... 684
32

List of Figures

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

17-127. PWCNT Data Field (D31:D0) .......................................................................................... 684
17-128. RADM64 Program Field (P31:P0) ..................................................................................... 688
17-129. RADM64 Control Field (C31:C0) ...................................................................................... 688
17-130. RADM64 Data Field (D31:D0) ......................................................................................... 688
17-131. RADM64 Add and Move Operation ................................................................................... 688
17-132. RCNT Program Field (P31:P0) ........................................................................................ 690
17-133. RCNT Control Field (C31:C0) ......................................................................................... 690
17-134. RCNT Data Field (D31:D0) ............................................................................................ 690
17-135. SCMP Program Field (P31:P0) ........................................................................................ 692
17-136. SCMP Control Field (C31:C0) ......................................................................................... 692
17-137. SCMP Data Field (D31:D0) ............................................................................................ 692
17-138. SCNT Program Field (P31:P0) ........................................................................................ 694
17-139. SCNT Control Field (C31:C0) .......................................................................................... 694
17-140. SCNT Data Field (D31:D0) ............................................................................................. 694
17-141. SHFT Program Field (P31:P0)......................................................................................... 696
17-142. SHFT Control Field (C31:C0) .......................................................................................... 696
17-143. SHFT Data Field (D31:D0) ............................................................................................. 696
17-144. WCAP Program Field (P31:P0)........................................................................................ 699
17-145. WCAP Control Field (C31:C0) ......................................................................................... 699
17-146. WCAP Data Field (D31:D0) ............................................................................................ 699
17-147. WCAPE Program Field (P31:P0) ...................................................................................... 701
17-148. WCAPE Control Field (C31:C0) ....................................................................................... 701
17-149. WCAPE Data Field (D31:D0) .......................................................................................... 701
18-1.

System Block Diagram ................................................................................................... 705

18-2.

HTU Block Diagram ...................................................................................................... 705

18-3.

Example of a HTU Transfer ............................................................................................. 706

18-4.

Single Buffer Timing and Memory Representation ................................................................... 707

18-5.

Timing Example for Circular Buffer Mode ............................................................................. 708

18-6.

Dual Buffer Timing ........................................................................................................ 709

18-7.

Timing Example for Auto Switch Buffer Mode ........................................................................ 710

18-8.

Timing for Disabling Control Packets .................................................................................. 711

18-9.

Timing Example Including Lost Requests ............................................................................. 712

18-10. Timing which Generates No Request Lost Error ..................................................................... 713
18-11. Timing which Generates a Request Lost Error ....................................................................... 713
18-12. Timing Example for Two WCAP Instructions ......................................................................... 714
18-13. Timing of the WCAP, ECNT, PCNT Example......................................................................... 717
18-14. Global Control Register (HTU GC) [offset = 00] ...................................................................... 721
18-15. Control Packet Enable Register (HTU CPENA) [offset = 04h] ...................................................... 722
18-16. Control Packet (CP) Busy Register 0 (HTU BUSY0) [offset = 08h] ................................................ 723
18-17. Control Packet (CP) Busy Register 1 (HTU BUSY1) [offset = 0Ch] ............................................... 724
18-18. Control Packet (CP) Busy Register 2 (HTU BUSY2) [offset = 10h] ................................................ 724
18-19. Control Packet (CP) Busy Register 3 (HTU BUSY3) [offset = 14h] ................................................ 725
18-20. Active Control Packet and Error Register (HTU ACPE) [offset = 18h] ............................................ 725
18-21. Request Lost and Bus Error Control Register (HTU RLBECTRL) [offset = 20h] ................................. 727
18-22. Buffer Full Interrupt Enable Set Register (HTU BFINTS) [offset = 24h] ........................................... 728
18-23. Buffer Full Interrupt Enable Clear Register (HTU BFINTC) [offset = 28h] ........................................ 728
18-24. Interrupt Mapping Register (HTU INTMAP) [offset = 2Ch] .......................................................... 729
18-25. Interrupt Offset Register 0 (HTU INTOFF0) [offset = 34h] .......................................................... 730
18-26. Interrupt Offset Register 1 (HTU INTOFF1) [offset = 38h] .......................................................... 731
SPNU517C – March 2018
Submit Documentation Feedback

List of Figures
Copyright © 2018, Texas Instruments Incorporated

33

www.ti.com

18-27. Buffer Initialization Mode Register (HTU BIM) [offset = 3Ch] ....................................................... 732
18-28. Request Lost Flag Register (HTU RLOSTFL) [offset = 40h] ........................................................ 734
18-29. Buffer Full Interrupt Flag Register (HTU BFINTFL) [offset = 44h] .................................................. 734
18-30. BER Interrupt Flag Register (HTU BERINTFL) [offset = 48h] ...................................................... 735
18-31. Memory Protection 1 Start Address Register (HTU MP1S) [offset = 4Ch] ........................................ 736
18-32. Memory Protection 1 End Address Register (HTU MP1E) [offset = 50h] ......................................... 736
18-33. Debug Control Register (HTU DCTRL) [offset = 54h] ............................................................... 737
18-34. Watch Point Register (HTU WPR) [offset = 58h] ..................................................................... 738
18-35. Watch Mask Register (HTU WMR) [offset = 5Ch] .................................................................... 738
18-36. Module Identification Register (HTU ID) [offset = 60h] .............................................................. 739
18-37. Parity Control Register (HTU PCR) [offset = 64h] .................................................................... 740
18-38. Parity Address Register (HTU PAR) [offset = 68h] ................................................................... 741
18-39. Memory Protection Control and Status Register (HTU MPCS) [offset = 70h] .................................... 742
18-40. Memory Protection Start Address Register 0 (HTU MP0S) [offset = 74h] ........................................ 745
18-41. Memory Protection End Address Register (HTU MP0E) [offset = 78h] ........................................... 745
18-42. Initial Full Address A Register (HTU IFADDRA) [offset = 00h] ..................................................... 747
18-43. Initial Full Address B Register (HTU IFADDRB) [offset = 04h] ..................................................... 747
18-44. Initial NHET Address and Control Register (HTU IHADDRCT) [offset = 08h] .................................... 748
18-45. Initial Transfer Count Register (HTU ITCOUNT) [offset = 0Ch] .................................................... 749
18-46. Current Full Address A Register (HTU CFADDRA) [offset = 100h] ................................................ 750
18-47. Current Full Address B Register (HTU CFADDRB) [offset = 104h] ................................................ 751
18-48. Current Frame Count Register (HTU CFCOUNT) [offset = 108h].................................................. 752
19-1.

I/O Function Quick Start Flow Chart ................................................................................... 757

19-2.

Interrupt Generation Function Quick Start Flow Chart ............................................................... 758

19-3.

GIO Module Diagram ..................................................................................................... 759

19-4.

GIO Block Diagram ....................................................................................................... 761

19-5.

GIO Global Control Register (GIOGCR0) [offset = 00h] ............................................................. 764

19-6.

GIO Interrupt Detect Register (GIOINTDET) [offset = 08h] ......................................................... 765

19-7.

GIO Interrupt Polarity Register (GIOPOL) [offset = 0Ch] ............................................................ 766

19-8.

GIO Interrupt Enable Set Register (GIOENASET) [offset = 10h] ................................................... 767

19-9.

GIO Interrupt Enable Clear Register (GIOENACLR) [offset = 14h] ................................................ 768

19-10. GIO Interrupt Priority Register (GIOLVLSET) [offset = 18h] ........................................................ 769
19-11. GIO Interrupt Priority Register (GIOLVLCLR) [offset = 1Ch] ........................................................ 771
19-12. GIO Interrupt Flag Register (GIOFLG) [offset = 20h] ................................................................ 772
19-13. GIO Offset 1 Register (GIOOFF1) [offset = 24h] ..................................................................... 773
19-14. GIO Offset 2 Register (GIOOFF2) [offset = 28h] ..................................................................... 774
19-15. GIO Emulation 1 Register (GIOEMU1) [offset = 2Ch] ............................................................... 775
19-16. GIO Emulation 2 Register (GIOEMU2) [offset = 30h] ................................................................ 776
19-17. GIO Data Direction Registers (GIODIR[A-B]) [offset = 34h, 54h] .................................................. 777
19-18. GIO Data Input Registers (GIODIN[A-B]) [offset = 38h, 58h] ....................................................... 777
19-19. GIO Data Output Registers (GIODOUT[A-B]) [offset = 3Ch, 5Ch] ................................................. 778
19-20. GIO Data Set Registers (GIODSET[A-B]) [offset = 40h, 60h] ...................................................... 778
19-21. GIO Data Clear Registers (GIODCLR[A-B]) [offset = 44h, 64h] .................................................... 779
19-22. GIO Open Drain Registers (GIOPDR[A-B]) [offset = 48h, 68h]..................................................... 779
19-23. GIO Pull Disable Registers (GIOPULDIS[A-B]) [offset = 4Ch, 6Ch] ............................................... 780
19-24. GIO Pull Select Registers (GIOPSL[A-B]) [offset = 50h, 70h] ...................................................... 780

34

20-1.

Block Diagram ............................................................................................................ 784

20-2.

Bit Timing ................................................................................................................. 786

20-3.

CAN Bit-timing Configuration ........................................................................................... 791

List of Figures

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

20-4.

Structure of a Message Object ......................................................................................... 793

20-5.

Message RAM Representation in Debug/Suspend Mode ........................................................... 796

20-6.

Message RAM Representation in RAM Direct Access Mode ...................................................... 796

20-7.

Data Transfer Between IF1 / IF2 Registers and Message RAM ................................................... 798

20-8.

Initialization of a Transmit Object ...................................................................................... 800

20-9.

Initialization of a Single Receive Object for Data Frames .......................................................... 800

20-10. Initialization of a Single Receive Object for Remote Frames ...................................................... 801
20-11. CPU Handling of a FIFO Buffer (Interrupt Driven) ................................................................... 806
20-12. CAN Interrupt Topology 1 ............................................................................................... 809
20-13. CAN Interrupt Topology 2 ............................................................................................... 810
20-14. Local Power-Down Mode Flow Diagram .............................................................................. 812
20-15. CAN Core in Silent Mode ............................................................................................... 813
20-16. CAN Core in Loop Back Mode ......................................................................................... 814
20-17. CAN Core in External Loop Back Mode .............................................................................. 815
20-18. CAN Core in Loop Back Combined with Silent Mode ............................................................... 816
20-19. CAN Control Register (DCAN CTL) [offset = 00] ..................................................................... 820
20-20. Error and Status Register (DCAN ES) [offset = 04h] ................................................................ 822
20-21. Error Counter Register (DCAN ERRC) [offset = 08h] ................................................................ 824
20-22. Bit Timing Register (DCAN BTR) [offset = 0Ch] ...................................................................... 825
20-23. Interrupt Register (DCAN INT) [offset = 10h] ......................................................................... 826
20-24. Test Register (DCAN TEST) [offset = 14h] ............................................................................ 827
20-25. Parity Error Code Register (DCAN PERR) [offset = 1Ch] ........................................................... 828
20-26. Core Release Register (DCAN REL) [offset = 20h] .................................................................. 828
20-27. Auto-Bus-On Time Register (DCAN ABOTR) [offset = 80h] ........................................................ 829
20-28. Transmission Request X Register (DCAN TXRQ X) [offset = 84h] ................................................ 829
20-29. Transmission Request 12 Register [offset = 88h] .................................................................... 830
20-30. Transmission Request 34 Register [offset = 8Ch] .................................................................... 830
20-31. Transmission Request 56 Register [offset = 90h] .................................................................... 830
20-32. Transmission Request 78 Register [offset = 94h] .................................................................... 830
20-33. New Data X Register (DCAN NWDAT X) [offset = 98h] ............................................................. 831
20-34. New Data 12 Register [offset = 9Ch] ................................................................................... 832
20-35. New Data 34 Register [offset = A0h] ................................................................................... 832
20-36. New Data 56 Register [offset = A4h] ................................................................................... 832
20-37. New Data 78 Register [offset = A8h] ................................................................................... 832
20-38. Interrupt Pending X Register (DCAN INTPND X) [offset = ACh] ................................................... 833
20-39. Interrupt Pending 12 Register [offset = B0h] .......................................................................... 834
20-40. Interrupt Pending 34 Register [offset = B4h] .......................................................................... 834
20-41. Interrupt Pending 56 Register [offset = B8h] .......................................................................... 834
20-42. Interrupt Pending 78 Register [offset = BCh] ......................................................................... 834
20-43. Message Valid X Register (DCAN MSGVAL X) [offset = C0h] ..................................................... 835
20-44. Message Valid 12 Register [offset = C4h] ............................................................................. 836
20-45. Message Valid 34 Register [offset = C8h] ............................................................................. 836
20-46. Message Valid 56 Register [offset = CCh] ............................................................................ 836
20-47. Message Valid 78 Register [offset = D0h] ............................................................................. 836
20-48. Interrupt Multiplexer 12 Register [offset = D8h] ....................................................................... 837
20-49. Interrupt Multiplexer 34 Register [offset = DCh] ...................................................................... 837
20-50. Interrupt Multiplexer 56 Register [offset = E0h] ....................................................................... 837
20-51. Interrupt Multiplexer 78 Register [offset = E4h] ....................................................................... 837
20-52. IF1 Command Registers (DCAN IF1CMD) [offset = 100h] .......................................................... 838
SPNU517C – March 2018
Submit Documentation Feedback

List of Figures
Copyright © 2018, Texas Instruments Incorporated

35

www.ti.com

20-53. IF1 Command Registers (CAN IF2CMD) [offset = 120h] ............................................................ 838
20-54. IF1 Mask Register (DCAN IF1MSK) [offset = 104h] ................................................................. 841
20-55. IF2 Mask Register (DCAN IF2MSK) [offset = 124h] ................................................................. 841
20-56. IF1 Arbitration Register (DCAN IF1ARB) [offset = 108h] ............................................................ 842
20-57. IF2 Arbitration Register (DCAN IF2ARB) [offset = 128h] ............................................................ 842
20-58. IF1 Message Control Register (DCAN IF1MCTL) [offset = 10Ch] ................................................. 843
20-59. IF2 Message Control Register (DCAN IF2MCTL) [offset = 12Ch] ................................................. 843
20-60. IF1 Data A Register (DCAN IF1DATA) [offset = 110h] .............................................................. 845
20-61. IF1 Data B Register (DCAN IF1DATB) [offset = 114h] .............................................................. 845
20-62. IF2 Data A Register (DCAN IF2DATA) [offset = 130h] .............................................................. 845
20-63. IF2 Data B Register (DCAN IF2DATB) [offset = 134h] .............................................................. 845
20-64. IF3 Observation Register (DCAN IF3OBS) [offset = 140h] ......................................................... 846
20-65. IF3 Mask Register (DCAN IF3MSK) [offset = 144h] ................................................................. 848
20-66. IF3 Arbitration Register (DCAN IF3ARB) [offset = 148h] ............................................................ 849
20-67. IF3 Message Control Register (DCAN IF3MCTL) [offset = 14Ch] ................................................. 850
20-68. IF3 Data A Register (DCAN IF3DATA) [offset = 150h] .............................................................. 851
20-69. IF3 Data B Register (DCAN IF3DATB) [offset = 154h] .............................................................. 851
20-70. IF3 Update Enable 12 Register [offset = 160h] ....................................................................... 852
20-71. IF3 Update Enable 34 Register [offset = 164h] ....................................................................... 852
20-72. IF3 Update Enable 56 Register [offset = 168h] ....................................................................... 852
20-73. IF3 Update Enable 78 Register [offset = 16Ch] ...................................................................... 852
20-74. CAN TX IO Control Register (DCAN TIOC) [offset = 1E0h] ........................................................ 853
20-75. CAN RX IO Control Register (DCAN RIOC) [offset = 1E4h] ........................................................ 854
21-1.

SPI Functional Logic Diagram .......................................................................................... 859

21-2.

SPI Three-Pin Operation ................................................................................................. 861

21-3.

Operation with SPICS .................................................................................................... 862

21-4.

Operation with SPIENA .................................................................................................. 863

21-5.

SPI Five-Pin Option with SPIENA and SPICS ........................................................................ 864

21-6.

Format for Transmitting an 12-Bit Word ............................................................................... 865

21-7.

Format for Receiving an 10-Bit Word .................................................................................. 865

21-8.

Clock Mode with Polarity = 0 and Phase = 0 ......................................................................... 866

21-9.

Clock Mode with Polarity = 0 and Phase = 1 ......................................................................... 866

21-10. Clock Mode with Polarity = 1 and Phase = 0 ......................................................................... 867
21-11. Clock Mode with Polarity = 1 and Phase = 1 ......................................................................... 867
21-12. Five Bits per Character (5-Pin Option) ................................................................................. 868
21-13. Typical Diagram when a Buffer in Master is in CSHOLD Mode (SPI-SPI) ........................................ 870
21-14. I/O Paths during I/O Loopback Modes ................................................................................. 873
21-15. TG Interrupt Structure ................................................................................................... 876
21-16. SPIFLG Interrupt Structure .............................................................................................. 876
21-17. SPI Global Control Register 0 (SPIGCR0) [offset = 00] ............................................................. 880
21-18. SPI Global Control Register 1 (SPIGCR1) [offset = 04h] ............................................................ 881
21-19. SPI Interrupt Register (SPIINT0) [offset = 08h] ....................................................................... 882
21-20. SPI Interrupt Level Register (SPILVL) [offset = 0Ch] ................................................................ 884
21-21. SPI Flag Register (SPIFLG) [offset = 10h] ............................................................................ 885
21-22. SPI Pin Control Register 0 (SPIPC0) [offset = 14h] .................................................................. 888
21-23. SPI Pin Control Register 1 (SPIPC1) [offset = 18h] .................................................................. 889
21-24. SPI Pin Control Register 2 (SPIPC2) [offset = 1Ch] ................................................................. 891
21-25. SPI Pin Control Register 3 (SPIPC3) [offset = 20h] .................................................................. 892
21-26. SPI Pin Control Register 4 (SPIPC4) [offset = 24h] .................................................................. 893
36

List of Figures

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

21-27. SPI Pin Control Register 5 (SPIPC5) [offset = 28h] .................................................................. 895
21-28. SPI Pin Control Register 6 (SPIPC6) [offset = 2Ch] ................................................................. 896
21-29. SPI Pin Control Register 7 (SPIPC7) [offset = 30h] .................................................................. 898
21-30. SPI Pin Control Register 8 (SPIPC8) [offset = 34h] .................................................................. 899
21-31. SPI Transmit Data Register 0 (SPIDAT0) [offset = 38h] ............................................................ 900
21-32. SPI Transmit Data Register 1 (SPIDAT1) [offset = 3Ch] ............................................................ 901
21-33. SPI Receive Buffer Register (SPIBUF) [offset = 40h]................................................................ 904
21-34. SPI Emulation Register (SPIEMU) [offset = 44h] ..................................................................... 906
21-35. SPI Delay Register (SPIDELAY) [offset = 48h] ....................................................................... 906
21-36. Example: t C2TDELAY= 8 VCLK Cycles .................................................................................... 908
21-37. Example: t T2CDELAY= 4 VCLK Cycles .................................................................................... 908
21-38. Transmit-Data-Finished-to-ENA-Inactive-Timeout .................................................................... 908
21-39. Chip-Select-Active-to-ENA-Signal-Active-Timeout ................................................................... 908
21-40. SPI Default Chip Select Register (SPIDEF) [offset = 4Ch] .......................................................... 909
21-41. SPI Data Format Registers (SPIFMT[3:0]) [offset = 5Ch-50h] ...................................................... 910
21-42. Interrupt Vector 0 (NTVECT0) [offset = 60h] .......................................................................... 912
21-43. Interrupt Vector 1 (INTVECT1) [offset = 64h] ......................................................................... 913
21-44. SPI Pin Control Register 9 (SPIPC9) [offset = 68h] ................................................................. 915
21-45. Multi-buffer Mode Enable Register (MIBSPIE) [offset = 70h] ....................................................... 916
21-46. TG Interrupt Enable Set Register (TGITENST) [offset = 74h] ...................................................... 917
21-47. TG Interrupt Enable Clear Register (TGITENCR) [offset = 78h] ................................................... 918
21-48. Transfer Group Interrupt Level Set Register (TGITLVST) [offset = 7Ch].......................................... 919
21-49. Transfer Group Interrupt Level Clear Register (TGITLVCR) [offset = 80h] ....................................... 920
21-50. Transfer Group Interrupt Flag Register (TGINTFLAG) [offset = 84h] .............................................. 921
21-51. Tick Counter Operation .................................................................................................. 922
21-52. Tick Count Register (TICKCNT) [offset = 90h]........................................................................ 922
21-53. Last TG End Pointer (LTGPEND) [offset = 94h] ...................................................................... 923
21-54. MibSPI TG Control Registers (TGxCTRL) [offsets = 98h-D4h] ..................................................... 924
21-55. Multi-buffer RAM Uncorrectable Parity Error Control Register (UERRCTRL) [offset = 120h] .................. 927
21-56. Multi-buffer RAM Uncorrectable Parity Error Status Register (UERRSTAT) [offset = 124h] ................... 928
21-57. RXRAM Uncorrectable Parity Error Address Register (UERRADDR1) [offset = 128h] ......................... 929
21-58. TXRAM Uncorrectable Parity Error Address Register (UERRADDR0) [offset = 12Ch] ......................... 930
21-59. RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) [offset = 130h] ............................ 931
21-60. I/O-Loopback Test Control Register (IOLPBKTSTCR) [offset = 134h] ............................................ 932
21-61. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) [offset =138h]........................................................................................................................ 934
21-62. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) [offset =13Ch] ....................................................................................................................... 936
21-63. Multi-Buffer RAM Configuration ......................................................................................... 938
21-64. Multi-buffer RAM Transmit Data Register (TXRAM) [offset = Base + 000h-1FFh] ............................... 940
21-65. Multi-buffer RAM Receive Buffer Register (RXRAM) [offset = RAM Base + 200h-3FFh] ....................... 943
21-66. Memory Map for Parity Locations During Normal and Test Mode ................................................. 946
21-67. Example of Memory-Mapped Parity Locations During Test Mode ................................................. 947
21-68. SPI/MibSPI Pins During Master Mode 3-pin Configuration ......................................................... 948
21-69. SPI/MibSPI Pins During Master Mode 4-pin with SPICS Configuation ............................................ 948
21-70. SPI/MibSPI Pins During Master Mode in 4-pin with SPIENA Configuration ...................................... 949
21-71. SPI/MibSPI Pins During Master/Slave Mode with 5-pin Configuration ............................................ 949
21-72. SPI/MibSPI Pins During Slave Mode 3-pin Configuration ........................................................... 950
21-73. SPI/MibSPI Pins During Slave Mode in 4-pin with SPIENA Configuration ........................................ 950
SPNU517C – March 2018
Submit Documentation Feedback

List of Figures
Copyright © 2018, Texas Instruments Incorporated

37

www.ti.com

21-74. SPI/MibSPI Pins During Slave Mode in 5-pin Configuration - (Single Slave) ..................................... 950
21-75. SPI/MibSPI Pins During Slave Mode in 5-pin Configuration - (Single/Multi Slave) .............................. 950
22-1.

SCI Block Diagram ....................................................................................................... 956

22-2.

SCI/LIN Block Diagram .................................................................................................. 957

22-3.

Typical SCI Data Frame Formats ....................................................................................... 958

22-4.

Asynchronous Communication Bit Timing ............................................................................. 959

22-5.

Superfractional Divider Example ........................................................................................ 961

22-6.

Idle-Line Multiprocessor Communication Format ..................................................................... 963

22-7.

Address-Bit Multiprocessor Communication Format ................................................................. 963

22-8.

Receive Buffers ........................................................................................................... 964

22-9.

Transmit Buffers .......................................................................................................... 965

22-10. General Interrupt Scheme ............................................................................................... 966
22-11. Interrupt Generation for Given Flags ................................................................................... 967
22-12. LIN Protocol Message Frame Format: Master Header and Slave Response .................................... 973
22-13. Header 3 Fields: Synch Break, Synch, and ID........................................................................ 973
22-14. Response Format of LIN Message Frame ............................................................................ 974
22-15. Message Header in Terms of Tbit ....................................................................................... 977
22-16. ID Field ..................................................................................................................... 977
22-17. Measurements for Synchronization .................................................................................... 979
22-18. Synchronization Validation Process and Baud Rate Adjustment ................................................... 980
22-19. Optional Embedded Checksum in Response for Extended Frames ............................................... 981
22-20. Checksum Compare and Send for Extended Frames ............................................................... 982
22-21. TXRX Error Detector ..................................................................................................... 984
22-22. Classic Checksum Generation at Transmitting Node ................................................................ 985
22-23. LIN 2.0-Compliant Checksum Generation at Transmitting Node ................................................... 985
22-24. ID Reception, Filtering and Validation ................................................................................. 987
22-25. LIN Message Frame Showing LIN Interrupt Timing and Sequence................................................ 989
22-26. Wakeup Signal Generation .............................................................................................. 993
22-27. SCI Global Control Register 0 (SCIGCR0) [offset = 00] ............................................................. 996
22-28. SCI Global Control Register 1 (SCIGCR1) [offset = 04h] ........................................................... 997
22-29. SCI Global Control Register 2 (SCIGCR2) [offset = 08h] .......................................................... 1001
22-30. SCI Set Interrupt Register (SCISETINT) [offset = 0Ch] ............................................................ 1002
22-31. SCI Clear Interrupt Register (SCICLEARINT) [offset = 10h] ...................................................... 1005
22-32. SCI Set Interrupt Level Register (SCISETINTLVL) [offset = 14h] ................................................ 1008
22-33. SCI Clear Interrupt Level Register (SCICLEARINTLVL) [offset = 18h] .......................................... 1010
22-34. SCI Flags Register (SCIFLR) [offset = 1Ch] ......................................................................... 1013
22-35. SCI Interrupt Vector Offset 0 (SCIINTVECT0) [offset = 20h] ...................................................... 1020
22-36. SCI Interrupt Vector Offset 1 (SCIINTVECT1) [offset = 24h] ...................................................... 1020
22-37. SCI Format Control Register (SCIFORMAT) [offset = 28h] ....................................................... 1021
22-38. Baud Rate Selection Register (BRS) [offset = 2Ch] ................................................................ 1022
22-39. Receiver Emulation Data Buffer (SCIED) [offset = 30h] ........................................................... 1023
22-40. Receiver Data Buffer (SCIRD) [offset = 34h] ........................................................................ 1024
22-41. Transmit Data Buffer Register (SCITD) [offset = 38h] .............................................................. 1025
22-42. SCI Pin I/O Control Register 0 (SCIPIO0) [offset = 3Ch] .......................................................... 1025
22-43. SCI Pin I/O Control Register 1 (SCIPIO1) [offset = 40h] ........................................................... 1026
22-44. SCI Pin I/O Control Register 2 (SCIPIO2) [offset = 44h] ........................................................... 1027
22-45. SCI Pin I/O Control Register 3 (SCIPIO3) [offset = 48h] ........................................................... 1028
22-46. SCI Pin I/O Control Register 4 (SCIPIO4) [offset = 4Ch] .......................................................... 1029
22-47. SCI Pin I/O Control Register 5 (SCIPIO5) [offset = 50h] ........................................................... 1030
38

List of Figures

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

22-48. SCI Pin I/O Control Register 6 (SCIPIO6) [offset = 54h] ........................................................... 1031
22-49. SCI Pin I/O Control Register 7 (SCIPIO7) [offset = 58h] ........................................................... 1032
22-50. SCI Pin I/O Control Register 8 (SCIPIO8) [offset = 5Ch] .......................................................... 1032
22-51. LIN Compare Register (LINCOMPARE) [offset = 60h] ............................................................. 1033
22-52. LIN Receive Buffer 0 Register (LINRD0) [offset = 64h] ............................................................ 1034
22-53. LIN Receive Buffer 1 Register (RD1) [offset = 68h] ................................................................ 1034
22-54. LIN Mask Register (LINMASK) [offset = 6Ch] ....................................................................... 1035
22-55. LIN Identification Register (LINID) [offset = 70h] .................................................................... 1036
22-56. LIN Transmit Buffer 0 Register (LINTD0) [offset = 74h] ............................................................ 1037
22-57. LIN Transmit Buffer 1 Register (LINTD1) [offset = 78h] ............................................................ 1037
22-58. Maximum Baud Rate Selection Register (MBRS) [offset = 7Ch] ................................................. 1038
22-59. Input/Output Error Enable Register (IODFTCTRL) [offset = 90h] ................................................. 1039
22-60. GPIO Functionality ...................................................................................................... 1041
23-1.

eFuse Self Test Flow Chart ............................................................................................ 1046

23-2.

EFC Boundary Control Register (EFCBOUND) [offset = 1Ch] .................................................... 1047

23-3.

EFC Pins Register (EFCPINS) [offset = 2Ch] ...................................................................... 1049

23-4.

EFC Error Status Register (EFCERRSTAT) [offset = 3Ch] ........................................................ 1050

23-5.

EFC Self Test Cycles Register (EFCSTCY) [offset = 48h] ........................................................ 1050

23-6.

EFC Self Test Cycles Register (EFCSTSIG) [offset = 4Ch] ....................................................... 1051

SPNU517C – March 2018
Submit Documentation Feedback

List of Figures
Copyright © 2018, Texas Instruments Incorporated

39

www.ti.com

List of Tables

40

2-1.

Definition of Terms ........................................................................................................ 64

2-2.

Bus Master / Slave Access Privileges .................................................................................. 65

2-3.

Module Registers / Memories Memory-Map ........................................................................... 67

2-4.

Flash Memory Banks and Sectors ...................................................................................... 70

2-5.

PBIST Memory Grouping ................................................................................................. 72

2-6.

PBIST Algorithm Mapping ................................................................................................ 73

2-7.

Memory Initialization Select Mapping ................................................................................... 75

2-8.

Causes of Resets .......................................................................................................... 76

2-9.

Clock Sources .............................................................................................................. 79

2-10.

Clock Domains.............................................................................................................. 80

2-11.

Typical Low-Power Modes ............................................................................................... 81

2-12.

Clock Test Mode Options ................................................................................................ 83

2-13.

Clock Source Selection for DCC1 Counter0 ........................................................................... 85

2-14.

Clock Source Selection for DCC1 Counter1 ........................................................................... 85

2-15.

Primary System Control Registers ....................................................................................... 86

2-16.

SYS Pin Control Register 1 (SYSPC1) Field Descriptions ........................................................... 87

2-17.

SYS Pin Control Register 2 (SYSPC2) Field Descriptions ........................................................... 88

2-18.

SYS Pin Control Register 3 (SYSPC3) Field Descriptions ........................................................... 88

2-19.

SYS Pin Control Register 4 (SYSPC4) Field Descriptions ........................................................... 89

2-20.

SYS Pin Control Register 5 (SYSPC5) Field Descriptions ........................................................... 89

2-21.

SYS Pin Control Register 6 (SYSPC6) Field Descriptions ........................................................... 90

2-22.

SYS Pin Control Register 7 (SYSPC7) Field Descriptions ........................................................... 90

2-23.

SYS Pin Control Register 8 (SYSPC8) Field Descriptions ........................................................... 91

2-24.

SYS Pin Control Register 9 (SYSPC9) Field Descriptions ........................................................... 91

2-25.

Clock Source Disable Register (CSDIS) Field Descriptions .......................................................... 92

2-26.

Clock Sources Table ....................................................................................................... 92

2-27.

Clock Source Disable Set Register (CSDISSET) Field Descriptions ................................................ 93

2-28.

Clock Source Disable Clear Register (CSDISCLR) Field Descriptions ............................................. 94

2-29.

Clock Domain Disable Register (CDDIS) Field Descriptions ......................................................... 95

2-30.

Clock Domain Disable Set Register (CDDISSET) Field Descriptions ............................................... 97

2-31.

Clock Domain Disable Clear Register (CDDISCLR) Field Descriptions ............................................ 98

2-32.

GCLK, HCLK, VCLK, and VCLK2 Source Register (GHVSRC) Field Descriptions ............................. 100

2-33.

Peripheral Asynchronous Clock Source Register (VCLKASRC) Field Descriptions ............................. 101

2-34.

RTI Clock Source Register (RCLKSRC) Field Descriptions ........................................................ 102

2-35.

Clock Source Valid Register (CSVSTAT) Field Descriptions ....................................................... 103

2-36.

Memory Self-Test Global Control Register (MSTGCR) Field Descriptions ....................................... 104

2-37.

Memory Hardware Initialization Global Control Register (MINITGCR) Field Descriptions ...................... 105

2-38.

PBIST Controller/Memory Initialization Enable Register (MSINENA) Field Descriptions ....................... 106

2-39.

Memory Self-Test Fail Status Register (MSTFAIL) Field Descriptions ............................................ 107

2-40.

MSTC Global Status Register (MSTCGSTAT) Field Descriptions ................................................. 108

2-41.

Memory Hardware Initialization Status Register (MINISTAT) Field Descriptions ................................ 109

2-42.

PLL Control Register 1 (PLLCTL1) Field Descriptions .............................................................. 110

2-43.

PLL Control Register 2 (PLLCTL2) Field Descriptions .............................................................. 112

2-44.

SYS Pin Control Register 10 (SYSPC10) Field Descriptions ....................................................... 113

2-45.

Die Identification Register, Lower Word (DIEIDL) Field Descriptions .............................................. 114

2-46.

Die Identification Register, Upper Word (DIEIDH) Field Descriptions ............................................. 114

2-47.

LPO/Clock Monitor Control Register (LPOMONCTL) Field Descriptions.......................................... 115

List of Tables

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

2-48.

Clock Test Register (CLKTEST) Field Descriptions.................................................................. 118

2-49.

DFT Control Register (DFTCTRLREG) Field Descriptions .......................................................... 120

2-50.

DFT Logic Access Mode ................................................................................................. 120

2-51.

DFT Control Register 2 (DFTCTRLREG2) Field Descriptions ..................................................... 121

2-52.

General Purpose Register (GPREG1) Field Descriptions ........................................................... 122

2-53.

Imprecise Fault Status Register (IMPFASTS) Field Descriptions .................................................. 123

2-54.

Imprecise Fault Write Address Register (IMPFTADD) Field Descriptions ........................................ 124

2-55.

System Software Interrupt Request 1 Register (SSIR1) Field Descriptions ...................................... 125

2-56.

System Software Interrupt Request 2 Register (SSIR2) Field Descriptions ...................................... 125

2-57.

System Software Interrupt Request 3 Register (SSIR3) Field Descriptions ...................................... 126

2-58.

System Software Interrupt Request 4 Register (SSIR4) Field Descriptions ...................................... 126

2-59.

RAM Control Register (RAMGCR) Field Descriptions ............................................................... 127

2-60.

Bus Matrix Module Control Register 1 (BMMCR) Field Descriptions .............................................. 128

2-61.

CPU Reset Control Register (CPURSTGCR) Field Descriptions .................................................. 129

2-62.

Clock Control Register (CLKCNTRL) Field Descriptions ............................................................ 130

2-63.

ECP Control Register (ECPCNTL) Field Descriptions ............................................................... 131

2-64.

DEV Parity Control Register 1 (DEVCR1) Field Descriptions ...................................................... 132

2-65.

System Exception Control Register (SYSECR) Field Descriptions ................................................ 132

2-66.

System Exception Status Register (SYSESR) Field Descriptions ................................................. 133

2-67.

System Test Abort Status Register (SYSTASR) Field Descriptions .............................................. 134

2-68.

Global Status Register (GLBSTAT) Field Descriptions .............................................................. 135

2-69.

Device Identification Register (DEVID) Field Descriptions .......................................................... 136

2-70.

Software Interrupt Vector Register (SSIVEC) Field Descriptions .................................................. 137

2-71.

System Software Interrupt Flag Register (SSIF) Field Descriptions ............................................... 138

2-72.

Secondary System Control Registers .................................................................................. 139

2-73.

CPU Logic BIST Clock Prescaler (STCLKDIV) Field Descriptions ................................................. 139

2-74.

Clock Slip Register (CLKSLIP) Field Descriptions ................................................................... 140

2-75.

EFUSE Controller Control Register (EFC_CTLREG) Field Descriptions .......................................... 141

2-76.

Die Identification Register, Lower Word (DIEIDL_REG0) Field Descriptions ..................................... 141

2-77.

Die Identification Register, Upper Word (DIEIDH_REG1) Field Descriptions .................................... 142

2-78.

Die Identification Register, Lower Word (DIEIDL_REG2) Field Descriptions ..................................... 142

2-79.

Die Identification Register, Upper Word (DIEIDH_REG3) Field Descriptions .................................... 143

2-80.

Peripheral Central Resource Control Registers ...................................................................... 144

2-81.

Peripheral Memory Protection Set Register 0 (PMPROTSET0) Field Descriptions ............................. 145

2-82.

Peripheral Memory Protection Set Register 1 (PMPROTSET1) Field Descriptions ............................. 145

2-83.

Peripheral Memory Protection Clear Register 0 (PMPROTCLR0) Field Descriptions ........................... 146

2-84.

Peripheral Memory Protection Clear Register 1 (PMPROTCLR1) Field Descriptions ........................... 146

2-85.

Peripheral Protection Set Register 0 (PPROTSET0) Field Descriptions .......................................... 147

2-86.

Peripheral Protection Set Register 1 (PPROTSET1) Field Descriptions .......................................... 148

2-87.

Peripheral Protection Set Register 2 (PPROTSET2) Field Descriptions .......................................... 148

2-88.

Peripheral Protection Set Register 3 (PPROTSET3) Field Descriptions .......................................... 149

2-89.

Peripheral Protection Clear Register 0 (PPROTCLR0) Field Descriptions ....................................... 149

2-90.

Peripheral Protection Clear Register 1 (PPROTCLR1) Field Descriptions ....................................... 150

2-91.

Peripheral Protection Clear Register 2 (PPROTCLR2) Field Descriptions ....................................... 150

2-92.

Peripheral Protection Clear Register 3 (PPROTCLR3) Field Descriptions ....................................... 151

2-93.

Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0) Field Descriptions ................... 152

2-94.

Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1) Field Descriptions ................... 152

2-95.

Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0) Field Descriptions ................. 153

2-96.

Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNCLR1) Field Descriptions ................... 153

SPNU517C – March 2018
Submit Documentation Feedback

List of Tables
Copyright © 2018, Texas Instruments Incorporated

41

www.ti.com

2-97.

Peripheral Power-Down Set Register 0 (PSPWRDWNSET0) Field Descriptions ................................ 154

2-98.

Peripheral Power-Down Set Register 1 (PSPWRDWNSET1) Field Descriptions ................................ 155

2-99.

Peripheral Power-Down Set Register 2 (PSPWRDWNSET2) Field Descriptions ................................ 155

2-100. Peripheral Power-Down Set Register 3 (PSPWRDWNSET3) Field Descriptions ................................ 156
2-101. Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0) Field Descriptions ............................. 156
2-102. Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1) Field Descriptions ............................. 157
2-103. Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2) Field Descriptions ............................. 157
2-104. Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR3) Field Descriptions ............................. 158

42

3-1.

IOMM Register Summary ................................................................................................ 164

3-2.

Revision Register Field Descriptions ................................................................................... 164

3-3.

Boot Mode Register Field Descriptions ................................................................................ 165

3-4.

Kicker Register 0 Field Descriptions ................................................................................... 165

3-5.

Kicker Register 1 Field Descriptions ................................................................................... 165

3-6.

Error Raw Status / Set Register Field Descriptions .................................................................. 166

3-7.

Error Signaling Enabled Status / Clear Register Field Descriptions ............................................... 167

3-8.

Error Enable Register Field Descriptions .............................................................................. 168

3-9.

Interrupt Enable Clear Register Field Descriptions ................................................................... 169

3-10.

Fault Address Register Field Descriptions ............................................................................ 169

3-11.

Fault Status Register Field Descriptions ............................................................................... 170

3-12.

FAULT_CLEAR_REG: Fault Clear Register Field Descriptions .................................................... 171

3-13.

Pin Multiplexing Control Registers Field Descriptions ............................................................... 172

3-14.

Multiplexing and Control ................................................................................................. 172

4-1.

ECC Encoding for BE32 Devices ....................................................................................... 177

4-2.

Syndrome Table, Decode to Bit in Error ............................................................................... 178

4-3.

Alternate Syndrome Table ............................................................................................... 179

4-4.

TI OTP Bank 0 Sector Information Field Descriptions ............................................................... 181

4-5.

TI OTP Sector Information Address .................................................................................... 181

4-6.

TI OTP Bank 0 Package and Memory Size Information Field Descriptions ...................................... 182

4-7.

TI OTP Bank 0 LPO Trim and Max HCLK Information Field Descriptions ........................................ 182

4-8.

DIAG_MODE Encoding .................................................................................................. 184

4-9.

Bus1 Diagnostic Mode Summary ....................................................................................... 187

4-10.

Bus 2 and ECC Diagnostic Mode Summary .......................................................................... 188

4-11.

Port Signals Diagnostic Mode Summary .............................................................................. 189

4-12.

Flash Control Registers .................................................................................................. 190

4-13.

Flash Option Control Register (FRDCNTL) Field Descriptions ..................................................... 191

4-14.

Flash Error Detection and Correction Control Register 1 (FEDACCTRL1) Field Descriptions ................. 192

4-15.

Flash Error Correction Control and Correction Register 2 (FEDACCTRL2) Field Descriptions ................ 194

4-16.

Flash Correctable Error Count Register (FCOR_ERR_CNT) Field Descriptions ................................ 194

4-17.

Flash Correctable Error Address Register (FCOR_ERR_ADD) Field Descriptions .............................. 195

4-18.

Flash Correctable Error Position Register (FCOR_ERR_POS) Field Descriptions .............................. 196

4-19.

Flash Error Detection and Correction Status Register (FEDACSTATUS) Field Descriptions .................. 197

4-20.

Flash Uncorrectable Error Address Register (FUNC_ERR_ADD) Field Descriptions ........................... 200

4-21.

Flash Error Detection and Correction Sector Disable Register (FEDACSDIS) Field Descriptions ............ 201

4-22.

Primary Address Tag Register (FPRIM_ADD)_TAG Field Descriptions .......................................... 203

4-23.

Duplicate Address Tag Register (FDUP_ADD)_TAG Field Descriptions.......................................... 203

4-24.

Flash Bank Protection Register (FBPROT) Field Descriptions ..................................................... 204

4-25.

Flash Bank Sector Enable Register (FBSE) Field Descriptions .................................................... 204

4-26.

Flash Bank Busy Register (FBBUSY) Field Descriptions ........................................................... 205

4-27.

Flash Bank Access Control Register (FBAC) Field Descriptions ................................................... 206

List of Tables

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

4-28.

Flash Bank Fallback Power Register (FBFALLBACK) Field Descriptions ........................................ 207

4-29.

Flash Pump Access Control Register 1 (FPAC1) Field Descriptions .............................................. 208

4-30.

Flash Pump Access Control Register 1 (FPAC1) Field Descriptions .............................................. 209

4-31.

Flash Pump Access Control Register 2 (FPAC2) Field Descriptions .............................................. 209

4-32.

Flash Module Access Control Register (FMAC) Field Descriptions ................................................ 210

4-33.

Flash Module Status Register (FMSTAT) Field Descriptions ....................................................... 211

4-34.

EEPROM Emulation Data MSW Register (FEMU_DMSW) Field Descriptions .................................. 213

4-35.

EEPROM Emulation Data LSW Register (FEMU_DLSW) Field Descriptions .................................... 213

4-36.

EEPROM Emulation ECC Register (FEMU_ECC) Field Descriptions ............................................. 214

4-37.

EEPROM Emulation Address Register (FEMU_ADDR) Field Descriptions ...................................... 215

4-38.

Diagnostic Control Register (FDIAGCTRL) Field Descriptions ..................................................... 216

4-39.

Uncorrected Raw Data High Register (FRAW_DATAH) Field Descriptions ...................................... 218

4-40.

Uncorrected Raw Data Low Register (FRAW_DATAL) Field Descriptions ....................................... 218

4-41.

Uncorrected Raw ECC Register (FRAW_ECC) Field Descriptions ................................................ 219

4-42.

Parity Override Register (FPAR_OVR) Field Descriptions .......................................................... 220

4-43.

Flash Error Detection and Correction Sector Disable Register (FEDACSDIS2) Field Descriptions ........... 221

4-44.

FSM Register Write Enable (FSM_WR_ENA) Field Descriptions .................................................. 223

4-45.

FSM Sector Register (FSM_SECTOR) Field Descriptions .......................................................... 223

4-46.

EPROM Emulation Configuration Register (EEPROM_CONFIG) Field Descriptions ........................... 224

4-47.

EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1) Field Descriptions ... 225

4-48.

EEPROM Emulation Error Correction Control Register 2 (EE_CTRL2) Field Descriptions .................... 226

4-49.

EEPROM Emulation Correctable Error Count Register (EE_COR_ERR_CNT) Field Descriptions ........... 227

4-50.

EEPROM Emulation Correctable Error Address Register (EE_COR_ERR_ADD) Field Descriptions ........ 227

4-51.

EEPROM Emulation Correctable Error Position Register (EE_COR_ERR_POS) Field Descriptions......... 228

4-52.

EEPROM Emulation Error Status Register (EE_STATUS) Field Descriptions ................................... 229

4-53.

EEPROM Emulation Uncorrectable Error Address Register (EE_UNC_ERR_ADD) Field Descriptions...... 230

4-54.

Flash Bank Configuration Register (FCFG_BANK) Field Descriptions ............................................ 231

5-1.

TCRAM Module Control and Status Registers........................................................................ 237

5-2.

TCRAM Module Control Register (RAMCTRL) Field Descriptions ................................................. 238

5-3.

TCRAM Module Single-Bit Error Correction Threshold Register (RAMTHRESHOLD) Field Descriptions ... 239

5-4.

TCRAM Module Single-Bit Error Occurrences Counter Register (RAMOCCUR) Field Descriptions .......... 240

5-5.

TCRAM Module Interrupt Control Register (RAMINTCTRL) Field Descriptions.................................. 240

5-6.

TCRAM Module Error Status Register (RAMERRSTATUS) Field Descriptions .................................. 241

5-7.

TCRAM Module Single-Bit Error Address Register (RAMSERRADDR) Field Descriptions .................... 242

5-8.

TCRAM Module Uncorrectable Error Address Register (RAMUERRADDR) Field Descriptions ............... 243

5-9.

TCRAM Module Test Mode Control Register (RAMTEST) Field Descriptions ................................... 244

5-10.

TCRAM Module Test Mode Vector Register (RAMADDRDEVECT) Field Descriptions ........................ 245

5-11.

TCRAM Module Parity Error Address Register (RAMPERRADDR) Field Descriptions ......................... 245

6-1.

PBIST Registers .......................................................................................................... 253

6-2.

RAM Configuration Register (RAMT) Field Descriptions ............................................................ 254

6-3.

Datalogger Register (DLR) Field Descriptions ........................................................................ 255

6-4.

Program Control Register (PCR) Field Descriptions ................................................................. 256

6-5.

PBIST Activate/Clock Enable Register (PACT) Field Descriptions ................................................ 257

6-6.

PBIST ID Register (PBISTID) Field Descriptions ..................................................................... 257

6-7.

Override Register (OVER) Field Descriptions......................................................................... 258

6-8.

Fail Status Fail Register 0 (FSRF0) Field Descriptions .............................................................. 259

6-9.

Fail Status Count 0 Register (FSRC0) Field Descriptions........................................................... 260

6-10.

Fail Status Count Register 1 (FSRC1) Field Descriptions........................................................... 260

6-11.

Fail Status Address 0 Register (FSRA0) Field Descriptions ........................................................ 261

SPNU517C – March 2018
Submit Documentation Feedback

List of Tables
Copyright © 2018, Texas Instruments Incorporated

43

www.ti.com

6-12.

Fail Status Address 1 Register (FSRA1) Field Descriptions ........................................................ 261

6-13.

Fail Status Data Register 0 (FSRDL0) Field Descriptions........................................................... 262

6-14.

Fail Status Data Register 1 (FSRDL1) Field Descriptions........................................................... 262

6-15.

ROM Mask Register (ROM) Field Descriptions ....................................................................... 263

6-16.

Algorithm Mask Register (ALGO) Field Descriptions ................................................................ 263

6-17.

RAM Info Mask Lower Register (RINFOL) Field Descriptions ...................................................... 264

6-18.

RAM Info Mask Upper Register (RINFOU) Field Descriptions ..................................................... 264

7-1.

STC Test Coverage and Duration ..................................................................................... 272

7-2.

STC Control Registers ................................................................................................... 273

7-3.

STC Global Control Register 0 (STCGCR0) Field Descriptions .................................................... 274

7-4.

STC Global Control Register 1 (STCGCR1) Field Descriptions .................................................... 274

7-5.

Self-Test Run Timeout Counter Preload Register (STCTPR) ...................................................... 275

7-6.

STC Current ROM Address Register (STC_CADDR) Field Descriptions ......................................... 275

7-7.

STC Current Interval Count Register (STCCICR) Field Descriptions .............................................. 276

7-8.

Self-Test Global Status Register (STCGSTAT) Field Descriptions ................................................ 277

7-9.

Self-Test Fail Status Register (STCFSTAT) Field Descriptions .................................................... 278

7-10.

CPU1 Current MISR Register (CPU1_CURMISR[3:0]) Field Descriptions ....................................... 279

7-11.

CPU2 Current MISR Register (CPU2_CURMISR[3:0]) Field Descriptions ....................................... 280

7-12.

Signature Compare Self Check Register (STCSCSCR) Field Descriptions ...................................... 281

8-1.

Compare Match Test Sequence ........................................................................................ 286

8-2.

Compare Mismatch Test Sequence .................................................................................... 287

8-3.

CCM-R4 Control Registers .............................................................................................. 288

8-4.

CCM-R4 Status Register (CCMSR) Field Descriptions .............................................................. 289

8-5.

CCM-R4 Key Register (CCMKEYR) Field Descriptions ............................................................. 290

9-1.

Valid Frequency Ranges for PLL ....................................................................................... 300

9-2.

PLL Value Encoding ...................................................................................................... 301

9-3.

Summary of PLL Timings ................................................................................................ 305

9-4.

PLL Module Registers .................................................................................................... 309

9-5.

LPOCLKDET Module Registers ........................................................................................ 309

9-6.

SSW PLL BIST Control Register 1 (SSWPLL1) Field Descriptions ................................................ 310

9-7.

SSW PLL BIST Control Register 2 (SSWPLL2) Field Descriptions ................................................ 311

9-8.

SSW PLL BIST Control Register 3 (SSWPLL3) Field Descriptions ................................................ 312

10-1.

Clock Source Selection for DCC Counter0 ........................................................................... 322

10-2.

Clock Source Selection for DCC Counter1 ........................................................................... 322

10-3.

DCC Registers ........................................................................................................... 323

10-4.

DCC Global Control Register (DCCGCTRL) Field Descriptions ................................................... 324

10-5.

DCC Revision ID Register (DCCREV) Field Descriptions .......................................................... 325

10-6.

DCC Counter0 Seed Register (DCCCNT0SEED) Field Descriptions ............................................. 325

10-7.

DCC Valid0 Seed Register (DCCVALID0SEED) Field Descriptions .............................................. 326

10-8.

DCC Counter1 Seed Register (DCCCNT1SEED) Field Descriptions ............................................. 326

10-9.

DCC Status Register (DCCSTAT) Field Descriptions ............................................................... 327

10-10. DCC Counter0 Value Register (DCCCNT0) Field Descriptions ................................................... 328
10-11. DCC Valid0 Value Register (DCCVALID0) Field Descriptions ..................................................... 329
10-12. DCC Counter1 Value Register (DCCCNT1) Field Descriptions ................................................... 329
10-13. DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) Field Descriptions ................... 330
10-14. DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) Field Descriptions ................... 330

44

11-1.

ESM Interrupt and ERROR Pin Behavior ............................................................................. 333

11-2.

ESM Module Registers................................................................................................... 339

11-3.

ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1) Field Descriptions .................. 340

List of Tables

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

11-4.

ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1) Field Descriptions .................. 340

11-5.

ESM Interrupt Enable Set Register 1 (ESMIESR1) Field Descriptions ............................................ 341

11-6.

ESM Interrupt Enable Clear Register 1 (ESMIECR1) Field Descriptions ......................................... 341

11-7.

ESM Interrupt Level Set Register 1 (ESMILSR1) Field Descriptions .............................................. 342

11-8.

ESM Interrupt Level Clear Register 1 (ESMILCR1) Field Descriptions ........................................... 342

11-9.

ESM Status Register 1 (ESMSR1) Field Descriptions .............................................................. 343

11-10. ESM Status Register 2 (ESMSR2) Field Descriptions .............................................................. 343
11-11. ESM Status Register 3 (ESMSR3) Field Descriptions .............................................................. 344
11-12. ESM ERROR Pin Status Register (ESMEPSR) Field Descriptions ................................................ 344
11-13. ESM Interrupt Offset High Register (ESMIOFFHR) Field Descriptions............................................ 345
11-14. ESM Interrupt Offset Low Register (ESMIOFFLR) Field Descriptions ............................................. 346
11-15. ESM Low-Time Counter Register (ESMLTCR) Field Descriptions ................................................. 347
11-16. ESM Low-Time Counter Preload Register (ESMLTCPR) Field Descriptions ..................................... 347
11-17. ESM Error Key Register (ESMEKR) Field Descriptions ............................................................. 348
11-18. ESM Status Shadow Register 2 (ESMSSR2) Field Descriptions .................................................. 348
11-19. ESM Influence ERROR Pin Set Register 4 (ESMIEPSR4) Field Descriptions ................................... 349
11-20. ESM Influence ERROR Pin Clear Register 4 (ESMIEPCR4) Field Descriptions ................................ 349
11-21. ESM Interrupt Enable Set Register 4 (ESMIESR4) Field Descriptions ............................................ 350
11-22. ESM Interrupt Enable Clear Register 4 (ESMIECR4) Field Descriptions ......................................... 350
11-23. ESM Interrupt Level Set Register 4 (ESMILSR4) Field Descriptions .............................................. 351
11-24. ESM Interrupt Level Clear Register 4 (ESMILCR4) Field Descriptions ........................................... 351
11-25. ESM Status Register 4 (ESMSR4) Field Descriptions ............................................................... 352
12-1.

RTI Registers .............................................................................................................. 362

12-2.

RTI Global Control Register (RTIGCTRL) Field Descriptions....................................................... 363

12-3.

RTI Capture Control Register (RTICAPCTRL) Field Descriptions ................................................. 364

12-4.

RTI Compare Control Register (RTICOMPCTRL) Field Descriptions ............................................. 365

12-5.

RTI Free Running Counter 0 Register (RTIFRC0) Field Descriptions ............................................. 366

12-6.

RTI Up Counter 0 Register (RTIUC0) Field Descriptions ........................................................... 366

12-7.

RTI Compare Up Counter 0 Register (RTICPUC0) Field Descriptions ............................................ 367

12-8.

RTI Capture Free Running Counter 0 Register (RTICAFRC0) Field Descriptions ............................... 367

12-9.

RTI Capture Up Counter 0 Register (RTICAUC0) Field Descriptions ............................................. 368

12-10. RTI Free Running Counter 1 Register (RTIFRC1) Field Descriptions ............................................. 368
12-11. RTI Up Counter 1 Register (RTIUC1) Field Descriptions ........................................................... 369
12-12. RTI Compare Up Counter 1 Register (RTICPUC1) Field Descriptions ............................................ 370
12-13. RTI Capture Free Running Counter 1 Register (RTICAFRC1) Field Descriptions ............................... 371
12-14. RTI Capture Up Counter 1 Register (RTICAUC1) Field Descriptions ............................................. 371
12-15. RTI Compare 0 Register (RTICOMP0) Field Descriptions .......................................................... 372
12-16. RTI Update Compare 0 Register (RTIUDCP0) Field Descriptions ................................................. 372
12-17. RTI Compare 1 Register (RTICOMP1) Field Descriptions .......................................................... 373
12-18. RTI Update Compare 1 Register (RTIUDCP1) Field Descriptions ................................................. 373
12-19. RTI Compare 2 Register (RTICOMP2) Field Descriptions .......................................................... 374
12-20. RTI Update Compare 2 Register (RTIUDCP2) Field Descriptions ................................................. 374
12-21. RTI Compare 3 Register (RTICOMP3) Field Descriptions .......................................................... 375
12-22. RTI Update Compare 3 Register (RTIUDCP3) Field Descriptions ................................................. 375
12-23. RTI Set Interrupt Control Register (RTISETINTENA) Field Descriptions ......................................... 376
12-24. RTI Clear Interrupt Control Register (RTICLEARINTENA) Field Descriptions ................................... 378
12-25. RTI Interrupt Flag Register (RTIINTFLAG) Field Descriptions...................................................... 380
12-26. Digital Watchdog Control Register (RTIDWDCTRL) Field Descriptions ........................................... 381
12-27. Digital Watchdog Preload Register (RTIDWDPRLD) Field Descriptions .......................................... 382
SPNU517C – March 2018
Submit Documentation Feedback

List of Tables
Copyright © 2018, Texas Instruments Incorporated

45

www.ti.com

12-28. Watchdog Status Register (RTIWDSTATUS) Field Descriptions .................................................. 383
12-29. RTI Watchdog Key Register (RTIDWDKEY) Field Descriptions.................................................... 384
12-30. Example of a WDKEY Sequence ....................................................................................... 384
12-31. RTI Watchdog Down Counter Register (RTIDWDCNTR) Field Descriptions ..................................... 385
12-32. Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) Field Descriptions ...................... 385
12-33. Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) Field Descriptions ................. 386
12-34. RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE)............................................. 387
12-35. RTI Compare 0 Clear Register (RTICMP0CLR) ...................................................................... 388
12-36. RTI Compare 1 Clear Register (RTICMP1CLR) ...................................................................... 388
12-37. RTI Compare 2 Clear Register (RTICMP2CLR) ...................................................................... 389
12-38. RTI Compare 3 Clear Register (RTICMP3CLR) ...................................................................... 389
13-1.

CRC Control Registers ................................................................................................... 395

13-2.

CRC Global Control Register 0 (CRC_CTRL0) Field Descriptions ................................................ 396

13-3.

CRC Global Control Register 1 (CRC_CTRL1) Field Descriptions ................................................ 396

13-4.

CRC Global Control Register 2 (CRC_CTRL2) Field Descriptions ................................................ 397

13-5.

Channel 1 PSA Signature Low Register (PSA_SIGREGL1) Field Descriptions ................................. 398

13-6.

Channel 1 PSA Signature High Register (PSA_SIGREGH1) Field Descriptions ................................ 398

13-7.

Channel 1 Raw Data Low Register (RAW_DATAREGL1) Field Descriptions .................................... 399

13-8.

Channel 1 Raw Data High Register (RAW_DATAREGH1) Field Descriptions ................................... 399

13-9.

Channel 2 PSA Signature Low Register (PSA_SIGREGL2) Field Descriptions ................................. 400

13-10. Channel 2 PSA Signature High Register (PSA_SIGREGH2) Field Descriptions ................................ 400
13-11. Channel 2 Raw Data Low Register (RAW_DATAREGL2) Field Descriptions .................................... 401
13-12. Channel 2 Raw Data High Register (RAW_DATAREGH2) Field Descriptions ................................... 401
13-13. Data Bus Selection Register Field Descriptions ...................................................................... 402
14-1.

VIM Control Registers .................................................................................................... 418

14-2.

Interrupt Vector Table Parity Flag Register (PARFLG) Field Descriptions ........................................ 419

14-3.

Interrupt Vector Table Parity Control Register (PARCTL) Field Descriptions .................................... 419

14-4.

Address Parity Error Register (ADDERR) Field Descriptions ....................................................... 420

14-5.

Fall Back Address Parity Error Register (FBPARERR) Field Descriptions ....................................... 420

14-6.

Interrupt Dispatch ......................................................................................................... 421

14-7.

IRQ Index Offset Vector Register (IRQINDEX) Field Descriptions ................................................. 422

14-8.

FIQ Index Offset Vector Register (FIQINDEX) Field Descriptions ................................................. 422

14-9.

FIQ/IRQ Program Control Registers (FIRQPRx) Field Descriptions ............................................... 423

14-10. Pending Interrupt Read Location Registers (INTREQx) Field Descriptions ...................................... 424
14-11. Interrupt Enable Set Registers (REQENASETx) Field Descriptions .............................................. 425
14-12. Interrupt Enable Clear Registers (REQENACLRx) Field Descriptions............................................. 426
14-13. Wake-Up Enable Set Registers (WAKEENASETx) Field Descriptions ............................................ 427
14-14. Wake-Up Enable Clear Registers (WAKEENACLRx) Field Descriptions ......................................... 428
14-15. IRQ Interrupt Vector Register (IRQVECREG) Field Descriptions .................................................. 429
14-16. FIQ Interrupt Vector Register (FIQVECREG) Field Descriptions ................................................... 429
14-17. Capture Event Register (CAPEVT) Field Descriptions .............................................................. 430
14-18. Interrupt Control Registers Organization .............................................................................. 431
14-19. Interrupt Control Registers (CHANCTRLx) Field Descriptions...................................................... 431

46

15-1.

EQEP Memory Map ...................................................................................................... 438

15-2.

Quadrature Decoder Truth Table ....................................................................................... 440

15-3.

eQEP Registers ........................................................................................................... 454

15-4.

eQEP Position Counter (QPOSCNT) Register Field Descriptions ................................................. 454

15-5.

eQEP Position Counter Initialization (QPOSINIT) Register Field Descriptions ................................... 455

15-6.

eQEP Maximum Position Count (QPOSMAX) Register Field Descriptions ....................................... 455

List of Tables

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

15-7.

eQEP Position-Compare (QPOSCMP) Register Field Descriptions ............................................... 455

15-8.

eQEP Index Position Latch (QPOSILAT) Register Field Descriptions............................................. 456

15-9.

eQEP Strobe Position Latch (QPOSSLAT) Register Field Descriptions .......................................... 456

15-10. eQEP Position Counter Latch (QPOSLAT) Register Field Descriptions .......................................... 456
15-11. eQEP Unit Timer (QUTMR) Register Field Descriptions ............................................................ 457
15-12. eQEP Unit Period (QUPRD) Register Field Descriptions ........................................................... 457
15-13. eQEP Watchdog Timer (QWDTMR) Register Field Descriptions .................................................. 457
15-14. eQEP Watchdog Period (QWDPRD) Register Field Description ................................................... 458
15-15. eQEP Decoder Control (QDECCTL) Register Field Descriptions .................................................. 459
15-16. eQEP Control (QEPCTL) Register Field Descriptions ............................................................... 460
15-17. eQEP Capture Control (QCAPCTL) Register Field Descriptions ................................................... 462
15-18. eQEP Position-compare Control (QPOSCTL) Register Field Descriptions ....................................... 463
15-19. eQEP Interrupt Enable (QEINT) Register Field Descriptions ....................................................... 464
15-20. eQEP Interrupt Flag (QFLG) Register Field Descriptions ........................................................... 465
15-21. eQEP Interrupt Clear (QCLR) Register Field Descriptions .......................................................... 466
15-22. eQEP Interrupt Force (QFRC) Register Field Descriptions ......................................................... 467
15-23. eQEP Status (QEPSTS) Register Field Descriptions ................................................................ 468
15-24. eQEP Capture Timer (QCTMR) Register Field Descriptions ....................................................... 469
15-25. eQEP Capture Period Register (QCPRD) Register Field Descriptions ............................................ 469
15-26. eQEP Capture Timer Latch (QCTMRLAT) Register Field Descriptions ........................................... 470
15-27. eQEP Capture Period Latch (QCPRDLAT) Register Field Descriptions .......................................... 470
16-1.

ADC Look-Up Table Field Descriptions ................................................................................ 484

16-2.

Calibration Reference Voltages ......................................................................................... 491

16-3.

Self-Test Reference Voltages ........................................................................................... 494

16-4.

Determination of ADC Input Channel Condition ...................................................................... 495

16-5.

Output Buffer and Pull Control Behavior for ADEVT as GPIO Pins................................................ 499

16-6.

ADC Registers ............................................................................................................ 500

16-7.

ADC Reset Control Register (ADRSTCR) Field Descriptions ...................................................... 502

16-8.

ADC Operating Mode Control Register (ADOPMODECR) Field Descriptions ................................... 503

16-9.

ADC Clock Control Register (ADCLOCKCR) Field Descriptions ................................................... 504

16-10. ADC Calibration Mode Control Register (ADCALCR) Field Descriptions ......................................... 505
16-11. ADC Event Group Operating Mode Control Register (ADEVMODECR) Field Descriptions .................... 508
16-12. ADC Group1 Operating Mode Control Register (ADG1MODECR) Field Descriptions .......................... 511
16-13. ADC Group 2 Operating Mode Control Register (ADG2MODECR) Field Descriptions ......................... 514
16-14. ADC Event Group Trigger Source Select Register (ADEVSRC) Field Descriptions ............................. 516
16-15. ADC Group1 Trigger Source Select Register (ADG1SRC) Field Descriptions ................................... 517
16-16. ADC Group2 Trigger Source Select Register (ADG2SRC) Field Descriptions ................................... 518
16-17. ADC Event Group Interrupt Enable Control Register (ADEVINTENA) Field Descriptions ...................... 519
16-18. ADC Group1 Interrupt Enable Control Register (ADG1INTENA) Field Descriptions ............................ 520
16-19. ADC Group2 Interrupt Enable Control Register (ADG2INTENA) Field Descriptions ............................ 521
16-20. ADC Event Group Interrupt Flag Register (ADEVINTFLG) Field Descriptions ................................... 522
16-21. ADC Group1 Interrupt Flag Register (ADG1INTFLG) Field Descriptions ......................................... 523
16-22. ADC Group2 Interrupt Flag Register (ADG2INTFLG) Field Descriptions ......................................... 524
16-23. ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) Field Descriptions .............. 525
16-24. ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR) Field Descriptions ..................... 525
16-25. ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) Field Descriptions ..................... 526
16-26. ADC Results Memory Configuration Register (ADBNDCR) Field Descriptions .................................. 527
16-27. ADC Results Memory Size Configuration Register (ADBNDEND) Field Descriptions .......................... 528
16-28. ADC Event Group Sampling Time Configuration Register (ADEVSAMP) Field Descriptions .................. 529
SPNU517C – March 2018
Submit Documentation Feedback

List of Tables
Copyright © 2018, Texas Instruments Incorporated

47

www.ti.com

16-29. ADC Group1 Sampling Time Configuration Register (ADG1SAMP) Field Descriptions ........................ 529
16-30. ADC Group2 Sampling Time Configuration Register (ADG2SAMP) Field Descriptions ........................ 530
16-31. ADC Event Group Status Register (ADEVSR) Field Descriptions ................................................. 531
16-32. ADC Group1 Status Register (ADG1SR) Field Descriptions ....................................................... 532
16-33. ADC Group2 Status Register (ADG2SR) Field Descriptions ....................................................... 533
16-34. ADC Event Group Channel Select Register (ADEVSEL) Field Descriptions ..................................... 534
16-35. ADC Group1 Channel Select Register (ADG1SEL) Field Descriptions ........................................... 535
16-36. ADC Group2 Channel Select Register (ADG2SEL) Field Descriptions ........................................... 536
16-37. ADC Calibration and Error Offset Correction Register (ADCALR) Field Descriptions ........................... 537
16-38. ADC State Machine Status Register (ADSMSTATE) Field Descriptions .......................................... 537
16-39. ADC Channel Last Conversion Value Register (ADLASTCONV) Field Descriptions ............................ 538
16-40. ADC Event Group Results' FIFO Register (ADEVBUFFER) Field Descriptions ................................. 539
16-41. ADC Group1 Results FIFO Register (ADG1BUFFER) Field Descriptions ........................................ 540
16-42. ADC Group2 Results FIFO Register (ADG2BUFFER) Field Descriptions ........................................ 541
16-43. ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER) Field Descriptions ............... 542
16-44. ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) Field Descriptions ..................... 543
16-45. ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) Field Descriptions ..................... 544
16-46. ADC ADEVT Pin Direction Control Register (ADEVTDIR) Field Descriptions .................................... 545
16-47. ADC ADEVT Pin Output Value Control Register (ADEVTOUT) Field Descriptions ............................. 546
16-48. ADC ADEVT Pin Input Value Register (ADEVTIN) Field Descriptions ............................................ 546
16-49. ADC ADEVT Pin Set Register (ADEVTSET) Field Descriptions ................................................... 547
16-50. ADC ADEVT Pin Clear Register (ADEVTCLR) Field Descriptions ................................................. 547
16-51. ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) Field Descriptions ................................ 548
16-52. ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) Field Descriptions .............................. 548
16-53. ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) Field Descriptions ............................... 549
16-54. ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN) Field Descriptions ....... 549
16-55. ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) Field Descriptions .............. 550
16-56. ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) Field Descriptions .............. 551
16-57. ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR) Field Descriptions ................ 553
16-58. ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK) Field Descriptions .................... 554
16-59. ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) Field Descriptions.......... 555
16-60. ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR) Field Descriptions ....... 555
16-61. ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG) Field Descriptions ....................... 556
16-62. ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF) Field Descriptions ..................... 556
16-63. ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR) Field Descriptions .................. 557
16-64. ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) Field Descriptions ........................ 557
16-65. ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) Field Descriptions ........................ 558
16-66. ADC Event Group RAM Write Address Register (ADEVRAMWRADDR) Field Descriptions ................... 558
16-67. ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) Field Descriptions ......................... 559
16-68. ADC Group2 RAM Write Address Register (ADG2RAMWRADDR) Field Descriptions ......................... 559
16-69. ADC Parity Control Register (ADPARCR) Field Descriptions ...................................................... 560
16-70. ADC Parity Error Address Register (ADPARADDR) Field Descriptions ........................................... 560
16-71. ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL) Field Descriptions ............................. 561
16-72. ADC Event Group Channel Selection Mode Control Register (ADEVCHNSELMODECTRL) Field
Descriptions ............................................................................................................... 561
16-73. ADC Group1 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL) Field Descriptions .. 562
16-74. ADC Group2 Channel Selection Mode Control Register (ADG2CHNSELMODECTRL) Field Descriptions .. 562
16-75. ADC Event Group Current Count Register (ADEVCURRCOUNT) Field Descriptions .......................... 563
16-76. ADC Event Group Maximum Count Register (ADEVMAXCOUNT) Field Descriptions.......................... 563
48

List of Tables

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

16-77. ADC Group1 Current Count Register (ADG1CURRCOUNT) Field Descriptions ................................ 564
16-78. ADC Group1 Maximum Count Register (ADG1MAXCOUNT) Field Descriptions ................................ 564
16-79. ADC Group2 Current Count Register (ADG2CURRCOUNT) Field Descriptions ................................ 565
16-80. ADC Group2 Maximum Count Register (ADG2MAXCOUNT) Field Descriptions ................................ 565
17-1.

N2HET RAM Base Addresses .......................................................................................... 576

17-2.

N2HET RAM Bank Structure ............................................................................................ 577

17-3.

Pin Safe State Upon Parity Error Detection ........................................................................... 578

17-4.

N2HET Parity Bit Mapping ............................................................................................... 579

17-5.

Prescale Factor Register Encoding .................................................................................... 580

17-6.

Interpretation of the 7-Bit HR Data Field............................................................................... 581

17-7.

Edge Detection Input Timing for Loop Resolution Instructions ..................................................... 591

17-8.

Edge Detection Input Timing for High Resolution Instructions...................................................... 591

17-9.

Input Buffer, Output Buffer, and Pull Control Behavior .............................................................. 596

17-10. N2HET Pin Disable Feature ............................................................................................. 597
17-11. Pulse Length Examples for Suppression Filter ....................................................................... 598
17-12. Interrupt Sources and Corresponding Offset Values in Registers HETOFFx..................................... 599
17-13. N2HET Registers ......................................................................................................... 605
17-14. Global Configuration Register (HETGCR) Field Descriptions ...................................................... 606
17-15. Prescale Factor Register (HETPFR) Field Descriptions ............................................................. 608
17-16. N2HET Current Address (HETADDR) Field Descriptions ........................................................... 609
17-17. Offset Index Priority Level 1 Register (HETOFF1) Field Descriptions ............................................. 610
17-18. Interrupt Offset Encoding Format ....................................................................................... 610
17-19. Offset Index Priority Level 2 Register (HETOFF2) Field Descriptions ............................................. 611
17-20. Interrupt Enable Set Register (HETINTENAS) Field Descriptions ................................................. 612
17-21. NHET Interrupt Enable Clear (HETINTENAC) Field Descriptions ................................................. 612
17-22. Exception Control Register 1 (HETEXC1) Field Descriptions ...................................................... 613
17-23. Exception Control Register 2 (HETEXC2) Field Descriptions ...................................................... 614
17-24. Interrupt Priority Register (HETPRY) Field Descriptions ............................................................ 615
17-25. Interrupt Flag Register (HETFLG) Field Descriptions ................................................................ 615
17-26. AND Share Control Register (HETAND) Field Descriptions ........................................................ 616
17-27. HR Share Control Register (HETHRSH) Field Descriptions ........................................................ 617
17-28. XOR Share Control Register (HETXOR) Field Descriptions ........................................................ 618
17-29. Request Enable Set Register (HETREQENS) Field Descriptions .................................................. 619
17-30. Request Enable Clear Register (HETREQENC) Field Descriptions ............................................... 619
17-31. N2HET Direction Register (HETDIR) Field Descriptions ............................................................ 620
17-32. N2HET Data Input Register (HETDIN) Field Descriptions .......................................................... 621
17-33. N2HET Data Output Register (HETDOUT) Field Descriptions ..................................................... 621
17-34. N2HET Data Set Register (HETDSET) Field Descriptions .......................................................... 622
17-35. N2HET Data Clear Register (HETDCLR) Field Descriptions ....................................................... 622
17-36. N2HET Open Drain Register (HETPDR) Field Descriptions ........................................................ 623
17-37. N2HET Pull Disable Register (HETPULDIS) Field Descriptions ................................................... 623
17-38. N2HET Pull Select Register (HETPSL) Field Descriptions.......................................................... 624
17-39. Parity Control Register (HETPCR) Field Descriptions ............................................................... 625
17-40. Parity Address Register (HETPAR) Field Descriptions .............................................................. 626
17-41. Parity Pin Register (HETPPR) Field Descriptions .................................................................... 627
17-42. Known State on Parity Error ............................................................................................. 627
17-43. Suppression Filter Preload Register (HETSFPRLD) Field Descriptions........................................... 628
17-44. Suppression Filter Enable Register (HETSFENA) Field Descriptions ............................................. 628
17-45. Loop Back Pair Select Register (HETLBPSEL) Field Descriptions ................................................ 629
SPNU517C – March 2018
Submit Documentation Feedback

List of Tables
Copyright © 2018, Texas Instruments Incorporated49

www.ti.com

17-46. Loop Back Pair Direction Register (HETLBPDIR) Field Descriptions ............................................. 630
17-47. NHET Pin Disable Register (HETPINDIS) Field Descriptions ...................................................... 631
17-48. Instruction Summary ..................................................................................................... 632
17-49. FLAGS Generated by Instruction ...................................................................................... 633
17-50. Interrupt Capable Instructions ........................................................................................... 633
17-51. Arithmetic / Bitwise Logic Sub-Opcodes ............................................................................... 645
17-52. Source Operand Choices ................................................................................................ 645
17-53. Destination Operand Choices ........................................................................................... 645
17-54. Shift Encoding ............................................................................................................. 646
17-55. Execution Time for ADC, ADD, AND, OR, SBB, SUB, XOR Instructions ......................................... 646
17-56. Move Types for ADM32 .................................................................................................. 651
17-57. Edge Select Encoding for APCNT ...................................................................................... 654
17-58. Branch Condition Encoding for BR ..................................................................................... 657
17-59. DADM64 Control Field Description ..................................................................................... 662
17-60. Event Encoding Format for ECNT ...................................................................................... 670
17-61. Magnitude Compare Order for MCMP ................................................................................. 672
17-62. Move Type Encoding Selection ......................................................................................... 675
17-63. MOV64 Control Field Descriptions ..................................................................................... 679
17-64. Comparison Type Encoding Format.................................................................................... 680
17-65. Counter Type Encoding Format ........................................................................................ 682
17-66. Comparison Type Encoding Format.................................................................................... 689
17-67. RADM64 Control Field Descriptions.................................................................................... 689
17-68. Step Width Encoding for SCNT ......................................................................................... 695
17-69. SHIFT MODE Encoding Format ........................................................................................ 697
17-70. SHIFT Condition Encoding .............................................................................................. 697
17-71. Event Encoding Format for WCAP ..................................................................................... 700
17-72. Event Encoding Format for WCAPE ................................................................................... 702
18-1.

CPENA / TMBx Priority Rules ........................................................................................... 711

18-2.

Triggered Control Packets ............................................................................................... 714

18-3.

DCP RAM .................................................................................................................. 716

18-4.

DCP Parity RAM .......................................................................................................... 716

18-5.

Field Addresses of the WCAP, ECNT, PCNT Example ............................................................. 717

18-6.

32-Bit-Transfer of Data Fields .......................................................................................... 718

18-7.

Destination Buffer Values ................................................................................................ 718

18-8.

64-Bit-Transfer of Control Field and Data Fields .................................................................... 719

18-9.

Destination Buffer Values ................................................................................................ 719

18-10. Control Register Mapping................................................................................................ 720
18-11. Global Control Register (HTU GC) Field Descriptions ............................................................... 721
18-12. Control Packet Enable Register (HTU CPENA) Field Descriptions ................................................ 722
18-13. CPENA Write Results .................................................................................................... 722
18-14. CPENA Read Results .................................................................................................... 722
18-15. Control Packet (CP) Busy Register 0 (HTU BUSY0) Field Descriptions .......................................... 723
18-16. Control Packet (CP) Busy Register 1 (HTU BUSY1) Field Descriptions .......................................... 724
18-17. Control Packet (CP) Busy Register 2 (HTU BUSY2) Field Descriptions .......................................... 724
18-18. Control Packet (CP) Busy Register 3 (HTU BUSY3) Field Descriptions .......................................... 725
18-19. Active Control Packet and Error Register (HTU ACPE) Field Descriptions ....................................... 725
18-20. Request Lost and Bus Error Control Register (HTU RLBECTRL) Field Descriptions ........................... 727
18-21. Buffer Full Interrupt Enable Set Register (HTU BFINTS) Field Descriptions ..................................... 728
18-22. Buffer Full Interrupt Enable Clear Register (HTU BFINTC) Field Descriptions ................................... 728
50

List of Tables

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

18-23. Interrupt Mapping Register (HTU INTMAP) Field Descriptions ..................................................... 729
18-24. Interrupt Offset Register 0 (HTU INTOFF0) Field Descriptions..................................................... 730
18-25. Interrupt Offset Register 1 (HTU INTOFF1) Field Descriptions..................................................... 731
18-26. Buffer Initialization Mode Register (HTU BIM) Field Descriptions .................................................. 732
18-27. Buffer Initialization ........................................................................................................ 732
18-28. Request Lost Flag Register (HTU RLOSTFL) Field Descriptions ................................................. 734
18-29. Buffer Full Interrupt Flag Register (HTU BFINTFL) Field Descriptions ........................................... 734
18-30. BER Interrupt Flag Register (HTU BERINTFL) Field Descriptions ................................................. 735
18-31. Memory Protection 1 Start Address Register (HTU MP1S) Field Descriptions................................... 736
18-32. Memory Protection 1 End Address Register (HTU MP1E) Field Descriptions ................................... 736
18-33. Debug Control Register (HTU DCTRL) Field Descriptions .......................................................... 737
18-34. Watch Point Register (HTU WPR) Field Descriptions ............................................................... 738
18-35. Watch Mask Register (HTU WMR) Field Descriptions............................................................... 738
18-36. Module Identification Register (HTU ID) Field Descriptions ......................................................... 739
18-37. Parity Control Register (HTU PCR) Field Descriptions .............................................................. 740
18-38. Parity Address Register (HTU PAR) Field Descriptions ............................................................. 741
18-39. Memory Protection Control and Status Register (HTU MPCS) Field Descriptions .............................. 742
18-40. Memory Protection 0 Start Address Register (HTU MP0S) Field Descriptions................................... 745
18-41. Memory Protection End Address Register (HTU MP0E) Field Descriptions ...................................... 745
18-42. Double Control Packet Memory Map................................................................................... 746
18-43. Initial Full Address A Register (HTU IFADDRA) Field Descriptions................................................ 747
18-44. Initial Full Address B Register (HTU IFADDRB) Field Descriptions................................................ 747
18-45. Initial N2HET Address and Control Register (HTU IHADDRCT) Field Descriptions ............................. 748
18-46. Initial Transfer Count Register (HTU ITCOUNT) Field Descriptions ............................................... 749
18-47. Current Full Address A Register (HTU CFADDRA) Field Descriptions ............................................ 750
18-48. Current Full Address B Register (HTU CFADDRB) Field Descriptions ............................................ 751
18-49. Current Frame Count Register (HTU CFCOUNT) Field Descriptions ............................................. 752
18-50. Application Examples for Setting the Transfer Modes of CP A and B of a DCP ................................. 753
19-1.

GIO Control Registers .................................................................................................... 763

19-2.

GIO Global Control Register (GIOGCR0) Field Descriptions ...................................................... 764

19-3.

GIO Interrupt Detect Register (GIOINTDET) Field Descriptions ................................................... 765

19-4.

GIO Interrupt Polarity Register (GIOPOL) Field Descriptions....................................................... 766

19-5.

GIO Interrupt Enable Set Register (GIOENASET) Field Descriptions ............................................. 767

19-6.

GIO Interrupt Enable Clear Register (GIOENACLR) Field Descriptions .......................................... 768

19-7.

GIO Interrupt Priority Register (GIOLVLSET) Field Descriptions .................................................. 769

19-8.

GIO Interrupt Priority Register (GIOLVLCLR) Field Descriptions .................................................. 771

19-9.

GIO Interrupt Flag Register (GIOFLG) Field Descriptions .......................................................... 772

19-10. GIO Offset 1 Register (GIOOFF1) Field Descriptions ............................................................... 773
19-11. GIO Offset 2 Register (GIOOFF2) Field Descriptions ............................................................... 774
19-12. GIO Emulation 1 Register (GIOEMU1) Field Descriptions .......................................................... 775
19-13. GIO Emulation 2 Register (GIOEMU2) Field Descriptions .......................................................... 776
19-14. GIO Data Direction Registers (GIODIR[A-B]) Field Descriptions ................................................... 777
19-15. GIO Data Input Registers (GIODIN[A-B]) Field Descriptions ....................................................... 777
19-16. GIO Data Output Registers (GIODOUT[A-B]) Field Descriptions .................................................. 778
19-17. GIO Data Set Registers (GIODSET[A-B]) Field Descriptions ....................................................... 778
19-18. GIO Data Clear Registers (GIODCLR[A-B]) Field Descriptions .................................................... 779
19-19. GIO Open Drain Registers (GIOPDR[A-B]) Field Descriptions ..................................................... 779
19-20. GIO Pull Disable Registers (GIOPULDIS[A-B]) Field Descriptions ................................................ 780
19-21. GIO Pull Select Registers (GIOPSL[A-B]) Field Descriptions....................................................... 780
SPNU517C – March 2018
Submit Documentation Feedback

List of Tables
Copyright © 2018, Texas Instruments Incorporated

51

www.ti.com

19-22. Output Buffer and Pull Control Behavior for GIO Pins ............................................................... 781
20-1.

Parameters of the CAN Bit Time ....................................................................................... 786

20-2.

Message Object Field Descriptions .................................................................................... 793

20-3.

Message RAM Addressing in Debug/Suspend and RDA mode ................................................... 795

20-4.

Message Interface Register Sets 1 and 2 ............................................................................ 797

20-5.

Message Interface Register 3 .......................................................................................... 799

20-6.

DCAN Control Registers ................................................................................................. 818

20-7.

CAN Control Register Field Descriptions .............................................................................. 820

20-8.

Error and Status Register Field Descriptions ......................................................................... 822

20-9.

Error Counter Register Field Descriptions ............................................................................. 824

20-10. Bit Timing Register Field Descriptions ................................................................................. 825
20-11. Interrupt Register Field Descriptions ................................................................................... 826
20-12. Test Register Field Descriptions ........................................................................................ 827
20-13. Parity Error Code Register Field Descriptions ........................................................................ 828
20-14. Core Release Register (DCAN REL) Field Descriptions ............................................................ 828
20-15. Auto-Bus-On Time Register Field Descriptions ....................................................................... 829
20-16. Transmission Request Registers Field Descriptions ................................................................. 830
20-17. New Data Registers Field Descriptions ................................................................................ 832
20-18. Interrupt Pending Registers Field Descriptions ....................................................................... 834
20-19. Message Valid Registers Field Descriptions .......................................................................... 836
20-20. Interrupt Multiplexer Registers Field Descriptions .................................................................... 837
20-21. IF1/IF2 Command Register Field Descriptions ....................................................................... 839
20-22. IF1/IF2 Mask Register Field Descriptions ............................................................................. 841
20-23. IF1/IF2 Arbitration Register Field Descriptions ....................................................................... 842
20-24. IF1/IF2 Message Control Register Field Descriptions ............................................................... 844
20-25. IF3 Observation Register Field Descriptions .......................................................................... 846
20-26. IF3 Mask Register Field Descriptions .................................................................................. 848
20-27. IF3 Arbitration Register Field Descriptions ............................................................................ 849
20-28. IF3 Message Control Register Field Descriptions .................................................................... 850
20-29. IF3 Update Control Register Field Descriptions ...................................................................... 852
20-30. CAN TX IO Control Register Field Descriptions ...................................................................... 853
20-31. CAN RX IO Control Register Field Descriptions ...................................................................... 854
21-1.

Pin Configurations ........................................................................................................ 859

21-2.

Clocking Modes ........................................................................................................... 866

21-3.

SPI Registers .............................................................................................................. 879

21-4.

SPI Global Control Register 0 (SPIGCR0) Field Descriptions ...................................................... 880

21-5.

SPI Global Control Register 1 (SPIGCR1) Field Descriptions ...................................................... 881

21-6.

SPI Interrupt Register (SPIINT0) Field Descriptions ................................................................. 882

21-7.

SPI Interrupt Level Register (SPILVL) Field Descriptions ........................................................... 884

21-8.

SPI Flag Register (SPIFLG) Field Descriptions ...................................................................... 885

21-9.

SPI Pin Control (SPIPC0) Field Descriptions ......................................................................... 888

21-10. SPI Pin Control Register (SPIPC1) Field Descriptions .............................................................. 889
21-11. SPI Pin Control Register 2 (SPIPC2) Field Descriptions ............................................................ 891
21-12. SPI Pin Control Register 3 (SPIPC3) Field Descriptions ............................................................ 892
21-13. SPI Pin Control Register 4 (SPIPC4) Field Descriptions ............................................................ 893
21-14. SPI Pin Control Register 5 (SPIPC5) Field Descriptions ............................................................ 895
21-15. SPI Pin Control Register 6 (SPIPC6) Field Descriptions ............................................................ 897
21-16. SPI Pin Control Register 7 (SPIPC7) Field Descriptions ............................................................ 898
21-17. SPI Pin Control Register 8 (SPIPC8) Field Descriptions ............................................................ 899
52

List of Tables

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

www.ti.com

21-18. SPI Transmit Data Register 0 (SPIDAT0) Field Descriptions ....................................................... 900
21-19. SPI Transmit Data Register 1 (SPIDAT1) Field Descriptions ....................................................... 901
21-20. Chip Select Number Active .............................................................................................. 903
21-21. SPI Receive Buffer Register (SPIBUF) Field Descriptions .......................................................... 904
21-22. SPI Emulation Register (SPIEMU) Field Descriptions ............................................................... 906
21-23. SPI Delay Register (SPIDELAY) Field Descriptions ................................................................. 906
21-24. SPI Default Chip Select Register (SPIDEF) Field Descriptions .................................................... 909
21-25. SPI Data Format Registers (SPIFMT[3:0]) Field Descriptions ...................................................... 910
21-26. Transfer Group Interrupt Vector 0 (INTVECT0) ...................................................................... 912
21-27. Transfer Group Interrupt Vector 1 (INTVECT1) ...................................................................... 913
21-28. SPI Pin Control Register 9 (SPIPC9) Field Descriptions ............................................................ 915
21-29. Multi-buffer Mode Enable Register (MIBSPIE) Field Descriptions ................................................. 916
21-30. TG Interrupt Enable Set Register (TGITENST) Field Descriptions ................................................ 917
21-31. TG Interrupt Enable Clear Register (TGITENCR) Field Descriptions .............................................. 918
21-32. Transfer Group Interrupt Level Set Register (TGITLVST) Field Descriptions .................................... 919
21-33. Transfer Group Interrupt Level Clear Register (TGITLVCR) Field Descriptions ................................. 920
21-34. Transfer Group Interrupt Level Clear Register (TGITLVCR) Field Descriptions ................................. 921
21-35. Tick Count Register (TICKCNT) Field Descriptions .................................................................. 922
21-36. Last TG End Pointer (LTGPEND) Field Descriptions ................................................................ 923
21-37. TG Control Registers (TGxCTRL) Field Descriptions ................................................................ 924
21-38. Multi-buffer RAM Uncorrectable Parity Error Control Register (UERRCTRL) Field Descriptions .............. 927
21-39. Multi-buffer RAM Uncorrectable Parity Error Status Register (UERRSTAT) Field Descriptions ............... 928
21-40. RXRAM Uncorrectable Parity Error Address Register (UERRADDR1) Field Descriptions ..................... 929
21-41. TXRAM Uncorrectable Parity Error Address Register (UERRADDR0) Field Descriptions ..................... 930
21-42. RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) Field Descriptions ........................ 931
21-43. I/O-Loopback Test Control Register (IOLPBKTSTCR) Field Descriptions ........................................ 932
21-44. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1) Field Descriptions ............................ 934
21-45. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2) Field Descriptions ............................ 936
21-46. Multi-buffer RAM Register Summary ................................................................................... 939
21-47. Multi-buffer RAM Transmit Data Register (TXRAM) Field Descriptions ........................................... 940
21-48. Chip Select Number Active .............................................................................................. 942
21-49. Multi-buffer Receive Buffer Register (RXRAM) Field Descriptions ................................................. 943
22-1.

Superfractional Bit Modulation for SCI Mode (Normal Configuration) ............................................. 960

22-2.

Superfractional Bit Modulation for SCI Mode (Maximum Configuration) .......................................... 961

22-3.

SCI Mode (Minimum Configuration) .................................................................................... 961

22-4.

SCI/LIN Interrupts ......................................................................................................... 968

22-5.

Response Length Info Using IDBYTE Field Bits [5:4] for LIN Standards Earlier than 1.3 ...................... 974

22-6.

Response Length with SCIFORMAT[18:16] Programming.......................................................... 974

22-7.

Superfractional Bit Modulation for LIN Master Mode and Slave Mode ............................................ 976

22-8.

Timeout Values in Tbit Units .............................................................................................. 983

22-9.

SCI/LIN Control Registers ............................................................................................... 995

22-10. SCI Global Control Register 0 (SCIGCR0) Field Descriptions ...................................................... 996
22-11. SCI Global Control Register 1 (SCIGCR1) Field Descriptions ...................................................... 997
22-12. SCI Receiver Status Flags ............................................................................................. 100022-13. SCI Transmitter Status Flags .......................................................................................... 100022-14. SCI Global Control Register 2 (SCIGCR2) Field Descriptions .................................................... 1001
22-15. SCI Set Interrupt Register (SCISETINT) Field Descriptions ....................................................... 1002
22-16. SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions................................................. 1005
22-17. SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions ........................................... 1008
SPNU517C – March 2018
Submit Documentation Feedback

List of Tables
Copyright © 2018, Texas Instruments Incorporated

53

www.ti.com

22-18. SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions .................................... 1010
22-19. SCI Flags Register (SCIFLR) Field Descriptions.................................................................... 1013
22-20. SCI Interrupt Vector Offset 0 (SCIINTVECT0) Field Descriptions ................................................ 1020
22-21. SCI Interrupt Vector Offset 1 (SCIINTVECT1) Field Descriptions ................................................ 1020
22-22. SCI Format Control Register (SCIFORMAT) Field Descriptions .................................................. 1021
22-23. Baud Rate Selection Register (BRS) Field Descriptions ........................................................... 1022
22-24. Comparative Baud Values for Different P Values, Asynchronous Mode ........................................ 1023
22-25. Receiver Emulation Data Buffer (SCIED) Field Descriptions ...................................................... 1023
22-26. Receiver Data Buffer (SCIRD) Field Descriptions .................................................................. 1024
22-27. Transmit Data Buffer Register (SCITD) Field Descriptions ........................................................ 1025
22-28. SCI Pin I/O Control Register 0 (SCIPIO0) Field Descriptions ..................................................... 1025
22-29. SCI Pin I/O Control Register 1 (SCIPIO1) Field Descriptions ..................................................... 1026
22-30. LINTX Pin Control ....................................................................................................... 1026
22-31. LINRX Pin Control ....................................................................................................... 1026
22-32. SCI Pin I/O Control Register 2 (SCIPIO2) Field Descriptions ..................................................... 1027
22-33. SCI Pin I/O Control Register 3 (SCIPIO3) Field Descriptions ..................................................... 1028
22-34. SCI Pin I/O Control Register 4 (SCIPIO4) Field Descriptions ..................................................... 1029
22-35. SCI Pin I/O Control Register 5 (SCIPIO5) Field Descriptions ..................................................... 1030
22-36. SCI Pin I/O Control Register 6 (SCIPIO6) Field Descriptions ..................................................... 1031
22-37. SCI Pin I/O Control Register 7 (SCIPIO7) Field Descriptions ..................................................... 1032
22-38. SCI Pin I/O Control Register 8 (SCIPIO8) Field Descriptions ..................................................... 1032
22-39. LIN Compare Register (LINCOMPARE) Field Descriptions ....................................................... 1033
22-40. LIN Receive Buffer 0 Register (LINRD0) Field Descriptions ...................................................... 1034
22-41. LIN Receive Buffer 1 Register (RD1) Field Descriptions........................................................... 1034
22-42. LIN Mask Register (LINMASK) Field Descriptions .................................................................. 1035
22-43. LIN Identification Register (LINID) Field Descriptions .............................................................. 1036
22-44. LIN Transmit Buffer 0 Register (LINTD0) Field Descriptions ...................................................... 1037
22-45. LIN Transmit Buffer 1 Register (LINTD1) Field Descriptions ...................................................... 1037
22-46. Maximum Baud Rate Selection Register (MBRS) Field Descriptions ............................................ 1038
22-47. Input/Output Error Enable Register (IODFTCTRL) Field Descriptions ........................................... 1039
22-48. Input Buffer, Output Buffer, and Pull Control Behavior as GPIO Pins ........................................... 1042

54

23-1.

ESM Signals Set by eFuse Controller ................................................................................ 104423-2.

eFuse Controller Registers............................................................................................. 1047

23-3.

EFC Boundary Register (EFCBOUND) Field Descriptions ....................................................... 1047

23-4.

EFC Pins Register (EFCPINS) Field Descriptions .................................................................. 1049

23-5.

EFC Error Status Register (EFCERRSTAT) Field Descriptions .................................................. 1050

23-6.

EFC Self Test Cycles Register (EFCSTCY) Field Descriptions .................................................. 1050

23-7.

EFC Self Test Cycles Register (EFCSTSIG) Field Descriptions .................................................. 1051

List of Tables

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Preface
SPNU517C – March 2018

Read This First
About This ManualThis Technical Reference Manual (TRM) details the integration, the environment, the functionaldescription, and the programming models for each peripheral and subsystem in the device.
The TRM should not be considered a substitute for the data manual, rather a companion guide that should
be used alongside the device-specific data manual to understand the details to program the device. The
primary purpose of the TRM is to abstract the programming details of the device from the data manual.
This allows the data manual to outline the high-level features of the device without unnecessary
information about register descriptions or programming models.

Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers may be shown with the suffix h or the prefix 0x. For example, the following
number is 40 hexadecimal (decimal 64): 40h or 0x40.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties with default reset value below. A legend explains the notation used for theproperties.
– Reserved bits in a register figure can have one of multiple meanings:• Not implemented on the device• Reserved for future device expansion• Reserved for TI testing• Reserved configurations of the device that are not supported– Writing nondefault values to the Reserved bits could cause unexpected behavior and should be
avoided.

Glossary
TI Glossary — This glossary lists and explains terms, acronyms, and definitions.

Related Documentation From Texas Instruments
For product information, visit the Texas Instruments website at http://www.ti.com.
SPNA163— Initialization of the TMS570LS043x, TMS570LS033x and RM42L432 Hercules ARM CortexR4 Microcontrollers Application Report. Provides a brief overview and initialization procedure of the
TMS570LS043x, TMS570LS033x, and RM42L432 series of microcontrollers in the Hercules family.
SPNS186—

TMS570LS04x/03x 16- and 32-BIT RISC Flash Microcontroller Data Manual.

SPNU552— Safety Manual for TMS570LS04x/03x Hercules™ ARM® Safety Critical Microcontrollers
User's Guide. A safety manual for the Texas Instruments Hercules safety critical microcontroller
product family. The product family utilizes a common safety architecture that is implemented in
multiple application focused products.

SPNU517C – March 2018
Submit Documentation Feedback

Read This First
Copyright © 2018, Texas Instruments Incorporated

55

www.ti.com

Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by therespective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community— TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore
ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki— Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster innovationand growth of general knowledge about the hardware and software surrounding these devices.

Trademarks
Hercules, E2E are trademarks of Texas Instruments.
Cortex, CoreSight are trademarks of ARM Limited.
ARM, Cortex are registered trademarks of ARM Limited.

56

Read This FirstSPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Chapter 1
SPNU517C – March 2018

Introduction
Topic

1.1
1.2
1.3

...........................................................................................................................

Page

Designed for Safety Applications ......................................................................... 58
Family Description ............................................................................................. 58
Endianism Considerations .................................................................................. 61

SPNU517C – March 2018
Submit Documentation Feedback

Introduction
Copyright © 2018, Texas Instruments Incorporated

57

Designed for Safety Applications

1.1

www.ti.com

Designed for Safety Applications
The TMS570LS04x/03x device architecture has been designed from the ground up to simplify
development of functionally safe systems. The basic architectural concept is known as a safe island
approach. Power, clock, reset, and basic processing function are protected to a high level of diagnostic
coverage in hardware. Some of the key features of the safe island region are:
• A dual core lockstep processing solution built around ARM® Cortex®-R4 CPU that detects failures atthe core boundary on a cycle by cycle basis. Special measures in processor layout, clock distribution,
power distribution, reset distribution, and temporal diversity are all implemented to mitigate common
cause failures of the logical CPU and its checker. For complete details on the ARM® Cortex®-R4 CPU,
refer to the ARM® Cortex®-R4 Technical Reference Manual.
• Hardware BIST controllers which provide an extremely high level of diagnostic coverage for thelockstep CPUs and SRAMs in the system, while executing faster and consuming less memory thanequivalent software-based self-test solutions• ECC on the SRAM and flash memories are tightly coupled to the R4. The ECC controllers are locatedinside the CPU. This approach has two key advantages:– The interconnect between the CPU and the memory is also covered by the diagnostic– The ECC logic itself is checked on a cycle by cycle basis• Onboard voltage and reset monitoring logic• Onboard oscillator and PLL failure detection logic including a backup RC oscillator that can be utilized
upon failure
The TMS570LS04x/03x device architecture also includes many features to simplify diagnostics ofremaining logic such as:• Continuous parity diagnostics on all peripheral memories• Analog and digital loopback to test for shorts on I/O• HW self-test and diagnostics on the ADC module to check integrity of both analog inputs and the ADC
core conversion function• A hardware engine for the background calculation of CRC signatures during data transfers• A centralized error reporting function including a status output pin to enable external monitoring of thedevice status

1.2

Family Description
The TMS570LS04x/03x integrates the ARM® Cortex®-R4 CPU that offers an efficient 1.66 DMIPS/MHzand has configurations that can run up to 80MHz providing up to 132 DMIPS. The device supports the bigendian [BE32] format.
The TMS570LS04x/03x has up to 384KB integrated Flash and up to 32KB data RAM with single-bit error
correction and double bit error detection. The flash memory on this device is a nonvolatile, electricallyerasable and programmable memory implemented with a 64-bit-wide data bus interface. The flash
operates on a 3.3V supply input (same level as I/O supply) for all read, program and erase operations.
When in pipeline mode, the flash operates with a system clock frequency of up to 80MHz. The SRAM
supports single-cycle read/write accesses in byte, halfword, and word modes.
The TMS570LS04x/03x device features peripherals for real-time control-based applications, including two
Next Generation High End Timer (N2HET) timing coprocessors with up to 19 total IO terminals and a 12bit A to D converter supporting up to 16 inputs.
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs,
capture or compare inputs, or general-purpose I/O. It is especially well suited for applications requiring
multiple sensor information and drive actuators with complex and accurate time pulses. A High End Timer
Transfer Unit (HET-TU) can perform DMA type transactions to transfer N2HET data to or from main
memory. A Memory Protection Unit (MPU) is built into the HET-TU.

58

Introduction

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Family Description

www.ti.com

The enhanced quadrature encoder pulse (eQEP) module is used for direct interface with a linear or rotaryincremental encoder to get position, direction, and speed information from a rotating machine as used inhigh-performance motion and position-control systems.
The device has a 12-bit-resolution MibADC with 16 total channels and 64 words of parity protected buffer
RAM. The MibADC channels can be converted individually or can be grouped by software for sequential
conversion sequences. There are three separate groupings. Each sequence can be converted once when
triggered or configured for continuous conversion mode.
The device has multiple communication interfaces: one MibSPI, two SPIs, one LIN/SCI, and two DCANs.
The SPI provides a convenient method of serial interaction for high-speed communications between
similar shift-register type devices. The LIN/SCI supports the Local Interconnect standard 2.0 and can beused as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN
supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that
efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per
second (Mbps). The DCAN is ideal for applications operating in noisy and harsh environments (forexample, automotive and industrial fields) that require reliable serial communication or multiplexed wiring.
The frequency-modulated phase-locked loop (FMPLL) clock module is used to multiply the externalfrequency reference to a higher frequency for internal use. The FMPLL provides one of the seven possible
clock source inputs to the global clock module (GCM). The GCM module manages the mapping between
the available clock sources and the device clock domains.
The device also has an external clock prescaler (ECP) module that, when enabled, outputs a continuous
external clock on the ECLK pin. The ECLK frequency is a user-programmable ratio of the peripheral
interface clock (VCLK) frequency or oscillator (OSCIN). This low frequency output can be monitored
externally as an indicator of the device operating frequency.
The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt orexternal Error pin/ball is triggered when a fault is detected. The nERROR can be monitored externally as
an indicator of a fault condition in the microcontroller.
The device supports all the built-in ARM® Cortex®-R4 CoreSight™ debug features.
With integrated safety features and a wide choice of communication and control peripherals, theTMS570LS04x/03x is an ideal solution for real time control applications with safety critical requirements.

SPNU517C – March 2018
Submit Documentation Feedback

Introduction
Copyright © 2018, Texas Instruments Incorporated

59

Family Description

www.ti.com

Figure 1-1. Block Diagram

DAP

AJSM

CCM-R4

FLTP1
FLTP2

Debug
Gasket

N2HET

Flash
384KB

VCCP

with
ICEPick

128 Words
with Parity

Cortex-R4
with MPU
Cortex-R4
8 regionswith ECC

with MPU
8 regionsRAM
32KB
with ECCnRSTnPORRST
TEST
ECLK

GIO

GIOA[7:0]/INT[7:0]

LIN

LINRX
LINTX

LBIST

MiBSPI1
8 Transfer
Groups128 Bufferswith Parity

BRIDGEOSCIN
OSCOUT
Kelvin_GND
VCCPLLVSSPLL

16KB

CRC

R4

Flash for
EEPROM
w/ECC

2 Channel

Slave I/FSPI2SIMOSPI2SOMISPI2CLK
SPI2nCS[0]SPI3SPI3SIMOSPI3SOMISPI3CLK
SPI3nCS[3:0]SPI3nENA

OSC
PLL
Clock
MonitorDCC

CAN1RXCAN1TX

RTI

16 Messages
with Parity

CAN2RXCAN2TX

VIM

MiBADC

96 Channel
with Parity

64 Words
with Parity

ADIN[21, 20, 17, 16, 11:0]
ADEVT
VCCAD / ADREFHIVSSAD / ADREFLO

eQEP

eQEPA
eQEPB
eQEPS
eQEPI

IOMM

32 Messages
with Parity

DCAN2

ESM

nERRORDCAN1

PCR

MIBSPI1SIMOMIBSPI1SOMIMIBSPI1CLKMIBSPI1nCS[3:0]
MIBSPI1nENA

SPI2

SCR
Peripheral
BridgeN2HET[31:28, 26, 24:22, 20:16,
14, 12, 10, 8, 6, 4, 2, 0]

SYS

STC

HTU
2 Regions
8 DCP
with MPU

nTRST
TMS
TCK
RTCK
TDI
TDO

60

Introduction

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Endianism Considerations

www.ti.com

1.3

Endianism Considerations

1.3.1 Big Endian (BE32)
The TMS570 family is based on the ARM® Cortex®-R4 core. ARM has designed this core to be used in
big-endian and little-endian systems. For the TI TMS570 family, the endianness has been configured toBE32. Big-endian systems store the most-significant byte of a multi-byte data field in the lowest memory
address. Also, the address of the multi-byte data field is the lowest address. Below is an example of thephysical addresses of individual bytes.
Figure 1-2. Example: SPIDELAY – FFF7 F448h
31

24

23

16

C2TDELAY[7:0]

T2CDELAY[7:0]

Byte 3 - FFF7 F448h

Byte 2 - FFF7 F449h

15

8

7

0

T2EDELAY[7:0]

C2EDELAY[7:0]

Byte 1 - FFF7 F44Ah

Byte 0 - FFF7 F44Bh

32-bit accesses to this register should use the lowest address, that is, 0xFFF7F448. Writing 0x11223344
to address 0xFFF7F448 shows the following when viewing the memory in 8-bit and 32-bit modes.

As such the headers provided as part of HALCoGen do take the endianness into account and provide
header structures that are agnostic to endianness. This is achieved by using C directives for the compiler
that make use of the compile options configured for the project by the user (__little_endian__ used in
Code Composer Studio codegen tools). This directive may need to be adapted for other compilers.
#ifdef __little_endian__char C2EDELAY:
char T2EDELAY:
char T2CDELAY:
char C2TDELAY:#else
char C2TDELAY:
char T2CDELAY:
char T2EDELAY:
char C2EDELAY
:

8U;
8U;
8U;
8U;

/**lt; 0xF448: CS to ENA/**lt; 0xF449: Transmit to ENA/**lt; 0xF44A: Transmit to CS/**lt; 0xF44B: CS to Transmit

*/
*/
*/
*/

8U;
8U;
8U;
8U;

/**lt; 0xF448: CS to Transmit/**lt; 0xF449: Transmit to CS/**lt; 0xF44A: Transmit to ENA/**lt; 0xF44B: CS to ENA

*/
*/
*/
*/

SPNU517C – March 2018
Submit Documentation Feedback

Introduction
Copyright © 2018, Texas Instruments Incorporated

61

Chapter 2
SPNU517C – March 2018

ArchitectureThis chapter consists of five sections. The first section describes specific aspects of the device
architecture. The second section describes the clocking structure of the microcontrollers. The third section
gives an overview of the device memory organization. The fourth section details exceptions on the device,and the last section describes the system and peripheral control registers of the microcontrollers.
Topic

2.1
2.2
2.3
2.4
2.5

62

...........................................................................................................................

Page

Introduction ...................................................................................................... 63
Memory Organization ......................................................................................... 66
Exceptions ........................................................................................................ 76
Clocks .............................................................................................................. 79
System and Peripheral Control Registers ............................................................. 86

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Introduction

www.ti.com

2.1

Introduction
The TMS570LS04x/03x family of microcontrollers is based on the Texas Instruments TMS570
Architecture. This chapter describes specific aspects of the architecture as applicable to the
TMS570LS04x/03x family of microcontrollers.

2.1.1 Architecture Block Diagram
The TMS570LS04x/03x microcontrollers are based on the TMS570 Platform architecture, which defines
the interconnect between the bus masters and the bus slaves.
Figure 2-1 shows a high-level architectural block diagram for the superset microcontroller.
Figure 2-1. Architectural Block Diagram
Flash
384MB
w/ ECCRAM
32KB
w/ ECC

Dual Cortex-R4
in LockStep

HTU1

VBUSM Switched Central Resource Controller(VBUSM SCR)

CRC

Flash
16KB
EEPROM Emulation
Flash Bank

ADC1

N2HET1

GIO

DCAN1

DCAN2

LIN

MibSPI1

SPI2

SPI3

eQEP

SPNU517C – March 2018
Submit Documentation Feedback

VBUSP: Peripheral Interface Bus

PCR: Peripheral Central Resource Controller

Architecture
Copyright © 2018, Texas Instruments Incorporated

63

Introduction

www.ti.com

2.1.2 Definitions of Terms
Table 2-1 provides a definition of terms used in the architectural block diagram.
Table 2-1. Definition of Terms

64

Acronym /TermFull Form

Description

ADCx

Analog-to-Digital Converter

The ADC uses the Successive Approximation Register architecture. It features aselectable 10-bit or 12-bit resolution. The ADC module also includes a RAM to
hold the conversion results. A digital logic wrapper manages accesses to thecontrol and status registers. There is one ADC module on this device.

CRC

Cyclic Redundancy Checker

The CRC module provides two channels to perform background signature
verification on any memory region. It also supports maximum-length Parallel
Signature Analysis (PDS) based on a 64-bit primitive polynomial. The CRC
module is a bus slave in this device.

DAP

Debug Access PortThe DAP allows a tool such as a debugger to read from or write to any region in
the device memory-map. The DAP is a bus master in this device.

DCANx

Controller Area Network
controller

The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time
control with robust communication rates of up to 1 megabit per second (Mbps).
The DCAN is ideal for applications operating in noisy and harsh environments(for example, automotive and industrial fields) that require reliable serial
communication or multiplexed wiring.

eFuse

Electronically Programmable
Fuse controller

Electrically programmable fuses (eFuses) are used to configure the device after
deassertion of PORRST. The eFuse values are read and loaded into internalregisters as part of the power-on-reset sequence. The eFuse values areprotected with Single-Bit Error Correction Double-Bit Error Detection (SECDED)
codes. These fuses are programmed during the initial factory test of the device.
The eFuse controller is designed so that the state of the eFuses cannot bechanged once the device is packaged.

eQEP

Enhanced Quadrature
Encoder Pulse Module

The enhanced quadrature encoder pulse (eQEP) module is used for directinterface with a linear or rotary incremental encoder to get position, direction,and speed information from a rotating machine for use in a high-performance
motion and position-control system.

ECC

Error Correction CodeThis is a code that is used by the Single-Bit Error Correction Double-Bit Error
Detection (SECDED) logic inside the two Cortex-R4 processors (CPUs). There
are 8 bits of ECC for every 64 bits of data accessed from the CPU tightlycoupled memories (flash and RAM).

EEPROM
Emulation FlashBank

Emulated Electrically
Erasable Programmable
Read-Only Memory

This is a flash bank that is dedicated for use as an emulated EEPROM. This
device supports 16KB of flash for emulated EEPROM.

GIO

General-purpose Input/Output The GIO module allows up to 16 terminals to be used as general-purpose Input
or Output. Each of these are also capable of generating an interrupt to the CPU.

HTUx

High-End Timer Transfer Unit

The HTU is a dedicated transfer unit for the New Enhanced High-End Timermodule. The HTU has a native interface to the N2HET RAM, and is used totransfer data to / from the N2HET RAM from / to another region in the device
memory-map. There is one HTU and one N2HET module on the device. The
HTUx are bus masters in this device.

LIN

Local Interconnect Network
controller

The LIN module supports the Local Interconnect standard revision 2.1 and canbe used as a UART in full-duplex mode using the standard Non-Return-to-Zero(NRZ) format.

Lockstep–

This is the mode of operation of the dual ARM Cortex-R4 CPUs. The outputs ofthe two CPUs are compared on each CPU clock cycle. Any miscompare is
flagged as an error of the highest severity level.

MibSPIx

Multi-Buffered Serial
Peripheral Interface

The MibSPIx modules also support the standard SPI communication protocol.
The transfers are all grouped into transfer chunks called “transfer groups”. Thesetransfer groups are made up of one ore more buffers in the MibSPIx RAM. The
RAM is used to hold the control information and data to be transmitted, as wellas the status information and data that is received. There is one MibSPI modulein this device.

N2HETxNew Enhanced High-End
Timer

The N2HET is an advanced intelligent timer that provides sophisticated timing
functions for real-time applications. The timer is software-controlled, using a
reduced instruction set, with a specialized timer micromachine and an attached
I/O port. The N2HET can be used for pulse width modulated outputs, capture orcompare inputs, or general-purpose I/O.

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Introduction

www.ti.com

Table 2-1. Definition of Terms (continued)
Acronym /TermFull Form

Description

PCR

Peripheral Central Resource
controller

The PCR manages the accesses to the peripheral registers and peripheral
memories. It provides a global reset for all the peripherals. It also supports thecapability to selectively enable or disable the clock for each peripheral
individually. The PCR also manages the accesses to the system module
registers required to configure the device’s clocks, interrupts, and so on. The
system module registers also include status flags for indicating exception
conditions – resets, aborts, errors, interrupts.

SPIx

Serial Peripheral Interface

The SPIx modules provide a clocked serial communication interface for reliablecommunication between the device and other serial devices with the standard
SPI interface. There are two SPI modules on this device.

VBUSM SCR

VBUSM Switched Central
Resource controller

This is the main device SCR. It arbitrates between the accesses from multiple
bus masters to the bus slaves using a round robin priority scheme.

2.1.3 Bus Master / Slave Access PrivilegesThis device implements some restrictions on the bus slave access privileges in order to improve theoverall throughput of the interconnect shown in Figure 2-1.
Table 2-2. Bus Master / Slave Access Privileges
Bus Slaves Being Accessed
Masters

Master ID

Access Mode

EEPROM Bank, ECC
Bits, OTP Regions

Non-CPU Accesses to
CPU Flash and RAM

CRC
ModulePCR
Modules

CPU Read0

User/Privilege

AllowedAllowedAllowedAllowedCPU Write

1

User/Privilege

Not allowed

AllowedAllowedAllowed

HTU

6

Privilege

Not allowed

AllowedAllowedAllowedSPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

65

Memory Organization

2.2

www.ti.com

Memory Organization

2.2.1 Memory-Map Overview
The Cortex-R4 uses a 32-bit address bus, giving it access to a memory space of 4GB. This space isdivided into several regions, each addressed by different memory selects. Figure 2-2 shows the superset
memory-map of the microcontroller.
The main flash instruction memory is addressed starting at 0x00000000 by default. This is also the reset
vector location – the ARM Cortex-R4 processor core starts execution from the reset vector address of
0x00000000 whenever the core gets reset.
The CPU data RAM is addressed starting at 0x08000000 by default.
The device also supports the swapping of the CPU instruction memory (flash) and data memory (RAM).
This can be done by configuring the MEM SWAP field of the Bus Matrix Module Control Register 1(BMMCR1).
After swapping, the data RAM is accessed starting from 0x00000000 and the RAM ECC locations areaccessed starting from 0x00400000. The flash memory is now accessed starting from 0x08000000.
Figure 2-2. Memory-Map
0xFFFFFFFF
SYSTEM Modules
0xFFF80000
0xFFF7FFFF
0xFF000000
0xFE000000

Peripherals - Frame 1
CRC
RESERVED

0xFCFFFFFF
0xFC000000

Peripherals - Frame 2
RESERVED

0xF07FFFFF
Flash Module Bus2 Interface(Flash ECC, OTP andEEPROM accesses)
0xF0000000
RESERVED

0x2005FFFF

Flash (384KB) (Mirrored Image)0x20000000
RESERVED
0x08407FFF
0x08400000

RAM - ECCRESERVED

0x08007FFF
RAM (32KB)
0x08000000
RESERVED
0x0005FFFF

Flash (384KB)

0x00000000
66

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Memory Organization

www.ti.com

2.2.2 Memory-Map Table
The control and status registers for each module are mapped within the CPU’s 4GB memory space. Somemodules also have associated memories, which are also mapped within this space.
Table 2-3 shows the starting and ending addresses of each module’s register frame and any associatedmemory. The table also shows the response generated by the module or the interconnect whenever anaccess is made to an unimplemented location inside the register or memory frame.
Table 2-3. Module Registers / Memories Memory-Map
Frame Address

Frame
Size

ActualSize

0x00FF_FFFF

16MB

384KB

0x0800_0000

0x0BFF_3FFF

64MB

32KB

0x2000_0000

0x20FF_FFFF

16MB

384KB

Name

Memory SelectTCM FlashCS00x0000_0000

TCM RAM + RAM
ECC

CSRAM0Mirrored FlashFlash mirror frame

Start

End

Response for Access to
Unimplemented
Location in Frame

CPU Tightly-Coupled Memories

Abort

Flash Bus2 Interface: OTP, ECC, EEPROM Bank
Customer OTP, TCM
Flash Bank

0xF000_0000

0xF000_FFFF

64KB

2KB

Customer OTP,
EEPROM Bank

0xF000_E000

0xF000_FFFF

8KB

1KB

Customer OTP–ECC,TCM Flash Bank

0xF004_0000

0xF004_03FF

1KB

512B

Customer OTP–ECC,
EEPROM Bank

0xF004_1C00

0xF004_1FFF

1KB

128B

TI OTP, TCM FlashBank

0xF008_0000

0xF008_FFFF

64KB

2KB

TI OTP, EEPROM
Bank

0xF008_E000

0xF008_FFFF

8KB

1KB

TI OTP–ECC, TCM
Flash Bank

0xF00C_0000

0xF00C_03FF

8KB

512B

TI OTP–ECC,
EEPROM Bank

0xF00C_1C00

0xF00C_1FFF

1KB

128B

EEPROM Bank–ECC

0xF010_0000

0xF013_FFFF

256KB

2KB

EEPROM Bank

0xF020_0000

0xF03F_FFFF

2MB

16KB

Flash Data SpaceECC

0xF040_0000

0xF04F_FFFF

1MB

48KB

Abort

Cyclic Redundancy Checker (CRC) Module Register Frame
CRC

CRC frame

0xFE00_0000

0xFEFF_FFFF

16MB

512B

Accesses above 0x200
generate an Abort.

128KB

2KB

Abort for accesses above
2KB

2KB

Wrap around foraccesses to
unimplemented addressoffsets lower than 0x7FF.
Abort generated foraccesses beyond offset
0x800.

2KB

Wrap around foraccesses to
unimplemented addressoffsets lower than 0x7FF.
Abort generated foraccesses beyond offset
0x800.

Peripheral Memories
MIBSPI1 RAM

DCAN2 RAM

DCAN1 RAM

PCS[7]

PCS[14]PCS[15]0xFF0E_0000

0xFF1C_0000

0xFF1E_0000

0xFF0F_FFFF

0xFF1D_FFFF

0xFF1F_FFFFSPNU517C – March 2018
Submit Documentation Feedback

128KB

128KB

Architecture
Copyright © 2018, Texas Instruments Incorporated

67

Memory Organization

www.ti.com

Table 2-3. Module Registers / Memories Memory-Map (continued)
Frame Address
Name

Memory Select

Start

End

Frame
Size

MIBADC RAM

PCS[31]

0xFF3E_0000

0xFF3F_FFFF

ActualSize

Response for Access to
Unimplemented
Location in Frame

8KB

Wrap around foraccesses to
unimplemented addressoffsets lower than
0x1FFF.

384B

Look-up table for ADC
wrapper. Starts at offset
0x2000 and ends at
0x217F. Wrap around foraccesses between offsets
0x180 and 0x3FFF.
Aborts generated foraccesses beyond 0x4000.

128KB

MIBADC Look-Up
Table

N2HET RAM

PCS[35]

0xFF46_0000

0xFF47_FFFF

128KB

16KB

Wrap around foraccesses to
unimplemented addressoffsets lower than
0x3FFF. Abort generated
for accesses beyond
0x3FFF.

HET TU RAM

PCS[39]0xFF4E_0000

0xFF4F_FFFF

128KB

1KB

Abort

Debug Components
CoreSight Debug
ROM

CSCS0

0xFFA0_0000

0xFFA0_0FFF

4KB

4KB

Reads return zeros,
writes have no effectCortex-R4 Debug

CSCS1

0xFFA0_1000

0xFFA0_1FFF

4KB

4KB

Reads return zeros,
writes have no effect

Peripheral Control Registers

68

HTU

PS[22]

0xFFF7_A400

0xFFF7_A4FF

256B

256B

Reads return zeros,
writes have no effect

N2HET

PS[17]

0xFFF7_B800

0xFFF7_B8FF

256B

256B

Reads return zeros,
writes have no effect

GIO

PS[16]

0xFFF7_BC00

0xFFF7_BCFF

256B

256B

Reads return zeros,
writes have no effect

MIBADC

PS[15]

0xFFF7_C000

0xFFF7_C1FF

512B

512B

Reads return zeros,
writes have no effect

DCAN1

PS[8]

0xFFF7_DC00

0xFFF7_DDFF

512B

512B

Reads return zeros,
writes have no effect

DCAN2

PS[8]

0xFFF7_DE00

0xFFF7_DFFF

512B

512B

Reads return zeros,
writes have no effect

LIN

PS[6]

0xFFF7_E400

0xFFF7_E4FF

256B

256B

Reads return zeros,
writes have no effectMibSPI1

PS[2]0xFFF7_F400

0xFFF7_F5FF

512B

512B

Reads return zeros,
writes have no effect

SPI2

PS[2]

0xFFF7_F600

0xFFF7_F7FF

512B

512B

Reads return zeros,
writes have no effect

SPI3

PS[1]

0xFFF7_F800

0xFFF7_F9FF

512B

512B

Reads return zeros,
writes have no effect

EQEP

PS[25]

0xFFF7_9900

0xFFF7_99FF

256B

256B

Reads return zeros,
writes have no effect

EQEP (Mirrored)

PS2[25]0xFCF7_9900

0xFCF7_99FF

256B

256B

Reads return zeros,
writes have no effectArchitecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Memory Organization

www.ti.com

Table 2-3. Module Registers / Memories Memory-Map (continued)
Frame Address
Name

Memory Select

Start

End

Frame
Size

ActualSize

Response for Access to
Unimplemented
Location in Frame

System Modules Control Registers and Memories

VIM RAMPPCS2

0xFFF8_2000

0xFFF8_2FFF

4KB

1KB

Wrap around foraccesses to
unimplemented addressoffsets lower than 0x3FF.
Accesses beyond 0x3FF
will be ignored.

Flash Wrapper

PPCS7

0xFFF8_7000

0xFFF8_7FFF

4KB

4KB

Abort

eFuse FarmController

PPCS120xFFF8_C000

0xFFF8_CFFF

4KB

4KB

Abort

PCR registers

PPS0

0xFFFF_E000

0xFFFF_E0FF

256B

256B

Reads return zeros,
writes have no effect

System Module Frame 2

PPS0

0xFFFF_E100

0xFFFF_E1FF

256B

256B

Reads return zeros,
writes have no effect

PBIST

PPS1

0xFFFF_E400

0xFFFF_E5FF

512B

512B

Reads return zeros,
writes have no effect

STC

PPS1

0xFFFF_E600

0xFFFF_E6FF

256B

256B

Reads return zeros,
writes have no effect

IOMM Multiplexing
Control Module

PPS2

0xFFFF_EA00

0xFFFF_EBFF

512B

512B

Generates address error
interrupt, if enabled

DCC

PPS3

0xFFFF_EC00

0xFFFF_ECFF

256B

256B

Reads return zeros,
writes have no effect

ESM

PPS5

0xFFFF_F500

0xFFFF_F5FF

256B

256B

Reads return zeros,
writes have no effect

CCM-R4PPS5

0xFFFF_F600

0xFFFF_F6FF

256B

256B

Reads return zeros,
writes have no effect

RAM ECC even

PPS6

0xFFFF_F800

0xFFFF_F8FF

256B

256B

Reads return zeros,
writes have no effect

RAM ECC odd

PPS6

0xFFFF_F9000xFFFF_F9FF

256B

256B

Reads return zeros,
writes have no effect

RTI + DWWD

PPS7

0xFFFF_FC00

0xFFFF_FCFF

256B

256B

Reads return zeros,
writes have no effect

VIM Parity

PPS7

0xFFFF_FD00

0xFFFF_FDFF

256B

256B

Reads return zeros,
writes have no effect

VIM

PPS7

0xFFFF_FE00

0xFFFF_FEFF

256B

256B

Reads return zeros,
writes have no effect

System Module Frame 1

PPS7

0xFFFF_FF00

0xFFFF_FFFF

256B

256B

Reads return zeros,
writes have no effectSPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

69

Memory Organization

www.ti.com

2.2.3 Flash on Microcontrollers
The TMS570LS04x/03x microcontroller supports up to 384KB of flash for use as program memory. The
microcontrollers also support a separate 16KB flash bank for use as emulated EEPROM.
2.2.3.1

Flash Bank Sectoring Configuration

The bank is divided into multiple sectors. A flash sector is the smallest region in the flash bank that mustbe erased. The sectoring configuration of each flash bank is shown in Table 2-4.
Refer to the device datasheet for electrical and timing specifications related to the flash module.
Table 2-4. Flash Memory Banks and Sectors (1) (2) (3)Memory Arrays(or Banks)

BANK0 (384 KBytes)

BANK7 (16 KBytes) for
EEPROM emulation

(1)
(2)
(3)
(4)

70

Block No.

0

Sector No.

Segment

Low Address

High Address

0

8K Bytes

0x0000_0000

0x0000_1FFF

1

8K Bytes

0x0000_2000

0x0000_3FFF

2

8K Bytes

0x0000_4000

0x0000_5FFF

3

8K Bytes

0x0000_6000

0x0000_7FFF

4

8K Bytes

0x0000_8000

0x0000_9FFF

5

8K Bytes

0x0000_A000

0x0000_BFFF

6

8K Bytes

0x0000_C000

0x0000_DFFF

7

8K Bytes

0x0000_E000

0x0000_FFFF8

8K Bytes

0x0001_0000

0x0001_1FFF

9

8K Bytes

0x0001_2000

0x0001_3FFF

10

8K Bytes

0x0001_4000

0x0001_5FFF

11

8K Bytes

0x0001_6000

0x0001_7FFF

12

32K Bytes

0x0001_8000

0x0001_FFFF

1

13128K Bytes

0x0002_0000

0x0003_FFFF2

14 (4)

128K Bytes

0x0004_0000

0x0005_FFFF00

4K Bytes

0xF020_0000

0xF020_0FFF

1

1

4K Bytes

0xF020_1000

0xF020_1FFF

2

2

4K Bytes

0xF020_2000

0xF020_2FFF

3

3

4K Bytes

0xF020_3000

0xF020_3FFF

The Flash banks are 144-bit wide bank with ECC support.
The flash bank7 is a FLEE bank and can be programmed while executing code from flash bank0.
Code execution is not allowed from flash bank7.
Sector 14 is not accessible or included in the TMS570LS03x configuration.

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Memory Organization

www.ti.com

2.2.3.2

ECC Protection for Flash Accesses

The TMS570LS04x/03x microcontroller protects all accesses to the on-chip flash memory by dedicatedSingle-Bit Error Correction Double-Bit Error Detection (SECDED) logic.
The access to the program memory – flash bank 0, is protected by SECDED logic implemented inside the
ARM Cortex-R4 CPU. Accesses to the EEPROM emulation flash bank (bank 7) are protected bydedicated SECDED logic inside the digital interface to the flash banks.
Both the SECDED logic implementations use Error Correction Codes (ECC) for correcting single-bit errors
and for detecting multiple-bit errors in the values read from the flash arrays. There is an 8-bit ECC for
every 64 bits of data. The ECC for the flash memory contents needs to be calculated by an external toolsuch as nowECC. The ECC can then be programmed into the flash array along with the actual application
code.
The ECC for the flash array is stored in the flash itself, and is mapped to a region starting at 0xF0400000
for the main flash bank 0, and to a region starting at 0xF0100000 for the EEPROM emulation flash bank 7.
NOTE: ECC Protection Not Enabled By Default
The SECDED logic inside the CPU is not enabled by default and must be enabled by theapplication.

Example 2-1. Code Example for Enabling ECC Protection for Main Flash Accesses
MRC p15, #0, r1, c1, c0, #1
ORR r1, r1, #0x02000000
DMB
MCR p15, #0, r1, c1, c0, #1;Enable ECC checking for ATCM

The ECC protection for accesses to the EEPROM emulation flash bank can be enabled by writing Ah tothe EDACEN field of the flash module’s Error Correction Control Register 1 (FEDACCTRL1). See
Chapter 4 for more details.
When the CPU detects an ECC single-, or double-bit error on a read from the flash memory, it signals thison a dedicated “Event” bus. This event bus signaling is also not enabled by default and must be enabledby the application.
Example 2-2. Code Example for Enabling the CPU Event Signaling
MRC p15,#0,r1,c9,c12,#0
ORR r1, r1, #0x00000010
MCR p15,#0,r1,c9,c12,#0
MRC p15,#0,r1,c9,c12,#0;Enabling Event monitor states;Set 4th bit ('X') of PMNC register

The digital logic that interfaces the ARM Cortex-R4 CPU to the flash banks captures the ECC error events
signaled by the CPU, and in turn generates error signals that are input to the central Error Signaling
Module (ESM) provided ECC protection is enabled within the digital logic by writing Ah to the EDACEN
field of the flash module's Error Correction Control Register 1 (FEDACCTRL1).

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

71

Memory Organization

www.ti.com

2.2.4 On-Chip SRAM
Several SRAM modules are implemented on the device to support the functionality of the modules
included.
Reads from the CPU data RAM are protected by ECC calculated inside the CPU. Reads from all othermemories are protected by configurable odd or even parity that is evaluated in parallel with the actual
read.
The TMS570LS04x/03x microcontrollers are targeted towards safety-critical applications, and it is criticalfor any failures in the on-chip SRAM modules to be identified before these modules are used for safetycritical functions. These microcontrollers support a Programmable Built-In Self-Test (PBIST) mechanismthat is used to test each on-chip SRAM module for faults. The PBIST is usually run on device start-up as it
is a destructive test and all contents of the tested SRAM module are overwritten during the test.
The microcontrollers also support a hardware-based auto-initialization of on-chip SRAM modules. This
process also takes into account the read protection scheme implemented for each SRAM module – ECC
or parity.
TI recommends that the PBIST routines be executed on the SRAM modules prior to the auto-initialization.
The following section describe these two processes.
2.2.4.1

PBIST RAM Grouping and Algorithm Mapping For On-Chip SRAM Modules

Table 2-5 shows the groupings of the various on-chip memories for PBIST. It also lists the memory types
and their assigned RAM Group Select (RGS) and Return Data Select (RDS). See Chapter 6 for moredetails on the usage of the RGS and RDS information.
Table 2-6 maps the different algorithms supported in application mode for the RAM groups. The table also
lists the background pattern options available for each algorithm.
NOTE: Recommended Memory Test Algorithm
March13 is the recommended algorithm for the memory self-test.

For PBIST ROM_CLK = HCLK/2.
Table 2-5. PBIST Memory Grouping

72

MemoryRAM Group#

Memory Type

RGS

RDS

PBIST_ROM

1

ROM

1

0

STC_ROM

2

ROM

2

0

DCAN1

3

Dual-port

30 .. 5DCAN2

4Dual-port

40 .. 5ESRAM1

6

Single-port

60/1 .. 4

MIBSPI1

7

Dual-port

70 .. 30 .. 1VIM

10Dual-port

8

MIBADC

11

Dual-port

9

0

N2HET

13

Dual-port

11

0 .. 11

HET TU

14

Dual-port

120 .. 5

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Memory Organization

www.ti.com

Table 2-6. PBIST Algorithm Mapping

Sr. No.

ALGO
Register Value

Algorithm

Memories
Under Test

10x00000001

triple_read_slow_read

20x00000002

triple_read_fast_read

30x00000004

march13n

Dual-port

40x00000008

march13n50x00000010

6

Available
Background
Patterns

Valid RAM Groups

Valid RINFO
Register Value

ROM

1,2

0x00000003

ROM

1,2

0x00000003

0x00000000,
0x96699669,
0x0F0F0F0F,
0xAA55AA55,
0xC3C3C3C3

3,4,7,10,11,13,140x0000364C

Single-port

0x00000000,
0x96699669,
0x0F0F0F0F,
0xAA55AA55,
0xC3C3C3C36,29

0x10000020

down1A_red

Dual-port

0xFFFFFFFF,
0xAAAAAAAA

3,4,7,10,11,13,140x0000364C

0x00000020

down1A_red

Single-port

0xFFFFFFFF,
0xAAAAAAAA

6,290x10000020

70x00000040

mapcolumn

Dual-port

0xFFFFFFFF,
0x00000000

3,4,7,10,11,13,140x0000364C

80x00000080

mapcolumn

Single-port

0xFFFFFFFF,
0x00000000

6,29

0x10000020

90x00000100

precharge

Dual-port

0xFFFFFFFF,
0x00000000

3,4,7,10,11,13,140x0000364C

100x00000200

precharge

Single-port

0xFFFFFFFF,
0x00000000

6,29

0x10000020

110x00000400

dtxn2

Dual-port

0xFFFFFFFF,
0x00000000

3,4,7,10,11,13,140x0000364C

120x00000800

dtxn2

Single-port

0xFFFFFFFF,
0x00000000

6,29

0x10000020

130x00001000

pmos_open

Dual-port

0xFFFFFFFF,
0x00000000

3,4,7,10,11,13,140x0000364C

140x00002000

pmos_open

Single-port

0xFFFFFFFF,
0x00000000

6,29

0x10000020

150x00004000

pmos_open_slice1

Dual-port

0xFFFFFFFF,
0x00000000

100x00000200

160x00008000

pmos_open_slice2

Dual-port

0xFFFFFFFF,
0x00000000

100x00000200

170x00010000

flip10Dual-port

0xFFFFFFFF

3,4,7,10,11,13,140x0000364C

180x00020000

flip10Single-port

0xFFFFFFFF

6,29

0x10000020

190x00040000

iddq

Dual-port

0x00000000

3,4,7,10,11,13,140x0000364C

200x00080000

iddq

Single-port

0x00000000

60x00000020

210x00100000

retention

Dual-port

0x00000000

3,4,7,10,11,13,140x0000364C

22

0x00200000

retention

Single-port

0x00000000

60x00000020

23

0x00400000

iddq

Dual-port

0xFFFFFFFF

3,4,7,10,11,13,140x0000364C

24

0x00800000

iddq

Single-port

0xFFFFFFFF

6

0x00000020

25

0x01000000

retention

Dual-port

0xFFFFFFFF

3,4,7,10,11,13,140x0000364C

26

0x02000000

retention

Single-port

0xFFFFFFFF

6

0x00000020

27

0x04000000

iddqrowstripe

Dual-port

0x00000000

3,4,7,10,11,13,140x0000364C

28

0x08000000

iddqrowstripe

Single-port

0x00000000

60x00000020

290x10000000

iddqrowstripe

Dual-port

0xFFFFFFFF

3,4,7,10,11,13,140x0000364C

30

0x20000000

iddqrowstripe

Single-port

0xFFFFFFFF

6

0x00000020

31

0x40000000

powerup_invpowerup

Dual-port

0xAAAAAAAA

33,34,36,39,40,42,43

0x000006CB

320x80000000

powerup_invpowerup

Single-port

0xAAAAAAAA

520x00080000

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

73

Memory Organization

2.2.4.2

www.ti.com

Auto-Initialization of On-Chip SRAM Modules

The device system provides the capability to perform a hardware initialization on most memories on thesystem bus and on the peripheral bus.
The intent of having the hardware initialization is to program the memory arrays with error detection
capability to a known state based on their error detection scheme – odd/even parity or ECC. For example,
the contents of the CPU data RAM after power-on reset is unknown. A hardware auto-initialization can bestarted so that there is no ECC error.
NOTE: Effect of ECC or Parity on Memory Auto-Initialization
The ECC or parity should be enabled on the RAMs before hardware auto-initialization starts
if parity or ECC is being used.

Auto-Initialization Sequence:
1. Enable the global hardware memory initialization key by programming 0xA into MINITGCR[3:0], theMemory Initialization Key field (MINITGENA) of the Memory Hardware Initialization Global Control
Register (MINITGCR) register.
2. Select the module on which the memory hardware initialization has to be performed by programming
the appropriate value into the MSINENA(31–0) bits in the MSINENA register. See Table 2-7.
3. If the global auto-initialization scheme is enabled, the corresponding module will initialize its memories
based on its memory error checking scheme (even parity or odd parity or ECC).
4. When the memory initialization is complete, the module will signal “memory initialization done”, whichsets the corresponding bit in the system module MIDONE field of the MINISTAT register to indicate thecompletion of its memory initialization.
5. When the memory hardware initialization completes for all modules, (indicated by each module’s
MIDONE bit being set), the memory hardware initialization done bit (MINIDONE) is set in the
MSTCGSTAT register.
Figure 2-3. Hardware Memory Initialization Protocol
VCLK
Write to enable
MINTIGENA key
Write to enable
MSINENAn(where n = 31:0)
Poll MIDONEn field of
MINISTAT register(where n = 31:0)
Poll MINIDONE bit,
MSTCGSTAT[8]SYS_MMISTARTn(where n = 31:0)(from System module
to memory modules)

When each enabled module completes
its hardware initialization, thecorresponding MIIDONE bit is set.
After all enabled modules’ hardware initialization
completes, the MINIDONE bit is set, indicating
all hardware memory initialization is done.

Memorymodulehardwareinitialization

DEV_MMIDONEn(where n = 31:0)(from memory modules
to System module)

Black indicates System register activity.
Gray indicates inter-module activity, not accessible via System register.

74

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Memory Organization

www.ti.com

Table 2-7. Memory Initialization Select Mapping
Memory

(1)

(2)

(3)

Address Range(1) (2)MSINENA Register Bit #

Start

End

RAM

0x08000000

0x0800FFFF

0MIBSPI1 RAM

0xFF0E0000

0xFF0FFFFF

7 (3)

DCAN2 RAM

0xFF1C0000

0xFF1DFFFF

6

DCAN1 RAM

0xFF1E0000

0xFF1FFFFF

5

MIBADC RAM

0xFF3E0000

0xFF3FFFFF

8

N2HET RAM

0xFF460000

0xFF47FFFF

3

HET TU RAM

0xFF4E0000

0xFF4FFFFF

4

VIM RAM

0xFFF82000

0xFFF82FFF

2

If ECC protection is enabled for the CPU data RAM, then the auto-initialization process also initializes the corresponding ECC
space.
If parity protection is enabled for the peripheral SRAM modules, then the parity bits will also be initialized along with the SRAM
modules.
The MibSPI module performs an initialization of the transmit and receive RAMs as soon as the multi-buffered mode is enabled.
This is independent of whether the application has already initialized these RAMs using the auto-initialization method or not. The
MibSPI module need to be released from reset by writing 1 to the SPIGCR0 register before starting auto-initialization on its
RAMs.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

75

Exceptions

2.3

www.ti.com

Exceptions
An “Exception” is an event that makes the processor temporarily halt the normal flow of program
execution, for example, to service an interrupt from a peripheral. Before attempting to handle anexception, the processor preserves the critical parts of the current processor state so that the original
program can resume when the handler routine has finished.
The following sections describe three exceptions – Reset, Abort and the System Software Interrupts.
For complete details on all exceptions, refer to the ARM® Cortex®-R4 Technical Reference Manual.

2.3.1 Resets
The TMS570LS04x/03x microcontroller can be reset by either of the conditions described in Table 2-8.
Each reset condition is indicated in the System Exception Status Register (SYSESR).
The device nRST terminal is an I/O. It can be driven low by an external circuit to force a warm reset on the
microcontroller. This terminal will be driven low as an output for a minimum of 32 peripheral clock (VCLK)
cycles for any device system reset condition. As a result the EXTRST bit in the SYSESR register,
SYSESR[3], gets set for all reset conditions listed in Table 2-8. The nRST is driven low as an output for alonger duration during device power-up or whenever the power-on reset (nPORRST) is driven low
externally. Refer the device datasheet for the electrical and timing specifications for the nRST.
Table 2-8. Causes of Resets
Condition

Description

Driving nPORRST pin low
externally

Cold reset, or power-on reset. This reset signal is typically driven by an external voltage
supervisor. This reset is flagged by the PORST bit in the SYSESR register, SYSESR[15].

Voltage Monitor reset

The microcontroller has an embedded voltage monitor that generates a power-on reset when thecore voltage gets out of a valid range, or when the I/O voltage falls below a threshold. This resetis also flagged by the PORST bit in the SYSESR register, SYSESR[15].
Note: The voltage monitor is not an alternative for an external voltage supervisor.

Driving nRST pin low externally Warm reset. This reset input is typically used in a system with multiple ICs and which requiresthat the microcontroller also gets reset whenever the other IC detects a fault condition. This resetis flagged by the EXTRST bit in the SYSESR, register SYSESR[3].
Oscillator failureThis reset is generated by the system module when the clock monitor detects an oscillator failcondition. Whether or not a reset is generated is also dictated by a register in the system module.
This reset is flagged by the OSCRST bit in the SYSESR register, SYSESR[14].

Software reset

This reset is generated by the application software writing a 1 to bit 15 of System Exception
Control Register (SYSECR) or a 0 to bit 14 of SYSECR. It is typically used by a bootloader typeof code that uses a software reset to allow the code execution to branch to the application code
once it is programmed into the program memory. This reset is flagged by the SWRST bit in the
SYSESR register, SYSESR[4].

CPU reset

This reset is generated by the CPU self-test controller (LBIST) or by changing the memory
protection (MMU/MPU) configuration in the CPURSTCR register. This reset is flagged by the
CPURST bit in the SYSESR register, SYSESR[5].

Debug reset

The ICEPICK logic implemented on the microcontroller allows a system reset to be generated via
the debug logic. This reset is flagged by the WDRST bit in the SYSESR register, SYSESR[13].

Watchdog reset

This reset is generated by the digital windowed watchdog (DWWD) module on the microcontroller.
The DWWD can generate a reset whenever the watchdog service window is violated. This reset isflagged by the WDRST bit in the SYSESR register, SYSESR[13].

2.3.2 Aborts
When the ARM Cortex-R4 processor's memory system cannot complete a memory access successfully,
an abort is generated. An error occurring on an instruction fetch generates a prefetch abort. Errors
occurring on data accesses generate data aborts. Aborts are also categorized as being either precise or
imprecise.

76

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Exceptions

www.ti.com

2.3.2.1

Prefetch Aborts

When a Prefetch Abort (PABT) occurs, the processor marks the prefetched instruction as invalid, but does
not take the exception until the instruction is to be executed. If the instruction is not executed, for example
because a branch occurs while it is in the pipeline, the abort does not take place.
All prefetch aborts are precise aborts.
2.3.2.2

Data Aborts

An error occurring on a data memory access can generate a data abort. If the instruction generating thememory access is not executed, for example, because it fails its condition codes, or is interrupted, thedata abort does not take place.
A Data Abort (DABT) can be either precise or imprecise, depending on the type of fault that caused it.
2.3.2.3

Precise Aborts

A precise abort, also known as a synchronous abort, is one for which the exception is guaranteed to betaken on the instruction that generated the aborting memory access. The abort handler can use the value
in the Link Register (r14_abt) to determine which instruction generated the abort, and the value in the
Saved Program Status Register (SPSR_abt) to determine the state of the processor when the abort
occurred.
2.3.2.4

Imprecise Aborts

An imprecise abort, also known as an asynchronous abort, is one for which the exception is taken on alater instruction to the instruction that generated the aborting memory access. The abort handler cannot
determine which instruction generated the abort, or the state of the processor when the abort occurred.
Therefore, imprecise aborts are normally fatal.
Imprecise aborts can be generated by store instructions to normal-type or device-type memory. When thestore instruction is committed, the data is normally written into a buffer that holds the data until thememory system has sufficient bandwidth to perform the write access. This gives read accesses higher
priority. The write data can be held in the buffer for a long period, during which many other instructions
can complete. If an error occurs when the write is finally performed, this generates an imprecise abort.
The TMS570LS04x/03x microcontroller architecture applies techniques at the system level to mitigate theimpact of imprecise aborts. System level adoption of write status sidebands to the data path allow bus
masters to comprehend imprecise aborts, turning them into precise aborts. In cases where this approachis not feasible, buffering bridges or other sources of imprecision may build a FIFO of current transactions
such that an imprecise abort may be registered at the point of imprecision for later analysis.
Masking Of Imprecise Aborts:
The nature of imprecise aborts means that they can occur while the processor is handling a different
abort. If an imprecise abort generates a new exception in such a situation, the banked link register(R14_abt) and the Saved Processor Status Register (SPSR_abt) values are overwritten. If this occurs
before the data is pushed to the stack in memory, the state information about the first abort is lost. To
prevent this from happening, the Current Processor Status Register (CPSR) contains a mask bit toindicate that an imprecise abort cannot be accepted, the A-bit. When the A-bit is set, any imprecise abortthat occurs is held pending by the processor until the A-bit is cleared, when the exception is actuallytaken. The A-bit is automatically set when abort, IRQ or FIQ exceptions are taken, and on reset. The
application must only clear the A-bit in an abort handler after the state information has either been stacked
to memory, or is no longer required.
NOTE: Default Behavior for Imprecise Aborts
The A-bit in the CPSR is set by default. This means that no imprecise abort exception will
occur. The application must enable imprecise abort exception generation by clearing the Abit of the CPSR.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

77

Exceptions

2.3.2.5

www.ti.com

Conditions That Generate Aborts

An Abort is generated under the following conditions on the TMS570LS04x/03x microcontrollers.
• Access to an illegal address (a nonimplemented address)• Access to a protected address (protection violation)• Parity / ECC / Time-out Error on a valid access
Illegal Addresses:
The illegal addresses and the responses to an access to these addresses are defined in Table 2-3.
Addresses Protected By MPU:
Memory access permissions can be configured via the ARM Cortex-R4 processor’s Memory Protection
Unit (MPU). For more details on the MPU configuration, refer to the ARM® Cortex®-R4 Technical
Reference Manual.
A memory access violation is logged as a permission fault in the CPU’s fault status register and the virtual
address of the access is logged into the CPU’s fault address register.
Protection of Peripheral Register and Memory Frames:
Accesses to the peripheral register and memory frames can be protected either by configuring the MPU orby configuring the Peripheral Central Resource (PCR) controller registers.
The PCR module PPROTSETx registers contain one bit per peripheral select quadrant. These bits define
the access permissions to the peripheral register frames. If the CPU attempts to write to a peripheral
register for which it does not have the correct permissions, a protection violation is detected and an Abort
occurs.
Some modules also enforce register updates to only be allowed when the CPU is in a privileged mode ofoperation. If the CPU writes to these registers in user mode, the writes are ignored.
The PCR module PMPROTSETx registers contain one bit per peripheral memory frame. These bits define
the access permissions to the peripheral memory frames. If the CPU attempts to write to a peripheral
memory for which it does not have the correct permissions, a protection violation is detected and an Abort
occurs.
NOTE: No Access Protection for Reads
The PCR PPROTSETx and PMPROTSETx registers protect the peripheral registers andmemories against illegal writes by the CPU. The CPU can read from the peripheral registers
and memories in both user and privileged modes.

2.3.3 System Software Interrupts
The system module provides the capability of generating up to four software interrupts. A softwareinterrupt is generated by writing the correct key value to either of the four System Software Interrupt
Registers (SSIRx). The SSI registers also allow the application to provide a label for that softwareinterrupt. This label is an 8-bit value that can then be used by the interrupt service routine to perform therequired task based on the value provided. The source of the system software interrupt is reflected in thesystem software interrupt vector (SSIVEC) register.

78

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Clocks

www.ti.com

2.4

ClocksThis section describes the clocking structure of the TMS570LS04x/03x microcontrollers.

2.4.1 Clock Sources
The devices support up to 5 clock sources. These are listed in Table 2-9. The electrical specifications aswell as timing requirements for each of the clock sources are specified in the device datasheet.
Table 2-9. Clock Sources

2.4.1.1

Clock Source #Clock Source Name

0

OSCIN

Description
Main oscillator. This is the primary clock for the microcontroller and is the only
clock that is input to the phase-locked loops. The oscillator frequency must be
between 5 and 20 MHZ.

1

PLL1

This is the output of the main PLL. The PLL is capable of modulating its output
frequency in a controlled manner to reduce the radiated emissions.

2

Reserved

This clock source is not available and must not be enabled or used as source
for any clock domain.

3

EXTCLKIN

External clock input. A square wave input can be applied to this device input
and used as a clock source inside the device. Use of EXTCLKIN requires
selecting the EXTCLKIN pin function in the PINMMR2 register.

4

LF LPO(Low-Frequency LPO)
CLK80K

This is the low-frequency output of the internal reference oscillator. This is
typically an 80 KHz signal (CLK80K) that is used by the real-time interrupt
module for generating periodic interrupts to wake up from a low power mode.

5

HF LPO(High-Frequency LPO)
CLK10M

This is the high-frequency output of the internal reference oscillator. This is
typically a 10 MHZ signal (CLK10M) that is used by the clock monitor module
as a reference clock to monitor the main oscillator frequency.

6

Reserved

This clock source is not available and must not be enabled or used as source
for any clock domain.

7

Reserved

This clock source is not available and must not be enabled or used as source
for any clock domain.

Enabling / Disabling Clock Sources

Each clock source can be independently enabled or disabled using the set of Clock Source Disable
registers – CSDIS, CSDISSET and CSDISCLR.
Each bit in these registers corresponds to the clock source number indicated in Table 2-9. For example,
setting bit 1 in the CSDIS or CSDISSET registers disables the PLL.
NOTE: Disabling the Main Oscillator or HF LPO
By default, the clock monitoring circuit is enabled and checks for the main oscillator
frequency to be within a certain range using the HF LPO as a reference. If the main oscillator
and/or the HF LPO are disabled with the clock monitoring still enabled, the clock monitor will
indicate an oscillator fault. The clock monitoring must be disabled before disabling the main
oscillator or the HF LPO clock source(s).

The clock source is only disabled once there is no active clock domain that is using that clock source.
Also, see Chapter 9 for more information on enabling/disabling the oscillator and PLL.
On the TMS570LS04x/03x microcontrollers, the clock sources 0, 4, and 5 are enabled by default.
2.4.1.2

Checking for Valid Clock Sources

The application can check whether a clock source is valid or not by checking the corresponding bit to be
set in the Clock Source Valid Status (CSVSTAT) register. For example, the application can check if bit 1 in
CSVSTAT is set before using the output of PLL as the source for any clock domain.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

79

Clocks

www.ti.com

2.4.2 Clock Domains
The clocking on this device is divided into multiple clock domains for flexibility in control as well as clock
source selection. There are 7 clock domains on this device. Each of these are described in Table 2-10.
Each of the control registers listed in Table 2-10 are defined in Section 2.5. The AC timing characteristics
for each clock domain are specified in the device datasheet.
Table 2-10. Clock Domains

2.4.2.1

Clock
Domain #Clock
DomainDefault
SourceSourceSelection
Register

0

GCLK

OSCIN

GHVSRC••••

Always the same frequency as HCLKIn phase with HCLKIs disabled separately from HCLK via the CDDISx registers bit 0
Can be divided by 1 to 8 when running CPU self-test (LBIST) using
the CLKDIV field of the STCCLKDIV register

0

GCLK2

OSCIN

GHVSRC••••

Always the same frequency as GCLK
2 cycles delayed from GCLKIs disabled along with GCLK
Gets divided by the same divider setting as that for GCLK whenrunning CPU self-test (LBIST)

1

HCLK

OSCIN

GHVSRC• Is disabled via the CDDISx registers bit 1

2

VCLK

OSCIN

GHVSRC••••

Divided down from HCLKCan be HCLK/1 or HCLK/2
Is disabled separately from HCLK via the CDDISx register bit 2
Can be disabled separately for the eQEP module via the CDDISxregister bit 9.

3

VCLK2

OSCIN

GHVSRC••••

Divided down from HCLKCan be HCLK/1 or HCLK/2
Frequency must be an integer multiple of VCLK frequency
Is disabled separately from HCLK via the CDDISx registers bit 3

4

VCLKA1VCLK

VCLKASRC• Defaults to VCLK as the source• Frequency can be as fast as HCLK frequency• Is disabled via the CDDISx registers bit 4

6

RTICLKVCLK

RCLKSRC• Defaults to VCLK as the source• If a clock source other than VCLK is selected for RTICLK, then the
RTICLK frequency must be less than or equal to VCLK/3 . The
application can ensure this by programming the RTI1DIV field of
the RCLKSRC register, if necessary• Is disabled via the CDDISx registers bit 6

Special Considerations

Enabling / Disabling Clock Domains

Each clock domain can be independently enabled or disabled using the set of Clock Domain Disable
registers – CDDIS, CDDISSET, and CDDISCLR.
Each bit in these registers corresponds to the clock domain number indicated in Table 2-10. For example,
setting bit 1 in the CDDIS or CDDISSET registers disables the HCLK clock domain. The clock domain will
be turned off only when every module that uses the HCLK domain gives the “permission” for HCLK to beturned off.
All clock domains are enabled by default, or upon a system reset, or whenever a wake up condition isdetected.

80

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Clocks

www.ti.com

2.4.2.2

Mapping Clock Sources to Clock Domains

Each clock domain needs to be mapped to a valid clock source. There are control registers that allow anapplication to choose the clock sources for each clock domain.
• Selecting clock source for GCLK, HCLK and VCLKx domains
The CPU clock (GCLK), the system module clock (HCLK), and the peripheral bus clocks (VCLKx) all use
the same clock source. This clock source is selected via the GHVSRC register. The default source for the
GCLK, HCLK and VCLKx is the main oscillator. That is, after power up, the GCLK and HCLK are runningat the OSCIN frequency, while the VCLKx frequency is the OSCIN frequency divided by 2.
• Selecting clock source for the VCLKA1 domain
The clock source for the VCLKA1 domain is selected via the VCLKASRC register. The default source for
the VCLKA1 domain is the VCLK.
• Selecting clock source for RTICLK domain
The clock source for RTICLK domain is selected via the RCLKSRC register. The default source for the
RTICLK domain is the VCLK.
NOTE: Selecting a clock source for RTICLK that is not VCLKWhen the application chooses a clock source for RTICLK domain that is not VCLK, then theapplication must ensure that the resulting RTICLK frequency must be less than or equal to
VCLK frequency divided by 3. The application can configure the RTI1DIV field of the
RCLKSRC register for dividing the selected clock source frequency by 1, 2, 4 or 8 to meetthis requirement.

2.4.3 Low-Power Modes
All clock domains are active in the normal operating mode. This is the default mode of operation. As
described in Section 2.4.1.1 and Section 2.4.2.1, the application can choose to disable any particular clock
source and domain that it does not plan to use. Also, the peripheral central resource controller (PCR) has
control registers to enable / disable the peripheral clock (VCLK) for each peripheral select. This offers theapplication a large number of choices for enabling / disabling clock sources, or clock domains, or clocks to
specific peripherals.
This section describes three particular low-power modes and their typical characteristics. They are not the
only low-power modes configurable by the application, as just described.
Table 2-11. Typical Low-Power Modes
Suggested
Wake Up
Clock
Source(s)

Mode
Name

Active ClockSource(s)Active Clock
Domain(s)DozeMain oscillator

RTICLK

RTI interrupt,
GIO interrupt,
CAN message,
SCI message

Main oscillator

Flash pump sleep -> active transition time+
Flash bank sleep -> standby transition time+
Flash bank standby -> active transition time

SnoozeLF LPORTICLK

RTI interrupt,
GIO interrupt,
CAN message,
SCI message

HF LPOHF LPO warm start-up time+
Flash pump sleep -> active transition time+
Flash bank sleep -> standby transition time+
Flash bank standby -> active transition time

Sleep

None

None

GIO interrupt,
CAN message,
SCI message

HF LPOHF LPO warm start-up time+
Flash pump sleep -> active transition time+
Flash bank sleep -> standby transition time+
Flash bank standby -> active transition time

Wake Up OptionsSPNU517C – March 2018
Submit Documentation Feedback

Wake Up Time (wake up detected -toCPU code execution start)

Architecture
Copyright © 2018, Texas Instruments Incorporated

81

Clocks

www.ti.com

2.4.3.1 Typical Software Sequence to Enter a Low-Power Mode
1. Program the flash banks and flash pump fall-back modes to be “sleep”.
The flash pump transitions from active to sleep mode only after all the flash banks have switched from
active to sleep mode. The flash banks start switching from active to sleep mode only after the banks
are not accessed for at least a duration defined by the Active Grace Period (AGP) parameter
configured for the banks. See Chapter 4 for more details.
2. Disable the clock sources that are not required to be kept active.
A clock source does not get disabled until all clock domains using that clock source are disabled first,
or are configured to use an alternate clock source.
3. Disable the clock domains that are not required to be kept active.
A clock domain does not get disabled until all modules using that clock domain “give their permission”
for that clock domain to be turned off.
4. Idle the Cortex-R4 core.
The ARM Cortex-R4 CPU has internal power management logic, and requires a dedicated instruction
to be used in order to enter a low power mode. This is the Wait For Interrupt (WFI) instruction.
When a WFI instruction is executed, the Cortex-R4 core flushes its pipeline, flushes all write buffers,
and completes all pending bus transactions. At this time the core indicates to the system that the clock
to the core can be stopped. This indication is used by the Global Clock Module (GCM) to turn off the
CPU clock domain (GCLK) if the CDDIS register bit 0 is set.
2.4.3.2

Special Considerations for Entry to Low-Power Modes

The bus masters can have ongoing transactions when the application wants to enter a low-power mode toturn off the clocks to those modules. This is not recommended as it could leave the device in an
unpredictable state. See the individual module chapters for more information about the sequence to befollowed to safely enter a low-power mode.
2.4.3.3

Selecting Clock Source Upon Wake Up

The domains for CPU clock (GCLK), the system clock (HCLK) and the peripheral clock (VCLKx) use thesame clock source selected via the GHVSRC field of the GHVSRC register. The GHVSRC register also
allows the application to choose the clock source after wake up via the GHVWAKE field.
When a wake up condition is detected, if the selected wake up clock source is not already active, theglobal clock module (GCM) will enable this selected clock source, wait for it to become valid, and then use
it for the GCLK, HCLK and VCLKx domains. The other clock domains VCLKAx and RTICLK retain theconfiguration for their clock source selection registers – VCLKASRC, VCLKACON1 and RCLKSRC.

82

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Clocks

www.ti.com

2.4.4 Clock Test Mode
The TMS570LS04x/03x microcontrollers support a test mode which allows a user to bring out several
different clock sources and clock domains on to the ECLK terminal. This is very useful information fordebug purposes. Each clock source also has a corresponding clock source valid status flag in the ClockSource Valid Status (CSVSTAT) register. The clock source valid status flags can also be brought out on to
the N2HET[2] terminal in this clock test mode.
The clock test mode is controlled by the CLKTEST register (Section 2.5.1.32) in the system module
register frame.
The clock test mode is enabled by writing 0x5 to the CLK_TEST_EN field.
The signal to be brought out on to the ECLK terminal is defined by the SEL_ECP_PIN field and the signal
to be brought out on to the N2HET[2] terminal is defined by the SEL_N2HET_PIN field.
These selections are defined in Table 2-12.
Table 2-12. Clock Test Mode Options
SEL_ECP_PIN

Signal on ECLKSEL_N2HET_PIN

Signal on N2HET[2]0000Oscillator

0000

Oscillator Valid status

0001

PLL1 free-running clock
output (PLLCLK)

0001

PLL1 Valid status

0010

Reserved

0010

Reserved

0011

Reserved

0011

Reserved

0100

CLK80K

0100

Reserved

0101

CLK10M

0101

CLK10M Valid status

0110

Reserved

0110

Reserved

0111

Reserved

0111

Reserved

1000

GCLK

1000

CLK80K Valid status

1001

RTI Base

1001

Oscillator Valid status

1010

Reserved

1010

Oscillator Valid status

1011

VCLKA1

1011

Oscillator Valid status

1100

Reserved

1100

Oscillator Valid status

1101

Reserved

1101

Oscillator Valid status

1110

Reserved

1110

Oscillator Valid status

1111

Flash HD Pump Oscillator

1111

Oscillator Valid status

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

83

Clocks

www.ti.com

2.4.5 Safety Considerations for Clocks
The TMS570LS04x/03x microcontrollers are targeted for use in several safety-critical applications. The
following sections describe the internal or external monitoring mechanisms that detect and signal clock
source failures.
2.4.5.1

Oscillator Monitor

The oscillator clock frequency is monitored by a dedicated circuitry called CLKDET using the HF LPO as
the reference clock. The CLKDET flags an oscillator fail condition whenever the OSCIN frequency falls
outside of a range which is defined by the HF LPO frequency. Please refer to the device datasheet for
specific frequency values.
The valid OSCIN range is defined as a minimum of f(HF LPO) / 4 to a maximum of f(HF LPO) × 4.
The application can select the device response to an oscillator fail indication. See Chapter 9 for moredetails on the oscillator monitoring and the system response choices.
2.4.5.2

PLL Slip Detector

The PLL macro implemented on the microcontroller has an embedded slip detection circuit. A PLL slip is
detected by the slip detector under the following conditions:
1. Reference cycle slip, RFSLIP — the output clock is running too fast relative to the reference clock
2. Feedback cycle slip, FBSLIP — the output clock is running too slow relative to the reference clock
The device also includes optional filters that can be enabled before a slip indication from the PLL isactually logged in the system module Global Status Register (GLBSTAT). Also, once a PLL slip condition
is logged in the system module global status register, the application can choose the device’s response to
the slip indication. See Chapter 9 for more details on PLL slip and the system response choices.
2.4.5.3

External Clock Monitor

The microcontrollers support a terminal called ECLK – External Clock, which is used to output a slow
frequency which is divided down from the device system clock frequency. An external circuit can monitor
the ECLK frequency in order to check that the device is operating at the correct frequency.
The frequency of the signal output on the ECLK pin can be divided down by 1 to 65536 from theperipheral clock (VCLK) frequency using the External Clock Prescaler Control Register (ECPCNTL). The
actual clock output on ECLK is enabled by setting the ECP CLK FUN bit of the SYSPC1 control register.

84

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Clocks

www.ti.com

2.4.5.4

Dual-Clock Comparator

The microcontroller includes a dual-clock comparator module. This module includes two down counterswhich independently count from two separate seed values at the rate of two independent clock
frequencies. One of the clock inputs is a reference clock input, selectable between the main oscillator or
the HF LPO in functional mode. The second clock input is selectable from among a set of defined signals.
This mechanism can be used to use a known-good clock to measure the frequency of another clock.
The DCC module has two counters. Table 2-13 and Table 2-14 show the options for selecting the clock
sources for both counters on the DCC module.
CNT0 CLKSRC is a control field in the DCCCNT0CLKSRC register. KEY and CNT1 CLKSRC are control
fields in the DCCCNT1CLKSRC register.
As can be seen, the main oscillator (OSCIN) can be used for counter 0 as a “known-good” reference
clock. The clock for counter 1 can be selected from among 5 options. See Chapter 10 for more details on
the DCC usage.
Table 2-13. Clock Source Selection for DCC1 Counter0
CNT0 CLKSRC

Clock Name

Clock Description

5h

HF LPOAh

TCK

High-Frequency Output of Internal Low-Power Oscillator
Test ClockAll other values

OSCIN

Main oscillator input

Table 2-14. Clock Source Selection for DCC1 Counter1
KEY

CNT1 CLKSRC

Clock Name

Clock Description

Ah0

PLL Output

Output from PLL

1hReserved

Reserved2h

LF LPO

Low-Frequency output of internal Low-Power Oscillator

3h

HF LPO

High-Frequency output of internal Low-Power Oscillator

4h

Reserved

Reserved

5h

EXTCLKIN

External clock input source #1

6h

Reserved

Reserved

7h

Reserved

Reserved

All other values

8h–Fh

VCLK

Don’t care

N2HET[31]Peripheral bus clock
Signal output on the N2HET[31] signal by the N2HET module,
either by the N2HET program execution, or by the application
toggling the N2HET[31] pin as general-purpose output.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

85

System and Peripheral Control Registers

2.5

www.ti.com

System and Peripheral Control Registers
The following sections describe the system and peripheral control registers of the TMS570LS04x/03x
microcontroller.

2.5.1 Primary System Control Registers (SYS)
This section describes the SYSTEM registers. These registers are broken up into two separate frames.
The start address of the primary system module frame is FFFF FF00h. The start address of the secondary
system module frame is FFFF E100h. The registers support 32-, 16-, and 8-bit writes. The offset is relative
to the system module frame start address.
Table 2-15 contains a summary of the primary system control registers.
Table 2-15. Primary System Control Registers

86

OffsetAcronym

Register Description

00h

SYSPC1

SYS Pin Control Register 1

Section 2.5.1.1

Section04h

SYSPC2

SYS Pin Control Register 2

Section 2.5.1.2

08h

SYSPC3

SYS Pin Control Register 3

Section 2.5.1.3

0Ch

SYSPC4

SYS Pin Control Register 4

Section 2.5.1.4

10h

SYSPC5

SYS Pin Control Register 5

Section 2.5.1.5

14h

SYSPC6

SYS Pin Control Register 6

Section 2.5.1.6

18h

SYSPC7

SYS Pin Control Register 7

Section 2.5.1.7

1Ch

SYSPC8

SYS Pin Control Register 8

Section 2.5.1.8

20h

SYSPC9SYS Pin Control Register 9

Section 2.5.1.9

30h

CSDIS

Clock Source Disable Register

Section 2.5.1.10

34h

CSDISSET

Clock Source Disable Set Register

Section 2.5.1.11

38h

CSDISCLR

Clock Source Disable Clear Register

Section 2.5.1.12

3Ch

CDDIS

Clock Domain Disable Register

Section 2.5.1.13

40h

CDDISSET

Clock Domain Disable Set Register

Section 2.5.1.14

44h

CDDISCLR

Clock Domain Disable Clear Register

Section 2.5.1.15

48h

GHVSRC

GCLK, HCLK, VCLK, and VCLK2 Source Register

Section 2.5.1.16

4Ch

VCLKASRC

Peripheral Asynchronous Clock Source Register

Section 2.5.1.17

50h

RCLKSRC

RTI Clock Source Register

Section 2.5.1.18

54h

CSVSTATClock Source Valid Status Register

Section 2.5.1.19

58h

MSTGCR

Memory Self-Test Global Control Register

Section 2.5.1.20

5Ch

MINITGCR

Memory Hardware Initialization Global Control Register

Section 2.5.1.21

60h

MSINENA

Memory Self-Test/Initialization Enable Register

Section 2.5.1.22

64h

MSTFAIL

Memory Self-Test Fail Status Register

Section 2.5.1.23

68h

MSTCGSTATMSTC Global Status Register

Section 2.5.1.24

6Ch

MINISTAT

Memory Hardware Initialization Status Register

Section 2.5.1.25

70h

PLLCTL1

PLL Control Register 1

Section 2.5.1.26

74h

PLLCTL2

PLL Control Register 2

Section 2.5.1.27

78h

SYSPC10

SYS Pin Control Register 10

Section 2.5.1.28

7Ch

DIEIDLDie Identification Register, Lower Word

Section 2.5.1.29

80h

DIEIDHDie Identification Register, Upper Word

Section 2.5.1.30

88h

LPOMONCTL

LPO/Clock Monitor Control Register

Section 2.5.1.31

8Ch

CLKTEST

Clock Test Register

Section 2.5.1.32

90h

DFTCTRLREGDFT Control Register

Section 2.5.1.33

94h

DFTCTRLREG2DFT Control Register 2

Section 2.5.1.34

A0h

GPREG1

General Purpose Register

Section 2.5.1.35

A8h

IMPFASTS

Imprecise Fault Status Register

Section 2.5.1.36

ACh

IMPFTADD

Imprecise Fault Write Address Register

Section 2.5.1.37

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

Table 2-15. Primary System Control Registers (continued)

2.5.1.1

OffsetAcronym

Register Description

B0h

SSIR1

System Software Interrupt Request 1 Register

Section 2.5.1.38

Section

B4h

SSIR2

System Software Interrupt Request 2 Register

Section 2.5.1.39

B8h

SSIR3

System Software Interrupt Request 3 Register

Section 2.5.1.40

BCh

SSIR4

System Software Interrupt Request 4 Register

Section 2.5.1.41

C0h

RAMGCRRAM Control Register

Section 2.5.1.42

C4h

BMMCR1Bus Matrix Module Control Register 1

Section 2.5.1.43

CCh

CPURSTCR

CPU Reset Control Register

Section 2.5.1.44

D0h

CLKCNTL

Clock Control Register

Section 2.5.1.45

D4h

ECPCNTLECP Control Register

Section 2.5.1.46

DCh

DEVCR1

DEV Parity Control Register 1

Section 2.5.1.47

E0h

SYSECR

System Exception Control Register

Section 2.5.1.48

E4h

SYSESR

System Exception Status Register

Section 2.5.1.49

E8h

SYSTASR

System Test Abort Status Register

Section 2.5.1.50

ECh

GLBSTAT

Global Status Register

Section 2.5.1.51

F0h

DEVID

Device Identification Register

Section 2.5.1.52

F4h

SSIVEC

Software Interrupt Vector Register

Section 2.5.1.53

F8h

SSIF

System Software Interrupt Flag Register

Section 2.5.1.54

SYS Pin Control Register 1 (SYSPC1)The SYSPC1 register, shown in Figure 2-4 and described in Table 2-16, controls the function of the ECLK
pin.
Figure 2-4. SYS Pin Control Register 1 (SYSPC1) (offset = 00h)
31

16
Reserved
R-0

15

1

0

Reserved

ECPCLKFUN

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-16. SYS Pin Control Register 1 (SYSPC1) Field Descriptions
Bit

Field

31-1

Reserved

0

Value
0

ECPCLKFUN

Description
Reads return 0. Writes have no effect.
ECLK function. This bit changes the function of the ECLK pin.

0

ECLK is in GIO mode.

1

ECLK is in functional mode as a clock output.
Note: Proper ECLK duty cycle is not assured until 1 ECLK cycle has elapsed after switching
into functional mode.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

87

System and Peripheral Control Registers

2.5.1.2

www.ti.com

SYS Pin Control Register 2 (SYSPC2)The SYSPC2 register, shown in Figure 2-5 and described in Table 2-17, controls whether the pin is an
input or an output when in GIO mode.
Figure 2-5. SYS Pin Control Register 2 (SYSPC2) (offset = 04h)
31

16
Reserved
R-0

15

1

0

Reserved

ECPCLKDIR

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-17. SYS Pin Control Register 2 (SYSPC2) Field Descriptions
Bit

Field

31-1

Reserved

0

Value
0

ECPCLKDIR

Description
Reads return 0. Writes have no effect.
ECLK data direction. This bit controls the direction of the ECLK pin when it is configured to be in
GIO mode only.

0

The ECLK pin is an input.
Note: If the pin direction is set as an input, the output buffer is tristated.

1

The ECLK pin is an output.
Note: The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the
SYSPC1 register.

2.5.1.3

SYS Pin Control Register 3 (SYSPC3)The SYSPC3 register, shown in Figure 2-6 and described in Table 2-18, displays the logic state of the
ECLK pin when it is in GIO mode.
Figure 2-6. SYS Pin Control Register 3 (SYSPC3) (offset = 08h)
31

16
Reserved
R-0

15

1

0

Reserved

ECPCLKDIN

R-0

R-U

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -U = Undefined

Table 2-18. SYS Pin Control Register 3 (SYSPC3) Field Descriptions
Bit

Field

31-1

Reserved

0

88

Value
0

ECPCLKDIN

Description
Reads return 0. Writes have no effect.
ECLK data in. This bit displays the logic state of the ECLK pin when it is configured to be in GIO
mode.

0

The ECLK pin is at logic low (0).

1

The ECLK pin is at logic high (1).

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.4

SYS Pin Control Register 4 (SYSPC4)The SYSPC4 register, shown in Figure 2-7 and described in Table 2-19, controls the logic level output
function of the ECLK pin when when it is configured as an output in GIO mode.
Figure 2-7. SYS Pin Control Register 4 (SYSPC4) (offset = 0Ch)
31

16
Reserved
R-0

15

1

0

Reserved

ECPCLKDOUT

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-19. SYS Pin Control Register 4 (SYSPC4) Field Descriptions
Bit

Field

31-1

Reserved

0

Value
0

ECPCLKDOUT

Description
Reads return 0. Writes have no effect.
ECLK data out write. This bit is only active when the ECLK pin is configured to be in GIO mode.
Writes to this bit will only take effect when the ECLK pin is configured as an output in GIO mode.
The current logic state of the ECLK pin will be displayed by this bit in both input and output GIO
mode.

0

The ECLK pin is driven to logic low (0).

1

The ECLK pin is driven to logic high (1).
Note: The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the
SYSPC1 register. The ECLK pin is placed in output mode by setting the ECPCLKDIR bit to 1
in the SYSPC2 register.

2.5.1.5

SYS Pin Control Register 5 (SYSPC5)The SYSPC5 register, shown in Figure 2-8 and described in Table 2-20, controls the set function of the
ECLK pin when when it is configured as an output in GIO mode.
Figure 2-8. SYS Pin Control Register 5 (SYSPC5) (offset = 10h)31

16
Reserved
R-0

15

1

0

Reserved

ECPCLKSET

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-20. SYS Pin Control Register 5 (SYSPC5) Field Descriptions
Bit

Field

31-1

Reserved

0

Value
0

ECPCLKSET

Description
Reads return 0. Writes have no effect.
ECLK data out set. This bit drives the output of the ECLK pin high when set in GIO output mode.

0

Write: Writing a 0 has no effect.

1

Write: The ECLK pin is driven to logic high (1).
Note: The current logic state of the ECPCLKDOUT bit will also be displayed by this bit when
the pin is configured in GIO output mode.
Note: The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the
SYSPC1 register. The ECLK pin is placed in output mode by setting the ECPCLKDIR bit to 1
in the SYSPC2 register.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

89

System and Peripheral Control Registers

2.5.1.6

www.ti.com

SYS Pin Control Register 6 (SYSPC6)The SYSPC6 register, shown in Figure 2-9 and described in Table 2-21, controls the clear function of the
ECLK pin when when it is configured as an output in GIO mode..
Figure 2-9. SYS Pin Control Register 6 (SYSPC6) (offset = 14h)31

16Reserved
R-0

15

1

0

Reserved

ECPCLKCLR

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-21. SYS Pin Control Register 6 (SYSPC6) Field Descriptions
Bit

Field

31-1

Reserved

0

Value
0

ECPCLKCLR

Description
Reads return 0. Writes have no effect.
ECLK data out clear. This bit drives the output of the ECLK pin low when set in GIO output mode.

0

Write: The ECLK pin value is unchanged.

1

Write: The ECLK pin is driven to logic low (0).
Note: The current logic state of the ECPCLKDOUT bit will also be displayed by this bit when
the pin is configured in GIO output mode.
Note: The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the
SYSPC1 register. The ECLK pin is placed in output mode by setting the ECPCLKDIR bit to 1
in the SYSPC2 register.

2.5.1.7

SYS Pin Control Register 7 (SYSPC7)The SYSPC7 register, shown in Figure 2-10 and described in Table 2-22, controls the open drain functionof the ECLK pin.
Figure 2-10. SYS Pin Control Register 7 (SYSPC7) (offset = 18h)31

16Reserved
R-0

15

1

0

Reserved

ECPCLKODE

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-22. SYS Pin Control Register 7 (SYSPC7) Field Descriptions
Bit

Field

31-1

Reserved

0

Value
0

ECPCLKODE

Description
Reads return 0. Writes have no effect.
ECLK open drain enable. This bit is only active when ECLK is configured to be in GIO mode.

0

The ECLK pin is configured in push/pull (normal GIO) mode.

1

The ECLK pin is configured in open drain mode. The ECPCLKDOUT bit in the SYSPC4 register
controls the state of the ECLK output buffer:
ECPCLKDOUT = 0 The ECLK output buffer is driven low
ECPCLKDOUT = 1 The ECLK output buffer is tristated
Note: The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the
SYSPC1 register.

90

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.8

SYS Pin Control Register 8 (SYSPC8)The SYSPC8 register, shown in Figure 2-11 and described in Table 2-23, controls the pull enable functionof the ECLK pin when it is configured as an input in GIO mode.
Figure 2-11. SYS Pin Control Register 8 (SYSPC8) (offset = 1Ch)
31

16
Reserved
R-0

15

1

0

Reserved

ECPCLKPUE

R-0

R/W-D

LEGEND: R/W = Read/Write; R = Read only; D = Device Specific; -n = value after reset

Table 2-23. SYS Pin Control Register 8 (SYSPC8) Field Descriptions
Bit

Field

31-1

Reserved

0

Value
0

ECPCLKPUE

Description
Reads return 0. Writes have no effect.
ECLK pull enable. Writes to this bit will only take effect when the ECLK pin is configured as an
input in GIO mode.

0

ECLK pull enable is active.

1

ECLK pull enable is inactive.
Note: The pull direction (up/down) is selected by the ECPCLKPS bit in the SYSPC9 register.
Note: The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the
SYSPC1 register. The ECLK pin is placed in input mode by clearing the ECPCLKDIR bit to 0
in the SYSPC2 register.

2.5.1.9

SYS Pin Control Register 9 (SYSPC9)The SYSPC9 register, shown in Figure 2-12 and described in Table 2-24, controls the pull up/pull down
configuration of the ECLK pin when it is configured as an input in GIO mode.
Figure 2-12. SYS Pin Control Register 9 (SYSPC9) (offset = 20h)
31

16
Reserved
R-0

15

1

0

Reserved

ECPCLKPS

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-24. SYS Pin Control Register 9 (SYSPC9) Field Descriptions
Bit

Field

31-1

Reserved0

ECPCLKPS

Value
0

Description
Reads return 0. Writes have no effect.
ECLK pull up/pull down select. This bit is only active when ECLK is configured as an input in GIO
mode and the pull up/pull down logic is enabled.

0

ECLK pull down is selected, when pull up/pull down logic is enabled.

1

ECLK pull up is selected, when pull up/pull down logic is enabled.
Note: The ECLK pin pull up/pull down logic is enabled by clearing the ECPCLKPUE bit to 0
in the SYSPC8 register.
Note: The ECLK pin is placed into GIO mode by clearing the ECPCLKFUN bit to 0 in the
SYSPC1 register. The ECLK pin is placed in input mode by clearing the ECPCLKDIR bit to 0
in the SYSPC2 register.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

91

System and Peripheral Control Registers

www.ti.com

2.5.1.10 Clock Source Disable Register (CSDIS)
The CSDIS register, shown in Figure 2-13 and described in Table 2-25, controls and displays the state ofthe device clock sources.
NOTE: Nonimplemented clock sources should not be enabled or used.

Figure 2-13. Clock Source Disable Register (CSDIS) (offset = 30h)
31

8Reserved
R-0
7

5

4

3

2

1

0

Reserved

6

CLKSR5OFF

CLKSR4OFF

CLKSR3OFF

Reserved

CLKSR1OFF

CLKSR0OFF

R-0

R/WP-0R/WP-0R/WP-1

R-1

R/WP-1

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-25. Clock Source Disable Register (CSDIS) Field Descriptions
Bit

Field

31-6

Reserved

5-3

CLKSR[5-3]OFF

Value
0

Description
Reads return 0. Writes have no effect.
Clock source[5-3] off.

0

Clock source[5-3] is enabled.

1

Clock source[5-3] is disabled.
Note: On wakeup, only clock sources 0, 4, and 5 are enabled.

2

Reserved

1-0

CLKSR[1-0]OFF1

Reads return 1. Writes have no effect.
Clock source[1-0] off.

0

Clock source[1-0] is enabled.

1

Clock source[1-0] is disabled.
Note: On wakeup, only clock sources 0, 4, and 5 are enabled.

Table 2-26. Clock Sources Table

92

Clock Source #Clock Source Name

Clock Source 0

Oscillator

Clock Source 1

PLL

Clock Source 2

Not Implemented

Clock Source 3

EXTCLKIN

Clock Source 4

Low Frequency LPO (Low Power Oscillator) clock

Clock Source 5

High Frequency LPO (Low Power Oscillator) clock

Clock Source 6

Not Implemented

Clock Source 7

Not Implemented

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.11 Clock Source Disable Set Register (CSDISSET)
The CSDISSET register, shown in Figure 2-14 and described in Table 2-27, sets clock sources to thedisabled state.
NOTE: A list of the available clock sources is shown in Table 2-26.

Figure 2-14. Clock Source Disable Set Register (CSDISSET) (offset = 34h)
31

8
Reserved
R-0
7

5

4

3

2

1

0

Reserved

6

SETCLKSR5OFFSETCLKSR4OFFSETCLKSR3
OFF

Reserved

SETCLKSR1OFFSETCLKSR0
OFF

R-0

R/WP-0R/WP-0R/WP-1

R-1

R/WP-1

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-27. Clock Source Disable Set Register (CSDISSET) Field Descriptions
Bit

Field

31-6

Reserved

5-3

SETCLKSR[5-3] OFF

Value
0

Description
Reads return 0. Writes have no effect.
Set clock source[5-3] to the disabled state.

0

Read: Clock source[5-3] is enabled.
Write: Clock source[5-3] is unchanged.

1

Read: Clock source[5-3] is disabled.
Write: Clock source[5-3] is set to the disabled state.
Note: After a new clock source disable bit is set via the CSDISSET register, the new
status of the bit will be reflected in the CSDIS, CSDISSET, and CSDISCLR registers.

2

Reserved

1-0

SETCLKSR[1-0] OFF

1

Reads return 1. Writes have no effect.
Set clock source[1-0] to the disabled state.

0

Read: Clock source[1-0] is enabled.
Write: Clock source[1-0] is unchanged.

1

Read: Clock source[1-0] is disabled.
Write: Clock source[1-0] is set to the disabled state.
Note: After a new clock source disable bit is set via the CSDISSET register, the new
status of the bit will be reflected in the CSDIS, CSDISSET, and CSDISCLR registers.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

93

System and Peripheral Control Registers

www.ti.com

2.5.1.12 Clock Source Disable Clear Register (CSDISCLR)
The CSDISCLR register, shown in Figure 2-15 and described in Table 2-28, clears clock sources to theenabled state.
NOTE: A list of the available clock sources is shown in Table 2-26.

Figure 2-15. Clock Source Disable Clear Register (CSDISCLR) (offset = 38h)
31

8
Reserved
R-0
7

5

4

3

2

1

0

Reserved

6

CLRCLKSR5OFF

CLRCLKSR4OFF

CLRCLKSR3
OFF

Reserved

CLRCLKSR1
OFF

CLRCLKSR0
OFF

R-0

R/WP-0R/WP-0R/WP-1

R-1

R/WP-1

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-28. Clock Source Disable Clear Register (CSDISCLR) Field Descriptions
Bit

Field

31-6

Reserved

5-3

CLRCLKSR[5-3] OFF

Value
0

Description
Reads return 0. Writes have no effect.
Enables clock source[5-3].

0

Read: Clock source[5-3] is enabled.
Write: Clock source[5-3] is unchanged.

1

Read: Clock source[5-3] is enabled.
Write: Clock source[5-3] is set to the enabled state.
Note: After a new clock source disable bit is set via the CSDISSET register, the new
status of the bit will be reflected in the CSDIS, CSDISSET, and CSDISCLR registers.

2

Reserved

1-0

CLRCLKSR[1-0] OFF

1

Reads return 1. Writes have no effect.
Enables clock source[1-0].

0

Read: Clock source[1-0] is enabled.
Write: Clock source[1-0] is unchanged.

1

Read: Clock source[1-0] is enabled.
Write: Clock source[1-0] is set to the enabled state.
Note: After a new clock source disable bit is set via the CSDISSET register, the new
status of the bit will be reflected in the CSDIS, CSDISSET, and CSDISCLR registers.

94

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.13 Clock Domain Disable Register (CDDIS)
The CDDIS register, shown in Figure 2-16 and described in Table 2-29, controls the state of the clock
domains.
NOTE: All the clock domains are enabled on wakeup.
The application should assure that when HCLK and VCLK_sys are turned off through the
HCLKOFF bit, the GCLK1 domain is also turned off.
The register bits in CDDIS are designated as high-integrity bits and have been implemented
with error-correcting logic such that each bit, although read and written as a single bit, isactually a multi-bit key with error correction capability. As such, single-bit flips within the “key”
can be corrected allowing protection of the system as a whole. An error detected is signaled
to the ESM module.

Figure 2-16. Clock Domain Disable Register (CDDIS) (offset = 3Ch)
31

16
Reserved
R-0
15

11

10

9

8

Reserved

12

Reserved

Reserved

VCLK_EQEP_
OFF

Reserved

R-0

R/WP-0 or 1

R/WP-0 or 1

R/WP-0R/WP-0

7

6

5

4

3

2

1

0

Reserved

RTICLK1OFF

Reserved

VCLKA1OFFVCLK2OFFVCLKPOFFHCLKOFFGCLKOFF

R/WP-0 or 1

R/WP-0R/WP-0 or 1

R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-29. Clock Domain Disable Register (CDDIS) Field Descriptions
Bit

Field

31-12

Reserved

0

Reads return 0. Writes have no effect.

11-10

Reserved

0-1

Reads return 0 or 1 and privilege mode writes allowed.

9

VCLK_EQEP_OFF

8-7

Reserved

6

RTICLK1OFF

5

Reserved

4

VCLKA1OFF

3

2

Value

Description

VCLK_EQEP_OFF domain off.
0

VCLK_EQEP_OFF domain is enabled.

1

VCLK_EQEP_OFF domain is disabled.

0-1

Reads return 0 or 1 and privilege mode writes allowed.
RTICLK1 domain off.

0

RTICLK1 domain is enabled.

1

RTICLK1 domain is disabled.

0-1

Reads return 0 or 1 and privilege mode writes allowed.
VCLKA1 domain off.

0

VCLKA1 domain is enabled.

1

VCLKA1 domain is disabled.

VCLK2OFFVCLK2 domain off.
0

VCLK2 domain is enabled.

1

VCLK2 domain is disabled.

VCLKPOFFVCLK_periph domain off.
0

VCLK_periph domain is enabled.

1

VCLK_periph domain is disabled.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

95

System and Peripheral Control Registers

www.ti.com

Table 2-29. Clock Domain Disable Register (CDDIS) Field Descriptions (continued)
Bit

Field

1

HCLKOFF

0

96

Value

Description
HCLK and VCLK_sys domains off.

0

HCLK and VCLK_sys domains are enabled.

1

HCLK and VCLK_sys domains are disabled.

GCLKOFFGCLK domain off.
0

GCLK domain is enabled.

1

GCLK domain is disabled.

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.14 Clock Domain Disable Set Register (CDDISSET)
This CDDISSET register, shown in Figure 2-17 and described in Table 2-30, sets clock domains to thedisabled state.
Figure 2-17. Clock Domain Disable Set Register (CDDISSET) (offset = 40h)
31

16
Reserved
R-0
15

11

10

9

8

Reserved

12

Reserved

Reserved

SETVCLK_
EQEP_
OFFReserved

R-0

R/WP-0 or 1

R/WP-0 or 1

R/WP-0R/WP-0

7

6

5

4

3

2

1

0

Reserved

SETRTI1CLKOFFReserved

SETVCLKA1
OFF

SETVCLK2OFF

SETVCLKPOFF

SETHCLKOFF

SETGCLK
OFF

R/WP-0 or 1

R/WP-0R/WP-0 or 1

R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-30. Clock Domain Disable Set Register (CDDISSET) Field Descriptions
Bit

Field

31-12

Reserved

0

Reads return 0. Writes have no effect.

11-10

Reserved

0-1

Reads return 0 or 1 and privilege mode writes allowed.

9

Value

SETVCLK_EQEP_OFF

Description

Set VCLK_EQEP_OFF domain off.
0

Read: VCLK_EQEP_OFF domain is enabled.
Write: VCLK_EQEP_OFF domain is unchanged.

1

Read: VCLK_EQEP_OFF domain is disabled.
Write: VCLK_EQEP_OFF domain is set to the enabled state.

8-7

Reserved

6

SETRTI1CLKOFF

0-1

Reads return 0 or 1 and privilege mode writes allowed.
Set RTICLK1 domain.

0

Read: RTICLK1 domain is enabled.
Write: RTICLK1 domain is unchanged.

1

Read: RTICLK1 domain is disabled.
Write: RTICLK1 domain is set to the enabled state.

5

Reserved

4

SETVCLKA1OFF

0-1

Reads return 0 or 1 and privilege mode writes allowed.
Set VCLKA1 domain.

0

Read: VCLKA1 domain is enabled.
Write: VCLKA1 domain is unchanged.

1

Read: VCLKA1 domain is disabled.
Write: VCLKA1 domain is set to the enabled state.

3

SETVCLK2OFF

Set VCLK2 domain.
0

Read: VCLK2 domain is enabled.
Write: VCLK2 domain is unchanged.

1

Read: VCLK2 domain is disabled.
Write: VCLK2 domain is set to the enabled state.

2

SETVCLKPOFF

Set VCLK_periph domain.
0

Read: VCLK_periph domain is enabled.
Write: VCLK_periph domain is unchanged.

1

Read: VCLK_periph domain is disabled.
Write: VCLK_periph domain is set to the enabled state.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

97

System and Peripheral Control Registers

www.ti.com

Table 2-30. Clock Domain Disable Set Register (CDDISSET) Field Descriptions (continued)
Bit

Field

1

SETHCLKOFF

Value

Description
Set HCLK and VCLK_sys domains.

0

Read: HCLK and VCLK_sys domain is enabled.
Write: HCLK and VCLK_sys domain is unchanged.

1

Read: HCLK and VCLK_sys domain is disabled.
Write: HCLK and VCLK_sys domain is set to the enabled state.

0

SETGCLKOFF

Set GCLK domain.
0

Read: GCLK domain is enabled.
Write: GCLK domain is unchanged.

1

Read: GCLK domain is disabled.
Write: GCLK domain is set to the enabled state.

2.5.1.15 Clock Domain Disable Clear Register (CDDISCLR)
The CDDISCLR register, shown in Figure 2-18 and described in Table 2-31, clears clock domains to theenabled state.
Figure 2-18. Clock Domain Disable Clear Register (CDDISCLR) (offset = 44h)
31

16
Reserved
R-0
15

11

10

9

8

Reserved

12

Reserved

Reserved

CLRVCLK_
EQEP_
OFFReserved

R-0

R/WP-0 or 1

R/WP-0 or 1

R/WP-0R/WP-0

7

6

5

4

3

2

1

0

Reserved

CLRRTI1CLKOFFReserved

CLRVCLKA1
OFF

CLRVCLK2OFF

CLRVCLKPOFF

CLRHCLKOFF

CLRGCLK
OFF

R/WP-0 or 1

R/WP-0R/WP-0 or 1

R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-31. Clock Domain Disable Clear Register (CDDISCLR) Field Descriptions
Bit

Field

31-12

Reserved

0

Reads return 0. Writes have no effect.

11-10

Reserved

0-1

Reads return 0 or 1 and privilege mode writes allowed.

9

Value

CLRVCLK_EQEP_OFF

Description

Clear VCLK_EQEP_OFF domain off.
0

Read: VCLK_EQEP_OFF domain is enabled.
Write: VCLK_EQEP_OFF domain is unchanged.

1

Read: VCLK_EQEP_OFF domain is disabled.
Write: VCLK_EQEP_OFF domain is set to the enabled state.

8-7

Reserved

6

CLRRTI1CLKOFF

0-1

Reads return 0 or 1 and privilege mode writes allowed.
Clear RTICLK1 domain.

0

Read: RTICLK1 domain is enabled.
Write: RTICLK1 domain is unchanged.

1

Read: RTICLK1 domain is disabled.
Write: RTICLK1 domain is cleared to the enabled state.

5

98

Reserved

0-1

Reads return 0 or 1 and privilege mode writes allowed.

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

Table 2-31. Clock Domain Disable Clear Register (CDDISCLR) Field Descriptions (continued)
Bit

Field

4

CLRVCLKA1OFF

Value

Description
Clear VCLKA1 domain.

0

Read: VCLKA1 domain is enabled.
Write: VCLKA1 domain is unchanged.

1

Read: VCLKA1 domain is disabled.
Write: VCLKA1 domain is cleared to the enabled state.

3

CLRVCLK2OFF

Clear VCLK2 domain.
0

Read: VCLK2 domain is enabled.
Write: VCLK2 domain is unchanged.

1

Read: VCLK2 domain is disabled.
Write: VCLK2 domain is cleared to the enabled state.

2

CLRVCLKPOFF

Clear VCLK_periph domain.
0

Read: VCLK_periph domain is enabled.
Write: VCLK_periph domain is unchanged.

1

Read: VCLK_periph domain is disabled.
Write: VCLK_periph domain is cleared to the enabled state.

1

CLRHCLKOFF

Clear HCLK and VCLK_sys domains.
0

Read: HCLK and VCLK_sys domain is enabled.
Write: HCLK and VCLK_sys domain is unchanged.

1

Read: HCLK and VCLK_sys domain is disabled.
Write: HCLK and VCLK_sys domain is cleared to the enabled state.

0

CLRGCLKOFF

Clear GCLK domain.
0

Read: GCLK domain is enabled.
Write: GCLK domain is unchanged.

1

Read: GCLK domain is disabled.
Write: GCLK domain is cleared to the enabled state.

2.5.1.16 GCLK, HCLK, VCLK, and VCLK2 Source Register (GHVSRC)The GHVSRC register, shown in Figure 2-19 and described in Table 2-32, controls the clock source
configuration for the GCLK, HCLK, VCLK and VCLK2 clock domains.
NOTE: Nonimplemented clock sources should not be enabled or used. A list of the available clock
sources is shown in Table 2-26.

Figure 2-19. GCLK, HCLK, VCLK, and VCLK2 Source Register (GHVSRC) (offset = 48h)
31

28

27

24

23

20

19

16

Reserved

GHVWAKE

Reserved

HVLPM

R-0

R/WP-0R-0

R/WP-0

15

4

3

0

Reserved

GHVSRC

R-0

R/WP-0LEGEND: R = Read only; R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

99

System and Peripheral Control Registers

www.ti.com

Table 2-32. GCLK, HCLK, VCLK, and VCLK2 Source Register (GHVSRC) Field Descriptions
Bit

Field

31-28

Reserved

27-24

GHVWAKE

Value
0

Reserved

19-16

HVLPM

0

Clock source0 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.

1h

Clock source1 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.

2h

Clock source2 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.

3h

Clock source3 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.

4h

Clock source4 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.

5h

Clock source5 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.

6h

Clock source6 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.

7h

Clock source7 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.

0

Reserved

3-0

GHVSRC

Reserved
Reads return 0. Writes have no effect.
HCLK, VCLK, VCLK2 source on wakeup when GCLK is turned off.

0

Clock source0 is the source for HCLK, VCLK, VCLK2 on wakeup.

1h

Clock source1 is the source for HCLK, VCLK, VCLK2 on wakeup.

2h

Clock source2 is the source for HCLK, VCLK, VCLK2 on wakeup.

3h

Clock source3 is the source for HCLK, VCLK, VCLK2 on wakeup.

4h

Clock source4 is the source for HCLK, VCLK, VCLK2 on wakeup.

5h

Clock source5 is the source for HCLK, VCLK, VCLK2 on wakeup.

6h

Clock source6 is the source for HCLK, VCLK, VCLK2 on wakeup.

7h

Clock source7 is the source for HCLK, VCLK, VCLK2 on wakeup.

8h-Fh
15-4

Reads return 0. Writes have no effect.
GCLK, HCLK, VCLK, VCLK2 source on wakeup.

8h-Fh
23-20

Description

0

Reserved
Reads return 0. Writes have no effect.
GCLK, HCLK, VCLK, VCLK2 current source.
Note: The GHVSRC[3-0] bits are updated with the HVLPM[3-0] setting when GCLK is turnedoff, and are updated with the GHVWAKE[3-0] setting on system wakeup.

0

Clock source0 is the source for GCLK, HCLK, VCLK, VCLK2.

1h

Clock source1 is the source for GCLK, HCLK, VCLK, VCLK2.

2h

Clock source2 is the source for GCLK, HCLK, VCLK, VCLK2.

3h

Clock source3 is the source for GCLK, HCLK, VCLK, VCLK2.

4h

Clock source4 is the source for GCLK, HCLK, VCLK, VCLK2.

5h

Clock source5 is the source for GCLK, HCLK, VCLK, VCLK2.

6h

Clock source6 is the source for GCLK, HCLK, VCLK, VCLK2.

7h

Clock source7 is the source for GCLK, HCLK, VCLK, VCLK2.

8h-Fh

100

Reserved

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.17 Peripheral Asynchronous Clock Source Register (VCLKASRC)
The VCLKASRC register, shown in Figure 2-20 and described in Table 2-33, sets the clock source for the
asynchronous peripheral clock domains to be configured to run from a specific clock source.
NOTE: Nonimplemented clock sources should not be enabled or used. A list of the available clock
sources is shown in Table 2-26.

Figure 2-20. Peripheral Asynchronous Clock Source Register (VCLKASRC) (offset = 4Ch)
31

16
Reserved
R-0

15

4

3

0

Reserved

VCLKA1S

R-0

R/WP-9h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-33. Peripheral Asynchronous Clock Source Register (VCLKASRC) Field Descriptions
Bit

Field

31-4

Reserved

3-0

VCLKA1S

Value
0

Description
Reads return 0. Writes have no effect.
Peripheral asynchronous clock1 source.

0

Clock source0 is the source for peripheral asynchronous clock1.

1h

Clock source1 is the source for peripheral asynchronous clock1.

2h

Clock source2 is the source for peripheral asynchronous clock1.

3h

Clock source3 is the source for peripheral asynchronous clock1.

4h

Clock source4 is the source for peripheral asynchronous clock1.

5h

Clock source5 is the source for peripheral asynchronous clock1.

6h

Clock source6 is the source for peripheral asynchronous clock1.

7h

Clock source7 is the source for peripheral asynchronous clock1.

8h-Fh

VCLK is the source for peripheral asynchronous clock1.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

101

System and Peripheral Control Registers

www.ti.com

2.5.1.18 RTI Clock Source Register (RCLKSRC)
The RCLKSRC register, shown in Figure 2-21 and described in Table 2-34, controls the RTI (Real TimeInterrupt) clock source selection.
NOTE: Important constraint when the RTI clock source is not VCLK
If the RTIx clock source is chosen to be anything other than the default VCLK, then the RTI
clock needs to be at least three times slower than the VCLK. This can be achieved byconfiguring the RTIxCLK divider in this register. This divider is internally bypassed when the
RTIx clock source is VCLK.

NOTE: A list of the available clock sources is shown in Table 2-26.

Figure 2-21. RTI Clock Source Register (RCLKSRC) (offset = 50h)
31

26

25

24

23

20

19

16

Reserved

Reserved

Reserved

Reserved

R-0

R/WP-1h

R-0

R/WP-9h

15

10

9

8

7

4

3

0

Reserved

RTI1DIV

Reserved

RTI1SRC

R-0

R/WP-1h

R-0

R/WP-9h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-34. RTI Clock Source Register (RCLKSRC) Field Descriptions
Bit

Field

31-26

Reserved

0

Reads return 0. Writes have no effect.

25-24

Reserved

1h

Reads return value and privilege mode writes allowed.

23-20

Reserved

0

Reads return 0. Writes have no effect.

19-16

Reserved

9h

Reads return value and privilege mode writes allowed.

15-10

Reserved

0

Reads return 0. Writes have no effect.

9-8

RTI1DIV

7-4

Reserved

3-0

RTI1SRCValue

RTI clock1 Divider.
0

RTICLK1 divider value is 1.

1h

RTICLK1 divider value is 2.

2h

RTICLK1 divider value is 4.

3h

RTICLK1 divider value is 8.

0

Reads return 0. Writes have no effect.
RTI clock1 source.

0

Clock source0 is the source for RTICLK1.

1h

Clock source1 is the source for RTICLK1.

2h

Clock source2 is the source for RTICLK1.

3h

Clock source3 is the source for RTICLK1.

4h

Clock source4 is the source for RTICLK1.

5h

Clock source5 is the source for RTICLK1.

6h

Clock source6 is the source for RTICLK1.

7h

Clock source7 is the source for RTICLK1.

8h-Fh

102

Description

VCLK is the source for RTICLK1.

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.19 Clock Source Valid Status Register (CSVSTAT)The CSVSTAT register, shown in Figure 2-22 and described in Table 2-35, indicates the status of usableclock sources.
NOTE: A list of the available clock sources is shown in Table 2-26.

Figure 2-22. Clock Source Valid Status Register (CSVSTAT) (offset = 54h)
31

8
Reserved
R-0
7

5

4

3

2

1

0

Reserved

6

CLKSR5V

CLKSR4V

CLKSR3V

Reserved

CLKSR1V

CLKSR0V

R-0

R-0

R-1

R-1

R-0

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 2-35. Clock Source Valid Register (CSVSTAT) Field Descriptions
Bit

Field

31-6

Reserved

5-3

CLKSR[5-3]V

Value
0

Description
Reads return 0. Writes have no effect.
Clock source[5-3] valid.

0

Clock source[5-3] is not valid.

1

Clock source[5-3] is valid.
Note: If the valid bit of the source of a clock domain is not set (that is, the clock source is
not fully stable), the respective clock domain is disabled by the Global Clock Module (GCM).

2

Reserved

1-0

CLKSR[1-0]V0Reads return 0. Writes have no effect.
Clock source[1–0] valid.

0

Clock source[1–0] is not valid.

1

Clock source[1–0] is valid.
Note: If the valid bit of the source of a clock domain is not set (that is, the clock source is
not fully stable), the respective clock domain is disabled.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

103

System and Peripheral Control Registers

www.ti.com

2.5.1.20 Memory Self-Test Global Control Register (MSTGCR)
The MSTGCR register, shown in Figure 2-23 and described in Table 2-36, controls several aspects of the
PBIST (Programmable Built-In Self Test) memory controller.
Figure 2-23. Memory Self-Test Global Control Register (MSTGCR) (offset = 58h)
31

16
Reserved
R-0

15

10

9

8

7

4

3

0

Reserved

ROM_DIV

Reserved

MSTGENA

R-0

R/WP-0R-0

R/WP-5h

LEGEND: R = Read only; R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 2-36. Memory Self-Test Global Control Register (MSTGCR) Field Descriptions
Bit

Field

31-10

Reserved

9-8

ROM_DIV

7-4

Reserved

3-0

MSTGENA

Value
0

Description
Reads return 0. Writes have no effect.
Prescaler divider bits for ROM clock source.

0

ROM clock source is HCLK divided by 1. PBIST will reset for 16 VBUS cycles.

1h

ROM clock source is HCLK divided by 2. PBIST will reset for 32 VBUS cycles.

2h

ROM clock source is HCLK divided by 4. PBIST will reset for 64 VBUS cycles.

3h

ROM clock source is HCLK divided by 8. PBIST will reset for 96 VBUS cycles.

0

Reads return 0. Writes have no effect.
Memory self-test controller global enable key
Note: Enabling the MSTGENA key will generate a reset to the state machine of the
PBIST controller.

Ah

Memory self-test controller is enabled.

All other values

Memory self-test controller is disabled.
Note: It is recommended that a value of 5h be used to disable the memory self-test
controller. This value will give maximum protection from a bit flip inducing event thatwould inadvertently enable the controller.

104

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.21 Memory Hardware Initialization Global Control Register (MINITGCR)
The MINITGCR register, shown in Figure 2-24 and described in Table 2-37, enables automatic hardware
memory initialization.
Figure 2-24. Memory Hardware Initialization Global Control Register (MINITGCR) (offset = 5Ch)
31

16
Reserved
R-0

15

4

3

0

Reserved

MINITGENA

R-0

R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-37. Memory Hardware Initialization Global Control Register (MINITGCR) Field Descriptions
Bit

Field

31-4

Reserved

3-0

MINITGENA

Value
0

Description
Reads return 0. Writes have no effect.
Memory hardware initialization global enable key.

AhGlobal memory hardware initialization is enabled.

All other values

Global memory hardware initialization is disabled.
Note: It is recommended that a value of 5h be used to disable memory hardware
initialization. This value will give maximum protection from an event that would
inadvertently enable the controller.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

105

System and Peripheral Control Registers

www.ti.com

2.5.1.22 PBIST Controller/ Memory Initialization Enable Register (MSINENA)
The MSINENA register, shown in Figure 2-25 and described in Table 2-38, enables PBIST controllers formemory self test and the memory modules initialized during automatic hardware memory initialization.
Figure 2-25. PBIST Controller/Memory Initialization Enable Register (MSINENA) (offset = 60h)
310
MSIENA[31:0]
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-38. PBIST Controller/Memory Initialization Enable Register (MSINENA) Field Descriptions
Bit

Field

31-0

MSIENA

Value

Description
PBIST controller and memory initialization enable register. In memory self-test mode, all thecorresponding bits of the memories to be tested should be set before enabling the global memory selftest controller key (MSTGENA) in the MSTGCR register (offset 58h). The reason for this is that
MSTGENA, in addition to being the global enable for all individual PBIST controllers, is the source forthe reset generation to all the PBIST controller state machines. Disabling the MSTGENA or
MINITGENA key (by writing from Ah to any other value) will reset all the MSIENA [31-0] bits to theirdefault values.
Note: Software should ensure that both the memory self-test global enable key (MSTGENA) andthe memory hardware initialization global key (MINITGENA) are not enabled at the same time.

0

In memory self-test mode (MSTGENA = Ah):PBIST controller [31-0] is disabled.
In memory Initialization mode (MINITGENA = Ah):
Memory module [31-0] auto hardware initialization is disabled.

1

In memory self-test mode (MSTGENA = Ah):PBIST controller [31-0] is enabled.
In memory Initialization mode (MINITGENA = Ah):
Memory module [31-0] auto hardware initialization is enabled.

106

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.23 Memory Self-Test Fail Status Register (MSTFAIL)
The MSTFAIL register, shown in Figure 2-26 and described in Table 2-39, shows the fail status of thememory self-tests.
Figure 2-26. Memory Self-Test Fail Status Register (MSTFAIL) (offset = 64h)
31

0
MSTF[31:0]
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-39. Memory Self-Test Fail Status Register (MSTFAIL) Field Descriptions
Bit

Field

31-0

MSTF

Value

Description
Memory self-test fail status bit.
Note: Disabling the MSTGENA key (by writing from Ah to any other value) will reset all theindividual fail status bits to their default values.

0

Read: PBIST controller [31-0] run did not fail.
Write: A write of 0 has no effect.

1

Read: PBIST controller [31-0] run failed.
Write: The bit is cleared to 0.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

107

System and Peripheral Control Registers

www.ti.com

2.5.1.24 MSTC Global Status Register (MSTCGSTAT)The MSTCGSTAT register, shown in Figure 2-27 and described in Table 2-40, shows the status of thememory hardware initialization and the memory seft-test.
Figure 2-27. MSTC Global Status Register (MSTCGSTAT) (offset = 68h)
31

16
Reserved
R-0

15

9

8

7

1

0

Reserved

MINIDONE

Reserved

MSTDONE

R-0

R/W1CP-0

R-0

R/W1CP-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; WP = Write in privileged mode only; -n = value after reset

Table 2-40. MSTC Global Status Register (MSTCGSTAT) Field Descriptions
Bit

Field

31-9

Reserved

8

MINIDONE

Value
0

Description
Reads return 0. Writes have no effect.
Memory hardware initialization complete status.
Note: Disabling the MINITGENA key (by writing from Ah to any other value) will clear the
MINIDONE status bit to 0.
Note: Individual memory initialization status is shown in the MINISTAT register.

0

Read: Memory hardware initialization is not complete for all memory.
Write: A write of 0 has no effect.

1

Read: Hardware initialization of all memory is completed.
Write: The bit is cleared to 0.

7-1

Reserved

0

MSTDONE0

Reads return 0. Writes have no effect.
Memory self-test run complete status.
Note: Disabling the MSTGENA key (by writing from Ah to any other value) will clear the
MSTDONE status bit to 0.

0

Read: Memory self-test is not completed.
Write: A write of 0 has no effect.

1

Read: Memory self-test is completed.
Write: The bit is cleared to 0.

108

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.25 Memory Hardware Initialization Status Register (MINISTAT)The MINISTAT register, shown in Figure 2-28 and described in Table 2-41, indicates the status of
hardware memory initialization.
Figure 2-28. Memory Hardware Initialization Status Register (MINISTAT) (offset = 6Ch)
31

0
MIDONE[31:0]
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-41. Memory Hardware Initialization Status Register (MINISTAT) Field Descriptions
Bit

Field

31-0

MIDONE

Value

Description
Memory hardware initialization status bit.

0

Read: Memory module[31-0] hardware initialization is not completed.
Write: A write of 0 has no effect.

1

Read: Memory module[31-0] hardware initialization is completed.
Write: The bit is cleared to 0.
Note: Disabling the MINITGENA key (by writing from Ah to any other value) will reset all theindividual status bits to 0.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

109

System and Peripheral Control Registers

www.ti.com

2.5.1.26 PLL Control Register 1 (PLLCTL1)
The PLLCTL1 register, shown in Figure 2-29 and described in Table 2-42, controls the output frequency of
PLL (Clock Source 1 - FMzPLL). It also controls the behavior of the device if a PLL slip or oscillator failure
is detected.
Figure 2-29. PLL Control Register 1 (PLLCTL1) (offset = 70h)
31

30

29

28

23

22

ROS

MASK_SLIPPLLDIV

24

ROF

Rsvd

21
REFCLKDIV

16

R/WP-0R/WP-1h

R/WP-Fh

R/WP-0R-0

R/WP-2h

150
PLLMUL
R/WP-5F00h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-42. PLL Control Register 1 (PLLCTL1) Field Descriptions
Bit

Field

31

ROS

Value

Description
Reset on PLL Slip0

Do not reset system when PLL slip is detected

1

Reset when PLL slip is detected
Note: BPOS (Bits 30-29) must also be enabled for ROS to be enabled.

30-29

MASK_SLIP

Mask detection of PLL slip
2h
All other values

Bypass on PLL Slip is disabled. If a PLL Slip is detected no action is taken.
Bypass on PLL Slip is enabled. If a PLL Slip is detected the device will automatically bypass
the PLL and use the oscillator to provide the device clock.
Note: If ROS (Bit 31) is set to 1 the device will be reset if a PLL Slip and the PLL will be
bypassed after the reset occurs.

28-24

PLLDIVPLL Output Clock Divider
R = PLLDIV + 1
f PLL CLK= f post_ODCLK / R
0f PLL CLK= f post_ODCLK / 11hf PLL CLK= f post_ODCLK / 2

:

:

1Fh
23

ROF

22

Reserved

21-16

REFCLKDIV

f PLL CLK= f post_ODCLK / 32
Reset on Oscillator Fail0

Do not reset system when oscillator is out of range.

1

Reset when oscillator is out of range.

0

Value has no effect on PLL operation.
Reference Clock Divider
NR = REFCLKDIV + 1
f INT CLK= f OSCIN / NR

0f INT CLK= f OSCIN / 11h

f INT CLK= f OSCIN / 2

:

:

3Fh

110

f INT CLK= f OSCIN / 64

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

Table 2-42. PLL Control Register 1 (PLLCTL1) Field Descriptions (continued)
Bit

Field

15-0

PLLMUL

Value

Description
PLL Multiplication Factor
Valid multiplication factors are from 1 to 256.
NF = (PLLMUL / 256) + 1
f VCO CLK= f INT CLK x NF

0h

f VCO CLK= f INT CLK x 1

100h

f VCO CLK= f INT CLK x 2

:

:

5B00h

f VCO CLK= f INT CLK x 92

5C00h

f VCO CLK= f INT CLK x 93

:
FF00h

:
f VCO CLK= f INT CLK x 256

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

111

System and Peripheral Control Registers

www.ti.com

2.5.1.27 PLL Control Register 2 (PLLCTL2)
The PLLCTL2 register, shown in Figure 2-30 and described in Table 2-43, controls the modulation
characteristics and the output divider of the PLL.
Figure 2-30. PLL Control Register 2 (PLLCTL2) (offset = 74h)
31

30

22

21

20

16

FMENA

SPREADINGRATE

Rsvd

MULMOD

R/WP-0R/WP-1FFh

R-0

R/WP-0

15

12

11

9

8

0

MULMODODPLL

SPR_AMOUNTR/WP-7h

R/WP-1h

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-43. PLL Control Register 2 (PLLCTL2) Field Descriptions
Bit

Field

31

FMENA

30-22

Value

Description
Frequency Modulation Enable.

0

Disable frequency modulation

1

Enable frequency modulation

SPREADINGRATE

NS = SPREADINGRATE + 1
f mod= f s= f INT CLK/(2 × NS)0f mod= f s= f INT CLK / (2 × 1)

1hf mod= f s= f INT CLK / (2 × 2)

:

:

1FFh
21

Reserved

20-12

MULMOD0

f mod= f s= f INT CLK / (2 × 512)
Value has no effect on PLL operation.
Multiplier Correction when Frequency Modulation is enabled
When FMENA = 0, MUL_when_MOD = 0; When FMENA = 1, MUL_when_MOD =(MULMOD / 256)0

No adder to NF

8h

MUL_when_MOD = 8/256

9h

MUL_when_MOD = 9/256

:

:

1FFh
11-9

ODPLL

MUL_when_MOD = 511/256
Internal PLL Output Divider.
OD = ODPLL + 1
f post-ODCLK= f VCO CLK/OD
Note that the PLL output clock is gated off if ODPLL is changed while the PLL is active.

8-0

0

f post-ODCLK= f VCO CLK / 1

1hf post-ODCLK= f VCO CLK / 2

:

:

7h

f post-ODCLK= f VCO CLK / 8

SPR_AMOUNT

Spreading Amount.
NV = (SPR_AMOUNT + 1)/2048
NV ranges from 1/2048 to 512/2048
Note that the PLL output clock is disabled for 1 modulation period if the SPR_AMOUNT field
is changed while the frequency modulation is enabled. If frequency modulation is disabled
and SPR_AMOUNT is changed, there is no effect on the PLL output clock.
0

NV = 1/2048

1h

NV = 2/2048

:

:

1FFh
112

NV = 512/2048

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.28 SYS Pin Control Register 10 (SYSPC10)The SYSPC10 register, shown in Figure 2-31 and described in Table 2-44, controls the function of the
ECLK slew mode.
Figure 2-31. SYS Pin Control Register 10 (SYSPC10) (offset = 78h)
31

16
Reserved
R-0

15

1

0

Reserved

ECLK_SLEW

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-44. SYS Pin Control Register 10 (SYSPC10) Field Descriptions
Bit

Field

31-1

Reserved

0

Value
0

ECLK_SLEW

Description
Reads return 0. Writes have no effect.
ECLK slew control. This bit controls between the fast or slow slew mode.

0

Fast mode is enabled; the normal output buffer is used for this pin.

1

Slow mode is enabled; slew rate control is used for this pin.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

113

System and Peripheral Control Registers

www.ti.com

2.5.1.29 Die Identification Register Lower Word (DIEIDL)The DIEIDL register, shown in Figure 2-32 and described in Table 2-45, contains information about the diewafer number, and X, Y wafer coordinates.
Figure 2-32. Die Identification Register, Lower Word (DIEIDL) [offset = 7Ch]
31

24

15

23

16

WAFER #Y WAFER COORDINATE

R-D

R-D

12

11

0

Y WAFER COORDINATEX WAFER COORDINATE

R-D

R-D

LEGEND: R = Read only; -n = value after reset; -D = device specific

Table 2-45. Die Identification Register, Lower Word (DIEIDL) Field Descriptions
Bit

Field

Description

31-24

WAFER #

These read-only bits contain the wafer number of the device.

23-12

Y WAFER COORDINATE

These read-only bits contain the Y wafer coordinate of the device.

11-0

X WAFER COORDINATE

These read-only bits contain the X wafer coordinate of the device.

NOTE: Die Identification Information
The die identification information will vary from unit to unit. This information is programmed
by TI as part of the initial device test procedure.

2.5.1.30 Die Identification Register Upper Word (DIEIDH)
The DIEIDH register, shown in Figure 2-33 and described in Table 2-46, contains information about thedie lot number.
Figure 2-33. Die Identification Register, Upper Word (DIEIDH) [offset = 80h]
31

24

23

16

Reserved

LOT #

R-0

R-D

15

0
LOT #
R-D

LEGEND: R/W = Read/Write; R = Read only; D = Value is device dependent; -n = value after reset

Table 2-46. Die Identification Register, Upper Word (DIEIDH) Field Descriptions
Bit

Field

Description

31-24

Reserved

Reserved for TI use. Writes have no effect.

23-0

LOT #

This read-only register contains the device lot number.

NOTE: Die Identification Information
The die identification information will vary from unit to unit. This information is programmed
by TI as part of the initial device test procedure.

114

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.31 LPO/Clock Monitor Control Register (LPOMONCTL)
The LPOMONCTL register, shown in Figure 2-34 and described in Table 2-47, controls the Low
Frequency (Clock Source 4) and High Frequency (Clock Source 5) Low Power Oscillator's trim values.
Figure 2-34. LPO/Clock Monitor Control Register (LPOMONCTL) [offset = 88h]
31

25

15

24

23

17

16

Reserved

BIAS ENABLE

Reserved

OSCFRQCONFIGCNT

R-0

R/WP-1

R-0

R/WP-0

13

12

8

7

5

4

0

Reserved

HFTRIM

Reserved

LFTRIM

R-0

R/WP-10h

R-0

R/WP-10h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-47. LPO/Clock Monitor Control Register (LPOMONCTL) Field Descriptions
Bit

Field

31-25

Reserved

24

23-17
16

Value
0

BIAS ENABLE

Reserved

Description
Read returns 0. Writes have no effect.
Bias enable. Reset by nPORRST.

0

The bias circuit inside the low-power oscillator (LPO) is disabled.

1

The bias circuit inside LPO is enabled.

0

Read returns 0. Writes have no effect.

OSCFRQCONFIGCNT

Configures the counter based on OSC frequency.
0

Read: OSC freq is ≤ 20MHz
Write: A write of 0 has no effect.

1

Read: OSC freq is > 20MHz and ≤ 80MHz
Write: A write of 1 has no effect.

15-13

Reserved

0

Read returns 0. Writes have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

115

System and Peripheral Control Registers

www.ti.com

Table 2-47. LPO/Clock Monitor Control Register (LPOMONCTL) Field Descriptions (continued)
Bit

Field

12-8

HFTRIM

Value

Description
High-frequency oscillator trim value. This five-bit value is used to center the HF oscillator'sfrequency. Reset by nPORRST.
Caution: This value should only be changed when the HF oscillator is not the source
for a clock domain; otherwise, a system failure could result.
The following HF TRIM values reflect for the F021 process.
The following values are the ratio, f / fo, expressed as a percent:

7-5

116

Reserved

0

29.52

1h

34.24

2h

38.85

3h

43.45

4h

47.99

5h

52.55

6h

57.02

7h

61.46

8h

65.92

9h

70.17

Ah

74.55

Bh

78.92

Ch

83.17

Dh

87.43

Eh

91.75

Fh

95.89

10h

100.00% (Default at Reset)

11h

104.0912h

108.1713h112.3214h

116.4115h120.6716h

124.4217h

128.3818h132.2419h

136.151Ah

140.151Bh

143.941Ch

148.02

1Dh

151.801Eh155.501Fh159.350

Read returns 0. Writes have no effect.

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

Table 2-47. LPO/Clock Monitor Control Register (LPOMONCTL) Field Descriptions (continued)
Bit

Field

4-0

LFTRIM

Value

Description
Low-frequency oscillator trim value. This five-bit value is used to center the LF oscillator'sfrequency. Reset by nPORRST.
Caution: This value should only be changed when the LF oscillator is not the source
for a clock domain; otherwise, a system failure could result.
The following LF TRIM values reflect for the F021 process.
The following values are the ratio, f / fo, expressed as a percent:

0

20.67

1h

25.76

2h

30.84

3h

35.90

4h

40.93

5h

45.95

6h

50.97

7h

55.91

8h

60.86

9h

65.78

Ah

70.75

Bh

75.63

Ch

80.61

Dh

85.39

Eh

90.23

Fh

95.11

10h

100.00% (Default at Reset)

11h

104.8412h

109.5113h

114.3114h

119.0115h

123.7516h

128.6217h133.3118h138.0319h

142.75

1Ah

147.321Bh152.02

1Ch

156.63

1Dh

161.381Eh165.901Fh170.42SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

117

System and Peripheral Control Registers

www.ti.com

2.5.1.32 Clock Test Register (CLKTEST)The CLKTEST register, shown in Figure 2-35 and described in Table 2-48, controls the clock signal that is
supplied to the ECLK pin for test and debug purposes.
NOTE: Clock Test Register Usage
This register should only be used for test and debug purposes.

NOTE: Nonimplemented clock sources should not be enabled or used.

Figure 2-35. Clock Test Register (CLKTEST) (offset = 8Ch)
31

26

25

24

Reserved

27

ALTLIMPCLOCKENABLERANGEDET
CTRL

RANGEDET
ENABLE

R-0

R/WP-0R/WP-0R/WP-0

23

20

19

16

Reserved

CLK_TEST_EN

R-0

R/WP-Ah

15

12

11

8

7

4

3

0

Reserved

SEL_N2HET_PIN

Reserved

SEL_ECP_PIN

R-0

R/WP-0R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-48. Clock Test Register (CLKTEST) Field Descriptions
Bit

Field

31-27

Reserved

26

25

24

Value
0

ALTLIMPCLOCKENABLE
0

The 10-MHz LPO fast clock is the compare clock for the clock detect
PFD circuit and the source to limp clock on a clock fail.

1

The ALTLIMPCLOCK driven on the GIOB[0] pin is the compare clock forthe clock detect PFD circuit and the source to limp clock on a clock fail.
Range detection control. This bit's functionality is dependant on the stateof the RANGEDETENSSEL bit (Bit 24) of the CLKTEST register.

0

The clock monitor range detection circuitry (RANGEDETECTENABLE) is
disabled.

1

The clock monitor range detection circuitry (RANGEDETECTENABLE) isenabled.

RANGEDETENABLE

Reserved

19-16

CLK_TEST_EN

Reads return 0. Writes have no effect.
This bit selects a clock driven by the GIOB[0] pin as an alternate limp
clock to the clock monitor phase frequency detect (PFD).

RANGEDETCTRL

23-20

Description

Selects range detection enable. This bit resets asynchronously on poweron reset.
0

The range detect enable is generated by the hardware in the clockmonitor wrapper.

1

The range detect enable is controlled by the RANGEDETCTRL bit (Bit25) of the CLKTEST register.

0

Reads return 0. Writes have no effect.
Clock test enable. This bit enables the clock going to the ECLK pin.
Note: The ECLK pin must also be placed into Functional mode bysetting the ECPCLKFUN bit to 1 in the SYSPC1 register.

15-12

118

Reserved

5h

Clock going to ECLK pin is enabled.

All other values

Clock going to ECLK pin is disabled.

0

Reads return 0. Writes have no effect.

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

Table 2-48. Clock Test Register (CLKTEST) Field Descriptions (continued)
Bit

Field

11-8

SEL_N2HET_PIN

Value

N2HET[2] pin clock source valid, clock source select0

Oscillator valid status1h

PLL1 valid status

2h-4h
5h
6h-7h
8h
9h-Fh
7-4

Reserved

3-0

SEL_ECP_PIN

Description

0

Reserved[CLK10M] High-frequency LPO (Low-Power Oscillator) clock valid status
Reserved[CLK80K] Low-frequency LPO (Low-Power Oscillator) clock valid status
Oscillator valid status
Reads return 0. Writes have no effect.
ECLK pin clock source selectNote: Only valid clock sources can be selected for the ECLK pin.
Valid clock sources are displayed by the CSVSTAT register.

0

Oscillator clock

1h

PLL1 clock output

2h-3h

Reserved

4h[CLK80K] Low-frequency LPO (Low-Power Oscillator) clock5h[CLK10M] High-frequency LPO (Low-Power Oscillator) clock

6h-7hReserved

8h

GCLK

9h

RTI Base

Ah

Reserved

Bh

VCLKA1

Ch-Eh

Reserved

Fh

Flash HD Pump Oscillator

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

119

System and Peripheral Control Registers

www.ti.com

2.5.1.33 DFT Control Register (DFTCTRLREG)This register is shown in Figure 2-36 and described in Table 2-49.
Figure 2-36. DFT Control Register (DFTCTRLREG) (offset = 90h)
31

16
Reserved
R-0

15

14

13

12

11

10

9

8

7

4

3

0

Reserved

DFTWRITE

Reserved

DFTREAD

Reserved

TEST_MODE_KEY

R-0

R/WP-1h

R-0

R/WP-1h

R-0

R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-49. DFT Control Register (DFTCTRLREG) Field Descriptions
Bit

Field

Value

31-14 Reserved

013-12 DFTWRITE

0-3h

11-10 Reserved

Description
Reads return 0. Writes have no effect.
DFT logic access. See Table 2-50.

0

9-8

DFTREAD

0-3h

7-4

Reserved0

3-0

TEST_MODE_KEY

Reads return 0. Writes have no effect.
DFT logic access. See Table 2-50.
Reads return 0. Writes have no effect.
Test mode key. This register is for internal TI use only.

Ah

Register key enable. ALL the bits can be written to only when the key is enabled. On
reset, these bits will be set to 5h.

All other values Register key disable. All bits in this register will maintain their default value and cannot
be written.

Table 2-50. DFT Logic Access ModeDFTWRITE

120

DFTREAD

Bit 13

Bit 12

Bit 9

Bit 8

0

0

0

0

Mode
Configured in stress mode

0

1

0

1

Configured in slow mode

1

0

1

0

Configured in fast mode

1

1

1

1

Configured in screen mode

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.34 DFT Control Register 2 (DFTCTRLREG2)
This register is shown in Figure 2-37 and described in Table 2-51.
Figure 2-37. DFT Control Register 2 (DFTCTRLREG2) (offset = 94h)
31

16
IMPDF[27:12]
R/WP-0

15

4

3

0

IMPDF[11:0]

TEST_MODE_KEY

R/WP-0R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-51. DFT Control Register 2 (DFTCTRLREG2) Field Descriptions
Bit

Field

31-4

IMPDF

3-0

Value

Description
DFT Implementation defined bits.

0

IMPDF is disabled.

1

IMPDF is enabled.

TEST_MODE_KEY

Test mode key. This register is for internal TI use only.
Ah

Register key enable. All the bits can be written to only when the key is enabled.

All other values Register key disable. All bits in this register will maintain their default value and cannot
be written.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

121

System and Peripheral Control Registers

www.ti.com

2.5.1.35 General Purpose Register (GPREG1)
This register is shown in Figure 2-38 and described in Table 2-52.
Figure 2-38. General Purpose Register (GPREG1) (offset = A0h)
31

26

25

20

19

16

Reserved

PLL1_FBSLIP_FILTER_COUNT

PLL1_FBSLIP_FILTER_KEY

R-0

R/WP-0R/WP-5h150Reserved
R-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-52. General Purpose Register (GPREG1) Field Descriptions
Bit

Field

31-26 Reserved
25-20 PLL1_FBSLIP_FILTER_ COUNT

Value
0
0-3Fh

Description
Reads return 0. Writes have no effect.
FBSLIP down counter programmed value.
Configures the system response when a FBSLIP is indicated by the
PLL macro. When PLL1_FBSLIP_FILTER_KEY is not Ah, the down
counter counts from the programmed value on every LPO highfrequency clock once PLL macro indicates FBSLIP. When the countreaches 0, if the synchronized FBSLIP signal is still high, an FBSLIP
condition is indicated to the system module and is captured in the
global status register. When the FBSLIP signal from the PLL macro isde-asserted before the count reaches 0, the counter is reloaded withthe programmed value.
On reset, counter value is 0. Counter must be programmed to a nonzero value and enabled for the filtering to be enabled.

0Filtering is disabled.

1hFiltering is enabled. Every slip is recognized.

2hFiltering is enabled. The slip must be at least 2 HF LPO cycles wide inorder to be recognized as a slip.

:

:

3Fh
19-16 PLL1_FBSLIP_FILTER_ KEY

15-0

122

Reserved

Filtering is enabled. The slip must be at least 63 HF LPO cycles wide inorder to be recognized as a slip.
Enable the FBSLIP filtering.

5h

On reset, the FBSLIP filter is disabled and the FBSLIP passes through.

FhThis is an unsupported value. You should avoid writing this value to thisbit field.

All othervaluesFBSLIP filtering is enabled. Recommended to program Ah in this bit
field. Enabling of the FBSLIP occurs when the KEY is programmed anda non-zero value is present in the COUNT field.

0

Reads return 0. Writes have no effect.

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.36 Imprecise Fault Status Register (IMPFASTS)
The IMPFASTS register, shown in Figure 2-39 and described in Table 2-53, displays information about
imprecise aborts that have occurred.
Figure 2-39. Imprecise Fault Status Register (IMPFASTS) (offset = A8h)
31

24

23

16

Reserved

MASTERID

R-0

R-0

15

9

8

Reserved

10

NCBA

VBUSA

7
Reserved

1

ATYPE

0

R-0

R-0

R-0

R-0

R/WC-0LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset

Table 2-53. Imprecise Fault Status Register (IMPFASTS) Field Descriptions
Bit

Field

Value

31-24

Reserved

0

23-16

MASTERID

0-FFh

Description
Reads return 0. Writes have no effect.
Master ID. This register indicates which master is responsible for the imprecise abort. The master ID
value depends on device implementation- see Table 2-2 for MASTERID values for each bus master.
Notes:• These bits are only updated when an imprecise abort occurs• These bits are cleared to 0 only on power-on reset. The value of these bits remains unchanged after
all other resets.

15-10
9

Reserved

0

NCBA

Reads return 0. Writes have no effect.
Non-cacheable, bufferable abort (NCBA). This register indicates the imprecise abort was generated bya non-cacheable, bufferable write or shared device write through the write buffer of the CPU.
Notes:• This bit is only updated when an imprecise abort generated by a non-cacheable, bufferable write or
shared device write occurs.
• This bit is cleared to 0 only on power-on reset. The value of this register remains unchanged after allother resets.

80

A NCBA is not responsible for the last imprecise abort.

1

A NCBA was written with an illegal address and generated an imprecise abort.

VBUSA

VBUS abort. This register indicates the imprecise abort was generated when writing into the peripheral
frame.
Notes:• This bit is only updated when an imprecise abort is generated when writing into the peripheral frame• This bit is cleared to 0 only on power-on reset. The value of this register remains unchanged after allother resets.

7-1

Reserved

0

ATYPE

0

The peripheral frame did not generate the last imprecise abort.

1

The peripheral frame was written with an illegal address and generated an imprecise abort.

0

Reads return 0. Writes have no effect.
Abort type.This bit indicates to the CPU whether the last abort was an imprecise abort or a precise
abort.
Notes:• This bit is updated after each abort is generated to the CPU.
• This bit is cleared on CPU read.
• This bit is cleared to 0 only on power-on reset. The value of this bit remains unchanged after all otherresets0

The last abort generated was a precise abort. MASTERID, VBUSA, NCBA, and IMPFTADD were not
updated.

1

The last abort generated was an imprecise abort. MASTERID, VBUSA, NCBA, and IMPFTADD were
updated.
Note: Once ATYPE is set, the IMPFAWADD and IMPFASTS bits are not updated by subsequent
ABORT signals.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

123

System and Peripheral Control Registers

www.ti.com

2.5.1.37 Imprecise Fault Address Register (IMPFTADD)
This IMPFTADD register, shown in Figure 2-40 and described in Table 2-54, shows the address at which
an imprecise abort occurred.
Figure 2-40. Imprecise Fault Write Address Register (IMPFTADD) (offset = ACh)31

0
IMPFTADD
R-0

LEGEND: R = Read only; -n = value after reset

Table 2-54. Imprecise Fault Write Address Register (IMPFTADD) Field Descriptions
Bit

Field

Description

31-0

IMPFTADD

These bits contain the fault address when an imprecise abort occurs.
Note: These bits are only updated when an imprecise abort occurs.
Note: These bits are cleared to 0 only on power-on reset. The value of this register remains unchanged
after all other resets.

124

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.38 System Software Interrupt Request 1 Register (SSIR1)
The SSIR1 register, shown in Figure 2-41 and described in Table 2-55, is used for software interrupt
generation.
NOTE: This register is mirrored at offset FCh for compatibility reasons.

Figure 2-41. System Software Interrupt Request 1 Register (SSIR1) (offset = B0h)
31

16
Reserved
R-0

15

8

7

0

SSKEY1SSDATA1

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-55. System Software Interrupt Request 1 Register (SSIR1) Field Descriptions
Bit

Field

31-16

Reserved

Value
0

Description

15-8

SSKEY10-FFh

System software interrupt request key. A 075h written to these bits initiates IRQ/FIQ interrupts.
Data in this field is always read as 0. The SSKEY1 field can be written into only if the write data
matches the key (75h). The SSDATA1 field can only be written into if the write data into this field,
the SSKEY1 field, matches the key (75h).

7-0

SSDATA1

0-FFh

System software interrupt data. These bits contain user read/write register bits. They may be usedby the application software as different entry points for the interrupt routine. The SSDATA1 fieldcannot be written into unless the write data into the SSKEY1 field matches the key (75h);
therefore, byte writes cannot be performed on the SSDATA1 field.

Reads return 0. Writes have no effect.

2.5.1.39 System Software Interrupt Request 2 Register (SSIR2)The SSIR2 register, shown in Figure 2-42 and described in Table 2-56, is used for software interrupt
generation.
Figure 2-42. System Software Interrupt Request 2 Register (SSIR2) (offset = B4h)
31

16
Reserved
R-0

15

8

7

0

SSKEY2SSDATA2

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-56. System Software Interrupt Request 2 Register (SSIR2) Field Descriptions
Bit

Field

31-16

Reserved

Value
0

Description

15-8

SSKEY20-FFh

System software interrupt2 request key. A 84h written to these bits initiates IRQ/FIQ interrupts.
Data in this field is always read as 0. The SSKEY2 field can be written into only if the write data
matches the key (84h). The SSDATA2 field can only be written into if the write data into this field,
the SSKEY2 field, matches the key (84h).

7-0

SSDATA2

0-FFh

System software interrupt data. These bits contain user read/write register bits. They may be usedby the application software as different entry points for the interrupt routine. The SSDATA2 fieldcannot be written into unless the write data into the SSKEY2 field matches the key (84h);
therefore, byte writes cannot be performed on the SSDATA2 field.

Reads return 0. Writes have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

125

System and Peripheral Control Registers

www.ti.com

2.5.1.40 System Software Interrupt Request 3 Register (SSIR3)
The SSIR3 register, shown in Figure 2-43 and described in Table 2-57, is used for software interrupt
generation.
Figure 2-43. System Software Interrupt Request 3 Register (SSIR3) (offset = B8h)31

16
Reserved
R-0

15

8

7

0

SSKEY3SSDATA3

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-57. System Software Interrupt Request 3 Register (SSIR3) Field Descriptions
Bit

Field

Value

Description

31-16

Reserved

015-8

SSKEY30-FFh

System software interrupt request key. A 93h written to these bits initiates IRQ/FIQ interrupts. Datain this field is always read as 0. The SSKEY3 field can be written into only if the write data
matches the key (93h). The SSDATA3 field can only be written into if the write data into this field,
the SSKEY3 field, matches the key (93h).

7-0

SSDATA3

0-FFh

System software interrupt data. These bits contain user read/write register bits. They may be usedby the application software as different entry points for the interrupt routine. The SSDATA3 fieldcannot be written into unless the write data into the SSKEY3 field matches the key (93h);
therefore, byte writes cannot be performed on the SSDATA3 field.

Reads return 0. Writes have no effect.

2.5.1.41 System Software Interrupt Request 4 Register (SSIR4)The SSIR4 register, shown in Figure 2-44 and described in Table 2-58, is used for software interrupt
generation.
Figure 2-44. System Software Interrupt Request 4 Register (SSIR4) (offset = BCh)
31

16
Reserved
R-0

15

8

7

0

SSKEY4SSDATA4

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-58. System Software Interrupt Request 4 Register (SSIR4) Field Descriptions
Bit

Field

31-16

Reserved

015-8

SSKEY40-FFh

System software interrupt2 request key. A A2h written to these bits initiates IRQ/FIQ interrupts.
Data in this field is always read as 0. The SSKEY4 field can be written into only if the write data
matches the key (A2h). The SSDATA4 field can only be written into if the write data into this field,
the SSKEY4 field, matches the key (A2h).

7-0

SSDATA4

0-FFh

System software interrupt data. These bits contain user read/write register bits. They may be usedby the application software as different entry points for the interrupt routine. The SSDATA4 fieldcannot be written into unless the write data into the SSKEY4 field matches the key (A2h);
therefore, byte writes cannot be performed on the SSDATA4 field.

126

Value

Description
Reads return 0. Writes have no effect.

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.42 RAM Control Register (RAMGCR)
The RAMGCR register, shown in Figure 2-45 and described in Table 2-59, is used to configure eSRAM
data and address wait states.
NOTE: The RAM_DFT_EN bits are for TI internal use only.
The contents of the RAM_DFT_EN field should not be changed.

Figure 2-45. RAM Control Register (RAMGCR) (offset = C0h)
31

20

19

16

Reserved

RAM_DFT_EN

R-0

R/WP-5h15

8Reserved
R-0

7

2

1

0

Reserved3

WST_AENA0

Reserved

WST_DENA0

R-0

R/WP-0R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-59. RAM Control Register (RAMGCR) Field Descriptions
Bit

Field

31-20 Reserved

Value
0

19-16 RAM_DFT_EN

Description
Reads return 0. Writes have no effect.
Functional mode RAM DFT (Design For Test) port enable key.
Note: For TI internal use only.

Ah

RAM DFT port is enabled.

All other values RAM DFT port is disabled.
Note: It is recommended that a value of 5h be used to disable the RAM DFT port.
This value will give maximum protection from a bit flip inducing event thatwould inadvertently enable the controller.
15-3
2

Reserved

0

WST_AENA0

1

Reserved

0

WST_DENA0

Reads return 0. Writes have no effect.
eSRAM data phase wait state enable bit.

0

The default address setup time for eSRAM0 is used.

1

The eSRAM address setup time is increased by one HCLK cycle.

0

Reads return 0. Writes have no effect.
eSRAM data phase wait state enable bit.

0

There are no wait states for eSRAM during the data phase.

1

The eSRAM data phase setup time is increased by one HCLK cycle.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

127

System and Peripheral Control Registers

www.ti.com

2.5.1.43 Bus Matrix Module Control Register 1 (BMMCR1)
The BMMCR1 register, shown in Figure 2-46 and described in Table 2-60, allows RAM and Program(Flash) memory addresses to be swapped.
Figure 2-46. Bus Matrix Module Control Register 1 (BMMCR) (offset = C4h)31

16
Reserved
R-0

15

4

3

0

Reserved

MEMSW

R-0

R/WP-AhLEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-60. Bus Matrix Module Control Register 1 (BMMCR) Field Descriptions
Bit

Field

31-4

Reserved

3-0

MEMSW

Value
0

Description
Reads return 0. Writes have no effect.
Memory swap key.
Note: A CPU reset must be issued after the memory swap key has been changed for the
memory swap to occur. A CPU reset can be initiated by changing the state of the CPU
RESET bit in the CPURSTCR register.

5h

Swapped memory-map:
eSRAM starts at address 0. Program memory (Flash) starts at address 800 0000h.

Ah

Default memory-map:
Program memory (Flash) starts at address 0. eSRAM starts at address 800 0000h.

All other values

128

The device memory-map is unchanged.

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.44

CPU Reset Control Register (CPURSTCR)

The CPURSTCR register shown in Figure 2-47 and described in Table 2-61 allows a reset to the CortexR4 CPU to be generated.
NOTE: The register bits in CPURSTCR are designated as high-integrity bits and have been
implemented with error-correcting logic such that each bit, although read and written as asingle bit, is actually a multi-bit key with error correction capability. As such, single-bit flips
within the “key” can be corrected allowing protection of the system as a whole. An error
detected is signaled to the ESM module.

Figure 2-47. CPU Reset Control Register (CPURSTCR) (offset = CCh)
31

16
Reserved
R-0

15

1

0

Reserved

CPU_RESET

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-61. CPU Reset Control Register (CPURSTGCR) Field Descriptions
Bit

Field

31-1

Reserved

0

Reads return 0. Writes have no effect.

CPU_RESET

0-1

CPU Reset.

0

Value

Description

Only the CPU is reset whenever this bit is toggled. There is no system reset.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

129

System and Peripheral Control Registers

www.ti.com

2.5.1.45 Clock Control Register (CLKCNTL)The CLKCNTL register, shown in Figure 2-48 and described in Table 2-62, controls peripheral reset andthe peripheral clock divide ratios.
NOTE: VCLK and VCLK2 clock ratio restrictions.
The VCLK2 frequency must always be greater than or equal to the VCLK frequency. The
VCLK2 frequency must be an integer multiple of the VCLK frequency.
In addition, the VCLK and VCLK2 clock ratios must not be changed simultaneously. Whenincreasing the frequency (decreasing the divider), first change the VCLK2R field and thenchange the VCLKR field. When reducing the frequency (increasing the divider), first change
the VCLKR field and then change the VCLK2R field.
You should do a read-back between the two writes. This assures that there are enough clock
cycles between the two writes.

Figure 2-48. Clock Control Register (CLKCNTRL) (offset = D0h)
31

28

27

24

23

20

19

16

ReservedVCLK2R

Reserved

VCLKR

R-0

R/WP-1h

R-0

R/WP-1h

15

9

8

7

0

Reserved

PENA

Reserved

R-0

R/WP-0

R-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-62. Clock Control Register (CLKCNTRL) Field Descriptions
Bit

Field

31-28

Reserved

27-24

VCLK2R

Value
0

Description
Reads return 0. Writes have no effect.
VBUS clock2 ratio.
Note: The VCLK2 frequency must always be greater than or equal to the VCLK frequency. The
VCLK2 frequency must be an integer multiple of the VCLK frequency. In addition, the VCLK and
VCLK2 clock ratios must not be changed simultaneously.

0

The VCLK2 speed is HCLK divided by 1.

1

The VCLK2 speed is HCLK divided by 2.

2h-Fh
23-20

Reserved

19-16

VCLKR

0

Reserved
Reads return 0. Writes have no effect.
VBUS clock ratio.
Note: The VCLK2 frequency must always be greater than or equal to the VCLK frequency. The
VCLK2 frequency must be an integer multiple of the VCLK frequency. In addition, the VCLK and
VCLK2 clock ratios must not be changed simultaneously.

0

The VCLK speed is HCLK divided by 1.

1

The VCLK speed is HCLK divided by 2.

2h-Fh
15-9
8

7-0

130

Reserved

0

PENA

Reserved

Reserved
Reads return 0. Writes have no effect.
Peripheral enable bit. The application must set this bit before accessing any peripheral0

The global peripheral/peripheral memory frames are in reset.

1

All peripheral/peripheral memory frames are out of reset.

0

Reads return 0. Writes have no effect.

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.46 ECP Control Register (ECPCNTL)
The ECP register, shown in Figure 2-49 and described in Table 2-63, configures the ECLK pin infunctional mode.
NOTE: ECLK Functional mode configuration.
The ECLK pin must be placed into Functional mode by setting the ECPCLKFUN bit to 1 in
the SYSPC1 register before a clock source will be visible on the ECLK pin.

Figure 2-49. ECP Control Register (ECPCNTL) (offset = D4h)
31

24

23

Reserved

25

ECPSSELECPCOS

22
Reserved

18

ECPINSEL

17

R-0

R/W-0

R/W-0

R-0

R/W-0

15

16

0
ECPDIV
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-63. ECP Control Register (ECPCNTL) Field Descriptions
Bit

Field

31-25

Reserved

24

ECPSSEL

Value
0

Description
Reads return 0. Writes have no effect.
This bit allows the selection between VCLK and OSCIN as the clock source for ECLK.
Note: Other ECLK clock sources are available for debug purposes by configuring the
CLKTEST register.

23

0

VCLK is selected as the ECP clock source.

1

OSCIN is selected as the ECP clock source.

ECPCOSECP continue on suspend.
Note: Suspend mode is entered while performing certain JTAG debugging operations.

22-18

Reserved

17-16

ECPINSEL

15-0

ECPDIV0ECLK output is disabled in suspend mode. ECLK output will be shut off and will not be seen on
the I/O pin of the device.

1

ECLK output is not disabled in suspend mode. ECLK output will not be shut off and will be seenon the I/O pin of the device.

0

Reads return 0. Writes have no effect.
Select ECP input clock source.

0

Tied Low

1h

HCLK

2h

External clock

3h

Tied Low

0-FFFFh

ECP divider value. The value of ECPDIV bits determine the external clock (ECP clock) frequency
as a ratio of VBUS clock or OSCIN as shown in the formula:

ECLK =V C L K o rO S C I N(E C P D IV + 1 )SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

131

System and Peripheral Control Registers

www.ti.com

2.5.1.47 DEV Parity Control Register 1 (DEVCR1)
This register is shown in Figure 2-50 and described in Table 2-64.
Figure 2-50. DEV Parity Control Register 1 (DEVCR1) (offset = DCh)
31

16
Reserved
R-0

15

4

3

0

Reserved

DEVPARSEL

R-0

R/WP-AhLEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-64. DEV Parity Control Register 1 (DEVCR1) Field Descriptions
Bit

Field

31-4

Reserved

Value

3-0

DEVPARSEL

0

Description
Reads return 0. Writes have no effect.
Device parity select bit key.
Note: After an odd (DEVPARSEL = 5h) or even (DEVPARSEL = Ah) scheme is programmed
into the DEVPARSEL register, any one bit change can be detected and will retain its
programmed scheme. More than one bit changes in DEVPARSEL will cause a default to odd
parity scheme.

5h

The device parity is even.

Ah

The device parity is odd.

2.5.1.48 System Exception Control Register (SYSECR)The SYSECR register, shown in Figure 2-51 and described in Table 2-65, is used to generate a software
reset.
NOTE: The register bits in SYSECR are designated as high-integrity bits and have been
implemented with error-correcting logic such that each bit, although read and written as asingle bit, is actually a multi-bit key with error correction capability. As such, single-bit flips
within the “key” can be corrected allowing protection of the system as a whole. An error
detected is signaled to the ESM module.

Figure 2-51. System Exception Control Register (SYSECR) (offset = E0h)
31

16
Reserved
R-0

15

14

RESET1RESET013
Reserved

0

R/WP-0R/WP-1

R-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-65. System Exception Control Register (SYSECR) Field Descriptions
Bit

Field

31-16

Reserved

15-14

RESET

Value
0

0, 2h-3h132

Reserved

Reads return 0. Writes have no effect.
Software reset bits. Setting RESET1 or clearing RESET0 causes a system software reset.

1h
13-0

Description0

No reset will occur.
A global system reset will occur.
Reads return 0. Writes have no effect.

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.49 System Exception Status Register (SYSESR)The SYSESR register, shown in Figure 2-52 and described in Table 2-66, shows the source for different
resets encountered. Previous reset source status bits are not automatically cleared if new resets occur.
After reading this register, the software should clear any flags that are set so that the source of future
resets can be determined. Any bit in this register can be cleared by writing a 1 to the bit.
Figure 2-52. System Exception Status Register (SYSESR) (offset = E4h)31

16
Reserved
R-0
15

14

13

PORST

OSCRST

WDRST

12
Reserved

R/WC-X

R/WC-X*

R/WC-X*

R-0

7

6

5

4

8

3

2

0

Reserved

CPURSTSWRSTEXTRST

Reserved

R-0

R/WC-X*

R/WC-X*

R/WC-X*

R-0

LEGEND: R/W = Read/Write; R = Read only; C= Clear; X = value unchanged after reset; X* = 0 after PORST but unchanged after otherresets; -n = value after reset; -n = value after reset

Table 2-66. System Exception Status Register (SYSESR) Field Descriptions
Bit

Field

31-16

Reserved

15

PORST

14

Value
0

Description
Reads return 0. Writes have no effect.
Power-on reset. This bit is set when a power-on reset occurs, either internally asserted by the VMON orexternally asserted by the nPORRST pin.

0

No power-on reset has occurred since this bit was last cleared.

1

A reset was caused by a power-on reset. (This bit should be cleared after being read so that
subsequent resets can be properly identified as not being power-on resets.)

OSCRST

Reset caused by an oscillator failure or PLL cycle slip. This bit is set when a reset is caused by an
oscillator failure or PLL slip.
Note: The action taken when an oscillator failure or PLL slip is detected must configured in the
PLLCTL1 register.

13

0

No reset has occurred due to an oscillator failure or a PLL cycle slip.

1

A reset was caused by an oscillator failure or a PLL cycle slip.

WDRST

Watchdog reset flag. This bit is set when the last reset was caused by the digital watchdog (DWD).
During debugging, the ICEPICK logic implemented on the microcontroller also allows a system reset tobe generated via the debug logic (DBGRST). This DBGRST reset is also indicated on the WDRST bit of
the SYSESR. This flag can also be set via a reset driven by ICEPICK.

12-6

Reserved

5

CPURST0

No reset has occurred because of the DWD.

1

A reset was caused by the DWD.

0

Reads return 0. Writes have no effect.
CPU reset flag. This bit is set when the CPU is reset.
Note: A CPU reset can be initiated by the CPU self-test controller (LBIST) or by changing thememory protection (MMU/MPU) configuration in CPURSTCR register.

40

No CPU reset has occurred.

1

A CPU reset occurred.

SWRST

Software reset flag. This bit is set when a software system reset has occurred.
Note: A software system reset can be initiated by writing to the RESET bits in the SYSECR
register.
0

No software reset has occurred.

1

A software reset occurred.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

133

System and Peripheral Control Registers

www.ti.com

Table 2-66. System Exception Status Register (SYSESR) Field Descriptions (continued)
Bit

Field

3

EXTRST

2-0

Reserved

Value

Description
External reset flag. This bit is set when a reset is caused by the external reset pin nRST or by any resetthat also asserts the nRST pin (PORST, OSCRST, WDRST and SWRST).

0

The external reset pin has not asserted a reset.

1

A reset has been caused by the external reset pin.

0

Reads return 0. Writes have no effect.

2.5.1.50 System Test Abort Status Register (SYSTASR)This register is shown in Figure 2-53 and described in Table 2-67.
Figure 2-53. System Test Abort Status Register (SYSTASR) (offset = E8h)31

16
Reserved
R-0

15

5

4

0

Reserved

EFUSE_Abort

R-0

R/WCP-X/0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; C = Clear; -X = Value unchanged after reset; -n = value
after reset

Table 2-67. System Test Abort Status Register (SYSTASR) Field Descriptions
Bit

Field

31-5

Reserved

4-0

EFUSE_Abort

Value
0

Reads return 0. Writes have no effect.
Test Abort status flag. These bits are set when test abort occurred:0

Read: The last operation (if any) completed successfully. This is also the value that theerror/status register is set to after reset.

1h

Read: Controller times out because there is no last row sent from the FuseROM.

2h

Read: The autoload machine was started, either through the SYS_INITZ signal from thesystem or the JTAG data register. In either case, the autoload machine did not findenough FuseROM data to fill the scan chain.

3hRead: The autoload machine was started, either through the SYS_INITZ signal from thesystem or the JTAG data register. In either case, the autoload machine starts the scanchain with a signature it expects to see after the scan chain is full. The autoload machine
was able to fill the scan chain, but the wrong signature was returned.

4h

Read: The autoload machine was started, either through the SYS_INITZ signal from thesystem or the JTAG data register. In either case, the autoload machine was not able or
not allowed to complete its operation.

All other values
1Fh

134

Description

Read: Reserved.
Write: These bits are cleared to 0.

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.51 Global Status Register (GLBSTAT)The GLBSTAT register, shown in Figure 2-54 and described in Table 2-68, indicates the FMzPLL (PLL1)
slip status and the oscillator fail status.
NOTE: PLL and OSC fail behavior
The device behavior after a PLL slip or an oscillator failure is configured in the PLLCTL1
register.

Figure 2-54. Global Status Register (GLBSTAT) [offset = ECh]
31

16
Reserved
R-0

15

9

8

Reserved

10

FBSLIPRFSLIP

7
Reserved

1

OSCFAIL

0

R-0

R/W1C-n

R/W1C-n

R-0

R/W1C-nLEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to Clear; -n = value after reset

Table 2-68. Global Status Register (GLBSTAT) Field Descriptions
Bit

Field

31-10

Reserved

9

FBSLIP

Value
0

Description
Reads return 0. Writes have no effect.
PLL over cycle slip detection. (cleared by nPORRST, maintains its previous value for all other resets)

0

Read: No PLL over cycle slip has been detected.
Write: The bit is unchanged.

1

Read: A PLL over cycle slip has been detected.
Write: The bit is cleared to 0.

8

RFSLIP

PLL under cycle slip detection. (cleared by nPORRST, maintains its previous value for all other resets)
0

Read: No PLL under cycle slip has been detected.
Write: The bit is unchanged.

1

Read: A PLL under cycle slip has been detected.
Write: The bit is cleared to 0.

7-1

Reserved

0

OSCFAIL

0

Reads return 0. Writes have no effect.
Oscillator fail flag bit. (cleared by nPORRST, maintains its previous value for all other resets)

0

Read: No oscillator failure has been detected.
Write: The bit is unchanged.

1

Read: An oscillator failure has been detected.
Write: The bit is cleared to 0.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

135

System and Peripheral Control Registers

www.ti.com

2.5.1.52 Device Identification Register (DEVID)
The DEVID is a read-only register. It contains device-specific information that is hard-coded during device
manufacture. For the initial silicon version, the device identification code value is 0x8048AD05. This
register is shown in Figure 2-55 and described in Table 2-69.
Figure 2-55. Device Identification Register (DEVID) (offset = F0h)
31

30

17

16

CP15

UNIQUE_ID

TECH

R-K

R-K

R-K

15

12

11

TECH

13

IO_VOLTAGEPERIPHERAL_PARITYFLASH_ECC

RAM_ECC

R-K

R-K

R-K

R-K

R-K

7

10

3

9

8

2

0

VERSION

PLATFORM_ID

R-K

R-K

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -K = constant value

Table 2-69. Device Identification Register (DEVID) Field Descriptions
Bit

Field

31

CP15

30-17 UNIQUE_ID

Value

CP15 CPU. This bit indicates whether the CPU has a coprocessor 15 (CP15).
0

The CPU has no CP15 present.

1

The CPU has a CP15 present. The CPU ID can be read using the CP15 C0,C0,0
register.

0-3FFFh

16-13 TECH

11

10-9

8

0

Device manufactured in the C05 process technology.

1hDevice manufactured in the F05 process technology.

2hDevice manufactured in the C035 process technology.

3hDevice manufactured in the F035 process technology.

4hDevice manufactured in the C021 process technology.

5hDevice manufactured in the F021 process technology.

IO_VOLTAGE

The I/O voltage is 3.3 V.

1The I/O voltage is 5 V.
Peripheral parity. This bit indicates whether or not peripheral memory parity ispresent.

0

The peripheral memories have no parity.

1

The peripheral memories have parity.
These bits indicate which parity is present for the program memory.

0

No memory protection is present.

1h

The program memory (Flash) has single-bit parity.

2h

The program memory (Flash) has ECC.

3h

Reserved

RAM_ECC

2-0

PLATFORM_ID

136

Input/output voltage. This bit defines the I/O voltage of the device.

FLASH_ECC

VERSION

Reserved

0
PERIPHERAL_PARITY

7-3

Device ID. The device ID is unique by device configuration.
These bits define the process technology by which the device was manufactured.

6h-Fh
12

Description

RAM ECC. This bit indicates whether or not RAM memory ECC is present.
0

The RAM memories do not have ECC.

1The RAM memories have ECC.

0-1Fh
5h

Version. These bits provide the revision of the device.
The device is part of the TMS570 family. The TMS570 ID is always 5h.

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.1.53 Software Interrupt Vector Register (SSIVEC)The SSIVEC register, shown in Figure 2-56 and described in Table 2-70, contains information about
software interrupts.
Figure 2-56. Software Interrupt Vector Register (SSIVEC) (offset = F4h)
31

16
Reserved
R-0

15

8

7

0

SSIDATA

SSIVECT

R-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-70. Software Interrupt Vector Register (SSIVEC) Field Descriptions
Bit

Field

Value

31-16

Reserved

0

15-8

SSIDATA

0-FFh

7-0

SSIVECT

Description
Reads return 0. Writes have no effect.
System software interrupt data key. These bits contain the data key value of the source for thesystem software interrupt, which is indicated by the vector in the SSIVEC[7-0] field.
These bits contain the source for the system software interrupt.
Note: A read from the SSIVECT bits clears the corresponding SSI_FLAG[4-1] bit in the
SSIF register, corresponding to the source vector of the system software interrupt.
Note: The SSIR[4-1] interrupt has the following priority order:
SSIR1 has the highest priority.
SSIR4 has the lowest priority.

0

No software interrupt is pending.

1h

A software interrupt has been generated by writing the correct key value to The SSIR1 register.

2h

A software interrupt has been generated by writing the correct key value to The SSIR2 register.

3h

A software interrupt has been generated by writing the correct key value to The SSIR3 register.

4h

A software interrupt has been generated by writing the correct key value to The SSIR4 register.

5h-FFhReserved

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

137

System and Peripheral Control Registers

www.ti.com

2.5.1.54 System Software Interrupt Flag Register (SSIF)The SSIF register, shown in Figure 2-57 and described in Table 2-71, contains software interrupt flag
status information.
Figure 2-57. System Software Interrupt Flag Register (SSIF) (offset = F8h)
31

16
Reserved
R-0
15

8
Reserved
R-0

7

3

2

1

0

Reserved

4

SSI_FLAG4

SSI_FLAG3

SSI_FLAG2

SSI_FLAG1

R-0

R/W1C-0

R/W1C-0

R/W1C-0

R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset

Table 2-71. System Software Interrupt Flag Register (SSIF) Field Descriptions
Bit

Field

31-4

Reserved

3-0

SSI_FLAG[4-1]

Value
0

Description
Reads return 0. Writes have no effect.
System software interrupt flag[4-1]. This flag is set when the correct SSKEY is written to the
SSIR register[4-1].
Note: A read from the SSIVEC register clears the corresponding SSI_FLAG[4-1] bit in the
SSIF, corresponding to the source vector of the system software interrupt.

0

Read: No IRQ/FIQ interrupt was generated since the bit was last cleared.
Write: The bit is unchanged.

1

Read: An IRQ/FIQ interrupt was generated.
Write: The bit is cleared to 0.

138

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.2 Secondary System Control Registers (SYS2)This section describes the secondary frame of system registers. The start address of the secondary
system module frame is FFFF E100. The registers support 32-, 16-, and 8-bit writes. The offset is relative
to the system module frame start address.
Table 2-72 lists the secondary system control registers.
NOTE: All additional registers in the secondary system frame are reserved.

Table 2-72. Secondary System Control Registers

2.5.2.1

OffsetAcronym

Register Description

Section08h

STCCLKDIV

CPU Logic BIST Clock Divider

Section 2.5.2.1

70h

CLKSLIPClock Slip Register

Section 2.5.2.2

ECh

EFC_CTLREG

EFUSE Controller Control Register

Section 2.5.2.3

F0h

DIEIDL_REG0

Die Identification Register Lower Word

Section 2.5.2.4

F4h

DIEIDH_REG1

Die Identification Register Upper Word

Section 2.5.2.5

F8h

DIEIDL_REG2

Die Identification Register Lower Word

Section 2.5.2.6

FCh

DIEIDH_REG3

Die Identification Register Upper Word

Section 2.5.2.7

CPU Logic Bist Clock Divider (STCLKDIV)This register is shown in Figure 2-58 and described in Table 2-73.
Figure 2-58. CPU Logic BIST Clock Prescaler (STCLKDIV) (offset = 08h)
31

27

26

24

23

16

Reserved

CLKDIV

Reserved

R-0

R/WP-0R-0

15

0Reserved
R-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-73. CPU Logic BIST Clock Prescaler (STCLKDIV) Field Descriptions
Bit

Field

31-27

Reserved

26-24

CLKDIV

23-0

Reserved

Value
0

Description
Reads return 0. Writes have no effect.
Clock divider/prescaler for CPU clock (GCLK) during logic BIST0STCCLK = HCLK/1

1h

STCCLK = HCLK/22h

STCCLK = HCLK/3

:

:

7h

STCCLK = HCLK/80

Reads return 0. Writes have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

139

System and Peripheral Control Registers

2.5.2.2

www.ti.com

Clock Slip Register (CLKSLIP)This register is shown in Figure 2-59 and described in Table 2-74.
Figure 2-59. Clock Slip Register (CLKSLIP) (offset = 70h)
31

16
Reserved
R-0

15

14

13

8

7

4

3

0

Reserved

PLL1_SLIP_FILTER_COUNT

Reserved

PLL1_SLIP_FILTER_KEY

R-0

R/WP-0R-0

R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-74. Clock Slip Register (CLKSLIP) Field Descriptions
Bit

Field

31-14 Reserved
13-8

Value
0

PLL1_SLIP_FILTER_COUNT

Description
Reads return 0. Writes have no effect.
PLL SLIP down counter programmed value. Count is on 10M clock.
On reset, counter value is 0. Counter must be programmed to a non-zerovalue and enabled for the filtering to be enabled.

7-4

Reserved

3-0

PLL1_SLIP_FILTER_KEY

140

0

Filtering is disabled.

1hFiltering is enabled. Every slip is recognized.

2hFiltering is enabled. The slip must be at least 2 HF LPO cycles wide in order
to be recognized as a slip.

:

:

3Fh

Filtering is enabled. The slip must be at least 63 HF LPO cycles wide in order
to be recognized as a slip.

0

Reads return 0. Writes have no effect.
Enable the PLL SLIP filtering.

5h

On reset, the PLL SLIP filter is disabled and the PLL SLIP passes through.

FhThis is an unsupported value. You should avoid writing this value to this bit
field.

All other values

PLL SLIP filtering is enabled. Recommended to program Ah in this bit field.
Enabling of the PLL SLIP occurs when the KEY is programmed and anonzero value is present in the COUNT field.

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.2.3

EFUSE Controller Control Register (EFC_CTLREG)This register is shown in Figure 2-60 and described in Table 2-75.
Figure 2-60. EFUSE Controller Control Register (EFC_CTLREG) (offset = ECh)
31

16
Reserved
R-0

15

4

3

0

Reserved

EFC_INSTR_WEN

R-0

R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-75. EFUSE Controller Control Register (EFC_CTLREG) Field Descriptions
Bit

Field

31-4

Reserved

Value

3-0

EFC_INSTR_WEN

0

Description
Reads return 0. Writes have no effect.
Enable user write of 4 EFUSE controller instructions.
SYS module generates the enable signal which will be tied to
OCP_FROM_WRITE_DISABLE on efuse controller port

AhWriting of instructions (Program, ProgramCRA, RunAutoload, andLoadFuseScanchain) to EFC is allowed enabled.

All other values Writing of instructions (Program, ProgramCRA, RunAutoload, andLoadFuseScanchain) in EFC registers is blocked.

2.5.2.4

Die Identification Register Lower Word (DIEIDL_REG0)

The DIEIDL_REG0 register is a duplicate of the DIEIDL register, see Section 2.5.1.29. The DIEIDL_REG0
register, shown in Figure 2-61 and described in Table 2-76, contains information about the die wafer
number, and X, Y wafer coordinates.
Figure 2-61. Die Identification Register, Lower Word (DIEIDL_REG0) [offset = F0h]
31

24

15

23

16

WAFER #Y WAFER COORDINATE

R-D

R-D

12

11

0

Y WAFER COORDINATEX WAFER COORDINATE

R-D

R-D

LEGEND: R = Read only; -n = value after reset; -D = device specific

Table 2-76. Die Identification Register, Lower Word (DIEIDL_REG0) Field Descriptions
Bit

Field

Description

31-24

WAFER #

These read-only bits contain the wafer number of the device.

23-12

Y WAFER COORDINATE

These read-only bits contain the Y wafer coordinate of the device.

11-0

X WAFER COORDINATE

These read-only bits contain the X wafer coordinate of the device.

NOTE: Die Identification Information
The die identification information will vary from unit to unit. This information is programmed
by TI as part of the initial device test procedure.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

141

System and Peripheral Control Registers

2.5.2.5

www.ti.com

Die Identification Register Upper Word (DIEIDH_REG1)

The DIEIDH_REG1 register is a duplicate of the DIEIDH register, see Section 2.5.1.30. The
DIEIDH_REG1 register, shown in Figure 2-62 and described in Table 2-77, contains information about thedie lot number.
Figure 2-62. Die Identification Register, Upper Word (DIEIDH_REG1) [offset = F4h]
31

24

23

16

Reserved

LOT #

R-0

R-D

15

0
LOT #
R-D

LEGEND: R/W = Read/Write; R = Read only; D = Value is device dependent; -n = value after reset

Table 2-77. Die Identification Register, Upper Word (DIEIDH_REG1) Field Descriptions
Bit

Field

Description

31-24

Reserved

Reserved for TI use. Writes have no effect.

23-0

LOT #

This read-only register contains the device lot number.

NOTE: Die Identification Information
The die identification information will vary from unit to unit. This information is programmed
by TI as part of the initial device test procedure.

2.5.2.6

Die Identification Register Lower Word (DIEIDL_REG2)

This register is shown in Figure 2-63 and described in Table 2-78.
Figure 2-63. Die Identification Register, Lower Word (DIEIDL_REG2) [offset = F8h]
310
DIEIDL2
R-X

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -X = Value unchanged after reset

Table 2-78. Die Identification Register, Lower Word (DIEIDL_REG2) Field Descriptions
Bit

Field

31-0

DIEIDL2(95-64)

142

Value
0-FFFF FFFFh

Description
This read-only register contains the lower word (95:64) of the die ID information. The
contents of this register is reserved.

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.2.7

Die Identification Register Upper Word (DIEIDH_REG3)

This register is shown in Figure 2-64 and described in Table 2-79.
Figure 2-64. Die Identification Register, Upper Word (DIEIDH_REG3) [offset = FCh]
31

0
DIEIDH2
R-X

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -X = Value unchanged after reset

Table 2-79. Die Identification Register, Upper Word (DIEIDH_REG3) Field Descriptions
Bit

Field

31-0

DIEIDH2(127-96)

Value

Description

0-FFFF FFFFh

This read-only register contains the upper word (127:97) of the die ID information. The
contents of this register is reserved.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

143

System and Peripheral Control Registers

www.ti.com

2.5.3 Peripheral Central Resource (PCR) Control Registers
This section describes the Peripheral Central Resource (PCR) control registers. The start address of the
PCR register frame is FFFF E000h. Table 2-80 lists the registers in the PCR, which are used to configure
protection to the peripherals in PCS and PS regions. Not all chip selects exist on this device.
Table 2-80. Peripheral Central Resource Control Registers

144

OffsetAcronym

Register Description

Section00h

PMPROTSET0

Peripheral Memory Protection Set Register 0

Section 2.5.3.1

04h

PMPROTSET1

Peripheral Memory Protection Set Register 1

Section 2.5.3.2

10h

PMPROTCLR0

Peripheral Memory Protection Clear Register 0

Section 2.5.3.3

14h

PMPROTCLR1

Peripheral Memory Protection Clear Register 1

Section 2.5.3.4

20h

PPROTSET0

Peripheral Protection Set Register 0

Section 2.5.3.5

24h

PPROTSET1

Peripheral Protection Set Register 1

Section 2.5.3.6

28h

PPROTSET2

Peripheral Protection Set Register 2

Section 2.5.3.7

2Ch

PPROTSET3

Peripheral Protection Set Register 3

Section 2.5.3.8

40h

PPROTCLR0

Peripheral Protection Clear Register 0

Section 2.5.3.9

44h

PPROTCLR1

Peripheral Protection Clear Register 1

Section 2.5.3.10

48h

PPROTCLR2

Peripheral Protection Clear Register 2

Section 2.5.3.11

4Ch

PPROTCLR3

Peripheral Protection Clear Register 3

Section 2.5.3.12

60h

PCSPWRDWNSET0

Peripheral Memory Power-Down Set Register 0

Section 2.5.3.13

64h

PCSPWRDWNSET1

Peripheral Memory Power-Down Set Register 1

Section 2.5.3.14

70h

PCSPWRDWNCLR0

Peripheral Memory Power-Down Clear Register 0

Section 2.5.3.15

74h

PCSPWRDWNCLR1

Peripheral Memory Power-Down Clear Register 1

Section 2.5.3.16

80h

PSPWRDWNSET0

Peripheral Power-Down Set Register 0

Section 2.5.3.17

84h

PSPWRDWNSET1

Peripheral Power-Down Set Register 1

Section 2.5.3.18

88h

PSPWRDWNSET2

Peripheral Power-Down Set Register 2

Section 2.5.3.19

8Ch

PSPWRDWNSET3

Peripheral Power-Down Set Register 3

Section 2.5.3.20

A0h

PSPWRDWNCLR0

Peripheral Power-Down Clear Register 0

Section 2.5.3.21

A4h

PSPWRDWNCLR1

Peripheral Power-Down Clear Register 1

Section 2.5.3.22

A8h

PSPWRDWNCLR2

Peripheral Power-Down Clear Register 2

Section 2.5.3.23

ACh

PSPWRDWNCLR3

Peripheral Power-Down Clear Register 3

Section 2.5.3.24

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.3.1

Peripheral Memory Protection Set Register 0 (PMPROTSET0)

This register is shown in Figure 2-65 and described in Table 2-81.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-65. Peripheral Memory Protection Set Register 0 (PMPROTSET0) (offset = 00h)31

0PCS[31-0]PROTSET
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-81. Peripheral Memory Protection Set Register 0 (PMPROTSET0) Field Descriptions
Bit

Field

31-0

PCS[31-0]PROTSET

Value

Description
Peripheral memory frame protection set.

0

Read: The peripheral memory framen can be written to and read from in both user andprivileged modes.
Write: The bit is unchanged.

1

Read: The peripheral memory framen can be written to only in privileged mode, but it
can be read in both user and privileged modes.
Write: The corresponding bit in PMPROTSET0 and PMPROTCLR0 registers is set to 1.

2.5.3.2

Peripheral Memory Protection Set Register 1 (PMPROTSET1)

This register is shown in Figure 2-66 and described in Table 2-82.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-66. Peripheral Memory Protection Set Register 1 (PMPROTSET1) (offset = 04h)31

0
PCS[63-32]PROTSET
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-82. Peripheral Memory Protection Set Register 1 (PMPROTSET1) Field Descriptions
Bit

Field

31-0

PCS[63-32]PROTSET

Value

Description
Peripheral memory frame protection set.

0

Read: The peripheral memory framen can be written to and read from in both user andprivileged modes.
Write: The bit is unchanged.

1

Read: The peripheral memory framen can be written to only in privileged mode, but it
can be read in both user and privileged modes.
Write: The corresponding bit in PMPROTSET1 and PMPROTCLR1 registers is set to 1.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

145

System and Peripheral Control Registers

2.5.3.3

www.ti.com

Peripheral Memory Protection Clear Register 0 (PMPROTCLR0)This register is shown in Figure 2-67 and described in Table 2-83.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-67. Peripheral Memory Protection Clear Register 0 (PMPROTCLR0) (offset = 10h)310PCS[31-0]PROTCLR
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-83. Peripheral Memory Protection Clear Register 0 (PMPROTCLR0) Field Descriptions
Bit

Field

31-0

PCS[31-0]PROTCLR

Value

Description
Peripheral memory frame protection clear.

0

Read: The peripheral memory framen can be written to and read from in both user andprivileged modes.
Write: The bit is unchanged.

1

Read: The peripheral memory framen can be written to only in privileged mode, but it
can be read in both user and privileged modes.
Write: The corresponding bit in PMPROTSET0 and PMPROTCLR0 registers is cleared
to 0.

2.5.3.4

Peripheral Memory Protection Clear Register 1 (PMPROTCLR1)

This register is shown in Figure 2-68 and described in Table 2-84.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-68. Peripheral Memory Protection Clear Register 1 (PMPROTCLR1) (offset = 14h)31

0PCS[63-32]PROTCLR
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-84. Peripheral Memory Protection Clear Register 1 (PMPROTCLR1) Field Descriptions
Bit

Field

31-0

PCS[63-32]PROTCLR

Value

Description
Peripheral memory frame protection clear.

0

Read: The peripheral memory framen can be written to and read from in both user andprivileged modes.
Write: The bit is unchanged.

1

Read: The peripheral memory framen can be written to only in privileged mode, but it
can be read in both user and privileged modes.
Write: The corresponding bit in PMPROTSET1 and PMPROTCLR1 registers is cleared
to 0.

146

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.3.5

Peripheral Protection Set Register 0 (PPROTSET0)

There is one bit for each quadrant for PS0 to PS7.
The following are the ways in which quadrants are used within a PS frame:a. The slave uses all the four quadrants:
Only the bit corresponding to the quadrant 0 of PSn is implemented. It protects the whole 1K-byte
frame. The remaining three bits are not implemented.
b. The slave uses two quadrants:
Each quadrant has to be in one of these groups: (Quad 0 and Quad 1) or (Quad 2 and Quad 3).
For the group Quad0/Quad1, the bit quadrant 0 protects both quadrants 0 and 1. The bit quadrant 1 is
not implemented.
For the group Quad2/Quad3, the bit quadrant 2 protects both quadrants 2 and 3. The bit quadrant 3 is
not implemented.
c. The slave uses only one quadrant:
In this case, the bit, as specified in Table 2-85, protects the slave.
The arrangement is true for all the peripheral select (PS0 to PS31).
This register holds bits for PS0 to PS7 and is shown in Figure 2-69 and described in Table 2-85.
NOTE: Writes to nonimplemented bits have no effect and reads are 0.

Figure 2-69. Peripheral Protection Set Register 0 (PPROTSET0) (offset = 20h)310PS[7-0]QUAD[3-0]PROTSET
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-85. Peripheral Protection Set Register 0 (PPROTSET0) Field Descriptions
Bit

Field

31-0

PS[7-0]QUAD[3-0]PROTSET

Value

Description
Peripheral select quadrant protection set.

0

Read: The peripheral select quadrant an be written to and read from in bothuser and privileged modes.
Write: The bit is unchanged.

1

Read: The peripheral select quadrant can be written to only in privilegedmode, but it can be read in both user and privileged modes.
Write: The corresponding bit in PPROTSET0 and PPROTCLR0 registers is set
to 1.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

147

System and Peripheral Control Registers

2.5.3.6

www.ti.com

Peripheral Protection Set Register 1 (PPROTSET1)

There is one bit for each quadrant for PS8 to PS15. The protection scheme is described in
Section 2.5.3.5. This register is shown in Figure 2-70 and described in Table 2-86.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-70. Peripheral Protection Set Register 1 (PPROTSET1) (offset = 24h)310PS[15-8]QUAD[3-0]PROTSET
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-86. Peripheral Protection Set Register 1 (PPROTSET1) Field Descriptions
Bit

Field

31-0

PS[15-8]QUAD[3-0]PROTSET

Value

Description
Peripheral select quadrant protection set.

0

Read: The peripheral select quadrant can be written to and read from in bothuser and privileged modes.
Write: The bit is unchanged.

1

Read: The peripheral select quadrant can be written to only in privilegedmode, but it can be read in both user and privileged modes.
Write: The corresponding bit in PPROTSET1 and PPROTCLR1 registers is set
to 1.

2.5.3.7

Peripheral Protection Set Register 2 (PPROTSET2)

There is one bit for each quadrant for PS16 to PS23. The protection scheme is described in
Section 2.5.3.5. This register is shown in Figure 2-71 and described in Table 2-87.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-71. Peripheral Protection Set Register 2 (PPROTSET2) (offset = 28h)310PS[23-16]QUAD[3-0]PROTSET
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-87. Peripheral Protection Set Register 2 (PPROTSET2) Field Descriptions
Bit

Field

31-0

PS[23-16]QUAD[3-0]PROTSET

Value

Description
Peripheral select quadrant protection set.

0

Read: The peripheral select quadrant can be written to and read from in bothuser and privileged modes.
Write: The bit is unchanged.

1

Read: The peripheral select quadrant can be written to only in privilegedmode, but it can be read in both user and privileged modes.
Write: The corresponding bit in PPROTSET2 and PPROTCLR2 registers is set
to 1.

148

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.3.8

Peripheral Protection Set Register 3 (PPROTSET3)

There is one bit for each quadrant for PS24 to PS31. The protection scheme is described in
Section 2.5.3.5. This register is shown in Figure 2-72 and described in Table 2-88.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-72. Peripheral Protection Set Register 3 (PPROTSET3) (offset = 2Ch)31

0
PS[31-24]QUAD[3-0]PROTSET
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-88. Peripheral Protection Set Register 3 (PPROTSET3) Field Descriptions
Bit

Field

31-0

PS[31-24]QUAD[3-0]PROTSET

Value

Description
Peripheral select quadrant protection set.

0

Read: The peripheral select quadrant can be written to and read from in bothuser and privileged modes.
Write: The bit is unchanged.

1

Read: The peripheral select quadrant can be written to only in privilegedmode, but it can be read in both user and privileged modes.
Write: The corresponding bit in PPROTSET3 and PPROTCLR3 registers is set
to 1.

2.5.3.9

Peripheral Protection Clear Register 0 (PPROTCLR0)

There is one bit for each quadrant for PS0 to PS7. The protection scheme is described in Section 2.5.3.5.
This register is shown in Figure 2-73 and described in Table 2-89.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-73. Peripheral Protection Clear Register 0 (PPROTCLR0) (offset = 40h)310PS[7-0]QUAD[3-0]PROTCLR
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-89. Peripheral Protection Clear Register 0 (PPROTCLR0) Field Descriptions
Bit

Field

31-0

PS[7-0]QUAD[3-0]PROTCLR

Value

Description
Peripheral select quadrant protection clear.

0

Read: The peripheral select quadrant can be written to and read from in bothuser and privileged modes.
Write: The bit is unchanged.

1

Read: The peripheral select quadrant can be written to only in privilegedmode, but it can be read in both user and privileged modes.
Write: The corresponding bit in PPROTSET0 and PPROTCLR0 registers iscleared to 0.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

149

System and Peripheral Control Registers

www.ti.com

2.5.3.10 Peripheral Protection Clear Register 1 (PPROTCLR1)
There is one bit for each quadrant for PS8 to PS15. The protection scheme is described in
Section 2.5.3.5. This register is shown in Figure 2-74 and described in Table 2-90.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-74. Peripheral Protection Clear Register 1 (PPROTCLR1) (offset = 44h)310PS[15-8]QUAD[3-0]PROTCLR
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-90. Peripheral Protection Clear Register 1 (PPROTCLR1) Field Descriptions
Bit

Field

31-0

PS[15-8]QUAD[3-0]PROTCLR

Value

Description
Peripheral select quadrant protection clear.

0

Read: The peripheral select quadrant can be written to and read from in bothuser and privileged modes.
Write: The bit is unchanged.

1

Read: The peripheral select quadrant can be written to only in privilegedmode, but it can be read in both user and privileged modes.
Write: The corresponding bit in PPROTSET1 and PPROTCLR1 registers iscleared to 0.

2.5.3.11 Peripheral Protection Clear Register 2 (PPROTCLR2)
There is one bit for each quadrant for PS16 to PS23. The protection scheme is described in
Section 2.5.3.5. This register is shown in Figure 2-75 and described in Table 2-91.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-75. Peripheral Protection Clear Register 2 (PPROTCLR2) (offset = 48h)31

0PS[23-16]QUAD[3-0]PROTCLR
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-91. Peripheral Protection Clear Register 2 (PPROTCLR2) Field Descriptions
Bit

Field

31-0

PS[23-16]QUAD[3-0]PROTCLR

Value

Description
Peripheral select quadrant protection clear.

0

Read: The peripheral select quadrant can be written to and read from in bothuser and privileged modes.
Write: The bit is unchanged.

1

Read: The peripheral select quadrant can be written to only in privilegedmode, but it can be read in both user and privileged modes.
Write: The corresponding bit in PPROTSET2 and PPROTCLR2 registers iscleared to 0.

150

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.3.12 Peripheral Protection Clear Register 3 (PPROTCLR3)
There is one bit for each quadrant for PS24 to PS31. The protection scheme is described in
Section 2.5.3.5. This register is shown in Figure 2-76 and described in Table 2-92.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-76. Peripheral Protection Clear Register 3 (PPROTCLR3) (offset = 4Ch)31

0
PS[31-24]QUAD[3-0]PROTCLR
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-92. Peripheral Protection Clear Register 3 (PPROTCLR3) Field Descriptions
Bit

Field

31-0

PS[31-24]QUAD[3-0]PROTCLR

Value

Description
Peripheral select quadrant protection clear.

0

Read: The peripheral select quadrant can be written to and read from in bothuser and privileged modes.
Write: The bit is unchanged.

1

Read: The peripheral select quadrant can be written to only in privilegedmode, but it can be read in both user and privileged modes.
Write: The corresponding bit in PPROTSET3 and PPROTCLR3 registers iscleared to 0.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

151

System and Peripheral Control Registers

www.ti.com

2.5.3.13 Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0)
Each bit corresponds to a bit at the same index in the PMPROT register in that they both relate to thesame peripheral. This register is shown in Figure 2-77 and described in Table 2-93.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-77. Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0) (offset = 60h)310PCS[31-0]PWRDNSET
R/WP-1LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-93. Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0) Field Descriptions
Bit

Field

31-0

PCS[31-0]PWRDNSET

Value

Description
Peripheral memory clock power-down set.

0

Read: The peripheral memory clock[31-0] is active.
Write: The bit is unchanged.

1

Read: The peripheral memory clock[31-0] is inactive.
Write: The corresponding bit in the PCSPWRDWNSET0 and PCSPWRDWNCLR0
registers is set to 1.

2.5.3.14 Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1)
This register is shown in Figure 2-78 and described in Table 2-94.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-78. Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1) (offset = 64h)310PCS[63-32]PWRDNSET
R/WP-1LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-94. Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1) Field Descriptions
Bit

Field

31-0

PCS[63-32]PWRDNSET

Value

Description
Peripheral memory clock power-down set.

0

Read: The peripheral memory clock[63-32] is active.
Write: The bit is unchanged.

1

Read: The peripheral memory clock[63-32] is inactive.
Write: The corresponding bit in the PCSPWRDWNSET1 and PCSPWRDWNCLR1
registers is set to 1.

152

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.3.15 Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0)This register is shown in Figure 2-79 and described in Table 2-95.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-79. Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0) (offset = 70h)310PCS[31-0]PWRDNCLR
R/WP-1LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-95. Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0) Field
Descriptions
Bit

Field

31-0

PCS[31-0]PWRDNCLR

Value

Description
Peripheral memory clock power-down clear.

0

Read: The peripheral memory clock[31-0] is active.
Write: The bit is unchanged.

1

Read: The peripheral memory clock[31-0] is inactive.
Write: The corresponding bit in the PCSPWRDWNSET0 and PCSPWRDWNCLR0
registers is cleared to 0.

2.5.3.16 Peripheral Memory Power-Down Clear Register 1 (PCSPWRDWNCLR1)
This register is shown in Figure 2-80 and described in Table 2-96.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-80. Peripheral Memory Power-Down Clear Register 1 (PCSPWRDWNCLR1) (offset = 74h)31

0PCS[63-32]PWRDNCLR
R/WP-1LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-96. Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNCLR1) Field Descriptions
Bit

Field

31-0

PCS[63-32]PWRDNCLR

Value

Description
Peripheral memory clock power-down clear.

0

Read: The peripheral memory clock[63-32] is active.
Write: The bit is unchanged.

1

Read: The peripheral memory clock[63-32] is inactive.
Write: The corresponding bit in the PCSPWRDWNSET1 and PCSPWRDWNCLR1
registers is cleared to 0.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

153

System and Peripheral Control Registers

www.ti.com

2.5.3.17 Peripheral Power-Down Set Register 0 (PSPWRDWNSET0)
There is one bit for each quadrant for PS0 to PS7. Each bit of this register corresponds to the bit at thesame index in the corresponding PPROT register in that they relate to the same peripheral. These bits areused to power down/power up the clock to the corresponding peripheral.
For every bit implemented in the PPROT register, there is one bit in the PSnPWRDWN register, except
when two peripherals (both in PS area) share buses. In that case, only one Power-Down bit is
implemented, at the position corresponding to that peripheral whose quadrant comes first (the lower
numbered).
The ways in which quadrants can be used within a frame are identical to what is described under
PPROTSET0, Section 2.5.3.5.
This arrangement is the same for bits of PS8 to PS31, presented in Section 2.5.3.18 - Section 2.5.3.24.
This register holds bits for PS0 to PS7. This register is shown in Figure 2-81 and described in Table 2-97.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-81. Peripheral Power-Down Set Register 0 (PSPWRDWNSET0) (offset = 80h)310PS[7-0]QUAD[3-0]PWRDWNSET
R/WP-1LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-97. Peripheral Power-Down Set Register 0 (PSPWRDWNSET0) Field Descriptions
Bit

Field

31-0

PS[7-0]QUAD[3-0]PWRDWNSET

Value

Description
Peripheral select quadrant clock power-down set.

0

Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.

1

Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET0 and PSPWRDWNCLR0
registers is set to 1.

154

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.3.18 Peripheral Power-Down Set Register 1 (PSPWRDWNSET1)
There is one bit for each quadrant for PS8 to PS15. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-82 and described in Table 2-98.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-82. Peripheral Power-Down Set Register 1 (PSPWRDWNSET1) (offset = 84h)310PS[15-8]QUAD[3-0]PWRDWNSET
R/WP-1LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-98. Peripheral Power-Down Set Register 1 (PSPWRDWNSET1) Field Descriptions
Bit

Field

31-0

PS[15-8]QUAD[3-0]PWRDWNSET

Value

Description
Peripheral select quadrant clock power-down set.

0

Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.

1

Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET1 and PSPWRDWNCLR1
registers is set to 1.

2.5.3.19 Peripheral Power-Down Set Register 2 (PSPWRDWNSET2)
There is one bit for each quadrant for PS16 to PS23. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-83 and described in Table 2-99.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-83. Peripheral Power-Down Set Register 2 (PSPWRDWNSET2) (offset = 88h)31

0PS[23-16]QUAD[3-0]PWRDWNSET
R/WP-1LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-99. Peripheral Power-Down Set Register 2 (PSPWRDWNSET2) Field Descriptions
Bit

Field

31-0

PS[23-16]QUAD[3-0]PWRDWNSET

Value

Description
Peripheral select quadrant clock power-down set.

0

Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.

1

Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET2 and PSPWRDWNCLR2
registers is set to 1.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

155

System and Peripheral Control Registers

www.ti.com

2.5.3.20 Peripheral Power-Down Set Register 3 (PSPWRDWNSET3)
There is one bit for each quadrant for PS24 to PS31. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-84 and described in Table 2-100.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-84. Peripheral Power-Down Set Register 3 (PSPWRDWNSET3) (offset = 8Ch)31

0
PS[31-24]QUAD[3-0]PWRDWNSET
R/WP-1LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-100. Peripheral Power-Down Set Register 3 (PSPWRDWNSET3) Field Descriptions
Bit

Field

31-0

PS[31-24]QUAD[3-0]PWRDWNSET

Value

Description
Peripheral select quadrant clock power-down set.

0

Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.

1

Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET3 and PSPWRDWNCLR3
registers is set to 1.

2.5.3.21 Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0)
There is one bit for each quadrant for PS0 to PS7. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-85 and described in Table 2-101.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-85. Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0) (offset = A0h)31

0PS[7-0]QUAD[3-0]PWRDWNCLR
R/WP-1LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-101. Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0) Field Descriptions
Bit

Field

31-0

PS[7-0]QUAD[3-0]PWRDWNCLR

Value

Description
Peripheral select quadrant clock power-down clear.

0

Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.

1

Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET0 and PSPWRDWNCLR0
registers is cleared to 0.

156

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

System and Peripheral Control Registers

www.ti.com

2.5.3.22 Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1)
There is one bit for each quadrant for PS8 to PS15. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-86 and described in Table 2-102.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-86. Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1) (offset = A4h)310PS[15-8]QUAD[3-0]PWRDWNCLR
R/WP-1LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-102. Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1) Field Descriptions
Bit

Field

31-0

PS[15-8]QUAD[3-0]PWRDWNCLR

Value

Description
Peripheral select quadrant clock power-down clear.

0

Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.

1

Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET1 and PSPWRDWNCLR1
registers is cleared to 0.

2.5.3.23 Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2)
There is one bit for each quadrant for PS16 to PS23. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-87 and described in Table 2-103.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-87. Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2) (offset = A8h)310PS[23-16]QUAD[3-0]PWRDWNCLR
R/WP-1LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-103. Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2) Field Descriptions
Bit

Field

31-0

PS[23-16]QUAD[3-0]PWRDWNCLR

Value

Description
Peripheral select quadrant clock power-down clear.

0

Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.

1

Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET2 and PSPWRDWNCLR2
registers is cleared to 0.

SPNU517C – March 2018
Submit Documentation Feedback

Architecture
Copyright © 2018, Texas Instruments Incorporated

157

System and Peripheral Control Registers

www.ti.com

2.5.3.24 Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR3)
There is one bit for each quadrant for PS24 to PS31. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-88 and described in Table 2-104.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to nonimplemented bits have no effect and reads are 0.

Figure 2-88. Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR) (offset = ACh)31

0PS[31-24]QUAD[3-0]PWRDWNCLR
R/WP-1LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-104. Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR3) Field Descriptions
Bit

Field

31-0

PS[31-24]QUAD[3-0]PWRDWNCLR

Value

Description
Peripheral select quadrant clock power-down clear.

0

Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.

1

Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET3 and PSPWRDWNCLR3
registers is cleared to 0.

158

Architecture

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Chapter 3
SPNU517C – March 2018

I/O Multiplexing and Control Module (IOMM)This chapter describes the I/O Multiplexing and Control Module (IOMM).
Topic

3.1
3.2
3.3
3.4
3.5

...........................................................................................................................

Page

Overview ........................................................................................................ 160
Main Features of I/O Multiplexing Module (IOMM) ................................................ 160
Control of Multiplexed Functions ....................................................................... 160
Safety Features ............................................................................................... 163
IOMM Registers ................................................................................................ 164

SPNU517C – March 2018
Submit Documentation Feedback

I/O Multiplexing and Control Module (IOMM)
Copyright © 2018, Texas Instruments Incorporated

159

Overview

3.1

www.ti.com

Overview
This chapter describes the overall features of the module that controls the I/O multiplexing on the device.
The mapping of control registers to multiplexing options is specified in Section 3.5.12.

3.2

Main Features of I/O Multiplexing Module (IOMM)
The IOMM contains memory-mapped registers (MMR) that control device-specific multiplexed functions.
The safety and diagnostic features of the IOMM are:
• Kicker mechanism to protect the MMRs from accidental writes• Error indication for access violations
The safety features of the IOMM are described in Section 3.4.

3.3

Control of Multiplexed Functions
Several functions are multiplexed on the device. The following sections describe the multiplexing scheme
and its implementation.

3.3.1 Control of Multiplexed Outputs
The signal multiplexing controlled by each memory-mapped control register (PINMMRn) is described inTable 3-14. Each byte in the PINMMR controls the functionality output on a single terminal. Consider thefollowing example in Figure 3-1 for the PINMMR1 control register.
Figure 3-1. PINMMR1 Control Register
31

25

24

Reserved

26

SPI2nCS[2]

GIOA[4]

R/WP-0R/WP-0R/WP-023

17

16

Reserved

18

SPI2nCS[3]

GIOA[3]

R/WP-0R/WP-0R/WP-1

9

8

Reserved

SPI3nCS[1]

GIOA[2]

R/WP-0R/WP-0R/WP-1

15

10

7

1

0

Reserved

2

SPI3nCS[2]

GIOA[1]

R/WP-0R/WP-0R/WP-1LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

•

•
•

160

Consider the multiplexing controlled by PINMMR1[15–8]. These bits control the multiplexing between
the GIOA[2] and SPI3nCS[1] for this device. The default function is GIOA[2]. This is indicated by bit 8of the PINMMR1 register being set to 1.
If the application wants an SPI3nCS[1] signal, then bit 8 of PINMMR1 must be cleared to 0 and bit 9
must be set to 1.
Each feature of the output function is determined by the function selected to be output on a terminal.

I/O Multiplexing and Control Module (IOMM)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl of Multiplexed Functions

www.ti.com

Figure 3-2 shows the multiplexing between the output functions for the pad. This terminal uses a 2mA
output buffer.
For example, the pad is driven by an output buffer with an 2mA drive strength. This output buffer has thefollowing signals: A (signal to be output), and GZ (output enable). Each of these signals is an output of amultiplexor that allows the selected function to control all available features of the output buffer.
The PINMMR control registers are used to implement a one-hot encoding scheme for selecting themultiplexed function:• For example, at least one of bit 8 or bit 9 must be set.
• If the application clears both bits 8 and 9, then the default function (GIOA[2]) will be selected for output
on the pad.
• If the application sets both bits 8 and 9, then the default function (GIOA[2]) will be selected for output
on the pad.
• If the application sets one or more reserved bit(s) within the byte 15–8, then the default function(GIOA[2]) will be selected for output on the pad.
Figure 3-2. Output Multiplexing Example
PINMMR1[8, 9]

2mA Output Buffer
GIOA2_OUT_nEN
GZ
SPI3nCS[1]_OUT_nEN
GIOA2
A

Y

SPI3nCS[1]pad

3.3.2 Inputs
The input signals are broadcast to all modules hooked up to a terminal. The application must ensure thatmodules that are not being used in the application do not react to a change on their input functions. As inthe example cited above, if the output function is selected as SPI3nCS[1], an output toggle will beviewable in the GIOA input register for the GIOA[2] input. Like wise, if GIOA[2] is selected on pin 5 andconfigured as an input, this input signal will also be seen in the SPI3 module nCS[1] bit location eventhough it was not selected to be active on pin 5.

SPNU517C – March 2018
Submit Documentation Feedback

I/O Multiplexing and Control Module (IOMM)
Copyright © 2018, Texas Instruments Incorporated

161

Control of Multiplexed Functions

www.ti.com

3.3.3 Control of Special Multiplexed Options
Special controls are implemented to affect particular functions on this device. These controls aredescribed in this section.
3.3.3.1 eQEPA Input• When PINMMR8[0] = 1, the eQEPA input is double-synchronized using VCLK.
• When PINMMR8[0] = 0 and PINMMR8[1] = 1, the eQEPA input is double-synchronized and thenqualified through a fixed 6-bit counter using VCLK.
• PINMMR8[0] = 0 and PINMMR8[1] = 0 is an invalid combination and behavior defaults to
PINMMR8[0] = 1.
3.3.3.2 eQEPB Input• When PINMMR8[8] = 1, the eQEPB input is double-synchronized using VCLK.
• When PINMMR8[8] = 0 and PINMMR8[9] = 1, the eQEPB input is double-synchronized and thenqualified through a fixed 6-bit counter using VCLK.
• PINMMR8[8] = 0 and PINMMR8[9] = 0 is an invalid combination and behavior defaults to
PINMMR8[8] = 1.
3.3.3.3 eQEPI Input• When PINMMR8[16] = 1, the eQEPI input is double-synchronized using VCLK.
• When PINMMR8[16] = 0 and PINMMR8[17] = 1, the eQEPI input is double-synchronized and thenqualified through a fixed 6-bit counter using VCLK.
• PINMMR8[16] = 0 and PINMMR8[17] = 0 is an invalid combination and behavior defaults to
PINMMR8[16] = 1.
3.3.3.4 eQEPS Input• When PINMMR8[24] = 1, the eQEPS input is double-synchronized using VCLK.
• When PINMMR8[24] = 0 and PINMMR8[25] = 1, the eQEPS input is double-synchronized and thenqualified through a fixed 6-bit counter using VCLK.
• PINMMR8[24] = 0 and PINMMR8[25] = 0 is an invalid combination and behavior defaults to
PINMMR8[24] = 1.
3.3.3.5 N2HET PIN_nDISABLE Input Port• When PINMMR9[0] = 1, GIOA[5] is connected directly to N2HET PIN_nDISABLE input of the N2HET
module.
• When PINMMR9[0] = 0 and PINMMR9[1] = 1, EQEPERR is inverted and double-synchronized using
VCLK before connecting directly to the N2HET PIN_nDISABLE input of the N2HET module.
• PINMMR9[0] = 0 and PINMMR9[1] = 0 is an invalid combination and behavior defaults to
PINMMR9[0] = 1.

162

I/O Multiplexing and Control Module (IOMM)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackSafety Features

www.ti.com

3.4

Safety Features
The IOMM supports certain safety functions that are designed to prevent unintentional changes to the I/O
multiplexing configuration. These are described in the following sections.

3.4.1 Locking Mechanism for Memory-Mapped Registers
The IOMM contains a mechanism to prevent any spurious writes from changing any of the PINMMR
values. The PINMMRs are locked by default and after any system reset. None of the PINMMRs can be
written under this condition. The application can read any of the IOMM registers regardless of the state of
the locking mechanism.
• Enabling Write Access to the PINMMRs
To enable write access to the PINMMRs, the CPU must write 0x83e70b13 to the kick0 register followed bya write of 0x95a4f1e0 to the kick1 register.
• Disabling Write Access to the PINMMRs
It is recommended to disable write access to the PINMMRs once the I/O multiplexing configuration iscompleted. This can be done by:• writing any other data value to either of the kick registers, or• restarting the unlock sequence by writing 0x83e70b13 to the kick0 register
NOTE: No Error On Write to Locked PINMMRs
There is no error response on any write accesses to the PINMMRs when write access is
disabled. None of the PINMMRs change state due to this write.

3.4.2 Error Conditions
The IOMM generates one error signal that is mapped to the Error Signaling Module’s Group 1, channel
37. This error signal is generated under either of the following two conditions:• Address Error – occurs when there is a read or a write access to an un-implemented memory location
within the IOMM register frame.
• Protection Error – occurs when the CPU writes to an IOMM register while not in a privileged mode ofoperation.

SPNU517C – March 2018
Submit Documentation Feedback

I/O Multiplexing and Control Module (IOMM)
Copyright © 2018, Texas Instruments Incorporated

163

IOMM Registers

3.5

www.ti.com

IOMM Registers
Table 3-1 shows a summary of the control registers in the IOMM. The address offset is specified from thebase address of FFFF EA00h.
Table 3-1. IOMM Register Summary
OffsetAcronym

Register Description

00h

REVISION_REG

Revision Register

Section 3.5.1

Section20h

BOOT_REG

Boot Mode Register

Section 3.5.2

38h

KICK_REG0

Kicker Register 0

Section 3.5.3

3Ch

KICK_REG1

Kicker Register 1

Section 3.5.4

E0h

ERR_RAW_STATUS_REG

Error Raw Status / Set Register

Section 3.5.5

E4h

ERR_ENABLED_STATUS_REG

Error Enabled Status / Clear Register

Section 3.5.6

E8h

ERR_ENABLE_REG

Error Signaling Enable Register

Section 3.5.7

ECh

ERR_ENABLE_CLR_REG

Error Signaling Enable Clear Register

Section 3.5.8

F4h

FAULT_ADDRESS_REG

Fault Address Register

Section 3.5.9

F8h

FAULT_STATUS_REG

Fault Status Register

Section 3.5.10

FCh

FAULT_CLEAR_REG

Fault Clear Register

Section 3.5.11

PINMMRn

Pin Multiplexing Control Registers

Section 3.5.12

110h-188h

3.5.1 REVISION_REG: Revision Register
Figure 3-3. REVISION_REG: Revision Register (Offset = 00h)
31

30

29

28

27

16

REV SCHEME

Reserved

REV MODULE

R-1

R-0

R-E84h

15

11

10

8

7

6

5

0

REV RTL

REV MAJORREV CUSTOMREV MINOR

R-0

R-1

R-0

R-2h

LEGEND: R = Read only; -n = value after reset

Table 3-2. Revision Register Field Descriptions
Bit

Field

Value

31-30 REV SCHEME

1

Revision Scheme

29-28 Reserved

0

Reads return zeros, writes have no effect.

27-16 REV MODULE

E84h

Description

Module Id

15-11 REV RTL

0

RTL Revision

10-8

REV MAJOR

1

Major Revision

7-6

REV CUSTOM

0

Custom Revision

5-0

REV MINOR

2hMinor Revision

164

I/O Multiplexing and Control Module (IOMM)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

IOMM Registers

www.ti.com

3.5.2 BOOT_REG: Boot Mode Register
Figure 3-4. BOOT_REG: Boot Mode Register (Offset = 20h)
31

16
Reserved
R-0

15

1

0

Reserved

ENDIAN

R-0

R-D

LEGEND: Read only; -n = value after reset; D = value read is determined by external configuration

Table 3-3. Boot Mode Register Field Descriptions
Bit

Field

31-1

Reserved

0

ENDIAN

Value
0

Description
Reads return zeros, writes have no effect.
Device endianness.

0

Device is configured in little-endian mode.

1

Device is configured in big-endian mode.

3.5.3 KICK_REG0: Kicker Register 0This register forms the first part of the unlock sequence for being able to update the I/O multiplexing
control registers (PINMMRnn).
Figure 3-5. KICK_REG0: Kicker Register 0 (Offset = 38h)
31

0
KICK0
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 3-4. Kicker Register 0 Field Descriptions
Bit

Field

Value

31-0

KICK0

0

Description
Kicker 0 Register. The value 83E7 0B13h must be written to KICK0 as part of the process to unlock the
CPU write access to the PINMMRn registers.

3.5.4 KICK_REG1: Kicker Register 1
This register forms the second part of the unlock sequence for being able to update the I/O multiplexing
control registers (PINMMRnn).
Figure 3-6. KICK_REG1: Kicker Register 1 (Offset = 3Ch)
31

0
KICK1
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 3-5. Kicker Register 1 Field Descriptions
Bit

Field

Value

31-0

KICK1

0

SPNU517C – March 2018
Submit Documentation Feedback

Description
Kicker 1 Register. The value 95A4 F1E0h must be written to the KICK1 as part of the process to unlock
the CPU write access to the PINMMRn registers.

I/O Multiplexing and Control Module (IOMM)
Copyright © 2018, Texas Instruments Incorporated

165

IOMM Registers

www.ti.com

3.5.5 ERR_RAW_STATUS_REG: Error Raw Status / Set Register
This register shows the statuses of the error conditions (before enabling) and allows setting the status.
Figure 3-7. ERR_RAW_STATUS_REG: Error Raw Status / Set Register (Offset = E0h)31

8
Reserved
R-0

7

1

0

Reserved

2

ADDR_ERRPROT_ERR

R-0

R/WP-0R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 3-6. Error Raw Status / Set Register Field Descriptions
Bit

Field

31-2

Reserved

1

ADDR_ERR

Value
0

Description
Read returns zeros, writes have no effect.
Addressing Error Status. An Addressing Error occurs when an unimplemented location inside the IOMM
register frame is accessed.

0

Read: Addressing Error has not occurred.
Write: Writing 0 has no effect.

1

Read: Addressing Error has been detected.
Write: Addressing Error status is set.

0

PROT_ERR

Protection Error Status. A Protection Error occurs when any control register inside the IOMM is written
in the CPU's user mode of operation.
0

Read: Protection Error has not occurred.
Write: Writing 0 has no effect.

1

Read: Protection Error has been detected.
Write: Protection Error status is set.

166

I/O Multiplexing and Control Module (IOMM)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

IOMM Registers

www.ti.com

3.5.6 ERR_ENABLED_STATUS_REG: Error Enabled Status / Clear Register
This register shows the error signal enabled status and allows clearing of the error status.
Figure 3-8. ERR_ENABLED_STATUS_REG: Error Enabled Status / Clear Register (Offset = E4h)31

8
Reserved
R-0

7

1

0

Reserved

2

ENABLED_ADDR_ERR

ENABLED_PROT_ERR

R-0

R/WP-0R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 3-7. Error Signaling Enabled Status / Clear Register Field Descriptions
Bit

Field

31-2

Reserved

1

Value
0

ENABLED_ADDR_ERR

Description
Read returns zeros, writes have no effect.
Addressing Error Signaling Enable Status and Status Clear0

Read: Addressing Error Signaling is disabled.
Write: Writing 0 has no effect.

1

Read: Addressing Error Signaling is enabled.
Write: Addressing Error status is cleared.

0

ENABLED_PROT_ERR

Protection Error Signaling Enable Status and Status Clear0

Read: Protection Error Signaling is disabled.
Write: Writing 0 has no effect.

1

Read: Protection Error Signaling is enabled.
Write: Protection Error status is cleared.

SPNU517C – March 2018
Submit Documentation Feedback

I/O Multiplexing and Control Module (IOMM)
Copyright © 2018, Texas Instruments Incorporated

167

IOMM Registers

www.ti.com

3.5.7 ERR_ENABLE_REG: Error Signaling Enable Register
This register shows the interrupt enable status and allows enabling of the interrupts.
Figure 3-9. ERR_ENABLE_REG: Error Signaling Enable Register (Offset = E8h)31

8Reserved
R-0

7

1

0

Reserved

2

ADDR_ERR_EN

PROT_ERR_EN

R-0

R/WP-0R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 3-8. Error Enable Register Field Descriptions
Bit

Field

31-2

Reserved

1

Value
0

ADDR_ERR_EN

Description
Read returns zeros, writes have no effect.
Addressing Error Signaling Enable

0

Read: Addressing Error Signaling is disabled.
Write: Writing 0 has no effect.

1

Read: Addressing Error Signaling is enabled.
Write: Addressing Error Signaling is enabled.

0

PROT_ERR_EN

Protection Error Signaling Enable
0

Read: Protection Error Signaling is disabled.
Write: Writing 0 has no effect.

1

Read: Protection Error Signaling is enabled.
Write: Protection Error Signaling is enabled.

168

I/O Multiplexing and Control Module (IOMM)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

IOMM Registers

www.ti.com

3.5.8 ERR_ENABLE_CLR_REG: Error Signaling Enable Clear Register
This register shows the error signaling enable status and allows disabling of the error signaling.
Figure 3-10. ERR_ENABLE_CLR_REG: Error Signaling Enable Clear Register (Offset = ECh)
31

8
Reserved
R-0

7

1

0

Reserved

2

ADDR_ERR_EN_CLR

PROT_ERR_EN_CLR

R-0

R/WP-0R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 3-9. Interrupt Enable Clear Register Field Descriptions
Bit

Field

31-2

Reserved

1

Value
0

ADDR_ERR_EN_CLR

Description
Read returns zeros, writes have no effect.
Addressing Error Signaling Enable Clear0

Read: Addressing Error signaling is disabled.
Write: Writing 0 has no effect.

1

Read: Addressing Error signaling is enabled.
Write: Addressing Error signaling is disabled.

0

PROT_ERR_EN_CLR

Protection Error Signaling Enable Clear0

Read: Protection Error signaling is disabled.
Write: Writing 0 has no effect.

1

Read: Protection Error signaling is enabled.
Write: Protection Error signaling is disabled.

3.5.9 FAULT_ADDRESS_REG: Fault Address Register
This register holds the address of the first fault transfer.
Figure 3-11. FAULT_ADDRESS_REG: Fault Address Register (Offset = F4h)
31

16
Reserved
R-0

15

9

8

0

Reserved

FAULT_ADDR

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 3-10. Fault Address Register Field Descriptions
Bit

Field

31-9

Reserved

0

Read returns zeros, writes have no effect.

8-0

FAULT_ADDR

0

Fault Address. This field captures the fault address in case of an address error or a protection
error condition.

SPNU517C – March 2018
Submit Documentation Feedback

Value

Description

I/O Multiplexing and Control Module (IOMM)
Copyright © 2018, Texas Instruments Incorporated

169

IOMM Registers

www.ti.com

3.5.10 FAULT_STATUS_REG: Fault Status Register
This register holds the status and attributes of the first fault transfer.
Figure 3-12. FAULT_STATUS_REG: Fault Status Register (Offset = F8h)
31

28

27

24

23

16

Reserved

FAULT_ID

FAULT_MSTID

R-0

R-0

R-0

15

8

7

6

Reserved

13

12
FAULT_PRIVID

9

Rsvd

FAULT_NS

Rsvd

5
FAULT_TYPE

0

R-0

R-0

R-0

R-0

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 3-11. Fault Status Register Field Descriptions
Bit

Field

31-28

Reserved

Value
0

27-24

FAULT_ID

0-FhFaulting Transaction ID

23-16

FAULT_MSTID

0-FFh

ID of Master that initiated the faulting transaction

15-13

Reserved

12-9

FAULT_PRIVID

00-Fh

Description
Reads return zeros, writes have no effect.

Reads return zeros, writes have no effect.
Faulting Privilege ID

8Reserved

0

Reads return zeros, writes have no effect.

7

FAULT_NS

0

Fault: Non-secure access is detected

6

Reserved

0

Reads return zeros, writes have no effect.

5-0

FAULT_TYPE

170

Type of fault detected.
0

No fault

1h

User execute fault

2hUser write fault

4hUser read fault

8hSupervisor execute fault

10hSupervisor write fault

20hSupervisor read fault

othersReserved

I/O Multiplexing and Control Module (IOMM)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

IOMM Registers

www.ti.com

3.5.11 FAULT_CLEAR_REG: Fault Clear Register
This register allows the application to clear the current fault so that another can be captured when 1 iswritten to this register.
Figure 3-13. FAULT_CLEAR_REG: Fault Clear Register (Offset = FCh)
31

16
Reserved
R-0

15

1

0

Reserved

FAULT_CLEAR

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 3-12. FAULT_CLEAR_REG: Fault Clear Register Field Descriptions
Bit

Field

31-1

Reserved

0

Value
0

FAULT_CLEAR

Description
Reads return zeros, writes have no effect.
Fault Clear0

Read: Current value of the FAULT_CLEAR bit is 0.
Write: Writing 0 has no effect.

1

Read: Current value of the FAULT_CLEAR bit is 1.
Write: Writing a 1 clears the current fault.

SPNU517C – March 2018
Submit Documentation Feedback

I/O Multiplexing and Control Module (IOMM)
Copyright © 2018, Texas Instruments Incorporated

171

IOMM Registers

www.ti.com

3.5.12 PINMMRn: Pin Multiplexing Control Registers
These registers control the multiplexing of the functionality available on each pad. There are 31 registers,
PINMMR0 through PINMMR30. PINMMR7 and PINMMR10 are implemented and accessible on thisdevice, but are not mapped and connected to anything functionally; the default value of PINMMR7 =0000 0001h and the default value of PINMMR10 = 0001 0101h. PINMMR11 through PINMMR30 are not
implemented on this device. Each 8-bit field of a PINMMR register controls the functionality of a single
ball/pin. The mapping between the PINMMRn control registers and the functionality selected on a given
terminal is defined in Table 3-14.
Figure 3-14. PINMMRn: Pin Multiplexing Control Registers (Offset = 110h-138h)
31

24

23

16

PINMMRn[31–24]

PINMMRxn23–16]

R/WP-1

R/WP-1

15

8

7

0

PINMMRn[15–8]

PINMMRn[7–0]

R/WP-1

R/WP-1LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 3-13. Pin Multiplexing Control Registers Field Descriptions
Bit

Field

31-24

PINMMRn[31–24]

Value
1h

23-16

PINMMRn[23–16]

1h

15-8

PINMMRn[15–8]

1h

7-0

PINMMRn[7–0]1hDescription
Each of these byte-fields controls the functionality on a given ball/pin. Refer to Table 3-14 for alist of multiplexed signals sorted by the control registers.

Table 3-14. Multiplexing and Control

172

Default Function

Selection Bit

Alternate Function 1

Selection Bit

Alternate Function 2

Selection Bit

GIOA[0]PINMMR0[8]SPI3nCS[3]PINMMR0[9]--

GIOA[1]PINMMR1[0]SPI3nCS[2]PINMMR1[1]--

GIOA[2]PINMMR1[8]SPI3nCS[1]PINMMR1[9]--GIOA[3]

PINMMR1[16]SPI2nCS[3]PINMMR1[17]--

GIOA[4]

PINMMR1[24]SPI2nCS[2]PINMMR1[25]--

GIOA[5]PINMMR2[0]EXTCLKIN

PINMMR2[1]--

GIOA[6]PINMMR2[8]SPI2nCS[1]PINMMR2[9]N2HET[31]PINMMR2[10]GIOA[7]PINMMR2[16]N2HET[29]PINMMR2[17]--MIBSPI1nCS[2]PINMMR3[0]N2HET[20]PINMMR3[1]N2HET[19]PINMMR3[2]SPI3CLKPINMMR3[16]EQEPA

PINMMR3[17]--SPI3nENAPINMMR3[24]EQEPB

PINMMR3[25]--SPI3nCS[0]PINMMR4[0]EQEPIPINMMR4[1]--

MIBSPI1nCS[3]PINMMR4[8]N2HET[26]PINMMR4[9]

-

-

ADEVT

PINMMR4[16]N2HET[28]PINMMR4[17]--MIBSPI1nENA

PINMMR5[8]N2HET[23]PINMMR5[9]

NHET[30]PINMMR5[10]MIBSPI1nCS[1]PINMMR6[8]EQEPS

PINMMR6[9]N2HET[17]PINMMR6[10]I/O Multiplexing and Control Module (IOMM)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Chapter 4
SPNU517C – March 2018

F021 Flash Module Controller
The Flash electrically-erasable programmable read-only memory module is a type of nonvolatile memorythat has fast read access times and is able to be reprogrammed in the field or in the application. This
chapter describes the F021 Flash module controller (FMC).
Topic

4.1
4.2
4.3
4.4
4.5
4.6
4.7

...........................................................................................................................

Page

Overview ........................................................................................................ 174
Default Flash Configuration .............................................................................. 175
SECDED ......................................................................................................... 176
Memory Map ................................................................................................... 180
Power On, Power Off Considerations ................................................................. 183
Emulation and SIL3 Diagnostic Modes ................................................................ 184
Control Registers ............................................................................................ 189

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

173

Overview

4.1

www.ti.com

Overview
The F021 Flash is used to provide non-volatile memory for instruction execution or data storage. The
Flash can be electrically programmed and erased many times to ease code development.
Refer to the following documents for support on how to initialize and use the on-chip Flash and its API:
• Initialization of the TMS570LS043x, TMS570LS033x and RM42L432 Hercules ARM Cortex-R4
Microcontrollers Application Report (SPNA163)• F021 (Texas Instruments 65nm Flash) Flash API Reference Guide (SPNU501)

4.1.1 Features
•
•

•
•
•

Read, program and erase with a single 3.3 V supply voltage
Supports error detection and correction– Single Error Correction and Double Error Detection (SECDED)– Error Correction Code (ECC) is evaluated in the CPU for the main Flash bank arrays and in theFlash Wrapper for the EEPROM emulation Flash banks– Address bits included in ECC calculation
Provides different read modes to optimize performance and verify the integrity of Flash contents
Provides built-in power mode control logic
Integrated program/erase state machine– Simplifies software algorithms– Supports simultaneous read access on a bank while performing a write or erase operation on any
one of the remaining banks– Suspend command allows read access to a sector being programmed/erased– Fast erase and program times (for details, see the device-specific data sheet)

For the actual size of the Flash memory for the device, see the device-specific data sheet.

4.1.2 Definition of Terms
Terms used in this document have the following meaning:• ATCM: Port A tightly coupled memory• BAGP (Bank Active Grace Period): Time (in HCLK cycles) from the most recent Flash access of aparticular bank until that bank enters fallback power mode. This reduces power consumption by theFlash. However, it can also increase access time.
• bw: Normal data space bank data width of a Flash bank. The bw is 128 bits (144 bits including theerror correction bits).
• bwe: EEPROM emulation bank is 64-bits wide (72 bits including the error correction bits).
• Charge pump: Voltage generators and associated control (logic, oscillator, and bandgap, for example).
• CSM: Program/erase command state machine• Fallback power mode: The power mode (active, standby or sleep, depending on which mode isselected) into which a bank or the charge pump falls back each time the active grace period expires.
• Flash bank: A group of Flash sectors that share input/output buffers, data paths, sense amplifiers, andcontrol logic.
• FEE: Flash EEPROM Emulation. Features on the FMC to support using a Flash type memory in placeof an EEPROM Flash memory. EEPROM is erasable by the word while this Flash memory is only
erasable by the sector. The FEE bank is accessible only through Bus 2 in a special address range andalways resides in bank 7.
• Flash module: Flash banks, charge pump, and Flash wrapper.
• Flash wrapper: Power and mode control logic, data path, wait logic, and write/erase state machines.
• FMC: Flash Module Controller.
• Command: A sequence of coded instructions to Flash module to execute a certain task.
174

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Overviewwww.ti.com

•

•
•

•
•
•
•
•
•

FSM (Flash State Machine) - State machine that parses and decodes FSM commands. It executes
embedded algorithms and generates control signals to both Flash bank and charge pump during theactual program/erase operation.
OTP (one-time programmable): A program-only-once Flash sector (cannot be erased)
PAGP (Pump Active Grace Period): Time (in HCLK cycles) from when the last of the banks haveentered fallback power mode until the pump enters a fallback power mode. This can reduce power
consumption by the Flash; however, it can also increase access time.
Pipeline mode: The mode in which Flash is read 128 bits (+ 16 bit ECC) at a time, providing higher
throughput.
Sector: A contiguous region of Flash memory that must be erased simultaneously.
Wide_Word: The width of the data output from the Flash bank. This is 144-bits wide for main Flashbanks and 72 bits wide for the FEE bank.
Standard read mode: The mode assumed when the pipeline mode is disabled. Physically, 128 (+ 16 bit
ECC) is read at a time. However, only 32 bits of data is used while the other bits of data are discarded.
Read Margin 1 mode: More stringent read mode designed for early detection of marginally erased bits.
Read Margin 0 mode: More stringent read mode designed for early detection of marginallyprogrammed bits.

4.1.3 F021 Flash Tools
Texas Instruments provides the following tools for F021 Flash:• nowECC Generation Tool - to generate the Flash ECC from the Flash data.
• nowFLASH Programming Tool - to erase/program/verify the device Flash content through JTAG.
• Code Composer Studio - the development environment with integrated Flash programming capabilities.
• F021 Flash API Library - a set of software peripheral functions to program/erase the Flash module.
Refer to F021 Flash API Reference Guide (SPNU501) for more information.

4.2

Default Flash Configuration
At power up, the Flash module state exhibits the following properties:• Wait states are set to 1 data wait state and 0 address wait states• Pipeline mode is disabled• The Flash content is protected from modification• Power modes are set to Active (no power savings)• The boot code must initialize the wait states (including data wait states and address wait states) andthe desired pipeline mode by initializing the FRDCNTL register to achieve the optimum system
performance. This needs to be done before switching to the final device operating frequency. Refer toInitialization of the TMS570LS043x, TMS570LS033x and RM42L432 Hercules ARM Cortex-R4
Microcontrollers Application Report (SPNA163) for more information.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

175

SECDED

4.3

www.ti.com

SECDEDThe Flash memory can be protected by Single Error Correction Double Error Detection (SECDED). The
main program memory is protected by the SECDED circuit inside of the Cortex-R4 CPU. All OTP and the
FEE memory (bank 7) is protected by SECDED logic in the Flash wrapper.

4.3.1 SECDED Initialization
Flash error detection and correction is not enabled at reset. To enable SECDED, error correction detection
must be enabled in the Flash wrapper, the CPU event bus must be enabled and SECDED must be
enabled within the CPU. Refer to Initialization of the TMS570LS043x, TMS570LS033x and RM42L432
Hercules ARM Cortex-R4 Microcontrollers Application Report (SPNA163) for information on these steps.
The ECC values for all of the ATCM program-memory space (Flash banks 0 through 6) must be
programmed into the Flash before SECDED is enabled. This can be done by generating the correct
values of the ECC with an external tool such as nowECC or may be generated by the programming tool.
The Cortex-R4 CPU may generate speculative fetches to any location within the ATCM memory space. A
speculative fetch to a location with invalid ECC, which is subsequently not used, will not create an abort,
but will set the ESM flags for a correctable or uncorrectable error. An uncorrectable error will
unconditionally cause the nERROR pin to toggle low. Therefore care must be taken to generate thecorrect ECC for the entire ATCM space including the holes between sections and any unused or blank
Flash areas.
The Cortex-R4 CPU does not generate speculative fetches into the address space of bank 7, the
EEPROM Emulation Flash. It is only necessary to initialize the ECC values of the locations which will be
intentionally read by the CPU or other bus masters.

176

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

SECDED

www.ti.com

4.3.2 ECC Encoding
Nineteen address lines are also included in the ECC calculation. A failure of a single address line inside of
the bank will be treated as an uncorrectable error. The ECC encoding is show in Table 4-1. Bits 31:0
come from the word at the address ending in 0x0 or 0x8, Bits 63:31 come from the word at the address
ending in 0x4 or 0xC.

Table 4-1. ECC Encoding for BE32 Devices
8
2

8
1

8
0

7
9

7
8

7
7

7
6

7
5

7
4

7
3

7
2

7
1

2
1

2
0

1
9

1
8

1
7

1
6

1
5

1
4

1
3

1
2

1
1

1
0

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

7
0

6
9

6
8

6
7

6
6

6
5

6
4

Participating Address BitsADDR_MSW_LSW

ECC Bit

0007F_00FFFF00_FF0000FF

7

7FF80_FF0000FF_FF0000FF

6

07F80_00FF00FF_00FF00FF

5

19F83_FCC0FCC0_FCC0FCC04

6A78D_E338E338_E338E338

3

2A9B5_99A699A6_99A699A6

2

0BAD1_57155715_57155715

1

554EA_D1B4D1B4_2E4B2E4B

0

x
x

x

x

x

x

x

x

x

x
x

x

x
x

x
x

x

x

x
x

0
9

0
8

0
7

0
6

0
5

0
4

0
3

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x
x

x
x

x

Participating Data Bits
6
3

6
2

6
1

6
0

5
9

5
8

5
7

5
6

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x
x

x
x

x

x

x

x

x
x

5
4

5
3

5
2

5
1

5
0

4
9

4
8

4
7

4
6

4
5

4
4

4
3

4
2

4
1

4
0

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x
x

x

5
5

x
x

x

x

x

x

x

x

x

x

x

x

x
x

x

x
x

x

x

x

x

x

x

x

x

x

x

x
x
x

x

x

x
x

x
x

x

x

x

x
x

3
8

3
7

3
6

3
5

3
4

3
3

3
2

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x
x

x

x

x
x

x

3
9

x

x

x
x

x

x

Participating Data Bits
2
6

2
5

2
4

x

x

x

x

x

x

x
x
x

x

x

(1)
(2)

2
2

x

x

x

x

x
x

x

2
3

2
1

x
x

x

2
0

x
x

1
9

x

x

x
x

x

1
7

x

1
6

x

x
x

1
4

1
3

x

x

x

x

x

x

x
x

x

1
5

1
2

1
1

1
0

0
9

0
8

x

x

x

x

1
8

x

x

x

x

x

x

x
x

x

x

x

x

x

x

x

x

3
0

2
9

2
8

2
7

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x
x

x

x

x

x

x

x

x

x

x

x

Parity (1)Check Bits (2)

0
7

0
6

0
5

0
4

0
3

0
2

0
1

0
0

x

x

x

x

x

x

x

x

Even

ECC[7]

x

x

x

x

x

x

x

x

Even

ECC[6]

x

x

x

x

x

x

x

x

Even

ECC[5]xx

Even

ECC[4]Odd

ECC[3]Odd

ECC[2]x

Even

ECC[1]x

Even

ECC[0]

x
x

x

3
1

x
x

x

x

x

x

x
x

x

x

x
x

x

x

For Odd parity, XOR a 1 to the row’s XOR result. For even Parity, use the row’s XOR result directly.
Each ECC[x] bit represents the XOR of all the address and data bits marked with x in the same row.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

177

SECDED

www.ti.com

4.3.3 Syndrome Table: Decode to Bit in Error
The syndrome is a 8 bit value which decodes to the bit in error. The bit in error can be a bit among the 64
data bits, the 19 address bits or a bit among the 8 ECC check bits. A syndrome value of 00000000
indicates there is no error. Any other syndrome combinations not shown in the table are un-correctable
multi-bit error. Errors of three of more bits may escape detection. The syndrome decoding is show inTable 4-2.
Table 4-2. Syndrome Table, Decode to Bit in Error
Address Bit Error Position
2
1

2
0

1
9

1
8

1
7

1
6

1
5

1
4

1
3

1
2

1
1

1
0

0
9

0
8

0
7

0
6

0
5

0
4

0
3

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

1

1

0

0

1

1

1

1

1

1

0

0

0

0

0

1

1

1

1

0

1

0

1

0

0

1

1

1

1

0

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

0

1

1

0

1

1

0

1

0

1

0

0

0

1

0

1

1

1

0

1

0

1

1

0

1

0

0

0

1

1

0

1

0

1

0

1

0

1

0

0

1

1

1

0

1

0

1

0

Data Bit Error Position
6
3

6
2

6
1

6
0

5
9

5
8

5
7

5
6

5
5

5
4

5
3

5
2

5
1

5
0

4
9

4
8

4
7

4
6

4
5

4
4

4
3

4
2

4
1

4
0

3
9

3
8

3
7

3
6

3
5

3
4

3
3

3
2

3
1

3
0

2
9

2
8

2
7

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

1

1

1

1

1

1

0

0

1

1

0

0

0

0

0

0

1

1

1

1

1

1

0

0

1

1

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

1

1

0

0

1

1

1

0

0

0

1

1

1

0

0

0

1

1

0

0

1

1

1

0

0

0

1

1

1

0

0

1

0

0

1

1

0

0

1

1

0

1

0

0

1

1

0

1

0

0

1

1

0

0

1

1

0

1

0

0

1

1

0

1

0

0

1

1

0

1

0

1

0

1

1

1

0

0

0

1

0

1

0

1

0

1

0

1

0

1

1

1

0

0

0

1

0

1

0

1

0

1

0

1

0

1

1

0

1

0

0

0

1

1

0

1

1

0

1

0

0

1

1

0

1

0

0

0

1

1

0

1

1

0

1

0

0

0

0

1

0

1

Data Bit Error Position

178

ECC Error Bit

2
6

2
5

2
4

2
3

2
2

2
1

2
0

1
9

1
8

1
7

1
6

1
5

1
4

1
3

1
2

1
1

1
0

0
9

0
8

0
7

0
6

0
5

0
4

0
3

0
2

0
1

0
0

0
7

0
6

0
5

0
4

0
3

0
2

0
1

0
0

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0 Bit[7]

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

1

0

0

0

0

0

0 Bit[6]

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

1

0

0

0

0

0 Bit[5]

1

0

0

1

1

0

0

0

0

0

0

1

1

1

1

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

1

0

0

0

0 Bit[4]

0

1

1

0

0

1

1

1

0

0

0

1

1

1

0

0

0

1

1

0

0

1

1

1

0

0

0

0

0

0

0

1

0

0

0 Bit[3]

0

0

1

1

0

1

0

0

1

1

0

1

0

0

1

1

0

0

1

1

0

1

0

0

1

1

0

0

0

0

0

0

1

0

0 Bit[2]

1

1

1

0

0

0

1

0

1

0

1

0

1

0

1

0

1

1

1

0

0

0

1

0

1

0

1

0

0

0

0

0

0

1

0

1

1

0

0

1

0

0

1

0

1

1

0

0

1

0

1

1

1

0

0

1

0

0

1

0

1

1

0

0

0

0

0

0

0

1 Bit[0]F021 Flash Module Controller

Bit1]

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

SECDED

www.ti.com

4.3.4 Syndrome Table: An Alternate Method
Table 4-3. Alternate Syndrome Table
Syndrome
lsb: 3:0

•
•
•
•
•

Syndrome msb 7:4
0x

1x

2x

3x

4x

5x

6x

7x

8x

9x

Ax

Bx

Cx

Dx

Ex

x0

good

E04

E05

D

E06

D

D

D38

E07

D

D

D54

D

M

M

Fx
D

x1

E00

D

D

D22

D

A19

A17

D

D

A04

M

D

M

D

D

D06

x2

E01

D

D

M

D

D58

D32

D

D

D42

D48

D

M

D

D

M

x3

D

D10

D16

D

M

D

D

A15

A09

D

D

M

D

D26

D00

D

x4

E02

D

D

D23

D

D59

D33

D

D

D43

D49

D

M

D

D

D07

x5

D

D11

D17

D

M

D

D

D39

A08

D

D

D55

D

D27

D01

D

x6

D

D12

D18

D

M

D

D

A14

A07

D

D

M

D

D28

D02

D

x7

M

D

D

M

D

D60

D34

D

D

D44

D50

D

M

D

D

M

x8

E03

D

D

M

D

D61

D35

D

D

D45

D51

D

M

D

D

M
D

x9

D

D13

D19

D

A21

D

D

A13

A06

D

D

M

D

D29

D03

xA

D

D14

D20

D

D57

D

D

A12

D41

D

D

M

D

D30

D04

D

xB

D09

D

D

M

D

D62

D36

D

D

D46

D52

D

D25

D

D

M

xC

D

D15

D21

D

A20

D

D

A11

A05

D

D

M

D

D31

D05

D

xD

M

D

D

M

D

D63

D37

D

D

D47

D53

D

M

D

D

M

xE

D08

D

D

M

D

A18

A16

D

D

A03

M

D

D24

D

D

M

xF

D

M

M

D

D56

D

D

A10

D40

D

D

M

D

M

M

D

E0x - Single-bit ECC error, correctable
Dxx - Single-bit data error, correctable
Axx - Single-bit address error, uncorrectable
D - Double-bit error, uncorrectableM - Multi-bit errors, uncorrectable

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

179

Memory Map

4.4

www.ti.com

Memory Map
The Flash module contains the program memory, which is mapped starting at location 0, and one
Customer OTP sector and one TI OTP sector per bank. The Customer OTP sectors may be programmedby the customer, but cannot be erased. They are typically blank in new parts. The TI OTP sectors areused to contain manufacturing information. They may be read by the customer but can not be
programmed or erased. The TI OTP sectors contain settings used by the Flash API to setup the Flashstate machine for erase and program operations.
All of these OTP regions are memory-mapped to facilitate ease of access by the CPU. They are memory
mapped to an offset starting at F000 0000h in the CPUs memory map.
The RWAIT value is used to define the number of wait states for the program-memory Flash. The EWAIT
value is used to define the number of wait states for the data Flash in bank 7. Bank 7 starting at offset
F020 0000h is dedicated for data storages such as EEPROM Emulation.
For the Flash Bank/Sectoring information, see the device-specific data sheet.

4.4.1 Location of Flash ECC Bits
The ECC bits are packed in their memory space as shown in Figure 4-1 and Figure 4-2.
The ECC bytes for bank 0 must be read as bytes or halfwords. Reading a single ECC byte from bank 0with ECC enabled will actually cause 144 bits to be read from the Flash, and the ECC bits will becorrected if necessary. Any errors in either of the two double-words accessed will be recorded in the
FEDACSTATUS register.
The ECC bytes for bank 7 must be read as bytes only. Reading a single ECC byte from bank 7 with ECC
enabled will actually cause 72 bits to be read from the Flash, and the ECC bits will be corrected if
necessary. Any errors in the double-word accessed will be recorded in the EE_STATUS register.
Figure 4-1. ECC Organization for Program Flash (144-Bits Wide)Big Endian
8-bit Read
0x00000028

64 – bit data word 50x00000020

64 – bit data word 40x00000018

64 – bit data word 30x00000010

64 – bit data word 2

0xF0400004

ECC40x00000008

64 – bit data word 1

0xF0400002

0x00000000

64 – bit data word 0

0xF0400000

0xF0400005

ECC50xF0400004

ECC40xF0400003

ECC3

ECC5

0xF0400002

ECC2

ECC2

ECC3

0xF0400001

ECC1

ECC0

ECC1

0xF0400000

ECC016-bit Read

Figure 4-2. ECC Organization for Bank 7 (72-Bits Wide)Big Endian
8-bit Read

180

0xF0200028

64 – bit data word 5

0xF0100005

ECC50xF0200020

64 – bit data word 4

0xF0100004

ECC40xF0200018

64 – bit data word 3

0xF0100003

ECC3

0xF0200010

64 – bit data word 2

0xF0100002

ECC20xF0200008

64 – bit data word 1

0xF0100001

ECC1

0xF0200000

64 – bit data word 0

0xF0100000

ECC0

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Memory Map

www.ti.com

4.4.2 OTP Memory
4.4.2.1

Flash Bank and Sector Sizes

Flash Bank/Sectoring information can be determined from the device-specific datasheet or can becomputed by reading locations in the TI OTP and FMC registers.
The number of banks, which banks are available, and the number of sectors for bank 0 can be read fromTI OTP location F008 0158h as shown in Figure 4-3 and described in Table 4-4.
The bank sector information is repeated once for each bank in the device. The number of sectors is
unique for each bank. The number of banks and which banks are implemented is repeated in eachlocation. Use the TI OTP information for bank 0 to determine which banks are in the device, and then readthe number of sectors for each bank using the TI OTP locations shown in Table 4-5.
Bank 0 will start at address 0000 0000h. Bank 7 will start at address F020 0000h. Refer to Table 4-5 tofind the starting address of other banks. Refer to Table 4-4 to find the sector sizes in each bank.
Figure 4-3. TI OTP Bank 0 Sector Information
31

24

23

16

Reserved

BX_NUM_Sectors

R

R

15

14

13

12

11

10

9

8

B7

B6

B5

B4

B3

B2

B1

B0

7
NUM_Banks

0

R-1

R-0

R-0

R-0

R-0

R-0

R-1

R-1

R

LEGEND: R = Read only

Table 4-4. TI OTP Bank 0 Sector Information Field Descriptions
Bit

Field

Value

31-24

Reserved

23-16

BX_NUM_Sectors

0

Description
Reserved. All bits will be read as 0.

1-32

Number of sectors in this bank.

15

B7

1

1 = Bank 7 is present

14

B6

0

0 = Bank 6 is not present

13

B5

0

0 = Bank 5 is not present

12

B4

0

0 = Bank 4 is not present

11

B3

0

0 = Bank 3 is not present

10

B2

0

0 = Bank 2 is not present

9

B1

1

1 = Bank 1 is present

8

B0

1

1 = Bank 0 is present

7-0

NUM_Banks

2 or 3

Number of banks on this part.

Table 4-5. TI OTP Sector Information AddressBankTI OTP Address

0F008 0158h

1F008 2158h

2F008 4158h

3F008 6158h

4F008 8158h

5F008 A158h

6F008 C158h

7F008 E158h

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

181

Memory Map

4.4.2.2

www.ti.com

Package and Memory Size

Package and memory size information can be determined from the device-specific datasheet, or can becomputed by reading locations in the TI OTP Bank 0 registers.
The package and memory size can be read from TI OTP location F008 015Ch as shown in Figure 4-4 anddescribed in Table 4-6.
Figure 4-4. TI OTP Bank 0 Package and Memory Size Information (F008 015Ch)
31

28

27

16

Reserved

PACKAGE

R

R

15

0
MEMORY_SIZER

LEGEND: R = Read only

Table 4-6. TI OTP Bank 0 Package and Memory Size Information Field Descriptions
Bit

Field

Description

31-28

Reserved

Reserved

27-16

PACKAGECount of pins in the package

15-0

MEMORY_SIZEFlash memory size in Kbytes

4.4.2.3

LPO Trim and Max HCLKThe HF LPO trim solution, LF LPO trim solution and maximum HCLK frequency can be read from TI OTP
location F008 01B4h as shown in Figure 4-5 and described in Table 4-7.
Figure 4-5. TI OTP Bank 0 LPO Trim and Max HCLK Information (F008 01B4h)
31

24

23

16

HFLPO_TRIM

LFLPO_TRIM

R

R

15

0
MAX_HCLKR

LEGEND: R = Read only

Table 4-7. TI OTP Bank 0 LPO Trim and Max HCLK Information Field Descriptions
Bit

Field

Description

31-24

HFLPO_TRIMHF LPO Trim Solution

23-16

LFLPO_TRIMLF LPO Trim Solution

15-0

MAX_HCLK

Maximum HCLK Speed

182

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Power On, Power Off Considerations

www.ti.com

4.4.2.4

Part Number Symbolization

Device part number symbolization information can be determined from the device-specific datasheet or
can be computed by reading locations in the TI OTP bank 0 registers.
The device part number symbolization can be read from TI OTP bank 0 location F008 01E0h throughF008 01FFh, as shown in Figure 4-6.
Figure 4-6. TI OTP Bank 0 Symbolization Information (F008 01E0h-F008 01FFh)
0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x54

0x4D

0x53

0x35

0x37

0x30

0x4C

0x53

0x33

0x31

0x33

0x37

0x43

0x50

0x47

0x45

R
0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x51

0x51

0x31

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

R
LEGEND: R = Read only

4.4.2.5

Deliberate ECC Errors for FMC ECC Checking

Deliberate single-bit and double-bit errors have been placed in the OTP for checking the FMC ECC
functionality. Any portion of the 64 bits in TI OTP bank 0 location F008 03F0h through F008 03F7h asshown in Figure 4-7 will generate a single-bit error. Any portion of the 64 bits in TI OTP bank 0 location
F008 03F8h through F008 03FFh as shown in Figure 4-7 will generate a double-bit error.
Figure 4-7. TI OTP Bank 0 Deliberate ECC Error Information (F008 03F0h-F008 03FFh)
0x00

0x04

0x08

0x0C

0x12345678

0x9ABCDEF1

0x12345678

0x9ABCDEF3

R

R

R

R

LEGEND: R = Read only, ECC is calculated for the value 0x123456789ABCDEF0

4.5

Power On, Power Off Considerations

4.5.1 Error Checking at Power On
As the device is coming out of the device reset sequence the Flash wrapper reads two configuration
words from the TI OTP section of bank 0. During these reads ECC is enabled. Single-bit errors arecorrected and uncorrectable errors will generate an ESM group 3 channel 7 error event. The ERROR pin

4.5.2 Flash Integrity at Power Off
If power is lost during a programming or erase operation, a power-on reset must be asserted before thecore supply voltage drops below specification. The PORRST pin has a glitch filter that means that the
PORRST pin must be asserted low tf(nPORRST) (2 µs) before the core supply drops below VccMIN (1.14V). If
this requirement is met, then the bits being programmed when PORRST goes low are indeterminate;however, the other bits in the Flash are not disturbed. Likewise, if this requirement is met, and PORRST isasserted while erasing, the sector or sectors being erased will have indeterminate bits; however, the othersectors in the same bank and the other banks will not be disturbed.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

183

Emulation and SIL3 Diagnostic Modes

4.6

www.ti.com

Emulation and SIL3 Diagnostic Modes

4.6.1 System Emulation
During emulation when the SUSPEND signal is high, the data read from memory is still passed to
SECDED for correction if ECC_ENABLE is active. If a correctable error is detected, then it is corrected but
an error event is not generated and the error occurrence counter is not incremented if in profiling mode. If
a double error is detected, then the raw data is returned without generating a double-error signal.
The SUSPEND signal can be disable by using the SUSP_IGNR bit in the Flash error detection andcorrection control register 1 (FEDACCTRL1). The SUSPEND signal should not be confused with thesuspend_now operation for the FSM.

4.6.2 Diagnostic Mode
The Flash wrapper can be put in diagnostic mode to verify various logic. There are multiple diagnostic
modes supported by the wrapper. A specific diagnostic mode is selected via the DIAG_MODE control bitsin the diagnostic control register (FDIAGCTRL), as listed in Table 4-8.
The diagnostic mode is only enabled by a 4-bit key stored in the DIAG_EN_KEY bits in FDIAGCTRL
register. Only DIAG_EN_KEY = 5h enables any diagnostic mode and all diagnostic modes use the
DIAG_TRIG bit in FDIAGCTRL register to initiate the action.
All tests run from any pipeline mode. Some of the diagnostic modes can corrupt the Flash data access,and generate errors as part of the test. Running in non-pipeline may minimize some of these conditions.
For all modes it is best to follow this sequence:
1. Write 5h to the DIAG_EN_KEY bits and set the desired DIAG_MODE control bits. This blocks many
UERR sources.
2. Set any data registers needed for this mode.
3. Write 1 to the DIAG_TRIG bit to initiate the action and allow UERRs to happen for one cycle.
4. Write Ah to the DIAG_EN_KEY bits to disable the diagnostic modes.
When the CONF_TYPE is 5 then the ECC logic is in the CPU and most of diagnostic modes are removed.
Some because the logic they test no longer exists and the others because the path is validated via the
ECC path to the CPU.
Table 4-8. DIAG_MODE Encoding
Mode

184

DIAG_MODE Bits

Description

0

0

0

0

Diagnostic mode is disabled. Same as DIAG_EN_KEY not equal to 5h.

1

0

0

1

ECC Data Correction test mode

2

0

1

0

ECC Syndrome Reporting test mode

3

0

1

1

ECC Malfunction test mode 1 (same data)

4

1

0

0

ECC Malfunction test mode 2 (inverted data)

5

1

0

1

Address Tag Register test mode

6

1

1

0

Reserved

7

1

1

1

ECC Data Correction Diagnostic test mode

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Emulation and SIL3 Diagnostic Modes

www.ti.com

4.6.2.1

ECC Data Correction Test Mode: DIAG_MODE = 1

This diagnostic mode can be enabled while ECC logic is also enabled for normal bank read. The Flashwrapper will arbitrate the usage of the ECC logic if a conflict occurs between a normal bank read anddiagnostic checking.
When in diagnostic data correction mode, FEMU_xxxx registers contain the 64-bit EEPROM emulation
data register, the 19-bit emulation address register and the 8-bit emulation check-bit register. These
values are used to enter diagnostic data to exercise the SECDED logic. The user can apply a value withan error in any bit location. When the DIAG_TRIG is set, the SECDED calculation is done and thecorrected values are saved back into the same FEMU_xxxx registers. The error position register is also
updated to indicate the bit position in error. Either ERR_ONE_FLG or ERR_ZERO_FLG bit is set when acorrectable error is detected. The D_COR_ERR bit will also be set in FEDACSTATUS register. For
uncorrectable error, the error status bit ERR_PRF_FLG is set as well as the D_UNC_ERR bit in the sameregister. Status bits should be cleared by the user before applying a new diagnostic data.
It takes multiple CPU transactions to preload the registers with diagnostic values. During this time, theresult of the diagnostic logic such as comparator can change. User should apply a trigger by setting
DIAG_TRIG bit to 1 as a qualifier after all registers are loaded with intended values. The DIAG_TRIG
serves to validate the diagnostic result. Only when DIAG_TRIG is high and a failing result in the diagnostic
logic will update the corresponding status flag and the position register.
4.6.2.2

ECC Syndrome Reporting Test Mode: DIAG_MODE = 2

When in diagnostic syndrome reporting mode, the resulting syndrome calculated by SECDED is captured
into the ECC check-bit register FEMU_ECC. The syndrome can be read by the user and compare with aknown syndrome value. Diagnostic data in FEMU_DxSW and FEMU_ADDR is not corrected and the error
position register is not updated. The FEDACSTATUS register error bits are not updated during this mode.
For devices with ECC_IN_CPU (CONF_TYPE = 5), the resulting FEMU_ECC value represents the 32-bit
byte swapped values. Here, bytes 7654_3210 are rearranged to 4567_0123. For instance, if the syndrome
shows an error in data bit 33, it would really be an error in EMU_DMW bit 57. You can also XOR the data
bit position with “011000”. (21h XOR 18h => 39h)
NOTE: The user should pre-load the registers with the test values with DIAG_TRIG = 0. After all test
values are written, the DIAG_TRIG should then be set high to validate the diagnostic result.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

185

Emulation and SIL3 Diagnostic Modes

4.6.2.3

www.ti.com

ECC Malfunction Test Mode 1: DIAG_MODE = 3

There are three inputs to the malfunction detection logic: the resulting syndrome, the original uncorrected
data, and the final corrected data.
In normal function, the malfunction detection logic will detect an error if the syndrome is 0 and if the data
before correction and the data after the correction is not equal or if the syndrome is not 0 and if the data
before correction and data after the correction is equal to each other. During diagnostic mode 3 or 4, user
supplied values are sent to the malfunction logic. No functional checking is done by the ecc_malfunction
logic while the mode is 3 or 4.
Diagnostic mode 3 is also known as “same data” mode. A diagnostic value can be stored in the ECCcheckbit register. The value stored in the 64-bit Raw data register will be supplied to the two inputs of themalfunction comparator logic. If a non-zero value is stored in the Raw ECC checkbit register(FRAW_ECC), then the malfunction logic should detect it as an error. The DIAG_TRIG is set to initiate thismode.
4.6.2.4

ECC Malfunction Test Mode 2: DIAG_MODE = 4This mode is also known as “inverted data” mode. A diagnostic value can be stored in the ECC checkbit
register. A value stored in the 64-bit Raw data register and its bit-wise inverted counterpart will be supplied
to the two inputs of the malfunction comparator logic. If a zero value is stored in the Raw ECC checkbit
register (FRAW_ECC), then the malfunction logic should detect it as an error.
Set the DIAG_ECC_SEL bits before entering mode 4 or enter mode 4 from a non-mode 4 and set the
DIAG_ECC_SEL bits at the same time.
4.6.2.5

Address Tag Register Test Mode: DIAG_MODE = 5
NOTE: The test code for Diag mode 5 needs to be executed from RAM or when executed from
Flash, the Flash Address Wait State (ASWSTEN) bit in the FRDCNTL register should be set
to 1. This is due to conflicting accesses by the CPU and Flash wrapper during the test
execution.

There are four sets of address tag registers. Each set consists of a primary and a duplicate address tag
registers. Normally, these registers store the recently issued CPU addresses during pipeline mode. To
detect errors in these registers, the primary and duplicate address tag registers are continuously
compared to each other if the buffer is valid. If they are different, then an address tag register error event
is generated.
These registers are memory-mapped. All primary address tag registers are memory-mapped to one
address and, likewise, all duplicate tag registers are mapped to another single address. During diagnostic
mode, each individual set can be selected by the DIAG_BUF_SEL (Diagnostic Buffer Select) bit in the
FDIAGCTRL register. User-supplied values can be written into the selected set during a diagnostic mode.
If different values are written into the primary and the duplicate address tag registers, then the
ADD_TAG_ERR (Address Tag Error) flag in the FEDACSTATUS register will be set. This diagnostic mode
uses the FRAW_DATAL register to supply the alternate address when DIAG_TRIG is set. The
FUNC_ERR_ADD register will not contain useful information during Diag mode 5. It will also trigger thenormal uncorrectable register freeze.
All address tags and buffer valid bits will be cleared to 0 when leaving Diag mode 5. Going to mode 5 andback out clears the pipeline buffers and is useful for other test modes also. No functional checking is doneby the address tag logic while the Diag mode is 5.
NOTE: The user should pre-load the registers with the test values with DIAG_TRIG = 0. After all test
values are written, the DIAG_TRIG should then be set high to validate the diagnostic result.

186

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Emulation and SIL3 Diagnostic Modes

www.ti.com

4.6.2.6

ECC Data Correction Diagnostic Test Mode: DIAG_MODE = 7

Testing the error correction and ECC logic in the CPU involves corrupting the ECC value returned to theCPU. By inverting one or more bits of the ECC, the CPU will detect errors in a selected data or ECC bit, orin any possible value returned by the ECC.
To set an error for a particular bit, use the syndrome (see Section 4.3.3). For example, if you want tocorrupt data bit 62 then put the value 5Bh into the test register.
The method uses the DATA_INV_PAR value in the FPAR_OVR register to alter the ECC during a slaveaccess cycle. The value in the DATA_INV_PAR register is XORed with the current ECC to give a bad
ECC value to the CPU. This only occurs when DIAG_MODE is 7, PAR_OVR_KEY in the FPAR_OVR
register is 5h, DIAG_EN_KEY in the FDIAGCTRL register is 5h, and the access is a slave cycle.
This mode can set the FEDACSTATUS register status error bits B1_UNC_ERR or ERR_ZERO_FLG, but
it will not set the D_UNC_ERR nor D_COR_ERR bits.
The sequence to do this test is:
1. Make sure the true DMA module is off.
2. Put 5h in BUS_PAR_DIS and 5h in PAR_OVR_KEY fields (00005Axxh) of the FPAR_OVR register.
3. Put the desired value in DAT_INV_PAR field of the FPAR_OVR register.
4. Put 7h in DIAG_MODE and 5h in DIAG_EN_KEY fields of the FDIAGCTRL register.
5. Read desired address from the mirrored Flash location. Mirrored Flash starts at address 0x20000000.
6. Put 0 in DIAG_MODE or Ah in one of the key fields to turn off this test.
7. Check error registers (FCOR_ERR_ADD, FEDACSTATUS, and FUNC_ERR_ADD) for ECC errors.
8. Repeat as necessary to test out the ECC.
9. Put 0 in DIAG_MODE field of the FDIAGCTRL register and Ah in both of the key fields to completely
disable this test at the end of the test.
10. Put 2h in PAR_OVR_KEY field (00005400h) of the FPAR_OVR register to clear DAT_INV_PAR field.

4.6.3 Diagnostic Mode Summary
The following tables give a summary of the input registers needed for each mode, the possible registers
that can change and the possible error bits in FEDACSTATUS that may set.
Table 4-9. Bus1 Diagnostic Mode Summary
DIAG
MODE Name

InputsPossible Outputs

Possible Error Bits
Set

Notes

1

ECC Data Correction
test mode

Not Applicable

2

ECC Syndrome Reporting
test mode

Not Applicable

3

ECC Malfunction
test mode 1

Not Applicable

4

ECC Malfunction
test mode 2

Not Applicable

5

Address Tag Register
test mode

FPRIM_ADD_TAG

FUNC_ERR_ADD (1)

ADD_TAG_ERR

FUNC_ERR_ADD

B1_UNC_ERR

FCOR_ERR_ADD

ERR_ZERO_FLG

FDUP_ADD_TAG
FRAW_DATAL(1)

6

Reserved

7

ECC Data Correction
Diagnostic test mode

DAT_INV_PAR

Slave access only

Register output value changes, but does not contain useful information.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

187

Emulation and SIL3 Diagnostic Modes

www.ti.com

Table 4-10. Bus 2 and ECC Diagnostic Mode Summary
DIAG
MODE Name
1

ECC Data Correction
test mode

InputsPossible Outputs

Possible Error Bits Set

FEUM_DMSWFEMU_ECC

D_UNC_ERR

FEMU_DLSWFUNC_ERR_ADD

D_COR_ERR

FEMU_ECC

FCOR_ERR_ADD

ERR_ONE_FLG

FEMU_ADDRFCOR_ERR_POS

ERR_ZERO_FLG

Notes

ERR_PRF_FLG
FEMU_ECC

EE_D_UNC_ERR

EE_UNC_ERR_ADD

EE_D_COR_ERR

EE_COR_ERR_ADD

EE_ERR_ONE_FLG

EE_COR_ERR_POS

EE_ERR_ZERO_FLG
EE_ERR_PRF_FLG

2

ECC Syndrome
Reporting test mode

FEMU_DMSWFEMU_ECCNA

FRAW_DATAHFRAW_DATAH (1)ECC_B2_MAL_ERR

FRAW_DATALFRAW_DATAL (1)

D_UNC_ERR

FRAW_ECCFRAW_ECC (1)

FEMU_DLSWFEMU_ECCFEMU_ADDR

3ECC Malfunction
test mode 1

FUNC_ERR_ADD (1)FRAW_DATAH (1)

EE_CMEFRAW_DATAL (1)EE_D_UNC_ERR

FRAW_ECC (1)EE_UNC_ERR_ADD (1)4ECC Malfunction
test mode 2

FRAW_DATAHFRAW_DATAH (2)

COMB2_MAL_G

FRAW_DATALFRAW_DATAL (2)ECC_B2_MAL_ERR

FRAW_ECCFRAW_ECC(2)

D_UNC_ERR

FUNC_ERR_ADD (2)FRAW_DATAH (2)

EE_CMGFRAW_DATAL (2)

EE_CMEFRAW_ECC(2)

EE_D_UNC_ERR

EE_UNC_ERR_ADD (2)

(1)
(2)

188

5

Address Tag Register
test modeNot applicable

6

Reserved

Not applicable

7

ECC Data Correction
Diagnostic test modeNot applicable

Register output value will change, but will not contain useful information.
Register output value will change, but will not contain useful information.

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Emulation and SIL3 Diagnostic Modes

www.ti.com

Table 4-11. Port Signals Diagnostic Mode Summary
Uncorrectable
Error

Correctable
Error

Address Bus
Parity Error

FEE
Uncorrectable
Error

FEE
Correctable
Error

Error InESM Group 3
Channel 7

ESM Group 1
Channel 6

ESM Group 2
Channel 4

ESM Group 1
Channel 36

ESM Group 1
Channel 35

ECC Data Correction
test mode

Bus 2

Yes

Yes

No

No

No

EEPROM

No

No

No

Yes

Yes

ECC Syndrome
Reporting test mode

Bus 2

No

No

No

No

No

EEPROM

No

No

No

No

No

3

ECC Malfunction
test mode 1

Bus 2

Yes

No

No

No

No

EEPROM

No

No

No

Yes

No

4

ECC Malfunction
test mode 2

Bus 2

Yes

No

No

No

No

EEPROM

No

No

No

Yes

No

Yes

No

No

No

No

DIAG
MODE Name12

5

Address Tag Register Bus 1
test mode

6

Reserved

—

—

—

—

—

—

7

ECC Data Correction
Diagnostic test mode

Bus 1

Yes

Yes

No

No

No

4.6.4 Read Margin
When the bits are programmed or erased, they are checked against a program_verify or erase_verify
reference level that is far away from the normal read reference point. Over time, bit levels may drift toward
the normal read point and if it is too much then a bit will read the wrong value. To counteract this, the bits
can be read using different read_margin reference points to give an early detection of the problem. The
bits can then be either re-programmed (most common) or the sector can be erased and reprogrammed.

4.7

Control Registers
This section details the Flash module registers, summarized in Table 4-12. A detailed description of eachregister and its bits is also provided.
The Flash module control registers can only be read and/or written by the CPU while in privileged mode.
Each register begins on a word boundary. All registers are 32-bit, 16-bit and 8-bit accessible. The start
address of the Flash module is FFF8 7000h.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

189

Control Registers

www.ti.com

Table 4-12. Flash Control Registers

190

OffsetAcronym

Register Description

00h

FRDCNTL

Flash Option Control Register

Section 4.7.1

Section08h

FEDACTRL1

Flash Error Detection and Correction Control Register 1

Section 4.7.2

0Ch

FEDACTRL2

Flash Error Detection and Correction Control Register 2

Section 4.7.3

10h

FCOR_ERR_CNT

Flash Correctable Error Count Register

Section 4.7.4

14h

FCOR_ERR_ADD

Flash Correctable Error Address Register

Section 4.7.5

18h

FCOR_ERR_POS

Flash Correctable Error Position Register

Section 4.7.6

1Ch

FEDACSTATUS

Flash Error Detection and Correction Status Register

Section 4.7.7

20h

FUNC_ERR_ADD

Flash Un-Correctable Error Address Register

Section 4.7.8

24h

FEDACSDIS

Flash Error Detection and Correction Sector Disable Register

Section 4.7.9

28h

FPRIM_ADD_TAG

Flash Primary Address Tag Register

Section 4.7.10

2Ch

FDUP_ADD_TAG

Flash Duplicate Address Tag Register

Section 4.7.11

30h

FBPROT

Flash Bank Protection Register

Section 4.7.12

34h

FBSE

Flash Bank Sector Enable Register

Section 4.7.13

38h

FBBUSY

Flash Bank Busy Register

Section 4.7.14

3Ch

FBAC

Flash Bank Access Control Register

Section 4.7.15

40h

FBFALLBACKFlash Bank Fallback Power Register

Section 4.7.16

44h

FBPRDY

Flash Bank/Pump Ready Register

Section 4.7.17

48h

FPAC1

Flash Pump Access Control Register 1

Section 4.7.18

4Ch

FPAC2

Flash Pump Access Control Register 2

Section 4.7.19

50h

FMAC

Flash Module Access Control Register

Section 4.7.20

54h

FMSTAT

Flash Module Status Register

Section 4.7.21

58h

FEMU_DMSWEEPROM Emulation Data MSW Register

Section 4.7.22

5Ch

FEMU_DLSWEEPROM Emulation Data LSW Register

Section 4.7.23

60h

FEMU_ECCEEPROM Emulation ECC Register

Section 4.7.24

68h

FEMU_ADDREEPROM Emulation Address Register

Section 4.7.25

6Ch

FDIAGCTRL

Diagnostic Control Register

Section 4.7.26

70h

FRAW_DATAH

Uncorrected Raw Data High Register

Section 4.7.27

74h

FRAW_DATAL

Uncorrected Raw Data Low Register

Section 4.7.28

78h

FRAW_ECC

Uncorrected Raw ECC Register

Section 4.7.29

7Ch

FPAR_OVR

Parity Override Register

Section 4.7.30

C0h

FEDACSDIS2

Flash Error Detection and Correction Sector Disable Register 2

Section 4.7.31

288h

FSM_WR_ENA

FSM Register Write Enable

Section 4.7.32

2A4h

FSM_SECTOR

FSM Sector Register

Section 4.7.33

2B8h

EEPROM_CONFIGEEPROM Emulation Configuration Register

Section 4.7.34

308h

EE_CTRL1

EEPROM Emulation Error Detection and Correction Control Register 1

Section 4.7.35

30Ch

EE_CTRL2

EEPROM Emulation Error Detection and Correction Control Register 2

Section 4.7.36

310h

EE_COR_ERR_CNT

EEPROM Emulation Correctable Error Count Register

Section 4.7.37

314h

EE_COR_ERR_ADD

EEPROM Emulation Correctable Error Address Register

Section 4.7.38

318h

EE_COR_ERR_POS

EEPROM Emulation Correctable Error Bit Position Register

Section 4.7.39

31Ch

EE_STATUSEEPROM Emulation Error Status Register

Section 4.7.40

320h

EE_UNC_ERR_ADD

EEPROM Emulation Un-Correctable Error Address Register

Section 4.7.41

400h

FCFG_BANK

Flash Bank Configuration Register

Section 4.7.42

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.1 Flash Option Control Register (FRDCNTL)FRDCNTL supports pipeline mode. This register controls Flash timings for the main Flash banks. For theequivalent register that controls Flash timings for the EEPROM Emulation Flash bank (bank 7), see
Section 4.7.34.
Figure 4-8. Flash Option Control Register (FRDCNTL) [offset = 00h]
31

16
Reserved
R-0
15

12

11

8

Reserved

RWAIT

R-0

R/WP-1

7

5

4

3

1

0

Reserved

ASWSTEN

Reserved

ENPIPE

R-0

R/WP-0R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-13. Flash Option Control Register (FRDCNTL) Field Descriptions
Bit

Field

Value

31-12

Reserved

0

11-8

RWAIT

0-Fh

Description
Reads return 0. Writes have no effect.
Random/data Read Wait StateThe random read wait state bits indicate how many wait states are added to a Flash readaccess. In Pipeline mode there is always one wait state even when RWAIT is set to 0.
Note: The required wait states for each HCLK frequency can be found in the device-specificdata sheet.

7-5

Reserved

4

ASWSTEN

0

Reads return 0. Writes have no effect.
Address Setup Wait State Enable0

Address Setup Wait State is disabled.

1

Address Setup Wait State is enabled. Address is latched one cycle before decoding todetermine pipeline hit or miss. Address Setup Wait State is only available in pipeline mode.
Note: The required address wait state for each HCLK frequency can be found in the devicespecific data sheet.

3-1

Reserved

0

ENPIPE0

Reads return 0. Writes have no effect.
Enable Pipeline Mode0

Pipeline mode is disabled.

1

Pipeline mode is enabled.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

191

Control Registers

www.ti.com

4.7.2 Flash Error Detection and Correction Control Register 1 (FEDACCTRL1)
This register controls ECC event detection for the main Flash banks. For the equivalent register that
controls ECC event detection for the EEPROM Emulation Flash bank (bank 7), see Section 4.7.35.
Figure 4-9. Flash Error Detection and Correction Control Register 1 (FEDACCTRL1) [offset = 08h]
31

25

24

Reserved

SUSP_IGNR

R-0

R/WP-0

23

20

19

16

Reserved

EDACMODE

R-0

R/WP-Ah

15

10

9

8

Reserved

11

EOFEN

EZFEN

EPEN

R-0

R/WP-0R/WP-0R/WP-07

4

3

0Reserved

EDACEN

R-0

R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-14. Flash Error Detection and Correction Control Register 1 (FEDACCTRL1)
Field Descriptions
Bit

Field

31-25

Reserved

24

Value
0

SUSP_IGNR

Description
Reads return 0. Writes have no effect.
Suspend Ignore.
In emulation mode, for example, viewing memory in the debugger's window, the CPU
suspend signal is set. This bit determines whether the CPU suspend signal is ignored by theFlash module.

0

CPU suspend signal blocks error bits setting and un-freezing.
The Flash module blocks all errors from setting the error bits in emulation mode and blocks
the un-freezing of the bits and registers by reading the FUNC_ERR_ADD register.

1

CPU suspend has no effect on error bit setting and un-freezing.
The Flash module ignores the CPU suspend signal and allows the error bits to set even inemulation mode. It also allows the Flash module to un-freeze the error bits and otherregisters by reading the FUNC_ERR_ADD register even in emulation mode.

23-20

Reserved

19-16

EDACMODE

0

Reads return 0. Writes have no effect.
Error Correction Mode for the main Flash banks. For EEPROM Emulation Flash bank (bank7), see Section 4.7.35.

5h

All other values

Single-bit errors during reads from OTP, ECC and the mirrored space (starting at
0x20000000) of banks 0 through 6, will be treated as uncorrectable errors by the Flashwrapper. The wrapper will assert an ESM group 3 error on channel 7 and the ERROR pin
will be activated. No abort will be taken by the CPU.
Single-bit errors during reads from OTP, ECC and the mirrored space (starting at
0x20000000) of banks 0 through 6, will be treated as correctable errors by the Flashwrapper. The wrapper will assert an ESM group 1 error on channel 6. The single-bit error will
be corrected.
Note: This mode does not affect reads from the main program Flash starting at address 0.
Note: Reading ECC bits will generate an ECC error based on the contents of the 8 ECC bits
and the 64 data bits they protect

15-11

192

Reserved

0

Reads return 0. Writes have no effect.

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

Table 4-14. Flash Error Detection and Correction Control Register 1 (FEDACCTRL1)
Field Descriptions (continued)
Bit

Field

10

EOFEN

Value

Description
Event on Ones Fail Enable0

No ESM error event is generated on a single-bit error where a 1 reads as a 0 when readingfrom the OTP or ECC memory locations.

1

An ESM error event is generated on a single-bit error where a 1 reads as a 0 when readingfrom the OTP or ECC memory locations.
Note: When either the EOFEN or the EZFEN bit is set, an error event will be generated on
ESM group 1 channel 6 when any correctable error is generated by reading the main
memory9

EZFEN

Event on Zeros Fail Enable0

No ESM error event is generated on a single-bit error where a 0 reads as a 1 when readingfrom the OTP or ECC memory locations.

1

An ESM error event is generated on a single-bit error where a 0 reads as a 1 when readingfrom the OTP or ECC memory locations.
Note: When either the EOFEN or the EZFEN bit is set, an error event will be generated on
ESM group 1 channel 6 when any correctable error is generated by reading the main
memory8

EPEN

Error Profiling Enable.
0Error profiling is disabled.

1

Error profiling is enabled.
The correctable error event is generated (ESM group 1 channel 6) when the number of CPU
accesses of correctable bit errors detected and corrected has reached the threshold value
defined in the FEDACCTRL2 register.

7-4

Reserved

3-0

EDACEN0

Reads return 0. Writes have no effect.
Error Detection and Correction Enable5h

CPU single and double error event signals are blocked.
Note: It is recommended to enable ECC in the Flash wrapper by writing Ah to these bits
before enabling ECC in the CPU. If ECC is enabled in the CPU, but not in the wrapper, theCPU will still check and correct single-bit ECC errors, and generate aborts on uncorrectableerrors for the main Flash. However, the generation of ESM events, the capture of failingaddresses and the detections and correction of errors in the OTP will be prevented.

All other values

Error Detection and Correction events are captured and sent to the ESM

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

193

Control Registers

www.ti.com

4.7.3 Flash Error Correction and Correction Control Register 2 (FEDACCTRL2)This register applies to ECC event detection for the main Flash banks. For the equivalent register thatapplies to the EEPROM Emulation Flash bank (bank 7), see Section 4.7.36.
Figure 4-10. Flash Error Correction and Correction Control Register 2 (FEDACCTRL2) [offset =
0Ch]
31

16
Reserved
R-0

150
SEC_THRESHOLD
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-15. Flash Error Correction Control and Correction Register 2 (FEDACCTRL2)
Field Descriptions
Bit

Field

Value

31-16

Reserved

15-0

SEC_THRESHOLD

0

Description
Reads return 0. Writes have no effect.

0FFFFhSingle Error Correction Threshold
When error profiling is enabled, this register contains the threshold value for the SEC(single error correction) occurrences before a correctable error event is generated (ESM
group 1, channel 6). A threshold of 0 disables the threshold so that it does not generate an
event.

4.7.4 Flash Correctable Error Count Register (FCOR_ERR_CNT)
This register applies to the main Flash banks. For the equivalent register that applies to the EEPROM
Emulation Flash bank (bank 7), see Section 4.7.37.
Figure 4-11. Flash Corectable Error Count Register (FCOR_ERR_CNT) [offset = 10h]31

16
Reserved
R-0

150
FERRCNT
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-16. Flash Correctable Error Count Register (FCOR_ERR_CNT) Field Descriptions
Bit

Field

Value

31-16

Reserved

0

15-0

FERRCNT

0-FFFFh

Description
Reads return 0. Writes have no effect.
Single Error Correction Count
This register contains the number of SEC (single error correction) occurrences. Writing any
value to this register resets the count value to 0. The counter resets to 0 when it increments tobe equal to the single error correction threshold. This register only increments when profilingmode is enabled. This register is not affected by the EOFEN or EZEFEN error control bits in the
FEDACCTRL1 register.

194

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.5 Flash Correctable Error Address Register (FCOR_ERR_ADD)
This register applies to the main Flash banks. For the equivalent register that applies to the EEPROM
Emulation Flash bank (bank 7), see Section 4.7.38.
The error address is captured during errors when either EOFEN or EZFEN enable bit is set. During error
profiling mode when only EPEN is set, the error address is not captured if a correctable error is detected.
This register is frozen while either the ERR_ZERO_FLG or the ERR_ONE_FLG bit is set in the
FEDACSTATUS register.
During emulation mode, this address is frozen even when read. By setting the SUSP_IGNR bit to 1 in the
FEDACCTRL1 register, this register can be un-frozen in emulation mode.
This register is not changed with the reset signal and contains unknown data at power-up.
Figure 4-12. Flash Correctable Error Address Register (FCOR_ERR_ADD) [offset = 14h]
31

16
COR_ERR_ADD
R-u

15

3

2

0

COR_ERR_ADD

B_OFF

R-u

R-u

LEGEND: R = Read only; -n = value after reset; -u = unchanged value on internal reset, cleared on power up

Table 4-17. Flash Correctable Error Address Register (FCOR_ERR_ADD) Field Descriptions
Bit

Field

Description

31-3

COR_ERR_ADD

Correctable Error Address
COR_ERR_ADD records the CPU logical address of which a correctable error is detected by the
ECC logic. This error address is frozen from begin updated until it is read by the CPU. Additional
error are blocked until this register is read.

2-0

B_OFF

Byte Offset
Since ECC is checked on 64 bit data, when checking main memory or OTP, the address captured
is aligned to a 64-bit boundary with address bits[2:0] equal to 0.When reading from the ECC bytes,
these bits will indicate the failing address of the ECC location associated with the failure. Whenreading an ECC byte, the ECC is checked against the 64 data bits they protect.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

195

Control Registers

www.ti.com

4.7.6 Flash Correctable Error Position Register (FCOR_ERR_POS)
This register applies to the main Flash banks. For the equivalent register that applies to the EEPROM
Emulation Flash bank (bank 7), see Section 4.7.39.
Note: The bit error position is only detected during reads of the OTP, the mirrored Flash image or the
ECC bytes. Single-bit errors corrected during reads of the main memory will only capture the failingaddress, but not the bit position. The bit position is captured during errors when either EOFEN or EZFEN
enable bit is set. During error profiling mode when only EPEN is set, the bit position is not captured if acorrectable error is detected. This register is frozen while either the ERR_ZERO_FLG or the
ERR_ONE_FLG bit is set in the FEDACSTATUS register.
During emulation mode, this address is frozen even when read. By setting the SUSP_IGNR bit to 1 in the
FEDACCTRL1 register, this register can be un-frozen in emulation mode.
This register is not changed with the reset signal and contains unknown data at power-up.
Figure 4-13. Flash Correctable Error Position Register (FCOR_ERR_POS) [offset = 18h]31

16Reserved
R-0

15

9

8

Reserved

10

BUS2

TYPE

7
ERR_POS

0

R-0

R-u

R-u

R-u

LEGEND: R = Read only; -n = value after reset; -u = unchanged value on internal reset, cleared on power up

Table 4-18. Flash Correctable Error Position Register (FCOR_ERR_POS) Field Descriptions
Bit

Field

31-10

Reserved

9

8

7-0

196

Value
0

BUS2

Reads return 0. Writes have no effect.
Bus 2 Error

0

The error was in the main Flash1

The error was from an OTP read

TYPE

ERR_POS

Description

ErrorType0

The error was one of the 64 data bits

1

The error was one of the 8 check bits

0-FFh

The bit address of the single-bit error.

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.7 Flash Error Detection and Correction Status Register (FEDACSTATUS)
This register applies to the main Flash banks. For the equivalent register that applies to the EEPROM
Emulation Flash bank (bank 7), see Section 4.7.40.
All these error status bits can be cleared by writing a 1 to the bit; writing a 0 has no effect.
The correctable errors in bits 2:0, and FSM_DONE bit 24, must be cleared before the end of their error
event service routine or else the error event will re-issue.
Figure 4-14. Flash Error Detection and Correction Status Register (FEDACSTATUS) [offset = 1Ch]
31

25

23

24

Reserved

FSM_DONE

R-0

RCP-u

20
Reserved

19

18

COMB2_MAL_ ECC_B2_MAL_
G
ERR

R-0

17

16

B2_UNC_ERR

B2_COR_
ERR

RCP-u

RCP-u

RCP-u

RCP-u

12

11

10

9

8

Reserved

D_UNC_ERR

ADD_TAG_ERR

ADD_PAR_
ERR

Reserved

B1_UNC_
ERR

R-0

RCP-u

RCP-u

RCP-u

R-0

RCP-u

15

13

7

3

2

1

0

Reserved

4

D_COR_ERR

ERR_ONE_FLG

ERR_ZERO_FLG

ERR_PRF_
FLG

R-0

RCP-u

RCP-u

RCP-u

RCP-u

LEGEND: R = Read only; RCP = Read and Clear in Privilege Mode; -n = value after reset; -u = unchanged value on internal reset, clearedon power up

Table 4-19. Flash Error Detection and Correction Status Register (FEDACSTATUS)
Field Descriptions
Bit

Field

31-25 Reserved
24

Value Description
0

FSM_DONE

Reads return 0. Writes have no effect.
Flash State Machine Done
This bit is set to 1 when the Flash state machine completes a program or erase operation.
This bit will generate an interrupt on VIM channel 61 if the FSM_EVT_EN bit of the
FSM_ST_MACHINE register is set. This bit must be cleared by writing a 1 to it in theinterrupt routine to clear the interrupt request.

23-20 Reserved
19

0

COMB2_MAL_G

Reads return 0. Writes have no effect.
Bus 2 Compare Malfunction Flag.

0Compare Malfunction detected on the Bus2 SECDED in diagnostic mode 4 or not in
diagnostic mode

1

Compare Malfunction not detected on the Bus2 SECDED or entered diagnostic mode 4This bit becomes 1 when entering diagnostic mode 4, with DIAG_ECC_SEL field set to 0
or 1, and will be cleared if diagnostic mode 4 triggers an error. This bit will reset to 0 andwill be 0 outside of diagnostic mode 4. Writing a 1 will set this bit to 1 only in diagnostic
mode 4 otherwise writes have no effect.

18

17

ECC_B2_MAL_ ERR

Bus 2 ECC Malfunction Error Flag
0

SECDED malfunction not detected on Bus2

1

SECDED malfunction detected on Bus2

B2_UNC_ERR

Bus 2 uncorrectable error
0

No bus 2 uncorrectable errors were detected1

A bus 2 uncorrectable error was detected
Two or more bits in the data, or ECC field; or a single-bit error in the address field havebeen found in error. Address-bit errors are considered an uncorrectable error. The
FUNC_ERR_ADD register should contain the Bus2 error location. This error will generate
an ESM group 3 channel 7 event.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

197

Control Registers

www.ti.com

Table 4-19. Flash Error Detection and Correction Status Register (FEDACSTATUS)
Field Descriptions (continued)
Bit

Field

16

B2_COR_ERR

Value Description
Bus 2 Correctable Error0

No bus2 correctable error was detected1

A bus 2 correctable error was detected
One bit in the data, or ECC field has been found in error. Either the ERR_ONE_FLAG or
ERR_ZERO_FLAG should be set in this register along with this bit. The
FCOR_ERR_ADD register should contain the error address, and the FCOR_ERR_POS
register should contain the failing bit position. This error will generate an ESM group 1channel 6 event.

15-13 Reserved
120

D_UNC_ERR

Reads return 0. Writes have no effect.
Diagnostic Uncorrectable Error
This bit sets when diagnostic mode 1 discovers a multi-bit error using he ECC. Thismeans two or more bits in the data, address or ECC field have been found in error. The
ECC is capable of correcting a single-bit error and this would show up in bit 3
D_COR_ERR. The ECC can always detect two bit errors. Three or more bit errors may
escape detection with the ECC. This bit also may set during other uncorrectable errors
and during the diagnostic mode like address tag errors and ECC malfunctions.

11

ADD_TAG_ERR

Address Tag Register Error Flag
0

Address Tag Register Error not detected

1

Address Tag Register Error detected.
This bit is set if the primary address tag has a hit but the duplicate address tag does notmatch the primary address tag. This bit is functional only when pipeline mode is enabled.
This error will create an ESM group 3 channel 7 event.

10

ADD_PAR_ERR

Address Parity Error Flag
0

No address parity error was detected.

1

A parity error was detected on the incoming address bus.
The full 32 bit address will be stored in FUNC_ERR_ADD register. This error will create
an ESM group 2 channel 4 event.

9

Reserved

8

B1_UNC_ERR

0

Reads return 0. Writes have no effect.
Bus 1 Uncorrectable Error Flag

0

No Bus 1 uncorrectable errors were detected1

A bus 1 uncorrectable error was detected
Two or more bits in the data, or ECC field; or a single-bit error in the address field havebeen found in error. Address-bit errors are considered an uncorrectable error. The
FUNC_ERR_ADD register will contain the Bus1 error location. This error will generate an
ESM group 3 channel 7 event.

7-4

Reserved

3

D_COR_ERR

0

Reads return 0. Writes have no effect.
Diagnostic Correctable Error Status Flag
This bit sets when diagnostic mode 1 discovers a single-bit correctable error using the
ECC. Multi-bit errors are flagged using the D_UNC_ERR bit. The uncorrectable error
address must be unfrozen in order to set this bit.

2

ERR_ONE_FLG

Error on One Fail Status Flag
0

No correctable error where a 1 read as a 0 on bus 2

1

A correctable error occurred on bus 2 where a 1 read as a 0
This bit is set if the EOFEN (Error on One Fail Enable) bit is set then, and one bit in thedata, or ECC field that should have been read as a 1, read as a 0. During the read the bit
is corrected to a 1. The FCOR_ERR_ADD register will contain the bus 2 error address,
and the FCOR_ERR_POS register will contain the failing bit position. This error will
generate an ESM group 1 channel 6 event. When this bit is set, the B2_CORR_ERR bit
will also be set. This error will generate an ESM group 1 channel 6 event.

198

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

Table 4-19. Flash Error Detection and Correction Status Register (FEDACSTATUS)
Field Descriptions (continued)
Bit

Field

1

ERR_ZERO_ FLG

Value Description
Error on Zero Fail Status Flag
0

No correctable errors on bus1 nor any correctable errors on bus 2 where a 0 was read asa1

1

A correctable error occurred on bus 1, or a correctable error occurred on bus 2 where a 0
was read as a 1
This bit is set if the EZFEN (Error on Zero Fail Enable) bit is set and a correctable error is
detected on bus 2 where a 0 is read as a 1 and corrected to be a 0, or if either the EZFEN
or the EOFEN bits are set and any single-bit error is detected and corrected on bus 1.
The FCOR_ERR_ADD register will contain the error address. If the error was on bus 2,
then the B2_COR_ERR bit will also be set and the FCOR_ERR_POS register will containthe failing bit position. The FCOR_ERR_POS register will not indicate the failing bit
position for a bus 1 error. This error will generate an ESM group 1 channel 6 event.

0

ERR_PRF_FLG

Error Profiling Status Flag
0

Error profiling is not enabled, or the number of correctable errors has not reached thethreshold programmed into the SEC_THRESHOLD register1

Error profiling is enabled and the number of correctable errors has reached the thresholdprogrammed into the SEC_THRESHOLD register

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

199

Control Registers

www.ti.com

4.7.8 Flash Uncorrectable Error Address Register (FUNC_ERR_ADD)
This register applies to ECC event detection for the main Flash banks. For the equivalent register thatapplies to the EEPROM Emulation Flash bank (bank 7), see Section 4.7.41.
During emulation mode, this address is frozen even when read. By setting the SUSP_IGNR bit to 1 in the
FEDACCTRL1 register, this register can be un-frozen in emulation mode.
This register is not changed with the reset signal and contains unknown data at power-up.
Figure 4-15. Flash Uncorrectable Error Address Register (FUNC_ERR_ADD) [offset = 20h]
31

16
UNC_ERR_ADD
R-u

15

3

2

0

UNC_ERR_ADD

B_OFF

R-u

R-u

LEGEND: R = Read only; -n = value after reset; -u = unchanged value on internal reset, cleared on power up

Table 4-20. Flash Uncorrectable Error Address Register (FUNC_ERR_ADD) Field Descriptions
Bit

Field

Description

31-3

UNC_ERR_ADD

Uncorrectable Error Address
UNC_ERR_ADD records the CPU logical address of which an uncorrectable error is detected by
the ECC logic in the CPU. The UNC_ERR_ADD also captures the error address when a address
bus parity mismatch is detected. This error address is frozen from begin updated until it is read by
the CPU. Additional error are blocked until this register is read.
This register captures the full 32 bit incoming address when there is a bus parity error. It only
captures address of 22:3 for multiple bit ECC errors. Address parity errors take priority over othererrors that happen in the same cycle.

2-0

B_OFF

Byte offset
Since ECC is checked on 64 bit data, when checking main memory or OTP, the address captured
is aligned to a 64-bit boundary with address bits[2:0] equal to 0.When reading from the ECC bytes,
these bits will indicate the failing address of the ECC location associated with the failure. Whenreading an ECC byte, the ECC is checked against the 64 data bits they protect.

200

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.9 Flash Error Detection and Correction Sector Disable Register (FEDACSDIS)
This register is used to disable the SECDED function for one or two sectors from the EEPROM Emulation
Flash (bank 7). An additional two sectors can have SECDED disabled by the use of the FEDACSDIS2
register (see Section 4.7.31).
Figure 4-16. Flash Error Detection and Correction Sector Disable Register (FEDACSDIS)[offset = 24h]
31

29

28

BankID1_Inverse

Rsvd

SectorID1_inverse

BankID1

Rsvd

SectorID1

RWP-0

R-0

RWP-0

RWP-0

R-0

RWP-0

15

27

24

11

8

23

21

7

5

20

19

4

16

13

12

BankID0_Inverse

Rsvd

SectorID0_inverse

BankID0

Rsvd

3
SectorID0

0

RWP-0

R-0

RWP-0

RWP-0

R-0

RWP-0

LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-21. Flash Error Detection and Correction Sector Disable Register (FEDACSDIS)
Field Descriptions
Bit

Field

Value

31-29 BankID1_Inverse

Description
The bank ID inverse bits are used with the bank ID bits to select the bank for which a
sector is disabled. The only bank that supports sector disable is bank 7.

0

If BankID1 = 7h and BankID1_inverse = 0, then if a valid sector is selected by SectorID1
and SectorID1_inverse that sector will have ECC checking disabled.

All othervaluesNo sector is disabled by disable ID 1.

Reserved

0

Read returns 0. Writes have no effect.

27-24 SectorID1_inverse

0-Fh

28

23-21 BankID1

The bank ID bits are used with the bank ID inverse bits to select the bank for which a
sector is disabled. The only bank that supports sector disable is bank 7.
7h20

Reserved

19-16 SectorID1

No sector is disabled by disable ID 1.

0

Read returns 0. Writes have no effect.

0-Fh

Reserved
SectorID0_inverse

7-5

BankID0

The sector ID bits are used with the sector ID inverse bits to determine which sector isdisabled. If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID
inverse bits are not an inverse of the sector ID bits, then no sector is disabled by disable
ID 1.
The bank ID inverse bits are used with the bank ID bits to select the bank for which a
sector is disabled. The only bank that supports sector disable is bank 7.

012

If BankID1 = 7h and BankID1_inverse = 0, then if a valid sector is selected by SectorID1
and SectorID1_inverse that sector will have ECC checking disabled.

All othervalues15-13 BankID0_Inverse

11-8

The sector ID inverse bits are used with the sector ID bits to determine which sector isdisabled. If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID
inverse bits are not an inverse of the sector ID bits, then no sector is disabled by disable
ID 1.

If BankID0 = 7h and BankID0_inverse = 0, then if a valid sector is selected by SectorID0
and SectorID0_inverse that sector will have ECC checking disabled.

All othervaluesNo sector is disabled by disable ID 0.

0

Read returns 0. Writes have no effect.

0-Fh

The sector ID inverse bits are used with the sector ID bits to determine which sector isdisabled. If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID
inverse bits are not an inverse of the sector ID bits, then no sector is disabled by disable
ID 0.
The bank ID bits are used with the bank ID inverse bits to select the bank for which a
sector is disabled. The only bank that supports sector disable is bank 7.

7h
All othervaluesIf BankID0 = 7h and BankID0_inverse = 0, then if a valid sector is selected by SectorID0
and SectorID0_inverse that sector will have ECC checking disabled.
No sector is disabled by disable ID 0.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

201

Control Registers

www.ti.com

Table 4-21. Flash Error Detection and Correction Sector Disable Register (FEDACSDIS)
Field Descriptions (continued)
Bit

Field

4

Reserved0

3-0SectorID0

0-Fh

202

Value

Description
Read returns 0. Writes have no effect.
The sector ID bits are used with the sector ID inverse bits to determine which sector isdisabled. If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID
inverse bits are not an inverse of the sector ID bits, then no sector is disabled by disable
ID 0.

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.10 Primary Address Tag Register (FPRIM_ADD_TAG)
This register is used to test the pipeline address tag registers (see Section 4.6.2.5).
Figure 4-17. Primary Address Tag Register (FPRIM_ADD_TAG) [offset = 28h]3116
PRIM_ADD_TAG[31:16]
RWP-0

15

4

3

0

PRIM_ADD_TAG[15:4]

0000

RWP-0

R-0

LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode;; -n = value after reset;

Table 4-22. Primary Address Tag Register (FPRIM_ADD)_TAG Field Descriptions
Bit

Field

31-4

PRIM_ADD_TAG

Value

Description

0-FFF FFFFh

Primary Address Tag Register
The primary address tag register selected by the DIAG_BUF_SEL bits in the
FDIAGCTRL register is memory-mapped here. This register can only be written inprivileged mode when diagnostic mode is enabled with DIAG_EN_KEY = 5h and
DIAG_MODE = 5h in the FDIAGCTRL register. This register is not updated with newFlash data if DIAG_EN_KEY is not equal to 5h or DIAG_MODE is 0 or 7h. Valid reads
can occur in any mode. The register clears when an address tag error is found andwhen leaving DIAG_MODE 5.

3-0

Reserved

0

Reads return 0. Writes have no effect.

4.7.11 Duplicate Address Tag Register (FDUP_ADD_TAG)
This register is used to test the pipeline address tag registers (see Section 4.6.2.5).
Figure 4-18. Duplicate Address Tag Register (FDUP_ADD_TAG) [offset = 2Ch]
31

16
DUP_ADD_TAG[31:16]
RWP-0

15

4

3

0

DUP_ADD_TAG[15:4]

0000

RWP-0

R-0

LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode;; -n = value after reset;

Table 4-23. Duplicate Address Tag Register (FDUP_ADD)_TAG Field Descriptions
Bit

Field

31-4

DUP_ADD_TAG

Value

Description

0-FFF FFFFh

Primary Address Tag Register
The duplicate address tag register selected by the DIAG_BUF_SEL bits in the
FDIAGCTRL register is memory-mapped here. This register can only be written inprivileged mode when diagnostic mode is enabled with DIAG_EN_KEY = 5h and
DIAG_MODE = 5h in the FDIAGCTRL register. This register is not updated with newFlash data if DIAG_EN_KEY is not equal to 5h or DIAG_MODE is 0 or 7h. Valid reads
can occur in any mode. The register clears when an address tag error is found andwhen leaving DIAG_MODE 5.

3-0

Reserved

0

Reads return 0. Writes have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

203

Control Registers

www.ti.com

4.7.12 Flash Bank Protection Register (FBPROT)
Figure 4-19. Flash Bank Protection Register (FBPROT) [offset = 30h]
31

16
Reserved
R-0

15

1

0

Reserved

PROTL1DIS

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-24. Flash Bank Protection Register (FBPROT) Field Descriptions
Bit

Field

31-1

Reserved

0

PROTL1DIS

Value
0

Description
Reads return 0. Writes have no effect.
Level 1 Protection Disable bit
Setting this bit disables protection from writing to the OTPPROTDIS bits in the FBAC register aswell as the BSE bits for all banks in the FBSE register. Clearing this bit enables protection anddisables write access to the OTPPROTDIS bits and FBSE register.

0

Level 1 protection is enabled.

1

Level 1 protection is disabled.

4.7.13 Flash Bank Sector Enable Register (FBSE)
FBSE provides one enable bit per sector for up to 16 sectors per bank. Each bank in the Flash module
has one FBSE register. The bank is selected via the BANK bits in the FMAC register. As only one bank at
a time can be selected by FMAC, only the register for the bank selected appears at this address.
Figure 4-20. Flash Bank Sector Enable Register (FBSE) [offset = 34h]
31

16
Reserved
R-0

150
BSE[15:0]
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-25. Flash Bank Sector Enable Register (FBSE) Field Descriptions
Bit

Field

31-16

Reserved

15-0

BSE

Value
0

Description
Reads return 0. Writes have no effect.
Bank Sector Enable
Each bit corresponds to a Flash sector in the bank specified by the FMAC register. Bit 0
corresponds to sector 0, bit 1 corresponds to sector 1, and so on. These bits can be set only when
PROTL1DIS = 1 in the FBPROT register and in privilege mode.

204

0

The corresponding numbered sector is disabled for program or erase access.

1

The corresponding numbered sector is enabled for program or erase access.

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.14 Flash Bank Busy Register (FBBUSY)
Figure 4-21. Flash Bank Busy Register (FBBUSY) [offset = 38h]
31

16
Reserved
R-0

15

8

7

0

Reserved

BUSY[7:0]

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 4-26. Flash Bank Busy Register (FBBUSY) Field Descriptions
Bit

Field

31-8

Reserved

7-0

BUSY

Value
0

Description
Reads return 0. Writes have no effect.
Bank Busy. Each bit corresponds to a Flash bank.

0

The corresponding bank is not busy

1

The corresponding bank is busy with a state machine or bus 2 operation, or the bank is not
implemented

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

205

Control Registers

www.ti.com

4.7.15 Flash Bank Access Control Register (FBAC)
Figure 4-22. Flash Bank Access Control Register (FBAC) [offset = 3Ch]
31

24

23

16

Reserved

OTPPROTDIS[7:0]

R-0

R/WP-0

15

8

7

0

BAGP

VREADST

R/WP-0R/WP-FhLEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-27. Flash Bank Access Control Register (FBAC) Field Descriptions
Bit

Field

31-24

Reserved

23-16

OTPPROTDIS

15-8

BAGP

Value
0

Description
Reads return 0. Writes have no effect.
OTP Sector Protection Disable. Each bit corresponds to a Flash bank. This bit can be set only
when PROTL1DIS = 1 in the FBPROT register and in privilege mode.

0

Programming of the OTP sector is disabled.

1

Programming of the OTP sector is enabled.

0-FFh

Bank Active Grace Period.
These bits contain the starting count value for the BAGP down counter. Any access to a given bankcauses its BAGP counter to reload the BAGP value for that bank. After the last access to this Flashbank, the down counter delays from 0 to 255 prescaled HCLK clock cycles before putting the bankinto one of the fallback power modes as determined by the FBFALLBACK register. This value must
be greater than 1 when the fallback mode is not ACTIVE.
Note: The prescaled clock used for the BAGP down counter is a clock divided by 16 from HCLK.

7-0

VREADST

0-FFh

VREAD Setup.
VREAD is generated by the Flash pump and used for Flash read operation. The bank power up
sequencing starts VREADST HCLK cycles after VREAD power supply becomes stable.
Note: There is not a programmable Bank Sleep counter and Standby counter register. The numberof clock cycles to transition from sleep to standby and standby to active is hardcoded in the Flashwrapper design.

206

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.16 Flash Bank Fallback Power Register (FBFALLBACK)
Figure 4-23. Flash Bank Fallback Power Register (FBFALLBACK) [offset = 40h]
31

16
Reserved
R-505h

15

14

13

4

3

2

1

0

BANKPWR7

Reserved

BANKPWR1BANKPWR0

R/WP-3h

R-3FFhR/WP-3h

R/WP-3h

LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-28. Flash Bank Fallback Power Register (FBFALLBACK) Field Descriptions
Bit

Field

Value

Description

31-16

Reserved505h

Do not write to these register bits

15-14

BANKPWR7

13-4

Reserved

3-2

BANKPWR1

1-0

Bank 7 Fallback Power Mode.
0Bank sleep mode

1hBank standby mode

2h

Reserved

3hBank active mode

3FFh

Do not write to these register bits.
Bank 1 Fallback Power Mode.

0Bank sleep mode

1hBank standby mode

2h

Reserved

3hBank active mode

BANKPWR0

Bank 0 Fallback Power Mode.
0Bank sleep mode

1hBank standby mode

2h

Reserved

3hBank active mode

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

207

Control Registers

www.ti.com

4.7.17 Flash Bank/Pump Ready Register (FBPRDY)
Figure 4-24. Flash Bank/Pump Ready Register (FBPRDY) [offset = 44h]
31

15

24

23

16

Reserved

BANKBUSY[n]R-0

R-1 (Unimplemented banks) or R-0 (Implemented banks)

14

8

7

0

PUMP
RDY

ReservedBANKRDY[n]

R-1

R-0

R-1

LEGEND: R = Read only; -n = value after reset

Table 4-29. Flash Pump Access Control Register 1 (FPAC1) Field Descriptions
Bit

Field

31-24

Reserved

23-16

BANKBUSY[7:0]

Value
0

Description
Read returns 0. Writes have no effect.
Bank busy bits (one bit for each bank)0

The bank is not busy.

1

The bank is busy, not ready or this bank is not implemented
Note: A bank is considered busy if it is being accessed by the TCM, Bus2 or the Flash statemachine.

15

PUMPRDY

14-8

Reserved

7-0

BANKRDY[7:0]208Flash pump ready flag0

Pump is not ready (Code must be executing from somewhere other than internal Flash)1

Pump is ready for Flash accesses

0

Read returns 0. Writes have no effect.
Bank ready bits (one bit for each bank)0Flash bank is in the sleep or standby state1

Flash bank is in the active state, or the bank is not implemented

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.18 Flash Pump Access Control Register 1 (FPAC1)
Figure 4-25. Flash Pump Access Control Register 1 (FPAC1) [offset = 48h]
31

27

26

16

Reserved

PSLEEP

R-0

R/WP-C8h15

1

0

Reserved

PUMPPWR

R-0

R/WP-1LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-30. Flash Pump Access Control Register 1 (FPAC1) Field Descriptions
Bit

Field

31-12

Reserved

26-16

PSLEEP

Value
0

Description
Reads return 0. Writes have no effect.

0-7FFh Pump Sleep.
These bits contain the starting count value for the charge pump sleep down counter. While thecharge pump is in sleep mode, the power mode management logic holds the charge pump sleep
counter at this value. When the charge pump exits sleep power mode, the down counter delays
from 0 to PSLEEP pump sleep down clock cycles before putting the charge pump into active power
mode.
Note: Pump sleep down counter clock is a divide by 2 input of HCLK. That is, there are 2 × HCLK
cycles for every PSLEEP counter cycle.

15-1

Reserved

0

PUMPPWR0

Reads return 0. Writes have no effect.
Flash Charge Pump Fallback Power Mode0

Sleep (all pump circuits disabled)

1

Active (all pump circuits active)

4.7.19 Flash Pump Access Control Register 2 (FPAC2)
Figure 4-26. Flash Pump Access Control Register 2 (FPAC2) [offset = 4Ch]
31

16
Reserved
R-0

15

0
PAGP
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-31. Flash Pump Access Control Register 2 (FPAC2) Field Descriptions
Bit

Field

31-16

Reserved

15-0

PAGP

Value
0
0-FFFFh

Description
Reads return 0. Writes have no effect.
Pump Active Grace Period
This register contains the starting count value for the PAGP mode down counter. Any access toFlash memory causes the counter to reload with the PAGP value. After the last access to Flashmemory, the down counter delays from 0 to 65535 prescaled HCLK clock cycles before
entering one of the charge pump fallback power modes as determined by PUMPPWR in the
FPAC1 register.
Note: The PAGP down counter is clocked by the same prescaled clock as the BAGP down
counter that is a divide by 16 of HCLK.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

209

Control Registers

www.ti.com

4.7.20 Flash Module Access Control Register (FMAC)
Figure 4-27. Flash Module Access Control Register (FMAC) [offset = 50h]
31

16
Reserved
R-0

15

3

2

0

Reserved

BANK

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-32. Flash Module Access Control Register (FMAC) Field Descriptions
Bit

Field

31-16

Reserved

2-0

BANK

Value
0
0-7h

Description
Reads return 0. Writes have no effect.
Bank Enable.
These bits select which bank is enabled for operations such as local register access, OTP sector
access, and program/erase commands. These bits select only one bank at a time from up to eightbanks depending on the specific device being used. For example, a 000 selects bank 0; 011 selectsbank 3.
Note: BANK can identify up to 8 Flash banks. If BANK is selected for an un-implemented bank,then the BANK will set itself to the number of an implemented bank. To determine if a bank isimplemented, write the bank number to BANK and read back the value to see if what was written
can be read back.

210

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.21 Flash Module Status Register (FMSTAT)
Figure 4-28. Flash Module Status Register (FMSTAT) [offset = 54h]
31

16
Reserved
R-0
15

14

13

12

11

10

9

8

Reserved

ILA

Reserved

PGV

R-0

R-0

R-0

R-0

Reserved

EV

Reserved

BUSY

R-0

R-0

R-0

R-0

7

6

5

4

3

2

1

0

ERS

PGM

INV-DATCSTATVOLTSTAT

ESUSP

PSUSP

SLOCK

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-33. Flash Module Status Register (FMSTAT) Field Descriptions
Bit

Field

31-15

Reserved

14

Value
0

ILA

Description
Read returns 0. Writes have no effect.
Illegal Address
When set, indicates that an illegal address is detected. Three conditions can set illegal address
flag.
1.
2.
3.
4.
5.

13

Reserved

12

PGV

0

Writing to a hole (un-implemented logical address space) within a Flash bank.
Writing to an address location to an un-implemented Flash space.
Input address for write is decoded to select a different bank from the bank ID register.
The address range does not match the type of FSM command. For example, the erase_sector
command must match the address regions.
TI-OTP address selected but CMD_EN in FSM_ST_MACHINE is not set.

Read returns 0. Writes have no effect.
Program Verify
When set, indicates that a word is not successfully programmed after the maximum allowed
number of program pulses are given for program operation.

11

Reserved

10

EV

0

Read returns 0. Writes have no effect.
Erase Verify
When set, indicates that a sector is not successfully erased after the maximum allowed number oferase pulses are given for erase operation. During Erase verify command, this flag is set
immediately if a bit is found to be 0.

9

Reserved

0

Read returns 0. Writes have no effect.

8

BUSY

When set, this bit indicates that a program, erase, or suspend operation is being processed.

7

ERS

Erase Active
When set, this bit indicates that the Flash module is actively performing an erase operation. This bit
is set when erasing starts and is cleared when erasing is complete. It is also cleared when theerase is suspended and set when the erase resumes.

6

PGM

Program Active
When set, this bit indicates that the Flash module is currently performing a program operation. Thisbit is set when programming starts and is cleared when programming is complete. It is also cleared
when programming is suspended and set when programming is resumes.

5

INVDAT

Invalid Data
When set, this bit indicates that the user attempted to program a “1” where a “0” was alreadypresent. This bit is cleared by the Clear Status command.

4

CSTAT

Command Status
Once the FSM starts any failure will set this bit. When set, this bit informs the host that the
program, erase, or validate sector command failed and the command was stopped. This bit iscleared by the Clear Status command. For some errors, this will be the only indication of an FSM
error because the cause does not fall within the other error bit types.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

211

Control Registers

www.ti.com

Table 4-33. Flash Module Status Register (FMSTAT) Field Descriptions (continued)
Bit

Field

3

VOLTSTAT

Value

Description
Core Voltage Status
When set, this bit indicates that the core voltage generator of the pump power supply dipped below
the lower limit allowable during a program or erase operation. This bit is cleared by the Clear Statuscommand.

2

ESUSP

Erase Suspended
When set, this bit indicates that the Flash module has received and processed an erase suspend
operation. This bit remains set until the erase resume command has been issued or until the
Clear_More command is run.

1

PSUSP

Program Suspended
When set, this bit indicates that the Flash module has received and processed a program suspend
operation. This bit remains set until the program resume command has been issued or until the
Clear_More command is run.

0

SLOCK

Sector Lock Status
When set, this bit indicates that the operation was halted because the target sector was locked forerasing and programming either by the sector protect bit or by OTP write protection disable bits.
(Bits BSE in FBSE register or OTPPROTDIS in register FBAC). This bit is cleared by the Clear
Status command.
No SLOCK FSM error will occur if all sectors in a bank erase operation are set to 1. All the sectors
will be checked but no SLOCK will be set if no operation occurs due to the SECT_ERASED bits
being set to all 1s. A SLOCK error will occur if attempting to do a sector erase with either BSE iscleared or SECT_ERASED is set.

212

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.22 EEPROM Emulation Data MSW Register (FEMU_DMSW)The Flash module controller includes hardware support computing the check bits for ECC, based on thedata and address being programmed into the EEPROM emulation array. To utilize this capability, theaddress to be programmed is written to the FEMU_ADDR register and the data to be programmed is
written to the FEMU_DMSW and FEMU_DLSW registers. The write to FEMU_DLSW triggers an ECC
calculation and the resulting check bits are available in the FEMU_ECC register. The value from
FEMU_ECC can then be used to program the check bits into the EEPROM emulation array for theparticular data word over which they were calculated.
Figure 4-29. EEPROM Emulation Data MSW Register (FEMU_DMSW) [offset = 58h]
31

0
EMU_DMSW[63:32]
RWP-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; -n = value after reset

Table 4-34. EEPROM Emulation Data MSW Register (FEMU_DMSW) Field Descriptions
Bit

Field

Description

31-0

EMU_DMSWEEPROM Emulation Most-Significant Data Word.
The most-significant data word of the 64-bits of data for which the ECC check bits are to be calculatedshould be programmed into this register.
This register is also used in diagnostic modes 1 and 2 where it supplies the upper data for checking the
SECDED hardware.

4.7.23 EEPROM Emulation Data LSW Register (FEMU_DLSW)The Flash module controller includes hardware support computing the check bits for ECC, based on thedata and address being programmed into the EEPROM emulation array. To utilize this capability, theaddress to be programmed is written to the FEMU_ADDR register and the data to be programmed is
written to the FEMU_DMSW and FEMU_DLSW registers. The write to FEMU_DLSW triggers an ECC
calculation and the resulting check bits are available in the FEMU_ECC register. The value from
FEMU_ECC can then be used to program the check bits into the EEPROM emulation array for theparticular data word over which they were calculated.
Figure 4-30. EEPROM Emulation Data LSW Register (FEMU_DLSW) [offset = 5Ch]
31

0
EMU_DLSW[31:0]
RWP-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; -n = value after reset

Table 4-35. EEPROM Emulation Data LSW Register (FEMU_DLSW) Field Descriptions
Bit

Field

Description

31-0

EMU_DLSW

EEPROM Emulation Least-Significant Data Word.
The least-significant data word of the 64-bits of data for which the ECC check bits are to be calculatedshould be programmed into this register.
This register is also used in diagnostic modes 1 and 2 where it supplies the lower data for checking the
SECDED hardware.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

213

Control Registers

www.ti.com

4.7.24 EEPROM Emulation ECC Register (FEMU_ECC)
NOTE: This register is only available when the module is configured to use the ECC logic;
otherwise, this register is reserved.

The Flash module controller includes hardware support computing the check bits for ECC, based on thedata and address being programmed into the EEPROM emulation array. To utilize this capability, theaddress to be programmed is written to the FEMU_ADDR register and the data to be programmed is
written to the FEMU_DMSW and FEMU_DLSW registers. The write to FEMU_DLSW triggers an ECC
calculation and the resulting check bits are available in the FEMU_ECC register. The value from
FEMU_ECC can then be used to program the check bits into the EEPROM emulation array for theparticular data word over which they were calculated.
Figure 4-31. EEPROM Emulation ECC Register (FEMU_ECC) [offset = 60h]
31

16
Reserved
R-0

15

8

7

0

Reserved

EMU_ECC[7:0]

R-0

R/WP-3h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; -n = value after reset

Table 4-36. EEPROM Emulation ECC Register (FEMU_ECC) Field Descriptions
Bit

Field

31-8

Reserved

7-0

EMU_ECC

Value

Description

0

Reserved
EEPROM Emulation ECC Check Bit Value.
This register contains the ECC check bits calculated by the FMC controller based on the address
written to FEMU_ADDR and the 64-bits of data written to FEMU_DMSW and FEMU_DLSW.
This register is also used in the diagnostic modes 1 and 2. In these modes, this register supplies
the ECC data for checking the SECDED. In mode 1, this register is filled with the desired ECC andafter the DIAG_TRIG is set this register is set to the ECC value returned from the SECDED
selected by DIAG_ECC_SEL. DIAG_EN_KEY and DIAG_TRIG must be set to fill this register in the
diagnostic modes. Writes to FEMU_DxSW will not affect this register in diagnostic modes 1 or 2.
In mode 2, this register is filled with the desired ECC and after the DIAG_TRIG is set this register is
set to the syndrome value returned from the SECDED selected by DIAG_ECC_SEL.
This register is only available when the module is configured to use the ECC logic; otherwise, it is a
reserved register.

214

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.25 EEPROM Emulation Address Register (FEMU_ADDR)The Flash module controller includes hardware support computing the check bits for ECC, based on thedata and address being programmed into the EEPROM emulation array. To utilize this capability, theaddress to be programmed is written to the FEMU_ADDR register and the data to be programmed is
written to the FEMU_DMSW and FEMU_DLSW registers. The write to FEMU_DLSW triggers an ECC
calculation and the resulting check bits are available in the FEMU_ECC register. The value from
FEMU_ECC can then be used to program the check bits into the EEPROM emulation array for theparticular data word over which they were calculated.
Figure 4-32. EEPROM Emulation Address Register (FEMU_ADDR) [offset = 68h]
31

22

21

16

Reserved

EMU_ADDR[21:16]

R-0

RWP-0

15

3

2

1

EMU_ADDR[15:3]

Reserved

RWP-0

R-0

0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; -n = value after reset

Table 4-37. EEPROM Emulation Address Register (FEMU_ADDR) Field Descriptions
Bit

Field

31-22

Reserved

Value
0

21-3

EMU_ADDR

0-7 FFFFh

Description
Reserved. Writes have no effect. It is not necessary to mask these upper ten bits whenwriting the address of bank 7 locations (0xF002xxxx); however, these bits are not used in
calculating the ECC value and will read back as 0.
EEPROM Emulation Address.
The address of the 64-bit data word over which ECC is to be calculated is written to thisfield. Note that only bits 21:3 are actually written and used for the calculation. The other bits
(31:22 and 2:0) are ignored, but do not need to be masked off before being written to thisregister.
This register is also used in diagnostic modes 1 and 2 where it supplies the address bits forchecking the SECDED hardware.

2-0

Reserved

0

Reserved. Writes have no effect. The lower three bits of the CPU address are not used in
the ECC calculation to align the data on a 64-bit boundary. These bits will read back as 0.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

215

Control Registers

www.ti.com

4.7.26 Diagnostic Control Register (FDIAGCTRL)First set the DIAG_MODE and the DIAG_EN_KEY bits before setting up the other registers to block theother registers from causing a false error. The final write should set the DIAG_TRIG bit to activate the test.
Running out of RAM will prevent problems with the diagnostic test corrupting the Flash access in some of
the modes.
Figure 4-33. Diagnostic Control Register (FDIAGCTRL) [offset = 6Ch]
31

25
Reserved
R-0

15

14

12

11

10

24

23

20

19

16

DIAG_TRIG

Reserved

DIAG_EN_KEY

R/WP-0R-0

R/WP-Ah

9

8

7

3

2

0

Rsvd

DIAG_ECC_SEL

Reserved

DIAG_BUF_
SEL

Reserved

DIAG_MODE

R-0

R/WP-0R-0

R/WP-0R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; -n = value after reset

Table 4-38. Diagnostic Control Register (FDIAGCTRL) Field Descriptions
Bit

Field

31-25 Reserved
24

Value

Description

0

Reserved

DIAG_TRIG

Diagnostic Trigger
Diagnostic trigger is the final qualifier for the diagnostic result. After setting all theother diagnostic register values, the DIAG_TRIG is set to 1. This activates thediagnostic logic for one access and then automatically clears the DIAG_TRIG value.
The DIAG_EN_KEY and DIAG_MODE bits must be set at least one cycle before
setting DIAG_TRIG.
This bit always reads as 0.

23-20 Reserved019-16 DIAG_EN_KEY

Reserved
Diagnostic Enable Key

5hDiagnostic mode is enabled.

All other values Diagnostic mode is disabled.
15

Reserved

014-12 DIAG_ECC_SEL

11-10 Reserved
9-8

216

Reserved
Diagnostic SECDED Select0

Select SECDED0 for diagnostic testing

1h

Select SECDED1 for diagnostic testing2h

Select SECDED2 for diagnostic testing (256 bit wide words only)

3h

Select SECDED3 for diagnostic testing (256 bit wide words only

4h

Select BUS2 SECDED for diagnostic testing5h

Select FEE SECDED for diagnostic testing (same ECC logic as BUS2, but sets the
FEE registers)

6h-7h

Reserved

0

Reserved

DIAG_BUF_ SEL

Diagnostic Buffer Select0

The DIAG_BUF_SEL selects the Instruction or Data buffer to read or write whenaccessing the FPRIM_ADD_TAG and FDUP_ADD_TAG registers. The address tags
consists of matching primary and duplicate address tag registers. All the primary
address tag registers are memory mapped to a common address (see Section 4.7.10)
and are selected by DIAG_BUF_SEL. The same occurs for the duplicate address (seeSection 4.7.11). Bit 0 selects a data buffer if high and an instruction buffer if low. Bit 1
indicates the buffer number.

0

Instruction Buffer 01hData Buffer 02h

Instruction Buffer 1

3hData Buffer 1

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

Table 4-38. Diagnostic Control Register (FDIAGCTRL) Field Descriptions (continued)
Bit

Field

7-4

Reserved

2-0

DIAG_MODE

Value

Description

0

Reserved
Diagnostic Mode0

Diagnostic mode is disabled. This is the same as DIAG_EN_KEY is not equal to 5h.

1hDiagnostic ECC Data Correction test mode (see Section 4.6.2.1)

2hDiagnostic ECC Syndrome Reporting test mode (see Section 4.6.2.2)

3h

ECC Malfunction test mode 1 (same data) (see Section 4.6.2.3)

4h

ECC Malfunction test mode 2 (inverted data) (see Section 4.6.2.4)5hAddress Tag Register test mode (see Section 4.6.2.5)

6hReserved

7h

ECC Data Correction Diagnostic test mode (see Section 4.6.2.6)

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

217

Control Registers

www.ti.com

4.7.27 Uncorrected Raw Data High Register (FRAW_DATAH)NOTE: Raw Data and Raw ECC registers can be loaded with diagnostic values only in diagnostic
modes 1 through 6 with DIAG_EN_KEY = 5h in the Diagnostic Control Register(FDIAGCTRL). These modes must be set for at least one clock cycle before writing to any
FRAW* register.

Figure 4-34. Uncorrected Raw Data High Register (FRAW_DATAH) [offset = 70h]
310
RAW_DATA[63:32]
RWP-u

LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; -n = value after reset; -u = Unchanged value on internal reset,
cleared on power up

Table 4-39. Uncorrected Raw Data High Register (FRAW_DATAH) Field Descriptions
Bit

Field

Description

31-0

RAW_DATA

Uncorrected Raw Data
This register contains the upper 32 bits of the 64-bit raw data used in diagnostic testing of the ECC logic.

4.7.28 Uncorrected Raw Data Low Register (FRAW_DATAL)NOTE: Raw Data and Raw ECC registers can be loaded with diagnostic values only in diagnostic
modes 1 through 6 with DIAG_EN_KEY = 5h in the Diagnostic Control Register(FDIAGCTRL). These modes must be set for at least one clock cycle before writing to any
FRAW* register.

Figure 4-35. Uncorrected Raw Data Low Register (FRAW_DATAL) [offset = 74h]
31

0
RAW_DATA[31:0]
RWP-u

LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; -n = value after reset -u = Unchanged value on internal reset,
cleared on power up

Table 4-40. Uncorrected Raw Data Low Register (FRAW_DATAL) Field Descriptions
Bit

Field

Description

31-0

RAW_DATA

Uncorrected Raw Data.
This register contains the lower 32 bits of the 64-bit raw data used in diagnostic testing of the ECC logic.

218

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.29 Uncorrected Raw ECC Register (FRAW_ECC)
NOTE: Raw Data and Raw ECC registers can be loaded with diagnostic values only in diagnostic
modes 1 through 6 with DIAG_EN_KEY = 5h in the Diagnostic Control Register(FDIAGCTRL). These modes must be set for at least one clock cycle before writing to any
FRAW* register.

Figure 4-36. Uncorrected Raw ECC Register (FRAW_ECC) [offset = 78h]
31

16
Reserved
R-0

15

9

8

7

0

Reserved

PIPE_BUF

RAW_ECC

R-0

R/WC-0R/WP-uLEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; C = Clear by writing a 1; -n = value after reset -u = Unchanged
value on internal reset, cleared on power up

Table 4-41. Uncorrected Raw ECC Register (FRAW_ECC) Field Descriptions
Bit

Field

31-9

Reserved

8

PIPE_BUF

7-0

RAW_ECC

Value

Description

0

Reserved
Error came from pipeline buffer hit

0This bit is cleared when the RAW_ECC field is updated with new valid information or by writing a 1
to this bit.

1

Latest error came from a pipeline buffer hit and the FRAW_DATH, FRAW_DATL, and RAW_ECC
fields will not contain information that matches the error address nor error status bits.

0-FFh

Uncorrected Raw ECC
This register contains the ECC data used in diagnostic testing of the ECC logic.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

219

Control Registers

www.ti.com

4.7.30 Parity Override Register (FPAR_OVR)
Figure 4-37. Parity Override Register (FPAR_OVR) [offset = 7Ch]
31

17

15

12

16

Reserved

BNK_INV_PAR

R-0

R/WP-0

11

9

8

7

0

BUS_PAR_DIS

PAR_OVR_KEY

ADD_INV_PAR

DAT_INV_PAR

R/WP-5h

R/WP-2h

R/WP-0R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-42. Parity Override Register (FPAR_OVR) Field Descriptions
Bit

Field

31-17

Reserved

16

15-12

Value

Description

0

Reserved

BNK_INV_PAR

Buffer Invert Parity. This bit is only implemented for parity configurations and is reserved for ECC
devices.
0

The SYS_ODD_PARITY value is used.

1

When 1 and PAR_OVR_KEY = 5h, then the current system parity signal SYS_ODD_PARITY is
inverted when doing bank parity calculations. This generates parity errors and causes interrupt
signals to be generated.

BUS_PAR_DIS

Disable Bus Parity. The read data parity is never disabled from this module.
Ah

The address bus parity error and buffer parity error are disabled and no checking is done and no
events are generated.

All other Any other value enables the parity checking on the Address bus and read data bus.
values11-9

PAR_OVR_KEY

Parity Override
5h

The selected ADD_INV_PAR and DAT_INV_PAR fields become active.

All other Any other value causes the module to use the global system parity bit in the system registervalues DEVCR1.
87-0

ADD_INV_PAR

Address Odd Parity. This bit is active only when PAR_OVR_KEY = 5h. This bit is set to the
SYS_ODD_PAR signal value on reset.
0

The SYS_ODD_PARITY value is used.

1

The incoming address bus inverts the system signal SYS_ODD_PARITY for parity calculations.
This causes parity errors and generate interrupt error signals.

DAT_INV_PAR

Data Odd Parity. This byte is active only when PAR_OVR_KEY = 5h.
0When 0 it will use the SYS_ODD_PARITY value.

1

The output read data inverts the system signal SYS_ODD_PARITY for parity calculations. This
causes parity errors and generates interrupt signals.
This byte can support up to a 64-bit data bus, but when the device has a 32-bit bus, bits 7:4 arereserved.
Bit 0 affects read bus bits 7:0, bit 1 affects read bus bits 15:8, and so on. Each active bit of this field
is set to the SYS_ODD_PAR signal value on reset.
The DAT_INV_PAR is used in the parity for the pipeline buffer logic and for the read data bus to theCPU.
When the ECC logic is in the CPU (CONF_TYPE = 5) and SIL3 is active, this field becomes the
ECC corrupting value for SIL3 diagnostic mode 7.
In diagnostic mode 7, the FPAR_OVR should be set to 00005Axxh to allow writes to the
DAT_INV_PAR field. This field should be written before entering diagnostic mode 7.

220F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.31 Flash Error Detection and Correction Sector Disable Register (FEDACSDIS2)
This register is used to disable the SECDED function for one or two sectors from the EEPROM Emulation
Flash (bank 7). An additional two sectors can have SECDED disabled by the use of the FEDACSDIS
register (see Section 4.7.9).
Figure 4-38. Flash Error Detection and Correction Sector Disable Register (FEDACSDIS2)[offset = C0h]
31

29

28

BankID3_Inverse

Rsvd

SectorID3_inverse

BankID3

Rsvd

SectorID3

RWP-0

R-0

RWP-0

RWP-0

R-0

RWP-0

15

27

24

11

8

23

21

7

5

20

19

4

16

13

12

BankID2_Inverse

Rsvd

SectorID2_inverse

BankID2

Rsvd

3
SectorID2

0

RWP-0

R-0

RWP-0

RWP-0

R-0

RWP-0

LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-43. Flash Error Detection and Correction Sector Disable Register (FEDACSDIS2)
Field Descriptions
Bit

Field

Value

31-29 BankID3_Inverse

Description
The bank ID inverse bits are used with the bank ID bits to select the bank for which a
sector is disabled. The only bank that supports sector disable is bank 7.

0

If BankID3 = 7h and BankID3_inverse = 0, then if a valid sector is selected by
SectorID3 and SectorID3_inverse that sector will have ECC checking disabled.

All other values No sector is disabled by disable ID 3.
28

Reserved

027-24 SectorID3_inverse

0-Fh

23-21 BankID3

Read returns 0. Writes have no effect.
The sector ID inverse bits are used with the sector ID bits to determine which sector isdisabled. If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID
inverse bits are not an inverse of the sector ID bits, then no sector is disabled bydisable ID 3.
The bank ID bits are used with the bank ID inverse bits to select the bank for which a
sector is disabled. The only bank that supports sector disable is bank 7.

7h

If BankID3 = 7h and BankID3_inverse = 0, then if a valid sector is selected by
SectorID3 and SectorID3_inverse that sector will have ECC checking disabled.

All other values No sector is disabled by disable ID 3.
20

Reserved

19-16 SectorID300-Fh

15-13 BankID2_Inverse

Read returns 0. Writes have no effect.
The sector ID bits are used with the sector ID inverse bits to determine which sector isdisabled. If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID
inverse bits are not an inverse of the sector ID bits, then no sector is disabled bydisable ID 3.
The bank ID inverse bits are used with the bank ID bits to select the bank for which a
sector is disabled. The only bank that supports sector disable is bank 7.

0

If BankID2 = 7h and BankID2_inverse = 0, then if a valid sector is selected by
SectorID2 and SectorID2_inverse that sector will have ECC checking disabled.

All other values No sector is disabled by disable ID 2.
12

Reserved

11-8

SectorID2_inverse

7-5

BankID2

00-Fh

Read returns 0. Writes have no effect.
The sector ID inverse bits are used with the sector ID bits to determine which sector isdisabled. If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID
inverse bits are not an inverse of the sector ID bits, then no sector is disabled bydisable ID 2.
The bank ID bits are used with the bank ID inverse bits to select the bank for which a
sector is disabled. The only bank that supports sector disable is bank 7.

7h

If BankID2 = 7h and BankID2_inverse = 0, then if a valid sector is selected by
SectorID2 and SectorID2_inverse that sector will have ECC checking disabled.

All other values No sector is disabled by disable ID 2.
4

Reserved

0

Read returns 0. Writes have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

221

Control Registers

www.ti.com

Table 4-43. Flash Error Detection and Correction Sector Disable Register (FEDACSDIS2)
Field Descriptions (continued)
Bit

Field

Value

Description

3-0

SectorID2

0-Fh

The sector ID bits are used with the sector ID inverse bits to determine which sector isdisabled. If the sector ID bits are not pointing to a valid sector (0-3) or the sector ID
inverse bits are not an inverse of the sector ID bits, then no sector is disabled bydisable ID 2.

222

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.32 FSM Register Write Enable (FSM_WR_ENA)
Figure 4-39. FSM Register Write Enable (FSM_WR_ENA) [offset = 288h]
31

16Reserved
R-0

15

3

2

0

Reserved

WR_ENA

R-0

R/WP-2h

LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-44. FSM Register Write Enable (FSM_WR_ENA) Field Descriptions
Bit

Field

31-16

Reserved

2-0

WR_ENA

Value

Description

0

Reads return 0. Writes have no effect.
FSM Write Enable5hThis register must contain 5h in order to write to any other register in the range FFF8 7200h
to FFF8 72FFh. This is the first register to be written when setting up the FSM.

All other values

For all other values, the FSM registers cannot be written.

4.7.33 FSM Sector Register (FSM_SECTOR)
This is a banked register. A separate register is implemented for each bank, but they all occupy the same
address. The correct bank must be selected in the FMAC register before reading or writing this register.
See Section 4.7.20.
Figure 4-40. FSM Sector Register (FSM_SECTOR) [offset = 2A4h]
31

16
SECT_ERASED[15:0]
R/WP-1

15

0
Reserved
R-0

LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-45. FSM Sector Register (FSM_SECTOR) Field Descriptions
Bit

Field

31-16

SECT_ERASED

Value

Description
Sectors Erased
There is one bit for each sector. Bit 16 corresponds to sector 0, bit 17 corresponds to sector 1, andso on.

15-0

Reserved0

During bank erase, each sector whose corresponding bit is 0 will be erased. After bank erase, thebit corresponding to each sector that is erased will be changed from 0 to 1.

1

During bank erase, each sector whose corresponding bit is 1 will not be erased.

0

These bits are used by the state machine during bank erase. Do not write to these bits.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

223

Control Registers

www.ti.com

4.7.34 EEPROM Emulation Configuration Register (EEPROM_CONFIG)
Figure 4-41. EEPROM Emulation Configuration Register (EEPROM_CONFIG) [offset = 2B8h]
31

20

15

19

16

Reserved

EWAIT

R-0

R/WP-1h98

70Reserved

AUTOSUSP_EN

AUTOSTART_GRACE

R-0

R/WP-0R/WP-2h

LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-46. EPROM Emulation Configuration Register (EEPROM_CONFIG) Field Descriptions
Bit

Field

Value

31-20

Reserved

0

19-16

EWAIT

0-Fh

Description
Reads return 0. Writes have no effect.
EEPROM Wait state Counter
Replaces the RWAIT count in the EEPROM register. The same formulas that apply to
RWAIT apply to EWAIT in the EEPROM bank.

15-9
8

Reserved

0

AUTOSUSP_EN

Reads return 0. Writes have no effect.
Auto suspend enable
The auto-suspend begins when the CPU or Bus2 attempts to access a bank with an active
and suspendable FSM operation. If this happens, the FSM automatically issues a suspendcommand and exits from the FSM. It then does the access. After the access, the FMC waits
for a time determined by the Autostart_grace field before issuing the FSM resumecommand.

7-0

224

0

Auto suspend is disabled.

1

Auto suspend is enabled.

AUTOSTART_GRACE

Auto-suspend Startup Grace Period1

The value in this register determines how many cycles the FMC waits after the last CPU or
Bus2 access before issuing the FSM resume command.

0

The FMC waits 16 HCLK periods for each count in the AUTOSTART_GRACE field. A valueof 2 waits for 32 periods after the last access. Each access resets the counter to the
AUTOSTART_GRACE value × 16.

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.35 EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1)
This register controls ECC event detection for the EEPROM Emulation Flash bank (bank 7). For theequivalent register that controls ECC event detection for the main Flash banks, see Section 4.7.2.
Figure 4-42. EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1)[offset = 308h]
3124
Reserved
R-5h

23

20

19

16

Reserved

EE_EDACMODE

R-0

R/WP-Ah

15

7

10

9

8

Reserved

EE_EOFEN

EE_EZFEN

EE_EPEN

R-0

R/WP-0R/WP-0R/WP-0

5

4

Reserved

6

EE_ALL1_OK

EE_ALL0_OK

3
EE_EDACEN

0

R-0

R/WP-0R/WP-0R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-47. EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1)
Field Descriptions
Bit

Field

31-20 Reserved

Value

Description

050h

Read returns 050h. Writes have no effect

19-16 EE_EDACMODE

Error Correction Mode for the EEPROM Emulation Flash bank (bank 7). For the main
Flash banks, see Section 4.7.2.
5hDetection only mode.
Note: In detection only mode single-bit errors will not be corrected, but will be treated as
uncorrectable errors. The single-bit error flags and profiling mode are disabled. Detection
only mode has the advantage that a triple bit error will be detected and not mistaken for asingle-bit error and mis-corrected.

All other values

Single-bit errors are corrected and multi-bit or address errors are detected
Note: It is recommended to leave the EE_EDACMODE field as Ah to guard against soft
errors from flipping EE_EDACMODE to a detection only.

15-11 Reserved
10

9

8

0

EE_EOFEN

Reads return 0. Writes have no effect.
EEPROM Emulation Event on a correctable One's Fail Enable bit

0

No ESM event will be generated on a single-bit error when a 1 reads as a 0 and iscorrected

1

An ESM group 1 channel 35 event will be generated on a single-bit error when a 1 reads
as a 0 and is corrected

EE_EZFENEEPROM Emulation Event on a correctable Zero's Fail Enable bit
0

No ESM event will be generated on a single-bit error when a 0 reads as a 1 and iscorrected

1

An ESM group 1 channel 35 event will be generated on a single-bit error when a 0 reads
as a 1 and is corrected

EE_EPEN

EEPROM Emulation Error Profiling Enable.
0Error profiling is disabled.

1

Error profiling is enabled.
An ESM group 1 channel 35 event will be generated when number of correctable bit
errors detected and corrected has reached the threshold value defined in the EE_CTRL2
register.

7-6

Reserved

0

Reads return 0. Writes have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

225

Control Registers

www.ti.com

Table 4-47. EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1)
Field Descriptions (continued)
Bit

Field

5

EE_ALL1_OK

Value

Description
EEPROM Emulation All One Condition Valid.

0

One condition valid is disabled.
Reading of an erased location (64 data bits and the corresponding 8 ECC bits are all 1s)
will generate ECC errors. The error counter for profiling will increment if all 1s aredetected.

1

One condition valid is enabled.
Reading of an erased location (64 data bits and the corresponding 8 ECC bits are all 1s)
will NOT generate ECC errors. The error counter for profiling will NOT increment if all 1s
are detected.

4

EE_ALL0_OK

EEPROM Emulation All Zero Condition Valid.
0

Zero condition valid is disabled.
Reading of all 0s (64 data bits and the corresponding 8 ECC bits are all 0s) will generate
ECC errors. The error counter for profiling will increment if all 0s are detected.

1

Zero condition valid is enabled.
Reading of all 0s (64 data bits and the corresponding 8 ECC bits are all 0s) will NOT
generate ECC errors. The error counter for profiling will NOT increment if all 0s aredetected.

3-0

EE_EDACEN

EEPROM Emulation Error Detection and Correction Enable
5h

Error Detection and Correction is disabled

All other values

Error Detection and Correction is enabled
Note: It is recommended to leave the EE_EDACEN field as Ah to guard against soft
errors from flipping the EE_EDACEN to a disabled state.

4.7.36 EEPROM Emulation Error Correction and Correction Control Register 2 (EE_CTRL2)
Figure 4-43. EEPROM Emulation Error Correction and Correction Control Register 2 (EE_CTRL2)[offset = 30Ch]
31

16
Reserved
R-0

150
EE_SEC_THRESHOLD
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-48. EEPROM Emulation Error Correction Control Register 2 (EE_CTRL2) Field Descriptions
Bit

Field

31-16 Reserved
15-0

EE_SEC_THRESHOLD

Value
0

Description
Reads return 0. Writes have no effect.

0-FFFFhEEPROM Emulation Single Error Correction Threshold
This register contains the threshold value for the SEC (single error correction)
occurrences before a single interrupt request is generated. A threshold of 0 disables
the threshold so that it never triggers the profile interrupt.

226

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.37 EEPROM Emulation Correctable Error Count Register (EE_COR_ERR_CNT)
Figure 4-44. EEPROM Emulation Error Corectable Error Count Register (EE_COR_ERR_CNT)[offset = 310h]
31

16
Reserved
R-0

150
EE_ERRCNT
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP=Write in Privilege Mode; -n = value after reset

Table 4-49. EEPROM Emulation Correctable Error Count Register (EE_COR_ERR_CNT)
Field Descriptions
Bit

Field

Value

31-16 Reserved
15-0

EE_ERRCNT

0
0-FFFFh

Description
Reads return 0. Writes have no effect.
Single Error Correction Count
This register contains the number of SEC (single error correction) occurrences. Writing
any value to this register resets the count value to 0. The counter resets to 0 when it
increments to be equal to the single error correction threshold. This register only
increments when profiling mode is enabled. This register is not affected by the
EE_ZERO_EN or EE_ONE_EN error control bits in the EE_CTRL1 register.

4.7.38 EEPROM Emulation Correctable Error Address Register (EE_COR_ERR_ADD)
During emulation mode, this address is frozen even when read. By setting the SUSP_IGNR bit to 1 in the
FEDACCTRL1 register, this register can be un-frozen in emulation mode.
This register is not changed with the reset signal and contains unknown data at power-up.
Figure 4-45. EEPROM Emulation Correctable Error Address Register (EE_COR_ERR_ADD)[offset = 314h]
3116
COR_ERR_ADD
R-u

15

3

2

0

COR_ERR_ADD

B_OFF

R-u

R-u

LEGEND: R = Read only; -n = value after reset; -u = unchanged value on internal reset, cleared on power up

Table 4-50. EEPROM Emulation Correctable Error Address Register (EE_COR_ERR_ADD)
Field Descriptions
Bit

Field

Description

31-3

COR_ERR_ADD

Correctable Error Address
COR_ERR_ADD records the CPU logical address of which a correctable error is detected by the
ECC logic. This error address is frozen from begin updated until it is read by the CPU. Additional
error are blocked until this register is read.

2-0

B_OFF

Byte offset
Since ECC is checked on 64 bit data, when checking main memory or OTP, the address captured
is aligned to a 64-bit boundary with address bits[2:0] equal to 0. When reading from the ECC bytes,
these bits will indicate the failing address of the ECC location associated with the failure. Whenreading an ECC byte, the ECC is checked against the 64 data bits they protect.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

227

Control Registers

www.ti.com

4.7.39 EEPROM Emulation Correctable Error Position Register (EE_COR_ERR_POS)
The bit position is captured during errors when either EE_EOFEN or EE_EZFEN enable bit is set. During
error profiling mode when only EE_EPEN is set, the bit position is not captured if a correctable error is
detected. This register is frozen while either the EE_ERR_ZERO_FLG or the EE_ERR_ONE_FLG bit isset in the EE_EDACSTATUS register.
During emulation mode, this address is frozen even when read. By setting the SUSP_IGNR bit to 1 in the
FEDACCTRL1 register, this register can be un-frozen in emulation mode.
This register is not changed with the reset signal and contains unknown data at power-up.
Figure 4-46. EEPROM Emulation Correctable Error Position Register (EE_COR_ERR_POS)[offset = 318h]
3116Reserved
R-0

15

8

7

0

Reserved

TYPE

EE_ERR_POS

R-0

R-u

R-u

LEGEND: R = Read only; -n = value after reset; -u = unchanged value on internal reset, cleared on power up

Table 4-51. EEPROM Emulation Correctable Error Position Register (EE_COR_ERR_POS)
Field Descriptions
Bit

Field

31-9

Reserved

8

7-0

228

Value
0

TYPE

EE_ERR_POS

Description
Reads return 0. Writes have no effect.
ErrorType0

The error was one of the 64 data bits

1

The error was one of the 8 check bits

0-FFh

The bit address of the single-bit error

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.40 EEPROM Emulation Error Status Register (EE_STATUS)
During emulation mode, this address is frozen even when read. By setting the SUSP_IGNR bit to 1 in the
FEDACCTRL1 register, this register can be un-frozen in emulation mode.
This register is not changed with the reset signal and contains unknown data at power-up.
All these error status bits can be deactivated by writing a 1 to the bit; writing a 0 has no effect.
Bits 0 to 3 show correctable errors while bits 4 to 12 show uncorrectable errors. When the uncorrectableerrors are triggered, the current address is stored in the EE_UNC_ERR_ADD register.
These error bits are not set while the FMC is in the suspend mode but they can be cleared in suspend by
writing 1s to the bits. By setting the SUSP_IGNR bit to 1 in the FEDACCTRL1 register, these error bits
can be set in suspend mode.
Figure 4-47. EEPROM Emulation Error Status Register (EE_STATUS) [offset = 31Ch]
31

16
Reserved
R-0
15

13

12

11

9

8

Reserved

EE_D_UNC_
ERR

Reserved

EE_UNC_
ERR

R-0

R/CP-uR-0

R/CP-u

7

6

5

4

3

2

1

0

Reserved

EE_CMG

Reserved

EE_CME

EE_D_COR_
ERR

EE_ERR_
ONE_FLG

EE_ERR_
ZERO_FLG

EE_ERR_PRF_FLG

R-0

R-0

R-0

R-0

R/CP-uR/CP-uR/CP-uR/CP-uLEGEND: R = Read only; R/CP=Read and Clear in Privilege Mode; -n = value after reset; -u = unchanged value on internal reset, clearedon power up

Table 4-52. EEPROM Emulation Error Status Register (EE_STATUS) Field Descriptions
Bit

Field

31-13

Reserved

12

11-9
8

0

EE_D_UNC_ERR

Reserved

Reserved

6

EE_CMG

5

Reserved

4

EE_CME

Description
Reads return 0. Writes have no effect.
Diagnostic Mode Uncorrectable Error Status Flag

0

No uncorrectable error was detected in diagnostic mode 1.

1

An uncorrectable error was detected in diagnostic mode 1. This means two or more bits inthe data or ECC field have been found in error, or one or more bits in the address havebeen found in error.

0

Reads return 0. Writes have no effect.

EE_UNC_ERR

7

3

Value

EEPROM Emulation Uncorrectable Error Flag
0

No uncorrectable errors were detected in bank 7.

1

An uncorrectable error was detected in bank 7.

0

Reads return 0. Writes have no effect.
EEPROM Emulation Compare Malfunction Good

0

Compare malfunction was detected on the Bus2 SECDED logic.

1Compare malfunction was not detected on the Bus2 SECDED logic.

0

Reads return 0. Writes have no effect.
EEPROM Emulation Compare Malfunction Error

0

Compare malfunction was not detected on the Bus2 SECDED logic.

1Compare malfunction was detected on the Bus2 SECDED logic.

EE_D_COR_ERR

Diagnostic Correctable Error Flag
0

No correctable error was detected.

1

A correctable error was detected.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

229

Control Registers

www.ti.com

Table 4-52. EEPROM Emulation Error Status Register (EE_STATUS) Field Descriptions (continued)
Bit

Field

2

EE_ERR_ONE_FLG

1

0

Value

Description
Error on One Fail Error Flag

0

No correctable error was detected.

1

A correctable error was detected.

EE_ERR_ZERO_FLG

Error on Zero Fail Error Flag
0

No correctable error was detected.

1

A correctable error was detected.

EE_ERR_PRF_FLG

Error Profiling Error Flag
0

No correctable error was detected.

1

A correctable error was detected.

4.7.41 EEPROM Emulation Uncorrectable Error Address Register (EE_UNC_ERR_ADD)
During emulation mode, this address is frozen even when read. By setting the SUSP_IGNR bit to 1 in the
FEDACCTRL1 register, this register can be un-frozen in emulation mode.
This register is not changed with the reset signal and contains unknown data at power-up.
Figure 4-48. EEPROM Emulation Uncorrectable Error Address Register (EE_UNC_ERR_ADD)[offset = 320h]
31

16
UNC_ERR_ADD
R-u

15

3

2

0

UNC_ERR_ADD

B_OFF

R-u

R-u

LEGEND: R = Read only; -n = value after reset; -u = unchanged value on internal reset, cleared on power up

Table 4-53. EEPROM Emulation Uncorrectable Error Address Register (EE_UNC_ERR_ADD)
Field Descriptions
Bit

Field

Description

31-3

UNC_ERR_ADD

Uncorrectable Error Address
UNC_ERR_ADD records the CPU logical address of which an un-correctable error is detected by
the ECC logic. This error address is frozen from begin updated until it is read by the CPU.
Additional error are blocked until this register is read.

2-0

B_OFF

Byte offset
Since ECC is checked on 64 bit data, when checking main memory or OTP, the address captured
is aligned to a 64-bit boundary with address bits[2:0] equal to 0. When reading from the ECC bytes,
these bits indicate the failing address of the ECC location associated with the failure. When reading
an ECC byte, the ECC is checked against the 64 data bits they protect.

230

F021 Flash Module Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

4.7.42 Flash Bank Configuration Register (FCFG_BANK)
Figure 4-49. Flash Bank Configuration Register (FCFG_BANK) [offset = 400h]
31

20

19

16

EE_BANK_WIDTH

Reserved

R-48h

R-1

15

4

3

0

MAIN_BANK_WIDTH

Reserved

R-90h

R-2h

LEGEND: R = Read only; -n = value after reset

Table 4-54. Flash Bank Configuration Register (FCFG_BANK) Field Descriptions
Bit

Field

31-20

EE_BANK_WIDTH

19-16

Reserved

15-4

MAIN_BANK_WIDTH

3-0

Reserved

Value

Description
Bank 7 width (72 bits wide)

48hThis read-only value indicates the maximum number of bits that can be programmed in thebank in one operation. The 72 bits includes 64 data bits and 8 ECC bits.

1

Writes have no effect.
Width of main Flash banks (144 bits wide)

90hThis read-only value indicates the maximum number of bits that can be programmed in thebank in one operation. The 144 bits includes 128 data bits and 16 ECC bits.

2h

Writes have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

F021 Flash Module Controller
Copyright © 2018, Texas Instruments Incorporated

231

Chapter 5
SPNU517C – March 2018

Tightly-Coupled RAM (TCRAM) ModuleThis chapter describes the tightly-coupled RAM (TCRAM) module.
Topic

5.1
5.2
5.3
5.4
5.5
5.6

232

...........................................................................................................................

Page

Overview ......................................................................................................... 233
RAM Memory Map ............................................................................................ 234
Safety Features ................................................................................................ 235
TCRAM Auto-Initialization .................................................................................. 236
Emulation / Debug Mode Behavior ...................................................................... 237
TCRAM Control and Status Registers ................................................................. 237

Tightly-Coupled RAM (TCRAM) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Overviewwww.ti.com

5.1

Overview
The Hercules family of microcontrollers are based on the ARM Cortex-R4 processor. This CPU has twotightly-coupled memory interfaces – ATCM and BTCM, which are used to interface to the program anddata memories, respectively. The Hercules MCUs use the ATCM interface for the main flash memory andthe BTCM interface for the CPU data RAM.

5.1.1 B0TCM and B1TCM Connection Diagram
The BTCM interface is further divided into two parts – B0TCM and B1TCM, which are both used tointerface to actual RAM banks as shown in Figure 5-1.
Figure 5-1. TCRAM Module Connections
VBUSP I/F PMT I/F

RTP I/F
36 Bit36 BitUpper 32 bits data
4 ECC bits

Cortex R4F
EVEN Address
TCM BUSB0
TCM

36 bit
RAM
Wide
RAM

TCRAMW 1
36 Bit64 Bit data bus
Lower 32 bits data
and 4 ECC bits

A
TCM

36 Bit36 bitRAM
WideRAM
36 BitB1
TCM

Upper 32 bits data
4 ECC bits

ODD Address
TCM BUS36 Bit36 bit
RAM
Wide
RAM

TCR AMW 2
36 Bit64 Bit data bus
Lower 32 bits data
and 4 ECC bits
VBUSP I/F PMT I/F

36 Bit36 bit
RAM
Wide
RAM

RTP I/F

5.1.2 Main Features
The main features of the tightly-coupled RAM interface module are:• Controls read/write accesses to the data RAM• Decodes addresses within the memory region allocated for the RAM• Supports read and write accesses in 64-bit, 32-bit, 16-bit or 8-bit access sizes– Does not support bit-wise operations• Safety Features:– Single-Error-Correction Double-Error-Detection (SECDED)• Uses the CPU's Event bus and maintains the SECDED status in memory-mapped registers• Captures the number of occurrences of single-bit or multi-bit errors as well as the RAM addressthat has the fault• Generates signals for indicating single-bit and multi-bit errors to the Error Signaling Module(ESM)– Parity Protection for BTCM Address Bus and Control Signals• Uses the CPU's TCM Address Parity Scheme and indicates an address bus parity error to the
ESM

SPNU517C – March 2018
Submit Documentation Feedback

Tightly-Coupled RAM (TCRAM) Module
Copyright © 2018, Texas Instruments Incorporated

233

RAM Memory Map•

5.2

www.ti.com– Redundant Address Decode Scheme• Checks the decoding of CPU address lines and generation of correct memory selects for theRAM banks
Supports auto-initialization of the CPU data RAM banks

RAM Memory Map
The ARM Cortex-R4 CPU allows up to 8MB to be accessed through the BTCM interface. The Hercules
family of microcontrollers support up to 256KB RAM on the BTCM interface. Check the specific part's
datasheet to identify the actual amount of TCRAM supported on the part. This RAM is protected by ECC
allowing the CPU to correct any single-bit errors and detect multi-bit errors within a 64-bit value. The error
correction codes (ECC) are stored in the RAM memory space as well. The memory map for the TCRAM
and the corresponding ECC space is shown in Figure 5-2. Any access to an unimplemented TCRAM
location results in an error response from the TCRAM module.
Figure 5-2. RAM Memory Map
8 MB

Illegal address

4MB + 256KB

Implemented ECC space
4MB
Illegal address
256KB

Implemented data space
0x0

Each RAM data word is 64-bits wide. These 64 bits are divided into two 32 bits per RAM bank as shownin Figure 5-1. The 8 bits of ECC are also divided into 4 bits per RAM bank.
For every 64-bit read from the RAM, an 8-bit ECC is also read by the CPU on its ECC bus. Similarly, forevery 64-bit write to the RAM, the CPU also writes an 8-bit ECC using the same ECC bus.
NOTE: Read-Modify-Write Requirement for Writes to RAM: The TCRAM interface module
supports 64-bit, 32-bit, 16-bit, or 8-bit writes to the RAM. However, the ECC is calculated by
the CPU for 64-bit values only. For any write access smaller than 64 bits, it is necessary toforce the CPU to perform a 64-bit read-modify-write operation in order to ensure that thecorrect ECC is also written. This can be done by setting the bit 1: BTCMRMW of c15, theSecondary Auxiliary Control Register of the CPU.

The ECC memory can also be directly accessed via memory-mapped offset addresses starting from 4MB,
as shown in Figure 5-2. A read from the ECC space results in the 8-bit ECC value appearing on each byteof the 64-bit CPU data. The ECC memory can only be written to as a 64-bit access. The write to the ECC
space must also first be enabled via the RAM Control Register (RAMCTRL).
Accesses to the ECC space are not traced out to the RAM Trace Port (RTP).
234

Tightly-Coupled RAM (TCRAM) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Safety Features

www.ti.com

NOTE: No ECC Error Generated for Accesses to ECC Memory: A read from the ECC space
sends the ECC value on both the 64-bit TCM read data bus as well as the 8-bit ECC bus.
This could result in the detection of a multi-bit error by the SECDED logic inside the CPU.
The TCRAM interface module ignores the ECC error indicated by the CPU for the access to
the ECC space.

5.3

Safety Features
The TCRAM interface module incorporates some features that are designed specifically with safety
considerations. These are described in the following sections.

5.3.1 Support for Cortex-R4 CPU's Single-Error-Correction Double-Error-Detection (SECDED)The TCRAM interface module monitors the CPU's event bus. The CPU's event bus signals single-bit or
multi-bit errors for B0TCM as well as B1TCM separately. These signals are monitored by the TCRAM
modules for each of these interfaces.
TCRAM Interface Module Features dedicated for SECDED Support:• Dedicated single-bit error counter– This counter is stored in a memory-mapped register called RAMOCCUR)– RAMOCCUR is used to count the single-bit errors corrected by the CPU's SECDED logic– The TCRAM interface module allows the application to generate an interrupt via the RAMINTCTRL
register when the number of single-bit errors corrected by the CPU exceeds a programmablethreshold, RAMTHRESHOLD• RAM Error Status Register– The errors detected by the TCRAM interface module as well as those indicated by the CPU areflagged in the RAMERRSTATUS register– There are separate bits to indicate single-bit error, double-bit error, address decode failure, addresscompare logic failure, read-address parity failure, and write-address parity failure• ECC Error Address Capture– Seperate registers to hold the address on which a single-bit error is detected (RAMSERRADDR) or
a double-bit error is detected (RAMUERRADDR)– The RAMSERRADDR register is only updated when the RAMTHRESHOLD value is set to 1
– Both the RAMSERRADDR and RAMUERRADDR capture the 64-bit address for the access to the
TCRAM as an offset from the base address of the TCRAM (0x08000000 by default)
NOTE: Cortex-R4 CPU Event Bus Signaling Not Enabled By Default: Upon power-up and after a
CPU reset, the event signaling mechanism inside the Cortex-R4 CPU is disabled. Thisfeature must be enabled by setting the Export (X-bit) of the Performance Monitoring andControl Register (PMNC) in the CPU. The TCRAM interface module can only capture thesingle-bit or double-bit ECC error occurrences once the CPU's event signaling mechanism isenabled.

SPNU517C – March 2018
Submit Documentation Feedback

Tightly-Coupled RAM (TCRAM) Module
Copyright © 2018, Texas Instruments Incorporated

235

Safety Features

www.ti.com

5.3.2 Support for Cortex-R4 CPU's Address and Control Bus Parity Checking
The Cortex-R4 CPU calculates a single parity-bit for the TCRAM address and control signals. The TCRAM
interface module also computes this parity bit based on the CPU's address bus and control signals. The
computed parity bit is compared against the parity bit received from the CPU. A mismatch is signaled as
an Address Parity Failure to the Error Signaling Module (ESM). There is a separate address parity failure
error channel for B0TCM and B1TCM.
The 64-bit TCRAM address that fails the parity check is captured in the RAMPERRADDR register as anoffset from the base address of the TCRAM (0x08000000 by default). The TCRAM interface module also
indicates the type of access, read or write, that failed the parity check. This is indicated by the
RADDR_PAR_FAIL or the WADDR_PAR_FAIL status flags in the RAMERRSTATUS register.
The RAMERRSTATUS and RAMPERRADDR registers must be cleared by the application in order for the
TCRAM interface module to continue capturing subsequent errors and error addresses.
The parity scheme used for the described parity checking mechanism is defined by the global systemparity selection. This can be configured using the DEVPARSEL field of the DEVCR1 control register in thesystem module. This device-wide parity scheme can be overridden inside the TCRAM interface module byconfiguring the Address Parity Override field in the RAMCTRL register.
NOTE: No Change Of Parity Scheme On-The-Fly: The TCRAM interface module does not support
on-the-fly change to the parity scheme being used for checking the CPU address bus andcontrol bus. The application must ensure that the parity polarity (odd or even) is not changed
while there is an ongoing access to the TCRAM.

5.3.3 Redundant Address Decode
The TCRAM interface module generates the memory selects for each of the TCRAM banks as well as the
ECC memory based on the CPU address. The logic to generate these memory selects is duplicated andthe outputs compared to detect any address decode errors. A mismatch is indicated as an Address Error
to the Error Signaling Module (ESM), one signal for B0TCM and one for B1TCM. The TCRAM or ECC
address that caused the fault is captured in the RAMUERRADDR register. This 64-bit address is stored as
an offset from the base of the TCRAM or ECC memory.
As described earlier, each individual physical RAM bank is 36 bits wide. Each RAM bank contributes 32
bits of data and 4 bits of ECC when the bus master performs a 64-bit read from the TCRAM. Each
TCRAM bank receives a memory select and the address from the TCRAM interface module. Any
difference between the address and the memory selects results in wrong data and ECC pair being sent to
the CPU. The CPU's SECDED block will detect this data error.
The TCRAM interface module also supports a mechanism to test the operation of the redundant address
decode logic and the compare logic. This testing is supported by providing a test stimulus, and can betriggered by the application by configuring the RAMTEST register. The address of any error identified
during testing of the redundant address decode and compare logic is not captured in the
RAMUERRADDR register.
NOTE: Address decode checking when in compare logic test mode: When the address decodeand compare logic test mode is enabled, the redundant address decode and compare logic
is not available for checking the proper generation of the memory selects for the TCRAM and
ECC memory.

5.4

TCRAM Auto-Initialization
The RAM memory can be initialized by using the dedicated auto-initialization hardware. The TCRAM
Module initializes the entire memory when the auto-init is enabled for the RAM. All RAM data memory is
initialized to zeros and the ECC memory is initialized to the correct ECC value for zeros, that is, 0Ch.

236

Tightly-Coupled RAM (TCRAM) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Emulation / Debug Mode Behavior

www.ti.com

5.5

Emulation / Debug Mode Behavior
The following describes the behavior of the TCRAM Module when in debug mode:• The RAMOCCUR register continues to count the single-bit error corrections performed by the CortexR4 CPU's SECDED logic.
• No single-bit error interrupt is generated nor is any single-bit error address captured even when the
RAMOCCUR counter reaches the programmed single-bit error correction threshold.
• No uncorrectable error interrupt is generated nor is any double-bit error address captured.
• No address parity error interrupt is generated nor is any parity error address captured.
• The RAMUERRADDR register is not cleared by a read in debug mode.
– That is, if a double-bit error address is captured and is not read by the CPU before entering debug
mode, then it remains frozen during debug mode even if it is read.
• The RAMPERRADDR register is not cleared by a read in debug mode.

5.6

TCRAM Control and Status Registers
The TCRAM Module registers listed in Table 5-1 are accessed through the system module register spacein the Cortex-R4 CPU's memory map. All registers are 32-bit wide and are located on a 32-bit boundary.
Reads and writes to registers are supported in 8-, 16-, and 32-bit accesses. The base address for thecontrol registers is FFFF F800h for even RAM ECC and FFFF F900h for odd RAM ECC.
Table 5-1. TCRAM Module Control and Status Registers
OffsetAcronym

Register Description

00h

RAMCTRLTCRAM Module Control Register

Section 5.6.1

04h

RAMTHRESHOLD

TCRAM Module Single-Bit Error Correction Threshold Register

Section 5.6.2

08h

RAMOCCUR

TCRAM Module Single-Bit Error Occurrences Control Register

Section 5.6.3

0Ch

RAMINTCTRL

TCRAM Module Interrupt Control Register

Section 5.6.4

10h

RAMERRSTATUS

TCRAM Module Error Status Register

Section 5.6.5

14h

RAMSERRADDR

TCRAM Module Single-Bit Error Address Register

Section 5.6.6

1Ch

RAMUERRADDR

TCRAM Module Uncorrectable Error Address Register

Section 5.6.7

30h

RAMTEST

TCRAM Module Test Mode Control Register

Section 5.6.8

38h

RAMADDRDECVECTTCRAM Module Test Mode Vector Register

Section 5.6.9

3Ch

RAMPERADDR

TCRAM Module Parity Error Address Register

Section 5.6.10

SPNU517C – March 2018
Submit Documentation Feedback

SectionTightly-Coupled RAM (TCRAM) Module
Copyright © 2018, Texas Instruments Incorporated

237

TCRAM Control and Status Registers

www.ti.com

5.6.1 TCRAM Module Control Register (RAMCTRL)The RAMCTRL register, shown in Figure 5-3 and described in Table 5-2, controls the safety features
supported by the TCRAM Module.
Figure 5-3. TCRAM Module Control Register (RAMCTRL) (offset = 00h)
31

30

Reserved

EMU_TRACE_
DIS

29
Reserved

28

ADDR_PARITY_OVERRIDE

R-0

R/WP-0R-0

R/WP-0

23

20

27

24

19

16

Reserved

ADDR_PARITY_DISABLE

R-0

R/WP-5h

15

9

7

8

Reserved

ECC_WR_EN

R-0

R/WP-04

3

0Reserved

ECC_DETECT_EN

R-0

R/WP-AhLEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 5-2. TCRAM Module Control Register (RAMCTRL) Field Descriptions
Bit

Field

31

Reserved

30

EMU_TRACE_DIS

29-28 Reserved

Value
0

Reads return 0. Writes have no effect.
Emulation Mode Trace Disable. This bit, when set, disables the tracing of read data to
RAM Trace Port (RTP) module during emulation mode access.

0

Data is allowed to be traced out to the trace modules during emulation mode accesses.

1

Data is blocked from being traced out to the trace modules during emulation mode
accesses.

0

Reads return 0. Writes have no effect.

27-24 ADDR_PARITY_OVERRIDE

23-20 Reserved

Description

Address Parity Override. This field, when set to Dh, will invert the parity scheme
selected by the device global parity selection. The address parity checker would thenwork on the inverted parity scheme. By default, the parity scheme is the same as theglobal device parity scheme.
Dh

Parity scheme is opposite to the device global parity scheme.

All othervaluesParity scheme is the same as the device global parity scheme.

0

Reads return 0. Writes have no effect.

19-16 ADDR_PARITY_DISABLE

Address Parity Detect Disable. This field, when set to Ah, disables the parity checking
for the address bus. The parity checking is enabled when this field is set to any othervalue.
Note: The application must ensure that the WADDR_PAR_FAIL and
RADDR_PAR_FAIL bits in RAMERRSTATUS register are cleared before enabling
address parity checking.

15-9
8

Reserved

Ah

Address parity checking is disabled.

All othervaluesAddress parity checking is enabled.

0

Reads return 0. Writes have no effect.

ECC_WR_EN

ECC Memory Write Enable. This bit is provided to prevent accidental writes to the ECC
memory. A write access to the ECC memory is allowed only when the ECC_WR_EN
bit is set to 1. If this bit is cleared, then any writes to ECC memory are ignored.
Note: Reads are allowed from the ECC memory regardless of the state of the
ECC_WR_EN bit.

2380

ECC memory writes are disabled.

1

ECC memory writes are enabled.

Tightly-Coupled RAM (TCRAM) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

TCRAM Control and Status Registers

www.ti.com

Table 5-2. TCRAM Module Control Register (RAMCTRL) Field Descriptions (continued)
Bit

Field

7-4

Reserved

3-0

ECC_DETECT_EN

Value
0

Description
Reads return 0. Writes have no effect.
ECC Detect Enable. This is a 4-bit key to enable the ECC detection feature in the
TCRAM Module. If this field is set to any value other than 5h, then the TCRAM Module
starts monitoring the TCM event bus and generates the corresponding error status
flags. The error status updates are done only when the ECC_DETECT_EN field is not
5h. The ECC detection is enabled by default as the ECC_DETECT_EN default value isAh.

5h

ECC detection is disabled.

All othervalues

ECC detection is enabled.

5.6.2 TCRAM Module Single-Bit Error Correction Threshold Register (RAMTHRESHOLD)The RAMTHRESHOLD register, shown in Figure 5-4 and described in Table 5-3, allows the application toconfigure the number of single-bit error corrections by the SECDED logic inside the Cortex-R4 CPU
before generating a single-bit error interrupt.
Figure 5-4. TCRAM Module Single-Bit Error Correction Threshold Register (RAMTHRESHOLD)(offset = 04h)
31

16
Reserved
R-0

150
THRESHOLD
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 5-3. TCRAM Module Single-Bit Error Correction Threshold Register (RAMTHRESHOLD)
Field Descriptions
Bit

Field

31-16

Reserved

15-0

THRESHOLD

Value
0
0-FFFFh

Description
Reads return 0. Writes have no effect.
Single-bit Error Threshold Count. This field contains the threshold value for the Single-bit Error
Correction (SEC) occurrences before the single-bit error interrupt is generated. If this thresholdis set to 1 then all single-bit error addresses are captured. To enable the error occurrence
detection, the threshold must be set to a non-zero value.

SPNU517C – March 2018
Submit Documentation Feedback

Tightly-Coupled RAM (TCRAM) Module
Copyright © 2018, Texas Instruments Incorporated

239

TCRAM Control and Status Registers

www.ti.com

5.6.3 TCRAM Module Single-Bit Error Occurrences Counter Register (RAMOCCUR)
The RAMOCCUR register, shown in Figure 5-5 and described in Table 5-4, indicates the number ofsingle-bit error corrections performed by the SEC logic inside the Cortex-R4 CPU.
Figure 5-5. TCRAM Module Single-Bit Error Occurrences Counter Register (RAMOCCUR)(offset = 08h)
31

16
Reserved
R-0

150
SINGLE_ERROR_OCCURRENCES
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 5-4. TCRAM Module Single-Bit Error Occurrences Counter Register (RAMOCCUR)
Field Descriptions
Bit

Field

Value

31-16 Reserved
15-00

SINGLE_ERROR_OCC
URRENCES

0-FFFFh

Description
Reads return 0. Writes have no effect.
Single-bit Error Correction Occurrences. This 16-bit counter contains the number ofsingle-bit error occurrences. RAMOCCUR is reset to zero when it becomes equal to the
THRESHOLD value set in the RAMTHRESHOLD register. The application must clear the
RAMOCCUR register by writing 0 before setting the THRESHOLD value. If the
RAMOCCUR value is already higher than the programmed THRESHOLD value then the
counter increments and wraps around (overflow) to zero.
Note: If the application tries to clear the RAMOCCUR register at the same time as
the TCRAM Module tried to update it, then the TCRAM Module takes priority.
Note: When the RAMTHRESHOLD register is set to 1, then the RAMOCCUR registermust be cleared whenever a single-bit error correction occurs in order to countsubsequent single-bit error corrections.

5.6.4 TCRAM Module Interrupt Control Register (RAMINTCTRL)The RAMINTCTRL register, shown in Figure 5-6 and described in Table 5-5, enables the generation of aninterrupt to the CPU whenever the number of single-bit error corrections (RAMOCCUR) reaches the
programmed threshold (RAMTHRESHOLD).
Figure 5-6. TCRAM Module Interrupt Control Register (RAMINTCTRL) (offset = 0Ch)
31

16
Reserved
R-0

15

1

0

Reserved

SERR_EN

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 5-5. TCRAM Module Interrupt Control Register (RAMINTCTRL) Field Descriptions
Bit

Field

31-1

Reserved

0

SERR_EN

240

Value
0

Description
Reads return 0. Writes have no effect.
Single-bit Error Correction Interrupt Enable. This bit, when set to 1, enables the generation of thesingle-bit error interrupt when the RAMOCCUR count reaches the programmed RAMTHRESHOLD.
If the interrupt is not enabled, the single-bit error counter continues to count by resetting back tozero without generating any error interrupt. The SERR status flag in the RAMERRSTATUS register
gets set regardless of whether the SERR interrupt is enabled or not.

0

Single-bit error generation is disabled.

1

Single-bit error generation is enabled.

Tightly-Coupled RAM (TCRAM) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

TCRAM Control and Status Registers

www.ti.com

5.6.5 TCRAM Module Error Status Register (RAMERRSTATUS)
The RAMERRSTATUS register, shown in Figure 5-7 and described in Table 5-6, indicates the status of
the various error conditions monitored by the TCRAM Module.
Figure 5-7. TCRAM Module Error Status Register (RAMERRSTATUS) (offset = 10h)31

16
Reserved
R-0
15

10

7

6

9

8

Reserved

WADDR_PAR_FAIL

RADDR_PAR_
FAIL

R-0

R/W1CP-0

R/W1CP-0

5

4

3

2

1

0

Reserved

DERR

ADDR_COMP_LOGIC_FAIL

Reserved

ADDR_DEC_
FAIL

Reserved

SERR

R-0

R/W1CP-0

R/W1CP-0

R-0

R/W1CP-0

R-0

R/W1CP-0

LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -n = value after reset

Table 5-6. TCRAM Module Error Status Register (RAMERRSTATUS) Field Descriptions
Bit

Field

31-10 Reserved

Value Description
0

Reads return 0. Writes have no effect.

9

WADDR_PAR_FAIL

0-1

This bit indicates a Write Address Parity Failure. This bit must be cleared by writing 1 to it
in order to enable the capture of parity error address for subsequent failures. This bit must
be in a cleared state for generation of any new parity error interrupt.

8

RADDR_PAR_FAIL

0-1

This bit indicates a Read Address Parity Failure. This bit must be cleared by writing 1 to it
in order to enable the capture of parity error address for subsequent failures. This bit must
be in a cleared state for generation of any new parity error interrupt.

7-6

Reserved

0

Reads return 0. Writes have no effect.

5

DERR

0-1

This bit indicates a multi-bit error detected by the Cortex-R4 SECDED logic.

4

ADDR_COMP_LOGIC_FAIL

0-1

Address decode logic element failed. This bit indicates that the redundant address decode
logic test scheme has detected that a compare element has malfunctioned during thetesting of the logic. This bit has to be cleared by writing 1 to it in order to enable thecapture of uncorrectable error address for subsequent failures. This bit has to be in acleared state for generation of a new uncorrectable error interrupt. This bit only gets set in
the test mode, and has no relevance in functional mode.

3

Reserved

0

Reads return 0. Writes have no effect.

2

ADDR_DEC_FAIL

0-1

Address decode failed. This bit indicates that an address error interrupt was generated by
the redundant address decode and compare logic due to a functional failure. This bit must
be cleared by writing 1 to it in order to enable the capture of uncorrectable error addressfor subsequent failures. This bit has to be in a cleared state for generation of a new
address error interrupt.

1

Reserved

0

Reads return 0. Writes have no effect.

0

SERR

0-1

Single Error Status. This bit indicates that the single-bit error threshold has been reached.
This bit is set even if the single-bit error threshold interrupt is disabled. This bit must be
cleared by writing 1 to it in order to clear the interrupt request and to enable subsequent
single-bit error interrupt generation.

SPNU517C – March 2018
Submit Documentation Feedback

Tightly-Coupled RAM (TCRAM) Module
Copyright © 2018, Texas Instruments Incorporated

241

TCRAM Control and Status Registers

www.ti.com

5.6.6 TCRAM Module Single-Bit Error Address Register (RAMSERRADDR)The RAMSERRADDR register, shown in Figure 5-8 and described in Table 5-7, captures the address forwhich the Cortex-R4 CPU detected a single-bit error.
NOTE: The SERR bit in the RAMERRSTATUS register must be cleared, by writing 1 to the bit, inorder to enable the RAMSERRADDR register to capture a subsequent new error address.

Figure 5-8. TCRAM Module Single-Bit Error Address Register (RAMSERRADDR) (offset = 14h)
31

18

17

16

Reserved

SINGLE_ERROR _ADDRESS

R-0

R-0

15

3

2

0

SINGLE_ERROR_ADDRESS

Reserved

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 5-7. TCRAM Module Single-Bit Error Address Register (RAMSERRADDR)
Field Descriptions
Bit

Field

Value

31-18 Reserved
17-3

SINGLE_ERROR_ADDRESS

0
0-7FFFh

Description
Reads return 0. Writes have no effect.
This register captures the bits 17-3 of the address for which the Cortex-R4 CPU
detects a single-bit error when the RAMTHRESHOLD register is set to 1. The lower
3 bits are always tied to zero so that the address captured is a double-word (64-bit)
address. This is a 64-bit address is stored as an offset from the base of the TCRAM
or ECC memory.
This register can only be reset by asserting power-on reset, and holds the last error
address even after a system reset.

2-0

242

Reserved

0

Reads return 0. Writes have no effect.

Tightly-Coupled RAM (TCRAM) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

TCRAM Control and Status Registers

www.ti.com

5.6.7 TCRAM Module Uncorrectable Error Address Register (RAMUERRADDR)The RAMUERRADDR register, shown in Figure 5-9 and described in Table 5-8, captures the address forwhich the Cortex-R4 CPU detected a multi-bit error.
Figure 5-9. TCRAM Module Uncorrectable Error Address Register (RAMUERRADDR) (offset = 1Ch)
31

23

22

16

Reserved

UNCORRECTABLE_ERROR_ADDRESS

R-0

R-0

15

3

2

0

UNCORRECTABLE_ERROR_ADDRESS

Reserved

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 5-8. TCRAM Module Uncorrectable Error Address Register (RAMUERRADDR)
Field Descriptions
Bit

Field

31-23 Reserved
22-3

UNCORRECTABLE_ERROR_ADDRESS

Value
0

Description
Reads return 0. Writes have no effect.

0-FFFFFh This register captures the address for which there was an uncorrectable error. The
uncorrectable error is indicated by the Cortex-R4 CPU's SECDED logic and theaddress error is indicated by the TCRAM Module's redundant address decode andcompare logic.
For the SECDED multi-bit or double-bit uncorrectable error, this register stores bits
17-3 of the TCM access address. The lower 3 bits 2-0 are always read as zeros toindicate that the latched address is a double-word address. The address bits 31-18
are read as zeros. This is a 64-bit address stored as an offset from the base of the
TCRAM or ECC memory.
For a redundant address decode and compare logic error, this register stores thecomplete TCM access address rounded to a double-word boundary (bits 22-3). Thiserror is also indicated by the ADDR_DEC_FAIL status flag in the RAMERRSTATUS
register.
The register has to be read-cleared to enable further error address captures.
Reading the register does not clear its contents but enables the register to be
updated with an uncorrectable error address.
This register can only be reset by asserting power-on reset, and holds the last error
address even after a system reset.

2-0

Reserved

0

Reads return 0. Writes have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

Tightly-Coupled RAM (TCRAM) Module
Copyright © 2018, Texas Instruments Incorporated

243

TCRAM Control and Status Registers

www.ti.com

5.6.8 TCRAM Module Test Mode Control Register (RAMTEST)The RAMTEST register, shown in Figure 5-10 and described in Table 5-9, controls the test mode of the
TCRAM Module.
Figure 5-10. TCRAM Module Test Mode Control Register (RAMTEST) (offset = 30h)
31

16
Reserved
R-0

15

9

8

7

6

5

4

3

0

Reserved

TRIGGERTEST_MODE

Reserved

TEST_ENABLE

R-0

R/WP-0R/WP-0R-0

R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 5-9. TCRAM Module Test Mode Control Register (RAMTEST) Field Descriptions
Bit

Field

Value

Description

31-9

Reserved

0

Reads return 0. Writes have no effect.

8

TRIGGER

0-1

Test Trigger. This is an auto reset test trigger used to test the redundant address decodeand compare logic. A redundant address decode test is executed when test mode isenabled and the test trigger is applied by writing a 1 to this bit. The trigger is valid only if
test is enabled and the correct mode is configured in the TEST_MODE field, and the
ADDR_DEC_FAIL, ADDR_COMP_LOGIC_FAIL, and DERR flags are cleared in the
RAMERRSTATUS register and the RAMUERRADDR register is read-cleared.

7-6

TEST_MODE

0-3h

Test Mode. This field selects either equality of inequality testing schemes.
If TEST MODE is set to 2h, equality check is done. The test stimulus stored in
ADDRTEST_VECT register is fed directly to both the channels of the comparator. If the
XOR of these two inputs is not zero, then UERR interrupt is generated and
ADDR_COMP_LOGIC_FAIL flag is set in RAMERRSTATUS register.
If TEST MODE is set to 1h, inequality check is done. The test stimulus stored in
ADDRTEST_VECT register is inverted and fed into one channel and the non-inverted
vector is fed into the other channel. If the XOR of these inputs is zero, then the UERR
interrupt is generated and ADDR_COMP_LOGIC_FAIL flag is set in RAMERRSTATUS
register.

5-4

Reserved

3-0

TEST_ENABLE

244

0

Reads return 0. Writes have no effect.
Test Enable. This is a 4-bit key to enable the redundant address decode and compare
logic test scheme. If the test scheme is enabled then the compare logic uses the test
vector inputs from the ADDRTEST_VECT register. The functional path comparison isdisabled when test mode is enabled.

Ah

Test mode is enabled.

All othervaluesTest mode is disabled.

Tightly-Coupled RAM (TCRAM) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

TCRAM Control and Status Registers

www.ti.com

5.6.9 TCRAM Module Test Mode Vector Register (RAMADDRDECVECT)The RAMADDRDECVECT register, shown in Figure 5-11 and described in Table 5-10, is used for testing
the redundant address decode and compare logic of the TCRAM Module.
Figure 5-11. TCRAM Module Test Mode Vector Register (RAMADDRDECVECT) (offset = 38h)
31

27

26

25

16

Reserved

ECC_SELECT

Reserved

R-0

R/WP-0R-0

150
RAM_CHIP_SELECT
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 5-10. TCRAM Module Test Mode Vector Register (RAMADDRDEVECT)
Field Descriptions
Bit

Field

Value

31-27 Reserved
26

ECC_SELECT

Reads return 0. Writes have no effect.

0-1

ECC Select. This bit is used to store the ECC select value for the redundant address
decode and compare logic. The stored value is passed as test stimulus for the built-in test
scheme.

0

Reads return 0. Writes have no effect.

25-16 Reserved
15-0

RAM_CHIP_SELECT

Description

0

0-FFFFh

RAM Chip Select. This field is used to store the RAM chip select value for the redundant
address decode and compare logic. The stored value is passed as test stimulus for thebuilt-in test scheme.

5.6.10 TCRAM Module Parity Error Address Register (RAMPERRADDR)The RAMPERRADDR register, shown in Figure 5-12 and described in Table 5-11, stores the address forwhich an address-parity error was detected.
Figure 5-12. TCRAM Module Parity Error Address Register (RAMPERRADDR) (offset = 3Ch)
31

23

22

16

Reserved

ADDRESS_PARITY_ERROR_ADDRESS

R-0

R-u

15

3

2

0

ADDRESS_PARITY_ERROR_ADDRESS

Reserved

R-u

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -u = unchanged value on internal reset, cleared on power up

Table 5-11. TCRAM Module Parity Error Address Register (RAMPERRADDR)
Field Descriptions
Bit

Field

31-23 Reserved
22-3

ADDRESS_PARITY_ER
ROR_ADDRESS

2-0

Reserved

Value
0
0-FFFFFh0

Description
Reads return 0. Writes have no effect.
Parity Error Address. This register stores the double-word boundary (bits 22-3) of the
TCM access address for which there was an address parity error. This register must be
read-cleared to enable further error address captures. Reading the register does not clear
the register contents but enables the register to be updated with a new parity error
address. This is a 64-bit address is stored as an offset from the base of the TCRAM or
ECC memory.
Reads return 0. Writes have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

Tightly-Coupled RAM (TCRAM) Module
Copyright © 2018, Texas Instruments Incorporated

245

Chapter 6
SPNU517C – March 2018

Programmable Built-In Self-Test (PBIST) ModuleThis chapter describes the programmable built-in self-test (PBIST) controller module used for testing theon-chip memories.
Topic

6.1
6.2
6.3
6.4
6.5
6.6

246

...........................................................................................................................

Page

Overview ........................................................................................................ 247
RAM Grouping and Algorithm ........................................................................... 248
PBIST Flow ..................................................................................................... 249
Memory Test Algorithms on the On-chip ROM .................................................... 251
PBIST Control Registers ................................................................................... 253
PBIST Configuration Examples .......................................................................... 265

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackOverviewwww.ti.com

6.1

Overview
The PBIST (Programmable Built-In Self-Test) controller architecture provides a run-time-programmablememory BIST engine for varying levels of coverage across many embedded memory instances.

6.1.1 Features of PBIST
•
•
•
•
•
•

Information regarding on-chip memories, memory groupings, memory background patterns and test
algorithms stored in dedicated on-chip PBIST ROM
Host processor interface to configure and start BIST of memories
Supports testing of PBIST ROM itself as well
Supports testing of each memory at its maximum access speed in application
Implements intelligent clock gating to conserve power
Execution of microcode from PBIST ROM supported for ROM clock speeds up to 112 MHz. Reference
the device specific datasheet for maximum PBIST execution frequency.

6.1.2 PBIST versus Application Software-Based Testing
The PBIST architecture consists of a small coprocessor with a dedicated instruction set targeted
specifically toward testing memories. This coprocessor executes test routines stored in the PBIST ROM
and runs them on multiple on-chip memory instances. The on-chip memory configuration information is
also stored in the PBIST ROM.
The PBIST Controller architecture offers significant advantages over tests running on the main Cortex-R4
processor (application software-based testing):• Embedded CPUs have a long access path to memories outside the tightly-couple memory sub-system,
while the PBIST controller has a dedicated path to the memories specifically for the self-test.
• Embedded CPUs are designed for their targeted use and are often not easily programmed for memory
test algorithms.
• The memory test algorithm code on embedded CPUs is typically significantly larger than that needed
for PBIST.
• The embedded CPU is significantly larger than the PBIST controller.

6.1.3 PBIST Block Diagram
Figure 6-1 illustrates the basic PBIST blocks and its wrapper logic for the device.
Figure 6-1. PBIST Block Diagram
Host CPU
Control Interface

PBIST
ROM

MemoryConfigurations,
Algorithms,
Backgrouns

PBIST
Controller
MemoryData
PathSystemandPeripheral
Memories

Data Logger

SPNU517C – March 2018
Submit Documentation Feedback

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

247

RAM Grouping and Algorithm

6.1.3.1

www.ti.com

On-chip ROM

The on-chip ROM contains the information regarding the algorithms and memories to be tested.
6.1.3.2

Host Processor Interface to the PBIST Controller Registers

The Cortex-R4 CPU can select the algorithm and RAM groups for the memories' self-test from the on-chip
ROM based on the application requirements. Once the self-test has executed, the CPU can query the
PBIST controller registers to identify any memories that failed the self-test and to then take appropriate
next steps as required by the application's author.
6.1.3.3

Memory Data Path

This is the read and write data path logic between different system and peripheral memories tightly
coupled to the PBIST memory interface. The PBIST controller executes each selected algorithm on eachvalid memory group sequentially until all the algorithms are executed.
NOTE: Not all algorithms are designed to run on all RAM groups. If an algorithm is selected to run
on an incompatible memory, this will result in a failure. Refer to Table 2-5 and Table 2-6 for
RAM grouping and algorithm information.

6.2

RAM Grouping and Algorithm
Table 2-5 gives the list of RAM groups and their types supported on the device. Table 2-6 maps thedifferent algorithms supported in application mode for the RAM groups with the background patterns used
for the particular algorithm.
NOTE: March13 is the most recommended algorithm for the memory self-test.

248

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

PBIST Flow

www.ti.com

6.3

PBIST Flow
Figure 6-1 illustrates the memory self-test flow.
Figure 6-2. PBIST Memory Self-Test Flow Diagram

Yes

Is system inreset = 1?
No

Setup memories, peripheral and clock tree like
HCLK, VCLK peripheral and ROMCLK as required
for the PBIST test.

Enable PBIST controller by
by writing MSIENA = 0x01

Reset the PBIST controller by
writing MSTGCR = 0x0A

Wait for approximately N
vbus clocks.

Enable pbist clocks and ROM
clock by writing PACT = 0x03

Select the RAM group andalgorithm using RINFO andALGO registers

Program OVER = 0 for self test without Overrideor OVER = 1 for RINFO Override

Write ROM = 0x03 to enable themicrocode load of the algorithm
and RAM info groups from theon Chip ROM

Write 0x14 to DLR register toconfigure PBIST in ROM modeand start the Test

Resume PBIST self test by writing
0x02 to the STR registerNo
Is (MSTDONE = 1) ?

Read FSRD and FSRA datalog
reg. for Fail data and address values

Yes

Is FSRF0 = 1 ?

Yes

Read RAMT reg for
RGS/RDS info

No
Disable pbist clocks and ROM
clock by writing PACT = 0

Disable PBIST Testby writing MSTGCR = 0x05

PBIST Selftest DoneSPNU517C – March 2018
Submit Documentation Feedback

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

249

PBIST Flow

www.ti.com

6.3.1 PBIST Sequence
1. Configure the device clock sources and domains so that they are running at their target frequencies.
2. Program the HCLK to PBIST ROM clock ratio by configuring the ROM_DIV field (bits 9:8) of the
MSTGCR register in the system module. This device supports a maximum PBIST ROM clock
frequency of HCLK.
3. Enable PBIST Controller by setting bit 0 of MSIENA register in the system module.
4. Enable the PBIST self-test by writing a value of Ah to bits 3:0 of the MSTGCR in the system module.
5. Wait for N VBUS clock cycles based on the HCLK to PBIST ROM clock ratio:
N = 16 when HCLK:PBIST ROM clock is 1:1
N = 32 when HCLK:PBIST ROM clock is 1:2
N = 64 when HCLK:PBIST ROM clock is 1:4
N = 64 when HCLK:PBIST ROM clock is 1:8
6. Write 1h to PACT register to enable the PBIST internal clocks.
7. Program the ALGO register to decide which algorithm from the instruction ROM must be selected (thedefault value of ALGO register is all 1s, meaning all algorithms are selected). Similarly, program the
RINFOL and RINFOU registers to indicate whether a particular RAM group in the instruction ROM
would get executed or not.
NOTE: In case of RAM Override (Override Register (OVER) = 00), the user should make sure that
only the algorithms that run on similar RAMs are selected. If a single port algorithm isselected in ROM Algorithm Mask Register (ALGO), the RAM Info Mask Lower Register(RINFOL) and RAM Info Mask Upper Register (RINFOU) must select only the single port
RAM’s. The same applies for two port RAM’s. Check Table 2-5 for information on thememory types.

8. Program OVER = 1h to run PBIST self-test without RAM override. Program OVER = 0 to run PBIST
self-test with RAM Override.
9. Write a value of 3h to the ROM mask register should the microcode for the Algorithms as well as theRAM groups loaded from the on chip PBIST ROM.
10. Write DLR (Data Logger register) with 14h to configure the PBIST run in ROM mode and to enable theconfiguration access. This starts the memory self-tests.
11. Wait for the PBIST self-test done by polling MSTDONE bit of MSTCGSTAT register in the systemmodule.
12. Once self-test is completed, check the Fail Status register FSRF0.
In case there is a failure (FSRF0 = 1h):a. Read RAMT register which indicates the RGS and RDS values of the failure RAM.
b. Read FSRC0 and FSRC1 registers which contains the failure count.
c. Read FSRA0 and FSRA1 registers which contains the address of first failure.
d. Read FSRDL0 and FSRDL1 registers which contains the failure data.
e. Write a value of 2h to the STR register to resume the test.
In case there is no failure (FSRF0 = 0), the memory self-test is completed.
a. Disable the PBIST internal clocks by writing a 0 to the PACT register.
b. Disable the PBIST self-test by writing a value of 5h to bits 3:0 of the MSTGCR in the systemmodule.
Repeat steps 2 through 9 for subsequent runs with different RAM group and algorithm configurations.
13. After required Memory tests are completed, Resume or Start the Normal Application software.

250

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Memory Test Algorithms on the On-chip ROM

www.ti.com

NOTE: The contents of the selected memory before the test will be completely lost. User softwaremust take care of data backup if required. Typically the PBIST tests are carried out at the
beginning of Application software.
Memory test fail information is reported in terms of RGS:RDS and not RAM GROUP. Check
Table 2-5 for information on the RGS:RDS information applicable to each memory being
tested.

6.4

Memory Test Algorithms on the On-chip ROM
This section provides a brief description for some of the test algorithms used for memory self-test.
1. March13N:• March13N is the baseline test algorithm for SRAM testing. It provides the highest overall coverage.
The other algorithms provide additional coverage of otherwise missed boundary conditions of the
SRAM operation.
• The concept behind the general march algorithm is to indicate:– The bit cell can be written and read as both a 1 and a 0.
– The bits around the bit cell do not affect the bit cell.
• The basic operation of the march is to initialize the array to a know pattern, then march a different
pattern through the memory.
• Type of faults detected by this algorithm:– Address decoder faults– Stuck-At faults– Coupled faults– State coupling faults– Parametric faults– Write recovery faults– Read/write logic faults
2. Map Column:• The MAP COLUMN algorithm is used to identify bit line sensitivities in the memory array. The
memory array is loaded with a row stripe pattern of all 1s in the first row followed by all 0s in thesecond row and repeated throughout the array. Then the values are read down each column onconsecutive cycles. The pattern in memory is inverted and run the column reads again.
• This particular pattern is looking for the following SRAM failure mechanisms:– Leakage due to a low resist path in a bit– An Open in the bit cell
– Leakage on a BIT or BITN line
– Miss-balance in the sense amp– Leakage in the sense– High resist in the sense amp– Failure of the pre-charge circuits after read operationsSPNU517C – March 2018
Submit Documentation Feedback

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

251

Memory Test Algorithms on the On-chip ROM

www.ti.com

3. Pre-Charge:• The Pre-Charge algorithm exercises the pre-charge capability within the SRAM array. It is
important to specifically target this issue as it is the only part of the analog portion of the SRAM
that is frequency sensitive.
• Similar to the MAP COLUMN algorithm, this algorithm works its way down the columns of the
SRAM. However, unlike the MAP COLUMN, this algorithm sandwiches a write between two reads
to force the worst-case conditions for the pre-charge circuits in the array.
• This test will fail when an increase in system frequency nears the minimum access time of thearray, at this boundary:– High voltage should operate better than low voltage.
– Likewise, low temperature should operate better than high temperature.
• If devices fail this test within the operational range of the CPU, then this is a very good test forcharacterizing the CPU/memory system.
4. DOWN1a:• The Down1 pattern forces the switching of all data bits and most address bits on consecutive readcycles. This is primarily a read/write test of the CPU/memory subsystem.
• The aggressive writes target at-speed write failures.
• It also targets row/column decode in the memory array.
• Targets the sense amps and sense amp multiplexors.
• Memory array output buffers.
• This algorithm operates as follows:– Load 1st half of the memory under test with one pattern.
– Load 2nd half of the memory under test with the bit-wise inverse of the pattern.
– Alternate sequential reads sequences between one sequence starting at the first of the array
and a second sequence starting at the end of the array.
– Upon completion of the read back, invert the patterns in both halves of the array and repeat theabove step.
– Perform an aggressive write sequence by alternate write between the bottom half of thememory upwards with an data pattern and the top half of the memory downwards with theinverse data pattern.
– Invert the data pattern for the above two steps to performing another sequence of aggressive
writes.
5. DTXN2a:This algorithm is used to target the global column decode Logic.

252

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

PBIST Control Registers

www.ti.com

6.5

PBIST Control Registers
PBIST controller uses configuration registers for programming the algorithm and its execution. All theconfiguration registers are memory mapped for access by the CPU through the Peripheral Bus interface.
The base address for the control registers is FFFF E400h.
NOTE: There is no watchdog functionality implemented in the PBIST controller. If a bad code is
executed, the PBIST runs forever. The PBIST controller does not guard against thissituation.
Registers are accessible only when the clock to the PBIST controller is active. The clock is
activated by first writing 1h to the PACT register.

Table 6-1. PBIST Registers
OffsetAcronym

Register Description

160h

RAMT

RAM Configuration Register

Section 6.5.1

Section164h

DLR

Datalogger Register

Section 6.5.2

16Ch

PCR

Program Control Register

Section 6.5.3

180h

PACT

PBIST Activate/Clock Enable Register

Section 6.5.4

184h

PBISTID

PBIST ID Register

Section 6.5.5

188h

OVER

Override Register

Section 6.5.6

190h

FSRF0

Fail Status Fail Register 0

Section 6.5.7

198h

FSRC0

Fail Status Count Register 0

Section 6.5.8

19Ch

FSRC1

Fail Status Count Register 1

Section 6.5.8

1A0h

FSRA0

Fail Status Address 0 Register

Section 6.5.9

1A4h

FSRA1

Fail Status Address 1 Register

Section 6.5.9

1A8h

FSRDL0

Fail Status Data Register 0

Section 6.5.10

1B0h

FSRDL1

Fail Status Data Register 1

Section 6.5.10

1C0h

ROM

ROM Mask Register

Section 6.5.11

1C4h

ALGO

ROM Algorithm Mask Register

Section 6.5.12

1C8h

RINFOLRAM Info Mask Lower Register

Section 6.5.13

1CCh

RINFOURAM Info Mask Upper Register

Section 6.5.14

SPNU517C – March 2018
Submit Documentation Feedback

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

253

PBIST Control Registers

www.ti.com

6.5.1 RAM Configuration Register (RAMT)
This register is divided into following internal registers, none of which have a default value after reset.
Figure 6-3 and Table 6-2 illustrate this register.
This register provides the information regarding the memory being currently tested. In case of a PBIST
failure, the application can read this register to identify the RGS:RDS values for the memory that failed theself-test.
Figure 6-3. RAM Configuration Register (RAMT) (offset = 160h)
31

24

23

16

RGS

RDS

R/W-x

R/W-x

15

8

7

6

5

2

1

0

DWR

SMS

PLS

RLS

R/W-x

R/W-x

R/W-x

R/W-x

LEGEND: R/W = Read/Write; R = Read only; -x = value is unknown after reset

Table 6-2. RAM Configuration Register (RAMT) Field Descriptions
Bit

Field

Description

31-24

RGS

Ram Group Select. Refer to Table 2-5 for information on the RGS value for each memory.

23-16

RDS

Return Data Select. Refer to Table 2-5 for information on the RDS values for each memory.

15-8

DWR

Data Width Register

7-6

SMS

Sense Margin Select Register

5-2

PLS

Pipeline Latency Select

1-0

RLS

RAM Latency Select254

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

PBIST Control Registers

www.ti.com

6.5.2 Datalogger Register (DLR)
This register puts the PBIST controller into the appropriate comparison modes for data logging. Figure 6-4
and Table 6-3 illustrate this register.
• DLR2: ROM-based testing mode
Writing a 1 to this register starts the ROM-based testing. This register is used to initiate ROM-based
testing from Config and ATE interfaces. Also, since a 1 in this bit position means the instruction ROM isused for memory testing, all the intermediate interrupts and PBIST done signal after each memory test aremasked until all the selected algorithms in the ROM are executed for all RAM groups. However, a failure
would stop the test and report the status immediately.
• DLR4: Configuration access modeThis mode, when set, indicates the CPU is being used to access PBIST.
Figure 6-4. Datalogger Register (DLR) (offset = 164h)31

16
Reserved
R-0

15

4

3

2

Reserved

5

DLR4

Rsvd

DLR2

1

Reserved

0

R-0

R/W-0

R/W-1

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-3. Datalogger Register (DLR) Field Descriptions
Bit

Field

31-5

Reserved

Value
0

Reads return 0. Do not change these bits from their default value of 0.

4

DLR4

0-1

Configuration access: setting this bit allows the host processor to configure the PBIST controller
registers.

3

Reserved

1

Reserved. Do not change this bit from its default value of 1.

2

DLR2

0-1

ROM-based testing: setting this bit enables the PBIST controller to execute test algorithms that are
stored in the PBIST ROM.

1-0

Reserved

0

Reserved. Do not change these bits from their default value of 0.

SPNU517C – March 2018
Submit Documentation Feedback

Description

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

255

PBIST Control Registers

www.ti.com

6.5.3 Program Control Register (PCR)
Figure 6-5 and Table 6-4 illustrate this register.
Figure 6-5. Program Control Register (PCR) (offset = 16Ch)
31

16
Reserved
R-0

15

5

4

0

Reserved

STR

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-4. Program Control Register (PCR) Field Descriptions
Bit

Field

31-5

Reserved

4-0

STR

Value
0

Reads return 0. Writes have no effect.
PBIST Controller Mode0

Reserved

1hStart / Time Stamp mode restart2h

Resume / Emulation read

4h

Stop

8h

Step / Step for emulation mode

10h

Check MISR mode

All other values

256

Description

Reserved

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

PBIST Control Registers

www.ti.com

6.5.4 PBIST Activate/Clock Enable Register (PACT)
This is the first register that needs to be programmed to activate the PBIST controller. Bit [0] is used forstatic clock gating, and unless a 1 is written to this bit, all the internal PBIST clocks are shut off. Figure 6-6
and Table 6-5 illustrate this register.
• PACT0
This bit must be set to turn on internal PBIST clocks. Setting this bit asserts an internal signal that is usedas the clock gate enable. As long as this bit is 0, any access to PBIST will not go through, and PBIST willremain in an almost zero-power mode.
NOTE: This register must be programmed to 1h during application self-test.

Figure 6-6. PBIST Activate/Clock Enable Register (PACT) (offset = 180h)
31

16
Reserved
R-0

15

1

0

Reserved

PACT0

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-5. PBIST Activate/Clock Enable Register (PACT) Field Descriptions
Bit

Field

31-1

Reserved

0

PACT0

Value

Description

0

Reads return 0. Writes have no effect.
PBIST internal clocks enable.

0

Disable PBIST internal clocks.

1

Enable PBIST internal clocks.

6.5.5 PBIST ID Register (PBISTID)
Functionality of the register is described in Figure 6-7 and Table 6-6.
Figure 6-7. PBIST ID Register (PBISTID) (offset = 184h)
31

16
Reserved
R-0

15

8

7

0

Reserved

PBIST ID

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-6. PBIST ID Register (PBISTID) Field Descriptions
Bit

Field

31-8

Reserved

Value
0

7-0

PBIST ID

0-FFh

SPNU517C – March 2018
Submit Documentation Feedback

Description
Reads return 0. Writes have no effect.
This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers.

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

257

PBIST Control Registers

www.ti.com

6.5.6 Override Register (OVER)
Functionality of the register is described in Figure 6-8 and Table 6-7.
• OVER0
While doing ROM-based testing, each algorithm downloaded from the ROM has a memory mask
associated with it that defines the applicable memory groups the algorithm will be run on. By default, this
bit is set to 1, which means the memory mask that is downloaded from the ROM will overwrite the RAM
info registers. The override bit can be reset by writing a 0 to it. In this case, the application can select theRAM groups to be tested by configuring the RAM info registers.
NOTE: When this override bit = 0, each algorithm selected in the ALGO register runs on each RAM
selected in the RINFOL and RINFOU registers. It must be ensured that:

1. Only the same type of memories (single port or two port) are selected, and
2. Only memories that are valid for all algorithms enabled via the ALGO registerare selected.
If the above two requirements are not met, the memory self-test fails.

Figure 6-8. Override Register (OVER) (offset = 188h)
31

16
Reserved
R-0

15

3

2

1

0

Reserved

Reserved

OVER0

R-0

R-0

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-7. Override Register (OVER) Field Descriptions
Bit

Field

31-3

Reserved

0

Reads return 0. Writes have no effect.

2-1

Reserved

0

Reserved. Do not change these bits from their default value of 0.

0

OVER0

258

Value

Description

RINFO Override Bit
0

The RAM info registers RINFOL and RINFOU are used to select the memories for test.

1

The memory information available from ROM overrides the RAM selection from the RAM info registers
RINFOL and RINFOU.

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

PBIST Control Registers

www.ti.com

6.5.7 Fail Status Fail Register (FSRF0)
This register indicates if Port0 failures occurred during a memory self-test. Bit [0] gets set whenever a
failure occurs. Functionality of the register is described in Figure 6-9 and Table 6-8.
Figure 6-9. Fail Status Fail Register 0 (FSRF0) (offset = 190h)
31

16
Reserved
R-0

15

1

0

Reserved

FSRF0

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 6-8. Fail Status Fail Register 0 (FSRF0) Field Descriptions
Bit

Field

31-1

Reserved

0

FSRF0

Value
0

Description
Reads return 0. Writes have no effect.
Fail Status 0. This bit would be cleared by reset of the module using MSTGCR register in systemmodule.

0

No failure occurred.

1

Failure occurred on port 0.

SPNU517C – March 2018
Submit Documentation Feedback

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

259

PBIST Control Registers

www.ti.com

6.5.8 Fail Status Count Registers (FSRC0 and FSRC1)
These registers keep count of the number of failures observed during the memory self-test. The PBIST
controller stops executing the memory self-test whenever a failure occurs in any memory instance for anyof the test algorithms. The value in FSRC0 / FSRC1 gets incremented by one whenever a failure occurs
and gets decremented by one when the failure is processed. FSRC0 is for Port 0 and FSRC1 is for Port 1.
Figure 6-10 and Table 6-9 illustrate the FSRC0 register; Figure 6-11 and Table 6-10 illustrate the FSRC1
register.
Figure 6-10. Fail Status Count 0 Register (FSRC0) (offset = 198h)31

16
Reserved
R-0

15

8

7

0

Reserved

FSRC0

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 6-9. Fail Status Count 0 Register (FSRC0) Field Descriptions
Bit

Field

Value

31-8

Reserved

0

7-0

FSRC0

0-FFh

Description
Reads return 0. Writes have no effect.
Fail Status Count 0. Indicates the number of failures on port 0.

Figure 6-11. Fail Status Count Register 1 (FSRC1) (offset = 19Ch)
31

16
Reserved
R-0

15

8

7

0

Reserved

FSRC1

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 6-10. Fail Status Count Register 1 (FSRC1) Field Descriptions
Bit

Field

31-8

Reserved

0

7-0

FSRC1

0-FFh

260

Value

Description
Reads return 0. Writes have no effect.
Fail Status Count 1. Indicates the number of failures on port 1.

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

PBIST Control Registers

www.ti.com

6.5.9 Fail Status Address Registers (FSRA0 and FSRA1)
These registers capture the memory address of the first failure on port 0 and port 1, respectively.
Figure 6-12 and Table 6-11 illustrate the FSRA0 register; Figure 6-13 and Table 6-12 illustrate the FSRA1
register.
Figure 6-12. Fail Status Address 0 Register (FSRA0) (offset = 1A0h)
31

16
Reserved
R-0

15

0
FSRA0
R-0

LEGEND: R = Read only; -n = value after reset

Table 6-11. Fail Status Address 0 Register (FSRA0) Field Descriptions
Bit

Field

31-16

Reserved

Value
0

15-0

FSRA0

0-FFFFh

Description
Reads return 0. Writes have no effect.
Fail Status Address 0. Contains the address of the first failure.

Figure 6-13. Fail Status Address 1 Register (FSRA1) (offset = 1A4h)
31

16
Reserved
R-0

15

0
FSRA1
R-0

LEGEND: R = Read only; -n = value after reset

Table 6-12. Fail Status Address 1 Register (FSRA1) Field Descriptions
Bit

Field

31-16

Reserved

Value
0

15-0

FSRA1

0-FFFFhSPNU517C – March 2018
Submit Documentation Feedback

Description
Reads return 0. Writes have no effect.
Fail Status Address 1. Contains the address of the first failure.

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

261

PBIST Control Registers

www.ti.com

6.5.10 Fail Status Data Registers (FSRDL0 and FSRDL1)
These registers are used to capture the failure data in case of a memory self-test failure. FSRDL0
corresponds to Port 0 and FSRDL1 corresponds to Port 1. Figure 6-14 and Table 6-13 illustrate the
FSRDL0 register; Figure 6-15 and Table 6-14 illustrate the FSRDL1 register.
Figure 6-14. Fail Status Data Register 0 (FSRDL0) (offset = 1A8h)
31

16
FSRDL0R-AAAAh

15

0
FSRDL0R-AAAAhLEGEND: R = Read only; -n = value after reset

Table 6-13. Fail Status Data Register 0 (FSRDL0) Field Descriptions
Bit

Field

Description

31-0

FSRDL0

Failure data on port 0

Figure 6-15. Fail Status Data Register 1 (FSRDL1) (offset = 1B0h)
31

16
FSRDL1
R-AAAAh

15

0
FSRDL1
R-AAAAhLEGEND: R = Read only; -n = value after reset

Table 6-14. Fail Status Data Register 1 (FSRDL1) Field Descriptions
Bit

Field

Description

31-0

FSRDL1

Failure data on port 1

262

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

PBIST Control Registers

www.ti.com

6.5.11 ROM Mask Register (ROM)This two-bit register sets appropriate ROM access modes for the PBIST controller. This register isillustrated in Figure 6-16. It can be programmed according to Table 6-15.
Figure 6-16. ROM Mask Register (ROM) (offset = 1C0h)
31

16
Reserved
R-0

15

2

1

0

Reserved

ROM

R-0

R/W-3hLEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-15. ROM Mask Register (ROM) Field Descriptions
Bit

Field

31-2

Reserved

1-0

ROM

Value
0

Description
Reads return 0. Writes have no effect.
ROM Mask

0

No information is used from ROM.

1h

Only RAM Group information from ROM.

2h

Only Algorithm information from ROM.

3h

Both Algorithm and RAM Group information from ROM. This option should be selected for application
self-test.

6.5.12 ROM Algorithm Mask Register (ALGO)This register is used to enable the algorithms to be used for the memory self-test routine. Each bit
corresponds to a specific algorithm. For an algorithm to be enabled, the corresponding bit in this registermust be set to 1. The default value of this register is all 1s, which means all the algorithms are enabled.
Bit [0] controls whether algorithm 1 is enabled or not. Figure 6-17 and Table 6-16 illustrate this register.
NOTE: Refer to Table 2-6 for available algorithms and the memories on which each algorithm canbe run.

Figure 6-17. ROM Algorithm Mask Register (ALGO) (offset = 1C4h)
31

24

23

16

ALGO[31-24]

ALGO[23-16]

R/W-FFh

R/W-FFh

15

8

7

0

ALGO[15-8]

ALGO[7-0]

R/W-FFh

R/W-FFhLEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-16. Algorithm Mask Register (ALGO) Field Descriptions
Bit

Field

31-0

ALGO[n]Value

Description
Algorithm 1-32 enable

0

Algorithm n is not selected.

1

Selects algorithm n for PBIST run.

SPNU517C – March 2018
Submit Documentation Feedback

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

263

PBIST Control Registers

www.ti.com

6.5.13 RAM Info Mask Lower Register (RINFOL)This register is used to select RAM groups to run the algorithms selected in the ALGO register. For analgorithm to be executed on a particular RAM group, the corresponding bit in this register must be set to 1.
The default value of this register is all 1s, which means all the RAM groups are selected. Bit [0] controls
whether RAM group 1 is selected or not. Figure 6-18 and Table 6-17 illustrate this register.
The information from this register is used only when bit [0] in the OVER register is not set.
NOTE: Refer to Table 2-5 for RAM info groups.

Figure 6-18. RAM Info Mask Lower Register (RINFOL) (offset = 1C8h)
31

24

23

16

RINFOL[31-24]

RINFOL[23-16]

R/W-FFh

R/W-FFh

15

8

7

0

RINFOL[15-8]

RINFOL[7-0]

R/W-FFh

R/W-FFhLEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-17. RAM Info Mask Lower Register (RINFOL) Field Descriptions
Bit

Field

31-0

RINFOL[n]Value

Description
RAM Group 1-32 enable0

RAM Group n is not selected.

1

Selects RAM group n for PBIST run.

6.5.14 RAM Info Mask Upper Register (RINFOU)
This register is used to select RAM groups to run the algorithms selected in the ALGO register. For analgorithm to be executed on a particular RAM group, the corresponding bit in this register must be set to 1.
The default value of this register is all 1s, which means all the RAM groups are selected. Bit [0] controls
whether RAM group 33 is selected or not. Figure 6-19 and Table 6-18 illustrate this register.
Figure 6-19. RAM Info Mask Upper Register (RINFOU) (offset = 1CCh)
31

24

23

16

RINFOU[31-24]

RINFOU[23-16]

R/W-FFh

R/W-FFh

15

8

7

0

RINFOU[15-8]

RINFOU[7-0]

R/W-FFh

R/W-FFhLEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-18. RAM Info Mask Upper Register (RINFOU) Field Descriptions
Bit

Field

31-0

RINFOU[n]

264

Value

Description
RAM Group 33-64 enable0

RAM Group n is not selected.

1

Selects RAM group n for PBIST run.

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

PBIST Configuration Examples

www.ti.com

6.6

PBIST Configuration Examples
The following examples assume that the PLL is locked and selected as clock source withHCLK = VCLK = 80MHz.

6.6.1 Example 1 : Configuration of PBIST Controller to Run Self-Test on DCAN1 RAM
This example explains the configurations for running March13, Down1A and Map Column algorithms on
DCAN1.
1. Program the HCLK to PBIST ROM clock ratio to 1:1 in system module.
MSTGCR[9:8] = 0
2. Enable PBIST Controller in system module.
MSIENA[31:0] = 0x00000001
3. Enable the PBIST self-test in system module.
MSTGCR[3:0] = 0xA
4. Wait for at least 16 VCLK cycles in a software loop.
5. Enable the PBIST internal clocks.
PACT = 0x1
6. Disable RAM Override. This will make the PBIST controller use the information provided by theapplication in the RINFOx and ALGO registers for the memory self-test.
OVER = 0x0
7. Select the Algorithm (refer to Table 2-6).
ALGO = 0x00000054 (Algo 3 = March13N, Algo 5 = down1A_red, Algo 7 = Map Column for two-port
DCAN1 RAM)
8. Program the RAM group Info to select DCAN1 (DCAN1 RAM is Group 3, refer to Table 2-5).
RINFOL = 0x00000004 (select RAM Group 3)
RINFOU = 0x00000000 (since this device supports up to RAM Group 14)
9. Select both Algorithm and RAM information from on chip PBIST ROM.
ROM = 0x3
10. Configure PBIST to run in ROM Mode and start PBIST run.
DLR = 0x14
11. Wait for PBIST test to complete by polling MSTDONE bit in system module.
while (MSTDONE != 1);
12. Once self-test is completed, check the Fail Status register FSRF0:
a. In case there is a failure (FSRF0 = 0x01):
i. Read RAMT register that indicates the RGS and RDS values of the failure RAM.
ii. Read FSRC0 and FSRC1 registers that contains the failure count.
iii. Read FSRA0 and FSRA1 registers that contains the address of first failure.
iv. Read FSRDL0 and FSRDL1 registers that contains the failure data.
v. Resume the Test, if required, using Program Control register (offset = 0x16C) STR = 2.
b. In case there is no failure (FSRF0 = 0x00), the memory self-test is completed:i. Disable the PBIST internal clocks.
PACT = 0
ii. Disable the PBIST self-test.
MSTGCR[3:0] = 0x5

SPNU517C – March 2018
Submit Documentation Feedback

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

265

PBIST Configuration Examples

www.ti.com

6.6.2 Example 2 : Configuration of PBIST Controller to Run Self-Test on ALL RAM Groups
This example explains the configurations for running March13, Down1A and Map Column algorithms on all
RAM groups defined in the PBIST ROM.
1. Program the HCLK to PBIST ROM clock ratio to 1:1 in system module.
MSTGCR[9:8] = 0
2. Enable PBIST Controller in system module.
MSIENA[31:0] = 0x00000001
3. Enable the PBIST self-test in system module.
MSTGCR[3:0] = 0xA
4. Wait for at least 16 VCLK cycles in a software loop.
5. Enable the PBIST internal clocks.
PACT = 0x1
6. Enable RAM Override.
OVER = 0x1
7. Select the Algorithms to be run (refer to Table 2-6).
ALGO = 0x000000FC (select March13N, Down1A and Map Column algorithms for single-port and twoport RAMs)
8. Select both Algorithm and RAM information from on chip PBIST ROM.
ROM = 0x3
9. Configure PBIST to run in ROM Mode and kickoff PBIST test.
DLR = 0x14
10. Wait for PBIST test to complete by polling MSTDONE bit in system module.
while (MSTDONE != 1)
11. Once self-test is completed, check the Fail Status register FSRF0:
a. In case there is a failure (FSRF0 = 0x01):
i. Read RAMT register that indicates the RGS and RDS values of the failure RAM.
ii. Read FSRC0 and FSRC1 registers that contains the failure count.
iii. Read FSRA0 and FSRA1 registers that contains the address of first failure.
iv. Read FSRDL0 and FSRDL1 registers that contains the failure data.
v. Resume the Test, if required, using Program Control register (offset = 0x16C) STR = 2.
b. In case there is no failure (FSRF0 = 0x00), the memory self-test is completed:i. Disable the PBIST internal clocks.
PACT = 0
ii. Disable the PBIST self-test.
MSTGCR[3:0] = 0x5

266

Programmable Built-In Self-Test (PBIST) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Chapter 7
SPNU517C – March 2018

CPU Self-Test Controller (STC) ModuleThis chapter describes the basics and configuration of the CPU self-test controller (STC) in the device.
Topic

7.1
7.2
7.3
7.4
7.5

...........................................................................................................................

Page

General Description ......................................................................................... 268
Application Self-Test Flow ................................................................................ 270
STC Test Coverage and Duration ....................................................................... 272
STC Control Registers ...................................................................................... 273
STC Configuration Example .............................................................................. 282

SPNU517C – March 2018
Submit Documentation Feedback

CPU Self-Test Controller (STC) Module
Copyright © 2018, Texas Instruments Incorporated

267

General Description

7.1

www.ti.com

General Description
The CPU self-test controller (STC) is used to test the ARM-CPU core using the Deterministic Logic Built-in
Self-Test (LBIST) Controller as the test engine. To achieve better coverage for the self-test of complex
cores like Cortex-R4, on-chip logic BIST is the preferred solution.

7.1.1 CPU Self-Test Controller Features
The CPU self-test controller has the following features:• Capable of running the complete test as well as running a few intervals at a time
– Ability to continue from the last executed interval (test set) as well as the ability to restart from the
beginning (first test set)
– Total of 26 intervals supported in this device• Complete isolation of the self-tested CPU core from the rest of the system during the self-test run– The self-tested CPU core master bus transaction signals are configured to be in idle mode during
the self-test run– Any master access to the CPU core under self-test will be held until the completion of the self-test• Ability to capture the failure interval number• Timeout counter for the CPU self-test run as a fail-safe feature• Able to read the MISR data (shifted from LBIST controller) of the last executed interval of the self-test
run for debugging purposes• STCCLK determines the self-test execution speed, STC clock divider (STCCLKDIV) register in thesystem module is used to divide HCLK (system clock) to generate STCCLK

7.1.2 STC Block Diagram
STC module provides an interface to the LBIST controller implemented on the core.
The CPU STC is composed of following blocks of logic:• ROM Interface• FSM and Sequence Control• Register Block• Peripheral Bus Interface (VBUSP Interface)• STC Bypass/ATE Interface
7.1.2.1

ROM Interface

This block handles the ROM address and control signal generation to read the self-test microcode fromthe ROM. The test microcode and golden signature value for each interval are stored in ROM.
7.1.2.1.1 FSM and Sequence Control
This block generates the signals and data to the LBIST controller based on the seed, test_type and scanchain depth.
7.1.2.1.2 Clock Control
The CLOCK CNTRL sub-block handles the internal clock selection and clock generation for the ROM and
LBIST controller.
7.1.2.2

Register BlockThis block handles the control of the self-test controller. This block contains various configuration andstatus registers which provide the result of a self-test run. These registers are memory mapped andaccessible through the Peripheral Bus (VBUSP) Interface. This block controls the reseeding (reloading theexisting seed of the PRPG) in the LBIST controller.
268

CPU Self-Test Controller (STC) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

General Description

www.ti.com

7.1.2.3

STC Bypass / ATE Interface

This is a production test interface. Only for TI internal use.
7.1.2.4

Peripheral Bus (VBUSP) Interface

STC control registers are accessed through the Peripheral Bus (VBUSP) Interface. During application
programming, configuration registers are programmed through the Peripheral Bus Interface to enable andrun the self-test controller.
Figure 7-1. STC Block Diagram
Global ClockController

Clock Controller
ESM

ROM

FSM
and
Sequence COMP
Controller BLK1

ROMInterface

COMP
BLK1

Cpu_Reset

misr_out
misr_out

STC

CPU1(BIST’ed core)
DBIST
CNTRL

STC REGSTC_BYPASS /BLOCK

ATE Interface

CCM

DBIST
CNTRL
CPU2
(BIST’ed
core)

VBUSP
Interface

PCR

Test

controller

SPNU517C – March 2018
Submit Documentation Feedback

CPU Self-Test Controller (STC) Module
Copyright © 2018, Texas Instruments Incorporated

269

Application Self-Test Flow

7.2

www.ti.com

Application Self-Test Flow
This section describes the STC module configuration and the application self-test flow that the user should
follow for successful execution.
The following two configurations must be part of the STC initialization code:• STC clock rate configuration, STC clock divider (STCCLKDIV) register in system module is used todivide HCLK (system clock) to generate STCCLK• Clear SYSESR register before triggering an STC test

7.2.1 STC Module Configuration•••

Configure the test interval count using STCGCR0[31:16] register. A maximum of 26 intervals aresupported in the device. The user can run 26 intervals together or in slices. If the tests are ran inslices, the user software can specify to the self-test controller whether to continue the run from the next
interval onwards or to restart from interval 0 using bit STCGCR0[0]. This bit gets reset after thecompletion of the self-test run.
Configure self-test run timeout counter preload register STCTPR. This register contains the total
number of VBUS clock cycles it will take before a self-test timeout error (TO_ERR) will be triggered
after the initiation of the self-test run.
Enable CPU self-test by writing the enable key to STCGCR1 register.

7.2.2 Context Saving
STC generates a CPU reset after completion of the test regardless of pass or fail. You can run the STC
test during startup or can divide STC into 26 or fewer intervals and run them during normal operation.
If STC is ran only on startup, the user software need not save the CPU contents since the reset caused
will go through all startup configurations. User should check the STCGSTAT register for the self-test
status before going to the application software.
If STC is divided into intervals and ran, user software must save the CPU contents and reload them after
the CPU reset caused by the completion of the STC test interval. The check for STC status should bypass
STC run if the reset is caused by an STC run to prevent a cyclic reset, that is, if reset is caused by STC
the second time through, then it should not be ran again. The user should also check the STCGSTAT
register for the self-test status before restoring the application software.
Following are some of the registers that are required to be backed up before and restored after self-test:
1. CPU core registers (all modes R0-R15, PC, CPSR)
2. CP15 System Control Coprocessor registers - MPU control and configuration registers, Auxiliary
Control Register used to Enable ECC, Fault Status Register.
3. CP13 Coprocessor Registers - FPU configuration registers, General Purpose Registers
4. Hardware Break Point and watch point registers like BVR, BSR, WVR, WSR etc.
For more information on the CPU reset, refer to the ARM® Cortex®-R4 Technical Reference Manual.
NOTE: Check all reset source flags in the SYSESR register after a CPU BIST execution. If a flag in
addition to CPU reset is set, clear the CPU reset flag and service the other reset sources
accordingly.

7.2.3 Entering CPU Idle Mode
After enabling the STC test by writing the STC enable key, the test is triggered only after the CPU is taken
to idle mode by executing the CPU Idle Instruction asm(“ WFI”).

270

CPU Self-Test Controller (STC) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Application Self-Test Flow

www.ti.com

7.2.4 Self-Test Completion and Error Generation
At the end of each interval, the 128 bit MISR value (reflected in registers CPUx_CURMISR[3:0]) from the
DBIST controller is shifted into the STC. This is compared with the golden MISR value stored in the ROM.
At the end of a CPU self-test, the STC controller updates the status flags in the Global Status Register(STCGSTAT) and resets the CPU. In case of a MISR mismatch or a test timeout, an error is generated
through the ESM module. A test error signal is asserted when a MISR mis-compare occurs during the selftest. A time out error is asserted when a timeout occurs during the self-test, meaning the test could notcomplete within the time specified in the timeout counter preload register STCTPR. However, at thedevice level, these two errors are combined and mapped to a single ESM channel. To identify which error
occurred, user software must check the Global Status Register (STCGSTAT) and the Fail Status Register(STCFSTAT) in the ESM interrupt service routine.
Figure 7-2 illustrates the application self-test flow chart, it is drawn based on the assumption that thedevice has gone through startup, necessary clocks initialized and the SYSESR register bits cleared.
Figure 7-2. Application Self-Test Flow Chart
Configure STCCLK rate using STCCLKDIV
register in SYS2 register frame.

Program the STCGCR0 registers tospecify the number of intervals(N), timeout
counter etc for a selftest run.

Configure STC_ENA Key toenable SelfTest
NO

StartUp selftest?

Store CPU state and Registers in Memory
before starting STC Test

YES

Configure CPU in WFI mode
(IDLE mode)NO

WFI executed?
YES

CPU SelfTest execution.
CPU configured into safe mode

YES

SelfTest Done?
NO

CPU reset asserted

Read the SelfTest and system status
registers.
Retrieve state of CPU and Registers
and continue Application Software.

SPNU517C – March 2018
Submit Documentation Feedback

CPU Self-Test Controller (STC) Module
Copyright © 2018, Texas Instruments Incorporated

271

STC Test Coverage and Duration

7.3

www.ti.com

STC Test Coverage and Duration
The test coverage and number of test execution cycles (STCCLK) for each test interval when the device isrunning at HCLK = 90 MHz, VCLK = 90 MHz, and STCCLK = 45 MHz are shown in Table 7-1.
Table 7-1. STC Test Coverage and Duration

272

Intervals

Test Coverage (%)

Test Time (Cycles)

0

0

0

0.00

1

60.06

1365

30.33

2

68.71

2730

60.67

3

73.35

4095

91.00

4

76.57

5460

121.33

5

78.7

6825

151.67

6

80.4

8190

182.00

7

81.76

9555

212.33

8

82.94

10920

242.67

9

83.84

12285

273.00

10

84.58

13650

303.33

11

85.31

15015

333.67

12

85.9

16380

364.00

13

86.59

17745

394.33

14

87.17

19110

424.67

15

87.67

20475

455.00

16

88.11

21840

485.33

17

88.53

23205

515.67

18

88.93

24570

546.00

19

89.26

25935

576.33

20

89.56

27300

606.67

21

89.86

28665

637.00

22

90.1

30030

667.33

23

90.36

31395

697.67

24

90.62

32760

728.00

25

90.86

34125

758.33

26

91.06

35490

788.67

CPU Self-Test Controller (STC) Module

Test Time (µs)

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

STC Control Registers

www.ti.com

7.4

STC Control Registers
STC control registers are accessed through Peripheral Bus (VBUSP) interface. Read and write access in
8, 16, and 32 bits are supported. The base address for the control registers is FFFF E600h.
NOTE: In suspend mode, all registers can be written regardless of user or privilege mode.

Table 7-2. STC Control Registers
OffsetAcronym

Register Description

00h

STCGCR0

STC Global Control Register 0

Section 7.4.1

Section04h

STCGCR1

STC Global Control Register 1

Section 7.4.2

08h

STCTPR

Self-Test Run Timeout Counter Preload Register

Section 7.4.3

0Ch

STC_CADDRSTC Current ROM Address Register

Section 7.4.4

10h

STCCICRSTC Current Interval Count Register

Section 7.4.5

14h

STCGSTAT

Self-Test Global Status Register

Section 7.4.6

18h

STCFSTAT

Self-Test Fail Status Register

Section 7.4.7

1Ch

CPU1_CURMISR3

CPU1 Current MISR Register 3

Section 7.4.8

20h

CPU1_CURMISR2

CPU1 Current MISR Register 2

Section 7.4.8

24h

CPU1_CURMISR1

CPU1 Current MISR Register 1

Section 7.4.8

28h

CPU1_CURMISR0

CPU1 Current MISR Register 0

Section 7.4.8

2Ch

CPU2_CURMISR3

CPU2 Current MISR Register 3

Section 7.4.930hCPU2_CURMISR2

CPU2 Current MISR Register 2

Section 7.4.9

34hCPU2_CURMISR1

CPU2 Current MISR Register 1

Section 7.4.9

38hCPU2_CURMISR0

CPU2 Current MISR Register 0

Section 7.4.9

3Ch

STCSCSCR

Signature Compare Self Check Register

Section 7.4.10

SPNU517C – March 2018
Submit Documentation Feedback

CPU Self-Test Controller (STC) Module
Copyright © 2018, Texas Instruments Incorporated

273

STC Control Registers

www.ti.com

7.4.1 STC Global Control Register 0 (STCGCR0)
This register is described in Figure 7-3 and Table 7-3.
NOTE: On a power-on reset or system reset, this register gets reset to its default values.

Figure 7-3. STC Global Control Register 0 (STCGCR0) (offset = 00h)
31

16
INTCOUNT
R/W-1

15

1

0

Reserved

RS_CNT

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 7-3. STC Global Control Register 0 (STCGCR0) Field Descriptions
Bit

Field

Value

Description

31-16

INTCOUNT

0-FFFFh

Number of intervals of self-test run.
This register specifies the number of intervals to run for the self-test run. This corresponds tothe number of intervals to be ran from the value reflected in the current interval counter.

15-1

Reserved

0

RS_CNT0

Reads return 0. Writes have no effect.
Restart or Continue
This bit specifies whether to continue the run from next interval onwards or to restart frominterval 0. This bit gets reset after the completion of a self-test run.

0

Continue STC run from the previous interval.

1

Restart STC run from interval 0.

7.4.2 STC Global Control Register 1 (STCGCR1)
This register is described in Figure 7-4 and Table 7-4.
NOTE: On a power-on reset or system reset, this register resets to its default value. Also at thecompletion of a self-test run, this register automatically resets to its default value.

Figure 7-4. STC Global Control Register 1 (STCGCR1) (offset = 04h)
31

16
Reserved
R-0

15

4

3

0

Reserved

STC_ENA

R-0

R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after nPORST (power on reset) or System reset

Table 7-4. STC Global Control Register 1 (STCGCR1) Field Descriptions
Bit

Field

31-4

Reserved

3-0

STC_ENA

274

Value
0

Description
Reads return 0. Writes have no effect.
Self-test run enable key.

AhSelf-test run is enabled.

All other values

Self-test run is disabled.

CPU Self-Test Controller (STC) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

STC Control Registers

www.ti.com

7.4.3 Self-Test Run Timeout Counter Preload Register (STCTPR)
This register is described in Figure 7-5 and Table 7-5.
NOTE: On a power-on reset or system reset, this register gets reset to its default values.

Figure 7-5. Self-Test Run Timeout Counter Preload Register (STCTPR) (offset = 08h)
31

0
RTOD
R/WP-FFFF FFFFh

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after nPORST (power on reset) or System reset

Table 7-5. Self-Test Run Timeout Counter Preload Register (STCTPR)
Bit

Field

Description

31-0

RTOD

Self-test timeout count preload.
This register contains the total number of VBUS clock cycles it will take before a self-test timeout error(TO_ERR) will be triggered after the initiation of the self-test run. This is a fail safe feature to prevent the device
from hanging up due to a runaway test during the self-test execution.
The preload count value gets loaded into the self-test time out down counter whenever a self-test run isinitiated (STC_KEY is enabled) and gets disabled on completion of a self-test run.

7.4.4 STC Current ROM Address Register (STC_CADDR)This register is described in Figure 7-6 and Table 7-6.
NOTE: When the RS_CNT bit in STCGCR0 is set to a 1 on the start of a self-test run, or on a
power-on reset or system reset, this register resets to all zeroes.

Figure 7-6. STC Current ROM Address Register (STC_CADDR) (offset = 0Ch)
31

0
ADDR
R-0

LEGEND: R = Read only; -n = value after nPORST (power on reset) or System reset

Table 7-6. STC Current ROM Address Register (STC_CADDR) Field Descriptions
Bit

Field

Description

31-0

ADDR

Current ROM AddressThis register reflects the current ROM address (for micro code load) which is the current value of the STC
program counter.

SPNU517C – March 2018
Submit Documentation Feedback

CPU Self-Test Controller (STC) Module
Copyright © 2018, Texas Instruments Incorporated

275

STC Control Registers

www.ti.com

7.4.5 STC Current Interval Count Register (STCCICR)
This register is described in Figure 7-7 and Table 7-7.
NOTE: When the RS_CNT bit in STCGCR0 is set to a 1 or on a power-on reset, the current intervalcounter resets to the default value.

Figure 7-7. STC Current Interval Count Register (STCCICR) (offset = 10h)31

16
Reserved
R-0

15

0
N
R-0

LEGEND: R = Read only; -n = value after reset

Table 7-7. STC Current Interval Count Register (STCCICR) Field Descriptions
Bit

Field

31-16

Reserved

15-0

N

Value
0
0-FFFFh

Description
Reads return 0. Writes have no effect.
Interval NumberThis specifies the last executed interval number.

276

CPU Self-Test Controller (STC) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

STC Control Registers

www.ti.com

7.4.6 Self-Test Global Status Register (STCGSTAT)This register is described in Figure 7-8 and Table 7-8.
NOTE: The two status bits can be cleared to their default values on a write of 1 to the bits.
Additionally, when the STC_ENA key in STCGCR1 is written from a disabled state toenabled state, the two status flags get cleared to their default values. This register gets reset
to its default value with power-on reset assertion.

Figure 7-8. Self-Test Global Status Register (STCGSTAT) (offset = 14h)31

8Reserved
R-0
10

Reserved

2

TEST_FAIL

TEST_DONE

R-0

R/WP-0R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 7-8. Self-Test Global Status Register (STCGSTAT) Field Descriptions
Bit

Field

31-2

Reserved

1

TEST_FAIL

0

Value
0

Description
Reads return 0. Writes have no effect.
Test Fail0

Self-test run has not failed.

1

Self-test run has failed.

TEST_DONE

Test Done0

Not completed.

1

Self-test run completed.
The test done flag is set to a 1 for any of the following conditions:
1.
2.
3.

When the STC run is complete without any failure
When a failure occurs on a STC run
When a timeout failure occurs

Reset is generated to the CPU on which the STC run is being performed when TEST_DONE goeshigh (the test is completed).

SPNU517C – March 2018
Submit Documentation Feedback

CPU Self-Test Controller (STC) Module
Copyright © 2018, Texas Instruments Incorporated

277

STC Control Registers

www.ti.com

7.4.7 Self-Test Fail Status Register (STCFSTAT)This register is described in Figure 7-9 and Table 7-9.
NOTE: The three status bits can be cleared to their default values on a write of 1 to the bits.
Additionally, when the STC_ENA key in STCGCR1 is written from a disabled state to an
enabled state, the three status bits get cleared to their default values. This register gets reset
to its default value with power-on reset assertion.

Figure 7-9. Self-Test Fail Status Register (STCFSTAT) (offset = 18h)31

8Reserved
R-0
2

1

0

Reserved

3

TO_ERR

CPU2_FAIL

CPU1_FAIL

R-0

R/WP-0R/WP-0R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after nPORST (power on reset) or System reset

Table 7-9. Self-Test Fail Status Register (STCFSTAT) Field Descriptions
Bit

Field

31-3

Reserved

2

TO_ERR

1

0

278

Value
0

Description
Reads return 0. Writes have no effect.
Timeout Error0

No time out error occurred.

1

Self-test run failed due to a timeout error.

CPU2_FAIL

CPU2 failure info0

No MISR mismatch for CPU2.

1

Self-test run failed due to MISR mismatch for CPU2.

CPU1_FAIL

CPU1 failure info0

No MISR mismatch for CPU1.

1

Self-test run failed due to MISR mismatch for CPU1.

CPU Self-Test Controller (STC) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

STC Control Registers

www.ti.com

7.4.8 CPU1 Current MISR Registers (CPU1_CURMISR3-CPU1_CURMISR0)This register is described in Figure 7-10 through Figure 7-13 and Table 7-10.
NOTE: On a power-on reset or system reset, this register gets reset to its default values.

Figure 7-10. CPU1 Current MISR Register 3 (CPU1_CURMISR3) (offset = 1Ch)
31

16
MISR[31:16]
R-0

15

0
MISR[15:0]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 7-11. CPU1 Current MISR Register 2 (CPU1_CURMISR2) (offset = 20h)
31

16
MISR[63:48]
R-0

15

0
MISR[47:32]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 7-12. CPU1 Current MISR Register 1 (CPU1_CURMISR1) (offset = 24h)31

16
MISR[95:80]
R-0

15

0
MISR[79:64]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 7-13. CPU1 Current MISR Register 0 (CPU1_CURMISR0) (offset = 28h)31

16
MISR[127:112]
R-0

15

0
MISR[111:96]
R-0

LEGEND: R = Read only; -n = value after reset

Table 7-10. CPU1 Current MISR Register (CPU1_CURMISR[3:0]) Field Descriptions
Bit

Field

Description

127-0

MISR

MISR data from CPU1
This register contains the MISR data from the CPU1 for the most recent interval. This value is compared with
the GOLDEN MISR value copied from ROM.

SPNU517C – March 2018
Submit Documentation Feedback

CPU Self-Test Controller (STC) Module
Copyright © 2018, Texas Instruments Incorporated

279

STC Control Registers

www.ti.com

7.4.9 CPU2 Current MISR Registers (CPU2_CURMISR3-CPU2_CURMISR0)This register is described in Figure 7-14 through Figure 7-17 and Table 7-11.
NOTE: On a power-on reset or system reset, this register gets reset to its default values.

Figure 7-14. CPU2 Current MISR Register 3 (CPU2_CURMISR3) (offset = 2Ch)
31

16
MISR[31:16]
R-0

15

0
MISR[15:0]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 7-15. CPU2 Current MISR Register 2 (CPU2_CURMISR2) (offset = 30h)31

16
MISR[63:48]
R-0

15

0
MISR[47:32]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 7-16. CPU2 Current MISR Register 1 (CPU2_CURMISR1) (offset = 34h)
31

16
MISR[95:80]
R-0

15

0
MISR[79:64]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 7-17. CPU2 Current MISR Register 0 (CPU2_CURMISR0) (offset = 38h)31

16
MISR[127:112]
R-0

15

0
MISR[111:96]
R-0

LEGEND: R = Read only; -n = value after reset

Table 7-11. CPU2 Current MISR Register (CPU2_CURMISR[3:0]) Field Descriptions
Bit

Field

Description

127-0

MISR

MISR data from CPU2
This register contains the MISR data from the CPU2 for the most recent interval. This value is compared with
the GOLDEN MISR value copied from ROM.

280

CPU Self-Test Controller (STC) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

STC Control Registers

www.ti.com

7.4.10 Signature Compare Self Check Register (STCSCSCR)
This register is described in Figure 7-18 and Table 7-12.
NOTE: This register is used to enable the self-check feature of the CPU Self-Test Controller's (STC)
signature compare logic. Self-check can only be done for the STC interval 0 by setting the
RS_CNT bit in STCGCR0 to 1 to restart the self-test. The STC run will fail for signature misscompare, provided the signature compare logic is operating correctly. To proceed withregular CPU self-test, STCSCSCR should be programmed to disable the self-check featureand clear the RS_CNT bit in STCGCR0 to 0. This register gets reset to its default value withpower-on or system reset assertion.

Figure 7-18. Signature Compare Self Check Register (STCSCSCR) (offset = 3Ch)
31

15
Reserved
R-0

15

5

4

3

0

Reserved

FAULT_INSSELF_CHECK_KEY

R-0

R/WP-0R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after nPORST (power on reset) or System reset

Table 7-12. Signature Compare Self Check Register (STCSCSCR) Field Descriptions
Bit

Field

31-5

Reserved

4

FAULT_INS

3-0

Value
0

Description
Reads return 0. Writes have no effect.
Fault Insertion0

No fault insertion.

1

Generates a signal out of the STC module to the CPU for inserting a stuck-at fault(stuck-at-0) in the CPU which will make the signature compare fail.

SELF_CHECK_KEY

Signature compare logic self-check key
Ah

Signature compare self-check is enabled.

All other values Signature compare self-check is disabled.

SPNU517C – March 2018
Submit Documentation Feedback

CPU Self-Test Controller (STC) Module
Copyright © 2018, Texas Instruments Incorporated

281

STC Configuration Example

7.5

www.ti.com

STC Configuration Example
The following example assumes that the PLL is locked and selected as the system clock source withVCLK = HCLK = 80MHz.

7.5.1 Example 1: Self-Test Run for 24 IntervalThis example explains the configurations for running STC Test for maximum Test Intervals 24.
1. Maximum STC clock rate support is HCLK/2. STCCLKDIV[26:24] register in the secondary systemmodule frame at location 0xFFFF E108 is used to program the STCCLK prescaler to divide down fromHCLK as necessary (0 for /1, 1 for /2, 2 for /3, and so on).
2. Clear CPU RST status bit in the System Exception Status Register in the system module.
SYSESR[5] = 1
3. Configure the test interval count in the STC module.
STCGCR0[31:16] = 24
4. Configure the self-test run rime out counter preload Register. This will be set to the maximum time forthis example but can be calculated as tTO = STCPTR X tc(VCLK)STCTPR[31:0] = 0xFFFFFFFF
5. Enable CPU self-test.
STCGCR1[3:0] = 0xA
6. Perform a context save of CPU state and configuration registers that gets reset on CPU reset.
7. Put the CPU in idle mode by executing CPU Idle Instruction.
asm(“ WFI”)
8. Upon CPU reset, verify the CPU RST status bit in the System Exception Status Register is set. This
also verifies that no other resets occurred during the self-test.
SYSESR[5] == 1
9. Check the STCGSTAT register for the self-test Status.
Check the TEST_DONE bit before evaluating the TEST_FAIL bit.
If TEST_DONE = 0, the self-test is not completed. Restart/resume the STC test.
If (TEST_DONE = 1 and TEST_FAIL = 1), the self-test is completed and failed.
• Read the STC Fail Status Register STCFSTAT[2:0] to identify the type of Failure (Timeout, CPU1 fail,CPU2 fail).
In case there is no failure (TEST_DONE = 1 and TEST_FAIL = 0), the memory self-test is completed
successfully.
• Recover the CPU status, configuration registers and continue application software.

282

CPU Self-Test Controller (STC) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Chapter 8
SPNU517C – March 2018

CPU Compare Module for Cortex™-R4 (CCM-R4)
This chapter describes the CPU compare module for Cortex-R4 (CCM-R4). This device implements two
instances of the Cortex-R4 CPU which are running in lock step to detect faults which may result in unsafe
operating conditions. The CCM-R4 detects faults and signals them to an error signaling module (ESM).
Topic...........................................................................................................................

8.1
8.2
8.3
8.4

Main Features ..................................................................................................
Block Diagram..................................................................................................
Module Operation .............................................................................................
CCM-R4 Control Registers .................................................................................

SPNU517C – March 2018
Submit Documentation Feedback

CPU Compare Module for Cortex™-R4 (CCM-R4)
Copyright © 2018, Texas Instruments Incorporated

Page

284
284
285
288

283

Main Features

8.1

www.ti.com

Main Features
Safety-critical applications require run-time detection of faults in the Central Processing Unit (CPU). For
this purpose, the CPU Compare Module for Cortex-R4 (CCM-R4) compares the core compare bus outputsof two Cortex-R4 CPUs running in a 1oo1D (one-out-of-one, with diagnostics) lockstep configuration. Any
difference in the core compare bus outputs of the CPUs is flagged as an error. For diagnostic purposes,
the CCM-R4 also incorporates a self-test capability to allow for boot time checking of hardware faults
within the CCM-R4 itself.
The main features of the CCM-R4 are:• run-time detection of faults• self-test capability• error forcing capability

8.2

Block Diagram
Figure 8-1 shows the interconnection diagram of the CCM-R4 with the two Cortex-R4 CPUs. The corecompare bus outputs of the CPUs are compared in the CCM-R4. To avoid common mode impacts, thesignals of the CPUs to be compared are temporally diverse. The output signals of the master CPU aredelayed 2 cycles while the input signals of checker CPU are delayed 2 cycles.
Figure 8-1. Block Diagram
CCM-R42 cycles delay
CCM-R4compareCPU1CLK

CPU 1
Master CPU

compareerror

ESM(ErrorSignaling
Module)CPU 2
Checker CPU

2 cycles delay
CPU2CLK

284

CPU Compare Module for Cortex™-R4 (CCM-R4)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

8.3

Module Operation
The CCM-R4 compares the core compare bus outputs of the master and checker Cortex-R4 CPUs on the
microcontroller and signals an error on any mismatch. This comparison is started 6 CPU clock cycles after
the CPU comes out of reset to ensure that CPU output signals have propagated to a known value after
reset. Once comparison is started, the CCM module continues to monitor the outputs of two CPUs without
any software intervention. Upon an error software needs to handle it.
The CCM-R4 can run in one of the following four operating modes:
1. 1oo1D lock step
2. self-test
3. error forcing
4. self-test error forcing
The operating mode can be selected by writing a dedicated key to the key register (MKEY).

8.3.1 1oo1D Lock Step Mode
This is the default mode on start-up.
In lock step mode, the compare bus output signals of both CPUs are compared. A difference in the CPUcompare bus outputs is indicated by signaling an error to the ESM which sets the error flag “CCM-R4 compare”.
NOTE: The CPU compare error asserts “CCM-R4 self-test error” flag as well. By doing this, the CPUcompare error has two paths (“CCM-R4 - compare” and “CCM-R4 self-test error” flag) to theESM, so that even if one of the paths fails, the error is still propagated to the ESM.

Not all internal registers of the Cortex R4 CPU have fixed values upon reset. To avoid an erroneous
CCMR4 compare error, the application software needs to ensure that the CPU registers of both CPUs are
initialized with the same values before the registers are used, including function calls where the registervalues are pushed onto the stack.

8.3.2 Self-Test ModeIn self-test mode, the CCM-R4 checks itself for faults. During self-test, the compare error module output
signal is deactivated. Any fault detected inside the CCM-R4 will be flagged by ESM error “CCM-R4 - selftest”.
In self-test mode, the CCM-R4 automatically generates test patterns to look for any hardware faults. If a
fault is detected, then a self-test error flag is set, a self-test error signal is asserted and sent to the ESM,
and the self-test is terminated immediately. If no fault is found during self-test, the self-test complete flag isset. In both cases, the CCM-R4 remains in self-test mode after the test has been terminated or completed,and the application needs to switch the CCM-R4 mode by writing another key to the mode key register(MKEY). During the self-test operation, the compare error signal output to the ESM is inactive irrespectiveof the compare result.
There are two types of patterns generated by CCM-R4 during self-test mode:i. Compare Match Test
ii. Compare Mismatch Test
CCM-R4 first generates Compare Match Test patterns, followed by Compare Mismatch Test patterns.
Each test pattern is applied on both CPU signal inputs of the CCM-R4’s compare block and clocked for
one cycle. The duration of self-test is 3615 CPU clock cycles (GCLK).
NOTE: During self-test, both CPUs can execute normally, but the compare logic will not be checking
any CPU signals. Also during self-test, only the compare unit logic is tested and not the
memory mapped register controls for the CCM-R4. The self-test is not interruptible.

SPNU517C – March 2018
Submit Documentation Feedback

CPU Compare Module for Cortex™-R4 (CCM-R4)
Copyright © 2018, Texas Instruments Incorporated

285

Module Operation

8.3.2.1

www.ti.com

Compare Match Test

During the Compare Match Test, there are four different test patterns generated to stimulate the CCM-R4.
An identical vector is applied to both input ports at the same time expecting a compare match. These
patterns cause the self-test logic to exercise every CPU compare bus output signal in parallel. If thecompare unit produces a compare mismatch then the self-test error flag is set, the self-test error signal isgenerated, and the Compare Match Test is terminated.
The four test patterns used for the Compare Match Test are:• All 1s on both CPU signal ports• All 0s on both CPU signal ports• 0xAs on both CPU signal ports• 0x5s on both CPU signal ports
These four test patterns will take four clock cycles to complete. Table 8-1 illustrates the sequence ofCompare Match Test.
Table 8-1. Compare Match Test Sequence
CPU 1 Signal Position286

CPU 2 Signal Position

Cycle

n:8

7

6

5

4

3

2

1

0

n:8

7

6

5

4

3

2

1

0

1s

1

1

1

1

1

1

1

1

1s

1

1

1

1

1

1

1

1

0

0s

0

0

0

0

0

0

0

0

0s

0

0

0

0

0

0

0

0

1

0xA

1

0

1

0

1

0

1

0

0xA

1

0

1

0

1

0

1

0

2

0x5

0

1

0

1

0

1

0

1

0x5

0

1

0

1

0

1

0

1

3

CPU Compare Module for Cortex™-R4 (CCM-R4)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

8.3.2.2

Compare Mismatch Test

During the Compare Mismatch Test, the number of test patterns is equal to twice the number of CPU
output signals to compare in lock step mode. An all 1s vector is applied to the CCM-R4’s CPU1 input port
and the same pattern is also applied to the CCM-R4’s CPU2 input port but with one bit flipped startingfrom signal position 0. The un-equal vector will cause the CCM-R4 to expect a compare mismatch atsignal position 0, if the CCM-R4 logic is working correctly. If, however, the CCM-R4 logic reports acompare match, the self-test error flag is set, the self-test error signal is asserted, and the Compare
Mismatch Test is terminated.
This Compare Mismatch Test algorithm repeats in a domino fashion with the next signal position flipped
while forcing all other signals to logic level 1. This sequence is repeated until every single signal positionis verified on both CPU signal ports.
The Compare Mismatch Test is terminated if the CCM-R4 reports a compare match versus the expectedcompare mismatch. This test ensures that the compare unit is able to detect a mismatch on every CPU
signal being compared. Table 8-2 illustrates the sequence of Compare Mismatch Test. There is no error
signal is sent to ESM if the expected errors are seen with each pattern.
Table 8-2. Compare Mismatch Test Sequence
CPU 1 Signal Positionn

CPU 2 Signal Position

n-1:8

7

6

5

4

3

2

1

0

n

n-1:8

7

6

5

4

3

2

1

0

Cycle

1

1

1s

1

1

1

1

1

1

1

1

1

1

1s

1

1

1

1

1

1

1

0

0

1

1

1s

1

1

1

1

1

1

1

1

1

1

1s

1

1

1

1

1

1

0

1

1

1

1

1s

1

1

1

1

1

1

1

1

1

1

1s

1

1

1

1

1

0

1

1

2

1

1

1s

1

1

1

1

1

1

1

1

1

1

1s

1

1

1

1

0

1

1

1

3
n-1

::
1

1

1s

1

1

1

1

1

1

1

1

1

0

1s

1

1

1

1

1

1

1

1

1

1

1s

1

1

1

1

1

1

1

1

0

1

1s

1

1

1

1

1

1

1

1

n

1

1

1s

1

1

1

1

1

1

1

0

1

1

1s

1

1

1

1

1

1

1

1

n+1

1

1

1s

1

1

1

1

1

1

0

1

1

1

1s

1

1

1

1

1

1

1

1

n+2

1

1

1s

1

1

1

1

1

0

1

1

1

1

1s

1

1

1

1

1

1

1

1

n+3

1

1

1s

1

1

1

1

0

1

1

1

1

1

1s

1

1

1

1

1

1

1

1

n+4

::
1

0

1s

1

1

1

1

1

1

1

1

1

1

1s

1

1

1

1

1

1

1

1

2n-1

0

1

1s

1

1

1

1

1

1

1

1

1

1

1s

1

1

1

1

1

1

1

1

2n

SPNU517C – March 2018
Submit Documentation Feedback

CPU Compare Module for Cortex™-R4 (CCM-R4)
Copyright © 2018, Texas Instruments Incorporated

287

Module Operation

www.ti.com

8.3.3 Error Forcing ModeIn error forcing mode, a test pattern is applied to the CPU related inputs of the CCM-R4 compare logic toforce an error in the compare error output signal of the compare unit. The ESM error flag “CCM-R4 compare” is expected after the error forcing mode completes. As a side effect, the “CCM-R4 self-test
error” flag is also asserted whenever the CPU compare error is asserted.
Error forcing mode is similar to the Compare Mismatch Test operation of self-test mode in which an
unequal vector is applied to the CCM-R4 CPU signal ports. The error forcing mode forces the compare
mismatch to actually assert the compare error output signal. This ensures that faults in the path between
CCM-R4 and ESM is detected.
Only one hardcoded test pattern is applied into CCM-R4 during error forcing mode. A repeated 0x5
pattern is applied to CPU1 signal port of CCM-R4 input while a repeated 0xA pattern is applied to theCPU2 signal port of CCM-R4 input. The error forcing mode takes one cycle to complete. Hence, the failingsignature is presented for one clock cycle. After that, the mode is automatically switched to lock step
mode. The key register (MKEY) will indicate the lock step key mode once it is switched to lock step mode.
During the one cycle required by the error forcing test, the CPU output signals are not compared. User
should expect the ESM to trigger a response (report the CCM-R4 fail). If no error is detected by ESM, thena hardware fault is present.

8.3.4 Self-Test Error Forcing ModeIn self-test error forcing mode, an error is forced at the self-test error signal. The compare unit is stillrunning in lockstep mode and the key is switched to lockstep after one clock cycle. The ESM error flag
“CCM-R4 - self-test” is expected after the self-test error forcing mode completes. Once the expected
errors are seen, the application can clean the error through ESM module.

8.3.5 Operation During CPU Debug Mode
Certain debug operations place the CPU in a halting debug state where the code execution is halted.
Because halting debug events are asynchronous, there is a possibility for the debug requests to cause
loss of lockstep. CCM-R4 will disable upon detection of halting debug requests. Core compare error will
not be generated and flags will not update. A CPU reset is needed to ensure the CPUs are again inlockstep and will also re-enable the CCM-R4.

8.4

CCM-R4 Control Registers
Table 8-3 lists the CCM-R4 registers. Each register begins on a 32-bit word boundary. The registers
support 32-bit, 16-bit, and 8-bit accesses. The base address for the control registers is FFFF F600h.
Table 8-3. CCM-R4 Control Registers

288

OffsetAcronym

Register Description

SectionFFFF F600h

CCMSR

CCM-R4 Status Register

Section 8.4.1

FFFF F604h

CCMKEYR

CCM-R4 Key Register

Section 8.4.2

CPU Compare Module for Cortex™-R4 (CCM-R4)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

CCM-R4 Control Registers

www.ti.com

8.4.1 CCM-R4 Status Register (CCMSR)
The contents of this register should be interpreted in context of what test was selected. That is, in whatmode the CCM is operating.
Figure 8-2. CCM-R4 Status Register (CCMSR) (offset = FFFF F600h)
31

17

15

16

Reserved

CPME

R-0

R/W1CP-0
10

Reserved

9

STC

8

7
Reserved

2

STET

STE

R-0

R-0

R-0

R-0

R-0

LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -n = value after reset

Table 8-4. CCM-R4 Status Register (CCMSR) Field Descriptions
Bit

Field

31-17

Reserved

16

CMPE

Value
0

Description
Reads return 0. Writes have no effect.
Compare Error
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: CPU signals are identical.
Write: Leaves the bit unchanged.

1

Read: CPU signal compare mismatch.
Write: Clears the bit.

15-9
8Reserved

0

STC

Reads return 0. Writes have no effect.
Self-test Complete
Note: This bit is always 0 when not in self-test mode. Once set, switching from self-test mode toother modes will clear this bit.
Read/Write in User and Privileged mode.

0

Read: Self-test on-going if self-test mode is entered.
Write: Writes have no effect.

1

Read: Self-test is complete.
Write: Writes have no effect.

7-2

Reserved

1

STET

0

Reads return 0. Writes have no effect.
Self-test Error Type
Read/Write in User and Privileged mode.

0

Read: Self-test failed during Compare Match Test if STE = 1.
Write: Writes have no effect.

1

Read: Self-test failed during Compare Mismatch Test if STE = 1.
Write: Writes have no effect.

0

STE

Self-test Error
Note: This bit gets updated when the self-test is complete or an error is detected.
Read/Write in User and Privileged mode.
0

Read: Self-test passed.
Write: Writes have no effect.

1

Read: Self-test failed.
Write: Writes have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

CPU Compare Module for Cortex™-R4 (CCM-R4)
Copyright © 2018, Texas Instruments Incorporated

289

CCM-R4 Control Registers

www.ti.com

8.4.2 CCM-R4 Key Register (CCMKEYR)
Figure 8-3. CCM-R4 Key Register (CCMKEYR) (offset = FFFF F604h)
31

16
Reserved
R-0

15

4

3

0

Reserved

MKEY

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privileged mode only; -n = value after reset

Table 8-5. CCM-R4 Key Register (CCMKEYR) Field Descriptions
Bit

Field

31-4

Reserved

3-0

MKEY

Value
0

Description
Reads return 0. Writes have no effect.
Mode Key
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: Returns current value of the MKEY.
Write: Lockstep mode.

6h

Read: Returns current value of the MKEY.
Write: Self-test mode.

9h

Read: Returns current value of the MKEY.
Write: Error Forcing mode.

Fh

Read: Returns current value of the MKEY.
Write: Self-test Error Forcing mode.
Note: It is recommended to not write any other key combinations. Invalid keys will result inswitching operation to lockstep mode.

290

CPU Compare Module for Cortex™-R4 (CCM-R4)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Chapter 9
SPNU517C – March 2018

Oscillator, PLL, and Clock Monitoring
This chapter describes the oscillator and PLL clock source paths for the device.
Topic

9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8

...........................................................................................................................

Page

Introduction ..................................................................................................... 292
Quick Start....................................................................................................... 293
Oscillator ......................................................................................................... 294
Low-Power Oscillator and Clock Detect (LPOCLKDET) ......................................... 296
PLL ................................................................................................................. 300
PLL Control Registers ....................................................................................... 309
Phase-Locked Loop Theory of Operation ............................................................ 313
Programming Example ...................................................................................... 315

SPNU517C – March 2018
Submit Documentation Feedback

Oscillator, PLL, and Clock Monitoring
Copyright © 2018, Texas Instruments Incorporated

291

Introduction

9.1

www.ti.com

Introduction
This chapter provides an overview of the oscillator and PLL clock source paths for the device.
The oscillator macro will pass a signal driven into the OSCIN pin to clock source 0 that is the device
default clock source on reset. When a crystal or resonator with appropriate load circuitry is connected to
OSCIN and OSCOUT, the oscillator macro drives the crystal/resonator to generate the input waveform. In
addition to being directly usable as clock source 0, the oscillator clock is the input to the PLL.
The oscillator frequency is continuously monitored by a dedicated clock detect circuit. If the frequency falls
out of a fixed range, the clock detect switches the clock from the oscillator to an internally generated, freerunning frequency (from the low power oscillator (LPO)).
The phase lock loop (PLL), a circuit in the microcontroller, is used to multiply the input frequency to somehigher (device operation) frequency. This frequency synthesis is useful for generating higher frequencies
than can be conveniently achieved with an external crystal or resonator. Additionally, the PLL allows theflexibility to be able to synthesize one of multiple frequency options from a given crystal or resonator.
Frequency modulation can be superimposed on the synthesized frequency. The modulation provides ameans to reduce the impact of electromagnetic radiation from the device; this reduction in measured
radiation can be useful in sensitive applications.

9.1.1 Features
The main features of the source clock path are:
• The oscillator may drive a crystal/resonator or be driven from an external source• The clock detect provides continuous monitoring of the oscillator frequency and provides an automatic
switch over to a free-running clock in case of oscillator failure.
• The FM-PLL module can be operated in either modulation or non-modulation mode.
• The phase-frequency detector assures lock to the fundamental reference frequency.
•

•

•

292

f PLL =

f O S C INNF´NROD ´ R(1)– Configurable prescale divider (NR) for the input clock– Configurable multiplier (NF)
– Configurable postscale dividers (OD, R)
The PLL may be used with modulation enabled.
– Configurable modulation frequency (NS)– Configurable modulation depth (NV)The slip control circuitry provides flexible response to a PLL failure (slip) including reset or automatic
switch over to oscillator.

Oscillator, PLL, and Clock Monitoring

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Quick Start

www.ti.com

9.2

Quick Start
The purpose of this section is to provide an overview of how to configure the oscillator and PLL clock
paths on power-up. More detailed descriptions are presented in later sections. Figure 9-1 shows theoscillator and PLL clock paths.
While power-on reset is asserted (low), the oscillator and low power oscillator (LPO) are enabled andstart-up by default. After power-on reset is released to a high level, the clock detect circuit (CLKDET)
begins to monitor the oscillator. If the oscillator is within a valid range, the oscillator becomes the default
clock for the device as it exits reset; if the oscillator is not within a valid range, the clock detect selects thehigh-frequency low power oscillator as the default clock for the device.
The low power oscillator has a wide frequency range which also creates a large valid window for the clock
detect; in order to refine the clock detect window, the low power oscillator can be trimmed. The initial trim
value is stored in one-time programmable section of the flash memory, address 0xF008_01B4. Bits 31:16
of this word contain a 16 bit value that may be programmed into LPOMONCTL(15:0) in order to initialize
the trim for both HF LPO and LF LPO. Software should read the initial trim values from flash and write
them to the control register.
The PLL is disabled by default on power-up. The PLL control registers (PLLCTL1 and PLLCTL2) must be
configured to set the desired output frequency. Then, the system PLL may be enabled (CLRCLKSR1OFF
bit in the Clock Source Disable Clear Register (CSDISCLR) of the System and Peripheral Control
Registers). The PLL has a valid bit that indicates the PLL is locked (CLKSR1V bit in the Clock Source
Valid Status Register (CSVSTAT) of the System and Peripheral Control Registers).
Prior to selecting the PLL clock as the source for a clock domain (for example, GCLK, HCLK, VCLKA1),
the domain and modules on the domain must be configured to accept the new frequency. An example of amodule that should be configured prior to selecting the PLL as clock source for GCLK and HCLK is thememory wrapper to insure that access times are maintained correctly.
Figure 9-1. Clock Path From Oscillator Through PLL To Device

load
capacitors

osc

OSCIN
CLKDET
OSCILLATOR

crystal

PLL1
slip

LPO
Clock source numbering can befound in the device data sheet.

OSCOUTKELVIN_GND

SPNU517C – March 2018
Submit Documentation Feedback

Oscillator, PLL, and Clock Monitoring
Copyright © 2018, Texas Instruments Incorporated

293

Oscillator

9.3

www.ti.com

Oscillator
The clock generation path through the PLL begins with the oscillator. The oscillator consists of three
separate pads -- OSCIN, OSCOUT, and KELVIN_GND (see Figure 9-2).
The oscillator is responsible for two independent functions:
1. The oscillator is responsible for generating positive feedback in the external crystal/resonator withappropriate load and tank circuitry. At start-up, the oscillator amplifies random noise. The external
circuitry acts like a band-pass and selects the crystal/resonator frequency to provide as positive
feedback into the amplifier. The positive feedback increases the amplitude of the output waveform into
the crystal/resonator (and the load circuitry), and the voltage waveform shows an envelope ofincreasing amplitude. The oscillator can drive a crystal frequency that is within the data sheet rangetc(OSC).
Looking at the input waveform into OSCIN, the voltage waveform is an AC-coupled, filtered version of
the OSCOUT waveform. The band-pass functionality of the crystal/resonator removes distortion fromthe OSCOUT waveform, leaving a sinusoidal input waveform.
NOTE: Vendor Validation of Resonators/Crystals
The crystal is a very tight bandpass filter while a resonator is a somewhat wider bandpass.
The load circuitry pulls the center frequency of the bandpass.
Texas Instruments strongly encourages each customer to submit samples of the device tothe resonator/crystal vendor for validation. The vendor is equipped to determine what load
capacitances will best tune their resonator/crystal to the microcontroller device for optimum
start-up and operation over temperature and voltage extremes. The vendor also factors inmargins for variations in the microcontroller process.

2. The oscillator is also responsible for squaring-up the input waveform. This squaring-up converts thesinusoid into a square wave at the core logic levels. The input path limits the input frequency range asa low-pass filter with a cutoff frequency.
The oscillator has a frequency range that is determined by the driving capability of external
crystals/resonators (feedback path). If a clock is driven directly into the oscillator, then the feedback
path is not relevant and the frequency range is determined solely by the forward path (that typicallyallows a higher frequency); the device can support inputs within the data sheet range tc(OSC_Sqr).
Figure 9-2. Clock Generation Pathload
capacitors
OSCIN
OSCILLATOR

crystalOSCOUTKELVIN_GND

294

Oscillator, PLL, and Clock Monitoring

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Oscillator

www.ti.com

9.3.1 Oscillator Implementation
The oscillator operates at 3.3V and uses a constant current source to drive current onto the OSCOUT
node (see Figure 9-3). An internal transistor shunts the current (and current from the external circuitry) to
GND. This current steering drives the voltage waveform on OSCOUT.
Figure 9-3. Oscillator ImplementationR

OSCOUT

OSCIN

9.3.2 Oscillator Enable
The oscillator is enabled asynchronously when nPORRST is low.
The oscillator is enabled by clearing bit 0 in the Clock Source Disable Register (CSDIS) or setting bit 0 in
the Clock Source Disable Clear Register (CSDISCLR) of the System and Peripheral Control Registers.
The bit sends a start signal to the oscillator. Bit 0 of CSDIS is cleared to 0 by default on a system or
power-on reset so that the oscillator starts-up by default. After the oscillator swings at a high-enoughamplitude to pass an input clock into the core domain and nPORRST is released, 1024 oscillator periods
are counted before setting the CLKSR0V bit in the Clock Source Valid Status Register (CSVSTAT) of the
System and Peripheral Control Registers. The oscillator generates clock source 0 in the global clock
module (GCM).

9.3.3 Oscillator Disable
The clock sources (for example, OSC, PLL) are disabled by setting the appropriate bit in the Clock Source
Disable Register (CSDIS) or setting the appropriate bit in the Clock Source Disable Set Register(CSDISSET) of the System and Peripheral Control Registers. These bits allow the clock source to disable
but do not force the behavior until the clock is no longer used as the source for a clock domain (forexample, GCLK, VCLK, VCLK2, RTICLK). The CLKSR0V bit in the Clock Source Valid Status Register(CSVSTAT), of the System and Peripheral Control Registers, is cleared after clock disable is asserted(which occurs after all clock domains are stopped).
The oscillator disable signal places the oscillator into a low power state, disconnects the feedback (bias)
resistor between OSCIN and OSCOUT, and OSCIN is grounded.

SPNU517C – March 2018
Submit Documentation Feedback

Oscillator, PLL, and Clock Monitoring
Copyright © 2018, Texas Instruments Incorporated

295

Low-Power Oscillator and Clock Detect (LPOCLKDET)

9.4

www.ti.com

Low-Power Oscillator and Clock Detect (LPOCLKDET)
The Low-Power Oscillator (LPO) is comprised of two oscillators -- HF LPO and LF LPO -- in a single
macro. The low-power oscillator and clock detect (LPOCLKDET) uses a relaxation oscillator to generate
an internal clock whose frequency is NOT tightly controlled. This frequency is used to monitor theoscillator input frequency and is also available as an independent clock source in the GCM.
The LPO produces two frequencies:• High-frequency low-power oscillator (HF LPO) with a nominal frequency of 9.6MHz; the HF LPO
generates clock source 5 in the GCM. Refer to the device datasheet for range values.
• Low-frequency low-power oscillator (LF LPO) with a nominal frequency of 85KHz; the LF LPO
generates clock source 4 in the GCM. Refer to the device datasheet for range values.
A single current source drives current onto a capacitor; when the voltage on the capacitor exceeds somethreshold, the clock toggles. The LPO uses a single current source and the two different comparators togenerate the HF LPO and LF LPO frequencies. The LPO is controlled by 4 different bit fields -CSDIS(5:4), HFTRIM, LFTRIM, and BIASEN.
• CSDIS.5 enables/disables the comparator that generates HF LPO.
• CSDIS.4 enables/disables the comparator that generates LF LPO.
• The HFTRIM and LFTRIM bit fields vary the current into the comparator to independently trim the HF
LPO and LF LPO frequencies (see Section 2.5.1.31).
• BIAS ENABLE enables/disables the current source that drives the LPO.

9.4.1 Clock Detect
The LPO HF clock frequency is typically near 9.6MHz. Refer to the device datasheet for range values. The
clock detect establishes a window for the oscillator by:
OSCIN > HF LPOmin / 4

OSCIN / 4 < HF LPOmax

OSCIN > 5.5[MHz] / 4 = 1.375[MHz]OSCIN < 4 × 19.5 = 78[MHz]The clock detect circuit works by checking for a rising edge on one clock (oscillator or HF LPO) between
rising edges of the other clock. The result is that in addition to flagging incorrect, repeating frequencies,
the circuit also fails due to transient conditions.
NOTE: Clock Detection of Oscillator MUST be Disabled Before Disabling HF LPO
The HF LPO frequency is the comparison frequency for the oscillator. The clock detection
must be disabled prior to disabling the HF LPO frequency.
If the clock detection is NOT disabled prior to disabling the HF LPO, the clock detect circuitry
will fail the oscillator as too fast (compared to the non-existent HF LPO). The clock detectcircuitry will switch to the non-existent clock, leaving the device without a valid clock.

296

Oscillator, PLL, and Clock Monitoring

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Low-Power Oscillator and Clock Detect (LPOCLKDET)

www.ti.com

9.4.2 Behavior on Oscillator Failure
If the oscillator frequency fails, the clock detects supplies:• the HF LPO clock to GCM clock source 0 instead of the oscillator• the HF LPO clock to GCM clock source 1 instead of the PLL
The HF LPO signal will be available as three different clock sources:• GCM clock source 0 (replacing the oscillator)• GCM clock source 1 (replacing the PLL)
• GCM clock source 5 as HF LPO
The automatic switch-over from oscillator to HF LPO allows the application to execute at a reduced
frequency and respond to a problem with the external crystal/resonator. During and after an oscillator
failure, the oscillator CLKSRnV bit in the Clock Source Valid Status Register (CSVSTAT), of the System
and Peripheral Control Registers, is set along with the OSCFAIL flag in the Global Status Register(GLBSTAT), of the System and Peripheral Control Registers.
It is useful to explicitly change the GHVSRC register, defining the current clock source for
GCLK/HCLK/VCLK domains, to the HF LPO after an oscillator failure.
When reset on oscillator failure is set, PLLCTL1.23 (ROF), the device responds to an oscillator failure by
generating a device reset.

9.4.3 Recovery from Oscillator Failure
If the oscillator fails, the clock detect switches the HF LPO frequency onto the oscillator source into the
GCM. The OSCFAIL flag in the Global Status Register (GLBSTAT), of the System and Peripheral Control
Registers, is also set.
The oscillator may be re-enabled (though if the failure was caused by a hard-fault, the re-enable will fail)through the following procedure:
1. Switch all clock domains from the oscillator to the HF LPO (for example, GHVSRC uses HF LPO,VCLKA1 uses HF LPO or VCLK, and so on).
2. If the PLL is used, disable the PLL by setting the appropriate bit in the Clock Source Disable Set
Register (CSDISSET) of the System and Peripheral Control Registers.
3. Disable the oscillator by setting the appropriate bit in the Clock Source Disable Set Register(CSDISSET). This action resets the clock detect and allows the oscillator to propagate through GCM
clock source 0.
4. Re-enable the oscillator by setting the appropriate bit in the Clock Source Disable Clear Register(CSDISCLR) of the System and Peripheral Control Registers.
5. Clear the OSCFAIL flag in the Global Status Register (GLBSTAT) by writing a 1 to the bit. The PLL slip
bits may also be set on an oscillator failure. These can also be cleared.
6. Switch the clock domains back to the oscillator.
7. Re-enable the PLL by setting the appropriate bit in the Clock Source Disable Clear Register(CSDISCLR).
NOTE: Clock Re-Enable Procedure Will Fail If Caused by a Hard Failure
Although it is possible to re-enable the oscillator after a failure, if the oscillator failure wascaused by a hard fault (for example, disconnected crystal/resonator terminal), the re-enable
process will fail.

SPNU517C – March 2018
Submit Documentation Feedback

Oscillator, PLL, and Clock Monitoring
Copyright © 2018, Texas Instruments Incorporated297

Low-Power Oscillator and Clock Detect (LPOCLKDET)

www.ti.com

9.4.4 LPOCLKDET Enable
The LPO is enabled by default while nPORRST is low. During this time, the current source initializes,
holding the relaxation oscillator in reset until initialized. After the current source releases the HF LPO andthe LF LPO, these clock frequencies slew to their final frequencies; the final frequency may be achieved
while nPORRST is active or after its release. After, nPORRST is released, the HF LPO Valid signal is set
32 HF LPO clock cycles later.
The clock detect is enabled once the oscillator and HF LPO are valid. Because an oscillator failure could
occur from reset, the clock detect logic must provide an override path. If the HF LPO is valid and theoscillator is not valid, the clock detect circuitry will become active (overriding the oscillator invalid signal)
after 16K LF LPO cycles (about 200 ms).

298

Oscillator, PLL, and Clock Monitoring

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Low-Power Oscillator and Clock Detect (LPOCLKDET)

www.ti.com

9.4.5 LPOCLKDET Disable
9.4.5.1

Disable Clock Detect

It is possible to disable the clock detect circuitry. For protection, this clock detect disable employs a 2-bit
key:• RANGE DET ENA SSET (CLKTEST.24) must be set to 1
• RANGE DET CTRL (CLKTEST.25) must be cleared to 0
In this case, the LPO HF and LF clocks are still active but the clock detect circuitry is disabled. The clock
detect unconditionally switches GCM_CLK_SRC(0) back to the oscillator so care should be taken to
insure that the oscillator is good before disabling the clock detect circuitry.
9.4.5.2

Disable LPO HF and LF Clocks

The LPO may be disabled by holding the relaxation oscillator clocks (HF and LF) in reset. The clock
detect must be disabled, and any clock domains using either HF or LF clocks must be switched to adifferent clock source. The LPO HF clock is reset by setting CSDIS.5; CSDISSET.5 is an easy way to set
specific bits without disturbing the rest of the register. The HF LPO clock disables several HF LPO cycles
after CSDIS is set.
Similarly, the LPO LF clock is reset by setting CSDIS.4, and in a similar way CSDISSET.4 can set the
specific CSDIS register bit without using a read-modify-write construction. The LF LPO disables several
LF LPO cycles after CSDIS is set.
Restarting the LPO clocks from this condition is fast and is known as a warm re-start. The CSDISCLR
register allows the user to clear CSDIS bits without using a read-modify-write code-construct.
9.4.5.3

Disable LPO Current Bias

The LPO current source may be disabled after the clock detect is disabled and HF and LF clock sources
are disabled. Turning off this current source places the LPOCLKDET into its lowest power configuration.
The bias may be disabled by clearing the BIAS ENABLE bit.
Restarting the LPO when the bias current has been disabled requires the current source to initialize firstand is, therefore slower than a warm re-start; re-enabling the LPO from this condition is known as a warm
re-start (similar to what happens during nPORRST active).

9.4.6 Trimming the HF LPO Oscillator
The HF LPO range varies considerably around 9.6MHz from device to device. In order to provide tightermonitoring of the crystal/resonator, it is useful to trim the oscillator. During device test, a trim value iswritten into the one-time programmable section of the flash memory (OTP), address 0xF008_01B4. Bits
31:16 of this OTP word contain a 16-bit value that may be programmed into LPOMONCTL[15:0] in order
to initialize the trim for both HF LPO and LF LPO.
When trimming the HF LPO, it is recommended to step the trim value so as not to make a large change to
any TRIM setting.
After the initial trim, further trimming may be done in LPOMONCTL, using the dual clock compare module(see Chapter 10) in order to determine the resultant frequency. This module allows for comparison of twoclock frequencies. Once the HF LPO is determined to be in-range with the initial HFTRIM setting from theOTP, the crystal oscillator may be used as a reference against which the HF LPO and LF LPO may befurther adjusted.

SPNU517C – March 2018
Submit Documentation Feedback

Oscillator, PLL, and Clock Monitoring
Copyright © 2018, Texas Instruments Incorporated

299

PLL

9.5

www.ti.com

PLL
The following bit fields from PLLCTL1 and PLLCTL2 configure the PLL:
• REFCLKDIV[5:0]• PLLMUL[15:0]• ODPLL[2:0]• PLLDIV[4:0]• SPR_AMOUNT[8:0]• SPREADINGRATE[8:0]• FMENA
The PLL is responsible for synthesizing an output frequency from the input clock (from the oscillator);
Figure 9-4 shows a simple block diagram of the PLL. The FM-PLL divides the reference input for a lower
frequency input into the PLL (fINTCLK = fCLKIN/NR). The PLL multiplies this internal frequency by NF to get the
VCO output clock frequency (fOutput CLK = fINTCLK× NF). The PLL output is subsequently divided by twoprescale values (OD and R). The value of OD is an integer from 1-8 and R is an integer from 1–32. This
output clock, PLL CLK, sources GCM clock source 1. Valid frequencies are shown in Table 9-1 while
Table 9-2 shows how that encoding is generated from the PLL bit fields.
[f(post_ODCLK) and f(GCLK) are data sheet parameters.]
Figure 9-4. Operation of the FM-PLL Module
CLKIN

÷NR

Output CLKINTCLK÷1 - ÷64

PLL÷OD

post-ODCLK

÷1 - ÷8÷R

PLL CLK÷1 - ÷32÷NF÷1 - ÷256

f CLKIN
1
1
f PLLCLK = ----------------- x NF x --------- x ---OD R
NR

Table 9-1. Valid Frequency Ranges for PLL
Frequency Limit
fCLKINf(OSC_Sqr)

fINTCLK

1MHz - f(OSC_Sqr)

fOutput CLK

150MHz - 550MHz

fpost-ODCLK

f(post_ODCLK)

fPLL CLKf(GCLK)

300 Oscillator, PLL, and Clock Monitoring

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

PLL

www.ti.com

Table 9-2. PLL Value Encoding
PLL
NR

NR = REFCLKDIV [5...0] + 1(2)

Non-modulated:NF =( P L L M U L [1 5 . . . 0 ] + 2 5 6 )
256

(3)

Modulated:

NF

NV

NF =

( P L L M U L [1 5 ... 0 ] + M U L M O D [ 8 ... 0 ] + 2 5 6 )
256

(4)

NV =

( S P R _ A M O U N T [ 8 ... 0 ] + 1)
2048

(5)

NS

NS = SPRRATE [8...0] + 1

(6)

OD

OD = ODPLL[2...0] + 1(7)

NOTE: ODPLL change should occur prior to enabling asynchronous clock domains
Since changing the ODPLL bit-field causes the PLL CLK to be gated, these changes to
ODPLL should be completed before configuring a clock domain for an asynchronous clock
source. Some clock domains (RTICLK, VCLK2) require a frequency relationship to the
VCLK.

fVCLK ³ 3 ´

f RTISRCRTIDIV

If the PLL is clocking VCLK and it is stopped for some cycles, then the frequency relationshipis temporarily violated.
Many asynchronous domains require frequency relationships between VCLK and theasynchronous domain. Therefore, if the PLL clock is the source for GCLK, HCLK and VCLK,
then the gating produces a short-term change in the PLL clock frequency (and hence, also
the VCLK frequency). As such, this frequency change could violate the requirements for an
asynchronous clock domain.

SPNU517C – March 2018
Submit Documentation Feedback

Oscillator, PLL, and Clock Monitoring
Copyright © 2018, Texas Instruments Incorporated

301

PLL

www.ti.com

9.5.1 Modulation
Optionally, the frequency can be modulated, that is, a controlled jitter is introduced onto the baselinefrequency of the PLL. This modulation mechanism is not shown in Figure 9-4. When the PLL is used in
the modulating mode, the programmable modulation block varies the PLL frequency from the baselinefrequency (fbaseline = (fCLKIN/NR) × NF/(OD × R)) to fbaseline × (1 - 2 × Depth) in a period defined by 1/fs; themodulation waveform is triangular and should be enabled after lock.
Modulation Period (1/fs)

f0 - n%Depth

Modulation

Frequency (MHz)f0

f0-2n%
Time (Ps)

The modulation is digital and the spreading profile is triangular, down-spread which implies:• the modulation waveform is composed of a series of frequency steps.
• the modulation frequency and modulation depth are both well controlled due to their digital character.
• the average frequency during modulation is lower than the average frequency prior to enabling
modulation. The depth of modulation, however, sets the new average frequency.
• the modulation frequency must be selected slower than the loop bandwidth. From a practicalperspective, NS should be near 20.
The modulation fields have a simple geometric meaning:• the modulation step size is:NV´ f O u tp u tC L K
NF••

the number of steps per modulation period is 2 × NS
the modulation depth is given by:

Df =

NS
NV
´
´ f O u tp u tC L K
2NF

D e p th [% ] =
•

N S
N V
´
2
N F

(9)

the modulation frequency is:

Tmod =
•

(8)

f OSC
2 ´ NR ´ NS

(10)MULMOD minimizes frequency offset when programmed as:( S P R _ A M O U N T [ 8 ... 0 ] + 1)( S P R R AT E [ 8 ... 0 ] + 1)
16

(11)

NOTE: Modulation should be enabled after Lock
Enable modulation after the lock is completed.

302

Oscillator, PLL, and Clock Monitoring

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

PLL

www.ti.com

9.5.2 PLL Output Control
The outputs from the PLL are the output clock, slip signals, and VALID.
• RFSLIP -- the RFSLIP signal indicates that the Output CLK is running too fast relative to INTCLK andsets a RFSLIP status flag in the Global Status Register (GLBSTAT) register, of the System andPeripheral Control Registers, if the slip signal is active during normal PLL operation; the RFSLIP flag ismasked off while the PLL is not active and during the PLL’s lock period.
• FBSLIP -- the FBSLIP signal indicates that the Output CLK is running too slow relative to INTCLK andsets a FBSLIP status flag in the Global Status Register (GLBSTAT) register, of the System andPeripheral Control Registers, if the slip signal is active during normal PLL operation; the FBSLIP flag ismasked off while the PLL is not active and during the PLL’s lock period.
• PLL Slip -- Logical-OR of the two PLL slip signals. Typically this signal is used to generate aconsolidated slip signal to the device (for example, error logic or exception generation). Also used togate VALID.
NOTE: Clearing Slip Bits
In order to clear any of the slip bits, it is necessary to disable the PLL first.

••

9.5.2.1

VALID -- is driven based upon whether the output clock, PLL CLK, is gated or not. However, the
VALID signal is dependent upon the PLL Slip signals so that VALID cannot be set if either slip signal isactive.
PLL Clock -- The PLL output clock runs at the programmed frequency. When enabled, it takes sometime to acquire the programmed frequency (see Section 9.5.2.1). Similarly, the disable has sometiming/constraints (see Section 9.5.2.2).
PLL Enable

After setting the PLL control registers, the clock source is enabled by clearing the appropriate bit in the
Clock Source Disable Register (CSDIS) or setting the appropriate bit in the Clock Source Disable Clear
Register (CSDISCLR) of the System and Peripheral Control Registers. The bit sends a signal to the PLLthat starts the process of enabling the PLL.
1. The PLL checks to make sure that the oscillator is ON. If not, it turns the oscillator ON.
2. The PLL begins a locking process in which the PLL slews from a starting frequency point to theprogrammed frequency. During this lock period, the PLL slip signals are typically active, and the PLL
masks off the signals during this phase. The lock phase takes the following length of time:
Parameter
Lock
Enable clocks after lock

Value
TLock = (512 × TOSCIN) + (1024 × NR × TOSCIN)
TEnable = 6 × TOSCIN

3. After the lock phase is complete (when lock counters expire), the PLL releases the slip signals to thesystem.
4. Then, after the slip signals are released and a delay to enable the clocks, the clock is released to thesystem and the appropriate CLKSRnV bit for the PLL is set in the Clock Source Valid Status Register(CSVSTAT) of the System and Peripheral Control Registers.

SPNU517C – March 2018
Submit Documentation Feedback

Oscillator, PLL, and Clock Monitoring
Copyright © 2018, Texas Instruments Incorporated

303

PLL

www.ti.com

9.5.2.2

PLL Disable

The clock sources (for example, OSC, PLL) are disabled by setting the appropriate bit in the Clock Source
Disable Register (CSDIS) or setting the appropriate bit in the Clock Source Disable Set Register(CSDISSET) of the System and Peripheral Control Registers. These bits allow the clock to disable but do
not force the behavior until the clock is no longer used as the source for a clock domain (for example,
GCLK, VCLK, VCLK2, RTICLK).
The PLL receives a signal to disable after the clock is no longer used by any clock domain. Within the
PLL, the clock is disabled and the appropriate CLKSRnV bit for the PLL in the Clock Source Valid Status
Register (CSVSTAT), of the System and Peripheral Control Registers, becomes inactive. Then the PLL isplaced into a low power state after the following length of time: TEnable = 150 × TOSCIN
9.5.2.3

OD-divider Change

The PLL gates the clock if the ODPLL bit-field is changed while the PLL is active. The output clock fromthe PLL is gated for 3 or 12 OSCIN clock cycles. As the post-ODCLK is gated in the low phase, the output
clock to the device -- PLL CLK -- may be gated in a high or low phase though the transition is always
glitchless: TODPLL = 3 × TOSCINNOTE: ODPLL change should occur prior to enabling asynchronous clock domains
Since changing the ODPLL bit-field causes the PLL CLK to be gated, these changes to
ODPLL should be completed before configuring a clock domain for an asynchronous clock
source. Some clock domains (RTICLK, VCLK2) require a frequency relationship to the
VCLK.

fVCLK ³ 3 ´

f RTISRCRTIDIV

If the PLL is clocking VCLK and it is stopped for some cycles, then the frequency relationshipis temporarily violated.
Many asynchronous domains require frequency relationships between VCLK and theasynchronous domain. Therefore, if the PLL clock is the source for GCLK, HCLK and VCLK,
then the gating produces a short-term change in the PLL clock frequency (and hence, also
the VCLK frequency). As such, this frequency change could violate the requirements for an
asynchronous clock domain.

9.5.2.4

Changing the PLL Operating Point While the PLL is Active

Once the valid bit (CLKSRnV bit in the Clock Source Valid Status Register (CSVSTAT) of the System andPeripheral Control Registers) is set, software may change values to the PLL. If the change of values
results in a small percentage change to the VCO frequency (∆fOutputCLK < 0.1 × fOutputCLK), then thesechanges can be done on-the-fly. In this mode, the values are updated into the PLL synchronously, and the
PLL re-locks to the new value without gating the clocks or the slip bits. If the operating point change is toolarge, then the slip bits will be set.
Conversely, if the changes to the VCO frequency are large, then the PLL should be disabled prior tochanging the values. Typically, any change to the REFCLKDIV field or large changes to the PLLMUL fieldin the PLL Control Register 1 (PLLCTL1) of the System and Peripheral Control Registers requires acomplete disable-and-relock strategy.

304

Oscillator, PLL, and Clock Monitoring

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

PLL

www.ti.com

9.5.2.5

Summary of PLL Timings

In addition to controlling the lock period and disabling the clock during an ODPLL change, the PLL also
generates reset delays. When power-on reset is released (nPORRST 0 --> 1), that release is delayed by1024 OSCIN cycles so that it is released at the same time that the oscillator valid is asserted. The system
reset release is delayed by an additional 8 oscillator clock cycles.
Table 9-3. Summary of PLL Timings
ParameternPORRST delay

Value
TnPORRST = 1024 x TOSCIN

nRST delay

TnRST = 1032 x TOSCIN

OSC valid

TOSCVALID = 1024 x TOSCIN

Lock

TLock = (512 x TOSCIN) + (1024 x NR x TOSCIN)

Enable clocks after lock

TEnable = 6 x TOSCIN

Disable clocks after lock

TEnable = 150 x TOSCIN

Change ODPLLTODPLL = 3 x TOSCINSPNU517C – March 2018
Submit Documentation Feedback

Oscillator, PLL, and Clock Monitoring
Copyright © 2018, Texas Instruments Incorporated

305

PLL

www.ti.com

9.5.3 Behavior on PLL Fail
The PLL allows flexible response to a PLL failure (slip). Like the oscillator, the PLL clock is configured bydefault to automatically switch-over to the oscillator in case of a PLL slip. (In this case, the oscillator
sources GCM clock source 1 as well as GCM clock source 0. Also, if the oscillator fails, LPO HF issourced to both GCM clock sources 0 and 1.)
A slip after the PLL has locked and while it is active is an indication of a PLL failure. The PLL provides
slip-filtering which enhances the flexibility of the PLL’s response to failure. The slip-filtering circuit samples
the slip based on HF LPO. The filter defines the number of consecutive HF LPO cycles for which the slip
signal must be active before the slip is recognized. This slip is latched in the RFSLIP and FBSLIP status
flags in the Global Status Register (GLBSTAT) register of the System and Peripheral Control Registers.
The PLL may enable/disable the automatic switch over as well as the error signaling; if the error signalingis enabled, a PLL slip may be configured to generate a reset. The automatic switch-over and suppressionof the error signals are controlled by the bypass on slip bit field -- BPOS[1:0] (PLLCTL1.(30:29)). When
BPOS[1:0] is disabled (BPOS[1:0] = 10b):• automatic response to the PLL slip is prevented• ESM/exception is NOT generated• reset on slip is not generated regardless of the state of the ROS bit• status bits are set on a PLL slip independent of BPOS[1:0]
When BPOS[1:0] is enabled (BPOS[1:0] = 00b OR 01b OR 11b):• PLL slip causes the clock source into GCM clock source 1 to shift from the PLL to the oscillator• ESM/exception is generated• reset on slip is generated if ROS is set
The effect of BPOS[1:0] on the system is shown in Figure 9-5.
Figure 9-5. PLL Slip Detection and Reset/Bypass Block Diagram

PLL Bypass CLK
Input from
Oscillator

CLK signal to
Clock Control Module

PLL CLKFMzPLL
Bypass on Slip
BPOS
Slip Detector
BPOS

306

ROS
Reset on Slip

Oscillator, PLL, and Clock Monitoring

To Device ResetSPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

PLL

www.ti.com

9.5.4 Recovery from a PLL Failure
If the PLL fails, the PLL slip causes the valid flag to be locked and causes the clock source into GCM
clock source 1 to shift from the PLL to the oscillator. This slip is latched in the RFSLIP and FBSLIP status
flags in the Global Status Register (GLBSTAT) register of the System and Peripheral Control Registers.
The PLL may be re-enabled (though if the failure was caused by a hard-fault, the re-enable will fail)through the following procedure:
1. Switch all clock domains from the PLL to the oscillator (for example, GHVSRC uses oscillator, VCLKA1
uses oscillator or VCLK, and so on).
2. Disable the PLL by setting the appropriate bit in the Clock Source Disable Set Register (CSDISSET) of
the System and Peripheral Control Registers. This action disables the PLL and causes the slip signal
to no longer be driven. VALID is not released until the slip is cleared.
3. Clear the RFSLIP or FBSLIP flags in the Global Status Register (GLBSTAT) register, of the System
and Peripheral Control Registers, by writing a 1 to the bits. After this step, the valid flag is unlocked
and cleared if it was previously set.
4. Re-enable the PLL by setting the appropriate bit in the Clock Source Disable Clear Register(CSDISCLR) of the System and Peripheral Control Registers.
5. Switch the clock domains back to the PLL.

9.5.5 PLL Modulation Depth Measurement
The PLL contains a circuit for estimating the depth of the modulation. The circuit counts clock edges overa fixed window of the modulation waveform (SSW_CAPTURE_COUNT in SSWPLL2) and clock edges
over the entire waveform (SSW_CLKOUT_COUNT in SSWPLL3). The capture ends after a predetermined number of clock edges in SSW_CLKOUT_COUNTER as set in TAP_COUNTER_DIS. Thereare 2 × NR windows per modulation waveform. The procedure for estimating the modulation depth is:
1. While GCLK is sourced by the oscillator and the PLL is enabled with modulation, configure SSWPLL1
as follows:a. CAPTURE_WINDOW_INDEX is set equal to NR.
b. COUNTER_RESET is set.
c. TAP_COUNTER_DIS is set to disable the measurement after SSW_CLKOUT_COUNT captures
this number of clocks. The measurement is disabled after the set tap is set AND the modulation
cycle ends.
d. Ensure that EXT_COUNTER_EN is cleared.
2. Ensure that both SSW_CAPTURE_COUNT and SSW_CLKOUT_COUNT are cleared (by the
COUNTER_RESET).
3. Set COUNTER_EN and clear COUNTER_RESET. This step releases the reset and enables thecounter to begin counting.
4. After a wait loop, poll for COUNTER_READ_READY to set. After the bit is set, read
SSW_CAPTURE_COUNT and SSW_CLKOUT_COUNT.
5. Compute the modulation depth as:æ 2 ´ NR ´ SSW _ CAPTURE _ COUNT ö÷÷
Depth = absçç1 SSW _ CLKOUT _ COUNTèøSPNU517C – March 2018
Submit Documentation Feedback(12)

Oscillator, PLL, and Clock Monitoring
Copyright © 2018, Texas Instruments Incorporated

307

PLL

www.ti.com

9.5.6 PLL Frequency Measurement Circuit
The same circuit that is used to measure modulation depth is also available to measure the averagefrequency of the PLL. In this mode, the PLL output (before the R-divider) is captured in
SSW_CLKOUT_COUNT while the oscillator is captured in SSW_CAPTURE_COUNT. The procedure forusing the PLL frequency measurement circuit is:
1. While the PLL is enabled, set EXT_COUNTER_EN.
2. Set COUNTER_EN. This bit clears both SSW_CAPTURE_COUNT and SSW_CLKOUT_COUNT andthen immediately enables for counting.
3. Wait for some software delay loop.
4. Clear COUNTER_EN. Wait for COUNTER_READ_READY to set. Read both
SSW_CAPTURE_COUNT and SSW_CLKOUT_COUNT and compute the ratio of PLL multiplication
as:

NF
SSW _ C LK O U T _ C O U N T=
NR ´ OD
SSW _ C APTU RE _ C O U N T(13)

5. Note that CAPTURE_WINDOW_INDEX, COUNTER_RESET, TAP_COUNTER_DIS are not used inthis procedure

308

Oscillator, PLL, and Clock Monitoring

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

PLL Control Registers

www.ti.com

9.6

PLL Control Registers
The clock module has two control registers (PLLCTL1 and PLLCTL2) located within the System andPeripheral Control Registers, plus it has four bits located in other System and Peripheral Control
Registers.
The FM-PLL is off at power-on. The clock source is enabled by clearing the appropriate bit in the ClockSource Disable Register (CSDIS) or setting the appropriate bit in the Clock Source Disable Clear Register(CSDISCLR) of the System and Peripheral Control Registers. [CSDISCLR and Clock Source Disable Set
Register (CSDISSET) also enable/disable the PLL and oscillator (and other clock sources).]
The LPOCLKDET module generates the OSCFAIL flag in the Global Status Register (GLBSTAT), of the
System and Peripheral Control Registers, if a problem with the reference oscillator is detected. The slip
signals are also registered in the RFSLIP and FBSLIP status flags in the Global Status Register(GLBSTAT) register, of the System and Peripheral Control Registers, in order to indicate the source of aclock failure.
The appropriate CLKSRnV bit for the PLL is set in the Clock Source Valid Status Register (CSVSTAT) of
the System and Peripheral Control Registers.
The following sections describe the PLL registers used in the system module. These registers support 8-,16-, and 32-bit write accesses. The reset values for these registers are configured so that an input
frequency in the range from 5MHz to 20MHz generates a valid clock.
Table 9-4. PLL Module Registers
Address

Acronym

Register Description

FFFF FF30h

CSDIS

Clock Source Disable Register

Section 2.5.1.10

SectionFFFF FF34h

CSDISSET

Clock Source Disable Set Register

Section 2.5.1.11

FFFF FF38h

CSDISCLR

Clock Source Disable Clear Register

Section 2.5.1.12

FFFF FF54h

CSVSTATClock Source Valid Status Register

Section 2.5.1.19

FFFF FF70h

PLLCTL1

PLL Control 1 Register

Section 2.5.1.26

FFFF FF74h

PLLCTL2

PLL Control 2 Register

Section 2.5.1.27

FFFF FFA0h

GPREG1

General Purpose Register

Section 2.5.1.35

FFFF FFECh

GLBSTAT

Global Status Register

Section 2.5.1.51

FFFF E170h

CLKSLIPClock Slip Register

Section 2.5.2.2

FFFF FF24h

SSWPLL1

PLL Modulation Depth Measurement Control Register

Section 9.6.1

FFFF FF28h

SSWPLL2

SSW PLL BIST Control Register 2

Section 9.6.2

FFFF FF2ChSSWPLL3

SSW PLL BIST Control Register 3

Section 9.6.3

Table 9-5. LPOCLKDET Module Registers
Address

Acronym

Register Description

FFFF FF88h

LPOMONCTL

LPO/Clock Monitor Control Register

Section 2.5.1.31

FFFF FF8Ch

CLKTEST

Clock Test Register

Section 2.5.1.32

SPNU517C – March 2018
Submit Documentation Feedback

Section

Oscillator, PLL, and Clock Monitoring
Copyright © 2018, Texas Instruments Incorporated309

PLL Control Registers

www.ti.com

9.6.1 PLL Modulation Depth Measurement Control Register (SSWPLL1)
Figure 9-6 illustrates this register and Table 9-6 provides the bit descriptions.
Figure 9-6. SSW PLL BIST Control Register 1 (SSWPLL1) (offset = 24h)31

16
Reserved
R-0
15

8
CAPTURE_WINDOW_INDEX
R/W-0

7

6

5

4

Reserved

COUNTER_
READ_ READY

COUNTER_RESETCOUNTER_EN3
TAP_COUNTER_DIS

1

EXT_COUNTER_
EN

0

R-0

R-0

R/W-1

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-6. SSW PLL BIST Control Register 1 (SSWPLL1) Field Descriptions
Bit

Field

31-16

Reserved

15-8

CAPTURE_WINDOW_INDEX

7

Reserved

6

COUNTER_READ_READY

Value
0
0-FFh

0

Description
Reads return 0. Writes have no effect.
The capture counter present in the PLL wrapper will count the PLL clock edges when
the current modulation phase capture window value is equal to these bits. Should be
set equal to NR.
Reads return 0. Writes have no effect.
Counter read ready.
Indicates that SSW_CAPTURE_COUNT (SSWPLL2) and SSW_CLKOUT_COUNT(SSWPLL3) can be read.

50Counter registers in SSWPLL2 and SSWPLL3 are not ready to read.

1

Counter registers in SSWPLL2 and SSWPLL3 are ready to read.

COUNTER_RESETCounter reset.
If EXT_COUNTER_EN = 0, COUNTER_RESET resets SSW_CAPTURE_COUNT(SSWPLL2) and SSW_CLKOUT_COUNT (SSWPLL3).
If EXT_COUNTER_EN = 1, this bit is ignored.
0

No impact to counters.

1

If EXT_COUNTER_EN = 0, then counters SSW_CAPTURE_COUNT and
SSW_CLKOUT_COUNT will be held in the reset state.
If EXT_COUNTER_EN = 1, this bit is ignored by the PLL wrapper.

4

COUNTER_EN

Counter enable.
If EXT_COUNTER_EN = 0, COUNTER_EN initializes the modulation depth
measurement. (In this mode, the disable is set to occur automatically.)
If EXT_COUNTER_EN = 1, the counters are enabled/disabled with COUNTER_EN.
0

If EXT_COUNTER_EN = 0, COUNTER_EN = 0 indicates that the counters areinactive.
If EXT_COUNTER_EN = 1, COUNTER_EN = 0 disables the counters.

1

If EXT_COUNTER_EN = 0, COUNTER_EN = 0 indicates that the counters are still
active.
If EXT_COUNTER_EN = 1, COUNTER_EN = 0 enables the counters.

310

Oscillator, PLL, and Clock Monitoring

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

PLL Control Registers

www.ti.com

Table 9-6. SSW PLL BIST Control Register 1 (SSWPLL1) Field Descriptions (continued)
Bit

Field

3-1

TAP_COUNTER_DIS

0

Value

Description
The value in this register is used to program a particular bit in CLKOUT counter.
When that particular bit in CLKOUT counter becomes 1, then both the CLKOUT
counter and the CAPTURE counter will stop counting when EXT_COUNTER_EN = 0.
When EXT_COUNTER_EN = 1, this bit field is not used.

0

Bit 16 of CLKOUT counter is selected. When this bit is set and the modulation period
finishes, the counters are disabled and READ_READY_FLAG is set.

1h

Bit 18 of CLKOUT counter is selected.

2h

Bit 20 of CLKOUT counter is selected.

3h

Bit 22 of CLKOUT counter is selected.

4h

Bit 24 of CLKOUT counter is selected.

5h

Bit 26 of CLKOUT counter is selected.

6h

Bit 28 of CLKOUT counter is selected.

7h

Bit 30 of CLKOUT counter is selected.

EXT_COUNTER_EN

Measurement mode.
0

Modulation Depth Measurement mode.

1

Frequency Measurement mode.

9.6.2 SSW PLL BIST Control Register 2 (SSWPLL2)This is an observation register used to log counter value for the capture counter inside the PLL wrapper.
The SSWPLL2 register is shown in Figure 9-7 and described in Table 9-7.
Figure 9-7. SSW PLL BIST Control Register 2 (SSWPLL2) (offset = 28h)310
SSW_CAPTURE_COUNT
R-0

LEGEND: R = Read only; -n = value after reset

Table 9-7. SSW PLL BIST Control Register 2 (SSWPLL2) Field Descriptions
Bit

Field

Description

31-0

SSW_CAPTURE_COUNT

Capture count. This register returns the value of the capture count.
When EXT_COUNTER_EN = 0, this counter increments within a fixed modulation window.
When EXT_COUNTER_EN = 1, this counter increments based upon the oscillator.

SPNU517C – March 2018
Submit Documentation Feedback

Oscillator, PLL, and Clock Monitoring
Copyright © 2018, Texas Instruments Incorporated

311

PLL Control Registers

www.ti.com

9.6.3 SSW PLL BIST Control Register 3 (SSWPLL3)
This is observation register used to log counter value for CLKOUT counter inside PLL wrapper. The
SSWPLL3 register is shown in Figure 9-8 and described in Table 9-8.
Figure 9-8. SSW PLL BIST Control Register 3 (SSWPLL3) (offset = 2Ch)
310
SSW_CLKOUT_COUNT
R-0

LEGEND: R = Read only; -n = value after reset

Table 9-8. SSW PLL BIST Control Register 3 (SSWPLL3) Field Descriptions
Bit

Field

Description

31-0

SSW_CLKOUT_COUNT

Value of CLKout count register. This counter increments based upon the PLL output (prior to theR-divider).

312

Oscillator, PLL, and Clock Monitoring

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Phase-Locked Loop Theory of Operation

www.ti.com

9.7

Phase-Locked Loop Theory of Operation
The PLL block consists of six logical sub-blocks:• Phase-Frequency Detector (PFD)• Charge Pump (CP)• Loop Filter (LF)
• Voltage-Controlled Oscillator (VCO)• Frequency Modulation• Slip Detector
Figure 9-9 illustrates the sub-blocks in a basic PLL circuit. The VCO adjusts its frequency until the two
signals into the PFD have the same phase and frequency. The feedback path (from VCO to PFD) divides
the frequency of the feedback signal by 2 × NF; this feedback divider requires the VCO to generate afrequency 2 × NF times greater than the internal frequency (OSCIN/NR). In the forward path (from VCO to
PLL CLK), the /2 block creates a clean duty cycle.
Figure 9-9. Basic PLL Circuit
Output CLKINTCLK
CLKIN

÷NR

PFD

CP

LF

÷2

÷NF

VCO

post-ODCLK

÷OD

÷2

÷R

PLL CLK

Feedback
CLK

9.7.1 Phase-Frequency Detector
The phase-frequency detector (PFD) compares the input reference phase/frequency to thephase/frequency of the feedback divider and generates two signals: an up pulse and a down pulse thatdrive a charge pump. The resulting charge, when integrated by the circuit at the LF pin, provides a VCO
control voltage, as shown in Figure 9-10.
Figure 9-10. PFD Timing
Input
reference
Feedback
divider output
Leading phase

Lagging phase

Up

Down

VCO control

Interpulse slope caused by filter time constant and leakage

voltage

SPNU517C – March 2018
Submit Documentation Feedback

Oscillator, PLL, and Clock Monitoring
Copyright © 2018, Texas Instruments Incorporated

313

Phase-Locked Loop Theory of Operation

www.ti.com

The width of the up pulse and the down pulse depends on the difference in phase between the two inputs.
For example, when the reference input leads the feedback input by 10 ns, then an up pulse of
approximately 10 ns is generated (see Figure 9-10). On the other hand, when the reference input lags the
feedback input by 10 ns, then a down pulse of approximately 10 ns is generated. When the two inputs areexactly in phase, the up pulse and down pulse become essentially zero-width. These pulses are fed to thecharge pump block, which meters charge into the low-pass loop filter.
The advantage of a phase-frequency detector over a phase-only detector is that it cannot lock to aharmonic or subharmonic of the reference. This important property also ensures that the output frequencyof the VCO is always exactly 2*NF times the reference frequency.
The reference feedback frequency is based upon the VCO frequency and the feedback divider. Fractional
multiplication is achieved by changing the feedback divider real-time in order to create the fractional
multiplication. As an example, if a multiplier of 100.5 is selected, the feedback divider divides by 100 and
101 in equal proportions; in this case, the PLLMUL bit field would be programmed as 99.5 (0x6380). This
fractional multiplication is useful when trying to achieve final frequencies that are non-integer to the input
frequency (for example, a final frequency that is a prime number). The fractional portion of the divider
should be small compared to the multiplier and so it is recommended that the fractional portion relate toparts in 16, implying that the last 4 bits should always be 0.

9.7.2 Charge Pump and Loop Filter
The charge pump (CP) add or remove charge from the loop filter based on the pulses coming from thephase-frequency detector (PFD).
Two components of the filter output signal are summed together: an integral component and a
proportional component. The integral component maintains a DC level going to the VCO to set its
frequency, and the proportional component makes the VCO track changes in phase to minimize jitter. The
capacitors and resistors required for the filter are integrated in silicon.

9.7.3 Voltage-Controlled Oscillator
The output frequency of the VCO is proportional to its input control voltage, which is generated by the
charge pump via the integrated loop filter. If the VCO oscillates too slowly, the feedback phase begins tolag the reference phase at the PFD, which increases the control voltage at the VCO. Conversely, if the
VCO oscillates too fast, the feedback phase begins to lead the reference phase at the PFD, which
decreases the control voltage at the VCO. These two actions keep the VCO running at the correct
frequency multiple of the reference.
Figure 9-11. PLL Modulation Block Diagram

CLKIN

÷NR

post-ODCLK

Output CLKINTCLK
PFD

CP

LF

VCO

÷2

÷OD

÷R

PLL CLK

Feedback
CLK

NF
NV
NS

314

Divider

÷2

Oscillator, PLL, and Clock Monitoring

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Phase-Locked Loop Theory of Operation

www.ti.com

9.7.4 Frequency Modulation
The output clock of the PLL changes frequency in a controlled way, centered around the unmodulated
output frequency. The modulation block directly modulates the VCO frequency at the loop filter, andcreates the triangular frequency modulation (see Figure 9-12).
Figure 9-12. Frequency versus Time
Modulation Period (1/fs)

Depth

f0

Modulation

Frequency (MHz)

f0+n%

f0-n%
Time (Ps)

9.8

Programming Example
This section provides an example of how to program the PLL. For non-modulation settings, the PLLCTL1
and PLLCTL2 settings from 130 nm process devices can be used without modification.
Suppose that, using a 20 MHz crystal, the application requires:• 180 MHz GCLK (and HCLK) frequency• 100 kHz spreading frequency• 0.5% spreading depth
1. Choose an NR and NS such that:

•
•

•
•
•

f CLKIN³ 40
NR ´ f s(14)

f CLKIN
2 ´ NR ´ NSf
2 ´ NS = CLKIN ³ 40
NR ´ f s
fs º

(15)

(16)

(NR,NS) = {(5,20), (4,25), (2,50), (1,100)}
Either NR = 5 and NS = 20 or NR = 4 and NS = 25 are reasonable. Another choice (NR = 3 andNS = 33) is possible, if the modulation frequency can vary from 100 KHz.
2. Choose Output CLK frequency as integer divider of output frequency near to 330 MHz. Output CLK
frequency shall not exceed 550 MHz or fall below 150 MHz.
The integer values for 180 MHz are 360 MHz or 540 MHz. 360 MHz is close to the target frequency of
330 MHz and we use this frequency.
3. In this case, either of the following equations are suitable choices for getting to 360 MHz.
Choose NR = 5, NS = 20 and set NF = 90 or choose NR = 4, NS = 25 and set NF = 72.

f CLKIN 20[ MHz ]f
20[ MHz ]== 5[ MHz ] or CLKIN == 4[ MHz ]
NR
5
4
NR

(17)

4. Select the output divider OD so that the post-ODCLK frequency does not exceed the maximum
frequency of output divider R (device-specific frequency). In this case, choose OD = 2 and R = 1.

SPNU517C – March 2018
Submit Documentation Feedback

Oscillator, PLL, and Clock Monitoring
Copyright © 2018, Texas Instruments Incorporated

315

Programming Example

www.ti.com

5. Compute the divider value NV:

D ep th =

0 .5
NV
NS
N V 20
=
´
=
´
100
NF
2
90
2

(18)

NV = 0.045
6. If it is important to maintain the same average frequency in modulation as in non-modulation, either NF
should be modified OR program the MULMOD bit field. The modulation fields create a multiplier offset
equal to:DNF =NV ´ NS2(19)

If using MULMOD[8:0], then:

MULMOD [8 ...0 ] NV ´ NS 0 .045 ´ 20
=
=
256
2
2
0 . 045 ´ 20
M U LM O D [8 ... 0 ] =´ 256 = 115 . 2
2

D NF =(20)(21)

MULMOD will be set to 115.
7. Convert the PLL parameters into bit field values:• NR = 5, implies that REFCLKDIV[5:0] = 4• NS = 20, implies that SPRATE[8:0] = 19 = 0x13
• NF = 90, implies that PLLMUL[15:0] = 0x5900• OD = 2, implies that ODPLL[2:0] = 1• R = 1, implies that PLLDIV[4:0] = 0• NV = 0.045, implies that SPR_AMOUNT = 91 = 0x5B
• MULMOD[8:0] = 115 = 0x73
8. Setting only these fields (that is, not BPOS, ROF, or ROS) yields:
PLLCTL1 = 0x00045900
PLLCTL2 = 0x04C7325B
When FMENA is turned on, PLLCTL2 = 0x84C7325B
The Output CLK is centered in the range from 150 MHz to 550 MHz at 360 MHz.
NF = 90 falls within the multiplier range from 1 to 256.
OD is selected so that post-ODCLK meets the device specification.

316

Oscillator, PLL, and Clock Monitoring

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Chapter 10
SPNU517C – March 2018

Dual-Clock Comparator (DCC) ModuleThis chapter describes the dual-clock comparator (DCC) module.
Topic

10.1
10.2
10.3
10.4

...........................................................................................................................

Page

Introduction .................................................................................................... 318
Module Operation ............................................................................................ 319
Clock Source Selection for Counter0 and Counter1 ............................................. 322
DCC Control Registers ..................................................................................... 323

SPNU517C – March 2018
Submit Documentation Feedback

Dual-Clock Comparator (DCC) Module
Copyright © 2018, Texas Instruments Incorporated

317

Introduction

www.ti.com

10.1 Introduction
The microcontroller includes one dual-clock comparator (DCC) module. The primary purpose of a DCC
module is to measure the frequency of a clock signal using a second clock signal as a reference. An
application can use this capability to further enhance the system safety.

10.1.1 Main Features
The main features of the DCC module are:• Allows application to ensure that a fixed ratio is maintained between frequencies of two clock signals• Supports the definition of a programmable tolerance window in terms of number of reference clock
cycles• Supports continuous monitoring without requiring application intervention• Alternatively can be used in a single-sequence mode for spot measurements• Flexible clock source selection for counter0 and counter1 resulting in several specific use cases

10.1.2 Block Diagram
Figure 10-1 illustrates the main concept of the DCC module.
Figure 10-1. DCC Block Diagram
Preload Count 0

Clock 0

Down Counter 00=Preload Valid 00Valid 0 Down Counter=

Comparison

Error

Preload Count1

Clock 1

318

Down Counter 1

Dual-Clock Comparator (DCC) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Module Operation

www.ti.com

10.2 Module Operation
As shown in Figure 10-1, the DCC contains two counters – counter0 and counter1, which are driven by
two signals – clock0 and clock1. The application programs the seed values for both these counters. The
application also configures the tolerance window time by configuring the valid counter for clock0.
Counter0 and counter1 both start counting simultaneously when the DCC is enabled. When counter0
counts down to zero, it triggers the count down of the tolerance window counter called valid0.
The seed values of counter0 and counter1 are selected such that if the actual frequencies of clock0 andclock1 are equal to their expected frequencies, then the counter1 will reach zero either at the same time
as counter0 or during the count down of the tolerance window counter.

10.2.1 Error Conditions
An error condition is generated by any one of the following:
1. Counter1 counts down to 0 before Counter0 reaches 0.
2. Counter1 does not reach 0 even when Counter0 and Valid0 have both reached 0.
3. Clock0 is not present.
4. Clock1 is not present.
Any error causes the counters to stop counting. An application may then read out the counter values tohelp determine what caused the error.
The counters can also get reloaded with the seed values and continue counting down under the following
conditions:• The module is reset or restarted by the application, OR• Counter0, Valid 0 and Counter1 all reach 0 without any error
Figure 10-2. Counter Relationship(no error)

Error

Count0Count0

Valid0

Valid0Count1Count1Clock00

Clock10

reloadtime

Clock1 must expire
in this window, otherwise
signal an error

SPNU517C – March 2018
Submit Documentation Feedback

reloadDual-Clock Comparator (DCC) Module
Copyright © 2018, Texas Instruments Incorporated

319

Module Operation

www.ti.com

Figure 10-3. Clock1 Slower Than Clock0 - Results in an Error and Stops Counting

Error

Count0
Clock0
Valid00Count1Clock10
time

reloadCounter1 does not reach 0
before VALID0 reaches 0

Figure 10-4. Clock1 Faster Than Clock0 - Results in an Error and Stops Counting

Error

Count0
Clock0
Valid00Count1Clock10
time

reloadCounter1 reaches 0 before
Counter0 reaches 0320

Dual-Clock Comparator (DCC) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Module Operation

www.ti.com

Figure 10-5. Clock1 Not Present - Results in an Error and Stops Counting

Error

Count0
Clock0
Valid00Count1Count1 does not count down
due to an inactive clock 1

Clock10
time

reloadAn error signal is generated since Count1
does not reach 0 in the Valid0 window.

Figure 10-6. Clock0 Not Present - Results in an Error and Stops Counting

Error
Count0Count0 and Valid 0 do notcount down due to an
inactive clock 0

Clock0
Valid0Count1Clock1

reloadtime

Counter1 reaches 0 at theright time, but since Clock0 is not running,
Valid0 hasn’t started, thus an error is generated.

SPNU517C – March 2018
Submit Documentation Feedback

Dual-Clock Comparator (DCC) Module
Copyright © 2018, Texas Instruments Incorporated

321

Module Operation

www.ti.com

10.2.2 Single-Shot Operation Mode
The DCC module can be programmed to count down one time by enabling the single-shot mode. In thismode, the DCC stops operating when the down counter0 and the valid counter0 reach 0.
At the end of one sequence of counting down in this single-shot mode, the DCC gets disabled
automatically, which prevents further counting.
If there is no error generated at the end of the sequence, then the DONE status flag is set and a DONE
interrupt is generated. The application must clear the DONE flag before restarting the DCC.
If an error is generated at the end of the sequence, then the ERROR status flag is set. The applicationmust clear the ERROR status flag before restarting the DCC.

10.3 Clock Source Selection for Counter0 and Counter1
The DCC module has two counters. Table 10-1 and Table 10-2 show the options for selecting the clock
sources for both counters on the DCC module.
CNT0_CLKSRC is a control field in the DCCCNT0CLKSRC register. KEY and CNT1_CLKSRC are control
fields in the DCCCNT1CLKSRC register.
Table 10-1. Clock Source Selection for DCC Counter0
CNT0 CLKSRC

Clock Name

5h

HF LPOClock Description
High-Frequency Output of Internal Low-Power Oscillator

Ah

TCK

Test ClockAll other values

OSCIN

Main oscillator input

Table 10-2. Clock Source Selection for DCC Counter1
KEY

CNT1 CLKSRC

Clock Name

Clock Description

Ah0

PLL1 Output

Output from PLL#1

1h

Reserved

Reserved2h

LF LPO

Low-Frequency output of internal Low-Power Oscillator

3h

HF LPO

High-Frequency output of internal Low-Power Oscillator

4h

Reserved

Reserved

5h

EXTCLKIN

External clock input source

6h

Reserved

Reserved

7h

Reserved

Reserved

8h–Fh

VCLK

Don’t care

N2HET[31]All other values

Peripheral bus clock
Signal on the N2HET[31] channel of the N2HET module, either
by N2HET program execution, or by the application toggling theN2HET[31] pin as general-purpose output.

NOTE: N2HET[31] can be configured to be brought to the pin using the IOMM module or remain aninternal signal. If this signal is assigned to a pin, the application may configure this pin as an
output to generate a clock for external use and monitor this clock using the N2HET[31] since
the N2HET[31] input buffer is routed to the DCC. Likewise, N2HET[31] can be selected as
the DCC clock source utilizing the internal N2HET[31] channel and still be configured as aphysical pin with the IOMM and used as an externally available GPIO. However, N2HET[31]cannot be configured as an external input to monitor an external signal such as a clock
source somewhere else in the system. For this last case, it is recommended to utilize theExternal Clock input pin (selectable in place of GIOA[5] by the IOMM module).

322

Dual-Clock Comparator (DCC) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

DCC Control Registers

www.ti.com

10.4 DCC Control Registers
Table 10-3 lists the dual-clock comparator (DCC) module control and status registers. The registers
support 8-bit, 16-bit, or 32-bit writes and are aligned on a word (32-bit) boundary. Table 10-3 shows
address offsets from the module base address. The base address for DCC registers is FFFF EC00h.
Table 10-3. DCC Registers
OffsetAcronym

Register Description

00h

DCCGCTRLDCC Global Control Register

Section 10.4.1

Section04h

DCCREVDCC Revision ID Register

Section 10.4.2

08h

DCCCNT0SEEDDCC Counter0 Seed Register

Section 10.4.3

0Ch

DCCVALID0SEEDDCC Valid0 Seed Register

Section 10.4.4

10h

DCCCNT1SEEDDCC Counter1 Seed Register

Section 10.4.5

14h

DCCSTATDCC Status Register

Section 10.4.6

18h

DCCDCNT0

DCC Counter0 Value Register

Section 10.4.7

1Ch

DCCVALID0

DCC Valid0 Value Register

Section 10.4.8

20h

DCCDCNT1

DCC Counter1 Value Register

Section 10.4.9

24h

DCCCNT1CLKSRCDCC Counter1 Clock Source Selection Register

Section 10.4.10

28h

DCCCNT0CLKSRCDCC Counter0 Clock Source Selection Register

Section 10.4.11

SPNU517C – March 2018
Submit Documentation Feedback

Dual-Clock Comparator (DCC) Module
Copyright © 2018, Texas Instruments Incorporated

323

DCC Control Registers

www.ti.com

10.4.1 DCC Global Control Register (DCCGCTRL)
Figure 10-7 and Table 10-4 describe the DCC Global Control register.
Figure 10-7. DCC Global Control Register (DCCGCTRL) (offset = 00h)
31

16
Reserved
R-0

15

12

11

8

7

4

3

0

DONE_INT_ENA

SINGLE_SHOT

ERR_ENA

DCC_ENA

R/WP-5h

R/WP-5h

R/WP-5h

R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 10-4. DCC Global Control Register (DCCGCTRL) Field Descriptions
Bit

Field

31-16 Reserved

Value
0

15-12 DONE_INT_ENA

Description
Reads return 0. Writes have no effect.
Done Interrupt Enable.
Any operation mode read, privileged mode write:

5h
All other values
11-8

SINGLE_SHOT

No interrupt is generated when the DONE flag is set in the DCC Status (DCCSTAT)
register.
DONE interrupt is generated when the DONE flag is set in the DCC Status (DCCSTAT)
register.
Single-Shot Mode Enable.
Any operation mode read, privileged mode write:Ah

DCC stops counting when counter0 and valid0 both reach 0.

Bh

DCC stops counting when counter1 reaches 0.

All other values
7-4

ERR_ENA

DCC counts continuously and only stops when an error occurs.
Error Interrupt Enable.
Any operation mode read, privileged mode write:

5h
All other values
3-0

DCC_ENA

No interrupt is generated when the ERR flag is set in the DCC Status (DCCSTAT)
register.
ERROR interrupt is generated when the ERR flag is set in the DCC Status (DCCSTAT)
register.
DCC Enable.
Any operation mode read, privileged mode write:

5h

All other values

All DCC counters are stopped and error-checking is disabled. When an error occurs, thecounters stop and this field is set to 5h automatically disabling the DCC counter in
hardware.
Read: Counters are enabled.
Write: Load counters with their seed values and begin counting. It is recommended towrite Ah to enable counters to protect against single-bit errors.

324

Dual-Clock Comparator (DCC) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

DCC Control Registers

www.ti.com

10.4.2 DCC Revision ID Register (DCCREV)
Figure 10-8 and Table 10-5 describe the DCC Revision ID register.
Figure 10-8. DCC Revision ID Register (DCCREV) (offset = 04h)
31

30

29

28

27

16

SCHEME

Reserved

FUNC

R-1

R-0

R-0

15

11

10

8

7

6

5

0

RTL

MAJOR

CUSTOM

MINOR

R-0

R-2h

R-0

R-4h

LEGEND: R = Read only; -n = value after reset

Table 10-5. DCC Revision ID Register (DCCREV) Field Descriptions
Bit

Field

31-30

SCHEME

Value
1

Description
Reads return 1, writes have no effect.

29-28

Reserved

0

Reads return 0. Writes have no effect.

27-16

FUNC

0

Functional release number. Reads return 0, writes have no effect.

15-11

RTL

0

Design release number. Reads return 0, writes have no effect.

10-8

MAJOR

2h

Major revision number. Reads return 2h, writes have no effect.

7-6

CUSTOM0

Custom version number. Reads return 0, writes have no effect.

5-0

MINOR

4h

Minor revision number. Reads return 4h, writes have no effect.

10.4.3 DCC Counter0 Seed Register (DCCCNT0SEED)
Figure 10-9 and Table 10-6 describe the DCC Counter0 Seed register.
NOTE: Seed for Counter0 must be non-zero
The DCC must only be enabled after programming a non-zero value in the counter0 seedregister.

Figure 10-9. DCC Counter0 Seed Register (DCCCNT0SEED) (offset = 08h)
31

20

19

16

Reserved

COUNT0_SEED

R-0

R/WP-015

0
COUNT0_SEED
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 10-6. DCC Counter0 Seed Register (DCCCNT0SEED) Field Descriptions
Bit

Field

31-20

Reserved

19-0

COUNT0_SEEDValue
0
0-FFFFFh

Description
Reads return 0. Writes have no effect.
Seed value for DCC counter0.
Reads in any operating mode return the current value of counter0.
Writing in privileged mode only sets the current seed value for counter0.

SPNU517C – March 2018
Submit Documentation Feedback

Dual-Clock Comparator (DCC) Module
Copyright © 2018, Texas Instruments Incorporated

325

DCC Control Registers

www.ti.com

10.4.4 DCC Valid0 Seed Register (DCCVALID0SEED)
Figure 10-10 and Table 10-7 describe the DCC Valid0 Seed register.
NOTE: Seed for Valid0 must be at least 4h
The DCC must only be enabled after programming a value greater than or equal to 4h in thevalid0 seed register.

Figure 10-10. DCC Valid0 Seed Register (DCCVALID0SEED) (offset = 0Ch)
31

16
Reserved
R-0

150
VALID0_SEED
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 10-7. DCC Valid0 Seed Register (DCCVALID0SEED) Field Descriptions
Bit

Field

31-16

Reserved

Value

15-0

VALID0_SEED

0
0-FFFFh

Description
Reads return 0. Writes have no effect.
Seed value for DCC Valid0. This value defines the window within which the counter1 mustreach 0. This window needs to be at least 4 cycles wide.
Reads in any operating mode return the current value of Valid0.
Writing in privileged mode only sets the current seed value for Valid0.

10.4.5 DCC Counter1 Seed Register (DCCCNT1SEED)
Figure 10-11 and Table 10-8 describe the DCC Counter1 Seed register.
NOTE: Seed for Counter1 must be non-zero
The DCC must only be enabled after programming a non-zero value in the counter1 seedregister.

Figure 10-11. DCC Counter1 Seed Register (DCCCNT1SEED) (offset = 10h)
31

20

19

16

Reserved

COUNT1_SEED

R-0

R/WP-015

0
COUNT1_SEED
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 10-8. DCC Counter1 Seed Register (DCCCNT1SEED) Field Descriptions
Bit

Field

31-20

Reserved

19-0

COUNT1_SEEDValue
0
0-FFFFFh

Description
Reads return 0. Writes have no effect.
Seed value for DCC counter1.
Reads in any operating mode return the current value of counter1.
Writing in privileged mode only sets the current seed value for counter1.

326

Dual-Clock Comparator (DCC) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

DCC Control Registers

www.ti.com

10.4.6 DCC Status Register (DCCSTAT)
Figure 10-7 and Table 10-4 describe the DCC Status register.
Figure 10-12. DCC Status Register (DCCSTAT) (offset = 14h)31

16Reserved
R-0

15

2
Reserved
R-0

1

0

DONE

ERR

R/W1CP-0 R/W1CP-0

LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -n = value after reset

Table 10-9. DCC Status Register (DCCSTAT) Field Descriptions
Bit

Field

31-2

Reserved

1

DONE FLG

Value
0

Description
Reads return 0. Writes have no effect.
Single-Shot Sequence Done flag. Indicates that a single-shot DCC sequence is done without any
error.

0

Read: Single-shot sequence is not done.
Write: Writing 0 has no effect.

1

Read: Single-shot sequence is done without any error.
Write: Writing 1 in privileged mode clears the DONE flag.

0

ERR FLG

Error flag. Indicates that a DCC error has occurred.
0

Read: DCC error has not occurred.
Write: Writing 0 has no effect.

1

Read: An error has occurred.
Write: Writing 1 in privileged mode clears the ERR flag.

SPNU517C – March 2018
Submit Documentation Feedback

Dual-Clock Comparator (DCC) Module
Copyright © 2018, Texas Instruments Incorporated

327

DCC Control Registers

www.ti.com

10.4.7 DCC Counter0 Value Register (DCCCNT0)
Figure 10-13 and Table 10-10 describe the DCC Counter0 Value register.
NOTE: Reads may not return exact current value of Counter0
Reading the counter0 value while counting is enabled may not return the exact value of thecounter0.

Figure 10-13. DCC Counter0 Value Register (DCCCNT0) (offset = 18h)
31

20

19

16

Reserved

COUNT0

R-0

R-0

15

0
COUNT0
R-0

LEGEND: R = Read only; -n = value after reset

Table 10-10. DCC Counter0 Value Register (DCCCNT0) Field Descriptions
Bit

Field

31-20

Reserved

Value
0

19-0

COUNT0

0-FFFFFh

Description
Reads return 0. Writes have no effect.
Current value of DCC counter0.
Reads in any operating mode return the current value of counter0.
Writes have no effect.

328

Dual-Clock Comparator (DCC) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

DCC Control Registers

www.ti.com

10.4.8 DCC Valid0 Value Register (DCCVALID0)
Figure 10-14 and Table 10-11 describe the DCC Valid0 Value register.
NOTE: Reads may not return exact current value of Valid0
Reading the valid0 value while counting is enabled may not return the exact value of thevalid0.

Figure 10-14. DCC Valid0 Value Register (DCCVALID0) (offset = 1Ch)
31

16
Reserved
R-0

150
VALID0
R-0

LEGEND: R = Read only; -n = value after reset

Table 10-11. DCC Valid0 Value Register (DCCVALID0) Field Descriptions
Bit

Field

31-16

Reserved

Value
0

15-0

VALID0

0-FFFFh

Description
Reads return 0. Writes have no effect.
Current value for DCC Valid0.
Reads in any operating mode return the current value of Valid0.
Writes have no effect.

10.4.9 DCC Counter1 Value Register (DCCCNT1)
Figure 10-15 and Table 10-12 describe the DCC Counter1 Value register.
NOTE: Reads may not return exact current value of Counter1
Reading the counter1 value while counting is enabled may not return the exact value of thecounter1.

Figure 10-15. DCC Counter1 Value Register (DCCCNT1) (offset = 20h)
31

20

19

16

Reserved

COUNT1

R-0

R/WP-015

0
COUNT1
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 10-12. DCC Counter1 Value Register (DCCCNT1) Field Descriptions
Bit

Field

Value

31-20

Reserved

0

19-0

COUNT1

0-FFFFFh

Description
Reads return 0. Writes have no effect.
Current value for DCC Counter1.
Reads in any operating mode return the current value of counter1.
Writes have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

Dual-Clock Comparator (DCC) Module
Copyright © 2018, Texas Instruments Incorporated

329

DCC Control Registers

www.ti.com

10.4.10 DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC)
Figure 10-15 and Table 10-12 describe the DCC Counter1 Value register.
Figure 10-16. DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) (offset = 24h)31

16
Reserved
R-0

15

12

11

4

3

0

KEY

Reserved

CNT1_CLKSRC

R/WP-5h

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 10-13. DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC)
Field Descriptions
Bit

Field

31-16

Reserved

15-12

KEY

Value

Description

0

Reads return 0. Writes have no effect.
Key to enable clock source selection for counter1.
Reads in any operating mode return the current value of the key.
Writing in privileged mode sets the key value.

11-4

Reserved

3-0

CNT1_CLKSRC

AhWriting Ah as the key enables the CNT1_CLKSRC field to define the clock source forcounter1.

All other values

Writing any other value as the key disables the clock source selection for counter1. In
this case, the N2HET signal is used as the source for counter1.

0

Reads return 0. Writes have no effect.

0-Fh

Clock Source for counter1 when KEY is programmed to be Ah. See Table 10-2.
Reads in any operating mode return the current value of CLKSRC.
Writes in privileged mode select the clock source for counter1.

10.4.11 DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC)
Figure 10-15 and Table 10-12 describe the DCC Counter0 Value register.
Figure 10-17. DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) (offset = 28h)31

16Reserved
R-0

15

4

3

0

Reserved

CNT0_CLKSRC

R-0

R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 10-14. DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC)
Field Descriptions
Bit

Field

31-4

Reserved

3-0

CNT0_CLKSRC

Value
0
0-Fh

Description
Reads return 0. Writes have no effect.
Clock Source for counter0. See Table 10-1.
Reads in any operating mode return the current value of CLKSRC.
Writes in privileged mode select the clock source for counter0.

330

Dual-Clock Comparator (DCC) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Chapter 11
SPNU517C – March 2018

Error Signaling Module (ESM)
This chapter provides the details of the error signaling module (ESM) that aggregates device errors andprovides the capability to define internal and external error response based on error severity.
Topic

11.1
11.2
11.3
11.4

...........................................................................................................................

Page

Overview ........................................................................................................ 332
Module Operation ............................................................................................ 334
Recommended Programming Procedure ............................................................ 338
Control Registers ............................................................................................ 339

SPNU517C – March 2018
Submit Documentation Feedback

Error Signaling Module (ESM)
Copyright © 2018, Texas Instruments Incorporated

331

Overviewwww.ti.com

11.1 Overview
The Error Signaling Module (ESM) collects and reports the various error conditions on the microcontroller.
The error condition is categorized based on a severity level. Error response is then generated based on
the category of the error. Possible error responses include a low-priority interrupt, high-priority interrupt,
and an external pin action.

11.1.1 Features
•

•
•
•

Up to 128 error channels are supported, divided into 3 different groups:– 64 Group1 (low-severity) channels with configurable interrupt generation and configurable ERROR
pin behavior– 32 Group2 (high-severity) channels with predefined interrupt generation and predefined ERROR pin
behavior– 32 Group3 (high-severity) channels with no interrupt generation and predefined ERROR pin
behavior. These channels have no interrupt response as they are reserved for CPU based
diagnostics that generate aborts directly to the CPU.
Dedicated device ERROR pin to signal an external observer
Configurable timebase for ERROR pin output
Error forcing capability for latent fault testing

11.1.2 Block Diagram
As shown in Figure 11-1, the ESM channels are divided into three groups. Group1 channels are
considered to be low-severity. Group1 errors have a configurable interrupt response and configurable
ERROR pin behavior. Note that the ESM Status Register 1 (ESMSR1) for error group1 gets updated,regardless of whether an ESM interrupt for that Group1 channel is enabled or not. Group2 channels areconnected to higher-severity error signals. Group2 errors generate a non-maskable high-priority interrupt
to the CPU and assert the ERROR pin. Group3 channels indicate errors of the highest severity. Check the
specific part's datasheet for identifying group3 errors and their expected responses. Group3 errors always
generate an ERROR pin output.
The ESM interrupt and ERROR pin behavior are also summarized in Table 11-1.
Figure 11-1. Block Diagram

Low-Priority
Interrupt

High-Priority
Interrupt HandlingHigh-Priority
Interrupt

Error Signal
Handling

DeviceERROR Output
PIN

error_group1

Interrupt Enable
Interrupt Priority
from Hardware Diagnostics

error_group2

ERROR Pin Enableerror_group3

332 Error Signaling Module (ESM)

to VIM Interrupt Controller

Low-Priority
Interrupt Handling

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Overviewwww.ti.com

Table 11-1. ESM Interrupt and ERROR Pin Behavior
Error GroupInterrupt to CPU

Interrupt Priority

ERROR Pin Response1

Can be enabled or disabled for eachchannelCan be selected as low/high-priority
for each channel

ERROR pin action can be selected
for each channel separately

2

Cannot be disabledHigh priority

ERROR pin is asserted

3

No interrupt

NA

ERROR pin is asserted

Figure 11-2 and Figure 11-3 show the interrupt response handling and ERROR pin response handlingwith register configuration. The total active time of the ERROR pin is controlled by the Low-Time Counter
Preload register (LTCP) and the key register (ESMEPSR) as shown in Figure 11-3. See Section 11.2.2 fordetails.

Figure 11-2. Interrupt Response Handling

Low-Priority
Interrupt

High-Priority
Interrupt HandlingHigh-Priority
Interrupt

error_group1

Interrupt Enable
Controlled by:
ESMIESR1
ESMIECR1
ESMIESR4
ESMIECR4
error_group2

Interrupt Priority
Controlled by:
ESMILSR1
ESMILCR1
ESMILSR4ESMILCR4

to VIM Interrupt Controller

Low-Priority
Interrupt Handling

Figure 11-3. ERROR Pin Response Handling

Peripheral clock (VCLK)

error_group1

ERROR Pin Enable
Controlled by:
ESMIEPSR1,ESMIEPCR1
ESMIEPSR4,
ESMIEPCR4

Error Signal
Control

Low-Time
Counter Preload(LTCP )

error_group2
Low-Time
Counter(LTC)

error_group3

ERROR

DeviceOutputPINESMEPSRSPNU517C – March 2018
Submit Documentation Feedback

Error Signaling Module (ESM)
Copyright © 2018, Texas Instruments Incorporated

333

Module Operation

www.ti.com

11.2 Module Operation
This device has 128 error channels, divided into 3 different error groups. Please refer to the device
datasheet for ESM channel assignment details.
The ESM module has error flags for each error channel. The error status registers ESMSR1, ESMSR4,ESMSR2, ESMSR3 provide status information on a pending error of Group1 (Channel 0-31), Group1(Channel 32-63), Group2, and Group3, respectively. The ESMEPSR register provides the current ERROR
status. The module also provides a status shadow register, ESMSSR2, which maintains the error flags ofGroup2 until power-on reset (PORRST) is asserted. See Section 11.2.1 for details of their behavior during
power on reset and warm reset.
Once an error occurs, the ESM module will set the corresponding error flags. In addition, it can trigger aninterrupt, ERROR pin outputs low depending on the ESM settings. Once the ERROR pin outputs low, apower on reset or a write of 5h to ESMEKR is required to release the ESM error pin back to normal state.
See Section 11.2.2 for details. The application can read the error status registers (ESMSR1, ESMSR4,ESMSR2, and ESMSR3) to debug the error. If an RST is triggered or the error interrupt has been served,
the error flag of Group2 should be read from ESMSSR2 because the error flag in ESMSR2 will be cleared
by RST.
The user can also test the functionality of the ERROR pin by forcing an error. See Section 11.2.3 fordetails.

11.2.1 Reset Behavior
Power on reset:• ERROR pin behavior
When PORRST is active, the ERROR pin is in a high impedance state (output drivers disabled).
• Register behavior
After PORRST, all registers in ESM module will be re-initialized to the default value. All the error status
registers are cleared to zero.
Warm reset (RST):• ERROR pin behavior
During RST, the ERROR pin is in “output active” state with pull-down disabled. The ERROR pin
remains unchanged after RST.
• Register behavior
After RST, ESMSR1, ESMSR4, ESMSSR2, ESMSR3 and ESMEPSR register values remains unchanged. Since RST does not clear the critical failure registers, the user can read those registers to
debug the failures after RST pin goes back to high.
After RST, if one of the flags in ESMSR1 and ESMSR4 is set, the interrupt service routine will becalled once the corresponding interrupt is enabled.
NOTE: ESMSR2 is cleared after RST. The flag in ESMSR2 gets cleared when reading theappropriate vector in the ESMIOFFHR offset register. Reading ESMIOFFHR will not clear the
ESMSR1, ESMSR4, and the shadow register ESMSSR2. Reading ESMIOFFLR will also not
clear the ESMSR1 and ESMSR4.

334

Error Signaling Module (ESM)SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Module Operation

www.ti.com

11.2.2 ERROR Pin Timing
The ERROR pin is an active-low function. The state of the pin is also readable from ERROR Pin Status
Register (ESMEPSR). The pin is in a high-impedance state during power-on reset. Once the ESM module
drives the ERROR pin low, it remains in this state for the time specified by the Low-Time Counter Preload
register (LTCPR). Based on the time period of the peripheral clock (VCLK), the total active time of the
ERROR pin can be calculated as:t ERROR _ low = tVCLK ´ ( LTCP + 1)

(22)

Once this period expires, the ERROR pin is set to high in case the reset of the ERROR pin was
requested. This request is done by writing an appropriate key (5h) to the key register (ESMEKR) during
the ERROR pin low time. Here are a few examples:
Example 1: ESM detects a failure and drives the ERROR pin low. No ERROR pin reset is requested. The
ERROR pin continues outputting low until power on reset occurs.
Figure 11-4. ERROR Pin Timing - Example 1

failureERRORtERROR_low

Example 2: ESM detects a failure and drives the ERROR pin low. An ERROR pin reset request is
received before tERROR_low expires. In this case, the ERROR pin is set to high immediately after tERROR_low
expires.
Figure 11-5. ERROR Pin Timing - Example 2

failureERROR

ERROR pin reset request
tERROR_low

Example 3: ESM detects a failure and drives the ERROR pin low. An ERROR pin reset request is
received after tERROR_low expires. In this case, the ERROR pin is set to high immediately after ERROR pin
reset request is received.
Figure 11-6. ERROR Pin Timing - Example 3

failureERROR

ERROR pin reset request
tERROR_low

SPNU517C – March 2018
Submit Documentation Feedback

Error Signaling Module (ESM)
Copyright © 2018, Texas Instruments Incorporated

335

Module Operation

www.ti.com

Example 4: ESM detects a failure and drives the ERROR pin low. Another failure occurs within the time
the pin stays low. In this case, the low-time counter will be reset when the other failure occurs. In otherwords, tERROR_low should be counted from whenever the most recent failure occurs.
Figure 11-7. ERROR Pin Timing - Example 4
ERROR pin reset request

failure failure
ERROR

tERROR_low
tERROR_low

Example 5: The reset of the ERROR pin was requested by the software even before the failure occurs. In
this case, the ERROR pin is set to high immediately after tERROR_low expires. This case is not recommended
and should be avoided by the application.
Figure 11-8. ERROR Pin Timing - Example 5

ERROR pin reset request
ERROR

failuretERROR_low

Example 6: Failure1, then ERROR pin reset request, then Failure2 occurs before ERROR pin gets reset.
In this case, the ERROR pin low-time is just extended (restarted) when the failure2 occurs and goes highwhen this count-down expires. There now is a scenario where the ERROR pin is high and the group2/3
status flag is set. To avoid this scenario, the application must write 5h followed by 0 to the ESM Error Key
Register (ESMEKR). In this case, the ERROR pin will go high and then go low again to indicate thesecond failure.

336

Error Signaling Module (ESM)SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Module Operation

www.ti.com

11.2.3 Forcing an Error Condition
The error response generation mechanism is testable by software by forcing an error condition. This
allows testing the ERROR pin functionality. By writing a dedicated key to the ESM Error Key Register(ESMEKR), the ERROR pin is set to low for the specified time. The following steps describe how to force
an error condition:
1. Check ERROR Pin Status Register (ESMEPSR). This register must be 1 to switch into the error forcing
mode.
The ESM module cannot be switched into the error forcing mode if a failure has already been detectedin functional mode. The application command to switch to error forcing mode is ignored.
2. Write 5h to the ESM Error Key Register (ESMEKR). After that, the ERROR pin should output low (error
force mode).
Once the application puts the ESM module in the error forcing mode, the ERROR pin cannot indicate
the normal error functionality. If a failure occurs during this time, it gets still latched and the LTC is
reset and stopped. The error output pin is already driven low on account of the error forcing mode.
When the ESM is forced back to normal functional mode, the LTC becomes active and forces the
ERROR pin low until the expiration of the LTC (see Figure 11-9).
3. Write 0 to the ESM Error Key Register (ESMEKR) back to the active normal mode.
If there are no errors detected while the ESM module is in the error forcing mode, the ERROR pin
goes high immediately after exiting the error forcing mode.
Figure 11-9. ERROR Pin Timing - Example 7
failureWrite “1010” to ESMEKR

Write “0101” to ESMEKR
Write “0” to ESMEKR

ERROR

tERROR_low

SPNU517C – March 2018
Submit Documentation Feedback

Error Signaling Module (ESM)
Copyright © 2018, Texas Instruments Incorporated

337

Recommended Programming Procedure

www.ti.com

11.3 Recommended Programming Procedure
During the initialization stage, the application code should follow the recommendations in Figure 11-10 toinitialize the ESM.
Figure 11-10. ESM Initialization
Power up or PORRST

Force error on ERROR pin to check the functionality of ERROR pin and external monitoring
device connected to ERROR pin (ESMEKR).

Initialize VIM RAM. Map the ESM low priority interrupt service routine and high priority interrupt
service routine to pre-defined device specific interrupt channel. (Refer to device specific datasheet.)

Enable the interrupt in VIM and CPU.

Map ESM interrupt to high/low (ESM Group1 only, see register
ESMILSR1,ESMILCR1, ESMILSR4, and ESMILCR4).

Enable ESM interrupt and influence on ERROR pin (ESM Group1 only, see register ESMIEPSR1,ESMIEPCR1, ESMIESR1,ESMIECR1, ESMIEPSR4, ESMIEPCR4, ESMIESR4, and ESMIECR4).

Define ESM Low-Time Counter Preload Register ESMLTCPR to determine the ERROR pin
low time in case an error occurs.

Once an error occurs, it can trigger an interrupt, ERROR pin outputs low depending on the ESM settings.
Once the ERROR pin outputs low, a power on reset or a write of 5h to ESMEKR is required to release theESM back to normal state. The application can read the error status registers (ESMSR1, ESMSR4,ESMSR2, and ESMSR3) to debug the error. If an RST is triggered or the error interrupt has been served,
the error flag of Group2 should be read from ESMSSR2 because the error flag in ESMSR2 will be cleared
by RST.

338

Error Signaling Module (ESM)SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

11.4 Control Registers
This section describes the ESM registers. Each register begins on a 32-bit word boundary. The registers
support 32-bit, 16-bit, and 8-bit accesses. The base address for the registers is FFFF F500h.
Table 11-2. ESM Module Registers
Acronym

Register Description

FFFF F500h

Address

ESMEEPAPR1

ESM Enable ERROR Pin Action/Response Register 1

Section 11.4.1

SectionFFFF F504h

ESMDEPAPR1

ESM Disable ERROR Pin Action/Response Register 1

Section 11.4.2

FFFF F508h

ESMIESR1

ESM Interrupt Enable Set Register 1

Section 11.4.3

FFFF F50Ch

ESMIECR1

ESM Interrupt Enable Clear Register 1

Section 11.4.4

FFFF F510h

ESMILSR1

Interrupt Level Set Register 1

Section 11.4.5

FFFF F514h

ESMILCR1

Interrupt Level Clear Register 1

Section 11.4.6

FFFF F518h

ESMSR1ESM Status Register 1

Section 11.4.7

FFFF F51Ch

ESMSR2ESM Status Register 2

Section 11.4.8

FFFF F520h

ESMSR3

ESM Status Register 3

Section 11.4.9

FFFF F524h

ESMEPSRESM ERROR Pin Status Register

Section 11.4.10

FFFF F528h

ESMIOFFHR

ESM Interrupt Offset High Register

Section 11.4.11

FFFF F52Ch

ESMIOFFLR

ESM Interrupt Offset Low Register

Section 11.4.12

FFFF F530h

ESMLTCR

ESM Low-Time Counter Register

Section 11.4.13

FFFF F534h

ESMLTCPR

ESM Low-Time Counter Preload Register

Section 11.4.14

FFFF F538h

ESMEKRESM Error Key Register

Section 11.4.15

FFFF F53ChESMSSR2ESM Status Shadow Register 2

Section 11.4.16

FFFF F540h

ESMIEPSR4

ESM Influence ERROR Pin Set Register 4

Section 11.4.17

FFFF F544h

ESMIEPCR4

ESM Influence ERROR Pin Clear Register 4

Section 11.4.18

FFFF F548h

ESMIESR4

ESM Interrupt Enable Set Register 4

Section 11.4.19

FFFF F54Ch

ESMIECR4

ESM Interrupt Enable Clear Register 4

Section 11.4.20

FFFF F550h

ESMILSR4Interrupt Level Set Register 4

Section 11.4.21

FFFF F554h

ESMILCR4

Interrupt Level Clear Register 4

Section 11.4.22

FFFF F558h

ESMSR4

ESM Status Register 4

Section 11.4.23

SPNU517C – March 2018
Submit Documentation Feedback

Error Signaling Module (ESM)
Copyright © 2018, Texas Instruments Incorporated

339

Control Registers

www.ti.com

11.4.1 ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1)This register is dedicated for Group1.
Figure 11-11. ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1)[address = FFFF F500h]
31

16
IEPSET
R/WP-015

0
IEPSET
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 11-3. ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1)
Field Descriptions
Bit

Field

31-0

IEPSET

Value

Description
Enable ERROR Pin Action/Response on Group 1.
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: Failure on channel x has no influence on ERROR pin.
Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR1 register unchanged.

1

Read: Failure on channel x has influence on ERROR pin.
Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the
ESMIEPCR1 register.

11.4.2 ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1)This register is dedicated for Group1.
Figure 11-12. ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1)[address = FFFF F504h]
31

16
IEPCLR
R/WP-015

0
IEPCLR
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 11-4. ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1)
Field Descriptions
Bit

Field

31-0

IEPCLR

Value

Description
Disable ERROR Pin Action/Response on Group 1.
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: Failure on channel x has no influence on ERROR pin.
Write: Leaves the bit and the corresponding set bit in the ESMIEPSR1 register unchanged.

1

Read: Failure on channel x has influence on ERROR pin.
Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the
ESMIEPSR1 register.

340

Error Signaling Module (ESM)SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

11.4.3 ESM Interrupt Enable Set Register 1 (ESMIESR1)This register is dedicated for Group1.
Figure 11-13. ESM Interrupt Enable Set Register 1 (ESMIESR1)[address = FFFF F508h]
31

16
INTENSETR/WP-015

0
INTENSETR/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 11-5. ESM Interrupt Enable Set Register 1 (ESMIESR1) Field Descriptions
Bit

Field

31-0

INTENSET

Value

Description
Set interrupt enable.
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: Interrupt is disabled.
Write: Leaves the bit and the corresponding clear bit in the ESMIECR1 register unchanged.

1

Read: Interrupt is enabled.
Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR1 register.

11.4.4 ESM Interrupt Enable Clear Register 1 (ESMIECR1)
This register is dedicated for Group1.
Figure 11-14. ESM Interrupt Enable Clear Register 1 (ESMIECR1)[address = FFFF F50Ch]
31

16
INTENCLR
R/WP-015

0
INTENCLR
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 11-6. ESM Interrupt Enable Clear Register 1 (ESMIECR1) Field Descriptions
Bit

Field

31-0

INTENCLR

Value

Description
Clear interrupt enable.
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: Interrupt is disabled.
Write: Leaves the bit and the corresponding set bit in the ESMIESR1 register unchanged.

1

Read: Interrupt is enabled.
Write: Disables interrupt and clears the corresponding set bit in the ESMIESR1 register.

SPNU517C – March 2018
Submit Documentation Feedback

Error Signaling Module (ESM)
Copyright © 2018, Texas Instruments Incorporated

341

Control Registers

www.ti.com

11.4.5 ESM Interrupt Level Set Register 1 (ESMILSR1)
This register is dedicated for Group1.
Figure 11-15. ESM Interrupt Level Set Register 1 (ESMILSR1)[address = FFFF F510h]
31

16
INTLVLSET
R/WP-015

0
INTLVLSET
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 11-7. ESM Interrupt Level Set Register 1 (ESMILSR1) Field Descriptions
Bit

Field

31-0

INTLVLSET

Value

Description
Set interrupt priority.
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: Interrupt of channel x is mapped to low-level interrupt line.
Write: Leaves the bit and the corresponding clear bit in the ESMILCR1 register unchanged.

1

Read: Interrupt of channel x is mapped to high-level interrupt line.
Write: Maps interrupt of channel x to high-level interrupt line and sets the corresponding clear bit in
the ESMILCR1 register.

11.4.6 ESM Interrupt Level Clear Register 1 (ESMILCR1)This register is dedicated for Group1.
Figure 11-16. ESM Interrupt Level Clear Register 1 (ESMILCR1)[address = FFFF F514h]
31

16
INTLVLCLR
R/WP-015

0
INTLVLCLR
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 11-8. ESM Interrupt Level Clear Register 1 (ESMILCR1) Field Descriptions
Bit

Field

31-0

INTLVLCLR

Value

Description
Clear interrupt priority.
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: Interrupt of channel x is mapped to low-level interrupt line.
Write: Leaves the bit and the corresponding set bit in the ESMILSR1 register unchanged.

1

Read: Interrupt of channel x is mapped to high-level interrupt line.
Write: Maps interrupt of channel x to low-level interrupt line and clears the corresponding set bit in
the ESMILSR1 register.

342

Error Signaling Module (ESM)SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

11.4.7 ESM Status Register 1 (ESMSR1)
This register is dedicated for Group1. Note that the ESMSR1 status register will get updated if an error
condition occurs, regardless if the corresponding interrupt enable flag is set or not.
Figure 11-17. ESM Status Register 1 (ESMSR1)[address = FFFF F518h]
31

16
ESF
R/W1CP-X/0

15

0
ESF
R/W1CP-X/0

LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset/PORRST; X = Value unchanged

Table 11-9. ESM Status Register 1 (ESMSR1) Field Descriptions
Bit

Field

31-0

ESF

Value

Description
Error Status Flag. Provides status information on a pending error.
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: No error occurred; no interrupt is pending.
Write: Leaves the bit unchanged.

1

Read: Error occurred; interrupt is pending.
Write: Clears the bit.
Note: After RST, if one of these flags are set and the corresponding interrupt are enabled, theinterrupt service routine will be called.

11.4.8 ESM Status Register 2 (ESMSR2)
This register is dedicated for Group2.
Figure 11-18. ESM Status Register 2 (ESMSR2)[address = FFFF F51Ch]
31

16
ESF
R/W1CP-0

15

0
ESF
R/W1CP-0

LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset

Table 11-10. ESM Status Register 2 (ESMSR2) Field Descriptions
Bit

Field

31-0

ESF

Value

Description
Error Status Flag. Provides status information on a pending error.
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: No error occurred; no interrupt is pending.
Write: Leaves the bit unchanged.

1

Read: Error occurred; interrupt is pending.
Write: Clears the bit. ESMSSR2 is not impacted by this action.
Note: In normal operation, the flag gets cleared when reading the appropriate vector in the
ESMIOFFHR offset register. Reading ESMIOFFHR will not clear the ESMSR1 and the shadow
register ESMSSR2.

SPNU517C – March 2018
Submit Documentation Feedback

Error Signaling Module (ESM)
Copyright © 2018, Texas Instruments Incorporated

343

Control Registers

www.ti.com

11.4.9 ESM Status Register 3 (ESMSR3)
This register is dedicated for Group3.
Figure 11-19. ESM Status Register 3 (ESMSR3)[address = FFFF F520h]
31

16
ESF
R/W1CP-X/0

15

0
ESF
R/W1CP-X/0

LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset/PORRST; X = Value unchanged

Table 11-11. ESM Status Register 3 (ESMSR3) Field Descriptions
Bit

Field

31-0

ESF

Value

Description
Error Status Flag. Provides status information on a pending error.
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: No error occurred.
Write: Leaves the bit unchanged.

1

Read: Error occurred.
Write: Clears the bit.

11.4.10 ESM ERROR Pin Status Register (ESMEPSR)
Figure 11-20. ESM ERROR Pin Status Register (ESMEPSR)[address = FFFF F524h]
31

16
Reserved
R-0

15

1

0

Reserved

EPSF

R-0

R-X/1

LEGEND: R = Read only; -n = value after reset/PORRST; X = Value unchanged

Table 11-12. ESM ERROR Pin Status Register (ESMEPSR) Field Descriptions
Bit

Field

31-1

Reserved

0

Value
0

EPSF

Description
Reads return 0. Writes have no effect.
ERROR Pin Status Flag. Provides status information for the ERROR pin.
Read/Write in User and Privileged mode.

0

Read: ERROR pin is low (active) if any error has occurred.
Write: Writes have no effect.

1

Read: ERROR pin is high if no error has occurred.
Write: Writes have no effect.
Note: This flag will be set to 1 after PORRST. The value will be unchanged after RST. The ERROR
pin status remains unchanged after RST.

344

Error Signaling Module (ESM)SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

11.4.11 ESM Interrupt Offset High Register (ESMIOFFHR)
Figure 11-21. ESM Interrupt Offset High Register (ESMIOFFHR)[address = FFFF F528h]
31

16
Reserved
R-0

15

7

6

0

Reserved

INTOFFH

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 11-13. ESM Interrupt Offset High Register (ESMIOFFHR) Field Descriptions
Bit

Field

31-7

Reserved

6-0

INTOFFH

Value
0

Description
Reads return 0. Writes have no effect.
Offset High-Level Interrupt. This vector gives the channel number of the highest-pending interrupt
request for the high-level interrupt line. Interrupts of error Group2 have higher priority thaninterrupts of error Group1. Inside a group, channel 0 has highest priority and channel 31 has lowest
priority.
User and privileged mode (read):
Returns number of pending interrupt with the highest priority for the high-level interrupt line.

0

No pending interrupt.

1hInterrupt pending for channel 0, error Group1.

:

:

20h

Interrupt pending for channel 31, error Group1.

21hInterrupt pending for channel 0, error Group2.

:

:

40h

Interrupt pending for channel 31, error Group2.

41hInterrupt pending for channel 32, error Group1.

:

:

60h

Interrupt pending for channel 63, error Group1.
Note: Reading the interrupt vector will clear the corresponding flag in the ESMSR2 register; will not
clear ESMSR1 and ESMSSR2 and the offset register gets updated.
User and privileged mode (write):
Writes have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

Error Signaling Module (ESM)
Copyright © 2018, Texas Instruments Incorporated

345

Control Registers

www.ti.com

11.4.12 ESM Interrupt Offset Low Register (ESMIOFFLR)
Figure 11-22. ESM Interrupt Offset Low Register (ESMIOFFLR)[address = FFFF F52Ch]
31

16
Reserved
R-0

15

7

6

0

Reserved

INTOFFL

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 11-14. ESM Interrupt Offset Low Register (ESMIOFFLR) Field Descriptions
Bit

Field

31-7

Reserved

6-0

INTOFFL

Value
0

Description
Reads return 0. Writes have no effect.
Offset Low-Level Interrupt. This vector gives the channel number of the highest-pending interrupt
request for the low-level interrupt line. Inside a group, channel 0 has highest priority and channel 31
has lowest priority.
User and privileged mode (read):
Returns number of pending interrupt with the highest priority for the low-level interrupt line.

0

No pending interrupt.

1hInterrupt pending for channel 0, error Group1.

:

:

20h

Interrupt pending for channel 31, error Group1.

21h-40h Reserved
41hInterrupt pending for channel 32, error Group1.

:

:

60h

Interrupt pending for channel 63, error Group1.
Note: Reading the interrupt vector will not clear the corresponding flag in the ESMSR1 register.
Group2 interrupts are fixed to the high-level interrupt line only.
User and privileged mode (write):
Writes have no effect.

346

Error Signaling Module (ESM)SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

11.4.13 ESM Low-Time Counter Register (ESMLTCR)
Figure 11-23. ESM Low-Time Counter Register (ESMLTCR)[address = FFFF F530h]
31

16
Reserved
R-0

15

0
LTC
R-3FFFhLEGEND: R = Read only; -n = value after reset

Table 11-15. ESM Low-Time Counter Register (ESMLTCR) Field Descriptions
Bit

Field

31-16

Reserved

Value

15-0

LTC

0

Description
Reads return 0. Writes have no effect.
ERROR Pin Low-Time Counter
16-bit preloadable down-counter to control low-time of ERROR pin. The low-time counter istriggered by the peripheral clock (VCLK).
Note: Low-time counter is set to the default preload value of the ESMLTCPR in the following cases:
1.
2.
3.

Reset (power on reset or warm reset)
An error occurs
User forces an error

11.4.14 ESM Low-Time Counter Preload Register (ESMLTCPR)
Figure 11-24. ESM Low-Time Counter Preload Register (ESMLTCPR)[address = FFFF F534h]
31

16
Reserved
R-0

15

14

13

0

LTCP

LTCP

R/WP-0R-3FFFhLEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 11-16. ESM Low-Time Counter Preload Register (ESMLTCPR) Field Descriptions
Bit

Field

31-16

Reserved

15-0

LTCP

Value
0
0-FFFFh

Description
Reads return 0. Writes have no effect.
ERROR Pin Low-Time Counter Pre-load Value
16-bit preload value for the ERROR pin low-time counter. Defines the minimum period for which
the ERROR pin will be driven to 16384 VCLK cycles.
Note: Only LTCP[15] and LTCP[14] are configurable (privileged mode write).

SPNU517C – March 2018
Submit Documentation Feedback

Error Signaling Module (ESM)
Copyright © 2018, Texas Instruments Incorporated

347

Control Registers

www.ti.com

11.4.15 ESM Error Key Register (ESMEKR)
Figure 11-25. ESM Error Key Register (ESMEKR)[address = FFFF F538h]
31

16
Reserved
R-0

15

4

3

0

Reserved

EKEY

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 11-17. ESM Error Key Register (ESMEKR) Field Descriptions
Bit

Field

31-4

Reserved

3-0

EKEY

Value

Description

0

Reads return 0. Writes have no effect.
Error Key. The key to reset the ERROR pin or to force an error on the ERROR pin.
User and privileged mode (read):
Returns current value of the EKEY.
Privileged mode (write):0

Activates normal mode (recommended default mode).

5h

The ERROR pin set to high when the low-time counter (LTC) has completed; then the EKEY
bit will switch back to normal mode (EKEY = 0000).

Ah

Forces error on ERROR pin.

All other values

Activates normal mode.

11.4.16 ESM Status Shadow Register 2 (ESMSSR2)
This register is dedicated for Group2.
Figure 11-26. ESM Status Shadow Register 2 (ESMSSR2)[address = FFFF F53Ch]
31

16
ESF
R/W1CP-X/0

15

0
ESF
R/W1CP-X/0

LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset/PORRST; X = Value unchanged

Table 11-18. ESM Status Shadow Register 2 (ESMSSR2) Field Descriptions
Bit

Field

31-0

ESF

Value

Description
Error Status Flag. Shadow register for status information on pending error.
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: No error occurred.
Write: Leaves the bit unchanged.

1

Read: Error occurred.
Write: Clears the bit. ESMSR2 is not impacted by this action.
Note: Errors are stored until they are cleared by the software or at power-on reset (PORRST).

348

Error Signaling Module (ESM)SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

11.4.17 ESM Influence ERROR Pin Set Register 4 (ESMIEPSR4)
This register is dedicated for Group1.
Figure 11-27. ESM Influence ERROR Pin Set Register 4 (ESMIEPSR4)[address = FFFF F540h]
31

16
IEPSET[63:48]
R/WP-015

0
IEPSET[47:32]
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 11-19. ESM Influence ERROR Pin Set Register 4 (ESMIEPSR4) Field Descriptions
Bit

Field

63-32

IEPSET

Value

Description
Set influence on ERROR pin.
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: Failure on channel x has no influence on ERROR pin.
Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR4 register unchanged.

1

Read: Failure on channel x has influence on ERROR pin.
Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the
ESMIEPCR4 register.

11.4.18 ESM Influence ERROR Pin Clear Register 4 (ESMIEPCR4)
This register is dedicated for Group1.
Figure 11-28. ESM Influence ERROR Pin Clear Register 4 (ESMIEPCR4)[address = FFFF F544h]
31

16
IEPCLR[63:48]
R/WP-015

0
IEPCLR[47:32]
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 11-20. ESM Influence ERROR Pin Clear Register 4 (ESMIEPCR4) Field Descriptions
Bit

Field

63-32

IEPCLR

Value

Description
Clear influence on ERROR pin.
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: Failure on channel x has no influence on ERROR pin.
Write: Leaves the bit and the corresponding set bit in the ESMIEPSR4 register unchanged.

1

Read: Failure on channel x has influence on ERROR pin.
Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the
ESMIEPSR4 register.

SPNU517C – March 2018
Submit Documentation Feedback

Error Signaling Module (ESM)
Copyright © 2018, Texas Instruments Incorporated

349

Control Registers

www.ti.com

11.4.19 ESM Interrupt Enable Set Register 4 (ESMIESR4)This register is dedicated for Group1.
Figure 11-29. ESM Interrupt Enable Set Register 4 (ESMIESR4)[address = FFFF F548h]
31

16
INTENSET[63:48]
R/WP-015

0
INTENSET[47:32]
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 11-21. ESM Interrupt Enable Set Register 4 (ESMIESR4) Field Descriptions
Bit

Field

63-32

INTENSET

Value

Description
Set interrupt enable.
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: Interrupt is disabled.
Write: Leaves the bit and the corresponding clear bit in the ESMIECR4 register unchanged.

1

Read: Interrupt is enabled.
Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR4 register.

11.4.20 ESM Interrupt Enable Clear Register 4 (ESMIECR4)This register is dedicated for Group1.
Figure 11-30. ESM Interrupt Enable Clear Register 4 (ESMIECR4)[address = FFFF F54Ch]
31

16
INTENCLR[63:48]
R/WP-015

0
INTENCLR[47:32]
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 11-22. ESM Interrupt Enable Clear Register 4 (ESMIECR4) Field Descriptions
Bit

Field

63-32

INTENCLR

Value

Description
Clear interrupt enable.
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: Interrupt is disabled.
Write: Leaves the bit and the corresponding set bit in the ESMIESR4 register unchanged.

1

Read: Interrupt is enabled.
Write: Disables interrupt and clears the corresponding set bit in the ESMIESR4 register.

350

Error Signaling Module (ESM)SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

11.4.21 ESM Interrupt Level Set Register 4 (ESMILSR4)This register is dedicated for Group1.
Figure 11-31. ESM Interrupt Level Set Register 4 (ESMILSR4)[address = FFFF F550h]
31

16
INTLVLSET[63:48]
R/WP-015

0
INTLVLSET[47:32]
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 11-23. ESM Interrupt Level Set Register 4 (ESMILSR4) Field Descriptions
Bit

Field

63-32

INTLVLSET

Value

Description
Set interrupt level.
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: Read: Interrupt of channel x is mapped to low-level interrupt line.
Write: Leaves the bit and the corresponding clear bit in the ESMILCR4 register unchanged.

1

Read: Interrupt of channel x is mapped to high-level interrupt line.
Write: Maps interrupt of channel x to high-level interrupt line and sets the corresponding clear bit in
the ESMILCR4 register.

11.4.22 ESM Interrupt Level Clear Register 4 (ESMILCR4)
This register is dedicated for Group1.
Figure 11-32. ESM Interrupt Level Clear Register 4 (ESMILCR4)[address = FFFF F554h]
31

16
INTLVLCLR[63:48]
R/WP-015

0
INTLVLCLR[47:32]
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 11-24. ESM Interrupt Level Clear Register 4 (ESMILCR4) Field Descriptions
Bit

Field

63-32

INTLVLCLR

Value

Description
Clear interrupt level.
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: Interrupt of channel x is mapped to low-level interrupt line.
Write: Leaves the bit and the corresponding set bit in the ESMILSR4 register unchanged.

1

Read: Interrupt of channel x is mapped to high-level interrupt line.
Write: Maps interrupt of channel x to low-level interrupt line and clears the corresponding set bit in
the ESMILSR4 register.

SPNU517C – March 2018
Submit Documentation Feedback

Error Signaling Module (ESM)
Copyright © 2018, Texas Instruments Incorporated

351

Control Registers

www.ti.com

11.4.23 ESM Status Register 4 (ESMSR4)
This register is dedicated for Group1.
Figure 11-33. ESM Status Register 4 (ESMSR4)[address = FFFF F558h]
31

16
ESF[63:48]
R/W1CP-X/0

15

0
ESF[47:32]
R/W1CP-X/0

LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset/PORRST; X = Value unchanged

Table 11-25. ESM Status Register 4 (ESMSR4) Field Descriptions
Bit

Field

63-32

ESF

Value

Description
Error Status Flag. Provides status information on a pending error.
Read in User and Privileged mode. Write in Privileged mode only.

0

Read: No error occurred; no interrupt is pending.
Write: Leaves the bit unchanged.

1

Read: Error occurred; interrupt is pending.
Write: Clears the bit.
Note: After RST, if one of these flags are set and the corresponding interrupt are enabled, theinterrupt service routine will be called.

352

Error Signaling Module (ESM)SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Chapter 12
SPNU517C – March 2018

Real-Time Interrupt (RTI) ModuleThis chapter describes the functionality of the real-time interrupt (RTI) module. The RTI is designed as an
operating system timer to support a real time operating system (RTOS).
Topic

12.1
12.2
12.3

...........................................................................................................................

Page

Overview ......................................................................................................... 354
Module Operation ............................................................................................. 355
RTI Control Registers ........................................................................................ 362

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

353

Overviewwww.ti.com

12.1 Overview
The real-time interrupt (RTI) module provides timer functionality for operating systems and forbenchmarking code. The RTI module can incorporate several counters that define the time bases needed
for scheduling in the operating system.
The timers also allow you to benchmark certain areas of code by reading the values of the counters at the
beginning and the end of the desired code range and calculating the difference between the values.

12.1.1 Features
The RTI module has the following features:• Two independent 64 bit counter blocks• Four configurable compares for generating operating system ticks. Each event can be driven by either
counter block 0 or counter block 1.
• Fast enabling/disabling of events• Two time stamp (capture) functions for system or peripheral interrupts, one for each counter block• Digital windowed watchdog

12.1.2 Industry Standard Compliance Statement
This module is specifically designed to fulfill the requirements for OSEK (Offene Systeme und deren
Schnittstellen für die Elektronik im Kraftfahrzeug, or Open Systems and the Corresponding Interfaces for
Automotive Electronics) as well as OSEK/time-compliant operating systems, but is not limited to it.

354

Real-Time Interrupt (RTI) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Module Operation

www.ti.com

12.2 Module Operation
Figure 12-1 illustrates the high level block diagram of the RTI module.
The RTI module has two independent counter blocks for generating different time bases: counter block 0
and counter block 1.
A compare unit compares the counters with programmable values and generates four independentinterrupt on compare matches. Each of the compare registers can be programmed to be compared toeither counter block 0 or counter block 1.
The following sections describe the individual functions in more detail.
Figure 12-1. RTI Block Diagram
Compare Unit
32

RTICLK
NTU0
NTU1
NTU2
NTU3

Counter Block 0
64-bitCapture Feature

Counter Block 1
64-bitCapture Feature

RTICLK

Event0

VIM REQ[2]Event1

VIM REQ[3]Event2

VIM REQ[4]Event3

VIM REQ[5]

32
32

32
32

32

12.2.1 Counter Operation
Each counter block consists of the following (see Figure 12-2):• One 32-bit prescale counter (RTIUC0 or RTIUC1)• One 32-bit free running counter (RTIFRC0 or RTIFRC1)
The RTIUC0/1 is driven by the RTICLK and counts up until the compare value in the compare up counterregister (RTICPUC0 or RTICPUC1) is reached. When the compare matches, RTIFRC0/1 is incremented
and RTIUC0/1 is reset to 0. If RTIFRC0/1 overflows, an interrupt is generated to the vectored interrupt
manager (VIM). The overflow interrupt is not intended to generate the time base for the operating system.
See Section 12.2.2 for the time base generation. The up counter together with the compare up countervalue prescale the RTI clock. The resulting formula for the frequency of the free running counter(RTIFRC0/1) is:f RTIFRCx ={f RTICLK--------------------------------------RTICPUCx + 1
f RTICLK-------------------32
2

when RTICPUCx ≠ 0when RTICPUCx = 0(23)

NOTE: Setting RTICPUCx equal to zero is not recommended. Doing so will hold the Up Counter atzero for two RTICLK cycles after it overflows from 0xFFFFFFFF to zero.

The counter values can be determined by reading the respective counter registers or by generating a
hardware event that captures the counter value into the respective capture register. Both functions aredescribed in the following sections.

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

355

Module Operation

www.ti.com

Figure 12-2. Counter Block Diagram
310Counter Block 0

Compare Up
Counter

OVLINT0

RTICPUC0

RTICLK0Up Counter
31

32

1

31

32

=

31

0

Free Running Counter

1

32

RTIFRC0To Compare
Unit

0

Up Counter
Register
RTIUC0

32

31

0

32

31

Capture Up
Counter0

Capture Free Running
Counter

RTICAUC0

RTICAFRC0
1

Control

CAP event source 0 from VIM
CAP event source 1 from VIM

RTICAPCTRL

310Counter Block 1

1

Compare Up
Counter

OVLINT1

RTICPUC1

RTICLK0Up Counter
31

32

1

31

32

=

31

1

0

Free Running Counter
RTIFRC132

To Compare
Unit

0

Up Counter
Register
RTIUC132

31

0Capture Up
Counter
RTICAUC1

356

32

31

0

Capture Free Running
Counter
RTICAFRC1

Real-Time Interrupt (RTI) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Module Operation

www.ti.com

12.2.1.1 Counter and Capture Read Consistency
Portions of the device internal databus are 32-bits wide. If the application wants to read the 64-bit countersor the 64-bit capture values, a certain order of 32-bit read operations needs to be followed. This is toprevent one counter incrementing in between the two separate read operations to both counters.
Reading the Counters
The free running counter (RTIFRCx) must be read first. This priority will ensure that in the cycle when the
CPU reads RTIFRCx, the up counter value is stored in its counter register (RTIUCx). The second read has
to access the up counter register (RTIUCx), which then holds the value which corresponds to the numberof RTICLK cycles that have elapsed at the time reading the free running counter register (RTIFRCx).
NOTE: The up counters are implemented as shadow registers. Reading RTIUCx without having
read RTIFRCx first will return always the same value. RTIUCx will only be updated when
RTIFRCx is read.

Reading the Capture Values
The free running counter capture register (RTICAFRCx) must be read first. This priority will ensure that in
the cycle when the CPU reads RTICAFRCx, the up counter value is stored in its counter register(RTICAUCx). The second read has to access the up counter register (RTICAUCx), which then holds thevalue captured at the time when reading the capture free running counter register (RTICAFRCx).
NOTE: The capture up counter registers are implemented as shadow registers. Reading RTICAUCx
without having read RTICAFRCx first will return always the same value. RTICAUCx will only
be updated when RTICAFRCx is read.

12.2.1.2 Capture Feature
Both counter blocks also provide a capture feature on external events. Two capture sources can trigger
the capture event. The source triggering the block is configurable (RTICAPCTRL). The sources originate
from the Vectored Interrupt Manager (VIM) and allow the generation of capture events when a peripheral
modules has generated an interrupt. Any of the peripheral interrupts can be selected as the capture eventin the VIM.
When an event is detected, RTIUCx and RTIFRCx are stored in the capture up counter (RTICAUCx) andcapture free running counter (RTICAFRCx) registers. The read order of the captured values must be thesame as the read order of the actual counters (see Section 12.2.1.1).

12.2.2 Interrupt Requests
There are four compare registers (RTICOMPy) to generate interrupt requests to the VIM. The interrupts
can be used to generate different time bases for the operating system. Each of the compare registers canbe configured to be compared to either RTIFRC0 or RTIFRC1. When the counter value matches thecompare value, an interrupt is generated. To allow periodic interrupts, a certain value can be added to thecompare value in RTICOMPy automatically. This value is stored in the update compare register(RTIUDCPy) and will be added after a compare is matched. The period of the generated interrupt can becalculated with:t COMPx = t RTICLK x (RTICPUCy + 1) x RTIUDCPy

if RTICPUCy ≠ 0,
t COMPx = t RTICLK x 232 x RTIUDCPy

if RTIUDCPy = 0,32

t COMPx = t RTICLK x (RTICPUCy + 1) x 2
SPNU517C – March 2018
Submit Documentation Feedback(24)
Real-Time Interrupt (RTI) Module

Copyright © 2018, Texas Instruments Incorporated

357

Module Operation

www.ti.com

Figure 12-3. Compare Unit Block Diagram (shows only 1 of 4 blocks for simplification)
31
0
Update Compare
RTIUDCP0 / RTIUDCP1
RTIUDCP2 / RTIUDCP3
32

+

31

0
CompareRTICOMP0 / RTICOMP1
RTICOMP2 / RTICOMP3

From counter
block 0

32

=

32

1

INT REQn

From counter
block 1

Enable/Disable
RTISETINTENA[3:0]
RTICLEARINTENA[3:0]Control
RTICOMPCTRL

Another interrupt that can be generated is the overflow interrupt (OVLINTx) in case the RTIFRCx counter
overflows.
The interrupts can be enabled in the RTISETINTENA register and disabled in the RTICLEARINTENA
register. The RTIINTFLAG register shows the pending interrupts.

12.2.3 RTI Clocking
The counter blocks are clocked with RTICLK (for definition, see Section 2.4.2).

12.2.4 Digital Watchdog (DWD)
The digital watchdog (DWD) is an optional safety diagnostic which can detect a runaway CPU andgenerate either a reset or NMI (non-maskable interrupt) response. It generates resets or NMIs after a
programmable period, or if no correct key sequence was written to the RTIWDKEY register. Figure 12-4
illustrates the DWD.
Figure 12-4. Digital Watchdog
To RESET
logic

15

0

RTIWDKEY
Reset
WD Finite State Machine=0

Discharge
24

15

0

Compare16 bit out to 2

KEY [1:0]

0

DWD down counter
RTIDWDCNTR

RTICLK

Suspend
nTRST
11

0

DWD preload
RTIDWDPRLD

358

31

31

0

DWD ctrl
RTIDWDCTRL=

Real-Time Interrupt (RTI) Module0

DWD hardwired
code

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Module Operation

www.ti.com

12.2.4.1 Digital Watchdog (DWD)
The DWD is disabled by default. If it should be used, it must be enabled by writing a 32-bit value to the
RTIDWDCTRL register.
NOTE:

Once the DWD is enabled, it cannot be disabled except by system reset or power on reset.

If the correct key sequence is written to the RTIWDKEY register (0xE51A followed by 0xA35C), the 25-bit
DWD down counter is reloaded with the left justified 12-bit preload value stored in RTIDWDPRLD. If an
incorrect value is written, a watchdog reset or NMI will occur immediately. A reset or NMI will also be
generated when the DWD down counter is decremented to 0.
While the device is in suspend mode (halting debug mode), the DWD down counter keeps the value it had
when entering suspend mode.
The DWD down counter will be decremented with the RTICLK frequency.
Figure 12-5. DWD Operation
0x1FFFFFF
PreloadRegister
Value left
shifted 13bits

DWD
Down
Counter

0
time

CPU
accessto DWD

Reset/NMI
set DWD
Preloadenable
DWD

write E51A
to WDKEY

write A35C write E51A write A35C
to WDKEY to WDKEY to WDKEY

The expiration time of the DWD down counter can be determined with the following equation:
texp = (DWDPRLD + 1) × 213/RTICLK
where
DWDPRLD = 0...4095
NOTE: Care should be taken to ensure that the CPU write to the watchdog register is made allowing
time for the write to propagate to the RTI.

12.2.4.2 Digital Windowed Watchdog (DWWD)
In addition to the time-out boundary configurable via the digital watchdog discussed in Section 12.2.4.1,
for enhanced safety metrics it is desirable to check for a watchdog "pet" within a time window rather thanusing a single time threshold. This is enabled by the digital windowed watchdog (DWWD) feature.
• Functional Behavior
The DWWD opens a configurable time window in which the watchdog must be serviced. Any attempt toservice the watchdog outside this time window, or a failure to service the watchdog in this time window,
will cause the watchdog to generate either a reset or a NMI to the CPU. This is controlled by configuring
the RTIWWDRXNCTRL register. As with the DWD, the DWWD is disabled after power on reset. When the
DWWD is configured to generate a non-maskable interrupt on a window violation, the watchdog counter
continues to count down. The NMI handler needs to clear the watchdog violation status flag(s) and then

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

359

Module Operation

www.ti.com

service the watchdog by writing the correct sequence in the watchdog key register. This service will cause
the watchdog counter to get reloaded from the preload value and start counting down. If the NMI handler
does not service the watchdog in time, it could count down all the way to zero and wrap around. If the NMI
Handler does not service the watchdog in time, the NMI gets generated continuously, each time thecounter counts to '0'.
The DWWD uses the Digital Watchdog (DWD) preload register (RTIDWDPRLD) setting to define the endtime of the window. The start-time of the window is defined by a window size configuration register(RTIWWDSIZECTRL).
The default window size is set to 100%, which corresponds to the DWD functionality of a time-out-only
watchdog. The window size can be selected (through register RTIWWDSIZECTRL) from among 100%,50%, 25%, 12.5%, 6.25% and 3.125% as shown in Figure 12-6. The window with the respective size will
be opened before the end of the DWD expiration. The user has to serve the watchdog in the window.
Otherwise, a reset or NMI will generate. Figure 12-7 shows an DWWD operation example (25% window).
• Configuration of DWWD
The DWWD preload value (same as DWD preload) can only be configured when the DWWD counter isdisabled. The window size and watchdog reaction to a violation can be configured even after thewatchdog has been enabled. Any changes to the window size and watchdog reaction configurations will
only take effect after the next servicing of the DWWD. This feature can be utilized to dynamically set
windows of different sizes based on task execution time, adding a program sequence element to thediagnostic which can improve fault coverage.
Figure 12-6. Digital Windowed Watchdog Timing Example
DWD Down
Counter

open window

100% window

open window

open window

50% window

open window

open window

open
window

25% window

open window

open
windowopen
window

12.5% window

open
windowopen
windowopen
window

6.25% window

op.
win

op.
win

op.
win

3.125% window

o
w

o
w

o
w

Figure 12-7. Digital Windowed Watchdog Operation Example (25% Window)
0x1FFFFFF

Preload Register Valueleft shifted 13bits

Open
Window

DWD
Down
Counter

Preload Register
Value left shifted
11bitsDWD can NOT be
served in this period

0

time

CPU
accessto DWD360

set DWD
PreloadConfig25%
DWD
Window

Reset/NMI
enable
DWD

Write
WD
Keys

Real-Time Interrupt (RTI) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Module Operation

www.ti.com

12.2.5 Low Power Modes
Low power modes allow the trade off of the current used during low power versus functionality and fast
wakeup response. All low power modes have the following characteristics:• CPU and system clocks are disabled.
• Flash banks and pump are in sleep mode.
• All peripheral modules are in low power modes and the clocks are disabled (exceptions to this may
occur and would be documented in the specific device data sheet).
Flexibility in enabling and disabling clocks allows for many different low-power modes (see Section 2.4.3).
The operation of the RTI Module is assured in Run, Doze, and Snooze modes. In Sleep mode, all clocks
will be switched off and the RTI will not work.
In Doze and Snooze modes, the RTI is active and is able to wake up the device with compare, time baseand overflow interrupts. The compare interrupts can be used to periodically wake up the device. The
overflow interrupt can be used to notify the operating system that a counter overflow has occurred.
Capturing events generated by the Vectored Interrupt Module (VIM) is also possible since, in both of these
low power modes, the peripheral modules are able to generate interrupts that can trigger capture events.
Capturing events while in Sleep mode is not supported as the clock to the RTI is not active.
NOTE: RTICLK in Doze ModeIn the special case of Doze Mode with PLL off, RTICLK might have a different period thanwith PLL enabled since RTICLK will be derived from the oscillator output. It has to beensured that the VCLK to RTICLK ratio is at least 3:1.

12.2.6 Halting Debug Mode Behaviour
Once the system enters halting debug mode, the behavior of the RTI depends on the COS (continue on
suspend) bit. If the bit is cleared and halting debug mode is active, all counters will stop operation. If the
bit is set to one, all counters will be clocked normally and the RTI will work like in normal mode.

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

361

RTI Control Registers

www.ti.com

12.3 RTI Control Registers
Table 12-1 provides a summary of the registers. The registers support 8-bit, 16-bit, and 32-bit writes. The
offset is relative to the associated peripheral select. See the following sections for detailed descriptions of
the registers. The base address for the control registers is FFFF FC00h. The address locations not listed
are reserved.
Table 12-1. RTI Registers

362

OffsetAcronym

Register Description

Section00h

RTIGCTRL

RTI Global Control Register

04h

RTITBCTRL

Reserved. Do NOT use.

08h

RTICAPCTRLRTI Capture Control Register

Section 12.3.2

0Ch

RTICOMPCTRLRTI Compare Control Register

Section 12.3.3

10h

RTIFRC0

RTI Free Running Counter 0 Register

Section 12.3.4

14h

RTIUC0

RTI Up Counter 0 Register

Section 12.3.5

18h

RTICPUC0

RTI Compare Up Counter 0 Register

Section 12.3.6

20h

RTICAFRC0

RTI Capture Free Running Counter 0 Register

Section 12.3.7

24h

RTICAUC0

RTI Capture Up Counter 0 Register

Section 12.3.8

30h

RTIFRC1

RTI Free Running Counter 1 Register

Section 12.3.9

34h

RTIUC1

RTI Up Counter 1 Register

Section 12.3.10

38h

RTICPUC1

RTI Compare Up Counter 1 Register

Section 12.3.11

40h

RTICAFRC1

RTI Capture Free Running Counter 1 Register

Section 12.3.12

44h

RTICAUC1

RTI Capture Up Counter 1 Register

Section 12.3.13

50h

RTICOMP0

RTI Compare 0 Register

Section 12.3.14

54h

RTIUDCP0

RTI Update Compare 0 Register

Section 12.3.15

58h

RTICOMP1

RTI Compare 1 Register

Section 12.3.16

5Ch

RTIUDCP1

RTI Update Compare 1 Register

Section 12.3.17

60h

RTICOMP2

RTI Compare 2 Register

Section 12.3.18

64h

RTIUDCP2

RTI Update Compare 2 Register

Section 12.3.19

Section 12.3.1

68h

RTICOMP3

RTI Compare 3 Register

Section 12.3.20

6Ch

RTIUDCP3

RTI Update Compare 3 Register

Section 12.3.21

70h

RTITBLCOMPReserved. Do not use.

74h

RTITBHCOMP

Reserved. Do not use.

80h

RTISETINTENARTI Set Interrupt Enable Register

Section 12.3.22

84h

RTICLEARINTENARTI Clear Interrupt Enable Register

Section 12.3.23

88h

RTIINTFLAG

RTI Interrupt Flag Register

Section 12.3.24

90h

RTIDWDCTRL

Digital Watchdog Control Register

Section 12.3.25

94h

RTIDWDPRLD

Digital Watchdog Preload Register

Section 12.3.26

98h

RTIWDSTATUS

Watchdog Status Register

Section 12.3.27

9Ch

RTIWDKEY

RTI Watchdog Key Register

Section 12.3.28

A0h

RTIDWDCNTR

RTI Digital Watchdog Down Counter Register

Section 12.3.29

A4h

RTIWWDRXNCTRL

Digital Windowed Watchdog Reaction Control Register

Section 12.3.30-

A8h

RTIWWDSIZECTRL

Digital Windowed Watchdog Window Size Control Register

Section 12.3.31

ACh

RTIINTCLRENABLE

RTI Compare Interrupt Clear Enable Register

Section 12.3.32

B0h

RTICOMP0CLR

RTI Compare 0 Clear Register

Section 12.3.33

B4h

RTICOMP1CLR

RTI Compare 1 Clear Register

Section 12.3.34

B8h

RTICOMP2CLR

RTI Compare 2 Clear Register

Section 12.3.35

BCh

RTICOMP3CLR

RTI Compare 3 Clear Register

Section 12.3.36

Real-Time Interrupt (RTI) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

RTI Control Registers

www.ti.com

NOTE: Writes to Reserved registers may clear the pending RTI interrupt.

12.3.1 RTI Global Control Register (RTIGCTRL)
The global control register starts/stops the counters and selects the signal compared with the timebase
control circuit. This register is shown in Figure 12-8 and described in Table 12-2.
Figure 12-8. RTI Global Control Register (RTIGCTRL) [offset = 00]
31

15

20

19

16

Reserved

Reserved

R-0

R/WP-0
1

0

COS

14
Reserved

2

CNT1EN

CNT0EN

R/WP-0R-0

R/WP-0R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 12-2. RTI Global Control Register (RTIGCTRL) Field Descriptions
Bit

Field

31-20

Reserved

0

Reads return 0. Writes have no effect.

19-16

Reserved

0

Reserved. Do NOT use.

15

COS

14-2

Reserved

1

CNT1EN

0

Value

Description

Continue on suspend. This bit determines if both counters are stopped when the device goes into
halting debug mode or if they continue counting.
0Counters are stopped while in halting debug mode.

1

Counters are running while in halting debug mode.

0

Reads return 0. Writes have no effect.
Counter 1 enable. This bit starts and stops counter block 1 (RTIUC1 and RTIFRC1).

0

Counter block 1 is stopped.

1

Counter block 1 is running.

CNT0ENCounter 0 enable. This bit starts and stops counter block 0 (RTIUC0 and RTIFRC0).
0Counter block 0 is stopped.

1

Counter block 0 is running.

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

363

RTI Control Registers

www.ti.com

12.3.2 RTI Capture Control Register (RTICAPCTRL)
The capture control register controls the capture source for the counters. This register is shown in
Figure 12-9 and described in Table 12-3.
Figure 12-9. RTI Capture Control Register (RTICAPCTRL) [offset = 08h]
31

8
Reserved
R-0
7

1

0

Reserved

2

CAPCNTR1CAPCNTR0

R-0

R/WP-0R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 12-3. RTI Capture Control Register (RTICAPCTRL) Field Descriptions
Bit

Field

31-2

Reserved

1

CAPCNTR1

0

364

Value
0

Description
Reads return 0. Writes have no effect.
Capture counter 1. This bit determines which external interrupt source triggers a capture event of
RTIUC1 and RTIFRC1.

0

Capture of RTIUC1/ RTIFRC1 is triggered by capture event source 0.

1

Capture of RTIUC1/ RTIFRC1 is triggered by capture event source 1.

CAPCNTR0

Capture counter 0. This bit determines which external interrupt source triggers a capture event of
RTIUC0 and RTIFRC0.
0

Capture of RTIUC0/ RTIFRC0 is triggered by capture event source 0.

1

Capture of RTIUC0/ RTIFRC0 is triggered by capture event source 1.

Real-Time Interrupt (RTI) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

RTI Control Registers

www.ti.com

12.3.3 RTI Compare Control Register (RTICOMPCTRL)
The compare control register controls the source for the compare registers. This register is shown in
Figure 12-10 and described in Table 12-4.
Figure 12-10. RTI Compare Control Register (RTICOMPCTRL) [offset = 0Ch]
31

16
Reserved
R-0
15

13

12

11

9

8

Reserved

COMPSEL3

Reserved

COMPSEL2

R-0

R/WP-0R-0

R/WP-0

7

5

4

3

1

0

Reserved

COMPSEL1

Reserved

COMPSEL0

R-0

R/WP-0R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 12-4. RTI Compare Control Register (RTICOMPCTRL) Field Descriptions
Bit

Field

31-13

Reserved

12

COMPSEL3

11-9

Reserved

8

COMPSEL2

7-5

Reserved

4

COMPSEL1

3-1

Reserved

0

COMPSEL0

Value
0

Description
Reads return 0. Writes have no effect.
Compare select 3. This bit determines the counter with which the compare value held in compare
register 3 (RTICOMP3) is compared.

0

Value will be compared with RTIFRC0.

1

Value will be compared with RTIFRC1.

0

Reads return 0. Writes have no effect.
Compare select 2. This bit determines the counter with which the compare value held in compare
register 2 (RTICOMP2) is compared.

0

Value will be compared with RTIFRC0.

1

Value will be compared with RTIFRC1.

0

Reads return 0. Writes have no effect.
Compare select 1. This bit determines the counter with which the compare value held in compare
register 1 (RTICOMP1) is compared.

0

Value will be compared with RTIFRC0.

1

Value will be compared with RTIFRC1.

0

Reads return 0. Writes have no effect.
Compare select 0. This bit determines the counter with which the compare value held in compare
register 0 (RTICOMP0) is compared.

0

Value will be compared with RTIFRC0.

1

Value will be compared with RTIFRC1.

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

365

RTI Control Registers

www.ti.com

12.3.4 RTI Free Running Counter 0 Register (RTIFRC0)
The free running counter 0 register holds the current value of free running counter 0. This register isshown in Figure 12-11 and described in Table 12-5.
Figure 12-11. RTI Free Running Counter 0 Register (RTIFRC0) [offset = 10h]
31

16
FRC0
R/WP-015

0FRC0
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-5. RTI Free Running Counter 0 Register (RTIFRC0) Field Descriptions
Bit

Field

Value

31-0

FRC0

0-FFFF FFFFh

Description
Free running counter 0. This registers holds the current value of the free running counter 0.
A read of this counter returns the current value of the counter.
The counter can be preset by writing (in privileged mode only) to this register. The counterincrements then from this written value upwards.
Note: If counters must be preset, they must be disabled in the RTIGCTRL register toensure consistency between RTIUC0 and RTIFRC0.

12.3.5 RTI Up Counter 0 Register (RTIUC0)
The up counter 0 register holds the current value of prescale counter. This register is shown in Figure 1212 and described in Table 12-6.
Figure 12-12. RTI Up Counter 0 Register (RTIUC0) [offset = 14h]
31

16
UC0
R/WP-015

0UC0
R/WP-0

LLEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-6. RTI Up Counter 0 Register (RTIUC0) Field Descriptions
Bit

Field

Value

31-0

UC0

0-FFFF FFFFh

Description
Up counter 0. This register holds the current value of the up counter 0 and prescales the RTI
clock. It will be only updated by a previous read of free running counter 0 (RTIFRC0). Thismethod of updating effectively gives a 64-bit read of both counters, without having the problem
of a counter being updated between two consecutive reads on up counter 0 (RTIUC0) and freerunning counter 0 (RTIFRC0).
A read of this counter returns the value of the counter at the time RTIFRC0 was read.
A write to this counter presets it with a value. The counter then increments from this written
value upwards.
Note: If counters must be preset, they must be disabled in the RTIGCTRL register to ensure
consistency between RTIUC0 and RTIFRC0.
Note: If the preset value is bigger than the compare value stored in register RTICPUC0,
then it can take a long time until a compare matches, since RTIUC0 has to count up until
it overflows.

366

Real-Time Interrupt (RTI) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

RTI Control Registers

www.ti.com

12.3.6 RTI Compare Up Counter 0 Register (RTICPUC0)
The compare up counter 0 register holds the value to be compared with prescale counter 0 (RTIUC0).
This register is shown in Figure 12-13 and described in Table 12-7.
Figure 12-13. RTI Compare Up Counter 0 Register (RTICPUC0) [offset = 18h]
31

16
CPUC0
R/WP-0150CPUC0
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-7. RTI Compare Up Counter 0 Register (RTICPUC0) Field Descriptions
Bit

Field

Value

31-0

CPUC0

0-FFFF FFFFh

Description
Compare up counter 0. This register holds the value that is compared with the up counter 0.
When the compare shows a match, the free running counter 0 (RTIFRC0) is incremented.
RTIUC0 is set to 0 when the counter value matches the RTICPUC0 value. The value set in thisregister prescales the RTI clock.
If CPUC0 = 0, then:
fFRC0 = RTICLK/(232 + 1) (Setting CPUC0 equal to 0 is not recommended. Doing so will hold theup counter at 0 for 2 RTICLK cycles after it overflows from FFFF FFFFh to 0.)
If CPUC0 ≠ 0, then:
fFRC0 = RTICLK/(RTICPUC0 + 1)
A read of this register returns the current compare value.
A write to this register:• If TBEXT = 0, the compare value is updated.
• If TBEXT = 1, the compare value is unchanged.

12.3.7 RTI Capture Free Running Counter 0 Register (RTICAFRC0)
The capture free running counter 0 register holds the free running counter 0 on external events. This
register is shown in Figure 12-14 and described in Table 12-8.
Figure 12-14. RTI Capture Free Running Counter 0 Register (RTICAFRC0) [offset = 20h]
31

16
CAFRC0
R-0

15

0
CAFRC0
R-0

LEGEND: R = Read only; -n = value after reset

Table 12-8. RTI Capture Free Running Counter 0 Register (RTICAFRC0) Field Descriptions
Bit

Field

31-0

CAFRC0Value
0-FFFF FFFFh

Description
Capture free running counter 0. This register captures the current value of the free runningcounter 0 (RTIFRC0) when an event occurs, controlled by the external capture control block.
A read of this register returns the value of RTIFRC0 on a capture event.

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

367

RTI Control Registers

www.ti.com

12.3.8 RTI Capture Up Counter 0 Register (RTICAUC0)
The capture up counter 0 register holds the current value of prescale counter 0 on external events. This
register is shown in Figure 12-15 and described in Table 12-9.
Figure 12-15. RTI Capture Up Counter 0 Register (RTICAUC0) [offset = 24]
31

16
CAUC0
R-0

15

0
CAUC0
R-0

LEGEND: R = Read only; -n = value after reset

Table 12-9. RTI Capture Up Counter 0 Register (RTICAUC0) Field Descriptions
Bit

Field

Value

31-0

CAUC0

0-FFFF FFFFh

Description
Capture up counter 0. This register captures the current value of the up counter 0 (RTIUC0)
when an event occurs, controlled by the external capture control block.
Note: The read sequence must be the same as with RTIUC0 and RTIFRC0. Therefore, theRTICAFRC0 register must be read before the RTICAUC0 register is read. This sequence
ensures that the value of the RTICAUC0 register is the corresponding value to the
RTICAFRC0 register, even if another capture event happens in between the two reads.
A read of this register returns the value of RTIUC0 on a capture event.

12.3.9 RTI Free Running Counter 1 Register (RTIFRC1)
The free running counter 1 register holds the current value of the free running counter 1. This register isshown in Figure 12-16 and described in Table 12-10.
Figure 12-16. RTI Free Running Counter 1 Register (RTIFRC1) [offset = 30h]
31

16
FRC1
R/WP-015

0FRC1
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-10. RTI Free Running Counter 1 Register (RTIFRC1) Field Descriptions
Bit

Field

Value

31-0

FRC1

0-FFFF FFFFh

Description
Free running counter 1. This register holds the current value of the free running counter 1 andwill be updated continuously.
A read of this register returns the current value of the counter.
A write to this register presets the counter. The counter increments then from this written value
upwards.
Note: If counters must be preset, they must be disabled in the RTIGCTRL register toensure consistency between RTIUC1 and RTIFRC1.

368

Real-Time Interrupt (RTI) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

RTI Control Registers

www.ti.com

12.3.10 RTI Up Counter 1 Register (RTIUC1)
The up counter 1 register holds the current value of the prescale counter 1. This register is shown in
Figure 12-17 and described in Table 12-11.
Figure 12-17. RTI Up Counter 1 Register (RTIUC1) [offset = 34h]
31

16
UC1
R/WP-015

0UC1
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-11. RTI Up Counter 1 Register (RTIUC1) Field Descriptions
Bit

Field

Value

31-0

UC1

0-FFFF FFFFh

Description
Up counter 1. This register holds the current value of the up counter 1 and prescales the RTI
clock. It will be only updated by a previous read of free running counter 1 (RTIFRC1). Thismethod of updating effectively gives a 64-bit read of both counters, without having the problem
of a counter being updated between two consecutive reads on RTIUC1 and RTIFRC1.
A read of this register will return the value of the counter when the RTIFRC1 was read.
A write to this register presets the counter. The counter then increments from this written value
upwards.
Note: If counters must be preset, they must be disabled in the RTIGCTRL register toensure consistency between RTIUC1 and RTIFRC1.
Note: If the preset value is bigger than the compare value stored in register RTICPUC1,
then it can take a long time until a compare matches, since RTIUC1 has to count up until
it overflows.

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

369

RTI Control Registers

www.ti.com

12.3.11 RTI Compare Up Counter 1 Register (RTICPUC1)
The compare up counter 1 register holds the value compared with prescale counter 1. This register isshown in Figure 12-18 and described in Table 12-12.
Figure 12-18. RTI Compare Up Counter 1 Register (RTICPUC1) [offset = 38h]
31

16
CPUC1
R/WP-015

0CPUC1
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-12. RTI Compare Up Counter 1 Register (RTICPUC1) Field Descriptions
Bit

Field

Value

31-0

CPUC1

0-FFFF FFFFh

Description
Compare up counter 1. This register holds the compare value, which is compared with the up
counter 1. When the compare matches, the free running counter 1 (RTIFRC1) is incremented.
The up counter is cleared to zero when the counter value matches the CPUC1 value. The value
set in this prescales the RTI clock according to the following formula:
If CPUC1 = 0, then:
fFRC0 = RTICLK/(232 + 1) (Setting CPUC1 equal to 0 is not recommended. Doing so will hold theup counter at 0 for 2 RTICLK cycles after it overflows from FFFF FFFFh to 0.)
If CPUC1 ≠ 0, then:
fFRC1 = RTICLK/(RTICPUC1 + 1)
A read of this register returns the current compare value.
A write to this register updates the compare value.

370

Real-Time Interrupt (RTI) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

RTI Control Registers

www.ti.com

12.3.12 RTI Capture Free Running Counter 1 Register (RTICAFRC1)
The capture free running counter 1 register holds the current value of free running counter 1 on external
events. This register is shown in Figure 12-19 and described in Table 12-13.
Figure 12-19. RTI Capture Free Running Counter 1 Register (RTICAFRC1) [offset = 40h]
31

16
CAFRC1
R-0

15

0
CAFRC1
R-0

LEGEND: R = Read only; -n = value after reset

Table 12-13. RTI Capture Free Running Counter 1 Register (RTICAFRC1) Field Descriptions
Bit

Field

31-0

CAFRC1Value
0-FFFF FFFFh

Description
Capture free running counter 1. This register captures the current value of the free runningcounter 1 (RTIFRC1) when an event occurs, controlled by the external capture control block.
A read of this register returns the value of RTIFRC1 on a capture event.

12.3.13 RTI Capture Up Counter 1 Register (RTICAUC1)
The capture up counter 1 register holds the current value of prescale counter 1 on external events. This
register is shown in Figure 12-20 and described in Table 12-14.
Figure 12-20. RTI Capture Up Counter 1 Register (RTICAUC1) [offset = 44h]
31

16
CAUC1
R-0

15

0
CAUC1
R-0

LEGEND: R = Read only; -n = value after reset

Table 12-14. RTI Capture Up Counter 1 Register (RTICAUC1) Field Descriptions
Bit

Field

Value

31-0

CAUC1

0-FFFF FFFFh

Description
Capture up counter 1. This register captures the current value of the up counter 1 (RTIUC1)
when an event occurs, controlled by the external capture control block.
Note: The RTICAFRC1 register must be read before the RTICAUC1 register is read. Thissequence ensures that the value of the RTICAUC1 register is the corresponding value tothe RTICAFRC1 register, even if another capture event happens in between the tworeads.
A read of this register returns the value of RTIUC1 on a capture event.

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

371

RTI Control Registers

www.ti.com

12.3.14 RTI Compare 0 Register (RTICOMP0)The compare 0 register holds the value to be compared with the counters. This register is shown in
Figure 12-21 and described in Table 12-15.
Figure 12-21. RTI Compare 0 Register (RTICOMP0) [offset = 50h]
31

16
COMP0
R/WP-015

0COMP0
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-15. RTI Compare 0 Register (RTICOMP0) Field Descriptions
Bit

Field

Value

31-0

COMP0

0-FFFF FFFFh

Description
Compare 0. This registers holds a value that is compared with the counter selected in thecompare control logic. If RTIFRC0 or RTIFRC1, depending on the counter selected, matches
the compare value, an interrupt is flagged.
A read of this register will return the current compare value.
A write to this register (in privileged mode only) will update the compare register with a newcompare value.

12.3.15 RTI Update Compare 0 Register (RTIUDCP0)
The update compare 0 register holds the value to be added to the compare register 0 value on a compare
match. This register is shown in Figure 12-22 and described in Table 12-16.
Figure 12-22. RTI Update Compare 0 Register (RTIUDCP0) [offset = 54h]
31

16
UDCP0
R/WP-0150UDCP0
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-16. RTI Update Compare 0 Register (RTIUDCP0) Field Descriptions
Bit

Field

Value

31-0

UDCP0

0-FFFF FFFFh

Description
Update compare 0. This register holds a value that is added to the value in the compare 0(RTICOMP0) register each time a compare matches. This function allows periodic interrupts tobe generated without software intervention.
A read of this register will return the value to be added to the RTICOMP0 register on the nextcompare match.
A write to this register will provide a new update value.

372

Real-Time Interrupt (RTI) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

RTI Control Registers

www.ti.com

12.3.16 RTI Compare 1 Register (RTICOMP1)
The compare 1 register holds the value to be compared to the counters. This register is shown in
Figure 12-23 and described in Table 12-17.
Figure 12-23. RTI Compare 1 Register (RTICOMP1) [offset = 58h]
31

16
COMP1
R/WP-015

0COMP1
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-17. RTI Compare 1 Register (RTICOMP1) Field Descriptions
Bit

Field

Value

31-0

COMP1

0-FFFF FFFFh

Description
Compare 1. This register holds a value that is compared with the counter selected in thecompare control logic. If RTIFRC0 or RTIFRC1, depending on the counter selected, matches
this compare value, an interrupt is flagged.
A read of this register will return the current compare value.
A write to this register will update the compare register with a new compare value.

12.3.17 RTI Update Compare 1 Register (RTIUDCP1)
The update compare 1 register holds the value to be added to the compare register 1 value on a compare
match. This register is shown in Figure 12-24 and described in Table 12-18.
Figure 12-24. RTI Update Compare 1 Register (RTIUDCP1) [offset = 5Ch]
31

16
UDCP1
R/WP-015

0UDCP1
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-18. RTI Update Compare 1 Register (RTIUDCP1) Field Descriptions
Bit

Field

Value

31-0

UDCP1

0-FFFF FFFFh

Description
Update compare 1. This register holds a value that is added to the value in the RTICOMP1
register each time a compare matches. This process allows periodic interrupts to be generated
without software intervention.
A read of this register will return the value to be added to the RTICOMP1 register on the nextcompare match. .
A write to this register will provide a new update value.

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

373

RTI Control Registers

www.ti.com

12.3.18 RTI Compare 2 Register (RTICOMP2)
The compare 2 register holds the value to be compared to the counters. This register is shown in
Figure 12-25 and described in Table 12-19.
Figure 12-25. RTI Compare 2 Register (RTICOMP2) [offset = 60h]
31

16
COMP2
R/WP-015

0COMP2
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-19. RTI Compare 2 Register (RTICOMP2) Field Descriptions
Bit

Field

Value

31-0

COMP2

0-FFFF FFFFh

Description
Compare 2. This register holds a value that is compared with the counter selected in thecompare control logic. If RTIFRC0 or RTIFRC1, depending on the counter selected, matches
this compare value, an interrupt is flagged.
A read of this register will return the current compare value.
A write to this register (in privileged mode only) will provide a new compare value.

12.3.19 RTI Update Compare 2 Register (RTIUDCP2)
The update compare 2 register holds the value to be added to the compare register 2 value on a compare
match. This register is shown in Figure 12-26 and described in Table 12-20.
Figure 12-26. RTI Update Compare 2 Register (RTIUDCP2) [offset = 64h]
31

16
UDCP2
R/WP-015

0UDCP2
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-20. RTI Update Compare 2 Register (RTIUDCP2) Field Descriptions
Bit

Field

Value

31-0

UDCP2

0-FFFF FFFFh

Description
Update compare 2. This register holds a value that is added to the value in the RTICOMP2
register each time a compare matches. This process makes it possible to generate periodic
interrupts without software intervention.
A read of this register will return the value to be added to the RTICOMP2 register on the nextcompare match.
A write to this register will provide a new update value.

374

Real-Time Interrupt (RTI) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

RTI Control Registers

www.ti.com

12.3.20 RTI Compare 3 Register (RTICOMP3)
The compare 3 register holds the value to be compared to the counters. This register is shown in
Figure 12-27 and described in Table 12-21.
Figure 12-27. RTI Compare 3 Register (RTICOMP3) [offset = 68h]
31

16
COMP3
R/WP-015

0COMP3
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-21. RTI Compare 3 Register (RTICOMP3) Field Descriptions
Bit

Field

Value

31-0

COMP3

0-FFFF FFFFh

Description
Compare 3. This register holds a value that is compared with the counter selected in thecompare control logic. If RTIFRC0 or RTIFRC1, depending on the counter selected, matches
this compare value, an interrupt is flagged.
A read of this register will return the current compare value.
A write to this register will provide a new compare value.

12.3.21 RTI Update Compare 3 Register (RTIUDCP3)
The update compare 3 register holds the value to be added to the compare register 3 value on a compare
match. This register is shown in Figure 12-28 and described in Table 12-22.
Figure 12-28. RTI Update Compare 3 Register (RTIUDCP3) [offset = 6Ch]
31

16
UDCP3
R/WP-015

0UDCP3
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-22. RTI Update Compare 3 Register (RTIUDCP3) Field Descriptions
Bit

Field

Value

31-0

UDCP3

0-FFFF FFFFh

Description
Update compare 3. This register holds a value that is added to the value in the RTICOMP3
register each time a compare matches. This process makes it possible to generate periodic
interrupts without software intervention.
A read of this register will return the value to be added to the RTICOMP3 register on the nextcompare match.
A write to this register will provide a new update value.

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

375

RTI Control Registers

www.ti.com

12.3.22 RTI Set Interrupt Enable Register (RTISETINTENA)
This register prevents the necessity of a read-modify-write operation if a particular interrupt should beenabled. This register is shown in Figure 12-29 and described in Table 12-23.
Figure 12-29. RTI Set Interrupt Control Register (RTISETINTENA) [offset = 80h]31

24
Reserved
R-0

23

18

17

16

Reserved

19

SETOVL1INTSETOVL0INTSETTBINT

R-0

R/WP-0R/WP-0R/WP-015

8
Reserved
R-0

7

3

2

1

0

Reserved

4

SETINT3

SETINT2

SETINT1

SETINT0

R-0

R/WP-0R/WP-0R/WP-0R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 12-23. RTI Set Interrupt Control Register (RTISETINTENA) Field Descriptions
Bit

Field

31-19

Reserved

18

Value
0

SETOVL1INT

Description
Reads return 0. Writes have no effect.
Set free running counter 1 overflow interrupt.

0

Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.

1
17

SETOVL0INT

Read or Write: Interrupt is enabled.
Set free running counter 0 overflow interrupt.

0

Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.

1
16

SETTBINT

Read or Write: Interrupt is enabled.
Set timebase interrupt.

0

Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.

15-4

Reserved

3

SETINT3

1

Read or Write: Interrupt is enabled.

0

Reads return 0. Writes have no effect.
Set compare interrupt 3.

0

Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.

1
2

SETINT2

Read or Write: Interrupt is enabled.
Set compare interrupt 2.

0

Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.

1
1

SETINT1

Read or Write: Interrupt is enabled.
Set compare interrupt 1.

0

Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.

1376

Read or Write: Interrupt is enabled.

Real-Time Interrupt (RTI) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

RTI Control Registers

www.ti.com

Table 12-23. RTI Set Interrupt Control Register (RTISETINTENA) Field Descriptions (continued)
Bit

Field

0

SETINT0

Value

Description
Set compare interrupt 0.

0Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.

1

Read or Write: Interrupt is enabled.

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

377

RTI Control Registers

www.ti.com

12.3.23 RTI Clear Interrupt Enable Register (RTICLEARINTENA)
This register prevents the necessity of a read-modify-write operation if a particular interrupt should bedisabled. This register is shown in Figure 12-30 and described in Table 12-24.
Figure 12-30. RTI Clear Interrupt Control Register (RTICLEARINTENA) [offset = 84h]
31

24
Reserved
R-0

23

19

18

Reserved

CLEAROVL1INT

R-0

R/WP-01716

CLEAROVL0INT

CLEARTBINT

R/WP-0R/WP-015

8
Reserved
R-0

7

3

2

1

0

Reserved

4

CLEARINT3

CLEARINT2

CLEARINT1

CLEARINT0

R-0

R/WP-0R/WP-0R/WP-0R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 12-24. RTI Clear Interrupt Control Register (RTICLEARINTENA) Field Descriptions
Bit

Field

31-19

Reserved

18

Value
0

CLEAROVL1INT

Description
Reads return 0. Writes have no effect.
Clear free running counter 1 overflow interrupt.

0

Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.

1

Read: Interrupt is enabled.
Write: Interrupt is disabled.

17

CLEAROVL0INT

Clear free running counter 0 overflow interrupt.
0

Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.

1

Read: Interrupt is enabled.
Write: Interrupt is disabled.

16

CLEARTBINTClear timebase interrupt.
0

Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.

1

Read: Interrupt is enabled.
Write: Interrupt is disabled.

15-4

Reserved

3

CLEARINT30

Reads return 0. Writes have no effect.
Clear compare interrupt 3.

0

Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.

1

Read: Interrupt is enabled.
Write: Interrupt is disabled.

2

CLEARINT2

Clear compare interrupt 2.
0

Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.

1

Read: Interrupt is enabled.
Write: Interrupt is disabled.

378

Real-Time Interrupt (RTI) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

RTI Control Registers

www.ti.com

Table 12-24. RTI Clear Interrupt Control Register (RTICLEARINTENA) Field Descriptions (continued)
Bit

Field

1

CLEARINT1

Value

Description
Clear compare interrupt 1.

0

Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.

1

Read: Interrupt is enabled.
Write: Interrupt is disabled.

0

CLEARINT0

Clear compare interrupt 0.
0Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.

1

Read: Interrupt is enabled.
Write: Interrupt is disabled.

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

379

RTI Control Registers

www.ti.com

12.3.24 RTI Interrupt Flag Register (RTIINTFLAG)The corresponding flags are set at every compare match of the RTIFRCx and RTICOMPx values, whether
the interrupt is enabled or not. This register is shown in Figure 12-31 and described in Table 12-25.
Figure 12-31. RTI Interrupt Flag Register (RTIINTFLAG) [offset = 88h]31

24
Reserved
R-0

23

19

17

16

OVL1INT18

OVL0INTTBINT

R/W1CP-0

R/W1CP-0

R/W1CP-0

Reserved
R-0
15

8
Reserved
R-0

7

3

2

1

0

Reserved

4

INT3

INT2

INT1

INT0

R-0

R/W1CP-0

R/W1CP-0

R/W1CP-0

R/W1CP-0

LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -n = value after reset

Table 12-25. RTI Interrupt Flag Register (RTIINTFLAG) Field Descriptions
Bit

Field

31-19

Reserved

18

OVL1INT

Value
0

Description
Reads return 0. Writes have no effect.
Free running counter 1 overflow interrupt flag. This bit determines if an interrupt is pending.

0

Read: No interrupt is pending.
Write: Bit is unchanged.

1

Read: Interrupt is pending.
Write: Bit is cleared to 0.

17

OVL0INTFree running counter 0 overflow interrupt flag. This bit determines if an interrupt is pending.
0

Read: No interrupt is pending.
Write: Bit is unchanged.

1

Read: Interrupt is pending.
Write: Bit is cleared to 0.

16

TBINT

Timebase interrupt flag. This flag is set when the TBEXT bit is cleared by detection of a missing
external clock edge. It will not be set by clearing TBEXT by software. It determines if an interrupt is
pending.
0

Read: No interrupt is pending.
Write: Bit is unchanged.

1

Read: Interrupt is pending.
Write: Bit is cleared to 0.

15-4
3

Reserved0

INT3

Reads return 0. Writes have no effect.
Interrupt flag 3. These bits determine if an interrupt due to a Compare 3 match is pending.

0

Read: No interrupt is pending.
Write: Bit is unchanged.

1

Read: Interrupt is pending.
Write: Bit is cleared to 0.

2

INT2

Interrupt flag 2. These bits determine if an interrupt due to a Compare 2 match is pending.
0

Read: No interrupt is pending.
Write: Bit is unchanged.

1

Read: Interrupt is pending.
Write: Bit is cleared to 0.

380

Real-Time Interrupt (RTI) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

RTI Control Registers

www.ti.com

Table 12-25. RTI Interrupt Flag Register (RTIINTFLAG) Field Descriptions (continued)
Bit

Field

1

INT1

Value

Description
Interrupt flag 1. These bits determine if an interrupt due to a Compare 1 match is pending.

0

Read: No interrupt is pending.
Write: Bit is unchanged.

1

Read: Interrupt is pending.
Write: Bit is cleared to 0.

0

INT0

Interrupt flag 0. These bits determine if an interrupt due to a Compare 0 match is pending.
0

Read: No interrupt is pending.
Write: Bit is unchanged.

1

Read: Interrupt is pending.
Write: Bit is cleared to 0.

12.3.25 Digital Watchdog Control Register (RTIDWDCTRL)
The software has to write to the DWDCTRL field in order to enable the DWD, as described below. Onceenabled, the watchdog can only be disabled by a system reset. The application cannot disable thewatchdog. However should the RTICLK source be changed to a source that is unimplemented it will havethe same effect as disabling the watchdog. This register is shown in Figure 12-31 and described inTable 12-25.
Figure 12-32. Digital Watchdog Control Register (RTIDWDCTRL) [offset = 90h]
31

16
DWDCTRL
R/WP-5312h

150
DWDCTRL
R/WP-ACEDhLEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-26. Digital Watchdog Control Register (RTIDWDCTRL) Field Descriptions
Bit

Field

31-0

DWDCTRL

Value

Description
Digital Watchdog Control.

5312 ACEDhRead: DWD counter is disabled.
Write: State of DWD counter is unchanged (stays enabled or disabled).

A985 59DAh

Read: DWD counter is enabled.
Write: DWD counter is enabled.

All other values

Read: DWD counter state is unchanged (enabled or disabled).
Write: State of DWD counter is unchanged (stays enabled or disabled).
Note: Once the enable value is written, all other future writes are blocked. In other words, once
DWD is enabled, it can only be disabled by system reset or power on reset. However should
the RTICLK source be changed to a source that is unimplemented it will have the same effectas disabling the watchdog.

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

381

RTI Control Registers

www.ti.com

12.3.26 Digital Watchdog Preload Register (RTIDWDPRLD)
This register sets the expiration time of the DWD. This register is shown in Figure 12-31 and described inTable 12-25.
Figure 12-33. Digital Watchdog Preload Register (RTIDWDPRLD) [offset = 94h]
31

16
Reserved
R-0

15

12

11

0

Reserved

DWDPRLD

R-0

R/WP-FFFh

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 12-27. Digital Watchdog Preload Register (RTIDWDPRLD) Field Descriptions
Bit

Field

Value

31-12

Reserved

0

11-0

DWDPRLD

0-FFFhDescription
Reads return 0 and writes have no effect.
Digital Watchdog Preload Value.
Read: The current preload value.
Write: Set the preload value. The DWD preload register can be configured only when the DWD isdisabled. Therefore, the application can only configure the DWD preload register before it enables
the DWD down counter.
The expiration time of the DWD Down Counter can be determined with following equation:
texp = (DWDPRLD+1) × 213 / RTICLK1
where: DWDPRLD = 0...4095

382

Real-Time Interrupt (RTI) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

RTI Control Registers

www.ti.com

12.3.27 Watchdog Status Register (RTIWDSTATUS)
This register records the status of the DWD. The values of the following status bits will not be affected bya soft reset. These bits are cleared by a power-on reset, or by a write of 1. These bits can be used fordebug purposes. This register is shown in Figure 12-31 and described in Table 12-25.
Figure 12-34. Watchdog Status Register (RTIWDSTATUS) [offset = 98h]
31

8
Reserved
R-0
7

5

4

3

2

1

0

Reserved

6

DWWD ST

END TIME
VIOL

START TIME
VIOL

KEY STDWD ST

Reserved

R-0

R/W1CP-x

R/W1CP-x

R/W1CP-x

R/W1CP-x

R/W1CP-x

R-0

LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; x = value is unknown after reset; -n = value
after reset

Table 12-28. Watchdog Status Register (RTIWDSTATUS) Field Descriptions
Bit

Field

31-6

Reserved

5

DWWD ST

Value
0

Description
Reads return 0. Writes have no effect.
Windowed Watchdog Status.

0

Read: No time-window violation has occurred.
Write: Leaves the current value unchanged.

1

Read: Time-window violation has occurred. The watchdog has generated either a system resetor a non-maskable interrupt to the CPU in this case.
Write: Bit is cleared to 0. This will also clear all other status flags in the RTIWDSTATUS
register. Clearing of the status flags will deassert the non-maskable interrupt generated due toviolation of the DWWD.

4

END TIME VIOL

Windowed Watchdog End Time Violation Status. This bit indicates whether the Watchdog
counter expired.
0

Read: No end-time window violation has occurred.
Write: Leaves the current value unchanged.

1

Read: End-time defined by the windowed watchdog configuration has been violated.
Write: Bit is cleared to 0.

3

START TIME VIOL

Windowed Watchdog Start Time Violation Status. This bit indicates whether the key is written
before the watchdog window opened up.
0

Read: No start-time window violation has occurred.
Write: Leaves the current value unchanged.

1

Read: Start-time defined by the windowed watchdog configuration has been violated.
Write: Bit is cleared to 0.

2

KEY ST

Watchdog key status. This bit indicates a reset or NMI generated by a wrong key or key
sequence written to the RTIWDKEY register.
0

Read: No wrong key or key-sequence written.
Write: Bit is unchanged.

1

Read: Wrong key or key-sequence written to RTIWDKEY register.
Write: Bit is cleared to 0.

1

DWD STDWD status. This bit is equivalent to bit END TIME VIOL.
0

Read: No reset or NMI was generated.
Write: Bit is unchanged.

1

Read: Reset or NMI was generated.
Write: Bit is cleared to 0.

0

Reserved

0

Reads return 0. Writes have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

383

RTI Control Registers

www.ti.com

12.3.28 RTI Watchdog Key Register (RTIWDKEY)This register must be written with the correct written key values to serve the watchdog. This register isshown in Figure 12-35 and described in Table 12-29.
NOTE: It has to be taken into account that the write to the RTIWDKEY register takes 3 VCLK cycles.

Figure 12-35. RTI Watchdog Key Register (RTIDWDKEY) [offset = 9Ch]
31

16
Reserved
R-0

15

0
WDKEY
R/WP-A35ChLEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 12-29. RTI Watchdog Key Register (RTIDWDKEY) Field Descriptions
Bit

Field

31-16

Reserved

Value
0

15-0

WDKEY

0-FFFFh

Description
Reads return 0 and writes have no effect.
Watchdog key. These bits provide the key sequence location.
Reads returns the current WDKEY value.
A write of E51Ah followed by A35Ch in two separate write operations defines the key sequence
and reloads the DWD. Writing any other value causes a reset or NMI, as shown in Table 12-30.
Writing any other value will cause the WDKEY to reset to A35Ch.

Table 12-30. Example of a WDKEY Sequence

384

Step

Value Written to WDKEY

Result1

A35Ch

No action

2

A35Ch

No action

3

E51Ah

WDKEY is enabled for reset or NMI by next A35Ch.

4

E51Ah

WDKEY is enabled for reset or NMI by next A35Ch.

5

E51Ah

WDKEY is enabled for reset or NMI by next A35Ch.

6

A35Ch

Watchdog is reset.

7

A35Ch

No action

8

E51Ah

WDKEY is enabled for reset or NMI by next A35Ch.

9

A35Ch

Watchdog is reset.

10

E51Ah

WDKEY is enabled for reset or NMI by next A35Ch.

11

2345h

System reset or NMI; incorrect value written to WDKEY.

Real-Time Interrupt (RTI) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

RTI Control Registers

www.ti.com

12.3.29 RTI Digital Watchdog Down Counter (RTIDWDCNTR)
This register provides the current value of the DWD down counter. This register is shown in Figure 12-36
and described in Table 12-31.
Figure 12-36. RTI Watchdog Down Counter Register (RTIDWDCNTR) [offset = A0h]
31

25

24

16

Reserved

DWDCNTR

R-0

R-1FFh150
DWDCNTR
R-FFFFhLEGEND: R = Read only; -n = value after reset

Table 12-31. RTI Watchdog Down Counter Register (RTIDWDCNTR) Field Descriptions
Bit

Field

Value

31-25

Reserved

024-0

DWDCNTR

0-1FF FFFFh

Description
Reads return 0 and writes have no effect.
DWD down counter.
Reads return the current counter value.

12.3.30 Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL)
This register selects the DWWD reaction if the watchdog is serviced outside the time window. This register
is shown in Figure 12-37 and described in Table 12-32.
Figure 12-37. Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) [offset = A4h]31

16
Reserved
R-0

15

4

3

0

ReservedWWDRXN

R-0

R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 12-32. Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) Field Descriptions
Bit

Field

31-4

Reserved

3-0

WWDRXN

Value
0

Description
Reads return 0 and writes have no effect.
The DWWD reaction.

5h

The windowed watchdog will cause a reset if the watchdog is serviced outside the time window
defined by the configuration, or if the watchdog is not serviced at all.

Ah

The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog isserviced outside the time window defined by the configuration, or if the watchdog is not serviced
at all.

All other values

The windowed watchdog will cause a reset if the watchdog is serviced outside the time window
defined by the configuration, or if the watchdog is not serviced at all.
Note: The DWWD reaction can be selected by the application even when the DWWD counter isalready enabled. If a change to the WWDRXN is made before the watchdog service window is
opened, then the change in the configuration takes effect immediately. If a change to the
WWDRXN is made when the watchdog service window is already open, then the change in
configuration takes effect only after the watchdog is serviced.

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

385

RTI Control Registers

www.ti.com

12.3.31 Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL)
This register selects the DWWD window size. This register is shown in Figure 12-38 and described inTable 12-33.
Figure 12-38. Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) [offset = A8h]
31

16
WWDSIZE
R-000015

0WWDSIZE
R/WP-0005h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 12-33. Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) Field
Descriptions
Bit

Field

31-0

WWDSIZE

Value
0

Description
The DWWD window size.

0000 0005h

100% (The functionality is the same as the standard time-out digital watchdog.)

0000 0050h

50%0000 0500h

25%0000 5000h

12.5%0005 0000h

6.25%

All other values

3.125%
Note: The DWWD window size can be selected by the application even when the DWWD
counter is already enabled. If a change to the WWDSIZE is made before the watchdog service
window is opened, then the change in the configuration takes effect immediately. If a change tothe WWDSIZE is made when the watchdog service window is already open, then the change in
configuration takes effect only after the watchdog is serviced.

386

Real-Time Interrupt (RTI) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

RTI Control Registers

www.ti.com

12.3.32 RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE)
This register enables an "auto-clear" of the compare interrupt enable bit after a compare equal event. This
register is shown in Figure 12-39 and described in Table 12-34.
Figure 12-39. RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE) [offset = ACh]
31

28

27

24

23

20

19

16

Reserved

INTCLRENABLE3

Reserved

INTCLRENABLE2

R-0

R/WP-5h

R-0

R/WP-5h

15

12

11

8

7

4

3

0

Reserved

INTCLRENABLE1

Reserved

INTCLRENABLE0

R-0

R/WP-5h

R-0

R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 12-34. RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE)
Bit

Field

Value

31-28 Reserved

027-24 INTCLRENABLE3

Description
Reads return 0. Writes have no effect.
Enables the auto-clear functionality on the compare 3 interrupt.

5h

Read: Auto-clear for compare 3 interrupt is disabled.
Privileged Write: Auto-clear for compare 3 interrupt becomes disabled.

All other values

Read: Auto-clear for compare 3 interrupt is enabled.
Privileged Write: Auto-clear for compare 3 interrupt becomes enabled.

23-20 Reserved019-16 INTCLRENABLE2

Reads return 0. Writes have no effect.
Enables the auto-clear functionality on the compare 2 interrupt.

5h

Read: Auto-clear for compare 2interrupt is disabled.
Privileged Write: Auto-clear for compare 2 interrupt becomes disabled.

All other values

Read: Auto-clear for compare 2 interrupt is enabled.
Privileged Write: Auto-clear for compare 2 interrupt becomes enabled.

15-12 Reserved
11-80INTCLRENABLE1

Reads return 0. Writes have no effect.
Enables the auto-clear functionality on the compare 1 interrupt.

5h

Read: Auto-clear for compare 1 interrupt is disabled.
Privileged Write: Auto-clear for compare 1 interrupt becomes disabled.

All other values

Read: Auto-clear for compare 1 interrupt is enabled.
Privileged Write: Auto-clear for compare 1 interrupt becomes enabled.

7-4

Reserved

3-0

INTCLRENABLE00

Reads return 0. Writes have no effect.
Enables the auto-clear functionality on the compare 0 interrupt.

5h

Read: Auto-clear for compare 0 interrupt is disabled.
Privileged Write: Auto-clear for compare 0 interrupt becomes disabled.

All other values

Read: Auto-clear for compare 0 interrupt is enabled.
Privileged Write: Auto-clear for compare 0 interrupt becomes enabled.

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

387

RTI Control Registers

www.ti.com

12.3.33 RTI Compare 0 Clear Register (RTICMP0CLR)
This registers holds a compare value, which is compared with the counter selected in the RTICOMPCTRL
register Section 12.3.3. If the Free Running Counter matches the compare value, the compare 0 interrupt
or DMA request line is cleared and the value in the RTIUDCP0 register Section 12.3.15 is added to thisregister. This register is shown in Figure 12-40 and described in Table 12-35.
Figure 12-40. RTI Compare 0 Clear Register (RTICMP0CLR) [offset = B0h]
31

16
CMP0CLR
R/WP-0

15

0
CMP0CLR
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-35. RTI Compare 0 Clear Register (RTICMP0CLR)
Bit

Field

31-0

CMP0CLRValue
0-FFFF FFFFh

Description
Compare 0 clear. This registers holds a compare value, which is compared with the counterselected in the RTICOMPCTRL register. If the Free Running Counter matches the compare
value, the compare 0 interrupt or DMA request line is cleared and the value in the RTIUDCP0
register Section 12.3.15 is added to this register.
Reads return the current compare clear value.
A privileged write to this register updates the compare clear value.

12.3.34 RTI Compare 1 Clear Register (RTICMP1CLR)This registers holds a compare value, which is compared with the counter selected in the RTICOMPCTRL
register Section 12.3.3. If the Free Running Counter matches the compare value, the compare 0 interrupt
or DMA request line is cleared and the value in the RTIUDCP1 register Section 12.3.17 is added to thisregister. This register is shown in Figure 12-41 and described in Table 12-36.
Figure 12-41. RTI Compare 1 Clear Register (RTICMP1CLR) [offset = B4h]
31

16
CMP1CLR
R/WP-0

15

0
CMP1CLR
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-36. RTI Compare 1 Clear Register (RTICMP1CLR)
Bit

Field

31-0

CMP0CLRValue
0-FFFF FFFFh

Description
Compare 1 clear. This registers holds a compare value, which is compared with the counterselected in the RTICOMPCTRL register. If the Free Running Counter matches the compare
value, the compare 1 interrupt or DMA request line is cleared and the value in the RTIUDCP1
register Section 12.3.17 is added to this register.
Reads return the current compare clear value.
A privileged write to this register updates the compare clear value.

388

Real-Time Interrupt (RTI) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

RTI Control Registers

www.ti.com

12.3.35 RTI Compare 2 Clear Register (RTICMP2CLR)This registers holds a compare value, which is compared with the counter selected in the RTICOMPCTRL
register Section 12.3.3. If the Free Running Counter matches the compare value, the compare 2 interrupt
or DMA request line is cleared and the value in the RTIUDCP2 register Section 12.3.19 is added to thisregister. This register is shown in Figure 12-42 and described in Table 12-37.
Figure 12-42. RTI Compare 2 Clear Register (RTICMP2CLR) [offset = B8h]
31

16
CMP2CLR
R/WP-015

0
CMP2CLR
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-37. RTI Compare 2 Clear Register (RTICMP2CLR)
Bit

Field

31-0

CMP2CLRValue
0-FFFF FFFFh

Description
Compare 2 clear. This registers holds a compare value, which is compared with the counterselected in the RTICOMPCTRL register. If the Free Running Counter matches the compare
value, the compare 2 interrupt or DMA request line is cleared and the value in the RTIUDCP2register Section 12.3.19 is added to this register.
Reads return the current compare clear value.
A privileged write to this register updates the compare clear value.

12.3.36 RTI Compare 3 Clear Register (RTICMP3CLR)
This registers holds a compare value, which is compared with the counter selected in the RTICOMPCTRL
register Section 12.3.3. If the Free Running Counter matches the compare value, the compare 3 interrupt
or DMA request line is cleared and the value in the RTIUDCP3 register Section 12.3.21 is added to thisregister. This register is shown in Figure 12-43 and described in Table 12-38.
Figure 12-43. RTI Compare 3 Clear Register (RTICMP3CLR) [offset = BCh]
31

16
CMP3CLR
R/WP-015

0
CMP3CLR
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 12-38. RTI Compare 3 Clear Register (RTICMP3CLR)
Bit

Field

31-0

CMP3CLRValue
0-FFFF FFFFh

Description
Compare 3 clear. This registers holds a compare value, which is compared with the counterselected in the RTICOMPCTRL register. If the Free Running Counter matches the compare
value, the compare 3 interrupt or DMA request line is cleared and the value in the RTIUDCP3
register Section 12.3.21 is added to this register.
Reads return the current compare clear value.
A privileged write to this register updates the compare clear value.

SPNU517C – March 2018
Submit Documentation Feedback

Real-Time Interrupt (RTI) Module
Copyright © 2018, Texas Instruments Incorporated

389

Chapter 13
SPNU517C – March 2018

Cyclic Redundancy Check (CRC) Controller ModuleThis chapter describes the cyclic redundancy check (CRC) controller module.
Topic

13.1
13.2
13.3
13.4

390

...........................................................................................................................

Page

Overview ........................................................................................................ 391
Module Operation ............................................................................................ 392
Example/Hints: Full-CPU Mode .......................................................................... 394
CRC Control Registers ...................................................................................... 395

Cyclic Redundancy Check (CRC) Controller Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackOverviewwww.ti.com

13.1 Overview
The CRC controller is a module that is used to perform CRC (Cyclic Redundancy Check) to verify the
integrity of a memory system. A signature representing the contents of the memory is obtained when thecontents of the memory are read into the CRC controller. The responsibility of the CRC controller is tocalculate the signature for a set of data and easy comparison of the calculated signature value against a
pre-determined good signature value. The CRC controller supports two channels to perform CRC
calculations on multiple memories in parallel and can be used on any memory system.

13.1.1 Features
The CRC controller offers:• Two channels to perform background signature verification on any memory sub-system.
• Data compression on 8-, 16-, 32-, and 64-bit data size.
• Maximum-length PSA (Parallel Signature Analysis) register constructed based on 64 bit primitive
polynomial.
• Support for Full-CPU mode of operation.
• Data trace capability on Peripheral Bus Master, Flash, and System RAM data buses.

13.1.2 Block Diagram
Figure 13-1 shows a block diagram of the CRC controller.
NOTE: Only Channel 1 can support data trace. See Section 13.2.5.

Figure 13-1. CRC Controller Block Diagram For One Channel
Read Data Bus (Peripheral, Flash,
System RAM)

Mux

Bus Matrix Module
64
Write Data
Data Synchronization
Register File64

FSM and Control
Raw Data Register

SPNU517C – March 2018
Submit Documentation Feedback

PSA Signature Register

Trace Enable
HBSTRB[7:0]

Cyclic Redundancy Check (CRC) Controller Module
Copyright © 2018, Texas Instruments Incorporated

391

Module Operation

www.ti.com

13.2 Module Operation
13.2.1 General Operation
There are two channels in the CRC controller with each having a memory-mapped PSA (Parallel
Signature Analysis) Signature Register. The CRC Controller can calculate the PSA signature over any
memory configuration or memory space and data patterns defined by the application using the Full CPU
mode of the CRC Controller. A data pattern can be 8-, 16-, 32-, or 64-bit data.
The CRC module performs the signature calculation which can then be compared with a pre-determinedvalue to determine a pass or fail criteria. When a data pattern is written to the PSA Signature Register it iscompressed into a signature. Once all of the chosen data has been written to the PSA Signature Register,a read of the PSA Signature Register will return the calculated signature for the data.
The CRC Controller also provides data trace capability using CRC Channel 1. During data trace, channel
1 monitors any data being read on the CPU data bus and compresses it and the results are shown in the
PSA Signature Register.

13.2.2 CRC Modes of Operation
For this device, the CRC module supports Full CPU mode of operation with or without data trace enabled.
In other TMS570 devices that include the DMA feature, Auto and Semi-Auto modes are supported inaddition to Full CPU mode.
13.2.2.1 Full CPU ModeIn Full-CPU mode, the CPU is used to transfer the data patterns and perform the final signature
verification. In this mode, the data patterns are read from memory and written into the PSA Signature
Register. After the data patterns are compressed using the PSA Signature register, the CPU can read thecalculated result from the PSA Signature Register and compare the calculated result to the predetermined CRC signature value.

13.2.3 PSA Signature Register
The 64-bit PSA Signature Register is based on the primitive polynomial (as in the following equation) to
produce the maximum length LFSR (Linear Feedback Shift Register), as shown in Figure 13-2.
64

4

3

f(x) = x + x + x + x + 1(25)

The serial implementation of LFSR has a limitation that, it requires n clock cycles to calculate the CRC
values for an n-bit data stream. The idea is to produce the same CRC value operating on a multi-bit data
stream, as would occur if the CRC were computed one bit at a time over the whole data stream. The
algorithm involves looping to simulate the shifting, and concatenating strings to build the equations after nshift.
Figure 13-2. Linear Feedback Shift Register (LFSR)
Data

392

D Q

D Q

D Q

D Q

D Q

D Q

X0

X1

X2

X3

X4

X63

Cyclic Redundancy Check (CRC) Controller Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

The parallel CRC calculation based on the polynomial can be illustrated in the following HDL code:for i in 63 to 0 loop
NEXT_CRC_VAL(0) := CRC_VAL(63) xor DATA(i);for j in 1 to 63 loop
case j iswhen 1|3|4 =>NEXT_CRC_VAL(j) :=CRC_VAL(j - 1) xor CRC_VAL(63) xor DATA(i);when others =>NEXT_CRC_VAL(j) := CRC_VAL(j - 1);
end case;end loop;
CRC_VAL := NEXT_CRC_VAL;
end loop;

NOTE: 1) The inner loop is to calculate the next value of each shift register bit after one cycle2) The outer loop is to simulate 64 cycles of shifting. The equation for each shift register bitis thus built before it is compressed into the shift register.
3) MSB of the DATA is shifted in first

There is one PSA Signature Register per CRC channel. The PSA Signature Register can be both read
and written. When it is written, it can either compress the data or just capture the data depending on thestate of CHx_MODE bits. If CHx_MODE=Data Capture, a seed value can be planted in the PSA Signature
Register without compression. If not in the Data Capture mode, the data written will be compressed by the
PSA Signature Register when it is written. Each channel can be seeded with different values before
compression starts. When the PSA Signature Register is read, it gives the calculated signature.
In Full-CPU mode, the number of data patterns to be compressed is determined by the CPU/applicationand signature calculation will continue as long as data continues to be written to the PSA Signature
Register or until a PSA Software Reset is generated for the channel using the CRC_CTRL0 register.
When the the software reset is instantiated, the PSA Signature Register is reset to all zeros.
The CRC Controller supports double word, word, half word and byte access to the PSA Signature
Register. During a non-double word write access, all unwritten bytes are padded with zero’s before
compression. Note that comparison between PSA Sector Signature Register and CRC Value Registershould always be completed using 64 bit accesses because a compressed value is always expressed asa 64 bit value.
The PSA Signature Register is reset to zero under the following conditions:• System reset• PSA Software reset• One sector of data patterns are compressed

13.2.4 Raw Data Register
The raw or un-compressed data written to the PSA Signature Register is also saved in the Raw Data
Register. This register is read only.

SPNU517C – March 2018
Submit Documentation Feedback

Cyclic Redundancy Check (CRC) Controller Module
Copyright © 2018, Texas Instruments Incorporated

393

Module Operation

www.ti.com

13.2.5 CPU Data Trace
CRC channel 1 can be used to trace (or "snoop") Flash, System RAM and Peripheral Bus Master databuses. However, at any one point, only one bus is traced. It is possible to disable the tracing of any of thebuses by setting the appropriate bits in the CRC_TRACE_BUS_SEL register or all data tracing by writing
zero to the CH1_TRACEEN bit of the CRC_CTRL2 register.
While tracing the data, there is a priority scheme implemented between the buses. The Peripheral Bus
Master has the highest priority followed by Flash, and finally the System RAM. For each data read by the
CPU on its data bus, the same data is compressed in the PSA Signature Register. In data trace mode, awrite to the PSA Signature Register does not get compressed. Therefore, it is possible to write a seedvalue into PSA Signature Register before the bus tracing takes place. For non- double word reads on thedata bus, all un-selected byte lanes are padded with zeros during compression.
13.2.5.1 Data Capture Mode used in Conjunction with Data Trace
Data capture mode is especially useful when it is used in conjunction when data trace for channel 1 isenabled (CRC_CTRL2.CH1_TRACEEN = 1). The seed value can be planted in PSA Signature Registerduring data capture mode by writing a seed value into PSA Signature Register. The data trace enable bitis then set to snoop and compress any read transaction on DAHB bus. When trace enable bit is set,
CRC_CTRL2.CH1_MODE is automatically reset to 0 (data capture mode). To change from one mode toanother mode in the middle of an on-going mode, perform the following steps:
1. Assert software reset for the respective channel.
2. Change from the current active mode to Data Capture mode (CRC_CTRL2.CH1_MODE = 0).
3. Change from Data Capture mode to the new mode.
4. Release software reset.

13.2.6 Power Down Mode
CRC module can be put into power down mode when the power down control bit PWDN is set. The
module wakes up when the PWDN bit is cleared. When CRC controller is in power down mode, data trace
is suspended. However, if CRC registers are accessed then data trace will resume.

13.2.7 Emulation
During emulation, registers and or memory spaces are often accessed in order to keep the information in
the IDE up to date or refreshed. As a result, during emulation/debug, these accesses will not impact thefunctional operation of the module. As an example, if data trace mode is active, accesses by the CPU todata are not compressed by the PSA Signature Register when the device is in suspend mode.

13.2.8 Peripheral Bus Interface
The CRC Controller is a peripheral slave module and has a similar bus interface to all other modules on
the device. The CRC Controller supports the following features:• Different sizes of burst operation.
• Aligned and unaligned accesses.
• Abort is generated for any illegal address accesses.

13.3

Example/Hints: Full-CPU Mode
In a system without the availability of a DMA controller, the CRC routine needs to be controlled by the
CPU and application software. The CPU needs to read from the memory area from which CRC is to be
performed and, if not using data trace mode, the data will need to be written to the PSA Signature
Register.
In a scenario where the memory space is very large or where bandwidth is a concern, the memory can bepartitioned into blocks each with a pre-determined signature. When partitioned, the CPU can transfer thedata to the PSA Signature Register on a cyclic basis so CPU resources are not overburdened by the CRC
calculation.

394

Cyclic Redundancy Check (CRC) Controller Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Example/Hints: Full-CPU Mode

www.ti.com

In addition, efficiency can be gained by utilizing the data trace mode and performing 64-bit reads of thedata over which the signature is to be calculated. When using this mode in a cyclic mode, data trace canbe disabled after each block of data is checked and the signature calculation continued on the next cycle
by re-enabling the data trace mode. Note, however, if data trace mode is used, care must be taken to
insure interrupt servicing does not corrupt the signature calculation given CPU data accesses will most
likely occur during interrupt servicing.

13.3.1 CRC Setup
For normal Full CPU mode of operation (without data trace enabled), the application software will need toconfigure the control registers for CRC operation. This is accomplished by first asserting the software
reset using the bits for the PSA channel(s) to be utilized in the calculation (CRC_CTRL0 register) andsetting the mode for Full CPU Mode using the CHx_MODE bits (CRC_CTRL2). If a seed value is desired,write the seed value to the PSA Signature Register before changing the Chx_MODE bits to Full CPU
Mode as the CHx_MODE bits will default to the Data Capture mode setting which allows data to be written
to the PSA Signature Register without compression.
Once the mode is established, read the first memory location/data pattern to be included in the PSA
signature calculation and write it to the PSA Signature Register and continue this cycle of reading the data
patterns and writing to the PSA Signature Register until all of the data to be included in the signature areread and written. Once all data has been read an written, read the PSA Signature Register to obtain the
final calculated signature and compare it with the expected signature to determine pass or fail.
Alternatively, data trace can be enabled by also setting the CH1_TRACEEN bit in the CRC_CTRL2
register and selecting the bus for the memory space from which the data will be read in the
CRC_TRACE_BUS_SEL register. Once this is completed, the data can simply be read by the CPU
without the need to write it to the PSA Signature Register. Once all of the data has been read, disable thedata trace mode and obtain the final calculated signature from the PSA Signature Register and comparewith the expected results for pass or fail determination.

13.4 CRC Control Registers
Table 13-1 lists the registers of the CRC Controller. All registers are in word boundary. 64-, 32-, 16-, and8-bit write accesses are supported to all registers. The base address for the control registers is FE000000h.
Table 13-1. CRC Control Registers
OffsetAcronym

Register Description

0h

CRC_CTRL0

CRC Global Control Register

Section 13.4.1

8h

CRC_CTRL1

CRC Global Control Register 1

Section 13.4.2

10h

CRC_CTRL2

CRC Global Control Register 2

Section 13.4.3

60h

PSA_SIGREGL1

Channel 1 PSA Signature Low Register

Section 13.4.464h

PSA_SIGREGH1

Channel 1 PSA Signature High Register

Section 13.4.5

78h

RAW_DATAREGL1

Channel 1 Raw Data Low Register

Section 13.4.6

7Ch

RAW_DATAREGH1

Channel 1 Raw Data High Register

Section 13.4.7

A0h

PSA_SIGREGL2

Channel 2 PSA Signature Low Register

Section 13.4.8

A4h

PSA_SIGREGH2

Channel 2 PSA Signature High Register

Section 13.4.9

B8h

RAW_DATAREGL2

Channel 2 Raw Data Low Register

Section 13.4.10

BCh

RAW_DATAREGH2

Channel 2 Raw Data High Register

Section 13.4.11

140h

CRC_TRACE_BUS_SEL

Data Bus Selection Register

Section 13.4.12

SPNU517C – March 2018
Submit Documentation Feedback

SectionCyclic Redundancy Check (CRC) Controller Module
Copyright © 2018, Texas Instruments Incorporated

395

CRC Control Registers

www.ti.com

13.4.1 CRC Global Control Register 0 (CRC_CTRL0)
Figure 13-3. CRC Global Control Register 0 (CRC_CTRL0) [offset = 00h]
31

16
Reserved
R-0
15

9

8

Reserved

CH2_PSA_SWREST

R-0

R/W-0

7

1

0

Reserved

CH1_PSA_SWREST

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13-2. CRC Global Control Register 0 (CRC_CTRL0) Field Descriptions
Bit

Field

31-9

Reserved

8

Value
0

CH2_PSA_SWREST

7-1

Reserved

0

CH1_PSA_SWREST

Description
Reads return 0. Writes have no effect.
Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all 0.
Software reset does not reset software reset bit itself. Therefore, CPU is required to clear
this bit by writing a 0.

0

PSA Signature Register is not reset.

1

PSA Signature Register is reset.

0

Reads return 0. Writes have no effect.
Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all 0.
Software reset does not reset software reset bit itself. Therefore, CPU is required to clear
this bit by writing a 0.

0

PSA Signature Register is not reset.

1

PSA Signature Register is reset.

13.4.2 CRC Global Control Register (CRC_CTRL1)
Figure 13-4. CRC Global Control Register 1 (CRC_CTRL1) [offset = 08h]
31

16
Reserved
R-0

15

1

0

Reserved

PWDN

R-0

RW-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13-3. CRC Global Control Register 1 (CRC_CTRL1) Field Descriptions
Bit

Field

31-1

Reserved

0

PWDN

396

Value
0

Description
Reads return 0. Writes have no effect.
Power Down. When set, CRC module is put in power-down mode.

0

CRC is not in power-down mode.

1

CRC is in power-down mode.

Cyclic Redundancy Check (CRC) Controller Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

CRC Control Registers

www.ti.com

13.4.3 CRC Global Control Register 2 (CRC_CTRL2)
Figure 13-5. CRC Global Control Register 2 (CRC_CTRL2) [offset = 10h]31

16
Reserved
R-0
15

10

7

9

8

Reserved

CH2_MODE

R-0

R/WP-0

5

4

3

2

1

0

Reserved

CH1_TRACEEN

Reserved

CH1_MODE

R-0

R/WP-0R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 13-4. CRC Global Control Register 2 (CRC_CTRL2) Field Descriptions
Bit

Field

31-10

Reserved

9-8

CH2_MODE

Value
0

1h-2h
Reserved

4

CH1_TRACEEN

3-2

Reserved

1-0

CH1_MODE

Data Capture mode.
Reserved

3h

Full CPU mode0

Reads return 0. Writes have no effect.
Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. The channel
traces (or "snoops") on the CPU Peripheral Bus Master, Flash, or System RAM buses (selected
through the CRC_TRACE_BUS_SEL register) for any read transaction. Any read data on thesebuses is compressed by the PSA Signature Register. When suspend is on, the PSA Signature
Register does not compress any read data on these buses. When trace enable bit is set, theCH1_MODE bit is automatically reset to 0 (Data Capture mode).

0

Data Trace is disabled.

1

Data Trace is enabled.

0

Reads return 0. Writes have no effect.
Channel 1 Mode Selection.

0
1h-2h
3h

SPNU517C – March 2018
Submit Documentation Feedback

Reads return 0. Writes have no effect.
Channel 2 Mode Selection.

0

7-5

Description

Data Capture mode.
Reserved
Full CPU mode

Cyclic Redundancy Check (CRC) Controller Module
Copyright © 2018, Texas Instruments Incorporated

397

CRC Control Registers

www.ti.com

13.4.4 Channel 1 PSA Signature Low Register (PSA_SIGREGL1)
Figure 13-6. Channel 1 PSA Signature Low Register (PSA_SIGREGL1) [offset = 60h]
310
PSASIG1
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 13-5. Channel 1 PSA Signature Low Register (PSA_SIGREGL1) Field Descriptions
Bit

Field

Description

31-0

PSASIG1

Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register.

13.4.5 Channel 1 PSA Signature High Register (PSA_SIGREGH1)
Figure 13-7. Channel 1 PSA Signature High Register (PSA_SIGREGH1) [offset = 64h]
31

0
PSASIG1
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 13-6. Channel 1 PSA Signature High Register (PSA_SIGREGH1) Field Descriptions
Bit

Field

Description

31-0

PSASIG1

Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register.

398

Cyclic Redundancy Check (CRC) Controller Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

CRC Control Registers

www.ti.com

13.4.6 Channel 1 Raw Data Low Register (RAW_DATAREGL1)
Figure 13-8. Channel 1 Raw Data Low Register (RAW_DATAREGL1) [offset = 78h]
31

0
RAW_DATA1
R-0

LEGEND: R = Read only; -n = value after reset

Table 13-7. Channel 1 Raw Data Low Register (RAW_DATAREGL1) Field Descriptions
Bit

Field

Description

31-0

RAW_DATA1

Channel 1 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data.

13.4.7 Channel 1 Raw Data High Register (RAW_DATAREGH1)
Figure 13-9. Channel 1 Raw Data High Register (RAW_DATAREGH1) [offset = 7Ch]
31

0
RAW_DATA1
R-0

LEGEND: R = Read only; -n = value after reset

Table 13-8. Channel 1 Raw Data High Register (RAW_DATAREGH1) Field Descriptions
Bit

Field

Description

31-0

RAW_DATA1

Channel 1 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data.

SPNU517C – March 2018
Submit Documentation Feedback

Cyclic Redundancy Check (CRC) Controller Module
Copyright © 2018, Texas Instruments Incorporated

399

CRC Control Registers

www.ti.com

13.4.8 Channel 2 PSA Signature Low Register (PSA_SIGREGL2)
Figure 13-10. Channel 2 PSA Signature Low Register (PSA_SIGREGL2) [offset = A0h]
31

0
PSASIG2
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 13-9. Channel 2 PSA Signature Low Register (PSA_SIGREGL2) Field Descriptions
Bit

Field

Description

31-0

PSASIG2

Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register.

13.4.9 Channel 2 PSA Signature High Register (PSA_SIGREGH2)
Figure 13-11. Channel 2 PSA Signature High Register (PSA_SIGREGH2) [offset = A4h]31

0
PSASIG2
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 13-10. Channel 2 PSA Signature High Register (PSA_SIGREGH2) Field Descriptions
Bit

Field

Description

31-0

PSASIG2

Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register.

400

Cyclic Redundancy Check (CRC) Controller Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

CRC Control Registers

www.ti.com

13.4.10 Channel 2 Raw Data Low Register (RAW_DATAREGL2)
Figure 13-12. Channel 2 Raw Data Low Register (RAW_DATAREGL2) [offset = B8h]
310
RAW_DATA2
R-0

LEGEND: R = Read only; -n = value after reset

Table 13-11. Channel 2 Raw Data Low Register (RAW_DATAREGL2) Field Descriptions
Bit

Field

Description

31-0

RAW_DATA2

Channel 2 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data..

13.4.11 Channel 2 Raw Data High Register (RAW_DATAREGH2)
Figure 13-13. Channel 2 Raw Data High Register (RAW_DATAREGH2) [offset = BCh]31

0
RAW_DATA2
R-0

LEGEND: R = Read only; -n = value after reset

Table 13-12. Channel 2 Raw Data High Register (RAW_DATAREGH2) Field Descriptions
Bit

Field

Description

31-0

RAW_DATA2

Channel 2 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data..

SPNU517C – March 2018
Submit Documentation Feedback

Cyclic Redundancy Check (CRC) Controller Module
Copyright © 2018, Texas Instruments Incorporated

401

CRC Control Registers

www.ti.com

13.4.12 Data Bus Selection Register (CRC_TRACE_BUS_SEL)
Figure 13-14. Data Bus Selection Register (CRC_TRACE_BUS_SEL) [offset = 140h]
31

16
Reserved
R-0

15

3

2

1

0

Reserved

MEn

DTCMEnITCMEn

R-0

R/W-1

R/W-1

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13-13. Data Bus Selection Register Field Descriptions
Bit

Field

31-3

Reserved

2

1

0

402

Value
0

MEn

Description
Reads return 0. Writes have no effect.
Enables the tracing of Peripheral Bus Master.

0

Tracing of Peripheral Bus Master has been disabled.

1

Tracing of Peripheral Bus Master has been enabled.

DTCMEnEnables the tracing of data TCM.
0

Tracing of System Odd and Even RAM buses have been disabled.

1

Tracing of System Odd and Even RAM buses have been enabled.

ITCMEnEnables the tracing of instruction TCM.
0

Tracing of Flash data bus has been disabled.

1

Tracing of Flash data bus has been enabled.

Cyclic Redundancy Check (CRC) Controller Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Chapter 14
SPNU517C – March 2018

Vectored Interrupt Manager (VIM) ModuleThis chapter describes the behavior of the vectored interrupt manager (VIM) module of the device family.
Topic

14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8

...........................................................................................................................

Page

Overview ......................................................................................................... 404
Device Level Interrupt Management .................................................................... 404
Interrupt Handling Inside VIM ............................................................................. 407
Interrupt Vector Table (VIM RAM) ....................................................................... 411
VIM Wakeup Interrupt ........................................................................................ 414
Capture Event Sources ..................................................................................... 415
Examples......................................................................................................... 415
VIM Control Registers ....................................................................................... 418

SPNU517C – March 2018
Submit Documentation Feedback

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

403

Overviewwww.ti.com

14.1 Overview
The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling themany interrupt sources present on a device. Interrupts are caused by events outside of the normal flow ofprogram execution. Normally, these events require a timely response from the central processing unit
(CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to
an interrupt service routine (ISR).
The VIM module has the following features:• Supports 95 interrupt channels, in both register vectored interrupt and hardware vectored interrupt
mode.
– Provides IRQ vector directly to the CPU VIC port
– Provides FIQ/IRQ vector through registers– Provides programmable priority and enable for interrupt request lines• Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.
• Provides two software dispatch mechanisms for backward compatibility with earlier generation of TI
processors.
– Index interrupt– Register vectored interrupt• Parity protected vector interrupt table against soft errors.

14.2 Device Level Interrupt Management
A block diagram of device level interrupt handling is shown in Figure 14-1. When an event occurs within aperipheral, the peripheral makes an interrupt request to the VIM. Then, VIM prioritizes the requests fromperipherals and provides the address of the highest interrupt service routine (ISR) to the CPU. Finally,
CPU starts executing the ISR instructions from that address in the ISR. Section 14.2.1 throughSection 14.2.3 provide additional details about these three steps.
Figure 14-1. Device Level Interrupt Block Diagram
Peripherals - Generate Interrupt Requests
ESM

ADC

LIN

SPI

DCAN

INT_REQ0 INT_REQ1

INT_REQ94

VIM
CPU Interrupts

Special Interrupts

NHET- Interrupt Enable- Interrupt Priority- Interrupt Mapping- Interrupt Generation

INT
IRQ
FIQ
IRQ
FIQ
FIQ
IRQ
IRQ
Table
Index
Index Vector
VectorRequestRequestt
VectorConfiguration Register RegisterRegister Register(Direct
CAPEVT[1:0] Wakeup_INT
Hardware

VBUSP

RTI

404

CPU

GCM

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

Vector)

VIC Port

SPNU517C – March 2018
Submit Documentation FeedbackDevice Level Interrupt Management

www.ti.com

14.2.1 Interrupt Generation at the Peripheral
Interrupt generation begins when an event occurs within a peripheral module. Some examples of interruptcapable events are expiration of a counter within a timer module, receipt of a character in acommunications module, and completion of a conversion in an analog-to-digital converter (ADC) module.
Some device peripherals are capable of requesting interrupts on more than one interrupt request line.
Interrupts are not always generated when an event occurs; the peripheral must make an interrupt request
to the VIM based on the event occurrence. Typically, the peripheral contains:• An interrupt flag bit for each event to signify the event occurrence.
• An interrupt enable bit to control whether the event occurrence causes an interrupt request to the VIM.

14.2.2 Interrupt Handling at the CPU
The ARM CPU provides two vectors for interrupt requests—fast interrupt requests (FIQs) and normalinterrupt requests (IRQs). FIQs are higher priority than IRQs, and FIQ interrupts may interrupt IRQ
interrupts.
NOTE: The FIQ implemented in Cortex-R4F is Non-Maskable Fast Interrupts (NMFI). Once FIQ isenabled (by clearing F bit in CPSR), it can NOT be disabled by setting F bit in CPSR. Only areset or an FIQ will be able to set the F bit in CPSR. By hardware, Non Maskable FIQ are
not reentrant.

After reset (power reset or warm reset), both FIQ and IRQ are disabled. The CPU may enable theseinterrupt request channels individually within the CPSR (Current Program Status Register); CPSR bits 6
and 7 must be cleared to enable the FIQ (bit 6) and IRQ (bit 7) interrupt requests at the CPU. CPSR iswritable in privilege mode only. Example 14-2 shows how to enable the IRQ and FIQ through CPSR.
When the CPU receives an interrupt request, the CPSR mode field changes to either FIQ or IRQ mode.
When an IRQ interrupt is received, the CPU disables other IRQ interrupts by setting CPSR bit 7. When an
FIQ interrupt is received, the CPU disables both IRQ and FIQ interrupts by setting CPSR bits 6 and 7.
A write of 1 to CPSR bit 7 disables the IRQ from CPU. However, a write of 1 to CPSR bit 6 leaves it
unchanged. Example 14-2 also shows how to disable the IRQ through CPSR.

SPNU517C – March 2018
Submit Documentation Feedback

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

405

Device Level Interrupt Management

www.ti.com

14.2.3 Software Interrupt Handling Options
The device supports three different possibilities for software to handle interrupts
1. Index interrupts mode (compatible with TMS470R1x legacy code)
After the interrupt is received by the CPU, the CPU branches to 0x18 (IRQ) or 0x1C (FIQ) to executethe main ISR. The main ISR routine reads the offset register (IRQINDEX, FIQINDEX) to determine thesource of the interrupt.
This mode is compatible with the TMS470R1x (CIM) module and provides the same interrupt registers.
This mode could be used if legacy code needs to be reused, porting it from the TMS470R1x family.
However, imported software will not benefit from the VIM improvements.
To port legacy software, the interrupt vector at 0x18 (IRQ) or 0x1C (FIQ) only needs to be a branchstatement to a software interrupt table. The software interrupt table reads the pending interrupt from avector offset register (FIQINDEX[7:0] for FIQ interrupts and IRQINDEX[7:0] for IRQ interrupts). All
pending interrupts can be viewed in the INTREQ register. Example 14-4 shows how to respond to FIQ
with short latency in this mode.
2. Register vectored interrupts (automatically provide vector address to application)
Before enabling interrupts, the application software also has to initiate the interrupt vector table (VIM
RAM).
Once the VIM receives an interrupt, it loads the address of ISR from interrupt vector table, and store it
into the interrupt vector register (IRQVECREG for IRQ interrupt, FIQVECREG for FIQ interrupt).
After the interrupt is received by the CPU, the CPU executes the instruction placed at 0x18 or 0x1C
(IRQ or FIQ vector) to load the address of ISR (interrupt vector) from the interrupt vector register.
Example 14-3 illustrates the configuration for the exception vectors using this mode.
3. Hardware vectored interrupts (automatically dispatch to ISR, IRQ only)
Before enabling interrupts, the application software must initiate the interrupt vector table (VIM RAM)
pointing to the ISR for each interrupt channel.
After the interrupt (IRQ) is received by the CPU, CPU reads the address of ISR directly from theinterface with VIM (VIC port) instead of branching to 0x18. The CPU will branch directly to the ISR.
The hardware vectored interrupt behavior must be explicitly enabled by setting the vector enable (VE)
bit in the CP15 R1 register. This bit resets to 0, so that the default state after reset is backward
compatible to earlier ARM CPU. Example 14-1 shows how to enable the hardware vectored interrupt.
NOTE: This mode is NOT available for FIQ.

4. Software-Based Priority Decoding Scheme
If the application uses a software-based interrupt priority decoding scheme instead of the hardware
vector capabilities, then there is an additional step which was not required on earlier devices. Thisversion of the VIM will hold an interrupt request generated by a peripheral. When the software clears
the interrupt condition in the source module (for example, RTI, GIO, and so on), then it must also
perform an additional clear of the interrupt request in the VIM. This can be done by reading the
IRQVECREG register ( Section 14.8.14) or FIQVECREG register (Section 14.8.15), or by writing a 1 tothe INTREQ(i) bit (Section 14.8.9) in the VIM. This is not necessary if any of the three previous
methods are used as the interrupt request bit in the VIM will be automatically cleared when the vector
is read.

406

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Interrupt Handling Inside VIM

www.ti.com

14.3 Interrupt Handling Inside VIM
A block diagram of the interrupt handling inside VIM is shown in Figure 14-2
Figure 14-2. VIM Interrupt Handling Block Diagram
INT_
REQ0

INT_
REQ1

INT_
REQ2

INT_
INT_
REQ93 REQ94

CHANNEL
MAPPINGCHAN0 CHAN1 CHAN2

CHAN93 CHAN94

INTERRUPTENABLE
INT_
INT_
INT_
CHAN0 CHAN1 CHAN2

INT_
INT_
CHAN93 CHAN94

IRQ / FIQ
LEVEL

FIQ_ FIQ_
CHAN93 CHAN94

FIQ_
FIQ_
FIQ_
CHAN0 CHAN1 CHAN2

IRQ_
CHAN2

FIQ

Register

FIQINDEX

FIQ INDEX

To CPUIRQ LEVELPRIORITY ENCODER
IRQ INDEX

FIQ LEVELPRIORITY ENCODER

IRQ_
IRQ_
CHAN93 CHAN94

IRQ

PROGRAMMABLE INTERRUPT VECTOR TABLE

To CPU

Register

IRQINDEX

Phantom Vector
Channel 0 Vector
Channel 1 Vector

Register

FIQVECREGSPNU517C – March 2018
Submit Documentation Feedback

IRQ VECTOR

FIQ VECTOR

Channel 94 Vector

TO CPU
VIC Port

Register

IRQVECREG

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

407

Interrupt Handling Inside VIM

www.ti.com

14.3.1 VIM Interrupt Channel Mapping
The VIM support 96 interrupt channels (including phantom interrupt). A block diagram of the VIM interrupt
requests arrangement from peripheral modules to the interrupt channels, is provided in Figure 14-3. Eachinterrupt channel(CHANx) has a corresponding mapping register bit field (CHANMAPx[6:0]). This mapping
register determines which interrupt channel it maps each VIM interrupt request. With this scheme, thesame request can be mapped to multiple channels. A lower numbered channel in each FIQ and IRQ has
higher priority. The programmability of the VIM allows software to control the interrupt priority.
Figure 14-3. VIM Channel Mapping
INT_ INT_ INT_
REQ0 REQ1 REQ2

CHANMAP2[6:0]

INT_
REQ94
NOTE:
CHAN0 and CHAN1 are hard wired to
INT_REQ0 and INT_REQ1, can NOT
be remapped.

7
CHAN2

CHANNEL
MAPPING
INT_ INT_ INT_
REQ0 REQ1 REQ2

CHANMAP94[6:0]
95 Interrupt
Channels

INT_
REQ94

7
CHAN94

NOTE: CHAN95
CHAN95 has no dedicated interrupt vector table entry. Therefore, CHAN95 shall NOT be
remapped to other INT_REQ (INT_REQ95 is reserved at device level).

In the reset state, the VIM maps all of the interrupt requests in the system to their respective interrupt
channels. Figure 14-4 shows the default state following the reset.
Figure 14-5 shows the VIM INT2 is remapped to both Channel 2 and 4, and INT3 is mapped to channel 3.
NOTE: By mapping INT2 to channel 2 and channel 4, and mapping INT3 to channel 3, it is possible
for the software to change the priority dynamically by changing the ENABLE register(REQENASET and REQENACLR). When channel 2 is enabled, the priority is:
1. INT0
2. INT1
3. INT2
4. INT3
Disabling channel 2, the priority becomes:
1.
2.
3.
4.

408

INT0
INT1
INT3
INT2

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Interrupt Handling Inside VIM

www.ti.com

Figure 14-4. VIM in Default State
Phantom Vector

0xFFF82000

Peripheral 0

INT_REQ0

CHANMAP0CHAN0Channel 0 Vector

0xFFF82004

Peripheral 1

INT_REQ1

CHANMAP1

CHAN1

Channel 1 Vector

0xFFF82008

Peripheral 2

INT_REQ2CHANMAP2CHAN2Channel 2 Vector

0xFFF8200C

Peripheral 3

INT_REQ3

CHANMAP3

CHAN3Channel 3 Vector

0xFFF82010

Peripheral 4

INT_REQ4

CHANMAP4CHAN4Channel 4 Vector

0xFFF82014

Interrupt
requests(from peripheral)

Interrupt
channels

Peripheral 93

INT_REQ93

CHANMAP93

CHAN93Channel 93 Vector

0xFFF82178

Peripheral 94

INT_REQ94

CHANMAP94

CHAN94Channel 94 Vector

0xFFF8217C

NOTE: CHAN0 and CHAN1 are hardwired to INT_REQ0 and INT_REQ1, so they cannot be
remapped.

Figure 14-5. VIM in a Programmed State
Phantom Vector

0xFFF82000

Peripheral 0

INT_REQ0

CHANMAP0CHAN0Channel 0 Vector

0xFFF82004

Peripheral 1

INT_REQ1

CHANMAP1

CHAN1

Channel 1 Vector

0xFFF82008

Peripheral 2

INT_REQ2CHANMAP2CHAN2Channel 2 Vector

0xFFF8200C

Peripheral 3

INT_REQ3

CHANMAP3

CHAN3Channel 3 Vector

0xFFF82010

Peripheral 4

INT_REQ4

CHANMAP4CHAN4Channel 4 Vector

0xFFF82014

Interrupt
requests(from peripheral)

Interrupt
channels

Peripheral 93

INT_REQ93

CHANMAP93

CHAN93Channel 93 Vector

0xFFF82178

Peripheral 94

INT_REQ94

CHANMAP94

CHAN94Channel 94 Vector

0xFFF8217C

NOTE: CHAN0 and CHAN1 are hard wired to INT_REQ0 and INT_REQ1, so they cannot be
remapped.

SPNU517C – March 2018
Submit Documentation Feedback

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

409

Interrupt Handling Inside VIM

www.ti.com

14.3.2 VIM Input Channel Management
As shown in Figure 14-6, the VIM enables channels on a channel-by-channel basis (in the REQENASET
and REQENACLR registers); unused channels may be masked to prevent spurious interrupts.
NOTE: The interrupt ENABLE register does not affect the value of INTREQ.

Figure 14-6. Interrupt Channel Management
INT FLAG
INTREQ.0
FIQ_CHAN[0]CHAN0INT_CHAN0
INT FLAG
INTREQ.1
FIQ_CHAN[1]CHAN1

INT_CHAN1
INT FLAG
INTREQ.2

CHAN2

1
REQENA.2

INT_CHAN2

Controlled by:
REQENASET.2
REQENACLR.20

FIQ_CHAN[2]IRQ_CHAN[2]FIRQPR.2

INT FLAG
INTREQ.95

CHAN95

FIQ_CHAN[95]1

REQENA.95

INT_CHAN95

Controlled by:
REQENASET.95
REQENACLR.95

0

IRQ_CHAN[95]FIRQPR.95

By default, interrupt CHAN0 is mapped to ESM (Error Signal Module) high level interrupt and CHAN1 isreserved for other NMI. For safety reasons, these two channels are mapped to FIQ only and can NOT be
disabled through ENABLE registers.
NOTE: NMI Channel
Channel 0 and channel 1 are not maskable by the REQENASET/REQENACLR bit and bothchannels are routed exclusively to FIQ/NMI request line (FIRQPR0 and FIRQPR1 have noeffect).

The VIM prioritizes the received interrupts based upon a programmed prioritization scheme. The VIM cansend two interrupt requests to the CPU simultaneously—one IRQ and one FIQ. If both interrupt types areenabled at the CPU level, then the FIQ has greater priority and is handled first. Each interrupt channel,
except channel 0 and 1, can be assigned to send either an FIQ or IRQ request to the CPU (in the
FIRQPR register).
The VIM provides a default prioritization scheme, which sends the lowest numbered active channel (ineach FIQ and IRQ classes) to the CPU. Within the FIQ and IRQ classes of interrupts, the lowest channel
has the highest priority interrupt. The channel number is programmable through register CHANMAPx.

410

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Interrupt Vector Table (VIM RAM)

www.ti.com

After the VIM has generated the vector corresponding to the highest active IRQ, it updates the FIQINDEXor the IRQINDEX register, depending on the class of interrupt. Then, it accesses the interrupt vector tableusing the vector value to fetch the address of the corresponding ISR. If the request is an FIQ classinterrupt, the address read from the interrupt vector table, is written to the FIQVECREG register. If therequest is an IRQ class interrupt, the address is written to the IRQVECREG register and put on the VIC
port of the CPU (in case of hardware vectored interrupt is enabled).
All of the interrupt registers are updated when a new high priority interrupt line becomes active.

14.4 Interrupt Vector Table (VIM RAM)
Interrupt vector table stores the address of ISRs. During register vectored interrupt and hardware vectoredinterrupt, VIM accesses the interrupt vector table using the vector value to fetch the address of thecorresponding ISR.
For safety reasons, the interrupt vector table has protection by parity to indicate corruption due to soft
errors. The parity scheme is implemented as a continuous background check based on memory access.
Section 14.4.1 through Section 14.4.4 describe how parity works in the interrupt vector table.
NOTE: Writes to the interrupt vector table parity flag register (PARFLG) and the interrupt vector
table parity control register (PARCTL) are in privilege mode only.

14.4.1 Interrupt Vector Table Operation
The interrupt vector table is organized in 96 words of 32 bits. 32-bit, 16-bit, and 8-bit accesses aresupported (when parity is disabled). Figure 14-7 shows the interrupt memory mapping. The table baseaddress is FFF8 2000h.
Figure 14-7. VIM Interrupt Address Memory Map
Interrupt vector table address space
0xFFF82000

Phantom Vector

0xFFF82004

Channel 0 Vector

0xFFF82008

Channel 1 Vector

0xFFF82178

Channel 93 Vector

0xFFF8217C

Channel 94 Vector

NOTE: The interrupt vector table only has 96 entries, one phantom vector and 95 interrupt channels.
Channel 95 does not have a dedicated vector and shall not be used.

SPNU517C – March 2018
Submit Documentation Feedback

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

411

Interrupt Vector Table (VIM RAM)

www.ti.com

There is one bit of parity per 32-bit ISR address. When a write is performed into the interrupt vector table,
the parity is calculated for the 32-bit word and a parity bit is written into the corresponding parity region ofinterrupt vector table.
NOTE: Only 32-bit write/read access are allowed on interrupt vector table if parity is required. Non
32-bit access might result in parity errors.

When a read occurs from the CPU or VIM, the VIM calculates the parity from the data coming from theinterrupt vector table and compares it to the parity stored in the table. The access of the data and theparity is performed in the same clock cycle.
If the parity bit does not match the calculated parity, a parity error is generated and the VIM stores theaddress of the error in the ADDERR register. The parity flag error (PARFLG) is set.
NOTE: The PARFLG register is only for bypassing the interrupt vector table in case of a parity fault.
It should be used only to maintain the interrupt vector table bypassed. The checking of theparity fault should be done in the error signaling module (ESM) module where all parity
errors are flagged.

Since the interrupt vector table may have an error, the FBPARERR register will provide to the VIC port,
IRQVECREG and FIQVECREG, a fall-back address to an ISR that can restore the interrupt vector table
content. The FBPARERR register should be set before initializing the interrupt in the interrupt vector table,
to avoid branching to an unpredictable location.
The normal operation is restored when the PARFLG is cleared by the CPU. It is recommended to restore
the content of the VIM before clearing the PARFLG.
The parity error signal is forwarded to the ESM.

14.4.2 Enabling and Controlling the VIM Parity
The polarity of VIM parity is controlled by the DEVCR1 register in the system module (address
FFFF FFDCh). The parity enable is controlled by the PARCTL register. After reset, the parity is disabled.
Parity checking can be enabled by writing 0xA (1010b) in the PARENA[3:0] bit field of the PARCTL
register. The default polarity is odd. The polarity can be changed to even by writing 5 (0101b) in the
DEVPARSEL[3:0] bit field of the DEVCR1 register.

14.4.3 Interrupt Vector Table Initialization
After reset, the interrupt vector table content including the parity bits is not initialized. Therefore, the CPU
needs to initialize all of the interrupt addresses into the table, before enabling the corresponding interrupt
channel. If parity is required, this initialization should be done after the parity functionality is enabled. In
this way, the corresponding parity bit will be automatically updated. This initialization is only required whenvectored interrupts are used, index interrupt management does not need the table to be initialized.

412

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Interrupt Vector Table (VIM RAM)

www.ti.com

14.4.4 Interrupt Vector Table Parity Testing
To test the parity checking mechanism, the parity RAM allows manual insertion of faults. This option is
implemented by the test bit in the PARCTL register. Once the bit is set, the parity bits are mapped to
0xFFF82400. After that, user can force faults into the parity bits. Finally, the parity error can be triggeredby reading interrupt vector table (not parity bit) from VIM or CPU.
The interrupt vector table parity can also be verified by inserting faults into interrupt vector table. Once theVIM parity is disabled in system module, user can modify interrupt vector table without impacting the parity
bit. After user re-enable interrupt vector table parity, the parity error can be triggered by reading interrupt
vector table from VIM or CPU.
Figure 14-8. Parity Bit Mapping
32-bit only accessible
31
0xFFF82000

0
Word 0Word 1
Word 2
Word 331
0xFFF82400

SPNU517C – March 2018
Submit Documentation Feedback

1

0

Read 0P0Read 0

P1

Read 0

P2

Read 0P3

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

413

VIM Wakeup Interrupt

www.ti.com

14.5 VIM Wakeup Interrupt
The wakeup interrupts are used to come out of low power mode (LPM). Any interrupt requests can beused to wake up the device. After reset, all interrupt requests are set to wake up from LPM. However, theVIM can mask unwanted interrupt lines for wake-up by using the WAKEENASET and WAKEENACLR
register. The value in REQENASET/REQENACLR does NOT impact the wakeup interrupt.
As shown in Figure 14-9, the WAKEENASET and WAKEENACLR registers will enable/disable an interrupt
for wake-up from low-power mode. All wake-up interrupts are “ORed” into a single signal WAKE_INT
connected to the Global Clock Module.
Figure 14-9. Detail of the IRQ Input
INT_REQ0

WAKEUP0
WAKEENA.0
Controlled by:
WAKEENASET.0
WAKEENACLR.0

INT_REQ1

WAKEUP1
WAKEENA.1
Controlled by:
WAKEENASET.1
WAKEENACLR.1

INT_REQ2

WAKEUP2

OR

WAKE_INT

WAKEENA.2
Controlled by:
WAKEENASET.2
WAKEENACLR.2

INT_REQ95

WAKEUP95
WAKEENA.95
Controlled by:
WAKEENASET.95
WAKEENACLR.95

414

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Capture Event Sources

www.ti.com

14.6 Capture Event Sources
The VIM can select any of the 96 interrupt requests to generate up to two capture events for the real-time
interrupt (RTI) module (see Figure 14-10). The value in REQENASET/REQENACLR does NOT impact thecapture event. Two registers (Section 14.8.16) are available, one for each capture event source.
Figure 14-10. Capture Event Sources
7

CAPEVTSRC0[6:0]7

INT_REQ0
INT_REQ1

INT_REQ0
INT_REQ1CAPEVT0
To RTICAPEVTSRC1[6:0]

CAPEVT1
To RTIINT_REQ94
INT_REQ95

INT_REQ94
INT_REQ95

14.7 Examples
The following sections provide examples about the operation of the VIM.

14.7.1 Examples - Configure CPU To Receive Interrupts
Example 14-1 shows how to set the vector enable (VE) bit in the CP15 R1 register to enable the hardware
vector interrupt. Example 14-2 shows how to enable/disable the IRQ and FIQ through CPSR. As aconvention, the program who calls these subroutines shall preserve register R1 if needed. Example 14-2
can ONLY run in privileged mode. However, in USER mode, the application software can force theprogram into software interrupt by instruction SWI. Then, in the software interrupt service routine, user canwrite register SPSR, which is the copy of CPSR in this exception mode.
Example 14-1. Enable Hardware Vector Interrupt (IRQ Only)_HW_Vec_Init
MRC p15 ,#0 ,R1 ,c1 ,c0 ,#0
ORR R1 ,R1 ,#0x01000000
MCR p15 ,#0 ,R1 ,c1 ,c0 ,#0
MOV PC, LR

SPNU517C – March 2018
Submit Documentation Feedback; Mask 0-31 bits except bit 24 in Sys; Ctrl Reg of CORTEX-R4; Enable bit 24

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

415

Examples

www.ti.com

Example 14-2. Enable/Disable IRQ/FIQ through CPSRFIQENABLE .equ 0x40
IRQENABLE .equ 0x80......
_Enable_Fiq
MRS R1, CPSR
BIC R1, R1, #FIQENABLE
MSR CPSR, R1
MOV PC, LR......
_Disable_Irq
MRS R1, CPSRORR R1, R1, #IRQENABLE
MSR CPSR, R1
MOV PC, LR......
_Enable_Irq
MRS R1, CPSR
BIC R1, R1, #IRQENABLE
MSR CPSR, R1
MOV PC, LR

14.7.2 Examples - Register Vector Interrupt and Index Interrupt Handling
Example 14-3 shows the configuration for the exception vectors in Register Vector Interrupt handling. Afterthe interrupt is received by the CPU, the CPU branches to 0x18 (IRQ) or 0x1C (FIQ). The instruction
placed here should be LDR PC, [PC,#-0x1B0]. The pending ISR address is written into the corresponding
vector register (IRQVECREG for IRQ, FIQVECREG for FIQ). The CPU reads the content of the registerand branches to the ISR.
Example 14-3. Exception Vector Configuration for VIM Vector.sect ".intvecs"
00000000h b _RESET
00000004h b _UNDEF_INST_INT
00000008h b _SW_INT
0000000Ch b _ABORT_PREF_INT
00000010h b _ABORT_DATA_INT
00000014h b #-800000018h ldr pc,[pc,#-0x1B0]
0000001Ch ldr pc,[pc,#-0x1B0]; RESET interrupt; UNDEFINED INSTRUCTION interrupt; SOFTWARE interrupt; ABORT (PREFETCH) interrupt; ABORT (DATA) interrupt; Reserved; IRQ interrupt; FIQ interrupt

NOTE: Program Counter (PC) always pointers two instructions beyond the current executed
instruction. In this case, PC equals to ‘0x18 or 0x1C + 0x08’. The LDR instruction load thememory at ‘PC - 0x1B0’, which is ‘0x18 or 0x1C + 0x08 - 0x1B0 = 0xFFFFFE70 or
0xFFFFFE74’. These are the address of IRQVECREG and FIQVECREG, which store thepending ISR address.

416

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Examples

www.ti.com

Example 14-4 shows a fast response to the FIQ interrupt in Index Interrupt and can be applied to a systemthat has more than one channel assigned as a FIQ. It is built in Index Interrupt compatible with
TMS470R1x legacy code.
Example 14-4. How to Respond to FIQ With Short Latency.sect ".intvecs"
00000000h b _RESET
00000004h b _UNDEF_INST_INT
00000008h b _SW_INT
0000000Ch b _ABORT_PREF_INT
00000010h b _ABORT_DATA_INT
00000014h b #-800000018h b _IRQ_ENTRY_0

0000001Ch ldrb R8, [PC,#-0x21d]

00000020h ldr PC, [PC, R8, LSL#2]

00000024h nop
00000028h _INT_TABLE
0000002Ch .word _FIQ_TABLE
00000030h .word _ISR100000034h .word _ISR2.
.

; Interrupt and exception vector sector; RESET interrupt; UNDEFINED INSTRUCTION interrupt; SOFTWARE interrupt; ABORT (PREFETCH) interrupt; ABORT (DATA) interrupt; Reserved; IRQ interrupt;*********************************; INTERRUPT PROCESSING AREA;*********************************; FIQ INTERRUPT ENTRY; R8 used to get the FIQ index; with address pointer to the; first FIQ banked register; Branch to the indexed interrupt; routine. The prefetch; operation causes the PC to be 2
; words (8 bytes) ahead of the; current instruction, so; pointing to _INT_TABLE.
; Required due to pipeline.
;=================================; FIQ INTERRUPT DISPATCH;=================================; beginning of FIQ Dispatch; dispatch to interrupt routine 1; dispatch to interrupt routine 2

Another way to improve the FIQ latency is to assign only one channel to the FIQ interrupt and to map the
ISR code corresponding to this channel directly starting at 0x1C.
NOTE: When the CPU is in vector-enabled mode, Example 14-3 and Example 14-4 are still valid.
The difference is that the CPU will not read from the 0x18 location during IRQ interrupt, butwill jump directly to the corresponding ISR routine.

SPNU517C – March 2018
Submit Documentation Feedback

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

417

VIM Control Registers

www.ti.com

14.8 VIM Control Registers
This section details the VIM module registers, summarized in Table 14-1.
Each register begins on a word boundary. All registers are 32-bit, 16-bit, and 8-bit accessible for read andwrite. Write is only possible in privilege mode. The base address of the control registers is FFFF FE00h.
The base address of the parity-related VIM registers is FFFF FD00h. The address locations not listed arereserved.
Table 14-1. VIM Control Registers
OffsetAcronym

Register Description

SectionParity-related Registers
ECh

PARFLGInterrupt Vector Table Parity Flag Register

Section 14.8.1

F0h

PARCTLInterrupt Vector Table Parity Control Register

Section 14.8.2

F4h

ADDERR

Address Parity Error Register

Section 14.8.3

F8h

FBPARERR

Fall-Back Address Parity Error Register

Section 14.8.4

Control Registers
00h

IRQINDEX

IRQ Index Offset Vector Register

Section 14.8.6

04h

FIQINDEX

FIQ Index Offset Vector Register

Section 14.8.7

10h

FIRQPR0FIQ/IRQ Program Control Register 0

Section 14.8.8

14h

FIRQPR1

FIQ/IRQ Program Control Register 1

Section 14.8.8

18h

FIRQPR2

FIQ/IRQ Program Control Register 2

Section 14.8.8

20h

INTREQ0

Pending Interrupt Read Location Register 0

Section 14.8.9

24h

INTREQ1

Pending Interrupt Read Location Register 1

Section 14.8.9

28h

INTREQ2

Pending Interrupt Read Location Register 2

Section 14.8.930h

REQENASET0

Interrupt Enable Set Register 0

Section 14.8.10

34h

REQENASET1

Interrupt Enable Set Register 1

Section 14.8.10

38h

REQENASET2Interrupt Enable Set Register 2

Section 14.8.10

40h

REQENACLR0Interrupt Enable Clear Register 0

Section 14.8.11

44h

REQENACLR1Interrupt Enable Clear Register 1

Section 14.8.11

48h

REQENACLR2Interrupt Enable Clear Register 2

Section 14.8.11

50h

WAKEENASET0

Wake-up Enable Set Register 0

Section 14.8.12

54h

WAKEENASET1

Wake-up Enable Set Register 1

Section 14.8.12

58h

WAKEENASET2

Wake-up Enable Set Register 2

Section 14.8.12

60h

WAKEENACLR0

Wake-up Enable Clear Register 0

Section 14.8.13

64h

WAKEENACLR1

Wake-up Enable Clear Register 1

Section 14.8.13

68h

WAKEENACLR2

Wake-up Enable Clear Register 2

Section 14.8.13

70h

IRQVECREG

IRQ Interrupt Vector Register

Section 14.8.14

74h

FIQVECREG

FIQ Interrupt Vector Register

Section 14.8.15

78h

CAPEVT

Capture Event Register

Section 14.8.16

CHANCTRL

VIM Interrupt Control Register

Section 14.8.17

80h-DCh418

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

VIM Control Registers

www.ti.com

14.8.1

Interrupt Vector Table Parity Flag Register (PARFLG)

Figure 14-11 and Table 14-2 describe this register.
Figure 14-11. Interrupt Vector Table Parity Flag Register (PARFLG) [offset = ECh]
31

16
Reserved
R-0

15

1

0

Reserved

PARFLG

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 14-2. Interrupt Vector Table Parity Flag Register (PARFLG) Field Descriptions
Bit

Field

31-1

Reserved

Value

0

PARFLG

0

Description
Read returns 0. Writes have no effect.
The PARFLG indicates that a parity error has been found and that the Interrupt Vector Table isbypassed. The resulting vector of any IRQ/FRQ interrupt is then the value contained in the
FBPARERR register until this bit has been cleared.

0

Read: No parity error has occurred.
Write: A write to this bit has no effect.

1

Read: A parity error has occurred and the Interrupt Vector Table is bypassed.
Write: The PARFLG is cleared and the interrupt vector can be read from the Interrupt Vector Table.

14.8.2 Interrupt Vector Table Parity Control Register (PARCTL)
Figure 14-12. Interrupt Vector Table Parity Control Register (PARCTL) [offset = F0h]
31

16
Reserved
R-0

15

9

8

7

4

3

0

Reserved

TEST

Reserved

PARENA

R-0

R/WP-0R-0

R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 14-3. Interrupt Vector Table Parity Control Register (PARCTL) Field Descriptions
Bit

Field

31-9

Reserved

8

Value
0

TEST

7-4

Reserved

3-0

PARENA

Description
Read returns 0. Writes have no effect.
This bit maps the parity bits into the Interrupt Vector Table frame to make them accessible by theCPU.

0

Parity bits are not memory mapped.

1

Parity bits are memory mapped.

0

Read returns 0. Writes have no effect.
VIM parity enable.

5h

The VIM parity is disabled.

All Others

The VIM parity is enabled.
Note: To avoid soft error to disable VIM parity checking, it is recommended to write Ah toenable parity checking.

SPNU517C – March 2018
Submit Documentation Feedback

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

419

VIM Control Registers

www.ti.com

14.8.3 Address Parity Error Register (ADDERR)
The address parity error register gives the address of the first parity error location.
NOTE: No computation is needed when reading the complete register to retrieve the address in theInterrupt Vector Table.
This register will never be reset by a power-on reset nor any other reset source.

Figure 14-13. Address Parity Error Register (ADDERR) [offset = F4h]31

16Interrupt Vector Table offset
R-FFF8h

15

9

8

2

1

0

Interrupt Vector Table offset

ADDERR

Word offset

R-0010 000b

R-x

R-0

LEGEND: R = Read only; -n = value after reset

Table 14-4. Address Parity Error Register (ADDERR) Field Descriptions
Bit

Field

Description

31-9Interrupt Vector Table
offsetInterrupt Vector Table offset. Reads are always FFF8 2xxxh; writes have no effect.

8-2

ADDERR

Address parity error register. This register gives the address of the first encountered parity error since
the flag has been clear. Subsequent parity errors will not update this register until the PARFLG registerhas been cleared.

1-0

Word offset

Note: This register is valid only when PARFLG is set (see Section 14.8.1).
Word offset. Reads are always 0; writes have no effect.

14.8.4 Fall-Back Address Parity Error Register (FBPARERR)
This register provides a fall-back address to the VIM if a parity error has occurred in the Interrupt Vector
Table. Figure 14-14 and Table 14-5 describe this register.
NOTE: This register will never be reset by a power-on reset nor any other reset source.

Figure 14-14. Fall-Back Address Parity Error Register (FBPARERR) [offset = F8h]
31

16
FBPARERR
R/WP-x150
FBPARERR
R/WP-xLEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset; x = Indeterminate

Table 14-5. Fall Back Address Parity Error Register (FBPARERR) Field Descriptions
Bit

Field

31-0

FBPARERR

Value
0-FFFF FFFFh

Description
Fall back address parity error. This register is used by the VIM if the Interrupt Vector Table
has been corrupted. The contents of the IRQVECREG and FIQVECREG registers will reflect
the value programmed in FBPARERR. The value provided to the VIC port will also reflect
FBPARERR until the PARFLG register has been cleared.
This register provides the address of the ISR that will restore the integrity of the Interrupt
Vector Table.

420

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

VIM Control Registers

www.ti.com

14.8.5 VIM Offset Vector Registers
The VIM offset register provides the user with the numerical index value that represents the pending
interrupt with the highest precedence. The register IRQINDEX holds the index to the highest priority IRQ
interrupt; the register FIQINDEX holds the index to the highest priority FIQ interrupt. The index can beused to locate the interrupt routine in a dispatch table, as shown in Table 14-6.
Table 14-6. Interrupt Dispatch
IRQINDEX / FIQINDEX Register Bit Field

Highest Priority Pending Interrupt Enabled

0x00

No interrupt

0x01

Channel 0

:

:

0x5F

Channel 94

0x60

Channel 95

NOTE: Channel 95 has no dedicated interrupt vector table entry. Therefore, Channel 95 shall NOT
be used in application.

The VIM offset registers are read only. They are updated continuously by the VIM. When an interrupt isserviced, the offset vectors show the index for the next highest pending interrupt or 0x0 if no interrupt is
pending.

SPNU517C – March 2018
Submit Documentation Feedback

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

421

VIM Control Registers

www.ti.com

14.8.6 IRQ Index Offset Vector Register (IRQINDEX)The IRQ offset register provides the user with the numerical index value that represents the pending IRQ
interrupt with the highest priority. Figure 14-15 and Table 14-7 describe this register.
Figure 14-15. IRQ Index Offset Vector Register (IRQINDEX) [offset = 00h]
31

16
Reserved
R-0

15

8

7

0

Reserved

IRQINDEX

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 14-7. IRQ Index Offset Vector Register (IRQINDEX) Field Descriptions
Bit

Field

Value

31-8

Reserved0

7-0

IRQINDEX

0-FFh

Description
Read returns 0. Writes have no effect.
IRQ index vector. The least-significant bits represent the index of the IRQ pending interrupt withthe highest precedence, as shown in Table 14-6. When no interrupts are pending, the leastsignificant byte of IRQINDEX is 0.
Note: A read of register IRQINDEX or IRQVECREG will cause IRQINDEX / IRQVECREG toreflect the index/ISR address for the next highest-priority pending IRQ interrupt. In case there isno other interrupt pending, the IRQINDEX will read 0x00 and the IRQVECREG register will readthe phantom interrupt address.

14.8.7 FIQ Index Offset Vector Registers (FIQINDEX)The FIQINDEX register provides the user with a numerical index value that represents the pending FIQ
interrupt with the highest priority. Figure 14-16 and Table 14-8 describe this register.
Figure 14-16. FIQ Index Offset Vector Register (FIQINDEX) [offset = 04h]
31

16
Reserved
R-0

15

8

7

0

Reserved

FIQINDEX

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 14-8. FIQ Index Offset Vector Register (FIQINDEX) Field Descriptions
Bit

Field

31-8

Reserved0

7-0

FIQINDEX

0-FFh

422

Value

Description
Read returns 0. Writes have no effect.
FIQ index offset vector. The least-significant bits represent the index of the FIQ pending
interrupt with the highest precedence, as shown in Table 14-6. When no interrupts are pending,the least-significant byte of FIQINDEX is 0x00.
Note: A read of register FIQINDEX or FIQVECREG will cause FIQINDEX / FIQVECREG toreflect the index/ISR address for the next highest-priority pending FIQ interrupt. In case there isno other interrupt pending, the FIQINDEX will read 0x00 and the FIQVECREG register will readthe phantom interrupt address.

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

VIM Control Registers

www.ti.com

14.8.8 FIQ/IRQ Program Control Registers (FIRQPR[0:2])
The FIQ/IRQ program control registers (FIRQPRx) determine whether a given interrupt request will beeither FIQ or IRQ. Figure 14-17, Figure 14-18, Figure 14-19 and Table 14-9 describe these registers.
NOTE: Channel 0 and 1 are FIQ only, not impacted by this register.

Figure 14-17. FIQ/IRQ Program Control Register 0 (FIRQPR0) [offset = 10h]
31

16
FIRQPR0[31:16]
R/WP-0

15

2

1

0

FIRQPR0[15:2]

Reserved

R/WP-0R-3h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Figure 14-18. FIQ/IRQ Program Control Register 1 (FIRQPR1) [offset = 14h]
31

16
FIRQPR1[63:48]
R/WP-015

0FIRQPR1[47:32]
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Figure 14-19. FIQ/IRQ Program Control Register 2 (FIRQPR2) [offset = 18h]
31

16
FIRQPR2[95:80]
R/WP-015

0FIRQPR2[79:64]
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 14-9. FIQ/IRQ Program Control Registers (FIRQPRx) Field Descriptions
Bit

Field

95-2

FIRQPRx[95:2]

1-0

Value

Reserved

SPNU517C – March 2018
Submit Documentation Feedback

Description
FIQ/IRQ program control bits. These bits determine whether an interrupt request from a peripheral
is of type FIQ or IRQ. Bit FIRQPRx[95:2] corresponds to request channel[95:2].

0

Interrupt request is of IRQ type.

1

Interrupt request is of FIQ type.

3h

Read only. Writes have no effect.

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

423

VIM Control Registers

www.ti.com

14.8.9 Pending Interrupt Read Location Registers (INTREQ[0:2])
The pending interrupt registers (INTREQx) give the pending interrupt requests. The register is updated
every vbus clock cycle. Figure 14-20, Figure 14-21, Figure 14-22 and Table 14-10 describe this register.
Figure 14-20. Pending Interrupt Read Location Register 0 (INTREQ0) [offset = 20h]
31

16
INTREQ0[31:16]
R/W1CP-0

150
INTREQ0[15:0]
R/W1CP-0

LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset

Figure 14-21. Pending Interrupt Read Location Register 1 (INTREQ1) Register [offset = 24h]
31

16
INTREQ1[63:48]
R/W1CP-0

150
INTREQ1[47:32]
R/W1CP-0

LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset

Figure 14-22. Pending Interrupt Read Location Register 2 (INTREQ2) Register [offset = 28h]
31

16
INTREQ2[95:80]
R/W1CP-0

150
INTREQ2[79:64]
R/W1CP-0

LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset

Table 14-10. Pending Interrupt Read Location Registers (INTREQx) Field Descriptions
Bit

Field

95-0

INTREQx[95:0]

Value

Description
Pending interrupt bits. These bits determine whether an interrupt request is pending for the request
channel between 0 and 95. The interrupt ENABLE register does not affect the value of the interrupt
pending bit. Bit INTREQx[95:0] corresponds to request channel[95:0].
User and Privilege Mode read:0

No interrupt event has occurred.

1

An interrupt is pending.
Privilege Mode write only:

424

0

Writing 0 has no effect.

1

Clears the interrupt pending status flag. This write-clear functionality is intended to allow clearing
those interrupts which have been signaled to VIM before enabling the interrupt channel, if they are
undesired.

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

VIM Control Registers

www.ti.com

14.8.10 Interrupt Enable Set Registers (REQENASET[0:2])
The interrupt enable set registers (REQENASETx) selectively enables individual request channels.
Figure 14-23, Figure 14-24, Figure 14-25 and Table 14-11 describe these registers.
NOTE: Channel 0 and 1 are always enabled, not impacted by this register.

Figure 14-23. Interrupt Enable Set Register 0 (REQENASET0) [offset = 30h]
31

16
REQENASET0[31:16]
R/WP-0

15

2

1

0

REQENASET0[15:2]

Reserved

R/WP-0R-3h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Figure 14-24. Interrupt Enable Set Register 1 (REQENASET1) [offset = 34h]
31

16
REQENASET1[63:48]
R/WP-015

0REQENASET1[47:32]
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Figure 14-25. Interrupt Enable Set Register 2 (REQENASET2) [offset = 38h]
31

16
REQENASET2[95:80]
R/WP-015

0REQENASET2[79:64]
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 14-11. Interrupt Enable Set Registers (REQENASETx) Field Descriptions
Bit

Field

95-2

REQENASETx[95:2]

Value

Description
Request enable set bits. This vector determines whether the interrupt request channel isenabled. Bit REQENASETx[95:2] corresponds to request channel[95:2].

0

Read: Interrupt request channel is disabled.
Write: A write of 0 has no effect.

1-0

Reserved

SPNU517C – March 2018
Submit Documentation Feedback

1

Read or Write: The interrupt request channel is enabled.

3h

Read only. Writes have no effect.

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

425

VIM Control Registers

www.ti.com

14.8.11 Interrupt Enable Clear Registers (REQENACLR[0:2])
The interrupt enable clear registers (REQENACLRx) selectively disables individual request channels.
Figure 14-26, Figure 14-27, Figure 14-28 and Table 14-12 describe these registers.
NOTE: Channel 0 and 1 are always enabled, not impacted by this register.

Figure 14-26. Interrupt Enable Clear Register 0 (REQENACLR0) [offset = 40h]
31

16
REQENACLR0[31:16]
R/WP-0

15

2

1

0

REQENACLR0[15:2]

Reserved

R/WP-0R-3h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Figure 14-27. Interrupt Enable Clear Register 1 (REQENACLR1) [offset = 44h]
31

16
REQENACLR1[63:48]
R/WP-015

0REQENACLR1[47:32]
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Figure 14-28. Interrupt Enable Clear Register 2 (REQENACLR2) [offset = 48h]
31

16
REQENACLR2[95:80]
R/WP-015

0REQENACLR2[79:64]
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 14-12. Interrupt Enable Clear Registers (REQENACLRx) Field Descriptions
Bit

Field

95-2

REQENACLRx[95:2]

Value

Description
Request enable clear bits. This vector determines whether the interrupt request channel isenabled. Bit REQENACLRx[95:2] corresponds to request channel[95:2].

0

Read: Interrupt request channel is disabled.
Write: A write of 0 has no effect.

1

Read: The interrupt request channel is enabled.
Write: The interrupt request channel is disabled.

1-0

426

Reserved

3h

Read only. Writes have no effect.

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

VIM Control Registers

www.ti.com

14.8.12 Wake-Up Enable Set Registers (WAKEENASET[0:2])
The wake-up enable set registers (WAKEENASETx) selectively enables individual wake-up interrupt
request lines. Figure 14-29, Figure 14-30, Figure 14-31 and Table 14-13 describe these registers.
Figure 14-29. Wake-Up Enable Set Register 0 (WAKEENASET0) [offset = 50h]
31

16
WAKEENASET0[31:16]
R/WP-FFFFh

15

0
WAKEENASET0[15:0]
R/WP-FFFFh

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Figure 14-30. Wake-Up Enable Set Register 1 (WAKEENASET1) [offset = 54h]
31

16
WAKEENASET1[63:48]
R/WP-FFFFh

15

0
WAKEENASET1[47:32]
R/WP-FFFFh

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Figure 14-31. Wake-Up Enable Set Register 2 (WAKEENASET2) [offset = 58h]
31

16
WAKEENASET2[95:80]
R/WP-FFFFh

15

0
WAKEENASET2[79:64]
R/WP-FFFFh

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Table 14-13. Wake-Up Enable Set Registers (WAKEENASETx) Field Descriptions
Bit

Field

95-0

WAKEENASETx[95:0]

Value

Description
Wake-up enable set bits. This vector determines whether the wake-up interrupt line is enabled.
Bit WAKEENASETx[95:0] corresponds to interrupt request channel[95:0].

0

Read: Interrupt request channel is disabled.
Write: A write of 0 has no effect.

1

SPNU517C – March 2018
Submit Documentation Feedback

Read or Write: The interrupt request channel is enabled.

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

427

VIM Control Registers

www.ti.com

14.8.13 Wake-Up Enable Clear Registers (WAKEENACLR[0:2])
The wake-up enable clear registers (WAKEENACLRx) selectively disables individual wake-up interrupt
request lines. Figure 14-32, Figure 14-33, Figure 14-34 and Table 14-14 describe these registers.
Figure 14-32. Wake-Up Enable Clear Register 0 (WAKEENACLR0) [offset = 60h]
31

16
WAKEENACLR0[31:16]
R/WP-FFFFh

15

0
WAKEENACLR0[15:0]
R/WP-FFFFh

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Figure 14-33. Wake-Up Enable Clear Register 1 (WAKEENACLR1) [offset = 64h]
31

16
WAKEENACLR1[63:48]
R/WP-FFFFh

15

0
WAKEENACLR1[47:32]
R/WP-FFFFh

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Figure 14-34. Wake-Up Enable Clear Register 2 (WAKEENACLR2) [offset = 68h]
31

16
WAKEENACLR2[95:80]
R/WP-FFFFh

15

0
WAKEENACLR2[79:64]
R/WP-FFFFh

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Table 14-14. Wake-Up Enable Clear Registers (WAKEENACLRx) Field Descriptions
Bit

Field

95-0

WAKEENACLRx[95:0
]

Value

Description
Wake-up enable clear bits. This vector determines whether the wake-up interrupt line isenabled. Bit WAKEENACLRx[95:0] corresponds to interrupt request channel[95:0].

0

Read: Wake-up interrupt channel is disabled.
Write: A write of 0 has no effect.

1

Read: The wake-up interrupt channel is enabled.
Write: The wake-up interrupt channel is disabled.

428

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

VIM Control Registers

www.ti.com

14.8.14 IRQ Interrupt Vector Register (IRQVECREG)
The interrupt vector register gives the address of the enabled and active IRQ interrupt. Figure 14-35 andTable 14-15 describe these registers.
Figure 14-35. IRQ Interrupt Vector Register (IRQVECREG) [offset = 70h]
31

16
IRQVECREG
R-0

15

0
IRQVECREG
R-0

LEGEND: R = Read only; -n = value after reset

Table 14-15. IRQ Interrupt Vector Register (IRQVECREG) Field Descriptions
Bit

Field

31-0

IRQVECREG

Value
From
Section 14.4

Description
IRQ interrupt vector register. This vector gives the address of the ISR with the highest
pending IRQ request. The CPU reads the address and branches to this location.
Note: A read of register IRQINDEX or IRQVECREG will cause IRQINDEX / IRQVECREG toreflect the index/ISR address for the next highest-priority pending IRQ interrupt. In case there
is no other interrupt pending, the IRQINDEX will read 0x00 and the IRQVECREG register will
read the phantom interrupt address.

14.8.15 FIQ Interrupt Vector Register (FIQVECREG)
The interrupt vector register gives the address of the enabled and active FIQ interrupt. Figure 14-36 andTable 14-16 describe these registers.
Figure 14-36. IRQ Interrupt Vector Register (FIQVECREG) [offset = 74h]
31

16
FIQVECREG
R-0

15

0
FIQVECREG
R-0

LEGEND: R = Read only; -n = value after reset; X = Unknown

Table 14-16. FIQ Interrupt Vector Register (FIQVECREG) Field Descriptions
Bit

Field

31-0

FIQVECREG

Value
From
Section 14.4

SPNU517C – March 2018
Submit Documentation Feedback

Description
FIQ interrupt vector register. This vector gives the address of the ISR with the highest
pending FIQ request. The CPU reads the address and branches to this location.
Note: A read of register FIQINDEX or FIQVECREG will cause FIQINDEX / FIQVECREG toreflect the index/ISR address for the next highest-priority pending FIQ interrupt. In case there
is no other interrupt pending, the FIQINDEX will read 0x00 and the FIQVECREG register will
read the phantom interrupt address.

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

429

VIM Control Registers

www.ti.com

14.8.16 Capture Event Register (CAPEVT)
Figure 14-37 and Table 14-17 describe this register.
Figure 14-37. Capture Event Register (CAPEVT) [offset = 78h]
31

23

22

16

Reserved

CAPEVTSRC1

R-U

R/W-0

15

7

6

0

Reserved

CAPEVTSRC0

R-U

R/W-0

LEGEND: R/W = Read/Write; R = Read only; U = Undefined; -n = value after reset

Table 14-17. Capture Event Register (CAPEVT) Field Descriptions
Bit

Field

31-23

Reserved

22-16

CAPEVTSRC1

15-7

Reserved

6-0

CAPEVTSRC0

Value
0

Reads are indeterminate and writes have no effect.
Capture event source 1 mapping control. These bits determine which interrupt request maps to thecapture event source 1 of the RTI:

0

Interrupt request 0.

1hInterrupt request 1.

:

:

5Fh

Interrupt request 95.

0

Reads are indeterminate and writes have no effect.
Capture event source 0 mapping control. These bits determine which interrupt request maps to thecapture event source 0 of the RTI:

0

Interrupt request 0.

1hInterrupt request 1.

:

:

5Fh

430

Description

Interrupt request 95.

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

VIM Control Registers

www.ti.com

14.8.17 VIM Interrupt Control Registers (CHANCTRL[0:23])
Twenty-four interrupt control registers control the 96 interrupt channels of the VIM. Each register controls
four interrupt channels: each of them is indexed from 0 to 95. Table 14-18 shows the organization of all
the registers and the reset value of each. Each four fields of the register has been named with a genericindex that refers to the detailed register organization. Figure 14-38 and Table 14-19 describe theseregisters.
Table 14-18. Interrupt Control Registers Organization

Address

RegisterAcronym

Register Field
31:24
CHANMAPx0

Register Field
23:16
CHANMAPx1

Register Field
15:8
CHANMAPx2

Register Field
7:0
CHANMAPx3

Reset Value

FFFF FE80h

CHANCTRL0

CHANMAP0

CHANMAP1

CHANMAP2CHANMAP30001 0203h

FFFF FE84h

CHANCTRL1

CHANMAP4CHANMAP5CHANMAP6CHANMAP70405 0607h

:

:

:

:

:

:

:

FFFF FED8h

CHANCTRL22

CHANMAP88

CHANMAP89

CHANMAP90

CHANMAP91

5859 5A5Bh

FFFF FEDCh

CHANCTRL23

CHANMAP92

CHANMAP93

CHANMAP94

CHANMAP95

5C5D 5E5Fh

NOTE: CHANMAP0 and CHANMAP1 are not programable. CHAN0 and CHAN1 are hard wired to
INT_REQ0 and INT_REQ1.
Do NOT write any value other than 0x5F to CHANMAP95. Channel 95 is reserved because
no interrupt vector table entry supports this channel.

Figure 14-38. Interrupt Control Registers (CHANCTRL[0:23])[offset = 80h-DCh]
31

30

24

23

22

16

Rsvd

CHANMAPx0

Rsvd

CHANMAPx1

R-U

R/W-n

R-U

R/W-n

15

14

8

7

6

0

Rsvd

CHANMAPx2

Rsvd

CHANMAPx3

R-U

R/W-n

R-U

R/W-n

LEGEND: R/W = Read/Write; R = Read only; U = Undefined; -n = value after reset (see Table 14-18)

Table 14-19. Interrupt Control Registers (CHANCTRLx) Field Descriptions
Bit

Field

31

Reserved

30-24

Value
0

CHANMAPx0

Description
Reads are indeterminate and writes have no effect.
CHANMAPx0(6-0). Interrupt CHANx0 mapping control. These bits determine which interrupt request
the priority channel CHANx0 maps to:0

Read: Interrupt request 0 maps to channel priority CHANx0.
Write: The default value of this bit after reset is given in Table 14-18 . The channel priority CHANx0
is set with the interrupt request.

1h

Read: Interrupt request 1 maps to channel priority CHANx0.
Write: The default value of this bit after reset is given in Table 14-18. The channel priority CHANx0
is set with the interrupt request.

:
5Fh

:
Read: Interrupt request 95 maps to channel priority CHANx0.
Write: The default value of this bit after reset is given in Table 14-18. The channel priority CHANx0
is set with the interrupt request.

23

Reserved

SPNU517C – March 2018
Submit Documentation Feedback0

Reads are indeterminate and writes have no effect.

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

431

VIM Control Registers

www.ti.com

Table 14-19. Interrupt Control Registers (CHANCTRLx) Field Descriptions (continued)
Bit

Field

22-16

CHANMAPx1

Value

Description
CHANMAPx1(6-0). Interrupt CHANx1 mapping control. These bits determine which interrupt request
the priority channel CHANx1 maps to:0

Read: Interrupt request 0 maps to channel priority CHANx1.
Write: The default value of this bit after reset is given in Table 14-18. The channel priority CHANx1
is set with the interrupt request.

1h

Read: Interrupt request 1 maps to channel priority CHANx1.
Write: The default value of this bit after reset is given in Table 14-18. The channel priority CHANx1
is set with the interrupt request.

:
5Fh

:
Read: Interrupt request 95 maps to channel priority CHANx1.
Write: The default value of this bit after reset is given in Table 14-18. The channel priority CHANx1
is set with the interrupt request.

15

Reserved

14-8

CHANMAPx20

Reads are indeterminate and writes have no effect.
CHANMAPx2(6-0). Interrupt CHANx2 mapping control. These bits determine which interrupt request
the priority channel CHANx2 maps to:0

Read: Interrupt request 0 maps to channel priority CHANx2.
Write: The default value of this bit after reset is given in Table 14-18. The channel priority CHANx2
is set with the interrupt request.

1h

Read: Interrupt request 1 maps to channel priority CHANx2.
Write: The default value of this bit after reset is given in Table 14-18. The channel priority CHANx2
is set with the interrupt request.

:
5Fh

:
Read: Interrupt request 95 maps to channel priority CHANx2.
Write: The default value of this bit after reset is given in Table 14-18. The channel priority CHANx2
is set with the interrupt request.

7

Reserved

6-0

CHANMAPx30

Reads are indeterminate and writes have no effect.
CHANMAPx3(6-0). Interrupt CHANx3 mapping control. These bits determine which interrupt request
the priority channel CHANx3 maps to:0

Read: Interrupt request 0 maps to channel priority CHANx3.
Write: The default value of this bit after reset is given in Table 14-18. The channel priority CHANx3
is set with the interrupt request.

1h

Read: Interrupt request 1 maps to channel priority CHANx3.
Write: The default value of this bit after reset is given in Table 14-18. The channel priority CHANx3
is set with the interrupt request.

:
5Fh

:
Read: Interrupt request 95 maps to channel priority CHANx3.
Write: The default value of this bit after reset is given in Table 14-18. The channel priority CHANx3
is set with the interrupt request.

432

Vectored Interrupt Manager (VIM) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Chapter 15
SPNU517C – March 2018

Enhanced Quadrature Encoder Pulse (eQEP) Module
The enhanced quadrature encoder pulse (eQEP) module is used for direct interface with a linear or rotaryincremental encoder to get position, direction, and speed information from a rotating machine for use in ahigh-performance motion and position-control system.
Topic

15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9

...........................................................................................................................

Page

Introduction ..................................................................................................... 434
Description ...................................................................................................... 436
Quadrature Decoder Unit (QDU) ......................................................................... 439
Position Counter and Control Unit (PCCU) .......................................................... 442
eQEP Edge Capture Unit ................................................................................... 449
eQEP Watchdog ............................................................................................... 452
Unit Timer Base................................................................................................ 452
eQEP Interrupt Structure ................................................................................... 453
eQEP Registers ................................................................................................ 454

SPNU517C – March 2018
Submit Documentation Feedback

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

433

Introduction

www.ti.com

15.1 Introduction
A single track of slots patterns the periphery of an incremental encoder disk, as shown in Figure 15-1.
These slots create an alternating pattern of dark and light lines. The disk count is defined as the numberof dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second track is added togenerate a signal that occurs once per revolution (index signal: QEPI), which can be used to indicate anabsolute position. Encoder manufacturers identify the index pulse using different terms such as index,
marker, home position, and zero reference
Figure 15-1. Optical Encoder Disk
QEPA

QEPB

QEPI

To derive direction information, the lines on the disk are read out by two different photo-elements that"look" at the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. This shift isrealized with a reticle or mask that restricts the view of the photo-element to the desired part of the disk
lines. As the disk rotates, the two photo-elements generate signals that are shifted 90° out of phase fromeach other. These are commonly called the quadrature QEPA and QEPB signals. The clockwise direction
for most encoders is defined as the QEPA channel going positive before the QEPB channel and viseversa as shown in Figure 15-2.
Figure 15-2. QEP Encoder Output Signal for Forward/Reverse Movement
T0

Clockwise shaft rotation/forward movement
0

1

2

3

4

5

6

7

N−6 N−5 N−4 N−3 N−2 N−1

0

QEPA
QEPB
QEPI

T0

Anti-clockwise shaft rotation/reverse movement0

N−1 N−2 N−3 N−4 N−5 N−6 N−7

6

5

4

3

2

1

0

N−1 N−2

QEPA
QEPB
QEPI

Legend: N = lines per revolution

The encoder wheel typically makes one revolution for every revolution of the motor or the wheel may be ata geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming fromthe QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line
encoder directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of
166.6 KHz, so by measuring the frequency of either the QEPA or QEPB output, the processor candetermine the velocity of the motor.
434

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Introduction

www.ti.com

Quadrature encoders from different manufacturers come with two forms of index pulse (gated index pulse
or ungated index pulse) as shown in Figure 15-3. A nonstandard form of index pulse is ungated. In theungated configuration, the index edges are not necessarily coincident with A and B signals. The gatedindex pulse is aligned to any of the four quadrature edges and width of the index pulse and can be equal
to a quarter, half, or full period of the quadrature signal.
Figure 15-3. Index Pulse Example
T0
QEPA

QEPB

0.25T0 ±0.1T0
QEPI(gated to
A and B)
0.5T0 ±0.1T0
QEPI(gated to A)
T0 ±0.5T0
QEPI(ungated)

Some typical applications of shaft encoders include robotics and even computer input in the form of amouse. Inside your mouse you can see where the mouse ball spins a pair of axles (a left/right, and an
up/down axle). These axles are connected to optical shaft encoders that effectively tell the computer how
fast and in what direction the mouse is moving.
General Issues: Estimating velocity from a digital position sensor is a cost-effective strategy in motor
control. Two different first order approximations for velocity may be written as:x(k) * x(k * 1)
v(k) [
+ DX
T
T
(26)
X
X
v(k) [+
t(k) * t(k * 1)
DT
(27)
where
v(k): Velocity at time instant kx(k): Position at time instant kx(k-1): Position at time instant k-1
T: Fixed unit time or inverse of velocity calculation rate
ΔX: Incremental position movement in unit time
t(k): Time instant "k"t(k-1): Time instant "k-1"
X: Fixed unit position
ΔT: Incremental time elapsed for unit position movement.
Equation 26 is the conventional approach to velocity estimation and it requires a time base to provide unit
time event for velocity calculation. Unit time is basically the inverse of the velocity calculation rate.

SPNU517C – March 2018
Submit Documentation Feedback

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

435

Description

www.ti.com

The encoder count (position) is read once during each unit time event. The quantity [x(k) - x(k-1)] is
formed by subtracting the previous reading from the current reading. Then the velocity estimate iscomputed by multiplying by the known constant 1/T (where T is the constant time between unit time
events and is known in advance).
Estimation based on Equation 26 has an inherent accuracy limit directly related to the resolution of theposition sensor and the unit time period T. For example, consider a 500-line per revolution quadrature
encoder with a velocity calculation rate of 400 Hz. When used for position the quadrature encoder gives afour-fold increase in resolution, in this case, 2000 counts per revolution. The minimum rotation that can bedetected is therefore 0.0005 revolutions, which gives a velocity resolution of 12 rpm when sampled at 400
Hz. While this resolution may be satisfactory at moderate or high speeds, for example, 1% error at 1200
rpm, it would clearly prove inadequate at low speeds. In fact, at speeds below 12 rpm, the speed estimate
would erroneously be zero much of the time.
At low speed, Equation 27 provides a more accurate approach. It requires a position sensor that outputs afixed interval pulse train, such as the aforementioned quadrature encoder. The width of each pulse isdefined by motor speed for a given sensor resolution. Equation 27 can be used to calculate motor speedby measuring the elapsed time between successive quadrature pulse edges. However, this method
suffers from the opposite limitation, as does Equation 26. A combination of relatively large motor speeds
and high sensor resolution makes the time interval ΔT small, and thus more greatly influenced by the timer
resolution. This can introduce considerable error into high-speed estimates.
For systems with a large speed range (that is, speed estimation is needed at both low and high speeds),
one approach is to use Equation 27 at low speed and have the application software switch over toEquation 26 when the motor speed rises above some specified threshold.

15.2 Description
This section provides the eQEP inputs, memory map, and functional description.

15.2.1 eQEP Inputs
The eQEP inputs include two pins for quadrature-clock mode or direction-count mode, an index (or 0marker), and a strobe input.
• QEPA/XCLK and QEPB/XDIR
These two pins can be used in quadrature-clock mode or direction-count mode.
– Quadrature-clock Mode
The eQEP encoders provide two square wave signals (A and B) 90 electrical degrees out of phase
whose phase relationship is used to determine the direction of rotation of the input shaft andnumber of eQEP pulses from the index position to derive the relative position information. For
forward or clockwise rotation, QEPA signal leads QEPB signal and vice versa. The quadrature
decoder uses these two inputs to generate quadrature-clock and direction signals.
– Direction-count Mode
In direction-count mode, direction and clock signals are provided directly from the external source.
Some position encoders have this type of output instead of quadrature output. The QEPA pin
provides the clock input and the QEPB pin provides the direction input.
• eQEPI: Index or Zero Marker
The eQEP encoder uses an index signal to assign an absolute start position from which position
information is incrementally encoded using quadrature pulses. This pin is connected to the index
output of the eQEP encoder to optionally reset the position counter for each revolution. This signal canbe used to initialize or latch the position counter on the occurrence of a desired event on the index pin.
• QEPS: Strobe Input
This general-purpose strobe signal can initialize or latch the position counter on the occurrence of adesired event on the strobe pin. This signal is typically connected to a sensor or limit switch to notifythat the motor has reached a defined position.

436

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Description

www.ti.com

15.2.2 Functional Description
The eQEP peripheral contains the following major functional units (as shown in Figure 15-4):• Programmable input qualification for each pin (part of the GPIO MUX)
• Quadrature decoder unit (QDU)• Position counter and control unit for position measurement (PCCU)• Quadrature edge-capture unit for low-speed measurement (QCAP)• Unit time base for speed/frequency measurement (UTIME)• Watchdog timer for detecting stalls (QWDOG)
Figure 15-4. Functional Block Diagram of the eQEP Peripheral
To CPUCDDIS.9

Data bus

VCLK

Enhanced QEP (eQEP) peripheral
QCAPCTL

QCPRD
QCTMR

16

16

16
Quadrature
capture unit
(QCAP)QCTMRLATQCPRDLAT
Registers
used bymultiple units
QEPCTLQEPSTS
QFLG

QUTMR
QUPRD

QWDTMRQWDPRD

32

16

UTIME

UTOUT

QWDOG

QDECCTL
16

WDTOUT
EQEPxINT

QCLK
QDIR
QI

VIM
32

Position counter/
control unit
(PCCU)QPOSLATQPOSSLATQPOSILATSPNU517C – March 2018
Submit Documentation Feedback

QS
PHE

Quadrature
decoder(QDU)

PCSOUT

32

32

16

QPOSCNTQPOSINITQPOSMAXQPOSCMP

QEINT
QFRC
QCLR
QPOSCTL

EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE

EQEPxA/XCLK

GPIO
MUX

EQEPxB/XDIR
EQEPxI
EQEPxS

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

437

Description

www.ti.com

15.2.3 eQEP Memory Map
Table 15-1 lists the registers with their memory locations, sizes, and reset values. See Section 15.9 fordetails of these registers.
Table 15-1. EQEP Memory Map

438

Address
OffsetAcronym

Register Description

Size(×16)/#shadow

00h

QPOSCNTReset

eQEP Position Counter Register

2/00000 0000h

04h

QPOSINITeQEP Initialization Position Count Register

2/00000 0000h

08h

QPOSMAXeQEP Maximum Position Count Register

2/00000 0000h

0Ch

QPOSCMPeQEP Position-compare Register

2/1

0000 0000h

10h

QPOSILAT

eQEP Index Position Latch

2/00000 0000h

14h

QPOSSLAT

eQEP Strobe Position Latch

2/00000 0000h

18h

QPOSLATeQEP Position Latch

2/00000 0000h

1Ch

QUTMR

eQEP Unit Timer Register

2/00000 0000h

20h

QUPRD

eQEP Unit Period Register

2/00000 0000h

26h

QWDTMR

eQEP Watchdog Timer Register

1/0

0000h

24h

QWDPRD

eQEP Watchdog Period Register

1/0

0000h

2Ah

QDECCTL

eQEP Decoder Control Register

1/0

0000h

28h

QEPCTLeQEP Control Register

1/0

0000h

2Eh

QCAPCTL

eQEP Capture Control Register

1/0

0000h

2Ch

QPOSCTL

eQEP Position-compare Control Register

1/0

0000h

32h

QEINT

eQEP Interrupt Enable Register

1/0

0000h

30h

QFLG

eQEP Interrupt Flag Register

1/0

0000h

36h

QCLR

eQEP Interrupt Clear Register

1/0

0000h

34h

QFRC

eQEP Interrupt Force Register

1/0

0000h

3Ah

QEPSTSeQEP Status Register

1/0

0000h

38h

QCTMR

eQEP Capture Timer Register

1/0

0000h

3Eh

QCPRD

eQEP Capture Period Register

1/0

0000h

3Ch

QCTMRLAT

eQEP Capture Timer Latch

1/0

0000h

42h

QCPRDLAT

eQEP Capture Period Latch

1/0

0000h

40h

Reserved

Reserved––

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Quadrature Decoder Unit (QDU)

www.ti.com

15.3 Quadrature Decoder Unit (QDU)
Figure 15-5 shows a functional block diagram of the QDU.
Figure 15-5. Functional Block Diagram of Decoder Unit
QFLG:PHEQEPSTS:QDF

QDECCTL:SWAP

QDECCTL:QAP

PHE

00
01

QCLK

10
11

iCLK
xCLK
xCLK
xCLK

QA

QDIR

10
11

EQEPxAIN

0
1

1
Quadrature
decoder

EQEPB
QB

00
01

0

EQEPA

EQEPxBIN

0

0
1

iDIR
xDIR

1
QDECCTL:QBP

1
0
x1
x2

x1, x22QDECCTL:XCR

QDECCTL:QSRC

QDECCTL:QIP
EQEPxIIN

0
0

QI

1
1
QDECCTL:IGATEEQEPxSIN

0QS

1QDECCTL:QSPQDECCTL:SPSEL

EQEPxIOUT0

PCSOUT

EQEPxSOUT
1
QDECCTL:SPSEL
EQEPxIOE

0QDECCTL:SOEN

EQEPxSOE

1

15.3.1 Position Counter Input Modes
Clock and direction input to position counter is selected using QDECCTL[QSRC] bits, based on interface
input requirement as follows:• Quadrature-count mode
• Direction-count mode
• Up-count mode
• Down-count mode
SPNU517C – March 2018
Submit Documentation Feedback

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

439

Quadrature Decoder Unit (QDU)

www.ti.com

15.3.1.1 Quadrature Count Mode
The quadrature decoder generates the direction and clock to the position counter in quadrature countmode.
Direction Decoding— The direction decoding logic of the eQEP circuit determines which one of thesequences (QEPA, QEPB) is the leading sequence and accordingly updates the direction
information in QEPSTS[QDF] bit. Table 15-2 and Figure 15-6 show the direction decoding logic intruth table and state machine form. Both edges of the QEPA and QEPB signals are sensed togenerate count pulses for the position counter. Therefore, the frequency of the clock generated by
the eQEP logic is four times that of each input sequence. Figure 15-7 shows the direction decoding
and clock generation from the eQEP input signals.
Table 15-2. Quadrature Decoder Truth Table
Previous Edge

Present EdgeQDIR

QPOSCNT

QA↑

QB↑

UP

Increment

QB↓

DOWN

Decrement

QA↓

TOGGLE

Increment or Decrement

QB↓

UP

Increment

QB↑

DOWN

Decrement

QA↑

TOGGLE

Increment or Decrement

QA↑

DOWN

Increment

QA↓

UP

DecrementQB↓

TOGGLE

Increment or Decrement

QA↓

DOWN

Increment

QA↑

UP

DecrementQB↑

TOGGLE

QA↓

QB↑

QB↓

Increment or Decrement

Figure 15-6. Quadrature Decoder State Machine(A,B)=(00)

Increment
counter(11)(10)

Increment
counter
10(01)
Decrement
counter

QEPA

Decrement
counter00
QEPB

Decrement
counter

Decrement
counter
01

eQEP signals
Increment
counter440

11

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

Increment
counter

SPNU517C – March 2018
Submit Documentation Feedback

Quadrature Decoder Unit (QDU)

www.ti.com

Figure 15-7. Quadrature-clock and Direction Decoding
QA

QB

QCLK

QDIR

QPOSCNT+1 +1 +1 +1 +1 +1+1−1 −1 −1 −1 −1 −1 −1 −1 −1 −1−1+1 +1 +1

−1 −1 −1 −1 −1 −1−1+1 +1 +1 +1 +1 +1 +1 +1 +1 +1+1−1 −1 −1

QA

QB

QCLK

QDIR

QPOSCNT

Phase Error Flag— In normal operating conditions, quadrature inputs QEPA and QEPB will be
90 degrees out of phase. The phase error flag (PHE) is set in the QFLG register when edgetransition is detected simultaneously on the QEPA and QEPB signals to optionally generateinterrupts. State transitions marked by dashed lines in Figure 15-6 are invalid transitions thatgenerate a phase error.
Count Multiplication— The eQEP position counter provides 4× the resolution of an input clock bygenerating a quadrature-clock (QCLK) on the rising/falling edges of both eQEP input clocks (QEPA
and QEPB) as shown in Figure 15-7.
Reverse Count— In normal quadrature count operation, QEPA input is fed to the QA input of thequadrature decoder and the QEPB input is fed to the QB input of the quadrature decoder. Reverse
counting is enabled by setting the SWAP bit in the QDECCTL register. This will swap the input tothe quadrature decoder thereby reversing the counting direction.
15.3.1.2 Direction-count Mode
Some position encoders provide direction and clock outputs, instead of quadrature outputs. In such cases,
direction-count mode can be used. QEPA input will provide the clock for position counter and the QEPB
input will have the direction information. The position counter is incremented on every rising edge of a
QEPA input when the direction input is high and decremented when the direction input is low.

SPNU517C – March 2018
Submit Documentation Feedback

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

441

Quadrature Decoder Unit (QDU)

www.ti.com

15.3.1.3 Up-Count Mode
The counter direction signal is hard-wired for up count and the position counter is used to measure thefrequency of the QEPA input. Setting of the QDECCTL[XCR] bit enables clock generation to the position
counter on both edges of the QEPA input, thereby increasing the measurement resolution by 2× factor.
15.3.1.4 Down-Count Mode
The counter direction signal is hardwired for a down count and the position counter is used to measure thefrequency of the QEPA input. Setting of the QDECCTL[XCR] bit enables clock generation to the position
counter on both edges of a QEPA input, thereby increasing the measurement resolution by 2× factor.

15.3.2 eQEP Input Polarity Selection
Each eQEP input can be inverted using QDECCTL[8:5] control bits. As an example, setting of
QDECCTL[QIP] bit will invert the index input.

15.3.3 Position-Compare Sync Output
The enhanced eQEP peripheral includes a position-compare unit that is used to generate the positioncompare sync signal on compare match between the position counter register (QPOSCNT) and theposition-compare register (QPOSCMP). This sync signal can be output using an index pin or strobe pin of
the EQEP peripheral.
Setting the QDECCTL[SOEN] bit enables the position-compare sync output and the QDECCTL[SPSEL] bit
selects either an eQEP index pin or an eQEP strobe pin.

15.4 Position Counter and Control Unit (PCCU)
The position counter and control unit provides two configuration registers (QEPCTL and QPOSCTL) for
setting up position counter operational modes, position counter initialization/latch modes and positioncompare logic for sync signal generation.

15.4.1 Position Counter Operating Modes
Position counter data may be captured in different manners. In some systems, the position counter isaccumulated continuously for multiple revolutions and the position counter value provides the position
information with respect to the known reference. An example of this is the quadrature encoder mounted on
the motor controlling the print head in the printer. Here the position counter is reset by moving the print
head to the home position and then position counter provides absolute position information with respect tohome position.
In other systems, the position counter is reset on every revolution using index pulse and position counter
provides rotor angle with respect to index pulse position.
Position counter can be configured to operate in following four modes• Position Counter Reset on Index Event• Position Counter Reset on Maximum Position• Position Counter Reset on the first Index Event• Position Counter Reset on Unit Time Out Event (Frequency Measurement)
In all the above operating modes, position counter is reset to 0 on overflow and to QPOSMAX registervalue on underflow. Overflow occurs when the position counter counts up after QPOSMAX value.
Underflow occurs when position counter counts down after 0. Interrupt flag is set to indicate
overflow/underflow in QFLG register.

442

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackPosition Counter and Control Unit (PCCU)

www.ti.com

15.4.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
If the index event occurs during the forward movement, then position counter is reset to 0 on the next
eQEP clock. If the index event occurs during the reverse movement, then the position counter is reset tothe value in the QPOSMAX register on the next eQEP clock.
First index marker is defined as the quadrature edge following the first index edge. The eQEP peripheral
records the occurrence of the first index marker (QEPSTS[FIMF]) and direction on the first index event
marker (QEPSTS[FIDF]) in QEPSTS registers, it also remembers the quadrature edge on the first index
marker so that same relative quadrature transition is used for index event reset operation.
For example, if the first reset operation occurs on the falling edge of QEPB during the forward direction,then all the subsequent reset must be aligned with the falling edge of QEPB for the forward rotation andon the rising edge of QEPB for the reverse rotation as shown in Figure 15-8.
The position-counter value is latched to the QPOSILAT register and direction information is recorded in
the QEPSTS[QDLF] bit on every index event marker. The position-counter error flag (QEPSTS[PCEF])
and error interrupt flag (QFLG[PCE]) are set if the latched value is not equal to 0 or QPOSMAX. The
position-counter error flag (QEPSTS[PCEF]) is updated on every index event marker and an interrupt flag
(QFLG[PCE]) will be set on error that can be cleared only through software.
The index event latch configuration QEPCTL[IEL] bits are ignored in this mode and position counter error
flag/interrupt flag are generated only in index event reset mode.
Figure 15-8. Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or F9Fh)
QA

QB

QI

QCLK

QEPSTS:QDF
F9F

F9D
QPOSCNT F9C
Index interrupt/
index event
markerQPOSILAT

F9F
0

1

2

3

4

5

4

3

2

1

F9D

F9B

F99

F97

0
F9E

F9E

F9F

F9C

F9A

F98

0

QEPSTS:QDLF

SPNU517C – March 2018
Submit Documentation Feedback

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

443

Position Counter and Control Unit (PCCU)

www.ti.com

15.4.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
If the position counter is equal to QPOSMAX, then the position counter is reset to 0 on the next eQEP
clock for forward movement and position counter overflow flag is set. If the position counter is equal toZERO, then the position counter is reset to QPOSMAX on the next QEP clock for reverse movement andposition counter underflow flag is set. Figure 15-9 shows the position counter reset operation in this mode.
First index marker is defined as the quadrature edge following the first index edge. The eQEP peripheral
records the occurrence of the first index marker (QEPSTS[FIMF]) and direction on the first index event
marker (QEPSTS[FIDF]) in the QEPSTS registers; it also remembers the quadrature edge on the firstindex marker so that the same relative quadrature transition is used for the software index marker(QEPCTL[IEL]=11).
Figure 15-9. Position Counter Underflow/Overflow (QPOSMAX = 4)
QA

QB

QCLK

QDIR

QPOSCNT

1

2

3

4

0

1

2

1

0

4

3

2

1

0

4

3

2

1

2

3

4

1

0

4

3

2

1

0

1

2

3

4

0

1

2

3

4

0

1

0

4

3

0

OV/UF

QA

QB

QCLK

QDIR

QPOSCNT

OV/UF

444

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackPosition Counter and Control Unit (PCCU)

www.ti.com

15.4.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
If the index event occurs during forward movement, then the position counter is reset to 0 on the next
eQEP clock. If the index event occurs during the reverse movement, then the position counter is reset tothe value in the QPOSMAX register on the next eQEP clock. Note that this is done only on the firstoccurrence and subsequently the position counter value is not reset on an index event; rather, it is reset
based on maximum position as described in Section 15.4.1.2.
First index marker is defined as the quadrature edge following the first index edge. The eQEP peripheral
records the occurrence of the first index marker (QEPSTS[FIMF]) and direction on the first index event
marker (QEPSTS[FIDF]) in QEPSTS registers, it also remembers the quadrature edge on the first index
marker so that same relative quadrature transition is used for software index marker (QEPCTL[IEL]=11).
15.4.1.4 Position Counter Reset on Unit Time out Event (QEPCTL[PCRM] = 11)
In this mode, the QPOSCNT value is latched to the QPOSLAT register and then the QPOSCNT is reset(to 0 or QPOSMAX, depending on the direction mode selected by QDECCTL[QSRC] bits on a unit time
event). This is useful for frequency measurement.

15.4.2 Position Counter Latch
The eQEP index and strobe input can be configured to latch the position counter (QPOSCNT) into
QPOSILAT and QPOSSLAT, respectively, on occurrence of a definite event on these pins.
15.4.2.1 Index Event Latch
In some applications, it may not be desirable to reset the position counter on every index event andinstead it may be required to operate the position counter in full 32-bit mode (QEPCTL[PCRM] = 01 andQEPCTL[PCRM] = 10 modes).
In such cases, the eQEP position counter can be configured to latch on the following events and direction
information is recorded in the QEPSTS[QDLF] bit on every index event marker.
• Latch on Rising edge (QEPCTL[IEL] = 01)• Latch on Falling edge (QEPCTL[IEL] = 10)• Latch on Index Event Marker (QEPCTL[IEL] = 11)This is particularly useful as an error checking mechanism to check if the position counter accumulated
the correct number of counts between index events. As an example, the 1000-line encoder must count4000 times when moving in the same direction between the index events.
The index event latch interrupt flag (QFLG[IEL]) is set when the position counter is latched to the
QPOSILAT register. The index event latch configuration bits (QEPCTZ[IEL]) are ignored when
QEPCTL[PCRM] = 00.
Latch on Rising Edge (QEPCTL[IEL] = 01)— The position counter value (QPOSCNT) is latched to the
QPOSILAT register on every rising edge of an index input.
Latch on Falling Edge (QEPCTL[IEL] = 10)— The position counter value (QPOSCNT) is latched to the
QPOSILAT register on every falling edge of index input.
Latch on Index Event Marker/Software Index Marker (QEPCTL[IEL] = 11— The first index marker isdefined as the quadrature edge following the first index edge. The eQEP peripheral records theoccurrence of the first index marker (QEPSTS[FIMF]) and direction on the first index event marker(QEPSTS[FIDF]) in the QEPSTS registers. It also remembers the quadrature edge on the firstindex marker so that same relative quadrature transition is used for latching the position counter(QEPCTL[IEL]=11).
Figure 15-10 shows the position counter latch using an index event marker.

SPNU517C – March 2018
Submit Documentation Feedback

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

445

Position Counter and Control Unit (PCCU)

www.ti.com

Figure 15-10. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1)
QA

QB

QI

QCLK

QEPSTS:QDF
F9D

F9F

FA1

FA3

FA4

QPOSCNT F9C

FA2

FA0

F9E

F9C

F9A

F98

FA5
F9E

FA0

FA2

F97

FA4

FA3

FA1

F9F

F9D

F9B

F99

Index interrupt/
index event
markerQPOSILATF9F

0QEPSTS:QDLF

15.4.2.2 Strobe Event Latch
The position-counter value is latched to the QPOSSLAT register on the rising edge of the strobe input by
clearing the QEPCTL[SEL] bit.
If the QEPCTL[SEL] bit is set, then the position counter value is latched to the QPOSSLAT register on therising edge of the strobe input for forward direction and on the falling edge of the strobe input for reverse
direction as shown in Figure 15-11.
The strobe event latch interrupt flag (QFLG[SEL) is set when the position counter is latched to the
QPOSSLAT register.
Figure 15-11. Strobe Event Latch (QEPCTL[SEL] = 1)
QA

QB

QS

QCLK

QEPST:QDF
F9D

F9F

FA1

FA3

FA4

QPOSCNT F9C
F9E

FA0

FA2

FA4

QIPOSSLAT

446

FA2

FA0

F9E

F9C

F9A

F98

FA5

F97
FA3

FA1

F9F

F9F

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

F9D

F9B

F99

F9F

SPNU517C – March 2018
Submit Documentation FeedbackPosition Counter and Control Unit (PCCU)

www.ti.com

15.4.3 Position Counter Initialization
The position counter can be initialized using following events:• Index event• Strobe event• Software initialization
Index Event Initialization (IEI)— The QEPI index input can be used to trigger the initialization of theposition counter at the rising or falling edge of the index input. If the QEPCTL[IEI] bits are 10, thenthe position counter (QPOSCNT) is initialized with a value in the QPOSINIT register on the risingedge of index input. Conversely, if the QEPCTL[IEI] bits are 11, initialization will be on the fallingedge of the index input.
Strobe Event Initialization (SEI)— If the QEPCTL[SEI] bits are 10, then the position counter is initializedwith a value in the QPOSINIT register on the rising edge of strobe input.
If QEPCTL[SEL] bits are 11, then the position counter is initialized with a value in the QPOSINIT
register on the rising edge of strobe input for forward direction and on the falling edge of strobe
input for reverse direction.
Software Initialization (SWI)— The position counter can be initialized in software by writing a 1 to the
QEPCTL[SWI] bit. This bit is not automatically cleared. While the bit is still set, if a 1 is written to it
again, the position counter will be re-initialized.

15.4.4 eQEP Position-compare Unit
The eQEP peripheral includes a position-compare unit that is used to generate a sync output and/orinterrupt on a position-compare match. Figure 15-12 shows a diagram. The position-compare(QPOSCMP) register is shadowed and shadow mode can be enabled or disabled using the
QPOSCTL[PSSHDW] bit. If the shadow mode is not enabled, the CPU writes directly to the active position
compare register.
Figure 15-12. eQEP Position-compare UnitQPOSCTL:PCSHDWQPOSCTL:PCLOADQPOSCMP

QFLG:PCR
QFLG:PCMQPOSCTL:PCSPWQPOSCTL:PCPOL832
PCEVENT

Pulse
stretcher

0

32

PCSOUT1QPOSCNTIn shadow mode, you can configure the position-compare unit (QPOSCTL[PCLOAD]) to load the shadow
register value into the active register on the following events and to generate the position-compare ready(QFLG[PCR]) interrupt after loading.
• Load on compare match• Load on position-counter zero event
The position-compare match (QFLG[PCM]) is set when the position-counter value (QPOSCNT) matcheswith the active position-compare register (QPOSCMP) and the position-compare sync output of the
programmable pulse width is generated on compare match to trigger an external device.
SPNU517C – March 2018
Submit Documentation Feedback

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

447

Position Counter and Control Unit (PCCU)

www.ti.com

For example, if QPOSCMP = 2, the position-compare unit generates a position-compare event on 1 to 2
transitions of the eQEP position counter for forward counting direction and on 3 to 2 transitions of theeQEP position counter for reverse counting direction (see Figure 15-13).
Section 15.9.15 shows the layout of the eQEP Position-Compare Control Register (QPOSCTL) anddescribes the QPOSCTL bit fields.
Figure 15-13. eQEP Position-compare Event Generation Points
432

eQEP counter

4
3

3
2

1

1

0

3

2

2

1

POSCMP=2

1

00

PCEVNTPCSOUT (active HIGH)PCSPWPCSOUT (active LOW)

The pulse stretcher logic in the position-compare unit generates a programmable position-compare sync
pulse output on the position-compare match. In the event of a new position-compare match while aprevious position-compare pulse is still active, then the pulse stretcher generates a pulse of specified
duration from the new position-compare event as shown in Figure 15-14.
Figure 15-14. eQEP Position-compare Sync Output Pulse StretcherDIR

QPOSCMPQPOSCNTPCEVNT

PCSPW

PCSPW
PCSPW

PCSOUT (active HIGH)

448

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

eQEP Edge Capture Unit

www.ti.com

15.5 eQEP Edge Capture Unit
The eQEP peripheral includes an integrated edge capture unit to measure the elapsed time between theunit position events as shown in Figure 15-15. This feature is typically used for low-speed measurement
using the following equation:Xv(k) ++ X
t(k) * t(k * 1)DT(28)
where,• X - Unit position is defined by integer multiple of quadrature edges (see Figure 15-16)• ΔT - Elapsed time between unit position events• v(k) - Velocity at time instant "k"The eQEP capture timer (QCTMR) runs from prescaled VCLK and the prescaler is programmed by the
QCAPCTL[CCPS] bits. The capture timer (QCTMR) value is latched into the capture period register(QCPRD) on every unit position event and then the capture timer is reset, a flag is set in
QEPSTS:UPEVNT to indicate that new value is latched into the QCPRD register. Software can check thisstatus flag before reading the period register for low speed measurement and clear the flag by writing 1.
Time measurement (ΔT) between unit position events will be correct if the following conditions are met:
• No more than 65,535 counts have occurred between unit position events.
• No direction change between unit position events.
The capture unit sets the eQEP overflow error flag (QEPSTS[COEF]) in the event of capture timer
overflow between unit position events. If a direction change occurs between the unit position events, thenan error flag is set in the status register (QEPSTS[CDEF]).
Capture Timer (QCTMR) and Capture period register (QCPRD) can be configured to latch on following
events.
• CPU read of QPOSCNT register• Unit time-out event
If the QEPCTL[QCLM] bit is cleared, then the capture timer and capture period values are latched into the
QCTMRLAT and QCPRDLAT registers, respectively, when the CPU reads the position counter(QPOSCNT).
If the QEPCTL[QCLM] bit is set, then the position counter, capture timer, and capture period values arelatched into the QPOSLAT, QCTMRLAT and QCPRDLAT registers, respectively, on unit time out.
Figure 15-17 shows the capture unit operation along with the position counter.

SPNU517C – March 2018
Submit Documentation Feedback

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

449

eQEP Edge Capture Unit

www.ti.com

Figure 15-15. eQEP Edge Capture Unit
16
0xFFFFQEPSTS:COEF
16
QCTMR
QCPRD
16

QCAPCTL:CCPS
3
3-bit binary
divider
x1, 1/2, 1/4...,
1/128

VCLK

CAPCLKQCTMRLATQCAPCTL:UPPSQCPRDLAT

4

16

Capture timer
control unit
(CTCU)QCAPCTL:CEN

QEPSTS:UPEVNTUPEVNTQEPSTS:CDEF

4-bit binary
divider
x1, 1/2, 1/4...,
1/2048Rising/fallingedge detect

QCLK

QDIR

UTIME
QEPCTL:UTE

QFLG:UTO

VCLK

QUTMR

UTOUT

QUPRD

NOTE:

The QCAPCTL[UPPS] prescaler should not be modified dynamically (such as switching theunit event prescaler from QCLK/4 to QCLK/8). Doing so may result in undefined behavior.
The QCAPCTL[CPPS] prescaler can be modified dynamically (such as switching CAPCLK
prescaling mode from SYSCLK/4 to SYSCLK/8) only after the capture unit is disabled.

Figure 15-16. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)
P

QA

QB

QCLK

UPEVNT
X=N x PN - Number of quadrature periods selected using QCAPCTL[UPPS] bits

450

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

eQEP Edge Capture Unit

www.ti.com

Figure 15-17. eQEP Edge Capture Unit - Timing Details
QEPA

QEPB

QCLK

QPOSCNTx(k)∆Xx(k−1)UPEVNT
t(k)

∆T
QCTMR
t(k−1)T
UTOUT

Velocity Calculation Equations:x(k) * x(k * 1)
v(k) ++ DX or
T
T

(29)

where
v(k): Velocity at time instant kx(k): Position at time instant kx(k-1): Position at time instant k-1
T: Fixed unit time or inverse of velocity calculation rate
ΔX: Incremental position movement in unit time
X: Fixed unit position
ΔT: Incremental time elapsed for unit position movementt(k): Time instant "k"t(k-1): Time instant "k-1"
Unit time (T) and unit period(X) are configured using the QUPRD and QCAPCTL[UPPS] registers.
Incremental position output and incremental time output is available in the QPOSLAT and QCPRDLAT
registers.

SPNU517C – March 2018
Submit Documentation Feedback

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

451

eQEP Watchdog

www.ti.com

Parameter

Relevant Register to Configure or Read the Information

T

Unit Period Register (QUPRD)

ΔX

Incremental Position = QPOSLAT(k) - QPOSLAT(K-1)

X

Fixed unit position defined by sensor resolution and ZCAPCTL[UPPS] bits

ΔT

Capture Period Latch (QCPRDLAT)

15.6 eQEP Watchdog
The eQEP peripheral contains a 16-bit watchdog timer that monitors the quadrature-clock to indicate
proper operation of the motion-control system. The eQEP watchdog timer is clocked from VCLK/64 andthe quadrate clock event (pulse) resets the watchdog timer. If no quadrature-clock event is detected until aperiod match (QWDPRD = QWDTMR), then the watchdog timer will time out and the watchdog interrupt
flag will be set (QFLG[WTO]). The time-out value is programmable through the watchdog period register(QWDPRD).
Figure 15-18. eQEP Watchdog Timer
QWDOG
QEPCTL:WDE
VCLK

/64

VCLK

QWDTMR
16

QCLK

RESET
WDTOUT
16
QWDPRD

QFLG:WTO

15.7 Unit Timer Base
The eQEP peripheral includes a 32-bit timer (QUTMR) that is clocked by VCLK to generate periodic
interrupts for velocity calculations. The unit time out interrupt is set (QFLG[UTO]) when the unit timer(QUTMR) matches the unit period register (QUPRD).
The eQEP peripheral can be configured to latch the position counter, capture timer, and capture period
values on a unit time out event so that latched values are used for velocity calculation as described in
Section 15.5.
Figure 15-19. eQEP Unit Time BaseUTIMEQEPCTL:UTE
VCLK

QUTMR
32
UTOUT
32
QUPRD

452

QFLG:UTO

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

eQEP Interrupt Structure

www.ti.com

15.8 eQEP Interrupt Structure
Figure 15-20 shows how the interrupt mechanism works in the EQEP module.
Eleven interrupt events (PCE, PHE, QDC, WTO, PCU, PCO, PCR, PCM, SEL, IEL and UTO) can begenerated. The interrupt control register (QEINT) is used to enable/disable individual interrupt event
sources. The interrupt flag register (QFLG) indicates if any interrupt event has been latched and contains
the global interrupt flag bit (INT). An interrupt pulse is generated only to the PIE if any of the interrupt
events is enabled, the flag bit is 1 and the INT flag bit is 0. The interrupt service routine will need to clear
the global interrupt flag bit and the serviced event, via the interrupt clear register (QCLR), before any otherinterrupt pulses are generated. You can force an interrupt event by way of the interrupt force register(QFRC), which is useful for test purposes.
Figure 15-20. EQEP Interrupt Generation
Set

Clr
Latch

QEINT:PCE

QCLR:INTClr
QFLG:INTQCLR:PCE

Latch
Set
EQEPxINT

Pulse
generator
when
input=1

0

0

QFRC:PCE
PCE

QFLG:PCE
1
QEINT:UTO
clr

QCLR:UTO

Latch
set

QFRC:UTOUTO

QFLG:UTOSPNU517C – March 2018
Submit Documentation Feedback

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

453

eQEP Registers

www.ti.com

15.9 eQEP Registers
Table 15-3 lists the eQEP registers. The base address for the control registers is FCF7 9900h.
Table 15-3. eQEP Registers
OffsetAcronym

Register Description

00h

QPOSCNTeQEP Position Counter Register

Section 15.9.1

Section04h

QPOSINITeQEP Initialization Position Count Register

Section 15.9.2

08h

QPOSMAXeQEP Maximum Position Count Register

Section 15.9.3

0Ch

QPOSCMPeQEP Position-compare Register

Section 15.9.4

10h

QPOSILAT

eQEP Index Position Latch Register

Section 15.9.5

14h

QPOSSLAT

eQEP Strobe Position Latch Register

Section 15.9.6

18h

QPOSLATeQEP Position Latch Register

Section 15.9.7

1Ch

QUTMR

eQEP Unit Timer Register

Section 15.9.8

20h

QUPRD

eQEP Unit Period Register

Section 15.9.926h

QWDTMR

eQEP Watchdog Timer Register

Section 15.9.10

24h

QWDPRD

eQEP Watchdog Period Register

Section 15.9.11

2Ah

QDECCTL

eQEP Decoder Control Register

Section 15.9.12

28h

QEPCTLeQEP Control Register

Section 15.9.13

2Eh

QCAPCTL

eQEP Capture Control Register

Section 15.9.14

2Ch

QPOSCTL

eQEP Position-Compare Control Register

Section 15.9.15

32h

QEINT

eQEP Interrupt Enable Register

Section 15.9.16

30h

QFLG

eQEP Interrupt Flag Register

Section 15.9.17

36h

QCLR

eQEP Interrupt Clear Register

Section 15.9.18

34h

QFRC

eQEP Interrupt Force Register

Section 15.9.19

3Ah

QEPSTSeQEP Status Register

Section 15.9.20

38h

QCTMR

eQEP Capture Timer Register

Section 15.9.21

3Eh

QCPRD

eQEP Capture Period Register

Section 15.9.22

3Ch

QCTMRLAT

eQEP Capture Timer Latch Register

Section 15.9.23

42h

QCPRDLAT

eQEP Capture Period Latch Register

Section 15.9.24

15.9.1 eQEP Position Counter Register (QPOSCNT)
Figure 15-21. eQEP Position Counter (QPOSCNT) Register (offset = 00h)
31

0
QPOSCNT
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 15-4. eQEP Position Counter (QPOSCNT) Register Field Descriptions
Bit

Field

Description

31-0

QPOSCNTThis 32-bit position counter register counts up/down on every eQEP pulse based on direction input. This counter
acts as a position integrator whose count value is proportional to position from a give reference point.

454

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

eQEP Registers

www.ti.com

15.9.2 eQEP Position Counter Initialization Register (QPOSINIT)
Figure 15-22. eQEP Position Counter Initialization (QPOSINIT) Register (offset = 04h)
31

0
QPOSINIT
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 15-5. eQEP Position Counter Initialization (QPOSINIT) Register Field Descriptions
Bit

Field

Description

31-0

QPOSINIT

This register contains the position value that is used to initialize the position counter based on external strobe orindex event. The position counter can be initialized through software.

15.9.3 eQEP Maximum Position Count Register (QPOSMAX)
Figure 15-23. eQEP Maximum Position Count Register (QPOSMAX) Register (offset = 08h)
31

0
QPOSMAX
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 15-6. eQEP Maximum Position Count (QPOSMAX) Register Field Descriptions
Bit

Field

Description

31-0

QPOSMAXThis register contains the maximum position counter value.

15.9.4 eQEP Position-Compare Register (QPOSCMP)
Figure 15-24. eQEP Position-Compare (QPOSCMP) Register (offset = 0Ch)
31

0QPOSCMP
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 15-7. eQEP Position-Compare (QPOSCMP) Register Field Descriptions
Bit

Field

Description

31-0

QPOSCMPThe position-compare value in this register is compared with the position counter (QPOSCNT) to generate sync
output and/or interrupt on compare match.

SPNU517C – March 2018
Submit Documentation Feedback

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

455

eQEP Registers

www.ti.com

15.9.5 eQEP Index Position Latch Register (QPOSILAT)
Figure 15-25. eQEP Index Position Latch (QPOSILAT) Register (offset = 10h)310QPOSILAT
R-0

LEGEND: R = Read only; -n = value after reset

Table 15-8. eQEP Index Position Latch (QPOSILAT) Register Field Descriptions
Bit

Field

Description

31-0

QPOSILAT

The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits.

15.9.6 eQEP Strobe Position Latch Register (QPOSSLAT)
Figure 15-26. eQEP Strobe Position Latch (QPOSSLAT) Register (offset = 14h)310
QPOSSLAT
R-0

LEGEND: R = Read only; -n = value after reset

Table 15-9. eQEP Strobe Position Latch (QPOSSLAT) Register Field Descriptions
Bit

Field

Description

31-0

QPOSSLAT

The position-counter value is latched into this register on strobe event as defined by the QEPCTL[SEL] bits.

15.9.7 eQEP Position Counter Latch Register (QPOSLAT)
Figure 15-27. eQEP Position Counter Latch (QPOSLAT) Register (offset = 18h)31

0
QPOSLAT
R-0

LEGEND: R = Read only; -n = value after reset

Table 15-10. eQEP Position Counter Latch (QPOSLAT) Register Field Descriptions
Bit

Field

Description

31-0

QPOSLATThe position-counter value is latched into this register on unit time out event.

456

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

eQEP Registers

www.ti.com

15.9.8 eQEP Unit Timer Register (QUTMR)
Figure 15-28. eQEP Unit Timer (QUTMR) Register (offset = 1Ch)
31

0
QUTMR
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 15-11. eQEP Unit Timer (QUTMR) Register Field Descriptions
Bit

Field

Description

31-0

QUTMR

This register acts as time base for unit time event generation. When this timer value matches with unit time period
value, unit time event is generated.

15.9.9 eQEP Register Unit Period Register (QUPRD)
Figure 15-29. eQEP Register Unit Period (QUPRD) Register (offset = 20h)
31

0
QUPRD
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 15-12. eQEP Unit Period (QUPRD) Register Field Descriptions
Bit

Field

Description

31-0

QUPRD

This register contains the period count for unit timer to generate periodic unit time events to latch the eQEP
position information at periodic interval and optionally to generate interrupt.

15.9.10 eQEP Watchdog Timer Register (QWDTMR)
Figure 15-30. eQEP Watchdog Timer (QWDTMR) Register (offset = 26h)
150
QWDTMR
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 15-13. eQEP Watchdog Timer (QWDTMR) Register Field Descriptions
Bit

Field

Description

15-0

QWDTMR

This register acts as time base for watch dog to detect motor stalls. When this timer value matches with watch dog
period value, watch dog timeout interrupt is generated. This register is reset upon edge transition in quadratureclock indicating the motion.

SPNU517C – March 2018
Submit Documentation Feedback

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

457

eQEP Registers

www.ti.com

15.9.11 eQEP Watchdog Period Register (QWDPRD)
Figure 15-31. eQEP Watchdog Period (QWDPRD) Register (offset = 24h)
150
QWDPRD
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 15-14. eQEP Watchdog Period (QWDPRD) Register Field Description
Bit

Field

Description

15-0

QWDPRD

This register contains the time-out count for the eQEP peripheral watch dog timer. When the watchdog timer
value matches the watchdog period value, a watchdog timeout interrupt is generated.

458

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

eQEP Registers

www.ti.com

15.9.12 eQEP Decoder Control Register (QDECCTL)
Figure 15-32. eQEP Decoder Control (QDECCTL) Register (offset = 2Ah)
15

14

13

12

11

10

9

8

QSRC

SOEN

SPSEL

XCR

SWAP

IGATE

QAP

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

5

4

7

6

0

QBP

QIP

QSP

Reserved

R/W-0

R/W-0

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15-15. eQEP Decoder Control (QDECCTL) Register Field Descriptions
Bit

Field

15-14

QSRC

13

12

11

10

9

8

7

6

5

4-0

Value

Position-counter source selection.
0

Quadrature count mode (QCLK = iCLK, QDIR = iDIR)

1h

Direction-count mode (QCLK = xCLK, QDIR = xDIR)

2h

UP count mode for frequency measurement (QCLK = xCLK, QDIR = 1)

3h

DOWN count mode for frequency measurement (QCLK = xCLK, QDIR = 0)

SOEN

Sync output-enable.
0

Disable position-compare sync output.

1

Enable position-compare sync output.

SPSEL

Sync output pin selection.
0

Index pin is used for sync output.

1

Strobe pin is used for sync output.

XCR

External clock rate.
0

2x resolution: Count the rising/falling edge.

1

1x resolution: Count the rising edge only.

SWAP

Swap quadrature clock inputs. This swaps the input to the quadrature decoder, reversing thecounting direction.
0

Quadrature-clock inputs are not swapped.

1

Quadrature-clock inputs are swapped.

IGATE

Index pulse gating option.
0

Disable gating of Index pulse.

1

Gate the index pin with strobe.

QAPQEPA input polarity.
0

No effect.

1

Negates QEPA input.

QBP

QEPB input polarity.
0

No effect.

1

Negates QEPB input.

QIP

QEPI input polarity.
0

No effect.

1

Negates QEPI input.

QSP

Reserved

SPNU517C – March 2018
Submit Documentation Feedback

Description

QEPS input polarity.
0

No effect.

1

Negates QEPS input.

0

Always write as 0.

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

459

eQEP Registers

www.ti.com

15.9.13 eQEP Control Register (QEPCTL)
Figure 15-33. eQEP Control (QEPCTL) Register (offset = 28h)
15

14

13

12

11

10

9

8

FREE, SOFT

PCRM

SEI

IEI

R/W-0

R/W-0

R/W-0

R/W-0

7

6

5

4

3

2

1

0

SWI

SEL

IEL

QPEN

QCLM

UTE

WDE

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 15-16. eQEP Control (QEPCTL) Register Field Descriptions
Bit

Field

15-14

FREE, SOFT

Value

Description
Emulation Control Bits.
QPOSCNT behavior:0

Position counter stops immediately on emulation suspend.

1h

Position counter continues to count until the rollover.

2h-3hPosition counter is unaffected by emulation suspend.
QWDTMR behavior:

0

Watchdog counter stops immediately.

1h

Watchdog counter counts until WD period match roll over.

2h-3hWatchdog counter is unaffected by emulation suspend.
QUTMR behavior:

0

Unit timer stops immediately.

1h

Unit timer counts until period rollover.

2h-3hUnit timer is unaffected by emulation suspend.
QCTMR behavior:

13-12

11-10

0

Capture Timer stops immediately.

1hCapture Timer counts until next unit period event.

2h-3hCapture Timer is unaffected by emulation suspend.

PCRM

Position counter reset mode.
0

Position counter reset on an index event.

1h

Position counter reset on the maximum position.

2h

Position counter reset on the first index event.

3h

Position counter reset on a unit time event.

SEI

Strobe event initialization of position counter.
0

Does nothing (action is disabled).

1h

Does nothing (action is disabled).

2h

Initializes the position counter on rising edge of the QEPS signal.

3h

Clockwise Direction: Initializes the position counter on the rising edge of QEPS strobe.
Counter Clockwise Direction: Initializes the position counter on the falling edge of QEPS strobe.

9-8

7

460

IEI

Index event initialization of position counter.
0

Do nothing (action is disabled).

1h

Do nothing (action is disabled).

2h

Initializes the position counter on the rising edge of the QEPI signal (QPOSCNT = QPOSINIT).

3h

Initializes the position counter on the falling edge of QEPI signal (QPOSCNT = QPOSINIT).

SWI

Software initialization of position counter.
0

Do nothing (action is disabled).

1

Initialize position counter (QPOSCNT = QPOSINIT). This bit is not cleared automatically.

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

eQEP Registers

www.ti.com

Table 15-16. eQEP Control (QEPCTL) Register Field Descriptions (continued)
Bit

Field

6

SEL

Value

Description
Strobe event latch of position counter.

0

The position counter is latched on the rising edge of QEPS strobe (QPOSSLAT = POSCCNT).
Latching on the falling edge can be done by inverting the strobe input using the QSP bit in the
QDECCTL register.

1

Clockwise Direction: Position counter is latched on rising edge of QEPS strobe.
Counter Clockwise Direction: Position counter is latched on falling edge of QEPS strobe.

5-4

3

2

1

0

IEL

Index event latch of position counter (software index marker).
0

Reserved

1hLatches position counter on rising edge of the index signal.

2hLatches position counter on falling edge of the index signal.

3h

Software index marker. Latches the position counter and quadrature direction flag on index event
marker. The position counter is latched to the QPOSILAT register and the direction flag is latched in
the QEPSTS[QDLF] bit. This mode is useful for software index marking.

QPEN

Quadrature position counter enable/software reset.
0

Reset the eQEP peripheral internal operating flags/read-only registers. Control/configuration
registers are not disturbed by a software reset.

1

eQEP position counter is enabled.

QCLM

eQEP capture latch mode.
0

Latch on position counter read by CPU. Capture timer and capture period values are latched into
QCTMRLAT and QCPRDLAT registers when CPU reads the QPOSCNT register.

1

Latch on unit time out. Position counter, capture timer and capture period values are latched into
QPOSLAT, QCTMRLAT and QCPRDLAT registers on unit time out.

UTE

eQEP unit timer enable.
0

Disable eQEP unit timer.

1

Enable eQEP unit timer.

WDE

SPNU517C – March 2018
Submit Documentation Feedback

eQEP watchdog enable.
0

Disable eQEP watchdog timer.

1

Enable eQEP watchdog timer.

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

461

eQEP Registers

www.ti.com

15.9.14 eQEP Capture Control Register (QCAPCTL)
Figure 15-34. eQEP Capture Control (QCAPCTL) Register (offset = 2Eh)
15

14

8

CEN

Reserved

R/W-0

R-0

7

6

4

3

0

Reserved

CCPS

UPPS

R-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15-17. eQEP Capture Control (QCAPCTL) Register Field Descriptions
Bit

Field

15

CEN

14-7

Reserved

6-4

CCPS

3-0

Value

Enable eQEP capture.
0

eQEP capture unit is disabled.

1

eQEP capture unit is enabled.

0

Always write as 0.
eQEP capture timer clock prescaler.

0

CAPCLK = VCLK/1

1h

CAPCLK = VCLK/22h

CAPCLK = VCLK/43h

CAPCLK = VCLK/84h

CAPCLK = VCLK/16

5h

CAPCLK = VCLK/32

6h

CAPCLK = VCLK/64

7h

CAPCLK = VCLK/128

UPPS

Unit position event prescaler.
0

UPEVNT = QCLK/1

1h

UPEVNT = QCLK/22h

UPEVNT = QCLK/43h

UPEVNT = QCLK/84h

UPEVNT = QCLK/165h

UPEVNT = QCLK/32

6h

UPEVNT = QCLK/64

7h

UPEVNT = QCLK/128

8h

UPEVNT = QCLK/256

9h

UPEVNT = QCLK/512

Ah

UPEVNT = QCLK/1024

Bh

UPEVNT = QCLK/2048

Ch-Fh

462

Description

Reserved

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

eQEP Registers

www.ti.com

15.9.15 eQEP Position-Compare Control Register (QPOSCTL)
Figure 15-35. eQEP Position-compare Control (QPOSCTL) Register (offset = 2Ch)
15

14

13

12

PCSHDW

PCLOAD

PCPOL

PCE

11
PCSPW

8

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

7

0
PCSPW
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 15-18. eQEP Position-compare Control (QPOSCTL) Register Field Descriptions
Bit

Field

15

PCSHDW

14

13

12

11-0

Value

Description
Position-compare shadow enable.

0

Shadow disabled, load Immediate.

1

Shadow enabled.

PCLOAD

Position-compare shadow load mode.
0

Load on QPOSCNT = 0.

1

Load when QPOSCNT = QPOSCMP.

PCPOLPolarity of sync output.
0

Active HIGH pulse output.

1

Active LOW pulse output.

PCE

Position-compare enable.
0

Disable position compare unit.

1

Enable position compare unit.

PCSPW

Select-position-compare sync output pulse width.
0

1 × 4 × VCLK cycles

1h

2 × 4 × VCLK cycles

:

:

FFFh

SPNU517C – March 2018
Submit Documentation Feedback

4096 × 4 × VCLK cycles

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

463

eQEP Registers

www.ti.com

15.9.16 eQEP Interrupt Enable Register (QEINT)
Figure 15-36. eQEP Interrupt Enable (QEINT) Register (offset = 32h)
15

12

7

11

10

9

8

Reserved

UTO

IEL

SEL

PCM

R-0

R/W-0

R/W-0

R/W-0

R/W-0

3

2

1

0

6

5

4

PCR

PCO

PCU

WTO

QDC

QPE

PCE

Reserved

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15-19. eQEP Interrupt Enable (QEINT) Register Field Descriptions
Bit

Field

15-12

Reserved

11

10

9

8

7

6

5

4

3

2

1

0

464

Value
0

UTO

Always write as 0.
Unit time out interrupt enable.

0Interrupt is disabled.

1

Interrupt is enabled.

IEL

Index event latch interrupt enable.
0Interrupt is disabled.

1

Interrupt is enabled.

SEL

Strobe event latch interrupt enable.
0Interrupt is disabled.

1

Interrupt is enabled.

PCM

Position-compare match interrupt enable.
0Interrupt is disabled.

1

Interrupt is enabled.

PCR

Position-compare ready interrupt enable.
0Interrupt is disabled.

1

Interrupt is enabled.

PCO

Position counter overflow interrupt enable.
0Interrupt is disabled.

1

Interrupt is enabled.

PCU

Position counter underflow interrupt enable.
0Interrupt is disabled.

1

Interrupt is enabled.

WTO

Watchdog time out interrupt enable.
0Interrupt is disabled.

1

Interrupt is enabled.

QDC

Quadrature direction change interrupt enable.
0Interrupt is disabled.

1

Interrupt is enabled.

QPE

Quadrature phase error interrupt enable.
0Interrupt is disabled.

1

Interrupt is enabled.

PCE

Reserved

Description

Position counter error interrupt enable.
0Interrupt is disabled.

1

Interrupt is enabled.

0

Reserved

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

eQEP Registers

www.ti.com

15.9.17 eQEP Interrupt Flag Register (QFLG)
Figure 15-37. eQEP Interrupt Flag (QFLG) Register (offset = 30h)
15

11

10

9

8

Reserved

12

UTO

IEL

SEL

PCM

R-0

R-0

R-0

R-0

R-0

7

6

5

4

3

2

1

0

PCR

PCO

PCU

WTO

QDC

PHE

PCE

INT

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 15-20. eQEP Interrupt Flag (QFLG) Register Field Descriptions
Bit

Field

15-12

Reserved

11

10

9

8

7

6

5

4

3

2

1

0

Value
0

UTO

Always write as 0.
Unit time out interrupt flag.

0

No interrupt is generated.

1

Set by eQEP unit timer period match.

IEL

Index event latch interrupt flag.
0

No interrupt is generated.

1

Set after latching the QPOSCNT to QPOSILAT.

SEL

Strobe event latch interrupt flag.
0

No interrupt is generated.

1

Set after latching the QPOSCNT to QPOSSLAT.

PCM

Position-compare match interrupt flag.
0

No interrupt is generated.

1

Set on position-compare match.

PCR

Position-compare ready interrupt flag.
0

No interrupt is generated.

1

Set after transferring the shadow register value to the active position compare register.

PCO

Position counter overflow interrupt flag.
0

No interrupt is generated.

1

Set on position counter overflow.

PCU

Position counter underflow interrupt flag.
0

No interrupt is generated.

1

Set on position counter underflow.

WTO

Watchdog time out interrupt flag.
0

No interrupt is generated.

1

Set by watchdog timeout.

QDC

Quadrature direction change interrupt flag.
0

No interrupt is generated.

1

Set during change of direction.

PHE

Quadrature phase error interrupt flag.
0

No interrupt is generated.

1

Set on simultaneous transition of QEPA and QEPB.

PCE

Position counter error interrupt flag.
0

No interrupt is generated.

1

Set on position counter error.

INT

SPNU517C – March 2018
Submit Documentation Feedback

Description

Global interrupt status flag.
0

No interrupt is generated.

1

Interrupt is generated.
Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

465

eQEP Registers

www.ti.com

15.9.18 eQEP Interrupt Clear Register (QCLR)
Figure 15-38. eQEP Interrupt Clear (QCLR) Register (offset = 36h)
15

12

7

11

10

9

8

Reserved

UTO

IEL

SEL

PCM

R-0

R/W-0

R/W-0

R/W-0

R/W-0

3

2

1

0

6

5

4

PCR

PCO

PCU

WTO

QDC

PHE

PCE

INT

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15-21. eQEP Interrupt Clear (QCLR) Register Field Descriptions
Bit

Field

15-12

Reserved

11

10

9

8

7

6

5

4

3

2

1

0

466

Value
0

UTO

Description
Always write as 0.
Clear unit time out interrupt flag.

0

No effect.

1

Clears the interrupt flag.

IEL

Clear index event latch interrupt flag.
0

No effect.

1

Clears the interrupt flag.

SEL

Clear strobe event latch interrupt flag.
0

No effect.

1

Clears the interrupt flag.

PCM

Clear eQEP compare match event interrupt flag.
0

No effect.

1

Clears the interrupt flag.

PCR

Clear position-compare ready interrupt flag.
0

No effect.

1

Clears the interrupt flag.

PCO

Clear position counter overflow interrupt flag.
0

No effect.

1

Clears the interrupt flag.

PCU

Clear position counter underflow interrupt flag.
0

No effect.

1

Clears the interrupt flag.

WTO

Clear watchdog timeout interrupt flag.
0

No effect.

1

Clears the interrupt flag.

QDC

Clear quadrature direction change interrupt flag.
0

No effect.

1

Clears the interrupt flag.

PHE

Clear quadrature phase error interrupt flag.
0

No effect.

1

Clears the interrupt flag.

PCE

Clear position counter error interrupt flag.
0

No effect.

1

Clears the interrupt flag.

INT

Global interrupt clear flag.
0

No effect.

1

Clears the interrupt flag and enables further interrupts to be generated if an event flags is set to 1.

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

eQEP Registers

www.ti.com

15.9.19 eQEP Interrupt Force Register (QFRC)
Figure 15-39. eQEP Interrupt Force (QFRC) Register (offset = 34h)
15

12

7

11

10

9

8

Reserved

UTO

IEL

SEL

PCM

R-0

R/W-0

R/W-0

R/W-0

R/W-0

3

2

1

0

6

5

4

PCR

PCO

PCU

WTO

QDC

PHE

PCE

Reserved

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15-22. eQEP Interrupt Force (QFRC) Register Field Descriptions
Bit

Field

15-12

Reserved

11

10

9

8

7

6

5

4

3

2

1

0

Value
0

UTO

Force unit time out interrupt.
No effect.

1

Force the interrupt.
Force index event latch interrupt.

0

No effect.

1

Force the interrupt.

SEL

Force strobe event latch interrupt.
0

No effect.

1

Force the interrupt.

PCM

Force position-compare match interrupt .
0

No effect.

1

Force the interrupt.

PCR

Force position-compare ready interrupt.
0

No effect.

1

Force the interrupt.

PCO

Force position counter overflow interrupt.
0

No effect.

1

Force the interrupt.

PCU

Force position counter underflow interrupt.
0

No effect.

1

Force the interrupt.

WTO

Force watchdog time out interrupt.
0

No effect.

1

Force the interrupt.

QDC

Force quadrature direction change interrupt.
0

No effect.

1

Force the interrupt.

PHE

Force quadrature phase error interrupt.
0

No effect.

1

Force the interrupt.

PCE

SPNU517C – March 2018
Submit Documentation Feedback

Always write as 0.

0
IEL

Reserved

Description

Force position counter error interrupt.
0

No effect.

1

Force the interrupt.

0

Always write as 0.

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

467

eQEP Registers

www.ti.com

15.9.20 eQEP Status Register (QEPSTS)
Figure 15-40. eQEP Status (QEPSTS) Register (offset = 3Ah)
15

8
Reserved
R-0

7

6

5

4

3

UPEVNT

FIDF

QDF

QDLF

COEF

R-1

R-0

R-0

R-0

R/W-0

2

1

0

CDEF

FIMF

PCEF

R/W-0

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15-23. eQEP Status (QEPSTS) Register Field Descriptions
Bit

Field

15-8

Reserved

7

UPEVNT

6

5

4

3

2

1

0

468

Value
0

Description
Always write as 0.
Unit position event flag.

0

No unit position event is detected.

1

Unit position event is detected. Write 1 to clear.

FIDF

Direction on the first index marker. Status of the direction is latched on the first index event marker.
0

Counter-clockwise rotation (or reverse movement) on the first index event.

1

Clockwise rotation (or forward movement) on the first index event.

QDF

Quadrature direction flag.
0Counter-clockwise rotation (or reverse movement).

1

Clockwise rotation (or forward movement).

QDLF

eQEP direction latch flag. Status of direction is latched on every index event marker.
0

Counter-clockwise rotation (or reverse movement) on index event marker.

1

Clockwise rotation (or forward movement) on index event marker.

COEF

Capture overflow error flag.
0

Sticky bit, cleared by writing 1.

1

Overflow occurred in eQEP capture timer (QCTMR).

CDEF

Capture direction error flag.
0

Sticky bit, cleared by writing 1.

1

Direction change occurred between the capture position event.

FIMFFirst index marker flag.
0

Sticky bit, cleared by writing 1.

1

Set by first occurrence of index pulse.

PCEF

Position counter error flag. This bit is not sticky and it is updated for every index event.
0

No error occurred during the last index transition.

1

Position counter error.

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

eQEP Registers

www.ti.com

15.9.21 eQEP Capture Timer Register (QCTMR)
Figure 15-41. eQEP Capture Timer (QCTMR) Register (offset = 38h)
15

0
QCTMR
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 15-24. eQEP Capture Timer (QCTMR) Register Field Descriptions
Bit

Field

Description

15-0

QCTMR

This register provides the time base for the edge capture unit.

15.9.22 eQEP Capture Period Register (QCPRD)
Figure 15-42. eQEP Capture Period (QCPRD) Register (offset = 3Eh)
15

0
QCPRD
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 15-25. eQEP Capture Period Register (QCPRD) Register Field Descriptions
Bit

Field

Description

15-0

QCPRD

This register holds the period count value between the last successive eQEP position events.

SPNU517C – March 2018
Submit Documentation Feedback

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

469

eQEP Registers

www.ti.com

15.9.23 eQEP Capture Timer Latch Register (QCTMRLAT)
Figure 15-43. eQEP Capture Timer Latch (QCTMRLAT) Register (offset = 3Ch)150
QCTMRLAT
R-0

LEGEND: R = Read only; -n = value after reset

Table 15-26. eQEP Capture Timer Latch (QCTMRLAT) Register Field Descriptions
Bit

Field

Description

15-0

QCTMRLAT

The eQEP capture timer value can be latched into this register on two events: unit timeout event or reading
the eQEP position counter.

15.9.24 eQEP Capture Period Latch Register (QCPRDLAT)
Figure 15-44. eQEP Capture Period Latch (QCPRDLAT) Register (offset = 42h)
150
QCPRDLAT
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 15-27. eQEP Capture Period Latch (QCPRDLAT) Register Field Descriptions
Bit

Field

Description

15-0

QCPRDLAT

The eQEP capture period value can be latched into this register on two events: unit timeout event or reading
the eQEP position counter.

470

Enhanced Quadrature Encoder Pulse (eQEP) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Chapter 16
SPNU517C – March 2018

Analog To Digital Converter (ADC) ModuleThis chapter describes the analog to digital converter (ADC) interface module.
Topic...........................................................................................................................

Page

16.1 Overview ......................................................................................................... 472
16.2 Introduction ..................................................................................................... 472
16.3 Basic Features and Usage of the ADC................................................................. 475
16.4 Advanced Conversion Group Configuration Options ............................................ 482
16.5 ADC Module Basic Interrupts ............................................................................. 488
16.6 ADC Magnitude Threshold Interrupts .................................................................. 489
16.7 ADC Special Modes .......................................................................................... 490
16.8 ADC Results’ RAM Special Features ................................................................... 497
16.9 ADEVT Pin General Purpose I/O Functionality ..................................................... 498
16.10 ADC Registers ................................................................................................ 500

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

471

Overviewwww.ti.com

16.1 Overview
The main features of the ADC module are:• Selectable 10-bit or 12-bit resolution• Successive-approximation-register architecture• Three conversion groups – Group1, Group2 and Event Group• All three conversion groups can be configured to be hardware-triggered; group1 and group2 can also
be triggered by software• Conversion results are stored in a 64-word memory (SRAM)– These 64 words are divided between the three conversion groups and are configurable by software– Accesses to the conversion result RAM are protected by parity• Selectable channel conversion order– Sequential conversions in ascending order of channel number, OR– User-defined channel conversion order with the Enhanced Channel Selection Mode
• Single or continuous conversion modes• Embedded self-test logic for input channel failure detection (open / short to power / short to ground)• Embedded calibration logic for offset error correction• Enhanced Power-down mode
• External event pin (ADEVT) to trigger conversions– ADEVT is also programmable as general-purpose I/O• Eight hardware events to trigger conversions

16.2 Introduction
This section presents a brief functional description of the analog-to-digital converter (ADC) module.
Figure 16-1 illustrates the components of the ADC module.

16.2.1 Input Multiplexor
The input multiplexor (MUX) connects the selected input channel to the AIN input of the ADC core. The
ADC module supports up to 16 input channels. The sequencer selects the channel to be converted.

16.2.2 Self-Test and Calibration Cell
The ADC includes specific hardware that allows a software algorithm to detect open/short on an ADC
analog input. It also allows the application program to calibrate the ADC. Also see Section 16.7.1 andSection 16.7.2.

472

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Introduction

www.ti.com

Figure 16-1. ADC Block Diagram

ADREFHI
Self Test&
Calibration

Input “Multiplexer”

S3
R1

S4

S6

R2

ADIN[21]

ADC_resS2

V C CA D

S1

Sample Cap
Discharge Switch
V SS ADADREFLO

ADIN[20]
ADIN[17]

16

Input
ChannelSelection
EV_INT
GP1_INT
GP2_INTInterrupt
Generation

MAG_THR_INTADEVSRC.EV_SRC[2:0],
ADG1SRC.G1_SRC[2:0]and ADG2SRC.G2_SRC[2:0]

ADCLK
START
ADC_res

ADIN[0]

SWCNTRL[3:0]

ADIN[1]

Samp_Cap_Discharge

AIN

PDZ

10/12-bit
Successive Approximation
Analog-to-Digital
Converter

End OfConversion

10/12-bit
ResultAnalog Core Interface

Sequencer and
ADC Results’ Memory Interface
Controller

Event Trigger
Generation
Results’ RAM

VBUS Interface for Access to ADC Registers and Results’ RAM

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

473

Introduction

www.ti.com

16.2.3 Analog-to-Digital Converter Core
The ADC core is a combination voltage scaling, charge redistribution Successive Approximation Register(SAR) based analog-to-digital converter. The core can be configured for operation in 10-bit resolution(default) or 12-bit resolution. This is controlled by the sequencer logic. This selection applies to all
conversions performed by the ADC module. It is not possible to convert some channels with a 12-bit
resolution and some with a 10-bit resolution.
A single conversion from an analog input to a digital conversion result occurs in two distinct periods:• Sampling Period:– The sequencer generates a START signal to the ADC core to signal the start of the sampling
period.
– The analog input signal is sampled directly on to the switched capacitor array during this period,
providing an inherent sample-and-hold function.
– The sampling period ends one full ADCLK after the falling edge of the START signal.
– The sequencer can control the sampling period duration by configuring the conversion group’s
sample time control register (ADEVSAMP, ADG1SAMP, ADG2SAMP). This register controls thetime for which the START signal stays high.
• Conversion Period:– The conversion period starts one full ADCLK after the falling edge of START.
– One bit of the conversion result is output on each rising edge of ADCLK in the conversion period,
starting with the most-significant bit first.
– The conversion period is 12 ADCLK cycles in case of a 12-bit ADC, and is 10 ADCLK cycles incase of a 10-bit ADC.
– The ADC core generates an End-Of-Conversion (EOC) signal to the sequencer at the end of theconversion period. At this time the complete 12-, or 10-bit conversion result is available.
– The sequencer captures the ADC core conversion result output as soon as EOC is driven High.
The analog conversion range is determined by the reference voltages: ADREFHI and ADREFLO. ADREFHI is the
top reference voltage and is the maximum analog voltage that can be converted. An analog input voltage
equal to ADREFHI or higher results in an output code of 0x3FF for 10-bit resolution and 0xFFF for 12-bit
resolution. ADREFLO is the bottom reference voltage and is the minimum analog voltage that can beconverted. Applying an input voltage equal to ADREFLO or lower results in an output code of 0x000. Both
ADREFHI and ADREFLO must be chosen not to exceed the analog power supplies: VCCAD and VSSAD,
respectively. Input voltages between ADREFHI and ADREFLO produce a conversion result given by
Equation 30 for 10-bit resolution and by Equation 31 for 12-bit resolution.
1024 x (InputVoltage - AD REFLO)
DigitalResult = -------------------------------------------------------------------------------------- – 0.5
AD REFHI - AD REFLO(30)

4096 x(InputVoltage - AD REFLO) – 0.5
DigitalResult = -------------------------------------------------------------------------------------(AD REFHI - AD REFLO)(31)

16.2.4 Sequencer
The sequencer coordinates the operations of the ADC, including the input multiplexor, the ADC core, andthe result memory. In addition, the logic of the sequencer sets the status register flags when theconversion is ongoing, stopped, or finished.
All the features of the sequencer are discussed in detail in the following sections.

474

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Introduction

www.ti.com

16.2.5 Conversion Groups
Several applications require groups of channels to be converted using a single trigger source for example.
There could also be some groups of channels identified which require a specific setting of the acquisition
time. The ADC module supports three conversion groups for this purpose – Group1, Group2 and the
Event Group.
Any of the available analog input channels can be assigned to any of the conversion groups. This also
allows a particular channel to be repeatedly sampled by selecting it in multiple groups. There is an
inherent priority scheme used when multiple conversion groups are triggered at once. The Event Group is
the highest-priority, followed by the Group1 and then the Group2.
The Event Group is always hardware event-triggered. Group1 and Group2 are software-triggered bydefault and can be configured to be hardware-, or event-triggered as well. The triggering of conversions ineach group is discussed in Section 16.3.6.
Each conversion group has a separate set of control registers to:• Select the input channels to be converted• Configure the mode of conversion: single conversion sequence or continuous conversions• Configure the input channel sampling time
• Configure the interrupt request generation conditions

16.3 Basic Features and Usage of the ADC
This section describes the usage of the basic features of the ADC module.

16.3.1 How to Select Between 12-bit and 10-bit Resolutions
The 10_12_BIT field of the ADC Operating Mode Control Register (ADOPMODECR) configures the ADC
to be in 10-bit or 12-bit resolution mode.
• If 10_12_BIT = 0, the module is in 10-bit resolution mode. This is the default mode of operation.
• If 10_12_BIT = 1, the module is in 12-bit resolution mode.

16.3.2 How to Set Up the ADCLK Speed
The ADC sequencer generates the clock for the ADC core, ADCLK. The ADC core uses the ADCLK
signal for its timing. The ADCLK is generated by dividing down the input clock to the ADC module, whichis the VBUSP interface clock, VCLK. A 5-bit field (PS) in the ADC Clock Control Register (ADCLOCKCR)
is used to divide down the VCLK by 1 up to 32. The ADCLK valid frequency range is specified in thedevice datasheet.
fADCLK = fVCLK / (PS + 1)
The maximum frequency for ADCLK is specified in the device datasheet.

16.3.3 How to Set Up the Input Channel Acquisition Time
The signal acquisition time for each group is separately configurable using the ADG1SAMP[11:0],
ADG2SAMP[11:0], and ADEVSAMP[11:0] registers.
The acquisition time is specified in terms of ADCLK cycles and ranges from a minimum of 2 ADCLK
cycles to a maximum of 4098 ADCLK cycles.
For example, Group1 acquisition time, tACQG1 = G1SAMP[11:0] + 2, in ADCLK cycles.
The minimum acquisition time is specified in the device datasheet. This time also depends on the
impedance of the circuit connected to the analog input channel being converted. See the ADC Source
Impedance for Hercules™ ARM® Safety MCUs Application Report (SPNA118).

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

475

Basic Features and Usage of the ADC

www.ti.com

16.3.4 How to Select an Input Channel for Conversion
The ADC module needs to be enabled first before selecting an input channel for conversion. The ADC
module can be enabled by setting the ADC EN bit in the ADC Operating Mode Control Register(ADOPMODECR). Multiple input channels can be selected for conversion in each group. Only one input
channel is converted at a time. The channels to be converted are configured in one or more of the three
conversion groups’ channel selection registers. Channels to be converted in Group1 are configured in theGroup1 Channel-Select Register (ADG1SEL), those to be converted in Group2 are configured in theGroup2 Channel-Select Register (ADG2SEL), and those to be converted in the Event Group are
configured in the Event Group Channel-Select Register (ADEVSEL).
The description in this section only refers to the case when the enhanced channel selection mode is notenabled. Input channel selection in the enhanced channel selection mode is defined in Section 16.4.

16.3.5 How to Select Between Single Conversion Sequence or Continuous Conversions
Each group has its own mode control register. The MODE field of these control registers allow theapplication to select between a single conversion sequence or continuous conversion mode.
NOTE: Selecting continuous conversion mode for all three groups
All three conversion groups cannot be configured to be in a continuous conversion mode. If
the application configures the group mode control registers to enable continuous conversion
mode for all three groups, then the Group2 will be automatically be configured to be in asingle conversion sequence mode.

With conversions ongoing in continuous conversion mode, if the MODE field of a group is cleared, thenthat group switches to the single conversion sequence mode. Conversions for this group will stop once allchannels selected for that group have been converted.

16.3.6 How to Start a Conversion
The conversion groups Group1 and Group2 are software-triggered by default. A conversion in thesegroups can be started just by writing the desired channels to the respective Channel-Select Registers. For
example, in order to convert channels 0, 1, 2, and 3 in Group1 and channels 8, 9, 10, and 11 in Group2,
the application just has to write 0x0000000F to ADG1SEL and 0x00000F00 to ADG2SEL. The ADC
module will start by servicing the group that was triggered first, Group1 in this example.
The conversions for all groups are performed in ascending order of the channel number. For the Group1
the conversions will be performed in the order: channel 0 first, followed by channel 1, then channel 2, andthen channel 3. The Group2 conversions will be performed in the order: channels 8, 9, 10, and 11.
The Event Group is only hardware-triggered. There are up to eight hardware event trigger sources definedfor the ADC module. Check the device datasheet for a complete listing of these eight hardware trigger
options.
The trigger source to be used needs to be configured in the ADEVSRC register. Similar registers also
exist for the Group1 and Group2 as these can also be configured to be event-triggered.
The polarity of the event trigger is also configurable, with a falling edge being the default.
An Event Group conversion starts when at least one channel is selected for conversion in this group, andwhen the defined event trigger occurs.
If any conversion group is configured to be in a continuous conversion mode, then it needs to only be
triggered once. All the channels selected for conversion in that group will be converted repeatedly.

16.3.7 How to Know When the Group Conversion is Completed
Each conversion group has a status flag to indicate when its conversion has ended. See ADEVSR,
ADG1SR, and ADG2SR. This bit is set when a conversion sequence for a group ends. This bit does isalways set if a group is configured for continuous conversions.

476

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Basic Features and Usage of the ADC

www.ti.com

16.3.8 How Results are Stored in the Results’ Memory
The ADC stores the conversion results in three separate memory regions in the ADC Results’ RAM, one
region for each group. Each memory region is a stack of buffers, with each buffer capable of holding one
conversion result. The number of buffers allocated for each group is programmed by configuring the ADC
module registers ADBNDCR and ADBNDEND.
ADBNDCR contains two 9-bit pointers BNDA and BNDB. BNDA, BNDB, and BNDEND are used topartition the total memory available into three memory regions as shown in Figure 16-2. Both BNDA andBNDB are pointers referenced from the start of the results’ memory. BNDA specifies the number of buffers
allocated for the Event Group conversion results in units of two buffers; BNDB specifies the number ofbuffers allocated for the Event Group plus Group1 in units of two buffers. Refer to Section 16.10.20 for
more details on configuring the ADC results’ memory.
ADBNDEND contains a 3-bit field called BNDEND that configures the total memory available. The ADC
module can support up to 1024 buffers. The device supports a maximum of 64 buffers for both the ADC
modules.
Figure 16-2. FIFO Implementation
0x00

Total Memory Depth

Event Memory Depth

BNDAGroup 1 Memory Depth

BNDBGroup 2 Memory Depth
BNDEND•••

Number of buffers for Event Group = 2 × BNDA
Number of buffers for Group1 = 2 × (BNDB – BNDA)
Number of buffers for Group2 = Total number of buffers – 2 × BNDB

16.3.9 How to Read the Results from the Results’ Memory
The CPU can read the conversion results in one of two ways:
1. By using the conversion results memory as a FIFO queue
2. By accessing the conversion results memory directly

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

477

Basic Features and Usage of the ADC

www.ti.com

16.3.9.1 Reading Conversion Results from a FIFO
The conversion results for each group can be accessed via a range of addresses provided to facilitate theuse of the ARM Cortex-R4 CPU’s Load-Multiple (LDM) instruction. A single read performed using the LDR
instruction can also be used to read out a single conversion result. The results are read out from thegroup’s memory region as a FIFO queue by reading from any location inside this address range. The
conversion result that got stored first gets read first. A result that is read from the memory in this method
is removed from the memory. For example, a read from any address in the range ADEVBUFFER (offset
90h to AFh) pulls out one conversion result from the Event Group memory.
Figure 16-3. Format of Conversion Result Read from FIFO, 12-bit ADC
Offset Address
Register
0x90 to 0xAF
ADEVBUFFER

0xB0 to 0xCF
ADG1BUFFER

0xD0 to 0xEF
ADG2BUFFER

31

30
15

29
14

28
13

27
12

26
11

25
10

EV_
EMPTY

24
9

23
8

22
7

21
6

20
5

19
4

18
3

Reserved

17
2

16
1

0

EV_CHID

Reserved

EV_DR

G1_
EMPTY

Reserved

G1_CHID

Reserved

G1_DR

G2_
EMPTY

Reserved

G2_CHID

Reserved

G2_DR

Figure 16-4. Format of Conversion Result Read from FIFO, 10-bit ADC
Offset Address
Register
0x90 to 0xAF
ADEVBUFFER

0xB0 to 0xCF
ADG1BUFFER

0xD0 to 0xEF
ADG2BUFFER

31

30
15

29
14

28
13

27
12

26
11

25
10

24
9

23
8

22
7

21
6

20
5

19
4

18
3

17
2

16
1

0

Reserved
EV_
EMPTY

EV_CHID

EV_DR
Reserved

G1_
EMPTY

G1_CHID

G2_
EMPTY

G2_CHID

G1_DR
Reserved
G2_DR

Option to read channel id along with conversion result:
The application has an option to read the channel id along with the conversion result. This is controlled by
the CHID field of the group’s mode control register. If the option to read the channel id is not selected, thechannel id field of the conversion result reads as zeros.
Protection against reading from empty FIFO:
There is also a hardware mechanism to protect the application from reading past the number of newconversion results held in the FIFO. Once all available conversion results have been read out of the FIFO
by the application, a subsequent read from the FIFO causes the mechanism to indicate that the FIFO isempty by setting the EMPTY field.
Debug / Emulation Support:
For debug purposes, each conversion group also provides an address that the application can read fromfor extracting the group’s conversion results. However, no status flags for a conversion group are affectedby reading from these emulation buffer addresses. For example, reading from ADEVEMUBUFFER (offset
0xF0) returns the next result in the Event Group buffer but does not actually remove that result from thebuffer or change the amount of data held in the buffer.

478

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Basic Features and Usage of the ADC

www.ti.com

16.3.9.2 Reading Conversion Results Directly from the Conversion Results’ Memory
The conversion result memory is part of the device’s memory map. The base address for the ADC result
memory is 0xFF3E0000.
Figure 16-5. ADC Memory-Mapping
0xFF3E0000

Conversion word 0

0xFF3E0004

Conversion word 1

0xFF3E0008

Conversion word 2

0xFF3E01F8

Conversion word 62

0xFF3E00FC

Conversion word 63

The application can identify the address ranges for each of the three memory regions for the three
conversion groups after performing the segmentation as described in Section 16.3.8. It is up to theapplication to read the desired results from the three conversion groups. The formats of the conversion
results when reading from RAM directly are shown in Figure 16-6 and Figure 16-7.
Figure 16-6. Format of Conversion Result Directly Read from ADC RAM, 12-bit ADC
31

30
15

29
14

28
13

27
12

26
11

25
10

24
9

23
8

22
7

21
6

20
5

19
4

18
3

17
2

16
1

Reserved

ADC RAM
addresschannel id [3-0]0channelid [4]

12-bit conversion result

Figure 16-7. Format of Conversion Result Directly Read from ADC RAM, 10-bit ADC
31

30
15

ADC RAM
address

29
14

Rsvd

28
13

27
12

channel id [4-0]

26
11

25
10

24
9

23
22
21
20
19
18
17
16
8
7
6
5
4
3
2
1
0
Reserved
10-bit conversion result

Note that there is no EMPTY field to protect the application from reading data that has been previously
read.
Each group does have a separate register which holds the address in the group’s result memory where
the ADC will write the next conversion result. These are the ADEVRAMWRADDR, ADG1RAMWRADDR,
and ADG2RAMWRADDR registers. The application can use this information to calculate how many valid
conversion results are available to be read.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

479

Basic Features and Usage of the ADC

www.ti.com

Benefit of reading conversion results directly from ADC RAM:The application does not have to read out conversion results sequentially as in the case of reading from a
FIFO. As a result, the application can selectively read the conversion results for any particular input
channel of interest without having to read other channels’ conversion results.
16.3.9.3 Example
Suppose that channels 0, 1, and 2 are selected for conversion in the Event Group, channels 4, 7, and 8
are selected for conversion in group 1, and channels 3, 5, and 6 are selected for conversion in group 2.
The conversion results will get stored in the three memory regions as shown in Figure 16-8.
Suppose that the CPU wants to read out the results for the Event Group from a FIFO queue. The CPU
needs to read from any address in the range ADEVBUFFER (offset 0x90 to 0xAF) multiple times, or do a“load multiple” from this range of addresses. This will cause the ADC to return the results for channel 0,then channel 1, then channel 2, then channel 0, and so on for each read access to this address range.
Now suppose that the application wants to read out the results for the group 1 from the RAM directly. The
conversion results for the group 1 are accessible starting from address ADC RAM Base Address + BNDA.
Also, it is known that the first result at this address is for the input channel 4, the next one is for input
channel 7, and so on. So the application can selectively read the conversion results for only one channel if
so desired.
Figure 16-8. Conversion Results Storage
0x00

Channel 0
Channel 1
Channel 2
Channel 0
Channel 1

Event Group Memory

Channel 2

EV RAM ADDR

...

BNDA

Channel 4
Channel 7
Channel 8
Channel 4
Channel 7Group 1 Memory

Channel 8

G1 RAM ADDR

...

BNDB

Channel 3
Channel 5
Channel 6
Channel 3
Channel 5Group 2 Memory

Channel 6

G2 RAM ADDR...

BNDEND

16.3.10 How to Stop a Conversion
A group’s conversion can be stopped by clearing the group’s channel select register.

480

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Basic Features and Usage of the ADC

www.ti.com

16.3.11 Example Sequence for Basic Configuration of ADC Module
The following sequence is necessary to configure the ADC to convert channels 0, 2, 4, and 8 in singleconversion mode using Group1:
1. Write 0 to the Reset Control Register (ADRSTCR) to release the module from the reset state.
2. Write 1 to the ADC_EN bit of the Operating Mode Control Register (ADOPMODECR) to enable the
ADC state machine.
3. Configure the ADCLK frequency by programming the desired divider into the Clock Control Register(ADCLOCKCR).
4. Configure the acquisition time for the group that is to be used. For example, configure the Group1
Sampling Time Control Register (ADG1SAMP) to set the acquisition time for Group1.
5. Select the channels that need to be converted in Group1 by writing to the Group1 Channel SelectRegister (ADG1SEL). In this example, a value of 0x115 needs to be written to ADG1SEL in order toselect channels 0, 2, 4, and 8 for conversion in Group1.
• The ADC sequencer will start the Group1 conversions as soon as the write to the ADG1SEL
register is completed.
6. Wait for the G1_END bit to be set in the Group1 Conversion Status Register (ADG1SR). This bit gets
set when all the channels selected for conversion in Group1 are converted and the results are stored in
the Group1 memory.
7. Read the conversion results by reading from the Group1 FIFO access location (ADG1BUFFER) or byreading directly from the Group1 results’ memory.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

481

Advanced Conversion Group Configuration Options

www.ti.com

16.4 Advanced Conversion Group Configuration Options
Figure 16-9 shows the operating mode control registers and the status registers for each of the three
conversion groups. The register addresses shown are offsets from the base address. The ADC register
frame base address is FFF7 C000h.
Figure 16-9. ADC Groups’ Operating Mode Control and Status Registers
Offset Address
Register

31

30
15

29
14

28
13

27
12

26
11

25
10

24

23

9

22

8

7

21
6

20
5

19

18

4

3

17
2

16
1

Reserved
0x010
ADEVMODECR
EV_
DATA_FMT

Reserved

Reserved

EV_
CHID

OVR_
EV_
RAM_
IGN

Rsvd

EV_
8BIT

EV_
MODE

0x014
ADG1MODECRG1_DATA_FMT

Reserved

G1_
CHID

OVR_
G1_
RAM_
IGN

Rsvd

G1_
8BIT

G1_
MODE

0x018
ADG2MODECRG2_DATA_FMT

Reserved

FRZ_
G1
No
Reset
On
ChnSelReserved

Reserved

FRZ_
EV
No
Reset
On
ChnSelReserved

Reserved

0
No
Reset
On
ChnSel

G2_
CHID

OVR_
G2_
RAM_
IGN

Rsvd

G2_
8BIT

G2_
MODE

FRZ_
G2

EV_
MEM_
EMPTY

EV_
BUSY

EV_
STOP

EV_
END

G1_
MEM_
EMPTY

G1_
BUSY

G1_
STOP

G1_
END

G2_
MEM_
EMPTY

G2_
BUSY

G2_
STOP

G2_
END

Reserved
0x06C
ADEVSR

Reserved
Reserved

0x070
ADG1SR

Reserved
Reserved

0x074
ADG2SR

Reserved
Reserved

0x19C
ADEVCURRCOUNT

Reserved

EV_CURRENT_COUNT
Reserved

0x1A0
ADEVMAXCOUNT

Reserved

EV_MAX_COUNT
Reserved

0x1A4
ADG1CURRCOUNT

Reserved

0x1A8
ADG1MAXCOUNT

Reserved

0x1AC
ADG2CURRCOUNT

Reserved

G1_CURRENT_COUNT
Reserved
G1_MAX_COUNT
Reserved
G2_CURRENT_COUNT
Reserved

0x1B0
ADG2MAXCOUNT

Reserved

G2_MAX_COUNTThe following sections describe each of these group configuration options separately.

482

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackAdvanced Conversion Group Configuration Options

www.ti.com

16.4.1 Group Trigger Options
The Group1 and Group2 operating mode control registers have an extra control bit: HW_TRIG. This bit
configures the group to be hardware event-triggered instead of software-triggered, which is the default.
When a group is configured to be event-triggered, the group conversion starts when at least one channel
is selected for conversion in this group, and when the defined event trigger occurs. The event trigger
source is defined for each group in the ADEVSRC, ADG1SRC, and the ADG2SRC registers. The actual
connections used as the event trigger sources are defined in the device datasheet for both the ADC
modules.

16.4.2 Analog Input Channel Selection Mode Options
The ADC modules on this device support two different modes for selecting the analog input channel to beconverted. These are the sequential channel selection mode (default), and the enhanced channel
selection mode. These two modes are now described:
16.4.2.1 Sequential Channel Selection Mode
This is the default mode and allows the ADC module to be used in a backwards compatible mode to the
ADC module on other Hercules™ ARM® Safety MCUs from Texas Instruments. As discussed in
Section 16.3.4, an analog input channel can be selected for conversion in one or more conversion groups
by setting the bit corresponding to that channel number in the group's channel select register.
16.4.2.2 Enhanced Channel Selection Mode
There are some important concepts related to the enhanced channel selection mode. These are defined
first:• Look-Up Table
This is a 32-word deep memory-mapped region used to define the analog input channel number to beconverted. The look-up tables (LUTs) for the three groups are stacked together so that the entire LUT
occupies 96 words. Each word is aligned on a 32-bit boundary. The LUTs for ADC start at
0xFF3E2000.
• Conversion Group Sub-Sequence
A group sub-sequence is defined as the conversion for a set of channels that is converted on eachconversion trigger. The number of channels selected for conversion in a group sub-sequence isdefined by the number of bits that are set in the group's channel select register. For example, setting
bits 0, 1, 29, and 31 in ADG1SEL means that each Group1 conversion sub-sequence consists of 4
conversions.
• LUT Index
A "CURRENT_COUNT" register for each group is maintained as an index into that group's LUT. This
register increments each time a channel conversion is completed. Therefore, as its name suggests, aread from this register returns the number of conversions completed since the last write to the group's
channel select register. The CURRENT_COUNT register resets to all zeros under any of the following
conditions:
1. The ADC peripheral is reset via a global peripheral reset
2. The ADC peripheral is reset via the ADC Reset Control Register, see Section 16.10.1
3. The CURRENT_COUNT becomes equal to the MAX_COUNT defined for that conversion group
4. The application writes zeros to the CURRENT_COUNT register
5. The conversion group's result RAM is reset• Maximum Number of Conversions
A "MAX_COUNT" register for each conversion group stores the maximum number of conversions to be
performed before the index into a group's LUT is reset to zero. This register can be programmed to avalue between 0 and 31. It is recommended to program the MAX_COUNT register with a value that isone less than a multiple of the number of channels in that group's conversion sub-sequence (numberof bits that are set in the group's channel select register).

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

483

Advanced Conversion Group Configuration Options

www.ti.com

16.4.2.2.1 Look-Up Table Details
As described earlier, each conversion group has a look-up table (LUT) that is used when the enhanced
channel selection mode is enabled. This look-up table starts at an offset of 8kB from the base of the ADC
results RAM. The LUT holds 32 entries for each of the three conversion groups. The first 32 entries are forthe event group, the next 32 entries are for Group1 and the last 32 entries are for Group2. Figure 16-10
shows an example LUT entry for the Event group.
Figure 16-10. Example Look-Up Table Entry
31

16
Reserved
R-0

15

13

12

8

7

5

4

0

Reserved

EV_EXT_CHN_MUX_SEL

Reserved

EV_INT_CHN_MUX_SEL

R-0

R/W-0

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-1. ADC Look-Up Table Field Descriptions
Bit

Field

31–13

Reserved

12–8

EV_EXT_CHN_MUX_SEL

7–5

Reserved

4–0

EV_INT_CHN_MUX_SEL

Value
0

Description
Reads return 0. Writes have no effect.
Do not write to this bit field.

0

Reads return 0. Writes have no effect.
This field defines the internal analog mux select that is output from the ADC module
when the Event group CURRENT_COUNT register points to this LUT entry, andwhen the Event group conversion is triggered with the enhanced channel selection
mode enabled.
This can be a value between 0 and 31, which corresponds to the internal analog
input channel number between 0 and 31. Note that this device only supports 16 input
channels. If the application configures an unavailable channel number in the
EV_INT_CHN_MUX_SEL field, the ADC will still perform the conversion and theresult will be indeterminate.

16.4.3 Single or Continuous Conversion Modes
The EV_MODE, G1_MODE, and G2_MODE bits are used to select between either single or continuous
conversion mode for each of the three groups.
16.4.3.1 Single Conversion Mode
A conversion group configured to be in single-conversion mode gets serviced only once by the ADC foreach group trigger. The trigger can be a software trigger as in the case of Group1 and Group2 by default,
or it could be a hardware event trigger as in the case of the Event Group or Group1 or Group2.
The entire conversion sequence, from the acceptance of the group conversion request to the end of thelast channel’s conversion, is flagged for each group by the corresponding BUSY bit in that group’s status
register. After single-conversion mode is started, the BUSY bit is read as 1 until the conversion of the lastchannel is complete. The END bit for the group is set once all the channels in that group are converted.
For example, say channels 0, 2, 4, and 6 are selected for conversion in Group1 in single-conversion
mode. When the Group1 gets serviced, the ADC will start conversion for channel 0, then channel 2, thenchannel 4, and then channel 6. It will then stop servicing the Group1, set the G1_END status bit, and look
to service the Event Group or the Group2, if required.

484

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackAdvanced Conversion Group Configuration Options

www.ti.com

16.4.3.2 Continuous Conversion Mode
A conversion group configured to be in continuous-conversion mode gets serviced by the ADC
continuously. The group still needs to be triggered appropriately for the first conversion to start. The
conversions are performed continuously thereafter.
The entire conversion sequence, from the acceptance of the group conversion request to the end of thelast channel’s conversion, is flagged for each group by the corresponding BUSY bit in that group’s status
register. After continuous-conversion mode is started, the BUSY bit is read as 1 as long as thecontinuous-conversion mode for this group is selected.
As an example, say the channels 0, 2, 4, and 6 are selected for conversion in Group1, now in continuousconversion mode. When the Group1 gets serviced, the ADC will complete conversions for channels 0, 2, 4
and 6, and then look to service the Event Group or the Group2. Once it is done servicing the Event Groupor the Group2, it will return to service the Group1 again. The Group1 does not need to be triggered again
for the repeated conversion.
NOTE: Configuring all conversion groups in continuous conversion mode
All the three groups cannot operate in continuous-conversion mode at the same time. If theapplication program configures all three groups to be in continuous-conversion mode, theGroup2 is automatically reset to single-conversion mode, and the G2_MODE bit in the
ADG2MODECR register is cleared to reflect the single-conversion mode of Group2.

16.4.4 Conversion Group Freeze Capability
The ADC module has an inherent priority order between the three conversion groups. This group priority
determines the order of conversion in case multiple groups are triggered. The priority of conversions
between the three groups in descending order is:
1. Event Group
2. Group1
3. Group2
Examples of conversion group priority:• If an Event Group conversion is ongoing in single conversion sequence mode and Group2 and Group1
conversions are requested, then the ADC will finish conversion of channels selected in Event Group,
then switch over to converting channels selected in Group1, and then convert channels selected inGroup2.
• If Group1 conversions are ongoing in continuous conversion mode and Group2 conversion isrequested, then the ADC will complete converting the current channel for Group1 and switch over toconverting channels selected in Group2. The new conversion request for Group2 has a higher priority
than the pending continuous conversion request for Group1.
The conversion group freeze capability allows the application to override this default priority between theconversion groups. Enabling the freeze capability allows the ADC to freeze a higher-priority conversion
group’s conversions whenever there is a request for conversion in another (lower-priority) group.
For example, setting the FRZ_EV bit in the ADEVMODECR register will allow the ADC to freeze ongoing
Event Group conversions whenever there is a pending request, or a new request for a Group1 or Group2
conversion. The conversions for the Event Group will be frozen as long as the Group1 or Group2
conversions are active. Once the Group1 or Group2 conversions are completed, the Event Group
conversions start from where they were frozen.
While a group’s conversions are frozen, the group’s STOP status bit is set. This bit is cleared once thegroup’s conversions are restarted.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

485

Advanced Conversion Group Configuration Options

www.ti.com

16.4.5 Conversion Group Memory Overrun Option
An overrun condition occurs when the ADC module tries to store more conversion results to a group’s
results’ memory which is already full. In this case, the ADC allows two options.
If the OVR_RAM_IGN bit in the group’s operating mode control register (ADEVMODECR,
ADG1MODECR, ADG2MODECR) is set, then the ADC module ignores the contents of the group’s results’memory and wraps around to overwrite the memory with the results of new conversions.
If the OVR_RAM_IGN bit is not set, then the application program has to read out the group’s results’memory upon an overrun condition; only then can the ADC continue to write new results to the memory.

16.4.6 Response on Writing Non-Zero Value to Conversion Group’s Channel Select Register
If the application writes a non-zero value to a group’s channel select register while that group’s
conversions are already being serviced, then that group’s conversions will be restarted with the new
configuration programmed in the channel select registers.
The following rules apply in terms of the effect on the ADC conversion sequence:• If the new conversion request comes from the same group as the ongoing conversion, then theongoing conversion will be stopped in whichever stage it is in, and the new sequence of conversions
will be started.
• If the new conversion request comes from a separate group, then the ongoing channel’s conversion
will be completed before starting the new sequence of conversions.
The following rules apply in terms of the effect on the group’s results memory:• If a group conversion is ongoing or is frozen, writing a non-zero value to the group’s channel selectregister will also reset its results FIFO. This does not clear the contents of the results FIFO; only the
ADC module is allowed to overwrite the FIFO’s contents with new conversion results starting from thefirst location.
• If the group conversion is completed (<GRP>_END flag is set), or the group is not being used, thenwriting a non-zero value to the group’s channel select register will either be reset or not depending on
the value of the NoResetOnChnSel bit for that group (ADEVMODECR, ADG1MODECR,
ADG2MODECR).
– If the NoResetOnChnSel bit is 0, then the group’s FIFO will be reset.
– If the NoResetOnChnSel bit is 1, then the group’s FIFO will not be reset.

486

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackAdvanced Conversion Group Configuration Options

www.ti.com

16.4.7 Conversion Result Size on Reading: 8-bit, 10-bit, or 12-bit
Some applications do not need the full 12-bit resolution of the ADC modules on the device and can workwith 8-bit or 10-bit conversion results.
16.4.7.1 ADC Configured in 12-bit Resolution
The mode control register for each conversion group contains a field called DATA_FMT, which defines theformat of the conversion result read out of the result RAM, when accessed as a FIFO.
The DATA_FMT field is encoded as follows:• If DATA_FMT = 00, the complete 12-bit conversion result is read out of the FIFO.
• If DATA_FMT = 01, the 12-bit conversion result is right-shifted by 2 and the resulting 10-bit result isread out of the FIFO.
• If DATA_FMT = 10, the 12-bit conversion result is right-shifted by 4 and the resulting 8-bit result is readout of the FIFO.
This control field is not effective when the application chooses to access the conversion result memory
directly. In that case, the application can choose to mask off the number of bits as required.
16.4.7.2 ADC Configured in 10-bit Resolution
The DATA_FMT field is not effective in this mode and the application has the choice to read either the full
10-bit conversion result or an 8-bit conversion result. This is controlled by the 8BIT field of the group’s
operating mode control register.
• If 8BIT = 0, the complete 10-bit conversion result is read out of the FIFO.
• If 8BIT = 1, the 10-bit conversion result is right-shifted by 2 and the resulting 8-bit result is read out of
the FIFO.

16.4.8 Option to Read Group Channel ID Along With Conversion Result
The ADC module allows the application program to also read out the analog input channel number alongwith its conversion result. This capability is enabled by setting the CHID bit in the group’s operating mode
control register.
• If CHID = 0, the bits [14-10] are forced to 00000 when the conversion results are read out from thegroup’s results’ FIFO.
• If CHID = 1, the bits [14-10] in the group’s results’ memory contain the input channel number to which
the conversion result belongs.
NOTE: Actual Storage of Channel ID
Regardless of whether the CHID bit is set or not, the channel number is always stored in
the memory along with the conversion result. The CHID bit only affects whether the channel
number is available with the conversion result when the group’s memory is read.
Therefore, the CHID bit for a group can be changed dynamically without affecting thatgroup’s ongoing conversions.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

487

ADC Module Basic Interrupts

www.ti.com

16.5 ADC Module Basic Interrupts
This section describes the basic interrupts generated by the ADC module.

16.5.1 Group Conversion End Interrupt
The ADC module sets the group’s conversion end flag (EV_END, G1_END, or G2_END) in that group’s
interrupt flag register (ADEVINTFLG, ADG1INTFLG, ADG2INTFLG) when all the channels selected forconversion in that group are converted. This causes a group conversion end interrupt to be generated, if
this interrupt is enabled by setting the group’s END_INT_EN control bit (EV_END_INT_EN,
G1_END_INT_EN, or G2_END_INT_EN).
This interrupt can be easily used for conversion groups configured to be in the single-conversion mode.
The application program can read out the conversion results, change the group’s configuration if
necessary, and restart the conversions by triggering the group from within the interrupt service routine.
For groups configured to be in continuous conversion mode, this interrupt condition is not practical as theconversions are always in progress. In this case, the Group Memory Threshold Interrupt is more practicalas the application can allow a programmable number of conversion results to accumulate before
interrupting the CPU.

16.5.2 Group Memory Threshold Interrupt
The ADC module has the ability to generate an interrupt for a fixed number of conversions for each group.
A group memory threshold register determines how many conversion results must be in a group’s memory
region before the CPU is interrupted. This feature can be used to significantly reduce the CPU load whenusing interrupts for reading the conversion results.
The group’s threshold register needs to be configured before the group conversions are triggered. This
threshold register value behaves like a down-counter, which decrements each time the ADC writes aconversion result to this group’s memory. This counter is incremented each time the application program
reads a conversion result from the results’ memory by accessing the FIFO queue. Simultaneous read (byapplication program) and write (by ADC module) operations from the group’s results’ memory leave thethreshold counter unchanged.
The threshold counter can decrement past 0 and become negative. It always increments back to its
original value when the memory region is emptied. To determine how many samples are in the memory
region at a given moment, the threshold counter can be subtracted from the originally configured thresholdcount.
Whenever the threshold counter transitions from +1 to 0, it sets the group’s threshold interrupt flag, andthe CPU is interrupted if the group’s threshold interrupt is enabled. The CPU is expected to clear theinterrupt flag after reading the conversion results from the memory.
The interrupt flag is not set when the threshold counter stays at 0 or transitions from -1 to 0.

16.5.3 Group Memory Overrun Interrupt
An interrupt can be generated for each group if the number of ADC conversions for that group exceed thenumber of buffers allocated for that conversion group. Alternatively, the application program can set thegroup’s OVR_RAM_IGN bit and allow the ADC module to overwrite the group’s results’ memory contents
with new conversion results.

488

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Magnitude Threshold Interrupts

www.ti.com

16.6 ADC Magnitude Threshold Interrupts
The ADC allows up to three magnitude threshold interrupts to be generated. The comparison parameters
are programmed via the ADC Magnitude Compare Interrupt x Control Register (ADMAGINTxCR).

16.6.1 Magnitude Threshold Interrupt Configuration
The following fields are configurable for each of the three available magnitude threshold interrupts:
1. CHN_THR_COMP: Specifies whether to compare two channels’ conversion results, or to compare achannel’s conversion result to a programmable threshold value. A value of 0 will select the
programmable threshold to be compared, and a value of 1 will select the conversion result of thechannel identified by the COMP_CHID field to be compared.
2. MAG_CHID: Specifies the channel number from 0 to 31 whose conversion result needs to bemonitored.
3. COMP_CHID: Specifies the channel number from 0 to 31 whose last conversion result is used for thecomparison with the conversion result of the channel being monitored.
4. MAG_THR: Specifies the value for comparison with the conversion result of the channel identified by
the MAG_CHID field.
5. CMP_GE_LT: Specifies whether the conversion result of the channel identified by MAG_CHID iscompared to be “greater than or equal to”, or “less than” the reference value. The reference value canbe the conversion result of another channel identified by the COMP_CHID field, or it could be athreshold value specified in the MAG_THR field. A value of 0 in the CMP_GE_LT field indicates a “lessthan” comparison and a value of 1 indicates a “greater than or equal to” comparison.

16.6.2 Magnitude Threshold Interrupt Comparison Mask Configuration
There is also a separate comparison mask register (ADMAGxMASK) for each of the three magnitude
threshold interrupts. This register is used to specify the bits that are masked off for the sake of thecomparison. For example, the lower 4 bits of the conversion result can be masked off by writing 0xF to theinterrupt comparison mask register, allowing a gross comparison to be made. By default, the full 10/12-bit
conversion results are compared.

16.6.3 Magnitude Threshold Interrupt Enable / Disable Control
Each of the three magnitude interrupts also have separate interrupt enable set (ADMAGINTENASET) andclear (ADMAGINTENACLR) registers. These are used to respectively enable and disable that particularmagnitude threshold interrupt from being generated. To enable a magnitude threshold interrupt, write a 1
to the corresponding bit of the interrupt enable set register. Conversely, to disable a magnitude thresholdinterrupt, write a 1 to the corresponding bit of the interrupt enable clear register.

16.6.4 Magnitude Threshold Interrupt Flags
There is a separate magnitude interrupt flag register (ADMAGINTFLG) that holds the flags for these threeinterrupts. This flag gets set whenever the comparison condition for the corresponding interrupt is met. A
magnitude threshold interrupt is generated if the corresponding flag is set inside the flag register, and theinterrupt generation is enabled. This flag can be cleared by writing a 1 to the flag or by reading from theinterrupt offset register in case of this interrupt being the current highest-priority pending interrupt.

16.6.5 Magnitude Threshold Interrupt Offset Register
It is possible to have multiple magnitude threshold interrupts pending at the same time. The magnitude
threshold interrupt offset register (ADMAGINTOFF) holds the index of the currently pending highest
priority magnitude threshold interrupt. The magnitude threshold interrupt 1 has the highest priority while
the magnitude threshold interrupt 3 has the lowest priority. This is a read-only register and returns zeros ifnone of the magnitude threshold interrupts are pending. Writes to this register have no effect.
A read from this register updates the register to the next highest-priority pending magnitude thresholdinterrupt. This read also clears the corresponding flag from the magnitude threshold interrupt flag register.
However, a read from the magnitude threshold interrupt offset register in emulation mode does not affectthe interrupt flag register or the interrupt offset register.
SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

489

ADC Special Modes

www.ti.com

16.7 ADC Special Modes
The ADC module supports some special modes for diagnostics and power saving purposes.

16.7.1 ADC Error Calibration Mode
The application program can activate a calibration sequence any time self-test mode is disabled(SELF_TEST = 0). This calibration sequence includes the conversion of an embedded calibrationreference voltage followed by the calculation of an offset error correction value.
NOTE: Disable Self-Test Mode Before Calibration
To avoid errors during the calibration operation, self-test mode must not be enabled during acalibration sequence. In addition, to ensure accurate results, calibrate the ADC in anenvironment with minimum noise.

Calibration mode is enabled by setting the CAL_EN bit (ADCALCR.0). The application needs to ensurethat no conversion group is being serviced when the calibration mode is enabled.
The input multiplexor gets disabled and only the reference voltage is connected to the ADC core input.
Switch S5 of Figure 16-11 is opened. In addition, the digital result issued from a conversion is output fromthe ADC core to the calibration and offset error correction register, ADCALR. The ADC results’ memory is
not affected by the calibration conversion.
When calibration mode is disabled, the ADC can be configured for normal conversions.
Figure 16-11. Self-Test and Calibration Logic
ADREFHIADREFLO

Self-test andcalibration

R1 ~ 5K
R2 ~ 7K

S3 S4

S1 S2
R2

R1

ADIN[0]
16

MUX

Vin

S5

ADC Core

ADIN[21]CALR
ADCALR.9:0
ADDRx.16,9:0

16.7.1.1 Calibration Conversion
The calibration conversion also needs to meet the minimum sampling time specification for the ADC. Thisvalue is typically 1 us. The Event Group sample time register (ADEVSAMP) is used to specify the numberof ADCLK cycles for the calibration conversion.
The BRIDGE_EN and HILO bits (ADCALCR.9:8) control the voltage to the calibration reference device
shown in Figure 16-13. The positions of the switches in calibration mode are listed in Table 16-2.

490

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Special Modes

www.ti.com

Table 16-2. Calibration Reference Voltages(1)

CAL_ENBRIDGE_EN

HILO

S1

S2

S3

S4

S5

Reference Voltage

1

0

0

1

0

1

0

0

(ADREFHI × R1 + ADREFLO × R2) / (R1 + R2)

1

0

1

0

1

0

1

0

(ADREFLO × R1 + ADREFHI × R2) / (R1 + R2)

1

1

0

0

1

1

0

0

ADREFLO

1

1

1

1

0

0

1

0

ADREFHI

0

X

X

0

0

0

0

1

Vin

(1)

The state of the switches in this table assumes that self-test mode is not enabled.

When CAL_ST (ADCALCR.16) is set, a calibration conversion is started. The voltage source selected via
the BRIDGE_EN and HILO bits is converted once (single conversion mode) and the digital result isreturned to the calibration and correction register, ADCALR, where it can be read by the CPU. The
CAL_ST bit acts as a flag and must be polled by the CPU. It is held set during the conversion process andautomatically clears to indicate the end of the reference voltage conversion.
NOTE: No Interrupt for end of calibration
The ADC does not generate an interrupt to signal the end of the calibration conversion. The
application must poll the CAL_ST bit to determine the end of the calibration conversion.

After the CAL_ST bit is set by the application program, it can only be reset by the end of the ongoing
conversion generated by the ADC core. If the calibration conversion is interrupted (CAL_EN bit is cleared),
the CAL_ST bit is held at 1 until a new calibration conversion has been set and completed. Setting the
CAL_ST bit while calibration is disabled (CAL_EN = 0) has no effect; however, in this situation, setting
CAL_EN immediately starts a calibration conversion. When the calibration conversion is interrupted by an
ADC enable (ADC_EN = 0, CAL_EN = 1, and CAL_ST = 1), a new conversion is automatically restarted
as soon as the ADC enable bit is released (ADC_EN = 1).
16.7.1.2 Calibration and Offset Error Correction Sequences
The number of measurements and the source to measure for an ADC calibration are application
dependent. The CAL_ST bit must be set for each calibration source to be measured. While calibration
mode is enabled, any available calibration sources can be converted according to the BRIDGE_EN andHILO bits (see Table 16-2). The digital results of the calibration measurements should be read from
ADCALR by the application after each reference conversion so that a correction value can be computed
and written back into ADCALR.
When the application has the necessary calibration data, it should compute the offset error correction
value and load it into the calibration and correction register, ADCALR. After the CAL_EN bit is cleared,
normal conversion mode restarts, continuing from where it was frozen, but with the addition of selfcorrection data.
In normal mode, the self-correction system adds the correction value stored in ADCALR to each digital
result before it is written to the respective group’s FIFO.
The basic calibration routine is as follows:
1. Enable calibration via CAL_EN (ADCALCR.0).
2. Select the voltage source via BRIDGE_EN and HILO (ADCALCR.9:8).
3. Start the conversion with CAL_ST (ADCALCR.16).
4. Wait for CAL_ST to go to 0.
5. Get the results from ADCALR and save to memory.
6. Loop to step 2 until the calibration conversion data is collected for the desired reference voltages.
7. Compute the error correction value using calibration data saved in memory.
8. Load the ADCALR register with the 2s complement of the computed error correction value.
9. Disable calibration mode.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

491

ADC Special Modes

www.ti.com

At this point, the ADC can be configured for normal operation, and it corrects each digital result with theerror correction value loaded in ADCALR.
NOTE: Prevent ADC Calibration Data From Being Overwritten
In calibration mode, the conversion result is written to ADCALR which overwrites any
previous calibration data; therefore, the ADCALR register must be read before a newconversion is started.

For no correction, a value of 0x0000 must be written to ADCALR. In noncalibration mode, the ADCALR
register can be read and written. Any value written to ADCALR in normal mode (CAL_EN = 0) is added toeach digital result from the ADC core.
16.7.1.3 Mid-Point Calibration
Because of its connections to the ADC’s reference voltage (VrefHi, VrefLo), the precision of the calibrationreference is voltage independent. On the other hand, the accuracy of the switched bridge resistor (R1 &R2) relies on the manufacturing process deviation. Consequently, the mid-point voltage’s accuracy can beaffected due to the imperfections in the two resistors (expected mismatch error is around 1.5%).
The switched reference voltage device has been specially designed to support a differential measurementof its mid-point voltage. This ensures the accuracy of the mid-point reference, and hence the efficiency ofthe calibration.
The differential mid-point calibration is software controlled; the algorithm (voltage source measurements
and associated calculation) is inserted within the calibration software module included in the application
program.
The basic differential mid-point calibration flow is illustrated here after:
1. The application program connects the voltage VrefHi to R1 and VrefLo to R2, (BRIDGE_EN = 0,
HILO = 0), launches a conversion of the input voltage V(cal1), and stores the digital result D(cal1) into
the memory.
2. Then the application program switches the voltage VrefHi to R2 and VrefLo to R1 (BRIDGE_EN = 0,
HILO = 1), converts this new input voltage V(cal2) and again stores the issued digital result D(cal2)
into the memory.
3. The actual value of the real middle point is obtained by computing the average of these two results.
[D(cal1)+D(cal2)] /2; Figure 16-12 summarizes the mid-point calibration flow.

492

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Special Modes

www.ti.com

Figure 16-12. Mid-point Value Calculation
Digital Code (hex)

FS

3FF

* The Real function shown is a straightline between the ends points of the realstaircase characteristic.

10-bit ADC’s Theoretical
Transfer Function

The Theoretical transfer function isfor reference only.

*Realstraight line
Transfer Function

D(cal2)D(cal)

R

D(cal1)Vin
VrefLoV(cal1)V(cal2)

VrefHi(VrefHi - VrefLo)/2

MEMORYV(cal1) = [VREFHI*R1+VREFLO*R2] / (R1 + R2)

D(cal1)V(cal2) = [VREFLO*R1+VREFHI*R2] / (R1 + R2)

D(cal2)CPU[V(cal1) + V(cal2)] / 2 = (VrefHi-VrefLo) / 2

SPNU517C – March 2018
Submit Documentation Feedback[D(cal1) + D(cal2)] / 2 = D(cal)Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

493

ADC Special Modes

www.ti.com

16.7.2 ADC Self-Test Mode
The ADC module supports a self-test mode which can be used to detect an open or a short on the ADC
input channels. Self-test mode is enabled by setting the SELF_TEST bit (ADCALCR.24). Any conversion
type (continuous or single conversion, freeze enabled or non-freeze enabled, interrupts enabled or
disabled) can be performed in this mode.
In normal mode, setting the self-test mode while a conversion sequence is in process can corrupt thecurrent channel conversion results. However, the next channel in the sequence is converted correctly
during the additional self-test cycle. The logic associated with both self-test and calibration is shown in
Figure 16-13.
Figure 16-13. Self-Test and Calibration Logic
ADREFHIADREFLO

Self-test andcalibration

R1 ~ 5K
R2 ~ 7K

S3 S4

S1 S2
R2

R1

ADIN[0]
16

MUX

Vin

S5

ADC Core

ADIN[21]CALR
ADCALR.9:0
ADDRx.16,9:0

In self-test mode, a test voltage defined by the HILO bit (ADCALCR.8) is provided to the ADC core input
through a resistor (see Table 16-3). To change the test source, this bit can be toggled before any single
conversion mode request. Changing this bit while a conversion is in progress can corrupt the results if thesource switches during the acquisition period.
Note that the switch S5 shown in Figure 16-13 is only for the purpose of explaining the self-test sequence.
There is no physical switch.
Table 16-3. Self-Test Reference Voltages (1)(1)

SELF_TEST

HILO

S1

S2

S3

S4

S5

Reference Voltage

1

0

0

1

1

0

1

ADREFLO via R1 || R2 connected to Vin

1

1

1

0

0

1

1

ADREFHI via R1 || R2 connected to Vin

0

X

0

0

0

0

1

Vin

Switches refer to Figure 16-13.

Conversions in self-test mode are started just as they are in the normal operating mode (seeSection 16.3.6). The conversion starts according to the configuration set in the three mode control
registers (ADEVMODECR, ADG1MODECR, ADG2MODECR) and the sampling time control registers(ADEVSAMP, ADG1SAMP, ADG2SAMP). The acquisition time for each conversion in self-test mode isextended to twice the normal configured acquisition time. The selected reference voltage and the input
voltage from the ADINx input channel are both connected to the ADC internal sampling capacitor
throughout this extended acquisition period. Figure 16-14 shows the self-test mode timing when the
ADREFLO is chosen as the reference voltage for the self-test mode conversion. It also assumes anexternal capacitor connected to the ADC input channel.
494

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Special Modes

www.ti.com

Figure 16-14. Timing for Self-Test Mode
Sample time doubled in self-test mode
Sample time in normal operation mode

Tsamp1ADREFLO + ADINx

Tsamp2
ADREFLO + ADINx

Conversion of last value sampled

Start

ADREFHI
Ext. Input
AD_Core _In

discharge of ext. cap

charging of ext. cap

ADREFLOtime

16.7.2.1 Use of Self-Test Mode to Determine Open/Short on ADC Input Channels
The following sequence needs to be used to deduce the ADC pin status:• Convert the channel with self test enabled and with the reference voltage as Vreflo. Store theconversion result, say Vd.
• Convert the channel with self test enabled and with the reference voltage as Vrefhi. Store theconversion result, say Vu.
• Convert the channel with self test disabled. Store the conversion result, say Vn.
The results can be interpreted using Table 16-4.
Table 16-4. Determination of ADC Input Channel Condition
Normal Conversion
Result, Vn

Self-test Conversion
Result, Vu

Self-test Conversion
Result, Vd

Pin Condition

Vn

Vn < Vu < ADREFHI

ADREFLO < Vd < Vn

Good

ADREFHIADREFHIapprox. ADREFHI

Shorted to ADREFHI

ADREFLO

approx. ADREFLO

ADREFLO

Shorted to ADREFLO

Unknown

ADREFHIADREFLO

Open

16.7.3 ADC Power-Down Mode
This is an inactive mode in which the clocks to the ADC module are stopped leaving the module in a staticstate. The clock to the ADC core (ADCLK) is stopped whenever there are no ongoing conversions. This is
the clock-gating implementation requirement. Also, the ADC module places the ADC core into the power
down mode such that there is minimal current drawn from the ADC operating and reference supplies.
16.7.3.1 Powering Down Just The ADC Core
The ADC core can be individually powered down without stopping the clocks to the ADC module. This canbe done by setting the POWERDOWN bit of the ADC Operating Mode Control Register(ADOPMODECR.3). Whenever a conversion is required the POWERDOWN bit must be cleared, and aminimum time td(PU-ADV), (see the specific device data sheet for actual value) has to be allowed before
starting a new conversion. This wait must be implemented in the application software.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

495

ADC Special Modes

www.ti.com

16.7.3.2 Enhanced Power-Down Mode
A bit in the ADC operating mode control register, IDLE_PWRDN (ADOPMODECR.4) enables theenhanced power-down mode of the ADC.
Once this bit is set, the ADC module will power down the ADC core whenever there are no more ongoingor pending ADC conversions. The ADC core will be powered down regardless of the state of the
POWERDOWN bit (ADOPMODECR.3).
The ADC module releases the ADC core from power down mode as soon as a new conversion isrequested. The ADC logic state machine then has to wait for at least td(PU-ADV) (see the device data sheet
for actual value) before starting a new conversion. The IDLE_PWRDN bit will remain set at all times. The
logic state machine can use this bit to determine that it needs to wait for a programmable number of VCLK
cycles before it allows the input channel to be sampled. This time is configured by the ADC Power Up
Delay Control register (ADPWRUPDLYCTRL).
If IDLE_PWRDN is not set, the ADC module does not wait for any additional delay before sampling the
input channel and the application software has to take account of this required delay.
16.7.3.3 Managing Clocks to the ADC Module
The clock to the ADC module can be turned off via the appropriate Peripheral Central Resource (PCR)
controller PSPWRDNSET register (check the specific device datasheet to identify the register and the bit
to be set). If a conversion is ongoing when this bit is set, the ADC module will wait until the current
conversion completes before allowing the ADC module clock to be stopped.

16.7.4 ADC Sample Capacitor Discharge Mode
This mode allows the charge on the ADC core’s internal sampling capacitor to be discharged before
starting the sampling phase of the next channel.
The ADC Sample Cap Discharge Mode is enabled by setting the SAMP_DIS_EN bit of the group’s
ADSAMPDISEN register. A discharge period for the sampling capacitor is added before the sampling
period for each channel as shown in Figure 16-15. The duration of this discharge period is configurable via
the corresponding group’s SAMP_DIS_CYC field in the ADSAMPDISEN register. The discharge time isspecified in terms of number of ADCLK cycles.
During the sample capacitor discharge period, the VREFLO reference voltage is connected to the input
voltage terminal of the ADC core. This allows any charge collected on the sampling capacitor from theprevious conversion to be discharged to ground. The VREFLO reference voltage is usually connected to
ground.
Figure 16-15. Timing for Sample Capacitor Discharge Mode
Sample cap discharge time

Tdischarge
VrefloSampling time

Tsamp
ADINx

Conversion of last value sampled

Start

496

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Results’ RAM Special Features

www.ti.com

16.8 ADC Results’ RAM Special Features
The following sections describe some of the special features supported by the ADC module to enhance
the results’ RAM testability and integrity.

16.8.1 ADC Results’ RAM Auto-Initialization
The ADC module allows the application to auto-initialize the ADC results’ RAM to all zeros. The
application must ensure that the ADC module is not in any of the conversion modes before triggering off
the auto-initialization process.
The auto-initialization sequence is as follows:
1. Enable the global hardware memory initialization key by programming a value of Ah to bits [3-0] of the
MINITGCR register of the System module.
2. Set the control bit for the ADC results’ RAM in the MSINENA System module register. Bit 8 of the
MSINENA register is used to control the initialization of the ADC results’ RAM. This starts theinitialization process. The BUF_INIT_ACTIVE flag in the ADC module ADBNDEND register will get set
to reflect that the initialization is ongoing.
3. When the memory initialization is completed, the corresponding status bit in the MINISTAT register will
be set. Also, the BUF_INIT_ACTIVE flag will get cleared.

16.8.2 ADC Results’ RAM Test ModeIn the defined conversion modes of the ADC, the application can only read from the ADC results’ RAM.
Only the ADC module is allowed to write to the results’ RAM. A special test mode is defined to allow theapplication to also write into the ADC results’ RAM - this mode is the ADC Results’ RAM Test Mode. Only
32-bit reads and writes are allowed to the ADC results’ RAM in this test mode.
NOTE: Contention on access to ADC Results’ RAM
The ADC module cannot handle a contention between the application write to the results’
RAM and the ADC writing a conversion result to the results’ RAM. The application mustensure that the ADC is not likely to write a new conversion result to the results’ RAM whenthe ADC Results’ RAM Test Mode is enabled.

The ADC Results’ RAM Test Mode is enabled by setting the RAM_TEST_EN bit in the ADOPMODECR.

16.8.3 ADC Results’ RAM Parity
The following shows the ADC Results’ RAM parity control registers.
Parity checking is implemented using parity on a per-half word basis for the ADC RAM. That is, there is
one parity bit for 16 bits of the ADC RAM. The polarity of the ADC RAM parity is controlled by the
DEVCR1 register in the system module (address = FFFF FFDCh). The parity checking is enabled by the
ADPARCR register. After reset, the parity checking is disabled and must be enabled if parity protection isrequired.
During a read access, the parity is calculated based on the data read from the ADC RAM and comparedwith the good parity value stored in the parity bits. If any word fails the parity check then the ADC
generates an error signal hooked up to the Error Signaling Module (ESM). The ADC RAM address which
generated the parity error is captured for host system debugging, and is frozen from being updated until it
is read by the application.
Testing the Parity Checking Mechanism:
To test the parity checking mechanism itself, the parity RAM is made writable by the CPU in a special test
mode. This is done by a control bit, TEST, in the ADPARCR register. Once this bit is set, the parity bits
are mapped to an address starting at an address offset of 4KB from the base address of the ADC RAM.
See Figure 16-16. The CPU can now manually insert parity errors. Note that the ADC RAM only supports
32-bit accesses.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

497

ADEVT Pin General Purpose I/O Functionality

www.ti.com

Figure 16-16. ADC Memory Map in Parity Test Mode
BASE ADDRESS

0xFF3E0000

Conversion word 0

0xFF3E0004

Conversion word 1

0xFF3E0008

Conversion word 2

0xFF3E01F8

Conversion word 62

0xFF3E00FC

Conversion word 63
Reserved

0xFF3E1000
Parity Bits

16.9 ADEVT Pin General Purpose I/O Functionality
The ADEVT pin can be configured as general-purpose I/O signals. The following sections describe thedifferent ways in which the application can configure the ADEVT pins.

16.9.1 GPIO Functionality
Figure 16-17 illustrates the GPIO functionality of the ADEVT pin.
Figure 16-17. GPIO Functionality of ADEVT
Output enable
ADEVT
pin

Data out
Data in

Pull control disable

Pull control
logic

Pull select498

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADEVT Pin General Purpose I/O Functionality

www.ti.com

Once the device power-on reset is released, the ADC module controls the state of the ADEVT pin.
• Pull control: The pull control can either be enabled or disabled by default (while system reset is active
and after it is released). The actual default state of the pull control is specified in the device datasheet.
The application can enable pull control by clearing the PDIS (pull control disable) bit in the
ADEVTPDIS register. In this case, if the PSEL (pull select) bit in the ADEVTPSEL register is set, thepin will have a pull-up. If the PSEL bit is cleared, the pin will have a pull-down. If the PDIS bit is set in
the control register, there is no pull-up or pull-down on the pin.
NOTE: Pull Behavior when ADEVT is configured as output
If the ADEVT pin is configured as output, then the pulls are disabled automatically. If the pin
is configured as input, the pulls are enabled or disabled depending on bit PDIS in the pull
disable register ADEVTPDIS.

••

Output buffer: The ADEVT pin can be driven as an output pin if the ADEVTDIR bit is set in the pin
direction control register.
Open-Drain Feature: The open drain output capability is enabled via the ADEVTPDR control register.
The ADEVT pin must be also configured to be an output pin for this mode.
– The output buffer is enabled if a low signal is being driven on to the pin.
– The output buffer is disabled if a high signal is being driven on to the pin.

16.9.2 Summary
The behavior of the output buffer, and the pull control is summarized in Table 16-5. The input buffer for
the ADEVT pin is enabled once the device power-on reset is released.
Table 16-5. Output Buffer and Pull Control Behavior for ADEVT as GPIO Pins

(1)
(2)
(3)
(4)

System Reset
Active?

Pin Direction(DIR) (1) (2)Pull Disable(PDIS) (1) (3)Pull Select(PSEL) (1) (4)

Yes

X

X

No

0

0

No

0

No
No
No

Pull Control

Output Buffer

X

EnabledDisabled0

Pull down

Disabled0

1

Pull up

Disabled0

1

0

Disabled

Disabled0

1

1

Disabled

Disabled

1

X

X

Disabled

Enabled

X = Don’t care
DIR = 0 for input, 1 for output
PDIS = 0 for enabling pull control, 1 for disabling pull control
PSEL= 0 for pull-down functionality, 1 for pull-up functionality

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

499

ADC Registers

www.ti.com

16.10 ADC Registers
All registers in the ADC module are 32-bit, word-aligned; 8-bit, 16-bit and 32-bit accesses are allowed.
The application must ensure that the reserved bits are always written as 0 to ensure software compatibility
to future revisions of the module. Table 16-6 shows register address offsets from the base address of the
ADC modules. The base address of ADC registers is FFF7 C000h.
Table 16-6. ADC Registers
OffsetAcronym

Register Description

Section00h

ADRSTCRADC Reset Control Register

Section 16.10.1

04h

ADOPMODECRADC Operating Mode Control Register

Section 16.10.2

08h

ADCLOCKCRADC Clock Control Register

Section 16.10.3

0Ch

ADCALCR

ADC Calibration Mode Control Register

Section 16.10.4

10h

ADEVMODECRADC Event Group Operating Mode Control Register

Section 16.10.5

14h

ADG1MODECRADC Group1 Operating Mode Control Register

Section 16.10.6

18h

ADG2MODECRADC Group2 Operating Mode Control Register

Section 16.10.7

1Ch

ADEVSRCADC Trigger Source Select Register

Section 16.10.8

20h

ADG1SRCADC Group1 Trigger Source Select Register

Section 16.10.9

24h

ADG2SRCADC Group2 Trigger Source Select Register

Section 16.10.10

28h

ADEVINTENAADC Event Interrupt Enable Control Register

Section 16.10.11

2Ch

ADG1INTENAADC Group1 Interrupt Enable Control Register

Section 16.10.1230h

ADG2INTENAADC Group2 Interrupt Enable Control Register

Section 16.10.13

34h

ADEVINTFLGADC Event Group Interrupt Flag Register

Section 16.10.14

38h

ADG1INTFLGADC Group1 Interrupt Flag Register

Section 16.10.15

3Ch

ADG2INTFLGADC Group2 Interrupt Flag Register

Section 16.10.16

40h

ADEVTHRINTCR

ADC Event Group Threshold Interrupt Control Register

Section 16.10.17

44h

ADG1THRINTCR

ADC Group1 Threshold Interrupt Control Register

Section 16.10.18

48h

ADG2THRINTCR

ADC Group2 Threshold Interrupt Control Register

Section 16.10.19

58h

ADBNDCRADC Results Memory Configuration Register

Section 16.10.20

5Ch

ADBNDEND

ADC Results Memory Size Configuration Register

Section 16.10.21

60h

ADEVSAMPADC Event Group Sampling Time Configuration Register

Section 16.10.22

64h

ADG1SAMPADC Group1 Sampling Time Configuration Register()

Section 16.10.23

68h

ADG2SAMPADC Group2 Sampling Time Configuration Register

Section 16.10.24

6Ch

ADEVSRADC Event Group Status Register

Section 16.10.25

70h

ADG1SRADC Group1 Status Register

Section 16.10.26

74h

ADG2SRADC Group2 Status Register

Section 16.10.27

78h

ADEVSELADC Event Group Channel Select Register

Section 16.10.28

7Ch

ADG1SELADC Group1 Channel Select Register

Section 16.10.29

80h

ADG2SELADC Group2 Channel Select Register

Section 16.10.30

84h

ADCALRADC Calibration and Error Offset Correction Register

Section 16.10.31

88h

ADSMSTATEADC State Machine Status Register

Section 16.10.32

8Ch

ADLASTCONVADC Channel Last Conversion Value Register

Section 16.10.33

90h-AFhADEVBUFFER

ADC Event Group Results FIFO Register

Section 16.10.34

B0h-CFh

ADG1BUFFERADC Group1 Results FIFO Register

Section 16.10.35

D0h-EFh

ADG2BUFFERADC Group2 Results FIFO Register

Section 16.10.36

F0h

ADEVEMUBUFFER

ADC Event Group Results Emulation FIFO Register

Section 16.10.37

F4h

ADG1EMUBUFFERADC Group1 Results Emulation FIFO Register

Section 16.10.38

F8h

ADG2EMUBUFFERADC Group2 Results Emulation FIFO Register

Section 16.10.39

FCh

ADEVTDIRADC ADEVT Pin Direction Control Register

Section 16.10.40

100h

ADEVTOUTADC ADEVT Pin Output Value Control Register

Section 16.10.41

104h

ADEVTIN

ADC ADEVT Pin Input Value Register

Section 16.10.42

500 Analog To Digital Converter (ADC) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

ADC Registers

www.ti.com

Table 16-6. ADC Registers (continued)
OffsetAcronym

Register Description

108h

ADEVTSETADC ADEVT Pin Set Register

Section 16.10.43

Section

10Ch

ADEVTCLR

ADC ADEVT Pin Clear Register

Section 16.10.44

110h

ADEVTPDRADC ADEVT Pin Open Drain Enable Register

Section 16.10.45

114h

ADEVTPDISADC ADEVT Pin Pull Control Disable Register

Section 16.10.46

118h

ADEVTPSELADC ADEVT Pin Pull Control Select Register

Section 16.10.47

11Ch

ADEVSAMPDISENADC Event Group Sample Cap Discharge Control Register

Section 16.10.48

120h

ADG1SAMPDISENADC Group1 Sample Cap Discharge Control Register

Section 16.10.49

124h

ADG2SAMPDISENADC Group2 Sample Cap Discharge Control Register

Section 16.10.50

128h-138h

ADMAGINTxCR

ADC Magnitude Compare Interrupt x Control Register

Section 16.10.51

12Ch-13Ch

ADMAGxMASKADC Magnitude Compare Interrupt x Mask Register

Section 16.10.52

158h

ADMAGINTENASET

ADC Magnitude Compare Interrupt Enable Set Register

Section 16.10.53

15Ch

ADMAGINTENACLR

ADC Magnitude Compare Interrupt Enable Clear Register

Section 16.10.54

160h

ADMAGINTFLG

ADC Magnitude Compare Interrupt Flag Register

Section 16.10.55

164h

ADMAGINTOFFADC Magnitude Compare Interrupt Offset Register

Section 16.10.56

168h

ADEVFIFORESETCRADC Event Group FIFO Reset Control Register

Section 16.10.57

16Ch

ADG1FIFORESETCRADC Group1 FIFO Reset Control Register

Section 16.10.58

170h

ADG2FIFORESETCRADC Group2 FIFO Reset Control Register

Section 16.10.59

174h

ADEVRAMWRADDR

ADC Event Group RAM Write Address Register

Section 16.10.60

178h

ADG1RAMWRADDRADC Group1 RAM Write Address Register

Section 16.10.61

17Ch

ADG2RAMWRADDRADC Group2 RAM Write Address Register

Section 16.10.62

180h

ADPARCR

ADC Parity Control Register

Section 16.10.63

184h

ADPARADDRADC Parity Error Address Register

Section 16.10.64

188h

ADPWRUPDLYCTRLADC Power-Up Delay Control Register

Section 16.10.65

190h

ADEVCHNSELMODECTRLADC Event Group Channel Selection Mode Control Register

Section 16.10.66

194h

ADG1CHNSELMODECTRLADC Group1 Channel Selection Mode Control Register

Section 16.10.67

198h

ADG2CHNSELMODECTRLADC Group2 Channel Selection Mode Control Register

Section 16.10.68

19Ch

ADEVCURRCOUNTADC Event Group Current Count Register

Section 16.10.69

1A0h

ADEVMAXCOUNTADC Event Group Max Count Register

Section 16.10.70

1A4h

ADG1CURRCOUNTADC Group1 Current Count Register

Section 16.10.71

1A8h

ADG1MAXCOUNTADC Group1 Max Count Register

Section 16.10.72

1ACh

ADG2CURRCOUNTADC Group2 Current Count Register

Section 16.10.73

1B0h

ADG2MAXCOUNTADC Group2 Max Count Register

Section 16.10.74

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

501

ADC Registers

www.ti.com

16.10.1 ADC Reset Control Register (ADRSTCR)
Figure 16-18 and Table 16-7 describe the ADRSTCR register.
Figure 16-18. ADC Reset Control Register (ADRSTCR) [offset = 00h]
31

1

0

Reserved

RESET

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 16-7. ADC Reset Control Register (ADRSTCR) Field Descriptions
Bit

Field

31-1

Reserved

0

RESET

502

Value
0

Description
Reads return 0. Writes have no effect.
This bit is used to reset the ADC internal state machines and control/status registers. This reset
state is held until this bit is cleared. Read in all modes, write in privileged mode.

0

Module is released from the reset state.

1

All the module's internal state machines and the control/status registers are reset.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.2 ADC Operating Mode Control Register (ADOPMODECR)
Figure 16-19 and Table 16-8 describe the ADOPMODECR register.
Figure 16-19. ADC Operating Mode Control Register (ADOPMODECR) [offset = 04h]
31

30

25

24

10_12_BIT

Reserved

COS

R/W-0

R-0

RW-1

23

21

20

17

16

Reserved

CHN_TEST_EN

RAM_TEST_EN

R-0

R/W-Ah

R/W-0

15

9

7

8

Reserved

POWERDOWN

R-0

RW-0

5

4

3

1

0

Reserved

IDLE_PWRDNReserved

ADC_EN

R-0

R/W-0

R-0

RW-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-8. ADC Operating Mode Control Register (ADOPMODECR) Field Descriptions
Bit

Field

31

10_12_BIT

Value

Description
This bit controls the resolution of the ADC core. It also affects the size of the conversion
results stored in the results’ RAM.
Any operation mode read/write:

30-25
24

Reserved

0

The ADC core and digital logic are configured to be in 10-bit resolution. This is the default
mode of operation.

1

The ADC core and digital logic are configured to be in 12-bit resolution.

0

Reads return 0. Writes have no effect.

COS

This bit affects emulation operation only. It defines whether the ADC core clock (ADCLK) is
immediately halted when the emulation system enters suspend mode or if it should continue
operating normally.
Note: If COS = 0 when the ADC module enters the emulation mode, then the accuracy ofthe conversion results can be affected depending on how long the module stays in theemulation mode.
Any operation mode read/write:

23-21

Reserved

20-17

CHN_TEST_EN

0

ADC module halts all ongoing conversions immediately after emulation mode is entered.

1

ADC module continues all ongoing conversions as per the configurations of the three
conversion groups.

0

Reads return 0. Writes have no effect.
Enable the input channels’ impedance measurement mode.
This mode is reserved for use by TI.
Any operation mode read/write:

16

5h

Input impedance measurement mode is enabled.

Ah

Input impedance measurement mode is disabled.

All othervalues

Input impedance measurement mode is disabled.

RAM_TEST_EN

Enable the ADC Results’ RAM Test Mode.
Refer to Section 16.8.2 for more details.
Any operation mode read/write:

15-9

Reserved

SPNU517C – March 2018
Submit Documentation Feedback

0

ADC RAM Test Mode is disabled. The application cannot write to the ADC RAM.

1

ADC RAM Test Mode is enabled. The application can directly write to the ADC RAM.

0

Reads return 0. Writes have no effect.
Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

503

ADC Registers

www.ti.com

Table 16-8. ADC Operating Mode Control Register (ADOPMODECR) Field Descriptions (continued)
Bit

Field

8

POWERDOWN

Value

Description
ADC Power Down. This bit powers down only the ADC core; the digital logic in thesequencer stays active. To release the core from power down mode, this bit must be
cleared. If a conversion is ongoing, the ADC module will wait until the current conversion iscompleted before powering down the ADC core.
Also refer to Section 16.10.65, ADC Power-Up Delay Control Register(ADPWRUPDLYCTRL).
Any operation mode read/write:

7-5

Reserved

4

IDLE_PWRDN0The state of the ADC core is controlled by the IDLE_PWRDN bit, or by a global power down
mode entry.

1

ADC core is in the power-down state.

0

Reads return 0. Writes have no effect.
ADC Power Down When Idle. When this bit is set, the ADC module will automatically power
down the ADC core whenever there are no conversions ongoing or pending. This is theenhanced power down mode.
Also refer to Section 16.10.65, ADC Power-Up Delay Control Register(ADPWRUPDLYCTRL).
Any operation mode read/write:

3-1

Reserved

0

ADC_EN0

The ADC stays in the normal operating mode even if no conversions are ongoing or
pending. The power down state is entered only by configuring the POWERDOWN bit or via
a global power down mode entry.

1Enhanced power down mode is enabled.

0

Reads return 0. Writes have no effect.
ADC Enable. This bit must be set to allow the ADC module to be configured to perform any
conversions.
Any operation mode read/write:0

No ADC conversions can occur. The input channel select registers: ADEVSEL, ADG1SEL,
and ADG2SEL are held at their reset values.

1

ADC conversions can now proceed as configured.

16.10.3 ADC Clock Control Register (ADCLOCKCR)
Figure 16-20 and Table 16-9 describe the ADCLOCKCR register.
Figure 16-20. ADC Clock Control Register (ADCLOCKCR) [offset = 08h]
31

5

4

0

Reserved

PS

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-9. ADC Clock Control Register (ADCLOCKCR) Field Descriptions
Bit

Field

31-5

Reserved

4-0

PS

Value
0
0-1Fh

Description
Reads return 0. Writes have no effect.
ADC Clock Prescaler. These bits define the prescaler value for the ADC core clock (ADCLK). The
ADCLK is generated by dividing down the input bus clock (VCLK) to the ADC module.
Note: The supported range for the ADC clock frequency is specified in the device datasheet. The
ADC clock prescaler must be configured to meet this datasheet specification.
Any operation mode read/write:t C(ADCLK) = t C(VCLK)× (PS + 1),
where tC(ADCLK) is the period of the ADCLK and tC(VCLK) is the period of the VCLK.

504

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.4 ADC Calibration Mode Control Register (ADCALCR)
Figure 16-21 and Table 16-10 describe the ADCALCR register.
Figure 16-21. ADC Calibration Mode Control Register (ADCALCR) [offset = 0Ch]
31

25

24

Reserved

SELF_TEST

R-0

RW-0

23

17

16

Reserved

CAL_ST

R-0

R/S-0

15

9

8

Reserved

10

BRIDGE_EN

HILO

R-0

RW-0

RW-0

7

1

0

Reserved

CAL_EN

R-0

RW-0

LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset

Table 16-10. ADC Calibration Mode Control Register (ADCALCR) Field Descriptions
Bit

Field

31-25

Reserved

24

SELF_TEST

Value
0

Description
Reads return 0. Writes have no effect.
ADC Self Test Enable. When this bit is Set, either ADREFHI or ADREFLO is connected through a
resistor to the selected input channel. The desired conversion mode is configured in the groupmode control registers. For more details on the ADC Self Test Mode, refer to Section 16.7.2.
Any operation mode read/write:

23-17

Reserved

16

CAL_ST0

ADC Self Test mode is disabled.

1

ADC Self Test mode is enabled.

0

Reads return 0. Writes have no effect.
ADC Calibration Conversion Start. Setting the CAL_ST bit while the CA_ EN bit is set starts
conversion of the selected reference voltage. The ADC module uses the sample time configured in
the Event Group sample time configuration register (ADEVSAMP) for the calibration conversion.
Any operation mode:0

Read: Calibration conversion has completed, or has not yet been started.
Write: Writing 0 to this bit has no effect.

1

Read: Calibration conversion is in progress.
Write: ADC module starts calibration conversion.

15-10

Reserved

0

Reads return 0. Writes have no effect.

9

BRIDGE_EN

Bridge Enable. When set with the HILO bit, BRIDGE_EN allows a reference voltage to beconverted in calibration mode. Table 16-2 defines the four different reference voltages that can beselected.

8

HILO

ADC Self Test mode and Calibration Mode Reference Source Selection.
In the ADC Self Test mode, this bit defines the test voltage to be combined through a resistor withthe selected input pin voltage. Refer to Section 16.7.2 for details on the ADC Self Test Mode.
In the ADC Calibration Mode, this bit defines the reference source polarity. Refer to Section 16.7.1
for details on the ADC Calibration Mode.
In the ADC module’s normal operating mode, this bit has no effect.

7-1

Reserved

SPNU517C – March 2018
Submit Documentation Feedback0

Reads return 0. Writes have no effect.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

505

ADC Registers

www.ti.com

Table 16-10. ADC Calibration Mode Control Register (ADCALCR) Field Descriptions (continued)
Bit

Field

0

CAL_EN

Value

Description
ADC Calibration Enable. When this bit is Set, the input channel multiplexor is disconnected and thecalibration reference voltage is connected to the ADC core input. The calibration reference voltage
is selected by the combination of the BRIDGE_EN and HILO. The actual conversion of thisreference voltage starts when the CAL_ST bit is set. If the CAL_ST bit is already set when the
CAL_EN bit is set, then the calibration conversion is immediately started.
Refer to Section 16.7.1 for more details on the ADC calibration mode.
Any operation mode read/write:

506

0Calibration mode is disabled.

1

Calibration mode is enabled.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.5 ADC Event Group Operating Mode Control Register (ADEVMODECR)
ADC Event Group Operating Mode Control Register (ADEVMODECR) is shown in Figure 16-22 andFigure 16-23, and described in Table 16-11. As shown, the format of the ADEVMODECR is different
based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 16-22. 12-bit ADC Event Group Operating Mode Control Register (ADEVMODECR)[offset = 10h]31

24
Reserved
R-0

23

17
Reserved
R-0

R/W-0

15

10

7

6

16
No Reset on
ChnSel98Reserved

EV_DATA_FMT

R-0

R/W-0

5

4

1

0

Reserved

EV_CHIDOVR_EV_
RAM_IGN

3
Reserved2

EV_MODE

FRZ_EV

R-0

R/W-0

R/W-0

R-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 16-23. 10-bit ADC Event Group Operating Mode Control Register (ADEVMODECR)[offset = 10h]31

24
Reserved
R-0

23

17

16

Reserved

No Reset on
ChnSel

R-0

R/W-0

15

8
Reserved
R-0

7

6

5

4

3

2

1

0

Reserved

EV_CHIDOVR_EV_
RAM_IGN

Reserved

EV_8BIT

EV_MODE

FRZ_EV

R-0

R/W-0

R/W-0

R-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

507

ADC Registers

www.ti.com

Table 16-11. ADC Event Group Operating Mode Control Register (ADEVMODECR)
Field Descriptions
Field

Value

Reserved0

No Reset on ChnSel

Description
Reads return 0. Writes have no effect.
No Event Group Results Memory Reset on New Channel Select.
This bit determines whether the event group results’ RAM is reset whenever a non-zero value is written
to the event group channel select register.
Any operation mode read/write:

0

Event group results RAM is reset when a non-zero value is written to event group channel selectregister, even if event group conversions are completed.

1

Event group results RAM is not reset when a non-zero value is written to event group channel selectregister, and event group conversions are completed.
If the event group conversions are ongoing (active or frozen), then writing a non-zero value to theevent group channel select register will always reset the event group results RAM.

EV_DATA_FMT

Event Group Read Data Format.
Note: This field is only applicable when the ADC module is configured to be a 12-bit ADC module. This
field is reserved when the module is configured as a 10-bit ADC module.
This field determines the format in which the conversion results are read out of the Event group results
RAM when using the FIFO interface, that is, when reading from the ADEVBUFFER orADEVEMUBUFFER locations.
Any operation mode read/write:
0

Conversion results are read out in full 12-bit format. This is the default mode.

1h

Conversion results are read out in 10-bit format. Bits 11-2 of the 12-bit conversion result are returned
as the 10-bit conversion result.

2hConversion results are read out in 8-bit format. Bits 11-4 of the 12-bit conversion result are returned as
the 8-bit conversion result.

3h

Reserved. The full 12-bit conversion result is returned if programmed.

EV_CHID

Enable Channel Id for the Event Group conversion results to be read. This bit only affects the “readfrom FIFO” mode. The ADC always stores the channel id in the results RAM. Any 16-bit read
performed in the “read from RAM” mode will return the 5-bit channel id along with the 10-bit conversion
result.
Any operation mode read/write:
0

Bits 14-10, the channel id field, of the data read from the Event Group results’ FIFO is read as 00000b.

1

Bits 14-10, the channel id field, of the data read from the Event Group results’ FIFO contains thenumber of the ADC analog input to which the conversion result belongs.

OVR_EV_RAM_IGN

This bit allows the ADC module to overwrite the contents of the Event Group results memory under anoverrun condition.
Any operation mode read/write:
0

The ADC cannot overwrite the contents of the Event Group results memory. When an overrun of thismemory occurs, the software needs to read out all the contents of this memory before the ADC is able
to write a new conversion result for the Event Group.

1

When an overrun of the Event Group results memory occurs, the ADC proceeds to overwrite thecontents with any new conversion results for the Event Group, starting with the first location in thismemory.

EV_8BIT

Event Group 8-bit result mode. This bit allows the Event Group conversion results to be read out in an
8-bit format. This bit only applies to the “read from FIFO” mode. The lower 2 bits of the 10-bit
conversion result are discarded and the upper 8 bits are shifted right two places to form the 8-bit
conversion result.
Note: This bit is only applicable when the ADC module is configured to be a 10-bit ADC module. Thisbit is reserved when the module is configured as a 12-bit ADC module.
Any operation mode read/write:

508

0

The Event Group conversion result is read out as a 10-bit value in the “read from Event Group FIFO”
mode.

1

The Event Group conversion result is read out as an 8-bit value in the “read from Event Group FIFO”
mode.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

Table 16-11. ADC Event Group Operating Mode Control Register (ADEVMODECR)
Field Descriptions (continued)
Field

Value

EV_MODE

Description
Event Group Conversion Mode. This bit defines whether the input channels selected for conversion in
the Event Group are converted only once per trigger, or are continuously converted.
Any operation mode read/write:0

The channels selected for conversion in the Event Group are converted only once when the selected
event trigger condition occurs.

1

The channels selected for conversion in the Event Group are converted continuously when theselected event trigger condition occurs.

FRZ_EVEvent Group Freeze Enable. This bit allows an Event Group conversion sequence to be frozen if aGroup1 or a Group2 conversion is requested. The Event Group conversion is kept frozen while theGroup1 or Group2 conversion is active, and continues from where it was frozen once the Group1 orGroup2 conversions are completed.
While the Event Group conversion is frozen, the EV_STOP status flag in the ADEVSR register
indicates that the Event Group conversions have stopped. This bit gets cleared when the Event Group
conversions resume.
Any operation mode read/write:
0

Event Group conversions cannot be frozen. All the channels selected for conversion in the Event
Group are converted before the ADC can switch over to servicing any other conversion group.

1

Event Group conversions are frozen whenever there is a request for conversion from Group1 orGroup2.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

509

ADC Registers

www.ti.com

16.10.6 ADC Group1 Operating Mode Control Register (ADG1MODECR)ADC Group1 Operating Mode Control Register (ADG1MODECR) is shown in Figure 16-24 and Figure 1625, and described in Table 16-12. As shown, the format of the ADG1MODECR is different based onwhether the ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 16-24. 12-bit ADC Group1 Operating Mode Control Register (ADG1MODECR)[offset = 14h]31

24
Reserved
R-0

23

17
Reserved
R-0

R/W-0

15

10

7

6

16
No Reset on
ChnSel98Reserved

G1_DATA_FMT

R-0

R/W-0

5

4

3

2

1

0

Reserved

G1_CHIDOVR_G1_
RAM_IGN

G1_HW_TRIG

Reserved

G1_MODE

FRZ_G1

R-0

R/W-0

R/W-0

R/W-0

R-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 16-25. 10-bit ADC Group1 Operating Mode Control Register (ADG1MODECR)[offset = 14h]31

24
Reserved
R-0

23

17

16

Reserved

No Reset on
ChnSel

R-0

R/W-0

15

8
Reserved
R-0

7

6

5

4

3

2

1

0

Reserved

G1_CHIDOVR_G1_
RAM_IGN

G1_HW_TRIG

G1_8BIT

G1_MODE

FRZ_G1

R-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

510

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

Table 16-12. ADC Group1 Operating Mode Control Register (ADG1MODECR)
Field Descriptions
Field
Reserved

Value
0

No Reset on ChnSel

Description
Reads return 0. Writes have no effect.
No Group1 Results Memory Reset on New Channel Select.
This bit determines whether the group1 results’ RAM is reset whenever a non-zero value is written to
the group1 channel select register.
Any operation mode read/write:

0Group1 results RAM is reset when a non-zero value is written to group1 channel select register, even ifgroup1 conversions are completed.

1Group1 results RAM is not reset when a non-zero value is written to group1 channel select register,and group1 conversions are completed.
If the group1 conversions are ongoing (active or frozen), then writing a nonzero value to the group1
channel select register will always reset the group1 results RAM.

G1_DATA_FMTGroup1 Read Data Format.
Note: This field is only applicable when the ADC module is configured to be a 12-bit ADC module. This
field is reserved when the module is configured as a 10-bit ADC module.
This field determines the format in which the conversion results are read out of the group1 results RAM
when using the FIFO interface, that is, when reading from the ADG1BUFFER or ADG1EMUBUFFER
locations.
Any operation mode read/write:
0

Conversion results are read out in full 12-bit format. This is the default mode.

1h

Conversion results are read out in 10-bit format. Bits 11-2 of the 12-bit conversion result are returned
as the 10-bit conversion result.

2hConversion results are read out in 8-bit format. Bits 11-4 of the 12-bit conversion result are returned as
the 8-bit conversion result.

3h

Reserved. The full 12-bit conversion result is returned if programmed.

G1_CHID

Enable Channel Id for the Group1 conversion results to be read. This bit only affects the “read from
FIFO” mode. The ADC always stores the channel id in the results RAM. Any 16-bit read performed in
the “read from RAM” mode will return the 5-bit channel id along with the 10-bit conversion result.
Any operation mode read/write:
0

Bits 14-10, the channel id field, of the data read from the Group1 results’ FIFO is read as 00000b.

1

Bits 14-10, the channel id field, of the data read from the Group1 results’ FIFO contains the number ofthe ADC analog input to which the conversion result belongs.

OVR_G1_RAM_IGN

This bit allows the ADC module to overwrite the contents of the Group1 results memory under anoverrun condition.
Any operation mode read/write:
0

The ADC cannot overwrite the contents of the Group1 results memory. When an overrun of thismemory occurs, the software needs to read out all the contents of this memory before the ADC is able
to write a new conversion result for the Group1.

1

When an overrun of the Group1 results memory occurs, the ADC proceeds to overwrite the contents
with any new conversion results for the Group1, starting with the first location in this memory.

G1_HW_TRIGGroup1 Hardware Triggered. This bit allows the Group1 to be hardware triggered. The Group1 is
software triggered by default. For more details on how to trigger a conversion group, refer to
Section 16.3.6.
Any operation mode read/write:
0

The Group1 is software-triggered. A Group1 conversion starts whenever the Group1 channel selectregister (ADG1SEL) is written with a non-zero value.

1

The Group1 is hardware-triggered. A Group1 conversion starts whenever the Group1 channel selectregister has a non-zero value, and the specified hardware trigger occurs. The hardware trigger for theGroup1 is specified in the Group1 Trigger Source register (ADG1SRC).

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

511

ADC Registers

www.ti.com

Table 16-12. ADC Group1 Operating Mode Control Register (ADG1MODECR)
Field Descriptions (continued)
Field

Value

G1_8BIT

Description
Group1 8-bit result mode.
Note: This bit is only applicable when the ADC module is configured to be a 10-bit ADC module. Thisbit is reserved when the module is configured as a 12-bit ADC moduleThis bit allows the Group1 conversion results to be read out in an 8-bit format. This bit only applies tothe “read from FIFO” mode. The lower 2 bits of the 10-bit conversion result are discarded and theupper 8 bits are shifted right two places to form the 8-bit conversion result.
Any operation mode read/write:

0

The Group1 conversion result is read out as a 10-bit value in the “read from Group1 FIFO” mode.

1

The Group1 conversion result is read out as an 8-bit value in the “read from Group1 FIFO” mode.

G1_MODEGroup1 Conversion Mode. This bit defines whether the input channels selected for conversion in theGroup1 are converted only once, or are continuously converted.
Any operation mode read/write:0

The channels selected for conversion in the Group1 are converted only once.

1

The channels selected for conversion in the Group1 are converted continuously.

FRZ_G1

Group1 Freeze Enable. This bit allows a Group1 conversion sequence to be frozen if an Event Groupor a Group2 conversion is requested. The Group1 conversion is kept frozen while the Event Group orGroup2 conversion is active, and continues from where it was frozen once the Event Group or Group2
conversions are completed.
While the Group1 conversion is frozen, the G1_STOP status flag in the ADG1SR register indicates that
the Group1 conversions have stopped. This bit gets cleared when the Group1 conversions resume.
Any operation mode read/write:

5120Group1 conversions cannot be frozen. All the channels selected for conversion in the Group1 areconverted before the ADC can switch over to servicing any other conversion group.

1

Group1 conversions are frozen whenever there is a request for conversion from Event Group orGroup2.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.7 ADC Group2 Operating Mode Control Register (ADG2MODECR)ADC Group2 Operating Mode Control Register (ADG2MODECR) is shown in Figure 16-26 and Figure 1627, described in Table 16-13. As shown, the format of the ADG2MODECR is different based on whether
the ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 16-26. 12-bit ADC Group2 Operating Mode Control Register (ADG2MODECR)[offset = 18h]31

24
Reserved
R-0

23

16
Reserved

No Reset on
ChnSel

R-0

R/W-0

15

10

7

6

9

8

Reserved

G2_DATA_FMT

R-0

R/W-0

5

4

3

2

1

0

Reserved

G2_CHIDOVR_G2_
RAM_IGN

G2_HW_TRIG

Reserved

G2_MODE

FRZ_G2

R-0

R/W-0

R/W-0

R/W-0

R-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 16-27. 10-bit ADC Group2 Operating Mode Control Register (ADG2MODECR)[offset = 18h]31

24
Reserved
R-0

23

16
Reserved

No Reset on
ChnSel

R-0

R/W-0

15

8
Reserved
R-0

7

6

5

4

3

2

1

0

Reserved

G2_CHIDOVR_G2_
RAM_IGN

G2_HW_TRIG

G2_8BIT

G2_MODE

FRZ_G2

R-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

513

ADC Registers

www.ti.com

Table 16-13. ADC Group 2 Operating Mode Control Register (ADG2MODECR)
Field Descriptions
Field

Value

Reserved0

No Reset on ChnSel

Description
Reads return 0. Writes have no effect.
No Group2 Results Memory Reset on New Channel Select.
This bit determines whether the group2 results’ RAM is reset whenever a non-zero value is written to
the group2 channel select register.
Any operation mode read/write:

0Group2 results RAM is reset when a non-zero value is written to group2 channel select register, even ifgroup2 conversions are completed.

1Group2 results RAM is not reset when a non-zero value is written to group2 channel select register,and group2 conversions are completed.
If the group2 conversions are ongoing (active or frozen), then writing a nonzero value to the group2
channel select register will always reset the group2 results RAM.

G2_DATA_FMTGroup2 Read Data Format.
Note: This field is only applicable when the ADC module is configured to be a 12-bit ADC module. This
field is reserved when the module is configured as a 10-bit ADC module.
This field determines the format in which the conversion results are read out of the group1 results RAM
when using the FIFO interface, that is, when reading from the ADG2BUFFER or ADG2EMUBUFFER
locations.
Any operation mode read/write:
0

Conversion results are read out in full 12-bit format. This is the default mode.

1h

Conversion results are read out in 10-bit format. Bits 11–2 of the 12-bit conversion result are returned
as the 10-bit conversion result.

2hConversion results are read out in 8-bit format. Bits 11–4 of the 12-bit conversion result are returned
as the 8-bit conversion result.

3h

Reserved. The full 12-bit conversion result is returned if programmed.

G2_CHID

Enable Channel Id for the Group2 conversion results to be read. This bit only affects the “read from
FIFO” mode. The ADC always stores the channel id in the results RAM. Any 16-bit read performed in
the “read from RAM” mode will return the 5-bit channel id along with the 10-bit conversion result.
Any operation mode read/write:
0

Bits 14-10, the channel id field, of the data read from the Group2 results’ FIFO is read as 00000b.

1

Bits 14-10, the channel id field, of the data read from the Group2 results’ FIFO contains the number ofthe ADC analog input to which the conversion result belongs.

OVR_G2_RAM_IGN

This bit allows the ADC module to overwrite the contents of the Group2 results memory under anoverrun condition.
Any operation mode read/write:
0

The ADC cannot overwrite the contents of the Group2 results memory. When an overrun of thismemory occurs, the software needs to read out all the contents of this memory before the ADC is able
to write a new conversion result for the Group2.

1

When an overrun of the Group2 results memory occurs, the ADC proceeds to overwrite the contents
with any new conversion results for the Group2, starting with the first location in this memory.

G2_HW_TRIGGroup2 Hardware Triggered. This bit allows the Group2 to be hardware triggered. The Group2 is
software triggered by default. For more details on how to trigger a conversion group, refer to
Section 16.3.6.
Any operation mode read/write:

514

0

The Group2 is software-triggered. A Group2 conversion starts whenever the Group2 channel selectregister (ADG2SEL) is written with a non-zero value.

1

The Group2 is hardware-triggered. A Group2 conversion starts whenever the Group2 channel selectregister has a non-zero value, and the specified hardware trigger occurs. The hardware trigger for theGroup2 is specified in the Group2 Trigger Source register (ADG2SRC).

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

Table 16-13. ADC Group 2 Operating Mode Control Register (ADG2MODECR)
Field Descriptions (continued)
Field

Value

G2_8BIT

Description
Group2 8-bit result mode.
Note: This bit is only applicable when the ADC module is configured to be a 10-bit ADC module. Thisbit is reserved when the module is configured as a 12-bit ADC module.
This bit allows the Group2 conversion results to be read out in an 8-bit format. This bit only applies tothe “read from FIFO” mode. The lower 2 bits of the 10-bit conversion result are discarded and theupper 8 bits are shifted right two places to form the 8-bit conversion result.
Any operation mode read/write:

0

The Group2 conversion result is read out as a 10-bit value in the “read from Group2 FIFO” mode.

1

The Group2 conversion result is read out as an 8-bit value in the “read from Group2 FIFO” mode.

G2_MODEGroup2 Conversion Mode. This bit defines whether the input channels selected for conversion in theGroup2 are converted only once, or are continuously converted.
Any operation mode read/write:0

The channels selected for conversion in the Group2 are converted only once.

1

The channels selected for conversion in the Group2 are converted continuously.

FRZ_G2

Group2 Freeze Enable. This bit allows a Group2 conversion sequence to be frozen if an Event Groupor a Group1 conversion is requested. The Group2 conversion is kept frozen while the Event Group orGroup1 conversion is active, and continues from where it was frozen once the Event Group or Group1
conversions are completed.
While the Group2 conversion is frozen, the G2_STOP status flag in the ADG2SR register indicates that
the Group2 conversions have stopped. This bit gets cleared when the Group2 conversions resume.
Any operation mode read/write:
0Group2 conversions cannot be frozen. All the channels selected for conversion in the Group2 areconverted before the ADC can switch over to servicing any other conversion group.

1

Group2 conversions are frozen whenever there is a request for conversion from Event Group orGroup1.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

515

ADC Registers

www.ti.com

16.10.8 ADC Event Group Trigger Source Select Register (ADEVSRC)
ADC Event Group Trigger Source Select Register (ADEVSRC) is shown in Figure 16-28 and described inTable 16-14.
Figure 16-28. ADC Event Group Trigger Source Select Register (ADEVSRC) [offset = 1Ch]
31

8
Reserved
R-0

7

4

3

Reserved

5

EV_EDG_BOTH

EV_EDG_SEL

2
EV_SRC

0

R-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-14. ADC Event Group Trigger Source Select Register (ADEVSRC) Field Descriptions
Bit

Field

31-5

Reserved

4

Value
0

EV_EDG_BOTH

Description
Reads return 0. Writes have no effect.
EV_Group Trigger Edge Polarity Select. This bit configures the event group to be triggered on bothrising and falling edge detected on the selected trigger source.
Any operation mode read/write:

30

The conversion is triggered only upon detecting an edge defined by the EV_EDGE_SEL bit.

1

The conversion is triggered upon detecting either a rising or falling edge.

EV_EDG_SEL

Event Group Trigger Edge Polarity Select. This bit determines the polarity of the transition on theselected source that triggers the Event Group conversion.
Any operation mode read/write:

2-00

A high-to-low transition on the selected source will trigger the Event Group conversion.

1

A low-to-high transition on the selected source will trigger the Event Group conversion.

EV_SRC

Event Group Trigger Source.
Any operation mode read/write:
0-7h

516

The ADC module allows a trigger source to be selected for the Event Group from up to eight
options. These options are device-specific and the device specification must be referred to identify
the actual trigger sources.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.9 ADC Group1 Trigger Source Select Register (ADG1SRC)
ADC Group1 Trigger Source Select Register (ADG1SRC) is shown in Figure 16-29 and described inTable 16-15.
Figure 16-29. ADC Group1 Trigger Source Select Register (ADG1SRC) [offset = 20h]
31

8
Reserved
R-0

7

4

3

Reserved

5

G1_EDG_BOTH

G1_EDG_SEL

2
G1_SRC

0

R-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-15. ADC Group1 Trigger Source Select Register (ADG1SRC) Field Descriptions
Bit

Field

31-5

Reserved

4

Value
0

G1_EDG_BOTH

Description
Reads return 0. Writes have no effect.
Group1 Trigger Edge Polarity Select. This bit configures the group1 to be triggered on both risingand falling edge detected on the selected trigger source.
Any operation mode read/write:

30

The conversion is triggered only upon detecting an edge defined by the G1_EDGE_SEL bit.

1

The conversion is triggered upon detecting either a rising or falling edge.

G1_EDG_SEL

Group1 Trigger Edge Polarity Select. This bit determines the polarity of the transition on theselected source that triggers the Group1 conversion.
Any operation mode read/write:

2-00

A high-to-low transition on the selected source will trigger the Group1 conversion.

1

A low-to-high transition on the selected source will trigger the Group1 conversion.

G1_SRCGroup1 Trigger Source.
Any operation mode read/write:
0-7h

SPNU517C – March 2018
Submit Documentation Feedback

The ADC module allows a trigger source to be selected for the Group1 from up to eight options.
These options are device-specific and the device specification must be referred to identify theactual trigger sources.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

517

ADC Registers

www.ti.com

16.10.10 ADC Group2 Trigger Source Select Register (ADG2SRC)ADC Group2 Trigger Source Select Register (ADG2SRC) is shown in Figure 16-30 and described inTable 16-16.
Figure 16-30. ADC Group2 Trigger Source Select Register (ADG2SRC) [offset = 24h]31

8Reserved
R-0

7

4

3

Reserved

5

G2_EDG_BOTH

G2_EDG_SEL

2
G2_SRC

0

R-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-16. ADC Group2 Trigger Source Select Register (ADG2SRC) Field Descriptions
Bit

Field

31-5

Reserved

4

Value
0

G2_EDG_BOTH

Description
Reads return 0. Writes have no effect.
Group2 Trigger Edge Polarity Select. This bit configures the group2 to be triggered on both risingand falling edge detected on the selected trigger source.
Any operation mode read/write:

30

The conversion is triggered only upon detecting an edge defined by the G2_EDGE_SEL bit.

1

The conversion is triggered upon detecting either a rising or falling edge.

G2_EDG_SEL

Group2 Trigger Edge Polarity Select. This bit determines the polarity of the transition on theselected source that triggers the Group2 conversion.
Any operation mode read/write:

2-00

A high-to-low transition on the selected source will trigger the Group2 conversion.

1

A low-to-high transition on the selected source will trigger the Group2 conversion.

G2_SRCGroup2 Trigger Source.
Any operation mode read/write:
0-7h

518

The ADC module allows a trigger source to be selected for the Group2 from up to eight options.
These options are device-specific and the device specification must be referred to identify theactual trigger sources.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.11 ADC Event Interrupt Enable Control Register (ADEVINTENA)ADC Event Group Interrupt Enable Control Register (ADEVINTENA) is shown in Figure 16-31 anddescribed in Table 16-17.
Figure 16-31. ADC Event Group Interrupt Enable Control Register (ADEVINTENA) [offset = 28h]31

8Reserved
7

4

3

2

1

0

Reserved

EV_END_
INT_EN

Reserved

EV_OVR_
INT_EN

EV_THR_
INT_EN

R-0

R/W-0

R-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-17. ADC Event Group Interrupt Enable Control Register (ADEVINTENA) Field Descriptions
Bit

Field

31-4

Reserved

3

Value
0

EV_END_INT_EN

Description
Reads return 0. Writes have no effect.
Event Group Conversion End Interrupt Enable. Refer to Section 16.5.1 for more details on theconversion end interrupts.
Any operation mode read/write:

2

Reserved

1

EV_OVR_INT_EN

0

No interrupt is generated when conversion of all the channels selected for conversion in the
Event Group is done.

1

An Event Group conversion end interrupt is generated when conversion of all the channels
selected for conversion in the Event Group is done.

0

Reads return 0. Writes have no effect.
Event Group Memory Overrun Interrupt Enable. A memory overrun occurs when the ADC tries
to write a new conversion result to the Event Group results memory that is already full. For
more details on the overrun interrupts, refer to Section 16.5.3.
Any operation mode read/write:00

No interrupt is generated if an Event Group memory overrun occurs.

1

An Event Group memory overrun interrupt is generated if an Event Group memory overrun
condition occurs.

EV_THR_INT_EN

Event Group Threshold Interrupt Enable. An Event Group threshold interrupt occurs when the
programmed Event Group threshold counter counts down to zero. Refer to Section 16.5.2 formore details.
Any operation mode read/write:

SPNU517C – March 2018
Submit Documentation Feedback0

No interrupt is generated if the Event Group threshold counter reaches zero.

1

An Event Group threshold interrupt is generated if the Event Group threshold counter reaches
zero.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

519

ADC Registers

www.ti.com

16.10.12 ADC Group1 Interrupt Enable Control Register (ADG1INTENA)ADC Group1 Interrupt Enable Control Register (ADG1INTENA) is shown in Figure 16-32 and described inTable 16-18.
Figure 16-32. ADC Group1 Interrupt Enable Control Register (ADG1INTENA) [offset = 2Ch]
31

8
Reserved
R-0
7

3

2

1

0

Reserved

4

G1_END_
INT_EN

Reserved

G1_OVR_
INT_EN

G1_THR_
INT_EN

R-0

R/W-0

R-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-18. ADC Group1 Interrupt Enable Control Register (ADG1INTENA) Field Descriptions
Bit

Field

31-4

Reserved

3

Value
0

G1_END_INT_EN

Description
Reads return 0. Writes have no effect.
Group1 Conversion End Interrupt Enable. Refer to Section 16.5.1 for more details on theconversion end interrupts.
Any operation mode read/write:

2

Reserved

1

G1_OVR_INT_EN

0

No interrupt is generated when conversion of all the channels selected for conversion in theGroup1 is done.

1

A Group1 conversion end interrupt is generated when conversion of all the channels selected
for conversion in the Group1 is done.

0

Reads return 0. Writes have no effect.
Group1 Memory Overrun Interrupt Enable. A memory overrun occurs when the ADC tries towrite a new conversion result to the Group1 results memory that is already full. For more details
on the overrun interrupts, refer to Section 16.5.3.
Any operation mode read/write:00

No interrupt is generated if a Group1 memory overrun occurs.

1

A Group1 memory overrun interrupt is generated if a Group1 memory overrun condition occurs.

G1_THR_INT_EN

Group1 Threshold Interrupt Enable. A Group1 threshold interrupt occurs when the programmed
Group1 threshold counter counts down to zero. Refer to Section 16.5.2 for more details.
Any operation mode read/write:

520

0

No interrupt is generated if the Group1 threshold counter reaches zero.

1

A Group1 threshold interrupt is generated if the Group1 threshold counter reaches zero.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.13 ADC Group2 Interrupt Enable Control Register (ADG2INTENA)ADC Group2 Interrupt Enable Control Register (ADG2INTENA) is shown in Figure 16-33 and described inTable 16-19.
Figure 16-33. ADC Group2 Interrupt Enable Control Register (ADG2INTENA) [offset = 30h]
31

8Reserved
R-0
7

3

2

1

0

Reserved

4

G2_END_
INT_EN

Reserved

G2_OVR_
INT_EN

G2_THR_
INT_EN

R-0

R/W-0

R-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-19. ADC Group2 Interrupt Enable Control Register (ADG2INTENA) Field Descriptions
Bit

Field

31-4

Reserved

3

Value
0

G2_END_INT_EN

Description
Reads return 0. Writes have no effect.
Group2 Conversion End Interrupt Enable. Refer to Section 16.5.1 for more details on theconversion end interrupts.
Any operation mode read/write:

2

Reserved

1G2_OVR_INT_EN

0

No interrupt is generated when conversion of all the channels selected for conversion in theGroup2 is done.

1

A Group2 conversion end interrupt is generated when conversion of all the channels selected
for conversion in the Group2 is done.

0

Reads return 0. Writes have no effect.
Group2 Memory Overrun Interrupt Enable. A memory overrun occurs when the ADC tries towrite a new conversion result to the Group2 results memory that is already full. For more details
on the overrun interrupts, refer to Section 16.5.3.
Any operation mode read/write:00

No interrupt is generated if a Group2 memory overrun occurs.

1

A Group2 memory overrun interrupt is generated if a Group2 memory overrun condition occurs.

G2_THR_INT_EN

Group2 Threshold Interrupt Enable. A Group2 threshold interrupt occurs when the programmed
Group2 threshold counter counts down to zero. Refer to Section 16.5.2 for more details.
Any operation mode read/write:

SPNU517C – March 2018
Submit Documentation Feedback0

No interrupt is generated if the Group2 threshold counter reaches zero.

1

A Group2 threshold interrupt is generated if the Group2 threshold counter reaches zero.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

521

ADC Registers

www.ti.com

16.10.14 ADC Event Group Interrupt Flag Register (ADEVINTFLG)
ADC Event Group Interrupt Enable Control Register (ADEVINTENA) is shown in Figure 16-34 anddescribed in Table 16-20.
Figure 16-34. ADC Event Group Interrupt Flag Register (ADEVINTFLG) [offset = 34h]
31

8
Reserved
R-0
7

3

2

1

0

Reserved

4

EV_END

EV_MEM_
EMPTY

EV_MEM_
OVERRUN

EV_THR_
INT_FLG

R-0

R/W1C-0

R-1

R-0

R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset

Table 16-20. ADC Event Group Interrupt Flag Register (ADEVINTFLG) Field Descriptions
Bit

Field

31-4

Reserved

3

EV_END

Value
0

Description
Reads return 0. Writes have no effect.
Event Group Conversion End. This bit will be set only if the Event Group conversions are
configured to be in the single-conversion mode.
Any operation mode read:0

All the channels selected for conversion in the Event Group have not yet been converted.

1

All the channels selected for conversion in the Event Group have been converted. An Event
Group conversion end interrupt is generated, if enabled, when this bit gets set.
This bit can be cleared by any one of the following ways:• By writing a 1 to this bit• By writing a 1 to the Event Group status register bit 0 (EV_END)• By reading one conversion result from the Event Group results’ memory in the “read from
FIFO” mode
• By writing a new set of channels to the Event Group channel select register2

EV_MEM_EMPTY

Event Group Results Memory Empty. This is a read-only bit; writes have no effect. It is not asource of an interrupt from the ADC module.
Any operation mode read:

1

0

The Event Group results memory is not empty.

1

The Event Group results memory is empty.

EV_MEM_OVERRUN

Event Group Memory Overrun. This is a read-only bit; writes have no effect.
Any operation mode read:00

Event Group results memory has not overrun.

1

Event Group results memory has overrun.

EV_THR_INT_FLG

Event Group Threshold Interrupt Flag.
Any operation mode read:0

The number of conversions completed for the Event Group is smaller than the thresholdprogrammed in the Event Group interrupt threshold register.

1

The number of conversions completed for the Event Group is equal to or greater than thethreshold programmed in the Event Group interrupt threshold register.
This bit can be cleared by writing a 1; writing a 0 has no effect.

522

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.15 ADC Group1 Interrupt Flag Register (ADG1INTFLG)
ADC Group1 Interrupt Flag Register (ADG1INTFLG) is shown in Figure 16-35 and described inTable 16-21.
Figure 16-35. ADC Group1 Interrupt Flag Register (ADG1INTFLG) [offset = 38h]
31

8
Reserved
R-0
7

3

2

1

0

Reserved

4

G1_END

G1_MEM_
EMPTY

G1_MEM_
OVERRUN

G1_THR_
INT_FLG

R-0

R/W1C-0

R-1

R-0

R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset

Table 16-21. ADC Group1 Interrupt Flag Register (ADG1INTFLG) Field Descriptions
Bit

Field

31-4

Reserved

3

G1_END

Value
0

Description
Reads return 0. Writes have no effect.
Group1 Conversion End. This bit will be set only if the Group1 conversions are configured to bein the single-conversion mode.
Any operation mode read:0

All the channels selected for conversion in the Group1 have not yet been converted.

1

All the channels selected for conversion in the Group1 have been converted. A Group1
conversion end interrupt is generated, if enabled, when this bit gets set.
This bit can be cleared by any one of the following ways:• By writing a 1 to this bit• By writing a 1 to the Group1 status register bit 0 (G1_END)• By reading one conversion result from the Group1 results’ memory in the “read from FIFO”
mode• By writing a new set of channels to the Group1 channel select register2

G1_MEM_EMPTYGroup1 Results Memory Empty. This is a read-only bit; writes have no effect. It is not a sourceof an interrupt from the ADC module.
Any operation mode read:

1

0

The Group1 results memory is not empty.

1

The Group1 results memory is empty.

G1_MEM_OVERRUNGroup1 Memory Overrun. This is a read-only bit; writes have no effect.
Any operation mode read:00Group1 results memory has not overrun.

1

Group1 results memory has overrun.

G1_THR_INT_FLG

Group1 Threshold Interrupt Flag.
Any operation mode read:0

The number of conversions completed for the Group1 is smaller than the thresholdprogrammed in the Group1 interrupt threshold register.

1

The number of conversions completed for the Group1 is equal to or greater than the thresholdprogrammed in the Group1 interrupt threshold register.
This bit can be cleared by writing a 1; writing a 0 has no effect.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

523

ADC Registers

www.ti.com

16.10.16 ADC Group2 Interrupt Flag Register (ADG2INTFLG)
ADC Group2 Interrupt Flag Register (ADG2INTFLG) is shown in Figure 16-36 and described inTable 16-22.
Figure 16-36. ADC Group2 Interrupt Flag Register (ADG2INTFLG) [offset = 3Ch]
31

8
Reserved
R-0
7

3

2

1

0

Reserved

4

G2_END

G2_MEM_
EMPTY

G2_MEM_
OVERRUN

G2_THR_
INT_FLG

R-0

R/W1C-0

R-1

R-0

R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset

Table 16-22. ADC Group2 Interrupt Flag Register (ADG2INTFLG) Field Descriptions
Bit

Field

31-4

Reserved

3

G2_END

Value
0

Description
Reads return 0. Writes have no effect.
Group2 Conversion End. This bit will be set only if the Group2 conversions are configured to bein the single-conversion mode.
Any operation mode read:0

All the channels selected for conversion in the Group2 have not yet been converted.

1

All the channels selected for conversion in the Group2 have been converted. A Group2
conversion end interrupt is generated, if enabled, when this bit gets set.
This bit can be cleared by any one of the following ways:• By writing a 1 to this bit• By writing a 1 to the Group2 status register bit 0 (G2_END)• By reading one conversion result from the Group2 results’ memory in the “read from FIFO”
mode• By writing a new set of channels to the Group2 channel select register

2

G2_MEM_EMPTYGroup2 Results Memory Empty. This is a read-only bit; writes have no effect. It is not a sourceof an interrupt from the ADC module.
Any operation mode read:

1

0

The Group2 results memory is not empty.

1

The Group2 results memory is empty.

G2_MEM_OVERRUNGroup2 Memory Overrun. This is a read-only bit; writes have no effect.
Any operation mode read:00Group2 results memory has not overrun.

1

Group2 results memory has overrun.

G2_THR_INT_FLG

Group2 Threshold Interrupt Flag.
Any operation mode read:0

The number of conversions completed for the Group2 is smaller than the thresholdprogrammed in the Group2 interrupt threshold register.

1

The number of conversions completed for the Group2 is equal to or greater than the thresholdprogrammed in the Group2 interrupt threshold register.
This bit can be cleared by writing a 1; writing a 0 has no effect.

524

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.17 ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR)ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) is shown in Figure 16-37 anddescribed in Table 16-23.
Figure 16-37. ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR)[offset = 40h]
31

16

15

9

8

0

Reserved

Sign Extension

EV_THR

R-0

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-23. ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR)
Field Descriptions
Bit

Field

31-16

Reserved

Value

15-9

Sign Extension

These bits always read the same as the bit 8 of this register.

8-0

EV_THR

Event Group Threshold Counter.

0

Description
Reads return 0. Writes have no effect.

Before ADC conversions begin on the Event Group, this field is initialized to the number ofconversion results that the Event Group memory should contain before interrupting the CPU. Thiscounter decrements when the ADC module writes a new conversion result to the Event Group
results’ memory. The counter increments for each read of a conversion result from the Event Group
results’ memory in the “read from FIFO” mode. The threshold counter is not affected for a direct
read from the Event Group results’ memory. Also, a simultaneous ADC write and a CPU read fromthe Event Group FIFO will leave the threshold counter unchanged. In case of an Event Group
Results’ memory overrun condition, if new conversion results are not allowed to overwrite theexisting memory contents, then the Event Group threshold counter is not decremented.
Refer to Section 16.5.2 for more details on the threshold interrupts.

16.10.18 ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR)ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR) is shown in Figure 16-38 anddescribed in Table 16-24.
Figure 16-38. ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR) [offset = 44h]
31

16

15

9

8

0

Reserved

Sign Extension

G1_THR

R-0

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-24. ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR)
Field Descriptions
Bit

Field

31-16

Reserved

Value

15-9

Sign Extension

These bits always read the same as the bit 8 of this register.

8-0

G1_THR

Group1 Threshold Counter.

0

Description
Reads return 0. Writes have no effect.

Before ADC conversions begin on the Group1, this field is initialized to the number of conversion
results that the Group1 memory should contain before interrupting the CPU. This counter
decrements when the ADC module writes a new conversion result to the Group1 results’ memory.
The counter increments for each read of a conversion result from the Group1 results’ memory in the“read from FIFO” mode. The threshold counter is not affected for a direct read from the group1
results’ memory. Also, a simultaneous ADC write and a CPU read from the Group1 FIFO will leave
the threshold counter unchanged. In case of an Group1 Results’ memory overrun condition, if newconversion results are not allowed to overwrite the existing memory contents, then the Group1
threshold counter is not decremented.
Refer to Section 16.5.2 for more details on the threshold interrupts.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

525

ADC Registers

www.ti.com

16.10.19 ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR)
The ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) is shown in Figure 16-39 anddescribed in Table 16-25.
Figure 16-39. ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) [offset = 48h]
31

16

15

9

8

0

Reserved

Sign Extension

G2_THR

R-0

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-25. ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR)
Field Descriptions
Bit

Field

31-16

Reserved

Value

15-9

Sign Extension

These bits always read the same as the bit 8 of this register.

8-0

G2_THR

Group2 Threshold Counter.

0

Description
Reads return 0. Writes have no effect.

Before ADC conversions begin on the Group2, this field is initialized to the number of conversion
results that the Group2 memory should contain before interrupting the CPU. This counter
decrements when the ADC module writes a new conversion result to the Group2 results’ memory.
The counter increments for each read of a conversion result from the Group2 results’ memory in the“read from FIFO” mode. The threshold counter is not affected for a direct read from the group2
results’ memory. Also, a simultaneous ADC write and a CPU read from the Group2 FIFO will leave
the threshold counter unchanged. In case of an Group2 Results’ memory overrun condition, if newconversion results are not allowed to overwrite the existing memory contents, then the Group2
threshold counter is not decremented.
Refer to Section 16.5.2 for more details on the threshold interrupts.

526

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.20 ADC Results Memory Configuration Register (ADBNDCR)ADC Results Memory Configuration Register (ADBNDCR) is shown in Figure 16-40 and described inTable 16-26.
Refer to Section 16.3.8 for further details on how the conversion results are stored in the ADC results’RAM.
Figure 16-40. ADC Results Memory Configuration Register (ADBNDCR) [offset = 58h]
31

25

24

16

Reserved

BNDA

R-0

R/W-0

15

9

8

0

Reserved

BNDB

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-26. ADC Results Memory Configuration Register (ADBNDCR) Field Descriptions
Bit

Field

31-25

Reserved

24-16

BNDA

Value
0

Description
Reads return 0. Writes have no effect.
Buffer Boundary A. These bits determine the memory available for the Event Group conversion
results. The memory available is specified in terms of pairs of result buffers.
Any operation mode read/write:

15-9

Reserved

8-0

BNDB

0

Event Group conversions are not required. If Event Group conversions are performed with the
BNDA value of zero, then the Event Group memory size will default to 1024 words. For proper
usage of the ADC results memory, configure the BNDA value to be non-zero and lower than the
BNDB value.

0-1FFhA total of (2 × BNDA) buffers are available in the ADC results memory for storing Event Group
conversion results.

0

Reads return 0. Writes have no effect.
Buffer Boundary B. These bits specify the number of buffers allocated for the Event Group plus
the number of buffers allocated for the Group1. The number of buffer pairs allocated for storing
Group1 conversion results can be determined by subtracting BNDA from BNDB. As a result,
BNDB must always be specified as greater than or equal to BNDA.
Any operation mode read/write:

00-1FFhSPNU517C – March 2018
Submit Documentation Feedback

Event Group as well as Group1 conversions are not required.
A total of 2 × (BNDB - BNDA) buffers are available in the ADC results memory for storing
Group1 conversion results.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

527

ADC Registers

www.ti.com

16.10.21 ADC Results Memory Size Configuration Register (ADBNDEND)
ADC Results Memory Size Configuration Register (ADBNDEND) is shown in Figure 16-41 and describedin Table 16-27.
Figure 16-41. ADC Results Memory Size Configuration Register (ADBNDEND) [offset = 5Ch]
31

17

16

Reserved

BUF_INIT_ACTIVE

R-0

R-0

15

3

2

0

Reserved

BNDEND

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-27. ADC Results Memory Size Configuration Register (ADBNDEND) Field Descriptions
Bit

Field

31-17

Reserved

16

Value
0

BUF_INIT_ACTIVE

Description
Reads return 0. Writes have no effect.
ADC Results Memory Auto-initialization Status.
Any operation mode read/write:

15-3

Reserved

2-0

BNDEND0

ADC Results Memory is currently not being initialized, and the ADC is available. If this bit isread as 0 after triggering an auto-initialization of the ADC results memory, then the ADC results
memory has been completely initialized to zeros. For devices requiring parity checking on the
ADC results memory, the parity bit in the results memory will also be initialized according to theparity polarity. The parity polarity as well as the auto-initialization process is controlled by the
System module. Refer to Chapter 2 for more details.

1

ADC results memory is being initialized, and the ADC is not available for conversion.

0

Reads return 0. Writes have no effect.
Buffer Boundary End. These bits specify the total number of memory buffers available forstoring the ADC conversion results. These bits should be programmed to match the number of
ADC conversion result buffers required to be used for the application.
Any operation mode read/write:

0

16 words available for storing ADC conversion results.

1h

32 words available for storing ADC conversion results.

2h

64 words available for storing ADC conversion results. This is the maximum configuration since
the ADC is 64 words total.

4h-7h

528

Reserved. These combinations must not be used.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.22 ADC Event Group Sampling Time Configuration Register (ADEVSAMP)ADC Event Group Sampling Time Configuration Register (ADEVSAMP) is shown in Figure 16-42 anddescribed in Table 16-28.
Figure 16-42. ADC Event Group Sampling Time Configuration Register (ADEVSAMP) [offset = 60h]
31

12

11

0

Reserved

EV_ACQ

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-28. ADC Event Group Sampling Time Configuration Register (ADEVSAMP)
Field Descriptions
Bit

Field

31-12

Reserved

11-0

EV_ACQ

Value
0

Description
Reads return 0. Writes have no effect.
Event Group Acquisition Time. These bits define the sampling window (SW) for the Event Group
conversions.
SW = EV_ACQ + 2 in terms of ADCLK cycles.
There are two factors that determine the minimum sampling window value required:First, the ADC module design requires that SW >= 3 ADCLK cycles.
Second, the ADC input impedance necessitates a certain minimum sampling time. This needs to beguaranteed by configuring the EV_ACQ value properly considering the frequency of the ADCLK
signal. Refer to the device datasheet to determine the minimum sampling time for this device.

16.10.23 ADC Group1 Sampling Time Configuration Register (ADG1SAMP)ADC Group1 Sampling Time Configuration Register (ADG1SAMP) is shown in Figure 16-43 anddescribed in Table 16-29.
Figure 16-43. ADC Group1 Sampling Time Configuration Register (ADG1SAMP) [offset = 64h]
31

12

11

0

Reserved

G1_ACQ

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-29. ADC Group1 Sampling Time Configuration Register (ADG1SAMP)
Field Descriptions
Bit

Field

31-12

Reserved

11-0

G1_ACQ

Value
0

Description
Reads return 0. Writes have no effect.
Group1 Acquisition Time. These bits define the sampling window (SW) for the Group1 conversions.
SW = G1_ACQ + 2 in terms of ADCLK cycles.
There are two factors that determine the minimum sampling window value required:First, the ADC module design requires that SW >= 3 ADCLK cycles.
Second, the ADC input impedance necessitates a certain minimum sampling time. This needs to beguaranteed by configuring the G1_ACQ value properly considering the frequency of the ADCLK
signal. Refer to the device datasheet to determine the minimum sampling time for this device.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

529

ADC Registers

www.ti.com

16.10.24 ADC Group2 Sampling Time Configuration Register (ADG2SAMP)ADC Group2 Sampling Time Configuration Register (ADG2SAMP) is shown in Figure 16-44 anddescribed in Table 16-30.
Figure 16-44. ADC Group2 Sampling Time Configuration Register (ADG2SAMP) [offset = 68h]
31

12

11

0

Reserved

G2_ACQ

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-30. ADC Group2 Sampling Time Configuration Register (ADG2SAMP)
Field Descriptions
Bit

Field

31-12

Reserved

11-0

G2_ACQ

Value
0

Description
Reads return 0. Writes have no effect.
Group2 Acquisition Time. These bits define the sampling window (SW) for the Group2 conversions.
SW = G2_ACQ + 2 in terms of ADCLK cycles.
There are two factors that determine the minimum sampling window value required:First, the ADC module design requires that SW >= 3 ADCLK cycles.
Second, the ADC input impedance necessitates a certain minimum sampling time. This needs to beguaranteed by configuring the G2_ACQ value properly considering the frequency of the ADCLK
signal. Refer to the device datasheet to determine the minimum sampling time for this device.

530

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.25 ADC Event Group Status Register (ADEVSR)ADC Event Group Status Register (ADEVSR) is shown in Figure 16-45 and described in Table 16-31.
Figure 16-45. ADC Event Group Status Register (ADEVSR) [offset = 6Ch]
31

8
Reserved
R-0

7

3

2

1

0

Reserved

4

EV_MEM_
EMPTY

EV_BUSY

EV_STOP

EV_END

R-0

R-1

R-0

R-0

R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset

Table 16-31. ADC Event Group Status Register (ADEVSR) Field Descriptions
Bit

Field

31-4

Reserved

3

Value
0

EV_MEM_EMPTY

Description
Reads return 0. Writes have no effect.
Event Group Results Memory Empty. This bit can be effectively used only when the conversion
results are read out of the Event Group results memory in the "read from FIFO" mode.
Any operation mode read:

2

0

The Event Group results memory has valid conversion results.

1

The Event Group results memory is empty, or does not contain any unread conversion results.

EV_BUSY

Event Group Conversion Busy.
Any operation mode read:

10

Event Group conversions are neither in progress nor frozen.

1

Event Group conversions are either in progress, or are frozen for servicing some other group.
This bit will always be set when the Event Group is configured to be in the continuous
conversion mode.

EV_STOP

Event Group Conversion Stopped.
Any operation mode read:00

Event Group conversions are not currently frozen.

1

Event Group conversions are currently frozen.

EV_END

Event Group Conversions Ended.
Any operation mode read:0

Event Group conversions have either not been started or have not yet completed since the lasttime this status bit was cleared.

1

The conversion for all the channels selected in the Event Group has completed. This bit can becleared under the following conditions:• By reading a conversion result from the Event Group results memory in the "read from FIFO"
mode.
• By writing a new value to the Event Group channel select register ADEVSEL.
• By writing a 1 to this bit.
• By disabling the ADC module by clearing the ADC_EN bit in the ADC operating mode control
register (ADOPMODECR).

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

531

ADC Registers

www.ti.com

16.10.26 ADC Group1 Status Register (ADG1SR)
ADC Group1 Status Register (ADG1SR) is shown in Figure 16-46 and described in Table 16-32.
Figure 16-46. ADC Group1 Status Register (ADG1SR) [offset = 70h]
31

8Reserved
R-0

7

3

2

1

0

Reserved

4

G1_MEM_
EMPTY

G1_BUSY

G1_STOP

G1_END

R-0

R-1

R-0

R-0

R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset

Table 16-32. ADC Group1 Status Register (ADG1SR) Field Descriptions
Bit

Field

31-4

Reserved

3

Value
0

G1_MEM_EMPTY

Description
Reads return 0. Writes have no effect.
Group1 Results Memory Empty. This bit can be effectively used only when the conversion
results are read out of the Group1 results memory in the "read from FIFO" mode.
Any operation mode read:

20

The Group1 results memory has valid conversion results.

1

The Group1 results memory is empty, or does not contain any unread conversion results.

G1_BUSY

Group1 Conversion Busy.
Any operation mode read:10Group1 conversions are neither in progress nor frozen.

1Group1 conversions are either in progress, or are frozen for servicing some other group. Thisbit will always be set when the Group1 is configured to be in the continuous conversion mode.

G1_STOPGroup1 Conversion Stopped.
Any operation mode read:00Group1 conversions are not currently frozen.

1Group1 conversions are currently frozen.

G1_ENDGroup1 Conversions Ended.
Any operation mode read:0Group1 conversions have either not been started or have not yet completed since the last time
this status bit was cleared.

1

The conversion for all the channels selected in the Group1 has completed. This bit can becleared under the following conditions:• By reading a conversion result from the Group1 results memory in the "read from FIFO"
mode.
• By writing a new value to the Group1 channel select register ADG1SEL.
• By writing a 1 to this bit.
• By disabling the ADC module by clearing the ADC_EN bit in the ADC operating mode control
register (ADOPMODECR).

532

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.27 ADC Group2 Status Register (ADG2SR)ADC Group2 Status Register (ADG2SR) is shown in Figure 16-47 and described in Table 16-33.
Figure 16-47. ADC Group2 Status Register (ADG2SR) [offset = 74h]31

8Reserved
R-0

7

3

2

1

0

Reserved

4

G2_MEM_
EMPTY

G2_BUSY

G2_STOP

G2_END

R-0

R-1

R-0

R-0

R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset

Table 16-33. ADC Group2 Status Register (ADG2SR) Field Descriptions
Bit

Field

31-4

Reserved

3

Value
0

G2_MEM_EMPTY

Description
Reads return 0. Writes have no effect.
Group2 Results Memory Empty. This bit can be effectively used only when the conversion
results are read out of the Group2 results memory in the "read from FIFO" mode.
Any operation mode read:

20

The Group2 results memory has valid conversion results.

1

The Group2 results memory is empty, or does not contain any unread conversion results.

G2_BUSY

Group2 Conversion Busy.
Any operation mode read:10Group2 conversions are neither in progress nor frozen.

1Group2 conversions are either in progress, or are frozen for servicing some other group. Thisbit will always be set when the Group2 is configured to be in the continuous conversion mode.

G2_STOPGroup2 Conversion Stopped.
Any operation mode read:00Group2 conversions are not currently frozen.

1Group2 conversions are currently frozen.

G2_ENDGroup2 Conversions Ended.
Any operation mode read:0Group2 conversions have either not been started or have not yet completed since the last time
this status bit was cleared.

1

The conversion for all the channels selected in the Group2 has completed. This bit can becleared under the following conditions:• By reading a conversion result from the Group2 results memory in the "read from FIFO"
mode.
• By writing a new value to the Group2 channel select register ADG2SEL.
• By writing a 1 to this bit.
• By disabling the ADC module by clearing the ADC_EN bit in the ADC operating mode control
register (ADOPMODECR).

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

533

ADC Registers

www.ti.com

16.10.28 ADC Event Group Channel Select Register (ADEVSEL)ADC Event Group Channel Select Register (ADEVSEL) is shown in Figure 16-48 and described inTable 16-34.
NOTE: Clearing ADEVSEL During a Conversion
Writing 0000h to ADEVSEL stops the Event Group conversions. This does not cause the
ADC Event Group results Memory pointer or the Event Group Threshold Register to bereset.

NOTE: Writing A Non-Zero Value To ADEVSEL During a Conversion
Writing a new value to ADEVSEL while a Channel in Event Group is being converted results
in a new conversion sequence starting immediately with the highest priority channel in the
new ADEVSEL selection. This also causes the ADC Event Group Results Memory pointer tobe reset so that the memory allocated for storing the Event Group conversion results gets
overwritten. Care should be taken to re-program the corresponding Interrupt Threshold
Counter again so that correct number of conversions happen before a Threshold interrupt isgenerated.

Figure 16-48. ADC Event Group Channel Select Register (ADEVSEL) [offset = 78h]
31

16

15

0

Reserved

EV_SEL

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-34. ADC Event Group Channel Select Register (ADEVSEL) Field Descriptions
Bit

Field

31-16

Reserved

15-0

EV_SEL

Value
0

Description
Reads return 0. Writes have no effect.
Event Group channels selected.
Any operation mode read/write:

0
Non-zero534

No ADC input channel is selected for conversion in the Event Group.
The channels marked by the bit positions that are set to 1 will be converted in ascendingorder when the Event Group is triggered.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.29 ADC Group1 Channel Select Register (ADG1SEL)ADC Group1 Channel Select Register (ADG1SEL) is shown in Figure 16-49 and described in Table 16-35.
NOTE: Clearing ADG1SEL During a Conversion
Writing 0000h to ADG1SEL stops the Group1 conversions. This does not cause the ADC
Group1 Results Memory pointer or the Group1 Threshold Register to be reset.

NOTE: Writing A Non-Zero Value To ADG1SEL During a Conversion
Writing a new value to ADG1SEL while a Channel in Group1 is being converted results in a
new conversion sequence starting immediately with the highest priority channel in the new
ADG1SEL selection. This also causes the ADC Group1 Results Memory pointer to be reset
so that the memory allocated for storing the Group1 conversion results gets overwritten.
Care should be taken to re-program the corresponding Interrupt Threshold Counter again sothat the correct number of conversions happen before a Threshold interrupt is generated.

Figure 16-49. ADC Group1 Channel Select Register (ADG1SEL) [offset = 7Ch]
31

16

15

0

Reserved

G1_SEL

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-35. ADC Group1 Channel Select Register (ADG1SEL) Field Descriptions
Bit

Field

31-16

Reserved

15-0

G1_SEL

Value
0

Description
Reads return 0. Writes have no effect.
Group1 channels selected.
Any operation mode read/write:

0
Non-zeroSPNU517C – March 2018
Submit Documentation Feedback

No ADC input channel is selected for conversion in the Group1.
The channels marked by the bit positions that are set to 1 will be converted in ascendingorder when the Group1 is triggered.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

535

ADC Registers

www.ti.com

16.10.30 ADC Group2 Channel Select Register (ADG2SEL)ADC Group2 Channel Select Register (ADG2SEL) is shown in Figure 16-50 and described in Table 16-36.
NOTE: Clearing ADG2SEL During a Conversion
Writing 0000h to ADG2SEL stops the Group2 conversions. This does not cause the ADC
Group2 Results Memory pointer or the Group2 Threshold Register to be reset.

NOTE: Writing A Non-Zero Value To ADG2SEL During a Conversion
Writing a new value to ADG2SEL while a Channel in Group2 is being converted results in a
new conversion sequence starting immediately with the highest priority channel in the new
ADG2SEL selection. This also causes the ADC Group2 Results Memory pointer to be reset
so that the memory allocated for storing the Group2 conversion results gets overwritten.
Care should be taken to re-program the corresponding Interrupt Threshold Counter again sothat correct number of conversions happen before a Threshold interrupt is generated.

Figure 16-50. ADC Group2 Channel Select Register (ADG2SEL) [offset = 80h]
31

16

15

0

Reserved

G2_SEL

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-36. ADC Group2 Channel Select Register (ADG2SEL) Field Descriptions
Bit

Field

31-16

Reserved

15-0

G2_SEL

Value
0

Description
Reads return 0. Writes have no effect.
Group2 channels selected.
Any operation mode read/write:

0
Non-zero536

No ADC input channel is selected for conversion in the Group2.
The channels marked by the bit positions that are set to 1 will be converted in ascendingorder when the Group2 is triggered.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.31 ADC Calibration and Error Offset Correction Register (ADCALR)ADC Calibration and Error Offset Correction Register (ADCALR) is shown in Figure 16-51 and Figure 1652, and described in Table 16-37. As shown, the format of the ADCALR is different based on whether the
ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 16-51. 12-bit ADC Calibration and Error Offset Correction Register (ADCALR) [offset = 84h]
31

12

11

0

Reserved

ADCALR

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 16-52. 10-bit ADC Calibration and Error Offset Correction Register (ADCALR) [offset = 84h]
31

10

9

0

Reserved

ADCALR

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-37. ADC Calibration and Error Offset Correction Register (ADCALR) Field Descriptions
Field

Value

Reserved

Description

0

Reads return 0. Writes have no effect.

ADCALRADC Calibration Result and Offset Error Correction Value.
The actual size of the ADCALR field is 12 bits or 10 bits depending on whether the ADC is configured to be
in 12-bit or 10-bit resolution mode, respectively. Bits 11-10 are reserved when the module is configured asa 10-bit ADC module.
The ADC module writes the results of the calibration conversions to this register. The application isrequired to use these conversion results and determine the ADC offset error. The application can thencompute the correction for the offset error and this correction value needs to be written back to the
ADCALR register in the 2's complement form.
During normal conversion (when calibration is disabled), the ADCALR register contents are automatically
added to each digital output from the ADC core before it is stored in the ADC results memory. For moredetails on error calibration, refer to Section 16.7.1.

16.10.32 ADC State Machine Status Register (ADSMSTATE)
Figure 16-53 and Table 16-38 describe the ADSMSTATE register.
Figure 16-53. ADC State Machine Status Register (ADSMSTATE) [offset = 88h]
31

4

3

0

Reserved

SMSTATE

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 16-38. ADC State Machine Status Register (ADSMSTATE) Field Descriptions
Bit

Field

31-4

Reserved

3-0

SMSTATE

Value
0

Description
Reads return 0. Writes have no effect.
ADC State Machine Current State.
These bits reflect the current state of the state machine and are reserved for use by TI for debug
purposes.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

537

ADC Registers

www.ti.com

16.10.33 ADC Channel Last Conversion Value Register (ADLASTCONV)ADC Channel Last Conversion Value Register (ADLASTCONV) is shown in Figure 16-54 and described inTable 16-39.
Figure 16-54. ADC Channel Last Conversion Value Register (ADLASTCONV) [offset = 8Ch]
31

24

23

0

Reserved

LAST_CONV

R-0

R-U

LEGEND: R = Read only; -U = value after reset is unknown; -n = value after reset

Table 16-39. ADC Channel Last Conversion Value Register (ADLASTCONV) Field Descriptions
Bit

Field

31-24

Reserved

23-0

LAST_CONV

Value
0

Description
Reads return 0. Writes have no effect.
ADC Input Channel's Last Converted Value.
This register indicates whether the last converted value for a particular input channel was lower orhigher than the mid-point of the reference voltage. In other words, this register acts as a digital
input register and can be read by the application to determine the digital level at the input pins.
This data is only valid for an input channel if it has been converted at least once.
Any operation mode read for each bit of this register:538

0

A level lower than the midpoint reference voltage was measured at the last conversion for thischannel.

1

A level higher than or equal to the midpoint reference voltage was measured at the last conversion
for this channel.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.34 ADC Event Group Results' FIFO Register (ADEVBUFFER)
ADC Event Group Results' FIFO Register (ADEVBUFFER) is shown in Figure 16-55 and Figure 16-56,
and described in Table 16-40. The format of the data read from the ADEVBUFFER locations is different
based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 16-55. 12-bit ADC Event Group Results' FIFO Register (ADEVBUFFER)[offset = 90h-AFh]
31

30

21

20

16

EV_EMPTY

Reserved

EV_CHID

R-1

R-0

R-0

15

12

11

0

Reserved

EV_DR

R-0

R-U

LEGEND: R = Read only; -U = value after reset is unknown; -n = value after reset

Figure 16-56. 10-bit ADC Event Group Results' FIFO Register (ADEVBUFFER)[offset = 90h-AFh]
31

16
Reserved
R-0
15

14

10

9

0

EV_EMPTY

EV_CHID

EV_DR

R-1

R-0

R-U

LEGEND: R = Read only; -U = value after reset is unknown; -n = value after reset

Table 16-40. ADC Event Group Results' FIFO Register (ADEVBUFFER) Field Descriptions
Field
Reserved

Value
0

EV_EMPTY

Description
Reads return 0. Writes have no effect.
Event Group FIFO Empty. This bit is applicable only when the "read from FIFO" mode is used for reading
the Event Group conversion results.
Any operation mode read:0

The data in the EV_DR field of this buffer is valid.

1

The data in the EV_DR field of this buffer is not valid and there are no valid data in the Event Group results
memory.

EV_CHID

Event Group Channel Id. These bits are also applicable only when the "read from FIFO" mode is used forreading the Event Group conversion results.
Any operation mode read:0

The conversion result in the EV_DR field of this buffer is from the ADC input channel 0, or the channel idmode is disabled in the Event Group mode control register (ADEVMODECR).

1h-1FhThe conversion result in the EV_DR field of this buffer is from the ADC input channel number denoted by
the EV_CHID field.

EV_DR

Event Group Digital Conversion Result.
The Event Group results’ FIFO location is aliased eight times, so that any word-aligned read from theaddress range 0x90 to 0xAF results in one conversion result to be read from the Event Group results’memory. This allows the ARM LDMIA instruction to read out up to 8 conversion results from the Event
Group results’ memory with just one instruction.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

539

ADC Registers

www.ti.com

16.10.35 ADC Group1 Results FIFO Register (ADG1BUFFER)
ADC Group1 Results FIFO Register (ADG1BUFFER) is shown in Figure 16-57 and Figure 16-58, anddescribed in Table 16-41. The format of the data read from the ADG1BUFFER locations is different basedon whether the ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 16-57. 12-bit ADC Group1 Results FIFO Register (ADG1BUFFER)[offset = B0h-CFh]
31

30

21

20

16

G1_EMPTY

Reserved

G1_CHID

R-1

R-0

R-0

15

12

11

0

Reserved

G1_DR

R-0

R-U

LEGEND: R = Read only; -U = value after reset is unknown; -n = value after reset

Figure 16-58. 10-bit ADC Group1 Results' FIFO Register (ADG1BUFFER)[offset = B0h-CFh]
31

16
Reserved
R-0
15

14

10

9

0

G1_EMPTY

G1_CHID

G1_DR

R-1

R-0

R-U

LEGEND: R = Read only; -U = value after reset is unknown; -n = value after reset

Table 16-41. ADC Group1 Results FIFO Register (ADG1BUFFER) Field Descriptions
Field

Value

Reserved

0

G1_EMPTY

Description
Reads return 0. Writes have no effect.
Group1 FIFO Empty. This bit is applicable only when the "read from FIFO" mode is used for reading theGroup1 conversion results.
Any operation mode read:0

The data in the G1_DR field of this buffer is valid.

1

The data in the G1_DR field of this buffer is not valid and there are no valid data in the Group1 results
memory.

G1_CHID

Group1 Channel Id. These bits are also applicable only when the "read from FIFO" mode is used forreading the Group1 conversion results.
Any operation mode read:

G1_DR

0

The conversion result in the G1_DR field of this buffer is from the ADC input channel 0, or the channel idmode is disabled in the Group1 mode control register (ADG1MODECR).

1h-1FhThe conversion result in the G1_DR field of this buffer is from the ADC input channel number denoted by
the G1_CHID field.
Group1 Digital Conversion Result.
The Group1 results’ FIFO location is aliased eight times, so that any word-aligned read from the address
range 0xB0 to 0xCF results in one conversion result to be read from the Group1 results’ memory. This
allows the ARM LDMIA instruction to read out up to 8 conversion results from the Group1 results’ memory
with just one instruction.

540

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.36 ADC Group2 Results FIFO Register (ADG2BUFFER)
ADC Group2 Results FIFO Register (ADG2BUFFER) is shown in Figure 16-59 and Figure 16-60, anddescribed in Table 16-42. The format of the data read from the ADG2BUFFER locations is different basedon whether the ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 16-59. 12-bit ADC Group2 Results FIFO Register (ADG2BUFFER)[offset = D0h-EFh]
31

30

21

20

16

G2_EMPTY

Reserved

G2_CHID

R-1

R-0

R-0

15

12

11

0

Reserved

G2_DR

R-0

R-U

LEGEND: R = Read only; -U = value after reset is unknown; -n = value after reset

Figure 16-60. 10-bit ADC Group2 Results' FIFO Register (ADG2BUFFER)[offset = D0h-EFh]
31

16
Reserved
R-0
15

14

10

9

0

G2_EMPTY

G2_CHID

G2_DR

R-1

R-0

R-U

LEGEND: R = Read only; -U = value after reset is unknown; -n = value after reset

Table 16-42. ADC Group2 Results FIFO Register (ADG2BUFFER) Field Descriptions
Field
Reserved

Value
0

G2_EMPTY

Description
Reads return 0. Writes have no effect.
Group2 FIFO Empty. This bit is applicable only when the "read from FIFO" mode is used for reading theGroup2 conversion results.
Any operation mode read:0

The data in the G2_DR field of this buffer is valid.

1

The data in the G2_DR field of this buffer is not valid and there are no valid data in the Group2 results
memory.

G2_CHID

Group2 Channel Id. These bits are also applicable only when the "read from FIFO" mode is used forreading the Group2 conversion results.
Any operation mode read:0

The conversion result in the G2_DR field of this buffer is from the ADC input channel 0, or the channel idmode is disabled in the Group2 mode control register (ADG2MODECR).

1h-1FhThe conversion result in the G2_DR field of this buffer is from the ADC input channel number denoted by
the G2_CHID field.

G2_DRGroup2 Digital Conversion Result.
The Group2 results’ FIFO location is aliased eight times, so that any word-aligned read from the address
range 0xD0 to 0xEF results in one conversion result to be read from the Group2 results’ memory. This
allows the ARM LDMIA instruction to read out up to 8 conversion results from the Group2 results’ memory
with just one instruction.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

541

ADC Registers

www.ti.com

16.10.37 ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER)
ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER) is shown in Figure 16-61 andFigure 16-62, and described in Table 16-43. As shown, the format of the data read from theADEVEMUBUFFER locations is different based on whether the ADC module is configured to be a 12-bit
or a 10-bit ADC module.
A read from this location also gives out one conversion result from the Event Group results’ memory alongwith the EV_EMPTY status bit and the optional channel id. However, this read will not affect any of thestatus flags in the Event Group interrupt flag register or the Event Group status register. This register isuseful for debuggers.
Figure 16-61. 12-bit ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER)[offset = F0h]
31

30

21

20

16

EV_EMPTY

Reserved

EV_CHID

R-1

R-0

R-0

15

12

11

0

Reserved

EV_DR

R-0

R-U

LEGEND: R = Read only; -U = value after reset is unknown; -n = value after reset

Figure 16-62. 10-bit ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER)[offset = F0h]
31

16
Reserved
R-0
15

14

10

9

0

EV_EMPTY

EV_CHID

EV_DR

R-1

R-0

R-U

LEGEND: R = Read only; -U = value after reset is unknown; -n = value after reset

Table 16-43. ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER)
Field Descriptions
Field

Value

Reserved0

EV_EMPTY

Description
Reads return 0. Writes have no effect.
Event Group FIFO Empty. This bit is applicable only when the "read from FIFO" mode is used for reading
the Event Group conversion results.
Any operation mode read:0

The data in the EV_DR field of this buffer is valid.

1

The data in the EV_DR field of this buffer is not valid and there are no valid data in the Event Group results
memory.

EV_CHID

Event Group Channel Id. These bits are also applicable only when the "read from FIFO" mode is used forreading the Event Group conversion results.
Any operation mode read:

EV_DR

0

The conversion result in the EV_DR field of this buffer is from the ADC input channel 0, or the channel idmode is disabled in the Event Group operating mode control register (ADEVMODECR).

1h-1FhThe conversion result in the EV_DR field of this buffer is from the ADC input channel number denoted by
the EV_CHID field.
Event Group Digital Conversion Result.
These bits contain the digital result output from the Event Group FIFO buffer. The result can be presented
in an 8-bit, 10-bit, or 12-bit format for a 12-bit ADC module, or in an 8-bit or 10-bit format for a 10-bit ADC
module. The conversion result data is automatically shifted right by the appropriate number of bits whenusing a reduced-size data format with the upper bits reading as zeros.

542

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.38 ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER)
ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) is shown in Figure 16-63 andFigure 16-64, described in Table 16-44. As shown, the format of the data read from theADG1EMUBUFFER locations is different based on whether the ADC module is configured to be a 12-bit
or a 10-bit ADC module.
A read from this location also gives out one conversion result from the Group1 results’ memory along with
the G1_EMPTY status bit and the optional channel id. However, this read will not affect any of the status
flags in the Group1 interrupt flag register or the Group1 status register. This register is useful for
debuggers.
Figure 16-63. 12-bit ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER)[offset = F4h]
31

30

21

20

16

G1_EMPTY

Reserved

G1_CHID

R-1

R-0

R-0

15

12

11

0

Reserved

G1_DR

R-0

R-U

LEGEND: R = Read only; -U = value after reset is unknown; -n = value after reset

Figure 16-64. 10-bit ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER)[offset = F4h]
31

16
Reserved
R-0
15

14

10

9

0

G1_EMPTY

G1_CHID

G1_DR

R-1

R-0

R-U

LEGEND: R = Read only; -U = value after reset is unknown; -n = value after reset

Table 16-44. ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) Field Descriptions
Field
Reserved

Value
0

G1_EMPTY

Description
Reads return 0. Writes have no effect.
Group1 FIFO Empty. This bit is applicable only when the "read from FIFO" mode is used for reading theGroup1 conversion results.
Any operation mode read:0

The data in the G1_DR field of this buffer is valid.

1

The data in the G1_DR field of this buffer is not valid and there are no valid data in the Group1 results
memory.

G1_CHID

Group1 Channel Id. These bits are also applicable only when the "read from FIFO" mode is used forreading the Group1 conversion results.
Any operation mode read:0

The conversion result in the G1_DR field of this buffer is from the ADC input channel 0, or the channel idmode is disabled in the Group1 operating mode control register (ADG1MODECR).

1h-1FhThe conversion result in the G1_DR field of this buffer is from the ADC input channel number denoted by
the G1_CHID field.

G1_DRGroup1 Digital Conversion Result.
These bits contain the digital result output from the Group 1 FIFO buffer. The result can be presented in an
8-bit, 10-bit, or 12-bit format for a 12-bit ADC module, or in an 8-bit or 10-bit format for a 10-bit ADC
module. The conversion result data is automatically shifted right by the appropriate number of bits whenusing a reduced-size data format with the upper bits reading as zeros.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

543

ADC Registers

www.ti.com

16.10.39 ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER)
ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) is shown in Figure 16-65 andFigure 16-66, described in Table 16-45. As shown, the format of the data read from theADG2EMUBUFFER locations is different based on whether the ADC module is configured to be a 12-bit
or a 10-bit ADC module.
A read from this location also gives out one conversion result from the Group2 results’ memory along with
the G2_EMPTY status bit and the optional channel id. However, this read will not affect any of the status
flags in the Group2 interrupt flag register or the Group2 status register. This register is useful for
debuggers.
Figure 16-65. 12-bit ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER)[offset = F8h]
31

30

21

20

16

G2_EMPTY

Reserved

G2_CHID

R-1

R-0

R-0

15

12

11

0

Reserved

G2_DR

R-0

R-U

LEGEND: R = Read only; -U = value after reset is unknown; -n = value after reset

Figure 16-66. 10-bit ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER)[offset = F8h]
31

16
Reserved
R-0
15

14

10

9

0

G2_EMPTY

G2_CHID

G2_DR

R-1

R-0

R-U

LEGEND: R = Read only; -U = value after reset is unknown; -n = value after reset

Table 16-45. ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) Field Descriptions
Field

Value

Reserved

0

G2_EMPTY

Description
Reads return 0. Writes have no effect.
Group2 FIFO Empty. This bit is applicable only when the "read from FIFO" mode is used for reading theGroup2 conversion results.
Any operation mode read:0

The data in the G2_DR field of this buffer is valid.

1

The data in the G2_DR field of this buffer is not valid and there are no valid data in the Group2 results
memory.

G2_CHID

Group2 Channel Id. These bits are also applicable only when the "read from FIFO" mode is used forreading the Group2 conversion results.
Any operation mode read:

G2_DR

0

The conversion result in the G2_DR field of this buffer is from the ADC input channel 0, or the channel idmode is disabled in the Group2 operating mode control register (ADG2MODECR).

1h-1FhThe conversion result in the G2_DR field of this buffer is from the ADC input channel number denoted by
the G2_CHID field.
Group2 Digital Conversion Result.
These bits contain the digital result output from the Group 2 FIFO buffer. The result can be presented in an
8-bit, 10-bit, or 12-bit format for a 12-bit ADC module, or in an 8-bit or 10-bit format for a 10-bit ADC
module. The conversion result data is automatically shifted right by the appropriate number of bits whenusing a reduced-size data format with the upper bits reading as zeros.

544

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.40 ADC ADEVT Pin Direction Control Register (ADEVTDIR)ADC ADEVT Pin Direction Control Register (ADEVTDIR) is shown in Figure 16-67 and described inTable 16-46.
Figure 16-67. ADC ADEVT Pin Direction Control Register (ADEVTDIR) [offset = FCh]
31

1

0

Reserved

ADEVT_DIR

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-46. ADC ADEVT Pin Direction Control Register (ADEVTDIR) Field Descriptions
Bit

Field

31-1

Reserved

0

ADEVT_DIR

Value
0

Description
Reads return 0. Writes have no effect.
ADEVT Pin Direction.
Any operating mode read/write:

SPNU517C – March 2018
Submit Documentation Feedback

0

ADEVT is an input pin; the output buffer is disabled.

1

ADEVT is an output pin; the output buffer is enabled.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

545

ADC Registers

www.ti.com

16.10.41 ADC ADEVT Pin Output Value Control Register (ADEVTOUT)ADC ADEVT Pin Output Value Control Register (ADEVTOUT) is shown in Figure 16-68 and described inTable 16-47.
Figure 16-68. ADC ADEVT Pin Output Value Control Register (ADEVTOUT) [offset = 100h]
31

1

0

Reserved

ADEVT_OUT

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-47. ADC ADEVT Pin Output Value Control Register (ADEVTOUT) Field Descriptions
Bit

Field

31-1

Reserved

0

Value
0

ADEVT_OUT

Description
Reads return 0. Writes have no effect.
ADEVT Pin Output Value. This bit determines the logic level to be output to the ADEVT pin when
the pin is configured to be an output pin.
Any operating mode read/write:

0

Output logic LOW on the ADEVT pin.

1

Output logic HIGH on the ADEVT pin.

16.10.42 ADC ADEVT Pin Input Value Register (ADEVTIN)ADC ADEVT Pin Input Value Register (ADEVTIN) is shown in Figure 16-69 and described in Table 16-48.
Figure 16-69. ADC ADEVT Pin Input Value Register (ADEVTIN) [offset = 104h]
31

1

0

Reserved

ADEVT_IN

R-0

R-U

LEGEND: R = Read only; -U = value after reset is unknown; -n = value after reset

Table 16-48. ADC ADEVT Pin Input Value Register (ADEVTIN) Field Descriptions
Bit

Field

31-1

Reserved

0

ADEVT_IN

Value
0

Description
Reads return 0. Writes have no effect.
ADEVT Pin Input Value. This is a read-only bit which reflects the logic level on the ADEVT pin.
Any operating mode read:

546

0

Logic LOW present on the ADEVT pin.

1

Logic HIGH present on the ADEVT pin.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.43 ADC ADEVT Pin Set Register (ADEVTSET)ADC ADEVT Pin Set Register (ADEVTSET) is shown in Figure 16-70 and described in Table 16-49.
Figure 16-70. ADC ADEVT Pin Set Register (ADEVTSET) [offset = 108h]
31

1

0

Reserved

ADEVT_SET

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-49. ADC ADEVT Pin Set Register (ADEVTSET) Field Descriptions
Bit

Field

31-1

Reserved

0

Value
0

ADEVT_SETDescription
Reads return 0. Writes have no effect.
ADEVT Pin Set. This bit drives the output of the ADEVT pin high. A read from this bit always
returns the current state of the ADEVT pin.
Any operating mode read/write:

0

Output value on the ADEVT pin is unchanged.

1

Output logic HIGH on the ADEVT pin, if the pin is configured to be an output pin.

16.10.44 ADC ADEVT Pin Clear Register (ADEVTCLR)
ADC ADEVT Pin Clear Register (ADEVTCLR) is shown in Figure 16-71 and described in Table 16-50.
Figure 16-71. ADC ADEVT Pin Clear Register (ADEVTCLR) [offset = 10Ch]
31

1

0

Reserved

ADEVT_CLR

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-50. ADC ADEVT Pin Clear Register (ADEVTCLR) Field Descriptions
Bit

Field

31-1

Reserved

0

Value
0

ADEVT_CLR

Description
Reads return 0. Writes have no effect.
ADEVT Pin Clear. A read from this bit always returns the current state of the ADEVT pin.
Any operating mode read/write:

SPNU517C – March 2018
Submit Documentation Feedback0

Output value on the ADEVT pin is unchanged.

1

Output logic LOW on the ADEVT pin, if the pin is configured to be an output pin.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

547

ADC Registers

www.ti.com

16.10.45 ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR)ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) is shown in Figure 16-72 and described inTable 16-51.
Figure 16-72. ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) [offset = 110h]
31

1

0

Reserved

ADEVT_PDR

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-51. ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) Field Descriptions
Bit

Field

31-1

Reserved

0

Value
0

ADEVT_PDR

Description
Reads return 0. Writes have no effect.
ADEVT Pin Open Drain Enable. This bit enables the open-drain capability for the ADEVT pin if it isconfigured to be an output and a logic HIGH is being driven on to the pin.
Any operating mode read/write:

0

Output value on the ADEVT pin is logic HIGH.

1

The ADEVT pin is tristated.

16.10.46 ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS)ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) is shown in Figure 16-73 and described inTable 16-52.
Figure 16-73. ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) [offset = 114h]
31

1

0

Reserved

ADEVT_PDIS

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-52. ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) Field Descriptions
Bit

Field

31-1

Reserved

0

Value
0

ADEVT_PDIS

Description
Reads return 0. Writes have no effect.
ADEVT Pin Pull Control Disable. This bit enables or disables the pull control on the ADEVT pin if it
is configured to be an input pin.
Any operating mode read/write:

548

0Pull on ADEVT pin is enabled.

1

Pull on ADEVT pin is disabled.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.47 ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL)ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) is shown in Figure 16-74 and described inTable 16-53.
Figure 16-74. ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) [offset = 118h]
31

1

0

Reserved

ADEVT_PSEL

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-53. ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) Field Descriptions
Bit

Field

31-1

Reserved

0

Value

Description

0

Reads return 0. Writes have no effect.

ADEVT_PSELADEVT Pin Pull Control Select. This bit selects a pull-down or pull-up on the ADEVT pin if it isconfigured to be an input pin.
Any operating mode read/write:
0

Pull down is selected on ADEVT pin.

1

Pull up is selected on ADEVT pin.

16.10.48 ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN)
ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN) is shown in Figure 16-75
and described in Table 16-54.
Figure 16-75. ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN)[offset = 11Ch]
31

16
Reserved
R-0

15

8

7

1

0

EV_SAMP_DIS_CYCReserved

EV_SAMP_DIS_EN

R/W-0

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-54. ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN)
Field Descriptions
Bit

Field

31-16

Reserved

15-8

EV_SAMP_DIS_CYC

7-1

Reserved0

EV_SAMP_DIS_EN

Value
0

Description
Reads return 0. Writes have no effect.
Event Group sample cap discharge cycles. These bits specify the duration in terms of ADCLK
cycles for which the ADC internal sampling capacitor is allowed to discharge before sampling
the input channel voltage.

0

Reads return 0. Writes have no effect.
Event Group sample cap discharge enable.
Any operation mode read/write:

SPNU517C – March 2018
Submit Documentation Feedback0

Event Group sample cap discharge mode is disabled.

1

Event Group sample cap discharge mode is enabled. The ADC internal sampling capacitor isconnected to the V REFLO reference voltage for a duration specified by the EV_SAMP_DIS_CYC
field. After this discharge time has expired the selected ADC input channel is sampled andconverted normally based on the Event Group settings.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

549

ADC Registers

www.ti.com

16.10.49 ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN)ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) is shown in Figure 16-76 anddescribed in Table 16-55.
Figure 16-76. ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN)[offset = 120h]
31

16
Reserved
R-0

15

8

7

1

0

G1_SAMP_DIS_CYCReserved

G1_SAMP_DIS_EN

R/W-0

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-55. ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN)
Field Descriptions
Bit

Field

31-16

Reserved

15-8

G1_SAMP_DIS_CYC

7-1

Reserved

0

G1_SAMP_DIS_EN

Value
0

Description
Reads return 0. Writes have no effect.
Group1 sample cap discharge cycles. These bits specify the duration in terms of ADCLK cycles
for which the ADC internal sampling capacitor is allowed to discharge before sampling the input
channel voltage.

0

Reads return 0. Writes have no effect.
Group1 sample cap discharge enable.
Any operation mode read/write:

5500Group1 sample cap discharge mode is disabled.

1

Group1 sample cap discharge mode is enabled. The ADC internal sampling capacitor isconnected to the VREFLO reference voltage for a duration specified by the G1_SAMP_DIS_CYC
field. After this discharge time has expired the selected ADC input channel is sampled andconverted normally based on the Group1 settings.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.50 ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN)ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) is shown in Figure 16-77 anddescribed in Table 16-56.
Figure 16-77. ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN)[offset = 124h]
31

16
Reserved
R-0

15

8

7

1

0

G2_SAMP_DIS_CYCReserved

G2_SAMP_DIS_EN

R/W-0

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-56. ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN)
Field Descriptions
Bit

Field

31-16

Reserved

15-8

G2_SAMP DIS CYC

7-1

Reserved

0

G2_SAMP_DIS_EN

Value
0

Description
Reads return 0. Writes have no effect.
Group2 sample cap discharge cycles. These bits specify the duration in terms of ADCLK cycles
for which the ADC internal sampling capacitor is allowed to discharge before sampling the input
channel voltage.

0

Reads return 0. Writes have no effect.
Group2 sample cap discharge enable.
Any operation mode read/write:

SPNU517C – March 2018
Submit Documentation Feedback0Group2 sample cap discharge mode is disabled.

1

Group2 sample cap discharge mode is enabled. The ADC internal sampling capacitor isconnected to the VREFLO reference voltage for a duration specified by the G2_SAMP_DIS_CYC
field. After this discharge time has expired the selected ADC input channel is sampled andconverted normally based on the Group2 settings.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

551

ADC Registers

www.ti.com

16.10.51 ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR)
ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR) are shown in Figure 16-78 and
Figure 16-79, and described in Table 16-57. As shown, the format of the ADMAGINTxCR is different
based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module. The ADC module
supports up to three magnitude compare interrupts. These registers are at offset addresses 128h, 130h,
and 138h.
Figure 16-78. 12-bit ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR)[offset = 128h-138h]
31

28

27

16

Reserved

MAG_THRx

R-0

R/W-0

15

14

13

CHN_THR_COMPx

CMP_GE_LTx

Reserved

COMP_CHIDx

R/W-0

R/W-0

R-0

R/W-0

7

12

5

8

4

0

Reserved

MAG_CHIDx

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 16-79. 10-bit ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR)[offset = 128h-138h]
31

30

26

25

16

Rsvd

MAG_CHIDx

MAG_THRx

R-0

R/W-0

R/W-0

15

13

12

8

Reserved

COMP_CHIDx

R-0

R/W-0

7

1

0

Reserved

2

CHN_THR_COMPx

CMP_GE_LTx

R-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

552

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

Table 16-57. ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR)
Field Descriptions
Field
Reserved

Value
0

Description
Reads return 0. Writes have no effect.

MAG_CHIDx

These bits specify the channel number from 0 to 31 for which the conversion result needs to bemonitored by the ADC.

MAG_THRx

These bits specify the 12-bit or 10-bit compare value that the ADC will use for the comparison with the
MAG_CHIDx channel's conversion result.

COMP_CHIDx

These bits specify the channel number from 0 to 31 whose last conversion result is compared with the
MAG_CHIDx channel's conversion result.

CHN_THR_COMPx

Channel OR Threshold comparison.
Any operation mode read/write:
0

The ADC module will compare the MAG_CHIDx channel's conversion result with the fixed thresholdvalue specified by the MAG_THRx field

1

The ADC module will compare the MAG_CHIDx channel's conversion result with the last conversion
result for the COMP_CHIDx channel.
Both the MAG_CHIDx and the COMP_CHIDx channel must have been converted at least once for the
ADC to perform the comparison.

CMP_GE_LTx"Greater than or equal to" OR "Less than" comparison operator.
Any operation mode read/write:
0

The ADC module will check if the conversion result is lower than the reference value (fixed thresholdor COMP_CHIDx conversion result).

1

The ADC module will check if the conversion result is greater than or equal to the reference value(fixed threshold or COMP_CHIDx conversion result).

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

553

ADC Registers

www.ti.com

16.10.52 ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK)ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK) is shown in Figure 16-80andFigure 16-81, and described in Table 16-58. As shown, the format of the ADMAGxMASK is different
based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module. There are threemask registers for the three magnitude compare interrupts. These registers are at offset addresses 12Ch,
134h, and 13Ch.
Figure 16-80. 12-bit ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK)[offset = 12Ch-13Ch]
31

12

11

0

Reserved

MAG_INTx_MASK

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 16-81. 10-bit ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK)[offset = 12Ch-13Ch]
31

10

9

0

Reserved

MAG_INTx_MASK

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-58. ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK) Field
Descriptions
Field

Value

Reserved

0

MAG_INTx_MASKDescription
Reads return 0. Writes have no effect.
These bits specify the mask for the comparison in order to generate the magnitude compare interrupt # x.
Any operation mode read/write:

554

0

The ADC module will not mask the corresponding bit for the comparison.

1

The ADC module will mask the corresponding bit for the comparison.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.53 ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET)
ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) is shown in Figure 16-82
and described in Table 16-59.
Figure 16-82. ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET)[offset = 158h]
31

3

2

0

Reserved

MAG_INT_ENA_SET

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-59. ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET)
Field Descriptions
Bit

Field

31-3

Reserved

2-0

MAG_INT_ENA_SET

Value
0

Description
Reads return 0. Writes have no effect.
Each of these three bits, when set, enable the corresponding magnitude compare interrupt.
Any operation mode read/write for each bit:

0

The enable status of the corresponding magnitude compare interrupt is left unchanged.

1

The corresponding magnitude compare interrupt is enabled.

16.10.54 ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR)ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR) is shown in Figure 16-83
and described in Table 16-60.
Figure 16-83. ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR)[offset = 15Ch]
31

3

2

0

Reserved

MAG_INT_ENA_CLR

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-60. ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR)
Field Descriptions
Bit

Field

31-3

Reserved

2-0

MAG_INT_ENA_CLR

Value
0

Description
Reads return 0. Writes have no effect.
Each of these three bits, when set, enable the corresponding magnitude compare interrupt.
Any operation mode read/write for each bit:

SPNU517C – March 2018
Submit Documentation Feedback0

The enable status of the corresponding magnitude compare interrupt is left unchanged.

1

The corresponding magnitude compare interrupt is disabled.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

555

ADC Registers

www.ti.com

16.10.55 ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG)
ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG) is shown in Figure 16-84 anddescribed in Table 16-61.
Figure 16-84. ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG) [offset = 160h]
31

3

2

0

Reserved

MAG_INT_FLG

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-61. ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG) Field Descriptions
Bit

Field

31-3

Reserved

2-0

MAG_INT_FLG

Value
0

Description
Reads return 0. Writes have no effect.
Magnitude Compare Interrupt Flags. These bits can be polled by the application to determine if themagnitude compares have been evaluated as true. When a magnitude compare interrupt flag is set,the corresponding magnitude compare interrupt will be generated if enabled.
Any operation mode, for each bit:0

Read: The condition for the corresponding magnitude threshold interrupt was false.
Write: The corresponding flag is left unchanged.

1

Read: The condition for the corresponding magnitude threshold interrupt was true.
Write: The corresponding flag is cleared. The flag can also be cleared by reading from themagnitude compare interrupt offset register.

16.10.56 ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF)ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF) is shown in Figure 16-85 anddescribed in Table 16-62.
Figure 16-85. ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF) [offset = 164h]
31

4

3

0

Reserved

MAG_INT_OFF

R-0

R/C-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset

Table 16-62. ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF) Field Descriptions
Bit

Field

31-4

Reserved

3-0

MAG_INT_OFF

Value
0

Description
Reads return 0. Writes have no effect.
Magnitude Compare Interrupt Offset. This field indexes the currently highest-priority magnitude
compare interrupt. Interrupt 1 has the highest priority and interrupt 3 has the lowest priority among
the magnitude compare interrupts.
Writes to these bits have no effect. A read from this register clears this register as well as thecorresponding magnitude compare interrupt flag in the ADMAGINTFLG register. However, a readfrom this register in emulation mode does not affect this register or the interrupt status flags.
Any operation mode read:556

0

No magnitude compare interrupt is pending.

1hMagnitude compare interrupt # 1 is pending.

2hMagnitude compare interrupt # 2 is pending.

3hMagnitude compare interrupt # 3 is pending.

4h-Fh

Reserved. These combinations do not occur.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.57 ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR)ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR) is shown in Figure 16-86 anddescribed in Table 16-63.
Figure 16-86. ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR) [offset = 168h]
31

1

0

Reserved

EV_FIFO_RESET

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-63. ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR)
Field Descriptions
Bit

Field

31-1

Reserved

0

Value
0

EV_FIFO_RESET

Description
Reads return 0. Writes have no effect.
ADC Event Group FIFO Reset. The application can set this bit in case of an overrun condition. This
allows the ADC module to overwrite the contents of the Event Group results memory starting fromthe first location.
When this bit is set to 1, the ADC module resets its internal Event Group results memory pointers.
Then this bit automatically gets cleared, so that the ADC module allows the Event Group results
memory to be overwritten only once each time this bit is set to 1. As a result, the EV_FIFO_RESET
bit will always be read as a 0.
The EV_FIFO_RESET bit will only have the desired effect when the Event Group results memory isin an overrun condition. It must be used when the data already available in the results memory canbe discarded.
If the application needs the Event Group memory to always be overwritten with the latest available
conversion results, then the OVR_EV_RAM_IGN bit in the Event Group operating mode control
register (ADEVMODECR) needs to be set to 1.

16.10.58 ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR)ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) is shown in Figure 16-87 anddescribed in Table 16-64.
Figure 16-87. ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) [offset = 16Ch]
31

1

0

Reserved

G1_FIFO_RESET

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-64. ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) Field Descriptions
Bit

Field

31-1

Reserved

0

Reads return 0. Writes have no effect.

G1_FIFO_RESET

0-1

ADC Group1 FIFO Reset. The application can set this bit in case of an overrun condition. This
allows the ADC module to overwrite the contents of the Group1 results memory starting from thefirst location.

0

Value

Description

When this bit is set to 1, the ADC module resets its internal Group1 results memory pointers. Then
this bit automatically gets cleared, so that the ADC module allows the Group1 results memory to be
overwritten only once each time this bit is set to 1. As a result, the G1_FIFO_RESET bit will always
be read as a 0.
The G1_FIFO_RESET bit will only have the desired effect when the Group1 results memory is in an
overrun condition. It must be used when the data already available in the results memory can bediscarded.
If the application needs the Group1 memory to always be overwritten with the latest available
conversion results, then the OVR_G1_RAM_IGN bit in the Group1 operating mode control register(ADG1MODECR) needs to be set to 1.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

557

ADC Registers

www.ti.com

16.10.59 ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR)ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) is shown in Figure 16-88 anddescribed in Table 16-65.
Figure 16-88. ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) [offset = 170h]
31

1

0

Reserved

G2_FIFO_RESET

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-65. ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) Field Descriptions
Bit

Field

31-1

Reserved

0

Reads return 0. Writes have no effect.

G2_FIFO_RESET

0-1

ADC Group2 FIFO Reset. The application can set this bit in case of an overrun condition. This
allows the ADC module to overwrite the contents of the Group2 results memory starting from thefirst location.

0

Value

Description

When this bit is set to 1, the ADC module resets its internal Group2 results memory pointers. Then
this bit automatically gets cleared, so that the ADC module allows the Group2 results memory to be
overwritten only once each time this bit is set to 1. As a result, the G2_FIFO_RESET bit will always
be read as a 0.
The G2_FIFO_RESET bit will only have the desired effect when the Group2 results memory is in an
overrun condition. It must be used when the data already available in the results memory can bediscarded.
If the application needs the Group2 memory to always be overwritten with the latest available
conversion results, then the OVR_G2_RAM_IGN bit in the Group2 operating mode control register(ADG2MODECR) needs to be set to 1.

16.10.60 ADC Event Group RAM Write Address Register (ADEVRAMWRADDR)ADC Event Group RAM Write Address Register (ADEVRAMWRADDR) is shown in Figure 16-89 anddescribed in Table 16-66.
Figure 16-89. ADC Event Group RAM Write Address Register (ADEVRAMWRADDR) [offset = 174h]
31

9

8

0

Reserved

EV_RAM_ADDR

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-66. ADC Event Group RAM Write Address Register (ADEVRAMWRADDR)
Field Descriptions
Bit

Field

31-9

Reserved

8-0

EV_RAM_ADDR

Value
0

Description
Reads return 0. Writes have no effect.
Event Group results memory write pointer. This field shows the address of the location where thenext Event Group conversion result will be stored. This is specified in terms of the buffer number.
The application can read this register to determine the number of valid Event Group conversion
results available until that time.

558

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.61 ADC Group1 RAM Write Address Register (ADG1RAMWRADDR)ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) is shown in Figure 16-90 and describedin Table 16-67.
Figure 16-90. ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) [offset = 178h]
31

9

8

0

Reserved

G1_RAM_ADDR

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-67. ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) Field Descriptions
Bit

Field

31-9

Reserved

8-0

G1_RAM_ADDR

Value
0

Description
Reads return 0. Writes have no effect.
Group1 results memory write pointer. This field shows the address of the location where the next
Group1 conversion result will be stored. This is specified in terms of the buffer number.
The application can read this register to determine the number of valid Group1 conversion results
available until that time.

16.10.62 ADC Group2 RAM Write Address Register (ADG2RAMWRADDR)ADC Group2 RAM Write Address Register (ADG2RAMWRADDR) is shown in Figure 16-91 and describedin Table 16-68.
Figure 16-91. ADC Group2 RAM Write Address Register (ADG2RAMWRADDR) [offset = 17Ch]
31

9

8

0

Reserved

G2_RAM_ADDR

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-68. ADC Group2 RAM Write Address Register (ADG2RAMWRADDR) Field Descriptions
Bit

Field

31-9

Reserved

8-0

G2_RAM_ADDR

Value
0

Description
Reads return 0. Writes have no effect.
Group2 results memory write pointer. This field shows the address of the location where the next
Group2 conversion result will be stored. This is specified in terms of the buffer number.
The application can read this register to determine the number of valid Group2 conversion results
available until that time.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

559

ADC Registers

www.ti.com

16.10.63 ADC Parity Control Register (ADPARCR)
ADC Parity Control Register (ADPARCR) is shown in Figure 16-92 and described in Table 16-69.
Figure 16-92. ADC Parity Control Register (ADPARCR) [offset = 180h]
31

16
Reserved
R-0

15

9

8

7

4

3

0

Reserved

TEST

Reserved

PARITY_ENA

R-0

R/WP-0R-0

R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 16-69. ADC Parity Control Register (ADPARCR) Field Descriptions
Bit

Field

31-9

Reserved

8

Value

Description

0

Reads return 0. Writes have no effect.

TEST

This bit maps the parity bits into the ADC results' RAM frame so that the application can accessthem.
Any operation mode read, privileged mode write:

7-4

Reserved

3-0

PARITY_ENA

0

The parity bits are not memory-mapped.

1

The parity bits are memory-mapped.

0

Reads return 0. Writes have no effect.
Enable parity checking. These bits enable the parity check on read operations and the parity
calculation on write operations to the ADC results memory.
If parity checking is enabled and a parity error is detected, the ADC module sends a parity error
signal to the System module.
Any operation mode read, privileged mode write:

5h

Parity check is disabled.

All other Parity check is enabled.
values16.10.64 ADC Parity Error Address Register (ADPARADDR)ADC Parity Error Address Register (ADPARADDR) is shown inFigure 16-93 and described in Table 16-70.
Figure 16-93. ADC Parity Error Address Register (ADPARADDR) [offset = 184h]
31

16
Reserved
R-0

15

12

11

2

1

0

Reserved

ERROR_ADDRESS

Reserved

R-0

R-U

R-0

LEGEND: R/W = Read/Write; R = Read only; -U = value after reset is unknown; -n = value after reset

Table 16-70. ADC Parity Error Address Register (ADPARADDR) Field Descriptions
Bit

Field

31-12

Reserved

11-2

ERROR_ADDRESS

1-0

Reserved

560

Value
0

Description
Reads return 0. Writes have no effect.
These bits hold the address of the first parity error generated in the ADC results' RAM. Thiserror address is frozen from being updated until it is read by the application. In emulation mode,
this address is maintained frozen even when read.

0

Reads return 0. Writes have no effect. Reading [11:0] provides the 32-bit aligned address.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.65 ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL)
Figure 16-94 and Table 16-71 describe the ADPWRDLYCTRL register.
Figure 16-94. ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL) [offset = 188h]
31

10

9

0

Reserved

PWRUP_DLY

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-71. ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL) Field Descriptions
Bit

Field

31-10

Reserved

9-0

PWRUP_DLY

Value
0

Description
Reads return 0. Writes have no effect.
This register defines the number of VCLK cycles that the ADC state machine has to wait after
releasing the ADC core from power down before starting a new conversion. Refer to Section 16.7.3
for more details.

16.10.66 ADC Event Group Channel Selection Mode Control Register(ADEVCHNSELMODECTRL)
Figure 16-95 and Table 16-72 describe the ADEVCHNSELMODECTRL register.
Figure 16-95. ADC Event Group Channel Selection Mode Control Register(ADEVCHNSELMODECTRL) [offset = 190h]
31

4

3

0

Reserved

EV_ENH_CHNSEL_MODE_ENABLE

R-0

R/W-5hLEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-72. ADC Event Group Channel Selection Mode Control Register(ADEVCHNSELMODECTRL) Field Descriptions
Bit

Field

31-4

Reserved

3-0

EV_ENH_CHNSEL_
MODE_ENABLE

Value
0

Description
Reads return 0. Writes have no effect.
Enable enhanced channel selection mode for Event group. Refer to Section 16.4.2.2 for a
description of the enhanced channel selection mode.

5h

Read: Indicates that the enhanced channel selection mode for Event group is not enabled.
The default sequential channel selection mode is used for Event group conversions.
Write: Disables the enhanced channel selection mode for Event group and enables thesequential channel selection mode.

Ah

Read: Indicates that the enhanced channel selection mode for Event group is enabled.
Write: Enables the enhanced channel selection mode for Event group.

All othervaluesSPNU517C – March 2018
Submit Documentation Feedback

Writing any value other than 5h or Ah to this field has no effect on the selected channel
selection mode for the Event group, and the ADC module continues to use the channel
selection mode that was previously programmed channel selection mode.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

561

ADC Registers

www.ti.com

16.10.67 ADC Group1 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL)
Figure 16-96 and Table 16-73 describe the ADG1CHNSELMODECTRL register.
Figure 16-96. ADC Group1 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL)[offset = 194h]
31

4

3

0

Reserved

G1_ENH_CHNSEL_MODE_ENABLE

R-0

R/W-5hLEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-73. ADC Group1 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL)
Field Descriptions
Bit

Field

31-4

Reserved

3-0

G1_ENH_CHNSEL_
MODE_ENABLE

Value
0

Description
Reads return 0. Writes have no effect.
Enable enhanced channel selection mode for Group1. Refer to Section 16.4.2.2 for a
description of the enhanced channel selection mode.

5h

Read: Indicates that the enhanced channel selection mode for Group1 is not enabled. The
default sequential channel selection mode is used for Group1 conversions.
Write: Disables the enhanced channel selection mode for Group1 and enables the sequential
channel selection mode.

Ah

Read: Indicates that the enhanced channel selection mode for Group1 is enabled.
Write: Enables the enhanced channel selection mode for Group1.

All othervaluesWriting any value other than 5h or Ah to this field has no effect on the selected channel
selection mode for the Group1, and the ADC module continues to use the channel selection
mode that was previously programmed channel selection mode.

16.10.68 ADC Group2 Channel Selection Mode Control Register (ADG2CHNSELMODECTRL)
Figure 16-97 and Table 16-74 describe the ADG2CHNSELMODECTRL register.
Figure 16-97. ADC Group2 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL)[offset = 198h]
31

4

3

0

Reserved

G2_ENH_CHNSEL_MODE_ENABLE

R-0

R/W-5hLEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-74. ADC Group2 Channel Selection Mode Control Register (ADG2CHNSELMODECTRL)
Field Descriptions
Bit

Field

31-4

Reserved

3-0

G2_ENH_CHNSEL_
MODE_ENABLE

Value
0

Description
Reads return 0. Writes have no effect.
Enable enhanced channel selection mode for Group2. Refer to Section 16.4.2.2 for a
description of the enhanced channel selection mode.

5h

Read: Indicates that the enhanced channel selection mode for Group2 is not enabled. The
default sequential channel selection mode is used for Group2 conversions.
Write: Disables the enhanced channel selection mode for Group2 and enables the sequential
channel selection mode.

Ah

Read: Indicates that the enhanced channel selection mode for Group2 is enabled.
Write: Enables the enhanced channel selection mode for Group2.

All othervalues562

Writing any value other than 5h or Ah to this field has no effect on the selected channel
selection mode for the Group2, and the ADC module continues to use the channel selection
mode that was previously programmed channel selection mode.

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.69 ADC Event Group Current Count Register (ADEVCURRCOUNT)
Figure 16-98 and Table 16-75 describe the ADEVCURRCOUNT register.
Figure 16-98. ADC Event Group Current Count Register (ADEVCURRCOUNT) [offset = 19Ch]
31

5

4

0

Reserved

EV_CURRENT_COUNT

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-75. ADC Event Group Current Count Register (ADEVCURRCOUNT) Field Descriptions
Bit

Field

31-5

Reserved

4-0

EV_CURRENT_COUNT

Value

Description

0

Reads return 0. Writes have no effect.
CURRENT_COUNT value for the Event group conversions when enhanced channel
selection mode is enabled. Refer to Section 16.4.2.2 for a description of the enhanced
channel selection mode.
This register resets to zero on any of the following conditions:
•
•
•
•
•

A peripheral reset occurs
An ADC software reset occurs via the ADC Reset Control Register (ADRSTCR)
EV_CURRENT_COUNT becomes equal to EV_MAX_COUNT
Application writes zeros to ADEVCURRCOUNT register
Event group's result RAM is reset

A read from the ADEVCURRCOUNT register returns the value of the current index into
the Event group's look-up table.

16.10.70 ADC Event Group Maximum Count Register (ADEVMAXCOUNT)
Figure 16-99 and Table 16-76 describe the ADEVMAXCOUNT register.
Figure 16-99. ADC Event Group Maximum Count Register (ADEVMAXCOUNT) [offset = 1A0h]
31

5

4

0

Reserved

EV_MAX_COUNT

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-76. ADC Event Group Maximum Count Register (ADEVMAXCOUNT) Field Descriptions
Bit

Field

31-5

Reserved

4-0

EV_MAX_COUNT

Value
0

Description
Reads return 0. Writes have no effect.
MAX_COUNT value for the Event group conversions when enhanced channel selection
mode is enabled. Refer to Section 16.4.2.2 for a description of the enhanced channel
selection mode.
It is recommended to clear the Event group's CURRENT_COUNT register(ADEVCURRCOUNT) whenever the EV_MAX_COUNT is changed.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

563

ADC Registers

www.ti.com

16.10.71 ADC Group1 Current Count Register (ADG1CURRCOUNT)
Figure 16-100 and Table 16-77 describe the ADG1CURRCOUNT register.
Figure 16-100. ADC Group1 Current Count Register (ADG1CURRCOUNT) [offset = 1A4h]
31

5

4

0

Reserved

G1_CURRENT_COUNT

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-77. ADC Group1 Current Count Register (ADG1CURRCOUNT) Field Descriptions
Bit

Field

31-5

Reserved

4-0

G1_CURRENT_COUNT

Value

Description

0

Reads return 0. Writes have no effect.
CURRENT_COUNT value for the Group1 conversions when enhanced channel selection
mode is enabled. Refer to Section 16.4.2.2 for a description of the enhanced channel
selection mode.
This register resets to zero on any of the following conditions:
•
•
•
•
•

A peripheral reset occurs
An ADC software reset occurs via the ADC Reset Control Register (ADRSTCR)
G1_CURRENT_COUNT becomes equal to G1_MAX_COUNT
Application writes zeros to ADG1CURRCOUNT register
Group1's result RAM is reset.

A read from the ADG1CURRCOUNT register returns the value of the current index into
the Group1's look-up table.

16.10.72 ADC Group1 Maximum Count Register (ADG1MAXCOUNT)
Figure 16-101 and Table 16-78 describe the ADG1MAXCOUNT register.
Figure 16-101. ADC Group1 Maximum Count Register (ADG1MAXCOUNT) [offset = 1A8h]
31

5

4

0

Reserved

G1_MAX_COUNT

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-78. ADC Group1 Maximum Count Register (ADG1MAXCOUNT) Field Descriptions
Bit

Field

31-5

Reserved

4-0

G1_MAX_COUNT

Value
0

Description
Reads return 0. Writes have no effect.
MAX_COUNT value for the Group1 conversions when enhanced channel selection mode isenabled. Refer to Section 16.4.2.2 for a description of the enhanced channel selection mode.
It is recommended to clear the Group1's CURRENT_COUNT register (ADG1CURRCOUNT)
whenever the G1_MAX_COUNT is changed.

564

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

ADC Registers

www.ti.com

16.10.73 ADC Group2 Current Count Register (ADG2CURRCOUNT)
Figure 16-102 and Table 16-79 describe the ADG2CURRCOUNT register.
Figure 16-102. ADC Group2 Current Count Register (ADG2CURRCOUNT) [offset = 1ACh]
31

5

4

0

Reserved

G2_CURRENT_COUNT

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-79. ADC Group2 Current Count Register (ADG2CURRCOUNT) Field Descriptions
Bit

Field

31-5

Reserved

4-0

G2_CURRENT_COUNT

Value

Description

0

Reads return 0. Writes have no effect.
CURRENT_COUNT value for the Group2 conversions when enhanced channel selection
mode is enabled. Refer to Section 16.4.2.2 for a description of the enhanced channel
selection mode.
This register resets to zero on any of the following conditions:
•
•
•
•
•

A peripheral reset occurs
An ADC software reset occurs via the ADC Reset Control Register (ADRSTCR)
G2_CURRENT_COUNT becomes equal to G2_MAX_COUNT
Application writes zeros to ADG2CURRCOUNT register
Group2's result RAM is reset.

A read from the ADG2CURRCOUNT register returns the value of the current index into
the Group2's look-up table.

16.10.74 ADC Group2 Maximum Count Register (ADG2MAXCOUNT)
Figure 16-103 and Table 16-80 describe the ADG2MAXCOUNT register.
Figure 16-103. ADC Group2 Maximum Count Register (ADG2MAXCOUNT) [offset = 1B0h]
31

5

4

0

Reserved

G2_MAX_COUNT

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-80. ADC Group2 Maximum Count Register (ADG2MAXCOUNT) Field Descriptions
Bit

Field

31-5

Reserved

4-0

G2_MAX_COUNT

Value
0

Description
Reads return 0. Writes have no effect.
MAX_COUNT value for the Group2 conversions when enhanced channel selection mode isenabled. Refer to Section 16.4.2.2 for a description of the enhanced channel selection mode.
It is recommended to clear the Group2's CURRENT_COUNT register (ADG2CURRCOUNT)
whenever the G2_MAX_COUNT is changed.

SPNU517C – March 2018
Submit Documentation Feedback

Analog To Digital Converter (ADC) Module
Copyright © 2018, Texas Instruments Incorporated

565

Chapter 17
SPNU517C – March 2018

High-End Timer (N2HET) ModuleThis chapter provides a general description of the High-End Timer (N2HET). The N2HET is a softwarecontrolled timer with a dedicated specialized timer micromachine and a set of 30 instructions. The N2HET
micromachine is connected to a port of up to 32 input/output (I/O) pins.
Topic

17.1
17.2
17.3
17.4
17.5

566

...........................................................................................................................
Features ..........................................................................................................
N2HET Functional Description ...........................................................................
Angle Functions ...............................................................................................
N2HET Control Registers ...................................................................................
Instruction Set..................................................................................................

High-End Timer (N2HET) Module

Page

567
572
601
605
632

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Features

www.ti.com

17.1 Features
•
•
•
•
•
•
•
•
•
•
•

Programmable timer for input and output timing functions
Reduced instruction set (30 instructions) for dedicated time and angle functions
Up to maximum of 128 96-bit words of instruction RAM protected by parity. Check your datasheet for
the actual number of words implemented.
User defined configuration of 25-bit virtual counters for timer, event counters and angle counters
7-bit hardware counters for each pin allow up to 32-bit resolution in conjunction with the 25-bit virtual
counters
Up to 32 pins usable for input signal measurements or output signal generation
Programmable suppression filter for each input pin with adjustable suppression window
Low CPU overhead and interrupt load
Efficient data transfer to or from the CPU memory with a dedicated High-End-Timer Transfer Unit
(HTU)
Diagnostic capabilities with different loopback mechanisms and pin status read back functionality
Hardware Angle Generator (HWAG)

17.1.1 Overview
The N2HET is a fifth-generation Texas Instruments (TI) advanced intelligent timer module. It provides anenhanced feature set compared to previous generations.
This timer module provides sophisticated timing functions for real-time applications such as engine
management or motor control. The high resolution hardware channels allow greater accuracy for widelyused timing functions such as period and pulse measurements, output compare, and PWMs.
The reduced instruction set, based mostly on very simple, but comprehensive instructions, improves thedefinition and development cycle time of an application and its derivatives. The N2HET breakpoint feature,
combined with various stop capabilities, makes the N2HET software application easy to debug.
17.1.1.1 Major Advantages
In addition to classic time functions such as input capture or multiple PWMs, higher-level time functions
can be easily implemented in the timer program main loop. Higher-level time functions include angle
driven wave forms, angle- and time-driven pulses, and input pulse width modulation (PWM) duty cycle
measurement.
Because of these high-level functions, data exchanges with the CPU are limited to the fundamental
parameters of the application (periods, pulse widths, angle values, and so on); and the real-time
constraints for parameter communication are dramatically minimized; for example, few interrupts are
required and asynchronous parameter updates are allowed.
The reduced instruction set and simple execution flow control make it simple and easy to develop andmodify programs. Simple algorithms can embed the entire flow control inside the N2HET program itself.
More complex algorithms can take advantage of the CPU access to the N2HET RAM. With this, the CPU
program can make calculations and can modify the timer program flow by changing the data and control
fields of the N2HET RAM. CPU access to the N2HET RAM also improves the debug and development oftimer programs. The CPU program can stop the N2HET and view the contents of the program, control,and data fields that reside in the N2HET RAM.
Finally, the modular structure provides maximum flexibility to address a wide range of applications. The
timer resolution can be selected from two cascaded prescalers to adjust the loop resolution and HR
clocks. The 32 I/O pins can provide any combination of input, period or pulse capture, and output
compare, including high resolution for each channel.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

567

Features

www.ti.com

17.1.1.2 Timer Module Structure and Execution
The timer consists of a specialized micromachine that operates a reduced instruction set. Two 25-bit
registers and three 32-bit registers are available to manipulate information such as time, event counts, andangle values. System performance is improved by a wide instruction format (96 bits) that allows theN2HET to fetch the instructional operation code and data in one system cycle, thus increasing the speed
at which data can be processed. The typical operations performed in the ALU are additions (count),
compares, and magnitude compares (higher or same).
Each instruction is made up of a 32-bit program field, a 32-bit control field and a 32-bit data field. The
N2HET execution unit fetches the complete 96-bit instruction in one cycle and executes it. All instructions
include a 9-bit field for specifying the address of the next instruction to be executed. Some instructions
also include a 9-bit conditional address, which is used as the next address whenever a particular conditionis true. This makes controlling the flow of an N2HET program inexpensive; in many cases a separate
branch instruction is not required.
The interface to the host CPU is based on both communication memory and control registers. The
communication memory includes timer instructions (program and data). This memory is typically initialized
by the CPU after reset before the timer starts execution. Once the timer program is loaded into thememory, the CPU starts the timer execution, and typically data parameters are then read or written into
the timer memory. The control registers include bits for selecting timer clock, configuring I/O pins, andcontrolling the timer module.
The programmer implements timer functions by combining instructions in specific sequences. For
instance, a single count (CNT) instruction implements a timer. A simple PWM generator can be
implemented with a two instruction sequence: CNT and compare (ECMP or MCMP). A complex timefunction may include many instructions in the sequence. The total timer program is a set of instructions
executed sequentially, one after the other. Reaching the end, the program must roll to the first instruction
so that it behaves as a loop. The time for a loop to execute is referred to as a loop resolution clock cycle
or loop resolution period (LRP). When the N2HET rolls over to the first instruction, the timer waits for theloop resolution clock to restart the execution of the loop to ensure that only one loop is executed for eachloop resolution clock.
The longest path through an N2HET program must be completed within the loop resolution clock (LRP).
Otherwise, the program will execute unpredictably because some instructions will not be executed eachtime through the loop. This effect creates a strong link between the accuracy of the timer functions and thenumber of functions (the number of instructions) the timer can perform. High resolution (HR) hardware
timer extensions are available for each of the N2HET pins to help overcome this limitation.
The high resolution hardware timers operate from the high resolution clock, which may be configured for
frequency multiples between 2 and 128 times the loop resolution clock frequency. This extending theresolution of timer events and measurements well beyond what is possible with only loop resolution
instructions.
Most of the commonly used N2HET instructions can operate either at loop resolution or high resolution;with the restriction that for each pin at most one high resolution instruction can be executed per loop
resolution period.
Certain instructions (MOV32, ADM32, ...) can modify the data fields of other instructions. This featureenables the N2HET program to implement double buffering on capture and compare functions. For
example, an ECMP compare instruction can be followed by a MOV32 instruction that is conditionally
executed when the ECMP instruction matches. The host CPU can update the next compare value by
writing asynchronously to the data field of the MOV32 instruction instead of writing directly to the data fieldof the ECMP instruction. The copy from the buffer (MOV32 data field) to the compare register (ECMP data
field) will occur when the MOV32 instruction is actually executed which occurs after the ECMP instruction
matches its current compare value. This is the same behavior as one would expect from a double bufferedhardware compare register.

568

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Features

www.ti.com

Other instructions (MOV64, RADM64) can modify both the control and data fields of other instructions.
This allows the N2HET to implement toggle functionality. For example, an ECMP instruction can befollowed by a pair of MOV64 instructions. The MOV64 instruction updates the data field of the ECMP
instruction to implement the double buffering behavior. But it also updates the control field of the ECMP
instruction which allows it to change things like pin action and the conditional address. If one MOV64
instruction configures the ECMP pin action to SET while the second changes it to CLEAR, and the two
MOV64 instructions update the conditional address to point to each other, then a single ECMP instruction
can be used to toggle a pin each time the compare match occurs.
17.1.1.3 Performance
Most instructions execute in one cycle, but a few take two or three cycles.
The N2HET can generate many complex output waveforms without CPU interrupts. Where special
algorithms are needed following a specific event (for example, missing teeth or a short/long input signal), a
minimal number of interrupts to the CPU are needed freeing the CPU for other tasks.
17.1.1.4 N2HET Compared to NHET
N2HET Enhancements from NHET include:• Eight new instructions: ADD, ADC, SUB, SBB, AND, OR, XOR, RCNT
• Full set of ALU flags Carry (C), Negative (N), Zero (Z), Overflow (V)• Branch instruction (BR) extended to support signed and unsigned arithmetic comparison conditions• Two additional 32-bit temporary working registers R, S
• New HETAND register for AND-Sharing of High Resolution structure between pairs of pins
• Improved high resolution PCNT instruction
17.1.1.5 NHET and N2HET Compared to HET
Compared to the HET module, the N2HET contains all of the enhancements described in Section 17.1.1.4
plus the following additional enhancements:• New Interrupt Enable Set and Clear registers• Capability to generate requests to the HET Transfer Unit (HTU) including new Request Enable Set andClear registers• NHET RAM parity error detection• Suppression filters for each of the 32 I/O channel and control register to configure the limiting
frequency and counter clock• Enhanced edge detection hardware that does not rely on the previous bit field in the control word of
the NHET instruction• The next, conditional and remote addresses are extended from 8 to 9 bits
• The loop resolution data fields are extended from 20 to 25 bits
• The high resolution data fields are extended from 5 to 7 bits
• Instructions with an adequate condition are able to specify the number of the request line, which
triggers the HET Transfer Unit (HTU)• The CNT instruction provides a bit, which allows to configure either an equal comparison or a greateror equal comparison when comparing the selected register value with the Max-value• The MOV32 instruction provides a new bit. If set to one the MOV32 will only perform the move, when
the Z-flag is set. If set to zero the MOV32 will perform the move whenever it is executed (independent
on the state of the Z-flag)• There is a new instruction WCAPE, which is a combination of a time stamp and an edge counter• New Open Drain, Pull Disable, and Pull Select registers

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

569

Features

www.ti.com

17.1.1.6 Instructions Features
The N2HET has the following instructions features:• N2HET uses a RISC-based specialized timer micromachine to carry out a set of 30 instructions• Instructions are implemented in a Very Long Instruction Word (VLIW) format (96-bits wide)• The N2HET program execution is self-driven by external or internal events, branching to special
routines based on input edges or output compares• Instructions point to the next instruction executed, eliminating the need for a program counter• Several instructions can change the program flow based on internal or external conditions
17.1.1.7 Program Usage
The N2HET instructions/program can be assembled with the N2HET assembler. The assembler generates
a C-structure which can be included into the main application program. The application has to copy thecontent of the structure into the N2HET RAM, set up necessary registers and start the N2HET program
execution. In addition to the C-structure, the assembler generates also a header file which makes it easy
for the main application to access the different instructions and change for example the duty cycle of a
PWM or read out the captured value of a specific signal edge.

17.1.2 Block Diagram
The N2HET module (see Figure 17-1) comprises four separate components:• Host interface• N2HET RAM• Specialized timer micromachine• I/O control (the N2HET is attached to an I/O port of up to 32 pins)

570

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Features

www.ti.com

Figure 17-1. N2HET Block Diagram
Peripheral bus

High Resolution
prescaler
HETPFR.5:0

Shadow Registers

Shadow Registers

HR clock(to IO PINCONTROL)

Loop resolution
prescaler
HETPFR.10:8

Address Decode

HOST
INTERFACE

Slave
MasterHETGCR.16
internal multiN2HET sync

Control RAM

Program RAM

Data RAMNHETRAM

CURRENT INSTRUCTION

PROGRAM FIELD
Ignore Suspend

CONTROL FIELDDATA FIELD

OFF

Stop

ON

HETGCR.17

Register A

HETGCR.0

SPECIALIZEDTIMERMICROMACHINE

Register B
Register R
Register S
Register T

HETADDR.8:0
To VIM
ComparePriority 1
HETFLG. 31:0

HETOFF1.7:0

To VIM
32 ALU

Priority 2

HETOFF2.7:0

HETPRY.31:0
Rotate/Shift by N

HETDIN.31:0
HET[31:0]32
HETDSET.31:0

I/O
PIN
CONTROLHETDOUT.31:0
HETDIR.31:0
HR clock

HETDCLR.31:0
HR block

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

571

N2HET Functional Description

www.ti.com

17.2 N2HET Functional Description
The N2HET contains RAM into which N2HET code is loaded. The N2HET code is run by the specialized
timer micromachine. The host interface and I/O control provide an interface to the CPU and external pins
respectively.

17.2.1 Specialized Timer Micromachine
The N2HET has its own instruction set, detailed in Section 17.5.1. The timer micromachine reads each
instruction from the N2HET RAM. The program and control fields contain the instructions for how thespecialized timer micromachine executes the command. For most instructions, the data field stores theinformation that needs to be manipulated.
The specialized timer micromachine executes the instructions stored in the N2HET RAM sequentially. The
N2HET program execution is self-driven by external or internal events. This means that input edges or
output compares may force the program to branch to special routines using a conditional address.
Figure 17-2 shows some of the major operations that the N2HET can carry out, namely compares,
captures, angle functions, additions, and shifts. The N2HET contains five registers (A, B, R, S, and T)
used to hold compare or counter values and are used by the N2HET instructions. Data may be taken fromthe registers or the data field for manipulation; likewise, the data may be returned to the registers or thedata field.
Figure 17-2. Specialized Timer Micromachine
From N2HET RAM

CURRENT INSTRUCTION

PROGRAM FIELD

Cont.

Off

Stop

On

DATA FIELDCONTROL FIELD

Register A

HETGCR.0

HETGCR.17

Register B
Register R
Register S
Register T

HETADDR.8:0

Priority 1
HETFLG. 31:0

Priority 2

HETOFF1.7:0
HETOFF2.7:0

To VIM
To VIM

Compare32 Bit ALU

HETPRY.31:0
Rotate/Shift By N

Specialized timer micromachine572

To I/O Control

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Functional Description

www.ti.com

17.2.1.1 Time Slots and Resolution Loop
Each instruction requires a specific number of cycles or time slots to execute. The resolution specified in
the prescaler bitfields determines the timer accuracy. All input captures, event counts, and output
compares are executed once in each resolution loop. HR captures and compares are possible (up to
N2HET clock accuracy) on the HR I/O pins. For more information about the HR I/O structure, see
Section 17.2.5.
17.2.1.2 Program Loop Time
The program loop time is the sum of all cycles used for instruction execution. This time may vary from one
loop to another if the N2HET program includes conditionally executed instructions.
The timer program restarts on every resolution loop. The start address is fixed at N2HET RAM address
00h. The longest path through a program must fit within one loop resolution period to guarantee complete
accuracy.
The last instruction of a program must branch back to the fixed start address (next program address=00h). When an N2HET program branches back to address 00h before the end of a loop resolution period,
the N2HET detects this and pauses instruction execution until the beginning of the next loop resolution
period.
The timing diagram below illustrates the program flow execution.
Figure 17-3. Program Flow Timings
Loop Resolution Period = LRPTime slot
VCLK2

...

High Res.
clock

...

Loop Res.
clock
Instructions

Program loop
1

2 34

N

1

2 34

Next program address=00h

17.2.1.3 Instruction Execution Sequence
The execution of a N2HET program begins with the first occurrence of the loop resolution clock, after the
N2HET is turned on. At the first and subsequent occurrences of the loop resolution, the instruction at
location address 00h is prefetched. The program execution begins at the occurrence of the loop resolution
clock and continues executing the instructions until the program branches to 00h location. The instruction
is prefetched at location 00h and execution flag is reset. The N2HET pauses instruction execution until theoccurrence of the loop resolution clock and resumes normal execution.
N2HET programs must be written so that they complete execution and return to address 00h before theoccurrence of the next loop resolution clock. If the N2HET program exceeds this execution time limit, thena program overflow condition occurs as described in Section 17.2.1.4.
17.2.1.4 Program Overflow Condition
If the number of time slots used in a program loop exceeds the number available time slots in one loop
resolution, the timer sets the program overflow interrupt flag located in the HETEXC2 register. To maintainsynchronization of the I/Os, this condition should never be allowed to occur in a normal operation. The
HETEXC2.PRGMOVRFLFLAG flag provides a mechanism for checking that the condition does not occur
during the debug and validation phases.
SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

573

N2HET Functional Description

www.ti.com

As Figure 17-4 illustrates, when a program overflow occurs, the currently executing N2HET program
sequence is interrupted and restarted at N2HETaddress 0 for the beginning of the next loop resolution
clock period. Also, HETEXC2.PRGMOVRFLFLAG is set.
If the instruction that caused the overflow (instruction at address 0xC in Figure 17-4) has any pin actions
selected, these pin actions will not be performed. However other actions of the instruction including
register and RAM updates will still be performed.
Figure 17-4. Use of the Overflow Interrupt Flag (HETEXC2)
Loop Resolution clock
N2HET Program
Address

0 1 2 3 7 8 A B

0

1 2 3 7 8 9 A B C 0 1 2

Program Overflow(HETEXC2.PRGMOVRFLFLAG)No Overflow.
Program returns to address 0
before start of next loop

Overflow.
Program did not returnto address 0 before startof next loop.

17.2.1.5 Architectural Restrictions on N2HET Programs
Certain architectural restrictions apply to N2HET programs:
1. The size of an N2HET program must be greater than one instruction.
2. An extra wait state is incurred by any instruction that modifies a field in the next instruction to be
executed.
3. Only one instruction (using high resolution) is allowed per high resolution pin.
4. Consecutive break points are not supported. Instructions with break points must have at least a
distance of two instructions (for example, at addresses 1, 3, 5, 7, and so on, assuming the program
executes linearly)
NOTE: While it would be unusual to code an N2HET program that is only one instruction long, it istrivial to modify such a program to meet the requirement of restriction 1. Simply add asecond instruction to the program, which may be a simple branch to zero.
To enforce restriction 3, the high resolution pin structures respond only to the first instructionthat is executed matching their pin number with hr_lr=HIGH, regardless of whether or not theen_pin_action field is ON. Subsequent instructions are ignored by the high resolution pin
structure for the remainder of the loop resolution period.

17.2.1.6 Multi-Resolution Scheme
The N2HET has the capability to virtually extend the counter width by executing instructions only once
every N loop resolution periods. This decreases the timer resolution, but extends the counter range which
may be useful when generating or measuring slow signals. Figure 17-5 illustrates how a multi-resolution
scheme may be implemented in an N2HET program. An unconditional Branch instruction and an index
sequence, using a MOV64 instruction in each low resolution loop, is required to control this particular
program flow.
NOTE: HR instructions must be placed in the main (full resolution) loop to ensure proper operation.

574

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Functional Description

www.ti.com

Figure 17-5. Multi-Resolution Operation Flow Example

Instructions withfull resolution(2 Ps)

Branch on
conditional address0Instructions withlower resolution(6 Ps)
Change conditional
address

1

2

Instructions withlower resolution(6 Ps)
Change conditional
address

Instructions withlower resolution(6 Ps)
Change conditional
address

17.2.1.7 Debug Capability
The N2HET supports breakpoints to allow you to more easily debug your N2HET program. Figure 17-6
provides an illustration of the breakpoint mechanism.
The steps to enable an N2HET breakpoint are:
1. Make sure the device nTRST pin is high, since N2HET breakpoints are disabled whenever this pin islow. (Normally this is handled automatically when a JTAG debugger is attached).
2. Attach a JTAG debugger and connect to the device that has been already programmed with theN2HET code that needs to debugged. (downloading to on-chip flash is outside the scope of thissection).
3. Execute the CPU program at least until the point where the N2HET program RAM has been initialized
by the CPU.
4. Open a memory window in the N2HET registers.
5. Make sure NHETEXC2.DEBUGSTATUSFLAG is cleared.
6. Open a memory window on the N2HET RAM
7. Set bit 22 in the program field of the instruction(s) on which you wish to break. Note that this instruction
will be executed before the N2HET is halted - slightly different from how CPU breakpoints behave.
8. Make sure the CPU and N2HET are running, if they are halted then restart the CPU through the JTAG
emulator (N2HET will start when the CPU starts).
9. Both the CPU and N2HET will halt when breakpoint is reached.
When the N2HET is halted, its state machines are frozen but all of the N2HET control registers can beaccessed through the JTAG emulator interface.
The current N2HET instruction address can be inspected by reading the HETADDR register; this should
be pointing to the instruction that caused the breakpoint.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

575

N2HET Functional Description

www.ti.com

The N2HET internal working registers (A,B,R,S,T) are not directly visible through the JTAG emulator
interface. If the content of these registers needs to be inspected, it is best to add an instruction like
MOV32 which copies the register value to the N2HET RAM. This RAM location can be inspected when the
N2HET halts.
To restart execution of both the CPU and the N2HET from the halted state:
1. Clear NHETEXC2.DEBUGSTATUSFLAG.
2. Clear bit 22 in the program field of the instruction on which the breakpoint was reached.
3. Restart the CPU through the normal JTAG emulator procedure (‘Run’ or ‘Go’). The N2HET willautomatically start executing when it sees that the CPU has exited the debug state.
Figure 17-6. Debug Control Configuration
Breakpoint bit (P22)

N2HET RAM

Device test
mode enable(nTRST)nTRST signal = 0: Functional modenTRST signal = 1: Test/Debug mode

Debug
mode
control

Debug request to CPU
Debug ack from CPU

Debug
statusbit

NOTE: Consecutive break points are not supported. Instructions with break points must have atleast a distance of two instructions (for example, at N2HET addresses 1, 3, 5, 7, and so on)

17.2.2 N2HET RAM Organization
The N2HET RAM is organized into two sections. The first contains the N2HET program itself. The second
contains parity protection bits for the N2HET program.
Each N2HET instruction is 96-bits wide but aligned to a 128-bit boundary. Instructions consist of three 32bit fields: Program, Control, and Data. Instructions are separated by a fourth unimplemented address toforce alignment to 128-bit boundaries.
The integrity of the N2HET program can be protected by Parity. Parity protection is enabled through theN2HET Parity Control Register (HETPCR).
Table 17-1 shows the base addresses for N2HET RAM and N2HET Parity RAM.
Table 17-1. N2HET RAM Base Addresses
N2HET Base Address

576

Memory0xFF46 0000

N2HET Instruction RAM (Program/Control/Data)

0xFF46 2000

N2HET Parity RAM

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Functional Description

www.ti.com

17.2.2.1 N2HET RAM Banking
Because the CPU must make updates to the N2HET RAM while the N2HET is executing, for example toupdate the duty cycle value of a PWM, it is important to understand how the N2HET RAM organization
facilitates simultaneous accesses by both the HOST CPU and the N2HET.
The N2HET RAM is implemented as 4 banks of 96-bit wide two port RAM. This means that there a total of
8 ports available; four read and four write. Normally the N2HET will use up to two of these ports at a time.
One read port is used to allow the N2HET to prefetch the next N2HET instruction while a write port may
be used to update the data or control fields that have changed as a result of executing the current
instruction.
N2HET accesses to its own internal RAM are given priority over accesses from an external host (CPU or
HTU), this makes N2HET program execution deterministic which is a critical requirement for a timer.
Most N2HET instructions execute in a single cycle. Cases where a wait state impacts the N2HET program
execution time are:
• The current N2HET instruction writes data back to the next N2HET in the execution sequence.
• The external host reads from an N2HET instruction where the automatic read-clear option is set, while
the N2HET is executing from/on the same address (See Section 17.2.4.3).
Except for the case of automatic read-clear, the external host is stalled when the host and N2HET have abank conflict. However this will typically only result in a stall of one cycle, due to the N2HET bank ordering
which is organized on the N2HET Address least significant bit boundaries (See Table 17-2).
Assuming most of the N2HET program executes linearly through the N2HET Address space; if a bankconflict does exist it is usually resolved in the next cycle as the N2HET program moves to the next bank.
N2HET programmers should avoid writing a program that accesses the same bank of N2HET RAM on
every cycle, as this could lock the external host out of the N2HET memory completely.
Table 17-2 describes the N2HET memory map, as viewed by the N2HET as well as from the memory
space of the host CPU.
Table 17-2. N2HET RAM Bank Structure
N2HET Address

Host CPU Address Space

Instruction

Program Field
Address

Control Field
Address

Data Field
Address

Reserved
AddressN2HET RAM
Bank

000h

XX0000hXX0004hXX0008hXX000Ch

A

001h

XX0010hXX0014hXX0018hXX001ChB

002h

XX0020hXX0024hXX0028hXX002ChC003h

XX0030hXX0034hXX0038hXX003Ch

D004h

XX0040hXX0044hXX0048hXX004Ch

A

:

:

:

:

:

:

03Fh

XX03F0h

XX03F4h

XX03F8h

XX03FCh

D040h

XX0400hXX0404hXX0408hXX040Ch

A

:

:

:

:

:

:

1FFh

XX1FF0h

XX1FF4h

XX1FF8h

XX1FFChD

NOTE: The external host interface supports any access size for reads, but only 32-bit writes
to the N2HET RAM are supported. Reserved addresses should not be accessed, theresult of doing so is indeterminate.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

577

N2HET Functional Description

www.ti.com

17.2.2.2 Parity Checking
The N2HET module can detect parity errors in N2HET RAM. As described in Section 17.2.2, the N2HET
allows 32-bit writes only. Therefore, N2HET RAM parity checking is implemented using one parity bit per
32-bit field in N2HET RAM.
Even or odd parity selection for N2HET parity detection can be configured in the system module. Parity
calculation and checking can be enabled/disabled by a 4-bit key in HETPCR.
During a read access to the N2HET RAM, the parity is calculated based on the data read from the RAM
and compared with the good parity value stored in the parity bits. The parity check is performed when the
N2HET execution unit makes a read access to N2HET RAM, but also when a different master (forexample, CPU or HTU) performs the read access. If any 32-bit-word fails the parity check then an error issignaled to the ESM module. The N2HET address, which generated the error is detected and is captured
in HETPAR for host system debugging. The address is frozen from being updated until it is read by thebus master.
The N2HET execution unit reads the instructions, which are 96-bit wide. They contain the program-,
control- and data-field whereby each is 32-bit wide. So when fetching N2HET instructions parity checking
is performed on three words in parallel.
If a parity error is detected in two or more words in the same cycle then only one address (word at thelower address) is captured. The captured N2HET address is always aligned to a 32-bit word boundary.
During debug, parity checking is still performed on accesses originating from the on-chip host CPU or
HTU. However, parity errors that are detected during an access initiated by the debugger are ignored.
17.2.2.3 Parity Error Detection Actions
Detection of a N2HET parity error causes the following actions:
1. An error is signaled to the ESM module.
2. The Parity Address Register (HETPAR) is loaded with the address of the faulty N2HET field.
3. N2HET execution immediately stops. (The instruction that triggered the parity error is not executed.)
4. The Turn-On/Off-Bit in the N2HET Global Configuration Register (HETGCR) is automatically cleared.
5. All N2HET internal flags are cleared.
6. All N2HET pins selected by N2HET Parity Pin Register (HETPPR) enter a predefined safe state.
7. Register HETDOUT is also updated to reflect changes in pin state due to HETPPR.
The safe state for N2HET pins selected through the HETPPR register depends on how the pin is
configured in the HETDIR, HETPDR, and HETPSL registers. Table 17-3 explains how the safe state isdetermined.
Table 17-3. Pin Safe State Upon Parity Error Detection

578

Safe StateHETDIR

HETPDRHETPSL

Drive Low

10

0

Drive High

1

0

1

High Impedance

1

1

x

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Functional Description

www.ti.com

17.2.2.4 Testing Parity Detection Logic
To test the parity detection logic, the parity RAM has to be made accessible to the CPU in order to allow adiagnostic program to insert parity errors. The control register bit HETPCR.TEST must be set in order tomake the parity RAM accessible. Once HETPCR.TEST is set, the parity bits are accessible as describedin Table 17-4.
Each 32-bit N2HET field has its own parity bit in the N2HET Parity RAM as shown in Table 17-4. There
are no parity bits for the reserved fields, since there is no physical N2HET RAM for these fields.
Table 17-4. N2HET Parity Bit Mapping
AddressN2HET1

Bits[31:1][0]

0xFF46_2000

Reads 0, Writes have no effectInstruction 0 Program Field Parity Bit

0xFF46_2004

Reads 0, Writes have no effectInstruction 0 Control Field Parity Bit

0xFF46_2008

Reads 0, Writes have no effectInstruction 0 Data Field Parity Bit

0xFF46_200C

Reads 0, Writes have no effect

Read 00xFF46_2010

Reads 0, Writes have no effectInstruction 1 Program Field Parity Bit

....

...

...

17.2.2.5 Initialization of Parity RAM
After device power up, the N2HET RAM contents including the parity bits cannot be guaranteed. In order
to avoid false parity failures due to the random state in which RAM powers up, the RAM has to be
initialized.
Before initializing the N2HET RAM, enable the N2HET parity logic by writing to HETPCR. Then the
N2HET Instruction RAM should be initialized. With parity enabled, the N2HET parity RAM will be initialized
automatically by N2HET at the same time that the N2HET instruction RAM is initialized by the CPU. Notethat loading the N2HET program with parity enabled is also effective.
Another possibility to initialize the N2HET memory and its parity bits is, to use the system module to start
the automatic initialization of all RAMs on the microcontroller. The RAMs will be initialized to ‘0’.
Depending on the even/odd parity selection, the parity bit will be calculated accordingly.

17.2.3 Time BaseAll N2HET timings are derived from VCLK2 (see Figure 17-7). Internally N2HET instructions execute at
the VCLK2 rate; but the timer loop clock and the high-resolution hardware timer clock can be scaled downfrom VCLK2. Two prescalers are available to adjust the timer loop resolution clock for the program loop,
and the high resolution (HR) clock for the HR I/O counters.
• Time Slots: The number of cycles available for instruction execution per loop. Time Slots is thenumber of VCLK2 cycles in a Loop Resolution Clock.
• High Resolution Clock: The high resolution clock is the smallest time increment with which a pin canchange it’s state or can be measured in the case of input signals. A 6-bit prescaler dividing VCLK2 bya user-defined HR prescale divide rate (hr) stored in the 6-bit HR prescale factor code (HETPFR). See
Table 17-5.
• Loop Resolution Clock: The loop resolution clock defines the timebase for executing all instructions
in a N2HET program. Since instructions can be conditionally executed, the longest path through theN2HET program must fit into one loop resolution clock period (LRP).A 3-bit prescaler dividing the HR
clock by a user-defined loop-resolution prescale divide rate (lr) stored in the 3-bit loop-resolution
prescale factor code (HETPFR). See Table 17-5.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

579

N2HET Functional Description

www.ti.com

Figure 17-7. Prescaler ConfigurationHRprescaler(6 bits)

VCLK2

Loop resolution
prescaler(3 bits)

Loop resolution
clock

HR
clock

The following abbreviations and relations are used in this document:
1. hr: high resolution prescale factor (1, 2, 3, 4,..., 63, 64)
2. lr: loop resolution prescale factor (1, 2, 4, 8, 16, 32, 64,128)
3. ts: Time slots (cycles) available for instruction execution per loop. ts = hr x lr
4. HRP = high resolution clock period HRP = hr · TVCLK2 (ns)5. LRP = loop resolution clock period LRP = lr · HRP (ns)The loop resolution period (LRP) must be selected to be larger than the number of Time slots (VCLK2
cycles) required to complete the worst-case execution path through the N2HET program. Otherwise a
program overflow condition may occur (see Section 17.2.1.4). Because of the relationship of time slots tothe hr and lr prescalers as described in item 3 above, increasing either hr or lr increases the number oftime slots available for program execution. However, lr would typically be increased first, since increasing
hr results in a decrease in timer resolution since it reduces the clock to the High Resolution IO structures.
The divide rates hr and lr can be defined in the HETPFR register. Table 17-5 lists the bit field encodings
for the prescale options.
Table 17-5. Prescale Factor Register Encoding
LRPFC - Loop Resolution

580

HRPFC - High Resolution

HETPFR[10:8]

Prescale Factor lr

HETPFR[5:0]

Prescale Factor hr

000

/1

000000

/1

001

/2

000001

/2

010

/4

000010

/3

011

/8

000011

/4

100

/16

:::::

:

101

/32

111101

/62

110

/64

111110

/63

111

/128

111111/64

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Functional Description

www.ti.com

17.2.3.1 Determining Loop Resolution
As an example, consider an application that requires high resolution of HRP = 62.5 ns, and loop resolutionof LRP = 8 μs, and needs at least 250 time slots for the N2HET application program.
Assuming VCLK2 = 32 MHz, the following shows which divide-by rates and which value in the Prescale
Factor Register (HETPFR) is required for the above requirements:2
hr
hr = 2
HRP = -------------------= ------------------ = 62.5ns
VCLK2 32MHz
lr =128lr x HRP = 128 x 62.5ns = 8 μs

ts = hr x lr = 2 x 128 = 256
hr = 2, lr = 128

HETPFR[31:0] = 0x00000701(32)

In the example above, if the loop resolution period needs to decrease from 8 μs to 4 μs, then only 128
time slots will be available for program execution. The program may need to be restructured as suggested
in Section 17.2.1.6.
17.2.3.2 The 7-Bit HR Data Field
The instruction execution examples of ECMP (Section 17.2.5.9), MCMP (Section 17.2.5.10), PCNT
(Section 17.2.5.12), PWCNT (Section 17.2.5.11), and WCAP (Section 17.2.5.13) show that the 7-bit HR
data field can generate or measure high resolution delays (HR delay) relative to the start of an LRP within
one N2HET loop LRP. The last section showed that:
LRP = lr × HRPThere are lr high resolution clock periods (HRP) within the N2HET loop resolution clock period (LRP). If lr= 128 then the HR delay can range from 0 to127 HRP clocks within LRP and all 7 bits of the HR data field
are needed. Instead of being limited to measuring and triggering events based on the loop resolution clock
period (LRP) the HR extension allows measurements and events to be described in terms fractions of an
LRP (down to 1/128 of an LRP). The only limitation is that a maximum of one HR delay can be specified
per pin during each loop resolution period.
Table 17-6 shows which bits of the HR data field are not used by the high resolution IO structures if lr isless than 128. In this case the non-relevant bits (LSBs) of the HR data fields will be one of the following:• Written as 0 for HR capture (for PCNT, WCAP)• Or interpreted as 0 for HR compare (for ECMP, MCMP. PWCNT)
Table 17-6. Interpretation of the 7-Bit HR Data Field
Loop Resolution
Prescale divide rate (lr)Bits of the HR data field (1)
D[6]

D[5]

D[4]

1

(1)

D[3]

D[2]

D[1]

D[0]

XXXXXXX

2

1/2

4

1/2

1/4

HRP Cycles delay range
0

XXXXXX

0 to 1XXXXX

0 to 3

8

1/2

1/4

1/8

16

1/2

1/4

1/8

1/16

XXXX

0 to 7

32

1/2

1/4

1/8

1/16

1/32

64

1/2

1/4

1/8

1/16

1/32

1/64

X

0 to 63

128

1/2

1/4

1/8

1/16

1/32

1/64

1/128

0 to 127

XXX

0 to 15
XX

0 to 31

X = Non-relevant bit (treated as 0)

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

581

N2HET Functional Description

www.ti.com

17.2.3.2.1 Example:
Prescale Factor Register (HETPFR) = 0x0300—> lr = 8 —> LRP = 8 · HRP
Assumption: HR data field = 0x50 = 1010000b
lr = 8 —> Bits D[3:0] are ignored —> HR delay = 101b = 5 HRPs
or by using the calculation with weight factors:
HR Delay= lr · (D[6] · 1/2 + D[5] · 1/4 + D[4] · 1/8 + D[3] · 1/16 + D[2] · 1/32 + D[1] · 1/64 + D[0] · 1/128)= 8 · (1 · 1/2 + 0 · 1/4 + 1 · 1/8 + 0 · 1/16 + 0 · 1/32 + 0 · 1/64 + 0 · 1/128)= 5 HRPs

17.2.4 Host Interface
The host interface controls all communications between timer-RAM and masters accessing the N2HET
RAM. It includes following components:
17.2.4.1 Host Accesses to N2HET RAM
The host interface supports the following types of accesses to N2HET RAM:• Read accesses of 8, 16, or 32 bits
• Read accesses of 64-bits that follow the shadow register sequence described in Section 17.2.4.2.
• Write accesses of 32 bits
Writes of 8 or 16 bits to N2HET RAM by an external host are not supported.
17.2.4.2 64-bit Read Access
The consecutive read of a control field CF(n) and a data field DF(n) of the same instruction (n) performedby the same master (for example, CPU or HTU) is always done as a simultaneous 64-bit read access.
This means that at the same time CF(n) is read, DF(n) is loaded in a shadow register. So the second
access will read DF(n) from the shadow register instead of the N2HET RAM.
In general a 64-bit read access of one master could be interrupted by a 64-bit read access of anothermaster. A total of three shadow registers are available. Therefore up to three masters can perform 64-bit
reads in an interleaved manner (Master1 CF, Master2 CF, Master3 CF, Master1 DF, Master2 DF, Master3
DF).
If all three shadow registers are activated and a 4th master performs a CF or DF read it will result in an
address error and the RAM access will not happen. Other access types by a fourth master (reads from thePF field or writes to any of the fields) will occur because these access types do not require an available
shadow register resource to complete.
17.2.4.3 Automatic Read Clear Feature
The N2HET provides a feature allowing to automatically clear the data field immediately after the data fieldis read by the external host CPU (or HTU). This feature is implemented via the control bit, which is locatedin the control field (bit C26). This is a static bit that can be used by any instruction, and specified in the
N2HET program by adding the option (control = ON) to the N2HET instruction. The automatic read clear
feature works for both 32 and 64 bit reads that follow the sequence described in Section 17.2.4.2.
When the host CPU reads the data field of that instruction, the current data value is returned to the host
CPU but the field is cleared automatically as a side effect of the read. In case the master reads data froman instruction currently executing, any new capture result is stored and this takes priority over the
automatic read clear feature, so that the new capture result is not lost.

582

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Functional Description

www.ti.com

As an example of where the automatic read clear feature is useful, consider the PCNT instruction. If this
instruction is configured for automatic read clear, then when the host CPU reads the PCNT data field it will
be cleared automatically. The host CPU can then poll the PCNT data field again, and as long as the field
returns a value of zero the host CPU program knows a new capture event has not occurred. If the data
field were not cleared, it would be impossible for the host CPU to determine whether the data field holds
data from the previous capture event, or if it happens to be data from a new capture event with the samevalue.
17.2.4.4 Emulation Mode
Emulation mode, used by the software debugger, is specified in the global configuration register. Whenthe host CPU debugger hits a breakpoint, the CPU sends a suspend signal to the modules. Two modes ofoperation are provided: suspend and ignore suspend.
• Suspend
When a suspend is issued, the timer operation stops at the end of the current timer instruction. However,
the CPU accesses to the timer RAM or control registers are freely executed.
• Ignore suspend
The timer RAM ignores the suspend signal and operates real time as normal.
17.2.4.5 Power-Down
After setting the turn-off bit in the Global Configuration Register (HETGCR), it is required to delay until theend of the timer program loop before putting the N2HET in power-down mode. This can be done by
waiting until the N2HET Current Address (HETADDR) becomes zero, before disabling the N2HET clock
source in the device’s Global Clock Module (GCM).

17.2.5 I/O Control
The N2HET has up to 32 pins. Refer to device-specific data manual for information concerning thenumber of N2HETIO available. All of the N2HET pins available are programmable as either inputs or
outputs.
These 32 I/Os have an identical structure connected to pins HET[31] to HET[0]. See Figure 17-8 for an
illustration of the I/O control. In addition all 32 I/Os have a special HR structure based on the HR clock.
This structure allows any N2HET instruction to use any of these I/Os with an accuracy of either loop
resolution or high resolution accuracy.
Figure 17-8. I/O Control
HETDIN

Timer data in

Loop
Resolution
Clock

HET[x]HETDSET

Timer data out

HETDOUTHETDCLRHETDIR

High Resolution
Structure

Pins N2HET [31] to N2HET [0] can be used by the CPU as general purpose inputs or outputs using theN2HET Data Input Register (HETDIN) for reading and N2HET Data Output Register (HETDOUT), N2HET
Data Set Register (HETDSET) or N2HET Data Clear Register (HETDCLR) for writing, depending on thetype of action to perform. The N2HET pins used as general purpose inputs are sampled on each VCLK2
period.
SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

583

N2HET Functional Description

www.ti.com

17.2.5.1 Using General Purpose I/O Data Set and Clear Registers
The N2HET Data Clear Register (HETDCLR) and N2HET Data Set Register (HETDSET) can be used tominimize the number of accesses to the peripheral to modify the output register and output pins. When theapplication needs to set or to reset some N2HET pins pins without changing the value of the others pins,
the first possibility is to read N2HET Data Output Register (HETDOUT), modify the content (AND, OR, andso on), and write the result into N2HET Data Output Register (HETDOUT). However, this read-modifywrite sequence could be interrupted by a different function modifying the same register which will result ina data coherency problem.
Using the N2HET Data Set Register (HETDSET) or N2HET Data Clear Register (HETDCLR), theapplication program must write the mask value (same mask value for the first option) to the register to set
or reset the desired pins. Any bits written as 0 to HETDSET and HETDCLR are left unchanged, which
avoids the possible coherency problem of the read-modify-write approach.
Coding Example (C program): Set pins using the 2 methods.
unsigned int MASK;
volatile unsigned int *HETDOUT,*HETDSET;...
*HETDOUT = *HETDOUT | MASK;*HETDSET = MASK;/* Variable that content the bit mask/* Pointer to HET registers*/*//* Read-modify-write of HETDOUT*//* Set the pin without reading HETDOUT */17.2.5.2 Loop Resolution Structure
The N2HET uses the pins N2HET [31:0] as input and/or output by the way of the instruction set. Actually,each pin could monitor the N2HET program or could be monitored by the N2HET program. By using the
I/O register of the N2HET, the CPU is able to interact with the N2HET program flow.
When an action (set or reset) is taken on a pin by the N2HET program, the N2HET will modify the pin at
the rising edge of the next loop resolution clock.
When an event occurs on a N2HET I/O pin, it is taken into account at the next rising edge of the loop
resolution clock.
The structure of each pin is shown in Figure 17-9.
Figure 17-9. N2HET Loop Resolution Structure for Each Bit
HETDIN

Timer data in

Loop
Resolution
Clock

HET[x]HETDSET

Timer data out

HETDOUTHETDCLRHETDIR

The example in Figure 17-10 shows a simple PWM generation with loop resolution accuracy. The
corresponding program is:
HETPFR[31:0] register = 0x201 --> lr=4 and hr=2 --> ts = 8
N2HET Program:
L00
L01

CNT
ECMP

{ next= L01, reg=A, irq=OFF, max = 4 }{ next= L00, cond_addr= L00, hr_lr=LOW, en_pin_action=ON, pin=0,
action=PULSEHI, reg=A, irq=OFF, data= 1, hr_data = 0x0 }; 25 bit compare value is 1 and the 7-bit HR compare value is 0584

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Functional Description

www.ti.com

The CNT and ECMP instructions are executed once each loop resolution cycle. When the CNT instruction
is executed, the specified register (A) and the CNT instruction data field are both incremented by one.
Next the ECMP is executed and the data field of the ECMP is compared with the specified register (A). If
both values match, then the pin action (PULSEHI in this case) will be performed in the next loop resolution
cycle. The CNT continues incrementing each loop resolution cycle. When the data field overflows (max +1), then the Z-flag is set by the CNT instruction. In the next loop resolution cycle, the Z-flag is evaluatedand the opposite pin action is performed if it is set. The Z-flag will only be active for one loop resolution
cycle.
Figure 17-10. Loop Resolution Instruction Execution Example
LRP
VCLK2
HR Clock
HRP
LR Clock
Instruction

0 1

0 1

0 1

0 1

0 1

0 1

0 1

Counter

4 0

1

2

3

4

0

1

Pin HET[0]Z-Flag25-bit ECMP
match

Pin action in next
loop resolution cycle

CNT resets
Sets Z-Flag

Opposite Pin action in
next loop resolution
cycle

17.2.5.3 High Resolution Structure
All 32 I/Os provide the HR structure based on the HR clock. The HR clock frequency is programmed
through the Prescale Factor Register (HETPFR). In addition to the standard I/O structure, all pins have HR
hardware so that these pins can be used as HR input captures (using the HR instructions PCNT or
WCAP) or HR output compares (using the HR instructions ECMP, MCMP, or PWCNT).
All five HR instructions (PCNT, WCAP, ECMP, MCMP, and PWCNT) have a dedicated hr_lr bit (highresolution/low resolution; program field bit 8) allowing operation either in HR mode or in standard
resolution mode by ignoring the HR field. By default, the hr_lr bit value is 0 which implies HR operation
mode. However, setting this bit to one allows the use of several HR instructions on a single HR pin. Only
one instruction is allowed to operate in HR mode (bit cleared to 0), but the other instructions can be usedin standard resolution mode (bit set to 1).
17.2.5.4 HR Block Diagram
Each time an HR instruction is executed on a given pin, the HR structure for that pin is programmed(which HR function to perform and on which edges it should take an action) with the information given by
the instruction. The HR structure for each pin decodes the pin select field of the instruction and programs
its HR structure if it matches.
NOTE: For each N2HET pin, only one instruction specifying a high resolution operation(hr_lr = HIGH) is allowed to execute per loop resolution period. This includes any instructions
where (hr_lr = HIGH) but (en_pin_action = OFF).
The first high resolution instruction that executes and specifies a particular pin locks out
subsequent high resolution instructions from operating on the same pin until the end fo thecurrent loop resolution period.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

585

N2HET Functional Description

www.ti.com

Figure 17-11. HR I/O Architecture
HETDIRHETDIN

Timer data in>
Loop
Resolution
Clock

HET[x]HETDSET
Timer data out

HETDOUTHETDCLR

HR
Structure
One PerPin{

HR control logic

Timer data in
HR prescale driver
Resolution clock

HR flags
HR up/down counter (7 bits)

HR compare data

HR register

17.2.5.5 HR Structures Sharing (Input)
The HR Share Control Register (HETHRSH) allows two HR structures to share the same pin for input
capture only. If these bits are set, the HR structures N and N+1 are connected to pin N. In this structure,pin N+1 remains available for general purpose input/output. See Figure 17-12.
Figure 17-12. Example of HR Structure Sharing for N2HET Pins 0/1
N2HET
HR 0

HET[0]

1
0

HET[1]

N2HET
HR 1

HR share 1/0

The following program gives an example how the HR share feature (HET[0] HR structure and HET[1] HR
structure shared) can be used for the PCNT instruction:
L00 PCNT { next=L01, type=rise2fall, pin=0 }L01 PCNT { next=L00, type=fall2rise, pin=1 }The HET[1] HR structure is also connected to the HET[0] pin. The L00_PCNT data field is able to capture
a high pulse and the L01_PCNT captures a low pulse on the same pin (N2HET [0] pin).

586

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Functional Description

www.ti.com

17.2.5.6 AND / XOR-shared HR Structure (Output)
Usually the N2HET design allows only one HR structure to generate HR edges on a pin configured as
output pin. The HETXOR register allows a logical XOR of the output signals of two consecutive HR
structures N (even) and N+1 (odd). See Figure 17-13. In this way, it is possible to generate pulses smaller
than the loop resolution clock since both edges can be generated by two independent HR structures. Thisis especially required for symmetrical PWM. See Figure 17-14.
The hardware provides a XOR gate that is connected to the outputs of the HR structure of twoconsecutive pins. In this structure, pin N+1 remains available for general purpose input/output.
Figure 17-13. XOR-shared HR I/O
HETXOR00

HET[0]N2HET HR 01

0

HET[1]N2HET HR 1
HETXOR0

The following N2HET program gives an example for one channel of the symmetrical PWM. The generated
timing is given in Figure 17-14.
MAXC .equ 22A_.equ 0 ; HR structure HR0
B_.equ 1 ; HR structure HR1
CN CNT{ next=EA, reg=A, max=MAXC }EA ECMP{ next=EB, cond_addr=MA, hr_lr=HIGH, en_pin_action=ON, pin=A_,
action=PULSELO, reg=A, data=17, hr_data=115 }MA MOV32 { next=EB, remote=EA, type=IMTOREG&REM, reg=NONE, data=17, hr_data=19 }EB ECMP{ next=CN, cond_addr=MB, hr_lr=HIGH, en_pin_action=ON, pin=B_,
action=PULSELO, reg=A, data=5, hr_data=13 }MB MOV32 { next=CN, remote=EB, type=IMTOREG&REM, reg=NONE, data=5, hr_data=13 }N2HET Settings and output signal calculation for this example program:• Pin HET[0] and HET[1] are XOR-shared.
• HETPFR[31:0] register = 0x700: lr = 128, hr = 1, time slots ts = 128• PWM period (determined by CNT_max field) = (22+1) · LRP = 2944 HRP• Length of high pulse of (HET[0] XOR HET[1]) =LH = (17·LRP + 115·HRP) - (5·LRP + 13·HRP)
With lr = 128 there is LRP = 128 · HRP, so
LH = (2291 - 653) · HRP = 1638 HRP• Duty cycle = DC = LH / PWM_period = 1638 HRP / (2944·HRP) = 55.6 %SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

587

N2HET Functional Description

www.ti.com

Figure 17-14 graphically shows the implementation of the XOR-shared feature. The first 2 waveforms(symmetrical counter and CNT) show a symmetric counter and asymmetric counter. The symmetriccounter is shown only to highlight the axis of symmetry and is not implemented in the N2HET. The
asymmetric counter, which is implemented with a CNT instruction, needs to be set to the period of thesymmetric counter. The next two waveforms (HR [0] and HR [1]) show the output of the HR structures,
which are the inputs for the XOR gate to create the PWM output on pin HET[0]. Notice that the pulses ofsignal HET[0] are centered about the axis of symmetry.
Figure 17-14. Symmetrical PWM with XOR-sharing Output
Symmetricalcounter(not in HET)

Asymmetricalcounter(CNT)

HET[0]HR0
HR1

As an alternative, HR structures may be shared using a logical AND function to combine the effects of thepin structures. The HETAND allows sharing two consecutive HR structures N (even) and N+1 (odd). See
Figure 17-15. In this structure, pin N+1 remains available for general purpose input/output.
NOTE: Setting both the HETAND bit and HETXOR bits at the same time for a given pair of N2HET
pins is not supported, must be avoided by the application program.

Figure 17-15. AND-shared HR I/OHETAND0

HET[0]

0

N2HET HR 0

1

HET[1]

0
N2HET HR 1
HETAND0

588

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Functional Description

www.ti.com

17.2.5.7 Loop Back Mode
The loop back feature can be used by the application to monitor an N2HET output signal. For example, if
a PWM is generated by HR structure 0, then a PCNT instruction assigned to HR structure 1 can measureback the pulse length or periods of the PWM output signal.
Loopback mode is activated between two high resolution structures by setting LBPSEL[x] to ‘1’ in the
HETLBPSEL Register for the corresponding structure pair. The direction of the loopback between the two
structures in the structure pair is determined by the value of LBPDIR[x] in the HETLBPDIR Register.
For example, if bit LBPSEL[0] is set to ‘1’, then HR structures 0 and 1 will be internally connected in loop
back mode. If bit LBPDIR[0] is set to ‘0’ then structure 0 will be the input and structure 1 will be the output.
Digital Loopback
Digital loopback mode is enabled by setting LBPTYPE[x] to ‘0’ in the HETLBPSEL Register for thecorresponding structure pairs. In digital loopback mode, the structure pairs are connected directly and theoutput buffers are bypassed. Therefore, the loopback values will NOT be seen on the corresponding pins.
Figure 17-16 shows an example of digital loopback between structures HR0 and HR1. LBSEL[0] has been
set to ‘1’ to enable loopback between the two structures. LBTYPE[0] has been set to ‘0’ to select digitalmode for the loopback pair. The LPBDIR[0] value will determine the direction of the loopback by selecting
which of the HR blocks is output, and which is input. The bold lines show the digital loopback path.
Figure 17-16. HR0 to HR1 Digital Loopback Logic: LBTYPE[0] = 0
Loopback values will NOT beseen on the pins in Digital
Loopback ModeHR 0

LBPDIR [0] value
determines which HR
block is input and which
is output

OutputBuffer

X

Pin 0

X

Pin 1

LBSEL[0] value
determines whether or
not loopback is enabled
for these two blocks

HR 1
OutputBufferSPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

589

N2HET Functional Description

www.ti.com

Analog Loopback
Analog loopback mode is enabled by setting LBPTYPE[x] to ‘1’ in the HETLBPSEL Register for thecorresponding structure pairs. In analog loopback mode, the structure pairs are connected outside of theoutput buffers. Therefore, the loopback values WILL be seen on the corresponding pins. Figure 17-17
shows an example of analog loopback between structures HR0 and HR1. LBSEL[0] has been set to ‘1’ toenable loopback between the two structures. LBTYPE[0] has been set to ‘1’ to select analog mode for the
loopback pair. The LPBDIR[0] value will determine the direction of the loopback by selecting which of the
HR blocks is output, and which is input. The bold lines show the analog loopback path.
Figure 17-17. HR0 to HR1 Analog Loop Back Logic: LBTYPE[0] = 1
Loopback values WIL L be seenon the pin s in Analog Loopback
Mode

LBPDIR [0] value
determ ines which HR
block is input and which
is output

HR 0

Outpu tBuffer

X

Pin 0

X

Pin 1

LBSEL[0] value
determ ines whether or
not loopback is enabled
for these two block s

HR 1

OutputBufferNote:• The loop back direction can be selected independent of the HETDIR register setting.
• The pin which is not driven by the N2HET output pin actions can still be used as normal GIO pin.

590

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Functional Description

www.ti.com

17.2.5.8 Edge Detection Input Timing
There are several timing requirements for input signals in order to be captured correctly by N2HET.
Figure 17-18 illustrates these requirements, with min and max values described in Table 17-7 (LoopResolution) and Table 17-8 (High Resolution).
Figure 17-18. N2HET Input Edge Detection
1

N2HETx3
4

2

Table 17-7. Edge Detection Input Timing for Loop Resolution Instructions
Parameter #Description

1

Input Signal Period, rising edge to rising edge

2

Input Signal Period, falling edge to falling edge

3

Input Signal, high phase

4

Input Signal, high phase

min

max

> 2 (hr) (lr) tc(VCLK2)< 225 (hr) (lr) tc(VCLK2)> (hr) (lr) tc(VCLK2)

Table 17-8. Edge Detection Input Timing for High Resolution Instructions
Parameter #Description

1

Input Signal Period, rising edge to rising edge

2

Input Signal Period, falling edge to falling edge

3

Input Signal, high phase

4

Input Signal, high phase

min

max

> (hr) (lr) tc(VCLK2)< 225 (hr) (lr) tc(VCLK2)> 2 (hr) tc(VCLK2)

These are the N2HET architectural limitations. Actual limitations will be slightly different due to on chiprouting and IO buffer delays, usually by several nanoseconds. Be sure to consult the device datasheet for
actual timings that apply to that device. Also, certain devices place additional restrictions on which pins
support the high resolution timings of Table 17-8, if present these additional limitations will also be calledout in the device datasheet.
Note that the max limit in Table 17-7 and Table 17-8 is based on the counter range of a single N2HET
instruction. The max value could be extended by employing an additional N2HET instruction to keep trackof counter overflows of the input counter / capture instruction.
17.2.5.9 PWM Generation Example 1 (in HR Mode)
The following example shows how an ECMP instruction works in high resolution mode. The example
assumes a VCLK2 of 32 MHz and the following values for the prescale divide rates (hr and lr), number oftime slots (ts), high and loop resolution period (HRP and LRP):
hr = 2, lr = 4, ts = hr × lr = 8
HRP = hr / VCLK2 = 2 / 32 MHz = 62.5 ns
LRP = (hr × lr) / VCLK2 = 8 / 32 MHz = 250 ns

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

591

N2HET Functional Description

www.ti.com

With ts = 8 there are eight time slots available for the program execution, which in this case will consist of
one CNT and one ECMP instruction as shown below. The data field of the ECMP instruction is the 32-bit
compare value, whereby the lower 7 bits represent the high resolution compare field.
When the 25-bit (loop resolution) compare matches, the HR compare value will be loaded from the 7 lower
bits of the instruction data field to the HR counter. At the next loop resolution clock, the HR counter willcount down at the HR clock frequency and perform the pin action when it reaches zero.
In the example illustrated by Figure 17-19, the 25-bit compare value is one and the 7-bit HR compare
value is two. According to Section 17.2.3.2, depending on the loop resolution divide rate (lr), only certain
bits of the 7-bit HR compare value are valid. In this example only the upper 2 bits (D[6:5]) are taken into
account. The example program below has a setting of hr_data = 100000b. Shifting this value right by 5bits, results in 10b which equals the two HR clock cycles delay mentioned above.
Figure 17-19. ECMP Execution Timings
LRP
VCLK2
HR Clock
HRP
LR Clock
Instruction

01

LR Counter4 0

HR Counter

0

0 1

01

1

01
2

2

01
3

1

01
4

01
0

1

0

HR delay

Pin HET[0]Z-FlagPin action in next
loop resolution cycle+
high resolution delay

25-bit ECMPmatch

CNT resets
Sets Z-Flag

Opposite Pin action in
next loop resolution
cycle

HETPFR[31:0] register = 0x201 --> lr=4 and hr=2 --> ts = 8
N2HET Program:
L00
L01

CNT
ECMP

{ next= L01, reg=A, irq=OFF, max = 4 }{ next= L00, cond_addr= L00, hr_lr=HIGH, en_pin_action=ON, pin=0,
action=PULSEHI, reg=A, irq=OFF, data= 1, hr_data = 0x40 }; 25 bit compare value is 1 and the 7-bit HR compare value is 2
; (Because of lr=4 the D[4:0] of the 7-bit HR field are ignored )NOTE: ECMP Opposite Actions
ECMP opposite pin actions are always synchronized to the loop resolution clock.

Changing the duty cycle of a PWM generated by an ECMP instruction, can lead to a missing pulse if thedata field of the instruction is updated directly. This can happen when it is changed from a high value to alower value while the CNT instruction has already passed the new updated lower value. To avoid this asynchronous duty cycle update can be performed with the use of an additional instruction (MOV32). This
instruction is only executed when the compare of the ECMP matches. For this the cond_addr of the ECMP
needs to point to the MOV32. On execution of the MOV32, it moves its data field into the data field of the
ECMP. The update of the duty cycle has to be made to the MOV32 data field instead of the ECMP data
field.

592

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Functional Description

www.ti.com

17.2.5.10 PWM Generation Example 2 (in HR Mode)
The MCMP instruction can also be used in HR mode. In this case operation is exactly the same as for the
ECMP instruction except that the 25-bit low resolution is now the result of a magnitude compare (greateror equal) rather than an equality compare. When the 25-bit (loop resolution) magnitude compare matches,the HR compare value will be loaded from the 7 lower bits of the instruction data field to the HR counter.
At the next loop resolution clock, the HR counter will count down at the HR clock frequency and performthe pin action when it reaches zero.
The MCMP instruction avoids the missing pulse problem of the ECMP instruction (see previous example),however the duty cycle of the signal might not be exact for one PWM period. The benefit of the MCMP isthat it avoids adding another instruction to do the duty cycle update synchronously.
17.2.5.11 Pulse Generation Example (in HR Mode)
The PWCNT instruction may also be used in HR mode to generate pulse outputs with HR width. It
generates a single pulse when the data field of the instruction is non-zero. It remains at the opposite pin
action when the data field is zero.
The PWCNT instruction operates conversely to the ECMP instruction. See Figure 17-20. For PWCNT, theopposite pin action is synchronous with the HR clock and for ECMP the pin action is synchronous with the
HR clock. The PWCNT pin action is synchronous with the loop resolution clock.
Figure 17-20. High/Low Resolution Modes for ECMP and PWCNT
ECMP

PWCNT

HR clock

LR clockPinactionOppositepin action

LR clockPinactionclock HR

Oppositepin action

17.2.5.12 Pulse Measurement Example (in HR Mode)
The PCNT instruction captures HR measurement of the high/low pulse time or periods of the input. As
shown in Figure 17-21, at marker (1) the input goes HIGH and the HR counter immediately begins tocount. The counter increments and rolls over until the falling edge on the input pin, where it captures thecounter value into the HR capture register (marker (2)). The PCNT instruction begins counting when thesynchronized input signal goes HIGH and captures both the 25-bit data field and the HR capture register
into RAM when the synchronized input falls (marker (3)).
NOTE: The HR capture value written into RAM is shifted appropriately depending on the loop
resolution prescale divide rate (lr). (See also Section 17.2.3.2.)

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

593

N2HET Functional Description

www.ti.com

Figure 17-21 shows what happens when the capture edge arrives after the HR counter overflows. This
causes the incremented value to be captured by the PCNT instruction.
Figure 17-21. PCNT Instruction Timing (With Capture Edge After HR Counter Overflow)
HR clock
Loop resclock
PCNT CFX

HR counter

0

0
1

2

3

0

1

1
2

3

2

0

0

HR capt.
reg

X

1

PCNT DFX

2

Input pin
Input pinsync’d1

2

3

Figure 17-22 shows what happens when the capture edge arrives before the HR counter overflows. This
causes the non-incremented value to be captured by the PCNT instruction.
Figure 17-22. PCNT Instruction Timing (With Capture Edge Before HR Counter Overflow)
HR clock
Loop resclock
PCNT CFX

HR counter

0

0
1

2

3

HR capt.
reg

X

PCNT DF

X

0

1

1
2

3

2

0

0
3
1

Input pin
Input pinsync’d1

594

2

High-End Timer (N2HET) Module

3

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Functional Description

www.ti.com

17.2.5.13 WCAP Execution Example (in HR Mode)
The HR capability is enabled for WCAP, if its hr_lr bit is zero. In this case the HR counter is always
enabled and is synchronized with the resolution loop. When the specified edge is detected, the current
value of the HR counter is captured in the HR capture register and written into the RAM after the next
WCAP execution. The WCAP instruction effectively time stamps the free running timer saved in a register(for example, register A shown in Figure 17-23).
Figure 17-23. WCAP Instruction Timing
LRP

HR clock
HRP

Loop resclock
Instruction

CNT WCAP

A register0

HR counter0

CNT WCAP

CNT WCAP

1
1

2

CNT WCAP

2
3

0

1

2

CNT WCAP

3
3

0

1

2

CNT WCAP

4
3

0

1

2

5
3

0

1

2

6
3

0

1

2

3

Input pin HET[0]sync’d to VCLK2
Input pin HET[0]sampled by LRP
HR capt.
reg

X

WCAP DF

X

2
4

WCAP
Previous bit
0x0240 captured to WCAP DF [31:0]

HETPFR_register = 0x0200 --> lr = 4, hr = 1, ts = 4
N2HET Program:
L00 CNT {reg=A, max=01ffffffh}
L01 WCAP {next=L00, cond_addr=L00, hr_lr=high, reg=A, event= FALL, pin=0,
data=0}In the example, the WCAP is configured to capture the counter when a falling edge occurs. The WCAP
data field (WCAP_DF) is updated in the loop succeeding the loop in which the edge occurred. The WCAP
instruction evaluates an edge by comparing its Previous bit with the sync’d input signal. In Figure 17-23,
the current value of the counter (4) is captured to WCAP_DF[31:7] and the value of the HR capture
register (2) is transferred to the valid bits (according the lr prescaler) of WCAP_DF[6:0]. Therefore, in theexample 0x0240 is captured in WCAP_DF[31:0].

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

595

N2HET Functional Description

www.ti.com

17.2.5.14 I/O Pull Control Feature
Figure 17-24. I/O Block Diagram Including Pull Control Logic
Output enable
Data out

N2HET pin

Data in
Input enable
Pull control disable

Pull control
logic

Pull selectThe following apply if the device is under reset:• Pull control: The reset pull control on the pins is enabled and a pulldown is configured.
• Input buffer: The input buffer is enabled.
• Output buffer: The output buffer is disabled.
The following apply if the device is out of reset:• Pull control: The pull control is enabled by clearing the corresponding bit in the N2HET Pull Disable
Register (HETPULDIS). In this case, if the corresponding bit in the N2HET Pull Select Register(HETPSL) is set, the pin will have a pull-up; if the bit in the N2HET Pull Select Register (HETPSL) is
cleared, the pin will have a pull-down. If the bit in the N2HET Pull Disable Register (HETPULDIS) isset, there is no pull-up or pull-down on the pin.
• Input buffer: In all cases, the input buffer is enabled.
NOTE: The pull-disable logic depends on the pin direction. If the pin is configured as output, thenthe pulls are disabled automatically. If the pin is configured as input, the pulls are enabled or
disabled depending on the pull disable register bit.

•

Output buffer: A pin can be driven as an output pin if the corresponding bit in the N2HET Direction
Register (HETDIR) is set AND the open-drain feature (N2HET Open Drain Register (HETPDR)) is notenabled. See Section 17.2.5.15 for more details.

The behavior of the input buffer, output buffer, and the pull control is summarized in Table 17-9.
Table 17-9. Input Buffer, Output Buffer, and Pull Control Behavior

(1)

596

Deviceunder
Reset?

Pin Direction(DIR) (1)Pull Disable(PULDIS) (1)Pull Select(PULSEL) (1)

Yes

X

X

No

0

0

No

0

No

0

No

0

No

1

Pull Control

Output Buffer

Input Buffer

X

EnabledDisabled

Enabled0

Pull down

Disabled

Enabled0

1

Pull up

Disabled

Enabled

10

Disabled

Disabled

Disabled

1

1

Disabled

Disabled

EnabledX

X

Disabled

EnabledEnabled

X = Don’t care

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Functional Description

www.ti.com

17.2.5.15 Open-Drain Feature
The following apply if the open-drain feature is enabled on a pin, that is, the corresponding bit in the
N2HET Open Drain Register (HETPDR) is set:
• Output buffer is enabled, if a low signal is being driven internally to the pin.
• Output buffer is disabled, if a high signal is being driven internally to the pin.
17.2.5.16 N2HET Pin Disable FeatureThis feature is provided for the safe operation of systems such as power converters and motor drives. It
can be used to inform the monitoring software of motor drive abnormalities such as over-voltage, overcurrent, and excessive temperature rise.
Figure 17-25. N2HET Pin Disable Feature Diagram
HETPINDISHETDIR

0
1

HETDOUTN2HET pin

HETDINto other N2HET pin structures
A

B

nDIS pin*
N2HET pin enable*nDIS pin realized by GIOA[5] (N2HET1)

Table 17-10 shows the conditions for the output buffer to be enabled/disabled.
Table 17-10. N2HET Pin Disable Feature
HETPINDIS.x

nDIS Pin (Input)

HET_PIN_ENA (HETGCR.24)

HETDIR.x

Output Buffer

0

X

X

0

Disabled

0

X

X

1

Enabled

1

0

X

0

Disabled

1

0

X

1

Disabled

1

1

X

0

Disabled

1

1

0

1

Disabled

1

1

1

1

EnabledAn interrupt capable device I/O pin can share the same pin as the N2HET nDIS signal. Normally GIOA[5]serves as nDIS. Check the device datasheet for the actual implementation. Sharing a pin with a GIO pinthat is Interrupt capable allows the N2HET nDIS input to also generate an interrupt to the CPU. An active
low level on nDIS is intended to signal an abnormal situation as described above. All N2HET pins, which
are selected with the N2HET Pin Disable Register (HETPINDIS), will be put in the high-impedance stateby hardware immediately after the nDIS signal is pulled low. At this time a CPU interrupt is issued, if it isenabled in the GIO pin logic.
The bit HET_PIN_ENA is automatically cleared in the failure condition and this state remains as long as
the software explicitly sets the bit again. The steps to do this are:• Software detects, by reading the HETDIN register of the GIO pin, that the level on nDIS is inactive(high).
• Software sets bit HET_PIN_ENA to deactivate the high impedance state of the pins.
SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

597

N2HET Functional Description

www.ti.com

17.2.6 Suppression Filters
Each N2HET pin is equipped with a suppression filter. If the pin is configured as an input it enables to filterout pulses shorter than a programmable duration. Each filter consists of a 10-bit down counter, whichstarts counting at a programmable preloaded value and is decremented using the VCLK2 clock.
• The counter starts counting when the filter input signal has the opposite state of the filter output signal.
The output signal is preset to the same input signal state after reset, in order to ensure proper
operation after device reset.
• Once the counter reaches zero without detecting an opposite pin state on the filter input signal, theoutput signal is set to the opposite state.
• When the counter detects an opposite pin action on the filter input signal before reaching zero, thecounter is loaded with it's preload value and the opposite pin action on the filter output signal does nottake place. The counter resumes at the preload value until it detects an opposite pin action on the
input signal again.
• Therefore the filter output signal is delayed compared to the filter input signal. The amount of delay
depends on the counter clock frequency (VCLK2) and the programmed preload value.
• The accuracy of the output signal is +/- the counter clock frequency.
Figure 17-26. Suppression Filter Counter Operation
Filter input
preload valueCounter0Filter output

Table 17-11 gives examples for a 100 MHz VCLK2 frequency.
Table 17-11. Pulse Length Examples for Suppression Filter

598

Possible values for the suppressed pulse length / frequency resulting from theprogrammable 10 bit preload value (0,1,..,1023)

Divider CCDIV

VCLK2

1

100.0 MHz

10 ns, 20 ns, …, 10.22 µs, 10.23 µs

50 MHz, 25 MHz, …, 48.924 kHz, 48.876 kHz

2

50.0 MHz

20 ns, 40 ns, …, 20.44 µs, 20.48 µs

25 MHz, 12.5 MHz, …, 24.462 kHz, 24.414 kHz

3

33.3 MHz

30 ns, 60 ns, …, 30.66 µs, 30.69 µs

16.7 MHz, 8.3 MHz, …, 16.308 kHz, 16.292 kHz

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Functional Description

www.ti.com

17.2.7 Interrupts and Exceptions
N2HET interrupts can be generated by any instruction that has an interrupt enable bit in its instruction
format. When the interrupt condition in an instruction is true and the interrupt enable bit of that instruction
is set an interrupt flag is then set in the N2HET Interrupt Flag Register (HETFLG). The address code forthis flag is determined by the five LSBs of the current timer program address. The flag in the N2HETInterrupt Flag Register (HETFLG) is set even if the corresponding bit in the N2HET Interrupt Enable Set
Register (HETINTENAS) is zero. To generate an interrupt the corresponding bit in the N2HET Interrupt
Enable Set Register (HETINTENAS) must be one. In the N2HET interrupt service routine, the main CPU
must first determine which source inside the N2HET created the interrupt request. This operation isaccelerated by the N2HET Offset Index Priority Level 1 Register (HETOFF1) or N2HET Offset Index
Priority Level 2 Register (HETOFF2) which automatically provide the number of the highest priority source
within each priority level. Reading the offset register will automatically clear the corresponding N2HET
interrupt flag which created the request. However, if the offset registers are not used by the N2HET
interrupt service routine, the flag should be cleared explicitly by the CPU once the interrupt has been
serviced.
Table 17-12. Interrupt Sources and Corresponding Offset Values in Registers HETOFFx
Source No.

Offset Value

no interrupt

0Instruction 0, 32, 64...

1

Instruction 1, 33, 65...

2

:

:

Instruction 31, 63, 95...

32

Program Overflow

33

APCNT underflow:

34

APCNT overflow

35

The instructions capable of generating interrupts are listed in Table 17-50.
Figure 17-27. Interrupt Functionality on Instruction Level
Interrupt condition
Interrupt enable
5 LSB address
code 00000

Interrupt
Flag 0Interrupt condition
Interrupt enable
5 LSB address
code 11111

Interrupt
Flag 31

Each interrupt source is associated with a priority level (level 1 or level 2). When multiple interrupts withthe same priority level occur during the same loop resolution the lowest flag bit is serviced first.
In addition to the interrupts generated by the instructions, the N2HET can generate three additional
exceptions:• Program overflow• APCNT underflow (see Section 17.3.1.2)• APCNT overflow (see Section 17.3.1.3)

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

599

N2HET Functional Description

www.ti.com

17.2.8 Hardware Priority Scheme:
If two or more software interrupts are pending on the same priority level, the offset value will show the one
with the highest priority. The interrupt with the highest priority is the one with the lower offset value. This
scheme is hard-wired in the offset encoder. See Figure 17-28.
Figure 17-28. Interrupt Flag/Priority Level ArchitecturePL
bit 0
SW Intflag 0

Offset index
encoder
for level 1priority

HET interrupt priority 1
offset vector

PL
bit 1
SW Intflag 1

PL
bit 23
SW Intflag 23

PL
bit 24
SW Intflag 24

Priority 1 global
interrupt request

To Vectored
Interrupt Manager

PL
bit 31SW Intflag 31

Priority 2 global
interrupt requestPL
bit 34
Exc Int
En 2
Exc Int
flag 2

Offset index
encoder
for level 2priority

600

High-End Timer (N2HET) Module

HET interrupt priority 2
offset vector

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Functional Description

www.ti.com

17.2.9 N2HET Requests to the HTU
As described in Section 17.5.3, the majority of the N2HET instructions are able to generate a transfer
request to the High-End Timer Transfer Unit (HTU) when an instruction-specific condition is true. One
N2HET instruction can select one of 8 request lines by programming the “reqnum” parameter. The“request” field in an instruction is used to enable, disable, or to generate a quiet request (seeSection 17.5.2) on the selected request line provided the request line is enabled using the HETREQENS
register. A request line can be disabled using the HETREQENC register. Quiet requests can be used by
the HTU. For quiet request, refer to Section 18.2.4.1.
Figure 17-29. Request Line Assignment Example
DCP[0]
DCP[1]
DCP[2]
DCP[3]
DCP[4]
DCP[5]
DCP[6]
DCP[7]HTUHTUREQ[0]HTUREQ[1]HTUREQ[2]HTUREQ[3]HTUREQ[4]HTUREQ[5]HTUREQ[6]HTUREQ[7]N2HET

17.3 Angle Functions
Engine management systems require an angle-referenced time base to synchronize signals to the engine
toothed wheel. The N2HET has a method to provide such a time base for low-end engine systems. The
reference is created by the N2HET using three dedicated instructions with fractional angle steps equal to/8, /16, /32, /64.

17.3.1 Software Angle Generator
The N2HET provides three specialized count instructions to generate an angle referenced time basesynchronized to an external reference signal (the toothed wheel signal) that defines angular reference
points.
The time base is used to generate fractional angle steps between the reference points. The step width K(= 8, 16, 32, or 64) programmed by the user defines the angle accuracy of the time base. These fractional
steps are then accumulated in an angle counter to form the absolute angle value.
The first counter, APCNT, incremented on each loop resolution clock measures the periods P(n) of theexternal signal. The second counter SCNT counts by step K up to the previous period value P(n-1),
measured by APCNT, and then recycles. The resulting period of SCNT is the fraction P(n-1) / K. The third
counter ACNT accumulates the fractions generated by SCNT.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

601

Angle Functions

www.ti.com

Figure 17-30 illustrates the basic operation of APCNT, SCNT, and ACNT.
A N2HET timer program can only have one angle generator.
Figure 17-30. Operation of N2HET Count Instructions
HET[2]
ext. ref.
signalAPCNT
periodcounterP(n-1)

P(n)

SCNT
step
counterP(n-1) P(n-1)
K
K

ACNT
angle
generator

K counts

Due to stepping, the final count of SCNT does not usually exactly match the target value P(n-1).
Figure 17-31 illustrates how SCNT compensates for this feature by starting each cycle with the remainder(final count - target) of the previous cycle.
Figure 17-31. SCNT Count Operation
Final Count = N0+nK

Target=P(n-1)

Final Count = N1+mK

E

SCNT
step
counter
N0+3K

N1+2K

N0+2K
N0+K
N0

602

N1+K
N1=N0+nK-P(n-1)

E

High-End Timer (N2HET) Module

N2=N1+mK-P(n-1)

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Angle Functions

www.ti.com

ACNT detects period variations of the external signal measured by APCNT and compensates related
counting errors. A period increase is flagged in the deceleration flag. A period decrease is flagged in theacceleration flag. If no variation is flagged, ACNT increments the counter value each time SCNT reaches
its target. If acceleration is detected, ACNT increments the counter value on each timer resolution (fastmode). If deceleration is detected, ACNT is stopped. Figure 17-32 illustrates how the compensations foracceleration and deceleration operate.
Figure 17-32. ACNT Period Variation Compensations
Deceleration

Acceleration

P(n)P(n+1)

HET[2]

ext. ref.
signalAPCNT
periodcounter
SCNT
stepcounter

ACNT

angle

generator

0

1

2

K-1

0

1

2

DCF
Deceleration
flag
ACF
Acceleration
flag

0 1
K-1

17.3.1.1 Singularities
Singularities (gaps, in this case, from missing teeth in a toothed wheel) in the external reference signal
can be masked. The start and end of singularities are defined by gap start and gap end values specified in
SCNT and ACNT. When ACNT reaches gap start or gap end, it sets/resets the gap flag.
While the gap flag is set, new periods of the external reference signal are ignored for angle computation.
SCNT uses the last period measured by APCNT just before gap start.
Figure 17-33 and Figure 17-34 illustrate the behavior of the angle generator during a gap after adeceleration or acceleration of the N2HET.
17.3.1.2 APCNT Underflow
The fastest valid external signal APCNT can accept must satisfy the following condition:
Step Width K < Period Min. Resolution (LRP)This condition fixes the maximum possible step width once the minimum period and the resolution of an
application are specified.
If a period value accidentally falls below the minimum allowed, APCNT stops the capture of these periods
and sets the APCNT underflow interrupt flag located in the exceptions interrupt control register. In such asituation, SCNT and ACNT continue to be executed using the last valid period captured by APCNT.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

603

Angle Functions

www.ti.com

17.3.1.3 APCNT Overflow
The slowest valid external signal APCNT can measure must satisfy the following condition:
Period Max Resolution < 33554431
When this limit is reached (APCNT Count equals all 1’s), APCNT stays at a maximum count (stops
counting). APCNT remains in this position until the next specified capture edge is detected on the selected
pin and sets the APCNT overflow interrupt flag located in the exceptions interrupt control register. In thissituation, SCNT and ACNT continue to be executed using the maximum APCNT period count.
Figure 17-33. N2HET Timings Associated with the Gap Flag (ACNT Deceleration)
Singularity
HET[2]
ext. ref.
signalAPCNT
periodcounter

DCF
Decel
flag

ACNT
angle
generator

GPF
Gap flag
Gap EndGap Start

Figure 17-34. N2HET Timings Associated with the Gap Flag (ACNT Acceleration)
Singularity
HET[2]
ext. ref.
signalAPCNT
periodcounter

ACF
Accel.
flag

ACNT
angle
generator

GPF
Gap flagGap Start

604

High-End Timer (N2HET) Module

Gap End

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Control Registers

www.ti.com

17.4

N2HET Control Registers
Table 17-13 summarizes all the N2HET registers. The base address for the control registers is
FFF7 B800h.
Table 17-13. N2HET Registers
OffsetAcronym

Register Description

00h

HETGCR

Global Configuration Register

Section 17.4.1

Section04h

HETPFR

Prescale Factor Register

Section 17.4.2

08h

HETADDRNHET Current Address Register

Section 17.4.3

0Ch

HETOFF1

Offset Index Priority Level 1 Register

Section 17.4.4

10h

HETOFF2

Offset Index Priority Level 2 Register

Section 17.4.5

14h

HETINTENASInterrupt Enable Set Register

Section 17.4.6

18h

HETINTENACInterrupt Enable Clear Register

Section 17.4.7

1Ch

HETEXC1

Exception Control Register 1

Section 17.4.8

20h

HETEXC2

Exception Control Register 2

Section 17.4.9

24h

HETPRYInterrupt Priority Register

Section 17.4.10

28h

HETFLGInterrupt Flag Register

Section 17.4.11

2Ch

HETAND

AND Share Control Register

Section 17.4.12

34h

HETHRSHHR Share Control Register

Section 17.4.13

38h

HETXORHR XOR-Share Control Register

Section 17.4.14

3Ch

HETREQENS

Request Enable Set Register

Section 17.4.15

40h

HETREQENC

Request Enable Clear Register

Section 17.4.16

44h

HETREQDS

Reserved. Do not use.

4Ch

HETDIRNHET Direction Register

Section 17.4.17

50h

HETDINNHET Data Input Register

Section 17.4.18

54h

HETDOUTNHET Data Output Register

Section 17.4.19

58h

HETDSETNHET Data Set Register

Section 17.4.20

5Ch

HETDCLRNHET Data Clear Register

Section 17.4.21

60h

HETPDRNHET Open Drain Register

Section 17.4.22

64h

HETPULDISNHET Pull Disable Register

Section 17.4.23

68h

HETPSLNHET Pull Select Register

Section 17.4.24

74h

HETPCR

Parity Control Register

Section 17.4.25

78h

HETPAR

Parity Address Register

Section 17.4.26

7Ch

HETPPR

Parity Pin Register

Section 17.4.27

80h

HETSFPRLDSuppression Filter Preload Register

Section 17.4.28

84h

HETSFENA

Suppression Filter Enable Register

Section 17.4.29

8Ch

HETLBPSEL

Loop Back Pair Select Register

Section 17.4.30

90h

HETLBPDIR

Loop Back Pair Direction Register

Section 17.4.31

94h

HETPINDISNHET Pin Disable Register

Section 17.4.32

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

605

N2HET Control Registers

www.ti.com

17.4.1 Global Configuration Register (HETGCR)
Figure 17-35. Global Configuration Register (HETGCR) [offset = 00h]
31

25

23

22

21

24

Reserved

HET_PIN_ENA

R-0

R/W-1

20

19

18

17

16

Reserved

MP

Reserved

PPF

IS

CMS

R-0

R/W-0

R-0

R/W-0

R/W-0

R/W-0

15

1

0

Reserved

TO

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17-14. Global Configuration Register (HETGCR) Field Descriptions
Bit

Field

31-25

Reserved

24

Value
0

HET_PIN_ENA

Description
Reads return 0. Writes have no effect.
Enables the output buffers of the pin structures depending on the value of nDIS and DIR.x when
PINDIS.x is set.
Note: This bit will automatically get cleared when nDIS pin (input port) value is 0.

23
22-21

Reserved0

No affect on the pin output buffer structure.

1

Enables the pin output buffer structure when DIR = output, PINDIS.x is set and nDIS = 1.

0

Reads return 0. Writes have no effect.

MP

Master Priority
The NHET can prioritize master accesses to N2HET RAM between the HET Transfer Unit andanother arbiter, which outputs the access of one of the remaining masters. The MP bits allow thefollowing selections:

20-19
18

Reserved

0

The HTU has lower priority to access the N2HET RAM than the arbiter output.

1h

The HTU has higher priority to access the N2HET RAM than the arbiter output.

2h

The HTU and the arbiter output use a round robin scheme to access the N2HET RAM.

3h

Reserved

0

Reads return 0. Writes have no effect.

PPF

Protect Program Fields
The PPF bit together with the Turn On/Off (TO) bit allows you to protect the program fields of all
instructions in N2HET RAM.
When TO = 0:0All masters can read and write the program fields.

1

All masters can read and write the program fields.
When TO = 1:

17

606

0

All masters can read and write the program fields.

1

The program fields are readable but not writable for all masters, which could access the N2HET
RAM. Possible masters are the CPU, HTU, and a secondary CPU (if available). Writes initiated bythese masters are discarded.

IS

Ignore Suspend
0

N2HET is stopped on suspend (the current timer instruction is completed). Timer RAM can be
freely accessed during suspend.

1

N2HET ignores suspend mode and continues operation.

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Control Registers

www.ti.com

Table 17-14. Global Configuration Register (HETGCR) Field Descriptions (continued)
Bit

Field

16

CMS

Value

Description
Clk_master/slave
This bit is used to synchronize multi-N2HETs. If set (N2HET is master), the N2HET outputs a signal
to synchronize the prescalers of the slave N2HET. By default, this bit is reset, which means a slave
configuration.
Note: This bit must be set to 1 for single-N2HET configuration.

15-1
0

Reserved

0

N2HET is configured as a slave.

1

N2HET is configured as a master.

0

Reads return 0. Writes have no effect.

TO

Turn On/Off
TO does not affect the state of the pins. You must set/reset the timer pins when they are turned off,or re-initialize the timer RAM and control registers before a reset. After a device reset, the timer isturned off by default.
0

N2HET is OFF. The timer program stops executing. Turn-off is automatically delayed until thecurrent timer program loop is completed. Turn-off does not affect the content of the timer RAM, ALU
registers, or control registers. Turn-off resets all flags.

1

N2HET is ON. The timer program execution starts synchronously to the Loop clock. In case ofmultiple N2HETs configuration, the slave N2HETs are waiting for the loop clock to come from themaster before starting execution. Then, the timer address points automatically address 00h(corresponding to program start).

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

607

N2HET Control Registers

www.ti.com

17.4.2 Prescale Factor Register (HETPFR)
Figure 17-36. Prescale Factor Register (HETPFR) [offset = 04h]
31

16
Reserved
R-0

15

11

10

8

7

6

5

0

Reserved

LRPFC

Reserved

HRPFC

R-0

R/WP-0R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 17-15. Prescale Factor Register (HETPFR) Field Descriptions
Bit

Field

31-11

Reserved

10-8

LRPFC

7-6

Reserved

5-0

HRPFC

608

Value
0

Description
Reads return 0. Writes have no effect.
Loop-Resolution Pre-scale Factor Code. LRPFC determines the loop-resolution prescale divide
rate (lr).

0

/1

1h

/2

2h

/4

3h

/8

4h

/16

5h

/32

6h

/64

7h

/128

0

Reads return 0. Writes have no effect.
High-Resolution Pre-scale Factor Code. HRPFC determines the high-resolution prescale divide
rate (hr).

0

/1

1h

/2

2h

/3

3h

/4

:

:

3Dh

/62

3Eh

/63

3Fh

/64

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Control Registers

www.ti.com

17.4.3 N2HET Current Address Register (HETADDR)
Figure 17-37. N2HET Current Address (HETADDR) [offset = 08h]
31

16
Reserved
R-0

15

9

8

0

Reserved

HETADDR

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 17-16. N2HET Current Address (HETADDR) Field Descriptions
Bit

Field

31-9

Reserved

8-0

HETADDR

Value
0

Description
Reads return 0. Writes have no effect.
N2HET Current Address
Read: Returns the current N2HET program address.
Write: No effect.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

609

N2HET Control Registers

www.ti.com

17.4.4 Offset Index Priority Level 1 Register (HETOFF1)
Figure 17-38. Offset Index Priority Level 1 Register (HETOFF1) [offset = 0Ch]
31

16
Reserved
R-0

15

6

5

0

Reserved

OFFSET1

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 17-17. Offset Index Priority Level 1 Register (HETOFF1) Field Descriptions
Bit

Field

31-6

Reserved

5-0

OFFSET1

Value
0

Description
Reads return 0. Writes have no effect.
OFFSET1 indexes the currently pending high-priority interrupt. Offset values and sources are listed inTable 17-18.
Read: Read of these bits determines the pending N2HET interrupt.
Write: No effect.
Note: In any read operation mode, the corresponding flag (in the HETFLG) is also cleared. In Emulation
mode the corresponding flag is not cleared.

Table 17-18. Interrupt Offset Encoding Format
Offset Value

610

Source No.

0

No interrupt

1

Instruction 0, 32, 64...

2

Instruction 1, 33, 65...

:

:

32

Instruction 31, 63, 95...

33

Program Overflow

34

APCNT Underflow

35

APCNT Overflow

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Control Registers

www.ti.com

17.4.5 Offset Index Priority Level 2 Register (HETOFF2)
Figure 17-39. Offset Index Priority Level 2 Register (HETOFF2) [offset = 10h]31

16
Reserved
R-0

15

6

5

0

Reserved

OFFSET2

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 17-19. Offset Index Priority Level 2 Register (HETOFF2) Field Descriptions
Bit

Field

31-6

Reserved

5-0

OFFSET2

Value
0

Description
Reads return 0. Writes have no effect.
OFFSET2 indexes the currently pending low-priority interrupt. Offset values and sources are listed inTable 17-18.
Read: Read of these bits determines the pending N2HET interrupt.
Write: No effect.
Note: In any read operation mode, the corresponding flag (in the HETFLG) is also cleared. In Emulation
mode the corresponding flag is not cleared.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

611

N2HET Control Registers

www.ti.com

17.4.6 Interrupt Enable Set Register (HETINTENAS)
Figure 17-40. Interrupt Enable Set Register (HETINTENAS) [offset = 14h]
31

16
HETINTENAS
R/W-0

15

0
HETINTENAS
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 17-20. Interrupt Enable Set Register (HETINTENAS) Field Descriptions
Bit

Field

Value

31-0

HETINTENAS[n]Description
Interrupt Enable Set bits. HETINTENAS is readable and writable in any operation mode.
Writing a 1 to bit x enables the interrupts of the N2HET instructions at N2HET addresses x+0,
x+32, x+64... Generating an interrupt requires to set bit x in HETINTENAS and to enable theinterrupt bit in one of the instructions at addresses x+0, x+32, x+64, and so on. To avoid ambiguity,
only one of the instructions x+0, x+32, x+64, and so on should have the interrupt enable bit (inside
the instruction) set. Writing a 0 to HETINTENAS has no effect.
When reading from HETINTENAS bit x gives the information, if N2HET instructions x+0, x+32,
x+64... have the interrupt enabled or disabled.

0

Read: Interrupt is disabled.
Write: No effect.

1

Read: Interrupt is enabled.
Write: Interrupt will be enabled.

17.4.7 Interrupt Enable Clear Register (HETINTENAC)
Figure 17-41. Interrupt Enable Clear (HETINTENAC) [offset = 18h]
31

16
HETINTENAC
R/W-0

15

0
HETINTENAC
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 17-21. NHET Interrupt Enable Clear (HETINTENAC) Field Descriptions
Bit

Field

31-0

HETINTENAC[n]ValueDescription
Interrupt Enable Clear bits. HETINTENAC is readable and writable in any operation mode.
Writing a 1 to bit x disables the interrupts of the N2HET instructions at N2HET addresses x+0,
x+32, x+64, and so on. (See also description in Table 17-20). Writing a 0 to HETINTENAC has noeffect.
When reading from HETINTENAC bit x gives the information, if N2HET instructions x+0, x+32,
x+64, and so on, have the interrupt enabled or disabled.

0

Read: Interrupt is disabled.
Write: No effect.

1

Read: Interrupt is enabled.
Write: Interrupt will be disabled.

612

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Control Registers

www.ti.com

17.4.8 Exception Control Register 1 (HETEXC1)
Figure 17-42. Exception Control Register (HETEXC1)
31

25

24

Reserved

APCNT_OVRFL_
ENA

R-0

R/W-0

23

17

16

Reserved

APCNT_UNRFL_
ENA

R-0

R/W-0

15

9

8

Reserved

PRGM_OVRFL_
ENA

R-0

R/W-0

7

2

1

0

Reserved

3

APCNT_OVRFL_
PRY

APCNT_UNRFL_
PRY

PRGM_OVRFL_
PRY

R-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17-22. Exception Control Register 1 (HETEXC1) Field Descriptions
Bit

Field

31-17 Reserved
24

15-9
8

Reserved

2

APCNT_OVRFL_PRY

0

APCNT Overflow Enable
APCNT overflow exception is not enabled.

1

Enables the APCNT overflow exception.

0

Reads return 0. Writes have no effect.
APCNT Underflow Enable

0

APCNT underflow exception is not enabled.

1

Enables the APCNT underflow exception.

0

Reads return 0. Writes have no effect.

PRGM_OVRFL_ENA

Reserved

Reads return 0. Writes have no effect.

0

APCNT_UNRFL_ENA

7-3

1

0

APCNT_OVRFL_ENA

23-17 Reserved
16

Value Description

Program Overflow Enable0

The program overflow exception is not enabled.

1

Enables the program overflow exception.

0

Reads return 0. Writes have no effect.
APCNT Overflow Exception Interrupt Priority

0

Exception priority level 2.

1

Exception priority level 1.

APCNT_UNRFL_PRY

APCNT Underflow Exception Interrupt Priority
0

Exception priority level 2.

1

Exception priority level 1.

PRGM_OVRFL_PRY

ProgramOverflow Exception Interrupt Priority
0

Exception priority level 2.

1

Exception priority level 1.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

613

N2HET Control Registers

www.ti.com

17.4.9 Exception Control Register 2 (HETEXC2)
Figure 17-43. Exception Control Register 2 (HETEXC2)
31

16
Reserved
R-0
15

9

8

Reserved

DEBUG_STATUS_
FLAG

R-0

R/WC-07

2

1

0Reserved

3

APCNT_OVRFL_
FLAG

APCNT_UNRFL_
FLAG

PRGM_OVRFL_
FLAG

R-0

R/W1C-0

R/W1C-0

R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset

Table 17-23. Exception Control Register 2 (HETEXC2) Field Descriptions
Bit

Field

31-9

Reserved

8

Value Description0

DEBUG_STATUS_FLAG

Reads return 0. Writes have no effect.
Debug Status Flag.
This flag is set when N2HET has stopped at a breakpoint. Also generates a debug
request to halt the ARM CPU.

0

Read: N2HET is either running, or stopped, flag cleared but not yet restarted.
Write: No effect.

1

Read: N2HET is stopped at a breakpoint.
Write: Clears the bit. To restart N2HET clear this bit and then restart the ARM CPU.
The N2HET and ARM CPU will start synchronously.

7-3

Reserved

2

APCNT_OVRFL_FLAG

0

Reads return 0. Writes have no effect.
APCNT Overflow Flag

0

Read: Exception has not occurred since the flag was cleared.
Write: No effect.

1

Read: Exception has occurred since the flag was cleared.
Write: Clears the bit.

1

APCNT_UNDFL_FLAG

APCNT Underflow Flag
0

Read: Exception has not occurred since the flag was cleared.
Write: No effect.

1

Read: Exception has occurred since the flag was cleared.
Write: Clears the bit.

0

PRGM_OVERFL_FLAG

Program Overflow Flag
0

Read: Exception has not occurred since the flag was cleared.
Write: No effect.

1

Read: Exception has occurred since the flag was cleared
Write: Clears the bit.

614

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Control Registers

www.ti.com

17.4.10 Interrupt Priority Register (HETPRY)
Figure 17-44. Interrupt Priority Register (HETPRY) [offset = 24h]
31

16
HETPRY
R/WP-015

0HETPRY
R/WP-0LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 17-24. Interrupt Priority Register (HETPRY) Field Descriptions
Bit

Field

31-0

HETPRY[n]ValueDescription
HET Interrupt Priority Level bits
Used to select the priority of any of the 32 potential interrupt sources coming from N2HET instructions.

0Interrupt priority level 2 (low level).

1

Interrupt priority level 1 (high level).

17.4.11 Interrupt Flag Register (HETFLG)
Figure 17-45. Interrupt Flag Register (HETFLG) [offset = 28h]
31

16
HETFLAG
R/W1C-0

150
HETFLAG
R/W1C-0

LEGEND: R/W = Read/Write; W1C = Write 1 to clear; X = Unknown; -n = value after reset

Table 17-25. Interrupt Flag Register (HETFLG) Field Descriptions
Bit

Field

31-0

HETFLAG[n]ValueDescription
Interrupt Flag Register Bits
Bit x is set when an interrupt condition has occurred on one of the instructions x+0, x+32, x+64, and soon. The flag position x (in the register) is decoded from the five LSBs of the instruction address thatgenerated the interrupt. The hardware will set the flag only if the interrupt enable bit (in thecorresponding instruction) is set. The flag will be set even if bit x in the Interrupt Enable Set Register(HETINTENAS) is not enabled. Enabling bit x in HETINTENAS is required if an interrupt should be
generated.
Clearing the flag can be done by writing a 1 to the flag. Alternatively reading the corresponding Offset
Index Priority Level 1 Register (HETOFF1) or Offset Index Priority Level 2 Register (HETOFF2) willautomatically clear the flag.

0

Read: No N2HET instruction with an interrupt has been reached since the flag was cleared.
Write: No effect.

1

Read: A N2HET instruction with an interrupt has been reached since the flag was cleared.
Write: Clears the bit.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

615

N2HET Control Registers

www.ti.com

17.4.12 AND Share Control Register (HETAND)
Figure 17-46. AND Share Control Register (HETAND) [offset = 2Ch]
31

16
Reserved
R-0
15

14

13

12

11

10

9

8

AND
SHARE31/30

AND
SHARE29/28

AND
SHARE27/26

AND
SHARE25/24

AND
SHARE23/22

AND
SHARE21/20

AND
SHARE19/18

AND
SHARE17/16

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

7

6

5

4

3

2

1

0

AND
SHARE15/14

AND
SHARE13/12

AND
SHARE11/10

AND
SHARE9/8

AND
SHARE7/6

AND
SHARE5/4

AND
SHARE3/2

AND
SHARE1/0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17-26. AND Share Control Register (HETAND) Field Descriptions
Bit

Field

31-16

Reserved

15-0

ANDSHARE
n+1 / nValue
0

Description
Reads return 0. Writes have no effect.
AND Share Enable
Enable the AND sharing of the same pin for two HR structures. For example, if bit ANDSHARE1/0
is set, the pin HET[0] will then be commanded by a logical AND of both HR structures 0 and 1.
Note: If HR AND SHARE bits are used, pins not connected to HR structures (the odd number pin ineach pair) can be accessed as general inputs/outputs.

616

0

HR Output of HET[n+1] and HET[n] are not AND shared.

1

HR Output of HET[n+1] and HET[n] are AND shared onto pin HET[n].

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Control Registers

www.ti.com

17.4.13 HR Share Control Register (HETHRSH)
Figure 17-47. HR Share Control Register (HETHRSH) [offset = 34h]
31

16
Reserved
R-0
15

14

13

12

11

10

9

8

HR
SHARE31/30

HR
SHARE29/28

HR
SHARE27/26

HR
SHARE25/24

HR
SHARE23/22

HR
SHARE21/20

HR
SHARE19/18

HR
SHARE17/16

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

7

6

5

4

3

2

1

0

HR
SHARE15/14

HR
SHARE13/12

HR
SHARE11/10

HR
SHARE9/8

HR
SHARE7/6

HR
SHARE5/4

HR
SHARE3/2

HR
SHARE1/0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17-27. HR Share Control Register (HETHRSH) Field Descriptions
Bit

Field

31-16

Reserved

15-0

HRSHAREn+1 / nValue
0

Description
Reads return 0. Writes have no effect.
HR Share Bits
Enables the share of the same pin for two HR structures. For example, if bit HRSHARE1/0 is set,
the pin HET[0] will then be connected to both HR input structures 0 and 1.
Note: If HR share bits are used, pins not connected to HR structures (the odd number pin in eachpair) can be accessed as general inputs/outputs.

0

HR Input of HET[n+1] and HET[n] are not shared.

1

HR Input of HET[n+1] and HET[n] are shared; both measure pin HET[n].

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

617

N2HET Control Registers

www.ti.com

17.4.14 XOR Share Control Register (HETXOR)
Figure 17-48. XOR Share Control Register (HETXOR) [offset = 38h]
31

16
Reserved
R-0
15

14

13

12

11

10

9

8

XOR
SHARE31/30

XOR
SHARE29/28

XOR
SHARE27/26

XOR
SHARE25/24

XOR
SHARE23/22

XOR
SHARE21/20

XOR
SHARE19/18

XOR
SHARE17/16

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

7

6

5

4

3

2

1

0

XOR
SHARE15/14

XOR
SHARE13/12

XOR
SHARE11/10

XOR
SHARE9/8

XOR
SHARE7/6

XOR
SHARE5/4

XOR
SHARE3/2

XOR
SHARE1/0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17-28. XOR Share Control Register (HETXOR) Field Descriptions
Bit

Field

31-16

Reserved

15-0

XORSHARE
n+1 / nValue
0

Description
Reads return 0. Writes have no effect.
XOR Share Enable
Enable the XOR-share of the same pin for two output HR structures. For example, if bit
XORSHARE1/0 is set, the pin HET[0] will then be commanded by a logical XOR of both HR
structures 0 and 1.
Note: If XOR share bits are used, pins not connected to HR structures (the odd number pin in eachpair) can be accessed as general inputs/outputs.

618

0

HR Output of HET[n+1] and HET[n] are not XOR shared.

1

HR Output of HET[n+1] and HET[n] are XOR shared onto pin HET[n].

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Control Registers

www.ti.com

17.4.15 Request Enable Set Register (HETREQENS)
Figure 17-49. Request Enable Set Register (HETREQENS) [offset = 3Ch]
31

8
Reserved
R-0
7

6

5

4

3

2

1

0

REQENA7

REQENA6

REQENA5

REQENA4

REQENA3

REQENA2

REQENA1

REQENA0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17-29. Request Enable Set Register (HETREQENS) Field Descriptions
Bit

Field

31-8

Reserved

7-0

REQENAn

Value
0

Description
Reads return 0. Writes have no effect.
Request Enable Bits0

Read: Returns the information that request line n is disabled.
Write: No effect.

1

Read: Returns the information that request line n is enabled.
Write: Writing a 1 to bit n enables the N2HET request line n.
Note: The request line triggers an HTU double control packet (DCP).
Note: A disabled request line does not memorize old requests. So there are no pending requests toservice after enabling request line n.

17.4.16 Request Enable Clear Register (HETREQENC)
Figure 17-50. Request Enable Clear Register (HETREQENC) [offset = 40h]
31

8Reserved
R-0
7

6

5

4

3

2

1

0

REQDIS7

REQDIS6

REQDIS5

REQDIS4REQDIS3

REQDIS2

REQDIS1

REQDIS0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17-30. Request Enable Clear Register (HETREQENC) Field Descriptions
Bit

Field

31-8

Reserved

7-0

REQDISn

Value
0

Description
Reads return 0. Writes have no effect.
Request Disable Bits0

Read: Returns the information that request line n is disabled.
Write: No effect.

1

Read: Returns the information that request line n is enabled.
Write: Writing a 1 to bit n disables the N2HET request line n.

NOTE: Please refer to the device data manual for information about how each of the 8 N2HET
request lines are connected to these modules. See also Section 17.2.9.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

619

N2HET Control Registers

www.ti.com

17.4.17 NHET Direction Register (HETDIR)
Figure 17-51. N2HET Direction Register (HETDIR) [offset = 4Ch]
31

16
HETDIR
R/W-0

150
HETDIR
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 17-31. N2HET Direction Register (HETDIR) Field Descriptions
Bit

Field

31-0

HETDIR[n]ValueDescription
Data direction of NHET pins0

Pin HET[n] is an input (and its output buffer is tristated).

1

Pin HET[n] is an output.

NOTE: Table 17-9 shows how the register bits of DIR, PULDIS, and PULSEL are affecting theN2HET pins.

620

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Control Registers

www.ti.com

17.4.18 N2HET Data Input Register (HETDIN)
Figure 17-52. N2HET Data Input Register (HETDIN) [offset = 50h]
31

16
HETDIN
R-x

150
HETDIN
R-x

LEGEND: R = Read only; -x = value is unknown after reset; -n = value after reset

Table 17-32. N2HET Data Input Register (HETDIN) Field Descriptions
Bit

Field

31-0

HETDIN[n]Value

Description
Data input. This bit displays the logic state of the pin.

0

Pin HET[n] is at logic low (0).

1

Pin HET[n] is at logic high (1).

17.4.19 N2HET Data Output Register (HETDOUT)
Figure 17-53. N2HET Data Output Register (HETDOUT) [offset = 54h]
31

16
HETDOUT
R/W-0

15

0
HETDOUT
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 17-33. N2HET Data Output Register (HETDOUT) Field Descriptions
Bit

Field

31-0

HETDOUT[n]Value

Description
Data out write. Writes to this bit will only take effect when the pin is configured as an output. The
current logic state of the pin will be displayed by this bit even when the pin state is changed bywriting to HETDSET or HETDCLR.

0

Pin HET[n] is at logic low (0).

1

Pin HET[n] is at logic high (1) if the HETPDR[n] bit = 0 or the output is in high-impedance state if
the HETPDR[n] bit = 1.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

621

N2HET Control Registers

www.ti.com

17.4.20 NHET Data Set Register (HETDSET)
Figure 17-54. N2HET Data Set Register (HETDSET) [offset = 58h]
31

16
HETDSET
R/WS-015

0HETDSET
R/WS-0LEGEND: R/W = Read/Write; S = Set; -n = value after reset

Table 17-34. N2HET Data Set Register (HETDSET) Field Descriptions
Bit

Field

31-0

HETDSET[n]ValueDescription
This register allows bits of HETDOUT to be set while avoiding the pitfalls of a read-modify-write
sequence in a multitasking environment.
Bits written as a logic 1 set the same bit in the HETDOUT register; while bits written as logic 0
leave the same bit in HETDOUT unchanged.
Reads from this address return the value of the HETDOUT register.

0

Write: HETDOUT[n] is unchanged.

1

Write: HETDOUT[n] is set.

17.4.21 N2HET Data Clear Register (HETDCLR)
Figure 17-55. N2HET Data Clear Register (HETDCLR) [offset = 5Ch]
31

16
HETDCLR
R/WC-015

0
HETDCLR
R/WC-0LEGEND: R/W = Read/Write; C = Clear; -n = value after reset

Table 17-35. N2HET Data Clear Register (HETDCLR) Field Descriptions
Bit

Field

31-0

HETDCLR[n]ValueDescription
This register allows bits of HETDOUT to be cleared while avoiding the pitfalls of a read-modify-write
sequence in a multitasking environment.
Bits written as a logic 1 clear the same bit in the HETDOUT register; while bits written as logic 0
leave the same bit in HETDOUT unchanged.
Reads from this address return the value of the HETDOUT register.

622

0

Write: HETDOUT[n] is unchanged.

1

Write: HETDOUT[n] is cleared.

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Control Registers

www.ti.com

17.4.22 N2HET Open Drain Register (HETPDR)
Values in this register enable or disable the open drain capability of the data pins.
Figure 17-56. N2HET Open Drain Register (HETPDR) [offset = 60h]
31

16
HETPDR
R/W-0

150
HETPDR
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 17-36. N2HET Open Drain Register (HETPDR) Field Descriptions
Bit

Field

31-0

HETPDR[n]ValueDescription
Open drain control for HET[n] pins

0

The pin is configured in push/pull mode.

1

The pin is configured in open drain mode. The HETDOUT register controls the state of the output
buffer:HETDOUT[n] = 0 The output buffer of pin HET[n] is driven low.
HETDOUT[n] = 1 The output buffer of pin HET[n] is tristated.

17.4.23 N2HET Pull Disable Register (HETPULDIS)
Values in this register enable or disable the pull-up/-down functionality of the pins.
Figure 17-57. N2HET Pull Disable Register (HETPULDIS) [offset = 64h]
31

16
HETPULDIS
R/W-n

15

0
HETPULDISR/W-n

LEGEND: R/W = Read/Write; -n = value after reset and is device dependent, see device-specific data manual

Table 17-37. N2HET Pull Disable Register (HETPULDIS) Field Descriptions
Bit

Field

31-0

HETPULDIS[n]ValueDescription
Pull disable for N2HET pins.

0

The pull functionality is enabled on pin HET[n].

1

The pull functionality is disabled on pin HET[n].

NOTE: See device data manual for which pins provide programmable pullups/pulldowns.
Table 17-9 shows how the register bits of HETDIR, HETPULDIS and HETPSL are affecting
the N2HET pins.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

623

N2HET Control Registers

www.ti.com

17.4.24 N2HET Pull Select Register (HETPSL)
Values in this register select the pull-up or pull-down functionality of the pins.
Figure 17-58. N2HET Pull Select Register (HETPSL) [offset = 68h]
31

16
HETPSL
R/W-0

15

0
HETPSL
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 17-38. N2HET Pull Select Register (HETPSL) Field Descriptions
Bit

Field

31-0

HETPSL[n]Value

Description
Pull select for NHET pins.

0

The pull down functionality is enabled if corresponding bit in HETPULDIS is 0.

1

The pull up functionality is enabled if corresponding bit in HETPULDIS is 0.

NOTE: See device data manual for which pins provide programmable pullups/pulldowns.
Table 17-9 shows how the register bits of HETDIR, HETPULDIS, and HETPSL are affecting
the N2HET pins.
The information of this register is also used to define the pin states after a parity error:
After a parity error all N2HET pins, which are

1. Defined as output pins in the HETDIR register
2. Not defined as open drain pins (with the HETPDR register)
3. Selected with the HETPPR register, will remain outputs, but automaticallychange their levels in the following way:
• If the HETPSL register specifies 0 for the pin, it will switch to low level.
• If the HETPSL register specifies 1 for the pin, it will switch to high level.
This behavior is independent of the value, which register HETPULDIS specifies for thecorresponding pin.

624

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Control Registers

www.ti.com

17.4.25 Parity Control Register (HETPCR)
Figure 17-59. Parity Control Register (HETPCR) [offset = 74h]31

16
Reserved
R-0

15

9

8

7

4

3

0

Reserved

TEST

Reserved

PARITY_ENA

R-0

R/WP-0R-0

R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 17-39. Parity Control Register (HETPCR) Field Descriptions
Bit

Field

31-9

Reserved

8

Value
0

TEST

Description
Reads return 0. Writes have no effect.
Test Bit. When this bit is set, the parity bits are mapped into the peripheral RAM frame to makethem accessible by the CPU.

0

Read: Parity bits are not memory-mapped.
Write: Disable mapping.

1

Read: Parity bits are memory-mapped.
Write: Enable mapping.

7-4

Reserved

3-0

PARITY_ENA

0

Reads return 0. Writes have no effect.
Enable/disable parity checking. This bit field enables or disables the parity check on read
operations and the parity calculation on write operations. If parity checking is enabled and a parity
error is detected the N2HET_UERR signal is activated.

5h

Read: Parity check is disabled.
Write: Disable checking.

OthersRead: Parity check is enabled.
Write: Enable checking.

NOTE: It is recommended to write Ah to enable error detection, to guard against soft errors flipping
PARITY_ENA to a disable state.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

625

N2HET Control Registers

www.ti.com

17.4.26 Parity Address Register (HETPAR)
Figure 17-60. Parity Address Register (HETPAR) [offset = 78h]
31

16
Reserved
R-0

15

13

12

2

1

0

Reserved

PAOFF

Reserved

R-0

R-X

R-0

LEGEND: R = Read only; X = Value is unchanged after reset; -n = value after reset

Table 17-40. Parity Address Register (HETPAR) Field Descriptions
Bit

Field

31-13

Reserved

12-2

PAOFF

Value
0

Description
Reads return 0. Writes have no effect.
Parity Error Address Offset. This register holds the offset address of the first parity error, which isdetected in N2HET RAM. This error address is frozen from being updated until it is read by the CPU.
During emulation mode, this address is frozen even when read.
In case of a N2HET RAM parity error, PAOFF will contain the offset address of the erroneous 32-bit
N2HET RAM field counted from the beginning of the N2HET RAM.
Examples: The 32-bit program field of instruction 0 will return 0, the 32-bit control field of instruction 0
will return 1, ..., the 32-bit control field of instruction 1 will return 5, and so on.
Read: Returns the offset address of the erroneous 32-bit word in bytes from the beginning of theN2HET RAM.
Write: No effect.

1-0

Reserved

0

Reads return 0. Writes have no effect.

NOTE: The Parity Error Address Register will not be reset, neither by PORRST nor by any otherreset source.

626

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Control Registers

www.ti.com

17.4.27 Parity Pin Register (HETPPR)
Figure 17-61. Parity Pin Register (HETPPR) [offset = 7Ch]
31

16
HETPPR
R/W-0

150
HETPPR
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 17-41. Parity Pin Register (HETPPR) Field Descriptions
Bit

Field

Value

31-0

HETPPR[n]Description
NHET Parity Pin Select Bits. Allows HET[n] pins to be configured to drive to a known state when an
N2HET parity error is detected.

0

Pin HET[n] is not affected by the detection of an N2HET parity error.

1

Pin HET[n] is driven to a known state when an N2HET parity error is detected. The known state is afunction of bits HETDIR[n], HETPSL[n], HETPDR[n] as described in Table 17-42 (this state is also
independent of HETPULDIS[n]).

Table 17-42. Known State on Parity Error
HETDIR[n]HETPDR[n]HETPSL[n]Known State on Parity Error

0

x

x

High Impedance

1

0

0

Drive Logic 0

1

0

1

Drive Logic 1

1

1

x

High Impedance

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

627

N2HET Control Registers

www.ti.com

17.4.28 Suppression Filter Preload Register (HETSFPRLD)
Figure 17-62. Suppression Filter Preload Register (HETSFPRLD) [offset = 80h]
31

18

15

10

17

16

Reserved

CCDIV

R-0

R/W-0

9

0

Reserved

CPRLD

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17-43. Suppression Filter Preload Register (HETSFPRLD) Field Descriptions
Bit

Field

31-18

Reserved

17-16

CCDIV

Value

Description

0

Reads return 0. Writes have no effect.
Counter Clock Divider
CCDIV determines the ratio between the counter clock and VCLK2.

15-10

Reserved

9-0

CPRLD

0

CCLK = VCLK21h

CCLK = VCLK2 / 22h

CCLK = VCLK2 / 3

3h

CCLK = VCLK2 / 40

Reads return 0. Writes have no effect.
Counter Preload ValueCPRLD contains the preload value for the counter clock.

17.4.29 Suppression Filter Enable Register (HETSFENA)
Figure 17-63. Suppression Filter Enable Register (HETSFENA) [offset = 84h]
31

16
HETSFENA
R/W-0

15

0
HETSFENA
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 17-44. Suppression Filter Enable Register (HETSFENA) Field Descriptions
Bit

Field

31-0

HETSFENA[n]Value

Description
Suppression Filter Enable Bits
Note: If the pin is configured as an output by the N2HET Direction Register (HETDIR), the filter is
automatically disabled independent on the bit in HETSFENA.

628

0

The input noise suppression filter for pin HET[n] is disabled.

1

The input noise suppression filter for pin HET[n] is enabled.

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Control Registers

www.ti.com

17.4.30 Loop Back Pair Select Register (HETLBPSEL)
Refer to Section 17.2.5.7 for a description of loopback test functions.
Figure 17-64. Loop Back Pair Select Register (HETLBPSEL) [offset = 8Ch]
31

30

29

28

27

26

25

24

LBPTYPE31/30 LBPTYPE29/28 LBPTYPE27/26 LBPTYPE25/24 LBPTYPE23/22 LBPTYPE21/20 LBPTYPE19/18 LBPTYPE17/16
R/W-0

R/W-0

R/W-0

23

22

21

R/W-0

LBPTYPE15/14 LBPTYPE13/12 LBPTYPE11/10
R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

20

19

18

17

16

LBPTYPE9/8

LBPTYPE7/6

LBPTYPE5/4

LBPTYPE3/2

LBPTYPE1/0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

15

14

13

12

11

10

9

8

LBPSEL31/30

LBPSEL29/28

LBPSEL27/26

LBPSEL25/24

LBPSEL23/22

LBPSEL21/20

LBPSEL19/18

LBPSEL17/16

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

7

6

5

4

3

2

1

0

LBPSEL15/14

LBPSEL13/12

LBPSEL11/10

LBPSEL9/8

LBPSEL7/6

LBPSEL5/4

LBPSEL3/2

LBPSEL1/0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 17-45. Loop Back Pair Select Register (HETLBPSEL) Field Descriptions
Bit

Field

31-16

LBPTYPE
n+1 / n

15-0

Value

Description
Loop Back Pair Type Select Bits
These bits are valid only when IODFT mode is enabled (HETLBPDIR[19:16] = 1010).

0Digital loopback is selected for HR structures on pins HET[n+1] and HET[n].

1Analog loopback is selected for HR structures on pins HET[n+1] and HET[n].

LBPSELn+1 / nLoop Back Pair Select Bits
These bits are valid only when IODFT mode is enabled (HETLBPDIR[19:16] = Ah).
If bit x is set, the HR structures on pins HET[n+1] and HET[n] are connected in a loop back mode. The
direction is given by LBPDIR n+1/n and type is selected by LBPTYPE n+1/n.
The pin which is not driven by the N2HET pin actions can still be used as normal GIO pin.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

629

N2HET Control Registers

www.ti.com

17.4.31 Loop Back Pair Direction Register (HETLBPDIR)
Refer to Section 17.2.5.7 for a description of loopback test functions.
Figure 17-65. Loop Back Pair Direction Register (HETLBPDIR) [offset = 90h]
31

20

19

16

Reserved

LBPTSTENA

R-0

R/WP-5h

15

14

13

12

11

10

9

8

LBPDIR31/30

LBPDIR29/28

LBPDIR27/26

LBPDIR25/24

LBPDIR23/22

LBPDIR21/20

LBPDIR19/18

LBPDIR17/16

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

7

6

5

4

3

2

1

0

LBPDIR15/14

LBPDIR13/12

LBPDIR11/10

LBPDIR9/8

LBPDIR7/6

LBPDIR5/4

LBPDIR3/2

LBPDIR1/0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 17-46. Loop Back Pair Direction Register (HETLBPDIR) Field Descriptions
Bit

Field

31-20

Reserved

19-16

LBPTSTENA

15-0

LBPDIRn+1 / nValue
0

Description
Reads return 0. Writes have no effect.
Loopback Test Enable Key

5h

Loopback Test is disabled.

Ah

Loopback Test is enabled.

OthersLoopback Test is disabled.
Loop Back Pair Direction Bits

0

The HR structures on pins HET[n+1] and HET[n] are internally connected with HET[n] as input andHET[n+1] as output.

1

The HR structures on pins HET[n+1] and HET[n] connected with HET[n] as output and HET[n+1]as input.

NOTE: The loop back direction can be selected independent on the HETDIR register setting.

630

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

N2HET Control Registers

www.ti.com

17.4.32 N2HET Pin Disable Register (HETPINDIS)
Figure 17-66. N2HET Pin Disable Register (HETPINDIS) [offset = 94h]
31

16
HETPINDIS
R/W-0

15

0
HETPINDIS
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 17-47. NHET Pin Disable Register (HETPINDIS) Field Descriptions
Bit

Field

31-0

HETPINDIS[n]ValueDescription
N2HET Pin Disable Bits

0

Logic low: No affect on the output buffer enable of the pin (is controlled by the value of the
HETDIR[n] bit).

1

Logic high: Output buffer of the pin is enabled if pin nDIS = 1, HET_PIN_ENA = 1, and HETDIR =1; or disabled if nDIS = 0, HETDIR = 0, or HET_PIN_ENA = 0.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

631

Instruction Set

www.ti.com

17.5 Instruction Set
17.5.1 Instruction Summary
Table 17-48 presents a list of the instructions in the N2HET instruction set. The pages following describe
each instruction in detail.
Table 17-48. Instruction Summary

(1)

632

Abbreviation

Instruction Name

OpcodeSub-Opcode

Cycles (1)ACMP

Angle Compare

Ch

-

1

ACNT

Angle Count

9h

-

2

ADCNST

Add Constant

5h

-

2

ADC

Add with Carry and Shift4h

C[25:23] = 011, C5 = 1

1-3

ADD

Add and Shift4h

C[25:23] = 001, C5 = 1

1-3

ADM32

Add Move 32

4hC[25:23] = 000, C5 = 1

1-2

AND

Bitwise AND and Shift4h

C[25:23] = 010, C5 = 1

1-3

APCNT

Angle Period Count

Eh

-

1-2

BR

Branch

Dh

-

1

CNT

Count

6h

-

1-2

DADM64

Data Add Move 64

2h

-

2

DJZ

Decrement and Jump if -zeroAhP[7:6] = 10

1

ECMP

Equality Compare0hC[6:5] = 00

1
1

ECNT

Event Count

Ah

P[7:6] = 01

MCMP

Magnitude Compare0hC[6] = 11

MOV32

Move 324h

C[5] = 0

1-2

MOV64

Move 64

1h

-

1

OR

Bitwise OR

4h

C[25:23] = 100, C5 = 1

1-3

PCNT

Period/Pulse Count

7h

-

1

PWCNT

Pulse Width Count

Ah

P[7:6] = 111

RADM64

Register Add Move 64

3h

-

1

RCNT

Ratio Count

Ah

P[7:6] = 00, P[0] = 1

3

SBB

Subtract with Borrow and Shift4h

C[25:23] =110, C[5] = 1

1-3

SCMP

Sequence Compare0hC[6:5] = 01

1

SCNT

Step Count

Ah

P[7:6] = 00, P[0] = 0

3

SHFT

Shift

Fh

C[3] = 01

SUB

Subtract and Shift4h

C[25:23] = 101, C[5] = 1

1-3
1

WCAP

Software Capture Word

Bh

-

WCAPE

Software Capture Word and Event Count

8h

-

1

XOR

Bitwise Exclusive-Or and Shift4h

C[25:23] = 111, C[5] = 1

1-3

Cycles refers to the clock cycle of the N2HET module; which on most devices is VCLK2. (Check the device datasheet
description of clock domains to confirm). If the high-resolution prescale value is set to /1, then this is also the same as thenumber of HR clock cycles.

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

Table 17-49. FLAGS Generated by Instruction
Abbreviation

Flag Name

Set/Reset by

Used byC

Carry Flag

ADC, ADD, AND, OR, RCNT, SBB, SUB, XOR

ADC, BR, SBB

N

Negative Flag

ADC, ADD, AND, OR, SBB, SUB, XOR

BR

V

Overflow Flag

ADC, ADD, AND, OR, SBB, SUB, XOR

BR

Z

Zero flag

ACNT, ADC, ADD, AND, APCNT, CNT, OR, PCNT,
SBB, SCNT, SHFT, SUB, XOR

ACMP, ACNT, BR, ECMP,
MCMP, MOV32, RCNT,
SCMP, SHFT

X

Angle Compare Match
Flag

ACMP

SCMP

SWF 0-1

Step Width flags

SCNT

ACNT

NAF

New Angle Flag

ACNT

NAF_global

New Angle Flag (global)

HWAG or NAF

ACMP, BR, CNT, ECMP,
ECNT,ACNT, SCNT

NAF_global
ACF

Acceleration Flag

ACNT

DCF

Deceleration Flag

ACNT

,ACNT, SCNTGPF

Gap Flag

ACNT

ACNT, APCNT

The instructions capable of generating software interrupts are listed in Table 17-50.
Table 17-50. Interrupt Capable Instructions
Interrupt Capable Instructions

Non Interrupt Capable Instructions

ACMP

ADC

ACNT

ADCNST

APCNT

ADD

BR

ADM32

CNT

AND

DJZ

DADM32

ECMP

MOV32

ECNT

MOV64

MCMP

OR

PCNT

RADM64

PWCNT

RCNT

SCMP

SBB

SHFT

SCNT

WCAP

SUB

WCAPE

XOR

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

633

Instruction Set

www.ti.com

17.5.2 Abbreviations, Encoding Formats and Bits
Abbreviations marked with a star (*) are available only on specific instructions.
U

Reading a bit marked with U will return an indeterminate value.

BRK

Defines the software breakpoint for the device software debugger.
Default: OFF
Location: Program field [22]nextDefines the program address of the next instruction in the program flow. This value
may be a label or an 9-bit unsigned integer.
Default: Current instruction + 1
Location: Program field [21:13]

reqnum*Defines the number of the request line (0,1,..,7) to trigger the HTU.
Default: 0
Location: Program field [25:23]

request*Allows to select between no request (NOREQ), request (GENREQ) and quiet request(QUIET). See Section 17.2.9.
Default: No request
Location: Control Field [28:27]

RequestC[28]C[27]

0

0

1

0

GENREQ01

request

QUIET

1

1

quiet requestNOREQ

To HTUno request

remote*Determines the 9-bit address of the remote address for the instruction.
Default: Current instruction + 1
Location: Program field [8:0]

control

Determines whether the immediate data field [31:0] is cleared when it is read. Whenthe bit is not set, reads do not clear the immediate data field.
Default: OFF
Location: Control field [26]en_pin_action* Determines whether the selected pin is ON so that the action occurs on the chosen pin
Default: OFF
Location: Control field [22]634

Cond_addr*

Conditional address (optional): Defines the address of the next instruction when thecondition occurs.
Default: Current address + 1
Location: Control field [21:13]

Pin*

Pin Select: Selects the pin on which the action occurs. Enter the pin number.
Default: pin 0
Location: Control field [12:8] except PCNT

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

The format CC{pin number} is also supported.
MSB
0

0

0

0

LSB

Description

0

0

0

Select HET[0]

0

0

1

Select HET[1](Each pin may be selected by writing its number in binary)
1

1

1

1

0

Select HET[30]

1

1

1

1

1

Select HET[31]Reg*Register select: Selects the register for data comparison and storage
Default: No register (None)
Location: Control field [2:1] except for CNT instruction.
Extended Register Select C[7] is available for ACMP, ADC, ADD, ADM32, AND,DADM64, ECMP, ECNT, MCMP, MOV32, MOV64, OR, RADM64, SBB, SHFT, SUB,
WCAP, WCAPE instructions.

Register

Ext Reg. C[7]

C[2]

C[1]

A

0

0

0

B

0

0

1

T

0

1

0

None

0

1

1

R

1

0

0

S

1

0

1

Reserved1

10

Reserved

1

1

1

Action*(2 Action Option) Either sets or clears the pin
Default: Clear
Location: Control Field [4]Action*Action

C[4]

Clear

0

Set

1

(4 Action Option) Either sets, clears, pulse high or pulse low on the pin. Set/clear are
single pin actions, pulse high/low include the opposite pin action.
Default: Clear
Location: Control Field [4:3]

ActionAction Type

C[4]

C[3]

Clear

Set low on match

0

0

Set

Set high on match

1

0

Pulse Low

Set low on match + reset to high on Z=1 (opposite action)

0

1

Pulse HighSet high on match + reset to low on Z=1 (opposite action)

1

1

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

635

Instruction Set

www.ti.com

hr_lr*

636

Specifies HIGH/LOW data resolution. If the hr_lr field is HIGH, the instruction uses the
hr_data field. If the hr_lr field is LOW, the hr_data field is ignored.
Default: HIGH
Location: Program Field [8]hr_lrProg. field [8]

LOW

1

HIGH

0

prv*

Specifies the initial value defining the previous bit (see Section 17.2.5.8). A value of
ON sets the previous pin-level bit to 1. A value of OFF sets the initial value of theprevious (prv) bit to 0. The prv bit is overwritten (set or reset) by the N2HET the firsttime the instruction is executed.
Default: OFF
Location: Control Field [25]cntl_val*

Available for DADM64, MOV64, and RADM64, this bit field allows the user to specify
the replacement value for the remote control field.

comp_mode*

Specifies the compare mode. This field is used with the 64-bit move instructions. This
field ensures that the sub-opcodes are moved correctly.
Default: ECMP
Location: Control Field [6:5]

Action

C[6]

C[5]

ECMP

0

0

Order

SCMP

0

1

MCMP1

1

0

REG_GE_DATA

MCMP2

1

1

DATA_GE_REG

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

17.5.3 Instruction Description
The following sections provide information for individual instructions.
Parameters in [] are optional. Refer to the N2HET assembler user guide for the default values whenparameters are omitted.
17.5.3.1 ACMP (Angle Compare)
SyntaxACMP {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][reqnum={3-bit unsigned integer}][request={NOREQ | GENREQ | QUIET}][control={OFF | ON}]
[en_pin_action={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}]pin={pin number}[action={CLEAR | SET}]
reg={A | B | R | S | T | NONE}[irq ={OFF | ON}]
data={25-bit unsigned integer}}

Figure 17-67. ACMP Program Field (P31:P0)
31

26 25

23

22

21

13 12

9

8

0

0

RequestNumberBRK

Next program address

1100

Reserved

6

3

1

9

4

9

Figure 17-68. ACMP Control Field (C31:C0)
31

29

26

25

24

Reserved

Request type

Control

Cout
prv

Reserved

En. pinactionConditional address

3

2

1

1

2

1

9

15

13

28

27

12

8

23

22

21

5

16

7

6

4

3

Conditional address

Pin select

Ext.
Reg

Reserved

PinactionRes.

Register select

2

1

Int.
ena

0

9

5

1

2

1

1

2

1

Figure 17-69. ACMP Data Field (D31:D0)
31

7

6

0

Data

Reserved

25

7

CyclesOne

Register modified

Selected register (A, B, R, S, or T)

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

637

Instruction Set

www.ti.com

The purpose of the comparison is to assert pin action when the angle compare value lies between the oldcounter value and the new counter value (held in the selected register). Since the angle increment varies
from one loop resolution clock to another, an exact equality test cannot be applied. Instead, the following
inequality is used to determine the occurrence of a match:
Old counter value < Angle compare value ≤ New counter value
This is done by performing following comparisons:Selected register value minus angle increment < angle compare value
Angle compare value ≤ Selected register value
register

Register B is recommended for typical applications with ACMP.

irq

Specifies whether or not an interrupt is generated. Specifying ON
generates an interrupt when the edge state is satisfied and the gap
flag is set. Specifying OFF prevents an interrupt from being
generated.
Default: OFF.

data

Specifies the 25-bit angle compare value.

Execution
X = 0;
If (Data <= Selected Register)
Cout = 0;
else
Cout = 1;
If (Z == 0 AND (Selected Register - Angle Inc. < Data ) AND Cout == 0) OR(Z == 1 AND (Cout_prv == 1 OR Cout == 0))){
X = 1;
If (Enable Pin Action == 1)
Selected Pin = Pin Action AT next loop resolution clock;
If (Interrupt Enable == 1)
HETFLG[n] = 1;/* n depends on address */If ([C28:C27] == 01)
Generate request on request line [P25:P23];
If ([C28:C27] == 11)
Generate quiet request on request line [P25:P23];
Jump to Conditional Address;}
else
Jump to Next Program Address;
Cout_prv = Cout (always executed)

NOTE: Carry-Out Signal (Cout)
Cout is the carry-out signal of the adder. Even if it is not a flag, it is valid all along ACMP
instruction execution.

Angle inc. = NAF_global or hardware angle generator 11-bit input.
The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 17.2.7.

638

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

17.5.3.2 ACNT (Angle Count)
SyntaxACNT {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][reqnum={3-bit unsigned integer}][request={NOREQ | GENREQ | QUIET}]
edge={RISING | FALLING}[irq ={OFF | ON}]
[control={OFF | ON}]
[prv={OFF | ON}]
gapend ={25-bit unsigned integer}
data={25-bit unsigned integer}}

Figure 17-70. ACNT Program Field (P31:P0)
31

23

22

0

26 25

RequestNumberBRK

21
Next program address

13 12
1001

9

Edge
select8

7
Reserved

1

Int.
ena

0

6

3

1

9

4

1

7

1

Figure 17-71. ACNT Control Field (C31:C0)
31

26

25

Res.

29 28

Requesttype

27

Control

Prv.

24
Gap End

0

3

2

1

1

25

Figure 17-72. ACNT Data Field (D31:D0)
31

7

6

0

Data

Reserved

25

7

CyclesTwo, as follows:• First cycle: Angle increment condition and gap end comparison.
• Second cycle: Gap start comparison.

Register modified

Register B (angle value)

Description

This instruction defines a specialized virtual timer used after SCNT and
APCNT to generate an angle-referenced time base that is synchronized to an
external signal (that is, a toothed wheel signal). ACNT uses pin HET[2]exclusively. The edge select must be the same as the HET[2] edge which wasselected in the previous APCNT.
ACNT refers to the same step width selection that the previous SCNT savedin flags SWF0 and SWF1 (see information on SCNT).
ACNT detects period variations of the external signal measured by APCNT
and compensates related count errors.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

639

Instruction Set

www.ti.com

A period increase is flagged in the deceleration flag (DCF). A period decreaseis flagged in the acceleration flag (ACF). If no variation is detected, ACNT
increments the counter value each time SCNT reaches its target.
If acceleration is detected, ACNT increments the counter value on each timer
resolution. If deceleration is detected ACNT does not increment and is thus
saturated.
ACNT also specifies the gap end angle value defining the end value of a gap
range in ACNT where period measurements in APCNT are temporarily
stopped to mask singularities in the external signal. ACNT uses register A
containing gap start and register B to store the counter value.

Edge

Specifies the edge for the input capture pin (HET[2]).

ActionP8

Edge SelectRising1

Detects a rising edge of HET[2]Falling0

Detects a falling edge of HET[2]irqON generates an interrupt when the edge state is satisfied and thegap flag is set. OFF prevents an interrupt from being generated.
Default: OFF.

gapendDefines the 25-bit end value of a gap range. The start value isdefined in the SCNT instruction.
GAPEND = (Step Value * (# of teeth on the toothed wheel + # of
missing teeth)) - 1

dataSpecifies the 25-bit initial count value for the data field.
Default: 0.

NOTE: Target Edge Field
The target edge field represents the three LSBs of data field register in case of step width =8, four LSBs for step width = 16, five LSBs for step width = 32 and six LSBs for step width =64.

Execution
Increment Condition: ((Z = 1 AND DCF = 0) OR ACF = 1)
Pin Edge Condition: Specified edge detected on HET[2]Target Edge Condition: (Target Edge field in data field = 0) AND (Angle
Increment condition is true) AND (GPF = 0)
If (Angle Increment Condition) is false{
NAF = 0;Register B = Data field register;}else{
NAF = 1;
If (Counter value != GapEnd){
Register B = Data field register + 1;
Data Field Register = Counter value + 1;}
640

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com
else{
Register B = 0;
Data Field Register = 0;
If (ACF == 0) DCF = 1;}}
Z = 0;

If (Data field register == GapStart){
GPF = 1;
If (Target Edge condition is true){
ACF = 0;If ((specified edge is not detected on pin HET[2]) AND (datafield register != 0) AND (ACF == 0) AND (angle increment conditionis true))
DCF = 1;}If (specified edge is detected on pin HET[2]){DCF = 0;If ((target_edge_field != 0) AND (DCF == 0)) ACF = 1;
If (GPF == 1){
GPF = 0;Z = 1;
If (Interrupt Enable == 1)
HETFLG[n] = 1;/* n depends on address */If ([C28:C27] == 01)
Generate request on request line [P25:P23];;
If ([C28:C27] == 11)
Generate quiet request on request line
[P25:P23];}}}
If ((target_edge_field != 0) and (pin_edge_cond == 1)){
pin_update = 0;}else if (target_edge_field == 0){
pin_update = 1;}
If (pin_update is true in next loop clock cycle){
Prv bit = Current Lx value of HET[2] pin;}
Jump to next program address;

The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 17.2.7.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

641

Instruction Set

www.ti.com

17.5.3.3 ADCNST (Add Constant)SyntaxADCNST {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][control={OFF | ON}]remote={label | 9-bit unsigned integer}
min_off={25-bit unsigned integer}
data={25-bit unsigned integer}[hr_data={7-bit unsigned integer}]}

Figure 17-73. ADCNST Program Field (P31:P0)
31

26 25

23

22

0

Reserved

BRK

21
Next program address

13 12
0101

9

8
Remote address

0

6

3

1

9

4

9

Figure 17-74. ADCNST Control Field (C31:C0)
31

27

26

25

Reserved

Control

Res.

5

1

24

0
Minimum offset

1

25

Figure 17-75. ADCNST Data Field (D31:D0)
31

642

7

6

0

Data

HR Data25

7

CyclesTwo

Register modified

Register T (implicity)

Description

ADCNST is an extension of ADM32. ADCNST first checks whether the data
field value at the remote address is zero; it then performs different adds andmoves on the result. ADCNST is typically used to extend the counter value of
PWCNT.

min_off

A 25-bit constant value that is added to the data field value if theremote data field is null.

data

A 25-bit value that is always added to the remote data field.
Default: 0.

hr_dataSeven least significant bits of the data addition to the remote data
field.
Default: 0.

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

Figure 17-76 and Figure 17-77 illustrate the behavior of ADCNST if the remote data field is zero or is not
zero.
Figure 17-76. ADCNST Operation If Remote Data Field[31:7] Is Not Zero
25-bit addition

LSBs (HR data field)

32 bits+

HR

Remote DF

HR

Immediate DF=

Remote DF

Figure 17-77. ADCNST Operation if Remote Data Field [31:7] Is Zero
25-bit addition

25 bits
Minimum offset
32 bits+

HR

Immediate DF=

HR

Remote DF

Execution
If (Remote Data Field Value [31:7] != 0)
Remote Data Field = Immediate Data Field + Remote Data Field;
else
Remote Data Field = Immediate Data Field + min. offset(bits C24:C0);
Jump to Next Program Address;

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

643

Instruction Set

www.ti.com

17.5.3.4 ADC, ADD, AND, OR, SBB, SUB, XOR
Syntax

ADC | ADD | AND | OR | SBB | SUB | XOR {src1 = { ZERO | IMM | A | B | R | S | T | ONES | REM | REMP }src2 = { ZERO | IMM | A | B | R | S | T | ONES }dest = { NONE | IMM | A | B | R | S | T }[rdest = { NONE | REM | REMP }][brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][remote={label | 9-bit unsigned integer}][control={OFF | ON}]
[init={OFF | ON}][smode = {LSL | CSL | LSR | CSR | RR | CRR | ASR }][scount = {5 bit unsigned integer}][data={25-bit unsigned integer}][hr_data={7-bit unsigned integer}]}

Figure 17-78. ADC, ADD, AND, OR, SBB, SUB, XOR Program Field (P31:P0)
31

26 25

23

22

0

Reserved

BRK

21
Next program address

13 12
0100

9

8
Remote address

0

6

3

1

9

4

9

Figure 17-79. ADC, ADD, AND, OR, SBB, SUB, XOR Control Field (C31:C0)
31

27

26

25

23

22

19

18

16

Reserved

Control

Sub Opcode

Src1

Src2

5

1

3

4

3

15

7

6

5

Smode

13

12
Scount8Ext. Reg

Init flag

1

4
Rdest

3

Register select

2

1

Res.

0

3

5

1

1

1

2

2

1

Figure 17-80. ADC, ADD, AND, OR, SBB, SUB, XOR Data Field (D31:D0)
31

644

7

6

0

Data

HR Data25

7

Cycles

One to three cycles, depending on operands selected. (See Table 17-55)

Register modified

Selected register (A, B, R, S, T, or NONE)

Description

This instruction performs the specified 32-bit arithmetic or logical operation on
operands src1 and src2, followed by an optional shift/rotate step. The result of
this operation is then stored to either an N2HET register or the immediate
data field of the instruction. In addition, the same result may be stored in aremote data field or the least signficant bits of a remote instruction program
field (P[8:0]). Bits P[8:0] of the program field are used by most instructions
formats to hold the remote address that the instruction operates on, so theability to update this field programatically makes it easier to write subroutinesthat operate on different data sets.

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

The Sub-Opcode field C[25:3] determines which type of operation (ADD, ADC, AND, OR, SBB, SUB,XOR) is executed by the instruction. A list of these operations and the corresponding Sub-Opcode
encoding can be found in Table 17-51.
All arithmetic is performed using 32-bit integer math. However, source and destination operands vary inwidth and can be 9 bits (REMP), 25 bits (A, B) or 32 bits (R,S,T, IMM, REM). Source operands REMP,
A,B are extended to 32-bits before being operated on. Also the result of the computation needs to betruncated before being written back to REMP, A, or B when these are selected as destination operands.
Table 17-52 provides a list of source operand options, how they are expanded to 32-bit integers (ifapplicable) and the control field encoding to select the option for src1 and src2 operands.
Table 17-53 provides a similar list of destination operands and their encodings. Up to two destination
operands may be selected for each instruction, a register/immediate destination and a remote destination
may be selected simultaneously. Truncation is performed independently for each destination operand as
appropriate to its size.
An optional shift step following the arithmetic or logical operation may be selected through the smode andscount operands. The shift or rotate type is selected by the smode field; Table 17-54 illustrates the options
that are available for smode. The number of bits shifted is determined by the scount operand.
Table 17-51. Arithmetic / Bitwise Logic Sub-Opcodes
Instruction

Description

Operation

Sub-Opcode

ADC

Add with Carry

result = src1 + src2 + C

C[25:23] = 011

ADD

Add

result = src1 + src2

C[25:23] = 001

AND

Bitwise Logic And

result = src1 & src2

C[25:23] = 010

OR

Bitwise Logic Or

result = src1 | src2

C[25:23] = 100

SBB

Subtract with Borrow

result = src1 - src2 - C

C[25:23] = 110

SUB

Subtract

result = src1 - src2

C[25:23] = 101

XOR

Bitwise Logic Exclusive Or

result = src1 ^ src2

C[25:23] = 111

Table 17-52. Source Operand Choices
Source Operand32-bit value

Address

src1

src2

A

{A[24:0], 0x00}

n/aC[22:19] = 0010

C[18:16] = 010

B{B[24:0], 0x00}

n/aC[22:19] = 0011

C[18:16] = 011

R

R[31:0]n/aC[22:19] = 0100

C[18:16] = 100

S

S[31:0]n/aC[22:19] = 0101

C[18:16] = 101

T

T[31:0]n/aC[22:19] = 0110

C[18:16] = 110

IMM

D[31:0]current instruction address

C[22:19] = 0001

C[18:16] = 001

ZERO

0x00000000

n/a

C[22:19] = 0000

C[18:16] = 000

ONES

0xFFFFFFFF

n/a

C[22:19] = 0111

C[18:16] = 111

REM

D[31:0]specified by remote[8:0]C[22:19] = 1000

n/a

REMP

{0x000000, P[8:0]}

specified by remote[8:0]C[22:19] = 1001

n/aTable 17-53. Destination Operand Choices
Destination
OperandStored Value

Address

dest

rdest

A

A[24:0] = result [31:8]

n/aC[7] = 0, C[2:1] = 00

n/aB

B[24:0] = result [31:8]

n/aC[7] = 0, C[2:1] = 01

n/aR

R[24:0] = result [31:0]

n/aC[7] = 1, C[2:1] = 00

n/aS

S[24:0] = result [31:0]

n/aC[7] = 1, C[2:1] = 01

n/aT

T[24:0] = result [31:0]

n/aC[7] = 0, C[2:1] = 10n/aHigh-End Timer (N2HET) Module 645

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

Table 17-53. Destination Operand Choices (continued)
Destination
OperandStored Value

Address

dest

rdest

IMM

D[31:0] = result [31:0]

current instruction address

C[7] = 1, C[2:1] = 10

n/a

NONE

n/a

n/a

C[7] = 0, C[2:1] = 11

C[4:3] = 00

REM

D[31:0] = result [31:0]

specified by remote[8:0]n/aC[4:3] = 01

REMP

P[8:0] = result [8:0]

specified by remote[8:0]n/aC[4:3] = 10

Table 17-54. Shift Encoding
Shift Type

C[15:13] smode

No Shift Applied000

Operation Illustrated (1)n/a - no shift
bit 31

ASR-Arithmetic Shift Right

001

LSL-Logical Shift Left

010

CSL-Carry Shift Left

011

LSR-Logical Shift Right

100

CSR-Carry Shift Right

101

0
IC2

S

bit 3100

bit 31

0
IC1

IC2

bit 310

bit 31

0

0

IC2

IC1

bit 31

RR - Rotate Right

0

110

IC2

bit 31

CRR – Carry Rotate Right

(1)

0
IC2

111

IC1 is the carry flag after the arithmetic / logical operation is performed. Ic2 is the updated carry flag after the shift operation is
performed. s is the sign bit.

Table 17-55. Execution Time for ADC, ADD, AND, OR, SBB, SUB, XOR Instructions

646

src1

dest

rdest

remote[8:0]

Cycle
s

ZERO, IMM, A, B, R, S, T, or ONES

A,B,R,S,T, or NONE

NONE

! = next[8:0]

1

REM or REMP

A,B,R,S,T, or NONE

NONE!= next[8:0]2ZERO, IMM, A, B, R, S, T, or ONES

IMM

REM

!= next[8:0]2ZERO, IMM, A, B, R, S, T, or ONES

A,B,R,S,T, or NONE

REMP!= next[8:0]2ZERO, IMM, A, B, R, S, T, or ONES

A,B,R,S,T, or NONE

NONE== next[8:0]2

REM or REMP

IMM

REM

x

3

x

IMM

REMP

x

3

REM or REMPx

REM== next[8:0]

3

x

x

REMP

== next[8:0]3High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

Execution/ Notes: IR1, IR2 are 32-bit intermediate results// SRC1, SRC2 are 32-bit sources selected//by fields src1, src2// IC1, IC2 are intermediate values of the carry flag// IZ1, IZ2 are intermediate values of the zero flag// IN1, IN2 are intermediate values of the negative flag// IV1, IV2 are intermediate values of the overflow flag// scount is the shift count (0 to 31) specified by C12:C8/********** SOURCE OPERAND DECODING STAGE **********/
switch (C22:C19){
case 0000:SRC1[31:0] = 0x00000000
case 0001:SRC1[31:0] = Immediate Data Field D[31:0]
case 0010:SRC1[31:8] = A[24:0]; SRC1[6:0] = 0
case 0011:SRC1[31:8] = B[24:0]; SRC1[6:0] = 0
case 0100:SRC1[31:0] = R[31:0]
case 0101:SRC1[31:0] = S[31:0]
case 0110:SRC1[31:0] = T[31:0]
case 0111:SRC1[31:0] = 0xFFFFFFFF
case 1000:SRC1[31:0] = Remote Data Field D[31:0]
case 1001:SRC1[31:9] = 0; SRC1[8:0] = Remote Program Field P[8:0]}switch (C18:C16){
case 000:SRC2[31:0] = 0x00000000
case 001:SRC2[31:0] = Immediate Data Field[31:0]
case 010:SRC2[31:8] = A[24:0]; SRC2[6:0] = 0
case 011:SRC2[31:8] = B[24:0]; SRC2[6:0] = 0
case 100:SRC2[31:0] = R[31:0]
case 101:SRC2[31:0] = S[31:0]
case 110:SRC2[31:0] = T[31:0]
case 111:SRC2[31:0] = 0xFFFFFFFF}/******** ARITHMETIC / LOGICAL OPERATION STAGE *******/
switch (C[25:23]){
case 011:IR1 = src1 + src2 + C // ADC
case 001:IR1 = src1 + src2 // ADD
case 010:IR1 = src1 & src2 // ANDcase 100:IR1 = src1 | src2 // ORcase 110:IR1 = src1 - src2 - C // SBB
case 101:IR1 = src1 - src2 // SUB
case 111:IR1 = src1 ^ src2 // XOR}
IC1 = Carry Out if Operation is ADD, ADC, SUB, SBB= 0 if Operation is AND, OR, XOR
IZ1 = Set if IR1 is zero, Clear if IR1 is non-zero
IN1 = IR[31]IV1 = (IC1 XOR IR1[31]) AND NOT(SRC1[31] XOR SRC2[31])/******************** SHIFT STAGE ********************/
switch (C15:C13){
case 000: // smode = No Shift
IR2 = IR1IC2 = IC1; IZ2 = IZ1; IN2 = IN1; IV2 = IV1;
case 001: // smode = Arithmetic Shift RightIR2[31 - scount : 0] = IR1[31:scount]if (scount>0) {IR2[31 : 31 - scount + 1] = IR1[31]SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

647

Instruction Set

www.ti.com
IC2 = IR1[scount-1]}
else {
IC2 = IC1}
IN2 = IR2[31];
if (IR2 == 0) { IZ2 = 1 } else {IZ2 = 0};
IV2 = (IR2[31] XOR IR1[31]) OR IV1
case 010: // smode = Logical Shift Left
IR2[31 : scount] = IR1[31 - scount: 0]
if (scount > 0) {IR2[scount - 1 : 0] = 0}
IC2 = IC1
IN2 = IR2[31];
if (IR2 == 0) { IZ2 = 1 } else {IZ2 = 0};
IV2 = (IR2[31] XOR IR1[31]) OR IV1
case 011: // smode = Carry Shift Left
IR2[31 : scount] = IR1[31 - scount: 0]
if (scount>0) {IR2[scount - 1 : 0] = [IC1,...IC1]
IC2 = IR1[31 - scount + 1]}
else{
IC2 = IC1}
IN2 = IR2[31];
if (IR2 == 0) { IZ2 = 1 } else {IZ2 = 0};
IV2 = (IR2[31] XOR IR1[31]) OR IV1
case 100: // smode = Logical Shift RightIR2[31 - scount : 0] = IR1[31:scount]if (scount>0) {IR2[31 : 31 - scount + 1] = 0}
IC2 = IC1
IN2 = IR2[31];
if (IR2 == 0) { IZ2 = 1 } else {IZ2 = 0};
IV2 = (IR2[31] XOR IR1[31]) OR IV1
case 101: // smode = Carry Shift RightIR2[31 - scount : 0] = IR1[31:scount]if(scount>0) {IR2[31:31-scount + 1] = [IC1,...IC1]
IC2 = IR1[scount-1]}
else {
IC2 = IC1}
IN2 = IR2[31];IZ2 = Set if IR2 == 0;
IV2 = (IR2[31] XOR IR1[31]) OR IV1
case 110: // smode = Rotate Right

648

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com
IR2[31 - scount : 0] = IR1[31:scount]if(scount>0) {IR2[31:31-scount+1] = IR1[scount-1:0]
IC2 = IR1[scount-1]}
else {
IC2 = IC1}
IN2 = IR2[31];
if (IR2 == 0) { IZ2 = 1 } else {IZ2 = 0};
IV2 = (IR2[31] XOR IR1[31]) OR IV1
case 111: // smode = Carry Rotate RightIR2[31 - scount : 0] = IR1[31:scount]if (scount == 0) {IC2 = IC1}else if (scount == 1) {IR2[31] = IC1
IC2 = IR1[0]}else {
IR2[31:31-scount+1] = {IR1[scount-2:0],IC1}IC2 = IR1[scount - 1]}
IN2 = IR2[31];
if (IR2 == 0) { IZ2 = 1 } else {IZ2 = 0};
IV2 = (IR2[31] XOR IR1[31]) OR IV1}/********** WRITE REGISTER DESTINATION STAGE ***********/
switch (C7, C2:C1){
case 000:A[24:0] = IR2[31:8]
case 001:B[24:0] = IR2[31:8]
case 010:T[31:0] = IR2[31:0]
case 011:IR2 is not stored in register, immediatecase 100:R[31:0] = IR2[31:0]
case 101:S[31:0] = IR2[31:0]
case 110:Immediate Data Field[31:0] = IR2case 111:IR2 is not stored in register, immediate}/*********** WRITE REMOTE DESTINATION STAGE ***********/
switch (C4:3){
case 00:IR2 is not stored in remote fieldcase 01:Remote Data Field D[31:0] = IR2case 10:Remote Program Field P[8:0] = IR2[8:0]case 11:IR2 is not stored in remote field}/***************** UPDATE FLAGS STAGE *****************/C FLAG = IC2
N FLAG = IN2
Z FLAG = IZ2
V FLAG = IV2
If (Init Flag == 1){
ACF = 0;
DCF = 1;
GPF = 0;
NAF = 0;}else ACF, DCF, GPF, NAF remain unchanged;
SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

649

Instruction Set

www.ti.com

17.5.3.5 ADM32 (Add Move 32)
Syntax

ADM32 {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]remote={label | 9-bit unsigned integer}[control={OFF | ON}]
[init={OFF | ON}]
type={IM&REGTOREG | REM&REGTOREG | IM&REMTOREG |IM&REGTOREM}
reg={A | B | R | S | T }data={25-bit unsigned integer}[hr_data={7-bit unsigned integer}]}

Figure 17-81. ADM32 Program Field (P31:P0)
31

26 25

23

22

0

Reserved

BRK

21
Next program address

13 12
0100

9

8
Remote address

0

6

3

1

9

4

9

Figure 17-82. ADM32 Control Field (C31:C0)
31

27

26

25

23

22

16

Reserved

Control

000

Reserved

5

1

3

15

15

7

6

5

4

Reserved

8

Ext Reg

Init flag

1

Move type3

Register select

2

1

Res.

0

15

1

1

1

2

2

1

Figure 17-83. ADM32 Data Field (D31:D0)31

7

0
HR Data25

7

CyclesOne or two cycles (see Table 17-56)

Register modified

Selected register (A, B, R, S, or T)

Description

This instruction modifies the selected ALU register or data field values at the
remote address depending on the move type. The modified value results fromadding the immediate or remote data field to the ALU register or the remote
data field, depending on the move type. Table description shows the C2 andC1 bit encoding for determining which register is selected.

init

650

6

Data

(Optional) Determines whether or not system flags are initialized. A
value of ON reinitializes the following system flags to these states:
Acceleration flag (ACF) = 0
Deceleration flag (DCF) = 1
Gap flag (GPF) = 0

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

New angle flag (NAF) = 0
A value of OFF results in no change to the system flags.
Default: OFF
typeSpecifies the move type to be executed.

Table 17-56. Move Types for ADM32
Type

C4

C3

Add

Destination(s)CyclesRegister A, B, R, S, or T

1

IM&REGTOREG

00Imm. data field + Reg. A, B, R, S,
or T

REM&REGTOREG

0

1

Remote data field + Reg. A, B, R,
S, or T

Register A, B, R, S, or T

2

IM&REMTOREG

1

0Imm. data field + Remote data
field

Register A, B, R, S, or T

2

IM&REGTOREM

1

1

Imm. data field + Reg. A, B, R, S,
or T

Remote data field1

If selected register is R, S, or T, the operation is a 32-bit Addition/move. If A or B register is selected, it islimited to 25-bit operation since A and B only support 25-bit.
data

Specifies the 25-bit integer value for the immediate data field.

hr_dataSpecifies the 7 least significant bits of the immediate data field.
Default: 0.

Execution
switch (C4:C3){
case 00:
Selected register = Selected register + Immediate Data Field;
case 01:
Selected register = Selected register + Remote Data Field;
case 10:
Selected register = Immediate Data Field + Remote Data Field;
case 11:
Remote Data Field = Selected register + Immediate Data Field;}
If (Init Flag == 1){
ACF = 0;
DCF = 1;
GPF = 0;
NAF = 0;}else
All flags remain unchanged;
Jump to Next Program Address;

Figure 17-84 and Figure 17-85 illustrate the ADM32 operation for various cases.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

651

Instruction Set

www.ti.com

Figure 17-84. ADM32 Add and Move Operation for IM&REGTOREG (Case 00)
25/32-bit addition/move

LSBs (HR data field)

32 bits
HR

Immediate DF+

HRRegister A, B, R, S or T(dashed for R, S, T)=

HR

Register A, B, R, S or T(dashed for R, S, T)

Figure 17-85. ADM32 Add and Move Operation for REM&REGTOREG (Case 01)
25/32-bit addition/move

LSBs (HR data field)

32 bits

652

HR

Remote DF+

HRRegister A, B, R, S, or T(dashed for R, S, T)=

HR

Register A, B, R, S, or T(dashed for R, S, T)

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

17.5.3.6 APCNT (Angle Period Count)
SyntaxAPCNT {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][reqnum={3-bit unsigned integer}][request={NOREQ | GENREQ | QUIET}][irq={OFF | ON}]
type={FALL2FALL | RISE2RISE}[control={OFF | ON}]
prv={OFF | ON}}]
period={25-bit unsigned integer}
data={25-bit unsigned integer}}

Figure 17-86. APCNT Program Field (P31:P0)
31

23

22

0

26 25

RequestNumberBRK

21
Next program address

13 12
1110

9

Int.
ena

8

7
Edge
select6

5

Reserved

0

6

3

1

9

4

1

2

6

Figure 17-87. APCNT Control Field (C31:C0)
31

26

25

Res.

29 28

Requesttype

27

Control

Prv.

24
Period Count

0

3

2

1

1

25

Figure 17-88. APCNT Data Field (D31:D0)
31

7

6

0

Data

Reserved

25

7

CyclesOne or two cycles• Cycle 1: edge detected (normal operation)• Cycle 2: edge detected and GPF = 1 and underflow condition is true
One cycle (normal operation) two cycles (edge detected)

Register modified

Register A and T (implicitly)

Description

This instruction is used before SCNT and ACNT to generate an anglereferenced time base synchronized to an external signal (that is, a toothed
wheel signal). It is assumed that the pin and edge selections are the same for
APCNT and ACNT.
APCNT is restricted to pin HET[2]. The toothed wheel must then be connected
to pin HET[2].
APCNT uses the gap flag (GPF) defined by ACNT to start or stop captures in
the period count field [C24:C0]. When GPF = 1, the previous period value isheld in the control field and in register T. When GPF = 0, the current period
value is captured in the control field and in register T.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

653

Instruction Set

www.ti.com

APCNT uses the step width flags (SWF0 and SWF1) defined by SCNT todetect period durations shorter than one step, and then disables capture.
The edge select encoding is shown in Table 17-57.

irq

ON generates an interrupt when the edge state is satisfied. OFF
prevents an interrupt from being generated.
Default: OFF.

type

Specifies the edge type that triggers the instruction.
Default: Fall2Fall.

Table 17-57. Edge Select Encoding for APCNT

654

type

P7

P6

Selected Condition

Fall2Fall

10

Falling edge

Rise2Rise

1

1

Rising edge

periodContains the 25-bit count value from the previous APCNT period.

data

25-bit value serving as a counter.
Default: 0.

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

Execution
Z = 0;
If (Data field register != 1FFFFFFh){
Register A = Data field register + 1;
Data field register = Data field register + 1;}
elseIf (specified edge not detected on HET[2]){Register A = 1FFFFFFh;
APCNT Ovflw flag = 1;}
If (specified edge detected on HET[2]){Z = 1;
If (Data field register == 1FFFFFFh){
Register A = 1FFFFFFh;
Register T = 1FFFFFFh;Period count = 1FFFFFFh;
Period count = 1FFFFFFh;}
elseIf (GPF == 0 AND Data Field register >= Step width){
Register A = Data field register + 1;
Register T = Register A;
Period count = Register T;
If (Interrupt Enable == 1)
HETFLG[n] = 1;/* n depends on address */If ([C28:C27] == 01)
Generate request on request line [P25:P23];
If ([C28:C27] == 11)
Generate quiet request on request line [P25:P23];}
If (GPF == 1)
Register T = Period count;
If (Data Field register < Step width){
Register T = Period count;
APCNT Undflw flag = 1;
Period Count = 000000h;}
Data field register = 000000h;}
else{
Register T = Period count;}
Prv bit = Current Lx value of HET[2] pin;
Jump to Next Program Address;

The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 17.2.7.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

655

Instruction Set

www.ti.com

17.5.3.7 BR (Branch)
SyntaxBR {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][reqnum={3-bit unsigned integer}][request={NOREQ | GENREQ | QUIET}][control={OFF | ON}]
[prv={OFF | ON}]
cond_addr={label | 9-bit unsigned integer}[pin= {pin number}]
event={NOCOND | FALL | RISE | BOTH | ZERO | NAF | LOW | HIGH | C | NC
| EQ | Z | NE | NZ | N | PZ | V | NV | ZN | P | GE | LT | GT | LE | LO | HS }[irq={OFF | ON}]}

Figure 17-89. BR Program Field (P31:P0)
31

26 25

23

22

21

13 12

9

8

0

0

RequestNumberBRK

Next program address

1101

Reserved

6

3

1

9

4

9

Figure 17-90. BR Control Field (C31:C0)
31

29

28

27

26

25

24

22

21

16

Reserved

Request type

Control

Prv

Reserved

Conditional address

3

2

1

1

3

9

15

13

12

8

7

3

2

1

0

Conditional address

Pin selectBranch cond.

Reserved

Int. ena

9

5

5

2

1

Figure 17-91. BR Data Field (D31:D0)
31

0
Reserved
32

CyclesOne

Register modified

None

Description

This instruction executes a jump to the conditional address [C21:C13] on a pin
or a flag condition, and can be used with all pins.
Table 17-58 provides the branch condition encoding.

event

656

Specifies the event that triggers a jump to the indexed program
address.
Default: FALL

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

irq

ON generates an interrupt when the event occurs that triggers thejump. If irq is set to OFF, no interrupt is generated.
Default: OFF.

Table 17-58. Branch Condition Encoding for BR
Event

C7

C6

C5

C4

C3

NOCOND

0

0

0

0

0

Branch Condition
Always

FALL

0

0

1

0

0

On falling edge on the selected pin

RISE

0

1

0

0

0

On rising edge on selected pin

BOTH

0

1

1

0

0

On rising or falling edge on selected pin

ZERO

1

0

0

0

0

If Zero flag is set

NAF

1

0

1

0

0

If NAF_global flag is set

LOW

1

1

0

0

0

On LOW level on selected pin

HIGH

1

1

1

0

0

On HIGH level on selected pin

C

0

0

0

0

1

Carry Set: C==1
Carry Not Set: C==0

NC

0

0

0

1

1

EQ, Z

0

0

1

0

1

Equal or Zero: Z==1

NE, NZ

0

0

1

1

1

Not Equal or Not Zero: Z==0

N

0

1

0

0

1

Negative: N==1

PZ

0

0

1

1

1

Positive or Zero: N==0

V

0

1

1

0

1

Overflow: V==1

NV

0

1

1

1

1

No Overflow: V==0

ZN

1

0

0

0

1

Zero or Negative: (Z OR N) == 1

P

1

0

0

1

1

Positive: (Z OR N) == 0

GE

1

0

1

1

1

Signed Greater Than or Equal: (N XOR V) == 0

L

1

0

1

0

1

Signed Less Than (N XOR V) == 1

G

1

1

0

1

1

Signed Greater Than (Z OR (N XOR V)) == 0

LE

1

1

0

0

1

Signed Less Than (Z OR (N XOR V)) == 1

LO

1

1

1

1

1

Unsigned Less Than: (C OR Z) == 0

HS

1

1

1

0

1

Unsigned Higher or Same (C OR Z) == 1

Execution
If (Condition is true){
If (Interrupt Enable == 1) HETFLG[n] = 1;/* n depends on address */If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];
Jump to Conditional Address;}
else{
Jump to Next Program Address;}
Prv bit = Current Lx value of selected pin; (Always Executed)

The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 17.2.7.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

657

Instruction Set

www.ti.com

17.5.3.8 CNT (Count)
SyntaxCNT {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][reqnum={3-bit unsigned integer}][request={NOREQ | GENREQ | QUIET}][angle_count={OFF | ON}]
[reg={A | B | T | NONE}][comp ={EQ | GE}]
[irq={OFF | ON}]
[control={OFF | ON}]
max={25-bit unsigned integer}[data={25-bit unsigned integer]}

Figure 17-92. CNT Program Field (P31:P0)
31

26 25

23

22

8

7

0

RequestNumberBRK

21
Next program address

13 12
0110

9

Angle
count

Register

6

Comp.
select

5

4
Res.

1

Int. ena

0

6

3

1

9

4

1

2

1

4

1

Figure 17-93. CNT Control Field (C31:C0)
31

26

25

Res.

29 28

Requesttype

27

ControlRes.

24
Max Count

0

3

2

1

1

25

Figure 17-94. CNT Data Field (D31:D0)
31

658

7

6

0

Data

Reserved

25

7

CyclesOne or two
One cycle (time mode), two cycles (angle mode)

Register modified

Selected register (A, B or T)

Description

This instruction defines a virtual timer. The counter value stored in the data
field [D31:7] is incremented unconditionally on each execution of the
instruction when in time mode (angle count bit [P8] = 0). When the countreaches the maximum count specified in the control field, the counter is reset.
It takes one cycle in this mode.
In angle mode (angle count bit [P8] = 1), CNT needs data from the software
angle generator (SWAG). When in angle count mode the angle increment
value will be 0 or 1. It takes two cycles in this mode.

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

angle_countSpecifies when the counter is incremented. A value of ON causes thecounter value to be incremented only if the new angle flag is set(NAF_global = 1). A value of OFF increments the counter each time
the CNT instruction is executed.
Default value for this field is OFF.

comp

When set to EQ the counter is reset, when it is equal to the maximum
count.
When set to GE the counter is reset, when it is greater or equal to the
maximum count.
Default: GE.

irq

ON generates an interrupt when the counter overflows to zero. Theinterrupt is not generated until the data field is reset to zero. If irq is
set to OFF, no interrupt is generated.
Default: OFF.

max

Specifies the 25-bit integer value that defines the maximum countvalue allowed in the data field. When the count in the data field isequal to max, the data field is reset to 0 and the Z system flag is set
to 1.

data

Specifies the 25-bit integer value serving as a counter.
Default: 0.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

659

Instruction Set

www.ti.com

Execution
Z = 0;If (Angle Count (bit P8 == 1)){
If (NAF_global == 0){
Selected register = immediate data field;
Jump to Next Program Address;}else{
If ((Immediate Data Field + Angle Increment) >= Max count){
Z = 1;
Selected register = ((Immediate Data Field + Angle Inc.) - Max count);
Immediate Data Field = ((Immediate Data Field + Angle Inc.) - Max count);
If (Interrupt Enable == 1) HETFLG[n] = 1;/* n depends on address */If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];}
else{
Selected register = Immediate Data Field + Angle Increment;
Immediate Data Field = Immediate Data Field + Angle Increment;}}}
else if(Time mode (bit P8 == 0)){
If [(P5==0) AND (Immediate Data Field == Max count)]
OR [(P5==1) AND (Immediate Data Field >= Max count)]{
Z = 1;
Selected register = 00000;
Immediate Data Field = 00000;
If (Interrupt Enable == 1) HETFLG[n] = 1;/* n depends on address */If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];}
else{
Selected register = Immediate Data Field + 1;
Immediate Data Field = Immediate Data Field + 1;}}
Jump to Next Program Address;

The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 17.2.7.

660

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

17.5.3.9 DADM64 (Data Add Move 64)
SyntaxDADM64 {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]remote={label | 9-bit unsigned integer}[request={NOREQ | GENREQ | QUIET}][control={OFF | ON}]
[en_pin_action={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}][pin={pin number}]comp_mode={ECMP | SCMP | MCMP1 | MCMP2}[action={CLEAR | SET | PULSELO | PULSEHI}][reg={A | B | R | S | T | NONE}][irq={OFF | ON}][data={25-bit unsigned integer][hr_data= {7-bit unsigned integer}]}-orSyntax

DADM64 {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]remote={label | 9-bit unsigned integer}
cntl_val={29-bit unsigned integer}
data={25-bit unsigned integer}[hr_data= {7-bit unsigned integer}]}

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

661

Instruction Set

www.ti.com

Figure 17-95. DADM64 Program Field (P31:P0)
31

26 25

23

22

21

13 12

9

8

0

0

Reserved

BRK

Next program address

0010

Remote Address

6

3

1

9

4

9

Figure 17-96. DADM64 Control Field (C31:C0)
31

29

28

27

26

25

23

22

21

16

Reserved

Request type

Control

Reserved

En. pinactionConditional address

3

2

1

3

1

9

15

7

6

Conditional address

13

12
Pin select

8

Ext
Reg

Comp. mode

5

4
Action3

Register select

2

1

Int.
ena

0

9

5

1

2

2

2

1

Figure 17-97. DADM64 Data Field (D31:D0)
31

7

6

0

Data

HR Data25

7

CyclesTwo

Register modified

Register T (implicitly)

Description

This instruction modifies the data field and the control field at the remoteaddress. The remote data field value is not just replaced, but is added with theDADM64 data field.
DADM64 has two distinct syntaxes. In the first syntax, bit values may be set
by assigning a value to each of the control fields. This syntax is convenient for
modifying control fields that are arranged similarly to the format of theDADM64 control field. A second syntax, in which the entire 29-bit control field
is specified by the cntl_val field, is convenient when the remote control field isdissimilar to the DADM64 control field. Either syntax may be used, but you
must use one or the other but not a combination of syntaxes.
Figure 17-98 shows the DADM64 add and move operation.
Figure 17-98. DADM64 Add and Move Operation
LSBs (HR Data Field)

32 bits
Immediate CF

Remote CF

HR

Immediate DF+

HR

Remote DF=

HR

Remote DF

Table 17-59. DADM64 Control Field Description
requestcontrol
en_pin_action
cond_addr

maintains the control field for the remote instruction
maintains the control field for the remote instruction
maintains the control field for the remote instruction
maintains the control field for the remote instruction

662 High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

Table 17-59. DADM64 Control Field Description (continued)pinregisteractionirq
data
hr_datacntl_valmaintains the control field for the remote instruction
maintains the control field for the remote instruction
maintains the control field for the remote instruction
maintains the control field for the remote instruction
Specifies the 25-bit initial value for the data field.
Seven least significant bits of the 32 bit data field.
Default: 0
Specifies the 29 least significant bits of the Control field.

Execution
Remote Data Field = Remote Data Field + Immediate Data Field;
Register T = Immediate Data Field;
Remote Control Field = Immediate Control Field;
Jump to Next Program Address;

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

663

Instruction Set

www.ti.com

17.5.3.10 DJZ (Decrement and Jump if Zero)NOTE: DJNZ is also a supported syntax. The functionality of the two instruction names is identical.

SyntaxDJZ {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][reqnum={3-bit unsigned integer}[request={NOREQ | GENREQ | QUIET}][control={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}][reg={A | B | T | NONE}][irq={OFF | ON}][data={25-bit unsigned integer]}

Figure 17-99. DJZ Program Field (P31:P0)
31

26 25

23

22

21

13 12

9

8

7

6

5

0

0

RequestNumberBRK

Next program address

1010

Res.

10

Reserved

6

3

1

9

4

1

2

6

Figure 17-100. DJZ Control Field (C31:C0)
31

29

28

27

26

25

22

21

16

Reserved

Request type

Control

Reserved

Conditional address

3

2

1

4

9

15

13

12

8

7

3

2

1

0

Conditional address

Reserved

Register selectInt. ena

9

10

2

1

Figure 17-101. DJZ Data Field (D31:D0)
31

664

7

6

0

Data

Reserved

25

7

CyclesOne

Register modified

Selected register (A, B, or T)

Description

This instruction defines a virtual down counter used for delayed execution ofcertain instructions (to generate minimum on/off times). When DJZ is
executed with counter value not zero, the counter value is decremented. If thecounter value is zero, the counter remains zero until it is reloaded with a nonzero value. The program flow can be modified when down counter value iszero by using the conditional address.

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

cond_addr

This field is not optional for the DJZ instruction.

irq

ON generates an interrupt when the data field reaches zero. No
interrupt is generated when the bit is OFF.
Default: OFF.

data

Specifies the 25-bit integer value used as a counter. This counter isdecremented each time the DJZ instruction is executed until thecounter reaches 0.
Default: 0.

Execution
If (Data != 0){
Data = Selected register = Data - 1;
Jump to Next Program Address;}
else{
Selected register = 000000h;
If (Interrupt Enable == 1) HETFLG[n] = 1;/* n depends on address */If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];
Jump to conditional Address;}

The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 17.2.7.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

665

Instruction Set

www.ti.com

17.5.3.11 ECMP (Equality Compare)
SyntaxECMP {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][reqnum={3-bit unsigned integer}[request={NOREQ | GENREQ | QUIET}][hr_lr={HIGH | LOW}][angle_comp={OFF | ON}]
[control={OFF | ON}]
[en_pin_action={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}]pin={pin number}[action={CLEAR | SET | PULSELO | PULSEHI}][reg={A | B | R | S| T | NONE}][irq={OFF | ON}][data={25-bit unsigned integer][hr_data={7-bit unsigned integer}]}

Figure 17-102. ECMP Program Field (P31:P0)
31

26 25

23

22

8

7

0

RequestNumberBRK

21
Next program address

13 12
0000

9

hr_lr

Angle
comp.

6
Reserved

0

6

3

1

9

4

1

1

7

Figure 17-103. ECMP Control Field (C31:C0)
31

29

28

27

26

25

23

22

21

16

Reserved

Request type

Control

Reserved

En. pinactionConditional address

3

2

1

3

1

9

15

13

12

8

7

6

5

4

3

2

1

0

Conditional address

Pin select

Ext
Reg

00

ActionRegister select

Int.
ena

9

5

1

2

2

2

1

Figure 17-104. ECMP Data Field (D31:D0)
31

666

7

6

0

Data

HR Data25

7

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

CyclesOne

Register modified

Register A, B, R, S or T if selected

Description

ECMP can use all pins. This instruction compares a 25-bit data value stored in
the data field (D31–D7) to the value stored in the selected ALU register (A, B,
R, S, or T). Register select encoding can be found in Section 17.5.2.
If R, S, or T registers are selected, and if the 25-bit data field matches, ECMP
updates the register with the 32-bit value (D31-D0).
If the hr_lr bit is cleared, the pin action will occur after a high resolution delay
from the next loop resolution clock. If the hr_lr bit is set, the delay is ignored.
This delay is programmed in the data field (D6–D0).
The behavior of the pins is governed by the four action options in bits C4:C3.
ECMP uses the zero flag to generate opposite pin action (synchronized to theloop resolution clock).

angle_comp

Determines if an angle compare is performed. A value of ON causes
the comparison to be performed only if the new angle flag is set (NAF
= 1). If OFF is specified, the compare is then performed regardless ofthe state of the new angle flag.
Default: OFF.

irq

Specifies whether or not an interrupt is generated. A value of ON
sends an interrupt if register and data field values are equivalent. If
OFF is selected, no interrupt is generated.
Default: OFF.

data

Specifies the value for the data field. This value is compared with theselected register.

hr_dataSpecifies the HR delay.
Default: 0.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

667

Instruction Set

www.ti.com

Execution
If (Angle Comp. bit == 0 OR (Angle Comp. bit == 1 AND NAF_global == 1)){
If (Selected register value == Immediate data field value){
If (hr_lr bit == 0){
If (Enable Pin action == 1){
Selected Pin = Pin Action AT next loop resolution clock + HR delay;
}
}
else
{
If (Enable Pin action == 1){
Selected Pin = Pin Action AT next loop resolution clock;}}
If (Z == 1 AND Opposite action == 1){
If (Enable Pin action == 1){
Selected Pin = opposite Pin Action AT next loop resolution clock;}
If (Interrupt Enable == 1) HETFLG[n] = 1;/* n depends on address */If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11)Generate quiet request on request line [P25:P23];
If (register R is selected) R register = Compare value (32 bit);
If (register S is selected) S register = Compare value (32 bit);
If (register T is selected) T register = Compare value (32 bit);
Jump to Conditional Address;}}
elseIf (Z == 1 AND Opposite action == 1){
If (Enable Pin action == 1){
Selected Pin = opposite Pin Action AT next loop resolution clock;}Jump to Next Program Address;}
else // Angle Comp. bit == 1 AND NAF_global == 0{
Jump to Next Program Address;}

The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 17.2.7.

668

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

17.5.3.12 ECNT (Event Count)
SyntaxECNT {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][reqnum={3-bit unsigned integer}[request={NOREQ | GENREQ | QUIET}][control={OFF | ON}]
[prv={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}]pin={pin number}
event={NAF | FALL | RISE | BOTH | ACCUHIGH | ACCULOW}[reg={A | B | R| S | T | NONE}][irq={OFF | ON}][data={25-bit unsigned integer]}

Figure 17-105. ECNT Program Field (P31:P0)
31

26 25

23

22

21

13 12

9

8

7

6

5

0

0

RequestNumberBRK

Next program address

1010

Res.

01

Reserved

6

3

1

9

4

1

2

6

Figure 17-106. ECNT Control Field (C31:C0)
31

26

25

Reserved

29

Request type

Control

Prv.

Reserved

Conditional address

3

2

1

1

3

9

15

13

28

27

12

24

8

22

7

21

6

16

4

3

2

1

0

Conditional address

Pin select

Ext
Reg

Event

Res.

Register select

Int.
ena

9

5

1

3

1

2

1

Figure 17-107. ECNT Data Field (D31:D0)
31

7

6

0

Data

Reserved

25

7

Cycles

One cycle

Register modified

Selected Register (A, B, R, S, T or none)

Description

This instruction defines a specialized 25-bit virtual counter used as an event
counter or pulse accumulator (see Table 17-60). The counter value is stored
in the data field [D31:D7] and the selected register. If one of the 32-bit
registers (R,S,T) is selected, the 25 bit count value is stored left justified in theregister with zeros in the seven least significant bits.
When an event count condition is specified, the counter value is incremented
on a pin edge condition or on the NAF condition (NAF is defined in ACNT).
This instruction can be used with all pins.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

669

Instruction Set

www.ti.com

event

The event that triggers the counter.

Table 17-60. Event Encoding Format for ECNT
Event

C6

C5

C4

Count Conditions

Mode

Int. Available

NAF

0

0

0

NAF flag is Set

Angle counter

Y

FALL

0

0

1

Falling edge on selected pin

Event counter

Y

RISE

0

1

0

Rising edge on selected pin

Event counter

Y

BOTH

0

1

1

Rising and Falling edge on
selected pin

Event counterY

ACCUHIGH

10-while pin is high level

Pulse accumulationN

ACCULOW

1

1-while pin is low level

Pulse accumulation

Nirq

ON generates an interrupt when event in counter mode occurs. No
interrupt is generated with OFF.
Default: OFF.

data

25-bit integer value serving as a counter.
Default: 0.

Execution
If (event occurs){
If (Register A or B Selected) {Selected register = Immediate Data Field + 1;}
If (Register R, S or T Selected){
Selected register[31:7] = Immediate Data Field + 1;
Selected register[6:0] = 0;}
Immediate Data Field = Immediate Data Field + 1;
If (Interrupt Enable == 1) HETFLG[n] = 1;/* n depends on address */If ([C28:C27] == 01) Generate request on line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on line [P25:P23];
Jump to Conditional Address;}
else{
Jump to Next Program Address;}
Prv bit = Current Logic (Lx) value of selected pin; (Always executed)

The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 17.2.7.

670

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

17.5.3.13 MCMP (Magnitude Compare)
SyntaxMCMP {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][reqnum={3-bit unsigned integer}[request={NOREQ | GENREQ | QUIET}][hr_lr={LOW |HIGH}][angle_comp={OFF | ON}][savesub={OFF | ON}]
[control={OFF | ON}]
[en_pin_action={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}]pin={pin number}order={REG_GE_DATA | DATA_GE_REG}[action={CLEAR | SET | PULSELO | PULSEHI}]
reg={A | B | R | S | T | NONE}[irq={OFF | ON}][data={25-bit unsigned integer][hr_data={7-bit unsigned integer}]}

Figure 17-108. MCMP Program Field (P31:P0)
31

26 25

23

22

8

7

6

5

0

RequestNumberBRK

21
Next program address

13 12
0000

9

hr_lr

Angle
comp.

Res.

Save
sub.

4

Res.

0

6

3

1

9

4

1

1

1

1

5

Figure 17-109. MCMP Control Field (C31:C0)
31

29

28

27

26

25

23

22

21

16

Reserved

Request type

Control

Reserved

En. pinactionConditional address

3

2

1

3

1

9

15

7

6

5

Conditional address

13

12
Pin select

8

Ext
Reg

1

Order

4
Action3

Register select

2

1

Int.
ena

0

9

5

1

1

1

2

2

1

Figure 17-110. MCMP Data Field (D31:D0)
31

7

6

0

Data

HR Data25

7

CyclesOne

Register modified

T (if save sub bit P[5] is set)

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

671

Instruction Set

www.ti.com

Description

This instruction compares the magnitude of the 25-bit data value stored in thedata field (D31-D7) and the 25-bit value stored in the selected ALU register(A, B, R, S, or T).
If the hr_lr bit is reset, pin action will occur after a delay from the next loop
resolution clock. If the hr_lr bit is set, the delay is ignored. This delay isprogrammed in the data field (D6-D0).
When the data value matches, an output pin can be set or reset according to
the pin action bit (C[4]). The pin will not change states if the enable pin action
bit (C[22]) is reset.
MCMP uses the zero flag set to generate opposite pin action (synchronized to
the loop resolution clock). The save sub bit (P[5]) provides the option to savethe result of a subtraction into register T.

NOTE: The Difference Between Compare Values
The difference between the two data values must not exceed (224) - 1.

angle_comp

Determines whether or not an angle compare is performed. A value of
ON causes the comparison to be performed only if the new angle flagis set (NAF = 1). If OFF is specified, the compare is then performed
regardless of the state of the new angle flag.
Default: OFF.

savesub

When set, the comparison result is saved into the T register (upper
25 bits).
Default: OFF.

order

Specifies the order of the operands for the comparison.

Table 17-61. Magnitude Compare Order for MCMP

672

Order

C5

Description

REG_GE_DATA

0

Evaluates to true if the register value is greater than or equal to the data field value.

DATA_GE_REG

1

Evaluates to true if the data field value is greater than or equal to the register value.

irq

Specifies whether or not an interrupt is generated. A value of ON
sends an interrupt if the compare match occurs according to the orderselected. If OFF is selected, no interrupt is generated.

data

Specifies the value for the data field. This value is compared with theselected register.

hr_data

HR delay. The default value for an unspecified bit is 0.

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

Execution
If (Angle Compare P[7] == 0 OR (P[7] == 1 AND NAF_global == 1)){
If( (Order C[5] == 1) AND (Data[31:7]- Selected register[31:7]) >= 0))
OR ( (Order C[5] == 0) AND Selected register[31:7] - Data[31:7]) >= 0)){
If (Order C[5] == 1 AND Save subtract P[5] == 1){
Register T[31:7] = Data[31:7] - Selected register[31:7];
Register T[6:0] = 0;}
If (Order C[5] == 0 AND Save subtract P[5] == 1){
Register T[31:7] = Selected register[31:7] - Data[31:7];
Register T[6:0] = 0;}
If (Enable Pin Action C[22] == 1){
If (hr_lr P[8] = 0) {Schedule Action on Selected Pin C[12:8] at start of next loop
+ HR Delay D[6:0];}
else{
Schedule Pin Action on Selected Pin C[12:8] at start of next loop;}}
If (Interrupt Enable == 1) HETFLG[n] = 1;/* n depends on address */If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];
Jump to Conditional Address;}
else if (Z == 1 AND Opposite Action C[3] == 1 ){If (Enable Pin Action C[22] == 1){
Schedule Opposite Pin Action on Selected Pin C[12:8] at start of next loop;}
Jump to Next Program Address;}
else
Jump to Next Program Address;}
else // Angle Comp. bit == 1 AND NAF_global == 0
Jump to Next Program Address;

The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 17.2.7.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

673

Instruction Set

www.ti.com

17.5.3.14 MOV32 (Data Move 32)
SyntaxMOV32 {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]remote={label | 9-bit unsigned integer}[control={OFF | ON}][z_cond={OFF | ON}]
[init={OFF | ON}]| ON}]
type={IMTOREG | IMTOREG&REM | REGTOREM | REMTOREG}[reg={A | B | R | S | T | NONE}][data={25-bit unsigned integer][hr_data={7-bit unsigned integer}]}

Figure 17-111. MOV32 Program Field (P31:P0)
31

23

22

0

26 25

Reserved

BRK

21
Next program address

13 12
0100

9

8
Remote Address

0

6

3

1

9

4

9

Figure 17-112. MOV32 Control Field (C31:C0)
31

27

26

25

23

22

21

16

Reserved

Control

Reserved

Z Fl. Cond.

Reserved

5

1

3

1

14

15

7

6

5

4

Reserved

8

Ext Reg

Init flag

0Move type3

Register select

2

1

Res.

0

14

1

1

1

2

2

1

Figure 17-113. MOV32 Data Field (D31:D0)
31

674

7

6

0

Data

HR Data25

7

CyclesOne or two cycles

Register modified

Selected register (A, B, R, S, or T)

Description

MOV32 replaces the selected ALU register and/or the data field values at the
remote address location depending on the move type.
Figure 17-114 through Figure 17-117 illustrate these operations. If no register
is selected, the move is not executed, except for configuration C4:C3 = 01,
where the remote data field is written with the immediate data field value.

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

remoteDetermines the location of the remote address.
Default: Current instruction + 1.

z_condWhen set to OFF the MOV32 performs the move operation specified
by the move type whenever it is executed (independent on the stateof the Z-Flag).
When set to ON the MOV32 performs the move operation specified
by the move type only when the Z-Flag is set.

init

(Optional) Determines whether or not system flags are initialized. A
value of ON reinitializes the following system flags to these states:
Acceleration flag (ACF) = 0
Deceleration flag (DCF) = 1
Gap flag (GPF) = 0
New angle flag (NAF) = 0
A value of OFF results in no change to the system flags.

typeSpecifies the move type to be executed.

Table 17-62. Move Type Encoding Selection
Move Type

C4

C3

SourceDestination(s)CyclesIMTOREG00

Immediate data field

Register A, B, R, S, or T

1

Remote data field and register
A, B, R, S, or T

1

IMTOREG&REM

0

1

Immediate data field

REGTOREM

1

0

Register A, B, R, S, or T

Remote data field

1

REMTOREG

1

1

Remote data field

Register A, B, R, S, or T

2

Figure 17-114. MOV32 Move Operation for IMTOREG (Case 00)
25/32-bit move

LSBs (HR data field)

32 bits
HR

Immediate DF

HRRegister A, B, or R, S or T(dashed for R, S, T)

reg

Specifies which register (A, B, T, or NONE) is involved in the move. A
register (A, B, or T) must be specified for every move type except
IMTOREG&REM. If NONE is used with move type IMTOREG&REM,
the MOV32 executes a move from the immediate data field to theremote data field. If NONE is used with any other move type, no
move is executed.

data

Specifies a 25-bit integer value to be written to the remote data fieldor selected register.

hr_data(Optional) HR delay. The default value for an unspecified bit is 0.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

675

Instruction Set

www.ti.com

Figure 17-115. MOV32 Move Operation for IMTOREG&REM (Case 01)
25/32-bit move

LSBs (HR data field)

32 bits
HR

Immediate DFHRHR

Remote DF

Register A, B, R, S or T(dashed for R, S, T)

Figure 17-116. MOV32 Move Operation for REGTOREM (Case 10)
25/32-bit moveHR

Register A, B, R, S, or T(dashed for R, S, T)

HR

Remote DF
LSBs (HR data field = 0 if A or B)

Figure 17-117. MOV32 Move Operation for REMTOREG (Case 11)
LSBs (HR data field)

25/32-bit move
32 bits
HR

Remote DF

HR Register A, B, R, S, or T(dashed for R, S, T)

676

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

Execution
If [(z_cond C[22] ==0) OR ((z_cond C[22] == 1) AND (Z Flag == 1))]{switch (type C[4:3]){
case 00: // IMTOREG
Selected register = Immediate Data Field;
case 01: // IMTOREG&REM
Selected register = Immediate Data Field;
Remote Data Field = Immediate Data Field;
case 10: // REGTOREM
Remote Data Field = Selected register;case 11: // REMTOREG
Selected register = Remote Data Field;}}
If (Init Flag == 1){
ACF = 0;
DCF = 1;
GPF = 0;
NAF = 0;}else
All flags remain unchanged;
Jump to Next Program Address;

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

677

Instruction Set

www.ti.com

17.5.3.15 MOV64 (Data Move 64)
SyntaxMOV64 {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]remote={label | 9-bit unsigned integer}[request={NOREQ | GENREQ | QUIET}][control={OFF | ON}]
[en_pin_action={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}][pin={pin number}]comp_mode={ECMP | SCMP | MCMP1 | MCMP2}[action={CLEAR | SET | PULSELO | PULSEHI}][reg={A | B | R | S | T | NONE}][irq={OFF | ON}][data={25-bit unsigned integer][hr_data= {7-bit unsigned integer}}-orSyntax

678

MOV64 {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]remote={label | 9-bit unsigned integer}
cntl_val={29-bit unsigned integer}[data={25-bit unsigned integer][hr_data= {7-bit unsigned integer}}

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

Figure 17-118. MOV64 Program Field (P31:P0)
31

26 25

23

22

21

13 12

9

8

0

0

Reserved

BRK

Next program address

0001

Remote Address

6

3

1

9

4

9

Figure 17-119. MOV64 Control Field (C31:C0)
31

29

28

27

26

25

23

22

21

16

Reserved

Request type

Control

Reserved

En. pinactionConditional address

3

2

1

3

1

9

15

7

6

Conditional address

13

12
Pin select

8

Ext
Reg

Comp. mode

5

4
Action3

Register select

2

1

Int.
ena

0

9

5

1

2

2

2

1

Figure 17-120. MOV64 Data Field (D31:D0)
31

7

6

0

Data

HR Data25

7

CyclesOne

Register modified

None

Description

This instruction modifies the data field and the control field at the remoteaddress.
MOV64 has two distinct syntaxes. In the first syntax, bit values may be set byassigning a value to each of the control fields. This syntax is convenient for
modifying control fields that are arranged similarly to the format of the MOV64
control field. A second syntax, in which the entire 29-bit control field isspecified by the cntl_val field, is convenient when the remote control field isdissimilar to the MOV64 control field. Either syntax may be used, but you mustuse one or the either but not a combination of syntaxes. See Figure 17-121.
Figure 17-121. MOV64 Move OperationHR

Immediate CF + DF

HRRemote CF + DF

Table 17-63. MOV64 Control Field Descriptions
requestcontrol
en_pin_action
cond_addr
pinregister, ext reg
comp_mode

Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Selects the comparison mode type to be used by the remote instruction.

High-End Timer (N2HET) Module 679

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

Table 17-63. MOV64 Control Field Descriptions (continued)
actionirq
data
hr_data

Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Specifies the 25-bit initial count value for the data field. If omitted, the field defaults to 0.
(Optional) HR delay. The default value for an unspecified bit is 0.

Table 17-64. Comparison Type Encoding Format
comp_mode

C[6]

C[5]

ECMP

0

0

MCMP Order

SCMP

0

1

MCMP1

1

0

REG_GE_DATA

MCMP2

1

1

DATA_GE_REG

Execution
Remote Data Field = Immediate Data Field;
Remote Control Field = Immediate control Field;
Jump to Next Program Address;

680

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

17.5.3.16 PCNT (Period/Pulse Count)
SyntaxPCNT {[hr_lr={HIGH | LOW}][brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][reqnum={3-bit unsigned integer}[request={NOREQ | GENREQ | QUIET}][irq={OFF | ON}]
type={FALL2RISE | RISE2FALL | FALL2FALL | RISE2RISE}
pin={pin number}[control={OFF | ON}]
[prv={OFF | ON}]
[period={25-bit unsigned integer}][data={25-bit unsigned integer][hr_data= {7-bit unsigned integer}}

Figure 17-122. PCNT Program Field (P31:P0)
31

26 25

23

22

6

5

0

RequestNumberBRK

21
Next program address

13 12
0111

9

Int.
ena

8

Type select

7

hr_lr

4

Pin
select

0

6

3

1

9

4

1

2

1

5

Figure 17-123. PCNT Control Field (C31:C0)
31

29 28

27

26

25

24

0

Res.

Requesttype

Control

Prv.

Period Count

3

2

1

1

25

Figure 17-124. PCNT Data Field (D31:D0)
31

7

6

0

Data

HR Data25

7

CyclesOne

Register modified

Register A

Description

This instruction detects the edges of the external signal at loop start andmeasures its period or pulse duration. The counter value stored in the control
field C[24:0] and in the register A is incremented each N2HET loop. PCNT
uses the HR structure on the pin to measure an HR period/pulse count value.

hr_lr(Optional) Specifies whether the PCNT instruction captures the HR
delay into the HR data field on the selected edge condition. If hr_lr is
0 (HIGH) then PCNT captures the HR delay. if hr_lr is 1 (LOW) then
PCNT only captures at loop resolution.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

681

Instruction Set

www.ti.com

irq(Optional) Specifies whether or not an interrupt is generated. A valueof ON sends an interrupt when a new value is captured. If OFF isselected, no interrupt is generated.

type(Optional) Determines the type of counter that is implemented.

Table 17-65. Counter Type Encoding Format
P7

P6

Period/Pulse SelectReset On

Capture On

Falling edge

Rising edge

FALL2RISE

00Count low-pulse duration on
selected pin

RISE2FALL

0

1

Count high-pulse duration on
selected pin

Rising edge

Falling edge

FALL2FALL

1

0

Count period between falling edges
on selected pin

Falling edge

Falling edge

RISE2RISE

1

1

Count period between rising edges
on selected pin

Rising edge

Rising edge

periodSpecifies the 25-bit integer value that holds the counter value. The
counter value is also stored in register A.
Default: 0.

data

25-bit integer representing the last captured counter value.
Default: 0.

hr_data

HR delay.
Default: 0.

If period-measure is selected, PCNT captures the counter value into the period/pulse data field [D31:D7]
on the selected edge. The HR structure provides HR capture field [D6:D0]. The counter value [C24:C0] is
reset on the same edge. The captured period value is a 32-bit value.
If pulse-measure is selected, PCNT captures the counter value into the period/pulse count field [D31:D7]
on the selected edge. The HR structure provides HR capture field [D6:D0]. The counter value [C24:C0] is
reset on the next opposite edge. The captured pulse value is a 32-bit value.
When the overflow count (all 1’s in the counter value) is reached, PCNT stops counting until the next resetedge is detected.
Note: For FALL2FALL/RISE2RISE, the user should always discard the first interrupt/HTU request if
interrupt/request are enabled before HET_ON. For both the types, reset edge and capture edge are thesame and the interrupt or HTU request is triggered on capture edge (which is nothing but the reset edge).
Once the execution unit is enabled, the first edge generates an interrupt but the value of the counter is of
no use as this is not the period between 2 edges. So first edge after turning on N2HET is used mainly forresetting the counter and start the period count.

682

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

Execution
Z = 0;If (Period C[24:0] != 1FF_FFFFh) {Period C[24:0] = Period C[24:0] + 1;}
Register A = Period C[24:0];
If (specified capture edge detected on selected pin){
Z = 1;If (Period value != 1FF_FFFFh){
HR Capture Value = selected HR counter;}else{
HR Capture Value = 7Fh;}If (Interrupt Enable == 1) HETFLG[n] = 1;/* n depends on address */If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];}
If (specified reset edge detected on selected pin){
Period value = 0000000h;}
Prv bit = Current Logic (Lx) value of selected pin;
Jump to Next Program Address;

The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 17.2.7.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

683

Instruction Set

www.ti.com

17.5.3.17 PWCNT (Pulse Width Count)
SyntaxPWCNT {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][reqnum={3-bit unsigned integer}[request={NOREQ | GENREQ | QUIET}][hr_lr={HIGH | LOW}][control={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}[en_pin_action={OFF | ON}]pin ={pin number}[action={CLEAR | SET | PULSELO | PULSEHI}][reg={A | B | T | NONE}][irq={OFF | ON}][data={25-bit unsigned integer][hr_data={7-bit unsigned integer}]}

Figure 17-125. PWCNT Program Field (P31:P0)
31

26 25

23

22

21

13 12

9

8

7

6

5

0

0

RequestNumberBRK

Next program address

1010

hr_lr

11

Reserved

6

3

1

9

4

1

2

6

Figure 17-126. PWCNT Control Field (C31:C0)
31

29

28

27

26

25

23

22

21

16

Reserved

Request type

Control

Reserved

En. pinactionConditional address

3

2

1

3

1

9

15

13

12

8

7

5

4

3

2

1

0

Conditional address

Pin selectReserved

ActionRegister select

Int.
ena

9

5

3

2

2

1

Figure 17-127. PWCNT Data Field (D31:D0)
31

684

7

6

0

Data

HR Data25

7

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

CyclesOne

Register modified

Selected register (A, B or T)

Description

This instruction defines a virtual timer used to generate variable length pulses.
The counter value stored in the data field is decremented unconditionally oneach timer resolution until it reaches zero, and it then stays at zero until it isreloaded with a non-zero value.
The specified pin action is performed as long as the count after count value isdecremented is greater than 0. The opposite pin action is performed when the
count after decrement just reaches 0.
If the hr_lr bit is reset, the opposite pin action will be taken after a HR delay
from the next loop resolution clock. If the hr_lr bit is set, the delay is ignored.
This delay is programmed in bits [D6:D0].

irq

ON generates an interrupt when the data field value reaches 0. No
interrupt is generated for OFF.
Default: OFF.

data

25-bit integer value serving as a counter.

hr_data

HR delay.
Default: 0.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

685

Instruction Set

www.ti.com

Execution
If (Data field value == 0){
Selected register = 0;
Jump to Next Program Address;}
If (Data field value > 1){
Selected register = Data field value - 1;
Data field value = Counter value - 1;
If (Enable Pin action == 1){
Selected Pin = Pin Action AT next loop resolution clock;}Jump to Next Program Address;}
If (Data field value == 1){
Selected register = 0000000h;
Data field value = 0000000h;
If (Opposite action == 1){
If (hr_lr bit == 0){
If (Enable Pin action == 1){
Selected Pin = Opposite level of Pin Action AT next loop resolution clock+ HR delay;
}
}
else
{
If (Enable Pin action == 1){
Selected Pin = Opposite level of Pin Action AT next loop
resolution clock;}}
If (Interrupt Enable == 1) HETFLG[n] = 1;/* n depends on address */If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];}
Jump to Conditional Address}

The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 17.2.7.

686High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

17.5.3.18 RADM64 (Register Add Move 64)
SyntaxRADM64 {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]remote={label | 9-bit unsigned integer}[request={NOREQ | GENREQ | QUIET}][control={OFF | ON}]
[en_pin_action={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}][pin={pin number}]comp_mode={ECMP | SCMP | MCMP1 | MCMP2}[action={CLEAR | SET | PULSELO | PULSEHI}][reg={A | B | R | S | T | NONE}][irq={OFF | ON}][data={25-bit unsigned integer][hr_data= {7-bit unsigned integer}}-orSyntax

RADM64 {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]remote={label | 9-bit unsigned integer}
cntl_val={29-bit unsigned integer}[data={25-bit unsigned integer][hr_data= {7-bit unsigned integer}}

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

687

Instruction Set

www.ti.com

Figure 17-128. RADM64 Program Field (P31:P0)
31

26 25

23

22

21

13 12

9

8

0

0

Reserved

BRK

Next program address

0011

Remote Address

6

3

1

9

4

9

Figure 17-129. RADM64 Control Field (C31:C0)
31

29

28

27

26

25

23

22

21

16

Reserved

Request type

Control

Reserved

En. pinactionConditional address

3

2

1

3

1

9

15

7

6

Conditional address

13

12
Pin select

8

Ext
Reg

Comp. mode

5

4
Action3

Register select

2

1

Int.
ena

0

9

5

1

2

2

2

1

Figure 17-130. RADM64 Data Field (D31:D0)
31

7

6

0

Data

HR Data25

7

CyclesNormally One Cycle. Two cycles if writing to remote address that is also thenext address.

Register modified

None

Description

This instruction modifies the data field, the HR data field and the control fieldat the remote address. The advantage over DADM64 is that It executes one
cycle faster. In case the R, S, or T register is selected, the addition is a 32-bit
addition. The table description shows the bit encoding for determining which
ALU register is selected.
RADM64 has two distinct syntaxes. In the first syntax, bit values may be set
by assigning a value to each of the control fields. This syntax is convenient for
modifying control fields that are arranged similar to the format of the RADM64
control field. A second syntax, in which the entire 29-bit control field isspecified by the cntl_val field, is convenient when the remote control field isdissimilar from the RADM64 control field. Either syntax may be used, but you
must use one or the either but not a combination of syntaxes. See Figure 17131.
Figure 17-131. RADM64 Add and Move Operation
LSBs (HR data field)

32 bits
Immediate CF

Remote CF

comp_mode

688

HR

Immediate DF+

HRRegister A, B, R, S, or T(dashed for R, S, T)=

HR

Remote DF

Selects the comparison mode type to be used.

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

Table 17-66. Comparison Type Encoding Format
comp_mode

C[6]

C[5]

ECMP

0

0

MCMP Order

SCMP

0

1

MCMP1

1

0

REG_GE_DATA

MCMP2

1

1

DATA_GE_REG

Table 17-67. RADM64 Control Field Descriptions
requestControl
en_pin_action
cond_addr
pinregisteractionirq
data
hr_datacntl_val

Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Maintains the control field for the remote instruction.
Specifies the 25-bit initial value for the data field. If omitted, the field defaults to 0.
Seven least significant bits of the 32-bit data field.
Default: 0.
Specifies the 29 least significant bits of the Control field.

Execution
Remote Data Field = Selected register + Immediate Data Field (including HR field);
Remote Control Field = Immediate Control Field;
Jump to Next Program Address;

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

689

Instruction Set

www.ti.com

17.5.3.19 RCNT (Ratio Count)
SyntaxRCNT {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][control={OFF | ON}]divisor={25-bit unsigned integer}[data={25-bit unsigned integer]}

Figure 17-132. RCNT Program Field (P31:P0)
31

26 25

23

22

21

13 12

9

8

7

6

5

4

3

1

0

0

Reserved

BRK

Next program address

1010

Res.

00

Step
width

Res.

1

6

3

1

9

4

1

2

2

3

1

Figure 17-133. RCNT Control Field (C31:C0)
31

27

26

25

24

Reserved

ControlRes.

Divisor

0

5

1

1

25

Figure 17-134. RCNT Data Field (D31:D0)
31

7

6

0

Data

Reserved

25

7

CyclesTwo Cycles (One Cycle if T=0)

Register modified

None

Description

RCNT is used with other instructions to convert an input period measurement
TInput to the form of (Equation 33) where the input period is expressed as afraction of a reference period TReference.

æ N ö
T In p u t = T R e fe re n c e · ç
÷
èM ø

(33)

RCNT computes the numerator N of (Equation 33). The denominator M of(Equation 33) is a constant that is of interest. For example, choosing M = 100
allows the input period to be expressed as a percentage (%) of the reference
period. Note that if TInput > TReference , then RCNT will return N > M ; which would
be correct if for example the input pulse period is 110% of the reference pulse
period.
RCNT expects that register T is loaded with the value of TReference. The input
period TInput is determined by counting the number of loop resolution periods
between edges on the input pin. This information is conveyed through the Z
flag from a PCNT instruction that precedes the RCNT instruction.
The divisor field of the RCNT instruction should be chosen as:
Divisor = M ·lr , where M is the desired denominator from(Equation 33) and lr is the loop resolution prescale value.

690

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

An example N2HET program that makes use of the RCNT instruction is:
L0: MOV32 { remote=dummy,type=IMTOREG,reg=T,data=0x8,hr_data=0};
L1: PCNT { hr_lr=HIGH,brk=OFF,type=FALL2FALL,pin=0};
L2: RCNT { divisor=320,data=0x4};
L3: BR {cond_addr=L5, event = Z}
L4: ADC { src1=ZERO,src2=IMM,dest=IMM,next=L0,data=0,hr_data=0};
L5: ADD { src1=REM,src2=ZERO,dest=IMM,remote=L4,data=0,hr_data=0};
L6: ADD { src1=ZERO,src2=ZERO,dest=NONE,rdest=REM,
next=L0,remote=L4,data=0,hr_data=0};
dummy

In this small program an input signal on pin 0 is measured both in terms of absolute cycles by the PCNT
instruction at L1 and as in 1/10ths of the reference period by the RCNT instruction at L2. In this example
the reference period is a constant 0x400 cycles; this value is loaded into register T by the MOV32
instruction at L0. (0x400 is data=8, hr_data=0)
RCNT follows PCNT and is initialized to a working count of T/2 (0x200) whenever the PCNT instruction
detects a falling edge on pin 0. Between falling edges on pin0, RCNT accumulates counts 10x faster than
PCNT; so that the working data field of RCNT will reach the reference value of 0x400 in 1/10th the timethat a PCNT instruction would. Each time the RCNT instruction passes the reference value, it sets the
carry out flag and subtracts the reference value from the working count. By accumulating carry-outs from
RCNT, the add with carry instruction at L4 effectively counts in increments of 1/10th of the reference
period. Note that the divisor value 320 is 10 times 32; this assumes lr=32.
When the next falling edge is detected on pin 0, PCNT sets the Z flag and the RCNT instruction resets
again to the initial data field of T/2. RCNT does not modify the Z flag, so that the branch instruction at L3
can execute instructions at L5, L6 instead of L4. The instructions at L5 and L6 capture the final result fromL4 and reset the ADC instruction at L4 to zero for the start of the next period measurement.
Execution
If (register T[31:0] != 00000000h){
C = 0;
If (Z == 0){
Data Field[31:0] = Data Field[31:0] + Divisor[24:0];
If (Data Field[31:0] >= Reg T[31:0]){
Data Field[31:0]=Data Field[31:0] - Reg T[31:0];
C = 1;}}
else{
Data Field[31:0] = T[31:0] >> 1; /* T/2 */}}Jump to Next Program Address;

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

691

Instruction Set

www.ti.com

17.5.3.20 SCMP (Sequence Compare)
SyntaxSCMP {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][reqnum={3-bit unsigned integer}[request={NOREQ | GENREQ | QUIET}][control={OFF | ON}]
[en_pin_action={OFF | ON}]
cond_addr={label | 9-bit unsigned integer}pin ={pin number}[action={CLEAR | SET}][restart={OFF | ON}]
[irq={OFF | ON}][data={25-bit unsigned integer]}

Figure 17-135. SCMP Program Field (P31:P0)
31

26 25

23

22

21

13 12

9

8

0

0

RequestNumberBRK

Next program address

0000

Reserved

6

3

1

9

4

9

Figure 17-136. SCMP Control Field (C31:C0)
31

26

25

24

Reserved

29

Request type

Control

Cout
prv

Reserved

En. pinactionConditional address

3

2

1

1

2

1

9

15

13

28

27

12

Conditional address

8
Pin select

9

5

23

7

22

21

6

5

16

1

0

Res.

01

Action4

Reserved

3

2

Restartenable

Int.
ena

1

2

1

2

1

1

Figure 17-137. SCMP Data Field (D31:D0)
31

692

7

6

0

Data

Reserved

25

7

CyclesOne

Register modified

Register T (implicitly)

Description

This instruction alternately performs angle- and time-based operations togenerate pulse sequences, using the angle referenced time base. These
pulse sequences last for a relative duration using a free running time base.
Generally, register B holds the angle values and register A holds the timevalues. Bit 0 of the conditional address field (C13) specifies whether the
instruction is operating in angle or time operation mode.

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

When the compared values match in angle mode, a pin can be set or reset
according to the pin action bit (C4). The pin does not change states if theenable pin action bit (C22) is reset.
The restart enable bit (C1) provides the option to unconditionally restart asequence using the X-flag bit of ACMP.

restartIf restart is set to ON and the X flag = 1, the assembler writes a valueof 1 into the immediate index field, writes the value in register A into
the immediate data field, and jumps to the next program address. The
X flag is set or cleared by the ACMP instruction. If restart is set toOFF, the X flag is ignored; no special action is performed.
Default: OFF.

irq

ON generates an interrupt if the compare match occurs in angle
mode. No interrupt is generated when the field is OFF.
Default: OFF.

data

Specifies the 25-bit compare value.

cond_addr

Since the LSB of the conditional address is used to select between
time mode and angle mode, and since the conditional address istaken only in time mode, the destination for the conditional address
must be odd.

Execution
If (Data field value <= Selected register value) Cout = 0; else Cout = 1;
If (Restart Enable == 1 AND X == 1){
C13 = 1;
Immediate Data Field = Register A;
Cout = 0;
Jump to Next Program Address;}
If (Angle Mode (C13 == 0) AND ((Restart En. == 1 AND X == 0) OR Restart En. == 0)){
If (Z == 0 AND (Register B value - Angle Inc. < Data field value) AND Cout == 0) OR(Z == 1 AND (Cout_prv == 1 OR Cout == 0))){If (Enable Pin Action == 1) Selected Pin = Pin Action;
If (Interrupt Enable == 1) HETFLG[n] = 1;/* n depends on address */If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];
Immediate Data Field = Register A;
C13 = 1; /*** switch to Time Mode ***/}
Jump to Next Program Address;}
Else If (Time Mode (C13 == 1)) AND ((Restart En. == 1 AND X == 0) OR Restart En. == 0){/* Result of subtract must not exceed 2^24 - 1 */Register T = Register A - Immediate Data Field;
Jump to Conditional Program Address;}
Cout_prv = Cout; (always executed)

The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 17.2.7.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

693

Instruction Set

www.ti.com

17.5.3.21 SCNT (Step Count)
SyntaxSCNT {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
step={8 | 16 | 32 | 64}[control={OFF | ON}]
gapstart={25-bit unsigned integer}[data={25-bit unsigned integer]}

Figure 17-138. SCNT Program Field (P31:P0)
31

1

0

0

26 25

Reserved

23

BRK

22

21
Next program address

13 12

1010

9

8
Res.

7

00

6

5

Step
width

4

3

Res.

1

6

3

1

9

4

1

2

2

3

1

Figure 17-139. SCNT Control Field (C31:C0)
31

26

25

Reserved

27

ControlRes.

24
Gap start

0

5

1

1

25

Figure 17-140. SCNT Data Field (D31:D0)
31

7

6

0

Data

Reserved

25

7

CyclesOne or two cycles (two cycles when DF is involved in the calculations)Register modified

Register A

Description

This instruction can be used only once in a program and defines a specialized
virtual timer used after APCNT and before ACNT to generate an anglereferenced time base synchronized to an external signal (that is, a toothed
wheel signal) as defined in APCNT and ACNT. Step width selection bits are
saved in two flags, SWF0, and SWF1, to be re-used in ACNT.
SCNT multiplies the frequency of the external signal by a constant K definedin the step width field, [P5:P4]. The bit encoding for this field is defined inTable 17-68.

stepSpecifies the step increment to be added to the counter value eachprogram resolution. These two bits provide the values for the SWF0
and SWF1 flags. The valid values are listed in Table 17-68.

694 High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

Table 17-68. Step Width Encoding for SCNT
P5

P4

0

0

Step Width (K)
8

0

1

16

1

0

32

1

1

64

gapstart

Defines the gap start angle, which SCNT writes to register A. The gap
start value has no effect on the SCNT instruction, but if the ACNT
instruction is being used, register A must contain the correct gap startvalue. For a typical toothed wheel gear:
GAPSTART = (stepwidth × (actual teeth on gear - 1)) + 1.

data

Specifies the 25-bit integer value serving as a counter.
Default: 0.

This instruction is incremented by the step value K on each timer resolution up to the previous period
value P(n-1) measured by APCNT (stored in register T). The resulting period of SCNT is: P(n - 1)/K
Due to stepping, the final count of SCNT will not usually exactly match the target p(n-1). SCNT
compensates for this error by starting each cycle with the remainder of the previous cycle.
When SCNT reaches the target p(n-1), the zero flag is set as an increment condition for ACNT.SCNT also
specifies a gap start angle, defining the start of a range in ACNT where period measurements in APCNT
are temporarily stopped to mask singularities in the external signal.
SCNT uses register A to store the gap start value. Gap start has no effect for SCNT.
Execution
SWF1 = P5;
SWF0 = P4;
Z = 0;If (register T != 0000000h){
If (DCF == 1 OR ACF == 1){
Data Field register = 0000000h;
Counter value = 0000000h;}
If (DCF == 0 AND ACF == 0){
Data Field register = Data field register + Step Width;}
If ((Data Field register - register T) >= 0){
Data field register = Data Field register - register T;
Z = 1;}
Register A = Gap start value;}
Jump to Next Program Address;

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

695

Instruction Set

www.ti.com

17.5.3.22 SHFT (Shift)
SyntaxSHFT {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][reqnum={3-bit unsigned integer}[request={NOREQ | GENREQ | QUIET}]
smode={OR0 | OL0 | OR1 | OL1 | ORZ | OLZ | IRM | ILL | IRZ | ILZ}
[control={OFF | ON}]
[prv={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}cond={UNC | FALL | RISE}
pin ={pin number}[reg={A | B | R | S | T | NONE}][irq={OFF | ON}][data={25-bit unsigned integer]}

Figure 17-141. SHFT Program Field (P31:P0)
31

26 25

23

22

21

13 12

9

8

4

3

0

0

RequestNumberBRK

Next program address

1111

Reserved

Smode

6

3

1

9

4

5

4

Figure 17-142. SHFT Control Field (C31:C0)
31

29

27

26

25

Reserved

Request type

Control

Prv.

Reserved

Conditional address

3

2

1

1

3

9

15

13

28

12

24

8

22

7

21

6

5

16

4

3

2

1

0

Conditional address

Pin select

Ext
Reg

Shift condition

Res.

0

Register select

Int.
ena

9

5

1

2

1

1

2

1

Figure 17-143. SHFT Data Field (D31:D0)
31

696

7

6

0

Data

Reserved

25

7

CyclesOne

Register modified

Selected register (A, B, R, S or T)

Description

This instruction shifts the data field of the Instruction. N2HET pins can beused for data in or data out. SHFT includes parameters to select the shift
direction (in, out, left, right), shift condition (shift on a defined clock edge on
HET[0] or shift always), register for data storage (A, B, R, S or T), and thedata pin.

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

smode

Shift mode

Table 17-69. SHIFT MODE Encoding Format
smode

P3

P2

P1

P0

Operation

OR0

0

0

0

0

Shift Out / Right

LSB 1st on HETx / 0 into MSB

OL0

0

0

0

1

Shift Out / Left

MSB 1st on HETx / 0 into LSB

OR1

0

0

1

0

Shift Out / Right

LSB 1st on HETx / 1 into MSB

OL1

0

0

1

1

Shift Out / Left

MSB 1st on HETx / 1 into LSB

ORZ

0

1

0

0

Shift Out / Right

LSB 1st on HETx / Z into MSB

OLZ

0

1

0

1

Shift Out / Left

MSB 1st on HETx / Z into LSB

IRM

1

0

0

0

Shift In / Right

HETx into MSB

ILL

1

0

0

1

Shift In / Left

HETx into LSB

IRZ

1

0

1

0

Shift In / Right

HETx in MSB / LSB into Z

ILZ

1

0

1

1

Shift In / Left

HETx in LSB / MSB into Z

cond

Specifies the shift condition.

Table 17-70. SHIFT Condition Encoding
C6

C5

0

X

Shift Condition
Always10

Rising edge of HET[0]11

Falling edge of HET[0]irq

ON generates an interrupt if the Z flag is set. A value of OFF does not
generate an interrupt.
Default: OFF.

data

Specifies the 25-bit value for the data field.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

697

Instruction Set

www.ti.com

Execution
If (SHIFT condition == 0X)
OR (SHIFT condition == 10 AND HET[0] rising edge)
OR (SHIFT condition == 11 AND HET[0] falling edge){
If ([P3:P2] == 00){
If ((Immediate Data Field == all 0’s AND [P3:P0] == 000X)
OR (Immediate Data Field == all 1’s AND [P3:P0] == 001X)){
Z = 1;}else{
Z = 0;}}
else If ([P3:P0] == 1010){
Z = LSB of the Immediate Data Field;}
else if ([P3:P0] == 1011){
Z = MSB of the Immediate Data Field;}}
If( (Immediate Data Field == all 0’s) OR(Immediate Data Field == all 1’s)){if (Interrupt Enable == 1)
HETFLG[n] = 1;{/* n depends on address */}Jump to Conditional Address;}
else{
Jump to Next Program Address;}
Prv. bit = HET[0] Pin level; (Always executed)
Shift Immediate Data Field once according to P[3:0];
Immediate Data Field = Result of the shift;
Selected register = Result of the shift;
Jump to Next Program Address;

NOTE: The immediate data field evaluates all 0s or all 1s and is performed before the shiftoperation.

The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 17.2.7.

698

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

17.5.3.23 WCAP (Software Capture Word)
SyntaxWCAP {[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][reqnum={3-bit unsigned integer}[request={NOREQ | GENREQ | QUIET}][hr_lr={HIGH | LOW}][control={OFF | ON}]
[prv={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}]pin ={pin number}
event={NOCOND | FALL | RISE | BOTH}
reg={A | B | R | S | T | NONE}[irq={OFF | ON}][data={25-bit unsigned integer][hr_data={7-bit unsigned integer}]}

Figure 17-144. WCAP Program Field (P31:P0)
31

26 25

23

22

21

13 12

9

8

7

0

0

RequestNumberBRK

Next program address

1011

hr_lr

Reserved

6

3

1

9

4

1

8

Figure 17-145. WCAP Control Field (C31:C0)
31

26

25

Reserved

29

Request type

Control

Prv.

Reserved

Conditional address

3

2

1

1

3

9

15

13

28

27

12

24

8

22

21

5

16

7

6

Conditional address

Pin select

Ext
Reg

Capturecondition

4

Reserved

3

Register select

2

1

Int.
ena

0

9

5

1

2

2

2

1

Figure 17-146. WCAP Data Field (D31:D0)
31

7

6

0

Data

HR Data25

7

CyclesOne

Register modified

None

Description

This instruction captures the selected register into the data field if the specified
capture condition is true on the selected pin. This instruction can be used withall pins.
If the hr_lr bit is reset, the WCAP instruction will capture an HR time stamp
into the data field on the selected edge condition. If the hr_lr bit is set, the HR
capture is ignored.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

699

Instruction Set

www.ti.com

event

Specifies the event that triggers the capture.

Table 17-71. Event Encoding Format for WCAP
C6

C5

Capture Condition0

0

Always01Capture on falling edge

10Capture on rising edge

1

1Capture on rising and falling edge

irq

ON generates an interrupt when the capture condition is met. No
interrupt is generated for OFF.
Default: OFF.

data

Specifies the 25-bit integer value to be written to the data field or
selected register.

hr_data

HR capture value.
Default: 0.

NOTE: WCAP in HR Mode: The HR Counter starts on a WCAP instruction execution (in the first
loop clock) and will synchronize to the next loop clock. When N2HET is turned on and acapture edge occurs in the first loop clock (where the HR counter hasn’t been synchronized
to the loop clock), then the captured HR counter value is wrong and is of no use. So thecaptured HR data in the first loop clock should be ignored.

Execution
If (Specified Capture Condition is true on Selected Pin
OR Unconditional capture is selected){
Immediate Data Field = Selected register value;
If (hr_lr bit == 0) Capture the HR value in Immediate HR Data Field;
If (Interrupt Enable == 1) HETFLG[n] = 1;/* n depends on address */If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];
Jump to Conditional Address;}
Jump to Next Program Address;
Prv bit = Current Logic (Lx) value of selected pin; (always executed)

The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 17.2.7.

700High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Instruction Set

www.ti.com

17.5.3.24 WCAPE (Software Capture Word and Event Count)
SyntaxWCAPE {
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}][reqnum={3-bit unsigned integer}[request={NOREQ | GENREQ | QUIET}][control={OFF | ON}]
[prv={OFF | ON}]
[cond_addr={label | 9-bit unsigned integer}pin ={pin number}
event={NOCOND | FALL | RISE | BOTH}[reg={A | B | R | S | T | NONE}][irq={OFF | ON}][ts_data={25-bit unsigned integer][ec_data={7-bit unsigned integer}]}

Figure 17-147. WCAPE Program Field (P31:P0)
31

26 25

23

22

21

13 12

9

8

0

0

RequestNumberBRK

Next program address

1000

Reserved

6

3

1

9

4

9

Figure 17-148. WCAPE Control Field (C31:C0)
31

29

26

25

Reserved

Request type

Control

Prv.

Reserved

Conditional address

3

2

1

1

3

9

15

13

28

27

12

24

8

23

22

7

6

21

5

16

4

3

2

1

0

Conditional address

Pin select

Ext
Reg

Capturecondition

Reserved

Register select

Int.
ena

9

5

1

2

2

2

1

Figure 17-149. WCAPE Data Field (D31:D0)
31

7

6

0

Time Stamp

Edge Counter25

7CyclesOne

Register modified

None

Description

This instruction captures the selected register into the data field [D31:D7] andincrements an event counter [D6:D0] if the specified capture condition is trueon the selected pin. This instruction can be used with all pins, but the timestamp [D31:D7] has loop resolution only.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer (N2HET) Module
Copyright © 2018, Texas Instruments Incorporated

701

Instruction Set

www.ti.com

event

Specifies the event that triggers the capture.

Table 17-72. Event Encoding Format for WCAPE
C6

C5

Capture Condition0

0

Always01Capture on falling edge

10Capture on rising edge

1

1Capture on rising and falling edge

irq

ON generates an interrupt when the capture condition is met. No
interrupt is generated for OFF.
Default: OFF.

ts_dataSpecifies the 25-bit integer value for [D31:D7]
Default: 0.

ec_dataSpecifies the initial 7-bit integer value for [D6:D0].
Default: 0.

Execution
If (Specified Capture Condition is true on Selected Pin
OR Unconditional capture is selected){
Immediate Data Field[31:7] = Selected register value;
Immediate Data Field [6:0] = Immediate Data Field [6:0] + 1;
If (Interrupt Enable == 1) HETFLG[n] = 1;/* n depends on address */If ([C28:C27] == 01) Generate request on request line [P25:P23];
If ([C28:C27] == 11) Generate quiet request on request line [P25:P23];
Jump to Conditional Address;}
Jump to Next Program Address;
Prv bit = Current Logic (Lx) value of selected pin; (always executed)

The specific interrupt flag that is triggered depends on the address from which the instruction is executed,
see Section 17.2.7.

702

High-End Timer (N2HET) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Chapter 18
SPNU517C – March 2018

High-End Timer Transfer Unit (HTU) ModuleThis chapter describes the high-end timer transfer unit (HTU) module. The HTU is specialized to transfer
N2HET (High End Timer) data to or from the microcontroller RAM.
Topic

18.1
18.2
18.3
18.4
18.5
18.6

...........................................................................................................................

Page

Overview ......................................................................................................... 704
Module Operation ............................................................................................. 704
Use Cases ....................................................................................................... 717
Control Registers ............................................................................................. 720
Double Control Packet Configuration Memory ..................................................... 746
Examples......................................................................................................... 753

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

703

Overviewwww.ti.com

18.1 Overview
The HET transfer unit is a dedicated direct memory access controller that transfers data between the
N2HET RAM and RAM buffers located in the main memory address range. This eliminates time
consuming CPU accesses to the N2HET RAM to gather measurement data or creating output waveforms
and thus freeing up the CPU to perform other tasks.

18.1.1 Features
•
•
•
•
•
•
•
•
•

Independently transfers data between the N2HET and the main memory
8 double control packets supporting dual buffer configuration
Transfer requests generated by N2HET instructions/events
One shot, circular and auto switch buffer transfer modes for each double control packet for flexible
buffer handling
Constant and post-increment addressing modes
32- or 64-bit transactions
Programmable memory protection region
Parity protect control packet RAM
Extensive diagnostic functionality

18.2 Module Operation
The HTU is tightly coupled to the N2HET and is not intended to transfer data from other peripheral
modules. It initiates transfers with the help of requests generated by the N2HET program and configurable
control packets. Figure 18-1 shows a system block diagram of the HTU and the main path for the datatransfer. The tight coupling and the dedicated bus into the SCR (Switched Central Resource) reduces theamount of data transferred on the peripheral bus, which increases the overall system performance.
However if the application decides to use the direct CPU access method to the N2HET RAM, it is free todo so.
Figure 18-2 shows a more detailed block diagram of the HTU module.
Transfers between N2HET RAM and the main memory are triggered by 8 different normal N2HET
requests. Quiet requests are used for specific cases and are discussed in Section 18.2.4.1. Control
packets, which store the source and destination addresses, the transfer count and other information (seeSection 18.5), are associated with the requests. A FIFO decouples the read- and write-path and allows to
do data-packing in the case of different read- and write-data sizes. The application can specify a section ofmemory into or from which the data is transferred. This serves as memory protection in the case that
information in the control packet RAM was unintentionally altered and avoids that the HTU can overwrite
important application data.
Control packets are implemented as double control packets (DCP) that allow to specify two buffers for thedata transfer. This enables the CPU to work with one buffer, while new data is transferred to/from theother buffer.
The control packet defines:• the start address of the source/destination buffers• the N2HET instruction address location• how many elements need to be transferred per request• the buffer size as the number of elements times the number of frames• the buffer handling704

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

Figure 18-1. System Block Diagram

RAM0
Cortex-R4

SCR2

Main Datapath

Slave
Port

RAM1

Main Datapath

MasterPort

SCR

Peripheral Bus

HTU

NHET

Figure 18-2. HTU Block Diagram
HTU

NHET

Control
Data

Data
FIFO

Address
Memory Protection

Normal8

SCR2

RequestQuiet

8

RequestControl Packet
RAMwith Parity

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

705

Module Operation

www.ti.com

A transfer is triggered when a certain condition (for example, capture, compare condition) is detected by a
N2HET instruction. The N2HET instruction specifies which request line to the HTU will be triggered at theevent. The DCPs have a fixed assignment to the request lines and the corresponding assignment can befound in the device datasheet. Once a request is triggered, it starts a frame transfer. A frame can containone or more elements. Elements are defined as 32-bit or 64-bit words of data.
Figure 18-3. Example of a HTU Transfer
Element Count = 2
Frame Count = 4

Frame 1Element1

Frame 3

Frame 2Element2

HTUREQ

Element3

HTUREQ

Element4

Element5

Frame 4
Element6

HTUREQ

Element7

Element8

HTUREQ18.2.1 Data Transfers Between Main RAM and N2HET RAM
18.2.1.1 Addressing Modes
The addressing modes of a control packet need to be distinguished between the main RAM of the CPU
and the N2HET RAM.
Main RAMFor each double control packet (see Section 18.2.1.3) the addressing mode for the main RAM (RAM0/1)
can be configured to constant or post-increment mode in register IHADDRCT.
• Constant Addressing: In constant mode, the HTU writes/reads the data to/from the same address inthe main RAM.
• Post-increment Addressing: In post-increment mode, the HTU writes/reads the data to/from the main
RAM by incrementing through the addresses after each transfer. If 32-bit transfers are selected it willautomatically increment by 4 Byte, if 64-bit transfers are selected, it will increment by 8 Byte. The
examples of Use Cases illustrate the post-increment mode, where the elements of consecutive frames
are transferred to/from consecutive locations in the main RAM buffer.
N2HET RAMHow a DCP addresses the N2HET RAM is determined by the initial N2HET address, the initial element
counter (IETCOUNT) and the N2HET addressing mode (ADDMH). The main difference to the main RAM
addressing mode is that the HET address is reset to the initial HET address for every first element of aframe. To implement constant addressing, the initial element counter needs to be set to 1. Post-increment
addressing is selected by programming the initial element counter to a value other than 1.

706

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

18.2.1.2 Single Buffer Implementation
In a single buffer implementation, the DCP is set up to transfer data to/from a single buffer in the main
RAM. With each transfer request, the programmed number of elements is transferred and the buffer
pointer is reset to its starting address after the programmed number of frame transfers have completed.
Figure 18-4 shows the request on one request line of the HTU and the frame running on the assigned
control packet visualized by the element counter. In the diagram, the frame has 5 element transfers(element count = 5).
Before the application reads the buffer, it has to disable the control packet to avoid that new data
overwrites the buffer while it's being accessed by the application. Regardless of the control packet being
disabled at t1 or t2 the last frame will always be completed, since the trigger request has been received
already. The application can determine any ongoing transfers by the TIPF flag and the NACP bits.
• One Shot Buffer Mode: If TMBA or TMBB is set to one shot buffer mode then the data stream willstop after all elements of buffer A or buffer B have been transferred. This means that thecorresponding DCP will be disabled after the last frame was transferred to/from buffer A or B and
CFTCTA or CFTCTB decrements to 0.
• Circular Buffer Mode: If TMBA or TMBB is set to circular buffer mode, then the data stream willcontinue back at the start of buffer A or B after all elements of buffer A or B have been transferred.The
example of Timing Example for Circular Buffer Mode assumes IETCOUNT=3 (Initial Element Transfer
Count), IFTCOUNT=3 (Initial Frame Transfer Count, SIZE=0 (Size of Transfer = 32-bit) and ADDFM=0(Addressing Mode Main Memory = Post Increment). So there are in total 9 32-bit values in the buffer. It
also assumes IFADDRx=10h. "U" means uninitialized.
Figure 18-4. Single Buffer Timing and Memory Representationt1
TU request (1)Element Counter
Element Number

XXX
5 4 3 2 1
6 7 8 9 10

5 4 3 2 1
1 2 3 4 5t2
5 4 3 2 1
11 12 13 14 15

Memory View

15
14
13
12

Increasing Address

11
10
9
1 Buffer

8
7
15
6
15
5
15
4
15
3
15
2
15
1

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

707

Module Operation

www.ti.com

Figure 18-5. Timing Example for Circular Buffer Modeend ofbufferend ofbufferrequest3

element counter
buffer location

2

1

3

2

1

3

1Ch 20h 24h

10h 14h 18h

2

1

3

2

1

3

10h 14h 18h

28h 2Ch 30h

2

1

3

1Ch 20h 24h2

1

28h 2Ch 30hbusy bitframe counter
CFTCTx

U

2

1

0

2

1

full address
CFADDRx

U

1Ch

28h

34h

1Ch

28h

buffer full flag
BFINTFL

708

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

18.2.1.3 Dual Buffer Implementation
The transfer unit provides double control packets (DCPs) supporting the use of two buffers per data
stream (per HTU request source). If one buffer should be read by the CPU, the data stream is directed tothe other buffer and the first buffer is frozen. Switching to the other buffer can be triggered with a write
access to the CPENA register or with the DCP configured to automatically switch to the other buffer when
the programmed number of frames has been transmitted. Freezing the buffer avoids this buffer to be
overwritten with new HET data while the CPU reads this buffer.
Figure 18-6 shows a timing example of two HET instructions 1 and 2, which are the request sources for
the HTU (and are controlled by DCP 1 and DCP 2). Each generated frame has 5 element transfers.
Request source 1 has two RAM buffers, controlled by two control packets 1A and 1B. Request source 2
has two RAM buffers, controlled by two control packets 2A and 2B.
Figure 18-6. Dual Buffer Timing
t1
TU request (1)Element Counter 1A
Element Counter 1B
Element NumberX

TU request (2)Element Counter 2A
Element Counter 2B
Element NumberXX

5 4 3 2 1

5 4 3 2 1

1 2 3 4 5

6 7 8 9 10XXX
5 4 3 2 1
11 12 13 14 15

5 4 3 2 1
16 17 18 19 20X

5 4 3 2 1

5 4 3 2 1

1 2 3 4 5

6 7 8 9 10X
5 4 3 2 1
11 12 13 14 15
t3

t2

5 4 3 2 1
16 17 18 19 20

SPNU517C – March 2018
Submit Documentation Feedback

10
9
8
7
6
5
4
3
2
1

Buffer 1A

SwitchIncreasing Address

Increasing Address

Memory View for DCP-1A/B

10
9
8
7
6
5
4
3
2
1

Buffer 1A

20
19
18
17
16
15
14
13
12
11

Buffer 1B

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

709

Module Operation

www.ti.com

Figure 18-6 shows a switch at time t1, where buffer 1A is frozen and data stream 1 is directed to buffer
1B, but only after the frame has been completed. It also shows the time (t2 or t3) where 2A is frozen anddata stream 2 is directed to buffer 2B. If the switch happens between the request and the start of theframe (for example, time t3), then the frame is processed by the new control packet (although the oldcontrol packet was active at the time of the request). The delays between the HTU requests and the startof the element transfers result from the fact that the HTU can process only one transfer at a time.
Auto Switch Buffer Mode
If TMBA is set to auto switch mode, then the data stream will continue at the start of buffer B after all
elements of buffer A have been transferred. This means that in the CPENA register, CP A is disabled and
CP B is enabled automatically and buffer B uses its initial main memory address and initial frame counterto start. The same principle is valid for TMBB and buffer B.
The examples of Figure 18-7 assumes IETCOUNT=3 (Initial Element Transfer Count), IFTCOUNT=3(Initial Frame Transfer Count, SIZE=0 (Size of Transfer = 32-bit) and ADDFM=0 (Addressing Mode Main
Memory = Post Increment). So there are in total 9 32-bit values in buffer A and B. It also assumes
IFADDRB=10h and IFADDRA=40h. "U" means uninitialized.
Figure 18-7. Timing Example for Auto Switch Buffer Mode
autoswitchauto
switchrequestelement counter3

buffer location

2

1

3

10h 14h 18h

2

1

3

1Ch 20h 24h

2

1

3

2

1

3

2

1

3

2

1

28h 2Ch 30hbusy bitframe counter
CFTCTBU

2

1

0full address
CFADDRB

U

1Ch

28h

34h

buffer full flag
BFINTFLbuffer location

40h 44h 48h4Ch 50h 54h58h 5Ch 60hbusy bit

710

frame counter
CFTCTA U

2

1

0

full address
CFADDRA U

4Ch

58h

64h

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

18.2.1.4 General Control Packet Behavior
The action defined by the selected mode will be performed at the end of the last frame, which has theframe counter value of 1. The one shot and auto switch mode will automatically update the CPENA
register at this time. Note, that for all three modes listed above, it is possible to switch to the other buffer
by writing to CPENA before the end of the current buffer is reached.
If a write access to CPENA happens while the last frame of DCP x (with frame counter = 1) is transferredthen the priority is defined by Table 18-1.
Table 18-1. CPENA / TMBx Priority Rules
Write access to CPENA bits (2*x+1) and (2*x) during theframe with frame counter = 1 ( (1))

Priority Rule

Disable:01 --> 00 or
10 --> 00

Disabling the DCP by the write to CPENA has priority, TMBx is
ignored.

Stay:
01 --> 01 or
10 --> 10

The write access to CPENA is ignored, TMBx has priority anddefines the action.

Switch:01 --> 10 or
10 --> 01

Switching the DCP by the write to CPENA has priority, TMBx is
ignored.

(1)

See read table of CPENA register (Table 18-14)

There could be a case where the CPU wants to do main memory operations, but does not want the HTU
modifying the main memory. It could happen that a request was already active, but the frame transfer
hasn't started yet when the application disabled the control packets. The timing diagram in Figure 18-8
shows this scenario.
Figure 18-8. Timing for Disabling Control Packets
DCP Disable
RequestBusy Bit
Frame Start

Since the request for the transfer was already received before the DCPx is disabled, the HTU will still start
the frame transfer. The application would poll the BUSYx bit during the time the DCPx was disabled andbefore the frame was started and would read a non-busy information. It then would start the main memory
operations thinking all transfers have completed, however after some time the HTU will start theoutstanding frame transfer and corrupt the main memory.
To avoid this, the application can set the VBUSHOLD bit to disable all transactions between the HTU andthe main memory. It has to poll the BUSBUSY bit to ensure that no outstanding transactions on the bus
are pending. The HTU will still receive all transfer requests from the N2HET, but it will not be able totransfer any data to or from the main memory, while the VBUSHOLD bit is set.

18.2.2 Arbitration of HTU Elements and Frames••

Frames do not interrupt each other. If a request occurs on DCP x while another frame runs on DCP y(and x ≠ y), then the current frame completes before the new frame starts.
If two or more request lines are active, the request line with the lower number (specified in the request
number field of the corresponding N2HET instruction) is serviced first.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

711

Module Operation

www.ti.com

18.2.3 Conditions for Frame Transfer Interruption
If a frame is currently transferred on DCP x and one of the events listed below happens, then the event
will (1.) clear the element counter of DCP x, (2.) stop new element transfers on DCP x (3.) clear the active
busy bit of DCP x and (4.) disable DCP x in the CPENA register. The DCPs other than DCP x will not beaffected.
• Request Lost Error of DCP x (with CORL bit set to 0).
• Parity Error of DCP x (with parity check enabled and COPE bit set to 0). See also Section 18.2.6.
• Bus Error of DCP x.
• Memory Protection Error of DCP x (with memory protection enabled). See also Section 18.2.5.
• Writing a 1 to a BUSY bit (belonging to DCP x) if that bit is 1. There is no effect if the BUSY bit is 0.
• Writing a 1 to the HTURES bit.
When a memory protection error occurs, the access to the protected address is blocked. The frame isstopped before the element, which caused the violation transfer, starts. All other errors will let the current
element transfer finish.
In case of the Request Lost and Bus Error, one more element transfer goes on the bus, before the frameis actually stopped. Accordingly, the busy bit is cleared after the element, which follows the element thatcaused the error.
In case of the Bus Error, the counter for the element, which follows the element that caused the error, iscaptured to the ERRETC register field.
NOTE: If the HTUEN bit is cleared during a frame is transferred, then the frame will be completed
before the HTU is disabled.

18.2.4 HTU Overload and Request Lost Detection
If the number of different HTU request sources is "high", the period between the requests is "short" and/or
the initial element counter values are "big", then the HTU could get into a overload situation. In Figure 189, all requests marked with "L" are lost, since their frame is not completed at the time the next request
occurs. Each number in the rows "TU request (x)" represents a time, where the associated N2HET
instruction generates a request on DCP x. The arrows in Figure 18-9 point to the associated frame, which
could be delayed compared to the request. The delays are caused by different frames, which are currently
processed. The figure assumes that the CORL bit in the RLBECTRL register is set, which causes the DCP
to stay enabled and let the data stream continue after a request lost error occurred on the DCP (see 3-L
for TU request (2)).
Figure 18-9. Timing Example Including Lost Requests
1
TU request (1)Element Counter
54321
TU request (2)Element Counter

2

3
54321

1

2

3-L
54321

54321
1

TU request (3)ElementCounter

454321 54321

2

4
54321
3-L

54321

Lost requests are signaled with the RLOSTFL register, and if enabled, can generate request lostinterrupts.
If the CORL bit is set, a frame will be completed and the corresponding DCP stays enabled even if arequest lost was generated during this frame.
In dual buffer mode, the request lost detection works continuously, independent of the CP switches.

712

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

18.2.4.1 Requests and Quiet Requests
In addition to generating too many transfer requests and thus overloading the HTU and not being able totransfer data at all, it can happen that inconsistent data is transferred. The following examples illustratesuch scenarios.
In the examples below, the HTU reads a frame of three elements from the datafield of three different
instructions. In Figure 18-10, the L3-Instruction generates the HTU request at time t2, t7, and so on. andthe according frame (at t3). The frame is delayed because of the HTU load. However, as shown in
Figure 18-10, the delay still allows the frame to complete before the datafield of instruction L1 is updated
again. However, when the delay is longer (as shown in Figure 18-11), then the frame could fall into theN2HET loop (LRP), in which the N2HET updates the data fields of the L1, L2 and L3 instructions. In thiscase, the HTU could read inconsistent data as shown in the diagram. A wrong (new) value is read from L1(at time t3), but correct ("old") values are read from L2 and L3 (at times t4 and t5).
Figure 18-10. Timing which Generates No Request Lost Error
LRP
SignalQuiet Request

Quiet Request

L1_Instr_DF[31:7]

3

6

L2_Instr_DF[31:7]

1

L3_Instr_DF[31:7]

2
3

2
Delay caused by TU load
t1 t2

t3 t4 t5

t6 t7

Frame

RequestRequestFigure 18-11. Timing which Generates a Request Lost Error
LRP
SignalQuiet Request

Quiet Request

L1_Instr_DF[31:7]

3

6

L2_Instr_DF[31:7]
L3_Instr_DF[31:7]

1

2
2

3
Delay caused by TU load

t1 t2

t3 t4 t5 t6 t7
Frame
RequestRequestTo prevent sending inconsistent data, the N2HET instructions are able to generate a quiet request, which
does not originate a transfer but is only used by the HTU for consistency check. If a frame has notcompleted since the last request (or has not even started) at the time the quiet request occurs, then the
HTU signals a request lost error. All instructions, which allow to generate a request can be configured togenerate a quiet request instead. So in the examples of Figure 18-10 and Figure 18-11, instruction L1
should be configured to generate a quiet request and instruction L3 to generate a normal request. In thecase of Figure 18-11, the corresponding bit in the RLOSTFL register will be set.
It is the responsibility of the N2HET software to enable a quiet request for the first instruction of an
instruction block, which is addressed by DCP x, and to enable a normal request only for the last
instruction of this block. Since enabling the quiet request should enable a proper request lost detection for
DCP x, both N2HET instructions need to specify the same DCP x (reqnum=x).
SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

713

Module Operation

www.ti.com

The control fields of the HET instructions provide a 2-bit field to configure one of the following possibilities(as shown in Table 18-2). A 3-bit field in the program field will select which of the 8 Double Control
Packets will be triggered by the request.
Table 18-2. Triggered Control Packets
Request Type Bit 1 Request Type Bit 0

Request Number

Don't care0

No request

0

1

Generate normal request

1

1

Generate quiet request

Specify number 0, 1,... or 7, which selects
the HTU request line

In the case of very light HTU load, but higher signal requirements (for example, high frequency), the quiet
request could also be used to define periods in which the data read by a control packet is safe. The
following HET code will capture counter time stamps to the L1-WCAP data field after rising edges (at pin
CC6) and to the L2-WCAP data field after falling edges (at pin CC6):
L0 CNT {reg=A, max=0x1FFFFFF}
L1 WCAP {reqnum=3, request=GENREQ, event=RISE, reg=A, pin=CC6}
L2 WCAP {reqnum=3, request=QUIET, event=FALL, reg=A, pin=CC7}; HET HRSHARE feature configured to assign both WCAPs to pin CC6

The HTU frame will have two elements: The first gives the time stamp of the rising edge r(n) and thesecond gives the time stamp of the previous falling edge f(n-1). Using the code above, requests (R) andthe quiet requests (QR) will occur at the times shown in Figure 18-12, and a request lost will only besignaled when the frame makes an access during the times marked with RL. So reading [22, 21] as frame
elements is correct. If the signal frequency would increase, then a wrong pair [22, 23] could be read, but
this will be signaled by a request lost error since at least e2 falls into the RL period.
Figure 18-12. Timing Example for Two WCAP Instructionsf(n-1)

LRP

r(n)

f(n)

r(n+1)Pin CC6
L00-CNT-DF

20

21

22

L01-WCAP-DF

23

24

22

R
L02-WCAP-DF

24

21
QR
OK

QR
RL

OK

RL

e1 e2
e2
TU Delay Frame

18.2.5 Memory Protection
This feature allows restricting accesses to certain areas in memory in order to protect critical application
data from unintentionally being manipulated by the HTU.
If the HTU memory protection feature is disabled, the full 4 GB address range can be accessed by the
HTU without exception. There are two memory regions that start and end addresses can be configured.
With the HTU memory protection feature enabled, read and write accesses by the HTU IFADDRA andIFADDRB registers inside the defined regions are allowed. HTU access to its tightly-coupled memory is
independent of the MPU, it routes through the dedicated HTU/NHET bus using the IHADDR bits in the
IHADDRCT register. See Section 18.2 for details on the tightly-coupled bus.

714

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

For accesses outside the regions, one of two modes is configurable:• Any access performed by the HTU is forbidden and will be signaled to the ESM module. Writeaccesses will be blocked.
• Read access is allowed but write access will be blocked and signaled to the ESM module.
To use one region only, REG01ENA must be 0. Bits ACCR01, INTENA01, and register settings of MP1S
and MP1E will be ignored.
To use both regions, the following rules must be followed:
1. Memory mapped region 0 covers a lower memory area as Memory mapped region 1.
2. REG01ENA is a 1 and REG0ENA is a 0.
3. ACCR01 is set for the desired access type, ACCR0 is ignored.
4. INTENA01 is set for the desired action, INTENA0 is ignored.
If an element transfer of DCP x generates a memory protection error, then:
1. The element counter of DCP x is cleared.
2. All new element transfers on DCP x are stopped.
3. The active busy bit of DCP x is cleared.
4. DCP x is disabled in the CPENA register. The DCPs other than DCP x will not be affected.
5. The FT flag will be set.
6. An error is signaled to the ESM module.

18.2.6 Control Packet RAM Parity Checking
The HTU module can detect parity errors in the DCP (Double Control Packet) RAM. DCP RAM parity
checking is implemented using one parity bit per byte. Even or odd parity checking can be selected in the
DEVCR1 register of the system module and can be enabled/disabled by a 4-bit key in the PCR register.
During a read access to the DCP RAM, the parity is calculated based on the data read from the RAM andcompared with the good parity value stored in the parity bits. The parity check is performed when the HTU
or any other master (for example, CPU) makes a read access to the DCP RAM. A read access within the
RAM section of an initial or current DCP checks all 16 bytes of the DCP at a time (see also DCP memorymap). For example, if a byte read access happens for DCP RAM address 0, but there is a parity error atbyte address Ch then the parity error will occur and the captured parity address will be Ch and not 0. The
address of the byte in which the error occurred can be read from the PAR register. If successive DCP
RAM read accesses generate multiple parity errors, only the address of the first detected error will be
captured and the PAR register will not be updated by subsequent errors until it is read by the application.
When multiple errors in a 16 byte word are detected, only the address of the lowest byte will be captured.
The application can decide whether to stop any transfers when a parity error is detected or to continuetransferring data. If the COPE (Continue On Parity Error) bit is 0 and parity checking is enabled, then the
HTU will not start the frame and the corresponding DCP will be automatically disabled in the CPENA
register. If a master other than the HTU (for example, CPU) reads the RAM section of DCP x and a parity
error is detected during this read access, while the parity check is enabled and the COPE bit is 0, then the
DCP x will be automatically disabled in the CPENA register. If a frame for this DCP x is ongoing during
this read access, then in addition the element counter of DCP x is cleared, all new element transfers on
DCP x are stopped and the active busy bit of DCP x is cleared. With COPE set to 1 and the parity checkenabled, the parity checking will still be performed, but the data transfer of an active DCP continues after
a parity error was detected for this DCP. So neither the DCP with the parity error will be disabled nor theframe will be stopped.
After a DCP is enabled (with CPENA using BIM = 0), then at the start of the first frame, the HTU performs
the parity check only on the initial DCP, since it does not need the current DCP information. For further
frames, the HTU performs the parity check for both initial and current DCP, since it needs bothinformation.
On a parity error detection, an error will also be signaled to the ESM module.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

715

Module Operation

www.ti.com

18.2.6.1 Parity Bit Mapping and Testing
To test the parity checking mechanism, the parity RAM can be made accessible in order to allow manual
fault insertion. Once the TEST bit is set, the parity bits are mapped to address FF4E 0200h.
When in test mode (the parity RAM is accessible), no parity checking will be done when reading fromparity RAM, but parity checking will still be performed for read accesses to the DCP RAM.
Table 18-3 and Table 18-4 show how the corresponding parity bits of the DCP RAM bytes are mapped
into the memory.
Each byte in DCP RAM has its own parity bit in the DCP Parity RAM. P0 is the parity bit for byte 0, P1 isthe parity bit for byte 1 and so on.
Table 18-3. DCP RAM
Bit

31

24

23

16

15

8

7

0

FF4E 0000h

Byte 0

Byte 1

Byte 2FF4E 0004h

Byte 4

Byte 5

Byte 6

Byte 3
Byte 7

FF4E 0008h

Byte 8Byte 9Byte 10

Byte 11

FF4E 000Ch

Byte 12

Byte 13

Byte 14

Byte 15

Table 18-4. DCP Parity RAM
Bit

24

16

8

0

FF4E 0200h

P0

P1

P2

P3

FF4E 0204h

P4

P5

P6

P7

FF4E 0208h

P8

P9

P10

P11

FF4E 020Ch

P12

P13

P14

P15

18.2.6.2 Initializing Parity Bits
After device power up, the DCP RAM content including the parity bit cannot be guaranteed. In order toavoid parity failures, when reading DCP RAM, the RAM has to be initialized first. This can simply be doneby writing known values into the RAM by software and the corresponding parity bit will be automaticallycalculated.
Another possibility to initialize the DCP memory and its parity bits is to use the system module, which is an
on-chip module external to the HTU. This module can start the automatic initialization of all RAMs on the
microcontroller including the HTU DCP RAM. This function initializes the complete DCP RAM to "0' when
activated by the system module. Depending on the even/odd parity selection, all parity bits will becalculated accordingly. The HTUEN bit must be cleared and the parity functionality must be enabled (byPARITY_ENA) during the automatic DCP RAM initialization. If HTUEN is 1 when the initialization istriggered by the system module, then the initialization will not be performed and the HTU operation is notaffected. If a 1 is written to HTUEN during the initialization, then the HTUEN bit will be set but the HTU will
not be enabled before the initialization completes.

716

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Use Cases

www.ti.com

18.3 Use Cases
18.3.1 Example: Single Element Transfer with One Trigger Request
This example considers the case that the HTU fills a RAM buffer in the main (CPU) data RAM. The HTU
reads from the instruction which generates the HTU requests.
This example uses a PCNT instruction. Every time the PCNT has captured a new pulse or period value, itwill automatically generate a transfer request to the HTU, which then transfers the value from the N2HET
RAM to the buffer RAM. So over time consecutive locations in the RAM buffer can be filled withconsecutive measurement values captured into the N2HET RAM data field of the same PCNT instruction
without loading or interrupting the CPU.

18.3.2 Example: Multiple Element Transfer with One Trigger Request
The following example shows how the HTU could be used to fill a RAM buffer with a data stream including
different types of measurement values belonging to the same N2HET input signal (on one pin): Time
stamp values (WCAP), edge counter values (ECNT) and last period values (PCNT).
Figure 18-13 shows the timing and Table 18-5 shows the byte addresses of the program- (PF), control(CF), data- (DF) and reserved field (res) of the WCAP-ECNT-PCNT instruction block. The timing and code
example assumes that all three instructions are assigned to the same N2HET pin.
Figure 18-13. Timing of the WCAP, ECNT, PCNT Example

CNT

2

WCAP

3

5

4

1

9

12

10
3
3

Quiet Request
Request

11

10

2
2

PCNT

8

6

3

ECNT

7

6

4

Quiet Request
RequestQuiet Request
RequestTable 18-5. Field Addresses of the WCAP, ECNT, PCNT Example
PF

CF

DF

Res

WCAP

30h

34h

38h

3Ch

ECNT

40h

44h

48h

4Ch

PCNT

50h

54h

58h

5Ch

In the HET code, the HTU request is enabled only for the last instruction (PCNT) of the WCAP-ECNTPCNT block. When the PCNT condition is true, it will cause the generated HTU frame to perform three
HTU element reads from the data fields of WCAP, ECNT, and PCNT.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

717

Use Cases

www.ti.com

32-Bit-Transfer of data fields:
Table 18-6 shows how the internal element counter, frame counter, and the address registers change overtime for the example described above. Every time the PCNT instruction captures a new value it generates
a request to the HTU, which starts a frame. At the end of each frame the frame counter decrements.
Table 18-6. 32-Bit-Transfer of Data Fields (1)Frame Counter

3

2

1

Element Counter

3

2

1

3

2

1

3

2

1

Source Address (HET)

38h

48h

58h

38h

48h

58h

38h

48h

58h

Destination Address (main CPU RAM)

70h

74h

78h

7Ch

80h

84h

88h

8Ch

90h

(1)

The diagram shows the byte addresses

The destination buffer is filled with the WCAP, ECNT, and PCNT data field values shown in Table 18-7.
Table 18-7. Destination Buffer Values
Address

Frame Count

Instruction

Value

70h

3

WCAP

3

74h

3

ECNT

1

78h

3

PCNT

2

7Ch

2

WCAP

6

80h

2

ECNT

2

84h

2

PCNT

3

88h

1

WCAP

10

8Ch

1

ECNT

3

90h

1

PCNT

4

The corresponding setup of the HTU control packet for this example is as follows:
IHADDR= 0x38// points to WCAP data field
IFADDRA= 0x70// points to buffer
ITCOUNT [frame count = 3] [element count = 3]
IHADDRCT = [DIR: Read HET and write to full address][SIZE: 32 bit]
[ADDMH: Increment HET address by 16 bytes][ADDMF: Post increment full address mode][Any transfer mode]

718

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Use Cases

www.ti.com

18.3.3 Example: 64-Bit-Transfer of Control Field and Data Fields
Table 18-8 shows how the internal element counter, frame counter, and the address registers change overtime assuming the same example as in Section 18.3.2, but now with a transfer size set to 64-bit. The HET
address now points to the control field of the instruction, so CF and DF are transferred as 64 bit data.
Table 18-8. 64-Bit-Transfer of Control Field and Data Fields (1)Frame Counter

3

2

1

Element Counter

3

2

1

3

2

1

3

2

1

HET (Source) Address

34h

44h

54h

34h

44h

54h

34h

44h

54h

Full (Destination) Address

70h

78h

80h

88h

90h

98h

A0h

A8h

B0h

(1)

The diagram shows the byte addresses.

The destination buffer is filled with the WCAP, ECNT, and PCNT control and data field values shown in
Table 18-9.
Table 18-9. Destination Buffer Values
Address

Frame Count

Instruction

Value

70h

3

WCAP

Control Field Value

74h

3

WCAP

3

78h

3

ECNT

Control Field Value

7Ch

3

ECNT

1

80h

3

PCNT

Control Field Value

84h

3

PCNT

2

88h

2

WCAP

Control Field Value

8Ch

2

WCAP

6

90h

2

ECNT

Control Field Value

94h

2

ECNT

2

98h

2

PCNT

Control Field Value

9Ch

2

PCNT

3

A0h

1

WCAP

Control Field Value

A4h

1

WCAP

10
Control Field Value

A8h

1

ECNT

ACh

1

ECNT

3

B0h

1

PCNT

Control Field Value

B4h

1

PCNT

4

The necessary setup of the HTU control packet (see Section 18.5) for this example is as follows:
IHADDR= 0x34 (points to WCAP control field)
IFADDR= 0x70 (points to buffer)
ITCOUNT [frame count = 3] [element count = 3]
IHADDRCT = [DIR: Read HET and write to full address][SIZE: 64 bit]
[ADDMH: Increment HET address by 16 bytes][ADDMF: post increment full address mode][Any transfer mode]

For different applications, which have the transfer direction set for reading the buffer and writing to HET
fields, the 64-bit transfer could be used to change the conditional addresses together with a new data
field.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

719

Control Registers

www.ti.com

18.4 Control Registers
Table 18-10 provides a summary of the registers. The registers support 8-bit, 16-bit, and 32-bit writes. The
offset is relative to the associated peripheral select. See the following sections for detailed descriptions of
the registers. The base address for the control registers is FFF7 A400h. The address locations not listed,
are reserved.
Table 18-10. Control Register Mapping

720

OffsetAcronym

Register Description

Section00h

HTU GC

Global Control Register

Section 18.4.1

04h

HTU CPENA

Control Packet Enable Register

Section 18.4.2

08h

HTU BUSY0

Control Packet Busy Register 0

Section 18.4.3

0Ch

HTU BUSY1

Control Packet Busy Register 1

Section 18.4.4

10h

HTU BUSY2

Control Packet Busy Register 2

Section 18.4.5

14h

HTU BUSY3

Control Packet Busy Register 3

Section 18.4.6

18h

HTU ACPE

Active Control Packet and Error Register

Section 18.4.7

20h

HTU RLBECTRL

Request Lost and Bus Error Control Register

Section 18.4.824h

HTU BFINTS

Buffer Full Interrupt Enable Set Register

Section 18.4.928h

HTU BFINTC

Buffer Full Interrupt Enable Clear Register

Section 18.4.10

2Ch

HTU INTMAPInterrupt Mapping Register

Section 18.4.11

34h

HTU INTOFF0

Interrupt Offset Register 0

Section 18.4.12

38h

HTU INTOFF1

Interrupt Offset Register 1

Section 18.4.13

3Ch

HTU BIM

Buffer Initialization Mode Register

Section 18.4.14

40h

HTU RLOSTFL

Request Lost Flag Register

Section 18.4.15

44h

HTU BFINTFL

Buffer Full Interrupt Flag Register

Section 18.4.16

48h

HTU BERINTFL

BER Interrupt Flag Register

Section 18.4.17

4Ch

HTU MP1S

Memory Protection 1 Start Address Register

Section 18.4.18

50h

HTU MP1E

Memory Protection 1 End Address Register

Section 18.4.19

54h

HTU DCTRL

Debug Control Register

Section 18.4.20

58h

HTU WPR

Watch Point Register

Section 18.4.21

5Ch

HTU WMR

Watch Mask Register

Section 18.4.22

60h

HTU ID

Module Identification Register

Section 18.4.23

64h

HTU PCR

Parity Control Register

Section 18.4.24

68h

HTU PAR

Parity Address Register

Section 18.4.25

70h

HTU MPCS

Memory Protection Control and Status Register

Section 18.4.26

74h

HTU MP0S

Memory Protection 0 Start Address Register

Section 18.4.27

78h

HTU MP0E

Memory Protection 0 End Address Register

Section 18.4.28

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

18.4.1 Global Control Register (HTU GC)
Figure 18-14. Global Control Register (HTU GC) [offset = 00]
31

25

24

23

17

16

Reserved

VBUSHOLD

Reserved

HTUEN

R-0

R/WP-0R-0

R/WP-0

15

9

8

7

1

0

Reserved

DEBM

Reserved

HTURES

R-0

R/WP-0R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 18-11. Global Control Register (HTU GC) Field Descriptions
Bit

Field

31-25

Reserved

24

VBUSHOLD

23-17

Reserved

16

HTUEN

Value
0

Description
Reads return 0. Writes have no effect.
Hold the VBUS bus.

0

The VBUS is not held.

1

The VBUSHOLD bit holds the bus used to transfer data between the HTU and the N2HET module.
When the BUS_BUSY bit is 0, then the bus is no longer busy. While the bus is held, requests will stillbe accepted. They will be acted upon when the VBUSHOLD is 0. Request lost conditions will be
detected and interrupts generated if they are enabled.

0

Reads return 0. Writes have no effect.
Transfer Unit Enable Bit.

0

The Transfer Unit is disabled.

1

The Transfer Unit is enabled.
The configuration registers and control packets should be set up first before the HTUEN bit is set to 1 toprevent it from carrying out unintended bus transactions. If the HTUEN bit is cleared to 0 during a frame
is transferred, then the frame will be completed before the HTU is disabled.
The HTUEN bit must be cleared and the parity functionality must be enabled (by PARITY_ENA) during
the automatic DCP RAM initialization (see Initializing Parity Bits). If HTUEN is 1 when the initialization istriggered by the system module, then the initialization will not be performed and the HTU operation is
not affected. If a 1 is written to HTUEN during the initialization, then the HTUEN bit will be set but the
HTU will not be enabled before the initialization completes.
Note: If HTU is disabled during a frame transfer, then the ongoing current frame will becompleted before the HTU module is disabled. If enabled again, then the transfer will restartfrom the initial frame count for the CP programmed.

15-9

Reserved

8

DEBM

0

Reads return 0. Writes have no effect.
Debug Mode0

The Transfer Unit is stopped in debug mode.
The HTU will complete the current frame, but not start any new frames. It will also ignore all requests
from the HET and not generate any request lost signals.

1

The Transfer Unit continues operation in debug mode.
Note: Since the HET has also an "ignore suspend" bit, there a several possibilities for the behavior of
the HET and HTU in suspend mode.

7-1

Reserved

0

HTURES

0

Reads return 0. Writes have no effect.
HTU Software Reset Request.

0

Reset request is not issued to the HTU module. Writing a 0 has no effect.

1

Reset request is issued to the HTU module.
Ongoing element transfers will be completed, before resetting the complete HTU module, similar to a
hardware reset. The HTURES bit will also be cleared. The recommended order of operations is:••••

SPNU517C – March 2018
Submit Documentation Feedback

Set the software reset bit. This also clears HTUEN.
Wait for the HTURES bit to clear.
Configure the HTU registers and packets.
Set the HTUEN bit to begin operation.

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

721

Control Registers

www.ti.com

18.4.2 Control Packet Enable Register (HTU CPENA)
This register enables or disables the individual double control packets (DCP).
Figure 18-15. Control Packet Enable Register (HTU CPENA) [offset = 04h]
31

16
Reserved
R-0

15

0
CPENA
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 18-12. Control Packet Enable Register (HTU CPENA) Field Descriptions
Bit

Field

31-16

Reserved

Value

15-0

CPENA

0

Description
Reads return 0. Writes have no effect.
CP Enable Bits
Bits (2*x) and (2*x+1) of CPENA control the double control packet (DCP) x (whereby x must be within
0,1,....,7).
See Table 18-13 for write rules.
See Table 18-14 for read rules.

Table 18-13. CPENA Write Results
Bit (2*x+1)

Bit (2*x)

Control packets (CP) B and A of DCP x are affected as follows:00

CP B and A are not changed.

01

CP B is disabled and CP A are enabled simultaneously.

10

CP B is enabled and CP A are disabled simultaneously.

1

1

CP B and CP A are both disabled simultaneously.

Table 18-14. CPENA Read Results

•
•

•

722

Bit (2*x+1)

Bit (2*x)

State of DCP:

00

The DCP is disabled.

01

CP B is disabled and CP A is enabled.

10

CP B is enabled and CP A is disabled.

1

1

Cannot be read.

The conditions listed in Section 18.2.3 can automatically disable DCP x. In this case bits (2*x) and(2*x+1) are both automatically set to 0.
When bits (2*x) and (2*x+1) change from 00 to 01 or from 00 to 10 caused by a write access to
CPENA, then old pending requests on the corresponding request line are cleared. This means only
new requests which occur after this write access cause the first HTU transfer for this DCP. This is not
the case when switching CPs (from 10 to 01 or from 01 to 10).
CP A and/or CP B of a DCP can be configured to one-shot, circular or auto-switch transfer mode via
the TMBA or TMBB bits in the IHADDRCT control packet configuration. If a write access to CPENA
occurs during the last frame of a buffer (with frame counter = 1) then the action defined by the write
access to CPENA and the action defined by TMBx can contradict. The priority rules for this case are
given in Table 18-1.

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

18.4.3 Control Packet (CP) Busy Register 0 (HTU BUSY0)This register displays the status of individual control packets.
Figure 18-16. Control Packet (CP) Busy Register 0 (HTU BUSY0) [offset = 08h]
31

25

24

23

17

16

Reserved

BUSY0A

Reserved

BUSY0B

R-0

R/W1CP-0

R-0

R/W1CP-0

15

9

8

7

1

0

Reserved

BUSY1A

Reserved

BUSY1B

R-0

R/W1CP-0

R-0

R/W1CP-0

LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode only to clear the bit; -n = value after reset

Table 18-15. Control Packet (CP) Busy Register 0 (HTU BUSY0) Field Descriptions
Bit

Field

31-25

Reserved

24

BUSY0A

23-17

Reserved

16

BUSY0B

15-9

Reserved

8

BUSY1A

7-1

Reserved0

BUSY1B

Value
0

Description
Reads return 0. Writes have no effect.
Busy Flag for CP A of DCP 0.

0

Reads return 0. Writes have no effect.
Busy Flag for CP B of DCP 0.

0

Reads return 0. Writes have no effect.
Busy Flag for CP A of DCP 1.

0

Reads return 0. Writes have no effect.
Busy Flag for CP B of DCP 1.

The bit is set when the frame on the according control packet starts (there could be a delay between therequest and the start of the frame).
The bit is automatically cleared at any of the following conditions:
1. At the end of a frame.
2. Writing a 1 to a BUSY bit (of DCP x) if that bit is 1. This will:a. clear the element counter of DCP x,b. stop all new element transfers on DCP x
c. clear the busy bit and (4.) disable DCP x in the CPENA register.
d. there is no effect if the BUSY bit is 0.
3. At the conditions listed in Section 18.2.3.
A write access to the CPENA register can stop a control packet (CP) in single buffer mode or it can switch
to the other CP of a DCP in dual buffer mode. If stopping or switching occurs while a frame runs on thecurrently active control packet, the CPU can poll the busy bit to determine when it is safe to read thebuffer.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

723

Control Registers

www.ti.com

18.4.4 Control Packet (CP) Busy Register 1 (HTU BUSY1)
This register displays the status of individual control packets.
Figure 18-17. Control Packet (CP) Busy Register 1 (HTU BUSY1) [offset = 0Ch]
31

25

24

23

17

16

Reserved

BUSY2A

Reserved

BUSY2B

R-0

R/W1CP-0

R-0

R/W1CP-0

15

9

8

7

1

0

Reserved

BUSY3A

Reserved

BUSY3B

R-0

R/W1CP-0

R-0

R/W1CP-0

LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode only to clear the bit; -n = value after reset

Table 18-16. Control Packet (CP) Busy Register 1 (HTU BUSY1) Field Descriptions
Bit

Field

31-25

Reserved

Value

24

BUSY2A

23-17

Reserved

16

BUSY2B

15-9

Reserved

8

BUSY3A

7-1

Reserved

0

BUSY3B

0

Description
Reads return 0. Writes have no effect.
Busy Flag for CP A of DCP 2.

0

Reads return 0. Writes have no effect.
Busy Flag for CP B of DCP 2.

0

Reads return 0. Writes have no effect.
Busy Flag for CP A of DCP 3.

0

Reads return 0. Writes have no effect.
Busy Flag for CP B of DCP 3.

See Section 18.4.3 for more details.

18.4.5 Control Packet (CP) Busy Register 2 (HTU BUSY2)
Figure 18-18. Control Packet (CP) Busy Register 2 (HTU BUSY2) [offset = 10h]
31

25

24

23

17

16

Reserved

BUSY4A

Reserved

BUSY4B

R-0

R/W1CP-0

R-0

R/W1CP-0

15

9

8

7

1

0

Reserved

BUSY5A

Reserved

BUSY5B

R-0

R/W1CP-0

R-0

R/W1CP-0

LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode only to clear the bit; -n = value after reset

Table 18-17. Control Packet (CP) Busy Register 2 (HTU BUSY2) Field Descriptions
Bit

Field

31-25

Reserved

24

BUSY4A

23-17

Reserved

16

BUSY4B

15-9

Reserved

8

BUSY5A

7-1

Reserved

0

BUSY5B

724

Value
0

Description
Reads return 0. Writes have no effect.
Busy Flag for CP A of DCP 4.

0

Reads return 0. Writes have no effect.
Busy Flag for CP B of DCP 4.

0

Reads return 0. Writes have no effect.
Busy Flag for CP A of DCP 5.

0

Reads return 0. Writes have no effect.
Busy Flag for CP B of DCP 5.

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

18.4.6 Control Packet (CP) Busy Register 3 (HTU BUSY3)
Figure 18-19. Control Packet (CP) Busy Register 3 (HTU BUSY3) [offset = 14h]
31

25

24

23

17

16

Reserved

BUSY6A

Reserved

BUSY6B

R-0

R/W1CP-0

R-0

R/W1CP-0

15

9

8

7

1

0

Reserved

BUSY7A

Reserved

BUSY7B

R-0

R/W1CP-0

R-0

R/W1CP-0

LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode only to clear the bit; -n = value after reset

Table 18-18. Control Packet (CP) Busy Register 3 (HTU BUSY3) Field Descriptions
Bit

Field

Value

31-25

Reserved

24

BUSY6A

23-17

Reserved

16

BUSY6B

15-9

Reserved

8

BUSY7A

7-1

Reserved

0

BUSY7B

Description

0

Reads return 0. Writes have no effect.
Busy Flag for CP A of DCP 6.

0

Reads return 0. Writes have no effect.
Busy Flag for CP B of DCP 6.

0

Reads return 0. Writes have no effect.
Busy Flag for CP A of DCP 7.

0

Reads return 0. Writes have no effect.
Busy Flag for CP B of DCP 7.

18.4.7 Active Control Packet and Error Register (HTU ACPE)
Figure 18-20. Active Control Packet and Error Register (HTU ACPE) [offset = 18h]
31

30

29

28

24

23

20

19

16

ERRF

Reserved

ERRETC

Reserved

ERRCPN

R/W1CP-0

R-0

R-0

R-0

R-0

15

14

13

TIPF

BUSBUSY

Rsvd

12
CETCOUNT

8

7
Reserved

4

3
NACP

0

R-0

R-0

R-0

R-0

R-0

R-0

LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode only to clear the bit; -n = value after reset

Table 18-19. Active Control Packet and Error Register (HTU ACPE) Field Descriptions
Bit

Field

31

ERRF

30-29

Value

Reserved

SPNU517C – March 2018
Submit Documentation Feedback

Description
Error Flag

0

No error occurred.

1

This bit is set when one of the conditions listed at ERRETC is fulfilled and ERRETC and ERRCPN
are captured. Once ERRF is set, it is cleared when reading the upper 16-bit word of the ACPE
register or the complete 32-bit register. It is also cleared when writing a 1 to ERRF. ERRF can beused to indicate if ERRETC and ERRCPN contain new unread data.

0

Reads return 0. Writes have no effect.

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

725

Control Registers

www.ti.com

Table 18-19. Active Control Packet and Error Register (HTU ACPE) Field Descriptions (continued)
Bit

Field

28-24

ERRETC

Value

Description
Error Element Transfer CountIf one of the following conditions happens the current element transfer counter of the control packet(specified by ERRCPN) is captured to ERRETC. Please see Section 18.2.3.
• Request Lost Error of control packet specified by ERRCPN. This is independent of the CORL bit.
• Parity Error of control packet specified by ERRCPN. This requires the parity check to be enabled,
but is independent of the COPE bit.
• Bus Error of control packet specified by ERRCPN.
• Memory Protection Error of control packet specified by ERRCPN. This requires the memory
protection to be enabled.
• Writing a 1 to a BUSY bit, which belongs to the control packet specified by ERRCPN, if that bit is
1. There is no effect, if the BUSY bit is 0.
ERRETC is frozen from being updated until the upper 16-bit word of the ACPE register or thecomplete 32-bit register is read by the CPU. After this read, the HTU will update ERRETC if one of
the above conditions is fulfilled again. During debugging, ERRETC stays frozen even when reading
the upper 16-bit word or the 32-bit register.

23-20

Reserved

19-16

ERRCPN0

Reads return 0. Writes have no effect.
Error Control Packet Number
If one of the conditions listed at ERRETC happens the number of the control packet, which caused
the condition, is captured to ERRCPN.
Control Packet

ERRCPN Value

CP A of DCP x

2x

CP B of DCP x

2 x+1

With x = 0,1,...or 7
ERRCPN is frozen from being updated until the upper 16-bit word of the ACPE register or thecomplete 32-bit register is read by the CPU. After this read, the HTU will update ERRCPN if one of
the above conditions is fulfilled again. During debugging, ERRCPN stays frozen even when reading
the upper 16-bit word or the 32-bit register. If one of the conditions is fulfilled ERRETC and
ERRCPN are updated simultaneously.
15

14

TIPF

Transfer in Progress Flag
0

No transfers are in progress.

1

A transfer is currently active. This bit is the result of a logical OR function of all BUSYxx flags of the
4 BUSYx registers.

BUSBUSY

13

Reserved

12-8

CETCOUNTBus is Busy0

Bus between N2HET and HTU is not busy.

1

When BUSBUSY is 1, the bus is busy with a transfer. It is different from TIPF above because
BUSBUSY will go low after VBUSHOLD is set to 1 and no transfers are pending between the HTU
and the main memory. TIPF will remain 1, if a transfer is still pending and VBUSPHOLD is 1.

0

Reads return 0. Writes have no effect.
Current Element Transfer CountCETCOUNT shows the current element transfer counter for the frame that is currently processed. If
the HTU does not currently transfer any frame, CETCOUNT is 0.
CETCOUNT is updated after the write part of a transfer. There is a period of up to 7 cycles between
the time the CETCOUNT is 0 and the HTU is finished updating the current DCP (and the CPENA
registers if the required conditions are fulfilled).

7-4

Reserved

3-0

NACP

0

Reads return 0. Writes have no effect.
Number of Active Control Packet
Indicates which CP currently processes a frame.
Active or Recent DCP

NACP Value

CP A of DCP x

2x

CP B of DCP x

2 x+1

With x = 0,1,...or 7
NACP is updated at the time the frame starts on the according CP, and it is updated with a newvalue when a frame starts on a different CP. Note, that there can be a delay between the request
and the start of the frame.

726

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

18.4.8 Request Lost and Bus Error Control Register (HTU RLBECTRL)
Figure 18-21. Request Lost and Bus Error Control Register (HTU RLBECTRL) [offset = 20h]
31

17

15

9

16

Reserved

BERINTENA

R-0

R/WP-08

7

1

0Reserved

CORL

Reserved

RLINTENA

R-0

R/WP-0R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 18-20. Request Lost and Bus Error Control Register (HTU RLBECTRL) Field Descriptions
Bit

Field

31-17

Reserved

16

15-9
8

Value
0

BERINTENA

Reserved

Reserved

0

RLINTENA

Reads return 0. Writes have no effect.
Bus Error Interrupt Enable Bit.

0

The bus error interrupt is disabled for all DCPs.

1

The bus error interrupt is enabled for all DCPs.

0

Reads return 0. Writes have no effect.

CORL

7-1

Description

Continue On Request Lost Error.
0

Stop current frame on request lost detection. Please see Conditions for Frame Transfer Interruption.

1

If CORL is 1 and DCP x is enabled, then DCP x will stay enabled after a request lost condition on DCP
x and element transfers will continue.

0

Reads return 0. Writes have no effect.
Request Lost Interrupt Enable Bit.

0

The request lost interrupt is disabled for all DCPs. Disabling RLINTENA will not clear the flags in the
RLOSTFL register.

1

The request lost interrupt is enabled for all DCPs. If bits are set in the RLOSTFL flag register at the time
RLINTENA is (re-) enabled, then the according interrupt(s) will occur (in the order of the priority of therequest lines).

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

727

Control Registers

www.ti.com

18.4.9 Buffer Full Interrupt Enable Set Register (HTU BFINTS)
This registers allows to enable the buffer full interrupts for the different control packets. Reading registers
BFINTS and BFINTC will return the same bits indicating the status which interrupt is enabled (1) or
disabled (0).
Figure 18-22. Buffer Full Interrupt Enable Set Register (HTU BFINTS) [offset = 24h]31

16
Reserved
R-0

150
BFINTENA
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 18-21. Buffer Full Interrupt Enable Set Register (HTU BFINTS) Field Descriptions
Bit

Field

31-16

Reserved

Value

15-0

BFINTENA

0

Description
Reads return 0. Writes have no effect.
Bus Full Interrupt Enable Bits. If the interrupt for CP A of a DCP is enabled, then the interrupt isgenerated once buffer A is full, that is, once the frame counter CFTCTA decrements to 0. The same
applies for CP B (and CFTCTB).

0Interrupt is disabled. Writing a 0 has no effect.

1

Writing to bit (2*x) enables the interrupt for CP A of DCP x.
Writing to bit (2*x+1) enables the interrupt for CP B of DCP x.

18.4.10 Buffer Full Interrupt Enable Clear Register (HTU BFINTC)
This registers allows to disable the buffer full interrupts for the different control packets. Reading registers
BFINTS and BFINTC will return the same bits indicating the status which interrupt is enabled (1) or
disabled (0)Figure 18-23. Buffer Full Interrupt Enable Clear Register (HTU BFINTC) [offset = 28h]31

16Reserved
R-0

150
BFINTDIS
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 18-22. Buffer Full Interrupt Enable Clear Register (HTU BFINTC) Field Descriptions
Bit

Field

31-16

Reserved

15-0

BFINTDIS

Value
0

Description
Reads return 0. Writes have no effect.
Buffer Full Interrupt Disable Bits.

0Interrupt is disabled. Writing a 0 has no effect.

1

Writing to bit (2*x) disables the interrupt for CP A of DCP x.
Writing to bit (2*x+1) disables the interrupt for CP B of DCP x.

728

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

18.4.11 Interrupt Mapping Register (HTU INTMAP)
Figure 18-24. Interrupt Mapping Register (HTU INTMAP) [offset = 2Ch]
31

17

16

Reserved

MAPSEL

R-0

R/WP-015

0CPINTMAP
R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 18-23. Interrupt Mapping Register (HTU INTMAP) Field Descriptions
Bit

Field

31-17

Reserved

16

MAPSEL

15-0

Value
0

Description
Reads return 0. Writes have no effect.
Interrupt Mapping Select Bit.

0

If MAPSEL is 0, then one bit of CPINTMAP selects one of two interrupt priorities 0 or 1 for the buffer
full interrupt for the according CP. The request lost and bus error interrupts of all CPs are set topriority 0, independent of CPINTMAP.

1

If MAPSEL is 1, then one bit of CPINTMAP determines if the buffer full, request lost and bus error
interrupts of the according CP are assigned either to interrupt line 0 or to 1.

CPINTMAP

CP Interrupt Mapping Bits.
0Interrupt of CP A (bit 2-x) of DCP x is mapped to interrupt line 0.
Interrupt of CP B (bit 2*x+1) of DCP x is mapped to interrupt line 0.

1

Interrupt of CP A (bit 2-x) of DCP x is mapped to interrupt line 1.
Interrupt of CP B (bit 2*x+1) of DCP x is mapped to interrupt line 1.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

729

Control Registers

www.ti.com

18.4.12 Interrupt Offset Register 0 (HTU INTOFF0)The INTOFF0 register reflects the highest priority interrupt flag bit set in the BERINTFL, RLOSTFL, or
BFINTFL flag registers with the appropriate CPINTMAP bit set to 0. The priority order (from high to low) is:
BER, RLOST, buffer-full. Interrupts for request lines with lower number have higher priority.
Figure 18-25. Interrupt Offset Register 0 (HTU INTOFF0) [offset = 34h]
31

16
Reserved
R-0

15

10

9

8

7

4

3

0

Reserved

INTTYPE0

Reserved

CPOFF0

R-0

R-0

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 18-24. Interrupt Offset Register 0 (HTU INTOFF0) Field Descriptions
Bit

Field

31-10

Reserved

9-8

INTTYPE0

7-4

Reserved

3-0

CPOFF0Value
0Description
Reads return 0. Writes have no effect.
Interrupt Type of Interrupt Line 0. Indicates whether a buffer-full, RLOST or BER interrupt, assigned tointerrupt line 0, is currently pending.

0

No interrupt.

1hInterrupt is caused by full buffer on CP/DCP specified by CPOFF0.

2h

RLOST interrupt is generated by CP/DCP specified by CPOFF0.

3h

BER interrupt is generated by CP/DCP specified by bits CPOFF0.

0

Reads return 0. Writes have no effect.
CP Offset. Indicates for which control packet the interrupt is pending, which is classified by INTTYPE0
and is assigned to interrupt line 0.

0

DCP 0, CP A

1h

DCP 0, CP B2h

DCP 1, CP A

3h

DCP 1, CP B4h

DCP 2, CP A

5h

DCP 2, CP B6h

DCP 3, CP A

7h

DCP 3, CP B8h

DCP 4, CP A

9h

DCP 4, CP B

Ah

DCP 5, CP A

Bh

DCP 5, CP B

Ch

DCP 6, CP A

Dh

DCP 6, CP B

Eh

DCP 7, CP AFh

DCP 7, CP B

NOTE: Reading CPOFF0 will clear the bit generating the current interrupt from appropriate flagregister (BERINTFL, RLOSTFL, or BFINTFL), except when in debug mode where reading
CPOFF0 will have no effect on the flag registers.
In order to read INTTYPE0 and CPOFF0 simultaneously, always read this register using
word or half-word but not using byte accesses.

730

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

18.4.13 Interrupt Offset Register 1 (HTU INTOFF1)
This register is organized identically to the INTOFF0 register. The difference is that INTOFF1 reflects thehighest priority interrupt flag bit set in the BERINTFL, RLOSTFL, or BFINTFL flag registers with theappropriate CPINTMAP bit set to 1.
Figure 18-26. Interrupt Offset Register 1 (HTU INTOFF1) [offset = 38h]
31

16
Reserved
R-0

15

10

9

8

7

4

3

1

Reserved

INTTYPE1

Reserved

CPOFF1

R-0

R-0

R-0

R-0

0

LEGEND: R = Read only; -n = value after reset

Table 18-25. Interrupt Offset Register 1 (HTU INTOFF1) Field Descriptions
Bit

Field

31-10

Reserved

9-8

INTTYPE1

7-5

Reserved

4-0

CPOFF1

Value
0

Description
Reads return 0. Writes have no effect.
Interrupt Type of Interrupt Line 1. Indicates whether a buffer-full, RLOST or BER interrup, assigned tointerrupt line 1, is currently pending.

0

No interrupt.

1hInterrupt is caused by full buffer on CP/DCP specified by CPOFF1.

2h

RLOST interrupt is generated by CP/DCP specified by CPOFF1.

3h

BER interrupt is generated by CP/DCP specified by bits CPOFF1.

0

Reads return 0. Writes have no effect.
CP Offset. Indicates for which DCP/CP the interrupt is pending, which is classified by INTTYPE1 and isassigned to interrupt line 10

DCP 0, CP A

1h

DCP 0, CP B2h

DCP 1, CP A

3h

DCP 1, CP B4h

DCP 2, CP A

5h

DCP 2, CP B6h

DCP 3, CP A

7h

DCP 3, CP B8h

DCP 4, CP A

9h

DCP 4, CP B

Ah

DCP 5, CP A

Bh

DCP 5, CP B

Ch

DCP 6, CP A

Dh

DCP 6, CP B

Eh

DCP 7, CP AFh

DCP 7, CP B

NOTE: Reading CPOFF1 will clear the bit generating the current interrupt from appropriate flagregister (BERINTFL, RLOSTFL, or BFINTFL), except when in debug mode where reading
CPOFF1 will have no effect on the flag registers.
In order to read INTTYPE1 and CPOFF1 simultaneously, always read this register using
word or half-word but not using byte accesses.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

731

Control Registers

www.ti.com

18.4.14 Buffer Initialization Mode Register (HTU BIM)
This register enables special applications, where one CP is temporarily disabled, but after having reenabled the CP, filling the buffer should not start back at its beginning, but should continue after the lastelement of the previous run.
Table 18-27 shows more details on the BIM usage.
Figure 18-27. Buffer Initialization Mode Register (HTU BIM) [offset = 3Ch]
31

16
Reserved
R-0

15

8

7

0

Reserved

BIM

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 18-26. Buffer Initialization Mode Register (HTU BIM) Field Descriptions
Bit

Field

31-8

Reserved

7-0

BIM

Value
0

Description
Reads return 0. Writes have no effect.
Buffer Initialization Mode
The BIM bits and the TMBx bits determine when a buffer is initialized, that means when its initial full
address IFADDRx and its initial frame counter IFTCOUNT is used.
When initializing (restarting) a buffer the information in the corresponding initial DCP RAM is loaded to ainternal state machine but not to the current DCP RAM (CFADDRx, CFTCTx). The current DCP RAM is
updated the first time when the first frame has finished.
A buffer is initialized:• In circular buffer transfer mode (defined by TMBx) when the end of the buffer is reached.
• When CPs are switched or enabled according to Buffer Initialization. The CPENA bits (2*x+1) and(2*x) are changed by write access to CPENA. For the first two rows of the table the change of the
CPENA bits could also be the result of the auto switch feature (as defined by TMBx).
BIM bit x only affects DCP x (with x = 0,1,...or 7).

Table 18-27. Buffer Initialization

Case

(1)
(2)
(3)

732

Change of CPENA Bits
(2*x+1) and (2*x)
Old State (1)New State

A

01

10

B

10

C

Action on Buffer A or B (of DCP x)
BIM Bit x = 0(normal mode)

BIM Bit x = 1(special mode)

Switch from CP A to B

Next frame starts at theinitial address of buffer B (3)Same as for BIM bit x = 001

Switch from CP B to A

Next frame starts at theinitial address of buffer A (3)Same as for BIM bit x = 0

01

01

Stay at CP A

Write to CPENA bits
(2*x+1) and (2*x) is ignored

Same as for BIM bit x = 0

E

10

10

Stay at CP B

Write to CPENA bits
(2*x+1) and (2*x) is ignored

Same as for BIM bit x = 0

E

00

01

Enable CP A

Next frame starts at theinitial address of buffer A

Next frame continues at thecurrent address of buffer A

F

00

10

Enable CP B

Next frame starts at theinitial address of buffer B

Next frame continues at thecurrent address of buffer B

G

xx

11

Disable both CPs

Stop DCP x

Same as for BIM bit x = 0(2)

See read table of CPENA register (Table 18-14).
See write table of CPENA register (Table 18-13).
This is regardless of whether the switch is done by a write access to CPENA or by the auto switch feature.

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

NOTE: For cases E and F above, after the last frame of a buffer, the HTU sets CFTCTx to 0 and
CFADDRx to the next address after the buffer. If the DCP was disabled during this state,then both CFTCTx and CFADDRx would contain invalid initialization values. Therefore, if a
DCP should continue at its current address, then the software should use one of thefollowing two procedures before it (re-) enables the DCP (as per Table 18-27):
1. If CFTCTx ≠ 0 then set BIM=1

2.

If CFTCTx = 0 then set
BIM=0
If CFTCTx ≠ 0 then set
BIM=1
If CFTCTx = 0 then {setBIM=1;

set CFTCTx = IFTCOUNT;
set CFADDRx = IFADDRx}
But note that these procedures are only required for the cases E and F and not for all theother cases shown in Table 18-27. Also, when a buffer reaches its end in circular mode, it
uses the initial DCP information to restart independently of the BIM setting (assuming it is not
temporarily disabled during CFTCTx = 0).

NOTE: Similarly, care needs to be taken when BIM is set to 1 and a DCP is enabled for the very firsttime. Also, in this case, CFTCTx and CFADDRx usually contain invalid initialization values.
The software can either solve this by setting BIM = 0 for the first time or setting CFADDRx to
IFADDRx and CFTCTx to IFTCOUNT before the DCP is enabled.

NOTE: If••

the HTUEN bit is changed to 1 after the HTU was disabled HTUEN = 0
the CPENA bit pair is 01 or 10 (during this HTUEN change)

then the corresponding BIM bit will decide if the corresponding buffer continues at its initial or
current address. Cases E and F in Table 18-27 also apply for this situation. The software
should use the procedures explained in the first note before setting HTUEN.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

733

Control Registers

www.ti.com

18.4.15 Request Lost Flag Register (HTU RLOSTFL)
Figure 18-28. Request Lost Flag Register (HTU RLOSTFL) [offset = 40h]
31

16
Reserved
R-0

150
CPRLFL
R/W1CP-0

LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode to clear the bit; -n = value after reset

Table 18-28. Request Lost Flag Register (HTU RLOSTFL) Field Descriptions
Bit

Field

31-16

Reserved

15-0

CPRLFL

Value
0

Description
Reads return 0. Writes have no effect.
CP Request Lost Flags0

No request was lost. Writing a 0 has no effect.

1

If bit (2*x) is set, a request was lost on CP A of DCP x.
If bit (2*x+1) is set, a request was lost on CP B of DCP x. Reading from INTOFFx in case of a RLOST
interrupt clears the corresponding flag. The state of the flag bit can be polled even if RLINTENA iscleared.
• Reading CPRLFL will not clear the flags or• Reading from INTOFFx clears the corresponding flag.
• Writing a 1 clears the corresponding flag.

18.4.16 Buffer Full Interrupt Flag Register (HTU BFINTFL)
Figure 18-29. Buffer Full Interrupt Flag Register (HTU BFINTFL) [offset = 44h]
31

16
Reserved
R-0

150
BFINTFL
R/W1CP-0

LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode to clear the bit; -n = value after reset

Table 18-29. Buffer Full Interrupt Flag Register (HTU BFINTFL) Field Descriptions
Bit

Field

31-16

Reserved

15-0

BFINTFL

Value
0

Description
Reads return 0. Writes have no effect.
Buffer Full Interrupt Flags

0

No buffer full condition is detected. Writing a 0 has no effect.

1

If bit (2*x) is set, a buffer full condition on CP A of DCP x has been detected.
If bit (2*x+1) is set, a buffer full condition on CP B of DCP x has been detected.
The BFINTFL flag is set after the last frame finishes on the corresponding buffer regardless of whether
the buffer is configured to one shot, circular or auto-switch mode. If BFINTFL is set in circular mode,
then a circular overrun has occurred on the corresponding buffer. This can be used to indicate whether
the buffer section after the frozen full address contains valid data or not.
Reading from INTOFFx in case of a buffer-full interrupt clears the corresponding flag. The state of theflag bit can be polled even if the corresponding interrupt enable bit is cleared.
• Reading BFINTFL will not clear the flags or• Reading INTOFFx will clear the corresponding flags or• Writing a 1 clears the corresponding flag.

734

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

18.4.17 BER Interrupt Flag Register (HTU BERINTFL)
A bus error interrupt results due to an address error or a timeout condition on the main memory access. A
bus error will stop the frame transfer. Please see Section 18.2.3.
Figure 18-30. BER Interrupt Flag Register (HTU BERINTFL) [offset = 48h]
31

16
Reserved
R-0

150
BERINTFL
R/W1CP-0

LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode to clear the bit; -n = value after reset

Table 18-30. BER Interrupt Flag Register (HTU BERINTFL) Field Descriptions
Bit

Field

31-16

Reserved

15-0

BERINTFL

Value
0

Description
Reads return 0. Writes have no effect.
Bus Error Interrupt Flags

0

No bus error condition is detected. Writing a 0 has no effect.

1

If bit (2*x) is set, then a BER interrupt is pending on CP A of DCP x.
If bit (2*x+1) is set, then a BER interrupt is pending on CP B of DCP x.
The state of the flag bit can be polled even if BERINTENA is cleared.
• Reading BERINTFL will not clear the flags or• Reading from INTOFFx in case of a BER interrupt clears the corresponding flag or• Writing a 1 clears the corresponding flag.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

735

Control Registers

www.ti.com

18.4.18 Memory Protection 1 Start Address Register (HTU MP1S)
This register configures the start address of memory protection region 1.
Figure 18-31. Memory Protection 1 Start Address Register (HTU MP1S) [offset = 4Ch]
31

16
STARTADDRESS1
R/WP-015

2STARTADDRESS1
R/WP-01

0

0

0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 18-31. Memory Protection 1 Start Address Register (HTU MP1S) Field Descriptions
Bit

Field

Description

31-0

STARTADDRESS1

The start address defines at which main memory address the region begins. A memory protection error
will be triggered, if the HTU accesses an address smaller than STARTADDRESS1 and the MPCS bit
REG01ENA register is configured accordingly. The address is 32-bit aligned, so the 2 LSBs are notsignificant and will always read 0.

18.4.19 Memory Protection 1 End Address Register (HTU MP1E)
Figure 18-32. Memory Protection 1 End Address Register (HTU MP1E) [offset = 50h]
31

16
ENDADDRESS1
R/WP-015

2
ENDADDRESS1
R/WP-01

0

0

0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 18-32. Memory Protection 1 End Address Register (HTU MP1E) Field Descriptions
Bit

Field

Description

31-0

ENDADDRESS1

The end address defines at which address the region ends. A memory protection error will be
triggered, if the HTU accesses an address bigger than ENDADDRESS1 and the register bit
REG01ENA is configured accordingly. The address is 32-bit aligned, so the 2 LSBs are not significant
and will always read 0. The effective end address is rounded up to the nearest word end address, thatis, 0x200 = 0x203.

736

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

18.4.20 Debug Control Register (HTU DCTRL)
This register allows to create watch points on access to a certain location. It is intended to help debug theapplication execution during program development.
Figure 18-33. Debug Control Register (HTU DCTRL) [offset = 54h]
31

28

27

24

23

17

16

Reserved

CPNUM

Reserved

HTUDBGS

R-0

R-0

R-0

R/WS-015

1

0Reserved

DBREN

R-0

R/WS-0LEGEND: R/W = Read/Write; R = Read only; WS = Write in suspend mode only; -n = value after reset

Table 18-33. Debug Control Register (HTU DCTRL) Field Descriptions
Bit

Field

31-28

Reserved

27-24

CPNUM

23-17

Reserved

16

HTUDBGS

Value
0

Description
Reads return 0. Writes have no effect.
CP Number. These bit fields indicate the CP which should cause the watch point to match.

0

CP A of DCP01h

CP B of DCP02h

CP A of DCP13h

CP B of DCP14h

CP A of DCP25h

CP B of DCP26h

CP A of DCP37h

CP B of DCP38h

CP A of DCP49h

CP B of DCP4Ah

CP A of DCP5

Bh

CP B of DCP5ChCP A of DCP6Dh

CP B of DCP6Eh

CP A of DCP7FhCP B of DCP70

Reads return 0. Writes have no effect.
HTU Debug Status. When the main memory address is equal to the unique address defined by WPR, orlies in the specified range resulting from WMR, then the HTUDBGS is set. If in addition DBREN is set,
then the application code execution will be stopped.
A 1 must be written to this bit in order to clear it and to release the CPU from debug halting state.

0

Read: No watch point condition was detected.
Write: No effect.

1

Read: A watch point condition was detected.
Write: Clears the bit.

15-1

Reserved

0

DBREN

0

Reads return 0. Writes have no effect.
Debug Request Enable
If a watch point matches and DBREN is set, then the application code execution will be stopped. Thisbit can only be set or cleared when in debug mode. This bit and all other bits of the DCTRL, WPR andWMR registers are reset by the test reset (nTRST) but not by the normal device reset.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

737

Control Registers

www.ti.com

18.4.21 Watch Point Register (HTU WPR)
This register defines the main memory address of the watch point.
Figure 18-34. Watch Point Register (HTU WPR) [offset = 58h]
31

16
WP
R/WS-015

0WP
R/WS-0LEGEND: R/W = Read/Write; WS = Write in suspend mode only; -n = value after reset

Table 18-34. Watch Point Register (HTU WPR) Field Descriptions
Bit

Field

Description

31-0

WP

Watch Point Register
A 32-bit address can be programmed into this register as a watch point. The WPR register is used along with
the Watch Mask Register ( WMR). When the main memory address is equal to the unique address defined by
WPR, or lies in the specified range resulting from WMR, then the HTUDBGS is set. If in addition DBREN is set,
then the application code execution is stopped.
This register can only be programmed during debug mode. This register and all other bits of the DCTRL andWMR registers are reset by the test reset (nTRST) but not by the normal device reset.

18.4.22 Watch Mask Register (HTU WMR)This register defines a mask of the main memory address of the watch point. It can be used to define amemory range in conjunction with the WPR register.
Figure 18-35. Watch Mask Register (HTU WMR) [offset = 5Ch]
31

16
WM
R/WS-015

0WM
R/WS-0LEGEND: R/W = Read/Write; WS = Write in suspend mode only; -n = value after reset

Table 18-35. Watch Mask Register (HTU WMR) Field Descriptions
Bit

Field

Description

31-0

WM

Watch Mask Register
Setting a bit in the WMR register to 1 has the effect of masking the corresponding bit in of the main memory
address, so that this bit is ignored for the address comparison.
This register can only be programmed during debug mode. This register and all other bits of the DCTRL and
WPR registers are reset by the test reset (nTRST) but not by the normal device reset.

738

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

18.4.23 Module Identification Register (HTU ID)
This register is for TI internal purposes and allows to keep track of the HTU module version on different
devices.
Figure 18-36. Module Identification Register (HTU ID) [offset = 60h]
31

24

23

16

Reserved

CLASS

R-0

R - Module Class Number

15

8

7

0

TYPE

REV

R - Class Subtype Number

R - Module Revision Number

LEGEND: R = Read only; -n = value after reset

Table 18-36. Module Identification Register (HTU ID) Field Descriptions
Bit

Field

31-24

Reserved

23-16

CLASS

Value
0

Description
Reads return 0. Writes have no effect.
Module ClassThis field defines the module class number as read-only constant value for the HTU module. Writes
have no effect.

15-8

TYPE

Subtype within a ClassThis field defines the subtype within a class as read-only constant value for the HTU module. Writes
have no effect.

7-0

REV

Module Revision NumberThis field defines the module revision number as read-only constant value for the HTU module. Writes
have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

739

Control Registers

www.ti.com

18.4.24 Parity Control Register (HTU PCR)
Figure 18-37. Parity Control Register (HTU PCR) [offset = 64h]
31

17

15

9

16

Reserved

COPE

R-0

R/WP-0

8

7

4

3

0

Reserved

TEST

Reserved

PARITY_ENA

R-0

R/WP-0R-0

R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 18-37. Parity Control Register (HTU PCR) Field Descriptions
Bit

Field

31-17

Reserved

16

Value
0

COPE

Description
Reads return 0. Writes have no effect.
Continue on Parity Error

0

The HTU performs parity checks every time it reads the RAM section of DCP x (with x = 0, 1,...
or 7), before the next frame (of DCP x) is started. If a parity error is detected during this readaccess and if the parity check is enabled, then the frame will not be started and DCP x will be
automatically disabled in the CPENA register.
If a master different than the HTU (for example, CPU) reads the RAM section of DCP x and aparity error is detected during this read access, while the parity check is enabled, then the DCP
x will automatically be disabled in the CPENA register. If a frame is active on DCP x during thisread access, then in addition the element counter of DCP x is cleared and all new elementtransfers on DCP x are stopped and the active busy bit of DCP x is cleared.

15-9
8

Reserved

1

The difference to COPE = 0 is, that the data transfer on a active DCP continues after a parity
error was detected on this DCP. So neither the DCP with the parity error will be disabled nor
the frame will be stopped.

0

Reads return 0. Writes have no effect.

TEST

7-4

Reserved

3-0

PARITY_ENA

Test. When this bit is set, the parity bits are mapped into the peripheral RAM frame to makethem accessible by the CPU.
0

Parity bits are not memory-mapped.

1

Parity bits are memory-mapped.

0

Reads return 0. Writes have no effect.
Enable/Disable Parity Checking. This bit field enables or disables the parity check on read
operations and the parity calculation on write operations. If parity checking is enabled and aparity error is detected, then the PEFT flag is set, PAOFF is captured if it is not currently frozen
and an interrupt is generated if it is enabled.

5h

Parity check is disabled.

All Others

Parity check is enabled.
Note: It is recommended to write Ah to enable error detection, to guard against single bitchanges from flipping PARITY_ENA to a disable state.

740

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

18.4.25 Parity Address Register (HTU PAR)
Figure 18-38. Parity Address Register (HTU PAR) [offset = 68h]
31

17

15

16

Reserved

PEFT

R-0

R/W1CP-0

9

80

Reserved

PAOFF

R-0

R-X

LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 in privilege mode to clear the bit; X = value is undefined; -n = value after
reset

Table 18-38. Parity Address Register (HTU PAR) Field Descriptions
Bit

Field

31-10

Reserved

16

Value
0

PEFT

Description
Reads return 0. Writes have no effect.
Parity Error Fault Flag. This bit is set, when the HTU detects a parity error and parity checking isenabled.

0

No fault is detected.

1

Fault is detected.
Note: Once PEFT is set, a read access to the lower 16 bits or to the complete 32-bit HTUPAR register
will clear the PEFT flag in non-debug mode. Another possibility to clear PEFT is to write a 1 to the
PEFT bit.

15-9

Reserved

8-0

PAOFF

0

Reads return 0. Writes have no effect.
Parity Error Address Offset. This bit field holds the address of the first parity error, which is detected in
the DCP RAM. PAOFF provides the offset address of the erroneous byte counted from the beginning of
the DCP memory. This error address is frozen from being updated until a read access to the lower 16
bits or to the complete 32-bit HTUPAR register happens. During debug mode, this address is frozen
even when read.
Note: The Parity Error Address bits will not be reset, neither by PORRST nor by any other reset source.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

741

Control Registers

www.ti.com

18.4.26 Memory Protection Control and Status Register (HTU MPCS)
Figure 18-39. Memory Protection Control and Status Register (HTU MPCS) [offset = 70h]
31

28

27

24

Reserved

CPNUM0

R-0

R-0

23

18

MPEFT1MPEFT0

R-0

R/W1CP-0

R/W1CP-0

12

11

8

Reserved

CPNUM1

R-0

R-0

6

16

Reserved

15

7

17

5

4

3

2

1

0

Reserved

INT ENA01

ACCR01

REG01ENAINT ENA0

ACCR0

REG0ENA

R-0

R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; W1CP = Write 1 in privilege mode to clear the bit; -n =value after reset

Table 18-39. Memory Protection Control and Status Register (HTU MPCS) Field Descriptions
Bit

Field

31-28

Reserved

27-24

CPNUM023-18

Reserved

17

MPEFT1

16

742

Value
0

Description
Reads return 0. Writes have no effect.
Control Packet Number for single memory protection region configuration. CPNUM0 holds the numberof the CP, which has caused the first memory protection error when only one memory protection regionis used. This number is not updated for multiple access violations until it is read by the CPU. During
debug mode, CPNUM0 is frozen even when read.

0

CP A of DCP01h

CP B of DCP02h

CP A of DCP13h

CP B of DCP14h

CP A of DCP25h

CP B of DCP26h

CP A of DCP37h

CP B of DCP38h

CP A of DCP49h

CP B of DCP4Ah

CP A of DCP5

Bh

CP B of DCP5ChCP A of DCP6Dh

CP B of DCP6Eh

CP A of DCP7FhCP B of DCP70

Reads return 0. Writes have no effect.
Memory Protection Error Fault Flag 1. This bit is set, when the HTU performs an access outside theregion defined by the MP0S and MP0E and the MP1S and MP1E registers, when the access violates
the rights defined by ACCR01 and when the REG01ENA bit is set.

0

No fault is detected. Writing a 0 has no effect.

1

Fault is detected. Writing a 1 clears the bit.

MPEFT0

Memory Protection Error Fault Flag 0. This bit is set, when the HTU performs an access outside theregion defined by the MP0S and MP0E registers, when the access violates the rights defined by ACCR
and when the REG0ENA bit is set.
0

No fault is detected. Writing a 0 has no effect.

1

Fault is detected. Writing a 1 clears the bit.

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

Table 18-39. Memory Protection Control and Status Register (HTU MPCS) Field Descriptions (continued)
Bit

Field

15-12

Reserved

11-8

CPNUM1

7-6

Reserved

5

INTENA01

4

3

2

1

Value
0

Description
Reads return 0. Writes have no effect.
Control Packet Number for single memory protection region configuration. CPNUM1 holds the numberof the CP, which has caused the first memory protection error when only one memory protection regionis used. This number is not updated for multiple access violations until it is read by the CPU. During
debug mode, CPNUM1 is frozen even when read.

0

CP A of DCP01h

CP B of DCP02h

CP A of DCP13h

CP B of DCP14h

CP A of DCP25h

CP B of DCP26h

CP A of DCP37h

CP B of DCP38h

CP A of DCP49h

CP B of DCP4Ah

CP A of DCP5

Bh

CP B of DCP5ChCP A of DCP6Dh

CP B of DCP6Eh

CP A of DCP7FhCP B of DCP70

Reads return 0. Writes have no effect.
Interrupt Enable 01. This bit needs to be set when working with two memory mapped regions and aerror should be generated to the ESM module on an access violation.

0

Error signaling is disabled.

1

Error signaling is enabled.

ACCR01

Access Rights 01. This bit defines the access rights for the HTU for accesses outside the region definedby the MP0S and MP0E and the MP1S and MP1E registers.
0

HTU read access is allowed but write access will be signaled.

1

Any access performed by the HTU is forbidden and will be signaled.

REG01ENA

Region Enable 01. This bit needs to be set when working with two memory-mapped regions. REG0ENA
must be set to 0 if this bit is set to a 1. Memory region 0 must be less than memory region 1.
0

The protection outside the memory region defined by the MP0S and MP0E and the MP1S and MP1E
registers is not enabled. This means the HTU can access any implemented memory space. REG0ENA
could still enabled to give protection outside the MP0S : MP0E region.

1

The protection outside the memory region defined by the MP0S and MP0E and the MP1S and MP0E
registers is enabled. This means the HTU can perform any access within the regions, but if it attempts
to perform a forbidden access outside of both of the regions (according to the ACCR01 configuration),
the access is signaled by the MPEFT1 flag. The number of the CP, which has caused the memory
protection error, is captured to CPNUM1 if it is not currently frozen and an error is generated if it isenabled.

INTENA0

Interrupt Enable 0. This bit needs to be set when working with one memory-mapped region and a error
should be generated to the ESM module on an access violation.
0

Error signaling is disabled.

1

Error signaling is enabled.

ACCR

Access Rights 0. This bit defines the access rights for the HTU for accesses outside the region definedby the MP0S and MP0E registers for a single memory protection region configuration.
0

HTU read access is allowed but write access will be signaled.

1

Any access performed by the HTU is forbidden and will be signaled.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

743

Control Registers

www.ti.com

Table 18-39. Memory Protection Control and Status Register (HTU MPCS) Field Descriptions (continued)
Bit

Field

0

REG0ENA

744

Value

Description
Region Enable 00

The protection outside the memory region defined by the MP0S and MP0E registers is not enabled.
This means the HTU can access any implemented memory space.

1

The protection outside the memory region defined by the MP0S and MP0E registers is enabled. Thismeans the HTU can perform any access within the region, but if it attempts to perform a forbidden
access outside the region (according to the ACCR configuration), the access is signaled by the
MPEFT0 flag, the number of the CP, which has caused the memory protection error, is captured to
CPNUM0 if it is not currently frozen and an error is generated if it is enabled.

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

18.4.27 Memory Protection Start Address Register 0 (HTU MP0S)
This register configures the start address of memory protection region 0
Figure 18-40. Memory Protection Start Address Register 0 (HTU MP0S) [offset = 74h]31

16STARTADDRESS0
R/WP-015

2STARTADDRESS0
R/WP-01

0

0

0

R/WP-0LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Table 18-40. Memory Protection 0 Start Address Register (HTU MP0S) Field Descriptions
Bit

Field

Description

31-0

ISTARTADDRESS0

The start address defines at which main memory address the region begins. A memory protection error
will be triggered, if the HTU accesses an address smaller than STARTADDRESS0 and the MPCS
register is configured accordingly. The address is 32-bit aligned, so the 2 LSBs are not significant andwill always read 0.

18.4.28 Memory Protection End Address Register (HTU MP0E)
Figure 18-41. Memory Protection End Address Register (HTU MP0E) [offset = 78h]
31

16
ENDADDRESS0
R/WP-015

2
ENDADDRESS0
R/WP-01

0

0

0

R/WP-0LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Table 18-41. Memory Protection End Address Register (HTU MP0E) Field Descriptions
Bit

Field

Description

31-0

ENDADDRESS0

The end address defines at which address the region ends. A memory protection error will be
triggered, if the HTU accesses an address bigger than ENDADDRESS0 and the register bit MPCS
register is configured accordingly. The address is 32-bit aligned, so the 2 LSBs are not significant andwill always read 0. The effective end address is rounded up to the nearest word end address, that is,
0x200 = 0x203.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

745

Double Control Packet Configuration Memory

www.ti.com

18.5 Double Control Packet Configuration Memory
All bits marked "reserved' are implemented in RAM and will be initialized to unknown values after power
on. Reserved locations can be written and read, but should be written with 0 to ensure future compatibility.
The HTU RAM can be cleared with the system RAM initialization function.
Table 18-42 provides a summary of the memory configuration. The base address for DCPs is
FF4E 0000h.
Table 18-42. Double Control Packet Memory Map

746

OffsetAcronym

Register Description

00h

HTU IFADDRA

Initial Full Address A Register

Section 18.5.1

Section04h

HTU IFADDRB

Initial Full Address B Register

Section 18.5.2

08h

HTU IHADDRCT

Initial N2HET Address and Control Register

Section 18.5.3

0Ch

HTU ITCOUNT

Initial Transfer Count Register

Section 18.5.4

100h

HTU CFADDRACurrent Full Address A Register

Section 18.5.5

104h

HTU CFADDRBCurrent Full Address B Register

Section 18.5.6

108h

HTU CFCOUNT

Current Frame Count Register

Section 18.5.7

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Double Control Packet Configuration Memory

www.ti.com

18.5.1 Initial Full Address A Register (HTU IFADDRA)
Figure 18-42. Initial Full Address A Register (HTU IFADDRA) [offset = 00h]
31

16
IFADDRAR/WP-X

15

0
IFADDRAR/WP-XLEGEND: R/W = Read/Write; WP = Write in privilege mode only; X = value is unknown; -n = value after reset

Table 18-43. Initial Full Address A Register (HTU IFADDRA) Field Descriptions
Bit

Field

Description

31-0

IFADDRA

Initial Address of Buffer A in main memory.
Initial (byte) address of buffer A placed in the main memory address range. Bits 0 and 1 are ignored by the
logic, due to 32-bit alignment.

18.5.2 Initial Full Address B Register (HTU IFADDRB)
Figure 18-43. Initial Full Address B Register (HTU IFADDRB) [offset = 04h]
31

16
IFADDRB
R/WP-X

15

0
IFADDRB
R/WP-XLEGEND: R/W = Read/Write; WP = Write in privilege mode only; X = value is unknown; -n = value after reset

Table 18-44. Initial Full Address B Register (HTU IFADDRB) Field Descriptions
Bit

Field

Description

31-0

IFADDRB

Initial Address of Buffer B in main memory.
Initial (byte) address of buffer B placed in the main memory address range. Bits 0 and 1 are ignored by the
logic, due to 32-bit alignment.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

747

Double Control Packet Configuration Memory

www.ti.com

18.5.3 Initial N2HET Address and Control Register (HTU IHADDRCT)
Figure 18-44. Initial NHET Address and Control Register (HTU IHADDRCT) [offset = 08h]
31

24
Reserved
R-0

23

22

21

DIR

SIZE

ADDMH

ADDMF

TMBA

TMBB

R/WP-X

R/WP-X

R/WP-X

R/WP-X

R/WP-X

R/WP-X

15

13

20

19

18

12

17

16

2

1

0

Reserved

IHADDR

Reserved

R-0

R/WP-X

R-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; X = value is unknown; -n = value after reset

Table 18-45. Initial N2HET Address and Control Register (HTU IHADDRCT) Field Descriptions
Bit

Field

31-24

Reserved

23

22

Value
0

DIR

Description
Reads return 0. Writes have no effect.
Direction of Transfer

0

N2HET address is read and main memory address is written.

1

Main memory address is read and N2HET address is written.

SIZE

Size of Transferred Data
032-bit transfer

164-bit transfer64-bit transfer examples: If the N2HET address points to the N2HET instruction Control Field (CF), thenthe CF and Data Field (DF) will be transferred. If the N2HET address points to the Program Field (PF),then the PF and CF will be transferred.

21

ADDMH

Addressing Mode N2HET Address. This bit determines the N2HET address index from one to the next
element of a frame.
0

Increment by 16 bytes.
Examples:If the initial N2HET address points to data field of instruction (n). Then the N2HET fields to betransferred by the elements of a frame are: data field of instruction (n), data field of instruction (n+1),
data field of instruction (n+2) and so on. If the initial N2HET address points to control field of instruction(n), then the N2HET fields to be transferred by the elements of a frame are: control field of instruction(n), control field of instruction (n+1), control field of instruction (n+2), and so on.

1

Increment by 8 bytes.
This mode is intended to be used together with the 64-bit transfer size to load short N2HET instruction
blocks into the N2HET RAM. So the sequence of transferred 64-bit elements could be: [PF and CF of
instruction (n)], [DF and RF of instruction (n)], [PF and CF of instruction (n+1)], [DF and RF of
instruction (n+1)], and so on.

20

ADDFM

Addressing Mode Main Memory Address0

Post-increment
Note: When post-increment is selected the HTU will automatically increment by 4 bytes for a 32-bit data
size and by 8 bytes for a 64-bit data size.

1
19-18

17-16

748

TMBA

Constant
Transfer Mode for Buffer A

0

One-Shot buffer mode

1h

Circular buffer mode2h-3hAuto-Switch mode

TMBB

Transfer Mode for Buffer B
0

One-Shot buffer mode

1h

Circular buffer mode2h-3hAuto-Switch mode

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Double Control Packet Configuration Memory

www.ti.com

Table 18-45. Initial N2HET Address and Control Register (HTU IHADDRCT) Field Descriptions (continued)
Bit

Field

15-13

Reserved

12-2

IHADDR

Value
0

Description
Reads return 0. Writes have no effect.
Initial N2HET Address
The initial N2HET Address points to the N2HET field, which is the first element of the frame.The N2HET
address (Bits 12:2) increments by 1 for each 32-bit N2HET field and starts with 0 at the first 32-bit fieldin the N2HET RAM.
Note: When the HTU addresses the N2HET RAM it uses only the number of address bits required forthe actual N2HET RAM size. If the N2HET address exceeds the actual N2HET RAM size, the unused
MSB bits of the address will be ignored and the address rolls over to the start of the N2HET RAM.

1-0

Reserved

0

Reads return 0. Writes have no effect.

18.5.4 Initial Transfer Count Register (HTU ITCOUNT)
Figure 18-45. Initial Transfer Count Register (HTU ITCOUNT) [offset = 0Ch]
31

21

20

16

Reserved

IETCOUNT

R-0

R/WP-X

15

8

7

0

Reserved

IFTCOUNT

R-0

R/WP-XLEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; X = value is unknown; -n = value after reset

Table 18-46. Initial Transfer Count Register (HTU ITCOUNT) Field Descriptions
Bit

Field

31-21

Reserved

20-16

IETCOUNT

15-8

Reserved

7-0

IFTCOUNT

Value
0

Description
Reads return 0. Writes have no effect.
Initial Element Transfer Count
Defines the number of element transfers.

0

Reads return 0. Writes have no effect.
Initial Frame Transfer Count
Defines the number of frame transfers.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

749

Double Control Packet Configuration Memory

www.ti.com

18.5.5 Current Full Address A Register (HTU CFADDRA)
Figure 18-46. Current Full Address A Register (HTU CFADDRA) [offset = 100h]
31

16
CFADDRAR/WP-X

15

0
CFADDRAR/WP-XLEGEND: R/W = Read/Write; WP = Write in privilege mode only; X = value is unknown; -n = value after reset

Table 18-47. Current Full Address A Register (HTU CFADDRA) Field Descriptions
Bit

Field

Description

31-0

CFADDRA

Current (byte) Address of Buffer A
The current main memory address register is updated at the end of each frame. Therefore it points to the start
address of the frame, which is the next to transfer, if currently no frame is transferred on this DCP. For an
ongoing frame transfer, it points to the start address of this frame. After the last element of a buffer wastransferred it will point to the buffer end address plus 0x4.
The main purpose of the current full address registers for buffer A and buffer B (see next section) is to enable
the software to find out the recently transferred element in the frozen buffer while the address of the active
buffer increments.
Note: A frame can be automatically stopped if any of the events listed in Conditions for Frame Transfer
Interruption happens. If a frame is stopped before it could complete, then the current full address register is not
updated and it will point to the start of the bad frame after the DCP was automatically disabled.

To transfer the first frame of buffer x, the information in the corresponding initial DCP RAM (IFADDRx,
IHADDRCT, ITCOUNT) is loaded to an internal state machine but not to the current DCP RAM(CFADDRx, CFTCTx).
This is valid for all of the following modes:• Buffer x has reached it's end in circular mode and rolls back to its start address.
• CP x is enabled by a CPENA access (and corresponding BIM bit is 0).
• A CPENA access or auto-switch mode causes a switch from CP y to CP x
This means after starting the transfer to/from buffer x, CFADDRx and CFTCTx is not updated before theend of the first frame. So before the software switches from CP y to CP x using a write access to the
CPENA register, it needs to initialize CFADDRx, CFTCTx. This allows the software to find out if the next
request on CP x after the switching to CP x was delayed or never occurring.

750

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Double Control Packet Configuration Memory

www.ti.com

18.5.6 Current Full Address B Register (HTU CFADDRB)
Figure 18-47. Current Full Address B Register (HTU CFADDRB) [offset = 104h]
31

16
CFADDRB
R/WP-X

15

0
CFADDRB
R/WP-XLEGEND: R/W = Read/Write; WP = Write in privilege mode only; X = value is unknown; -n = value after reset

Table 18-48. Current Full Address B Register (HTU CFADDRB) Field Descriptions
Bit

Field

Description

31-0

CFADDRB

Current (byte) Address of Buffer B
The current main memory address register is updated at the end of each frame. Therefore it points to the start
address of the frame, which is the next to transfer, if currently no frame is transferred on this DCP. If currently aframe is transferred, then it points to the start address of this frame. After the last element of a buffer wastransferred it will point to the buffer end address plus 0x4.
The main purpose of the current full address registers for buffer A and buffer B (see next section) is to enable
the software to find out the recently transferred element in the frozen buffer while the address of the active
buffer increments.
Note: A frame can be automatically stopped if any of the events listed in Conditions for Frame Transfer
Interruption happens. If a frame is stopped before it could complete, then the current full address register is not
updated and it will point to the start of the bad frame after the DCP was automatically disabled.

To transfer the first frame of buffer x, the information in the corresponding initial DCP RAM (IFADDRx,
IHADDRCT, ITCOUNT) is loaded to an internal state machine but not to the current DCP RAM(CFADDRx, CFTCTx).
This is valid for all of the following modes:• Buffer x has reached it's end in circular mode and rolls back to its start address.
• CP x is enabled by a CPENA access (and corresponding BIM bit is 0).
• A CPENA access or auto-switch mode causes a switch from CP y to CP x
This means after starting the transfer to/from buffer x, CFADDRx and CFTCTx is not updated before theend of the first frame. So before the software switches from CP y to CP x using a write access to the
CPENA register, it needs to initialize CFADDRx, CFTCTx. This allows the software to find out if the next
request on CP x after the switching to CP x was delayed or never occurring.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

751

Double Control Packet Configuration Memory

www.ti.com

18.5.7 Current Frame Count Register (HTU CFCOUNT)The current frame count register enables the software to find out the recent frame in the buffer while thecounter of the active buffer decrements.
Figure 18-48. Current Frame Count Register (HTU CFCOUNT) [offset = 108h]
31

24

23

16

Reserved

CFTCTA

R-0

R/WP-X

15

8

7

0

Reserved

CFTCTB

R-0

R/WP-XLEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; X = value is unknown; -n = value after reset

Table 18-49. Current Frame Count Register (HTU CFCOUNT) Field Descriptions
Bit

Field

31-24

Reserved

23-16

CFTCTA

15-8

Reserved

7-0

CFTCTB

752

Value
0

Description
Reads return 0. Writes have no effect.
Current Frame Transfer Count for CP A. It is updated at the end of each frame.

0

Reads return 0. Writes have no effect.
Current Frame Transfer Count for CP B. It is updated at the end of each frame.

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Examples

www.ti.com

18.6 Examples
18.6.1 Application Examples for Setting the Transfer Modes of CP A and B of a DCP
Table 18-50. Application Examples for Setting the Transfer Modes of CP A and B of a DCP
CP A

CP B

One shotNot used

Buffer A can be used as a one-shot buffer. A buffer full interrupt enabled for CP A cansignal reaching the end of the buffer.

Auto switch

One shotCan double the buffer size for a one-shot buffer. A buffer full interrupt enabled for CP
B can signal reaching the end of the buffer.

Circular

Circular

The CPU can switch the buffers at arbitrary times. It will fill or read the frozen buffer
during the other buffer is filled or read by the HTU. Interrupts are not required for thiscase.

Auto switch

Buffer full interrupts (enabled for CP A and B) signal when the end of a buffer isreached. After one buffer is completed the according CPU interrupt routine will read orrefill this buffer. At the same time the other buffer is read or filled by the HTU. Here thetime when the buffer must be read is determined by the time of the interrupt(determined by the frequency of the N2HET transfer requests).

Auto switch

18.6.2 Software Example Sequence Assuming Circular Mode for Both CP A and B
The example assumes the N2HET address to be read and the main memory address to be written.
I1
I2
I3
I4

CPU initializes initial DCP: IFADDRA, IFADDRB, IHADDRCT, ITCOUNT
CPU clears current DCP: CFADDRA, CFADDRB, CFTCTA, CFTCTB
CPU clears BFINTFL flag of CP A and B
Enable CP A with the CPENA register. Now the HTU fills buffer A

After some time the CPU intends to read buffer A:

A1
A2
A3
A4
A5
A6
A7
A8

CPU enables CP B and disables CP A by writing to the CPENA register. After thisswitch, the HTU fills buffer B. Filling buffer B starts with its initial full address and initialframe counter.
CPU waits for CP A busy bit equals 0
Optional: CPU verifies that the CP A request lost flag is not set. The bus error flag of CP
A could also be checked.
CPU reads the frozen CFTCTA, which indicates the fill level in the buffer
CPU sets current CP A (CFTCTA and/or CFADDRA) to 0. This allows to find out if any
request has happened during the next time buffer A is active.
CPU reads BFINTFL flag of buffer A
CPU clears the BFINTFL flag of buffer A. This is an initialization for the next time buffer
A is used.
CPU reads valid values of frozen buffer A. After reading the CPU does not need to clear
the frozen buffer A.

SPNU517C – March 2018
Submit Documentation Feedback

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

753

Examples

www.ti.com

After some time the CPU intends to read buffer B:

B1
B2
B3
B4
B5
B6
B7
B8

CPU enables CP A and disables CP B by writing to the CPENA register. After thisswitch, the HTU fills buffer A. Filling buffer A starts with its initial full address and initialframe counter.
CPU waits for CP B busy bit equals 0
Optional: CPU verifies that the CP B request lost flag is not set. The bus error flag of CP
B could also be checked.
CPU reads the frozen CFTCTB, which indicates the fill level in the buffer
CPU sets current CP B (CFTCTB and/or CFADDRB) to 0. This allows to find out if any
request has happened during the next time buffer B is active.
CPU reads BFINTFL flag of buffer B
CPU clears the BFINTFL flag of buffer B. This is an initialization for the next time buffer
B is used.
CPU reads valid values of frozen buffer B. After reading the CPU does not need to clear
the frozen buffer B.

After some time the CPU intends to read buffer A:
A1) ... see above...
NOTE: The buffer full interrupt doesn't need to be enabled. The BFINTFL flag is used to indicate acircular overrun of the buffer. If the BFINTFL flag is set, also the buffer section after thefrozen full address could be read.

Steps A3 and B3 in the example sequence above imply that request lost interrupts are disabled. The
example below assumes that request lost interrupts are enabled.
Request lost detection with interrupt enabled.

18.6.3 Example of an Interrupt Dispatch Flow for a Request Lost Interrupt
•
•
•
•

•

754

A request lost occurs and the interrupt routine starts.
Reading INTOFFx.INTYPEx shows that RLOSTFL is the interrupt source.
Reading INTOFFx.CPOFFx = Ah shows that DCP 5 / CP A has caused the RLOSTFL interrupt. The
hardware automatically clears bit (2·5+0) in RLOSTFL.
Reading RLOSTFL= 84h shows that also another request lost event happened on DCP 1 / CP A [bit(2·1+0)] and on DCP 3 / CP B [bit (2·3+1)] at the same time or after the request lost occurred on DCP
5 / CP A.
Writing back 84h to RLOSTFL clears bits 2 and 7 and the according pending interrupts.

High-End Timer Transfer Unit (HTU) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Chapter 19
SPNU517C – March 2018

General-Purpose Input/Output (GIO) ModuleThis chapter describes the general-purpose input/output (GIO) module. The GIO module provides thefamily of devices with input/output (I/O) capability. The I/O pins are bidirectional and bit-programmable.
The GIO module also supports external interrupt capability.
Topic

19.1
19.2
19.3
19.4
19.5
19.6

...........................................................................................................................

Page

Overview ......................................................................................................... 756
Quick Start Guide ............................................................................................. 757
Functional Description of GIO Module................................................................. 759
Device Modes of Operation ................................................................................ 762
GIO Control Registers ....................................................................................... 763
I/O Control Summary ........................................................................................ 781

SPNU517C – March 2018
Submit Documentation Feedback

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

755

Overviewwww.ti.com

19.1 Overview
The GIO module offers general-purpose input and output capability. It supports up to eight 8-bit ports for a
total of up to 64 GIO terminals. Each of these 64 terminals can be independently configured as input or
output and configured as required by the application. The GIO module also supports generation ofinterrupts whenever a rising edge or falling edge or any toggle is detected on up to 32 of these GIO
terminals. Refer to the device datasheet for identifying the number of GIO ports supported and the GIO
terminals capable of generating an interrupt.
The main features of the GIO module are summarized as follows:• Allows each GIO terminal to be configured for general-purpose input or output functions• Supports programmable pull directions on each input GIO terminal• Supports GIO output in push/pull or open-drain modes• Allows up to 32 GIO terminals to be used for generating interrupt requests

756

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Quick Start Guide

www.ti.com

19.2 Quick Start Guide
The GIO module comprises two separate components: an input/output (I/O) block and an interrupt
generation block. Figure 19-1 and Figure 19-2 show what you should do after reset to configure the GIO
module as I/O or for generating interrupts.
In GIO interrupt service routine, you shall read the GIO offset register (GIOOFF1 or GIOOFF2, dependingon high-/low-level interrupt) to clear the flag and find the pending interrupt GIO channel.
Figure 19-1. I/O Function Quick Start Flow Chart
Power-On Reset

Release Peripheral Reset by setting PENA bit in
Clock Control Register (0xFFFFFFD0)

Enable clock to GIO through PCR(Check device datasheet for the peripheral select)

Bring GIO out of reset by writing 1 to GIOGCR0

Configure as input/output?
Input

OutputClear corresponding bits in GIODIR to 0

Set corresponding bits in GIODIR to 1

Enable pull?

Open drain?
Yes

No

Clear corresponding bits in
GIOPULDIS to 0

Set corresponding bits in
GIOPULDIS to 1

Yes

No
Set corresponding bits in
GIOPDR to 1

Clear corresponding bits in
GIOPDR to 0

Pull up/down?
Down
Clear corresponding
bits in GIOPSL to 0

Output 1 or 0?
Set corresponding bits
in to GIOPSL to 1

0

1
Write 1 to corresponding bitsin GIODSET

Write 1 to corresponding bitsin GIODCLR

Read corresponding bits in GIODIN, getting input value

SPNU517C – March 2018
Submit Documentation Feedback

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

757

Quick Start Guide

www.ti.com

Figure 19-2. Interrupt Generation Function Quick Start Flow Chart
Power-On Reset

Enable Peripherals by setting PENA bit in Clock Control Register (0xFFFFFFD0)

Enable GIO through PCR (Check devicedatasheet for the peripheral select)

Initialize vector interrupt table - Map GIO low level interrupt and / or high levelinterrupt service routine to pre-defined device specific interrupt channel.
(Check device datasheet)

Enable the FIQ/IRQ interrupt in VIM (Check VIM User Guide)

Enable the FIQ/IRQ interrupt in CPU (Check CPU User Guide)

Bring GIO out of reset (See register GIOGCR0)

Both rising and falling edge / single edge trigger interrupt?
Both edge

Single edge

Set corresponding bits in GIOINTDETto 1

Clear corresponding bits in GIOINTDETto 0

Rising/Falling edge?
Rising

Falling

Set corresponding bits in
GIOPOL to 1

Clear corresponding bits in
GIOPOL to 0

Configure as high /low level interrupt?
High level

Low level

Write 1 to corresponding bits in GIOLVLSET

Write 1 to corresponding bits in GIOLVLCLR

Write 0xFF to clean the GIO interrupt flag register GIOFLG

Write 1 to corresponding bits in GIOENASET to enable interrupt

758

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackFunctional Description of GIO Module

www.ti.com

19.3 Functional Description of GIO Module
As shown in Figure 19-3, the GIO module comprises of two separate components: an input/output (I/O)
block and an interrupt block.
Figure 19-3. GIO Module Diagram

GIO Modulexx
xx

GIOx[7:0] port

PIN
CONTROL
BLOCKInterrupt Requests

INTERRUPTCONTROLBLOCK

To Interrupt Manager

Host Interface

19.3.1 I/O Functions
The I/O block allows each GIO terminal to be configured for use as a general-purpose input or output inthe application. The GIO module supports multiple registers to control the various aspects of the input andoutput functions. These are described as follows.
• Data direction (GIODIR)
Configures GIO terminal(s) as input (default) or output through the GIODIRx registers.
• Data input (GIODIN)
Reflects the logic level on GIO terminals in the GIODINx registers. A high voltage (V IH or greater)
applied to the pin causes a high value (1) in the data input register (GIODIN[7:0]). When a low voltage(V IL or less) is applied to the pin, the data input register reads a low value (0). The V IH and V IL values
are device specific and can be found in the device datasheet.
• Data output (GIODOUT)
Configures the logic level to be output on GIO terminal(s) configured as outputs. A low value (0) written
to the data output register forces the pin to a low output voltage (V OL or lower). A high value (1) written
to the data output register (GIODOUTx) forces the pin to a high output voltage (V OH or higher) if theopen drain functionality is disabled (GIOPDRx[7:0]). If open drain functionality is enabled, a high value(1) written to the data output register forces the pin to a high-impedance state (Z).
• Data set (GIODSET)
Allows logic HIGH to be output on GIO terminal(s) configured as outputs by writing 1's to the required
bits in the GIODSETx registers. If open drain functionality is enabled, a high value (1) written to thedata output register forces the pin to a high-impedance state (Z). The GIODSETx registers eliminate
the need for the application to perform a read-modify-write operation when it needs to set one or more
GIO pin(s).
• Data clear (GIODCLR)
Allows logic LOW to be output on GIO terminal(s) configured as outputs by writing 1s to the required
bits in the GIODCLRx registers. The GIODCLRx registers eliminate the need for the application to
perform a read-modify-write operation when it needs to clear one or more GIO pin(s).
• Open drain (GIOPDR)Open drain functionality is enabled or disabled (default) using the open drain register GIOPDR[7:0]
register. If open-drain mode output is enabled on a pin, a high value (1) written to the data output
register (GIODOUTx[7:0]) forces the pin to a high impedance state (Z).
SPNU517C – March 2018
Submit Documentation Feedback

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

759

Functional Description of GIO Module••

www.ti.com

Pull disable (GIOPULDIS)Disables the internal pull on GIO terminal(s) configured as inputs by writing to the GIOPULDISxregisters.
Pull select (GIOPSL)
Selects internal pull down (default) or pull up on GIO terminal(s) configured as inputs by writing to the
GIOPULSELx registers.

Refer to the specific device's datasheet to identify the number of GIO ports as well as the input and output
functions supported. Some devices may not support the programmable pull controls. In that case, the pull
disable and the pull select register controls will not work.

19.3.2 Interrupt Function
The GIO module supports up to 32 terminals to be configured for generating an interrupt to the hostprocessor through the Vectored Interrupt Manager (VIM). The main functions of the interrupt block are:• Select the GIO pin(s) that is/are used to generate interrupt(s)This is done via the interrupt enable set and clear registers, GIOENASET and GIOENACLR.
• Select the edge on the selected GIO pin(s) that is/are used to generate interrupt(s): rising/falling/both
Rising or falling edge can be selected via the GIOPOL register. If interrupt is required to be generated
on both rising and falling edges, this can be configured via the GIOINTDET register.
• Select the interrupt priority
Low- or high-level interrupt can be selected through the GIOLVLSET and GIOLVLCLR registers.
• Individual interrupt flags are set in the GIOFLG register
The terminals on GIO ports A through D are all interrupt-capable and can be used to handle either general
I/O functions or interrupt requests. Each interrupt request can be connected to the VIM at one of two
different levels – High (or A) and Low (or B), depending on the VIM channel number. The VIM has aninherent priority scheme so that a request on a lower number channel has a higher priority than a request
on a higher number channel. Refer the device datasheet to identify the VIM channel numbers for the GIOlevel A and level B interrupt requests. Also note that the interrupt priority of level A and level B interrupt
handling blocks can be re-programmed in the VIM.

19.3.3 GIO Block Diagram
The GIO block diagram (Figure 19-4) represents the flow of information through a pin. The shaded area
corresponds to the I/O block; the unshaded area corresponds to the interrupt block.

760

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackFunctional Description of GIO Module

www.ti.com

Figure 19-4. GIO Block Diagram

GIOPSL

Pull Select

GIOPULDIS
Pull Disable
GIODIRx
GIOPDRxGIODSETx
external pin

GIODOUTx
GIODINx

Falling edge

Interrupt disable

Rising edge

Interrupt enableLow-level
High-level

GIOPOL

GIOFLG

GIOENASET
GIOENACLR

GIOLVLSET
GIOLVLCLR

Low-level(level B)
interrupt(1)

handling

High-level(level A)
interrupt

GIOINTDETTo
VIM

VBUSP (peripheral bus)

GIODCLRx

(1)

To
VIM

handling(1)

A single low-level-interrupt-handling block and a single high-level-interrupt-handling block service all of theinterrupt-capable external pins, but only one pin can be serviced by an interrupt block at a time.

SPNU517C – March 2018
Submit Documentation Feedback

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

761

Device Modes of Operation

www.ti.com

19.4 Device Modes of Operation
The GIO module behaves differently in different modes of operation. There are two main modes:• Emulation mode
• Power-down mode (low-power mode)

19.4.1 Emulation Mode
Emulation mode is used by debugger tools to stop the CPU at breakpoints to read registers.
NOTE: Emulation Mode and Emulation Registers
Emulation mode is a mode of operation of the device and is separate from the GIO
emulation registers (GIOEMU1 and GIOEMU2). The contents of these emulation registers
are identical to the contents of GIO offset registers (GIOOFF1 and GIOOFF2). Bothemulation registers and GIO offset registers are NOT cleared when they are read inemulation mode. GIO offset registers are cleared when they are read in normal mode (otherthan emulation mode). The emulation registers are NOT cleared when they are read innormal mode. The intention for the emulation registers is that software can use them without
clearing the flags.

During emulation mode:• External interrupts are not captured because the VIM is unable to service interrupts.
• Any register can be read without affecting the state of the system.
• A write to a register still does affect the state of the system.

19.4.2 Power-Down Mode (Low-Power Mode)
In power-down mode, the clock signal to the GIO module is disabled. Thus, there is no switching and theonly current draw comes from leakage current. In power-down mode, interrupt pins become level-sensitive
rather than edge-sensitive. The polarity bit changes function from falling-edge-triggered to low-leveltriggered and rising-edge-triggered to high-level-triggered. A corresponding level on an interrupt pin pulls
the module out of low-power mode, if the interrupt is also enabled to wake up the device out of a lowpower mode.
19.4.2.1 Module-Level Power Down
The GIO module can be placed into a power down state by disabling the GIO peripheral module via theappropriate bit in the peripheral power down register. Please refer to the Peripheral Central Resource
Registers (Section 2.5.3) for details.
19.4.2.2 Device-Level Power Down
The entire device can be placed in one of the pre-defined low-power modes: doze, snooze, or sleep using
the clock source and clock domain disable registers in the system module.

762

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

GIO Control Registers

www.ti.com

19.5 GIO Control Registers
Table 19-1 shows the summary of the GIO registers. The registers are accessible in 8-, 16-, and 32-bit
reads or writes.
The start address for the GIO module is FFF7 BC00h.
The GIO module supports up to 8 ports. Refer to your device-specific data manual to identify the actual
number of GIO ports and the number of pins in each GIO port implemented on this device.
The GIO module supports up to 4 interrupt-capable ports. Refer to the device datasheet to identify theactual number of interrupt-capable GIO ports and the number of pins in each GIO port implemented on
this device.
Table 19-1. GIO Control Registers
OffsetAcronym

Register Description

00h

GIOGCR0

GIO Global Control Register

Section 19.5.1

Section08h

GIOINTDET

GIO Interrupt Detect Register

Section 19.5.2

0Ch

GIOPOLGIO Interrupt Polarity Register

Section 19.5.3

10h

GIOENASET

GIO Interrupt Enable Set Register

Section 19.5.4.1

14h

GIOENACLRGIO Interrupt Enable Clear Register

Section 19.5.4.2

18h

GIOLVLSET

GIO Interrupt Priority Set Register

Section 19.5.5.1

1Ch

GIOLVLCLRGIO Interrupt Priority Clear Register

Section 19.5.5.2

20h

GIOFLG

GIO Interrupt Flag Register

Section 19.5.6

24h

GIOOFF1

GIO Offset 1 Register

Section 19.5.7
Section 19.5.8

28h

GIOOFF2

GIO Offset 2 Register

2Ch

GIOEMU1

GIO Emulation 1 Register

Section 19.5.930h

GIOEMU2

GIO Emulation 2 Register

Section 19.5.10

34h

GIODIRAGIO Data Direction Register

Section 19.5.11

38h

GIODINA

GIO Data Input Register

Section 19.5.12

3Ch

GIODOUTAGIO Data Output Register

Section 19.5.13

40h

GIODSETAGIO Data Set Register

Section 19.5.14

44h

GIODCLRAGIO Data Clear Register

Section 19.5.15

48h

GIOPDRAGIO Open Drain Register

Section 19.5.16

4Ch

GIOPULDISAGIO Pull Disable Register

Section 19.5.17

50h

GIOPSLAGIO Pull Select Register

Section 19.5.18

54h

GIODIRB

GIO Data Direction Register

Section 19.5.11

58h

GIODINB

GIO Data Input Register

Section 19.5.12

5Ch

GIODOUTBGIO Data Output Register

Section 19.5.13

60h

GIODSETBGIO Data Set Register

Section 19.5.14

64h

GIODCLRB

GIO Data Clear Register

Section 19.5.15

68h

GIOPDRB

GIO Open Drain Register

Section 19.5.16

6Ch

GIOPULDISBGIO Pull Disable Register

Section 19.5.17

70h

GIOPSLB

GIO Pull Select Register

Section 19.5.18

SPNU517C – March 2018
Submit Documentation Feedback

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

763

GIO Control Registers

www.ti.com

19.5.1 GIO Global Control Register (GIOGCR0)
The GIOGCR0 register contains one bit that controls the module reset status. Writing a 0 to this bit puts
the module in a reset state. After system reset, this bit must be set to 1 before configuring any otherregister of the GIO module. Figure 19-5 and Table 19-2 describe this register.
Figure 19-5. GIO Global Control Register (GIOGCR0) [offset = 00h]
31

16
Reserved
R-0

15

1

0

Reserved

RESET

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 19-2. GIO Global Control Register (GIOGCR0) Field Descriptions
Bit

Field

31-1

Reserved

0

RESET

Value
0

Description
Reads return 0. Writes have no effect.
GIO reset.

0

The GIO is in reset state.

1

The GIO is operating normally.

NOTE: Note that putting the GIO module in reset state is not the same as putting it in a low-powerstate.

764

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

GIO Control Registers

www.ti.com

19.5.2 GIO Interrupt Detect Register (GIOINTDET)The GIO module supports generation of an interrupt request to CPU when a rising edge, falling edge, orboth edges is detected on one or more GIO pin(s). The GIOINTDET register allows both rising and fallingedges to be detected, while the GIOPOL register allows the application to define whether a rising edge ora falling edge is to be detected. Figure 19-6 and Table 19-3 describe this register.
Figure 19-6. GIO Interrupt Detect Register (GIOINTDET) [offset = 08h]
31

24

23

16

GIOINTDET 3

GIOINTDET 2

R/W-0

R/W-0

15

8

7

0

GIOINTDET 1

GIOINTDET 0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 19-3. GIO Interrupt Detect Register (GIOINTDET) Field Descriptions
Bit

Field

31-24

GIOINTDET 3

23-16

15-8

7-0

Value

Interrupt detection select for pins GIOD[7:0]0

The flag sets on either a falling or a rising edge on the corresponding pin, depending on the polarity
setup in the polarity register (GIOPOL).

1

The flag sets on both the rising and falling edges on the corresponding pin.

GIOINTDET 2Interrupt detection select for pins GIOC[7:0]0

The flag sets on either a falling or a rising edge on the corresponding pin, depending on the polarity
setup in the polarity register (GIOPOL).

1

The flag sets on both the rising and falling edges on the corresponding pin.

GIOINTDET 1

Interrupt detection select for pins GIOB[7:0]0

The flag sets on either a falling or a rising edge on the corresponding pin, depending on the polarity
setup in the polarity register (GIOPOL).

1

The flag sets on both the rising and falling edges on the corresponding pin.

GIOINTDET 0

SPNU517C – March 2018
Submit Documentation Feedback

Description

Interrupt detection select for pins GIOA[7:0]0

The flag sets on either a falling or a rising edge on the corresponding pin, depending on the polarity
setup in the polarity register (GIOPOL).

1

The flag sets on both the rising and falling edges on the corresponding pin.

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

765

GIO Control Registers

www.ti.com

19.5.3 GIO Interrupt Polarity Register (GIOPOL)The GIOPOL register configures the polarity of the edge, rising edge or falling edge, that needs to be
detected. When the device is in low-power mode, the GIOPOL register controls the level, high or low,which will be detected by the GIO module. Figure 19-7 and Table 19-4 describe this register.
Figure 19-7. GIO Interrupt Polarity Register (GIOPOL) [offset = 0Ch]
31

24

23

16

GIOPOL 3

GIOPOL 2

R/W-0

R/W-0

15

8

7

0

GIOPOL 1

GIOPOL 0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 19-4. GIO Interrupt Polarity Register (GIOPOL) Field Descriptions
Bit

Field

31-24

GIOPOL 3

Value

Description
Interrupt polarity select for pins GIOD[7:0]Normal operation (user or privileged mode):0

The flag is set on the falling edge on the corresponding pin.

1

The flag is set on the rising edge on the corresponding pin.
Low-power mode (GIO module clocks off):

23-16

0

The interrupt is triggered on the low level.

1

The interrupt is triggered on the high level.

GIOPOL 2

Interrupt polarity select for pins GIOC[7:0]Normal operation (user or privileged mode):0

The flag is set on the falling edge on the corresponding pin.

1

The flag is set on the rising edge on the corresponding pin.
Low-power mode (GIO module clocks off):

15-8

0

The interrupt is triggered on the low level.

1

The interrupt is triggered on the high level.

GIOPOL 1

Interrupt polarity select for pins GIOB[7:0]Normal operation (user or privileged mode):0

The flag is set on the falling edge on the corresponding pin.

1

The flag is set on the rising edge on the corresponding pin.
Low-power mode (GIO module clocks off):

7-0

0

The interrupt is triggered on the low level.

1

The interrupt is triggered on the high level.

GIOPOL 0

Interrupt polarity select for pins GIOA[7:0]Normal operation (user or privileged mode):0

The flag is set on the falling edge on the corresponding pin.

1

The flag is set on the rising edge on the corresponding pin.
Low-power mode (GIO module clocks off):766

0

The interrupt is triggered on the low level.

1

The interrupt is triggered on the high level.

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

GIO Control Registers

www.ti.com

19.5.4 GIO Interrupt Enable Registers (GIOENASET and GIOENACLR)The GIOENASET and GIOENACLR registers control which interrupt-capable pins are actually configured
as interrupts. If the interrupt is enabled, the rising edge, falling edge, or both edges on the selected pinlead to an interrupt request.
19.5.4.1 GIOENASET Register
Figure 19-8 and Table 19-5 describe this register.
NOTE: Enabling Interrupt at the Device Level
The interrupt channel in the Vectored Interrupt Manager (VIM) must be enabled for theinterrupt request to be forwarded to the CPU. Additionally, the ARM CPU (CPSR bit 7 or 6)
must be cleared to respond to interrupt requests (IRQ/FIQ).

Figure 19-8. GIO Interrupt Enable Set Register (GIOENASET) [offset = 10h]
31

24

23

16

GIOENASET 3

GIOENASET 2

R/W-0

R/W-0

15

8

7

0

GIOENASET 1

GIOENASET 0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 19-5. GIO Interrupt Enable Set Register (GIOENASET) Field Descriptions
Bit

Field

31-24

GIOENASET 3

Value

Description
Interrupt enable for pins GIOD[7:0]0Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: Enables the interrupt.

23-16

GIOENASET 2Interrupt enable for pins GIOC[7:0]0Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: Enables the interrupt.

15-8

GIOENASET 1

Interrupt enable for pins GIOB[7:0]0Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: Enables the interrupt.

7-0

GIOENASET 0

Interrupt enable for pins GIOA[7:0]0Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: Enables the interrupt.

SPNU517C – March 2018
Submit Documentation Feedback

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

767

GIO Control Registers

www.ti.com

19.5.4.2 GIOENACLR Register
This register disables the interrupt. Figure 19-9 and Table 19-6 describe this register.
Figure 19-9. GIO Interrupt Enable Clear Register (GIOENACLR) [offset = 14h]
31

24

23

16

GIOENACLR 3

GIOENACLR 2

R/W-0

R/W-0

15

8

7

0

GIOENACLR 1

GIOENACLR 0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 19-6. GIO Interrupt Enable Clear Register (GIOENACLR) Field Descriptions
Bit

Field

31-24

GIOENACLR 3

Value

Description
Interrupt disable for pins GIOD[7:0]0Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: Disables the interrupt.

23-16

GIOENACLR 2Interrupt disable for pins GIOC[7:0]0Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: Disables the interrupt.

15-8

GIOENACLR 1

Interrupt disable for pins GIOB[7:0]0Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: Disables the interrupt.

7-0

GIOENACLR 0Interrupt disable for pins GIOA[7:0]0Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: Disables the interrupt.

768

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

GIO Control Registers

www.ti.com

19.5.5 GIO Interrupt Priority Registers (GIOLVLSET and GIOLVLCLR)The GIOLVLSET and GIOLVLCLR registers configure the interrupts as high-level (level A) or low-level(level B) going to the Vectored Interrupt Manager (VIM). Each interrupt is individually configured.
• The high-level interrupts are recorded to GIOOFF1 and GIOEMU1.
• The low-level interrupts are recorded to GIOOFF2 and GIOEMU2.
NOTE: The GIO module can generate two interrupt requests. These are connected to two separate
channels on the Vectored Interrupt Manager (VIM). The lower-numbered VIM channels arehigher priority. The GIO interrupt connected to a lower-number channel is the high-level (alsocalled level A) GIO interrupt, while the GIO interrupt connected to a higher-number channel
is the low-level (also called level B) GIO interrupt.

19.5.5.1 GIOLVLSET Register
The GIOLVLSET register is used to configure an interrupt as a high-level interrupt going to the VIM. An
interrupt can be configured as a high-level interrupt by writing a 1 into the corresponding bit of the
GIOLVLSET register. Writing a 0 has no effect. Figure 19-10 and Table 19-7 describe this register.
Figure 19-10. GIO Interrupt Priority Register (GIOLVLSET) [offset = 18h]
31

16
GIOLVLSET 3

GIOLVLSET 2

R/W-0

R/W-0

15

8

7

0

GIOLVLSET 1

GIOLVLSET 0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 19-7. GIO Interrupt Priority Register (GIOLVLSET) Field Descriptions
Bit

Field

31-24

GIOLVLSET 3

Value

Description
GIO high-priority interrupt for pins GIOD[7:0].

0

Read: The interrupt is a low-level interrupt. The low-level interrupts are recorded to GIOOFF2
and GIOEMU2.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is set as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
Write: Sets the interrupt as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.

23-16

GIOLVLSET 2

GIO high-priority interrupt for pins GIOC[7:0].
0

Read: The interrupt is a low-level interrupt. The low-level interrupts are recorded to GIOOFF2
and GIOEMU2.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is set as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
Write: Sets the interrupt as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.

15-8

GIOLVLSET 1

GIO high-priority interrupt for pins GIOB[7:0].
0

Read: The interrupt is a low-level interrupt. The low-level interrupts are recorded to GIOOFF2
and GIOEMU2.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is set as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
Write: Sets the interrupt as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.

SPNU517C – March 2018
Submit Documentation Feedback

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

769

GIO Control Registers

www.ti.com

Table 19-7. GIO Interrupt Priority Register (GIOLVLSET) Field Descriptions (continued)
Bit

Field

7-0

GIOLVLSET 0

Value

Description
GIO high-priority interrupt for pins GIOA[7:0].

0

Read: The interrupt is a low-level interrupt. The low-level interrupts are recorded to GIOOFF2
and GIOEMU2.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is set as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
Write: Sets the interrupt as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.

770

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

GIO Control Registers

www.ti.com

19.5.5.2 GIOLVLCLR Register
The GIOLVLCLR register is used to configure an interrupt as a low-level interrupt going to the VIM. An
interrupt can be configured as a low-level interrupt by writing a 1 into the corresponding bit of the
GIOLVLCLR register. Writing a 0 has no effect. Figure 19-11 and Table 19-8 describe this register.
Figure 19-11. GIO Interrupt Priority Register (GIOLVLCLR) [offset = 1Ch]
31

16
GIOLVLCLR 3

GIOLVLCLR 2

R/W-0

R/W-0

15

8

7

0

GIOLVLCLR 1

GIOLVLCLR 0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 19-8. GIO Interrupt Priority Register (GIOLVLCLR) Field Descriptions
Bit

Field

31-24

GIOLVLCLR 3

Value

Description
GIO low-priority interrupt for pins GIOD[7:0]0Read: The interrupt is a low-level interrupt.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is set as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
Write: Sets the interrupt as a low-level interrupt. The low-level interrupts are recorded to
GIOOFF2 and GIOEMU2.

23-16

GIOLVLCLR 2

GIO low-priority interrupt for pins GIOC[7:0]0Read: The interrupt is a low-level interrupt.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is set as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
Write: Sets the interrupt as a low-level interrupt. The low-level interrupts are recorded to
GIOOFF2 and GIOEMU2.

15-8

GIOLVLCLR 1

GIO low-priority interrupt for pins GIOB[7:0]0Read: The interrupt is a low-level interrupt.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is set as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
Write: Sets the interrupt as a low-level interrupt. The low-level interrupts are recorded to
GIOOFF2 and GIOEMU2.

7-0

GIOLVLCLR 0

GIO low-priority interrupt for pins GIOA[7:0]0Read: The interrupt is a low-level interrupt.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is set as a high-level interrupt. The high-level interrupts are recorded to
GIOOFF1 and GIOEMU1.
Write: Sets the interrupt as a low-level interrupt. The low-level interrupts are recorded to
GIOOFF2 and GIOEMU2.

SPNU517C – March 2018
Submit Documentation Feedback

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

771

GIO Control Registers

www.ti.com

19.5.6 GIO Interrupt Flag Register (GIOFLG)The GIOFLG register contains flags indicating that the transition edge (as set in GIOINTDET and GIOPOL
registers) has occurred. The flag can be cleared by the CPU writing a 1 to the flag that is set. The flag isalso cleared by reading the appropriate interrupt offset register (GIOOFF1 or GIOOFF2). Figure 19-12 andTable 19-9 describe this register.
Figure 19-12. GIO Interrupt Flag Register (GIOFLG) [offset = 20h]
31

24

23

16

GIOFLG 3

GIOFLG 2

R/W1C-0

R/W1C-0

15

8

7

0

GIOFLG 1

GIOFLG 0

R/W1C-0

R/W1C-0

LEGEND: R/W = Read/Write; W1C = Write 1 to clear; -n = value after reset

Table 19-9. GIO Interrupt Flag Register (GIOFLG) Field Descriptions
Bit

Field

31-24

GIOFLG 3

Value

Description
GIO flag for pins GIOD[7:0]0Read: A transition has not occurred since the last clear.
Write: Writing a 0 to this bit has no effect.

1

Read: The selected transition on the corresponding pin has occurred.
Write: The corresponding bit is cleared to 0.
Note: This bit is also cleared by a read to the corresponding bit in the appropriate offset
register.

23-16

GIOFLG 2

GIO flag for pins GIOC[7:0]0Read: A transition has not occurred since the last clear.
Write: Writing a 0 to this bit has no effect.

1

Read: The selected transition on the corresponding pin has occurred.
Write: The corresponding bit is cleared to 0.
Note: This bit is also cleared by a read to the corresponding bit in the appropriate offset
register.

15-8

GIOFLG 1

GIO flag for pins GIOB[7:0]0Read: A transition has not occurred since the last clear.
Write: Writing a 0 to this bit has no effect.

1

Read: The selected transition on the corresponding pin has occurred.
Write: The corresponding bit is cleared to 0.
Note: This bit is also cleared by a read to the corresponding bit in the appropriate offset
register.

7-0

GIOFLG 0

GIO flag for pins GIOA[7:0]0Read: A transition has not occurred since the last clear.
Write: Writing a 0 to this bit has no effect.

1

Read: The selected transition on the corresponding pin has occurred.
Write: The corresponding bit is cleared to 0.
Note: This bit is also cleared by a read to the corresponding bit in the appropriate offset
register.

NOTE: An interrupt flag gets set when the selected transition happens on the corresponding GIO pin
regardless of whether the interrupt generation is enabled or not. It is recommended toclear a flag before enabling the interrupt generation for a transition on the corresponding GIO
pin.

772

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

GIO Control Registers

www.ti.com

19.5.7 GIO Offset Register 1 (GIOOFF1)
The GIOOFF1 register provides a numerical offset value that represents the pending external interrupt
with high priority. The offset value can be used to locate the position of the interrupt routine in a vector
table in application software. Figure 19-13 and Table 19-10 describe this register.
NOTE: Reading this register clears it, GIOEMU1 and the corresponding flag bit in the GIOFLG
register. However, in emulation mode, a read to this register does not clear any register orflag. If more than one GIO interrupts are pending, then reading the GIOOFF1 register willchange the contents of GIOOFF1 and GIOEMU1 to show the offset value for the next
highest-priority pending interrupt. The application can choose to service all GIO interrupts
from the same service routine by continuing to read the GIOOFF1 register until it reads
zeros.

Figure 19-13. GIO Offset 1 Register (GIOOFF1) [offset = 24h]31

16
Reserved
R-0

15

6

5

0

Reserved

GIOOFF1

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 19-10. GIO Offset 1 Register (GIOOFF1) Field Descriptions
Bit

Field

31-6

Reserved

5-0

GIOOFF1

Value
0

Description
Reads return 0. Writes have no effect.
GIO offset 1. These bits index the currently pending high-priority interrupt. This register and theflag bit (in the GIOFLG register) are also cleared when this register is read, except in emulation
mode.

0

No interrupt is pending.

1hInterrupt 0 (corresponding to GIOA0) is pending with a high priority.

:

:

8h

Interrupt 7 (corresponding to GIOA7) is pending with a high priority.

9hInterrupt 8 (corresponding to GIOB0) is pending with a high priority.

:

:

10h

Interrupt 16 (corresponding to GIOB7) is pending with a high priority.

:

:

20h

Interrupt 32 (corresponding to GIOD7) is pending with a high priority.

21h-3FhSPNU517C – March 2018
Submit Documentation Feedback

Reserved

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

773

GIO Control Registers

www.ti.com

19.5.8 GIO Offset B Register (GIOOFF2)The GIOOFF2 register provides a numerical offset value that represents the pending external interrupt
with low priority. The offset value can be used to locate the position of the interrupt routine in a vector
table in application software. Figure 19-14 and Table 19-11 describe this register.
NOTE: Reading this register clears it, GIOEMU2 and the corresponding flag bit in the GIOFLG
register. However, in emulation mode, a read to this register does not clear any register orflag. If more than one GIO interrupts are pending, then reading the GIOOFF1 register willchange the contents of GIOOFF2 and GIOEMU2 to show the offset value for the next
highest-priority pending interrupt. The application can choose to service all GIO interrupts
from the same service routine by continuing to read the GIOOFF1 register until it reads
zeros.

Figure 19-14. GIO Offset 2 Register (GIOOFF2) [offset = 28h]31

16Reserved
R-0

15

6

5

0

Reserved

GIOOFF2

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 19-11. GIO Offset 2 Register (GIOOFF2) Field Descriptions
Bit

Field

31-6

Reserved

5-0

GIOOFF2

Value
0

Reads return 0. Writes have no effect.
GIO offset 2. These bits index the currently pending low-priority interrupt. This register and theflag bit (in the GIOFLG register) are also cleared when this register is read, except in emulation
mode.

0

No interrupt is pending.

1hInterrupt 0 (corresponding to GIOA0) is pending with a low priority.

:

:

8h

Interrupt 7 (corresponding to GIOA7) is pending with a low priority.

9hInterrupt 8 (corresponding to GIOB0) is pending with a low priority.

:

:

10h

Interrupt 16 (corresponding to GIOB7) is pending with a low priority.

:

:

20h

Interrupt 32 (corresponding to GIOD7) is pending with a low priority.

21h-3Fh

774

Description

Reserved

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

GIO Control Registers

www.ti.com

19.5.9 GIO Emulation A Register (GIOEMU1)The GIOEMU1 register is a read-only register. The contents of this register are identical to the contents of
GIOOFF1. The intention for the this register is that software can use it without clearing the flags.
Figure 19-15 and Table 19-12 describe this register.
NOTE: The corresponding flag in the GIOFLG register is not cleared when the GIOEMU1 register isread.

Figure 19-15. GIO Emulation 1 Register (GIOEMU1) [offset = 2Ch]
31

16
Reserved
R-0

15

6

5

0

Reserved

GIOEMU1

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 19-12. GIO Emulation 1 Register (GIOEMU1) Field Descriptions
Bit

Field

31-6

Reserved

5-0

GIOEMU1

Value
0

Description
Reads return 0. Writes have no effect.
GIO offset emulation 1. These bits index the currently pending high-priority interrupt. No registeror flag is cleared by reading this register.

0

No interrupt is pending.

1hInterrupt 0 (corresponding to GIOA0) is pending with a high priority.

:

:

8h

Interrupt 7 (corresponding to GIOA7) is pending with a high priority.

9hInterrupt 8 (corresponding to GIOB0) is pending with a high priority.

:

:

10h

Interrupt 16 (corresponding to GIOB7) is pending with a high priority.

:

:

20h

Interrupt 32 (corresponding to GIOD7) is pending with a high priority.

21h-3FhSPNU517C – March 2018
Submit Documentation Feedback

Reserved

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

775

GIO Control Registers

www.ti.com

19.5.10 GIO Emulation B Register (GIOEMU2)The GIOEMU2 register is a read-only register. The contents of this register are identical to the contents of
GIOOFF2. The intention for the this register is that software can use it without clearing the flags.
Figure 19-16 and Table 19-13 describe this register.
NOTE: The corresponding flag in the GIOFLG register is not cleared when the GIOEMU2 register isread.

Figure 19-16. GIO Emulation 2 Register (GIOEMU2) [offset = 30h]
31

16
Reserved
R-0

15

6

5

0

Reserved

GIOEMU2

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 19-13. GIO Emulation 2 Register (GIOEMU2) Field Descriptions
Bit

Field

31-6

Reserved

5-0

GIOEMU2

Value
0

Reads return 0. Writes have no effect.
GIO offset emulation 2. These bits index the currently pending low-priority interrupt. No registeror flag is cleared by reading this register.

0

No interrupt is pending.

1hInterrupt 0 (corresponding to GIOA0) is pending with a low priority.

:

:

8h

Interrupt 7 (corresponding to GIOA7) is pending with a low priority.

9hInterrupt 8 (corresponding to GIOB0) is pending with a low priority.

:

:

10h

Interrupt 16 (corresponding to GIOB7) is pending with a low priority.

:

:

20h

Interrupt 32 (corresponding to GIOD7) is pending with a low priority.

21h-3Fh

776

Description

Reserved

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

GIO Control Registers

www.ti.com

19.5.11 GIO Data Direction Registers (GIODIR[A-B])
The GIODIR register controls whether the pins of a given port are configured as inputs or outputs.
Figure 19-17 and Table 19-14 describe this register.
Figure 19-17. GIO Data Direction Registers (GIODIR[A-B]) [offset = 34h, 54h]
31

16
Reserved
R-0

15

8

7

0

Reserved

GIODIR[7:0]

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19-14. GIO Data Direction Registers (GIODIR[A-B]) Field Descriptions
Bit

Field

31-8

Reserved

7-0

GIODIR[n]Value0

Description
Reads return 0. Writes have no effect.
GIO data direction of port n, pins [7:0]0

The GIO pin is an input. Note: If the pin direction is set as an input, the output buffer is tristated.

1

The GIO pin is an output.

19.5.12 GIO Data Input Registers (GIODIN[A-B])
Values in the GIODIN register reflect the current state (high = 1 or low = 0) on the pins of the port.
Figure 19-18 and Table 19-15 describe this register.
Figure 19-18. GIO Data Input Registers (GIODIN[A-B]) [offset = 38h, 58h]
31

16
Reserved
R-0

15

8

7

0

Reserved

GIODIN[7:0]

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19-15. GIO Data Input Registers (GIODIN[A-B]) Field Descriptions
Bit

Field

31-8

Reserved

7-0

GIODIN[n]Value

SPNU517C – March 2018
Submit Documentation Feedback0

Description
Reads return 0. Writes have no effect.
GIO data input for port n, pins [7:0]0The pin is at logic low (0).

1

The pin is at logic high (1).

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

777

GIO Control Registers

www.ti.com

19.5.13 GIO Data Output Registers (GIODOUT[A-B])
Values in the GIODOUT register specify the output state (high = 1 or low = 0) of the pins of the port when
they are configured as outputs. Figure 19-19 and Table 19-16 describe this register.
NOTE: Values in the GIODSET register set the data output control register bits to 1 regardless ofthe current value in the GIODOUT bits.

Figure 19-19. GIO Data Output Registers (GIODOUT[A-B]) [offset = 3Ch, 5Ch]
31

16
Reserved
R-0

15

8

7

0

Reserved

GIODOUT[7:0]

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19-16. GIO Data Output Registers (GIODOUT[A-B]) Field Descriptions
Bit

Field

31-8

Reserved

7-0

GIODOUT[n]

Value
0

Description
Reads return 0. Writes have no effect.
GIO data output of port n, pins[7:0].

0

The pin is driven to logic low (0).

1

The pin is driven to logic high (1).
Note: Output is in high impedance state if the GIOPDRx bit = 1 and GIODOUTx bit = 1.
Note: GIO pin is placed in output mode by setting the GIODIRx bit to 1.

19.5.14 GIO Data Set Registers (GIODSET[A-B])
Values in this register set the data output control register bits to 1 regardless of the current value in the
GIODOUT bits. The contents of this register reflect the contents of GIODOUT. Figure 19-20 and Table 1917 describe this register.
Figure 19-20. GIO Data Set Registers (GIODSET[A-B]) [offset = 40h, 60h]
31

16
Reserved
R-0

15

8

7

0

Reserved

GIODSET[7:0]

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19-17. GIO Data Set Registers (GIODSET[A-B]) Field Descriptions
Bit

Field

31-8

Reserved

7-0

GIODSET[n]

Value
0

Description
Reads return 0. Writes have no effect.
GIO data set for port n, pins[7:0]. This bit drives the output of GIO pin high.

0

Write: Writing a 0 has no effect.

1

Write: The corresponding GIO pin is driven to logic high (1).
Note: The current logic state of the GIODOUT bit will also be displayed by this bit.
Note: GIO pin is placed in output mode by setting the GIODIRx bit to 1.

778

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

GIO Control Registers

www.ti.com

19.5.15 GIO Data Clear Registers (GIODCLR[A-B])
Values in this register clear the data output register (GIO Data Output Register [A-H]) bit to 0 regardless of
its current value. The contents of this register reflect the contents of GIODOUT. Figure 19-21 andTable 19-18 describe this register.
Figure 19-21. GIO Data Clear Registers (GIODCLR[A-B]) [offset = 44h, 64h]
31

16
Reserved
R-0

15

8

7

0

Reserved

GIODCLR[7:0]

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19-18. GIO Data Clear Registers (GIODCLR[A-B]) Field Descriptions
Bit

Field

31-8

Reserved

7-0

GIODCLR[n]

Value
0

Description
Reads return 0. Writes have no effect.
GIO data clear for port n, pins[7:0]. This bit drives the output of GIO pin low.

0

Write: Writing a 0 has no effect.

1

Write: The corresponding GIO pin is driven to logic low (0).
Note: The current logic state of the GIODOUT bit will also be displayed by this bit.
Note: GIO pin is placed in output mode by setting the GIODIRx bit to 1.

19.5.16 GIO Open Drain Registers (GIOPDR[A-B])
Values in this register enable or disable the open drain capability of the data pins. Figure 19-22 andTable 19-19 describe this register.
Figure 19-22. GIO Open Drain Registers (GIOPDR[A-B]) [offset = 48h, 68h]
31

16
Reserved
R-0

15

8

7

0

Reserved

GIOPDR[7:0]

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19-19. GIO Open Drain Registers (GIOPDR[A-B]) Field Descriptions
Bit

Field

31-8

Reserved

7-0

GIOPDR[n]Value

SPNU517C – March 2018
Submit Documentation Feedback0

Description
Reads return 0. Writes have no effect.
GIO open drain for port n, pins[7:0]0

The GIO pin is configured in push/pull (normal GIO) mode. The output voltage is V OLor lower if
GIODOUT bit = 0 and V OH or higher if GIODOUT bit = 1.

1

The GIO pin is configured in open drain mode. The GIODOUTx bit controls the state of the GIO
output buffer: GIODOUTx = 0, the GIO output buffer is driven low; GIODOUTx = 1, the GIO output
buffer is tristated.

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

779

GIO Control Registers

www.ti.com

19.5.17 GIO Pull Disable Registers (GIOPULDIS[A-B])
Values in this register enable or disable the pull control capability of the pins. Figure 19-23 and Table 1920 describe this register.
Figure 19-23. GIO Pull Disable Registers (GIOPULDIS[A-B]) [offset = 4Ch, 6Ch]
31

16
Reserved
R-0

15

8

7

0

Reserved

GIOPULDIS[7:0]

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19-20. GIO Pull Disable Registers (GIOPULDIS[A-B]) Field Descriptions
Bit

Field

31-8

Reserved

7-0

GIOPULDIS[n]

Value
0

Description
Reads return 0. Writes have no effect.
GIO pull disable for port n, pins[7:0]. Writes to this bit will only take effect when the GIO pin
configured as an input pin.

0

The pull functionality is enabled.

1

The pull functionality is disabled.
Note: The GIO pin is placed in input mode by clearing the GIODIRx bit to 0.

19.5.18 GIO Pull Select Registers (GIOPSL[A-B])
Values in this register select the pull up or pull down functionality of the pins. Figure 19-24 and Table 1921 describe this register.
Figure 19-24. GIO Pull Select Registers (GIOPSL[A-B]) [offset = 50h, 70h]
31

16
Reserved
R-0

15

8

7

0

Reserved

GIOPSL[7:0]

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19-21. GIO Pull Select Registers (GIOPSL[A-B]) Field Descriptions
Bit

Field

31-8

Reserved

7-0

GIOPSL[n]Value0

Description
Reads return 0. Writes have no effect.
GIO pull select for port n, pins[7:0]0The pull down functionality is select, when pull up/pull down logic is enabled.

1

The pull up functionality is select, when pull up/pull down logic is enabled.
Note: The pull up/pull down functionality is enabled by clearing corresponding bit in
GIOPULDIS to 0.

780

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

I/O Control Summary

www.ti.com

19.6 I/O Control Summary
The behavior of the output buffer and the pull control is summarized in Table 19-22.
Table 19-22. Output Buffer and Pull Control Behavior for GIO Pins

(1)
(2)
(3)
(4)
(5)
(6)

Module under
Reset?

Pin Direction(GIODIR) (1) (2)Open Drain
Enable(GIOPDR) (1) (3)Pull Disable(GIOPULDIS) (1) (4)Pull Select(GIOPSL) (1) (5)

Yes

X

X

X

No

0

X

0

No

0

X

No

0

No

0

No
No

Pull Control

Output Buffer (6)X

EnabledDisabled0

Pull down

Disabled0

1

Pull up

DisabledX

1

0

Disabled

DisabledX

1

1

Disabled

Disabled

1

0

X

X

Disabled

Enabled

1

1

X

X

Disabled

Enabled

X = Don't care
GIODIR = 0 for input; = 1 for output
See Section 19.5.16
GIOPULDIS = 0 for enabling pull control; = 1 for disabling pull control
GIOPSL= 0 for pull-down functionality; = 1 for pull-up functionality
If open drain is enabled, output buffer will be disabled if a high level (1) is being output.

SPNU517C – March 2018
Submit Documentation Feedback

General-Purpose Input/Output (GIO) Module
Copyright © 2018, Texas Instruments Incorporated

781

Chapter 20
SPNU517C – March 2018

Controller Area Network (DCAN) ModuleThis chapter describes the controller area network (DCAN) module.
Topic

20.1
20.2
20.3

782

...........................................................................................................................

Page

Overview ........................................................................................................ 783
Module Operation ............................................................................................. 783
DCAN Control Registers ................................................................................... 818

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackOverviewwww.ti.com

20.1 Overview
The Controller Area Network is a high-integrity, serial, multi-master communication protocol for distributed
real-time applications. This CAN module is implemented according to ISO 11898-1 and is suitable forindustrial, automotive and general embedded communications.

20.1.1 Features
The DCAN module provides the following features:Protocol• Supports CAN protocol version 2.0 part A, B
Speed
• Bit rates up to 1 MBit/s
MailBox• Configurable Message objects• Individual identifier masks for each message object• Programmable FIFO mode for message objects
Power• Global power down and wakeup support• Local power down and wakeup support
Debug• Suspend mode for debug support• Programmable loop-back modes for self-test operation• Direct access to Message RAM in test mode
• Supports Two interrupt lines - Level 0 and Level 1
Others• Automatic Message RAM initialization• Automatic bus on after Bus-Off state by a programmable 32-bit timer• CAN Rx / Tx pins configurable as general purpose IO pins
• Software module reset• Message RAM parity check mechanism• Dual clock source to reduce jitter20.2 Module Operation
20.2.1 Functional Description
The CAN protocol is an ISO standard (ISO 11898) for serial data communication. This protocol uses NonReturn To Zero (NRZ) with bit-stuffing. And the communication is carried over a two-wire balanced
signaling scheme.
The DCAN data communication happens through the CAN_TX and CAN_RX pins. An additionaltransceiver hardware is required for the connection to the physical layer (CAN bus) CAN_High and
CAN_Low.
The DCAN register set can be accessed directly by the CPU. These registers are used to control andconfigure the CAN module and the Message RAM.
Individual CAN message objects should be configured for communication over a CAN network. The
message objects and identifier masks are stored in the Message RAM.
The CAN module internally handles functions such as acceptance filtering, transfer of messages from andto the Message RAM, handling of transmission requests as well as the generation of interrupts.
SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

783

Module Operation

www.ti.com

20.2.2 CAN Blocks
The DCAN Module, shown in Figure 20-1, is comprised of the following basic blocks.
20.2.2.1 CAN Core
The CAN Core consists of the CAN Protocol Controller and the Rx/Tx Shift Register. It handles all ISO
11898-1 protocol functions.
20.2.2.2 Message RAM
The DCAN Message RAM enables storage of CAN messages.
20.2.2.3 Message Handler
The Message Handler is a state machine that controls the data transfer between the single ported
Message RAM and the CAN Core’s Rx/Tx Shift Register. It also handles acceptance filtering and theinterrupt request generation as programmed in the control registers.
Figure 20-1. Block Diagram

784

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

20.2.2.4 Message RAM Interface
The Interface Register sets control the CPU read and write accesses to the Message RAM.
There are three interface registers IF1,IF2 and IF3.
IF1 and IF2 Interface Registers sets for read and write access.
IF3 Interface Register set for read access only.
The Interface Registers have the same word-length as the Message RAM.
Additional information can be found in Section 20.2.6.
20.2.2.5 Register and Message Object Access
During normal operation, data consistency of the message objects is guaranteed by indirectly accessing
the message objects through the interface registers IF1 and IF2.
In order to be able to perform tests on the message object memory, a dedicated test mode has been
implemented, which allows direct access by the CPU. During normal operation direct access has to be
avoided.
20.2.2.6 Dual Clock Source
Two clock domains are provided to the DCAN module:
1. VCLK - The peripheral synchronous clock domain as the general module clock source.
2. VCLKA - The peripheral asynchronous clock source domain provided to the CAN core as clock source(CAN_CLK) for generating the CAN Bit Timing.
If a frequency modulated clock output from FMPLL is used as the VCLK source, then VCLKA should bederived from an unmodulated clock source (for example, OSCIN source).
The clock source for VCLKA is selected by the Peripheral Asynchronous Clock Source Register in thesystem module.
Both clock domains can be derived from the same clock source (so that VCLK = VCLKA). However, if
frequency modulation in the FMPLL is enabled (spread spectrum clock), then due to the high precision
clocking requirements of the CAN Core, the FMPLL clock source should not be used for VCLKA.
Alternatively, a separate clock without any modulation (for example, derived directly from the OSCIN
clock) should be used for VCLKA.
Please refer to the system module reference guide and the device datasheet for more information how to
configure the relevant clock source registers in the system module.
Between the two clock domains, a synchronization mechanism is implemented in the DCAN module inorder to ensure correct data transfer.

NOTE: If the dual clock functionality is used, then VCLK must always be higher or equal to
CAN_CLK (derived from the asynchronous clock source), in order to achieve a stablefunctionality of the DCAN. Here also the frequency shift of the modulated VCLK has to beconsidered:ƒ0, VCLK ± ΔƒFM,VCLK ≥ ƒCANCLKThe CAN Core has to be programmed to at least 8 clock cycles per bit time. To achieve atransfer rate of 1 MBaud when using the asynchronous clock domain as the clock source for
CAN_CLK, an oscillator frequency of 8MHz or higher has to be used.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

785

Module Operation

www.ti.com

20.2.3 CAN Bit Timing
The DCAN supports bit rates between less than 1 kBit/s and 1000 kBit/s.
Each member of the CAN network has its own clock generator, typically derived from a crystal oscillator.
The Bit timing parameters can be configured individually for each CAN node, creating a common Bit rateeven though the CAN nodes’ oscillator periods (fosc) may be different.
20.2.3.1 Bit Time and Bit Rate
According to the CAN specification, the Bit time is divided into four segments (see Figure 20-2):• Synchronization Segment (Sync_Seg)• Propagation Time Segment (Prop_Seg)• Phase Buffer Segment 1 (Phase_Seg1)• Phase Buffer Segment 2 (Phase_Seg2)
Figure 20-2. Bit Timing
Nominal CAN bit time

Sync_
Seg

Prop_Seg

Phase_Seg1

Phase_Seg2

1 time quantum(tq)

Sample point

Each segment consists of a specific number of time quanta. The length of one time quantum, (tq), which isthe basic time unit of the bit time, is given by the CAN_CLK and the Baud Rate Prescalers (BRPE and
BRP). With these two Baud Rate Prescalers combined, divider values from 1 to 1024 can be programmed:
tq = Baud Rate Prescaler / CAN_CLKApart from the fixed length of the synchronization segment, these numbers are programmable.
Table 20-1 describes the minimum programmable ranges required by the CAN protocol. A given bit rate
may be met by different Bit time configurations.
NOTE: For proper functionality of the CAN network, the physical delay times and the oscillator’s
tolerance range have to be considered.

Table 20-1. Parameters of the CAN Bit Time

786

Parameter

Range

RemarkSync_Seg

1 tq (fixed)

Synchronization of bus input to CAN_CLK

Prop_Seg[1 … 8] tq

Compensates for the physical delay times

Phase_Seg1[1 … 8] tq

May be lengthened temporarily by synchronization

Phase_Seg2[1 … 8] tq

May be shortened temporarily by synchronization

Synchronization Jump Width (SJW)[1 … 4] tq

May not be longer than either Phase Buffer Segment

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

20.2.3.1.1 Synchronization Segment
The Synchronization Segment (Sync_Seg) is the part of the bit time where edges of the CAN bus level are
expected to occur. If an edge occurs outside of Sync_Seg, its distance to the Sync_Seg is called thephase error of this edge.
20.2.3.1.2 Propagation Time Segment
This part of the bit time is used to compensate physical delay times within the CAN network. These delay
times consist of the signal propagation time on the bus and the internal delay time of the CAN nodes.
20.2.3.1.3 Phase Buffer Segments and Synchronization
The Phase Buffer Segments (Phase_Seg1 and Phase_Seg2) and the Synchronization Jump Width (SJW)
are used to compensate for the oscillator tolerance.
The Phase Buffer Segments surround the sample point. The Phase Buffer Segments may be lengthenedor shortened by synchronization.
The Synchronization Jump Width (SJW) defines how far the resynchronizing mechanism may move thesample point inside the limits defined by the Phase Buffer Segments to compensate for edge phaseerrors.
Synchronizations occur on edges from recessive to dominant. Their purpose is to control the distance
between edges and sample points.
Edges are detected by sampling the actual bus level in each time quantum and comparing it with the bus
level at the previous sample point. A synchronization may be done only if a recessive bit was sampled at
the previous sample point and if the actual time quantum’s bus level is dominant.
An edge is synchronous if it occurs inside of Sync_Seg, otherwise its distance to the Sync_Seg is theedge phase error, measured in time quanta. If the edge occurs before Sync_Seg, the phase error is
negative, else it is positive.
20.2.3.1.4 Oscillator Tolerance Range
With the introduction of CAN protocol version 1.2, the option to synchronize on edges from dominant torecessive became obsolete. Only edges from recessive to dominant are considered for synchronization.
The protocol update to version 2.0 (A and B) had no influence on the oscillator tolerance.
The tolerance range df for an oscillator’s frequency fosc around the nominal frequency fnom with:(1-df) x fnom ≤ fosc ≤ (1+df) x fnom

(34)

depends on the proportions of Phase_Seg1, Phase_Seg2, SJW, and the bit time. The maximum tolerance
df is the defined by two conditions (both shall be met):min(Phase_Seg1, Phase_Seg2)
I: df ≤ ----------------------------------------------------------------------[2x(13xbit_time - Phase_Seg2 )]SJW
II: df ≤ ------------------------20xbit_time(35)

It has to be considered that SJW may not be larger than the smaller of the Phase Buffer Segments andthat the Propagation Time Segment limits that part of the bit time that may be used for the Phase Buffer
Segments.
The combination Prop_Seg = 1 and Phase_Seg1 = Phase_Seg2 = SJW = 4 allows the largest possible
oscillator tolerance of 1.58%. This combination with a Propagation Time Segment of only 10% of the bittime is not suitable for short bit times; it can be used for bit rates of up to 125 kBit/s (bit time = 8 μs) with abus length of 40 m.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

787

Module Operation

www.ti.com

20.2.3.2 DCAN Bit Timing Registers
In the DCAN, the bit timing configuration is programmed in two register bytes, additionally a third byte fora baud rate prescaler extension of 4 bits (BREP) is provided. The sum of Prop_Seg and Phase_Seg1 (asTSEG1) is combined with Phase_Seg2 (as TSEG2) in one byte, SJW and BRP (plus BRPE in third byte)
are combined in the other byte
In this bit timing register, the components TSEG1, TSEG2, SJW and BRP have to be programmed to anumerical value that is one less than its functional value; so instead of values in the range of [1… n],values in the range of [0 … n-1] are programmed. That way, SJW (functional range of [1 … 4]) isrepresented by only two bits.
Therefore the length of the Bit time is (programmed values) [TSEG1 + TSEG2 + 3] tq or (functional values)[Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq.
The data in the Bit Timing Register (BTR) is the configuration input of the CAN protocol controller. The
Baud Rate Prescaler (configured by BRPE/BRP) defines the length of the time quantum (the basic time
unit of the bit time); the Bit Timing Logic (configured by TSEG1, TSEG2, and SJW) defines the number oftime quanta in the bit time.
20.2.3.2.1 Calculation of the Bit Timing Parameters
Usually, the calculation of the bit timing configuration starts with a desired bit rate or bit time. The resulting
Bit time (1 / Bit rate) must be an integer multiple of the CAN clock period.
NOTE: 8 MHz is the minimum CAN clock frequency required to operate the DCAN at a bit rate of
1 MBit/s.

The bit time may consist of 8 to 25 time quanta. The length of the time quantum tq is defined by the Baud
Rate Prescaler with tq = (Baud Rate Prescaler) / CAN_CLK. Several combinations may lead to the desired
bit time, allowing iterations of the following steps.
First part of the bit time to be defined is the Prop_Seg. Its length depends on the delay times measured in
the system. A maximum bus length as well as a maximum node delay has to be defined for expandible
CAN bus systems. The resulting time for Prop_Seg is converted into time quanta (rounded up to thenearest integer multiple of tq).
The Sync_Seg is 1 tq long (fixed), leaving (bit time – Prop_Seg – 1) tq for the two Phase Buffer Segments.
If the number of remaining tq is even, the Phase Buffer Segments have the same length, Phase_Seg2 =Phase_Seg1, else Phase_Seg2 = Phase_Seg1 + 1.
The minimum nominal length of Phase_Seg2 has to be regarded as well. Phase_Seg2 may not be shorter
than any CAN controller’s Information Processing Time in the network, which is device dependent and canbe in the range of [0 … 2] tq.
The length of the Synchronization Jump Width is set to its maximum value, which is the minimum of 4 andPhase_Seg1.
If more than one configurations are possible to reach a certain Bit rate, it is recommended to choose theconfiguration that allows the highest oscillator tolerance range.
CAN nodes with different clocks require different configurations to come to the same bit rate. The
calculation of the propagation time in the CAN network, based on the nodes with the longest delay times,
is done once for the whole network.
The CAN system’s oscillator tolerance range is limited by the node with the lowest tolerance range.
The calculation may show that bus length or bit rate have to be decreased or that the oscillator
frequencies’ stability has to be increased in order to find a protocol compliant configuration of the CAN bit
timing.

788

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

The resulting configuration is written into the Bit Timing Register:Tseg2 = Phase_Seg2-1
Tseg1 = Phase_Seg1+ Prop_Seg-1
SJW = SynchronizationJumpWidth-1
BRP = Prescaler-1
20.2.3.2.2 Example for Bit Timing at High Baudrate
In this example, the frequency of CAN_CLK is 10 MHz, BRP is 0, the bit rate is 1 MBit/s.
tq
delay of bus driverdelay of receiver circuit
delay of bus line (40m)
tProp
tSJW
tTSeg1
tTSeg2tSync-Seg
bit time
tolerance for CAN_CLK

100
60
40
220
700
100
800
100
100
1000
1.58

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%

=

tCAN_CLK

=
=
=
=
=
=
=

INT (2 × delays + 1) = 7 × tq
1 × tqtProp + tSJWInformation Processing Time + 1 × tq
1 × tqtSync-Seg + tTSeg1 + tTSeg2==

min(TSeg1, TSeg2)----------------------------------------------------------------------[2 x (13 x bit_time - TSeg2)]

(36)

0.1µs
---------------------------------------------------------[2 x (13 x 1µs - 0.1µs)]

(37)

0.38%

In this example, the concatenated bit time parameters are (1-1)3&(8-1)4&(1-1)2&(1-1)6, so the Bit Timing
Register is programmed to 0000 0700h.

20.2.3.2.3 Example for Bit Timing at Low Baudrate
In this example, the frequency of CAN_CLK is 2 MHz, BRP is 1, the bit rate is 100 KBit/s.
tq
delay of bus driverdelay of receiver circuit
delay of bus line (40m)
tProp
tSJW
tTSeg1
tTSeg2tSync-Seg
bit time
tolerance for CAN_CLKSPNU517C – March 2018
Submit Documentation Feedback

1
200
80
220
1
4
5
3
1
9
0.43

µs
ns
ns
ns
µs
µs
µs
µs
µs
µs
%

=

2 × tCAN_CLK

=
=
=
=
=
=
=

1 × tq
4 × tqtProp + tSJWInformation Processing Time + 3 × tq
1 × tqtSync-Seg + tTSeg1 + tTSeg2
min(TSeg1, TSeg2)----------------------------------------------------------------------[2 x (13 x bit_time - TSeg2)]

(38)

=

3µs
---------------------------------------------------------[2 x (13 x 9µs - 3µs)]

(39)

=

1.32%

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

789

Module Operation

www.ti.com

In this example, the concatenated bit time parameters are (3-1)3&(5-1)4&(4-1)2&(2-1)6, so the Bit Timing
Register is programmed to 0000 24C1h.

20.2.4 CAN Module Configuration
After a hardware reset all CAN protocol functions are disabled. The CAN module must be initialized andconfigured before it can participate on the CAN bus.
20.2.4.1 DCAN RAM Initialization through harware
To start with a clean DCAN RAM ,the complete DCAN RAM can be initialized with zeros and the
ecc/parity bits set accordingly by configuring the following registers in the system module:
1. Memory Hardware Initialization Global Control Register (MINITGCR)
2. Memory Initialization Enable Register (MSINENA)
For more details on RAM hardware initialization support, refer to the system module.
20.2.4.2 CAN Module Initialization
To initialize the CAN Controller, you have to set up the CAN Bit timing and those message objects thathave to be used for CAN communication. Message objects that are not needed, can be deactivated.
So the two critical steps are:
1. Configuration of CAN Bit Timings
2. Configuration of Message Objects
20.2.4.2.1 Software Configuration of CAN Bit Timings
This step involves configuring the CAN baud rate register with the calculated CAN bit timing value. The
calculation procedure of CAN bit timing values for BTR register are mentioned in Section 20.2.3. Refer toFigure 20-3 for CAN bit timing software configuration flow.

790

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

Figure 20-3. CAN Bit-timing Configuration
Normal Mode
Set Init = 1

Set CCE = 1

Wait for Init =1
Initialization Mode

Write Bit timing values into BTR

Clear CCE and Init
CCE = 0 , Init =0

Wait for Init =0
Normal Mode

Step 1: Enter “initialization mode” by setting the Init (Initialization) bit in the CAN Control Register.
While the Init bit is set, the message transfer from and to the CAN bus is stopped, and the status of the
CAN_TX output is recessive (high).
The CAN error counters are not updated. Setting the Init bit does not change any other configuration
register.
Also note that the CAN module is also in initialization mode on hardware reset and during Bus-Off.
Step 2: Set the CCE (Configure Change Enable) bit in the CAN Control Register.
The access to the Bit Timing Register for the configuration of the Bit timing is enabled when both Init andCCE bits in the CAN Control Register are set.
Step 3: Wait for the Init bit to get set. This would make sure that the module has entered “Initializationmode”.
Step 4: Write the Bit-Timing values into the BTR (Bit-Timing Register) Register.
Refer to Section 20.2.3.2.1 for BTR value calculation for a given bit-timing.
Step 5: Clear the CCE bit followed by Init bit.
Step 6: Wait for the Init bit to clear. This would make sure that the module has come out of “initializationmode”.
After step 6 (Init bit cleared), the module will attempt a synchronization on the CAN bus, provided that the
BTR settings are meeting the CAN bus parameters.
SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

791

Module Operation

www.ti.com

NOTE: The module would not come out of the “initialization mode” if any incorrect BTR values are
written in step 4.

20.2.4.2.2 Configuration of Message Objects
The whole Message RAM should be configured before putting the CAN into operation. All the message
objects are deactivated by default. The user should configure the message object that are to be used to aparticular identifier. The user can change the configuration of any message object or deactivate it whenrequired.
The message objects can be configured only through the Interface registers (IFx) and the CPU does nothave direct access to the message object (Message RAM) when DCAN is in operation.
To configure the message objects, the user must know about:
1. The message object structure (Section 20.2.5)
2. The interface register set (IFx) (Section 20.2.6)
NOTE: The message objects initialization is independent of the bit-timing configuration procedure.

792

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

20.2.5 Message RAM
The DCAN Message RAM contains message objects and parity bits for the message objects.
20.2.5.1 Structure of Message Objects
Figure 20-4 shows the structure of a message object.
The grayed fields are those parts of the message object that are represented in dedicated registers. For
example, the transmit request flags of all message objects are represented in centralized transmit request
registers.
Figure 20-4. Structure of a Message Object
UMask
MsgValMsk[28:0]
ID[28:0]

MXtd
Xtd

MDir
Dir

EoB
DLC[3:0]

Message Object
unused NewDat
Data 0
Data 1

MsgLstData 2RxIE
TxIE
Data 3 Data 4

IntPndData 5

RmtEn
Data 6

TxRqstData 7

Table 20-2. Message Object Field Descriptions
Name

Value

MsgValDescription
Message valid0

The message object is ignored by the Message Handler.

1

The message object is to be used by the Message Handler.
Note: The CPU should reset the MsgVal bit of all unused Messages Objects during the initialization
before it resets bit Init in the CAN Control Register. MsgVal must also be reset if the messages object
is no longer used in operation. For reconfiguration of message objects during normal operation see
Section 20.2.7.6 and Section 20.2.7.7.

UMask

Use Acceptance Mask
0

Mask bits (Msk[28:0], MXtd and MDir) are ignored and not used for acceptance filtering.

1

Mask bits are used for acceptance filtering.
Note: If the UMask bit is set to 1, the message object's mask bits have to be programmed duringinitialization of the message object before MsgVal is set to 1.

ID[28:0]

Message IdentifierID[28:0]29-bit ("extended") identifier bits

ID[28:18]

11-bit ("standard") identifier bits

Msk[28:0]

Identifier Mask
0

The corresponding bit in the message identifier is not used for acceptance filtering (don't care).

1

The corresponding bit in the message identifier is used for acceptance filtering.

Xtd

Extended Identifier0

The 11-bit ("standard") identifier will be used for this message object.

1

The 29-bit ("extended") identifier will be used for this message object.

MXtd

Mask Extended Identifier0

The extended identifier bit (IDE) has no effect on the acceptance filtering.

1

The extended identifier bit (IDE) is used for acceptance filtering.
Note: When 11-bit ("standard") identifiers are used for a message object, the identifiers of received
data frames are written into bits ID[28:18]. For acceptance filtering, only these bits together with mask
bits Msk[28:18] are considered.

Dir

Message Direction
0

Direction = receive: On TxRqst, a remote frame with the identifier of this message object istransmitted. On reception of a data frame with matching identifier, the message is stored in thismessage object.

1

Direction = transmit: On TxRqst, a data frame is transmitted. On reception of a remote frame withmatching identifier, the TxRqst bit of this message object is set (if RmtEn = 1).

MDir

Mask Message Direction
0

The message direction bit (Dir) has no effect on the acceptance filtering.

1

The message direction bit (Dir) is used for acceptance filtering.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

793

Module Operation

www.ti.com

Table 20-2. Message Object Field Descriptions (continued)
Name

Value

EOB

Description
End of Block0

The message object is part of a FIFO Buffer block and is not the last message object of this FIFO
Buffer block.

1

The message object is a single message object or the last message object in a FIFO Buffer Block.
Note: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single
message objects (not belonging to a FIFO Buffer), this bit must always be set to 1.

NewDatNew Data0

No new data has been written into the data bytes of this message object by the Message Handler
since the last time when this flag was cleared by the CPU.

1

The Message Handler or the CPU has written new data into the data bytes of this message object.

MsgLstMessage Lost (only valid for message objects with direction = receive)0

No message was lost since the last time when this bit was reset by the CPU.

1

The Message Handler stored a new message into this message object when NewDat was still set, so
the previous message has been overwritten.

RxIE

Receive Interrupt Enable
0

IntPnd will not be triggered after the successful reception of a frame.

1

IntPnd will be triggered after the successful reception of a frame.

TxIETransmit Interrupt Enable
0

IntPnd will not be triggered after the successful transmission of a frame.

1

IntPnd will be triggered after the successful transmission of a frame.

IntPndInterrupt Pending0This message object is not the source of an interrupt.

1This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will
point to this message object if there is no other interrupt source with higher priority.

RmtEn

Remote Enable0

At the reception of a Remote Frame, TxRqst is not changed.

1

At the reception of a Remote Frame, TxRqst is set.

TxRqstTransmit Request
0This message object is not waiting for a transmission.

1

The transmission of this message object is requested and is not yet done.

DLC[3:0]

Data Length Code
0-8

Data Frame has 0-8 data bytes.

9-15

Data Frame has 8 data bytes.
Note: The Data Length Code of a message object must be defined to the same value as in thecorresponding objects with the same identifier at other nodes. When the Message Handler stores adata frame, it will write the DLC to the value given by the received message.

Data 0

1st data byte of a CAN Data Frame

Data 1

2nd data byte of a CAN Data Frame

Data 2

3rd data byte of a CAN Data Frame

Data 34th data byte of a CAN Data Frame

Data 45th data byte of a CAN Data Frame

Data 56th data byte of a CAN Data Frame

Data 67th data byte of a CAN Data Frame

Data 78th data byte of a CAN Data Frame
Note: Byte Data 0 is the first data byte shifted into the shift register of the CAN Core during a
reception, byte Data 7 is the last. When the Message Handler stores a data frame, it will write all theeight data bytes into a message object. If the Data Length Code is less than 8, the remaining bytes ofthe message object may be overwritten by undefined values.

794

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

20.2.5.2 Addressing Message Objects in RAM
The starting location of a particular message object in RAM is:
Message RAM base address + (message object number) × 0x20.
This means that Message Object 1 starts at offset 0x0020; Message Object 2 starts at offset 0x0040, andso on.
NOTE: 0 is not a valid message object number. Writing to the address of an unimplemented
message object may overwrite an implemented message object.
The base address for DCAN1 RAM is 0xFF1E 0000, and DCAN2 RAM is 0xFF1C 0000.

Message Object number 1 has the highest priority.
Table 20-3. Message RAM Addressing in Debug/Suspend and RDA mode
Message
ObjectNumberBase Address Offset

Word
Number

1

0x00200x0024

Debug/Suspend mode,see Section 20.2.5.3

RDA mode,
see Section 20.2.5.4

1

ParityData Bytes 4-7

2

MXtd, MDir, Mask

Data Bytes 0-3

0x0028

3

Xtd, Dir, ID

ID[27:0], DLC

0x002C

4

Ctrl

Mask, Xtd, Dir, ID[28]0x00305

Data Bytes 3-0

Parity, Ctrl, MXtd, MDir

0x0034

6

Data Bytes 7-4

--

:

:

:

:

:

31

0x03E01

ParityData Bytes 4-7

0x03E4

2

MXtd, MDir, Mask

Data Bytes 0-3

0x03E8

3

Xtd, Dir, ID

ID[27]:0, DLC

0x03EC

4

Ctrl

Mask, Xtd, Dir, ID[28]0x03F05

Data Bytes 3-0

Parity, Ctrl, MXtd, MDir

0x03F4

6

Data Bytes 7-4

--

:

:

:

:

:

63

0x07E01

ParityData Bytes 4-7

0x07E4

2

MXtd, MDir, Mask

Data Bytes 0-3

64

SPNU517C – March 2018
Submit Documentation Feedback

0x07E8

3

Xtd, Dir, ID

ID[27:0], DLC

0x07EC

4

Ctrl

Mask, Xtd, Dir, ID[28]0x07F05

Data Bytes 3-0

Parity, Ctrl, MXtd, MDir

0x07F4

6

Data Bytes 7-4--0x00001

ParityData Bytes 4-7

0x0004

2

MXtd, MDir, Mask

Data Bytes 0-30x0008

3

Xtd, Dir, ID

ID[27]:0, DLC

0x000C

4

Ctrl

Mask, Xtd, Dir, ID[28]0x00105

Data Bytes 3-0

Parity, Ctrl, MXtd, MDir

0x0014

6

Data Bytes 7-4--

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

795

Module Operation

www.ti.com

20.2.5.3 Message RAM Representation in Debug/Suspend ModeIn Debug/Suspend mode, the Message RAM will be memory mapped. This allows the external debug unit
to access the Message RAM.
NOTE: During Debug/Suspend Mode, the Message RAM cannot be accessed via the IFx register
sets.

Figure 20-5. Message RAM Representation in Debug/Suspend Mode
Bit

31

30

29

15

28

14

13

27
12

26
11

MsgAddr + 0x08

MsgAddr + 0x0C

24

23

9

8

22
7

21
6

20

19

5

4

18

17

3

16

2

1

0

Reserved

MsgAddr + 0x00

MsgAddr + 0x04

25
10

Reserved
MXtd

MDir

Rsvd

Rsvd

Xtd

Dir

Parity[4:0]
Msk[28:16]
Msk[15:0]
ID[28:16]
ID[15:0]
Reserved

Rsvd

MsgLst

Rsvd

UMask

MsgAddr + 0x10

MsgAddr + 0x14

TxIE

RxIE

RmtEn

Rsvd

EOB

Reserved

DLC[3:0]

Data 3

Data 2

Data 1

Data 0

Data 7

Data 6

Data 5

Data 420.2.5.4 Message RAM Representation in Direct Access Mode
When the RDA bit in Test Register is set while the DCAN module is in Test Mode (Test bit in CAN control
register is set), the CPU has direct access to the Message RAM. Due to the 32-bit bus structure, the RAM
is split into word lines to support this feature. The CPU has access to one word line at a time only.
In RAM Direct Access mode, the RAM is represented by a continuous memory space within the address
frame of the DCAN module, starting at the Message RAM base address.
NOTE: During Direct Access Mode, the Message RAM cannot be accessed via the IFx register sets.
Before entering RDA mode, it must be ensured that the Init bit is set to avoid any conflicts
with the message handler accessing the message RAM.
Any read or write to the RAM addresses for RamDirectAccess during normal operation mode
(TestMode bit or RDA bit is not set) will be ignored.
Writes to Reserved bits have no effect.

Figure 20-6. Message RAM Representation in RAM Direct Access Mode
Bit

31

30
15

29
14

MsgAddr + 0x00

MsgAddr + 0x04

28
13

27
12

24
9

23
8

22
7

21
6

20

19

5

4

Data 6

Data 7

Data 0

Data 1

Data 218

17

3

Data 5

16

2

1

0

Data 3ID[27:12]
ID[11:0]

DLC[3:0]
Msk[28:13]

MsgAddr + 0x0C

796

25
10

Data 4

MsgAddr + 0x08

MsgAddr + 0x102611

Msk[12:0]

Xtd

Dir

ID[28]

EOB

MXtd

MDir

Reserved
Parity[3:0]

Reserved

MsgLstUMask

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

TxIE

RxIE

RmtEn

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

20.2.6 Message Interface Register Sets
Accesses to the Message RAM are performed via the Interface Register sets.
1. Interface Register 1 and 2
2. Interface Register 3
The third Interface Register set IF3 can be configured to automatically receive control and user data from
the Message RAM when a message object has been updated after reception of a CAN message. The
CPU does not need to initiate the transfer from Message RAM to IF3 Register set.
The Message Handler avoids potential conflicts between concurrent accesses to Message RAM and CAN
frame reception/transmission.
There are two modes where the Message RAM can be directly accessed by the CPU:
1. In Debug/Suspend mode (see Section 20.2.5.3)
2. In RAM Direct Access (RDA) mode (see Section 20.2.5.4)
For the Message RAM Base address, please refer to the device datasheet.
A complete message object (see Section 20.2.5.1) or parts of the message object may be transferred
between the Message RAM and the IF1/IF2 Register set (see Section 20.3.20) in one single transfer.
20.2.6.1 Message Interface Register Sets 1 and 2
The Interface Register sets IF1 and IF2 provide indirect read/write access from the CPU to the Message
RAM. The IF1 and IF2 register sets can buffer control and user data to be transferred to and from themessage objects.
Table 20-4. Message Interface Register Sets 1 and 2
Address

IF1 Register Set

Address

IF2 Register Set

16 15

0 [CAN Base +] 31

16 15[CAN Base +] 31
0x100

IF1 Command Mask

IF1 Command
Request

0x120

IF2 Command Mask

0
IF2 Command
Request

0x104

IF1 Mask 2

IF1 Mask 1

0x124

IF2 Mask 2

IF2 Mask 1

0x108

IF1 Arbitration 2

IF1 Arbitration 1

0x128

IF2 Arbitration 2

IF2 Arbitration 1

0x10C

Rsvd

IF1 Message Control

0x12C

Rsvd

IF2 Message Control

0x110

IF1 Data A 2

IF1 Data A 1

0x130

IF2 Data A 2

IF2 Data A 1

0x114

IF1 Data B 2

IF1 Data B 1

0x134

IF2 Data B 2

IF2 Data B 1

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

797

Module Operation

www.ti.com

20.2.6.2 Using Message Interface Register Sets 1 and 2
The Command Register addresses the desired message object in the Message RAM and specifies
whether a complete message object or only parts should be transferred. The data transfer is initiated bywriting the message number to the bits [7:0] of the Command Register.
When the CPU initiates a data transfer between the IF1/IF2 Registers and Message RAM, the Message
Handler sets the Busy bit in the respective Command Register to ‘1’. After the transfer has completed, theBusy bit is set back to ‘0’ (see Figure 20-7).
Figure 20-7. Data Transfer Between IF1 / IF2 Registers and Message RAM
START

No
Write message number to command register
Yes
Busy = 1

No

WR/RD = 1

Yes

Read message object to IF1/IF2
Read message object to IF1/IF2
Write IF1/IF2 to message RAM

Busy = 0798

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

20.2.6.3 Message Interface Register 3
The IF3 register set can automatically be updated with received message objects without the need toinitiate the transfer from Message RAM by CPU.
Table 20-5. Message Interface Register 3
Address[CAN Base +]IF3 Register Set
31

16 15

0

0x140

reserved

IF3 Observation

0x144

IF3 Mask 2

IF3 Mask 1

0x148

IF3 Arbitration 2

IF3 Arbitration 1

0x14C

reserved

IF3 Message Control

0x150

IF3 Data A 2

IF3 Data A 1

0x154

IF3 Data B 2IF3 Data B 1

0x160

IF3 Update Enable 2

IF3 Update Enable 1

0x164

IF3 Update Enable 4

IF3 Update Enable 30x168

IF3 Update Enable 6

IF3 Update Enable 5

0x16C

IF3 Update Enable 8

IF3 Update Enable 7...

The automatic update functionality can be programmed for each message object (see IF3 Update Enable
Register, Section 20.3.29).
All valid message objects in Message RAM that are configured for automatic update, will be checked for
active NewDat flags. If such a message object is found, it will be transferred to the IF3 register, as
controlled by IF3 Observation register. If more than one NewDat flag is active, the message object withthe lowest number has the highest priority for automatic IF3 update.
The NewDat bit in the message object will be reset by a transfer to IF3.
NOTE: The IF3 register set can not be used for transferring data into message objects.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

799

Module Operation

www.ti.com

20.2.7 Message Object Configurations
This section describes the possible message object configurations for CAN communication.
20.2.7.1 Configuration of a Transmit Object for Data Frames
Figure 20-8 shows how a Transmit Object can be initialized.
Figure 20-8. Initialization of a Transmit Object
MsgVal
1

Arb
appl.

Data
appl.

Mask
appl.

EoB
1

Dir
1

NewDat0

MsgLst
0

RxIE
0

TxIE
appl.

IntPnd
0

RmtEn
appl.

TxRqst0

The Arbitration bits (ID[28:0] and Xtd bit) are given by the application. They define the identifier and typeof the outgoing message. If an 11-bit Identifier (Standard Frame) is used (Xtd = 0), it is programmed toID[28:18]. In this case, ID[17:0] can be ignored.
The Data Registers (DLC[3:0] and Data0-7) are given by the application, TxRqst and RmtEn should not be
set before the data is valid.
If the TxIE bit is set, the IntPnd bit will be set after a successful transmission of the message object.
If the RmtEn bit is set, a matching received Remote Frame will cause the TxRqst bit to be set; the Remote
Frame will autonomously be answered by a Data Frame.
The Mask bits (Msk[28:0], UMask, MXtd, and MDir bits) may be used (UMask = 1) to allow groups ofRemote Frames with similar identifiers to set the TxRqst bit. The Dir bit should not be masked. For details,
see Section 20.2.8.8. Identifier masking must be disabled (UMask = 0) if no Remote Frames are allowed
to set the TxRqst bit (RmtEn = 0).
20.2.7.2 Configuration of a Transmit Object for Remote Frames
It is not necessary to configure Transmit Objects for the transmission of Remote Frames. Setting TxRqst
for a Receive Object will cause the transmission of a Remote Frame with the same identifier as the Data
Frame for which this receive Object is configured.
20.2.7.3 Configuration of a Single Receive Object for Data Frames
Figure 20-9 shows how a Receive Object for Data Frames can be initialized.
Figure 20-9. Initialization of a Single Receive Object for Data Frames
MsgVal
1

Arb
appl.

Data
appl.

Mask
appl.

EoB
1

Dir
0

NewDat0

MsgLst
0

RxIE
appl.

TxIE
0

IntPnd0

RmtEn
0

TxRqst0

The Arbitration bits (ID[28:0] and Xtd bit) are given by the application. They define the identifier and typeof accepted received messages. If an 11-bit Identifier (Standard Frame) is used (Xtd = 0), it isprogrammed to ID[28:18]. In this case, ID[17:0] can be ignored. When a Data Frame with an 11-bit
Identifier is received, ID[17:0] will be set to 0.
The Data Length Code (DLC[3:0]) is given by the application. When the Message Handler stores a Data
Frame in the message object, it will store the received Data Length Code and eight data bytes. If the Data
Length Code is less than 8, the remaining bytes of the message object may be overwritten by non
specified values.
The Mask bits (Msk[28:0], UMask, MXtd, and MDir bits) may be used (UMask = 1) to allow groups of Data
Frames with similar identifiers to be accepted. The Dir bit should not be masked in typical applications. If
some bits of the Mask bits are set to “don’t care”, the corresponding bits of the Arbitration Register will beoverwritten by the bits of the stored Data Frame.
If the RxIE bit is set, the IntPnd bit will be set when a received Data Frame is accepted and stored in themessage object.
If the TxRqst bit is set, the transmission of a Remote Frame with the same identifier as actually stored in
the Arbitration bits will be triggered. The content of the Arbitration bits may change if the Mask bits areused (UMask = 1) for acceptance filtering.
800

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

20.2.7.4 Configuration of a Single Receive Object for Remote Frames
Figure 20-10 shows how a Receive Object for Remote Frames can be initialized.
Figure 20-10. Initialization of a Single Receive Object for Remote Frames
MsgVal
1

Arb
appl.

Data
appl.

Mask
appl.

EoB
1

Dir
1

NewDat0

MsgLst
0

RxIE
appl.

TxIE
0

IntPnd0

RmtEn
0

TxRqst0

Receive Objects for Remote Frames may be used to monitor Remote Frames on the CAN bus. The
Remote Frame stored in the Receive Object will not trigger the transmission of a Data Frame. Receive
Objects for Remote Frames may be expanded to a FIFO buffer, see Section 20.2.7.5.
UMask must be set to 1. The Mask bits (Msk[28:0], UMask, MXtd, and MDir bits) may be set to “mustmatch” or to “don’t care”, to allow groups of Remote Frames with similar identifiers to be accepted. The Dir
bit should not be masked in typical applications. For details, see Section 20.2.8.8.
The Arbitration bits (ID[28:0] and Xtd bit) may be given by the application. They define the identifier andtype of accepted received Remote Frames. If some bits of the Mask bits are set to “don’t care”, thecorresponding bits of the Arbitration bits will be overwritten by the bits of the stored Remote Frame. If an
11-bit Identifier (Standard Frame) is used (Xtd = 0), it is programmed to ID[28:18]. In this case, ID[17:0]
can be ignored. When a Remote Frame with an 11-bit Identifier is received, ID[17:0] will be set to 0.
The Data Length Code (DLC[3:0]) may be given by the application. When the Message Handler stores a
Remote Frame in the message object, it will store the received Data Length Code. The data bytes of themessage object will remain unchanged.
If the RxIE bit is set, the IntPnd bit will be set when a received Remote Frame is accepted and stored in
the message object.
20.2.7.5 Configuration of a FIFO BufferWith the exception of the EoB bit, the configuration of Receive Objects belonging to a FIFO Buffer is thesame as the configuration of a single Receive Object.
To concatenate multiple message objects to a FIFO Buffer, the identifiers and masks (if used) of thesemessage objects have to be programmed to matching values. Due to the implicit priority of the message
objects, the message object with the lowest number will be the first message object of the FIFO Buffer.
The EoB bit of all message objects of a FIFO Buffer except the last one have to be programmed to zero.
The EoB bits of the last message object of a FIFO Buffer is set to 1, configuring it as the end of the block.
20.2.7.6 Reconfiguration of Message Objects for the Reception of Frames
A message object with Dir = 0 is configured for the reception of data frames, with Dir = 1 AND Umask = 1
AND RmtEn = 0 it is configured for the reception of remote frames.
It is necessary to reset MsgVal to not valid before changing any of the following configuration and control
bits: ID[28:0], Xtd, Dir, DLC[3:0], RxIE, TxIE, RmtEn, EoB, Umask, Msk[28:0], MXtd, and MDir.
These parts of a message object may be changed without clearing MsgVal: Data[7:0], TxRqst, NewDat,
MsgLst, and IntPnd.
20.2.7.7 Reconfiguration of Message Objects for the Transmission of Frames
A message object with Dir = 1 AND (Umask = 0 OR RmtEn = 1) is configured for the transmission of data
frames.
It is necessary to reset MsgVal to not valid before changing any of the following configuration and control
bits: Dir, RxIE, TxIE, RmtEn, EoB, Umask, Msk[28:0], MXtd, and MDir.
These parts of a message object may be changed without clearing MsgVal: ID[28-0], Xtd, DLC[3:0],
Data[7:0], TxRqst, NewDat, MsgLst, and IntPnd.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

801

Module Operation

www.ti.com

20.2.8 Message Handling
When initialization is finished, the DCAN module synchronizes itself to the traffic on the CAN bus. It does
acceptance filtering on received messages and stores those frames that are accepted into the designatedmessage objects.
The application has to update the data of the messages to be transmitted and enable and request theirtransmission. The transmission is requested automatically when a matching Remote Frame is received.
The application may read messages that are received and accepted. Messages that are not read before
the next messages is accepted for the same message object will be overwritten.
Messages may be read based on interrupts or by polling.
20.2.8.1 Message Handler Overview
The Message Handler state machine controls the data transfer between the Rx/Tx Shift Register of the
CAN Core and the Message RAM. It performs the following tasks:• Data Transfer from Message RAM to CAN Core (messages to be transmitted).
• Data Transfer from CAN Core to the Message RAM (received messages).
• Data Transfer from CAN Core to the Acceptance Filtering unit.
• Scanning of Message RAM for a matching message object (acceptance filtering).
• Scanning the same message object after being changed by IF1/IF2 registers when priority is same or
higher as message the object found by last scanning.
• Handling of TxRqst flags.
• Handling of interrupt flags.
The Message Handler registers contains status flags of all message objects grouped into the following
topics:• Transmission Request flags• New Data flags• Interrupt Pending Flags• Message Valid Registers
Instead of collecting the listed status information of each message object via IFx registers separately,
these Message Handler registers provides a fast and easy way to get an overview (for example, about all
pending transmission requests).
All Message Handler registers are read-only.
20.2.8.2 Receive/Transmit Priority
The receive/transmit priority for the message objects is attached to the message number, not to the CAN
identifier. Message object 1 has the highest priority, while the last implemented message object has thelowest priority. If more than one transmission request is pending, they are serviced due to the priority of
the corresponding message object, so messages with the highest priority can be placed in the message
objects with the lowest numbers.
The acceptance filtering for received Data Frames or Remote Frames is also done in ascending order ofmessage objects, so a frame that has been accepted by a message object cannot be accepted by anothermessage object with a higher Message Number. The last message object may be configured to accept
any Data Frame or Remote Frame that was not accepted by any other message object, for nodes thatneed to log the complete message traffic on the CAN bus.

802

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

20.2.8.3 Transmission of Messages in Event Driven CAN Communication
If the shift register of the CAN Core is ready for loading and if there is no data transfer between the IFx
Registers and Message RAM, the d bits in the Message Valid Register and the TxRqst bits in theTransmission Request Register are evaluated. The valid message object with the highest priority pendingtransmission request is loaded into the shift register by the Message Handler and the transmission isstarted. The message object’s NewDat bit is reset.
After a successful transmission and if no new data was written to the message object (NewDat = 0) since
the start of the transmission, the TxRqst bit will be reset. If TxIE is set, IntPnd will be set after a successfultransmission. If the DCAN has lost the arbitration or if an error occurred during the transmission, themessage will be retransmitted as soon as the CAN bus is free again. If meanwhile the transmission of amessage with higher priority has been requested, the messages will be transmitted in the order of theirpriority.
If Automatic Retransmission mode is disabled by setting the DAR bit in the CAN Control Register, thebehavior of bits TxRqst and NewDat in the Message Control Register of the Interface Register set is asfollows:• When a transmission starts, the TxRqst bit of the respective Interface Register set is reset, while bit
NewDat remains set.
• When the transmission has been successfully completed, the NewDat bit is reset.
When a transmission failed (lost arbitration or error) bit NewDat remains set. To restart the transmission,
the application has to set TxRqst again.
Received Remote Frames do not require a Receive Object. They will automatically trigger thetransmission of a Data Frame, if in the matching Transmit Object the RmtEn bit is set.
20.2.8.4 Updating a Transmit Object
The CPU may update the data bytes of a Transmit Object any time via the IF1/IF2 Interface Registers,neither d nor TxRqst have to be reset before the update.
Even if only a part of the data bytes are to be updated, all four bytes in the corresponding IF1/IF2 Data A
Register or IF1/IF2 Data B Register have to be valid before the content of that register is transferred to themessage object. Either the CPU has to write all four bytes into the IF1/IF2 Data Register or the message
object is transferred to the IF1/IF2 Data Register before the CPU writes the new data bytes.
When only the data bytes are updated, first 0x87 can be written to bits [23:16] of the Command Registerand then the number of the message object is written to bits [7:0] of the Command Register, concurrently
updating the data bytes and setting TxRqst with NewDat.
To prevent the reset of TxRqst at the end of a transmission that may already be in progress while the data
is updated, NewDat has to be set together with TxRqst in event driven CAN communication. For details,
see Section 20.2.8.3.
When NewDat is set together with TxRqst, NewDat will be reset as soon as the new transmission has
started.
20.2.8.5 Changing a Transmit Object
If the number of implemented message objects is not sufficient to be used as permanent message objects
only, the Transmit Objects may be managed dynamically. The CPU can write the whole message(Arbitration, Control, and Data) into the Interface Register. The bits [23:16] of the Command Register canbe set to 0xB7 for the transfer of the whole message object content into the message object. Beforechanging the configuration of a message object, MsgVal has to be reset (see Section 20.2.7.7).
If a previously requested transmission of this message object is not completed but already in progress, itwill be continued; however it will not be repeated if it is disturbed.
To only update the data bytes of a message to be transmitted, bits [23:16] of the Command Registershould be set to 0x87.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

803

Module Operation

www.ti.com

NOTE: After the update of the Transmit Object, the Interface Register set will contain a copy of theactual contents of the object, including the part that had not been updated.

20.2.8.6 Acceptance Filtering of Received Messages
When the arbitration and control bits (Identifier + IDE + RTR + DLC) of an incoming message iscompletely shifted into the shift register of the CAN Core, the Message Handler starts to scan of the
Message RAM for a matching valid message object:• The Acceptance Filtering unit is loaded with the arbitration bits from the CAN Core shift register.
• Then the arbitration and mask bits (including MsgVal, UMask, NewDat, and EoB) of Message Object 1
are loaded into the Acceptance Filtering unit and are compared with the arbitration bits from the shift
register. This is repeated for all following message objects until a matching message object is found, or
until the end of the Message RAM is reached.
• If a match occurs, the scanning is stopped and the Message Handler proceeds depending on the typeof the frame (Data Frame or Remote Frame) received.
20.2.8.7 Reception of Data Frames
The Message Handler stores the message from the CAN Core shift register into the respective message
object in the Message RAM. Not only the data bytes, but all arbitration bits and the Data Length Code arestored into the corresponding message object. This ensures that the data bytes stay associated to theidentifier even if arbitration mask registers are used.
The NewDat bit is set to indicate that new data (not yet seen by the CPU) has been received. The CPU
should reset the NewDat bit when it reads the message object. If at the time of the reception the NewDat
bit was already set, MsgLst is set to indicate that the previous data (supposedly not seen by the CPU) is
lost. If the RxIE bit is set, the IntPnd bit is set, causing the Interrupt Register to point to this message
object.
The TxRqst bit of this message object is reset to prevent the transmission of a Remote Frame, while therequested Data Frame has just been received.
20.2.8.8 Reception of Remote Frames
When a Remote Frame is received, three different configurations of the matching message object have to
be considered:
1. Dir = 1 (direction = transmit), RmtEn = 1, UMask = 1 or 0. The TxRqst bit of this message object is set
at the reception of a matching Remote Frame. The rest of the message object remains unchanged.
2. Dir = 1 (direction = transmit), RmtEn = 0, UMask = 0. The Remote Frame is ignored, this message
object remains unchanged.
3. Dir = 1 (direction = transmit), RmtEn = 0, UMask = 1. The Remote Frame is treated similar to areceived Data Frame. At the reception of a matching Remote Frame, the TxRqst bit of this message
object is reset. The arbitration and control bits (Identifier + IDE + RTR + DLC) from the shift registerare stored in the message object in the Message RAM and the NewDat bit of this message object isset. The data bytes of the message object remain unchanged.
20.2.8.9 Reading Received Messages
The CPU may read a received message any time via the IFx Interface Registers, the data consistency isguaranteed by the Message Handler state machine.
Typically the CPU will write first 0x7F to bits [23:16] and then the number of the message object to bits
[7:0] of the Command Register. That combination will transfer the whole received message from the
Message RAM into the Interface Register set. Additionally, the bits NewDat and IntPnd are cleared in the
Message RAM (not in the Interface Register set). The values of these bits in the Message Control
Register always reflect the status before resetting the bits.
If the message object uses masks for acceptance filtering, the arbitration bits show which of the different
matching messages has been received.
804

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

The actual value of NewDat shows whether a new message has been received since last time when thismessage object was read. The actual value of MsgLst shows whether more than one message have been
received since the last time when this message object was read. MsgLst will not be automatically reset.
20.2.8.10

Requesting New Data for a Receive Object

By means of a Remote Frame, the CPU may request another CAN node to provide new data for a receive
object. Setting the TxRqst bit of a receive object will cause the transmission of a Remote Frame with thereceive object’s identifier. This Remote Frame triggers the other CAN node to start the transmission of thematching Data Frame. If the matching Data Frame is received before the Remote Frame could betransmitted, the TxRqst bit is automatically reset.
Setting the TxRqst bit without changing the contents of a message object requires the value 0x84 in bits
[23:16] of the Command Register.
20.2.8.11 Storing Received Messages in FIFO Buffers
Several message objects may be grouped to form one or more FIFO Buffers. Each FIFO Buffer configured
to store received messages with a particular (group of) Identifier(s). Arbitration and Mask Registers of the
FIFO Buffer’s message objects are identical. The EoB (End of Buffer) bits of all but the last of the FIFO
Buffer’s message objects are 0, in the last one the EoB bit is 1.
Received messages with identifiers matching to a FIFO Buffer are stored into a message object of thisFIFO Buffer, starting with the message object with the lowest message number.
When a message is stored into a message object of a FIFO Buffer the NewDat bit of this message object
is set. By setting NewDat while EoB is 0, the message object is locked for further write accesses by the
Message Handler until the CPU has cleared the NewDat bit.
Messages are stored into a FIFO Buffer until the last message object of this FIFO Buffer is reached. If
none of the preceding message objects is released by writing NewDat to 0, all further messages for thisFIFO Buffer will be written into the last message object of the FIFO Buffer (EoB = 1) and therefore
overwrite previous messages in this message object.
20.2.8.12

Reading from a FIFO Buffer

Several messages may be accumulated in a set of message objects that are concatenated to form a FIFO
Buffer before the application program is required (in order to avoid the loss of data) to empty the buffer.
A FIFO Buffer of length N will store N-1 plus the last received message since last time it was cleared.
A FIFO Buffer is cleared by reading and resetting the NewDat bits of all its message objects, starting at
the FIFO Object with the lowest message number. This should be done in a subroutine following theexample shown in Figure 20-11.
NOTE: All message objects of a FIFO buffer needs to be read and cleared before the next batch of
messages can be stored. Otherwise true FIFO functionality can not be guaranteed, since themessage objects of a partly read buffer will be re-filled according to the normal (descending)priority.

Reading from a FIFO Buffer message object and resetting its NewDat bit is handled the same way asreading from a single message object.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

805

Module Operation

www.ti.com

Figure 20-11. CPU Handling of a FIFO Buffer (Interrupt Driven)
START

Message interrupt

Read interrupt identifiercase interrupt identifier
else

0x80000x0000Status ChangeInterrupt Handling

END

IFx command register [31:16] = 0x007F
Message Number = interrupt identifier

Write Message Number to IF1/IF2 command register(Transfer message to IF1/IF2 registers,
clear NewDat and IntPnd)

Read IF1/IF2 message control

NewDat = 1

No

Yes
Read data from IF1/IF2 Data A,B

EoB = 1Yes

No
Next Message Number in this FIFO Buffer

806

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

20.2.9 CAN Message Transfer
Once the DCAN is initialized and the Init bit is reset to 0, the CAN Core synchronizes itself to the CAN bus
and is ready for message transfer as per the configured message objects.
The CPU may enable the interrupt lines (setting IE0 and IE1 to 1) at the same time when it clears Init and
CCE. The status interrupts EIE and SIE may be enabled simultaneously.
The CAN communication can be carried out in any of the following two modes:
1. Interrupt mode
2. Polling mode.
The Interrupt Register points to those message objects with IntPnd = 1. It is updated even if the interrupt
lines to the CPU are disabled (IE0 and IE1 are 0).
The CPU may poll all Message Object’s NewDat and TxRqst bits in parallel from the NewData X
Registers and the Transmission Request X Registers. Polling can be made easier if all Transmit Objects
are grouped at the low numbers, all Receive Objects are grouped at the high numbers.
Received messages are stored into their appropriate message objects if they pass acceptance filtering.
The whole message (including all arbitration bits, DLC and up to eight data bytes) is stored into themessage object. As a consequence, when the identifier mask is used, the arbitration bits that are masked
to “don’t care” may change in the message object when a received message is stored.
The CPU may read or write each message at any time via the Interface Registers, as the Message
Handler guarantees data consistency in case of concurrent accesses (for reconfiguration, see
Section 20.2.7.6)
If a permanent message object (arbitration and control bits set up during configuration and leaving
unchanged for multiple CAN transfers) exists for the message, it is possible to only update the data bytes.
If several transmit messages should be assigned to one message object, the whole message object has
to be configured before the transmission of this message is requested.
The transmission of multiple message objects may be requested at the same time. They are subsequently
transmitted, according to their internal priority.
Messages may be updated or set to not valid at any time, even if a requested transmission is still pending(for reconfiguration, see Section 20.2.7.7). However, the data bytes will be discarded if a message isupdated before a pending transmission has started.
Depending on the configuration of the message object, a transmission may be automatically requested by
the reception of a remote frame with a matching identifier.
20.2.9.1 Automatic Retransmission
According to the CAN Specification (ISO11898), the DCAN provides a mechanism to automaticallyretransmit frames that have lost arbitration or have been disturbed by errors during transmission. The
frame transmission service will not be confirmed to the user before the transmission is successfullycompleted.
By default, this automatic retransmission is enabled. It can be disabled by setting bit DAR (Disable
Automatic Retransmission) in CAN Control Register. Further details to this mode are provided in
Section 20.2.8.3.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

807

Module Operation

www.ti.com

20.2.9.2 Auto-Bus-On
Per default, after the DCAN has entered Bus-Off state, the CPU can start a Bus-Off-Recovery sequence
by resetting Init bit. If this is not done, the module will stay in Bus-Off state.
The DCAN provides an automatic Auto-Bus-On feature that is enabled by bit ABO in CAN Control
Register. If set, the DCAN will automatically start the Bus-Off-Recovery sequence. The sequence can bedelayed by a user-defined number of VCLK cycles that can be defined in Auto-Bus-On Time Register.
NOTE: If the DCAN goes Bus-Off due to massive occurrence of CAN bus errors, it stops all bus
activities and automatically sets the Init bit. Once the Init bit has been reset by the CPU or
due to the Auto-Bus-On feature, the device will wait for 129 occurrences of Bus Idle (equal to
129 × 11 consecutive recessive bits) before resuming normal operation. At the end of the
Bus-Off recovery sequence, the error counters will be reset.

20.2.10 Interrupt Functionality
Interrupts can be generated on two interrupt lines:
1. DCAN0INT line
2. DCAN1INT line
These lines can be enabled by setting the IE0 and IE1 bits, respectively, in the CAN Control Register.
The DCAN provides three groups of interrupt sources: Message Object Interrupts, Status ChangeInterrupts and Error Interrupts (see Figure 20-12 and Figure 20-13).
The source of an interrupt can be determined by the interrupt identifiers Int0ID / Int1ID in the Interrupt
Register (see Section 20.3.5). When no interrupt is pending, the register will hold the value zero.
Each interrupt line remains active until the dedicated field in the Interrupt Register DCAN INT (Int0ID /Int1ID) again reach zero (this means the cause of the interrupt is reset), or until IE0 / IE1 are reset.
The value 0x8000 in the Int0ID field indicates that an interrupt is pending because the CAN Core has
updated (not necessarily changed) the Error and Status Register (Error Interrupt or Status Interrupt). This
interrupt has the highest priority. The CPU can update (reset) the status bits WakeUpPnd, RxOk, TxOk
and LEC by reading the Error and Status Register DCAN ES, but a write access of the CPU will nevergenerate or reset an interrupt.
Values between 1 and the number of the last message object indicates that the source of the interrupt is
one of the message objects, Int0ID resp. Int1ID will point to the pending message interrupt with thehighest priority. The Message Object 1 has the highest priority, the last message object has the lowest
priority.
An interrupt service routine that reads the message that is the source of the interrupt, may read themessage and reset the message object’s IntPnd at the same time (ClrIntPnd bit in the IF1/IF2 Command
Register). When IntPnd is cleared, the Interrupt Register will point to the next message object with apending interrupt.
20.2.10.1 Message Object Interrupts
Message Object interrupts are generated by events from the message objects. They are controlled by theflags IntPND, TxIE and RxIE, that are described in Section 20.2.5.1.
Message Object interrupts can be routed to either DCAN0INT or DCAN1INT line, controlled by theInterrupt Multiplexer Register (see Section 20.3.18).

808

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

20.2.10.2 Status Change Interrupts
The events WakeUpPnd, RxOk, TxOk and LEC in Error and Status Register (DCAN ES) belong to the
Status Change Interrupts. The Status Change Interrupt group can be enabled by bit in CAN Control
Register.
If SIE is set, a Status Change Interrupt will be generated at each CAN frame, independent of bus errors orvalid CAN communication, and also independent of the Message RAM configuration.
Status Change interrupts can only be routed to interrupt line DCAN0INT that has to be enabled by setting
IE0 in the CAN Control Register.
NOTE: Reading the Error and Status Register will clear the WakeUpPnd flag. If in global powerdown mode, the WakeUpPnd flag is cleared by such a read access before the DCAN module
has been waken up by the system, the DCAN may re-assert the WakeUpPnd flag, and asecond interrupt may occur (additional information can be found in Section 20.2.11.2).

20.2.10.3 Error Interrupts
The events PER, BOff and EWarn (monitored in Error and Status Register, DCAN ES) belong to the Error
Interrupts. The Error Interrupt group can be enabled by setting bit EIE in CAN Control Register.
Error interrupts can only be routed to interrupt line DCAN0INT that has to be enabled by setting IE0 in the
CAN Control Register.
Figure 20-12. CAN Interrupt Topology 1
Status Change Interrupts

Message Object Interrupts

RX OK

Message
Object 1

LEC

Transmit OK

Receive OK
Transmit OK

Error and Status ChangeInterrupts are Routed to
DCAN0INT line

TX OK

Receive OK

Last
Message
ObjectSIE

WakeUpPnd

IE0

Message
ObjectInterrupt

DCAN0INTEIEBus Off
Error
Warning
ParityError

Error Interrupts

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

809

Module Operation

www.ti.com

Figure 20-13. CAN Interrupt Topology 2
Message Object Interrupts
IntPndMux(1)Message
Object 1

RxIE

Receive OK
Transmit OK

IE1

TxIE

DCAN1INT

Last
Message
ObjectIntPndMux(n)RxIEReceive OK
Transmit OK

Message Object Interrupts
can be Routed to
DCAN0INT or DCAN1INT Line
IE0

TxIE
DCAN0INT
To Status Interrupt

20.2.11 Global Power-Down Mode
The device architecture supports a centralized global power down control over the peripheral modules
through the Peripheral Central Resource (PCR) module (Additional information can be found in Platform
Architecture Specification).
20.2.11.1 Entering Global Power-Down Mode
The global power-down mode for the DCAN is requested by setting the appropriate peripheral power
down set bit (PSPWRDWNSETx) in the PCR module.
The DCAN then finishes all transmit requests of the message objects. When all requests are done, theDCAN waits until a bus idle state is recognized. Then it will automatically set the Init bit to indicate that the
global power-down mode has been entered.
20.2.11.2 Wakeup From Global Power-Down Mode
When the DCAN module is in global power-down mode, a CAN bus activity detection circuit exists, which
can be active, if enabled. If this circuit is active,on occurrence of a dominant CAN bus level, the DCAN will
set the WakeUpPnd bit in Error and Status Register (DCAN ES).
If Status Interrupts are enabled, also an interrupt will be generated. This interrupt could be used by theapplication to wakeup the DCAN. For this, the application needs to set the appropriate peripheral power
down clear bit (PSPWRDWNCLRx) in the PCR module, and to clear the Init bit in CAN Control Register.
After the Init bit has been cleared, the DCAN module waits until it detects 11 consecutive recessive bits on
the CAN_RX pin and then goes Bus-Active again.
NOTE: The CAN transceiver circuit has to stay active during CAN bus activity detection. The first
CAN message, which initiates the bus activity, cannot be received. This means that the firstmessage received in power-down mode is lost.

810

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

20.2.12 Local Power-Down Mode
Besides the centralized power down mechanism controlled by the PCR module (global power down, see
Section 20.2.15), the DCAN supports a local power-down mode that can be controlled within the DCAN
control registers.
20.2.12.1 Entering Local Power-Down Mode
The local power-down mode is requested by setting the PDR bit in CAN Control Register.
The DCAN then finishes all transmit requests of the message objects. When all requests are done, DCAN
waits until a bus idle state is recognized. Then it will automatically set the Init bit in CAN Control Registerto prevent any further CAN transfers, and it will also set the PDA bit in CAN Error and Status Register.
With setting the PDA bits, the DCAN module indicates that the local power-down mode has been entered.
During local power-down mode, the internal clocks of the DCAN module are turned off, but there is a
wake-up logic (see Section 20.2.12.2) that can be active, if enabled. Also the actual contents of the control
registers can be read back.
NOTE: In local low power mode, the application should not clear the Init bit while PDR is set. If there
are any messages in the Message RAM configured as to be transmitted and the application
resets the Init bit, these messages may be sent.

20.2.12.2 Wakeup From Local Power-Down Mode
There are two ways to wake up the DCAN from local power-down mode:
1. The application could wake up the DCAN module manually by clearing the PDR bit and then clearing
the Init bit in CAN Control Register.
2. Alternatively, a CAN bus activity detection circuit can be activated by setting the wake up on bus
activity bit (WUBA) in CAN Control Register. If this circuit is active, on occurrence of a dominant CAN
bus level, the DCAN will automatically start the wake up sequence. It will clear the PDR bit in CAN
Control Register and also clear the PDA bit in Error and Status Register. The WakeUpPnd bit in CAN
Error and Status Register will be set. If Status Interrupts are enabled, also an interrupt will be
generated. Finally the Init bit in CAN control register will be cleared.
After the Init bit has been cleared, the module waits until it detects 11 consecutive recessive bits on the
CAN_RX pin and then goes Bus-Active again.
NOTE: The CAN transceiver circuit has to stay active while CAN bus observation. The first CAN
message, which initiates the bus activity, cannot be received. This means that the firstmessage received in power-down and automatic wake-up mode, is lost.

Figure 20-14 shows a flow diagram about entering and leaving local power-down mode.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

811

Module Operation

www.ti.com

Figure 20-14. Local Power-Down Mode Flow Diagram

812

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

20.2.13 GIO Support
The CAN_RX and CAN_TX pins of each DCAN module can be used as general purpose IO pins, if CAN
functionality is not needed. This function is controlled by the CAN TX IO Control register (seeSection 20.3.30) and the CAN RX IO Control register (see Section 20.3.31).

20.2.14 Test Modes
The DCAN provides several test modes that are mainly intended for production tests or self test.
For all test modes, the Test bit in the CAN Control Register needs to be set to 1. This enables write
access to the Test Register.
NOTE: When using any of the Loop Back modes, it must be ensured by software that all message
transfers are finished before setting the Init bit to 1.

20.2.14.1 Silent Mode
The Silent Mode may be used to analyze the traffic on the CAN bus without affecting it by sending
dominant bits (for example, acknowledge bit, overload flag, active error flag). The DCAN is still able toreceive valid data frames and valid remote frames, but it will not send any dominant bits. However, these
are internally routed to the CAN Core.
Figure 20-15 shows the connection of signals CAN_TX and CAN_RX to the CAN Core in Silent Mode.
Silent Mode can be activated by setting the Silent bit in Test Register to 1.
In ISO 11898-1, the Silent Mode is called the Bus Monitoring Mode.
Figure 20-15. CAN Core in Silent Mode

CAN_TX CAN_RX

DCAN

=1

Tx

Rx

CAN Core

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

813

Module Operation

www.ti.com

20.2.14.2 Loop Back Mode
The Loop Back Mode is mainly intended for hardware self-test functions. In this mode, the CAN Core uses
internal feedback from Tx output to Rx input. Transmitted messages are treated as received messages,
and can be stored into message objects if they pass acceptance filtering. The actual value of the CAN_RX
input pin is disregarded by the CAN Core. Transmitted messages still can be monitored at the CAN_TX
pin.
In order to be independent from external stimulation, the CAN Core ignores acknowledge errors (recessive
bit sampled in the acknowledge slot of a data/remote frame) in Loop Back Mode.
Figure 20-16 shows the connection of signals CAN_TX and CAN_RX to the CAN Core in Loop Back
Mode.
Loop Back Mode can be activated by setting the LBack bit in Test Register to 1.
NOTE: In Loop Back mode, the signal path from CAN Core to Tx pin, the Tx pin itself, and the signal
path from Tx pin back to CAN Core are disregarded. For including these into the testing, seeExternal Loop Back mode (Section 20.2.14.3).

Figure 20-16. CAN Core in Loop Back Mode

CAN_TX CAN_RX

DCAN

Tx

Rx

CAN Core

814

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

20.2.14.3 External Loop Back Mode
The External Loop Back Mode is similar to the Loop Back Mode, however it includes the signal path fromCAN Core to Tx pin, the Tx pin itself, and the signal path from Tx pin back to CAN Core. When External
Loop Back Mode is selected, the input of the CAN core is connected to the input buffer of the Tx pin.
With this configuration, the Tx pin IO circuit can be tested.
External Loop Back Mode can be activated by setting the EXL bit in Test Register to 1.
Figure 20-17 shows the connection of signals CAN_TX and CAN_RX to the CAN Core in External Loop
Back Mode.
NOTE: When Loop Back Mode is active (LBack bit is set), the EXL bit will be ignored.

Figure 20-17. CAN Core in External Loop Back Mode

CAN_TXpin

CAN_RX
pin

DCAN

Rx

Tx

CAN Core

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

815

Module Operation

www.ti.com

20.2.14.4 Loop Back Combined with Silent Mode
It is also possible to combine Loop Back Mode and Silent Mode by setting the LBack and Silent bits at thesame time. This mode can be used for a “Hot Self-test”, that is, the DCAN hardware can be tested without
affecting the CAN network. In this mode, the CAN_RX pin is disconnected from the CAN Core and no
dominant bits will be sent on the CAN_TX pin.
Figure 20-18 shows the connection of the signals CAN_TX and CAN_RX to the CAN Core in case of the
combination of Loop Back Mode with Silent Mode.
Figure 20-18. CAN Core in Loop Back Combined with Silent Mode

CAN_TX CAN_RX

DCAN
=1

Tx

Rx

CAN Core

20.2.14.5 Software Control of CAN_TX Pin
Four output functions are available for the CAN transmit pin CAN_TX. Additionally to its default function(serial data output), the CAN_TX pin can drive constant dominant or recessive values, or it can drive the
CAN Sample Point signal to monitor the CAN Core’s bit timing.
Combined with the readable value of the CAN_RX pin, this can be used to check the physical layer of the
CAN bus.
The output mode of pin CAN_TX is selected by programming the Test Register Tx bits as described in
Section 20.3.6.
NOTE: The software control for pin CAN_TX interferes with CAN protocol functions. For CAN
message transfer or any of the test modes, Loop Back Mode, External Loop Back Mode, orSilent Mode, the CAN_TX pin should operate in its default functionality.

816

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Operation

www.ti.com

20.2.15 Parity Check Mechanism
The DCAN provides a parity check mechanism to ensure data integrity of Message RAM data. For eachword (32 bits) in Message RAM, one parity bit will be calculated. The formation of the different words isaccording to the Message RAM representation in RDA mode (see Section 20.2.5.4).
Parity information is stored in the Message RAM on write accesses and will be checked against the storedparity bit from Message RAM on read accesses.
The parity check functionality can be enabled or disabled by PMD bit field in CAN Control Register.
In case of disabled parity check, the parity bits in message RAM will be left unchanged on write access todata area and no check will be done on read access.
If parity checking is enabled, parity bits will be automatically generated and checked by the DCAN. The
parity bits could be read in Debug/Suspend mode (see Section 20.2.5.3) or in RDA mode (seeSection 20.2.5.4). However, direct write access to the parity bits is only possible in this two modes withparity check disabled.
A parity bit will be set, if the modulo-2-sum of the data bits is 1. This definition is equivalent to: The parity
bit will be set, if the number of 1 bits in the data is odd.
NOTE: Parity scheme can be changed via the System module DEV Parity Control Register1 on
device basis for all peri RAMs.

20.2.15.1 Behavior on Parity Error
On any read access to Message RAM (for example, during start of a CAN frame transmission), the parityof the message object will be checked. If a parity error is detected, the PER bit in Error and Status
Register will be set. If error interrupts are enabled, also an interrupt would be generated. In order to avoid
the transmission of invalid data over the CAN bus, the d bit of the message object will be reset.
The message object data can be read by the host CPU, independently of parity errors. Thus, theapplication has to ensure that the read data is valid, for example, by immediately checking the Parity Error
Code register on parity error interrupt.
NOTE: During RAM initialization, no parity check will be done.

20.2.15.2 Parity Testing
Testing the parity mechanism can be done by enabling the bit RDA (RamDirectAccess) and manually
writing the parity bits directly to the dedicated RAM locations. With this, data and parity bits could bechecked when reading directly from RAM.
NOTE: If parity check was disabled, the application has to ensure correct parity bit handling in orderto prevent parity errors later on when parity check is enabled.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

817

Module Operation

www.ti.com

20.2.16 Debug/Suspend Mode
When the CPU is halted during debug, all DCAN registers are visible and can be inspected and modified
by the CPU.
In addition, the Message RAM is directly memory-mapped as described in Table 20-3.
The CAN controller provides two options for entering the debug/suspend state. The options are controlled
by the IDS bit in the CAN Control Register (DCAN CTL). By default, when IDS is 0, the DCAN controller
completes any active transfers on the CAN bus and waits until the bus is idle before halting. When IDS is
1, the DCAN halts immediately as soon as the CPU is halted.
The InitDbg bit in DCAN CTL register indicates when the DCAN controller has actually entered the
debug/suspend state.
NOTE: During Debug/Suspend Mode, the Message RAM cannot be accessed via the IFx registersets.
Writing to control registers in debug/suspend mode may influence the CAN state machineand further message handling.

For debug support, the auto clear functionality of the following DCAN registers is disabled:• Error and Status Register (clear of status flags by read)• IF1/IF2 Command Registers

20.3 DCAN Control Registers
Table 20-6 lists the control registers of the DCAN. After hardware reset, the registers of the DCAN holdthe values shown in the register descriptions. The base address for the control registers is FFF7 DC00h
for DCAN1 and FFF7 DE00h for DCAN2.
Additionally, the Bus-Off state is reset and the CAN_TX pin is set to recessive (HIGH). The Init bit in the
CAN Control Register is set to enable the software initialization. The DCAN will not influence the CAN bus
until the CPU resets Init to 0.
Table 20-6. DCAN Control Registers
OffsetAcronym

Register Description

Section00h

DCAN CTLCAN Control Register

Section 20.3.1

04h

DCAN ES

Error and Status Register

Section 20.3.2

08h

DCAN ERRC

Error Counter Register

Section 20.3.3

0Ch

DCAN BTR

Bit Timing Register

Section 20.3.4

10h

DCAN INTInterrupt Register

Section 20.3.5

14h

DCAN TEST

Test Register

Section 20.3.6

1Ch

DCAN PERR

Parity Error Code Register

Section 20.3.7

20h

DCAN REL

Core Release Register

Section 20.3.880h

DCAN ABOTR

Auto-Bus-On Time Register

Section 20.3.984h

DCAN TXRQXTransmission Request X Register

Section 20.3.10

88h

DCAN TXRQ12

Transmission Request 12 Register

Section 20.3.11

8Ch

DCAN TXRQ34

Transmission Request 34 Register

Section 20.3.11

90h

DCAN TXRQ56

Transmission Request 56 Register

Section 20.3.11

94h

DCAN TXRQ78

Transmission Request 78 Register

Section 20.3.11

98h

DCAN NWDATXNew Data X Register

Section 20.3.12

9Ch

DCAN NWDAT12New Data 12 Register

Section 20.3.13

A0h

DCAN NWDAT34

New Data 34 Register

Section 20.3.13

A4h

DCAN NWDAT56

New Data 56 Register

Section 20.3.13

A8h

DCAN NWDAT78

New Data 78 Register

Section 20.3.13

ACh

DCAN INTPNDXInterrupt Pending X Register

Section 20.3.14

818 Controller Area Network (DCAN) Module

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

DCAN Control Registers

www.ti.com

Table 20-6. DCAN Control Registers (continued)
OffsetAcronym

Register Description

B0h

DCAN INTPND12Interrupt Pending 12 Register

Section 20.3.15

Section

B4h

DCAN INTPND34

Interrupt Pending 34 Register

Section 20.3.15

B8h

DCAN INTPND56

Interrupt Pending 56 Register

Section 20.3.15

BCh

DCAN INTPND78

Interrupt Pending 78 Register

Section 20.3.15

C0h

DCAN MSGVALX

Message Valid X Register

Section 20.3.16

C4h

DCAN MSGVAL12

Message Valid 12 Register

Section 20.3.17

C8h

DCAN MSGVAL34

Message Valid 34 Register

Section 20.3.17

CCh

DCAN MSGVAL56

Message Valid 56 Register

Section 20.3.17

D0h

DCAN MSGVAL78

Message Valid 78 Register

Section 20.3.17

D8h

DCAN INTMUX12Interrupt Multiplexer 12 Register

Section 20.3.18

DCh

DCAN INTMUX34

Interrupt Multiplexer 34 Register

Section 20.3.18

E0h

DCAN INTMUX56

Interrupt Multiplexer 56 Register

Section 20.3.18

E4h

DCAN INTMUX78

Interrupt Multiplexer 78 Register

Section 20.3.18

100h

DCAN IF1CMD

IF1 Command Register

Section 20.3.19

104h

DCAN IF1MSK

IF1 Mask Register

Section 20.3.20

108h

DCAN IF1ARB

IF1 Arbitration Register

Section 20.3.21

10Ch

DCAN IF1MCTL

IF1 Message Control Register

Section 20.3.22

110h

DCAN IF1DATA

IF1 Data A Register

Section 20.3.23

114h

DCAN IF1DATB

IF1 Data B Register

Section 20.3.23

120h

DCAN IF2CMD

IF2 Command Register

Section 20.3.19

124h

DCAN IF2MSK

IF2 Mask Register

Section 20.3.20

128h

DCAN IF2ARB

IF2 Arbitration Register

Section 20.3.21

12Ch

DCAN IF2MCTL

IF2 Message Control Register

Section 20.3.22

130h

DCAN IF2DATA

IF2 Data A Register

Section 20.3.23

134h

DCAN IF2DATB

IF2 Data B Register

Section 20.3.23

140h

DCAN IF3OBS

IF3 Observation Register

Section 20.3.24

144h

DCAN IF3MSK

IF3 Mask Register

Section 20.3.25

148h

DCAN IF3ARB

IF3 Arbitration Register

Section 20.3.26

14Ch

DCAN IF3MCTL

IF3 Message Control Register

Section 20.3.27

150h

DCAN IF3DATA

IF3 Data A Register

Section 20.3.28

154h

DCAN IF3DATB

IF3 Data B Register

Section 20.3.28

160h

DCAN IF3UPD12IF3 Update Enable 12 Register

Section 20.3.29

164h

DCAN IF3UPD34

IF3 Update Enable 34 Register

Section 20.3.29

168h

DCAN IF3UPD56

IF3 Update Enable 56 Register

Section 20.3.29

16Ch

DCAN IF3UPD78

IF3 Update Enable 78 Register

Section 20.3.29

1E0h

DCAN TIOCCAN TX IO Control Register

Section 20.3.30

1E4h

DCAN RIOCCAN RX IO Control Register

Section 20.3.31

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

819

DCAN Control Registers

www.ti.com

20.3.1 CAN Control Register (DCAN CTL)
Figure 20-19. CAN Control Register (DCAN CTL) [offset = 00]
31

26

23

22

21

R-0

R-0

R-0
13

25

24

Reserved

WUBA

PDR

R-0

R/W-0

R/W-0

20

19

18

17

16

IE1

InitDbg

R/W-0

R/W-0

R/W-0

R/W-0

R-0

Reserved

15

14

9

8

SWR

Reserved

PMD

10

ABO

IDS

R/WP-0R-0

R/W-5h

R/W-0

R/W-0

7

6

5

4

3

2

1

0

Test

CCE

DAR

Reserved

EIE

SIE

IE0

Init

R/W-0

R/W-0

R/W-0

R-0

R/W-0

R/W-0

R/W-0

R/W-1

LEGEND: R/W = Read/Write; R = Read only; WP = Write protected by Init bit; -n = value after reset

Table 20-7. CAN Control Register Field Descriptions
Bit

Field

31-26

Reserved

25

WUBA

Value
0

Description
These bits are always read as 0. Writes have no effect.
Automatic wake up on bus activity when in local power-down mode.

0

No detection of a dominant CAN bus level while in local power-down mode.

1

Detection of a dominant CAN bus level while in local power-down mode is enabled. On occurrenceof a dominant CAN bus level, the wake up sequence is started. (Additional information can befound in Section 20.2.12.)
Note: The CAN message, which Initiates the bus activity, cannot be received. This means that thefirst message received in power-down and automatic wake-up mode, will be lost.

24

PDR

Request for local low power-down mode.
0

No application request for local low power-down mode. If the application has cleared this bit while
DCAN in local power-down mode, also the Init bit has to be cleared.

1

Local power-down mode has been requested by application. The DCAN will acknowledge the local
power-down mode by setting bit PDA in Error and Status Register. The local clocks will be turned
off by DCAN internal logic (Additional information can be found in Section 20.2.12).

23-21

Reserved

0

These bits are always read as 0. Writes have no effect.

20-18

Reserved

0

Reserved. Do not use.

17

16

15

IE1

Interrupt line 1 enable.
0

Disabled. Module Interrupt DCAN1INT is always low.

1

Enabled. Interrupts will assert line DCAN1INT to 1; line remains active until pending interrupts areprocessed.

InitDbg

Internal Init state while debug access.
0

Not in debug mode, or debug mode requested but is not entered.

1

Debug mode requested and is internally entered; the DCAN is ready for debug accesses.

SWR

SW Reset enable.
0

Normal operation.

1

Module is forced to reset state. This bit will automatically get cleared after execution of SW reset
after one VBUSP clock cycle.
Note: To execute SW reset the following procedure is necessary:
1.
2.

14

820

Reserved

0

Set Init bit to shut down CAN communication.
Set SWR bit additionally to Init bit.

This bit is always read as 0. Writes have no effect.

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

Table 20-7. CAN Control Register Field Descriptions (continued)
Bit

Field

13-10

PMD

9

8

7

6

5

Parity function is enabled.
Auto-Bus-On enable.

0

The Auto-Bus-On feature is disabled.

1

The Auto-Bus-On feature is enabled.
Interruption Debug Support enable.

0

When Debug/Suspend mode is requested, DCAN will wait for a started transmission or reception to
be completed before entering Debug/Suspend mode.

1

When Debug/Suspend mode is requested, DCAN will interrupt any transmission or reception, andenter Debug/Suspend mode immediately.
Test Mode enable.

0

Normal operation

1

Test mode

CCE

Configuration Change Enable.
0

The CPU has no write access to the BTR config register.

1

The CPU has write access to the BTR config register (when Init bit is set).

DAR

EIE

0

Parity function is disabled.

Test

3

1

5h
OthersIDS

Reserved

Description
Parity enable.

ABO

4

2

Value

Disable Automatic Retransmission.
0

Automatic Retransmission of not successful messages is enabled.

1

Automatic Retransmission is disabled.

0This bit is always read as 0. Writes have no effect.
Error Interrupt Enable.

0

Disabled. PER, BOff, and EWarn bits cannot generate an interrupt.

1

Enabled. PER, BOff, and EWarn bits can generate an interrupt at DCAN0INT line and affect theInterrupt Register.

SIE

Status Change Interrupt Enable.
0

Disabled. WakeUpPnd, RxOk, TxOk, and LEC bits cannot generate an interrupt.

1

Enabled. WakeUpPnd, RxOk, TxOk, and LEC can generate an interrupt at DCAN0INT line andaffect the Interrupt Register.

IE0

Interrupt line 0 enable.
0

Disabled. Module Interrupt DCAN0INT is always low.

1

Enabled. Interrupts will assert line DCAN0INT to 1; line remains active until pending interrupts areprocessed.

Init

Initialization.
0

Normal operation.

1

Initialization mode is entered.

NOTE: The Bus-Off recovery sequence (see CAN specification) cannot be shortened by setting or
resetting Init bit. If the module goes Bus-Off, it will automatically set the Init bit and stop all
bus activities.
When the Init bit is cleared by the application again, the module will then wait for 129
occurrences of Bus Idle (129 × 11 consecutive recessive bits) before resuming normal
operation. At the end of the Bus-Off recovery sequence, the error counters will be reset.
After the Init bit is reset, each time when a sequence of 11 recessive bits is monitored, a Bit0
error code is written to the Error and Status Register, enabling the CPU to check whether the
CAN bus is stuck at dominant or continuously disturbed, and to monitor the proceeding of the
Bus-Off recovery sequence.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

821

DCAN Control Registers

www.ti.com

20.3.2 Error and Status Register (DCAN ES)
Figure 20-20. Error and Status Register (DCAN ES) [offset = 04h]
31

16
Reserved
R-0
15

11

10

9

Reserved

PDA

WakeUpPnd

PER

R-0

R-0

R/C-0

R/C-0

7

6

5

4

3

BOff

EWarn

EPass

RxOK

TxOK

2
LEC

R-0

R-0

R-0

R/C-0

R/C-0

R/S-7h80

LEGEND: R = Read only; C = Clear; S = Set; -n = value after reset

Table 20-8. Error and Status Register Field Descriptions
Bit

Field

31-11

Reserved

10

9

Value
0

PDA

Description
These bits are always read as 0. Writes have no effect.
Local power-down mode acknowledge.

0

DCAN is not in local power-down mode.

1

Application request for setting DCAN to local power-down mode was successful. DCAN is in local
power-down mode.

WakeUpPnd

Wake Up Pending
This bit can be used by the CPU to identify the DCAN as the source to wake up the system.

8

7

6

5

4

3

822

0

No Wake Up is requested by DCAN.

1

DCAN has initiated a wake up of the system due to dominant CAN bus while module power down.
This bit will be reset if Error and Status Register is read.

PER

Parity Error Detected0

No parity error has been detected since last read access.

1

The parity check mechanism has detected a parity error in the Message RAM. This bit will be reset
if Error and Status Register is read.

BOff

Bus-Off State0

The CAN module is not Bus-Off state.

1

The CAN module is in Bus-Off state.

EWarn

Warning State
0

Both error counters are below the error warning limit of 96.

1

At least one of the error counters has reached the error warning limit of 96.

EPass

Error Passive State0

On CAN Bus error, the DCAN could send active error frames.

1

The CAN Core is in the error passive state as defined in the CAN Specification.

RxOK

Received a message successfully.
0

No message has been successfully received since the last time when this bit was read by the CPU.
This bit is never reset by DCAN internal events.

1

A message has been successfully received since the last time when this bit was reset by a readaccess of the CPU (independent of the result of acceptance filtering).This bit will be reset if Error
and Status Register is read.

TxOKTransmitted a message successfully.
0

No message has been successfully transmitted since the last time when this bit was read by theCPU. This bit is never reset by DCAN internal events.

1

A message has been successfully transmitted (error free and acknowledged by at least one othernode) since the last time when this bit was reset by a read access of the CPU. This bit will be reset
if Error and Status Register is read.

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

Table 20-8. Error and Status Register Field Descriptions (continued)
Bit

Field

2-0

LEC

Value

Description
Last Error CodeThe LEC field indicates the type of the last error on the CAN bus. This field will be cleared to 0
when a message has been transferred (reception or transmission) without error.

0

No Error

1h

Stuff Error: More than five equal bits in a row have been detected in a part of a received message
where this is not allowed.

2h

Form Error: A fixed format part of a received frame has the wrong format.

3h

Ack Error: The message this CAN Core transmitted was not acknowledged by another node.

4h

Bit1 Error: During the transmission of a message (with the exception of the arbitration field), thedevice wanted to send a recessive level (bit of logical value 1), but the monitored bus value wasdominant.

5h

Bit0 Error: During the transmission of a message (or acknowledge bit, or active error flag, oroverload flag), the device wanted to send a dominant level (logical value 0), but the monitored bus
level was recessive. During Bus-Off recovery, this status is set each time a sequence of 11
recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus-Off
recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).

6h

CRC Error: In a received message, the CRC check sum was incorrect. (CRC received for an
incoming message does not match the calculated CRC for the received data).

7h

No CAN bus event was detected since the last time when CPU has read the Error and Status
Register. Any read access to the Error and Status Register re-Initializes the LEC to value 7h.

Interrupts are generated by bits PER, BOff, and EWarn (if EIE bit in CAN Control Register is set) and bybits WakeUpPnd, RxOk, TxOk, and LEC (if SIE bit in CAN Control Register is set). A change of bit EPass
will not generate an Interrupt.
NOTE: Reading the Error and Status Register clears the WakeUpPnd, PER, RxOk, and TxOk bits
and sets the LEC to value 7h. Additionally, the Status Interrupt value (8000h) in the Interrupt
Register will be replaced by the next lower priority interrupt value.
For debug support, the auto clear functionality of Error and Status Register (clear of status
flags by read) is disabled when in Debug/Suspend mode.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

823

DCAN Control Registers

www.ti.com

20.3.3 Error Counter Register (DCAN ERRC)
Figure 20-21. Error Counter Register (DCAN ERRC) [offset = 08h]
31

16
Reserved
R-0

15

14

8

7

0

RP

REC

TEC

R-0

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 20-9. Error Counter Register Field Descriptions
Bit

Field

31-16

Reserved

15

Value
0

RP

Description
These bits are always read as 0. Writes have no effect.
Receive Error Passive0

The Receive Error Counter is below the error passive level.

1

The Receive Error Counter has reached the error passive level as defined in the CAN Specification.

14-8

REC

0-7Fh

Receive Error Counter. Actual state of the Receive Error Counter.

7-0

TEC

0-FFh

Transmit Error Counter. Actual state of the Transmit Error Counter.

824

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

20.3.4 Bit Timing Register (DCAN BTR)
Figure 20-22. Bit Timing Register (DCAN BTR) [offset = 0Ch]
31

15

20

14

12

19

16

Reserved

BRPE

R-0

R/WP-0

11

8

7

6

5

0

Rsvd

TSeg2

TSeg1

SJW

BRP

R-0

R/WP-2h

R/WP-3h

R/WP-0R/WP-1h

LEGEND: R/W = Read/Write; R = Read only; WP = Write Protected by CCE bit; -n = value after reset

Table 20-10. Bit Timing Register Field Descriptions
Bit

Field

31-20

Reserved
BRPE

Value
0
0-Fh

Description
These bits are always read as 0. Writes have no effect.
Baud Rate Prescaler Extension.
Valid programmed values are 0 to 15. By programming BRPE the Baud Rate Prescaler can beextended to values up to 1024.

15

Reserved

0

14-12

TSeg2

0-7h

This bit is always read as 0. Writes have no effect.
Time segment after the sample point.
Valid programmed values are 0 to 7. The actual TSeg2 value that is interpreted for the Bit Timing
will be the programmed TSeg2 value + 1.

11-8

TSeg1

1h-Fh

Time segment before the sample point.
Valid programmed values are 1 to 15. The actual TSeg1 value interpreted for the Bit Timing will be
the programmed TSeg1 value + 1.

7-6

SJW

0-3h

Synchronization Jump Width
Valid programmed values are 0 to 3.The actual SJW value interpreted for the Synchronization willbe the programmed SJW value + 1.

5-0

BRP

0-3Fh

Baud Rate Prescaler
Value by which the CAN_CLK frequency is divided for generating the bit time quanta. The bit timeis built up from a multiple of this quanta. Valid programmed values are 0 to 63.The actual BRP
value interpreted for the Bit Timing will be the programmed BRP value + 1.

NOTE: This register is only writable if CCE and Init bits in the CAN Control Register are set.
The CAN bit time may be programmed in the range of 8 to 25 time quanta.
The CAN time quantum may be programmed in the range of 1 to 1024 CAN_CLK periods.

With a CAN_CLK of 8 MHz and BRPE = 00, the reset value of 2301h configures the DCAN for a bit rate of
500kBit/s.
For details, see Section 20.2.3.2.1.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

825

DCAN Control Registers

www.ti.com

20.3.5 Interrupt Register (DCAN INT)
Figure 20-23. Interrupt Register (DCAN INT) [offset = 10h]
31

24

23

16

Reserved

Int1ID

R-0

R-0

15

0
Int0ID
R-0

LEGEND: R = Read only; -n = value after reset

Table 20-11. Interrupt Register Field Descriptions
Bit

Field

31-24

Reserved

23-16

Int1ID

Value
0

Description
These bits are always read as 0. Writes have no effect.
Interrupt 1 Identifier (indicates the message object with the highest-pending interrupt).

0

No interrupt is pending.

1h-10hNumber of message object that caused the interrupt for DCAN2.

1h-20hNumber of message object that caused the interrupt for DCAN1.

11h-FFh

Reserved for DCAN2.

21h-FFh

Reserved for DCAN1.
If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt
with the highest priority. The DCAN1INT interrupt line remains active until Int1ID reaches
value 0 (the cause of the interrupt is reset) or until IE1 is cleared.
A message interrupt is cleared by clearing the message object's IntPnd bit.
Among the message interrupts, the message object's interrupt priority decreases withincreasing message number.

15-0

Int0IDInterrupt Identifier (the number here indicates the source of the interrupt).
0

No interrupt is pending.

1h-10hNumber of message object that caused the interrupt for DCAN2.

1h-20hNumber of message object that caused the interrupt for DCAN1.

11h-7FFFh

Reserved for DCAN2.

21h-7FFFh

Reserved for DCAN1.

8000h
8001h-FFFFh

Error and Status Register value is not 0x07.
Reserved
If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt
with the highest priority. The DCAN0INT interrupt line remains active until Int0ID reaches
value 0 (the cause of the interrupt is reset) or until IE0 is cleared.
The Status Interrupt has the highest priority. Among the message interrupts, the message
object's interrupt priority decreases with increasing message number.

826

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

20.3.6 Test Register (DCAN TEST)
Figure 20-24. Test Register (DCAN TEST) [offset = 14h]31

16Reserved
R-0
15

10

7

6

9

8

Reserved

RDA

EXL

R-0

R/WP-0R/WP-0

4

3

Rx

Tx

5

LBack

Silent2
Reserved

0R-U

R/WP-0R/WP-0R/WP-0

R-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write Protected by Test bit; -n = value after reset; U = Undefined

Table 20-12. Test Register Field Descriptions
Bit

Field

31-10

Reserved

9

8

7

6-5

4

3

2-0

Value
0

RDA

These bits are always read as 0. Writes have no effect.
RAM Direct Access Enable0

Normal operation

1

Direct access to the RAM is enabled while in Test Mode.

EXL

External Loop Back Mode Enable0

Disabled

1

EnabledRx

Receive Pin. Monitors the actual value of the CAN_RX pin.
0

The CAN bus is dominant.

1

The CAN bus is recessive.

Tx

Control of CAN_TX pin
0

Normal operation, CAN_TX is controlled by the CAN Core.

1h

Sample Point can be monitored at CAN_TX pin.

2h

CAN_TX pin drives a dominant value.

3h

CAN_TX pin drives a recessive value.

LBack

Loop Back Mode Enable0

Disabled

1

EnabledSilentReserved

Description

Silent Mode Enable0

Disabled

1

Enabled0

These bits are always read as 0. Writes have no effect.

For all test modes, the Test bit in CAN Control Register needs to be set to 1. If Test bit is set, the RDA,
EXL, Tx1, Tx0, LBack, and Silent bits are writable. Bit Rx monitors the state of pin CAN_RX and therefore
is only readable. All Test Register functions are disabled when the Test bit is cleared to 0.
NOTE: The Test Register is only writable if Test bit in CAN Control Register is set.
Setting Tx[1:0] other than 00 will disturb message transfer.
When the internal loop back mode is active (LBack bit is set), the EXL bit will be ignored.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

827

DCAN Control Registers

www.ti.com

20.3.7 Parity Error Code Register (DCAN PERR)
Figure 20-25. Parity Error Code Register (DCAN PERR) [offset = 1Ch]
31

16
Reserved
R-0

15

14

11

10

8

7

0

Reserved

Word Number

Message Number

R-0

R-U

R-U

LEGEND: R = Read only; U = Undefined; -n = value after reset

Table 20-13. Parity Error Code Register Field Descriptions
Bit

Field

31-11

Reserved

10-8

Word Number

Value
0

Message Number

These bits are always read as 0. Writes have no effect.
Word number where parity error has been detected.

1h-5h
7-0

Description

RDA word number (1 to 5) of the message object (according to the Message RAM representation in
RDA mode, see Section 20.2.5.4).

1h-FFh Message object number where parity error has been detected. For DCAN1, only values 1h-20h arevalid; values 21h-FFh are invalid. For DCAN2, only values 1h-10h are valid; values 11h-FFh areinvalid.

If a parity error is detected, the PER flag will be set in the Error and Status Register. This bit is not resetby the parity check mechanism; it must be reset by reading the Error and Status Register.
In addition to the PER flag, the Parity Error Code Register will indicate the memory area where the parity
error has been detected (message number and word number).
If more than one word with a parity error was detected, the highest word number with a parity error will be
displayed.
After a parity error has been detected, the register will hold the last error code until power is removed.

20.3.8 Core Release Register (DCAN REL)
Figure 20-26. Core Release Register (DCAN REL) [offset = 20h]
31

28

27

24

23

20

19

16

REL

STEP

SUBSTEP

YEAR

R-Ah

R-3h

R-1h

R-7h

15

8

7

0

MON

DAY

R-5h

R-4h

LEGEND: R = Read only; -n = value after reset

Table 20-14. Core Release Register (DCAN REL) Field Descriptions
Bit

Field

Value

Description

31-28

REL

0-9h

Core Release. One digit, BCD-coded.

27-24

STEP

0-9h

Step of Core Release. One digit, BCD-coded.

23-20

SUBSTEP

0-9h

Substep of Core Release. One digit, BCD-coded.

19-16

YEAR

0-9h

Design Time Stamp, Year. One digit, BCD-coded. This field is set by constant parameter on DCAN
synthesis.

15-8

MON

0-12h

Design Time Stamp, Month. Two digits, BCD-coded. This field is set by constant parameter on
DCAN synthesis.

7-0

DAY

0-31h

Design Time Stamp, Day. Two digits, BCD-coded. This field is set by constant parameter on DCAN
synthesis.

828

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

20.3.9 Auto-Bus-On Time Register (DCAN ABOTR)
Figure 20-27. Auto-Bus-On Time Register (DCAN ABOTR) [offset = 80h]
31

16
ABO_TIME
R/W-0

15

0
ABO_TIME
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 20-15. Auto-Bus-On Time Register Field Descriptions
Bit

Field

Value

31-0

ABO_TIME

Description

0-FFFF FFFFh

Number of VBUS clock cycles before a Bus-Off recovery sequence is started byclearing the Init bit. This function has to be enabled by setting the ABO bit in the
CAN Control Register.
The Auto-Bus-On timer is realized by a 32-bit counter that starts to count down to
0 when the module goes Bus-Off.
The counter will be reloaded with the preload value of the ABO_TIME register
after this phase.

NOTE: On write access to the CAN Control register while Auto-Bus-On timer is running, the AutoBus-On procedure will be aborted.
During Debug/Suspend mode, running Auto-Bus-On timer will be paused.

20.3.10 Transmission Request X Register (DCAN TXRQ X)
With the Transmission Request X Register, the CPU can detect if one or more bits in the different
Transmission Request Registers are set. Each register bit represents a group of eight message objects. If
at least one of the TxRqst bits of these message objects are set, the corresponding bit in theTransmission Request X Register will be set.
Figure 20-28. Transmission Request X Register (DCAN TXRQ X) [offset = 84h]
31

16
Reserved
R-0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TxRqstReg8

TxRqstReg7

TxRqstReg6

TxRqstReg5

TxRqstReg4

TxRqstReg3

TxRqstReg2

TxRqstReg1

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Example 1
Bit 0 of the Transmission Request X Register represents byte 0 of the Transmission Request 1 Register. If
one or more bits in this byte are set, bit 0 of the Transmission Request X Register will be set.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

829

DCAN Control Registers

www.ti.com

20.3.11 Transmission Request Registers (DCAN TXRQ12 to DCAN TXRQ78)
These registers hold the TxRqst bits of the implemented message objects. By reading out these bits, theCPU can check for pending transmission requests. The TxRqst bit in a specific message object can be
set/reset by the CPU via the IF1/IF2 Message Interface Registers, or by the Message Handler after
reception of a remote frame or after a successful transmission.
Figure 20-29. Transmission Request 12 Register [offset = 88h]
310
TxRqst[32:1]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 20-30. Transmission Request 34 Register [offset = 8Ch]
31

0
TxRqst[64:33]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 20-31. Transmission Request 56 Register [offset = 90h]
310
TxRqst[96:65]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 20-32. Transmission Request 78 Register [offset = 94h]
31

0
TxRqst[128:97]
R-0

LEGEND: R = Read only; -n = value after reset

Table 20-16. Transmission Request Registers Field Descriptions
Bit

Name

31-0

TxRqs[128:1]

830

Value

Description
Transmission Request Bits (for all message objects).

0

No transmission has been requested for this message object.

1

The transmission of this message object is requested and is not yet done.

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

20.3.12 New Data X Register (DCAN NWDAT X)
With the New Data X Register, the CPU can detect if one or more bits in the different New Data Registers
are set. Each register bit represents a group of eight message objects. If at least on of the NewDat bits ofthese message objects are set, the corresponding bit in the New Data X Register will be set.
Figure 20-33. New Data X Register (DCAN NWDAT X) [offset = 98h]
31

16
Reserved
R-0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

NewDatReg8

NewDatReg7

NewDatReg6

NewDatReg5

NewDatReg4

NewDatReg3

NewDatReg2

NewDatReg1

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Equation 1
Bit 0 of the New Data X Register represents byte 0 of the New Data 1 Register. If one or more bits in thisbyte are set, bit 0 of the New Data X Register will be set.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

831

DCAN Control Registers

www.ti.com

20.3.13 New Data Registers (DCAN NWDAT12 to DCAN NWDAT78)
These registers hold the NewDat bits of the implemented message objects. By reading out these bits, theCPU can check for new data in the message objects. The NewDat bit of a specific message object can be
set/reset by the CPU via the IF1/IF2 Interface Register sets, or by the Message Handler after reception ofa data frame or after a successful transmission.
Figure 20-34. New Data 12 Register [offset = 9Ch]
31

0
NewDat[32:1]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 20-35. New Data 34 Register [offset = A0h]
31

0
NewDat[64:33]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 20-36. New Data 56 Register [offset = A4h]
31

0
NewDat[96:65]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 20-37. New Data 78 Register [offset = A8h]
31

0
NewDat[128:97]
R-0

LEGEND: R = Read only; -n = value after reset

Table 20-17. New Data Registers Field Descriptions
Bit

Name

31-0

NewDat[128:1]

832

Value

Description
New Data Bits (for all message objects).

0

No new data has been written into the data portion of this message object by the Message Handler
since the last time when this flag was cleared by the CPU.

1

The Message Handler or the CPU has written new data into the data portion of this message
object.

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

20.3.14 Interrupt Pending X Register (DCAN INTPND X)
With the Interrupt Pending X Register, the CPU can detect if one or more bits in the different Interrupt
Pending Registers are set. Each bit of this register represents a group of eight message objects. If at least
one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X
Register will be set.
Figure 20-38. Interrupt Pending X Register (DCAN INTPND X) [offset = ACh]31

16
Reserved
R-0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

IntPndReg8

IntPndReg7

IntPndReg6

IntPndReg5

IntPndReg4

IntPndReg3

IntPndReg2

IntPndReg1

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Example 2
Bit 0 of the Interrupt Pending X Register represents byte 0 of the Interrupt Pending 1 Register. If one ormore bits in this byte are set, bit 0 of the Interrupt Pending X Register will be set.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

833

DCAN Control Registers

www.ti.com

20.3.15 Interrupt Pending Registers (DCAN INTPND12 to DCAN INTPND78)
These registers hold the IntPnd bits of the implemented message objects. By reading out these bits, theCPU can check for pending interrupts in the message objects. The IntPnd bit of a specific message object
can be set/reset by the CPU via the IF1/IF2 Interface Register sets, or by the Message Handler after a
reception or a successful transmission.
Figure 20-39. Interrupt Pending 12 Register [offset = B0h]
310
IntPnd[32:1]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 20-40. Interrupt Pending 34 Register [offset = B4h]
310
IntPnd[64:33]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 20-41. Interrupt Pending 56 Register [offset = B8h]
310
IntPnd[96:65]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 20-42. Interrupt Pending 78 Register [offset = BCh]
31

0
IntPnd[128:97]
R-0

LEGEND: R = Read only; -n = value after reset

Table 20-18. Interrupt Pending Registers Field Descriptions
Bit

Name

31-0

IntPnd[128:1]

834

Value

Description
Interrupt Pending Bits (for all message objects).

0This message object is not the source of an interrupt.

1This message object is the source of an interrupt.

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

20.3.16 Message Valid X Register (DCAN MSGVAL X)
With the Message Valid X Register, the CPU can detect if one or more bits in the different Message Valid
Registers are set. Each bit of this register represents a group of eight message objects. If at least one of
the MsgVal bits of these message objects are set, the corresponding bit in the Message Valid X Register
will be set.
Figure 20-43. Message Valid X Register (DCAN MSGVAL X) [offset = C0h]31

16
Reserved
R-0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MsgValReg8

MsgValReg7

MsgValReg6

MsgValReg5

MsgValReg4

MsgValReg3

MsgValReg2

MsgValReg1

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Example 3
Bit 0 of the Message Valid X Register represents byte 0 of the Message Valid 1 Register. If one or more
bits in this byte are set, bit 0 of the Message Valid X Register will be set.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

835

DCAN Control Registers

www.ti.com

20.3.17 Message Valid Registers (DCAN MSGVAL12 to DCAN MSGVAL78)
These registers hold the MsgVal bits of the implemented message objects. By reading out these bits, theCPU can check which message objects are valid. The MsgVal bit of a specific message object can be
set/reset by the CPU via the IF1/IF2 Interface Register sets, or by the Message Handler after a reception
or a successful transmission.
Figure 20-44. Message Valid 12 Register [offset = C4h]
310
MsgVal[32:1]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 20-45. Message Valid 34 Register [offset = C8h]
310
MsgVal[64:33]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 20-46. Message Valid 56 Register [offset = CCh]310
MsgVal[96:65]
R-0

LEGEND: R = Read only; -n = value after reset

Figure 20-47. Message Valid 78 Register [offset = D0h]
310
MsgVal[128:97]
R-0

LEGEND: R = Read only; -n = value after reset

Table 20-19. Message Valid Registers Field Descriptions
Bit

Name

31-0

MsgVal[128:1]

836

Value

Description
Message Valid Bits (for all message objects).

0This message object is ignored by the Message Handler.

1This message object is configured and will be considered by the Message Handler.

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

20.3.18 Interrupt Multiplexer Registers (DCAN INTMUX12 to DCAN INTMUX78)
The IntMux flag determines for each message object which of the two interrupt lines (DCAN0INT or
DCAN1INT) will be asserted when the IntPnd of this message object is set. Both interrupt lines can be
globally enabled or disabled by setting or clearing IE0 and IE1 bits in CAN Control Register.
The IntPnd bit of a specific message object can be set or reset by the CPU via the IF1/IF2 Interface
Register sets, or by Message Handler after reception or successful transmission of a frame. This will also
affect the Int0ID resp Int1ID flags in the Interrupt Register.
Figure 20-48. Interrupt Multiplexer 12 Register [offset = D8h]
31

0
IntMux[32:1]
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Figure 20-49. Interrupt Multiplexer 34 Register [offset = DCh]
31

0
IntMux[64:33]
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Figure 20-50. Interrupt Multiplexer 56 Register [offset = E0h]
31

0
IntMux[96:65]
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Figure 20-51. Interrupt Multiplexer 78 Register [offset = E4h]
31

0
IntMux[128:97]
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 20-20. Interrupt Multiplexer Registers Field Descriptions
Bit

Name

31-0

IntMux[128:1]

Value

SPNU517C – March 2018
Submit Documentation Feedback

Description
Multiplexes IntPnd value to either DCAN0INT or DCAN1INT interrupt lines. The mapping from thebits to the message objects is as follows:
Bit 0 -> last implemented message object.
Bit 1 -> message object number 1.
Bit 2 -> message object number 2.

0

DCAN0INT line is active if corresponding IntPnd flag is 1.

1

DCAN1INT line is active if corresponding IntPnd flag is 1.

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

837

DCAN Control Registers

www.ti.com

20.3.19 IF1/IF2 Command Registers (DCAN IF1CMD, DCAN IF2CMD)
The IF1/IF2 Command Register configure and Initiate the transfer between the IF1/IF2 Register sets andthe Message RAM. It is configurable which portions of the message object should be transferred.
A transfer is started when the CPU writes the message number to bits [7:0] of the IF1/IF2 Command
Register. With this write operation, the Busy bit is automatically set to 1 to indicate that a transfer is inprogress.
After 4 to 14 VBUS clock cycles, the transfer between the Interface Register and the Message RAM will
be completed and the Busy bit is cleared. The maximum number of cycles is needed when the message
transfer concurs with a CAN message transmission, acceptance filtering, or message storage.
If the CPU writes to both IF1/IF2 Command Registers consecutively (request of a second transfer while
first transfer is still in progress), the second transfer will start after the first one has been completed.
NOTE: While the Busy bit is 1, IF1/IF2 Register sets are write protected.
If an invalid Message Number is written to bits [7:0] of the IF1/IF2 Command Register, theMessage Handler may access an implemented (valid) message object instead.

Figure 20-52. IF1 Command Registers (DCAN IF1CMD) [offset = 100h]31

24
Reserved
R-0

23

22

21

20

19

18

17

16

WR_RD

Mask

Arb

Control

ClrIntPnd

TxRqst/NewDat

DataA

DataB

R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0

13

15

14

Busy

Reserved

Reserved

8

R-0

R/WP/C-0

R-0

70
Message Number
R/WP-1h

LEGEND: R/W = Read/Write; R = Read; WP = Protected Write (protected by Busy bit); C = Clear by IF1 Access; -n = value after reset

Figure 20-53. IF1 Command Registers (CAN IF2CMD) [offset = 120h]
31

24
Reserved
R-0

23

22

21

20

19

18

17

16

WR_RD

Mask

Arb

Control

ClrIntPnd

TxRqst/NewDat

DataA

DataB

R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0

13

15

14

Busy

Reserved

Reserved

8

R-0

R/WP/C-0

R-0

70
Message Number
R/WP-1h

LEGEND: R/W = Read/Write; R = Read; WP = Protected Write (protected by Busy bit); C = Clear by IF1 Access; -n = value after reset

838

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

Table 20-21. IF1/IF2 Command Register Field Descriptions
Bit

Field

31-24

Reserved

23

WR_RD

22

Value
0

Description
These bits are always read as 0. Writes have no effect.
Write/Read0

Direction = Read: Transfer direction is from the message object addressed by Message
Number (Bits [7:0]) to the IF1/IF2 register set.

1

Direction = Write: Transfer direction is from the IF1/IF2 register set to the message object
addressed by Message Number (Bits [7:0]).

Mask

Access Mask bits0

Mask bits will not be changed.

1

Direction = Read: The Mask bits (Identifier Mask + MDir + MXtd) will be transferred from themessage object addressed by Message Number (Bits [7:0]) to the IF1/IF2 Register set.
Direction = Write: The Mask bits (Identifier Mask + MDir + MXtd) will be transferred from theIF1/IF2 Register set to the message object addressed by Message Number (Bits [7:0]).

21

Arb

Access Arbitration bits
0

Arbitration bits will not be changed.

1

Direction = Read: The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred fromthe message object addressed by Message Number (Bits [7:0]) to the corresponding IF1/IF2
Register set.
Direction = Write: The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred fromthe IF1/IF2 Register set to the message object addressed by Message Number (Bits [7:0]).

20

Control

Access Control bits0

Control bits will not be changed.

1

Direction = Read: The Message Control bits will be transferred from the message object
addressed by Message Number (Bits [7:0]) to the corresponding IF1/IF2 Register set.
Direction = Write: The Message Control bits will be transferred from the IF1/IF2 Register set tothe message object addressed by Message Number (Bits [7:0]).
If the TxRqst/NewDat bit in this register (Bit [18]) is set, the TxRqst/NewDat bit in the IF1/IF2
Message Control Register will be ignored.

19

ClrIntPnd

Clear Interrupt Pending bit
0

IntPnd bit will not be changed.

1

Direction = Read: Clears IntPnd bit in the message object.
Direction = Write: This bit is ignored. Copying of IntPnd flag from IF1/IF2 Registers to Message
RAM can be controlled by only the Control flag (Bit [20]).

18

TxRqst/NewDat

Access Transmission Request bit0

Direction = Read: NewDat bit will not be changed.
Direction = Write: TxRqst/NewDat bit will be handled according to the Control bit.

1

Direction = Read: Clears NewDat bit in the message object.
Direction = Write: Sets TxRqst/NewDat in the message object.
Note: If a CAN transmission is requested by setting TxRqst/NewDat in this register, theTxRqst/NewDat bits in the message object will be set to 1 and independent of the values in
IF1/IF2 Message Control Register.
A read access to a message object can be combined with the reset of the control bits IntPnd
and NewDat. The values of these bits transferred to the IF1/IF2 Message Control Register
always reflect the status before resetting them.

17

DataA

Access Data Bytes 0-30Data Bytes 0-3 will not be changed.

1

Direction = Read: The Data Bytes 0-3 will be transferred from the message object addressed by
the Message Number (Bits [7:0]) to the corresponding IF1/IF2 Register set.
Direction = Write: The Data Bytes 0-3 will be transferred from the IF1/IF2 Register set to themessage object addressed by the Message Number (Bits [7:0]).
Note: The duration of the message transfer is independent of the number of bytes to betransferred.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

839

DCAN Control Registers

www.ti.com

Table 20-21. IF1/IF2 Command Register Field Descriptions (continued)
Bit

Field

16

DataB

Value

Description
Access Data Bytes 4-70Data Bytes 4-7 will not be changed.

1

Direction = Read: The Data Bytes 4-7 will be transferred from the message object addressed by
the Message Number (Bits [7:0]) to the corresponding IF1/IF2 Register set.
Direction = Write: The Data Bytes 4-7 will be transferred from the IF1/IF2 Register set to themessage object addressed by the Message Number (Bits [7:0]).
Note: The duration of the message transfer is independent of the number of bytes to betransferred.

15

Busy

Busy flag
0

No transfer between IF1/IF2 Register set and Message RAM is in progress.

1

Transfer between IF1/IF2 Register set and Message RAM is in progress.
This bit is set to 1 after the message number has been written to bits [7:0]. IF1/IF2 Register set
will be write-protected. The bit is cleared after read/write action has finished.

14

Reserved

0

Reserved. Do not use.

13-8

Reserved

0

These bits are always read as 0. Writes have no effect.

7-0

Message Number

Number of message object in Message RAM that is used for data transfer.
0Invalid message number.

1h-10hValid message numbers for DCAN2.

1h-20hValid message numbers for DCAN1.

11h-FFh

Invalid message numbers for DCAN2.

21h-FFh

Invalid message numbers for DCAN1.
Note: When an invalid message number is written to the IF1/IF2 Command Register that ishigher than the last implemented message object number, a modulo addressing will occur. For
example, when accessing message object 33 in a DCAN module with 32 message objects only,
the message object 1 will be accessed instead.

840

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

20.3.20 IF1/IF2 Mask Registers (DCAN IF1MSK, DCAN IF2MSK)The bits of the IF1/IF2 Mask Registers mirror the mask bits of a message object. The function of therelevant message objects bits is described in Section 20.2.5.1.
NOTE: While the Busy bit in the IF1/IF2 Command Register is 1, IF1/IF2 Register Set is write
protected.

Figure 20-54. IF1 Mask Register (DCAN IF1MSK) [offset = 104h]
31

30

29

MXtd

MDir

Rsvd

28
Msk[28:16]

16

R/WP-1 R/WP-1

R-1

R/WP-1FFFh

15

0
Msk[15:0]
R/WP-FFFFh

LEGEND: R/W = Read/Write; R = Read; WP = Protected Write (protected by Busy bit); -n = value after reset

Figure 20-55. IF2 Mask Register (DCAN IF2MSK) [offset = 124h]
31

30

29

MXtd

MDir

Rsvd

28
Msk[28:16]

16

R/WP-1 R/WP-1

R-1

R/WP-1FFFh

15

0
Msk[15:0]
R/WP-FFFFh

LEGEND: R/W = Read/Write; R = Read; WP = Protected Write (protected by Busy bit); -n = value after reset

Table 20-22. IF1/IF2 Mask Register Field Descriptions
Bit

Field

31

MXtd

Value

Description
Mask Extended Identifier0

The extended identifier bit (IDE) has no effect on the acceptance filtering.

1

The extended identifier bit (IDE) is used for acceptance filtering.
When 11-bit ("standard") identifiers are used for a message object, the identifiers of received Data
Frames are written into bits ID[28:18]. For acceptance filtering, only these bits with mask bits
Msk[28:18] are considered.

30

MDir

29

Reserved28-0

Msk[28:0]

SPNU517C – March 2018
Submit Documentation Feedback

Mask Message Direction
0

The message direction bit (Dir) has no effect on the acceptance filtering.

1

The message direction bit (Dir) is used for acceptance filtering.

1

These bits are always read as 1. Writes have no effect.
Identifier Mask

0

The corresponding bit in the identifier of the message object is not used for acceptance filtering(don't care).

1

The corresponding bit in the identifier of the message object is used for acceptance filtering.

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

841

DCAN Control Registers

www.ti.com

20.3.21 IF1/IF2 Arbitration Registers (DCAN IF1ARB, DCAN IF2ARB)
The bits of the IF1/IF2 Arbitration Registers mirror the arbitration bits of a message object. The function of
the relevant message objects bits is described in Section 20.2.5.1.
NOTE: While the Busy bit in the IF1/IF2 Command Register is 1, IF1/IF2 Register Set is write
protected.

Figure 20-56. IF1 Arbitration Register (DCAN IF1ARB) [offset = 108h]
31

30

29

MsgVal

Xtd

Dir

28

16
ID[28:16]

R/WP-0 R/WP-0 R/WP-0

R/WP-015

0ID[15:0]
R/WP-0LEGEND: R/W = Read/Write; WP = Protected Write (protected by Busy bit); -n = value after reset

Figure 20-57. IF2 Arbitration Register (DCAN IF2ARB) [offset = 128h]
31

30

29

MsgVal

Xtd

Dir

28

16
ID[28:16]

R/WP-0 R/WP-0 R/WP-0

R/WP-015

0ID[15:0]
R/WP-0LEGEND: R/W = Read/Write; WP = Protected Write (protected by Busy bit); -n = value after reset

Table 20-23. IF1/IF2 Arbitration Register Field Descriptions
Bit

Field

31

MsgValValue

Description
Message Valid0

The message object is ignored by the Message Handler.

1

The message object is used by the Message Handler.
Note: The CPU should reset the MsgVal bit of all unused Messages Objects during theinitialization before it resets bit Init in the CAN Control Register. MsgVal must also be reset if
the messages object is no longer used in operation. For reconfiguration of message objects
during normal operation, see Section 20.2.7.6 and Section 20.2.7.7.

30

29

28-0

842

Xtd

Extended Identifier0

The 11-bit ("standard") identifier is used for this message object.

1

The 29-bit ("extended") identifier is used for this message object.

Dir

Message direction
0

Direction = Receive: On TxRqst, a Remote Frame with the identifier of this message object istransmitted. On receiving a Data Frame with a matching identifier, this message is stored in thismessage object.

1

Direction = Transmit: On TxRqst, the respective message object is transmitted as a Data
Frame. On receiving a Remote Frame with a matching identifier, the TxRqst bit of this message
object is set (if RmtEn = 1).

ID[28:0]

Message IdentifierID[28:0]29-bit Identifier ("Extended Frame")ID[28:18]

11-bit Identifier ("Standard Frame")

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

The Arbitration bits ID[28:0], Xtd, and Dir are used to define the identifier and type of outgoing messagesand (together with the Mask bits Msk[28:0], MXtd, and MDir) for acceptance filtering of incoming
messages.
A received message is stored into the valid message object with matching identifier and Direction =receive (Data Frame) or Direction = transmit (Remote Frame).
Extended frames can be stored only in message objects with Xtd = 1, standard frames in message objects
with Xtd = 0.
If a received message (Data Frame or Remote Frame) matches more than one valid message objects, it
is stored into the one with the lowest message number.

20.3.22 IF1/IF2 Message Control Registers (DCAN IF1MCTL, DCAN IF2MCTL)The bits of the IF1/IF2 Message Control Registers mirror the message control bits of a message object.
The function of the relevant message objects bits is described in Section 20.2.5.1.
NOTE: While the Busy bit in the IF1/IF2 Command Register is 1, IF1/IF2 Register Set is write
protected.

Figure 20-58. IF1 Message Control Register (DCAN IF1MCTL) [offset = 10Ch]
31

16
Reserved
R-0
15

14

13

12

11

10

9

8

NewDatMsgLstIntPnd

UMask

TxIE

RxIE

RmtEn

TxRqst

R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0

7

6

4

3

0

EoB

Reserved

DLC

R/WP-0R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read; WP = Protected Write (protected by Busy bit); -n = value after reset

Figure 20-59. IF2 Message Control Register (DCAN IF2MCTL) [offset = 12Ch]
31

16
Reserved
R-0
15

14

13

12

11

10

9

8

NewDatMsgLstIntPnd

UMask

TxIE

RxIE

RmtEn

TxRqst

R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0

7

6

4

3

0

EoB

Reserved

DLC

R/WP-0R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read; WP = Protected Write (protected by Busy bit); -n = value after reset

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

843

DCAN Control Registers

www.ti.com

Table 20-24. IF1/IF2 Message Control Register Field Descriptions
Bit

Field

31-16

Reserved

15

NewDat

14

13

12

Value
0

Description
These bits are always read as 0. Writes have no effect.
New Data0

No new data has been written into the data portion of this message object by the Message Handler
since the last time this flag was cleared by the CPU.

1

The Message Handler or the CPU has written new data into the data portion of this message
object.

MsgLstMessage Lost (only valid for message objects with direction = receive).
0

No message lost since the last time when this bit was reset by the CPU.

1

The Message Handler stored a new message into this object when NewDat was still set, so theprevious message has been overwritten.

IntPndInterrupt Pending0This message object is not the source of an interrupt.

1This message object is the source of an interrupt. The interrupt identifier in the interrupt register will
point to this message object if there is no other interrupt source with higher priority.

UMask

Use Acceptance Mask
0

Mask is ignored.

1

Use Mask (Msk[28:0], MXtd, and MDir) for acceptance filtering.
If the UMask bit is set to 1, the message object's mask bits have to be programmed duringinitialization of the message object before MsgVal is set to 1.

11

10

9

8

7

TxIE

Transmit Interrupt Enable
0

IntPnd will not be triggered after the successful transmission of a frame.

1

IntPnd will be triggered after the successful transmission of a frame.

RxIE

Receive Interrupt Enable
0

IntPnd will not be triggered after the successful reception of a frame.

1

IntPnd will be triggered after the successful reception of a frame.

RmtEn

Remote Enable0

At the reception of a Remote Frame, TxRqst is not changed.

1

At the reception of a Remote Frame, TxRqst is set.

TxRqstTransmit Request
0This message object is not waiting for a transmission.

1

The transmission of this message object is requested and not yet done.

EoB

End of Block0

The message object is part of a FIFO Buffer block and is not the last message object of this FIFO
Buffer block.

1

The message object is a single message object or the last message object in a FIFO Buffer block.
Note: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single
message objects (not belonging to a FIFO Buffer), this bit must always be set to 1.

6-4

Reserved

3-0

DLC

0

These bits are always read as 0. Writes have no effect.
Data Length Code

0-8

Data Frame has 0-8 data bytes.

9-15

Data Frame has 8 data bytes.
Note: The Data Length Code of a message object must be defined the same as in all thecorresponding objects with the same identifier at other nodes. When the message handler stores adata frame, it will write the DLC to the value given by the received message.

844

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

20.3.23 IF1/IF2 Data A and Data B Registers (DCAN IF1DATA/DATB, DCAN IF2DATA/DATB)The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order.
In a CAN Data Frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In
CAN's serial bit stream, the MSB of each byte will be transmitted first
Figure 20-60. IF1 Data A Register (DCAN IF1DATA) [offset = 110h]
31

24

23

16

Data 3

Data 2

R/WP-0R/WP-0

15

8

7

0

Data 1

Data 0R/WP-0R/WP-0LEGEND: R/W = Read/Write; WP = Protected Write (protected by Busy bit); -n = value after reset

Figure 20-61. IF1 Data B Register (DCAN IF1DATB) [offset = 114h]
31

24

23

16

Data 7

Data 6

R/WP-0R/WP-0

15

8

7

0

Data 5

Data 4

R/WP-0R/WP-0LEGEND: R/W = Read/Write; WP = Protected Write (protected by Busy bit); -n = value after reset

Figure 20-62. IF2 Data A Register (DCAN IF2DATA) [offset = 130h]
31

24

23

16

Data 3

Data 2

R/WP-0R/WP-0

15

8

7

0

Data 1

Data 0R/WP-0R/WP-0LEGEND: R/W = Read/Write; WP = Protected Write (protected by Busy bit); -n = value after reset

Figure 20-63. IF2 Data B Register (DCAN IF2DATB) [offset = 134h]
31

24

23

16

Data 7

Data 6

R/WP-0R/WP-0

15

8

7

0

Data 5

Data 4

R/WP-0R/WP-0LEGEND: R/W = Read/Write; WP = Protected Write (protected by Busy bit); -n = value after reset

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

845

DCAN Control Registers

www.ti.com

20.3.24 IF3 Observation Register (DCAN IF3OBS)
The IF3 register set can automatically be updated with received message objects without the need toInitiate the transfer from Message RAM by CPU (Additional information can be found in Section 20.2.5.1).
The observation flags (bits [4:0]) in the IF3 Observation register are used to determine which data sectionsof the IF3 Interface Register set have to be read. After all marked data sections are read, the DCAN isenabled to update the IF3 Interface Register set with new data.
Any access order of single bytes or half-words is supported. When using byte or half-word accesses, adata section is marked as completed, if all bytes are read.
NOTE: If IF3 Update Enable is used and no Observation flag is set, the corresponding message
objects will be copied to IF3.

A write access to this register enables updating of IF3 Interface Register set with new data.
The status of the current read-cycle can be observed via status flags (Bits [12:8]).
Since there is no IF3 interrupt line available in this device, no interrupt will be generated by the IF3Upd
flag.
With this, the observation status bits and the IF3Upd bit could be used by the application to realize thenotification about new IF3 content in polling mode.
Figure 20-64. IF3 Observation Register (DCAN IF3OBS) [offset = 140h]
31

16
Reserved
R-0
12

11

10

9

8

IF3Upd15

14
Reserved

13

IF3SDB

IF3SDA

IF3SC

IF3SA

IF3SM

R-0

R-0

R-0

R-0

R-0

R-0

R-0

7

4

3

2

1

0

Reserved

5

DataB

DataA

Ctrl

Arb

Mask

R-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 20-25. IF3 Observation Register Field Descriptions
Bit

Field

31-16

Reserved

15

IF3Upd14-13

Reserved

12

IF3SDB

11

10

846

Value
0

Description
These bits are always read as 0. Writes have no effect.
IF3 Update Data0

No new data has been loaded since IF3 was last read.

1

New data has been loaded since IF3 was last read.

0

These bits are always read as 0. Writes have no effect
IF3 Status of Data B read access.

0

All Data B bytes are already read or are not marked to be read.

1

Data B section still has data to read.

IF3SDA

IF3 Status of Data A read access.
0

All Data A bytes are already read or are not marked to be read.

1

Data A section still has data to read.

IF3SC

IF3 Status of Control bits read access.
0

All Control section bytes are already read or are not marked to be read.

1

Control section still has data to read.

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

Table 20-25. IF3 Observation Register Field Descriptions (continued)
Bit

Field

9

IF3SA

8

Reserved

4

DataB

2

1

0

0

All Arbitration data bytes are already read or are not marked to be read.

1

Arbitration section still has data to read.
IF3 Status of Mask data read access.

0

All Mask data bytes are already read or are not marked to be read.

1

Mask section still has data to read.

0

These bits are always read as 0. Writes have no effect
Data B read observation.

0

Data B section does not need to be read.

1

Data B section has to be read to enable next IF3 update.

DataA

Data A read observation.
0

Data A section does not need to be read.

1

Data A section has to be read to enable next IF3 update.

Ctrl

Ctrl read observation.
0

Ctrl section does not need to be read.

1

Ctrl section has to be read to enable next IF3 update.

Arb

Arbitration data read observation.
0

Arbitration data does not need to be read.

1

Arbitration data has to be read to enable next IF3 update.

Mask

SPNU517C – March 2018
Submit Documentation Feedback

Description
IF3 Status of Arbitration data read access.

IF3SM

7-5

3

Value

Mask data read observation.
0

Mask data does not need to be read.

1

Mask data has to be read to enable next IF3 update.

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

847

DCAN Control Registers

www.ti.com

20.3.25 IF3 Mask Register (DCAN IF3MSK)
Figure 20-65. IF3 Mask Register (DCAN IF3MSK) [offset = 144h]
31

30

29

28

MXtd

MDir

Rsvd

Msk[28:16]

16

R-1

R-1

R-1

R-1FFFh150
Msk[15:0]
R-FFFFhLEGEND: R = Read; -n = value after reset

Table 20-26. IF3 Mask Register Field Descriptions
Bit

Field

31

MXtd

Value

Description
Mask Extended Identifier0

The extended identifier bit (IDE) has no effect on acceptance filtering.

1

The extended identifier bit (IDE) is used for acceptance filtering.
Note: When 11-bit ("standard") identifiers are used for a message object, the identifiers of received
Data Frames are written into bits ID[28:18]. For acceptance filtering, only these bits, together withmask bits Msk[28:18], are considered.

30

MDir

29

Reserved28-0

Msk[28:0]

848

Mask Message Direction
0

The message direction bit (Dir) has no effect on acceptance filtering.

1

The message direction bit (Dir) is used for acceptance filtering.

1

This bit is always read as 1. Writes have no effect.
Identifier Mask

0

The corresponding bit in the identifier of the message object is not used for acceptance filtering(don't care).

1

The corresponding bit in the identifier of the message object is used for acceptance filtering.

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

20.3.26 IF3 Arbitration Register (DCAN IF3ARB)
Figure 20-66. IF3 Arbitration Register (DCAN IF3ARB) [offset = 148h]
31

30

29

MsgVal

Xtd

R-0

28
ID[28:16]

16

R-0

R-0

R-0

R-0

15

0
ID[15:0]
R-0

LEGEND: R = Read; -n = value after reset

Table 20-27. IF3 Arbitration Register Field Descriptions
Bit

Field

31

MsgValValue

Description
Message Valid0

The message object is ignored by the Message Handler.

1

The message object is to be used by the Message Handler.
Note: The CPU should reset the MsgVal bit of all unused Messages Objects during theinitialization before it resets bit Init in the CAN Control Register. MsgVal must also be reset if
the messages object is no longer used in operation. For reconfiguration of message objects
during normal operation, see Section 20.2.7.6 and Section 20.2.7.7.

30

29

28-0

Xtd

Extended Identifier0

The 11-bit ("standard") identifier is used for this message object.

1

The 29-bit ("extended") identifier is used for this message object.

Dir

Message direction
0

Direction = Receive: On TxRqst, a remote frame with the identifier of this message object istransmitted. On receiving a data frame with a matching identifier, the message is stored in thismessage object.

1

Direction = Transmit: On TxRqst, the respective message object is transmitted as a data frame.
On receiving a remote frame with a matching identifier, the TxRqst bit of this message object isset (if RmtEn = 1).

ID[28:0]

Message IdentifierID[28:0]29-bit Identifier ("Extended Frame")ID[28:18]

11-bit Identifier ("Standard Frame")

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

849

DCAN Control Registers

www.ti.com

20.3.27 IF3 Message Control Register (DCAN IF3MCTL)
Figure 20-67. IF3 Message Control Register (DCAN IF3MCTL) [offset = 14Ch]
31

16
Reserved
R-0
15

14

13

12

11

10

9

8

NewDatMsgLstIntPnd

UMask

TxIE

RxIE

RmtEn

TxRqst

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

7

6

4

3

0

EoB

Reserved

DLC

R-0

R-0

R-0

LEGEND: R = Read; -n = value after reset

Table 20-28. IF3 Message Control Register Field Descriptions
Bit

Field

31-16

Reserved

15

NewDat

14

13

12

Value
0

Description
These bits are always read as 0. Writes have no effect.
New Data0

No new data has been written into the data portion of this message object by the Message Handler
since the last time this flag was cleared by the CPU.

1

The Message Handler or the CPU has written new data into the data portion of this message
object.

MsgLstMessage Lost (only valid for message objects with direction = receive).
0

No message lost since the last time when this bit was reset by the CPU.

1

The Message Handler stored a new message into this object when NewDat was still set, so theprevious message has been overwritten.

IntPndInterrupt Pending0This message object is not the source of an interrupt.

1This message object is the source of an interrupt. The interrupt identifier in the interrupt register will
point to this message object if there is no other interrupt source with higher priority.

UMask

Use Acceptance Mask
0

Mask is ignored.

1

Use Mask (Msk[28:0], MXtd, and MDir) for acceptance filtering.
If the UMask bit is set to 1, the message object's mask bits have to be programmed duringinitialization of the message object before MsgVal is set to 1.

11

10

9

8

850

TxIE

Transmit Interrupt Enable
0

IntPnd will not be triggered after the successful transmission of a frame.

1

IntPnd will be triggered after the successful transmission of a frame.

RxIE

Receive Interrupt Enable
0

IntPnd will not be triggered after the successful transmission of a frame.

1

IntPnd will be triggered after the successful transmission of a frame.

RmtEn

Remote Enable0

At the reception of a Remote Frame, TxRqst is not changed.

1

At the reception of a Remote Frame, TxRqst is set.

TxRqstTransmit Request
0This message object is not waiting for a transmission.

1

The transmission of this message object is requested and not yet done.

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

Table 20-28. IF3 Message Control Register Field Descriptions (continued)
Bit

Field

7

EoB

Value

Description
End of Block0

The message object is part of a FIFO Buffer block and is not the last message object of the FIFO
Buffer block.

1

The message object is a single message object or the last message object in a FIFO Buffer block.
Note: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single
message objects (not belonging to a FIFO Buffer), this bit must always be set to 1.

6-4

Reserved

3-0

DLC

0

These bits are always read as 0. Writes have no effect.
Data Length Code

0-8

Data Frame has 0-8 data bytes.

9-15

Data Frame has 8 data bytes.
Note: The Data Length Code of a message object must be defined the same as in all thecorresponding objects with the same identifier at other nodes. When the message handler stores adata frame, it will write the DLC to the value given by the received message.

20.3.28 IF3 Data A and Data B Registers (DCAN IF3DATA/DATB)The data bytes of CAN messages are stored in the IF3 registers in the following order.
In a CAN Data Frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In
CAN's serial bit stream, the MSB of each byte will be transmitted first.
Figure 20-68. IF3 Data A Register (DCAN IF3DATA) [offset = 150h]
31

24

23

16

Data 3

Data 2

R-0

R-0

15

8

7

0

Data 1

Data 0

R-0

R-0

LEGEND: R = Read; -n = value after reset

Figure 20-69. IF3 Data B Register (DCAN IF3DATB) [offset = 154h]
31

24

23

16

Data 7

Data 6

R/WP-0R/WP-0

15

8

7

0

Data 5

Data 4

R-0

R-0

LEGEND: R = Read; -n = value after reset

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

851

DCAN Control Registers

www.ti.com

20.3.29 IF3 Update Enable Registers (DCAN IF3UPD12 to IF3UPD78)
The automatic update functionality of the IF3 register set can be configured for each message object. A
message object is enabled for automatic IF3 update, if the dedicated IF3UpdEn flag is set. This meansthat an active NewDat flag of this message object (for example, due to reception of a CAN frame) will
trigger an automatic copy of the whole message object to IF3 register set.
NOTE: IF3 Update enable should not be set for transmit objects.

Figure 20-70. IF3 Update Enable 12 Register [offset = 160h]
31

0IF3UpdEn[32:1]
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Figure 20-71. IF3 Update Enable 34 Register [offset = 164h]31

0IF3UpdEn[64:33]
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Figure 20-72. IF3 Update Enable 56 Register [offset = 168h]31

0IF3UpdEn[96:65]
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Figure 20-73. IF3 Update Enable 78 Register [offset = 16Ch]
31

0IF3UpdEn[128:97]
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 20-29. IF3 Update Control Register Field Descriptions
Bit

Name

31-0

IF3UpdEn[128:1]

852

Value

Description
IF3 Update Enabled (for all message objects).

0

Automatic IF3 update is disabled for this message object.

1

Automatic IF3 update is enabled for this message object. A message object is scheduled to becopied to IF3 register set, if NewDat flag of the message object is active.

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

20.3.30 CAN TX IO Control Register (DCAN TIOC)
The CAN_TX pin of the DCAN module can be used as general-purpose IO pin if CAN function is notneeded.
NOTE: The values of the IO Control registers are only writable if Init bit of CAN Control Register isset.
The OD, Func, Dir, and Out bits of the CAN TX IO Control register are forced to certain
values when Init bit of CAN Control Register is reset (see bit descriptions).

Figure 20-74. CAN TX IO Control Register (DCAN TIOC) [offset = 1E0h]
31

19

18

17

16

Reserved

PU

PD

OD

R-0

R/W-D

R/W-D

R/WP-0

15

4
Reserved
R-0

3

2

1

0

Func

Dir

Out

In

R/WP-0 R/WP-0 R/WP-0

R-U

LEGEND: R/W = Read/Write; R = Read; WP = Protected Write (protected by Init bit); D = Device-dependent; U = Undefined;-n = value after reset

Table 20-30. CAN TX IO Control Register Field Descriptions
Bit

Field

31-19

Reserved

18

17

16

Value
0

PU

Description
These bits are always read as 0. Writes have no effect.
CAN_TX Pullup/Pulldown select. This bit is only active when CAN_TX is configured to be an input.

0

CAN_TX Pulldown is selected, when pull logic is active (PD = 0).

1

CAN_TX Pullup is selected, when pull logic is active (PD = 0).

PD

CAN_TX pull disable. This bit is only active when CAN_TX is configured to be an input.
0

CAN_TX pull is active.

1

CAN_TX pull is disabled.

OD

CAN_TX open drain enable. This bit is only active when CAN_TX is configured to be in GIO mode
(TIOC.Func = 0).
0

The CAN_TX pin is configured in push/pull mode.

1

The CAN_TX pin is configured in open drain mode.
Forced to 0 if Init bit of CAN control register is reset.

15-4
3

Reserved

0

Func

These bits are always read as 0. Writes have no effect.
CAN_TX function. This bit changes the function of the CAN_TX pin.

0

CAN_TX pin is in GIO mode.

1

CAN_TX pin is in functional mode (as an output to transmit CAN data).
Forced to 1 if Init bit of CAN control register is reset.

2

Dir

CAN_TX data direction. This bit controls the direction of the CAN_TX pin when it is configured to be
in GIO mode only (TIOC.Func = 0).
0

The CAN_TX pin is an input.

1

The CAN_TX pin is an output.
Forced to 1 if Init bit of CAN control register is reset.

1

Out

CAN_TX data out write. This bit is only active when CAN_TX pin is configured to be in GIO mode
(TIOC.Func = 0) and configured to be an output pin (TIOC.Dir = 1). The value of this bit indicatesthe value to be output to the CAN_TX pin.
0

The CAN_TX pin is driven to logic low (0).

1

The CAN_TX pin is at logic high (1).
Forced to Tx output of the CAN Core, if Init bit of CAN Control register is reset.

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

853

DCAN Control Registers

www.ti.com

Table 20-30. CAN TX IO Control Register Field Descriptions (continued)
Bit

Field

0

In

Value

Description
CAN_TX data in.

0

The CAN_TX pin is at logic low (0).

1

The CAN_TX pin is at logic high (1).
Note: When CAN_TX pin is connected to a CAN transceiver, an external pullup resistor has to be
used to ensure that the CAN bus will not be disturbed (for example, while the DCAN module isreset).

20.3.31 CAN RX IO Control Register (DCAN RIOC)
The CAN_RX pin of the DCAN module can be used as general-purpose IO pin if CAN function is notneeded.
NOTE: The values of the IO Control registers are writable only if Init bit of CAN Control Register isset.
The OD, Func, and Dir bits of the CAN RX IO Control register are forced to certain values
when Init bit of CAN Control Register is reset, see bit description.

Figure 20-75. CAN RX IO Control Register (DCAN RIOC) [offset = 1E4h]
31

18

17

16

Reserved

19

PU

PD

OD

R-0

R/W-D

R/W-D

R/WP-0

15

4
Reserved
R-0

3

2

1

0

Func

Dir

Out

In

R/WP-0 R/WP-0 R/WP-0

R-U

LEGEND: R/W = Read/Write; R = Read; WP = Protected Write (protected by Init bit); D = Device-dependent; U = Undefined;-n = value after reset

Table 20-31. CAN RX IO Control Register Field Descriptions
Bit

Field

31-19

Reserved

18

17

16

Value
0

PU

Description
These bits are always read as 0. Writes have no effect.
CAN_RX Pullup/Pulldown select. This bit is only active when CAN_RX is configured to be an input.

0

CAN_RX Pulldown is selected, when pull logic is active (PD = 0).

1

CAN_RX Pullup is selected, when pull logic is active (PD = 0).

PD

CAN_RX pull disable. This bit is only active when CAN_RX is configured to be an input.
0

CAN_RX pull is active.

1

CAN_RX pull is disabled.

OD

CAN_RX open drain enable. This bit is only active when CAN_RX is configured to be in GIO mode
(RIOC.Func = 0).
0

The CAN_RX pin is configured in push/pull mode.

1

The CAN_RX pin is configured in open drain mode.
Forced to 0 if Init bit of CAN control register is reset.

15-4
3

Reserved

0

Func

These bits are always read as 0. Writes have no effect.
CAN_RX function. This bit changes the function of the CAN_RX pin.

0

CAN_RX pin is in GIO mode.

1

CAN_RX pin is in functional mode (as an input to receive CAN data).
Forced to 1 if Init bit of CAN control register is reset.

854

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

DCAN Control Registers

www.ti.com

Table 20-31. CAN RX IO Control Register Field Descriptions (continued)
Bit

Field

2

Dir

Value

Description
CAN_RX data direction. This bit controls the direction of the CAN_RX pin when it is configured to
be in GIO mode only (RIOC.Func = 0).

0

The CAN_RX pin is an input.

1

The CAN_RX pin is an output.
Forced to 0 if Init bit of CAN control register is reset.

1

0

Out

CAN_RX data out write. This bit is only active when CAN_RX pin is configured to be in GIO mode
(RIOC.Func = 0) and configured to be an output pin (RIOC.Dir = 1). The value of this bit indicatesthe value to be output to the CAN_RX pin.
0

The CAN_RX pin is driven to logic low (0).

1

The CAN_RX pin is at logic high (1).

In

CAN_RX data in.
0

The CAN_RX pin is at logic low (0).

1

The CAN_RX pin is at logic high (1).
Note: When CAN_RX pin is connected to a CAN transceiver, an external pullup resistor has to be
used to ensure that the CAN bus will not be disturbed (for example, while the DCAN module isreset).

SPNU517C – March 2018
Submit Documentation Feedback

Controller Area Network (DCAN) Module
Copyright © 2018, Texas Instruments Incorporated

855

Chapter 21
SPNU517C – March 2018

Multi-Buffered Serial Peripheral Interface Module (MibSPI)This chapter provides the specifications for a 16-bit configurable synchronous multi-buffered multi-pin
serial peripheral interface (MibSPI). The MibSPI is a programmable-length shift register used for highspeed communication between external peripherals or other microcontrollers.
Throughout this chapter, all references to SPI also apply to MibSPI unless otherwise noted.
Topic...........................................................................................................................

Page

21.1 Overview ......................................................................................................... 857
21.2 Operating Modes .............................................................................................. 858
21.3 Test Features ................................................................................................... 872
21.4 General-Purpose I/O.......................................................................................... 874
21.5 Low-Power Mode .............................................................................................. 874
21.6 Interrupts......................................................................................................... 875
21.7 Module Configuration........................................................................................ 877
21.8 Control Registers ............................................................................................. 879
21.9 Multi-Buffer RAM .............................................................................................. 938
21.10 Parity Memory................................................................................................. 945
21.11 MibSPI Pin Timing Parameters .......................................................................... 948

856

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackOverviewwww.ti.com

21.1 Overview
The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream ofprogrammed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display
drivers, and analog-to-digital converters.
The SPI has the following attributes:• 16-bit shift register• Receive buffer register• 11-bit baud clock generator• Serial clock (SPICLK) pin• SPI enable (SPIENA) pin• Up to 4 slave chip select (SPICS) pins
• SPICLK can be internally-generated (and driven) or received from an external clock source• Each word transferred can have a unique format• SPI pins can be used as functional or digital Input/Output pins (GIOs)
NOTE: SIMO - Slave In Master Out Pin
SOMI - Slave Out Master In Pin
SPICS - SPI Chip Select Pin
SPIENA - SPI Enable Pin.
This device contains one MibSPI (MibSPI1) and two SPIs (SPIP2 and SPI3). All threemodules support up to four SPICS, one SPICLK pins. MibSPI1 and SPI3 support one
SPIENA pin each. All of them support one SPISOMI/SPISIMO pair.

21.1.1 Word Format Options
Each word transferred can have a unique format. Several format characteristics are programmable foreach word transferred:• SPICLK frequency• Character length (2 to 16 bits)• Phase (with and without delay)• Polarity (high or low)
• Parity enabled/disabled• Chip Select (CS) timers for setup and hold• Shift direction (Most Significant Bit (MSB)- first or Least Significant Bit (LSB)- first)

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

857

Overviewwww.ti.com

21.1.2 Multi-buffering (Mib) Support
The MibSPI has a programmable buffer memory that enables programmed transmission to be completed
without CPU intervention. The buffers are combined in different Transfer Groups (TGs) that can betriggered by external events (timers, Input/Output activity, and so on) or by the internal tick counter. Theinternal tick counter supports periodic trigger events.
21.1.2.1 Multi-buffer Mode
Multi-buffer mode is an extension to the SPI. In multi-buffer mode, many extended features are
configurable:• Number of buffers for each peripheral (or data source/destination, up to 128 buffers supported) orgroup (up to 8 groupings)• Triggers for each groups trigger types and trigger sources for individual groups (14 external trigger
sources and 1 internal trigger source supported)• Memory fault detection via an internal parity circuit
21.1.2.2 Compatibility Mode
Compatibility mode of the MibSPI makes it behave exactly like a standard platform SPI module andensures full compatibility with other SPIs. All features in compatibility mode of the MibSPI are directly
applicable to a SPI. Multi-buffer mode features are not available in compatibility mode.
NOTE: The SPIDAT0 register is not accessible in the multi-buffer mode of MibSPI. It is only
accessible in compatibility mode.

21.1.3 Transmission Lock (Multi-Buffer Mode Master Only)
Some slave devices require transmission of a command followed by data. In this case the SPI transaction
should not be interrupted by another group transfer. The LOCK bit within each buffer allows a consecutive
transfer to happen without being interrupted by another higher-priority group transfer.

21.2 Operating Modes
The SPI can be configured via software to operate as either a master or a slave. The MASTER bit(SPIGCR1[0]) selects the configuration of the SPISIMO and SPISOMI pins. CLKMOD bit (SPIGCR1[1])determines whether an internal or external clock source will be used.
The slave chip select (SPICS) pins are used when communicating with multiple slave devices or, with asingle slave, to delimit messages containing a leading register address. When the a write occurs to
SPIDAT1 in master mode, the SPICS pins are automatically driven to select the specified slave.
Handshaking mechanism, provided by the SPIENA pin, enables a slave SPI to delay the generation of theclock signal supplied by the master if it is not prepared for the next exchange of data.

21.2.1 Pin Configurations
The SPI supports data connections as shown in Table 21-1.
NOTE:
1.
2.

858

When the SPICS signals are disabled, the chip select field in the transmit data is not
used.
When the SPIENA signal is disabled, the SPIENA pin is ignored in master mode, andnot driven as part of the SPI transaction in slave mode.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Operating Modes

www.ti.com

Table 21-1. Pin Configurations
Pin

Master Mode

Slave Mode

SPICLK

Drives the clock to external devices

Receives the clock from the external master

SPISOMI

Receives data from the external slave

Sends data to the external master

SPISIMO

Transmits data to the external slave

Receives data from the external master

SPIENASPIENA disabled:GIO

SPIENA enabled:
Receives ENA signal fromthe external slave

SPIENA disabled:GIO

SPIENA enabled:
Drives ENA signal from theexternal master

SPICS

SPICS disabled:GIO

SPICS enabled:
Selects one or more slave
devicesSPICS disabled:GIO

SPICS enabled:
Receives the CS signal fromthe external master21.2.2 Data Handling
Figure 21-1 shows the SPI transaction hardware. TXBUF and RXBUF are internal buffers that are
intended to improve the overall throughput of data transfer. TXBUF is a transmit buffer, while RXBUF is areceive buffer.
Figure 21-1. SPI Functional Logic Diagram
Peripheral Write

Peripheral ReadSPIBUFSPIDAT0/SPIDAT1RXOVRN

16

RXOVR INT INT_LVL
ENARX INT ENA

RXEMPTY
TXBUF

TX INT ENA

INT0
INT1

16

16 TXFULL
16

TX shift register

RXBUF

Clock phase

Clock polarity

CharlenPrescale

SPISOMISPISIMORX shift register

Kernel FSM

Modegeneration
logic

CLKMOD

SPI clock generation logic
Pin Directions in Slave Mode

Peripheral clock
1
2
3
4

SPICLK

This is a representative diagram, which shows three-pin mode hardware.
TXBUF, RXBUF, and SHIFT_REGISTER are user-invisible registers.
SPIDAT0 and SPIDAT1 are user-visible, and are physically mapped to the contents of TXBUF.
SPISIMO, SPISOMI, SPICLK pin directions depend on the Master or Slave Mode.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

859

Operating Modes

www.ti.com

21.2.2.1 Data Sequencing when SPIDAT0 or SPIDAT1 is Written• If both the TX shift register and TXBUF are empty, then the data is directly copied to the TX shift
register. If transmit interrupts are enabled, a transmitter-empty interrupt is generated.
• If the TX shift register is already full or is in the process of shifting and if TXBUF is empty, then thedata written to SPIDAT0 / SPIDAT1 is copied to TXBUF and TXFULL flag is set to 1 at the same time.
• When a shift operation is complete, data from the TXBUF (if it is full) is copied into TX shift registerand the TXFULL flag is cleared to 0 to indicate that next data can be fetched. A transmitter-empty
interrupt (if enabled) is generated at the same time.
21.2.2.2 Data Sequencing when All Bits Shifted into RXSHIFT Register• If both SPIBUF and RXBUF are empty, the received data in RX shift register is directly copied into
SPIBUF and the receive interrupt (if enabled) is generated. The RXEMPTY flag in SPIBUF is clearedat the same time.
• If SPIBUF is already full at the end of receive completion, the RX shift register contents is copied to
RXBUF. The receive complete interrupt line remains high.
• If SPIBUF is read by the CPU and if RXBUF is full, then the contents of RXBUF are copied to SPIBUF
as soon as SPIBUF is read. RXEMPTY flag remains cleared, indicating that SPIBUF is still full.
• If both SPIBUF and RXBUF are full, then RXBUF will be overwritten and the RXOVR interrupt flag is
set and an interrupt is generated, if enabled.

860

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Operating Modes

www.ti.com

21.2.2.3 Three-Pin Mode
In master mode configuration (MASTER = 1 and CLKMOD = 1), the SPI provides the serial clock on the
SPICLK pin. Data is transmitted on the SPISIMO pin and received on the SPISOMI pin (see Figure 21-2).
Data written to the shift register (SPIDAT0 / SPIDAT1) initiates data transmission on the SPISIMO pin,
MSB first. Simultaneously, received data is shifted through the SPISOMI pin into the LSB of the SPIDAT0
register. When the selected number of bits have been transmitted, the received data in the shift register istransferred to the SPIBUF register for the CPU to read. Data is stored right-justified in SPIBUF.
See Section 21.2.2.1 and Section 21.2.2.2 for details about the data handling for transmit and receive
operations.
In slave mode configuration (MASTER = 0 and CLKMOD = 0), data shifts out on the SPISOMI pin and inon the SPISIMO pin. The SPICLK pin is used as the input for the serial shift clock, which is supplied fromthe external network master. The transfer rate is defined by this clock.
Data written to the SPIDAT0 or SPIDAT1 register is transmitted to the network when the SPICLK signal isreceived from the network master. To receive data, the SPI waits for the network master to send the
SPICLK signal and then shifts data on the SPISIMO pin into the RX shift register. If data is to betransmitted by the slave simultaneously, it must be written to the SPIDAT0 or SPIDAT1register before thebeginning of the SPICLK signal.
Figure 21-2. SPI Three-Pin Operation
Master(Master = 1; CLKMOD = 1)

MSB

Slave
(Master = 0; CLKMOD = 0)

SPISIMOSPISIMOSPISOMILSBSPISOMIMSBSPIDAT0

SPICLKSPICLKLSBSPIDAT0

Write to SPIDAT0
Write to SPIDATSPICLKSPISIMOSPISOMISPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

861

Operating Modes

www.ti.com

21.2.3 Operation with SPICS
In master mode, each chip select signal is used to select a specific slave. In slave mode, the chip selectsignal is used to enable and disable the transfer. Chip-select functionality is enabled by setting one of the
SPICS pins as a chip select. It is disabled by setting all SPICS pins as GIOs in SPIPC0.
21.2.3.1 Multiple Chip Selects
The SPICS pins that are used must be configured as functional pins in the SPIPC0 register. The default
pattern to be put on the SPICS when all the slaves are deactivated is set in the SPIDEF register. Thispattern allows different slaves with different chip-select polarity to be activated by the SPI.
The master-mode SPI is capable of driving either 0 or 1 as the active value for any SPICS output pin. The
drive state for SPICS pins is controlled by the CSNR field of SPIDAT1. The pattern that is driven will
select the slave to which the transmission is dedicated.
In slave mode, the SPI can only be selected by an active value of 0 on any of its selected SPICS input
pins.
Figure 21-3. Operation with SPICS
MasterSlave(Master = 1; CLKMOD = 1)

(Master = 0; CLKMOD = 0)MSB

SPISIMOSPISIMOSPISOMILSBSPISOMIMSBSPIDAT1SPICLKSPICLK

SPICS

SPICS

Write to SPIDAT1LSBSPIDAT0

Write to SPIDAT1SPICS
SPICLKSPISIMOSPISOMI

862

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Operating Modes

www.ti.com

21.2.4 Operation with SPIENAThe SPIENA operates as a WAIT signal pin. For both the slave and the master, the SPIENA pin must be
configured to be functional (SPIPC0[8] = 1). In this mode, an active low signal from the slave on the
SPIENA pin allows the master SPI to drive the clock pulse stream. A high signal tells the master to holdthe clock signal (and delay SPI activity).
If the SPIENA pin is in high-impedance mode (ENABLE_HIGHZ = 1), the slave will put SPIENA into thehigh-impedance once it completes receiving a new character. If the SPIENA pin is in push-pull mode
(ENABLE_HIGHZ = 0), the slave will drive SPIENA to 1 once it completes receiving a new character. The
slave will drive SPIENA low again for the next word to transfer, after new data is written to the slave TX
shift register.
In master mode (CLKMOD = 1), if the SPIENA pin is configured as functional, then the pin will act as an
input pin. If configured as a slave SPI and as functional, the SPIENA pin acts as an output pin.
NOTE: During a transfer, if a slave-mode SPI detects a deassertion of its chip select before its
internal character length counter overflows, then it places SPISOMI and SPIENA (if
ENABLE_HIGHZ bit is set to 1) in high-z mode. Once this condition has occurred, if a
SPICLK edge is detected while the chip select is deasserted, then the SPI stops that transfer
and sets an DLENERR error flag and generates an interrupt (if enabled).

Figure 21-4. Operation with SPIENA
MasterSlave(Master = 1; CLKMOD = 1)

(Master = 0; CLKMOD = 0)MSB
SPIDAT0

SPISIMOSPISIMOSPISOMILSBSPISOMIMSBLSBSPICLKSPICLKSPIDAT0

Write to SPIDAT0 SPIENASPIENA

Write to SPIDAT0

Write to SPIDAT0 (SLAVE)
Write to SPIDAT0 (master)
SPIENASPICLKSPISIMOSPISOMISPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

863

Operating Modes

www.ti.com

21.2.5 Five-Pin Operation (Hardware Handshaking)Five-pin operation combines the functionality of three-pin mode, plus the enable pin and one or more chip
select pins. The result is full hardware handshaking. To use this mode, both the SPIENA pin and therequired number of SPICS pins must be configured as functional pins.
If the SPIENA pin is in high-impedance mode (ENABLE_HIGHZ = 1), the slave SPI will put this signal into
the high-impedance state by default. The slave will drive the signal SPIENA low when new data is written
to the slave shift register and the slave has been selected by the master (SPICS is low).
If the SPIENA pin is in push-pull mode (ENABLE_HIGHZ = 0), the slave SPI drives this pin high by default
when it is in functional mode. The slave SPI will drive the SPIENA signal low when new data is written to
the slave shift register (SPIDAT0/SPIDAT1) and the slave is selected by the master (SPICS is low). If theslave is deselected by the master (SPICS goes high), the slave SPIENA signal is driven high.
NOTE: Push-pull mode of the SPIENA pin can be used only when there is a single slave in thesystem. When multiple SPI slave devices are connected to the common SPIENA pin, all of
the slaves should configure their SPIENA pins in high-z mode.

In master mode, if the SPICS pins are configured as functional pins, then the pins will be in output mode.
A write to the master’s SPIDAT1/SPIDAT0 register will automatically drive the SPICS signals low. The
master will drive the SPICS signals high again after completing the transfer of the bits of the data.
In slave mode (CLKMOD = 0), the SPICS pins will act as SPI functional inputs.
Figure 21-5. SPI Five-Pin Option with SPIENA and SPICS
MasterSlave(Master = 1; CLKMOD = 1)

(Master = 0; CLKMOD = 0)MSB

SPISIMOSPISIMOSPISOMILSBSPISOMIMSBSPIDAT1SPICLKSPICLK

Write to SPIDAT1

SPICS

SPICS

SPIENASPIENALSBSPIDAT0
Write to SPIDAT0

Write to SPIDAT1 (MASTER)

SPICS
Write to SPIDAT0 (SLAVE)SPIENASPICLKSPISIMOSPISOMI

864

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Operating Modes

www.ti.com

21.2.6 Data Formats
To support multiple different types of slaves in one SPI network, four independent data word formats are
implemented that allow configuration of individual data word length, polarity, phase, and bit rate. Eachword transmitted can select which data format to use via the bits DFSEL[1:0] in its control field from one of
the four data word formats. Same data format can be supported on multiple chip selects.
Data formats 0, 1, 2, and 3 can be configured through SPIFMTx control registers.
Each SPI data format includes the standard SPI data format with enhanced features:• Individually-configurable shift direction can be used to select MSB first or LSB first, whereas the
position of the MSB depends on the configured data word length.
• Receive data is automatically right-aligned, independent of shift direction and data word length.
Transmit data has to be written right-aligned into the SPI and the internal shift register will transmit
according to the selected shift direction and data word length for correct transfer.
• To increase fault detection of data transmission and reception, an odd or even parity bit can be addedat the end of a data word. The parity generator can be enabled or disabled individually for each data
format. If a received parity bit does not match with the locally calculated parity bit, the parity error flag
(PARITYERR) is set and an interrupt is asserted (if enabled).
Since the master-mode SPI can drive two consecutive accesses to the same slave, an 8-bit delay counteris available to satisfy the delay time for data to be refreshed in the accessed slave. The delay counter canbe programmed as part of the data format.
CHARLEN[4:0] specifies the number of bits (2 to 16) in the data word. The CHARLEN[4:0] value directs
the state control logic to count the number of bits received or transmitted to determine when a complete
word is transferred.
Data word length must be programmed to the same length for both the master and the slave. However,when chip selects are used, there may be multiple targets with different lengths in the system.
NOTE: Data must be right-justified when it is written to the SPI for transmission irrespective of its
character length or word length.

Figure 21-6 shows how a 12-bit word (0xEC9) needs to be written to the transmit buffer to be transmitted
correctly.
Figure 21-6. Format for Transmitting an 12-Bit Word
D15
x

D14
x

D13
x

D12
x

D11
1

D10
1

D9
1

D8
0

D7
1

D6
1

D5
0

D4
0

D3
1

D2
0

D1
0

D0
1

D1
1

D0
0

NOTE: The received data is always stored right-justified regardless of the character length ordirection of shifting and is padded with leading 0s when the character length is less than 16
bits.

Figure 21-7 shows how a 10-bit word (0x0A2) is stored in the buffer once it is received.
Figure 21-7. Format for Receiving an 10-Bit Word
D15
0

D14
0

D13
0

D12
0

SPNU517C – March 2018
Submit Documentation Feedback

D11
0

D10
0

D9
0

D8
0

D7
1

D6
0

D5
1

D4
0

D3
0

D2
0

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

865

Operating Modes

www.ti.com

21.2.7 Clocking Modes
SPICLK may operate in four different modes, depending on the choice of phase (delay/no delay) and thepolarity (rising edge/falling edge) of the clock.
The data input and output edges depend on the values of both POLARITY and PHASE as shown in
Table 21-2.
Table 21-2. Clocking Modes
POLARITY

PHASE

0

0

ActionData is output on the rising edge of SPICLK. Input data is latched on the falling edge.

01

Data is output one half-cycle before the first rising edge of SPICLK and on subsequentfalling edges. Input data is latched on the rising edge of SPICLK.

10

Data is output on the falling edge of SPICLK. Input data is latched on the rising edge.

1

1

Data is output one half-cycle before the first falling edge of SPICLK and on
subsequent rising edges. Input data is latched on the falling edge of SPICLK.

Figure 21-8 to Figure 21-11 illustrate the four possible configurations of SPICLK corresponding to eachmode. Having four signal options allows the SPI to interface with many different types of serial devices.
Figure 21-8. Clock Mode with Polarity = 0 and Phase = 0
Write SPIDATSPICLK

1

2

3

4

5

6

7

8

SPISIMO

MSB

D6

D5

D4

D3

D2

D1

LSB

SPISOMI

D7

D6

D5

D4

D3

D2

D1

D0

receive sample

Data is output on the rising edge of SPICLK.
Input data is latched on the falling edge of SPICLK.

Figure 21-9. Clock Mode with Polarity = 0 and Phase = 1
Write SPIDATSPICLK

1

2

3

4

5

6

7

8

SPISIMO

MSB

D6

D5

D4

D3

D2

D1

LSB

SPISOMI

D7

D6

D5

D4

D3

D2

D1

D0

receive sample

Data is output one-half cycle before the first rising edge of SPICLK and on subsequent falling edges of SPICLK
Input data is latched on the rising edge of SPICLK

866

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Operating Modes

www.ti.com

Figure 21-10. Clock Mode with Polarity = 1 and Phase = 0
Write SPIDATSPICLK
1

2

3

4

5

6

7

8

SPISIMO

MSB

D6

D5

D4

D3

D2

D1

LSB

SPISOMI

D7

D6

D5

D4

D3

D2

D1

D0

receive sample
Data is output on the falling edge of SPICLK.
Input data is latched on the rising edge of SPICLK.

Figure 21-11. Clock Mode with Polarity = 1 and Phase = 1
Write SPIDATSPICLK
1

2

3

4

5

6

7

8

SPISIMO

MSB

D6

D5

D4

D3

D2

D1

LSB

SPISOMI

D7

D6

D5

D4

D3

D2

D1

D0

receive sample

Data is output one-half cycle before the first falling edge of SPICLK and on the subsequent rising edges of SPICLK.
Input data is latched on the falling edge of SPICLK.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

867

Operating Modes

www.ti.com

21.2.8 Data Transfer Example
Figure 21-12 illustrates a SPI data transfer between two devices using a character length of five bits.
Figure 21-12. Five Bits per Character (5-Pin Option)
SPICLK signal options:
Clock polarity = 0
Clock phase = 0

4

3

2

1

0

4

3

2

1

0

4

3

2

1

0

4

3

2

1

0

Clock polarity = 0
Clock phase = 1
Clock polarity = 1
Clock phase = 0
Clock polarity = 1
Clock phase = 1

SPICS

SPIENASPISOMI
from slave
SPISIMO
from master
Master SPI
Interrupt flag
Slave SPIInterrupt flag

868

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Operating Modes

www.ti.com

21.2.9 Decoded and Encoded Chip Select (Master Only)
In this device the SPI can connect to up to 4 individual slave devices using chip-selects by routing one
wire to each slave. The 4 chip selects in the control field are directly connected to the 4 pins. The default
value of each chip select (not active) can be configured via the register CSDEF. During a transmission,
the value of the chip select control field (CSNR) of the SPIDAT1 register (SPIDAT1) is driven on the
SPICS pins. When the transmission finishes the default chip-select value (defined by the CSDEF register)is put on the SPICS pins.
The SPI can support more than 4 slaves by using encoded chip selects. To connect the SPI with encodedslaves devices, the CSNR field allows multiple active SPICS pins at the same time, which enables
encoded chip selects from 0 to 16. To use encoded chip selects, all 4 chip select lines have to beconnected to each slave device and each slave needs to have a unique chip-select address. The CSDEF
register is used to provide the address at which slaves devices are all de-selected.
Users can combine decoded and encoded chip selects. For example, n SPICS pins can be used for
encoding a n-bit address and the remaining pins can be connected to decoded-mode slaves.

21.2.10 Variable Chip Select Setup and Hold Timing (Master Only)
In order to support slow slave devices a delay counter can be configured to delay data transmission after
the chip select is activated. A second delay counter can be configured to delay the chip select deactivation
after the last data bit is transferred. Both delay counters are clocked with peripheral clock (VCLK).
If a particular data format specifically does not require these additional set-up or hold times for the chip
select pin(s), then they can be disabled in the corresponding SPIFMTx register.

21.2.11 Hold Chip-Select Active
Some slave devices require the chip select signal to be held continuously active during several
consecutive data word transfers. Other slave devices require the chip select signal to be deactivatedbetween consecutive data word transfers.
CSHOLD is programmable in both master and slave modes of the multi-buffer mode of SPI. However, themeaning of CSHOLD in master mode and slave mode are different.
NOTE: If the CSHOLD bit is set within the current data control field, the programmed hold time andthe following programmed set-up time will not be applied between transactions.

21.2.11.1 The CSHOLD Bit in Master Mode
Each word in a master-mode SPI can be individually initialized for one of the two modes via the CSHOLD
bit in its control field.
If the CSHOLD bit is set in the control field of a word, the chip select signal will not be deactivated until thenext control field is loaded with new chip select information. Since the chip-select is maintained active
between two transfers, the chip-select hold delay (T2CDELAY) is not applied at the end of the current
transaction, and the chip-select set-up time delay (C2TDELAY) is not applied as well at the beginning of
the following transaction. However, the wait delay (WDELAY) will be still applied between the twotransactions, if the WDEL bit is set within the control field.
Figure 21-13 shows the SPI pins when a master-mode SPI transfers a word that has its CSHOLD bit set.
The chip-select pins will not be deasserted after the completion of this word. If the next word to transmit
has the same chip-select number (CSNR) value, the chip select pins will be maintained until thecompletion of the second word, regardless of whether the CSHOLD bit is set or not.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

869

Operating Modes

www.ti.com

Figure 21-13. Typical Diagram when a Buffer in Master is in CSHOLD Mode (SPI-SPI)WORD1
CSHOLD = 1

WORD2
CSHOLD = 0

Write to SPIDAT1

Write to SPIDAT1SPICS
SPICLKSPISIMO

Write to SPIDAT0 (SLAVE)

Write to SPIDAT0 (SLAVE)SPIENASPISOMI21.2.11.2 The CSHOLD Bit in Slave Mode (Multi-buffered Mode)
If the CSHOLD bit in a buffer is set to 1, then the MibSPI does not wait for the SPICS pins to be deactivated at the end of the shift operation to copy the received data to the receive RAM. With this feature,
it is possible for a slave in multi-buffer mode to do multiple data transfers without requiring the SPICS pins
to be deasserted between two buffer transfers.
If the CSHOLD bit in a buffer is cleared to 0 in a slave MibSPI, even after the shift operation is done, the
MibSPI waits until the SPICS pin (if functional) is deasserted to copy the received data to the RXRAM.
If the CSHOLD bit is maintained as 0 across all the buffers, then the slave in multi-buffer mode requires its
SPICS pins to be deasserted between any two buffer transfers; otherwise, the Slave SPI will be unable torespond to the next data transfer.
NOTE: In compatibility mode, the slave does not require the SPICS pin to be deasserted between
two buffer transfers. The CSHOLD bit of the slave will be ignored in compatibility mode.

870

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Operating Modes

www.ti.com

21.2.12 Detection of Slave Desynchronization (Master Only)
When a slave supports generation of an enable signal (ENA), desynchronization can be detected. With
the enable signal a slave indicates to the master that it is ready to exchange data. A desynchronization
can occur if one or more clock edges are missed by the slave. In this case the slave may block the SOMI
line until it detects clock edges corresponding to the next data word. This would corrupt the data word of
the desynchronized slave and the consecutive data word. A configurable 8-bit time-out counter(T2EDELAY), which is clocked with SPICLK, is implemented to detect this slave malfunction. After thetransmission has finished (end of last bit transferred: either last data bit or parity bit) the counter is started.
If the ENA signal generated by the slave does not become inactive before the counter overflows, the
DESYNC flag is set and an interrupt is asserted (if enabled).
NOTE: Inconsistency of Desynchronization Flag in Compatibility Mode MibSPI
Because of the nature of this error, under some circumstances it is possible for a desync
error detected for the previous buffer to be visible in the current buffer. This is due to the factthat receive completion flag/interrupt will be generated when the buffer transfer is completed.
But desync will be detected after the buffer transfer is completed. So, if VBUS master reads
the received data quickly when an RXINT is detected, then the status flag may not reflect thecorrect desync condition. This inconsistency in the desync flag is valid only in compatibility
mode of MibSPI. In multi-buffer mode, the desync flag is always assured to be for the current
buffer.

21.2.13 ENA Signal Time-Out (Master Only)
The SPI in master mode waits for the hardware handshake signal (ENA) coming from the addressed slave
before performing a data transfer. To avoid stalling the SPI by a non-responsive slave device, a time-out
value can be configured using C2EDELAY. If the time-out counter overflows before an active ENA signal
is sampled, the TIMEOUT flag in the status register SPIFLG is set and the TIMEOUT flag in the status
field of the corresponding buffer is set.
NOTE: When the chip select signal becomes active, no breaks in transmission are allowed. The
next arbitration is performed while waiting for the time-out to occur.

21.2.14 Data-Length Error
A SPI can generate an error flag by detecting any mismatch in length of received or transmitted data andthe programmed character length under certain conditions.
Data-Length Error in Master Mode: During a data transfer, if the SPI detects a de-assertion of the
SPIENA pin (by the slave) while the character counter is not overflowed, then an error flag is set toindicate a data-length error. This can be caused by a slave receiving extra clocks (for example, due tonoise on the SPICLK line).
NOTE: In a master mode SPI, the data length error will be generated only if the SPIENA pin isenabled as a functional pin.

Data-Length Error in Slave Mode: During a transfer, if the SPI detects a de-assertion of the SPICS pin
before its character length counter overflows, then an error flag is set to indicate a data-length error. Thissituation can arise If the slave SPI misses one or more SPICLK pulses from the master. This error in slave
mode implies that both the transmitted and received data were not complete.
NOTE: In a slave-mode SPI, the data-length error flag will be generated only if at least one of the
SPICS pins are configured as functional, and are being used for selecting the slave.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

871

Operating Modes

www.ti.com

21.2.15 Continuous Self-Test (Master/Slave)
During data transfer, the SPI compares its own internal transmit data with its transmit data on the bus. The
sample point for the compare is at one-half SPI clock after transmit point. If the data on the bus does notmatch the expected value, the bit-error (BITERR) flag is set and an interrupt is asserted if enabled.
NOTE: The compare is made from the output pin using its input buffer.

21.2.16 Half Duplex Mode
SPI by protocol is Full Duplex in nature, which means simultaneous TX and RX operations happen on two
separate data pins, SIMO and SOMI. However, it is possible to use SPI/MibSPI to do the TX-onlyoperation (ignoring the RX data) and the RX-only operation (using dummy TX data and ignoring the TX
pin). But this will require that both SOMI and SIMO lines are bonded out in a chip to be able to support
both TX-only or RX-only features.
21.2.16.1 Half Duplex Mode in Master
The Half Duplex Mode gives an additional flexibility to use the SIMO pin that is normally used TX pin in
Master mode to work like an RX pin while the HDUPLEX_ENAx bit is set to 1. In Half Duplex Mastermode, SIMO pin itself acts as an RX pin. Switching between Full Duplex and Half Duplex can be achieved
using the SPIFMTx registers being selected using the DFSEL[1:0] bits of SPIDATx or TXRAM locations.
21.2.16.2 Half Duplex Mode in Slave
In case of Slave mode, the SIMO pin which is normally an RX pin, will act as a TX pin while the
HDUPLEX_ENAx bit is set to 1. In Half Duplex Slave mode, SIMO pin itself acts as a TX pin. Switching
between Full Duplex and Half Duplex can be achieved using the SPIFMTx registers being selected using
the DFSEL[1:0] bits of SPIDATx or TXRAM locations.

21.3 Test Features
21.3.1 Internal Loop-Back Test Mode (Master Only)
The internal loop-back self-test mode can be utilized to test the SPI transmit and receive paths, including
the shift registers, the SPI buffer registers, and the parity generator. In this mode the transmit signal isinternally feedback to the receiver, whereas the SIMO, SOMI, and CLK pin are disconnected; that is, thetransmitted data is internally transferred to the corresponding receive buffer while external signals remainunchanged.
This mode allows the CPU to write into the transmit buffer, and check that the receive buffer contains thecorrect transmit data. If an error occurs the corresponding error is set within the status field.
NOTE: This mode cannot be changed during transmission.

872

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackTest Features

www.ti.com

21.3.2 Input/Output Loopback Test Mode
Input/Output Loopback Test mode supports the testing of all Input/Output pins without the aid of an
external interface. Loopback can be configured as either analog-loopback (loopback through the pin-level
input/output buffers) or digital loopback (internal to the SPI module). With Input/Output Loopback, allfunctional features of the SPI can be tested. Transmit data is fed back through the receive-data line(s).
See Figure 21-14 for a diagram of the types of feedback available. The IOLPBKTSTCR register defines allof the available control fields.
In loopback mode, it is also possible to induce various error conditions. See Section 21.8.39 for details of
the register field controlling these features.
In Input/Output loopback test modes, even when the module is in slave mode, the SPICLK is generated
internally. This SPICLK is used for all loopback-mode SPI transactions. Slave-mode features can betested without the help of another master SPI, using the internally-generated SPICLK. Chip selects arealso generated by the slave itself while it is in Input/Output loopback mode.
In Input/Output loopback test modes, if the module is in master mode, the nENA signal is also generated
by internal logic so that an external interface is not required.
NOTE: Usage Guideline for Input/Output Loopback
Input/Output Loopback mode should be used with caution because, in some configurations,even the receive pins will be driven with transmit data. During testing, it should be ensured
that none of the SPI pins are driven by any other device connected to them. Otherwise, if
analog loopback is selected in I/O Loopback mode, then testing may damage the device.

Figure 21-14. I/O Paths during I/O Loopback Modestr

TX SHIFT REG

TX
LPBK_TYPE

RXP_ENA

RX SHIFT REG

Reeeeeeeeee
RX

Checks the analog loopback path through the receive buffer
Checks the analog loopback path through the transmit buffer
Digital loopback path
This diagram is intended to illustrate loopback paths and therefore may omit some normal-mode paths.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

873

General-Purpose I/O

www.ti.com

21.3.2.1 IO Loopback Mode Operation in Slave ModeIn multi-buffer slave mode, there are some additional requirements for using I/O loopback mode (IOLPBK).
In multi-buffer slave mode, the chip-select pins are the triggers for various TGs. Enabling the IOLPBK
mode by writing 0xA to the IOLPBTSTENA bits of the IOLPBKTSTCR register triggers TG0 by driving
SPICS to 0. The actual number of chip selects can be programmed to have any or all of the SPICS pins
as functional. All other configurations should be completed before enabling the IOLPBK mode in multibuffer slave mode since it triggers TG0.
After the first buffer transfer is completed, the CSNR field of the current buffer is used to trigger the next
buffer. So, if multiple TGs are desired to be tested, then the CSNR field of the final buffer in each TG
should hold the number of the next TG to be triggered. As long as TG boundaries are well defined and areenabled, the completion of one TG will trigger the next TG.
To stop the transfer in multi-buffer slave mode in I/O Loopback configuration, either IOLPBK mode can bedisabled by writing 5h to the IOLPBTSTENA bits or all of the TGs can be disabled.

21.4 General-Purpose I/O
All of the SPI pins may be programmed via the SPIPCx control registers to be either functional or generalpurpose I/O pins.
If the SPI function is to be used, application software must ensure that at least the SPICLK pin and the
SOMI and/or SIMO pins are configured as SPI functional pins, and not as GIO pins, or else the SPI statemachine will be held in reset, preventing SPI transactions.
SPI pins support:• internal pull-up resistors• internal pull-down resistors• open-drain or push-pull mode

21.5 Low-Power Mode
The SPI can be put into either local or global low-power mode. Global low-power mode is asserted by thesystem and is not controlled by the SPI. During global low-power mode, all clocks to the SPI are turnedoff, making the module completely inactive.
Local low-power mode is asserted by setting the POWERDOWN (SPIGCR1[8]) bit; setting this bit stops
the clocks to the SPI internal logic and registers. Setting the POWERDOWN bit causes the SPI to enter
local low-power mode and clearing the POWERDOWN bit causes SPI to exit from local low-power mode.
All registers remain accessible during local power-down mode, since the clock to the SPI registers is
temporarily re-enabled for each access. RAM buffers are also accessible during low power mode.
NOTE: Since entering a low-power mode has the effect of suspending all state-machine activities,care must be taken when entering such modes to ensure that a valid state is entered when
low-power mode is active. Application software must ensure that a low power mode is notentered during a data transfer.

874

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Interrupts

www.ti.com

21.6 Interrupts
There are two levels of vectorized interrupts supported by the SPI. These interrupts can be caused under
the following circumstances:• Transmission error• Receive overrun• Receive complete (receive buffer full)• Transmit buffer empty
These interrupts may be enabled or disabled via the SPIINT0 register.
During transmission, if one of the following errors occurs: BITERR, DESYNC, DLENERR, PARITYERR, or
TIMEOUT, the corresponding bit in the SPIFLG register is set. If the corresponding enable bit is set, thenan interrupt is generated. The level of all the above interrupts is set by the bit fields in the SPILVL register.
The error interrupts are enabled and prioritized independently from each other, but the interrupt generated
will be the same if multiple errors are enabled on the same level. The SPIFLG register should be used todetermine the actual cause of an error.
NOTE: Since there are two interrupt lines, one each for Level 0 and Level 1, it is possible for a
programmer to separate out the interrupts for receive buffer full and transmit buffer empty.
By programming one to Level 0 and the other to Level 1, it is possible to avoid a check onwhether an interrupt occurred for transmit or for receive. A programmer can also choose togroup all of the error interrupts into one interrupt line and both TX-empty and RX-fullinterrupts into another interrupt line using the LVL control register. In this way, it is possible
to separate error-checking from normal data handling.

21.6.1 Interrupts in Multi-Buffer ModeIn multi-buffer mode, the SPI can generate interrupts on two levels.
In normal multi-buffer operation, the receive and transmit are not used and therefore the enable bits of
SPIINT0 are not used.
The interrupts available in multi-buffer mode are:• Transmission error interrupt• Receive overrun interrupt• TG suspended interrupt• TG completed interrupt
When a TG has finished and the corresponding enable bit in the TGINTENA register is set, a transferfinished interrupt is generated. The level of priority of the interrupt is determined by the corresponding bit
in the TGINTLVL register.
When a TG is suspended by a buffer that has been set as suspend to wait until TXFULL flag or/and
RXEMPTY flag are set, and if the corresponding bit in the TGINTENA register is set, an transfersuspended interrupt is generated. The level of priority of the interrupt is determined by the corresponding
bit in the TGINTLVL register.
Figure 21-15 illustrates the TG interrupts.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

875

Interrupts

www.ti.com

Figure 21-15. TG Interrupt Structure0
Finished
ENAx

LVLx 0

Suspended
TG x

LVL 0

1

1
ENAx

Vector

LVL 1

LVLx

X +1
Bit 0

During transmission, if one of the following errors occurs, BITERR, DESYNC, PARITYERR, TIMEOUT,DLENERR, the corresponding flag in the SPIFLG register is set. If the enable bit is set, then an interrupt isgenerated. The level of the interrupts could be generated according to the bit field in SPILVL register.
The RXOVRN interrupt is generated when a buffer in the RXRAM is overwritten by a new received word.
While writing newly received data to a RXRAM location, if the RXEMPTY bit of the corresponding location
is 0, then the RXOVR bit will be set to 1 during the write operation, so that the buffer starts to indicate an
overrun. This RXOVR flag is also reflected in SPIFLG register as RXOVRNINTFLG and the corresponding
vector number is updated in TGINTVECT0/TGINTVECT1 register. If an overrun interrupt is enabled, thenan interrupt will be generated indicating an overrun condition.
The error interrupts are enabled and prioritized independently from each other, but the vector generated
by the SPI will be the same if multiple errors are enabled on the same level.
Figure 21-16. SPIFLG Interrupt Structure0
BITERR

1

DESYNC

1

PARITYERR

1

0

0
LVL 0

0
TIMEOUT1RXOVRN

1

DLENERR

1

LVL 1

0

0

ENAx

LVLx

Since the priority of an error interrupt is lower than a completion/suspend interrupt for a TG, the interrupts
can be split into two levels. By programming all the error interrupts into Level 0 and TG-complete / TGsuspend interrupts into Level 1, it is possible to get a clear indication of the source of error interrupts.
However, when a vector register shows an error interrupt, the actual buffer for which the error has
occurred is not readily identifiable. Since each buffer in the multi-buffer RAM is stored along with its
individual status flags, each buffer should be read until a buffer with any error flag set is found.
A separate interrupt line is provided to indicate the uncorrectable error condition in the MibSPI. This line isavailable (and valid) only in the multi-buffer mode of the MibSPI module and if the parity error detection
feature for multi-buffer RAM is enabled.
876

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Module Configuration

www.ti.com

21.7 Module Configuration
MibSPI can be configured to function as normal SPI and multi-buffered SPI. Upon power-up or a systemlevel reset, each bit in the module registers is set to a default state. The registers are writable only after
the RESET bit is set to 1.

21.7.1 Compatibility (SPI) Mode Configuration
The following list details the configuration steps that software should perform prior to the transmission or
reception of data. As long as the SPIEN bit in the Global Control Register 1 (SPIGCR1) is cleared to 0 theentire time that the SPI is being configured, the order in which the registers are programmed is notimportant.
• Enable SPI by setting RESET bit.
• Configure the SIMO, SOMI, SPICLK, and optional SPICS and SPIENA, pins for SPI functionality by
setting the corresponding bit in SPIPC0 register.
• Configure the module to function as Master or Slave using CLKMOD and MASTER bits.
• Configure the required SPI data format using SPIFMTx register.
• If the module is selected to function as Master, the delay parameters can be configured using
SPIDELAY register.
• Enable the Interrupts using SPIINT0 register if required.
• Select the chip select to be used by setting CSNR bits in SPIDAT1 register.
• Configure CSHOLD and WDEL bits in SPIDAT1 register if required.
• Select the Data word format by setting DFSEL bits. Select the Number of the configured SPIFMTx
register (0 to 3) to used for the communication.
• Set LOOPBACK bit to connect the transmitter to the receiver internally. (This feature is used to perform
a self-test. Do not configure for normal communication to external devices).
• Set SPIENA to 1 after the SPI is configured.
• Perform Transmit and receive data, using SPIDAT1 and SPIBUF register.
• You must wait for TXFULL to reset or TXINT before writing next data to SPIDAT1 register.
• You must wait for RXEMPTY to reset or RXINT before reading the data from SPIBUF register.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

877

Module Configuration

www.ti.com

21.7.2 MibSPI Mode Configuration
The following list details the configuration steps that software should perform prior to the transmission or
reception of data in MIBSPI mode. As long as the SPIEN bit in the Global Control Register 1 (SPIGCR1)
is cleared to 0 the entire time that the SPI is being configured, the order in which the registers areprogrammed is not important.
• Enable SPI by setting RESET bit.
• Set MSPIENA to 1 to get access to multi-buffer mode registers.
• Configure the SIMO, SOMI, SPICLK, and optional SPICS and SPIENA, pins for SPI functionality by
setting the corresponding bit in SPIPC0 register.
• Configure the module to function as Master or Slave using CLKMOD and MASTER bits.
• Configure the required SPI data format using SPIFMTx register.
• If the module is selected to function as Master, the delay parameters can be configured using
SPIDELAY register.
• Check for BUFINITACTIVE bit to be active before configuring MIBSPI RAM. (From Device Power On it
take Number of Buffers × Peripheral clock period to initialize complete RAM.)• Enable the Transfer Group interrupts using TGITENST register if required.
• Enable error interrupts using SPIINT0 register if required.
• Set SPIENA to 1 after the SPI is configured.
• The Trigger Source, Trigger Event, Transfer Group start address for the corresponding Transfergroups can be configured using the corresponding TGxCTRL register.
• Configure LPEND to specify the end address of the last TG.
• Similar to SPIDAT1 register 16 Bit Control fields in every TXRAM buffer in the TG has to be
configured.
• Configure one of the eight BUFMODE available for each buffer.
• Fill the data to be transmitted in TXDATA field in TXRAM buffers.
• Configure TGENA bit to enable the required Transfer groups. (In case of Trigger event always setting
TGENA will trigger the transfer group).
• At the occurrence of the correct trigger event the Transfer group will be triggered and data gets
transmitted and received one after the other with out any CPU intervention.
• You can poll Transfer-group interrupt flag or wait for a transfer-completed interrupt to read and write
new data to the buffers.

878

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

21.8 Control Registers
This section describes the SPI control, data, and pin registers. The registers support 8-bit, 16-bit and 32bit writes. The offset is relative to the associated base address of this module in a system. The baseaddress for the control registers is FFF7 F400h for MibSPI1, FFF7 F600h for SPI2, and FFF7 F800h for
SPI3.
NOTE: TI highly recommends that write values corresponding to the reserved locations of registers
be maintained as 0 consistently. This allows future enhancements to use these reserved bits
as control bits without affecting the functionality of the module with any older versions ofsoftware.

Table 21-3. SPI Registers(1)

OffsetAcronym

Register Description

Section00h

SPIGCR0

SPI Global Control Register 0

Section 21.8.1

04h

SPIGCR1

SPI Global Control Register 1

Section 21.8.2

08h

SPIINT0

SPI Interrupt Register

Section 21.8.3

0Ch

SPILVL

SPI Interrupt Level Register

Section 21.8.4

10h

SPIFLGSPI Flag Register

Section 21.8.5

14h

SPIPC0SPI Pin Control Register 0

Section 21.8.6

18h

SPIPC1SPI Pin Control Register 1

Section 21.8.7

1Ch

SPIPC2SPI Pin Control Register 2

Section 21.8.8

20h

SPIPC3

SPI Pin Control Register 3

Section 21.8.9

24h

SPIPC4

SPI Pin Control Register 4

Section 21.8.10

28h

SPIPC5

SPI Pin Control Register 5

Section 21.8.11

2Ch

SPIPC6

SPI Pin Control Register 6

Section 21.8.12

30h

SPIPC7

SPI Pin Control Register 7

Section 21.8.13

34h

SPIPC8SPI Pin Control Register 8

Section 21.8.14

38h

SPIDAT0

SPI Transmit Data Register 0

Section 21.8.15

3Ch

SPIDAT1

SPI Transmit Data Register 1

Section 21.8.16

40h

SPIBUFSPI Receive Buffer Register

Section 21.8.17

44h

SPIEMUSPI Emulation Register

Section 21.8.18

48h

SPIDELAYSPI Delay Register

Section 21.8.19

4Ch

SPIDEFSPI Default Chip Select Register

Section 21.8.20

50h-5ChSPIFMTSPI Data Format Registers

Section 21.8.21

60h

INTVECT0Interrupt Vector 0

Section 21.8.22

64h

INTVECT1

Interrupt Vector 1

Section 21.8.23

(1)

68h

SPIPC9SPI Pin Control Register 9

Section 21.8.24

70h

MIBSPIE

Multi-buffer Mode Enable Register

Section 21.8.25

74h

TGITENSTTG Interrupt Enable Set Register

Section 21.8.26

78h

TGITENCRTG Interrupt Enable Clear Register

Section 21.8.27

7Ch

TGITLVST

Transfer Group Interrupt Level Set Register

Section 21.8.28

80h

TGITLVCR

Transfer Group Interrupt Level Clear Register

Section 21.8.29

84h

TGINTFLG

Transfer Group Interrupt Flag Register

Section 21.8.30

90h

TICKCNT

Tick Count Register

Section 21.8.31

94h

LTGPEND

Last TG End PointerSection 21.8.32

98h-D4h

TGxCTRL

TGx Control Registers

Section 21.8.33

120h

UERRCTRL

Multi-buffer RAM Uncorrectable Parity Error Control Register

Section 21.8.34

124h

UERRSTAT

Multi-buffer RAM Uncorrectable Parity Error Status Register

Section 21.8.35

128h

UERRADDR1

RXRAM Uncorrectable Parity Error Address Register

Section 21.8.36

SPIPC9 only applies to SPI2.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI) 879
Copyright © 2018, Texas Instruments Incorporated

Control Registers

www.ti.com

Table 21-3. SPI Registers (continued)
OffsetAcronym

Register Description

12Ch

UERRADR0

TXRAM Uncorrectable Parity Error Address Register

Section 21.8.37

Section130h

RXOVRN_BUF_ADDR

RXRAM Overrun Buffer Address Register

Section 21.8.38

134h

IOLPBKTSTCR

I/O Loopback Test Control Register

Section 21.8.39

138h

EXTENDED_PRESCALE1SPI Extended Prescale Register 1

Section 21.8.40

13Ch

EXTENDED_PRESCALE2SPI Extended Prescale Register 2

Section 21.8.41

21.8.1 SPI Global Control Register 0 (SPIGCR0)
Figure 21-17. SPI Global Control Register 0 (SPIGCR0) [offset = 00]
31

16
Reserved
R-0

15

1

0

Reserved

nRESET

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 21-4. SPI Global Control Register 0 (SPIGCR0) Field Descriptions
Bit

Field

31-1

Reserved

0

nRESET

880

Value
0

Description
Reads return 0. Writes have no effect.
This is the local reset control for the module. This bit needs to be set to 1 before any operation on SPI /MibSPI can be done. Only after setting this bit to 1, the Auto Initialization of Multi-buffer RAM starts.
Clearing this bit to 0 results in all of the control and status register values to return to their default
values.

0

SPI is in the reset state.

1

SPI is out of the reset state.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

21.8.2 SPI Global Control Register 1 (SPIGCR1)
Figure 21-18. SPI Global Control Register 1 (SPIGCR1) [offset = 04h]
31

25

24

23

17

16

Reserved

SPIEN

Reserved

LOOPBACK

R-0

R/W-0

R-0

R/WP-0

15

9

8

7

2

1

0

Reserved

POWERDOWN

Reserved

CLKMOD

MASTER

R-0

R/W-0

R-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 21-5. SPI Global Control Register 1 (SPIGCR1) Field Descriptions
Bit

Field

31-25

Reserved

24

SPIEN

Value
0

Description
Reads return 0. Writes have no effect.
SPI enable. This bit enables SPI transfers. This bit must be set to 1 after all other SPI
configuration bits have been written. When the SPIEN bit is 0 or cleared to 0, the following SPI
registers get forced to their default states:• Both TX and RX shift registers• The TXDATA fields of the SPI Transmit Data Register 0 (SPIDAT0) and the SPI Transmit
Data Register 1 (SPIDAT1)• All the fields of the SPI Flag Register (SPIFLG)• Contents of SPIBUF and the internal RXBUF registers

23-17

Reserved

16

LOOPBACK

0The SPI is not activated for transfers.

1

Activates SPI.

0

Reads return 0. Writes have no effect.
Internal loop-back test mode. The internal self-test option can be enabled by setting this bit. If
the SPISIMO and SPISOMI pins are configured with SPI functionality, then the SPISIMO[7:0]pins are internally connected to the SPISOMI[7:0] pins (transmit data is looped back as receivedata). GIO mode for these pins is not supported in loopback mode. Externally, during loop-back
operation, the SPICLK pin outputs an inactive value and SPISOMI[7:0] remains in the highimpedance state. If the SPI is initialized in slave mode or a data transfer is ongoing, errors may
result.
Note: This loopback mode can only be used in master mode. Master mode must be
selected before setting LOOPBACK. When this mode is selected, the CLKMOD bit should
be set to 1, meaning that SPICLK is internally generated.

15-9
8

Reserved

0Internal loop-back test mode is disabled.

1

Internal loop-back test mode is enabled.

0

Reads return 0. Writes have no effect.

POWERDOWN

7-2

Reserved

1

CLKMOD

When active, the SPI state machine enters a power-down state.
0

The SPI is in active mode.

1

The SPI is in power-down mode.

0

Reads return 0. Writes have no effect.
Clock mode. This bit selects either an internal or external clock source. This bit also determines
the I/O direction of the SPIENA and SPICS pins in functional mode.

0

Clock is external.
• SPIENA is an output.
• SPICS are inputs.

1

Clock is internally-generated.
• SPIENA is an input.
• SPICS are outputs.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

881

Control Registers

www.ti.com

Table 21-5. SPI Global Control Register 1 (SPIGCR1) Field Descriptions (continued)
Bit

Field

0

MASTER

Value

Description
SPISIMO/SPISOMI pin direction determination. Sets the direction of the SPISIMO andSPISOMI pins.
Note: For master-mode operation of the SPI, MASTER bit should be set to 1 and
CLKMOD bit can be set either 1 or 0. The master-mode SPI can run on an external clock
on SPICLK.
For slave mode operation, both the MASTER and CLKMOD bits should be cleared to 0.
Any other combinations may result in unpredictable behavior of the SPI. In slave mode.
SPICLK will not be generated internally in slave mode.

0

SPISIMO[7:0] pins are inputs, SPISOMI[7:0] pins are outputs.

1

SPISOMI[7:0] pins are inputs, SPISIMO[7:0] pins are outputs.

21.8.3 SPI Interrupt Register (SPIINT0)
Figure 21-19. SPI Interrupt Register (SPIINT0) [offset = 08h]
31

25

24

Reserved

ENABLEHIGHZ

R-0

R/W-0

23

17

16

Reserved

Reserved

R-0

R/W-0

15

9

8

Reserved

10

TXINT
ENA

RXINT
ENA

R-0

R/W-0

R/W-0

7

6

5

4

3

2

1

0

Reserved

RXOVRNINT
ENA

Reserved

BITERRENA

DESYNC
ENA

PARERRENA

TIMEOUTENADLENERR
ENA

R-0

R/W-0

R-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-6. SPI Interrupt Register (SPIINT0) Field Descriptions
Bit

Field

31-25

Reserved

24

Value
0

ENABLEHIGHZ

Description
Reads return 0. Writes have no effect.
SPIENA pin high-impedance enable. When active, the SPIENA pin (when it is configured as a
WAIT functional output signal in a slave SPI) is forced to high-impedance when not driving a
low signal. If inactive, then the pin will output both a high and a low signal.

0

SPIENA pin is pulled high when not active.

1

SPIENA pin remains high-impedance when not active.

23-17

Reserved

0

Reads return 0. Writes have no effect.

16

Reserved

0

Reserved. Do not use.

15-10

Reserved

0

Reads return 0. Writes have no effect.

882

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

Table 21-6. SPI Interrupt Register (SPIINT0) Field Descriptions (continued)
Bit

Field

9

TXINTENA

Value

Description
Causes an interrupt to be generated every time data is written to the shift register, so that thenext word can be written to TXBUF. Setting this bit will generate an interrupt if the TXINTFLG
bit (SPI Flag Register (SPIFLG)[9]) is set to 1.

0

No interrupt will be generated upon TXINTFLG being set to 1.

1

An interrupt will be generated upon TXINTFLG being set to 1.
The transmitter empty interrupt is valid in compatibility mode of SPI only. In multi-bufferedmode, this interrupts will not be generated, even if it is enabled.
Note: An interrupt request will be generated as soon as this bit is set to 1. By default it
will be generated on the INT0 line. The SPILVL register can be programmed to change
the interrupt line.

8

RXINTENA

Causes an interrupt to be generated when the RXINTFLAG bit (SPI Flag Register (SPIFLG)[8])is set by hardware.
0Interrupt will not be generated.

1

Interrupt will be generated.
The receiver full interrupt is valid in compatibility mode of SPI only. In multi-buffered mode, thisinterrupts will not be generated, even if it is enabled.

7

Reserved

6

RXOVRNINTENA

5

Reserved

4

BITERRENA

3

2

1

0

0

Reads return 0. Writes have no effect.
Overrun interrupt enable.

0Overrun interrupt will not be generated.

1

Overrun interrupt will be generated.

0

Reads return 0. Writes have no effect.
Enables interrupt on bit error.

0

No interrupt asserted upon bit error.

1

Enables interrupt on bit error.

DESYNCENA

Enables interrupt on desynchronized slave. DESYNCENA is used in master mode only.
0

No interrupt asserted upon desynchronization error.

1

An interrupt is asserted on desynchronization of the slave (DESYNC = 1).

PARERRENA

Enables interrupt-on-parity-error.
0

No interrupt asserted on parity error.

1

An interrupt is asserted on a parity error.

TIMEOUTENA

Enables interrupt on ENA signal time-out.
0

No interrupt asserted upon ENA signal time-out.

1

An interrupt is asserted on a time-out of the ENA signal.

DLENERRENA

Data length error interrupt enable. A data length error occurs under the following conditions.
Master: When SPIENA is used, if the SPIENA pin from the slave is deasserted before themaster has completed its transfer, the data length error is set. That is, if the character lengthcounter has not overflowed while SPIENA deassertion is detected, then it means that the slave
has neither received full data from the master nor has it transmitted complete data.
Slave: When SPICS pins are used, if the incoming valid SPICS pin is deactivated before thecharacter length counter overflows, then the data length error is set.

SPNU517C – March 2018
Submit Documentation Feedback0

No interrupt is generated upon data length error.

1

An interrupt is asserted when a data-length error occurs.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

883

Control Registers

www.ti.com

21.8.4 SPI Interrupt Level Register (SPILVL)
Figure 21-20. SPI Interrupt Level Register (SPILVL) [offset = 0Ch]
31

16
Reserved
R-0
15

10

9

8

Reserved

TXINT
LVL

RXINT
LVL

R-0

R/W-0

R/W-0

7

6

5

4

3

2

1

0

Reserved

RXOVRNINT
LVLReserved

BITERRLVL

DESYNC
LVL

PARERRLVL

TIMEOUTLVL

DLENERR
LVL

R-0

R/W-0

R-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-7. SPI Interrupt Level Register (SPILVL) Field Descriptions
Bit

Field

31-10

Reserved

9

TXINTLVL

8

Reserved

6

RXOVRNINTLVL

5Reserved

4

BITERRLVL

2

1

0

884

0

Description
Reads return 0. Writes have no effect.
Transmit interrupt level.

0

Transmit interrupt is mapped to interrupt line INT0.

1

Transmit interrupt is mapped to interrupt line INT1.

RXINTLVL

7

3

Value

Receive interrupt level.
0

Receive interrupt is mapped to interrupt line INT0.

1

Receive interrupt is mapped to interrupt line INT1.

0

Reads return 0. Writes have no effect.
Receive overrun interrupt level.

0

Receive overrun interrupt is mapped to interrupt line INT0.

1

Receive overrun interrupt is mapped to interrupt line INT1.

0

Reads return 0. Writes have no effect.
Bit error interrupt level.

0

Bit error interrupt is mapped to interrupt line INT0.

1

Bit error interrupt is mapped to interrupt line INT1.

DESYNCLVL

Desynchronized slave interrupt level. (master mode only).
0

An interrupt caused by desynchronization of the slave is mapped to interrupt line INT0.

1

An interrupt caused by desynchronization of the slave is mapped to interrupt line INT1.

PARERRLVLParity error interrupt level.
0

A parity error interrupt is mapped to interrupt line INT0.

1

A parity error interrupt is mapped to interrupt line INT1.

TIMEOUTLVLSPIENA pin time-out interrupt level.
0

An interrupt on a time-out of the ENA signal (TIMEOUT = 1) is mapped to interrupt line INT0.

1

An interrupt on a time-out of the ENA signal (TIMEOUT = 1) is mapped to interrupt line INT1.

DLENERRLVL

Data length error interrupt level (line) select.
0

An interrupt on data length error is mapped to interrupt line INT0.

1

An interrupt on data length error is mapped to interrupt line INT1.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

21.8.5 SPI Flag Register (SPIFLG)
Software must check all flag bits when reading this register.
Figure 21-21. SPI Flag Register (SPIFLG) [offset = 10h]
31

25

24

23

16

Reserved

BUFINITACTIVE

Reserved

R-0

R-0

R-0

15

9

8

Reserved

10

TXINT
FLG

RXINT
FLG

R-0

R-0

R/W1C-0

7

6

5

4

3

2

1

0

Reserved

RXOVRNINT
FLG

Reserved

BITERRFLG

DESYNC
FLG

PARERRFLG

TIMEOUTFLG

DLENERR
FLG

R-0

R/W1C-0

R-0

R/W1C-0

R/W1C-0

R/W1C-0

R/W1C-0

R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset

Table 21-8. SPI Flag Register (SPIFLG) Field Descriptions
Bit

Field

31-25

Reserved

24

Value
0

BUFINITACTIVE

Description
Reads return 0. Writes have no effect.
Indicates the status of multi-buffer initialization process. Software can poll for this bit todetermine if it can proceed with the register configuration of multi-buffer mode registers or buffer
handling.
Note: If the SPIFLG register is read while the multi-buffer RAM is being initialized, the
BUFINITACTIVE bit will be read as 1. If SPIFLG is read after the internal automatic buffer
initialization is complete, this bit will be read as 0. This bit will show a value of 1 as longas the nRESET bit is 0, but does not really indicate that buffer initialization is underway.
Buffer initialization starts only when the nRESET bit is set to 1.

23-10

Reserved

9

TXINTFLG

0

Multi-buffer RAM initialization is complete.

1

Multi-buffer RAM is still being initialized. Do not attempt to write to either multi-buffer RAM or
any multi-buffer mode registers.

0

Reads return 0. Writes have no effect.
Transmitter-empty interrupt flag. Serves as an interrupt flag indicating that the transmit buffer(TXBUF) is empty and a new word can be written to it. This flag is set when a word is copied tothe shift register either directly from SPIDAT0/SPIDAT1 or from the TXBUF register. This bit iscleared by one of following methods:• Writing a new data to either SPIDAT0 or SPIDAT1• Writing a 0 to SPIEN (SPIGCR1[24])SPNU517C – March 2018
Submit Documentation Feedback

0

Transmit buffer is now full. No interrupt pending for transmitter empty.

1

Transmit buffer is empty. An interrupt is pending to fill the transmitter.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

885

Control Registers

www.ti.com

Table 21-8. SPI Flag Register (SPIFLG) Field Descriptions (continued)
Bit

Field

8

RXINTFLG

Value

Description
Receiver-full interrupt flag. This flag is set when a word is received and copied into the buffer
register (SPIBUF). If RXINTEN is enabled, an interrupt is also generated. This bit is cleared
under the following methods:
•
•
•
•
•

Reading the SPIBUF register
Reading TGINTVECT0 or TGINTVECT1 register when there is a receive buffer full interrupt
Writing a 1 to this bit
Writing a 0 to SPIEN (SPIGCR1[24])System reset

During emulation mode, however, a read to the emulation register (SPIEMU) does not clear thisflag bit.
0

No new received data pending. Receive buffer is empty.

1

A newly received data is ready to be read. Receive buffer is full.
Note: Clearing RXINTFLG bit by writing a 1 before reading the SPIBUF sets the RXEMPTY
bit of the SPIBUF register too. In this way, you can ignore a received word. However, if
the internal RXBUF is already full, the data from RXBUF will be copied to SPIBUF and the
RXEMPTY bit will be cleared again. The SPIBUF contents should be read first if thissituation needs to be avoided.

7

Reserved

6

RXOVRNINTFLG

0

Reads return 0. Writes have no effect.
Receiver overrun flag. The SPI hardware sets this bit when a receive operation completes
before the previous character has been read from the receive buffer. The bit indicates that thelast received character has been overwritten and therefore lost. The SPI will generate aninterrupt request if this bit is set and the RXOVRN INTEN bit (SPIINT0.6) is set high. This bit iscleared under the following conditions in compatibility mode of MibSPI:• Reading TGINTVECT0 or TGINTVECT1 register when there is a receive-buffer-overrun
interrupt• Writing a 1 to RXOVRNINTFLG in the SPI Flag Register (SPIFLG) itself• Writing a 0 to SPIEN• Reading the data field of the SPIBUF register
Note: Reading the SPIBUF register does not clear this RXOVRNINTFLG bit. If an RXOVRNinterrupt is detected, then the SPIBUF may need to be read twice to get to the overrun
buffer. This is due to the fact that the overrun will always occur to the internal RXBUF.
Each read to the SPIBUF will result in RXBUF contents (if it is full) getting copied to
SPIBUF.
Note: There is a special condition under which the RXOVRNINTFLG flag gets set. If both
SPIBUF and RXBUF are already full and while another reception is underway, if any
errors (TIMEOUT, BITERR, and DLEN_ERR) occur, then RXOVR in RXBUF andRXOVRNINTFLG in SPIFLG registers will be set to indicate that the status flags are
getting overwritten by the new transfer. This overrun should be treated like a receive
overrun.
In multi-buffer mode of MibSPI, this bit is cleared under the following conditions:• Reading the RXOVRN_BUF_ADDR register• Writing a 1 to RXOVRNINTFLG in the SPI Flag Register (SPIFLG) itself
In multi-buffer mode, if RXOVRNINTFLG is set, then the address of the buffer which
experienced the overrun is available in RXOVRN_BUF_ADDR.

5Reserved

4

BITERRFLG

0Overrun condition did not occur.

1

Overrun condition has occurred.

0

Reads return 0. Writes have no effect.
Mismatch of internal transmit data and transmitted data. This flag can be cleared by one of thefollowing methods:• Write a 1 to this bit• Clear the SPIENA bit to 08860

No bit error occurred.

1

A bit error occurred. The SPI samples the signal of the transmit pin (master: SIMO, slave:
SOMI) at the receive point (half clock cycle after transmit point). If the sampled value differsfrom the transmitted value a bit error is detected and the flag BITERRFLG is set. If BITERRENA
is set an interrupt is asserted. Possible reasons for a bit error can be an excessively high bit
rate, capacitive load, or another master/slave trying to transmit at the same time.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

Table 21-8. SPI Flag Register (SPIFLG) Field Descriptions (continued)
Bit

Field

3

DESYNCFLG

Value

Description
Desynchronization of slave device. Desynchronization monitor is active in master mode only.
This flag can be cleared by one of the following methods:• Write a 1 to this bit• Clear the SPIENA bit to 020

No slave desynchronization detected.

1

A slave device is desynchronized. The master monitors the ENAble signal coming from theslave device and sets the DESYNC flag after the last bit is transmitted plus t T2EDELAY. If
DESYNCENA is set an interrupt is asserted. Desynchronization can occur if a slave device
misses a clock edge coming from the master.

PARERRFLG

Calculated parity differs from received parity bit. If the parity generator is enabled (can beselected individually for each buffer) an even or odd parity bit is added at the end of a data
word. During reception of the data word the parity generator calculates the reference parity andcompares it to the received parity bit. In the event of a mismatch the PARITYERR flag is set
and an interrupt is asserted if PARERRENA is set. This flag can be cleared by one of thefollowing methods:• Write a 1 to this bit• Clear the SPIENA bit to 010

No parity error detected.

1

A parity error occurred.

TIMEOUTFLG

Time-out caused by nonactivation of ENA signal. This flag can be cleared by one of thefollowing methods:• Write a 1 to this bit• Clear the SPIENA bit to 0

00

No ENA-signal time-out occurred.

1

An ENA signal time-out occurred. The SPI generates a time-out because the slave has not
responded in time by activating the ENA signal after the chip select signal has been activated. If
a time-out condition is detected the corresponding chip select is deactivated immediately and
the TIMEOUT flag is set. In addition the TIMEOUT flag in the status field of the corresponding
buffer is set. The transmit request of the concerned buffer is cleared, that is, the SPI does not
re-start a data transfer from this buffer.

DLENERRFLG

Data-length error flag. This flag can be cleared by one of the following methods:• Write a 1 to this bit• Clear the SPIENA bit to 0
Note: Whenever any transmission errors (TIMEOUT, BITERR, DLEN_ERR, PARITY_ERR,DESYNC) are detected and the error flags are cleared by writing to the error bit in the
SPIFLG register, the corresponding error flag in SPIBUF does not get cleared. Softwareneeds to read the SPIBUF until it becomes empty before proceeding. This ensures that
all of the old status bits in SPIBUF are cleared before starting the next transfer.

SPNU517C – March 2018
Submit Documentation Feedback0

No data length error has occurred.

1

A data length error has occurred.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

887

Control Registers

www.ti.com

21.8.6 SPI Pin Control Register 0 (SPIPC0)NOTE: Register bits vary by device
Register bits 31-24 and 23-16 of SPIPC0 to SPIPC9 reflect the number of SIMO/SOMI datalines per device. On devices with 8 data-line support, all of bits 31 to 16 are implemented.
On devices with less than 8 data lines, only a subset of these bits are available.
Unimplemented bits return 0 upon read and are not writable.

Figure 21-22. SPI Pin Control Register 0 (SPIPC0) [offset = 14h]
31

24

23

16

Reserved

Reserved

R/W-0

R/W-0

15

11

10

9

8

Reserved

12

SOMIFUN0

SIMOFUN0

CLKFUNENAFUN

R-0

R/W-0

R/W-0

R/W-0

R/W-0

7

0
SCSFUN
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-9. SPI Pin Control (SPIPC0) Field Descriptions
Bit

Field

31-24

Reserved

Value
0

Description
Reserved. Do not use.
Note: Bit 24 is not physically implemented. It is a mirror of bit 11. Any write to bit 24 will bereflected on bit 11. When bit 24 and bit 11 are simultaneously written, the value of bit 11 willcontrol the SPISOMI[0] pin. The read value of bit 24 always reflects the value of bit 11.

23-16

Reserved

0

Reserved. Do not use.
Note: Bit 16 is not physically implemented. It is a mirror of bit 10. Any write to bit 16 will bereflected on bit 10. When bit 16 and bit 10 are simultaneously written, the value of bit 10 willcontrol the SPISOMI[x] pin. The read value of bit 16 always reflects the value of bit 10.

15-12

Reserved

11

SOMIFUN0

0

Reads return 0. Writes have no effect.
Slave out, master in function. This bit determines whether the SPISOMI0 pin is to be used as a
general-purpose I/O pin or as a SPI functional pin.

0

The SPISOMI0 pin is a GIO pin.

1

The SPISOMI0 pin is a SPI functional pin.
Note: SPISOMI0 pin will always have to be programmed as functional pins for any SPI
transfers.

10

SIMOFUN0

Slave in, master out function. This bits determine whether each SPISIMO0 pin is to be used as a
general-purpose I/O pin or as a SPI functional pin.
0

The SPISIMO0 pin is a GIO pin.

1

The SPISIMO0 pin is a SPI functional pin.
Note: SPISIMO0 pin will always have to be programmed as functional pins for any SPI
transfers.

9

8

888

CLKFUNSPI clock function. This bit determines whether the SPICLK pin is to be used as a general-purpose
I/O pin, or as a SPI functional pin.
0

The SPICLK pin is a GIO pin.

1

The SPICLK pin is a SPI functional pin.

ENAFUNSPIENA function. This bit determines whether the SPIENA pin is to be used as a general-purpose
I/O pin or as a SPI functional pin.
0

The SPIENA pin is a GIO pin.

1

The SPIENA pin is a SPI functional pin.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

Table 21-9. SPI Pin Control (SPIPC0) Field Descriptions (continued)
Bit

Field

7-0

SCSFUN

Value

Description
SPICS function. Determines whether each SPICS pin is to be used as a general-purpose I/O pin or
as a SPI functional pin. If the slave SPICS pins are in functional mode and receive an inactive highsignal, the slave SPI will place its output in a high-impedance state and disable shifting.

0

The SPICS pin is a GIO pin.

1

The SPICS pin is a SPI functional pin.

21.8.7 SPI Pin Control Register 1 (SPIPC1)
NOTE: Register bits vary by device
Register bits 31-24 and 23-16 of this register reflect the number of SIMO/SOMI data lines per
device. On devices with 8 data-line support, all of bits 31 to 16 are implemented. On devices
with less than 8 data lines, only a subset of these bits are available. Unimplemented bits
return 0 upon read and are not writable.

Figure 21-23. SPI Pin Control Register 1 (SPIPC1) [offset = 18h]
31

24

23

16

SOMIDIRSIMODIR

R/W-0

R/W-0

15

11

10

9

8

Reserved

12

SOMIDIR0SIMODIR0

CLKDIRENADIR

R-0

R/W-0

R/W-0

R/W-0

R/W-0

7

0
SCSDIR
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-10. SPI Pin Control Register (SPIPC1) Field Descriptions
Bit

Field

31-24

SOMIDIR

Value

Description
SPISOMIx direction. Controls the direction of each SPISOMIx pin when used for general-purpose
I/O. If SPISOMIx pin is used as a SPI functional pin, the I/O direction is determined by the MASTER
bit in the SPIGCR1 register.
Note: Duplicate Control Bits for SPISOMI0. Bit 24 is not physically implemented. It is a mirrorof bit 11. Any write to bit 24 will be reflected on bit 11. When bit 24 and bit 11 aresimultaneously written, the value of bit 11 will control the SPISOMI pin. The read value of bit
24 always reflects the value of bit 11.

23-16

0

The SPISOMIx pin is an input.

1

The SPISOMIx pin is an output.

SIMODIRSPISIMOx direction. Controls the direction of each SPISIMOx pin when used for general-purpose
I/O. If SPISIMOx pin is used as a SPI functional pin, the I/O direction is determined by the MASTER
bit in the SPIGCR1 register.
Note: Duplicate Control Bits for SPISIMO. Bit 16 is not physically implemented. It is a mirrorof bit 10. Any write to bit 16 will be reflected on bit 10. When bit 16 and bit 10 are
simultaneously written, the value of bit 10 will control the SPISIMO pin. The read value of bit
16 always reflects the value of bit 10.

15-12

Reserved

SPNU517C – March 2018
Submit Documentation Feedback

0

The SPISIMOx pin is an input.

1

The SPISIMOx pin is an output.

0

Reads return 0. Writes have no effect.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

889

Control Registers

www.ti.com

Table 21-10. SPI Pin Control Register (SPIPC1) Field Descriptions (continued)
Bit

Field

11

SOMIDIR0

10

9

8

7-0

890

Value

Description
SPISOMI0 direction. This bit controls the direction of the SPISOMI0 pin when it is used as a
general-purpose I/O pin. If the SPISOMI0 pin is used as a SPI functional pin, the I/O direction isdetermined by the MASTER bit in the SPIGCR1 register.

0

The SPISOMI0 pin is an input.

1

The SPISOMI0 pin is an output.

SIMODIR0SPISIMO0 direction. This bit controls the direction of the SPISIMO0 pin when it is used as a
general-purpose I/O pin. If the SPISIMO0 pin is used as a SPI functional pin, the I/O direction isdetermined by the MASTER bit in the SPIGCR1 register.
0

The SPISIMO0 pin is an input.

1

The SPISIMO0 pin is an output.

CLKDIRSPICLK direction. This bit controls the direction of the SPICLK pin when it is used as a generalpurpose I/O pin. In functional mode, the I/O direction is determined by the CLKMOD bit.
0

The SPICLK pin is an input.

1

The SPICLK pin is an output.

ENADIRSPIENA direction. This bit controls the direction of the SPIENA pin when it is used as a generalpurpose I/O. If the SPIENA pin is used as a functional pin, then the I/O direction is determined by
the CLKMOD bit (SPIGCR1[1]).
0

The SPIENA pin is an input.

1

The SPIENA pin is an output.

SCSDIRSPICS direction. These bits control the direction of each SPICS pin when it is used as a generalpurpose I/O pin. Each pin could be configured independently from the others If the SPICS is used
as a SPI functional pin; the I/O direction is determined by the CLKMOD bit (SPIGCR1[1]).
0

The SPICS pin is an input.

1

The SPICS pin is an output.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

21.8.8 SPI Pin Control Register 2 (SPIPC2)
NOTE: Register bits vary by device
Register bits 31-24 and 23-16 of this register reflect the number of SIMO/SOMI data lines per
device. On devices with 8 data-line support, all of bits 31 to 16 are implemented. On devices
with less than 8 data lines, only a subset of these bits are available. Unimplemented bits
return 0 upon read and are not writable.

Figure 21-24. SPI Pin Control Register 2 (SPIPC2) [offset = 1Ch]
31

24

23

16

SOMIDIN

SIMODIN

R/W-U

R/W-U

15

11

10

9

8

Reserved

12

SOMIDIN0

SIMODIN0

CLKDINENADIN

R-0

R-U

R-U

R-U

R-U

7

0
SCSDINR/W-U

LEGEND: R/W = Read/Write; R = Read only; U = Undefined; -n = value after reset

Table 21-11. SPI Pin Control Register 2 (SPIPC2) Field Descriptions
Bit

Field

31-24

SOMIDIN

23-16

Reserved

11

SOMIDIN0

9

8

7-0

SPISOMIx data in. The value of each SPISOMIx pin.
The SPISOMIx pin is logic 0.

1

The SPISOMIx pin is logic 1.
SPISIMOx data in. The value of each SPISIMOx pin.

0

The SPISIMOx pin is logic 0.

1

The SPISIMOx pin is logic 1.

0

Reads return 0. Writes have no effect.
SPISOMI0 data in. The value of the SPISOMI0 pin.

0

The SPISOMI0 pin is logic 0.

1

The SPISOMI0 pin is logic 1.

SIMODIN0SPISIMO0 data in. The value of the SPISIMO0 pin.
0

The SPISIMO0 pin is logic 0.

1

The SPISIMO0 pin is logic 1.

CLKDIN

Clock data in. The value of the SPICLK pin.
0

The SPICLK pin is logic 0.

1

The SPICLK pin is logic 1.

ENADINSPIENA data in. The value of the SPIENA pin.
0

The SPIENA pin is logic 0.

1

The SPIENA pin is logic 1.

SCSDINSPNU517C – March 2018
Submit Documentation Feedback

Description

0
SIMODIN

15-12

10

Value

SPICS data in. The value of each SPICS pin.
0

The SPICS pin is logic 0.

1

The SPICS pin is logic 1.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

891

Control Registers

www.ti.com

21.8.9 SPI Pin Control Register 3 (SPIPC3)
NOTE: Register bits vary by device
Register bits 31-24 and 23-16 of this register reflect the number of SIMO/SOMI data lines per
device. On devices with 8 data-line support, all of bits 31 to 16 are implemented. On devices
with less than 8 data lines, only a subset of these bits are available. Unimplemented bits
return 0 upon read and are not writable.

Figure 21-25. SPI Pin Control Register 3 (SPIPC3) [offset = 20h]
31

24

23

16

SOMIDOUTSIMODOUT

R/W-U

R/W-U

15

11

10

9

8

Reserved

12

SOMIDOUT0

SIMODOUT0

CLKDOUTENADOUT

R-0

R/W-U

R/W-U

R/W-U

R/W-U

7

0
SCSDOUTR/W-U

LEGEND: R/W = Read/Write; R = Read only; U = Undefined; -n = value after reset

Table 21-12. SPI Pin Control Register 3 (SPIPC3) Field Descriptions
Bit

Field

31-24

SOMIDOUT

Value

Description
SPISOMIx data out write. This bit is only active when the SPISOMIx pin is configured as a generalpurpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to thepin.
Bit 11 or bit 24 can be used to set the direction for pin SPISOMI0. If a 32-bit write is
performed, bit 11 will have priority over bit 24.

23-16

0

Current value on SPISOMIx pin is logic 0.

1

Current value on SPISOMIx pin is logic 1

SIMODOUTSPISIMOx data out write. This bit is only active when the SPISIMOx pin is configured as a generalpurpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to thepin.
Bit 10 or bit 16 can be used to set the direction for pin SPISIMO0. If a 32-bit write is
performed, bit 10 will have priority over bit 16.

15-12
11

10

9

892

Reserved0

Current value on SPISIMOx pin is logic 0.

1

Current value on SPISIMOx pin is logic 1.

0

Reads return 0. Writes have no effect.

SOMIDOUT0SPISOMI0 data out write. This bit is only active when the SPISOMI0 pin is configured as a generalpurpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to thepin.
0Current value on SPISOMI0 pin is logic 0.

1

Current value on SPISOMI0 pin is logic 1.

SIMODOUT0SPISIMO0 data out write. This bit is only active when the SPISIMO0 pin is configured as a generalpurpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to thepin.
0

The SPISIMO0 pin is logic 0.

1

The SPISIMO0 pin is logic 1.

CLKDOUTSPICLK data out write. This bit is only active when the SPICLK pin is configured as a generalpurpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to thepin.
0

The SPICLK pin is logic 0.

1

The SPICLK pin is logic 1.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

Table 21-12. SPI Pin Control Register 3 (SPIPC3) Field Descriptions (continued)
Bit

Field

8

ENADOUT

7-0

Value

Description
SPIENA data out write. Only active when the SPIENA pin is configured as a general-purpose I/O
pin and configured as an output pin. The value of this bit indicates the value sent to the pin.

0

The SPIENA pin is logic 0.

1

The SPIENA pin is logic 1.

SCSDOUTSPICS data out write. Only active when the SPICS pins are configured as a general-purpose I/O
pins and configured as output pins. The value of these bits indicates the value sent to the pins.
0

The SPICS pin is logic 0.

1

The SPICS pin is logic 1.

21.8.10 SPI Pin Control Register 4 (SPIPC4)
NOTE: Register bits vary by device
Register bits 31-24 and 23-16 of this register reflect the number of SIMO/SOMI data lines per
device. On devices with 8 data-line support, all of bits 31 to 16 are implemented. On devices
with less than 8 data lines, only a subset of these bits are available. Unimplemented bits
return 0 upon read and are not writable.

Figure 21-26. SPI Pin Control Register 4 (SPIPC4) [offset = 24h]
31

24

23

16

SOMISETSIMOSET

R/W-U

R/W-U

15

11

10

9

8

Reserved

12

SOMISET0SIMOSET0

CLKSET

ENASET

R-0

R/W-U

R/W-U

R/W-U

R/W-U

7

0
SCSSET
R/W-U

LEGEND: R/W = Read/Write; R = Read only; U = Undefined; -n = value after reset

Table 21-13. SPI Pin Control Register 4 (SPIPC4) Field Descriptions
Bit

Field

31-24

SOMISET

Value

Description
SPISOMIx data out set. This pin is only active when the SPISOMIx pin is configured as a generalpurpose output pin.
Bit 11 or bit 24 can be used to set the SPISOMI0 pin. If a 32-bit write is performed, bit 11 will
have priority over bit 24.

0

Read: SPISOMIx pin is logic 0.
Write: Writing a 0 to this bit has no effect.

1

Read: SPISOMIx pin is logic 1.
Write: Logic 1 is placed on SPISOMIx pin, if it is in general-purpose output mode.

23-16

SIMOSETSPISIMOx data out set. This bit is only active when the SPISIMOx pin is configured as a generalpurpose output pin.
Bit 10 or bit 16 can be used to set the SPISIMO0 pin. If a 32-bit write is performed, bit 10 will
have priority over bit 16.
0

Read: SPISIMOx pin is logic 0.
Write: Writing a 0 to this bit has no effect.

1

Read: SPISIMOx pin is logic 1.
Write: Logic 1 is placed on SPISIMOx pin, if it is in general-purpose output mode.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

893

Control Registers

www.ti.com

Table 21-13. SPI Pin Control Register 4 (SPIPC4) Field Descriptions (continued)
Bit

Field

15-12

Reserved

11

SOMISET0

Value
0

Description
Reads return 0. Writes have no effect.
SPISOMI0 data out set. This pin is only active when the SPISOMI0 pin is configured as a generalpurpose output pin.

0

Read: SPISOMI0 pin is logic 0.
Write: Writing a 0 to this bit has no effect.

1

Read: SPISOMI0 pin is logic 1.
Write: Logic 1 is placed on SPISOMI0 pin, if it is in general-purpose output mode.

10

SIMOSET0SPISIMO0 data out set. This pin is only active when the SPISIMO0 pin is configured as a generalpurpose output pin.
0

Read: SPISIMO0 pin is logic 0.
Write: Writing a 0 to this bit has no effect.

1

Read: SPISIMO0 pin is logic 1.
Write: Logic 1 is placed on SPISIMO0 pin, if it is in general-purpose output mode.

9

CLKSETSPICLK data out set. This bit is only active when the SPICLK pin is configured as a generalpurpose output pin.
0

Read: SPICLK pin is logic 0.
Write: Writing a 0 to this bit has no effect.

1

Read: SPICLK pin is logic 1.
Write: Logic 1 is placed on SPICLK pin, if it is in general-purpose output mode.

8

ENASETSPIENA data out set. This bit is only active when the SPIENA pin is configured as a generalpurpose output pin.
0

Read: SPIENA pin is logic 0.
Write: Writing a 0 to this bit has no effect.

1

Read: SPIENA pin is logic 1.
Write: Logic 1 is placed on SPIENA pin, if it is in general-purpose O/P mode.

7-0

SCSSETSPICS data out set. This bit is only active when the SPICS pin is configured as a general-purpose
output pin. A value of 1 written to this bit sets the corresponding SCSDOUT bit to 1.
0

Read: SPICS pin is logic 0.
Write: Writing a 0 to this bit has no effect.

1

Read: SPICS pin is logic 1.
Write: Logic 1 is placed on SPICS pin, if it is in general-purpose output mode.

894

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

21.8.11 SPI Pin Control Register 5 (SPIPC5)
NOTE: Register bits vary by device
Register bits 31-24 and 23-16 of this register reflect the number of SIMO/SOMI data lines per
device. On devices with 8 data-line support, all of bits 31 to 16 are implemented. On devices
with less than 8 data lines, only a subset of these bits are available. Unimplemented bits
return 0 upon read and are not writable.

Figure 21-27. SPI Pin Control Register 5 (SPIPC5) [offset = 28h]
31

24

23

16

SOMICLR

SIMOCLR

R/W-U

R/W-U

15

11

10

9

8

Reserved

12

SOMICLR0

SIMOCLR0

CLKCLRENACLR

R-0

R/W-U

R/W-U

R/W-U

R/W-U

7

0
SCSCLR
R/W-U

LEGEND: R/W = Read/Write; R = Read only; U = Undefined; -n = value after reset

Table 21-14. SPI Pin Control Register 5 (SPIPC5) Field Descriptions
Bit

Field

31-24

SOMICLR

Value

Description
SPISOMIx data out clear. This pin is only active when the SPISOMIx pin is configured as a generalpurpose output pin.
Bit 11 or bit 24 can be used to set the SPISOMI0 pin. If a 32-bit write is performed, bit 11 will
have priority over bit 24.

0

Read: The current value on SOMIDOUTx is 0.
Write: Writing a 0 to this bit has no effect.

1

Read: The current value on SOMIDOUTx is 1.
Write: Logic 0 is placed on SPISOMIx pin if it is in general-purpose output mode.

23-16

SIMOCLRSPISIMOx data out clear. This bit is only active when the SPISIMOx pin is configured as a generalpurpose output pin.
Bit 10 or bit 16 can be used to set the SPISIMO0 pin. If a 32-bit write is performed, bit 10 will
have priority over bit 16.
0

Read: The current value on SOMODOUTx is 0.
Write: Writing a 0 to this bit has no effect.

1

Read: The current value on SOMODOUTx is 1.
Write: Logic 0 is placed on SPISIMIx pin if it is in general-purpose output mode.

15-12

Reserved

11

SOMICLR00

Reads return 0. Writes have no effect.
SPISOMI0 data out clear. This pin is only active when the SPISOMI0 pin is configured as a
general-purpose output pin.

0

Read: The current value on SPISOMI0 is 0.
Write: Writing a 0 to this bit has no effect.

1

Read: The current value on SPISOMI0 is 1.
Write: Logic 0 is placed on SPISOMI0 pin, if it is in general-purpose output mode.

10

SIMOCLR0SPISIMO0 data out clear. This pin is only active when the SPISIMO0 pin is configured as a
general-purpose output pin.
0

Read: The current value on SPISIMO0 is 0.
Write: Writing a 0 to this bit has no effect.

1

Read: The current value on SPISIMO0 is 1.
Write: Logic 0 is placed on SPISIMO0 pin, if it is in general-purpose output mode.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

895

Control Registers

www.ti.com

Table 21-14. SPI Pin Control Register 5 (SPIPC5) Field Descriptions (continued)
Bit

Field

9

CLKCLR

Value

Description
SPICLK data out clear. This bit is only active when the SPICLK pin is configured as a generalpurpose output pin.

0

Read: The current value on SPICLK is 0.
Write: Writing a 0 to this bit has no effect.

1

Read: The current value on SPICLK is 1.
Write: Logic 0 is placed on SPICLK pin, if it is in general-purpose output mode.

8

ENACLRSPIENA data out clear. This bit is only active when the SPIENA pin is configured as a generalpurpose output pin. A value of 1 written to this bit clears the corresponding ENABLEDOUT bit to 0.
0

Read: The current value on SPIENA is 0.
Write: Writing a 0 to this bit has no effect.

1

Read: The current value on SPIENA is 1.
Write: Logic 0 is placed on SPIENA pin, if it is in general-purpose output mode.

7-0

SCSCLRSPICS data out clear. This bit is only active when the SPICS pin is configured as a general-purpose
output pin.
0

Read: The current value on SCSDOUT is 0.
Write: Writing a 0 to this bit has no effect.

1

Read: The current value on SCSDOUT is 1.
Write: Logic 0 is placed on SPICS pin, if it is in general-purpose output mode.

21.8.12 SPI Pin Control Register 6 (SPIPC6)
NOTE: Register bits vary by device
Register bits 31-24 and 23-16 of SPIPC0 to SPIPC9 reflect the number of SIMO/SOMI datalines per device. On devices with 8 data-line support, all of bits 31 to 16 are implemented.
On devices with less than 8 data lines, only a subset of these bits are available.
Unimplemented bits return 0 upon read and are not writable.

Figure 21-28. SPI Pin Control Register 6 (SPIPC6) [offset = 2Ch]
31

24

23

16

SOMIPDRSIMOPDR

R/W-0

R/W-0

15

11

10

9

8

Reserved

12

SOMIPDR0SIMOPDR0

CLKPDR

ENAPDR

R-0

R/W-0

R/W-0

R/W-0

R/W-0

7

0
SCSPDR
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

896

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

Table 21-15. SPI Pin Control Register 6 (SPIPC6) Field Descriptions
Bit

Field

31-24

SOMIPDR

Value

Description
SPISOMIx open drain enable. This bit enables open drain capability for each SPISOMIx pin, if thefollowing conditions are met:
• SOMIDIRx = 1 (SPISOMIx pin is configured in GIO mode as an output pin)
• SOMIDOUTx = 1
Bit 11 or bit 24 can both be used to enable open-drain for SPISOMI0. If a 32-bit write is
performed, bit 11 will have priority over bit 24.

23-16

0

Output value on the SPISOMIx pin is logic 1.

1

Output pin SPISOMIx is in a high-impedance state.

SIMOPDRSPISIMOx open drain enable. This bit enables open drain capability for each SPISIMOx pin, if thefollowing conditions are met:
• SIMODIRx = 1 (SPISIMOx pin is configured in GIO mode as an output pin)
• SIMODOUTx = 1
Bit 10 or bit 16 can both be used to enable open-drain for SPISIMO0. If a 32-bit write is
performed, bit 10 will have priority over bit 16.

15-12

Reserved

11

SOMIPDR00

Output value on the SPISIMOx pin is logic 1.

1

Output pin SPISIMOx is in a high-impedance state.

0

Reads return 0. Writes have no effect.
SPISOMI0 open-drain enable. This bit enables open-drain capability for SPISOMI0, if the following
conditions are met.
• SPISOMI0 pin is configured in GIO mode as an output pin• Output value on SPISOMI0 pin is logic 1.

100

Output value on the SPISOMI0 pin is logic 1.

1

Output pin SPISOMI0 is in a high-impedance state.

SIMOPDR0SPISIMO0 open-drain enable. This bit enables open -drain capability for the SPISIMO0 pin, if thefollowing conditions are met.
• SPISIMO0 pin is configured in GIO mode as an output pin• Output value on SPISIMO0 pin is logic 1.

90

Output value on the SPISIMO0 pin is logic 1.

1

Output pin SPISIMO0 is in a high-impedance state.

CLKPDRSPICLK open drain enable. This bit enables open drain capability for the SPICLK pin, if thefollowing conditions are met:
• SPICLK pin is configured in GIO mode as an output pin• SPICLKDOUT = 1

80

Output value on the SPICLK pin is logic 1.

1

Output pin SPICLK is in a high-impedance state.

ENAPDRSPIENA pin open drain enable. This bit enables open drain capability for the SPIENA pin, if thefollowing conditions are met:
• SPIENA pin configured in GIO mode as an output pin• SPIENADOUT = 1

7-00

Output value on the SPIENA pin is logic 1.

1

Output pin SPIENA is in a high-impedance state.

SCSPDRSPICS open drain enable. This bit enables open drain capability for each SPICS pin, if the following
conditions are met:
• SPICS pin is configured in GIO mode as an output pin• SCSDOUT = 1

SPNU517C – March 2018
Submit Documentation Feedback0

Output value on the SPICS pin is logic 1.

1

Output pin SPICS is in a high-impedance state.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

897

Control Registers

www.ti.com

21.8.13 SPI Pin Control Register 7 (SPIPC7)
NOTE: Register bits vary by device
Register bits 31-24 and 23-16 of this register reflect the number of SIMO/SOMI data lines per
device. On devices with 8 data-line support, all of bits 31 to 16 are implemented. On devices
with less than 8 data lines, only a subset of these bits are available. Unimplemented bits
return 0 upon read and are not writable.

NOTE: Default Register Value
The default values of these register bits vary by device. See your device datasheet for
information about default pin states, which correspond to the register reset values (see thepin-list table).

Figure 21-29. SPI Pin Control Register 7 (SPIPC7) [offset = 30h]
31

24

23

16

SOMIDISSIMODIS

R/W-n

R/W-n

15

11

10

9

8

Reserved

12

SOMIPDIS0SIMOPDIS0

CLKPDIS

ENAPDIS

R-0

R/W-n

R/W-n

R/W-n

R/W-n

7

0
SCSPDIS
R/W-n

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-16. SPI Pin Control Register 7 (SPIPC7) Field Descriptions
Bit

Field

31-24

SOMIDIS

Value

Description
SPISOMIx pull control disable. This bit disables pull control capability for each SPISOMIx pin if it isin input mode, regardless of whether it is in functional or GIO mode.
Note: Bit 11 or bit 24 can be used to set pull-disable for SPISOMIO. If a 32-bit write is
performed, bit 11 will have priority over bit 24.

23-16

0

Pull control on the SPISOMIx pin is enabled.

1

Pull control on the SPISOMIx pin is disabled.

SIMODISSPISIMOx pull control disable. This bit disables pull control capability for the SPISIMOx pin if it is in
input mode, regardless of whether it is in functional or GIO mode.
Note: Bit 10 or bit 16 can be used to set pull-disable for SPISIMO0. If a 32-bit write is
performed, bit 10 will have priority over bit 16.

15-12

Reserved

11

SOMIPDIS0

10

898

0

Pull control on the SPISIMOx pin is enabled.

1

Pull control on the SPISIMOx pin is disabled.

0

Reads return 0. Writes have no effect.
SPISOMI0 pull control disable. This bit disables pull control capability for the pin SPISOMI0 pin if it
is in input mode, regardless of whether it is in functional or GIO mode.

0

Pull control on the SPISOMI0 pin is enabled.

1

Pull control on the SPISOMI0 pin is disabled.

SIMOPDIS0SPISIMO0 pull control disable. This bit disables pull control capability for the pin SPISIMO0 pin if it
is in input mode, regardless of whether it is in functional or GIO mode.
0

Pull control on the SPISIMO0 pin is enabled.

1

Pull control on the SPISIMO0 pin is disabled.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

Table 21-16. SPI Pin Control Register 7 (SPIPC7) Field Descriptions (continued)
Bit

Field

9

CLKPDIS

8

Value

SPICLK pull control disable. This bit disables pull control capability for the pin SPICLK pin if it is in
input mode, regardless of whether it is in functional or GIO mode.
0

Pull control on the SPICLK pin is enabled.

1

Pull control on the SPICLK pin is disabled.

ENAPDIS

7-0

Description

SPIENA pull control disable. This bit disables pull control capability for the pin SPIENA pin if it is in
input mode, regardless of whether it is in functional or GIO mode.
0

Pull control on the SPIENA pin is enabled.

1

Pull control on the SPIENA pin is disabled.

SCSPDISSPICS pull control disable. This bit disables pull control capability for each SPICS pin if it is in input
mode, regardless of whether it is in functional or GIO mode.
0

Pull control on the SPICS pin is enabled.

1

Pull control on the SPICS pin is disabled.

21.8.14 SPI Pin Control Register 8 (SPIPC8)
NOTE: Register bits vary by device
Register bits 31-24 and 23-16 of this register reflect the number of SIMO/SOMI data lines per
device. On devices with 8 data-line support, all of bits 31 to 16 are implemented. On devices
with less than 8 data lines, only a subset of these bits are available. Unimplemented bits
return 0 upon read and are not writable.

NOTE: Default Register Value
The default values of these register bits vary by device. See your device datasheet for
information about default pin states, which correspond to the register reset values (see thepin-list table).

Figure 21-30. SPI Pin Control Register 8 (SPIPC8) [offset = 34h]
31

24

23

16

SOMIPSELSIMOPSEL

R/W-n

R/W-n

15

11

10

9

8

Reserved

12

SOMIPSEL0

SIMOPSEL0

CLKPSEL

ENAPSEL

R-0

R/W-n

R/W-n

R/W-n

R/W-n

7

0
SCSPSEL
R/W-n

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-17. SPI Pin Control Register 8 (SPIPC8) Field Descriptions
Bit

Field

31-24

SOMIPSEL

Value

Description
SPISOMIx pull select. This bit selects the type of pull logic for each SPISOMIx pin.
Note: Bit 11 or bit 24 can be used to set pull-select for SPISOMI0. If a 32-bit write is
performed, bit 11 will have priority over bit 24.

SPNU517C – March 2018
Submit Documentation Feedback0

Pull down on the SPISOMIx pin.

1

Pull up on the SPISOMIx pin.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

899

Control Registers

www.ti.com

Table 21-17. SPI Pin Control Register 8 (SPIPC8) Field Descriptions (continued)
Bit

Field

23-16

SIMOPSEL

Value

Description
SPISIMOx pull select. This bit selects the type of pull logic for each SPISIMOx pin.
Note: Bit 10 or bit 16 can be used to set pull-select for SPISIMO0. If a 32-bit write is
performed, bit 10 will have priority over bit 16.

15-12

Reserved

11

SOMIPSEL0

10

9

8

7-0

0

Pull down on the SPISIMOx pin.

1

Pull up on the SPISIMOx pin.

0

Reads return 0. Writes have no effect.
SPISOMI0 pull select. This bit selects the type of pull logic at the SPISOMI0 pin.

0

Pull down on the SPISOMI0 pin.

1

Pull up on the SPISOMI0 pin.

SIMOPSEL0SPISIMO0 pull select. This bit selects the type of pull logic at the SPISIMO0 pin.
0

Pull down on the SPISIMO0 pin.

1

Pull up on the SPISIMO0 pin.

CLKPSELSPICLK pull select. This bit selects the type of pull logic at the SPICLK pin.
0

Pull down on the SPICLK pin.

1

Pull up on the SPICLK pin.

ENAPSELSPIENA pull select. This bit selects the type of pull logic at the SPIENA pin.
0

Pull down on the SPIENA pin.

1

Pull up on the SPIENA pin.

SCSPSELSPICS pull select. This bit selects the type of pull logic for each SPICS pin.
0

Pull down on the SPICS pin.

1

Pull up on the SPICS pin.

21.8.15 SPI Transmit Data Register 0 (SPIDAT0)
Figure 21-31. SPI Transmit Data Register 0 (SPIDAT0) [offset = 38h]
31

16
Reserved
R-0

150
TXDATA
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-18. SPI Transmit Data Register 0 (SPIDAT0) Field Descriptions
Bit

Field

Value

31-16

Reserved

0

15-0

TXDATA

0-FFFFh

Description
Reads return 0. Writes have no effect.
SPI transmit data. When written, these bits will be copied to the shift register if it is empty. If theshift register is not empty, TXBUF holds the written data. SPIEN (SPICGR1[24]) must be set to
1 before this register can be written to. Writing a 0 to the SPIEN register forces the lower 16 bitsof the SPIDAT0 to 0x00.
Note: When this register is read, the contents TXBUF, which holds the latest written data,
will be returned.
Note: Regardless of character length, the transmit word should be right-justified before
writing to the SPIDAT1 register.
Note: The default data format control register for SPIDAT0 is SPIFMT0. However, it ispossible to reprogram the DFSEL[1:0] fields of SPIDAT1 before using SPIDAT0, to selecta different SPIFMTx register.
Note: It is highly recommended to use SPIDAT1 register, SPIDAT0 is supported forcompatibility reasons.

900

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

21.8.16 SPI Transmit Data Register 1 (SPIDAT1)NOTE: Writing to only the control fields, bits 28 through 16, does not initiate any SPI transfer inmaster mode. This feature can be used to set up SPICLK phase or polarity before actually
starting the transfer by only updating the DFSEL bit field to select the required phase andpolarity combination.

Figure 21-32. SPI Transmit Data Register 1 (SPIDAT1) [offset = 3Ch]
31

29

28

27

26

Reserved

CSHOLD

Rsvd

WDEL

25

DFSEL

24

23
CSNR

16

R-0

R/W-0

R-0

R/W-0

R/W-0

R/W-0

15

0
TXDATA
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-19. SPI Transmit Data Register 1 (SPIDAT1) Field Descriptions
Bit

Field

31-29

Reserved

28

CSHOLD

27

Reserved

26

WDEL

Value
0

Description
Reads return 0. Writes have no effect.
Chip select hold mode. The CSHOLD bit is supported in master mode only in compatibility-mode of
SPI, (it is ignored in slave mode). CSHOLD defines the behavior of the chip select line at the end of adata transfer.

0

The chip select signal is deactivated at the end of a transfer after the T2CDELAY time has passed. If
two consecutive transfers are dedicated to the same chip select this chip select signal will bedeactivated for at least 2VCLK cycles before it is activated again.

1

The chip select signal is held active at the end of a transfer until a control field with new data andcontrol information is loaded into SPIDAT1. If the new chip select number equals the previous one,the active chip select signal is extended until the end of transfer with CSHOLD cleared, or until the
chip-select number changes.

0

Reads return 0. Writes have no effect.
Enable the delay counter at the end of the current transaction.
Note: The WDEL bit is supported in master mode only. In slave mode, this bit will be ignored.

0

No delay will be inserted. However, SPICS pins will still be de-activated for at least for 2VCLK cycles
if CSHOLD = 0.
Note: The duration for which the SPICS pin remains deactivated depends upon the time taken
to supply a new word after completing the shift operation. If TXBUF is already full, then the
SPICS pin will be deasserted for at least two VCLK cycles (if WDEL = 0).

1

25-24

23-16

DFSEL

CSNR

After a transaction, WDELAY of the corresponding data format will be loaded into the delay counter.
No transaction will be performed until the WDELAY counter overflows. The SPICS pins will be deactivated for at least (WDELAY + 2) × VCLK_Period duration.
Data word format select0Data word format 0 is selected.

1hData word format 1 is selected.

2hData word format 2 is selected.

3hData word format 3 is selected.

0-FFh

Chip select (CS) number. CSNR defines the chip select pins that will be activated during the datatransfer. CSNR is a bit-mask that controls all chip select pins. See Table 21-20.
Note: If your MibSPI has less than 8 chip select pins, all unused upper bits will be 0. For
example, the MiBSPI has 4 chip select pins, if you write FFh to CSNR, the actual number
stored in CSNR is 1Fh.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

901

Control Registers

www.ti.com

Table 21-19. SPI Transmit Data Register 1 (SPIDAT1) Field Descriptions (continued)
Bit

Field

Value

15-0

TXDATA

0-FFFFh Transfer data. When written, these bits are copied to the shift register if it is empty. If the shift
register is not empty, then they are held in TXBUF.

Description

SPIEN must be set to 1 before this register can be written to. Writing a 0 to SPIEN forces the lower
16 bits of SPIDAT1 to 0x0000.
A write to this register (or to the TXDATA field only) drives the contents of the CSNR field on the
SPICS pins, if the pins are configured as functional pins (automatic chip select, see Section 21.2).
When this register is read, the contents of TXBUF, that holds the latest data written, will be returned.
Note: Regardless of the character length, the transmit data should be right-justified before
writing to the SPIDAT1 register.

902 Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

Table 21-20. Chip Select Number Active
CSNR Value

Chip Select Active:
CS[3]

0h

CS[2]

CS[1]

CS[0]

No chip select pin is active.

1h

x

2h

x

3h

x

4h

x

5h

x

6h

x

x

x

x

7h
8h

x

9h

x

Ah

x

x
x
x
x

x

Bh

x

Ch

x

x

x

Dh

x

x

Eh

x

x

x

Fh

x

x

x

x
x
x

10h
11h

x

12h

x

13h

x

14h

x

15h

x

16h

x

x

17h

x

x

18h

x

19h

x

1Ah

x

x
x
x
x

1Bh

x

1Ch

x

x

1Dh

x

x

1Eh

x

x

x

1Fh

x

x

x

SPNU517C – March 2018
Submit Documentation Feedback

x

x

x
x
x

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

903

Control Registers

www.ti.com

21.8.17 SPI Receive Buffer Register (SPIBUF)
Figure 21-33. SPI Receive Buffer Register (SPIBUF) [offset = 40h]
31

30

29

28

27

26

25

24

RXEMPTY

RXOVR

TXFULL

BITERRDESYNCPARITYERRTIMEOUTDLENERR

R-1

R-0

R-0

R-0

R-0

R-0

R-0

R-0

23

16
LCSNR
R-0

15

0
RXDATA
R-0

LEGEND: R = Read only; -n = value after reset

Table 21-21. SPI Receive Buffer Register (SPIBUF) Field Descriptions
Bit

Field

31

RXEMPTY

Value

Description
Receive data buffer empty. When the host reads the RXDATA field or the entire SPIBUF register,
it automatically sets the RXEMPTY flag. When a data transfer is completed, the received data is
copied into RXDATA, and the RXEMPTY flag is cleared.

0

New data has been received and copied into the RXDATA.

1

No data has been received since the last read of RXDATA.
This flag gets set to 1 under the following conditions:• Reading the RXDATA portion of the SPIBUF register• Writing a 1 to clear the RXINTFLG bit in the SPI Flag Register (SPIFLG)
Write-clearing the RXINTFLG bit before reading the SPIBUF indicates the received data is being
ignored. Conversely, RXINTFLG can be cleared by reading the RXDATA portion of SPIBUF (orthe entire register).

30

RXOVR

Receive data buffer overrun. When a data transfer is completed and the received data is copied
into RXBUF while it is already full, RXOVR is set. Overruns always occur to RXBUF, not to
SPIBUF; the contents of SPIBUF are overwritten only after it is read by the Peripheral (VBUSP)
master (CPU or other host processor).
If enabled, the RXOVRN interrupt is generated when RXBUF is overwritten, and reading either SPI
Flag Register (SPIFLG) or SPIVECTx shows the RXOVRN condition. Two read operations fromthe SPIBUF register are required to reach the overwritten buffer word (one to read SPIBUF, whichthen transfers RXDATA into SPIBUF for the second read).
Note: This flag is cleared to 0 when the RXDATA field of the SPIBUF register is read.
Note: A special condition under which RXOVR flag gets set. If both SPIBUF and RXBUF are
already full and while another buffer receive is underway, if any errors such as TIMEOUT,
BITERR and DLEN_ERR occur, then RXOVR in RXBUF and SPI Flag Register (SPIFLG)
registers will be set to indicate that the status flags are getting overwritten by the newtransfer. This overrun should be treated like a normal receive overrun.

29

904

0

No receive data overrun condition occurred since last read of the data field.

1

A receive data overrun condition occurred since last read of the data field.

TXFULL

Transmit data buffer full. This flag is a read-only flag. Writing into the SPIDAT0 or SPIDAT1 field
while the TX shift register is full will automatically set the TXFULL flag. Once the word is copied tothe shift register, the TXFULL flag will be cleared. Writing to SPIDAT0 or SPIDAT1 when bothTXBUF and the TX shift register are empty does not set the TXFULL flag.
0

The transmit buffer is empty; SPIDAT0/SPIDAT1 is ready to accept a new data.

1

The transmit buffer is full; SPIDAT0/SPIDAT1 is not ready to accept new data.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

Table 21-21. SPI Receive Buffer Register (SPIBUF) Field Descriptions (continued)
Bit

Field

28

BITERR

Value

Description
Bit error. There was a mismatch of internal transmit data and transmitted data.
Note: This flag is cleared to 0 when the RXDATA field of the SPIBUF register is read.

27

0

No bit error occurred.

1

A bit error occurred. The SPI samples the signal of the transmit pins (master: SIMOx, slave:
SOMIx) at the receive point (one-half clock cycle after the transmit point). If the sampled value
differs from the transmitted value, a bit error is detected and the BITERR flag is set. Possible
reasons for a bit error include noise, an excessively high bit rate, capacitive load, or anothermaster/slave trying to transmit at the same time.

DESYNC

Desynchronization of slave device. This bit is valid in master mode only.
The master monitors the ENA signal coming from the slave device and sets the DESYNC flag if
ENA is deactivated before the last reception point or after the last bit is transmitted plus t T2EDELAY.
If DESYNCENA is set, an interrupt is asserted. Desynchronization can occur if a slave device
misses a clock edge coming from the master.
Note: In the Compatibility Mode MibSPI, under some circumstances it is possible for adesync error detected for the previous buffer to be visible in the current buffer. This isbecause the receive completion flag/interrupt is generated when the buffer transfer iscompleted. But desynchronization is detected after the buffer transfer is completed. So, if
the VBUS master reads the received data quickly when an RXINT is detected, then thestatus flag may not reflect the correct desync condition. In multi-buffer mode, the desync
flag is always assured to be for the current buffer.
Note: This flag is cleared to 0 when the RXDATA field of the SPIBUF register is read.

26

0

No slave desynchronization detected.

1

A slave device is desynchronized.

PARITYERR

Parity error. The calculated parity differs from the received parity bit.
If the parity generator is enabled (selected individually for each buffer) an even or odd parity bit isadded at the end of a data word. During reception of the data word, the parity generator calculates
the reference parity and compares it to the received parity bit. If a mismatch is detected, the
PARITYERR flag is set.
Note: This flag is cleared to 0 when the RXDATA field of the SPIBUF register is read.

250

No parity error detected.

1

A parity error occurred.

TIMEOUT

Time-out because of non-activation of SPIENA pin.
The SPI generates a time-out when the slave does not respond in time by activating the ENA
signal after the chip select signal has been activated. If a time-out condition is detected, thecorresponding chip select is deactivated immediately and the TIMEOUT flag is set. In addition, theTIMEOUT flag in the status field of the corresponding buffer and in the SPI Flag Register(SPIFLG) is set.
Note: This bit is valid only in master mode.
Note: This flag is cleared to 0 when the RXDATA field of the SPIBUF register is read.

24

0

No SPIENA pin time-out occurred.

1

An SPIENA signal time-out occurred.

DLENERR

Data length error flag.
Note: This flag is cleared to 0 when the RXDATA field of the SPIBUF register is read.
0

No data-length error has occurred.

1

A data length error has occurred.

23-16

LCSNR

0-FFh

Last chip select number. LCSNR in the status field is a copy of CSNR in the corresponding control
field. It contains the chip select number that was activated during the last word transfer.

15-0

RXDATA

0-FFFFh

SPI receive data. This is the received word, transferred from the receive shift-register at the end of
a transfer. Regardless of the programmed character length and the direction of shifting, thereceived data is stored right-justified in the register.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

905

Control Registers

www.ti.com

21.8.18 SPI Emulation Register (SPIEMU)
Figure 21-34. SPI Emulation Register (SPIEMU) [offset = 44h]
31

16
Reserved
R-8000h15

0
EMU_RXDATA
R-0

LEGEND: R = Read only; -n = value after reset

Table 21-22. SPI Emulation Register (SPIEMU) Field Descriptions
Bit

Field

Value

Description

31-16 Reserved

8000h

Reads return 0. Writes have no effect.

15-0

0-FFFFh

SPI receive data. The SPI emulation register is a mirror of the SPIBUF register. The only
difference between SPIEMU and SPIBUF is that a read from SPIEMU does not clear anyof the status flags.

EMU_RXDATA

21.8.19 SPI Delay Register (SPIDELAY)
Figure 21-35. SPI Delay Register (SPIDELAY) [offset = 48h]
31

24

23

16

C2TDELAY

T2CDELAY

R/W-0

R/W-0

15

8

7

0

T2EDELAY

C2EDELAY

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 21-23. SPI Delay Register (SPIDELAY) Field Descriptions
Bit

Field

Value

Description

31-24

C2TDELAY

0-FFh

Chip-select-active to transmit-start delay. See Figure 21-36 for an example. C2TDELAY is used
only in master mode. It defines a setup time (for the slave device) that delays the datatransmission from the chip select active edge by a multiple of VCLK cycles.
The setup time value is calculated as follows.
t C2TDELAY = (C2TDELAY + 2) × VCLK Period
Example: VCLK = 25 MHz -> VCLK Period = 40ns; C2TDELAY = 07h;
> t C2TDELAY = 360 ns
When the chip select signal becomes active, the slave has to prepare data transfer within 360 ns.
Note: If phase = 1, the delay between SPICS falling edge to the first edge of SPICLK will
have an additional 0.5 SPICLK period delay. This delay is as per the SPI protocol.

906

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

Table 21-23. SPI Delay Register (SPIDELAY) Field Descriptions (continued)
Bit

Field

Value

Description

23-16

T2CDELAY

0-FFh

Transmit-end-to-chip-select-inactive-delay. See Figure 21-37 for an example. T2CDELAY is used
only in master mode. It defines a hold time for the slave device that delays the chip selectdeactivation by a multiple of VCLK cycles after the last bit is transferred. The hold time value iscalculated as follows:
t T2CDELAY = (T2CDELAY +1) × VCLK Period
Example: VCLK = 25 MHz -> VCLK Period = 40ns; T2CDELAY = 03h;
> t T2CDELAY = 160 ns
After the last data bit (or parity bit) is being transferred the chip select signal is held active for 160
ns.
Note: If phase = 0, then between the last edge of SPICLK and rise-edge of SPICS there will
be an additional delay of 0.5 SPICLK period. This is as per the SPI protocol.
Both C2TDELAY and T2CDELAY counters do not have any dependency on the SPIENA pinvalue. Even if the SPIENA pin is asserted by the slave, the master will continue to delay the startof SPICLK until the C2TDELAY counter overflows.
Similarly, even if the SPIENA pin is deasserted by the slave, the master will continue to hold the
SPICS pins active until the T2CDELAY counter overflows. In this way, it is guaranteed that the
setup and hold times of the SPICS pins are determined by the delay timers alone. To achieve
better throughput, it should be ensured that these two timers are kept at the minimum possible
values.

15-8

T2EDELAY

0-FFh

Transmit-data-finished to ENA-pin-inactive time-out. T2EDELAY is used in master mode only. It
defines a time-out value as a multiple of SPI clock before SPIENA signal has to become inactive
and after SPICS becomes inactive. SPICLK depends on which data format is selected. If the slave
device is missing one or more clock edges, it becomes de-synchronized. In this case, although themaster has finished the data transfer, the slave is still waiting for the missed clock pulses and the
ENA signal is not disabled.
The T2EDELAY defines a time-out value that triggers the DESYNC flag, if the SPIENA signal is
not deactivated in time. The DESYNC flag is set to indicate that the slave device did not de-assert
its SPIENA pin in time to acknowledge that it received all bits of the sent word. See Figure 21-38
for an example of this condition.
Note: DESYNC is also set if the SPI detects a de-assertion of SPIENA before the end of thetransmission. The time-out value is calculated as follows:
tT2EDELAY = T2EDELAY/SPIclock
Example: SPIclock = 8 Mbit/s; T2EDELAY = 10h;
> t T2EDELAY = 2 µs
The slave device has to disable the ENA signal within 2, otherwise DESYNC is set and aninterrupt is asserted (if enabled).

7-0

C2EDELAY

0-FFh

Chip-select-active to ENA-signal-active time-out. C2EDELAY is used only in master mode and it
applies only if the addressed slave generates an ENA signal as a hardware handshake response.
C2EDELAY defines the maximum time between when the SPI activates the chip-select signal andthe addressed slave has to respond by activating the ENA signal. C2EDELAY defines a time-out
value as a multiple of SPI clocks. The SPI clock depends on whether data format 0 or data format
1 is selected. See Figure 21-39 for an example of this condition.
Note: If the slave device does not respond with the ENA signal before the time-out value isreached, the TIMEOUT flag in the SPIFLG register is set and a interrupt is asserted (ifenabled).
If a time-out occurs, the SPI clears the transmit request of the timed-out buffer, sets the TIMEOUT
flag for the current buffer, and continues with the transfer of the next buffer in the sequence that is
enabled.
The timeout value is calculated as follows: tC2EDELAY = C2EDELAY/SPIclock
Example: SPIclock = 8 Mbit/s; C2EDELAY = 30 h;> t C2EDELAY = 6 ms
The slave device has to activate the ENA signal within 6 ms after the SPI has activated the chip
select signal (SPICS), otherwise the TIMEOUT flag is set and an interrupt is asserted (if enabled).

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

907

Control Registers

www.ti.com

Figure 21-36. Example: t C2TDELAY= 8 VCLK Cycles
SPICS
SPICLKSPISOMIVCLK
tC2TDELAY

Figure 21-37. Example: t T2CDELAY= 4 VCLK Cycles
SPICS
SPICLKSPISOMIVCLK
tT2CDELAY

Figure 21-38. Transmit-Data-Finished-to-ENA-Inactive-Timeout
SPICS
SPIENASPICLKSPISOMItT2EDELAY

Figure 21-39. Chip-Select-Active-to-ENA-Signal-Active-Timeout
SPICS
SPIENASPICLKSPISOMItC2EDELAY

908

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

21.8.20 SPI Default Chip Select Register (SPIDEF)
Figure 21-40. SPI Default Chip Select Register (SPIDEF) [offset = 4Ch]
31

16
Reserved
R-0

15

8

7

0

Reserved

CSDEF

R-0

R/W-FFhLEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-24. SPI Default Chip Select Register (SPIDEF) Field Descriptions
Bit

Field

31-8

Reserved

7-0

CDEF

Value
0
0-FFh

Description
Reads return 0. Writes have no effect.
Chip select default pattern. Master-mode only.
The CSDEF bits are output to the SPICS pins when no transmission is being performed. It allows
you to set a programmable chip-select pattern that deselects all of the SPI slaves.

0

SPICS is cleared to 0 when no transfer is active.

1

SPICS is set to 1 when no transfer is active.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

909

Control Registers

www.ti.com

21.8.21 SPI Data Format Registers (SPIFMT)
Figure 21-41. SPI Data Format Registers (SPIFMT[3:0]) [offset = 5Ch-50h]
31

24
WDELAY
R/WP-0

23

22

21

20

19

18

17

16

PARPOLPARITYENAWAITENASHIFTDIRHDUPLEX_ENAx

DIS_CS_TIMERS

POLARITY

PHASE

R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0

7

5

15

8

4

0

PRESCALE

Reserved

CHARLEN

R/WP-0R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 21-25. SPI Data Format Registers (SPIFMT[3:0]) Field Descriptions
Bit

Field

31-24 WDELAY

Value

Description

0-FFh

Delay in between transmissions for data format x (x= 0,1,2,3).Idle time that will be appliedat the end of the current transmission if the bit WDEL is set in the current buffer. The
delay to be applied is equal to:
WDELAY × PVCLK + 2 × PVCLKP VCLK -> Period of VCLK.

23

22PARPOL

Parity polarity: even or odd. PARPOLx can be modified in privilege mode only. It can beused for data format x (x= 0,1,2,3).
0

An even parity flag is added at the end of the transmit data stream.

1

An odd parity flag is added at the end of the transmit data stream.

PARITYENA

Parity enable for data format x.
No parity generation/ verification is performed for this data format.

21

20

910

0

A parity bit is transmitted at the end of each transmitted word. At the end of a transfer theparity generator compares the received parity bit with the locally-calculated parity flag. If
the parity bits do not match the RXERR flag is set in the corresponding control field. The
parity type (even or odd) can be selected via the PARPOL bit.

1

Note: If an uncorrectable error flag is set in a slave-mode SPI, then the wrong parity
bit will be transmitted to indicate to the master that there has been some issue withthe data parity. The SOMI pins will be forced to transmit all 0s, and the parity bit willbe transmitted as 1 if even parity is selected and as 0 if odd parity is selected(using the PARPOLx bit of this register). This behavior occurs regardless of an
uncorrectable parity error on either TXRAM or RXRAM.

WAITENA

The master waits for the ENA signal from slave for data format x. WAITENA is valid inmaster mode only. WAITENA enables a flexible SPI network where slaves with ENA
signal and slaves without ENA signal can be mixed. WAITENA defines, for eachtransferred word, whether the addressed slave generates the ENA signal or not.
0

The SPI does not wait for the ENA signal from the slave and directly starts the transfer.

1

Before the SPI starts the data transfer it waits for the ENA signal to become low. If the
ENA signal is not pulled down by the addressed slave before the internal time-out counter(C2EDELAY) overflows, then the master aborts the transfer and sets the TIMEOUT error
flag.

SHIFTDIR

Shift direction for data format x. With bit SHIFTDIRx, the shift direction for data format x(x=0,1,2,3) can be selected.
0

MSB is shifted out first.

1

LSB is shifted out first.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

Table 21-25. SPI Data Format Registers (SPIFMT[3:0]) Field Descriptions (continued)
Bit

Field

19

HDUPLEX_ENAx

Value

Description
Half Duplex transfer mode enable for Data Format x. This bit controls the I/O function of
SOMI/SIMO lines for a specific requirement where in the case of Master mode, TX pin SIMO will act as an RX pin, and in the case of Slave mode, RX pin - SIMO will act as a
TX pin..

0

Normal Full Duplex transfer.

1

If MASTER = 1, SIMO pin will act as an RX pin (No TX possible). If MASTER = 0, SIMO
pin will act as a TX pin (No RX possible).
For all normal operations, HDUPLEX_ENAx bits should always remain ‘0’. It is intended
for the usage when the SIMO pin is used for both TX and RX operations at different times.

18

17

DIS_CS_TIMERS

Disable chip-select timers for this format.The C2TDELAY and T2CDELAY timers are by
default enabled for all the data format registers. Using this bit, these timers can bedisabled for a particular data format, if they are not required. When a master is handling
multiple slaves, with varied set-up hold requirement, the application can selectively
choose to include or not include the chip-select delay timers for any slaves.
0

Both C2TDELAY and T2CDELAY counts are inserted for the chip selects.

1

No C2TDELAY or T2CDELAY is inserted in the chip select timings.

POLARITY

SPI data format x clock polarity. POLARITYx defines the clock polarity of data format x.
The following restrictions apply when switching clock phase and/or polarity:• In 3-pin/4-pin with nENA pin configuration of a slave SPI, the clock phase and polarity
cannot be changed on-the-fly between two transfers. The slave should be reset andreconfigured if clock phase/polarity needs to be switched. In summary, SPI format
switching is not fully supported in slave mode.
• Even while using chip select pins, the polarity of SPICLK can be switched only while
the slave is not selected by a valid chip select. The master SPI should ensure thatwhile switching SPICLK polarity, it has deselected all of its slaves. Otherwise, theswitching of SPICLK polarity may be incorrectly treated as a clock edge by someslaves.

16

15-8

0

If POLARITYx is cleared to 0, the SPI clock signal is low-inactive, that is, before and after
data transfer the clock signal is low.

1

If POLARITYx is set to 1, the SPI clock signal is high-inactive, that is, before and after
data transfer the clock signal is high.

PHASE

SPI data format x clock delay. PHASEx defines the clock delay of data format x.
0

If PHASEx is cleared to 0, the SPI clock signal is not delayed versus the transmit/receive
data stream. The first data bit is transmitted with the first clock edge and the first bit isreceived with the second (inverse) clock edge.

1

If PHASEx is set to 1, the SPI clock signal is delayed by a half SPI clock cycle versus thetransmit/receive data stream. The first transmit bit has to output prior to the first clockedge. The master and slave receive the first bit with the first edge.

PRESCALE

SPI data format x prescaler. PRESCALEx determines the bit transfer rate of data format x
if the SPI is the network master. PRESCALEx is use to derive SPICLK from VCLK. If the
SPI is configured as slave, PRESCALEx does not need to be configured. The clock rate
for data format x can be calculated as:
BRFormatx = VCLK / (PRESCALEx + 1)
Note: When PRESCALEx is cleared to 0, the SPI clock rate defaults to VCLK/2.

7-5

Reserved

04-0

CHARLEN

0-1Fh

SPNU517C – March 2018
Submit Documentation Feedback

Reads return 0. Writes have no effect.
SPI data format x data-word length. CHARLENx defines the word length of data format x.
Legal values are 0x02 (data word length = 2 bit) to 10h (data word length = 16). Illegal
values, such as 00 or 1Fh are not allowed; their effect is indeterminate.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

911

Control Registers

www.ti.com

21.8.22 Interrupt Vector 0 (INTVECT0)NOTE: The TG interrupt is not available in MibSPI in compatibility mode. Therefore, there is no
possibility to access this register in compatibility mode.

Figure 21-42. Interrupt Vector 0 (NTVECT0) [offset = 60h]
31

16
Reserved
R-0

15

6

5

1

0

Reserved

INTVECT0SUSPEND0

R-0

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 21-26. Transfer Group Interrupt Vector 0 (INTVECT0)
Bit

Field

31-6

Reserved

5-1

INTVECT0Value
0

Description
Reads return 0. Writes have no effect.
INTVECT0. Interrupt vector for interrupt line INT0.
Returns the vector of the pending interrupt at interrupt line INT0. If more than one interrupt is
pending, INTVECT0 always references the highest prior interrupt source first.
Note:This field reflects the status of the SPIFLG register in vector format. Any updates to the
SPIFLG register will automatically cause updates to this field.

0Transfer group x (x = 0 to 15) has a pending interrupt. SUSPEND0 reflects the type of interrupt(suspended or finished).

11h

Error Interrupt pending. The lower half of SPIFLG contains more details about the type of error.

13h

The pending interrupt is a Receive Buffer Overrun interrupt.

12h

SPI mode: The pending interrupt is a Receive Buffer Full interrupt.
Mib mode: Reserved. This bit combination should not occur.

14h

SPI mode: The pending interrupt is a Transmit Buffer Empty interrupt.
Mib mode: Reserved. This bit combination should not occur.

All othervalues0

There is no pending interrupt.

1h + xSUSPEND0

SPI mode: Reserved. These bit combinations should not occur.
Transfer suspended / Transfer finished interrupt flag.
Every time INTVECT0 is read by the host, the corresponding interrupt flag of the referenced
transfer group is cleared and INTVECT0 is updated with the vector coming next in the priority
chain.

0

The interrupt type is a transfer finished interrupt. In other words, the buffer array referenced by
INTVECT0 has asserted an interrupt because all of data from the transfer group has beentransferred.

1

The interrupt type is a "transfer suspended" interrupt. In other words, the transfer group referenced
by INTVECT0 has asserted an interrupt because the buffer to be transferred next is in suspend-towait mode.

NOTE: Reading from the INTVECT0 register when Transmit Empty is indicated does not clear the
TXINTFLG flag in the SPI Flag Register (SPIFLG). Writing a new word to the SPIDATx
register clears the Transmit Empty interrupt.

912

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

NOTE: In multi-buffer mode, INTVECT0 contains the interrupt for the highest priority transfer group.
A read from INTVECT0 automatically causes the next-highest priority transfer group's
interrupt status to get loaded into INTVECT0 and its corresponding SUSPEND flag to getloaded into SUSPEND0. The transfer group with the lowest number has the highest priority,and the transfer group with the highest number has the lowest priority.
Reading the INTVECT0 register when the RXOVRN interrupt is indicated in multi-buffer
mode does not clear the RXOVRN flag and hence does not clear the vector. The RXOVRNinterrupt vector may be cleared in multi-buffer mode either by write-clearing the RXOVRNflag in the SPI Flag Register (SPIFLG) or by reading the RXRAM Overrun Buffer Address
Register (RXOVRN_BUF_ADDR).

21.8.23 Interrupt Vector 1 (INTVECT1)
NOTE: The TG interrupt is not available in SPI in compatibility mode compatibility mode. Therefore,
there is no possibility to access this register in compatibility mode.

Figure 21-43. Interrupt Vector 1 (INTVECT1) [offset = 64h]
31

16
Reserved
R-0

15

6

5

1

0

Reserved

INTVECT1SUSPEND1

R-0

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 21-27. Transfer Group Interrupt Vector 1 (INTVECT1)
Bit

Field

31-6

Reserved

5-1

INTVECT1

Value
0

Description
Reads return 0. Writes have no effect.
INTVECT1. Interrupt vector for interrupt line INT1.
Returns the vector of the pending interrupt at interrupt line INT1. If more than one interrupt is
pending, INTVECT1 always references the highest prior interrupt source first.
Note:This field reflects the status of the SPIFLG register in vector format. Any updates to the
SPIFLG register will automatically cause updates to this field.

0

There is no pending interrupt. SPI mode only.

11h

Error Interrupt pending. The lower half of SPIINT1 contains more details about the type of error.
SPI mode only.

13h

The pending interrupt is a Receive Buffer Overrun interrupt. SPI mode only.

12h

The pending interrupt is a Receive Buffer Full interrupt. SPI mode only.

14h

The pending interrupt is a Transmit Buffer Empty interrupt. SPI mode only.

All othervalues0

SUSPEND1

Reserved. These bit combinations should not occur. SPI mode only.
Transfer suspended / Transfer finished interrupt flag.
Every time INTVECT1 is read by the host, the corresponding interrupt flag of the referenced
transfer group is cleared and INTVECT1 is updated with the vector coming next in the priority
chain.

0

The interrupt type is a transfer finished interrupt. In other words, the buffer array referenced by
INTVECT1 has asserted an interrupt because all of data from the transfer group has beentransferred.

1

The interrupt type is a transfer suspended interrupt. In other words, the transfer group referenced
by INTVECT1 has asserted an interrupt because the buffer to be transferred next is in suspend-towait mode.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

913

Control Registers

www.ti.com

NOTE: Reading from the INTVECT1 register when Transmit Empty is indicated does not clear the
TXINTFLG flag in the SPI Flag Register (SPIFLG). Writing a new word to the SPIDATx
register clears the Transmit Empty interrupt.

NOTE: In multi-buffer mode, INTVECT1 contains the interrupt for the highest priority transfer group.
A read from INTVECT1 automatically causes the next-highest priority transfer group's
interrupt status to get loaded into INTVECT1 and its corresponding SUSPEND flag to getloaded into SUSPEND1. The transfer group with the lowest number has the highest priority,and the transfer group with the highest number has the lowest priority.
Reading the INTVECT1 register when the RXOVRN interrupt is indicated in multi-buffer
mode does not clear the RXOVRN flag and hence does not clear the vector. The RXOVRNinterrupt vector may be cleared in multi-buffer mode either by write-clearing the RXOVRNflag in the SPI Flag Register (SPIFLG) or by reading the RXRAM Overrun Buffer Address
Register (RXOVRN_BUF_ADDR).

914

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

21.8.24 SPI Pin Control Register 9 (SPIPC9)SPIPC9 only applies to SPI2.
Figure 21-44. SPI Pin Control Register 9 (SPIPC9) [offset = 68h]
31

25

24

23

17

16

Reserved

SOMISRS0

Reserved

SIMOSRS0

R-0

R/W-0

R-0

R/W-0

15

11

10

9

Reserved

12

SOMISRS0SIMOSRS0

CLKSRS

8
Reserved

0

R-0

R/W-0

R/W-0

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-28. SPI Pin Control Register 9 (SPIPC9) Field Descriptions
Bit

Field

31-25

Reserved

24

SOMISRS0Value
0

Description
Reads return the value that was last written. Writes have no effect.
SPI2 SOMI[0] slew control. This bit controls between the fast or slow slew mode.
Note: Duplicate Control Bits for SPI2 SOMI[0]. Bit 24 is not physically implemented. It is amirror of bit 11. Any write to bit 24 will be reflected on bit 11. When bit 24 and bit 11 aresimultaneously written, the value of bit 11 will control the SPI2 SOMI[0] pin. The read valueof bit 24 always reflects the value of bit 11.

23-17

Reserved

16

SIMOSRS00Fast mode is enabled; the normal output buffer is used for this pin.

1

Slow mode is enabled; slew rate control is used for this pin.

0

Reads return the value that was last written. Writes have no effect.
SPI2 SIMO[0] slew control. This bit controls between the fast or slow slew mode.
Note: Duplicate Control Bits for SPI2 SIMO[0]. Bit 16 is not physically implemented. It is amirror of bit 10. Any write to bit 16 will be reflected on bit 10. When bit 16 and bit 10 are
simultaneously written, the value of bit 10 will control the SPI2 SIMO[0] pin. The read valueof bit 16 always reflects the value of bit 10.

15-12

Reserved

11

SOMISRS0

10

9

8-0

0

Fast mode is enabled; the normal output buffer is used for this pin.

1

Slow mode is enabled; slew rate control is used for this pin.

0

Reads return 0. Writes have no effect.
SPI2 SOMI[0] slew control. This bit controls between the fast or slow slew mode.

0

Fast mode is enabled; the normal output buffer is used for this pin.

1

Slow mode is enabled; slew rate control is used for this pin.

SIMOSRS0

SPI2 SIMO[0] slew control. This bit controls between the fast or slow slew mode.
0

Fast mode is enabled; the normal output buffer is used for this pin.

1

Slow mode is enabled; slew rate control is used for this pin.

CLKSRS

Reserved

SPNU517C – March 2018
Submit Documentation Feedback

SPI2 CLK slew control. This bit controls between the fast or slow slew mode.
0

Fast mode is enabled; the normal output buffer is used for this pin.

1

Slow mode is enabled; slew rate control is used for this pin.

0

Reads return the value that was last written. Writes have no effect.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

915

Control Registers

www.ti.com

21.8.25 Multi-buffer Mode Enable Register (MIBSPIE)NOTE: Accessibility of Multi-Buffer RAM
The multi-buffer RAM is not accessible unless the MSPIENA bit set to 1. The only exception
to this is in test mode, where, by setting RXRAMACCESS to 1, the multi-buffer RAM can be
fully accessed for both read and write.

Figure 21-45. Multi-buffer Mode Enable Register (MIBSPIE) [offset = 70h]
31

17

16

Reserved

RXRAM_ACCESS

R-0

R/WP-015

1

0Reserved

MSPIENA

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 21-29. Multi-buffer Mode Enable Register (MIBSPIE) Field Descriptions
Bit

Field

31-17

Reserved

16

Value
0

RXRAM_ACCESS

Description
Reads return 0. Writes have no effect.
Receive-RAM access control. During normal operating mode of SPI, the receive data/status
portion of multi-buffer RAM is read-only. To enable testing of receive RAM, direct read/write
access is enabled by setting this bit.

0

The RX portion of multi-buffer RAM is not writable by the CPU.

1

The whole of multi-buffer RAM is fully accessible for read/write by the CPU.
Note: The RX RAM ACCESS bit remains 0 after reset and it should remain cleared to 0 at
all times, except when testing the RAM. SPI should be given a local reset by using thenRESET (SPIGCR0[0]) bit after RAM testing is performed so that the multi-buffer RAM
gets re-initialized.

15-1

Reserved

0

MSPIENA

0

Reads return 0. Writes have no effect.
Multi-buffer mode enable. After power-up or reset, MSPIENA remains cleared, which meansthat the SPI runs in compatibility mode by default. If multi-buffer mode is desired, this registershould be configured first after configuring the SPIGCR0 register. If MSPIENA is not set to 1,
the multi-buffer mode registers are not writable.

0

The SPI runs in compatibility mode, that is, in this mode the MibSPI is fully code-compliant tothe standard device SPI. No multi-buffered-mode features are supported.

1

The SPI is configured to run in multi-buffer mode.

NOTE: Accessibility of Registers
Registers from this offset address onwards are not accessible in SPI compatibility mode.
They are accessible only in the multi-buffer mode.

916

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

21.8.26 TG Interrupt Enable Set Register (TGITENST)
The register TGITENST contains the TG interrupt enable flags for transfer-finished and for transfersuspended events. Each of the enable bits in the higher half-word and the lower half-word of TGITENST
belongs to one TG.
The register map shown in Figure 21-46 and Table 21-30 represents a super-set device with the
maximum number of TGs (16) assumed. The actual number of bits available varies per device.
Figure 21-46. TG Interrupt Enable Set Register (TGITENST) [offset = 74h]
31

16
SETINTENRDY[15:0]
R/W-0

15

0
SETINTENSUS[15:0]
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 21-30. TG Interrupt Enable Set Register (TGITENST) Field Descriptions
Bit

Field

31-16

SETINTENRDY[n]Value

Description
TG interrupt set (enable) when transfer finished. Bit 16 corresponds to TG0, bit 17 corresponds
to TG1, and so on.

0

Read: The TGx-completed interrupt is disabled. This interrupt does not get generated whenTGx completes.
Write: A write of 0 to this bit has no effect.

1

Read: The TGx-completed interrupt is enabled. The interrupt gets generated when TGx
completes.
Write: Enable the TGx-completed interrupt. The interrupt gets generated when TGx completes.

15-0

SETINTENSUS[n]TG interrupt set (enabled) when transfer suspended. Bit 0 corresponds to TG0, bit 1
corresponds to TG1, and so on.
0

Read: The TGx-completed interrupt is disabled. This interrupt does not get generated whenTGx is suspended.
Write: A write of 0 to this bit has no effect.

1

Read: The TGx-completed interrupt is enabled. The interrupt gets generated when TGx issuspended.
Write: Enable the TGx-completed interrupt. The interrupt gets generated when TGx issuspended.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

917

Control Registers

www.ti.com

21.8.27 TG Interrupt Enable Clear Register (TGITENCR)
The register TGITENCR is used to clear the interrupt enables for the TG-completed interrupt and the TGsuspended interrupts.
The register map shown in Figure 21-47 and Table 21-31 represents a super-set device with the
maximum number of TGs (16) assumed. The actual number of bits available varies per device.
Figure 21-47. TG Interrupt Enable Clear Register (TGITENCR) [offset = 78h]
31

16
CLRINTENRDY[15:0]
R/W-0

15

0
CLRINTENSUS[15:0]
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 21-31. TG Interrupt Enable Clear Register (TGITENCR) Field Descriptions
Bit

Field

31-16

CLRINTENRDY[n]Value

Description
TG interrupt clear (disabled) when transfer finished. Bit 16 corresponds to TG0, bit 17
corresponds to TG1, and so on.

0

Read: The TGx-completed interrupt is disabled. This interrupt does not get generated whenTGx completes.
Write: A write of 0 to this bit has no effect.

1

Read: The TGx-completed interrupt is enabled. The interrupt gets generated when TGx
completes.
Write: Disable the TGx-completed interrupt. The interrupt does not get generated when TGx
completes.

15-0

CLRINTENSUS[n]TG interrupt clear (disabled) when transfer suspended. Bit 0 corresponds to TG0, bit 1
corresponds to TG1, and so on.
0

Read: The TGx-completed interrupt is disabled. This interrupt does not get generated whenTGx is suspended.
Write: A write of 0 to this bit has no effect.

1

Read: The TGx-completed interrupt is enabled. The interrupt gets generated when TGx issuspended.
Write: Disable the TGx-completed interrupt. The interrupt does not get generated when TGx issuspended.

918

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

21.8.28 Transfer Group Interrupt Level Set Register (TGITLVST)
The register TGITLVST sets the level of interrupts for transfer completed interrupt and for transfer
suspended interrupt to level 1.
The register map shown in Figure 21-48 andTable 21-32 represents a super-set device with the maximum
number of TGs (16) assumed. The actual number of bits available varies per device.
Figure 21-48. Transfer Group Interrupt Level Set Register (TGITLVST) [offset = 7Ch]
31

16
SETINTLVLRDY[15:0]
R/W-0

15

0
SETINTLVLSUS[15:0]
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 21-32. Transfer Group Interrupt Level Set Register (TGITLVST) Field Descriptions
Bit

Field

31-16

SETINTLVLRDY[n]Value

Description
Transfer-group completed interrupt level set. Bit 16 corresponds to TG0, bit 17 corresponds to
TG1, and so on.

0

Read: The TGx-completed interrupt is set to INT0.
Write: A write of 0 to this bit has no effect.

1

Read: The TGx-completed interrupt is set to INT1.
Write: Set the TGx-completed interrupt to INT1.

15-0

SETINTLVLSUS[n]Transfer-group suspended interrupt level set. Bit 0 corresponds to TG0, bit 1 corresponds to
TG1, and so on.
0

Read: The TGx-suspended interrupt is set to INT0.
Write: A write of 0 to this bit has no effect.

1

Read: The TGx-suspended interrupt is set to INT1.
Write: Set the TG-x suspended interrupt to INT1.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

919

Control Registers

www.ti.com

21.8.29 Transfer Group Interrupt Level Clear Register (TGITLVCR)
The register TGITLVCR clears the level of interrupts for transfer completed interrupt and for transfer
suspended interrupt to level 0.
The register map shown in Figure 21-49 and Table 21-33 represents a super-set device with the
maximum number of TGs (16) assumed. The actual number of bits available varies per device.
Figure 21-49. Transfer Group Interrupt Level Clear Register (TGITLVCR) [offset = 80h]
31

16
CLRINTLVLRDY[15:0]
R/W-0

15

0
CLRINTLVLSUS[15:0]
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 21-33. Transfer Group Interrupt Level Clear Register (TGITLVCR) Field Descriptions
Bit

Field

31-16

CLRINTLVLRDY[n]Value

Description
Transfer-group completed interrupt level clear. Bit 16 corresponds to TG0, bit 17 corresponds to
TG1, and so on.

0

Read: The TGx-completed interrupt is set to INT0.
Write: A write of 0 to this bit has no effect.

1

Read: The TGx-completed interrupt is set to INT1.
Write: Clear the TGx-completed interrupt to INT0.

15-0

CLRINTLVLSUS[n]Transfer group suspended interrupt level clear. Bit 0 corresponds to TG0, bit 1 corresponds to
TG1, and so on.
0

Read: The TGx-suspended interrupt is set to INT0.
Write: A write of 0 to this bit has no effect.

1

Read: The TGx-suspended interrupt is set to INT1.
Write: Clear the TG-x suspended interrupt to INT0.

920

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

21.8.30 Transfer Group Interrupt Flag Register (TGINTFLAG)The TGINTFLAG register comprises the transfer group interrupt flags for transfer-completed interrupts(INTFLGRDYx) and for transfer-suspended interrupts (INTFLGSUSx). Each of the interrupt flags in thehigher half-word and the lower half-word of TGINTFLAG belongs to one TG.
The register map shown in Figure 21-50 and Table 21-34 represents a super-set device with the
maximum number of TGs (16) assumed. The actual number of bits available varies per device.
Figure 21-50. Transfer Group Interrupt Flag Register (TGINTFLAG) [offset = 84h]
31

16
INTFLGRDY[15:0]
R/W1C-0

150
INTFLGSUS[15:0]
R/W1C-0

LEGEND: R/W = Read/Write; W1C = Write 1 to clear; -n = value after reset

Table 21-34. Transfer Group Interrupt Level Clear Register (TGITLVCR) Field Descriptions
Bit

Field

31-16

INTFLGRDY[
n]

Value

Description
Transfer-group interrupt flag for a transfer-completed interrupt. Bit 16 corresponds to TG0, bit 17
corresponds to TG1, and so on.
Note: Read Clear Behavior. Reading the interrupt vector registers TGINTVECT0 or TGINTVECT1
automatically clears the interrupt flag bit INTFLGRDYx referenced by the vector number given by
INTVECT0/INTVECT1 bits, if the SUSPEND[0:1] bit in the vector registers is 0.

0

Read: No transfer-completed interrupt occurred since last clearing of the INTFLGRDYx flag.
Write: A write of 0 to this bit has no effect.

1

Read: A transfer finished interrupt from transfer group x occurred. No matter whether the interrupt isenabled or disabled (INTENRDYx = don't care) or whether the interrupt is mapped to INT0 or INT1,
INTFLGRDYx is set right after the transfer from TGx is finished.
Write: The corresponding bit flag is cleared.

15-0

INTFLGSUS[
n]Transfer-group interrupt flag for a transfer-suspend interrupt. Bit 0 corresponds to TG0, bit 1
corresponds to TG1, and so on.
Note: Read Clear Behavior. Reading the interrupt vector registers TGINTVECT0 or TGINTVECT1
automatically clears the interrupt flag bit INTFLGSUSx referenced by the vector number given by
INTVECT0/INTVECT1 bits, if the SUSPEND[0:1] bit in the corresponding vector registers is 1.
0

Read: No transfer-suspended interrupt occurred since the last clearing of the INTFLGSUSx flag.
Write: A write of 0 to this bit has no effect.

1

Read: A transfer-suspended interrupt from TGx occurred. No matter whether the interrupt is enabled or
disabled (INTENSUSx = don't care) or whether the interrupt is mapped to INT0 or INT1, INTFLGSUSx
is set right after the transfer from transfer group x is suspended.
Write: The corresponding bit flag is cleared.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

921

Control Registers

www.ti.com

21.8.31 Tick Count Register (TICKCNT)One of the trigger sources for TGs is an internal periodic time trigger. This time trigger is called a tickcounter and is basically a down-counter with a preload/reload value. Every time the tick counter detects anunderflow it reloads the initial value and toggles the trigger signal provided to the TGs.
The trigger signal, shown in Figure 21-51 as a square wave, illustrates the different trigger event types for
the TGs (for example, rising edge, falling edge, and both edges).
Figure 21-51. Tick Counter Operation
Tick counter
Trigger signal
Counter reload

This register is shown in Figure 21-52 and described in Table 21-35.
Figure 21-52. Tick Count Register (TICKCNT) [offset = 90h]
31

30

TICKENARELOAD29

CLKCTRL

28

27
Reserved

16

R/W-0

R/S-0

R/W-0

R-0

15

0
TICKVALUE
R/W-0

LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset

Table 21-35. Tick Count Register (TICKCNT) Field Descriptions
Bit

Field

31

TICKENA

Value

Description
Tick counter enable.

0

The internal tick counter is disabled. The counter value remains unchanged.
Note: When the tick counter is disabled, the trigger signal is forced low.

1

30

RELOAD

The internal tick counter is enabled and is clocked by the clock source selected by CLKCTRL.
When TICKENA goes from 0 to 1, the tick counter is automatically loaded with the contents of
TICKVALUE.
Pre-load the tick counter. RELOAD is a set-only bit; writing a 1 to it reloads the tick counter withthe value stored in TICKVALUE. Reading RELOAD always returns a 0.
Note: When the tick counter is reloaded by the RELOAD bit, the trigger signal is not
toggled.

29-28

CLKCTRL

Tick counter clock source control. CLKCTRL defines the clock source that is used to clock theinternal tick counter.
0

SPICLK of data word format 0 is selected as the clock source of the tick counter.

1h

SPICLK of data word format 1 is selected as the clock source of the tick counter.

2h

SPICLK of data word format 2 is selected as the clock source of the tick counter.

3h

SPICLK of data word format 3 is selected as the clock source of the tick counter.
Reads return 0. Writes have no effect.

27-16

Reserved

0

15-0

TICKVALUE

0-FFFFh922

Initial value for the tick counter. TICKVALUE stores the initial value for the tick counter. The tickcounter is loaded with the contents of TICKVALUE every time an underflow condition occurs andevery time the RELOAD flag is set by the host.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

21.8.32 Last TG End Pointer (LTGPEND)
Figure 21-53. Last TG End Pointer (LTGPEND) [offset = 94h]
31

15

29

28

24

23

16

Reserved

TG_IN_SERVICE

Reserved

R-0

R-0

R-0

14

8

7

0

Rsvd

LPEND

Reserved

R-0

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-36. Last TG End Pointer (LTGPEND) Field Descriptions
Bit

Field

31-29

Reserved

28-24

TG_IN_SERVICE

Value
0

Description
Reads return 0. Writes have no effect.
The TG number currently being serviced by the sequencer. These bits indicate the current
TG that is being serviced. This field can generally be used for code debugging.

0

No TG is being serviced by the sequencer.

1h

TG0 is being serviced by the sequencer.

:

:

10h

TG15 is being serviced by the sequencer.
Note: The number of transfer groups varies by device.

11h-1Fh
23-15

Reserved

0

14-8

LPEND

0-7Fh

Invalid values.
Reads return 0. Writes have no effect.
Last TG end pointer. Usually the TG end address (PEND) is inherently defined by the startvalue of the starting pointer of the subsequent TG (PSTART). The TG ends one word
before the next TG starts (PEND[x] = PSTART[x+1] - 1). For a full configuration of MibSPI,
the last TG has no subsequent TG, that is, no end address is defined. Therefore, LPEND
has to be programmed to specify explicitly the end address of the last TG.
Note: When using all 8 transfer groups, program the LPEND bits to define the end of
the last transfer group. When using less than 8 transfer groups, leave the LPEND bits
programmed to point to the end of the buffer and create a dummy transfer group thatdefines the end of your last intentional transfer group and occupies all the remaining
buffer space.

7-0

Reserved

SPNU517C – March 2018
Submit Documentation Feedback0

Reads return 0. Writes have no effect.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

923

Control Registers

www.ti.com

21.8.33 TGx Control Registers (TGxCTRL)
Each TG can be configured by one dedicated control register. The following register description shows
one control register(x) that is identical for all TGs. For example, the control register for TG 2 is named
TG2CTRL and is located at base address + 98h + 4 × 2. The actual number of available control registers
varies by device.
Figure 21-54. MibSPI TG Control Registers (TGxCTRL) [offsets = 98h-D4h]
31

30

29

28

TGENA

ONESHOT

PRST

TGTD

Reserved

R/W-0

R/W-0

R/W-0

R-0

R-0

23

15

27

20

24

19

16

TRIGEVTTRIGSRC

R/W-0

R/W-0

14

8

7

6

0

Rsvd

PSTART

Rsvd

PCURRENT

R-0

R/W-0

R-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-37. TG Control Registers (TGxCTRL) Field Descriptions
Bit

Field

31

TGENA

Value

Description
TGx enable.
If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx) a group transfer is
initiated if no higher priority TG is in active transfer mode or if one or more higher-priority TGs arein transfer-suspend mode.
Disabling a TG while a transfer is ongoing will finish the ongoing word transfer but not the wholegroup transfer.

30

0TGx is disabled.

1

TGx is enabled.

ONESHOTx

29

Single transfer for TGx.
0

TGx initiates a transfer every time a trigger event occurs and TGENA is set.

1

A transfer from TGx will be performed only once (one shot) after a valid trigger event at the
selected trigger source. After the transfer is finished the TGENAx control bit will be cleared andtherefore no additional transfer can be triggered before the host enables the TG again. This one
shot mode ensures that after one group transfer the host has enough time to read the received
data and to provide new transmit data.

PRSTx

TGx pointer reset mode. Configures the way to resolve trigger events during an ongoing transfer.
This bit is meaningful only for level-triggered TGs. Edge-triggered TGs cannot be restarted before
their completion by another edge. The PRST bit will have no effect on this behavior.
Note: When the PRST bit is set, if the buffer being transferred at the time of a new trigger
event is a LOCK or CSHOLD buffer, then only after finishing those transfers, the TG will berestarted. This means that even if the TG is re-triggered, the TG will only be restarted after
finishing the transfer of the first non-LOCK or non-CSHOLD buffer.
This means that TX control fields such as LOCK and CSHOLD have higher priority over anythingelse. They have the capability to delay the restart of the TG even if it is re-triggered when PRST is1.

28

If a trigger event occurs during a transfer from TGx, the event is ignored and is not storedinternally. The TGx transfer has priority over additional trigger events.

1

The TGx pointer (PCURRENTx) will be reset to the start address (PSTARTx) when a valid trigger
event occurs at the selected trigger source while a transfer from the same TG is ongoing. Every
trigger event resets PCURRENTx no matter whether the concerned TG is in transfer mode or not.
The trigger events have priority over the ongoing transfer.

TGTDx

27-24

924

0

Reserved

TG triggered.
0

TGx has not been triggered or is no longer waiting for service.

1

TGx has been triggered and is either currently being serviced or waiting for servicing.

0

Reads return 0. Writes have no effect.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

Table 21-37. TG Control Registers (TGxCTRL) Field Descriptions (continued)
Bit

Field

23-20

TRIGEVTx

Value

Description
Type of trigger event. A level-triggered TG can be stopped by de-activating the level trigger.
However, the following restrictions apply.
• Once the transfer of a buffer with CSHOLD or LOCK bit set starts, deactivating the trigger level
does not stop the transfer until the sequencer completes the transfer of the next non-CSHOLD
or non-LOCK buffer in the same TG.
• Once the last buffer in a TG is pre-fetched, de-activating the trigger level does not stop thetransfer group until the last buffer transfer is completed. This means even if the trigger level isdeactivated at the beginning of the penultimate (one-before-last) buffer transfer, the sequencer
continues with the same TG until it is completed.

0

never

Never trigger TGx. This is the default value after reset.

1hrisingedge

A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a transfer for
TGx.

2h

fallingedge

A falling edge (1 to 0) at the selected trigger source (TRIGSRCx) initiates a transfer for
TGx.

3h

both
edges

Rising and falling edges at the selected trigger source (TRIGSRCx) initiates a transfer
for TGx.

4h

Rsvd

Reserved

5hhighactive

While the selected trigger source (TRIGSRCx) is at a logic high level (1) the grouptransfer is continued and at the end of one group transfer restarted at the beginning. If
the logic level changes to low (0) during an ongoing group transfer, the whole grouptransfer will be stopped.
Note: If ONESHOTx is set the transfer is performed only once.

6h

lowactive

7h

always

While the selected trigger source (TRIGSRCx) is at a logic low level (0) the grouptransfer is continued and at the end of one restarted at the beginning. If the logic levelchanges to high (1) during an ongoing group transfer, the whole group transfer will be
stopped.
Note: If ONESHOTx is set the transfer is performed only once.
A repetitive group transfer will be performed.
Note: By setting the TRIGSRC to 0, the TRIGEVT to 7h (ALWAYS), and the
ONESHOTx bit to 1, software can trigger this TG. Upon setting the TGENA bit, theTG is immediately triggered.
Note: If ONESHOTx is set the transfer is performed only once.

8h-Fh

SPNU517C – March 2018
Submit Documentation Feedback

Rsvd

Reserved

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

925

Control Registers

www.ti.com

Table 21-37. TG Control Registers (TGxCTRL) Field Descriptions (continued)
Bit

Field

19-16

TRIGSRCx

Value

Description
Trigger source. After reset, the trigger sources of all TGs are disabled.

0

Disabled

1h

EXT0

External trigger source 0. The actual source varies per device (for example, HET I/O
channel, event pin).

2h

EXT1

External trigger source 1. The actual source varies per device (for example, HET I/O
channel, event pin).

3h

EXT2

External trigger source 2. The actual source varies per device (for example, HET I/O
channel, event pin).

4h

EXT3

External trigger source 3. The actual source varies per device (for example, HET I/O
channel, event pin).

5h

EXT4

External trigger source 4. The actual source varies per device (for example, HET I/O
channel, event pin).

6h

EXT5

External trigger source 5. The actual source varies per device (for example, HET I/O
channel, event pin).

7h

EXT6

External trigger source 6. The actual source varies per device (for example, HET I/O
channel, event pin).

8h

EXT7

External trigger source 7. The actual source varies per device (for example, HET I/O
channel, event pin).

9h

EXT8

External trigger source 8. The actual source varies per device (for example, HET I/O
channel, event pin).

Ah

EXT9

External trigger source 9. The actual source varies per device (for example, HET I/O
channel, event pin).

Bh

EXT10

External trigger source 10. The actual source varies per device (for example, HET I/O
channel, event pin).

Ch

EXT11

External trigger source 11. The actual source varies per device (for example, HET I/O
channel, event pin).

Dh

EXT12

External trigger source 12. The actual source varies per device (for example, HET I/O
channel, event pin).

Eh

EXT13

External trigger source 13. The actual source varies per device (for example, HET I/O
channel, event pin).

TICK

Internal periodic event trigger. The tick counter can initiate periodic group transfers.

Fh
15

Reserved

014-8

PSTARTx

0-7Fh

Reads return 0. Writes have no effect.
TG start address. PSTARTx stores the start address of the corresponding TG. The corresponding
end address is inherently defined by the subsequent TG's start address minus one (PENDx[TGx] =PSTARTx[TGx+1] - 1). PSTARTx is copied into PCURRENTx when:• The TG is enabled• The end of the TG is reached during a transfer• A trigger event occurs while PRST is set to 1

7

Reserved

6-0

PCURRENTx

00-7Fh

Reads return 0. Writes have no effect.
Pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127) of
the buffer that corresponds to this TG. If the TG switches from active transfer mode to suspend towait, PCURRENTx contains the address of the currently suspended word. After the TG resumes
from suspend to wait mode, the next buffer will be transferred; that is, no buffer data is transferredbecause of suspend to wait mode.

NOTE: Register bits vary by device
TG0 has the highest priority and TG15 has the lowest priority. Under the following conditions
a lower priority TG cannot be interrupted by a higher priority TG.

1. When there is a CSHOLD or LOCK buffer, until the completion of the next buffertransfer which is a non-CSHOLD or non-LOCK buffer.
2. Once the last word in a TG is pre-fetched.

926

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

21.8.34 Multi-buffer RAM Uncorrectable Parity Error Control Register (UERRCTRL)
Figure 21-55. Multi-buffer RAM Uncorrectable Parity Error Control Register (UERRCTRL)[offset = 120h]
31

16
Reserved
R-0

15

9

8

7

4

3

0

Reserved

PTESTEN

Reserved

EDEN

R-0

R/WP-0R-0

R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 21-38. Multi-buffer RAM Uncorrectable Parity Error Control Register (UERRCTRL)
Field Descriptions
Bit

Field

31-9

Reserved

8

PTESTEN

7-4

Reserved

3-0

EDEN

Value
0

Description
Reads return 0. Writes have no effect.
Parity memory test enable. This bit maps the parity bits corresponding to multi-buffer RAM
locations into the peripheral RAM frame to make them accessible by the CPU. See
Section 21.10 for further details about parity memory testing.

0

Parity bits are not memory-mapped.

1

Parity bits are memory-mapped.

0

Reads return 0. Writes have no effect.
Error detection enable. These bits enable parity error detection.

5h
All other values

Parity error detection logic (default) is disabled.
Parity error detection logic is enabled.
Note: It is recommended to write a 1010 to enable error detection, to guard against a soft
error from disabling parity error detect.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

927

Control Registers

www.ti.com

21.8.35 Multi-buffer RAM Uncorrectable Parity Error Status Register (UERRSTAT)
Figure 21-56. Multi-buffer RAM Uncorrectable Parity Error Status Register (UERRSTAT)[offset = 124h]
31

16
Reserved
R-0

15

1

0

Reserved

2

EDFLG1

EDFLG0

R-0

R/W1C-0

R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset

Table 21-39. Multi-buffer RAM Uncorrectable Parity Error Status Register (UERRSTAT)
Field Descriptions
Bit

Field

31-2

Reserved

1

EDFLG1

Value
0

Description
Reads return 0. Writes have no effect.
Uncorrectable parity error detection flag. This flag indicates if a parity error occurred in the RXRAM.
Note: Reading the UERRADDR1 register clears the EDFLG1 bit.

0

Read: No error has occurred.
Write: Writing a 0 to this bit has no effect.

1

Read: An error was detected and the address is captured in the UERRADDR1 register.
Write: The bit is cleared to 0.

0

EDFLG0Uncorrectable parity error detection flag. This flag indicates if a parity error occurred in the TXRAM.
Note: Reading the UERRADDR0 register clears the EDFLG0 bit.
0

Read: No error has occurred.
Write: Writing a 0 to this bit has no effect.

1

Read: An error was detected and the address is captured in the UERRADDR0 register.
Write: The bit is cleared to 0.

928

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

21.8.36 RXRAM Uncorrectable Parity Error Address Register (UERRADDR1)
Figure 21-57. RXRAM Uncorrectable Parity Error Address Register (UERRADDR1) [offset = 128h]31

16
Reserved
R-0

15

10

9

0

Reserved

OVERADDR1

R-0

R/C-x

LEGEND: R = Read only; C = Clear; -n = value after reset

Table 21-40. RXRAM Uncorrectable Parity Error Address Register (UERRADDR1) Field Descriptions
Bit

Field

31-10

Reserved

9-0

OVERADDR1Value
0200h-3FFh

Description
Reads return 0. Writes have no effect.
Uncorrectable parity error address for RXRAM. This register holds the address where aparity error is generated while reading RXRAM. Only the CPU can read from RXRAM
locations. The address captured is byte-aligned. This error address is frozen from being
updated until it is read by the CPU. The offset address of RXRAM varies from 200h-3FFh.
The register does not clear its contents during or after module-level reset, system-level resetor even power-on reset.
A read operation to this register clears its contents to the default value 200h. After a poweron reset the contents will be unpredictable. A read operation can be performed after powerup to keep the register at its default value, if required. However, the contents of this registerare meaningful only when EDFLG1 is set to 1.
Note: A read of the UERRADDR1 register will clear EDFLG1 in the UERRSTAT register.
However, in emulation mode when the SUSPEND signal is high, a read from the
UERRADDR1 register does not clear EDFLG1.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

929

Control Registers

www.ti.com

21.8.37 TXRAM Uncorrectable Parity Error Address Register (UERRADDR0)
Figure 21-58. TXRAM Uncorrectable Parity Error Address Register (UERRADDR0) [offset = 12Ch]
31

16
Reserved
R-0

15

9

8

0

Reserved

UERRADDR0

R-0

R/C-x

LEGEND: R = Read only; C = Clear; -n = value after reset

Table 21-41. TXRAM Uncorrectable Parity Error Address Register (UERRADDR0) Field Descriptions
Bit

Field

31-9

Reserved

8-0

UERRADDR1

Value
00-1FFhDescription
Reads return 0. Writes have no effect.
Uncorrectable parity error address for TXRAM. This register holds the address where a parity
error is generated while reading from TXRAM. The TXRAM can be read either by CPU or by
the MibSPI sequencer logic for transmission. The address captured is byte- aligned. This error
address is frozen from being updated until it is read by the CPU. The offset address of TXRAM
varies from 0-1FFh.
The register does not clear its contents during or after module-level reset, system-level reset, oreven power-on reset.
A read operation to this register clears its contents to all 0s. After a power-on reset, thecontents of this register will be unpredictable. A read operation can be performed after powerup to clear the this register's contents, if required. However, the contents of this register are
meaningful only when EDFLG0 is set to 1.
Note: A read from the UERRADDR0 register will clear EDFLG0 in the UERRSTAT register.
However, in emulation mode when the SUSPEND signal is high, a read from the
UERRADDR0 register does not clear EDFLG0.

930

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

21.8.38 RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR)In multi-buffer mode, if a particular RXRAM location is written by the MibSPI sequencer logic after thecompletion of a new transfer when that location already contains valid data, the RX_OVR bit will be set to
1 while the data is being written. The RXOVRN_BUF_ADDR register captures the address of the RXRAM
location for which a receiver overrun condition occurred.
Figure 21-59. RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) [offset = 130h]
31

16
Reserved
R-0

15

10

9

0

Reserved

RXOVRN_BUF_ADDR

R-0

R-200hLEGEND: R = Read only; -n = value after reset

Table 21-42. RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) Field Descriptions
Bit

Field

31-10 Reserved
9-0

RXOVRN_BUF_ADDR

Value

Description

0

Reads return 0. Writes have no effect.

200h-3FCh

Address in RXRAM at which an overwrite occurred. This address value will show only
the offset address of the RAM location in the multi-buffer RAM address space. Referto the device-specific data sheet for the actual absolute address of RXRAM.
This word-aligned address can vary from 200h-3FCh. Contents of this register are
valid only when any of the INTVECT0 or INTVECT1 and SPIFLG registers show an
RXOVRN error vector while in multi-buffer mode. If there are multiple overrun errors,then this register holds the address of first overrun address until it is read.
Note: Reading this register clears the RXOVRN interrupt flag in the SPIFLG
register and the TGINTVECTx.
Note: Receiver overrun errors in multi-buffer mode can be completely avoided
by using the SUSPEND until RXEMPTY feature, which can be programmed into
each buffer of any TG. However, using the SUSPEND until RXEMPTY feature will
make the sequencer wait until the current RXRAM location is read by the VBUS
master before it can start the transfer for the same buffer location again. This
may affect the overall throughput of the SPI transfer. By enabling the interrupt
on RXOVRN in multi-buffer mode, the user can rely on interrupts to know if a
receiver overrun has occurred. The address of the overrun in RXRAM is
indicated in this RXOVRN_BUF_ADDR register.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

931

Control Registers

www.ti.com

21.8.39 I/O-Loopback Test Control Register (IOLPBKTSTCR)
This register controls test mode for I/O pins. It also controls whether loop-back should be digital or analog.
In addition, it contains control bits to induce error conditions into the module. These are to be used only formodule testing.
All of the control/status bits in this register are valid only when the IOLPBKTSTENA field is set to Ah.
Figure 21-60. I/O-Loopback Test Control Register (IOLPBKTSTCR) [offset = 134h]
31

25

23

21

24

Reserved

SCS_FAIL_
FLG

R-0

R/W1C-0

20

19

18

17

16

Reserved

CTRL_
BITERRCTRL_
DESYNCCTRL_
PARERRCTRL_
TIMEOUTCTRL_DLENERR

R-0

R/WP-0R/WP-0R/WP-0R/WP-0R/WP-0

12

11

15

7

6

8

Reserved

IOLPBKTSTENA

R-0

R/WP-02

1

0Reserved

5
ERR_SCS_PIN

3

CTRL_SCS_PIN_ERRLPBKTYPERXPENA

R-0

R/WP-0R/WP-0R/WP-0R/WP-0LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; WP = Write in privilege mode only; -n = value after reset

Table 21-43. I/O-Loopback Test Control Register (IOLPBKTSTCR) Field Descriptions
Bit

Field

31-25 Reserved
24

Value
0

SCS_FAIL_FLG

Description
Reads return 0. Writes have no effect.
Bit indicating a failure on SPICS pin compare during analog loopback.

0

Read: No miscompares occurred on any of the eight chip select pins (vs. the internal
chip select number CSNR during transfers).
Write: Writing a 0 to this bit has no effect.

1

Read: A comparison between the internal CSNR field and the analog looped-backvalue of one or more of the SPICS pins failed. A stuck-at fault is detected on one of
the SPICS. Comparison is done only on the pins that are configured as functional andduring transfer operation.
Write: This flag bit is cleared.

23-21 Reserved
20

19

18

17

932

0

CTRL_BITERR

Reads return 0. Writes have no effect.
Controls inducing of BITERR during I/O loopback test mode.

0

Do not interfere with looped-back data.

1

Induces bit errors by inverting the value of the incoming data during loopback.

CTRL_DESYNC

Controls inducing of the desync error during I/O loopback test mode.
0

Do not cause a desync error.

1

Induce a desync error by forcing the incoming SPIENA pin (if functional) to remain 0
even after the transfer is complete. This forcing will be retained until the kernel
reaches the idle state.

CTRL_PARERR

Controls inducing of the parity errors during I/O loopback test mode.
0

Do not cause a parity error.

1

Induce a parity error by inverting the polarity of the parity bit.

CTRL_TIMEOUT

Controls inducing of the timeout error during I/O loopback test mode.
0

Do not cause a timeout error.

1

Induce a timeout error by forcing the incoming SPIENA pin (if functional) to remain 1
when transmission is initiated. The forcing will be retained until the kernel reaches theidle state.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

Table 21-43. I/O-Loopback Test Control Register (IOLPBKTSTCR) Field Descriptions (continued)
Bit

Field

16

CTRL_DLENERR

Value

Description
Controls inducing of the data length error during I/O loopback test mode.

0

Do not cause a data-length error.

1

Induce a data-length error.
Master mode: The SPIENA pin (if functional) is forced to 1 when the module starts
shifting data.
Slave mode: The incoming SPICS pin (if functional) is forced to 1 when the module
starts shifting data.

15-12 Reserved
11-8

0

IOLPBKSTENA

Reads return 0. Writes have no effect.
Module I/O loopback test enable key.

Ah

Enable I/O loopback test mode.

All other values Disable I/O loopback test mode.
7-6

Reserved

5-3

ERR_SCS_PIN

0

Inject error on chip-select pin number x. The value in this field is decoded as thenumber of the chip select pin on which to inject an error. During analog loopback, if
CTRL SCS PIN ERR bit is set to 1, then the chip select pin selected by this field isforced to the opposite of its value in the CSNR.
0

Select SPICS[0] for injecting error.

1h

Select SPICS[1] for injecting error.

2h

Select SPICS[2] for injecting error.

3h

Select SPICS[3] for injecting error.

4h-7h
2

1

0

Reads return 0. Writes have no effect.

CTRL_SCS_PIN_ERR

Reserved
Enable/disable the injection of an error on the SPICS pins. The individual SPICS pins
can be chosen using the ERR SCS PIN field.

0

Disable the SPICS error-inducing logic.

1

Enable the SPICS error-inducing logic.

LPBKTYPE

Module I/O loopback type (analog/digital). See Figure 21-14 for the different types ofloopback modes.
0

Enable Digital loopback when IOLPBKTSTENA = 1010.

1

Enable Analog loopback when IOLPBKTSTENA = 1010.

RXPENA

Enable analog loopback through the receive pin.
Note: This bit is valid only when LPBK TYPE = 1, which chooses analog
loopback mode.

SPNU517C – March 2018
Submit Documentation Feedback0

Analog loopback is through the transmit pin.

1

Analog loopback is through the receive pin.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

933

Control Registers

www.ti.com

21.8.40 SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and
SPIFMT1)
This register provides an extended Prescale values for SPICLK generation to be able to interface withmuch slower SPI Slaves. This is an extension of SPIFMT0 and SPIFMT1 registers. For example,
EPRESCALE_FMT1[7:0] of EXTENDED_PRESCALE1 and PRESCALE1 of SPIFMT1 register will always
reflect the same contents. Similarly, EPRESCALE_FMT0[7:0] and PRESCALE0 of SPIFMT0 reflect thesame contents.
Figure 21-61. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and
SPIFMT1) [offset = 138h]
31

27

26

16

Reserved

EPRESCALE_FMT1

R-0

R/WP-0

15

11

10

0

Reserved

EPRESCALE_FMT0

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 21-44. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1) Field Descriptions
Bit

Field

31-27 Reserved
26-16 EPRESCALE_FMT1

Value
00-7FFhDescription
Reads return 0. Writes have no effect.
EPRESCALE_FMT1. Extended Prescale value for SPIFMT1. EPRESCALE_FMT1
determines the bit transfer rate of data format 1 if the SPI/MibSPI is the network
master. EPRESCALE_FMT1 is use to derive SPICLK from VCLK. If the SPI is
configured as slave, EPRESCALE_FMT1 does not need to be configured. These
EPRESCALE_FMT1[7:0] bits and PRESCALE1 bits of SPIFMT1 register will point tothe same physically implemented register. The clock rate for data format 1 can becalculated as:
BRFormat1 = VCLK / (EPRESCALE_FMT1 + 1)
Write: This register field should be written if a SPICLK prescaler of more VCLK/256 isrequired. This field provides a prescaler of up to VCLK/2048 for SPICLK. Writing tothis register field will also get reflected in the PRESCALE1 bits of SPIFMT1 register.
Read: Reading this field will reflect the PRESCALE value based on the last written
register field, that is, EXTENDED_PRESCALE1[26:16] or SPIFMT1[15:8] register.
Note: If Extended Prescaler is required, it should be ensured that
EXTENDED_PRESCALE1 register is programmed after SPIFMT1 register is
programmed. This is to ensure that the final SPICLK prescale value is controlled
by EXTENDED_PRESCALE1 register when a prescale of more 256 is intended
on SPICLK. Writing to PRESCALE1 field of SPIFMT1 will automatically clear
EPRESCALE_FMT1[10:8] bits to 000 so that the integrity of PRESCALE value ismaintained.

15-11 Reserved

934

0

Reads return 0. Writes have no effect.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

Table 21-44. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1) Field Descriptions (continued)
Bit

Field

Value

Description

10-0

EPRESCALE_FMT0

0-7FFhEPRESCALE_FMT0. Extended Prescale value for SPIFMT0. EPRESCALE_FMT0
determines the bit transfer rate of data format 0 if the SPI/MibSPI is the network
master. EPRESCALE_FMT0 is use to derive SPICLK from VCLK. If the SPI is
configured as slave, EPRESCALE_FMT0 does not need to be configured. These
EPRESCALE_FMT0[7:0] bits and PRESCALE0 bits of SPIFMT0 register will point tothe same physically implemented register. The clock rate for data format 0 can becalculated as:
BRFormat0 = VCLK / (EPRESCALE_FMT0 + 1)
Write: This register field should be written if a SPICLK prescaler of more VCLK/256 isrequired. This field provides a prescaler of up to VCLK/2048 for SPICLK. Writing tothis register field will also get reflected in the PRESCALE0 bits of SPIFMT0 register.
Read: Reading this field will reflect the PRESCALE value based on the last written
register field, that is, EXTENDED_PRESCALE0[10:0] or SPIFMT0[15:8] register.
Note: If Extended Prescaler is required, it should be ensured that
EXTENDED_PRESCALE1 register is programmed after SPIFMT0 register is
programmed. This is to ensure that the final SPICLK prescale value is controlled
by EXTENDED_PRESCALE1 register when a prescale of more 256 is intended
on SPICLK. Writing to PRESCALE0 field of SPIFMT0 will automatically clear
EPRESCALE_FMT0[10:8] bits to 000 so that the integrity of PRESCALE value ismaintained.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

935

Control Registers

www.ti.com

21.8.41 SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 andSPIFMT3)
This register provides an extended Prescale values for SPICLK generation to be able to interface withmuch slower SPI Slaves. This is an extension of SPIFMT2 and SPIFMT3 registers. For example,
EPRESCALE_FMT3[7:0] of EXTENDED_PRESCALE2 and PRESCALE3 of SPIFMT3 register will always
reflect the same contents. Similarly, EPRESCALE_FMT2[7:0] and PRESCALE2 of SPIFMT2 reflect thesame contents.
Figure 21-62. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 andSPIFMT3) [offset = 13Ch]
31

27

26

16

Reserved

EPRESCALE_FMT3

R-0

R/WP-0

15

11

10

0

Reserved

EPRESCALE_FMT2

R-0

R/WP-0LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 21-45. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2) Field Descriptions
Bit

Field

31-27

Reserved

26-16

EPRESCALE_FMT3

Value
00-7FFhDescription
Reads return 0. Writes have no effect.
EPRESCALE_FMT3. Extended Prescale value for SPIFMT3. EPRESCALE_FMT3
determines the bit transfer rate of data format 3 if the SPI/MibSPI is the network
master. EPRESCALE_FMT3 is use to derive SPICLK from VCLK. If the SPI is
configured as slave, EPRESCALE_FMT3 does not need to be configured. These
EPRESCALE_FMT3[7:0] bits and PRESCALE3 bits of SPIFMT3 register will point tothe same physically implemented register. The clock rate for data format 1 can becalculated as:
BRFormat3 = VCLK / (EPRESCALE_FMT3 + 1)
Write: This register field should be written if a SPICLK prescaler of more VCLK/256 isrequired. This field provides a prescaler of up to VCLK/2048 for SPICLK. Writing tothis register field will also get reflected in the PRESCALE3 bits of SPIFMT3 register.
Read: Reading this field will reflect the PRESCALE value based on the last written
register field, that is, EXTENDED_PRESCALE3[26:16] or SPIFMT3[15:8] register.
Note: If Extended Prescaler is required, it should be ensured that
EXTENDED_PRESCALE2 register is programmed after SPIFMT3 register is
programmed. This is to ensure that the final SPICLK prescale value iscontrolled by EXTENDED_PRESCALE2 register when a prescale of more 256 isintended on SPICLK. Writing to PRESCALE3 field of SPIFMT3 will automatically
clear EPRESCALE_FMT3[10:8] bits to 000 so that the integrity of PRESCALE
value is maintained.

15-11

Reserved

0

Reads return 0. Writes have no effect.

936

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackControl Registers

www.ti.com

Table 21-45. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2) Field Descriptions (continued)
Bit

Field

Value

Description

10-0

EPRESCALE_FMT2

0-7FFhEPRESCALE_FMT2. Extended Prescale value for SPIFMT2. EPRESCALE_FMT2
determines the bit transfer rate of data format 2 if the SPI/MibSPI is the network
master. EPRESCALE_FMT2 is use to derive SPICLK from VCLK. If the SPI is
configured as slave, EPRESCALE_FMT2 does not need to be configured. These
EPRESCALE_FMT2[7:0] bits and PRESCALE2 bits of SPIFMT2 register will point tothe same physically implemented register. The clock rate for data format 0 can becalculated as:
BRFormat2 = VCLK / (EPRESCALE_FMT2 + 1)
Write: This register field should be written if a SPICLK prescaler of more VCLK/256 isrequired. This field provides a prescaler of up to VCLK/2048 for SPICLK. Writing tothis register field will also get reflected in the PRESCALE2 bits of SPIFMT2 register.
Read: Reading this field will reflect the PRESCALE value based on the last written
register field, that is, EXTENDED_PRESCALE2[10:0] or SPIFMT2[15:8] register.
Note: If Extended Prescaler is required, it should be ensured that
EXTENDED_PRESCALE2 register is programmed after SPIFMT2 register is
programmed. This is to ensure that the final SPICLK prescale value iscontrolled by EXTENDED_PRESCALE2 register when a prescale of more 256 isintended on SPICLK. Writing to PRESCALE2 field of SPIFMT2 will automatically
clear EPRESCALE_FMT2[10:8] bits to 000 so that the integrity of PRESCALE
value is maintained.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

937

Multi-Buffer RAM

www.ti.com

21.9 Multi-Buffer RAM
The multi-buffer RAM is used for holding transit & received data, control and status information. The multibuffer RAM contains two banks of up to 128 32-bit words for a maximum configuration. One bank
(TXRAM) contains entries for transmit data (replicating the SPIDAT1 register). The other bank (RXRAM)
contains received data (replicating the SPIBUF register). The buffers can be partitioned into multiple TGs,
each containing a programmable number of buffers. Each of the buffers can be subdivided into 16-bit
transmit field, 16-bit receive field, 16-bit control field, and 16-bit status field, as displayed in Figure 21-63.
A 4-bit parity field per word is also included in each bank of RAM.
Figure 21-63. Multi-Buffer RAM Configuration
TXRAM Bank
35

Buffer 0
1
2
3
...
126
127

RXRAM Bank

32 31
16 15
Control0
Transmit0
Parity0
Parity1
Control1
Transmit1
Parity2Control2
Transmit2
Parity3Control3
Transmit3

Parity126
Parity127

Control126
Control127

Transmit126
Transmit127

Optional

0 35
Parity0
Parity1
Parity2
Parity332 31

Parity126
Parity127

16 15

Status0
Status1
Status2
Status3

Receive0
Receive1
Receive2
Receive3

Status126
Status127

Receive126
Receive127

0

Optional

All fields can be read and written with 8-bit, 16-bit, or 32-bit accesses.
The transmit fields can be written and read in the address range 000h to 1FFh. The transmit words
contain data and control fields.
The receive RAM fields are read-only and can be accessed through the address range 200h to 3FCh. The
receive words contain data and status fields.
The chip select number bit field CSNR[7:0] of the control field for a given word is mirrored into thecorresponding receive-buffer status field after transmission.
The Parity is automatically calculated and copied to Parity location
NOTE: Please refer to the specific device datasheet for the actual number of transmit and receive
buffers.
Write to unimplemented buffer is overwriting the corresponding implemented buffer. In
MIBSPI, if the RAM SIZE specified is 32 buffers, write to 33rd buffer overwrites 1st buffer,
write to 34th buffer overwrites 2st buffer and so on.

938

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffer RAM

www.ti.com

21.9.1 Multi-Buffer RAM Auto Initialization
When the MIBSPI is out of reset mode, auto initialization of multi-buffer RAM starts. The application code
must check for BUFINITACTIVE bit to be 0 (Multi-buffer RAM initialization is complete) before configuringmulti-buffer RAM.
Besides the default auto initialization after reset, the auto-initialization sequence can also be done by:
1. Enable the global hardware memory initialization key by programming a value of 1010b to the bits [3:0]of the MINITGCR register of the System module.
2. Set the control bit for the multi-buffer RAM in the MSINENA System module register. This bit is devicespecific for each memory that support auto-initialization. Please refer to the device datasheet to identify
the control bit for the multi-buffer RAM. This starts the initialization process. The BUFINITACTIVE bit
will get set to reflect that the initialization is ongoing.
3. When the memory initialization is completed, the corresponding status bit in the MINISTAT register will
be set. Also, the BUFINITACTIVE bit will get cleared.
4. Disable the global hardware memory initialization key by programming a value of 0101 to the bits [3:0]of the MINITGCR register of the System module.
Please refer to the Architecture User Guide for more details on the memory auto-initialization process.
NOTE: During Auto Initialization process, all the Multi-buffer mode registers (except MIBSPIE) will
be reset to their default values. So, it should be ensured that Auto Initialization is completed
before configuring the Multi-buffer mode registers.

21.9.2 Multi-buffer RAM Register Summary
This section describes the Multi-buffer RAM control and transmit-data fields of each word of TXRAM, andthe status and receive-data fields of each word of RXRAM. The base address for multi-buffer RAM is
FF0E 0000h for MibSPI1 RAM.
Table 21-46. Multi-buffer RAM Register Summary
OffsetAcronym

Register Description

Base + 000h-1FFh

TXRAM

Multi-buffer RAM Transmit Data Register

Section 21.9.3

Base + 200h-3FFh

RXRAM

Multi-buffer RAM Receive Buffer Register

Section 21.9.4

SPNU517C – March 2018
Submit Documentation Feedback

SectionMulti-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

939

Multi-Buffer RAM

www.ti.com

21.9.3 Multi-buffer RAM Transmit Data Register (TXRAM)
Each word of TXRAM is a transmit-buffer register.
NOTE: Writing to only the control fields, bits 28 through 16, does not initiate any SPI transfer inmaster mode. This feature can be used to set up SPICLK phase or polarity before actually
starting the transfer by only updating the DFSEL bit field to select the required phase andpolarity combination.

Figure 21-64. Multi-buffer RAM Transmit Data Register (TXRAM)[offset = Base + 000h-1FFh]
31

28

27

26

BUFMODE29

CSHOLD

LOCK

WDEL

25

DFSEL

24

23
CSNR

16

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

15

0
TXDATA
R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 21-47. Multi-buffer RAM Transmit Data Register (TXRAM) Field Descriptions
Bit

Field

31-29

BUFMODE

Value

Description
Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word.
When one of the "skip" modes is selected, the sequencer checks the buffer status every time it
reads from this buffer. If the current buffer status (TXFULL, RXEMPTY) does not match, the buffer
is skipped without a data transfer.
When one of the "suspend" modes is selected, the sequencer checks the buffer status when it
reads from this buffer. If TXFULL and/or RXEMPTY do not match, the sequencer waits until amatch occurs. No data transfer is initiated until the status condition of this buffer changes.

28

940

0

disabled. The buffer is disabled

1hskip single-transfer mode. Skip this buffer until the corresponding TXFULL flag is set (newtransmit data is available).

2hskip overwrite-protect mode. Skip this buffer until the corresponding RXEMPTY flag is set (newreceive data can be stored in RXDATA without data loss).

3h

skip single-transfer overwrite-protect mode. Skip this buffer until both of the corresponding
TXFULL and RXEMPTY flags are set. (new transmit data available and previous data received by
the host).

4h

continuous mode. Initiate a transfer each time the sequencer checks this buffer. Data words are
retransmitted if the buffer has not been updated. Receive data is overwritten, even if it has notbeen read.

5hsuspend single-transfer mode. Suspend-to-wait until the corresponding TXFULL flag is set (thesequencer stops at the current buffer until new transmit data is written in the TXDATA field).

6hsuspend overwrite-protect mode. Suspend-to-wait until the corresponding RXEMPTY flag is set(the sequencer stops at the current buffer until the previously-received data is read by the host.

7hsuspend single-transfer overwrite-protect mode. Suspend-to-wait until the corresponding
TXFULL and RXEMPTY flags are set (the sequencer stops at the current buffer until new transmit
data is written into the TXDATA field and the previously-received data is read by the host).

CSHOLD

Chip select hold mode. The CSHOLD bit is supported in master mode only, it is ignored in slavemode. CSHOLD defines the behavior of the chip select line at the end of a data transfer.
0

The chip select signal is deactivated at the end of a transfer after the T2CDELAY time has passed.
If two consecutive transfers are dedicated to the same chip select this chip select signal will bedeactivated for at least 2VCLK cycles before it is activated again.

1

The chip select signal is held active at the end of a transfer until a control field with new data andcontrol information is loaded into SPIDAT1. If the new chip select number equals the previous one,the active chip select signal is extended until the end of transfer with CSHOLD cleared, or until the
chip-select number changes.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffer RAM

www.ti.com

Table 21-47. Multi-buffer RAM Transmit Data Register (TXRAM) Field Descriptions (continued)
Bit

Field

27

LOCK

26

Value

Description
Lock two consecutive buffer words. Do not allow interruption by TGs with higher priority.

0

Any higher-priority TG can begin at the end of the current transaction.

1

A higher-priority TG cannot occur until after the next unlocked buffer word is transferred.

WDEL

Enable the delay counter at the end of the current transaction.
Note: The WDEL bit is supported in master mode only. In slave mode, this bit is ignored.
0

No delay will be inserted. However, SPICS pins will still be de-activated for at least for 2VCLK
cycles if CSHOLD = 0.
Note: The duration for which the SPICS pin remains deactivated also depends upon the time
taken to supply a new word after completing the shift operation (in compatibility mode). If
TXBUF is already full, then the SPICS pin will be deasserted for at least two VCLK cycles (ifWDEL = 0).

1

25-24

23-16

DFSEL

CSNR

After a transaction, WDELAY of the corresponding data format will be loaded into the delay
counter. No transaction will be performed until the WDELAY counter overflows. The SPICS pins
will be de-activated for at least (WDELAY + 2) × VCLK_Period duration.
Data word format select.

0

Data word format 0 is selected.

1hData word format 1 is selected.

2hData word format 2 is selected.

3hData word format 3 is selected.

0-FFh

Chip select (CS) number. CSNR defines the chip select pins that will be activated during the datatransfer. CSNR is a bit-mask that controls all chip select pins. See Table 21-48.
Note: If your MibSPI has less than 8 chip select pins, all unused upper bits will be 0. For
example, the MiBSPI has 4 chip select pins, if you write FFh to CSNR, the actual number
stored in CSNR is 1Fh.

15-0

TXDATA

0-7FFFh Transfer data. When written, these bits are copied to the shift register if it is empty. If the shift
register is not empty, then they are held in TXBUF.
SPIEN must be set to 1 before this register can be written to. Writing a 0 to SPIEN forces the lower
16 bits of TXDATA to 0.
A write to this register (or to the TXDATA field only) drives the contents of the CSNR field on the
SPICS pins, if the pins are configured as functional pins (automatic chip select, see Section 21.2).
When this register is read, the contents of TXBUF, which holds the latest data written, will be
returned.
Note: Regardless of the character length, the transmit data should be right-justified before
writing to the SPIDAT1 register.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI) 941
Copyright © 2018, Texas Instruments Incorporated

Multi-Buffer RAM

www.ti.com

Table 21-48. Chip Select Number Active
CSNR Value

Chip Select Active:
CS[3]

CS[2]

0h

CS[1]

CS[0]

No chip select pin is active.

1h

x

2h

x

3h

x

4h

x

5h

x

6h

x

x

x

x

7h
8h

x

9h

x

Ah

x

x
x
x
x

x

Bh

x

Ch

x

x

x

Dh

x

x

Eh

x

x

x

Fh

x

x

x

x
x
x

10h
11h

x

12h

x

13h

942

x

14h

x

15h

x

16h

x

x

17h

x

x

18h

x

19h

x

1Ah

x

x
x
x
x

x

1Bh

x

1Ch

x

x

x

1Dh

x

x

1Eh

x

x

x

1Fh

x

x

x

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporatedxx
x

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffer RAM

www.ti.com

21.9.4 Multi-buffer RAM Receive Buffer Register (RXRAM)
Each word of RXRAM is a receive-buffer register.
Figure 21-65. Multi-buffer RAM Receive Buffer Register (RXRAM)[offset = RAM Base + 200h-3FFh]
31

30

29

28

27

26

25

24

RXEMPTY

RXOVR

TXFULL

BITERRDESYNCPARITYERRTIMEOUTDLENERR

RS-1

RC-0

R-0

RC-0

RC-0

RC-0

RC-0

RC-0

23

16
LCSNR
R-0

15

0
RXDATA
R/W-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; S = Set; -n = value after reset

Table 21-49. Multi-buffer Receive Buffer Register (RXRAM) Field Descriptions
Bit

Field

31

RXEMPTY

Value

Description
Receive data buffer empty.When the host reads the RXDATA field or the entire RXRAM register, it
automatically sets the RXEMPTY flag. When a data transfer is completed, the received data is
copied into RXDATA, and the RXEMPTY flag is cleared.

0

New data has been received and copied into RXDATA.

1

No data has been received since the last read of RXDATA.
This flag gets set to 1 under the following conditions:• Reading the RXDATA portion of the RXRAM register• Writing a 1 to clear the RXINTFLG bit in the SPI Flag Register (SPIFLG)
Write-clearing the RXINTFLG bit before reading RXDATA indicates the received data is being
ignored. Conversely, RXINTFLG can be cleared by reading the RXDATA portion of RXRAM (orthe entire register).

30

RXOVR

Receive data buffer overrun. When a data transfer is completed and the received data is copied
into RXBUF while it is already full, RXOVR is set. Overruns always occur to RXBUF, not to
RXRAM; the contents of RXRAM are overwritten only after it is read by the Peripheral (VBUSP)
master (CPU or other host processor).
If enabled, the RXOVRN interrupt is generated when RXBUF is overwritten, and reading either SPI
Flag Register (SPIFLG) or SPIVECTx shows the RXOVRN condition. Two read operations fromthe RXRAM register are required to reach the overwritten buffer word (one to read RXRAM, whichthen transfers RXDATA into RXRAM for the second read).
Note: This flag is cleared to 0 when the RXDATA field of the SPIBUF register is read.
Note: A special condition under which RXOVR flag gets set. If both RXRAM and RXBUF are
already full and while another buffer receive is underway, if any errors such as TIMEOUT,
BITERR and DLEN_ERR occur, then RXOVR in RXBUF and SPI Flag Register (SPIFLG)
registers will be set to indicate that the status flags are getting overwritten by the newtransfer. This overrun should be treated like a normal receive overrun.

29

0

No receive data overrun condition occurred since last read of the data field.

1

A receive data overrun condition occurred since last read of the data field.

TXFULL

Transmit data buffer full.This flag is a read-only flag. Writing into the SPIDAT0 or SPIDAT1 field
while the TX shift register is full will automatically set the TXFULL flag. Once the word is copied tothe shift register, the TXFULL flag will be cleared. Writing to SPIDAT0 or SPIDAT1 when bothTXBUF and the TX shift register are empty does not set the TXFULL flag.
0

The transmit buffer is empty; SPIDAT0/SPIDAT1 is ready to accept a new data.

1

The transmit buffer is full; SPIDAT0/SPIDAT1 is not ready to accept new data.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

943

Multi-Buffer RAM

www.ti.com

Table 21-49. Multi-buffer Receive Buffer Register (RXRAM) Field Descriptions (continued)
Bit

Field

28

BITERR

Value

Description
Bit error. There was a mismatch of internal transmit data and transmitted data.
Note: This flag is cleared to 0 when the RXDATA field of the RXRAM register is read.

27

0

No bit error occurred.

1

A bit error occurred. The SPI samples the signal of the transmit pins (master: SIMOx, slave:
SOMIx) at the receive point (one-half clock cycle after the transmit point). If the sampled value
differs from the transmitted value, a bit error is detected and the BITERR flag is set. Possible
reasons for a bit error include noise, an excessively high bit rate, capacitive load, or anothermaster/slave trying to transmit at the same time.

DESYNC

Desynchronization of slave device. This bit is valid in master mode only.
The master monitors the ENA signal coming from the slave device and sets the DESYNC flag if
ENA is deactivated before the last reception point or after the last bit is transmitted plus t T2EDELAY.
If DESYNCENA is set, an interrupt is asserted. Desynchronization can occur if a slave device
misses a clock edge coming from the master.
Note: In the Compatibility Mode MibSPI, under some circumstances it is possible for adesync error detected for the previous buffer to be visible in the current buffer. This isbecause the receive completion flag/interrupt is generated when the buffer transfer iscompleted. But desynchronization is detected after the buffer transfer is completed. So, if
the VBUS master reads the received data quickly when an RXINT is detected, then thestatus flag may not reflect the correct desync condition. In multi-buffer mode, the desync
flag is always assured to be for the current buffer.
Note: This flag is cleared to 0 when the RXDATA field of the RXRAM register is read.

26

0

No slave desynchronization is detected.

1

A slave device is desynchronized.

PARITYERR

Parity error. The calculated parity differs from the received parity bit.
If the parity generator is enabled (selected individually for each buffer) an even or odd parity bit isadded at the end of a data word. During reception of the data word, the parity generator calculates
the reference parity and compares it to the received parity bit. If a mismatch is detected, the
PARITYERR flag is set.
Note: This flag is cleared to 0 when the RXDATA field of the RXRAM register is read.

250

No parity error is detected.

1

A parity error occurred.

TIMEOUT

Time-out because of non-activation of SPIENA pin.
The SPI generates a time-out when the slave does not respond in time by activating the ENA
signal after the chip select signal has been activated. If a time-out condition is detected, thecorresponding chip select is deactivated immediately and the TIMEOUT flag is set. In addition, theTIMEOUT flag in the status field of the corresponding buffer and in the SPI Flag Register(SPIFLG) is set.
Note: This bit is valid only in master mode.
Note: This flag is cleared to 0 when the RXDATA field of the RXRAM register is read.

24

0

No SPIENA pin time-out occurred.

1

An SPIENA signal time-out occurred.

DLENERR

Data length error flag.
Note: This flag is cleared to 0 when the RXDATA field of the RXRAM register is read.
0

No data-length error has occurred.

1

A data length error has occurred.

23-16

LCSNR

0-FFh

Last chip select number. LCSNR in the status field is a copy of CSNR in the corresponding control
field. It contains the chip select number that was activated during the last word transfer.

15-0

RXDATA

0-FFFFh

SPI receive data. This is the received word, transferred from the receive shift-register at the end of
a transfer. Regardless of the programmed character length and the direction of shifting, thereceived data is stored right-justified in the register.

944

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Parity Memory

www.ti.com

21.10 Parity Memory
The parity portion of multi-buffer RAM is not accessible by the CPU during normal operating modes.
However, each read or write operation to the control/data/status portion of the multi-buffer RAM causes
reads/writes to the parity portion as well.
• Each write to the multi-buffer RAM (either from the Peripheral interface or by the MibSPI itself) causes
a write operation to the parity portion of RAM simultaneously to update the equivalent parity bits.
• Each read operation from the multi-buffer RAM (either from the Peripheral interface or by the MibSPI
itself) causes a read operation from the parity portion of the RAM for parity comparison purpose.
• Reads/Writes to multi-buffer RAM can either be caused by any CPU accesses or by the sequencer
logic of MibSPI itself.
• Incase of Parity error ESM module is notified to generate MIBSPI Parity ESM interrupt. User can checkthe error status and address location captured in the UERRSTAT and UERRADDRx registers
respectively.
For testing the parity portion of the multi-buffer RAM, which is a 4-bit field per word address (1 bit perbyte), a separate parity memory test mode is available. Parity memory test mode can be enabled anddisabled by the PTESTEN bit in the UERRCTRL register.
During the parity test mode, the parity locations are addressable at the address between
RAM_BASE_ADDR + 0x400h and RAM_BASE_ADDR + 0x7FFh. Each location corresponds,
sequentially, to each TXRAM word, then to each RXRAM word. See Figure 21-66 for a diagram of thememory map of parity memory during normal operating mode and during parity test mode.
During parity test mode, after writing the data/control portion of the RAM, the parity locations can be
written with incorrect parity bits to intentionally cause parity errors.
See the device-specific data sheet to get the actual base address of the multi-buffer RAM.
NOTE: The RX_RAM_ACCESS bit can also be set to 1 during the parity test mode to be enable
writes to RXRAM locations. Both parity RAM testing and RXRAM testing can be done
together.

There are 4 bits of parity corresponding to each of the 32-bit multi-buffer locations. Individual bits in theparity memory are byte-addressable in parity test mode. See the example in Figure 21-67 for further
details.
NOTE: Polarity of the parity (odd/even) varies by device. In some devices, a control register in thesystem module can be used to select odd or even parity.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

945

Parity Memory

www.ti.com

Figure 21-66. Memory Map for Parity Locations During Normal and Test Mode
Memory Map During Normal Operation(Parity locations are not accessible by CPU)
Address
BASE+0x000h

3

0 31

Parity0

TXBUF0Parity1

Parity126

TXBUF1.
.
.
TXBUF126

Parity127

TXBUF127.
.
BASE+0x1FFh

3
BASE+0x200h

0 31

Address
BASE+0x000h

031
TXBUF0TXBUF1.
.
.
TXBUF126

BASE+0x1FFh

TXBUF127

BASE+0x200h

RXBUF00Parity0

RXBUF0Parity1

Parity126

RXBUF1.
.
.
RXBUF126

Parity127

RXBUF127.
.
BASE+0x3FFh

0

Memory Map During Parity Test Mode
(Parity locations are accessible by CPU)RXBUF1.
.
.
RXBUF126
BASE+0x3FFh

RXBUF127
Multi-Buffer RAM

Multi-Buffer RAM
31 24 16
BASE+0x400h

80

TX Parity0
TX Parity1

TX Parity126
BASE+0x5FFh

TX Parity127

BASE+0x600h

RX Parity0
RX Parity1

RX Parity126
BASE+0x7FFh

RX Parity127
Parity Memory* BASE - Base Address of Multi-Buffer RAM
Refer to specific Device Data sheet
for the actual value of BASE.

946* Shaded areas indicate they are physically notpresent.

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Parity Memory

www.ti.com

21.10.1 Example of Parity Memory Organization
Suppose TXBUF5 (6th location in TXRAM) in the multi-buffer RAM is written with a value of A001_AA55.
If the polarity of the parity is set to odd, the corresponding parity location parity5 will get updated withequivalent parity of 1011 in its field.
During parity-memory test mode, these bits can be individually byte addressed. The return data will be abyte adjusted with actual parity bit in the LSB of the byte. If a word is read from the word-boundary
address of parity locations, then each bit of the 4-bit parity is byte-adjusted and a 32-bit word is returned.
0s will be padded into the parity bits to get each byte. See Figure 21-67 for a diagram.
Figure 21-67. Example of Memory-Mapped Parity Locations During Test Mode
3
BASE+014h0 31

01 0 1 1

A001AA55

Parity5

TXBUF5

Memory organization during normal mode
31
BASE+014h

0
A001AA55
TXBUF5

BASE+ 400h + 014h

31

240000000

1 0000000

16

8

0

0 0000000

1 0000000

1

Parity5Parity memory locations during test mode (memory mapped)
1 Shadedareas indicate reads return 0, writes have no effect. These registers are not physically present.
NOTE: Read Access to Parity Memory Locations
Parity memory locations can be read even without entering into parity memory test mode.
Their address remains as in memory test mode. It is only to enter parity-memory test mode
to enable write access to the parity memory locations.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

947

MibSPI Pin Timing Parameters

www.ti.com

21.11 MibSPI Pin Timing Parameters
The pin timings of SPI can be classified based on its mode of operation. In each mode, different
configurations like Phase & Polarity affect the pin timings.
The pin directions are based on the mode of operation.
Master mode SPI:• SPICLK (SPI Clock) - Output• SPISIMO (SPI Slave In Master Out) - Output• SPICS (SPI Slave Chip Selects) - Output• SPISOMI (SPI Slave Out Master In) - Input• SPIENA (SPI slave ready Enable) - Input
Slave mode SPI:• SPICLK - Input• SPISIMO - Input• SPICS - Input• SPISOMI - Output• SPIENA - Output
NOTE: All the timing diagrams given below are with Phase = 0 and Polarity = 0, unless explicitly
stated otherwise.

21.11.1 Master Mode Timings for SPI/MibSPI
Figure 21-68. SPI/MibSPI Pins During Master Mode 3-pin Configuration
VCLK
Write to SPIDATSPICLKSPISIMOSPISOMI* Dotted vertical lines indicate the receive edges

Figure 21-69. SPI/MibSPI Pins During Master Mode 4-pin with SPICS Configuation
VCLK
Write to SPIDATSPICSSPICLKSPISIMOSPISOMI* Dotted vertical lines indicate the receive edges

948

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

MibSPI Pin Timing Parameters

www.ti.com

Figure 21-70. SPI/MibSPI Pins During Master Mode in 4-pin with SPIENA Configuration
VCLK
Write to SPIDATSPIENASPICLKSPISIMOSPISOMI* De-activation of SPIENA pin is controlled by the Slave.
* Dotted vertical lines indicate the receive edges

Figure 21-71. SPI/MibSPI Pins During Master/Slave Mode with 5-pin Configuration
VCLK

MasterWrite to SPIDATSPICSSPICLKSPISIMO

Slave

Write to SPIDATSPIENASPISOMI* Dotted vertical lines indicate the receive edges for the Master* ENABLE_HIGHZ is cleared to 0 in Slave SPISPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

949

MibSPI Pin Timing Parameters

www.ti.com

21.11.2 Slave Mode Timings for SPI/MibSPI
Figure 21-72. SPI/MibSPI Pins During Slave Mode 3-pin Configuration
Write to SPIDATVCLKSPICLKSPISOMISPISIMO* Dotted vertical lines indicate the receive edges

Figure 21-73. SPI/MibSPI Pins During Slave Mode in 4-pin with SPIENA Configuration
Write to SPIDATSPIENAVCLKSPICLK* Diagram shows a relationship between the SPIENA from Slave and SPICLK from MasterFigure 21-74. SPI/MibSPI Pins During Slave Mode in 5-pin Configuration - (Single Slave)
SPICS
Write to SPIDATVCLKSPIENASPICLK* ENABLE_HIGHZ is cleared to 0 in Slave SPI* Diagram shows relationship between the SPICS from a Master to SPIENA from Slave SPI when SPIENA
is configured in Push-Pull mode

Figure 21-75. SPI/MibSPI Pins During Slave Mode in 5-pin Configuration - (Single/Multi Slave)
SPICS
Write to SPIDATVCLKSPIENASPICLK* ENABLE_HIGHZ is set to 1 in Slave SPI* Diagram shows relationship between the SPICS from a Master to SPIENA from Slave SPI when SPIENA
is configured in High-Impedance mode

950

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

MibSPI Pin Timing Parameters

www.ti.com

21.11.3 Master Mode Timing Parameter Details
In case of Master, the module drives out SPICLK. It also drives out the Transmit data on SPISIMO withrespect to its internal SPICLK. In case of Master mode, the RX data on the SPISOMI pin is registered withrespect to SPICLK received through the input buffer from the I/O pad.
If the chip select pin is functional, then the Master will drive out the SPICS pins before starting the
SPICLK. If the SPIENA pin is functional, then the Master will wait for an active low from the Slave on the
input pin to start the SPICLK.

21.11.4 Slave Mode Timing Parameter Details
In case of Slave mode, the module will drive only the SPISOMI and SPIENA pins. All other pins are inputs
to it. The RX data on the SPISIMO pin will be registered with respect to the SPICLK pin. The Slave will
use the SPICS pin to drive out the SPIENA pin if both are functional. If 4-pin with SPIENA is configured,then the Slave will drive out an active-low signal on the SPIENA pin when a new data is written to the TX
Shift Register. Irrespective of 4-pin with SPIENA or 5-pin configuration, the Slave will deassert the
SPIENA pin after the last bit is received. If ENABLE_HIGHZ (SPIINT0.24) bit is 0, the de-asserted value ofthe SPIENA pin will be 1. Otherwise, it will depend upon the internal pull up or pull down resistor (ifimplemented) depending upon the Specification of the Chip.

SPNU517C – March 2018
Submit Documentation Feedback

Multi-Buffered Serial Peripheral Interface Module (MibSPI)
Copyright © 2018, Texas Instruments Incorporated

951

Chapter 22
SPNU517C – March 2018

Serial Communication Interface (SCI)/Local Interconnect
Network (LIN) ModuleThis chapter describes the serial communication interface (SCI) / local interconnect network (LIN) module.
The SCI/LIN is compliant to the LIN 2.1 protocol specified in the LIN Specification Package. This module
can be configured to operate in either SCI (UART) or LIN mode.
Topic...........................................................................................................................

Page

22.1 Introduction and Features ................................................................................. 953
22.2 SCI Communication Formats ............................................................................. 958
22.3 SCI Interrupts ................................................................................................... 966
22.4 SCI Configurations ........................................................................................... 969
22.5 SCI Low-Power Mode ........................................................................................ 971
22.6 LIN Communication Formats ............................................................................. 972
22.7 LIN Interrupts ................................................................................................... 989
22.8 LIN Configurations............................................................................................ 990
22.9 Low-Power Mode .............................................................................................. 992
22.10 Emulation Mode .............................................................................................. 994
22.11 SCI/LIN Control Registers................................................................................. 995
22.12 GPIO Functionality......................................................................................... 1041

952

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Introduction and Features

www.ti.com

22.1 Introduction and Features
The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module isan SCI. The SCI’s hardware features are augmented to achieve LIN compatibility.
The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturnto zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a Kline.
The LIN standard is based on the SCI (UART) serial data link format. The communication concept issingle-master/multiple-slave with a message identification for multi-cast transmission between any network
nodes.
Throughout the chapter Compatibility Mode refers to SCI Mode functionary of SCI/LIN Module. The initialpart of the chapter explains about the SCI functionality and later part about the LIN functionality. Though
the register are common for LIN and SCI, the register descriptions has notes to identify the register / bit
usage in different modes.

22.1.1 SCI Features
The following are the features of the SCI module:• Standard universal asynchronous receiver-transmitter (UART) communication• Supports full- or half-duplex operation• Standard nonreturn to zero (NRZ) format• Double-buffered receive and transmit functions in compatibility mode
• Supports two individually enabled interrupt lines: level 0 and level 1• Configurable frame format of 3 to 13 bits per character based on the following:– Data word length programmable from one to eight bits
– Additional address bit in address-bit mode
– Parity programmable for zero or one parity bit, odd or even parity– Stop programmable for one or two stop bits
• Asynchronous or isosynchronous communication modes• Two multiprocessor communication formats allow communication between more than two devices• Sleep mode is available to free CPU resources during multiprocessor communication and then wakeup to receive an incoming message• The 24-bit programmable baud rate supports 224 different baud rates provide high accuracy baud rate
selection• Five error flags and Seven status flags provide detailed information regarding SCI events• Two external pins: LINRX and LINTX• Multi-buffered receive and transmit units
NOTE: SCI/LIN module does not support UART hardware flow control. This feature can be
implemented in software using a general purpose I/O pin.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

953

Introduction and Features

www.ti.com

22.1.2 LIN Features
The following are the features of the LIN module:• Compatibility with LIN 1.3, 2.0 and 2.1protocols• Configurable Baud Rate up to 20 Kbits/s• Two external pins: LINRX and LINTX.
• Multi-buffered receive and transmit units• Identification masks for message filtering• Automatic master header generation– Programmable synchronization break field– Synchronization field– Identifier field• Slave automatic synchronization– Synchronization break detection– Optional baud rate update– Synchronization validation• 231 programmable transmission rates with 7 fractional bits
• Wakeup on LINRX dominant level from transceiver• Automatic wakeup support– Wakeup signal generation– Expiration times on wakeup signals• Automatic bus idle detection• Error detection– Bit error– Bus error– No-response error– Checksum error– Synchronization field error– Parity error• 2 Interrupt lines with priority encoding for:– Receive– Transmit– ID, error, and status• Support for LIN 2.0 checksum• Enhanced synchronizer finite state machine (FSM) support for frame processing• Enhanced handling of extended frames• Enhanced baud rate generator• Update wakeup/go to sleep

954

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Introduction and Features

www.ti.com

22.1.3 Block Diagram
The SCI/LIN module contains core SCI block with added sub-blocks to support LIN protocol.
Three Major components of the SCI Module are:• Transmitter• Baud Clock Generator• Receiver
Transmitter (TX) contains two major registers to perform the double- buffering:• The transmitter data buffer register (SCITD) contains data loaded by the CPU to be transferred to theshift register for transmission.
• The transmitter shift register (SCITXSHF) loads data from the data buffer (SCITD) and shifts data onto
the LINTX pin, one bit at a time.
Baud Clock Generator• A programmable baud generator produces either a baud clock scaled from VBUSP CLK.
Receiver (RX) contains two major registers to perform the double- buffering:• The receiver shift register (SCIRXSHF) shifts data in from the LINRX pin one bit at a time and transfers
completed data into the receive data buffer.
• The receiver data buffer register (SCIRD) contains received data transferred from the receiver shift
register
The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt
bits. The receiver and transmitter may each be operated independently or simultaneously in full duplex
mode.
To ensure data integrity, the SCI checks the data it receives for breaks, parity, overrun, and framing
errors. The bit rate (baud) is programmable to over 16 million different rates through a 24-bit baud-selectregister. Figure 22-1 shows the detailed SCI block diagram.
The SCI/LIN module is based on the standalone SCI with the addition of an error detector (parity
calculator, checksum calculator, and bit monitor), a mask filter, a synchronizer, and a multi-buffered
receiver and transmitter. The SCI interface and the baud generator are modified as part of the hardwareenhancements for LIN compatibility. Figure 22-2 shows the SCI/LIN block diagram.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

955

Introduction and Features

www.ti.com

Figure 22-1. SCI Block Diagram
TRANSMITTER
Address bit†SCITXSHF
Shift register
LINTX

TX EMPTYSCIFLR.11
1

TXWAKESCIFLR.10

VCLK
Peripheral

8

TXRDY
SCIFLR.8

Transmit buffer
SCITD

Baud clock
generator

TX INT ENASCISETINT.8

TX INTTXENA
SCIGCR1.25

CLOCK
SCIGCR1.5

SCI

Baud rate
registers
SCIBAUDRECEIVERSCIRXSHF
Shift register
BRKDTSCIFLR.0
RXENA
SCIGCR1.24

8

RXWAKESCIFLR.12

956

Receive buffer
SCIRD

WAKEUPSCIFLR.1

LINRX
BRKDT INT ENASCISETINT.0

ERR INT

WAKEUP INT ENASCISETINT.1

PE OE FESCIFLR24:26

RXRDY
SCIFLR.9

RX INT ENASCISETINT.9

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

RX INT

SPNU517C – March 2018
Submit Documentation Feedback

Introduction and Features

www.ti.com

Figure 22-2. SCI/LIN Block Diagram
Read data bus
Write data bus
Address bus

Interface

CHECKSUM
Calculator
ID parity
checker
Bit monitor
TXRX error
detector (TED)

Timeout control

Counter
LINRX/SCIRX

CompareFSM

LINTX/SCITX

SCISynchronizer

Mask
filter8 receive
buffers
8 transmit
buffers
LIN

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

957

SCI Communication Formats

www.ti.com

22.2 SCI Communication Formats
The SCI module can be configured to meet the requirements of many applications. Because
communication formats vary depending on the specific application, many attributes of the SCI/LIN are user
configurable. The list below describes these configuration options:• SCI Frame format• SCI Timing modes• SCI Baud rate
• SCI Multiprocessor modes

22.2.1 SCI Frame Formats
The SCI uses a programmable frame format. All frames consist of the following:• One start bit• One to eight data bits
• Zero or one address bit• Zero or one parity bit• One or two stop bits
The frame format for both the transmitter and receiver is programmable through the bits in the SCIGCR1
register. Both receive and transmit data is in nonreturn to zero (NRZ) format, which means that thetransmit and receive lines are at logic high when idle. Each frame transmission begins with a start bit, inwhich the transmitter pulls the SCI line low (logic low). Following the start bit, the frame data is sent andreceived least significant bit first (LSB).
An address bit is present in each frame if the SCI is configured to be in address-bit mode but is notpresent in any frame if the SCI is configured for idle-line mode. The format of frames with and without theaddress bit is illustrated in Figure 22-3.
A parity bit is present in every frame when the PARITY ENA bit is set. The value of the parity bit depends
on the number of one bits in the frame and whether odd or even parity has been selected via the PARITY
ENA bit. Both examples in Figure 22-3 have parity enabled.
All frames include one stop bit, which is always a high level. This high level at the end of each frame isused to indicate the end of a frame to ensure synchronization between communicating devices. Two stop
bits are transmitted if the STOP bit in SCIGCR1 register is set. The examples shown in Figure 22-3 use
one stop bit per frame.
Figure 22-3. Typical SCI Data Frame Formats
Idle-line mode

Start

0
(LSBit)

1

2

3

4

5

6

7
Parity(MSBit)6

7(MSBit)Stop

Address bit mode

Start

0
(LSBit)

1

2

3

4

5

Addr

ParityStop

Address bit

958

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI Communication Formats

www.ti.com

22.2.2 SCI Timing Mode
The SCI can be configured to use asynchronous or isosynchronous timing using TIMING MODE bit in
SCIGCR1 register.
22.2.2.1 Asynchronous Timing Mode
The asynchronous timing mode uses only the receive and transmit data lines to interface with devices
using the standard universal asynchronous receiver- transmitter (UART) protocol.
In the asynchronous timing mode, each bit in a frame has a duration of 16 SCI baud clock periods. Each
bit therefore consists of 16 samples (one for each clock period). When the SCI is using asynchronousmode, the baud rates of all communicating devices must match as closely as possible. Receive errors
result from devices communicating at different baud rates.
With the receiver in the asynchronous timing mode, the SCI detects a valid start bit if the first four samples
after a falling edge on the LINRX pin are of logic level 0. As soon as a falling edge is detected on LINRX,
the SCI assumes that a frame is being received and synchronizes itself to the bus.
To prevent interpreting noise as Start bit SCI expects LINRX line to be low for at least four contiguous SCI
baud clock periods to detect a valid start bit. The bus is considered idle if this condition is not met. When avalid start bit is detected, the SCI determines the value of each bit by sampling the LINRX line value
during the seventh, eighth, and ninth SCI baud clock periods. A majority vote of these three samples isused to determine the value stored in the SCI receiver shift register. By sampling in the middle of the bit,the SCI reduces errors caused by propagation delays and rise and fall times and data line noises.
Figure 22-4 illustrates how the receiver samples a start bit and a data bit in asynchronous timing mode.
The transmitter transmits each bit for a duration of 16 SCI baud clock periods. During the first clock period
for a bit, the transmitter shifts the value of that bit onto the LINTX pin. The transmitter then holds thecurrent bit value on LINTX for 16 SCI baud clock periods.
Figure 22-4. Asynchronous Communication Bit Timing
Majority
vote

Falling edge
detected

1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 161 2 3 4 5

LINRX
Start bit

LSB of data
16 SCI baud clock periods/bit

22.2.2.2 Isosynchronous Timing Mode
In isosynchronous timing mode, each bit in a frame has a duration of exactly 1 baud clock period andtherefore consists of a single sample. With this timing configuration, the transmitter and receiver are
required to make use of the SCICLK pin to synchronize communication with other SCI. This mode is notsupported on this device because SCICLK pin is not available.

22.2.3 SCI Baud Rate
The SCI/LIN has an internally generated serial clock determined by the peripheral VCLK and theprescalers P and M in this register. The SCI uses the 24-bit integer prescaler P value in the BRS registerto select the required baud rates. The additional 4-bit fractional divider M refines the baud rate selection.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

959

SCI Communication Formats

www.ti.com

In asynchronous timing mode, the SCI generates a baud clock according to the following formula:
VCLK Frequency
M
P + 1 + -----16

SCICLK Frequency = ----------------------------------------------------SCICLK Frequency---------------------------------------------------------16

Asynchronous baud value =For P = 0,
Asynchronous baud value =VCLK Frequency------------------------------------------------32(40)

22.2.3.1 Superfractional Divider, SCI Asynchronous Mode
The superfractional divider is available in SCI asynchronous mode (idle-line and address-bit mode).
Building on the 4-bit fractional divider M (BRS[27:24]), the superfractional divider uses an additional 3-bit
modulating value, illustrated in Table 22-2. The bits with a 1 in the table will have an additional VCLK
period added to their Tbit. If the character length is more than 10, then the modulation table will be a rolledover version of the original table (Table 22-1), as shown in Table 22-2.
The baud rate will vary over a data field to average according to the BRS[30:28] value by a “d” fraction of
the peripheral internal clock: 0<d<1. Refer Figure 22-5 for a simple Average “d’ calculation based on “U”
value (BRS[30:28]).
The instantaneous bit time is expressed in terms of TVCLK as follows:
For all P other than 0, and all M and d (0 or 1),

é æ
ù
Mö
T i bit = ê16ç P + 1 + ÷ + d úTVCLK
16 ø
ë è
û

(41)

For P = 0 Tbit = 32TVCLK
The averaged bit time is expressed in terms of TVCLK as follows:
For all P other than 0, and all M and d (0<d<1),

ù
é æ
M ö
T a b it = ê1 6 ç P + 1 +÷ + d ú TV C L K
16 ø
û
ë è

(42)

For P = 0 Tbit = 32TVCLK
Table 22-1. Superfractional Bit Modulation for SCI Mode (Normal Configuration) (1)

(1)

960

BRS[30:28]

Start Bit

D[0]

D[1]

D[2]

D[3]

D[4]

D[5]

D[6]

D[7]

Stop Bit

0h

0

0

0

0

0

0

0

0

0

0

1h

1

0

0

0

0

0

0

0

1

0

2h

1

0

0

0

1

0

0

0

1

0

3h

1

0

1

0

1

0

0

0

1

0

4h

1

0

1

0

1

0

1

0

1

0

5h

1

1

1

0

1

0

1

0

1

1

6h

1

1

1

0

1

1

1

0

1

1

7h

1

1

1

1

1

1

1

0

1

1

Normal configuration = Start + 8 Data Bits + Stop Bit

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI Communication Formats

www.ti.com

Table 22-2. Superfractional Bit Modulation for SCI Mode (Maximum Configuration) (1)(1)

BRS[30:28]

Start Bit

D[0]

D[1]

D[2]

D[3]

D[4]

D[5]

D[6]

D[7]

Addr

Parity

0h

0

0

0

0

0

0

0

0

0

0

0

Stop0 Stop1
0

0

1h

1

0

0

0

0

0

0

0

1

0

0

0

0

2h

1

0

0

0

1

0

0

0

1

0

0

0

1

3h

1

0

1

0

1

0

0

0

1

0

1

0

1

4h

1

0

1

0

1

0

1

0

1

0

1

0

1

5h

1

1

1

0

1

0

1

0

1

1

1

0

1

6h

1

1

1

0

1

1

1

0

1

1

1

0

1

7h

1

1

1

1

1

1

1

0

1

1

1

1

1

Maximum configuration = Start + 8 Data Bits + Addr Bit + Parity Bit + Stop Bit 0 + Stop Bit 1

Table 22-3. SCI Mode (Minimum Configuration) (1)(1)

BRS[30:28]

Start Bit

D[0]

Stop

0h

0

0

0

1h

1

0

0

2h

1

0

0

3h

1

0

1

4h

1

0

1

5h

1

1

1

6h

1

1

1

7h

1

1

1

Minimum configuration = Start + 1 Data Bits + Stop Bit

Figure 22-5. Superfractional Divider Example
Normal Data Frame with BRS[31:28] = 0

ST

0

1

2

3

4

5

6

7

4

5

6

7

STOP

Tbit

Normal Data Frame with BRS[31:28] = 1
ST

0

1

2

3

STOP

d = Number of Vclk Added / Total Number of Bits
Tbit
+TvclkSPNU517C – March 2018
Submit Documentation Feedback= 2 / 10 = 0.2

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

961

SCI Communication Formats

www.ti.com

22.2.4 SCI Multiprocessor Communication Modes
In some applications, the SCI may be connected to more than one serial communication device. In such amultiprocessor configuration, several frames of data may be sent to all connected devices or to anindividual device. In the case of data sent to an individual device, the receiving devices must determine
when they are being addressed. When a message is not intended for them, the devices can ignore thefollowing data. When only two devices make up the SCI network, addressing is not needed, so
multiprocessor communication schemes are not required.
SCI supports two multiprocessor communication modes which can be selected using COMM MODE bit:
• Idle-Line Mode
• Address Bit Mode
When the SCI is not used in a multiprocessor environment, software can consider all frames as data
frames. In this case, the only distinction between the idle-line and address-bit modes is the presence of an
extra bit (the address bit) in each frame sent with the address-bit protocol.
The SCI allows full-duplex communication where data can be sent and received via the transmit andreceive pins simultaneously. However, the protocol used by the SCI assumes that only one device
transmits data on the same bus line at any one time. No arbitration is done by the SCI.
22.2.4.1 Idle-Line Multiprocessor Modes
In idle-line multiprocessor mode, a frame that is preceded by an idle period (10 or more idle bits) is anaddress frame. A frame that is preceded by fewer than 10 idle bits is a data frame. Figure 22-6 illustrates
the format of several blocks and frames with idle-line mode.
There are two ways to transmit an address frame using idle-line mode:
Method 1: In software, deliberately leave an idle period between the transmission of the last data frame ofthe previous block and the address frame of the new block.
Method 2: Configure the SCI to automatically send an idle period between the last data frame of theprevious block and the address frame of the new block.
Although Method 1 is only accomplished by a delay loop in software, Method 2 can be implemented byusing the transmit buffer and the TXWAKE bit in the following manner:
Step 1: Write a 1 to the TXWAKE bit.
Step 2: Write a dummy data value to the SCITD register. This triggers the SCI to begin the idle period assoon as the transmitter shift register is empty.
Step 3: Wait for the SCI to clear the TXWAKE flag.
Step 4: Write the address value to SCITD.
As indicated by Step 3, software should wait for the SCI to clear the TXWAKE bit. However, the SCI
clears the TXWAKE bit at the same time it sets TXRDY (that is, transfers data from SCITD into
SCITXSHF). Therefore, if the TX INT ENA bit is set, the transfer of data from SCITD to SCITXSHF causes
an interrupt to be generated at the same time that the SCI clears the TXWAKE bit. If this interrupt method
is used, software is not required to poll the TXWAKE bit waiting for the SCI to clear it.
When idle-line multiprocessor communications are used, software must ensure that the idle time exceeds
10 bit periods before addresses (using one of the methods mentioned above), and software must also
ensure that data frames are written to the transmitter quickly enough to be sent without a delay of 10 bit
periods between frames. Failure to comply with these conditions will result in data interpretation errors byother devices receiving the transmission.

962

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI Communication Formats

www.ti.com

Figure 22-6. Idle-Line Multiprocessor Communication Format
Blocks of frames
Blocks separated by 10 or more idle bits
Data format(pins LINRX,
LINTX)

Address frame

Data

Fewer than
10 idle bits

Data frame

ParityStop

Start

ParityStop

Address

Start

Start
Idle period

ParityStop

One block of frames

Data format
expanded

Last data

Data frame

22.2.4.2 Address-Bit Multiprocessor ModeIn the address-bit protocol, each frame has an extra bit immediately following the data field called anaddress bit. A frame with the address bit set to 1 is an address frame; a frame with the address bit set to 0
is a data frame. The idle period timing is irrelevant in this mode. Figure 22-7 illustrates the format ofseveral blocks and frames with the address-bit mode.
When address-bit mode is used, the value of the TXWAKE bit is the value sent as the address bit. To
send an address frame, software must set the TXWAKE bit. This bit is cleared as the contents of the
SCITD are shifted from the TXWAKE register so that all frames sent are data except when the TXWAKE
bit is written as a 1.
No dummy write to SCITD is required before an address frame is sent in address-bit mode. The first byte
written to SCITD after the TXWAKE bit is written to 1 is transmitted with the address bit set when addressbit mode is used.
Figure 22-7. Address-Bit Multiprocessor Communication Format
Several blocks of frames

Data format(pins LINRX,
LINTX)

Address frame(address bit = 1)

Data frame
Idle time(address bit = 0)
is of nosignificance

Idle timeis of nosignificance

1

Stop

Addr

Parity

Start

0

Stop

Data

Parity

Start

1

Stop

Addr

ParityStart

Idle time is not significant
Data format
expanded

Address frame(address bit = 1)

One block

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

963

SCI Communication Formats

www.ti.com

22.2.5 SCI Multi-Buffered Mode
To reduce CPU load when Receiving or Transmitting data in interrupt mode, the SCI/LIN module has eight
separate receive and transmit buffers. Multi-buffered mode is enabled by setting the MBUF MODE bit in
the SCIGCR1 register.
The multi-buffer 3-bit counter counts the data bytes transferred from the SCIRXSHF register to the RDy
receive buffers and TDy transmit buffers register to SCITXSHF register. The 3-bit compare registercontains the number of data bytes expected to be received or transmitted. the LENGTH value in
SCIFORMAT register indicates the expected length and is used to load the 3-bit compare register.
A receive interrupt (RX interrupt; see the SCIINTVECT0 and SCIINTVECT1registers) and a receive ready
RXRDY flag set in SCIFLR register could occur after receiving a response if there are no response receive
errors for the frame (such as a frame error or overrun error).
A transmit interrupt (TX interrupt) and a transmit ready flag (TXRDY flag in SCIFLR register could occur
after transmitting a response.
Figure 22-8 and Figure 22-9 shows the receive and transmit multi-buffer functional block diagram.
Figure 22-8. Receive Buffers
RX

7

SCIRXSHF0CHECKSUMCALCULATORCE Flag

RX Ready Flag

7
7
7
7
7
7
7
7

964

RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7

0
0

3-bit
Compare0No
Receive
Errors=MBUF MODE

0
0
0

3-bit
Counter00Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

Not
MBUF MODESPNU517C – March 2018
Submit Documentation Feedback

SCI Communication Formats

www.ti.com

Figure 22-9. Transmit Buffers
TX

7

SCITXSHF0CHECKSUMCALCULATOR

7
7
7
7
7
7
7
7

SPNU517C – March 2018
Submit Documentation Feedback

TD0
TD1
TD2
TD3
TD4
TD5
TD6
TD7

0
0

3-bit
CompareCE Flag

TX Ready Flag

0=
MBUF MODE

0
0
0

3-bit
Counter

0

Not
MBUF MODE

0

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

965

SCI Interrupts

www.ti.com

22.3 SCI Interrupts
The SCI/LIN module has two interrupt lines, level 0 and level 1, to the vectored interrupt manager (VIM)
module (see Figure 22-10). Two offset registers SCIINTVECT0 and SCIINTVECT1 determine which flag
triggered the interrupt according to the respective priority encoders. Each interrupt condition has a bit toenable/disable the interrupt in the SCISETINT and SCICLRINT registers respectively.
Each interrupt also has a bit that can be set as interrupt level 0(INT0) or as interrupt level 1(INT1). By
default, interrupts are in interrupt level 0. SCISETINTLVL sets a given interrupt to level1.
SCICLEARINTLVL resets a given interrupt level to the default level 0.
The interrupt vector registers SCIINTVECT0 and SCIINTVECT1 return the vector of the pending interrupt
line INT0 or INT1. If more than one interrupt is pending, the interrupt vector register holds the highest
priority interrupt.
Figure 22-10. General Interrupt Scheme
INT0
INT1

Priority Encoder 1

INT 1

Priority Encoder 0

INT 0

INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
INT10
INT11
INT12
INT13
INT14
INT15
INT16

SCISETINT
SCICLRINT
SCISETINTLSCICLRLSCIINTFLRSCIINTVECT0SCIINTVECT1

966

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI Interrupts

www.ti.com

Figure 22-11. Interrupt Generation for Given Flags
5-bit
INTVECT0

Priority
Encoder 0

...
...

INT0
INTx LVL
FLAGx
ENA INT x

...

INT1

...

Priority
Encoder 1

5-bit
INTVECT1

22.3.1 Transmit Interrupt
To use transmit interrupt functionality, SET TX INT bit must be enabled. The transmit ready (TXRDY) flagis set when the SCI transfers the contents of SCITD to the shift register, SCITXSHF. The TXRDY flag
indicates that SCITD is ready to be loaded with more data. In addition, the SCI sets the TX EMPTY bit ifboth the SCITD and SCITXSHF registers are empty. If the SET TX INT bit is set, then a transmit interrupt
is generated when the TXRDY flag goes high. Transmit Interrupt is not generated immediately after setting
the SET TX INT bit. Transmit Interrupt is generated only after the first transfer from SCITD to SCITXSHF.
That is, the first data has to be written to SCITD by the User before any interrupt gets generated. To
transmit further data the user can write data to SCITD in the transmit Interrupt service routine.
Writing data to the SCITD register clears the TXRDY bit. When this data has been moved to the
SCITXSHF register, the TXRDY bit is set again. The interrupt request can be suspended by setting the
CLR TX INT bit; however, when the SET TX INT bit is again set to 1, the TXRDY interrupt is asserted
again. The transmit interrupt request can be eliminated until the next series of values is written to SCITD,
by disabling the transmitter via the TXENA bit, by a software reset SWnRST, or by a device hardware
reset.

22.3.2 Receive Interrupt
The receive ready (RXRDY) flag is set when the SCI transfers newly received data from SCIRXSHF to
SCIRD. The RXRDY flag therefore indicates that the SCI has new data to be read. Receive interrupts areenabled by the SET RX INT bit. If the SET RX INT is set when the SCI sets the RXRDY flag, then areceive interrupt is generated. The received data can be read in the Interrupt Service routine.

22.3.3 WakeUp Interrupt
SCI sets the WAKEUP flag if bus activity on the RX line either prevents power-down mode from being
entered, or RX line activity causes an exit from power-down mode. If enabled (SET WAKEUP INT),
wakeup interrupt is triggered once WAKEUP flag is set.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

967

SCI Interrupts

www.ti.com

22.3.4 Error Interrupts
The following error detection are supported with Interrupt by the SCI module:• Parity errors (PE)• Frame errors (FE)• Break Detect errors (BRKDT)• Overrun errors (OE)
• Bit errors (BE)If all of these errors (PE, FE, BRKDT, OE, BE) are flagged, an interrupt for the flagged errors will be
generated if enabled. A message is valid for both the transmitter and the receiver if there is no error
detected until the end of the frame. Each of these flags is located in the receiver status (SCIFLR) register.
There are 16 interrupt sources in the SCI/LIN module, In SCI mode 8 interrupts are supported, as seen in
Table 22-4.
Table 22-4. SCI/LIN Interrupts
Offset (1)Interrupt

0

No interrupt

1

Wakeup2
3

Applicable to SCI

Applicable to LIN

Yes

Yes

Inconsistent-synch-field error

No

Yes

Parity error

Yes

Yes

4

ID

No

Yes

5

Physical bus error

No

Yes

6

Frame error

Yes

Yes

7

Break detect

Yes

No

8

Checksum error

No

Yes

9

Overrun error

Yes

Yes

10

Bit error

Yes

Yes

11

Receive

Yes

Yes

12

Transmit

Yes

Yes

13

No-response error

No

Yes

14

Timeout after wakeup signal (150 ms)

No

Yes

15

Timeout after three wakeup signals (1.5 s)

No

Yes

16

Timeout (Bus Idle, 4s)

No

Yes

(1)

968

Offset 1 is the highest priority. Offset 16 is the lowest priority.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI Configurations

www.ti.com

22.4 SCI Configurations
Before the SCI sends or receives data, its registers should be properly configured. Upon power-up or asystem-level reset, each bit in the SCI registers is set to a default state. The registers are writable only
after the RESET bit in the SCIGCR0 register is set to 1. Of particular importance is the SWnRST bit in the
SCIGCR1 register. The SWnRST is an active-low bit initialized to 0 and keeps the SCI in a reset state
until it is programmed to 1. Therefore, all SCI configuration should be completed before a 1 is written to
the SWnRST bit.
The following list details the configuration steps that software should perform prior to the transmission or
reception of data. As long as the SWnRST bit is cleared to 0 the entire time that the SCI is being
configured, the order in which the registers are programmed is not important.
• Enable SCI by setting the RESET bit to 1.
• Clear the SWnRST bit to 0 before SCI is configured.
• Select the desired frame format by programming the SCIGCR1 register.
• Set both the RX FUNC and TX FUNC bits in SCIPIO0 to 1 to configure the LINRX and LINTX pins for
SCI functionality.
• Select the baud rate to be used for communication by programming the BRS register.
• Set the CLOCK bit in SCIGCR1 to 1 to select the internal clock.
• Set the CONT bit in SCIGCR1 to 1 to make SCI not halt for an emulation breakpoint until its current
reception or transmission is complete (this bit is used only in an emulation environment).
• Set the LOOP BACK bit in SCIGCR1 to 1 to connect the transmitter to the receiver internally (thisfeature is used to perform a self-test).
• Set the RXENA bit in SCIGCR1 to 1, if data is to be received.
• Set the TXENA bitin SCIGCR1 to 1, if data is to be transmitted.
• Set the SWnRST bit to 1 after SCI is configured.
• Perform receiving or transmitting data (see Section 22.4.1 or Section 22.4.2).

22.4.1 Receiving Data
The SCI receiver is enabled to receive messages if both the RX FUNC bit and the RXENA bit are set to 1.
If the RX FUNC bit is not set, the LINRX pin functions as a general-purpose I/O pin rather than as an SCI
function pin.
SCI module can receive data in one of the following modes:• Single-Buffer (Normal) Mode
• Multi-Buffer Mode
After a valid idle period is detected, data is automatically received as it arrives on the LINRX pin.
22.4.1.1 Receiving Data in Single-Buffer Mode
Single-buffer mode is selected when the MBUF MODE bit in SCIGCR1 is cleared to 0. In this mode, SCI
sets the RXRDY bit when it transfers newly received data from SCIRXSHF to SCIRD. The SCI clears the
RXRDY bit after the new data in SCIRD has been read. Also, as data is transferred from SCIRXSHF to
SCIRD, the SCI sets the FE, OE, or PE flags if any of these error conditions were detected in the received
data. These error conditions are supported with configurable interrupt capability. The wake-up and breakdetect status bits are also set if one of these errors occurs, but they do not necessarily occur at the sametime that new data is being loaded into SCIRD.
You can receive data by:
1. Polling Receive Ready Flag
2. Receive Interrupt
In polling method, software can poll for the RXRDY bit and read the data from the SCIRD register once
the RXRDY bit is set high. The CPU is unnecessarily overloaded by selecting the polling method. To avoid
this, you can use the interrupt method. To use the interrupt method, the SET RX INT bit is set. An
interrupt is generated the moment the RXRDY bit is set.
SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

969

SCI Configurations

www.ti.com

22.4.1.2 Receiving Data in Multi-Buffer Mode
Multi-buffer mode is selected when the MBUF MODE bit in SCIGCR1 is set to 1. In this mode, SCI sets
the RXRDY bit after receiving the programmed number of data in the receive buffer, the complete frame.
The error condition detection logic is similar to the single-buffer mode, except that it monitors for thecomplete frame. Like single-buffer mode, you can use the polling or interrupt method to read the data. The
SCI clears the RXRDY bit after the new data in SCIRD has been read.

22.4.2 Transmitting Data
The SCI transmitter is enabled if both the TX FUNC bit and the TXENA bit are set to 1. If the TX FUNC bit
is not set, the LINTX pin functions as a general-purpose I/O pin rather than as an SCI function pin. Anyvalue written to the SCITD before TXENA is set to 1 is not transmitted. Both of these control bits allow for
the SCI transmitter to be held inactive independently of the receiver.
SCI module can transmit data in one of the following modes:• Single-Buffer (Normal) Mode
• Multi-Buffered or Buffered SCI Mode.
22.4.2.1 Transmitting Data in Single-Buffer Mode
Single-buffer mode is selected when the MBUF MODE bit in SCIGCR1 is cleared to 0. In this mode, SCI
waits for data to be written to SCITD, transfers it to SCITXSHF, and transmits the data. The TXRDY and
TX EMPTY bits indicate the status of the transmit buffers. That is, when the transmitter is ready for data to
be written to SCITD, the TXRDY bit is set. Additionally, if both SCITD and SCITXSHF are empty, then the
TX EMPTY bit is also set.
You can transmit data by:
1. Polling Transmit Ready Flag
2. Transmit Interrupt
In polling method, software can poll for the TXRDY bit to go high before writing the data to the SCITD
register. The CPU is unnecessarily overloaded by selecting the polling method. To avoid this, you can use
the interrupt method. To use the interrupt method, the SET TX INT bit is set. An interrupt is generated themoment the TXRDY bit is set. When the SCI has completed transmission of all pending frames, the
SCITXSHF register and SCITD are empty, the TXRDY bit is set, and an interrupt is generated, if enabled.
Because all data has been transmitted, the interrupt should be halted. This can either be done bydisabling the transmit interrupt (CLR TX INT) or by disabling the transmitter (clear TXENA bit).
NOTE: The TXRDY flag cannot be cleared by reading the corresponding interrupt offset in the
SCIINTVECT0 or SCIINTVECT1 register.

22.4.2.2 Transmitting Data in Multi-Buffer Mode
Multi-buffer mode is selected when the MBUF MODE bit in SCIGCR1 is set to 1. Like single-buffer mode,
you can use the polling or interrupt method to write the data to be transmitted. The transmitted data has tobe written to the SCITD registers. SCI waits for data to be written to the SCITD register and transfers the
programmed number of bytes to SCITXSHF to transmit one by one automatically.

970

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI Low-Power Mode

www.ti.com

22.5 SCI Low-Power Mode
The SCI/LIN can be put in either local or global low-power mode. Global low-power mode is asserted by
the system and is not controlled by the SCI/LIN. During global low-power mode, all clocks to the SCI/LIN
are turned off so the module is completely inactive.
Local low-power mode is asserted by setting the POWERDOWN bit; setting this bit stops the clocks to the
SCI/LIN internal logic and the module registers. Setting the POWERDOWN bit causes the SCI to enter
local low-power mode and clearing the POWERDOWN bit causes SCI/LIN to exit from local low-power
mode. All the registers are accessible during local power-down mode as any register access enables theclock to SCI for that particular access alone.
The wake-up interrupt is used to allow the SCI to exit low-power mode automatically when a low level isdetected on the LINRX pin and also this clears the POWERDOWN bit. If wake-up interrupt is disabled,
then the SCI/LIN immediately enters low-power mode whenever it is requested and also any activity on
the LINRX pin does not cause the SCI to exit low-power mode.
NOTE: Enabling Local Low-Power Mode During Receive and Transmit
If the wake-up interrupt is enabled and low-power mode is requested while the receiver isreceiving data, then the SCI immediately generates a wake-up interrupt to clear the
powerdown bit and prevents the SCI from entering low-power mode and thus completes thecurrent reception. Otherwise, if the wake-up interrupt is disabled, then the SCI completes thecurrent reception and then enters the low-power mode.

22.5.1 Sleep Mode for Multiprocessor Communication
When the SCI receives data and transfers that data from SCIRXSHF to SCIRD, the RXRDY bit is set and
if RX INT ENA is set, the SCI also generates an interrupt. The interrupt triggers the CPU to read the newly
received frame before another one is received. In multiprocessor communication modes, this default
behavior may be enhanced to provide selective indication of new data. When SCI receives an address
frame that does not match its address, the device can ignore the data following this non-matching addressuntil the next address frame by using sleep mode. Sleep mode can be used with both idle-line andaddress-bit multiprocessor modes.
If sleep mode is enabled by the SLEEP bit, then the SCI transfers data from SCIRXSHF to SCIRD only foraddress frames. Therefore, in sleep mode, all data frames are assembled in the SCIRXSHF register
without being shifted into the SCIRD and without initiating a receive interrupt. Upon reception of an
address frame, the contents of the SCIRXSHF are moved into SCIRD, and the software must read SCIRD
and determine if the SCI is being addressed by comparing the received address against the address
previously set in the software and stored somewhere in memory (the SCI does not have hardware
available for address comparison). If the SCI is being addressed, the software must clear the SLEEP bit
so that the SCI will load SCIRD with the data of the data frames that follow the address frame.
When the SCI has been addressed and sleep mode has been disabled (in software) to allow the receipt of
data, the SCI should check the RXWAKE bit (SCIFLR.12) to determine when the next address has been
received. This bit is set to 1 if the current value in SCIRD is an address and set to 0 if SCIRD contains
data. If the RXWAKE bit is set, then software should check the address in SCIRD against its own address.
If it is still being addressed, then sleep mode should remain disabled. Otherwise, the SLEEP bit should be
set again.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

971

LIN Communication Formats

www.ti.com

Following is a sequence of events typical of sleep mode operation:• The SCI is configured and both sleep mode and receive actions are enabled.
• An address frame is received and a receive interrupt is generated.
• Software compares the received address frame against that set by software and determines that the
SCI is not being addressed, so the value of the SLEEP bit is not changed.
• Several data frames are shifted into SCIRXSHF, but no data is moved to SCIRD and no receive
interrupts are generated.
• A new address frame is received and a receive interrupt is generated.
• Software compares the received address frame against that set by software and determines that the
SCI is being addressed and clears the SLEEP bit.
• Data shifted into SCIRXSHF is transferred to SCIRD, and a receive interrupt is generated after eachdata frame is received.
• In each interrupt routine, software checks RXWAKE to determine if the current frame is an address
frame.
• Another address frame is received, RXWAKE is set, software determines that the SCI is not being
addressed and sets the SLEEP bit back to 1. No receive interrupts are generated for the data frames
following this address frame.
By ignoring data frames that are not intended for the device, fewer interrupts are generated. These
interrupts would otherwise require CPU intervention to read data that is of no significance to this specificdevice. Using sleep mode can help free some CPU resources.
Except for the RXRDY flag, the SCI continues to update the receiver status flags (see Table 22-12) while
sleep mode is active. In this way, if an error occurs on the receive line, an application can immediately
respond to the error and take the appropriate corrective action.
Because the RXRDY bit is not updated for data frames when sleep mode is enabled, the SCI can enable
sleep mode and use a polling algorithm if desired. In this case, when RXRDY is set, software knows that a
new address has been received. If the SCI is not being addressed, then the software should not change
the value of the SLEEP bit and should continue to poll RXRDY.

22.6 LIN Communication Formats
The SCI/LIN module can be used in LIN mode or SCI mode. The enhancements for baud generation andadditional receive/transmit buffers necessary for LIN mode operation are also part of the enhanced
buffered SCI module. LIN mode is selected by enabling LIN MODE bit in SCIGCR1 register.
NOTE: The SCI/LIN is built around the SCI platform and uses a similar sampling scheme: 16
samples for each bit with majority vote on samples 8, 9, and 10.

The SCI/LIN control registers are located at the SCI/LIN base address. For a detailed description of eachregister, see Section 22.11.

22.6.1 LIN Standards
For compatibility with LIN2.0 standard the following additional features are implemented over LIN1.3:
i. Support for LIN 2.0 checksum
ii. Enhanced synchronizer FSM support for frame processingiii. Enhanced handling of extended frames
iv. Enhanced baudrate generator
v. Update wakeup/go to sleep
The LIN module covers the CPU performance-consuming features, defined in the LIN Specification
Package Revision 1.3 and 2.0 by hardware.
The Master Mode of LIN module is compatible with LIN 2.1 standard.

972

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

LIN Communication Formats

www.ti.com

22.6.2 Message Frame
The LIN protocol defines a message frame format, illustrated in Figure 22-12. Each frame includes one
master header, one response, one in-frame response space, and inter-byte spaces. In-frame-response
and inter-byte spaces may be 0.
There is no arbitration in the definition of the LIN protocol; therefore, multiple slave nodes responding to aheader might be detected as an error.
The LIN bus is a single channel wired-AND. The bus has a binary level: either dominant for a value of 0,
or recessive for a value of 1.
Figure 22-12. LIN Protocol Message Frame Format: Master Header and Slave Response

Message Frame

Master or Slave
Slave Response

Master Header

In-frame space
Sync Break

Sync Field

ID Field

1, 2, 3, ...8 Data Fields

Checksum

22.6.2.1 Message Header
The header of a message is initiated by a master (see Figure 22-13) and consists of a three fieldsequence:• The synch break field signaling the beginning of a message• The synch field conveying bit rate information of the LIN bus• The ID field denoting the content of a message
Figure 22-13. Header 3 Fields: Synch Break, Synch, and ID
SYNCH BREAK FIELDSPNU517C – March 2018
Submit Documentation Feedback

SYNCH FIELD

ID FIELD

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

973

LIN Communication Formats

www.ti.com

22.6.2.2 Response
The format of the response is as illustrated in Figure 22-14. There are two types of fields in a response:
data and checksum. The data field consists of exactly one data byte, one start bit, and one stop bit, for a
total of 10 bits. The LSB is transmitted first. The checksum field consists of one checksum byte, one start
bit and one stop bit. The checksum byte is the inverted modulo-256 sum over all data bytes in the data
fields of the response.
Figure 22-14. Response Format of LIN Message Frame
Response
1 to 8 Data Fields

Checksum
Fieldinterbyte spaces

The format of the response is a stream of N data fields and one checksum field. Typically N is from 1 to 8,
with the exception of the extended command frames (Section 22.6.6). The length N of the response isindicated either with the optional length control bits of the ID Field (this is used in standards earlier than
LIN 1.x); see Table 22-5, or by LENGTH value in SCIFORMAT[18:16] register; see Table 22-6. The
SCI/LIN module supports response lengths from 1 to 8 bytes in compliance with LIN 2.0.
Table 22-5. Response Length Info Using IDBYTE Field Bits [5:4] for LIN Standards Earlier than 1.3
ID5

ID4

Number of Data bytes

0

0

2

0

1

2

1

0

4

1

1

8

Table 22-6. Response Length with SCIFORMAT[18:16] Programming

974

SCIFORMAT[18:16]

No. of Bytes

000

1

001

2

010

3

011

4

100

5

101

6

110

7

111

8

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

LIN Communication Formats

www.ti.com

22.6.3 Synchronizer
The synchronizer has three major functions in the messaging between master and slave nodes. It
generates the master header data stream, it synchronizes to the LIN bus for responding, and it locallydetects timeouts. A bit rate is programmed using the prescalers in the BRS register to match the indicated
LIN_speed value in the LIN description file.
The LIN synchronizer will perform the following functions: master header signal generation, slave
detection and synchronization to message header with optional baud rate adjustment, responsetransmission timing and timeout control.
The LIN synchronizer is capable of detecting an incoming break and initializing communication at all
times.

22.6.4 Baud Rate
The transmission baud rate of any node is configured by the CPU at the beginning; this defines the bittime Tbit. The bit time is derived from the fields P and M in the baud rate selection register (BRS). There isan additional 3-bit fractional divider value, field U in the BRS register, which further fine-tunes the data
field baud rate.
The ranges for the prescaler values in the BRS register are:P = 0, 1, 2, 3, . . . , 224 - 1
M = 0, 1, 2, . . . , 15
U = 0, 1, 2, 3, 4, 5, 6, 7
The P, M, and U values in the BRS register are user programmable. The P and M dividers could be used
for both SCI mode and LIN mode to select a baud rate. The U value is an additional 3-bit value
determining that “a TVCLK“ (with a = 0,1) is added to each Tbit as explained in Section 22.6.4.2. If the
ADAPT bit is set and the LIN slave is in adaptive baud rate mode, then all these divider values areautomatically obtained during header reception when the synchronization field is measured.
The LIN protocol defines baud rate boundaries as follows:
1kHz ≤ FLINCLK ≤ 20kHz
All transmitted bits are shifted in and out at Tbit periods.
22.6.4.1 Fractional Divider
The M field in the BRS register modifies the integer prescaler P for fine tuning of the baud rate. The M
value adds in increments of 1/16 of the P value.
The bit time, Tbit is expressed in terms of the VCLK period TVCLK as follows:
For all P other than 0, and all M,

Möæ
Tbit = 16ç P + 1 + ÷TVCLK
16 ø
è

(43)

For P= 0 : Tbit = 32TVCLK
Therefore, the LINCLK frequency is given by:FVCLKFLINCLK = ------------------------------------M)
16(P +1 + ----16
FVCLK
FLINCLK = -------------------32

SPNU517C – March 2018
Submit Documentation Feedback

For all P other than zero

For P = 0(44)

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

975

LIN Communication Formats

www.ti.com

22.6.4.2 Superfractional Divider
The superfractional divider scheme applies to the following modes:• LIN master mode (synch field + identifier field + response field + checksum field)• LIN slave mode (response field + checksum field)
22.6.4.3 Superfractional Divider In LIN Mode
Building on the 4-bit fractional divider M (BRS[27:24], the superfractional divider uses an additional 3-bit
modulating value, illustrated in Table 22-7. The sync field (0x55), the identifier field and the response field
can all be seen as 8-bit data bytes flanked by a start bit and a stop bit. The bits with a 1 in the table will
have an additional VCLK period added to their Tbit.
Table 22-7. Superfractional Bit Modulation for LIN Master Mode and Slave Mode (1)BRS[30:28]

Start Bit

D[0]

D[1]

D[2]

D[3]

D[4]

D[5]

D[6]

D[7]

Stop Bit

0h

0

0

0

0

0

0

0

0

0

0

1h

1

0

0

0

0

0

0

0

1

0

2h

1

0

0

0

1

0

0

0

1

0

3h

1

0

1

0

1

0

0

0

1

0

4h

1

0

1

0

1

0

1

0

1

0

5h

1

1

1

0

1

0

1

0

1

1

6h

1

1

1

0

1

1

1

0

1

1

7h

1

1

1

1

1

1

1

0

1

1

(1)

1. In LIN master mode bit modulation applies to synch field + identifier field + response field
2. In LIN slave mode bit modulation applies to identifier field + response field
The baud rate will vary over a LIN data field to average according to the BRS[30:28] value by a d fractionof the peripheral internal clock: 0<d<1.
The instantaneous bit time is expressed in terms of TVCLK as follows:
For all P other than 0, and all M and d (0 or 1),

é æ
ù
Mö
T i bit = ê16ç P + 1 + ÷ + d úTVCLK
16 ø
ë è
û

(45)

For P = 0 Tbit = 32TVCLK
The averaged bit time is expressed in terms of TVCLK as follows.
For all P other than 0, and all M and d (0<d<1),

ù
é æ
M ö
T a b it = ê1 6 ç P + 1 +÷ + d ú TV C L K
16 ø
û
ë è

(46)

For P = 0 Tbit = 32TVCLKWith the superfractional divider, a LIN baud rate of 20 kbps is achievable with an internal clock VCLK of
726 kHz. Furthermore, a rate of 400 kbps is achievable with an VCLK of 14.6 MHz.

976

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

LIN Communication Formats

www.ti.com

22.6.5 Header Generation
Automatic generation of the LIN protocol header data stream is supported without CPU interaction. The
CPU will trigger a message header generation and the LIN state machine will handle the generation itself.
A master node initiates header generation on CPU writes to the IDBYTE in the LINID register. The header
is always sent by the master to initiate a LIN communication and consists of three fields: break field,
synchronization field, and identification field, as seen in Figure 22-15.
Figure 22-15. Message Header in Terms of Tbit
SDEL
1..4 Tbit

ID FIELD
10 TbitSYNCH FIELD
10 Tbit

STOP BIT

START BITSYNCH BREAK
13+(0...7) Tbit

1

•

•
•

0

1

0

1

0

1

0

The break field consists of two components:– The synchronization break (SYNCH BREAK) consists of a minimum of 13 (dominant) low bits to a
maximum of 20 dominant bits. The synch break length may be extended from the minimum with the
3-bit SBREAK value in the LINCOMP register.
– The synchronization break delimiter (SDEL) consists of a minimum of 1 (recessive) high bit to a
maximum of 4 recessive bits. The delimiter marks the end of the synchronization break field. The
synch break delimiter length depends on the 2-bit SDEL value in the LINCOMP register.
The synchronization field (SYNCH FIELD) consists of one start bit, byte 0x55, and a stop bit. It is used
to convey Tbit information and resynchronize LIN bus nodes.
The identifier field’s ID byte may use six bits as an identifier, with optional length control (seeNote:Optional Control Length Bits), and two optional bits as parity of the identifier. The identifier parity
is used and checked if the PARITY ENA bit is set. If length control bits are not used, then there can bea total of 64 identifiers plus parity. If neither length control or parity are used there can be up to 256
identifiers. See Figure 22-16 for an illustration of the ID field.
Figure 22-16. ID Field

ID 0

ID 1

ID2

ID3

ID 4

ID 5

O pti on al
Len gthC o n tr o l
B it s

P0

P1

Stop
Bit

Start
Bit

ID Fie ld

O pti o n a l
P a ri ty
B its

NOTE: Optional Control Length Bits
The control length bits only apply to LIN standards prior to LIN 1.3. IDBYTE field conveys
response length information if compliant to standards earlier than LIN1.3. The SCIFORMAT
register stores the length of the response for later versions of the LIN protocol.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

977

LIN Communication Formats

www.ti.com

NOTE: If the BLIN module, configured as Slave in multi-buffer mode, is in the process oftransmitting data while a new header comes in, the module might end up in responding withthe data from the previous interrupted response (not the data corresponding to the new ID).
To avoid this scenario the following procedure could be used:
1. Check for the Bit Error (BE) during the response transmission. If the BE flag is set, thisindicates that a collision has happened on the LIN bus (here because of the new Synch
Break).
2. In the Bit Error ISR, configure the TD0 and TD1 registers with the next set of data to betransmitted on a TX Match for the incoming ID. Before writing to TD0/TD1 make surethat there was not already an update because of a Bit Error; otherwise TD0/TD1 might
be written twice for one ID.
3. Once the complete ID is received, based on the match, the newly configured data will betransmitted by the node.

22.6.5.1 Event Triggered Frame Handling Proposal
The LIN 2.0 protocol uses event-triggered frames that may occasionally cause collisions. Event-triggered
frames have to be handled in software.
If no slave answers to an event triggered frame header, the master node will set the NRE flag, and a NREinterrupt will occur if enabled. If a collision occurs, a frame error and checksum error may arise before the
NRE error. Those errors are flagged and the appropriate interrupts will occur, if enabled.
Frame errors and checksum errors depend on the behavior and synchronization of the responding slaves.
If the slaves are totally synchronized and stop transmission once the collision occurred, it is possible that
only the NRE error is flagged despite the occurrence of a collision. To detect if there has been a receptionof one byte before the NRE error is flagged, the BUS BUSY flag can be used as an indicator.
The bus busy flag is set on the reception of the first bit of the header and remains set until the header
reception is complete, and again is set on the reception of the first bit of the response. In the case of acollision the flag is cleared in the same cycle as the NRE flag is set.
Software could implement the following sequence:• Once the reception of the header is done (poll for RXID flag), wait for the bus busy flag to get set or
NRE flag to get set.
• If bus busy flag is not set before NRE flag, then it is a true no response case (no data has beentransmitted onto the bus).
• If bus busy flag gets set, then wait for NRE flag to get set or for successful reception. If NRE flag is set,
then in this case a collision has occurred on the bus.
Even in the case of a collision, the received (corrupted) data is accessible in the RX buffers; registers
LINRD0 and LINRD1.

978

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

LIN Communication Formats

www.ti.com

22.6.5.2 Header Reception and Adaptive Baud Rate
A slave node baud rate can optionally be adjusted to the detected bit rate as an option to the LIN module.
The adaptive baud rate option is enabled by setting the ADAPT bit. During header reception, a slavemeasures the baud rate during detection of the synch field. If ADAPT bit is set, then the measured baudrate is compared to the slave node’s programmed baud rate and adjusted to the LIN bus baud rate if
necessary.
The LIN synchronizer determines two measurements: BRK_count and BAUD_count (Figure 22-17). These
values are always calculated during the Header reception for synch field validation (Figure 22-18).
Figure 22-17. Measurements for Synchronization
SYNCH BREAK

ID FIELD
10 TbitSYNCH FIELD
10 Tbit

STOP BIT

START BIT

SDEL

1

BRK_count
1

0

1

0

1

0

1

0

BAUD_count2

3

4

By measuring the values BRK_count and BAUD_count, a valid synch break sequence can be detected as
described in Figure 22-18. The four numbered events in Figure 22-17 signal the start/stop of thesynchronizer counter. The synchronizer counter uses VCLK as the time base.
The synchronizer counter is used to measure the synch break relative to the detecting node Tbit. For aslave node receiving the synch break, a threshold of 11 Tbit is used as required by the LIN protocol. For
detection of the dominant data stream of the synch break, the synchronizer counter is started on a fallingedge and stopped on a rising edge of the LINRX. On detection of the synch break delimiter, thesynchronizer counter value is saved and then reset.
On detection of five consecutive falling edges, the BAUD_count is measured. Bit timing calculation andconsistency to required accuracy is implemented following the recommendations of LIN revision 2.0. A
slave node can calculate a single Tbit time by division of BAUD_count by 8. In addition, for consistency
between the detected edges the following is evaluated:
BAUD_count + BAUD_count » 2 + BAUD_count » 3 ≤ BRK_count
The BAUD_count value is shifted 3 times to the right and rounded using the first insignificant bit to obtaina Tbit unit. If the ADAPT bit is set, then the detected baud rate is compared to the programmed baud rate.
During the header reception processing as illustrated in Figure 22-18, if the measured BRK_count value isless than 11 Tbit, the synch break is not valid according to the protocol for a fixed rate. If the ADAPT bit isset, then the MBRS register is used for measuring BRK_count and BAUD_count values and automaticallyadjusts to any allowed LIN bus rate (refer to LIN Specification Package 2.0).
NOTE: In adaptive mode the MBRS divider should be set to allow a maximum baud rate that is not
more than 10% above the expected operating baud rate in the LIN network. Otherwise a0x00 data byte could mistakenly be detected as a synch break.
The break-threshold relative to the slave node is 11 Tbit. The break is 13 Tbit as specified in
LIN version 1.3.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

979

LIN Communication Formats

www.ti.com

Figure 22-18. Synchronization Validation Process and Baud Rate Adjustment
LINRX=1
Wait for fallingedge

1

On LINRX

while
LINRX=0

Increment
countercounter ≥11Tb it ?

NooReset counter

Yes
Increment
counter
2

LINRX=0On LINRX

Save counter( SBRK_count)and reset it3

On 1st LINRX falling edge

increment
counter4

On 5th LINRX falling edge

Save counter ( BAUD_count)
Verify valid Synch Field
If ADAPT=1, compare baud rate and Baud
Update flag is set if baudrates differ

Receive ID Field
Wait for Response

980

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

LIN Communication Formats

www.ti.com

If the synch field is not detected within the given tolerances, the inconsistent-synch-field-error (ISFE) flag
will be set. An ISFE interrupt will be generated, if enabled by its respective bit in the SCISETINT register.
The ID byte should be received after the synch field validation was successful. Any time a valid break(larger than 11 Tbit) is detected, the receiver’s state machine should reset to reception of this new frame.
This reset condition is only valid during response state, not if an additional synch break occurs during
header reception.
NOTE: When an inconsistent synch field (ISFE) error occurs, suggested action for the application is
to Reset the SWnRST bit and Set the SWnRST bit to make sure that the internal statemachines are back to their normal states

22.6.6 Extended Frames Handling
The LIN protocol 2.0 and prior includes two extended frames with identifiers 62 (user defined) and 63(reserved extended). The response data length of the user-defined frame (ID 62, or 0x3E) is unlimited.
The length for this identifier will be set at network configuration time to be shared with the LIN bus nodes.
Extended frame communication is triggered on reception of a header with identifier 0x3E; see Figure 2219. Once the extended frame communication is triggered, unlike normal frames, this communicationneeds to be stopped before issuing another header. To stop the extended frame communication the
STOP EXT FRAME bit must be set.
Figure 22-19. Optional Embedded Checksum in Response for Extended Frames
Extended Frame With Embedded Checksum Bytes

N Data Fields Response

Master Header
In-frame space
Sync Break

Sync Field

ID Field

Checksum

Checksum

Checksum

An ID interrupt will be generated (if enabled and there is a match) on reception of ID 62 (0x3E). This
interrupt allows the CPU using a software counter to keep track of the bytes that are being sent out anddecides when to calculate and insert a checksum byte (recommended at periodic rates). To handle thisprocedure, SC bit is used. A write to the send checksum bit SC will initiate an automatic send of thechecksum byte. The last data field should always be a checksum in compliance with the LIN protocol.
The periodicity of the checksum insertion, defined at network configuration time, is used by the receiving
node to evaluate the checksum of the ongoing message, and has the benefit of enhanced reliability.
For the sending node, the checksum is automatically embedded each time the send checksum bit SC isset. For the receiving node, the checksum is compared each time the compare checksum bit CC is set;
see Figure 22-20.
NOTE: The LIN 2.0 enhanced checksum does not apply to the reserved identifiers. The reserved
identifiers always use the classic checksum.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

981

LIN Communication Formats

www.ti.com

Figure 22-20. Checksum Compare and Send for Extended Frames
CompareChecksum

7

SCIRXSHF

0

RX

0

TX

CHECKSUM CALCULATOR
Send
Checksum

7

SCITXSHF

22.6.7 Timeout Control
Any LIN node listening to the bus and expecting a response initiated from a master node could flag a noresponse error timeout event. The LIN protocol defines four types of timeout events, which are all handled
by the hardware of the LIN module. The four LIN protocol events are:• No-response timeout error• Bus idle detection• Timeout after wakeup signal• Timeout after three wakeup signals
22.6.7.1 No-Response Error (NRE)The no-response error will occur when any node expecting a response waits for TFRAME_MAX time and themessage frame is not fully completed within the maximum length allowed, TFRAME_MAX. After this time a noresponse error (NRE) is flagged in the NRE bit of the SCIFLR register. An interrupt is triggered if enabled.
As specified in the LIN 1.3 standard, the minimum time to transmit a frame is:
TFRAME_MIN = THEADER_MIN + TDATA_FIELD + TCHECKSUM_FIELD= 44 + 10N
where N = number of data fields.
And the maximum time frame is given by:
TFRAME_MAX = TFRAME_MIN * 1.4= (44 + 10N) * 1.4
The timeout value TFRAME_MAX is derived from the N number of data fields value. The N value is either
embedded in the header’s ID field for messages or is part of the description file. In the latter case, the 3bit CHAR value in SCIFORMAT register, will indicate the value for N.
NOTE: The length coding of the ID field does not apply to two extended frame identifiers, ID fields of
0x3E (62) and 0x3F (63). In these cases, the ID field can be followed by an arbitrary numberof data byte fields. Also, the LIN 2.0 protocol specification mentions that ID field 0x3F (63)cannot be used. For these two cases, the NRE will not be handled by the LIN controller
hardware.

982

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

LIN Communication Formats

www.ti.com

Table 22-8. Timeout Values in Tbit UnitsN

TDATA_FIELDTFRAME_MIN

TFRAME_MAX

1

10

54

76

2

20

64

90

3

30

74

104

4

40

84

118

5

50

94

132

6

60

104

146

7

70

114

160

8

80

124

174

22.6.7.2 Bus Idle Detection
The second type of timeout can occur when a node detects an inactive LIN bus: no transitions between
recessive and dominant values are detected on the bus. This happens after a minimum of 4 s (this is80,000 FLINCLK cycles with the fastest bus rate of 20 kbps). If a node detects no activity in the bus as the
TIMEOUT bit is set, then it can be assumed that the LIN bus is in sleep mode. Application software canuse the Timeout flag to determine when the LIN bus is inactive and put the LIN into sleep mode by writing
the POWERDOWN bit.
NOTE: After the timeout was flagged, a SW nRESET should be asserted before entering LowPower Mode. This is required to reset the receiver in case that an incomplete frame was on
the bus before the idle period.

22.6.7.3 Timeout after Wakeup Signal and Timeout after Three Wakeup Signals
The third and fourth types of timeout are related to the wakeup signal. A node initiating a wakeup should
expect a header from the master within a defined amount of time: timeout after wakeup signal. See
Section 22.9.3 for more details.

22.6.8 TXRX Error Detector (TED)
The following sources of error are detected by the TXRX error detector logic (TED). The TED logic
consists of a bit monitor, an ID parity checker, and a checksum error. The following errors are detected:• Bit errors (BE)• Physical bus errors (PBE)• Identifier parity errors (PE)• Checksum errors (CE)All of these errors (BE, PBE, PE, CE) are flagged. An interrupt for the flagged errors will be generated if
enabled. A message is valid for both the transmitter and the receiver if there is no error detected until theend of the frame.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

983

LIN Communication Formats

www.ti.com

22.6.8.1 Bit Errors
A bit error (BE) is detected at the bit time when the bit value that is monitored is different from the bit valuethat is sent. A bit error is indicated by the BE flag in SCIFLR. After signaling a BE, the transmission isaborted no later than the next byte. The bit monitor ensures that the transmitted bit in LINTX is the correct
value on the LIN bus by reading back on the LINRX pin as shown in Figure 22-21.
NOTE: If BE Occurs due to New Header reception during a Slave Response, NRE/TIMEOUT flag
will not be set for the new Frame.

Figure 22-21. TXRX Error Detector
ID
PARITYCHECKER

ID-Parity-Error
ID-Parity Error Flag
ID-Pairty Interrupt(if enabled)

Checksum-Error Flag
Checksum-Error Int.
(if enabled)

CHECKSUMCALCULATORVBAT7SCIRXSHF

Bit-Error Flag
Bit-Error Int. (if enabled)
Bus-Error Flag
Bus-Error Int. (if enabled)

7

SCITXSHF

0

BIT MONITOR=0

LIN BUS

RX

T
X

GND

22.6.8.2 Physical Bus Errors
A Physical Bus Error (PBE) has to be detected by a master if no valid message can be generated on thebus (Bus shorted to GND or VBAT). The bit monitor detects a PBE during the header transmission, if noSynch Break can be generated (for example, because of a bus shortage to VBAT) or if no Synch break
Delimiter can be generated (for example, because of a bus shortage to GND). Once the Synch BreakDelimiter was validated, all other deviations between the monitored and the sent bit value are flagged as
Bit Errors (BE) for this frame.
22.6.8.3 ID Parity Errors
If parity is enabled, an ID parity error (PE) is detected if any of the two parity bits of the sent ID byte are
not equal to the calculated parity on the receiver node. The two parity bits are generated using thefollowing mixed parity algorithm.

P 0 = ID 0 Å ID 1 Å ID 2 Å ID 4 ( even P a rity )P 1 = ID 1 Å ID 3 Å ID 4 Å ID 5 ( o d d P a rity )(47)

If an ID-parity error is detected, the ID-parity error is flagged, and the received ID is not valid. See
Section 22.6.9 for details.

984

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

LIN Communication Formats

www.ti.com

22.6.8.4 Checksum Errors
A checksum error (CE) is detected and flagged at the receiving end if the calculated modulo-256 sum over
all received data bytes (including the ID byte if it is the enhanced checksum type) plus the checksum byte
does not result in 0xFF. The modulo-256 sum is calculated over each byte by adding with carry, where thecarry bit of each addition is added to the LSB of its resulting sum.
For the transmitting node, the checksum byte sent at the end of a message is the inverted sum of all thedata bytes (see Figure 22-22) for classic checksum implementation. The checksum byte is the inverted
sum of the identifier byte and all the data bytes (see Figure 22-23) for the LIN 2.0 compliant enhanced
checksum implementation. The classic checksum implementation should always be used for reserved
identifiers 60 to 63; therefore, the CTYPE bit will be overridden in this case. For signal-carrying-frame
identifiers (0 to 59) the type of checksum used depends on the CTYPE bit.
Figure 22-22. Classic Checksum Generation at Transmitting Node

Response

Checksum
Field

1 to 8 Data Fields

Checkbyte+

Modulo-256 sum

INVERT

Figure 22-23. LIN 2.0-Compliant Checksum Generation at Transmitting Node

Response

From
HeaderID Field

Checksum
Field

1 to 8 Data Fields

Checkbyte
Modulo-256 sum

SPNU517C – March 2018
Submit Documentation Feedback+

INVERT

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

985

LIN Communication Formats

www.ti.com

22.6.9 Message Filtering and Validation
Message filtering uses the entire identifier to determine which nodes will participate in a response, either
receiving or transmitting a response. Therefore, two acceptance masks are used, as shown in Figure 2224. During header reception, all nodes filter the ID-Field (ID-Field is the part of the header explained in
Figure 22-16) to determine whether they transmit a response or receive a response for the current
message. There are two masks for message ID filtering: one to accept a response reception, the other toinitiate a response transmission. See Figure 22-24. All nodes compare the received ID to the identifier
stored in the ID-SlaveTask BYTE of the LINID register and use the RX ID MASK and the TX ID MASK
fields in the LINMASK register to filter the bits of the identifier that should not be compared.
If there is an RX match with no parity error and the RXENA bit is set, there will be an ID RX flag and aninterrupt will be triggered if enabled. If there is a TX match with no parity error and the TXENA bit is set,
there will be an ID TX flag and an interrupt will be triggered if enabled in the SCISETINT register.
The masked bits become don’t cares for the comparison. To build a mask for a set of identifiers, an XOR
function could be used.
For example, to build a mask to accept IDs 0x26 and 0x25 using LINID[7:0] = 0x20; that is, compare 5
most significant bits (MSBs) and filter 3 least significant bits (LSBs), the acceptance mask could be:( 0 x 26 + 0 x 25 ) Å 0 x 20 = 0 x 07

(48)

A mask of all zeros will compare all bits of the received identifier in the shift register with the ID-BYTE in
LINID[7:0]. If HGEN CTRL is set to 1, a mask of 0xFF will always cause a match. A mask of all 1s will
filter all bits of the received identifier, and thus there will be an ID match regardless of the content of the
ID-SlaveTask BYTE field in the LINID register.
NOTE: When the HGEN CTRL bit = 0, the LIN nodes compare the received ID to the ID-BYTE fieldin the LINID register, and use the RX ID MASK and the TX ID MASK in the LINMASK
register to filter the bits of the identifier that should not be compared.
If there is an RX match with no parity error and the RXENA bit is set, there will be an ID RX
flag and an interrupt will be triggered if enabled. A mask of all 0s will compare all bits of thereceived identifier in the shift register with the ID-BYTE field in LINID[7:0]. A mask of all 1s
will filter all bits of the received identifier and there will be no match.

During header reception, the received identifier is copied to the Received ID field LINID[23:16]. If there isno parity error and there is either a TX match or an RX match, then the corresponding TX or RX ID flag isset. If the ID interrupt is enabled, then an ID interrupt is generated.
After the ID interrupt is generated, the CPU may read the Received ID field LINID[23:16] and determine
what response to load into the transmit buffers.
NOTE: When byte 0 is written to TD0 (LINTD0[31:24]), the response transmission is automaticallygenerated.

In multi-buffer mode, the TXRDY flag will be set when all the response data bytes and checksum byte arecopied to the shift register SCITXSHF. In non multi-buffer mode, the TXRDY flag is set each time a byte iscopied to the SCITXSHF register, and also for the last byte of the frame after the checksum byte is copied
to the SCITXSHF register.
In multi-buffer mode, the TXEMPTY flag is set when both the transmit buffer(s) TDy and the SCITXSHF
shift register are emptied and the checksum has been sent. In non multi-buffer mode, TXEMPTY is set
each time TD0 and SCITXSHF are emptied, except for the last byte of the frame where the checksum
byte must also be transmitted.
If parity is enabled, all slave receiving nodes will validate the identifier using all eight bits of the received
ID byte. The SCI/LIN will flag a corrupted identifier if an ID-parity error is detected.

986

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

LIN Communication Formats

www.ti.com

Figure 22-24. ID Reception, Filtering and Validation
Parity Enable

ID
ParityChecke r

RX

7

ID Parity Error

23

LI NID

16

7

SCIRXSHF

0

7

RX ID M ask

0

I D-Byte

No
ID-Pa rit y
Error

=

0

0

7 ID- Slave Task Byte 0

1

HGEN CTRL

7

7

TX ID Mask

ID-Byt e

RX
Match

From
SCIRXSHF

=

0

0

0

7 ID- SlaveTaskByte 0

1

TX
Match

RXENA

AND

ID-RX
Flag

No
ID-Parit y
Error

A ND

ID
INT

ID-TX
F la g

HGEN CTRLSPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

987

LIN Communication Formats

www.ti.com

22.6.10 Receive Buffers
To reduce CPU load when receiving a LIN N-byte (with N = 1–8) response in interrupt mode , the SCI/LIN
module has eight receive buffers. These buffers can store an entire LIN response in the RDy receive
buffers.
The checksum byte following the data bytes is validated by the internal checksum calculator. The
checksum error (CE) flag indicates a checksum error and a CE interrupt will be generated if enabled in the
SCISETINT register.
The multi-buffer 3-bit counter counts the data bytes transferred from the SCIRXSHF register to the RDy
receive buffers if multi-buffer mode is enabled, or to RD0 if multi-buffer mode is disabled. The 3-bit
compare register contains the number of data bytes expected to be received. In cases where the ID BYTE
field does not convey message length (see Note:Optional Control Length Bits in Section 22.6.5), the
LENGTH value, indicates the expected length and is used to load the 3-bit compare register. Whether thelength control field or the LENGTH value is used is selectable with the COMM MODE bit.
Figure 22-8 illustrates the receive buffers.
A receive interrupt and a receive ready RXRDY flag set could occur after receiving a response if there are
no response receive errors for the frame (such as, there is no checksum error, frame error, and overrun
error). The checksum byte will be compared before acknowledging a reception.

NOTE: In multi-buffer mode following are the scenarios associated with clearing the "RXRDY" flagbit:
1. The RXRDY flag cannot be cleared by reading the corresponding interrupt offset in the
SCIINTVECT0/1 register.
2. For LENGTH less than or equal to 4, Read to RD0 register will clear the “RXRDY” flag.
3. For LENGTH greater than 4, Read to RD1 register will clear the “RXRDY” flag.

22.6.11

Transmit Buffers

To reduce the CPU load when transmitting a LIN N-byte (with N = 1–8) response in interrupt mode, the
SCI/LIN module has eight transmit buffers, TD0–TD7 in LINTD0 and LINTD1. With these transmit buffers,
an entire LIN response field can be pre-loaded in the TXy transmit buffers.
The multi-buffer 3-bit counter counts the data bytes transferred from the TDy transmit buffers register if
multi-buffer mode is enabled, or from TD0 to SCITXSHF if multi-buffer mode is disabled. The 3-bit
compare register contains the number of data bytes expected to be transmitted. If the ID field is not used
to convey message length (see Note: Optional Control Length Bits in Section 22.6.5), the LENGTH value
indicates the expected length and is used instead to load the 3-bit compare register. Whether the length
control field or the LENGTH value is used is selectable with the COMM MODE bit.
A transmit interrupt (TX interrupt), and a transmit ready flag (TXRDY flag) could occur after transmitting a
response.
Figure 22-9 illustrates the transmit buffers.
The checksum byte will be automatically generated by the checksum calculator and sent after the datafields transmission is finished. The multi-buffer 3-bit counter counts the data bytes transferred from the
TDy buffers into the SCITXSHF register.
NOTE: The transmit interrupt request can be eliminated until the next series of data is written into
the transmit buffers LINTD0 and LINTD1, by disabling the corresponding interrupt via the
SCICLRINT register or by disabling the transmitter via the TXENA bit.

988

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

LIN Interrupts

www.ti.com

22.7 LIN Interrupts
LIN and SCI mode have a common Interrupt block as explained in Section 22.3. There are 16 interrupt
sources in the SCI/LIN module, with 8 of them being LIN mode only, as seen in Table 22-4.
A LIN message frame indicating the timing and sequence of the LIN interrupts that could occur is shown in
Figure 22-25.
Figure 22-25. LIN Message Frame Showing LIN Interrupt Timing and Sequence
TFrameMax
Slave Response

Master Header

TBus Idle (4s)In-frame space

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

Timeout - Bus Idle (4s) Int.

No Response Error Int.

FE
Checksum Error Int.
RX Int. (multi-buffer/
last byte single buffer)

Frame Error Int. (FE)TX Int. (multi buffer/
last byte single buffer)

RX Int. (single buffer)
TX Int. (single buffer)

RX Int. (single buffer)
Overrun Error Int.
TX Int. (single buffer)

Bit Error Int.

Parity Error Int.
ID Interrupt

Physical Bus
Error Int.(Master)

ChecksumFE

ISF Error Int.

1, 2, 3, ...8 Data Fields

FE

ID FieldFE

Sync Field

TX Int. (single buffer)

Sync Break989

LIN Configurations

www.ti.com

22.8 LIN Configurations
The following list details the configuration steps that software should perform prior to the transmission or
reception of data in LIN mode. As long as the SWnRST bit in the SCIGCR1 register is cleared to 0 theentire time that the LIN is being configured, the order in which the registers are programmed is notimportant.
• Enable LIN by setting the RESET bit in SCIGCR0 to 1.
• Clear the SWnRST bit to 0 before LIN is configured.
• Select the desired frame format by programming the SCIGCR1 register.
• Set both the RX FUNC and TX FUNC bits in SCIPIO0 to 1 to configure the LINRX and LINTX pins for
LIN functionality.
• Set the LIN MODE bit in SCIGCR1 to 1 to enable LIN mode.
• Select Master or Slave mode by programming the CLOCK bit in SCIGCR1.
• Set the MBUF MODE bit in SCIGCR1 to 1 to select multi-buffer mode.
• Select the baud rate to be used for communication by programming the BRS register.
• Set the maximum baud rate to be used for communication by programming the MBRS register.
• Set the CONT bit in SCIGCR1 to 1 to make LIN not halt for an emulation breakpoint until its current
reception or transmission is complete (this bit is used only in an emulation environment).
• Set LOOP BACK bit in SCIGCR1 to 1 to connect the transmitter to the receiver internally (this featureis used to perform a self-test).
• Set the RXENA bit in SCIGCR1 to 1, if data is to be received.
• Set the TXENA bit in SCIGCR1 to 1, if data is to be transmitted.
• Select the RX ID MASK and the TX ID MASK fields in the LINMASK register.
• Set the SWnRST bit to 1 after LIN is configured.
• Perform receiving or transmitting data (see Section 22.8.1 or Section 22.8.2).

22.8.1 Receiving Data
The LIN receiver is enabled to receive messages if both the RX FUNC bit and the RXENA bit are set to 1.
If the RX FUNC bit is not set, the LINRX pin functions as a general-purpose I/O pin rather than as a LIN
function pin.
The ID RX FLAG is set after a valid LIN ID is received with RX Match. An ID interrupt is generated, if
enabled.
22.8.1.1 Receiving Data in Single-Buffer Mode
Single-buffer mode is selected when the MBUF MODE bit is cleared to 0. In this mode, LIN sets the
RXRDY bit when it transfers newly received data from SCIRXSHF to RD0. The SCI clears the RXRDY bit
after the new data in RD0 has been read. Also, as data is transferred from SCIRXSHF to RD0, the LIN
sets the FE, OE, or PE flags if any of these error conditions were detected in the received data. Theseerror conditions are supported with configurable interrupt capability.
You can receive data by:
1. Polling Receive Ready Flag
2. Receive Interrupt
In polling method, software can poll for the RXRDY bit and read the data from RD0 byte of the LINRD0register once the RXRDY bit is set high. The CPU is unnecessarily overloaded by selecting the polling
method. To avoid this, you can use the interrupt method. To use the interrupt method, the SET RX INT bit
is set. An interrupt is generated the moment the RXRDY bit is set. If the checksum scheme is enabled by
setting the Compare Checksum (CC) bit to 1, the checksum will be compared on the byte that is currently
being received, which is expected to be the checksum byte. The CC bit will be cleared once the checksum
is received. A CE will immediately be flagged if there is a checksum error.

990

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

LIN Configurations

www.ti.com

22.8.1.2 Receiving Data in Multi-Buffer Mode
Multi-buffer mode is selected when the MBUF MODE bit is set to 1. In this mode, LIN sets the RXRDY bit
after receiving the programmed number of data in the receive buffer and the checksum field, the complete
frame. The error condition detection logic is similar to the single-buffer mode, except that it monitors forthe complete frame. Like single-buffer mode, you can use the polling or interrupt method to read the data.
The received data has to be read from the LINRD0 and LINRD1 registers, based on the number of bytes.
For a LENGTH less than or equal to 4, a read from the LINRD0 register clears the RXRDY flag. For a
LENGTH greater than 4, a read from the LINRD1 register clears the RXRDY flag. If the checksum scheme
is enabled by setting the Compare Checksum (CC) bit to 1 during the reception of the data, then the bytethat is received after the reception of the programmed number of data bytes indicated by the LENGTH
field is treated as a checksum byte. The CC bit will be cleared once the checksum is received andcompared.

22.8.2 Transmitting Data
The LIN transmitter is enabled if both the TX FUNC bit and the TXENA bit are set to 1. If the TX FUNC bit
is not set, the LINTX pin functions as a general-purpose I/O pin rather than as a LIN function pin. Anyvalue written to the TD0 before the TXENA bit is set to 1 is not transmitted. Both of these control bits allow
for the LIN transmitter to be held inactive independently of the receiver.
The ID TX flag is set after a valid LIN ID is received with TX Match. An ID interrupt is generated, if
enabled.
22.8.2.1 Transmitting Data in Single-Buffer Mode
Single-buffer mode is selected when the MBUF MODE bit is cleared to 0. In this mode, LIN waits for data
to be written to TD0, transfers it to SCITXSHF, and transmits the data. The TXRDY and TX EMPTY bits
indicate the status of the transmit buffers. That is, when the transmitter is ready for data to be written to
TD0, the TXRDY bit is set. Additionally, if both TD0 and SCITXSHF are empty, then the TX EMPTY bit isalso set.
You can transmit data by:
1. Polling Transmit Ready Flag
2. Transmit Interrupt
In polling method, software can poll for the TXRDY bit to go high before writing the data to the TD0. The
CPU is unnecessarily overloaded by selecting the polling method. To avoid this, you can use the interrupt
method. To use the interrupt method, the SET TX INT bit is set. An interrupt is generated the moment the
TXRDY bit is set. When the LIN has completed transmission of all pending frames, the SCITXSHF registerand the TD0 are empty, the TXRDY bit is set, and an interrupt is generated, if enabled. Because all data
has been transmitted, the interrupt should be halted. This can either be done by disabling the transmit
interrupt (CLR TX INT) or by disabling the transmitter (clear TXENA bit). If the checksum scheme isenabled by setting the Send Checksum (SC) bit to 1, the checksum byte will be sent after the current byte
transmission. The SC bit will be cleared after the checksum byte has been transmitted.

NOTE: The TXRDY flag cannot be cleared by reading the corresponding interrupt offset in the
SCIINTVECT0 or SCIINTVECT1 register.

22.8.2.2 Transmitting Data in Multi-Buffer Mode
Multi-buffer mode is selected when the MBUF MODE bit is set to 1. Like single-buffer mode, you can use
the polling or interrupt method to write the data to be transmitted. The transmitted data has to be written to
the LINTD0 and LINTD1 registers, based on the number of bytes. LIN waits for data to be written to Byte
0 (TD0) of the LINTD0 register and transfers the programmed number of bytes to SCITXSHF to transmit
one by one automatically. If the checksum scheme is enabled by setting the Send Checksum (SC) bit to 1,
the checksum will be sent after transmission of the last byte of the programmed number of data bytes,
indicated by the LENGTH field. The SC bit will be cleared after the checksum byte has been transmitted.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

991

Low-Power Mode

www.ti.com

22.9 Low-Power Mode
The SCI/LIN module can be put in either local or global low-power mode. Global low-power mode isasserted by the system and is not controlled by the SCI/LIN module. During global low-power mode, allclocks to the SCI/LIN are turned off so the module is completely inactive. If global low-power mode isrequested while the receiver is receiving data, then the SCI/BLIN completes the current reception andthen enters the low-power mode, that is, module enters low-power mode only when Busy bit (SCIFLR.3) iscleared.
The BLIN module may enter low-power mode either when there was no activity on the LINRX pin for morethan 4s (this can be either a constant recessive or dominant level) or when a Sleep Command frame wasreceived. Once the Timeout flag (SCIFLR.4) was set or once a Sleep Command was received, the
POWERDOWN bit (SCIGCR2.0) must be set by the application software to make the module enter local
low-power mode. A wakeup signal will terminate the sleep mode of the LIN bus.
NOTE: Enabling Local Low-Power Mode During Receive and Transmit
If the wakeup interrupt is enabled and low-power mode is requested while the receiver isreceiving data, then the SCI/LIN immediately generates a wake-up interrupt to clear the
powerdown bit. Thus, the SCI/LIN is prevented from entering low-power mode andcompletes the current reception. Otherwise, if the wakeup interrupt is disabled, the SCI/LIN
completes the current reception and then enters the low-power mode.

22.9.1 Entering Sleep ModeIn LIN protocol, a sleep command is used to broadcast the sleep mode to all nodes. The sleep commandconsists of a diagnostic master request frame with identifier 0x3C (60), with the first data field as 0x00.
There should be no activity in the bus once all nodes receive the sleep command: the bus is in sleep
mode.
Local low-power mode is asserted by setting the POWERDOWN bit; setting this bit stops the clocks to the
SCI/LIN internal logic and registers. Clearing the POWERDOWN bit causes SCI/LIN to exit from local lowpower mode. All the registers are accessible during local power-down mode. If a register is accessed in
low-power mode, this access results in enabling the clock to the module for that particular access alone.

992

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation FeedbackLow-Power Mode

www.ti.com

22.9.2 Wakeup
The wakeup interrupt is used to allow the SCI/LIN module to automatically exit low-power mode. A
SCI/LIN wakeup is triggered when a low level is detected on the receive RX pin, and this clears the
POWERDOWN bit.
NOTE: If the wakeup interrupt is disabled then the SCI/LIN enters low-power mode whenever it isrequested to do so, but a low level on the receive RX pin does NOT cause the SCI/LIN toexit low-power mode.

In LIN mode, any node can terminate sleep mode by sending a wakeup signal; see Figure 22-26. A slave
node that detects the bus in sleep mode, and with a wakeup request pending, will send a wakeup signal.
The wakeup signal is a dominant value on the LIN bus for TWUSIG; this is at least 5 Tbits for the LIN bus
baud rates. The wakeup signal is generated by sending an 0xF0 byte containing 5 dominant Tbits and 5
recessive Tbits.
Figure 22-26. Wakeup Signal Generation
WAKEUP SIGNALSYNCH BREAK

BUS INOPERATIONAL MODE

BUS IN SLEEP MODE

TWUSIG

TINITIALIZE

0.25ms ≤ TWUSIG ≤ 5ms(49)

Assuming a perfect bus with no noise or loading effects, a write of 0xF0 to TD0 will load the transmitter tomeet the wakeup signal timing requirement for TWUSIG. Then, setting the GENWU bit will transmit thepreloaded value in TD0 for a wakeup signal transmission.
NOTE: The GENWU bit can be set/reset only when SWnRST is set to’1’ and the node is in power
down mode. The bit will be cleared on a valid synch break detection. A master sending a
wakeup request, will exit power down mode upon reception of the wakeup pulse. The bit will
be cleared on a SWnRST. This can be used to stop a master from sending further wakeup
requests.

The TI TPIC1021 LIN transceiver, upon receiving a wakeup signal, will translate it to the microcontroller
for wakeup with a dominant level on the RX pin, or a signal to the voltage regulator. While the
POWERDOWN bit is set, if the LIN module detects a recessive-to-dominant edge (falling edge) on the RX
pin, it will generate a wakeup interrupt if enabled in the SCISETINT register.
According to LIN protocol 2.0, the TI TPIC1021 LIN transceiver detecting a dominant level on the bus
longer than 150 ms will detect it as a wakeup request. The LIN controller’s slave is ready to listen to thebus in less than 100 ms (TINITIALIZE<100ms) after a dominant-to-recessive edge (end-of-wakeup signal).

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated993

Low-Power Mode

www.ti.com

22.9.3 Wakeup Timeouts
The LIN protocol defines the following timeouts for a wakeup sequence. After a wakeup signal has been
sent to the bus, all nodes wait for the master to send a header. If no synch field is detected before 150 ms(3,000 cycles at 20 kHz) after wakeup signal is transmitted, a new wakeup is sent by the same node thatrequested the first wakeup. This sequence is not repeated more than two times. After three attempts towake up the LIN bus, wakeup signal generation is suspended for a 1.5 s (30,000 cycles at 20 kHz) period
after three breaks.
NOTE: To achieve compatibility to LIN1.3 timeout conditions, the MBRS register must be set toassure that the LIN 2.0 (real-time-based) timings meet the LIN 1.3 bit time base. A node
triggering the wakeup should set the MBRS register accordingly to meet the targeted time as
128 Tbits × programmed prescaler.
The LIN controller handles the wakeup expiration times defined by the LIN protocol with ahardware implementation.

22.10 Emulation ModeIn emulation mode, the CONT bit determines how the SCI/LIN operates when the program is suspended.
The SCI/LIN counters are affected by this bit during debug mode. when set, the counters are not stopped
and when cleared, the counters are stopped debug mode.
Any reads in emulation mode to a SCI/LIN register will not have any effect on the flags in the SCIFLR
register.
NOTE: When emulation mode is entered during the Frame transmission or reception of the frame
and CONT bit is not set, Communication is not expected to be successful. The suggested
usage is to set CONT bit during emulation mode for successful communication.

994

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

22.11 SCI/LIN Control Registers
The SCI/LIN module registers are based on the SCI registers, with added functionality registers enabledby the LIN MODE bit in the SCIGCR1 register.
These registers are accessible in 8-, 16-, and 32-bit reads or writes. The SCI/LIN is controlled andaccessed through the registers listed in Table 22-9. Among the features that can be programmed are the
LIN protocol mode, communication and timing modes, baud rate value, frame format, and interrupt
configuration. The base address for the control registers is FFF7 E400h.
Table 22-9. SCI/LIN Control Registers
OffsetAcronym

Register Description

Section00h

SCIGCR0SCI Global Control Register 0

Section 22.11.1

04h

SCIGCR1SCI Global Control Register 1

Section 22.11.2

08h

SCIGCR2SCI Global Control Register 2

Section 22.11.3

0Ch

SCISETINTSCI Set Interrupt Register

Section 22.11.4

10h

SCICLEARINTSCI Clear Interrupt Register

Section 22.11.5

14h

SCISETINTLVLSCI Set Interrupt Level Register

Section 22.11.6

18h

SCICLEARINTLVLSCI Clear Interrupt Level Register

Section 22.11.7

1Ch

SCIFLRSCI Flags Register

Section 22.11.8

20h

SCIINTVECT0SCI Interrupt Vector Offset 0

Section 22.11.9

24h

SCIINTVECT1SCI Interrupt Vector Offset 1

Section 22.11.10
Section 22.11.11

28h

SCIFORMATSCI Format Control Register

2Ch

BRS

Baud Rate Selection Register

Section 22.11.12

30h

SCIED

Receiver Emulation Data Buffer

Section 22.11.13.1

34h

SCIRD

Receiver Data Buffer

Section 22.11.13.2

38h

SCITD

Transmit Data Buffer

Section 22.11.13.3

3Ch

SCIPIO0SCI Pin I/O Control Register 0

Section 22.11.14

40h

SCIPIO1SCI Pin I/O Control Register 1

Section 22.11.15

44h

SCIPIO2SCI Pin I/O Control Register 2

Section 22.11.16

48h

SCIPIO3SCI Pin I/O Control Register 3

Section 22.11.17

4Ch

SCIPIO4SCI Pin I/O Control Register 4

Section 22.11.18

50h

SCIPIO5SCI Pin I/O Control Register 5

Section 22.11.19

54h

SCIPIO6SCI Pin I/O Control Register 6

Section 22.11.20

58h

SCIPIO7SCI Pin I/O Control Register 7

Section 22.11.21

5Ch

SCIPIO8SCI Pin I/O Control Register 8

Section 22.11.22

60h

LINCOMPARE

LIN Compare Register

Section 22.11.23

64h

LINRD0

LIN Receive Buffer 0 Register

Section 22.11.24

68h

LINRD1

LIN Receive Buffer 1 Register

Section 22.11.25

6Ch

LINMASK

LIN Mask Register

Section 22.11.26

70h

LINID

LIN Identification Register

Section 22.11.27

74h

LINTD0

LIN Transmit Buffer 0

Section 22.11.28

78h

LINTD1

LIN Transmit Buffer 1

Section 22.11.29

7Ch

MBRS

Maximum Baud Rate Selection Register

Section 22.11.30

90h

IODFTCTRL

Input/Output Error Enable Register

Section 22.11.31

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

995

SCI/LIN Control Registers

www.ti.com

22.11.1 SCI Global Control Register 0 (SCIGCR0)
The SCIGCR0 register defines the module reset. Figure 22-27 and Table 22-10 illustrate this register.
Figure 22-27. SCI Global Control Register 0 (SCIGCR0) [offset = 00]
31

16
Reserved
R-0

15

1

0

Reserved

RESET

R-0

RWP-0

LEGEND: R/W = Read/Write; R = Read only; RWP = Read/Write in privileged mode only; -n = value after reset

Table 22-10. SCI Global Control Register 0 (SCIGCR0) Field Descriptions
Bit

Field

31-1

Reserved

0

RESET

Value
0

Description
Reads return 0. Writes have no effect.
This bit resets the SCI/LIN module. This bit is effective in SCI and LIN mode.

0

SCI/LIN module is in reset.

1

SCI/LIN module is out of reset.
Note: Read/Write in privileged mode only.

996

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

22.11.2 SCI Global Control Register 1 (SCIGCR1)
The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI.
Figure 22-28 and Table 22-11 illustrate this register.
Figure 22-28. SCI Global Control Register 1 (SCIGCR1) [offset = 04h]
31

25

24

Reserved

26

TXENA

RXENA

R-0

R/W-0

R/W-0

23

18

15

14

17

16

Reserved

CONT

LOOP BACK

R-0

R/W-0

R/W-0

13

12

11

10

9

8

Reserved

STOP EXTFRAME

HGEN CTRL

CTYPE

MBUF MODE

ADAPT

SLEEP

R-0

R/WL-0R/WL-0R/WL-0

R/W-0

R/WL-0

R/W-0

7

6

5

4

3

2

1

0

SWnRST

LIN MODE

CLOCK

STOP

PARITYPARITY ENA

TIMING MODE

COMM MODE

R/W-0

R/W-0

R/W-0

R/WC-0

R/WC-0

R/W-0

R/WC-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; WC = Write in SCI-compatible mode only; WL = Write in
LIN mode only; -n = value after reset

Table 22-11. SCI Global Control Register 1 (SCIGCR1) Field Descriptions
Bit

Field

31-26

Reserved

25

TXENA

Value
0

Description
Reads return 0. Writes have no effect.
Transmit enable. This bit is effective in LIN and SCI modes. Data is transferred from SCITD, or
the TDy (with y=0, 1,...7) buffers in LIN mode to the SCITXSHF shift out register only when the
TXENA bit is set.

0

Transfers from SCITD or TDy to SCITXSHF are disabled.

1

Transfers from SCITD or TDy to SCITXSHF are enabled.
Note: Data written to SCITD or the transmit multi-buffer before TXENA is set is nottransmitted. If TXENA is cleared while transmission is ongoing, the data previously
written to SCITD is sent (including the checksum byte in LIN mode).

24

RXENA

Receive enable. This bit is effective in LIN and SCI modes. RXENA allows or prevents thetransfer of data from SCIRXSHF to SCIRD or the receive multi-buffers.
0

The receiver will not transfer data from the shift buffer to the receive buffer or multi-buffers.

1

The receiver will transfer data from the shift buffer to the receive buffer or multi-buffers.
Note: Clearing RXENA stops received characters from being transferred into the receive
buffer or multi-buffers, prevents the RX status flags (see Table 22-12) from being updated
by receive data, and inhibits both receive and error interrupts. However, the shift register
continues to assemble data regardless of the state of RXENA.
Note: If RXENA is cleared before a frame is completely received, the data from the frame
is not transferred into the receive buffer.
Note: If RXENA is set before a frame is completely received, the data from the frame istransferred into the receive buffer. If RXENA is set while SCIRXSHF is in the process ofassembling a frame, the status flags are not assured to be accurate for that frame. To
ensure that the status flags correctly reflect what was detected on the bus during aparticular frame, RXENA should be set before the detection of that frame.

23-18

Reserved

SPNU517C – March 2018
Submit Documentation Feedback0

Reads return 0. Writes have no effect.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

997

SCI/LIN Control Registers

www.ti.com

Table 22-11. SCI Global Control Register 1 (SCIGCR1) Field Descriptions (continued)
Bit

Field

17

CONT

16

15-14
13

12

Value

Continue on suspend. This bit is effective in LIN and SCI modes. This bit has an effect only
when a program is being debugged with an emulator, and it determines how the SCI/LIN
operates when the program is suspended. The SCI/LIN counters are affected by this bit: when
the bit is set the counters are not stopped, when the bit is cleared the counters are stopped
during debug mode.
0

When debug mode is entered, the SCI/LIN state machine is frozen. Transmissions and LIN
counters are halted and resume when debug mode is exited.

1

When debug mode is entered, the SCI/LIN continues to operate until the current transmit andreceive functions are complete.

LOOP BACKReserved

Description

Loopback bit. This bit is effective in LIN and SCI modes. The self-checking option for the
SCI/LIN can be selected with this bit. If the LINITX and LINRX pins are configured with SCI/LIN
functionality, then the LINTX pin is internally connected to the LINRX pin. Externally, during loop
back operation, the LINTX pin outputs a high value and the LINRX pin is in a high-impedancestate. If this bit value is changed while the SCI/LIN is transmitting or receiving data, errors may
result.
0Loop back mode is disabled.

1

Loop back mode is enabled.

0

Reads return 0. Writes have no effect.

STOP EXT FRAME

Stop extended frame communication. This bit is effective in LIN mode only. This bit can be
written only during extended frame communication. When the extended frame communication is
stopped, this bit is cleared automatically.
0This bit has no effect.

1

Extended frame communication will be stopped when current frame transmission/reception iscompleted.

HGEN CTRL

HGEN control. This bit is effective in LIN mode only. This bit controls the type of mask filtering
comparison
0

ID filtering using the ID-BYTE field in LIN Identification Register (LINID) occurs.
Mask of FFh in LIN Mask Register (LINMASK) register will result in no match.

1

ID filtering uses ID-SlaveTask BYTE (recommended).
Mask of FFh in LIN Mask Register (LINMASK) register will result in ALWAYS match.
Note: For software compatibility with future LIN modules the HGEN CTRL bit must be set
to 1, the RX ID MASK must be set to FFh and the TX ID MASK must be set to FFh.

11

10

9

998

CTYPE

Checksum type. This bit is effective in LIN mode only. This bit controls the type of checksum tobe used: classic or enhanced.
0Classic checksum is used.

1

Enhanced checksum is used.

MBUF MODE

Multi-buffer mode. This bit is effective in LIN and SCI modes. This bit controls receive/transmit
buffer usage, that is, whether the RX/TX multi-buffers are used or a single register, RD0/TD0, isused.
0The multi-buffer mode is disabled.

1

The multi-buffer mode is enabled.

ADAPT

Adapt. This mode is effective in LIN mode only. This bit has an effect during the detection of thesynch field. Two LIN protocol bit rate modes could be enabled with this bit according to thenode capability file definition: automatic or select. The software and network configuration will
decide which of these two modes are enabled. When this bit is cleared, the LIN 2.0 protocol
fixed bit rate should be used. If the ADAPT bit is set, a SCI/LIN slave node detecting the baudrate will compare it to the prescalers in BRS register and update it if they are different. The BRS
register will be updated with the new value. If this bit is not set there will be no adjustment to
the BRS register.
0

Automatic baud rate adjustment is disabled.

1

Automatic baud rate adjustment is enabled.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

Table 22-11. SCI Global Control Register 1 (SCIGCR1) Field Descriptions (continued)
Bit

Field

8

SLEEP

Value

Description
SCI sleep. This bit is effective in SCI mode only. In a multiprocessor configuration, this bit
controls the receive sleep function. Clearing this bit brings the SCI/LIN out of sleep mode.

0

Sleep mode is disabled.

1

Sleep mode is enabled.
Note: The receiver still operates when the SLEEP bit is set; however, RXRDY is updated
and SCIRD is loaded with new data only when an address frame is detected. The
remaining receiver status flags (see Table 22-12 ) are updated and an error interrupt isrequested if the corresponding interrupt enable bit is set, regardless of the value of the
SLEEP bit. In this way, if an error is detected on the receive data line while the SCI isasleep, software can promptly deal with the error condition.
Note: The SLEEP bit is not automatically cleared when an address byte is detected.
See Section 22.5.1 for more information on using the SLEEP bit for multiprocessor
communication.

7

SWnRST

Software reset (active low). This bit is effective in LIN and SCI modes.
0

The SCI/LIN is in its reset state; no data will be transmitted or received. Writing a 0 to this bit
initializes the SCI/LIN state machines and operating flags as defined in Table 22-12 andTable 22-13. All affected logic is held in the reset state until a 1 is written to this bit.

1

The SCI/LIN is in its ready state; transmission and reception can be done. After this bit is set to1, the configuration of the module should not change.
Note: The SCI/LIN should only be configured while SWnRST = 0.

65

LIN MODE

LIN mode. This bit is effective in LIN and SCI mode. This bit controls the module mode ofoperation.
0

LIN mode is disabled; SCI mode is enabled.

1

LIN mode is enabled; SCI mode is disabled.

CLOCK

SCI internal clock enable. The CLOCK bit determines the source of the module clock on the
SCICLK pin. It also determines whether a LIN node is a slave or master.
SCI mode0

The external SCICLK is the clock source.
Note: If an external clock is selected, then the internal baud rate generator and baud rate
registers are bypassed. The maximum frequency allowed for an externally sourced SCI
clock is VCLK/16.

1

The internal SCICLK is the clock source.
LIN mode

40

The node is in slave mode.

1

The node is in master mode.

STOP

SCI number of stop bits per frame. This bit is effective in SCI mode only.
0

One stop bit is used.

1

Two stop bits are used.
Note: The receiver checks for only one stop bit. However in idle-line mode, the receiverwaits until the end of the second stop bit (if STOP = 1) to begin checking for an idle
period.

3

PARITYSCI parity odd/even selection. This bit is effective in SCI mode only. If the PARITY ENA bit isset, PARITY designates odd or even parity.
0

Odd parity is used.

1

Even parity is used.
The parity bit is calculated based on the data bits in each frame and the address bit (inaddress-bit mode). The start and stop fields in the frame are not included in the parity
calculation.
For odd parity, the SCI transmits and expects to receive a value in the parity bit thatmakes odd the total number of bits in the frame with the value of 1.
For even parity, the SCI transmits and expects to receive a value in the parity bit thatmakes even the total number of bits in the frame with the value of 1.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

999

SCI/LIN Control Registers

www.ti.com

Table 22-11. SCI Global Control Register 1 (SCIGCR1) Field Descriptions (continued)
Bit

Field

2

PARITY ENA

Value

Description
Parity enable. This bit enables or disables the parity function.
SCI or buffered SCI mode0

Parity is disabled; no parity bit is generated during transmission or is expected during reception.

1

Parity is enabled. A parity bit is generated during transmission and is expected during reception.
LIN mode

10

ID field parity verification is disabled.

1

ID field parity verification is enabled.

TIMING MODE

0

SCI timing mode bit. This bit is effective in SCI mode only. it selects the SCI timing mode.
0

Synchronous timing is used.

1

Asynchronous timing is used.

COMM MODE

SCI/LIN communication mode bit. In compatibility mode it selects the SCI communication mode.
In LIN mode it selects length control option for ID-field bits ID4 and ID5.
SCI mode0

Idle-line mode is used.

1

Address-bit mode is used.
LIN mode0

ID4 and ID5 are not used for length control.

1

ID4 and ID5 are used for length control.

Table 22-12. SCI Receiver Status Flags(1)

SCI Flag

Register

Bit

Value After Reset (1)CE

SCIFLR

29

0

ISFE

SCIFLR

28

0

NRE

SCIFLR

27

0FE

SCIFLR

26

0OE

SCIFLR

25

0PE

SCIFLR

24

0

RXWAKESCIFLR

12

0

RXRDY

SCIFLR

90

BUSY

SCIFLR

30IDLE

SCIFLR

2

0

WAKE UPSCIFLR

1

0

BRKDT

SCIFLR00

The flags are frozen with their reset value while SWnRST = 0.

Table 22-13. SCI Transmitter Status Flags

(1)

1000

SCI Flag

Register

Bit

Value After Reset (1)BE

SCIFLR

31

0

PBE

SCIFLR30

0

TX WAKESCIFLR

10

0

TX EMPTYSCIFLR

11

1

TXRDY

SCIFLR

8

1

The flags are frozen with their reset value while SWnRST = 0.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

22.11.3 SCI Global Control Register 2 (SCIGCR2)The SCIGCR2 register is used to send or compare a checksum byte during extended frames, to generate
a wakeup and for low-power mode control of the LIN module. Figure 22-29 and Table 22-14 illustrate thisregister.
Figure 22-29. SCI Global Control Register 2 (SCIGCR2) [offset = 08h]
31

18

15

17

16

Reserved

CC

SC

R-0

R/WL-0R/WL-0

9

8

7

1

0

Reserved

GEN WU

Reserved

POWERDOWN

R-0

R/W-0

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; WL = Write in LIN mode only; -n = value after reset

Table 22-14. SCI Global Control Register 2 (SCIGCR2) Field Descriptions
Bit

Field

31-18

Reserved

17

Value
0

CC

Description
Reads return 0. Writes have no effect.
Compare checksum. LIN mode only. This bit is used by the receiver for extended frames to triggera checksum compare. The user will initiate this transaction by writing a one to this bit. CC bit has tobe set only after RX_RDY flag is set for the last received data.
In non-multi-buffer mode, when the CC bit is set, the checksum will be compared on the byte that is
expected to be the checksum byte.
During multi-buffer mode, the following scenarios are associated with the CC bit:a) If the CC bit is set during the reception of the data, then the byte that is received after the
reception of the programmed number of data bytes as indicated by SCIFORMAT[18:16] is treatedas a checksum byte.
b) If the CC bit is set during the idle period (that is, during the inter-frame space), then theimmediate next byte will be treated as a checksum byte.
c) CC bit will be auto cleared after the checkbyte has been received and compared. Checksum
reception is not guaranteed if CC bit is write cleared by software during the checksum reception.
See Section 22.6.6 for more details.

160

No checksum compare will occur.

1

Compare checksum on expected checksum byte.

SC

Send checksum byte. This bit is effective in LIN mode only. This bit is used by the transmitter withextended frames to send a checksum byte. In non-multi-buffer mode, the checksum byte will besent after the current byte transmission. In multi-buffer mode, the checksum byte will be sent after
the last byte count, indicated by the SCIFORMAT[18:16]). See Section 22.6.6 for more details. This
byte will be cleared after the checksum byte has been transmitted.
In non-multi-buffer mode, the checksum byte will be sent after the current byte transmission.
During multi-buffer mode, the following scenarios are associated with the SC bit:a) The checkbyte will be sent after the last byte count, indicated by the SCIFORMAT[18:16]).
b) Checksum will not be sent if SC is set before transmitting the very first byte(that is, during
interframe space).
c) SC bit will be auto cleared after the checkbyte has been transmitted. Checksum transmission is
not guaranteed if SC bit is write cleared by software during the checksum transmission. See
Section 22.6.6 for more details.

15-9

Reserved

8

GEN WU

7-1

Reserved

SPNU517C – March 2018
Submit Documentation Feedback0

No checksum byte will be sent.

1

A checksum byte will be sent.

0

Reads return 0. Writes have no effect.
Generate wakeup signal. This bit is effective in LIN mode only. This bit controls the generation of a
wakeup signal, by transmitting the TDO buffer value. The LIN protocol specifies that this signal
should be a dominant for T WUSIG. This bit is cleared on reception of a valid synch break.

0

No wakeup signal will be generated.

1

The TDO buffer value will be transmitted for a wakeup signal. The bit will be cleared on a SWnRST.

0

Reads return 0. Writes have no effect.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1001

SCI/LIN Control Registers

www.ti.com

Table 22-14. SCI Global Control Register 2 (SCIGCR2) Field Descriptions (continued)
Bit

Field

0

POWERDOWN

Value

Description
Power down. This bit is effective in LIN or SCI mode. When this bit is set, the SCI/LIN module
attempts to enter local low-power mode. If the POWERDOWN bit is set while the receiver is actively
receiving data and the wakeup interrupt is disabled, then the SCI/LIN will delay entering low-powermode until the reception is completed. In LIN mode, the user may set the POWERDOWN bit after
receiving a sleep command or on idle bus detection (more than 4 seconds). See Section 22.9 formore information on low-power mode.

0

The SCI/LIN module is in normal operation.

1

The SCI/LIN module enters local low-power mode.

22.11.4 SCI Set Interrupt Register (SCISETINT)
Figure 22-30 and Table 22-15 illustrate this register. Refer Figure 22-30 for details on when different
interrupt flags get set in a frame during LIN Mode.
Figure 22-30. SCI Set Interrupt Register (SCISETINT) [offset = 0Ch]
31

30

29

28

27

26

25

24

SET
BE INTSETPBE INTSETCE INT

SETISFE INTSET
NRE INTSETFE INTSETOE INTSETPE INT

R/WL-0R/WL-0R/WL-0R/WL-0R/WL-0

R/W-0

R/W-0

R/W-0

23

16
Reserved
R-0

15

14

13

12

10

9

8

ReservedSET
ID INT

ReservedSET
RX INTSETTX INT

R-0

R/WL-0

R-0

R/W-0

R/W-0

7

6

5

4

SET
TOA3WUS INTSETTOAWUS INT

Reserved

SET
TIMEOUT INT

R/WL-0R/WL-0R-0

R/WL-03

2

1

0Reserved

SET
WAKEUP INTSETBRKDT INT

R-0

R/W-0

R/WC-0LEGEND: R/W = Read/Write; R = Read only; WL = Write in LIN mode only; WC = Write in SCI-compatible mode only; -n = value after reset

Table 22-15. SCI Set Interrupt Register (SCISETINT) Field Descriptions
Bit

Field

31

SET BE INT

Value

Description
Set bit error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN
module to generate an interrupt when there is a bit error.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1
30

SET PBE INT

Read or write: The interrupt is enabled.
Set physical bus error interrupt. This bit is effective in LIN mode only. Setting this bit enables
the SCI/LIN module to generate an interrupt when a physical bus error occurs.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1
29

SET CE INT

Read or write: The interrupt is enabled.
Set checksum-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the
SCI/LIN module to generate an interrupt when there is a checksum error.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

1002

Read or write: The interrupt is enabled.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

Table 22-15. SCI Set Interrupt Register (SCISETINT) Field Descriptions (continued)
Bit

Field

28

SET ISFE INT

Value

Description
Set inconsistent-synch-field-error interrupt. This bit is effective in LIN mode only. Setting this bit
enables the SCI/LIN module to generate an interrupt when there is an inconsistent synch fielderror.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1
27

SET NRE INT

Read or write: The interrupt is enabled.
Set no-response-error interrupt. This bit is effective in LIN mode only. Setting this bit enables
the SCI/LIN module to generate an interrupt when a no-response error occurs.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1
26

SET FE INT

Read or write: The interrupt is enabled.
Set framing-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit
enables the SCI/LIN module to generate an interrupt when a framing error occurs.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1
25

SET OE INT

Read or write: The interrupt is enabled.
Set overrun-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit
enables the SCI/LIN module to generate an interrupt when an overrun error occurs.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1
24

SET PE INT

Read or write: The interrupt is enabled.
Set parity interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables
the SCI/LIN module to generate an interrupt when a parity error occurs.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

23-14

Reserved13

SET ID INT

1Read or write: The interrupt is enabled.

0

Reads return 0. Writes have no effect.
Set identification interrupt. This bit is effective in LIN mode only. This bit is set to enable aninterrupt when a valid matching identifier is received. See Section 22.6.9 for more details.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

12-10

Reserved

9

SET RX INT

1Read or write: The interrupt is enabled.

0

Reads return 0. Writes have no effect.
Receiver interrupt enable. This bit is effective in LIN or SCI-compatible mode. Setting this bit
enables the SCI/LIN to generate a receive interrupt after a frame has been completely received
and the data is being transferred from SCIRXSHF to SCIRD.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1
8

SET TX INTRead or write: The interrupt is enabled.
Set transmitter interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit
enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to
SCITXSHF and the TXRDY bit is being set.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1
7

SET TOA3WUS INTRead or write: The interrupt is enabled.
Set timeout after three wakeup signals interrupt. This bit is effective in LIN mode only. Setting
this bit enables the SCI/LIN to generate an interrupt when a timeout occurs after three wakeup
signals have been sent.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

SPNU517C – March 2018
Submit Documentation Feedback

Read or write: The interrupt is enabled.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1003

SCI/LIN Control Registers

www.ti.com

Table 22-15. SCI Set Interrupt Register (SCISETINT) Field Descriptions (continued)
Bit

Field

6

SET TOAWUS INT

Value

Description
Set timeout after wakeup signal interrupt. This bit is effective in LIN mode only. Setting this bit
enables the SCI/LIN to generate an interrupt when a timeout occurs after one wakeup signal
has been sent.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

5

Reserved

4

SET TIMEOUT INT

1Read or write: The interrupt is enabled.

0

Reads return 0. Writes have no effect.
Set timeout interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN
to generate an interrupt when there is no LIN bus activity (bus idle) for at least four seconds.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

3-2

Reserved

1

SET WAKEUP INT

1Read or write: The interrupt is enabled.

0

Reads return 0. Writes have no effect.
Set wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit
enables the SCI/LIN to generate a wakeup interrupt and thereby exit low-power mode. If
enabled, the wakeup interrupt is asserted when local low-power mode is requested while thereceiver is busy or if a low level is detected on the LINRX pin during low-power mode.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

10

SET BRKDT INT

Read or write: The interrupt is enabled.
Set break-detect interrupt. This bit is effective in SCI-compatible mode only. Setting this bit
enables the SCI/LIN to generate an error interrupt if a break condition is detected on the LINRX
pin.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

1004

Read or write: The interrupt is enabled.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

22.11.5 SCI Clear Interrupt Register (SCICLEARINT)
Figure 22-31 and Table 22-16 illustrate this register. SCICLEARINT register is used to clear the enabledinterrupts without accessing SCISETINT register.
Figure 22-31. SCI Clear Interrupt Register (SCICLEARINT) [offset = 10h]
31

30

29

28

27

26

25

24

CLR
BE INT

CLR
PBE INT

CLR
CE INT

CLR
ISFE INT

CLR
RE INT

CLR
FE INT

CLR
OE INT

CLR
PE INT

R/WL-0R/WL-0R/WL-0R/WL-0R/WL-0

R/W-0

R/W-0

R/W-0

23

16
Reserved
R-0

15

9

8

Reserved

14

CLR
ID INT

13

12
Reserved

CLR
RX INT

CLR
TX INT

R-0

R/WL-0

R-0

R/W-0

R/W-0

7

6

5

4

CLR
TOA3WUS INT

CLRTOAWUS INT

Reserved

CLR
TIMEOUT INT

R/WL-0R/WL-0R-0

R/WL-0

10

3

2

1

0

Reserved

CLR
WAKEUP INT

CLRBRKDT INT

R-0

R/W-0

R/WC-0LEGEND: R/W = Read/Write; R = Read only; WL = Write in LIN mode only; WC = Write in SCI-compatible mode only; -n = value after reset

Table 22-16. SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions
Bit

Field

31

CLR BE INT

Value

Description
Clear bit error interrupt. This bit is effective in LIN mode only. This bit disables the bit error
interrupt when set.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: The interrupt is disabled.

30

CLR PBE INT

Clear physical bus error interrupt. This bit is effective in LIN mode only. This bit disables thephysical-bus error interrupt when set.
0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: The interrupt is disabled.

29

CLR CE INT

Clear checksum-error interrupt. This bit is effective in LIN mode only. This bit disables thechecksum interrupt when set.
0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: The interrupt is disabled.

28

CLR ISFE INT

Clear inconsistent-synch-field-error (ISFE) interrupt. This bit is effective in LIN mode only. Thisbit disables the ISFE interrupt when set.
0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: The interrupt is disabled.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1005

SCI/LIN Control Registers

www.ti.com

Table 22-16. SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions (continued)
Bit

Field

27

CLR NRE INT

Value

Description
Clear no-response-error interrupt. This bit is effective in LIN mode only. This bit disables the
NRE interrupt when set.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: The interrupt is disabled.

26

CLR FE INT

Clear framing-error interrupt. This bit is effective in LIN or SCI mode. This bit disables theframing-error interrupt when set.
0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: The interrupt is disabled.

25

CLR OE INT

Clear overrun-error interrupt. This bit is effective in LIN or SCI mode. This bit disables the
SCI/LIN overrun error interrupt when set.
0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: The interrupt is disabled.

24

CLR PE INT

Clear parity interrupt. This bit is effective in LIN or SCI mode. This bit disables the parity error
interrupt when set.
0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: The interrupt is disabled.

23-14

Reserved

13

CLR ID INT

0

Reads return 0. Writes have no effect.
Clear ID interrupt. This bit is effective in LIN mode only. This bit disables the ID interrupt whenset.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: The interrupt is disabled.

12-10

Reserved

9

CLR RX INT

0

Reads return 0. Writes have no effect.
Clear receiver interrupt. This bit is effective in LIN or SCI mode. This bit disables the receiverinterrupt when set.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: The interrupt is disabled.

8

CLR TX INT

Clear transmitter interrupt. This bit is effective in LIN or SCI mode. This bit disables thetransmitter interrupt when set.
0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: The interrupt is disabled.

7

CLR TOA3WUS INT

Clear timeout after three wakeup signals interrupt. This bit is effective in LIN mode only. This bit
disables the timeout after three wakeup signals interrupt when set.
0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: The interrupt is disabled.

1006

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

Table 22-16. SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions (continued)
Bit

Field

6

CLR TOAWUS INT

Value

Description
Clear timeout after wakeup signal interrupt. This bit is effective in LIN mode only. This bit
disables the timeout after one wakeup signal interrupt when set.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: The interrupt is disabled.

5

Reserved

4

CLR TIMEOUT INT

0

Reads return 0. Writes have no effect.
Clear timeout interrupt. This bit is effective in LIN mode only. This bit disables the timeout (LIN
bus idle) interrupt when set.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: The interrupt is disabled.

3-2

Reserved

1

CLR WAKEUP INT

0

Reads return 0. Writes have no effect.
Clear wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. This bit disables
the wakeup interrupt when set.

0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: The interrupt is disabled.

0

CLR BRKDT INT

Clear break-detect interrupt. This bit is effective in SCI-compatible mode only. This bit disables
the break-detect interrupt when set.
0

Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt is enabled.
Write: The interrupt is disabled.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1007

SCI/LIN Control Registers

www.ti.com

22.11.6 SCI Set Interrupt Level Register (SCISETINTLVL)
Figure 22-32 and Table 22-17 illustrate this register.
Figure 22-32. SCI Set Interrupt Level Register (SCISETINTLVL) [offset = 14h]
31

30

29

28

27

26

25

24

SET BEINT LVLSET PBEINT LVLSET CEINT LVLSET ISFE
INT LVLSET NREINT LVLSET FEINT LVLSET OEINT LVLSET PEINT LVL

R/WL-0R/WL-0R/WL-0R/WL-0R/WL-0

R/W-0

R/W-0

R/W-0

23

16
Reserved
R-0

15

14

13

12

10

9

8

Reserved

SET ID
INT LVL

Reserved

SET RX
INT LVLSET TX
INT LVL

R-0

R/WL-0

R-0

R/W-0

R/W-0

7

6

5

4

SET
TOA3WUSINT LVLSETTOAWUS
INT LVL

Reserved

SET
TIMEOUTINT LVL

R/WL-0R/WL-0R-0

R/WL-03

2

1

0Reserved

SET
WAKEUP
INT LVLSETBRKDTINT LVL

R-0

R/W-0

R/WC-0LEGEND: R/W = Read/Write; R = Read only; WL = Write in LIN mode only; WC = Write in SCI-compatible mode only; -n = value after reset

Table 22-17. SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions
Bit

Field

31

SET BE INT LVL

Value

Description
Set bit error interrupt level. This bit is effective in LIN mode only.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1
30

SET PBE INT LVL

Read or write: The interrupt level is mapped to the INT1 line.
Set physical bus error interrupt level. This bit is effective in LIN mode only.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1
29

SET CE INT LVL

Read or write: The interrupt level is mapped to the INT1 line.
Set checksum-error interrupt level. This bit is effective in LIN mode only.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1
28

SET ISFE INT LVL

Read or write: The interrupt level is mapped to the INT1 line.
Set inconsistent-synch-field-error interrupt level. This bit is effective in LIN mode only.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1
27

SET NRE INT LVL

Read or write: The interrupt level is mapped to the INT1 line.
Set no-response-error interrupt level. This bit is effective in LIN mode only.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1
26

SET FE INT LVL

Read or write: The interrupt level is mapped to the INT1 line.
Set framing-error interrupt level. This bit is effective in LIN or SCI-compatible mode.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

1008

Read or write: The interrupt level is mapped to the INT1 line.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

Table 22-17. SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions (continued)
Bit

Field

25

SET OE INT LVL

Value

Description
Set overrun-error interrupt level. This bit is effective in LIN or SCI-compatible mode.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1
24

SET PE INT LVL

Read or write: The interrupt level is mapped to the INT1 line.
Set parity error interrupt level. This bit is effective in LIN or SCI-compatible mode.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

23-14
13

Reserved

1

Read or write: The interrupt level is mapped to the INT1 line.

0

Reads return 0. Writes have no effect.

SET ID INT LVL

Set ID interrupt level. This bit is effective in LIN mode only.
0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

12-10
9

Reserved

1

Read or write: The interrupt level is mapped to the INT1 line.

0

Reads return 0. Writes have no effect.

SET RX INT LVL

Set receiver interrupt level. This bit is effective in LIN or SCI-compatible mode.
0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1
8

SET TX INT LVL

Read or write: The interrupt level is mapped to the INT1 line.
Set transmitter interrupt level. This bit is effective in LIN or SCI-compatible mode.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1
7

SET TOA3WUS INT LVL

Read or write: The interrupt level is mapped to the INT1 line.
Set timeout after three wakeup signals interrupt level. This bit is effective in LIN mode only.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1
6

SET TOAWUS INT LVL

Read or write: The interrupt level is mapped to the INT1 line.
Set timeout after wakeup signal interrupt level. This bit is effective in LIN mode only.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

5

Reserved

4

SET TIMEOUT INT LVL

1

Read or write: The interrupt level is mapped to the INT1 line.

0

Reads return 0. Writes have no effect.
Set timeout interrupt level. This bit is effective in LIN mode only.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

3-2

Reserved

1

SET WAKEUP INT LVL

1

Read or write: The interrupt level is mapped to the INT1 line.

0

Reads return 0. Writes have no effect.
Set wake-up interrupt level. This bit is effective in LIN or SCI-compatible mode.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

10

SET BRKDT INT LVL

Read or write: The interrupt level is mapped to the INT1 line.
Set break-detect interrupt level. This bit is effective in SCI-compatible mode only.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

SPNU517C – March 2018
Submit Documentation Feedback

Read or write: The interrupt level is mapped to the INT1 line.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1009

SCI/LIN Control Registers

www.ti.com

22.11.7 SCI Clear Interrupt Level Register (SCICLEARINTLVL)
Figure 22-33 and Table 22-18 illustrate this register.
Figure 22-33. SCI Clear Interrupt Level Register (SCICLEARINTLVL) [offset = 18h]
31

30

29

28

27

26

25

24

CLR BEINT LVL

CLR PBEINT LVL

CLR CEINT LVL

CLR ISFE
INT LVL

CLR NREINT LVL

CLR FEINT LVL

CLR OEINT LVL

CLR PEINT LVL

R/WL-0R/WL-0R/WL-0R/WL-0R/WL-0

R/W-0

R/W-0

R/W-0

23

16
Reserved
R-0

15

14

13

12

10

9

8

Reserved

CLR ID
INT LVL

Reserved

CLR RX
INT LVL

CLR TX
INT LVL

R-0

R/WL-0

R-0

R/W-0

R/W-0

7

6

5

4

CLR
TOA3WUSINT LVLCLR
TOAWUS
INT LVL

Reserved

CLR
TIMEOUTINT LVL

R/WL-0R/WL-0R-0

R/WL-03

2

1

0Reserved

CLR
WAKEUP
INT LVLCLR
BRKDT
INT LVL

R-0

R/W-0

R/WC-0LEGEND: R/W = Read/Write; R = Read only; WL = Write in LIN mode only; WC = Write in SCI-compatible mode only; -n = value after reset

Table 22-18. SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions
Bit

Field

31

CLR BE INT LVL

Value

Description
Clear bit error interrupt. This bit is effective in LIN mode only.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.

30

CLR PBE INT LVL

Clear physical bus error interrupt. This bit is effective in LIN mode only.
0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.

29

CLR CE INT LVL

Clear checksum-error interrupt. This bit is effective in LIN mode only.
0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.

28

CLR ISFE INT LVL

Clear inconsistent-synch-field-error (ISFE) interrupt. This bit is effective in LIN mode only.
0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.

27

CLR NRE INT LVL

Clear no-response-error interrupt. This bit is effective in LIN mode only.
0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.

1010

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

Table 22-18. SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions (continued)
Bit

Field

26

CLR FE INT LVL

Value

Description
Clear framing-error interrupt. This bit is effective in LIN or SCI-compatible mode.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.

25

CLR OE INT LVL

Clear overrun-error interrupt. This bit is effective in LIN or SCI-compatible mode.
0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.

24

CLR PE INT LVL

Clear parity interrupt. This bit is effective in LIN or SCI-compatible mode.
0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.

23-14
13

Reserved

0

CLR ID INT LVL

Reads return 0. Writes have no effect.
Clear ID interrupt. This bit is effective in LIN mode only.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.

12-10
9

Reserved

0

CLR RX INT LVL

Reads return 0. Writes have no effect.
Clear receiver interrupt. This bit is effective in LIN or SCI-compatible mode.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.

8

CLR TX INT LVL

Clear transmitter interrupt. This bit is effective in LIN or SCI-compatible mode.
0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.

7

CLR TOA3WUS INT LVL

Clear timeout after three wakeup signals interrupt. This bit is effective in LIN mode only.
0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.

6

CLR TOAWUS INT LVL

Clear timeout after wakeup signal interrupt. This bit is effective in LIN mode only.
0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.

5

Reserved

SPNU517C – March 2018
Submit Documentation Feedback0

Reads return 0. Writes have no effect.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1011

SCI/LIN Control Registers

www.ti.com

Table 22-18. SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions (continued)
Bit

Field

4

CLR TIMEOUT INT LVL

Value

Description
Clear timeout interrupt. This bit is effective in LIN mode only.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.

3-2

Reserved

1

CLR WAKEUP INT LVL

0

Reads return 0. Writes have no effect.
Clear wake-up interrupt. This bit is effective in LIN or SCI-compatible mode.

0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.

0

CLR BRKDT INT LVL

Clear break-detect interrupt. This bit is effective in SCI-compatible mode only.
0

Read: The interrupt level is mapped to the INT0 line.
Write: Writing a 0 to this bit has no effect.

1

Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.

1012

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

22.11.8 SCI Flags Register (SCIFLR)
Figure 22-34 and Table 22-19 illustrate this register.
Figure 22-34. SCI Flags Register (SCIFLR) [offset = 1Ch]
31

30

29

28

27

26

25

24

BE

PBE

CE

ISFE

NRE

FE

OE

PE

R/WL-0R/WL-0R/WL-0R/WL-0R/WL-0

R/W-0

R/W-0

R/W-0

23

16
Reserved
R-0

15

14

13

12

11

10

9

8

Reserved

ID RX

ID TX

RX WAKETX EMPTY

TX WAKERX RDYTX RDY

R-0

R/WL-0R/WL-0

R/WC-0

R/W-1

R/WC-0

R/W-0

R/W-1

7

6

5

4

3

2

1

0

TOA3WUSTOAWUS

Reserved

TIMEOUT

BUSY

IDLE

WAKEUP

BRKDT

R/WL-0R/WL-0R-0

R/WL-0R/W-0

R-0

R/WL-0

R/WC-0LEGEND: R/W = Read/Write; R = Read only; WC = Write in SCI-compatible mode only; WL = Write in LIN mode only; -n = value after reset

Table 22-19. SCI Flags Register (SCIFLR) Field Descriptions
Bit

Field

31

BE

Value

Description
Bit error flag. This bit is effective in LIN mode only. This bit is set when a bit error has occurred.
This is detected by the internal bit monitor. See Section 22.6.8 for more information. The bit error
flag is cleared by any of the following:
•
•
•
•
•
•

0

Setting of the SWnRST bit
Setting of the RESET bit
A system reset
Writing a 1 to this bit
On reception of a new synch breakReading the corresponding interrupt offset in SCIINTVECT0/1

Read: No error has been detected since this bit was last cleared.
Write: Writing a 0 to this bit has no effect.

1

Read: An error has been detected since this bit was last cleared.
Write: The bit is cleared to 0.

30

PBE

Physical bus error flag. This bit is effective in LIN mode only. This bit is set when a physical bus
error has been detected by the bit monitor in TED. See Section 22.6.8 for more information. The
physical bus error flag is cleared by the following:
•
•
•
•
•
•

Setting of the SWnRST bit
Setting of the RESET bit
A system reset
Writing a 1 to this bit
On reception of a new synch breakReading the corresponding interrupt offset in SCIINTVECT0/1

Note: The PBE will only be flagged, if no Synch Break can be generated (for example,
because of a bus shortage to VBAT) or if no Synch Break Delimiter can be generated (forexample, because of a bus shortage to GND).
0

Read: No error has been detected since this bit was last cleared.
Write: Writing a 0 to this bit has no effect.

1

Read: An error has been detected since this bit was last cleared.
Write: The bit is cleared to 0.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1013

SCI/LIN Control Registers

www.ti.com

Table 22-19. SCI Flags Register (SCIFLR) Field Descriptions (continued)
Bit

Field

29

CE

Value

Description
Checksum error flag. This bit is effective in LIN mode only. This bit is set when a checksum error
has been detected by a receiving node. This error is detected by the TED logic. See Section 22.6.8
for more information. The type of checksum to be used depends on the CTYPE bit in SCIGCR1.
The checksum error flag is cleared by the following:
•
•
•
•
•
•

0

Setting of the SWnRST bit
Setting of the RESET bit
A system reset
Writing a 1 to this bit
Reception of a new synch breakReading the corresponding interrupt offset in SCIINTVECT0/1

Read: No error has been detected since this bit was last cleared.
Write: Writing a 0 to this bit has no effect.

1

Read: An error has been detected since this bit was last cleared.
Write: The bit is cleared to 0.

28

ISFE

Inconsistent synch field error flag. This bit is effective in LIN mode only. This bit is set when an
inconsistent synch field error has been detected by the synchronizer during header reception. See
Section 22.6.5.2 for more information. The inconsistent synch field error flag is cleared by thefollowing:
•
•
•
•
•
•
0

Setting of the SWnRST bit
Setting of the RESET bit
A system reset
Writing a 1 to this bit
Reception of a new synch breakReading the corresponding interrupt offset in SCIINTVECT0/1

Read: No inconsistent synch field error has been detected.
Write: Writing a 0 to this bit has no effect.

1

Read: An inconsistent synch field error has been detected.
Write: The bit is cleared to 0.

27

NRE

No-response error flag. This bit is effective in LIN mode only. This bit is set when there is no
response to a master's header completed within TFRAME_MAX. This timeout period is applied formessage frames of known length (identifiers 0 to 61). This error is detected by the synchronizer.
See Section 22.6.7 for more information. The no-response error flag is cleared by the following:
•
•
•
•
•
•
0

Setting of the SWnRST bit
Setting of the RESET bit
A system reset
Writing a 1 to this bit
Reception of a new synch breakReading the corresponding interrupt offset in SCIINTVECT0/1

Read: No no-response error has been detected since the last clear.
Write: Writing a 0 to this bit has no effect.

1

Read: A no-response error has been detected.
Write: The bit is cleared to 0.

1014

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

Table 22-19. SCI Flags Register (SCIFLR) Field Descriptions (continued)
Bit

Field

26

FE

Value

Description
Framing error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when an
expected stop bit is not found. In SCI compatibility mode, only the first stop bit is checked. The
missing stop bit indicates that synchronization with the start bit has been lost and that the characteris incorrectly framed. Detection of a framing error causes the SCI/LIN to generate an error interrupt
if the SET FE INT bit is set in the register SCISETINT. The framing error flag is cleared by thefollowing:
•
•
•
•
•
•

Setting of the SWnRST bit
Setting of the RESET bit
A system reset
Writing a 1 to this bit
Reading the corresponding interrupt offset in SCIINTVECT0/1
Reception of a new character/frame, depending on whether the module is in SCI compatible or
LIN mode

In multi-buffer mode the frame is defined in the SCIFORMAT register.
0

Read: No framing error has been detected since the last clear.
Write: Writing a 0 to this bit has no effect.

1

Read: A framing error has been detected since the last clear.
Write: The bit is cleared to 0.

25

OE

Overrun error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when thetransfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy
buffers in LINRD0 and LINRD1. Detection of an overrun error causes the LIN to generate an error
interrupt if the SET OE INT bit = 1. The OE flag is reset by the following:
•
•
•
•
•
0

Setting of the SWnRST bit
Setting of the RESET bit
A system reset
Writing a 1 to this bit
Reading the corresponding interrupt offset in SCIINTVECT0/1

Read: No overrun error has been detected since the last clear.
Write: Writing a 0 to this bit has no effect.

1

Read: An overrun error has been detected.
Write: The bit is cleared to 0.

24

PE

Parity error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity
error is detected in the received data. In SCI address-bit mode, the parity is calculated on the data
and address bit fields of the received frame. In idle-line mode, only the data is used to calculate
parity. An error is generated when a character is received with a mismatch between the number of
1s and its parity bit. If the parity function is disabled (SCIGCR[2] = 0), the PE flag is disabled andread as 0. Detection of a parity error causes the LIN to generate an error interrupt if the SET PE
INT bit = 1. The PE bit is reset by the following:
•
•
•
•
•

Setting of the SWnRST bit
Setting of the RESET bit
A system reset
Writing a 1 to this bit
Reception of a new character or frame, depending on whether the module is in SCI compatibleor LIN mode, respectively.
• Reading the corresponding interrupt offset in SCIINTVECT0/1
0

Read: No parity error has been detected since the last clear.
Write: Writing a 0 to this bit has no effect.

1

Read: A parity error has been detected.
Write: The bit is cleared to 0.

23-15

Reserved

SPNU517C – March 2018
Submit Documentation Feedback0

Reads return 0. Writes have no effect.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1015

SCI/LIN Control Registers

www.ti.com

Table 22-19. SCI Flags Register (SCIFLR) Field Descriptions (continued)
Bit

Field

14

ID RX

Value

Description
Identifier on receive flag. This bit is effective in LIN mode only. This flag is set once an identifier isreceived with an receive match and no ID-parity error. See Section 22.6.9 for more details. This flag
indicates that a new valid identifier has been received on an RX match. This bit is cleared by thefollowing:
•
•
•
•
•
•
•

0

Setting of the SWnRST bit
Setting of the RESET bit
A system reset
Writing a 1 to this bit
Reading the LINID register
Reception of a new synch breakReading the corresponding interrupt offset in SCIINTVECT0/1

Read: No valid ID has been received since the last clear.
Write: Writing a 0 to this bit has no effect.

1

Read: A valid ID RX has been received in LINID[23:16] on an RX match.
Write: The bit is cleared to 0.

13

ID TX

Identifier on transmit flag. This bit is effective in LIN mode only. This flag is set when an identifier isreceived with a transmit match and no ID-parity error. See Section 22.6.9 for more details. This flag
indicates that a new valid identifier has been received on a TX match. This bit is cleared by thefollowing:
•
•
•
•
•
•
•
0

Setting the SWnRST bit
Setting of the RESET bit
A system reset
Writing a 1 to this bit
Reading the LINID register
Receiving a new synch breakReading the corresponding interrupt offset in SCIINTVECT0/1

Read: No valid ID has been received since the last clear.
Write: Writing a 0 to this bit has no effect.

1

Read: A valid ID TX has been received in LINID[23:16] on an TX match.
Write: The bit is cleared to 0.

12

RX WAKE

Receiver wakeup detect flag. This bit is effective in SCI-compatible mode only. The SCI sets this bit
to indicate that the data currently in SCIRD is an address. RX WAKE is cleared by the following:
•
•
•
•

11

Setting of the SWnRST bit
Setting of the RESET bit
A system reset
Upon receipt of a data frame.

0

The data in SCIRD is not an address.

1

The data in SCIRD is an address.

TX EMPTY

Transmitter empty flag. This flag indicates the transmitter's buffer register(s) (SCITD/TDy) and shift
register (SCITXSHF) are empty. In multi-buffer mode, this flag indicates the TDx registers and shift
register (SCITXSHF) are empty. In non-multi-buffer mode, this flag indicates the LINTD0 byte andthe shift register (SCITXSHF) are empty.
Note: The RESET bit, an active SWnRST (SCIGCR1[7]) or a system reset sets this bit. Thisbit does not cause an interrupt request.
SCI mode or LIN non-multi-buffer mode
0

Transmitter buffer or shift register (or both) are loaded with data.

1

Transmitter buffer and shift registers are both empty.
In LIN mode using multi-buffer mode

1016

0

Multi-buffer or shift register (or all) are loaded with data.

1

Multi-buffer and shift registers are all empty.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

Table 22-19. SCI Flags Register (SCIFLR) Field Descriptions (continued)
Bit

Field

10

TX WAKE

Value

Description
Transmitter wakeup method select. This bit is effective in SCI mode only. The TX WAKE bit
controls whether the data in SCITD should be sent as an address or data frame using
multiprocessor communication format. This bit is set to 1 or 0 by software before a byte is written to
SCITD and is cleared by the SCI when data is transferred from SCITD to SCITXSHF or by asystem reset.
Note: TXWAKE is not cleared by the SWnRST bit.
Address-bit mode0

Frame to be transmitted will be data (address bit = 0).

1

Frame to be transmitted will be an address (address bit = 1).
Idle-line mode

90

The frame to be transmitted will be data.

1

The following frame to be transmitted will be an address (writing a 1 to this bit followed by writing
dummy data to the SCITD will result in a idle period of 11 bit periods before the next frame istransmitted).

RX RDY

Receiver ready flag. In SCI-compatible mode, the receiver sets this bit to indicate that the SCIRD
contains new data and is ready to be read by the CPU. In LIN mode, RX RDY is set once a valid
frame is received in multi-buffer mode, a valid frame being a message frame received with noerrors. In non-multi-buffer mode, RX RDY is set for each received byte and will be set for the lastbyte of the frame if there are no errors. The SCI/LIN generates a receive interrupt when RX RDYflag bit is set if the SET RX INT bit is set (SCISETINT[9]); RX RDY is cleared by the following:
•
•
•
•
•
•

Setting of the SWnRST bit
Setting of the RESET bit
A system reset
Writing a 1 to this bit
Reading the SCIRD register in compatibility mode
Reading the last data byte RDy of the response in LIN mode

Note: The RXRDY flag cannot be cleared by reading the corresponding interrupt offset in the
SCIINTVECT0/1 register.
0

Read: No new data is in SCIRD.
Write: Writing a 0 to this bit has no effect.

1

Read: New data is ready to be read from SCIRD.
Write: The bit is cleared to 0.

8

TX RDY

Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer(s)register(s) (SCITD in compatibility mode and LINTD0/LINTD1 in multi-buffer mode) are ready to getanother character from a CPU write.
In SCI, writing data to SCITD automatically clears this bit. In LIN mode, this bit is cleared once byte
0 (TD0) is written to LINTD0. This bit is set after the data of the TX buffer is shifted into the
SCITXSHF register. This event can trigger a transmit interrupt after data is copied to the TX shift
register SCITXSHF, if the SET TX INT is set.
Note:1) TXRDY is also set to 1 either by setting of the RESET bit, enabling SWnRST or by asystem reset.
2) The TXRDY flag cannot be cleared by reading the corresponding interrupt offset in the
SCIINTVECT0/1 register.
3) The transmit interrupt request can be eliminated until the next series of data written into
the transmit buffers LINTD0 and LINTD1, by disabling the corresponding interrupt via the
SCICLEARINT register or by disabling the transmitter via the TXENA bit.
SCI mode0

SCITD is full.

1

SCITD is ready to receive the next character.
LIN mode0

The multi-buffers are full.

1

The multi-buffers are ready to receive the next character(s).
For more information on transmit interrupt handling, see the SCI document for compatibility modeand Section 22.6.9 for LIN mode.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1017

SCI/LIN Control Registers

www.ti.com

Table 22-19. SCI Flags Register (SCIFLR) Field Descriptions (continued)
Bit

Field

7

TOA3WUS

Value

Description
Timeout after three wakeup signals flag. This bit is effective in LIN mode only. This flag is set if
there is no synch break received after three wakeup signals and a period of 1.5 seconds has
passed. Such expiration time is used before issuing another round of wakeup signals. This bit iscleared by the following:
•
•
•
•
•

Setting of the SWnRST bit
Setting of the RESET bit
A system reset
Writing a 1 to this bit
Reading the corresponding interrupt offset in SCIINTVECT0/1

See Section 22.9.3 for more information.
0

Read: No timeout occurred after three wakeup signals.
Write: Writing a 0 to this bit has no effect.

1

Read: Timeout occurred after three wakeup signals and 1.5 seconds time.
Write: The bit is cleared to 0.

6

TOAWUS

Timeout after wakeup signal flag. This bit is effective in LIN mode only. This bit is set if there is no
synch break received after a wakeup signal has been sent. A minimum of 150 ms expiration time isused before issuing another wakeup signal. This bit is cleared by the following:
•
•
•
•
•

Setting the SWnRST bit
Setting of the RESET bit
A system reset occurring
Writing a 1 to this bit
Reading the corresponding interrupt offset in SCIINTVECT0/1

See Section 22.9.3 for more information.
0

Read: No timeout occurred after one wakeup signal (150 ms).
Write: Writing a 0 to this bit has no effect.

1

Read: Timeout occurred after one wakeup signal.
Write: The bit is cleared to 0.

5

Reserved

4

TIMEOUT

0

Reads return 0. Writes have no effect.
LIN bus idle timeout flag. This bit is effective in LIN mode only. This bit is set earliest after at least
four seconds of bus inactivity. Bus inactivity is defined as no transactions between recessive anddominant (and vice versa). This bit is cleared by the following:
•
•
•
•
•

Setting the SWnRST bit
Setting of the RESET bit
A system reset occurring
Writing a 1 to this bit
Reading the corresponding interrupt offset in SCIINTVECT0/1

See Section 22.6.7 for more information.
0

Read: No bus idle has been detected since this bit was last cleared.
Write: Writing a 0 to this bit has no effect.

1

Read: A LIN bus idle has been detected.
Write: The bit is cleared to 0.

3

BUSY

Bus busy flag. This bit is effective in LIN mode and SCI-compatible mode. This bit indicates
whether the receiver is in the process of receiving a frame. As soon as the receiver detects the
beginning of a start bit, the BUSY bit is set to 1. When the reception of a frame is complete, the
SCI/LIN clears the BUSY bit. If SET WAKEUP INT is set and power down is requested while this bit
is set, the SCI/LIN automatically prevents low-power mode from being entered and generates
wakeup interrupt. The BUSY bit is controlled directly by the SCI/LIN receiver, but this bit can also
be cleared by the following:• Setting the SWnRST bit• Setting of the RESET bit• A system reset occurring

1018

0

The receiver is not currently receiving a frame.

1

The receiver is currently receiving a frame.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

Table 22-19. SCI Flags Register (SCIFLR) Field Descriptions (continued)
Bit

Field

2

IDLE

Value

Description
SCI receiver in idle state. This bit is effective in SCI-compatible mode only. While this bit is set, theSCI looks for an idle period to resynchronize itself with the bit stream. The receiver does notreceive any data while the bit is set. The bus must be idle for 11 bit periods to clear this bit. The
SCI enters the idle state if one of the following events occurs:
•
•
•
•

1

A system reset
An SCI software reset
A power down
The RX pin is configured as a general I/O pin

0

The idle period has been detected; the SCI is ready to receive.

1

The idle period has not been detected; the SCI will not receive any data.

WAKEUP

Wakeup flag. This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver ortransmitter activity has taken the module out of power-down mode. An interrupt is generated if the
SET WAKEUP INT bit (SCISETINT[2]) is set. It is cleared by the following:
•
•
•
•
•

Setting of the SWnRST bit
Setting of the RESET bit
A system reset
Writing a 1 to this bit
Reading the corresponding interrupt offset in SCIINTVECT0/1

For compatibility mode, see the SCI document for more information on low-power mode.
0

Read: The module will not wake up from power-down mode.
Write: Writing a 0 to this bit has no effect.

1

Read: Wake up from power-down mode.
Write: The bit is cleared to 0.

0

BRKDT

SCI break-detect flag. This bit is effective in SCI-compatible mode only. This bit is set when the SCI
detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains
continuously low for at least 10 bits after a missing first stop bit, that is, after a framing error.
Detection of a break condition causes the SCI to generate an error interrupt if the SET BRKDT INT
bit is set. The BRKDT bit is reset by the following:
•
•
•
•
•
0

Setting of the SWnRST bit
Setting of the RESET bit
A system reset
Writing a 1 to this bit
Reading the corresponding interrupt offset in SCIINTVECT0/1

Read: No break condition has been detected since the last clear.
Write: Writing a 0 to this bit has no effect.

1

Read: A break condition has been detected.
Write: The bit is cleared to 0.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1019

SCI/LIN Control Registers

www.ti.com

22.11.9 SCI Interrupt Vector Offset 0 (SCIINTVECT0)
Figure 22-35 and Table 22-20 illustrate this register.
Figure 22-35. SCI Interrupt Vector Offset 0 (SCIINTVECT0) [offset = 20h]
31

16
Reserved
R-0

15

5

4

0

Reserved

INTVECT0

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 22-20. SCI Interrupt Vector Offset 0 (SCIINTVECT0) Field Descriptions
Bit

Field

31-5

Reserved

Value
0

4-0

INVECT0

0-1Fh

Description
Reads return 0. Writes have no effect.
Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. A read tothis register updates its value to the next highest priority pending interrupt in SCIFLR and clears
the flag in SCIFLR corresponding to the offset that was read. See Table 22-4 for a list of theinterrupts.
Note: The flags for the receive (SCIFLR[9]) and the transmit (SCIFLR[8]) interrupt cannot becleared by reading the corresponding offset vector in this register (see detailed descriptionin SCIFLR register).

22.11.10 SCI Interrupt Vector Offset 1 (SCIINTVECT1)
Figure 22-36 and Table 22-21 illustrate this register.
Figure 22-36. SCI Interrupt Vector Offset 1 (SCIINTVECT1) [offset = 24h]31

16
Reserved
R-0

15

5

4

0

Reserved

INTVECT1

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 22-21. SCI Interrupt Vector Offset 1 (SCIINTVECT1) Field Descriptions
Bit

Field

Value

31-5

Reserved

04-0

INVECT1

0-1Fh

Description
Reads return 0. Writes have no effect.
Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. A read tothis register updates its value to the next highest priority pending interrupt in SCIFLR and clears
the flag in SCIFLR corresponding to the offset that was read. See Table 22-4 for list of interrupts.
Note: The flags for the receive (SCIFLR[9]) and the transmit (SCIFLR[8]) interrupt cannot becleared by reading the corresponding offset vector in this register (see detailed descriptionin SCIFLR register).

1020

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

22.11.11 SCI Format Control Register (SCIFORMAT)
Figure 22-37 and Table 22-22 illustrate this register.
Figure 22-37. SCI Format Control Register (SCIFORMAT) [offset = 28h]
31

19

18

16

Reserved

LENGTH

R-0

R/W-0

15

3

2

0

Reserved

CHAR

R-0

R/WC-0LEGEND: R/W = Read/Write; R = Read only; WC = Write in SCI-compatible mode only; -n = value after reset

Table 22-22. SCI Format Control Register (SCIFORMAT) Field Descriptions
Bit

Field

31-19

Reserved

Value
0

18-16

LENGTH

0-3h

Description
Reads return 0. Writes have no effect.
Frame length control bits. In LIN mode, these bits indicate the number of bytes in the response
field from 1 to 8 bytes. In buffered SCI mode, these bits indicate the number of characters, with thenumber of bits per character specified in CHAR (SCIFORMAT[2:0]).
When these bits are used to indicate LIN response length (SCIGCR1[0] = 1), then when there is
an ID RX match, this value should be updated with the expected length of the response. In
buffered SCI mode, these bits indicate the transmitter/receiver format for the number of characters:
1 to 8. There can be up to eight characters with eight bits each.

15-3

Reserved

2-0

CHAR

0

The response field has 1 byte/character.

1h

The response field has 2 bytes/characters.

2h

The response field has 3 bytes/characters.

3h

The response field has 4 bytes/characters.

4h

The response field has 5 bytes/characters.

5h

The response field has 6 bytes/characters.

6h

The response field has 7 bytes/characters.

7h

The response field has 8 bytes/characters.

0

Reads return 0. Writes have no effect.

0-7h

Character length control bits. These bits are effective in non-buffered SCI and buffered SCI modes
only. These bits set the SCI character length from 1 to 8 bits.
In non-buffered SCI and buffered SCI mode, when data of fewer than eight bits in length isreceived, it is left justified in SCIRD/RDy and padded with trailing zeros. Data read from the
SCIRD should be shifted by software to make the received data right justified.
Data written to the SCITD should be right justified but does not need to be padded withleading zeros.

0

The character is 1 bit long.

1h

The character is 2 bits long.

2h

The character is 3 bits long.

3h

The character is 4 bits long.

4h

The character is 5 bits long.

5h

The character is 6 bits long.

6h

The character is 7 bits long.

7h

The character is 8 bits long.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1021

SCI/LIN Control Registers

www.ti.com

22.11.12 Baud Rate Selection Register (BRS)This section describes the baud rate selection register. Figure 22-38 and Table 22-23 illustrate thisregister.
Figure 22-38. Baud Rate Selection Register (BRS) [offset = 2Ch]
31

30

28

27

24

23

16

Rsvd

U

M

PRESCALER P

R-0

R/W-0

R/W-0

R/W-0

15

0
PRESCALER P
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22-23. Baud Rate Selection Register (BRS) Field Descriptions
Bit

Field

31

Reserved

Value
0

Description
Reads return 0. Writes have no effect.

30-28

U

0-2h

SCI/LIN super fractional divider selection. These bits are effective in LIN or SCI
asynchronous mode. These bits are an additional fractional part for the baud rate
specification. These bits allow a super-fine tuning of the fractional baud rate with seven moreintermediate values for each of the M fractional divider values. See Section 22.6.4.1 for moredetails.

27-24

M

0-3h

SCI/LIN 4-bit fractional divider selection. These bits are effective in LIN or SCI asynchronousmode. These bits are used to select a baud rate for the SCI/LIN module, and they are a
fractional part for the baud rate specification. The M divider allows fine-tuning of the baudrate over the P prescaler with 15 additional intermediate values for each of the P integer
values.See Section 22.6.4.1 for more details.

23-0

PRESCALER P

0-FF FFFFh

These bits are used to select a baud rate for the SCI/LIN module. These bits are effective in
LIN mode and SCI compatibility.
The SCI/LIN has an internally generated serial clock determined by the VCLK and theprescalers P and M in this register. The LIN uses the 24-bit integer prescaler P value of thisregister to select one of over 16,700,000. The additional 4-bit fractional divider M refines thebaudrate selection PRESCALER[27:24].
NOTE: In LIN mode, ONLY the asynchronous mode and baurdrate values are used.
The baud rate can be calculated using the following formulas:
Asynchronous baud value =

((

))

(50)

(

)

(51)

(

)

(52)

(

)

(53)

VCLK Frequency
M
16 P + 1 +16

Isosynchronous baud value = VCLK Frequency
P+1

For P = 0,
Asynchronous baud value = VCLK Frequency
32

Isosynchronous baud value = VCLK Frequency
2

Table 22-24 contains comparative baud values for different P values, with VCLK = 50 MHz,for asynchronous mode.

1022

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

Table 22-24. Comparative Baud Values for Different P Values, Asynchronous Mode (1) (2)24-Bit Register Value

(1)
(2)

Baud Selected

Percent Error

Decimal

Hex

Ideal

Actual2600001A

1152001157400.47

53000035

57600

57870

0.47

80

000050

38400

38580

0.47

162

0000A2

19200

19172

-0.15

299

00012B

10400

10417

0.16

325

000145

9600

9586

-0.15

399

00018F7812.57812.50.00

65000028A

4800

4800

0.00

15624

003BA0

200

200

0.00

624999098967550.00

VCLK = 50 MHz
Values are in decimal except for column 2.

22.11.13 SCI Data Buffers (SCIED, SCIRD, SCITD)
The SCI has three addressable registers in which transmit and receive data is stored. These three
registers are available in SCI mode only.
22.11.13.1 Receiver Emulation Data Buffer (SCIED)The SCIED register is addressed at a location different from SCIRD, but is physically the same register.
Figure 22-39 and Table 22-25 illustrate this register.
Figure 22-39. Receiver Emulation Data Buffer (SCIED) [offset = 30h]
31

16
Reserved
R-0

15

8

7

0

Reserved

ED

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 22-25. Receiver Emulation Data Buffer (SCIED) Field Descriptions
Bit

Field

31-8

Reserved

7-0

ED

Value
0
0-FFh

SPNU517C – March 2018
Submit Documentation Feedback

Description
Reads return 0. Writes have no effect.
Emulator data. This bit is effective in SCI-compatible mode only. Reading SCIED[7:0] does notclear the RXRDY flag, unlike reading SCIRD. This register should be used only by an emulator
that must continually read the data buffer without affecting the RXRDY flag.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1023

SCI/LIN Control Registers

www.ti.com

22.11.13.2 Receiver Data Buffer (SCIRD)
This register provides a location for the receiver data. Figure 22-40 and Table 22-26 illustrate this register.
Figure 22-40. Receiver Data Buffer (SCIRD) [offset = 34h]
31

16
Reserved
R-0

15

8

7

0

Reserved

RD

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 22-26. Receiver Data Buffer (SCIRD) Field Descriptions
Bit

Field

31-8

Reserved

7-0

RD

Value
0
0-FFh

Description
Reads return 0. Writes have no effect.
Receiver data. This bit is effective in SCI-compatible mode only. When a frame has been
completely received, the data in the frame is transferred from the receiver shift register SCIRXSHF
to this register. As this transfer occurs, the RXRDY flag is set and a receive interrupt is generated
if SET RX INT is set.
Note: When the data is read from SCIRD, the RXRDY flag is automatically cleared.

NOTE: When the SCI receives data that is fewer than eight bits in length, it loads the data into thisregister in a left justified format padded with trailing zeros. Therefore, the user software
should perform a logical shift on the data by the correct number of positions to make it rightjustified.

1024

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

22.11.13.3 Transmit Data Buffer Register (SCITD)
Data to be transmitted is written to the SCITD register. Figure 22-41 and Table 22-27 illustrate thisregister.
Figure 22-41. Transmit Data Buffer Register (SCITD) [offset = 38h]
31

16
Reserved
R-0

15

8

7

0

Reserved

TD

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22-27. Transmit Data Buffer Register (SCITD) Field Descriptions
Bit

Field

31-8

Reserved

7-0

TD

Value
0
0-FFh

Description
Reads return 0. Writes have no effect.
Transmit data. This bit is effective in SCI-compatible mode only. Data to be transmitted is written
to the SCITD register. The transfer of data from this register to the transmit shift register
SCITXSHF sets the TXRDY flag, which indicates that SCITD is ready to be loaded with anotherbyte of data.
Note: If SET TX INT is set, this data transfer also causes an interrupt.

NOTE: Data written to the SCITD register that is fewer than eight bits long must be right justified, but
it does not need to be padded with leading zeros.

22.11.14 SCI Pin I/O Control Register 0 (SCIPIO0)
Figure 22-42 and Table 22-28 illustrate this register.
Figure 22-42. SCI Pin I/O Control Register 0 (SCIPIO0) [offset = 3Ch]
31

8
Reserved
R-0
7

3

2

1

0

Reserved

TX FUNC

RX FUNC

Reserved

R-0

R/W-0

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22-28. SCI Pin I/O Control Register 0 (SCIPIO0) Field Descriptions
Bit

Field

31-3

Reserved

2

TX FUNC

1

0

Value
0

Reads return 0. Writes have no effect.
Transfer function. This bit is effective in LIN or SCI mode. This bit defines the function of pin LINTX.

0

LINTX is a general-purpose digital I/O pin.

1

LINTX is the SCI/LIN transmit pin.

RX FUNC

Reserved

Description

Receive function. This bit is effective in LIN or SCI mode. This bit defines the function of pin LINRX.
0

LINRX is a general-purpose digital I/O pin.

1

LINRX is the SCI/LIN receive pin.

0

Reads return 0. Writes have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1025

SCI/LIN Control Registers

www.ti.com

22.11.15 SCI Pin I/O Control Register 1 (SCIPIO1)
Figure 22-43 and Table 22-29 illustrate this register.
Figure 22-43. SCI Pin I/O Control Register 1 (SCIPIO1) [offset = 40h]
31

8Reserved
R-0
7

2

1

0

Reserved

3

TX DIRRX DIR

Reserved

R-0

R/W-0

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22-29. SCI Pin I/O Control Register 1 (SCIPIO1) Field Descriptions
Bit

Field

31-3

Reserved

2

TX DIR

1

Value
0

Reserved

Reads return 0. Writes have no effect.
Transmit pin direction. This bit is effective in LIN or SCI mode. This bit determines the data direction on
the LINTX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). See Table 22-30
for the LINTX pin control with this bit and others.

0

LINTX is a general-purpose input pin.

1

LINTX is a general-purpose output pin.

RX DIR

0

Description

Receive pin direction. This bit is effective in LIN or SCI mode. This bit determines the data direction on
the LINRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 22-31
for the LINRX pin control with this bit and others.
0

LINRX is a general-purpose input pin.

1

LINRX is a general-purpose output pin.

0

Reads return 0. Writes have no effect.

Table 22-30. LINTX Pin Control
Function

TX IN (1)TX OUT

TX FUNC

TX DIR

LINTX

X

X

1

X

General purpose input

X

X

0

0

General purpose output, high

X

1

0

1

General purpose output, low

X

0

0

1

(1)

TX IN is a read-only bit. Its value always reflects the level of the LINTX pin.

Table 22-31. LINRX Pin Control
Function

RX IN (1)RX OUT

RX FUNC

RX DIR

LINRX

X

X

1

X

General purpose input

X

X

0

0

General purpose output, high

X

1

0

1

General purpose output, low

X

0

0

1

(1)

1026

RX IN is a read-only bit. Its value always reflects the level of the LINRX pin.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

22.11.16 SCI Pin I/O Control Register 2 (SCIPIO2)
Figure 22-44 and Table 22-32 illustrate this register.
Figure 22-44. SCI Pin I/O Control Register 2 (SCIPIO2) [offset = 44h]
31

8
Reserved
R-0
7

2

1

0

Reserved

3

TX IN

RX IN

Reserved

R-0

R-X

R-X

R-X

LEGEND: R = Read only; X = value is indeterminate; -n = value after reset

Table 22-32. SCI Pin I/O Control Register 2 (SCIPIO2) Field Descriptions
Bit

Field

31-3

Reserved

2

1

0

Value
0

TX IN

Reads return 0. Writes have no effect.
Transmit pin in. This bit is effective in LIN or SCI mode. This bit contains the current value on the LINTX
pin.

0

The LINTX pin is at logic low (0).

1

The LINTX pin is at logic high (1).

RX IN

Reserved

Description

Receive pin in. This bit is effective in LIN or SCI mode. This bit contains the current value on the LINRX
pin.
0

The LINRX pin is at logic low (0).

1

The LINRX pin is at logic high (1).

x

Writes have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1027

SCI/LIN Control Registers

www.ti.com

22.11.17 SCI Pin I/O Control Register 3 (SCIPIO3)
Figure 22-45 and Table 22-33 illustrate this register.
Figure 22-45. SCI Pin I/O Control Register 3 (SCIPIO3) [offset = 48h]31

8Reserved
R-0
7

2

1

0

Reserved

3

TX OUT

RX OUT

Reserved

R-0

R/W-0

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22-33. SCI Pin I/O Control Register 3 (SCIPIO3) Field Descriptions
Bit

Field

31-3

Reserved

2

TX OUT

Value
0

Description
Reads return 0. Writes have no effect.
Transmit pin out. This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin
LINTX if the following conditions are met:
• TX FUNC = 0 (LINTX pin is a general-purpose I/O.)• TX DIR = 1 (LINTX pin is a general-purpose output.)
See Table 22-30 for an explanation of this bit’s effect in combination with other bits.

10

The output on the LINTX pin is at logic low (0).

1

The output on the LINTX pin is at logic high (1). (Output voltage is VOH or higher if TXPDR = 0, andoutput is in high-impedance state if TXPDR = 1)RX OUT

Receive pin out. This bit is effective in LIN or SCI mode. This bit specifies the logic to be output on pin
LINRX if the following conditions are met:
• RX FUNC = 0 (LINRX pin is a general-purpose I/O.)• RX DIR = 1 (LINRX pin is a general-purpose output.)
See Table 22-31 for an explanation of this bit’s effect in combination with the other bits.

0

1028

Reserved0

The output on the LINRX pin is at logic low (0).

1

The output on the LINRX pin is at logic high (1). (Output voltage is VOH or higher if RXPDR = 0, andoutput is in high-impedance state if RXPDR = 1)0

Reads return 0. Writes have no effect.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

22.11.18 SCI Pin I/O Control Register 4 (SCIPIO4)
Figure 22-46 and Table 22-34 illustrate this register.
Figure 22-46. SCI Pin I/O Control Register 4 (SCIPIO4) [offset = 4Ch]
31

8
Reserved
R-0
7

2

1

0

Reserved

3

TX SET

RX SET

Reserved

R-0

R/W-0

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22-34. SCI Pin I/O Control Register 4 (SCIPIO4) Field Descriptions
Bit

Field

31-3

Reserved

2

TX SET

Value
0

Description
Reads return 0. Writes have no effect.
Transmit pin set. This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin
LINTX if the following conditions are met:
• TX FUNC = 0 (LINTX pin is a general-purpose I/O.)• TX DIR = 1 (LINTX pin is a general-purpose output.)
See Table 22-30 for an explanation of this bit’s effect in combination with other bits.

0

Read: The output on LINTX pin is at logic low (0).
Write: Writing a 0 to this bit has no effect.

1
1

RX SET

Read or write: The output on LINTX pin is at logic high (1).
Receive pin set. This bit is effective in LIN or SCI mode. This bit sets the data to be output on pin
LINRX if the following conditions are met:
• RX FUNC = 0 (LINRX pin is a general-purpose I/O.)• RX DIR = 1 (LINRX pin is a general-purpose output.)
See Table 22-31 for an explanation of this bit’s effect in combination with the other bits.

0

Read: The output on LINRX pin is at logic low (0).
Write: Writing a 0 to this bit has no effect.

0

Reserved

1

Read or write: The output on LINRX pin is at logic high (1).

0

Reads return 0. Writes have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1029

SCI/LIN Control Registers

www.ti.com

22.11.19 SCI Pin I/O Control Register 5 (SCIPIO5)
Figure 22-47 and Table 22-35 illustrate this register.
Figure 22-47. SCI Pin I/O Control Register 5 (SCIPIO5) [offset = 50h]31

8Reserved
R-0
7

2

1

0

Reserved

3

TX CLRRX CLR

Reserved

R-0

R/W-0

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22-35. SCI Pin I/O Control Register 5 (SCIPIO5) Field Descriptions
Bit

Field

31-3

Reserved

2

TX CLR

Value
0

Description
Reads return 0. Writes have no effect.
Transmit pin clear. This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin
LINTX if the following conditions are met:
• TX FUNC = 0 (LINTX pin is a general-purpose I/O.)• TX DIR = 1 (LINTX pin is a general-purpose output.)0

Read: The output on LINTX pin is at logic low (0).
Write: Writing a 0 to this bit has no effect.

1

Read: The output on LINTX pin is at logic high (1).
Write: The output on LINTX pin is at logic low (0).

1

RX CLR

Receive pin clear. This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin
LINRX if the following conditions are met:
• RX FUNC = 0 (LINRX pin is a general-purpose I/O.)• RX DIR = 1 (LINRX pin is a general-purpose output.)0

Read: The output on LINRX pin is at logic low (0).
Write: Writing a 0 to this bit has no effect.

1

Read: The output on LINRX pin is at logic high (1).
Write: The output on LINRX pin is at logic low (0).

0

1030

Reserved

0

Reads return 0. Writes have no effect.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

22.11.20 SCI Pin I/O Control Register 6 (SCIPIO6)
Figure 22-48 and Table 22-36 illustrate this register.
Figure 22-48. SCI Pin I/O Control Register 6 (SCIPIO6) [offset = 54h]
31

8
Reserved
R-0
2

1

0

Reserved

3

TX PDR

RX PDR

Reserved

R-0

R/W-0

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22-36. SCI Pin I/O Control Register 6 (SCIPIO6) Field Descriptions
Bit

Field

31-3

Reserved

2

TX PDR

Value
0

Description
Reads return 0. Writes have no effect.
Transmit pin open drain enable. This bit is effective in LIN or SCI mode. This bit enables open-drain
capability in the output pin LINTX, if the following conditions are met:
• TX FUNC = 0 (LINTX pin is a general-purpose I/O.)• TX DIR = 1 (LINTX pin is a general-purpose output.)

10Open-drain functionality is disabled; the output voltage is VOL or lower if TXOUT = 0, and is VOH or
higher if TXOUT = 1.

1

Open-drain functionality is enabled; the output voltage is VOL or lower if TXOUT = 0, and is highimpedance if TXOUT = 1.

RX PDR

Receive pin open drain enable. This bit is effective in LIN or SCI mode. This bit enables open-drain
capability in the output pin LINRX, if the following conditions are met:
• RX FUNC = 0 (LINRX pin is a general-purpose I/O.)• RX DIR = 1 (LINRX pin is a general-purpose output.)0

Reserved

0Open-drain functionality is disabled; the output voltage is VOL or lower if RXOUT = 0, and is VOH or
higher if RXOUT = 1.

1

Open-drain functionality is enabled; the output voltage is VOL or lower if RXOUT = 0, and is highimpedance if RXOUT = 1.

0

Reads return 0. Writes have no effect.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1031

SCI/LIN Control Registers

www.ti.com

22.11.21 SCI Pin I/O Control Register 7 (SCIPIO7)
Figure 22-49 and Table 22-37 illustrate this register.
Figure 22-49. SCI Pin I/O Control Register 7 (SCIPIO7) [offset = 58h]
31

8
Reserved
R-0
7

2

1

0

Reserved

3

TX PD

RX PD

Reserved

R-0

R/W-n

R/W-n

R-n

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, Refer to the Terminal Functions in the device datasheet for default pin
settings.

Table 22-37. SCI Pin I/O Control Register 7 (SCIPIO7) Field Descriptions
Bit

Field

31-3

Reserved

2

TX PD

1

Value
0

Reserved

Reads return 0. Writes have no effect.
Transmit pin pull control disable. This bit is effective in LIN or SCI mode. This bit disables pull control
capability on the input pin LINTX.

0

The pull control on the LINTX pin is enabled.

1

The pull control on the LINTX pin is disabled.

RX PD

0

Description

Receive pin pull control disable. This bit is effective in LIN or SCI mode. This bit disables pull control
capability on the input pin LINRX.
0

Pull control on the LINRX pin is enabled.

1

Pull control on the LINRX pin is disabled.

0

Writes have no effect.

22.11.22 SCI Pin I/O Control Register 8 (SCIPIO8)
Figure 22-50 and Table 22-38 illustrate this register.
Figure 22-50. SCI Pin I/O Control Register 8 (SCIPIO8) [offset = 5Ch]
31

8
Reserved
R-0
7

3

2

1

0

Reserved

TX PSL

RX PSL

Reserved

R-0

R/W-n

R/W-n

R-n

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, Refer to the Terminal Functions in the device datasheet for default pin
settings.

Table 22-38. SCI Pin I/O Control Register 8 (SCIPIO8) Field Descriptions
Bit

Field

31-3

Reserved

2

TX PSL

1

0
1032

Value
0

Reads return 0. Writes have no effect.
TX pin pull select. This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin
LINTX.

0

The LINTX pin is a pull down.

1

The LINTX pin is a pull up.

RX PSL

Reserved

Description

RX pin pull select. This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin
LINRX.
0

The LINRX pin is a pull down.

1

The LINRX pin is a pull up.

0

Writes have no effect.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

22.11.23 LIN Compare Register (LINCOMPARE)
Figure 22-51 and Table 22-39 illustrate this register.
Figure 22-51. LIN Compare Register (LINCOMPARE) [offset = 60h]
31

16
Reserved
R-0

15

10

9

8

7

3

2

0

Reserved

SDEL

Reserved

SBREAK

R-0

RWP-0

R-0

RWP-0

LEGEND: R/W = Read/Write; R = Read only; RWP = Read/Write in privileged mode only; --n = value after reset

Table 22-39. LIN Compare Register (LINCOMPARE) Field Descriptions
Bit

Field

31-10

Reserved

9-8

SDEL

Value
0

Description
Reads return 0. Writes have no effect.
2-bit synch delimiter compare. These bits are effective in LIN mode only. These bits are used toconfigure the number of Tbit for the synch delimiter in the synch field. The default value is 0.
The formula to program the value (in Tbits) for the synchronization delimiter is:
TSDEL = (SDEL + 1) Tbit

7-3

Reserved

2-0

SBREAK0

The synch delimiter has 1 Tbit.

1h

The synch delimiter has 2 Tbit.

2h

The synch delimiter has 3 Tbit.

3h

The synch delimiter has 4 Tbit.

0

Reads return 0. Writes have no effect.
Synch break extend. These bits are effective in LIN mode only. These bits are used to configure thenumber of Tbit for the synch break to extend the minimum 13 Tbit break field to a maximum of 20 Tbit
long.
Note: The default value is 0, which adds nothing to the automatically generated SYNCH BREAK.
The formula to program the value (in Tbits) for the SYNCH BREAK is:
TSYNBRK = 13Tbit + (SBREAK × Tbit)

0

The synch break has no additional Tbit.

1h

The synch break has 1 additional Tbit.

2h

The synch break has 2 additional Tbit.

3h

The synch break has 3 additional Tbit.

4h

The synch break has 4 additional Tbit.

5h

The synch break has 5 additional Tbit.

6h

The synch break has 6 additional Tbit.

7h

The synch break has 7 additional Tbit.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1033

SCI/LIN Control Registers

www.ti.com

22.11.24 LIN Receive Buffer 0 Register (LINRD0)
Figure 22-52 and Table 22-40 illustrate this register.
Figure 22-52. LIN Receive Buffer 0 Register (LINRD0) [offset = 64h]
31

24

23

16

RD0

RD1

R-0

R-0

15

8

7

0

RD2

RD3

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 22-40. LIN Receive Buffer 0 Register (LINRD0) Field Descriptions
Bit

Field

Value

Description

31-24

RD0

0-FFh

Receive buffer 0. Byte 0 of the response data byte. Each response data-byte that is received in
the SCIRXSHFT register is transferred to the corresponding RDy bit field according to the numberof bytes received. A read of this byte clears the RXDY byte.
Note: RD<x-1> is equivalent to data byte <x> of the LIN frame.

23-16

RD1

0-FFh

Receive buffer 1. Byte 1 of the response data byte. Each response data-byte that is received in
the SCIRXSHFT register is transferred to the corresponding RDy register according to the numberof bytes received.

15-8

RD2

0-FFh

Receive buffer 2. Byte 2 of the response data byte. Each response data-byte that is received in
the SCIRXSHFT register is transferred to the corresponding RDy register according to the numberof bytes received.

7-0

RD3

0-FFh

Receive buffer 3. Byte 3 of the response data byte. Each response data-byte that is received in
the SCIRXSHFT register is transferred to the corresponding RDy register according to the numberof bytes received.

22.11.25 LIN Receive Buffer 1 Register (LINRD1)
Figure 22-53 and Table 22-41 illustrate this register.
Figure 22-53. LIN Receive Buffer 1 Register (RD1) [offset = 68h]
31

24

23

16

RD4

RD5

R-0

R-0

15

8

7

0

RD6

RD7

R-0

R-0

LEGEND: R = Read only; -n = value after reset

Table 22-41. LIN Receive Buffer 1 Register (RD1) Field Descriptions
Bit

Field

Value

Description

31-24

RD4

0-FFh

Receive buffer 4. Byte 4 of the response data byte. Each response data-byte that is received in
the SCIRXSHFT register is transferred to the corresponding register according to the number ofbytes received.
Note: RD<x-1> is equivalent to data byte <x> of the LIN frame.

23-16

RD5

0-FFh

Receive buffer 5. Byte 5 of the response data byte. Each response data-byte that is received in
the SCIRXSHFT register is transferred to the corresponding register according to the number ofbytes received.

15-8

RD6

0-FFh

Receive buffer 6. Byte 6 of the response data byte. Each response data-byte that is received in
the SCIRXSHFT register is transferred to the corresponding register according to the number ofbytes received.

7-0

RD7

0-FFh

Receive buffer 7. Byte 7 of the response data byte. Each response data-byte that is received in
the SCIRXSHFT register is transferred to the corresponding register according to the number ofbytes received.

1034

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

22.11.26 LIN Mask Register (LINMASK)
Figure 22-54 and Table 22-42 illustrate this register.
Figure 22-54. LIN Mask Register (LINMASK) [offset = 6Ch]
31

24

23

16

Reserved

RX ID MASK

R-0

R/WL-0

15

8

7

0

Reserved

TX ID MASK

R-0

R/WL-0LEGEND: R/W = Read/Write; R = Read only; WL = Write in LIN mode only; -n = value after reset

Table 22-42. LIN Mask Register (LINMASK) Field Descriptions
Bit

Field

31-24

Reserved

23-16

RX ID MASK

15-8

Reserved

7-0

TX ID MASK

Value
0
0-FFh

0
0-FFh

SPNU517C – March 2018
Submit Documentation Feedback

Description
Reads return 0. Writes have no effect.
Receive ID mask. These bits are effective in LIN mode only. This 8-bit mask is used for filtering an
incoming ID message and comparing it to the ID-byte. A compare match of the received ID with
the RX ID MASK will set the ID RX flag and trigger an ID interrupt if enabled (SET ID INT in
SCISETINT). A 0 bit in the mask indicates that bit is compared to the ID-byte. A 1 bit in the mask
indicates that bit is filtered and therefore is not used in the compare.
Reads return 0. Writes have no effect.
Transmit ID mask. These bits are effective in LIN mode only. This 8-bit mask is used for filtering
an incoming ID message and comparing it to the ID-byte. A compare match of the received ID with
the TX ID MASK will set the ID TX flag and trigger an ID interrupt if enabled (SET ID INT in
SCISETINT). A 0 bit in the mask indicates that bit is compared to the ID-byte. A 1 bit in the mask
indicates that bit is filtered and therefore is not used for the compare.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1035

SCI/LIN Control Registers

www.ti.com

22.11.27 LIN Identification Register (LINID)
Figure 22-55 and Table 22-43 illustrate this register.
Figure 22-55. LIN Identification Register (LINID) [offset = 70h]
31

24

23

16

Reserved

RECEIVED ID

R-0

R-0

15

8

7

0

ID-SLAVETASK BYTEID BYTE

R/WL-0R/WL-0LEGEND: R/W = Read/Write; R = Read only; WL = Write in LIN mode only; -n = value after reset

Table 22-43. LIN Identification Register (LINID) Field Descriptions
Bit

Field

31-24 Reserved

Value
0

Description
Reads return 0. Writes have no effect.

23-16 RECEIVED ID

0-FFh

Received identification. These bits are effective in LIN mode only. This byte contains thecurrent message identifier. During header reception the received ID is copied from the
SCIRXSHF register to this byte if there is no ID-parity error and there has been an RX/TX
match.

15-8

ID-SLAVETASK BYTE

0-FFh

ID-SlaveTask Byte. These bits are effective in LIN mode only. This field contains theidentifier to which the received ID of an incoming header will be compared to decide
whether a receive response, a transmit response, or no action needs to be performed by
the LIN node when a header with that particular ID is received.

7-0

ID BYTE

0-FFh

ID byte. This field is effective in LIN mode only. This byte is the LIN mode message ID.
On a master node, a write to this register by the CPU initiates a header transmission. Fora slave task, this byte is used for message filtering when HGEN CTRL = 0.

NOTE: For software compatibility with future LIN modules, the HGEN CTRL bit must be set to 1, theRX ID MASK field must be set to FFh, and the TX ID MASK field must be set to FFh.

1036

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

22.11.28 LIN Transmit Buffer 0 Register (LINTD0)
Figure 22-56 and Table 22-44 illustrate this register.
Figure 22-56. LIN Transmit Buffer 0 Register (LINTD0) [offset = 74h]
31

24

23

16

TD0

TD1

R/W-0

R/W-0

15

8

7

0

TD2

TD3

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 22-44. LIN Transmit Buffer 0 Register (LINTD0) Field Descriptions
Bit

Field

Value

Description

31-24

TD0

0-FFh

8-Bit transmit buffer 0. Byte 0 to be transmitted is written into this register and then copied to
SCITXSHF for transmission. Once byte 0 is written in TD0 buffer, transmission will be initiated.
Note: TD<x-1> is equivalent to data byte <x> of the LIN frame.

23-16

TD1

0-FFh

8-Bit transmit buffer 1. Byte 1 to be transmitted is written into this register and then copied to
SCITXSHF for transmission.

15-8

TD2

0-FFh

8-Bit transmit buffer 2. Byte 2 to be transmitted is written into this register and then copied to
SCITXSHF for transmission.

7-0

TD3

0-FFh

8-Bit transmit buffer 3. Byte 3 to be transmitted is written into this register and then copied to
SCITXSHF for transmission.

22.11.29 LIN Transmit Buffer 1 Register (LINTD1)
Figure 22-57 and Table 22-45 illustrate this register.
Figure 22-57. LIN Transmit Buffer 1 Register (LINTD1) [offset = 78h]
31

24

23

16

TD4

TD5

R/W-0

R/W-0

15

8

7

0

TD6

TD7

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 22-45. LIN Transmit Buffer 1 Register (LINTD1) Field Descriptions
Bit

Field

Value

Description

31-24

TD4

0-FFh

8-Bit transmit buffer 4. Byte 4 to be transmitted is written into this register and then copied to
SCITXSHF for transmission.
Note: TD<x-1> is equivalent to data byte <x> of the LIN frame.

23-16

TD5

0-FFh

8-Bit transmit buffer 5. Byte 5 to be transmitted is written into this register and then copied to
SCITXSHF for transmission.

15-8

TD6

0-FFh

8-Bit transmit buffer 6. Byte 6 to be transmitted is written into this register and then copied to
SCITXSHF for transmission.

7-0

TD7

0-FFh

8-Bit transmit buffer 7. Byte 7 to be transmitted is written into this register and then copied to
SCITXSHF for transmission.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1037

SCI/LIN Control Registers

www.ti.com

22.11.30 Maximum Baud Rate Selection Register (MBRS)
Figure 22-58 and Table 22-46 illustrate this register.
Figure 22-58. Maximum Baud Rate Selection Register (MBRS) [offset = 7Ch]
31

16
Reserved
R-0

15

13

12

0

Reserved

MBR

R-0

R/WL-DAChLEGEND: R/W = Read/Write; R = Read only; WL = Write in LIN mode only; -n = value after reset

Table 22-46. Maximum Baud Rate Selection Register (MBRS) Field Descriptions
Bit

Field

31-13

Reserved

12-0

MBR

Value
0
0-1FFFh

Description
Reads return 0. Writes have no effect.
Maximum baud rate prescaler. This bit is effective in LIN mode only. This 13-bit prescaler isused during the synchronization phase (see Section 22.6.5.2) of a slave module if the ADAPT
bit is set. In this way, a SCI/LIN slave using an automatic or select bit rate modes detects any
LIN bus legal rate automatically.
The MBR value should be programmed to allow a maximum baud rate that is not more than
10% above the expected operating baud rate in the LIN network. Otherwise, a 0x00 data byte
could mistakenly be detected as a sync break.
The default value for a 70MHz VCLK is 0xDAC.
This MBR prescaler is used by the wake-up and idle time counters for a constant expiration
time relative to a 20 kHz rate.
MBR =

1038

0.9x VCLK
maxbaudrate

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated(54)

SPNU517C – March 2018
Submit Documentation Feedback

SCI/LIN Control Registers

www.ti.com

22.11.31 Input/Output Error Enable Register (IODFTCTRL)
All the bits in the IODFTCTRL register are used in IODFT (I/O design for test) mode only. Figure 22-59
and Table 22-47 illustrate this register. After the basic SCI/LIN module configuration, enable the required
Error mode to be created followed by IODFT Key enable.
NOTE: 1) All the bits are used in IODFT mode only.
2) Each IODFT are expected to be checked individually.
3) ISFE Error will not be Flagged during IODFT mode.

Figure 22-59. Input/Output Error Enable Register (IODFTCTRL) [offset = 90h]
31

30

29

28

27

26

25

24

BEN

PBEN

CEN

ISFE

ReservedFEN

PEN

BRKDT ENA

R/WL-0R/WL-0R/WL-0R/WL-0R-0

R/W-0

R/WC-0

R/WC-0

20

19

18

23

21

16

Reserved

PIN SAMPLE MASKTX SHIFT

R-0

R/W-0

R/W-0

15

12

11

8

Reserved

IODFTENA

R-0

R/WP-5h7

1

0Reserved

2

LPB ENA

RXP ENA

R-0

R/WP-0R/WP-0LEGEND: R/W = Read/Write; R = Read only; WL = Write in LIN mode only; WC = Write in SCI-compatible mode only; WP = Write inprivilege mode only; -n = value after reset

Table 22-47. Input/Output Error Enable Register (IODFTCTRL) Field Descriptions
Bit

Field

31

BEN

30

29

28

Value

Bit error enable. This bit is effective in LIN mode only. This bit is used to create a bit error.
0

No bit error is created.

1

The bit received is ORed with 1 and passed to the bit monitor circuitry.

PBEN

Physical bus error enable. This bit is effective in LIN mode only. This bit is used to create aphysical bus error.
0

No error is created.

1

The bit received during synch break field transmission is ORed with 1 and passed to the bitmonitor circuitry.

CEN

Checksum error enable. This bit is effective in LIN mode only. This bit is used to create achecksum error.
0

No error is created.

1

The polarity of the CTYPE (checksum type) in the receive checksum calculator is changed
so that a checksum error is occurred.

ISFE

27

Reserved

26

FEN

SPNU517C – March 2018
Submit Documentation Feedback

Description

Inconsistent synch field (ISF) error enable. This bit is effective in LIN mode only. This bit isused to create an ISF error.
0

No error is created.

1

The bit widths in the synch field are varied so that the ISF check fails and the error flag is
set.

0

Reads return 0. Writes have no effect.
Frame error enable. This bit is used to create a frame error.

0

No error is created.

1

The stop bit received is ANDed with 0 and passed to the stop bit check circuitry.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1039

SCI/LIN Control Registers

www.ti.com

Table 22-47. Input/Output Error Enable Register (IODFTCTRL) Field Descriptions (continued)
Bit

Field

25

PEN

24

Value

Parity error enable. This bit is effective in SCI-compatible mode only. This bit is used tocreate a parity error.
0

No parity error occurs.

1

The parity bit received is toggled so that a parity error occurs.

BRKDT ENA

32-21

Reserved

20-19

PIN SAMPLE MASK

Description

Break detect error enable. This bit is effective in SCI-compatible mode only. This bit is used
to create a BRKDT error.
0

No error is created.

1

The stop bit of the frame is ANDed with 0 and passed to the RSM so that a frame error
occurs. Then the RX pin is forced to continuous low for 10 Tbit so that a BRKDT error
occurs.

0

Reads return 0. Writes have no effect.
Pin sample mask. These bits define the sample number at which the TX pin value that isbeing transmitted will be inverted to verify the receive pin samples majority detection
circuitry.
Note: In IODFT mode testing for pin_sample mask must be done with prescalar P
programmed greater than 2 (P > 2).

18-16

0

No mask is used.

1h

Invert the TX Pin value at TBIT_CENTER.

2h

Invert the TX Pin value at TBIT_CENTER + SCLK.

3h

Invert the TX Pin value at TBIT_CENTER + 2 SCLK.

TX SHIFT

15-12

Reserved

11-8

IODFTENA

7-2

Reserved

1

LPB ENA

Transmit shift. These bits define the amount by which the value on TX pin is delayed so thatthe value on the RX pin is asynchronous. This feature is not applicable to the start bit.
0

No delay occurs.

1h

The value is delayed by 1 SCLK.

2h

The value is delayed by 2 SCLK.

3h

The value is delayed by 3 SCLK.

4h

The value is delayed by 4 SCLK.

5h

The value is delayed by 5 SCLK.

6h

The value is delayed by 6 SCLK.

7h

The value is delayed by 7 SCLK.

0

Reads return 0. Writes have no effect.
IODFT enable key. Write access permitted in Privilege mode only.

Ah

IODFT is enabled.

All Others

IODFT is disabled.

0

Reads return 0. Writes have no effect.
Module loopback enable. Write access permitted in Privilege mode only.
Note: In analog loopback mode the complete communication path through the I/Os
can be tested, whereas in digital loopback mode the I/O buffers are excluded fromthis path.

0

1040

0

Digital loopback is enabled.

1

Analog loopback is enabled in module I/O DFT mode when IODFTENA = 1010.

RXP ENA

Module analog loopback through receive pin enable. Write access permitted in Privilege
mode only. This bit defines whether the I/O buffers for the transmit or the receive pin are
included in the communication path (in analog loopback mode).
0

Analog loopback through the transmit pin is enabled.

1

Analog loopback through the receive pin is enabled.

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

GPIO Functionality

www.ti.com

22.12 GPIO Functionality
The following sections apply to all device pins that can be configured as functional or general-purpose I/O
pins.

22.12.1 GPIO Functionality
Figure 22-60 illustrates the GPIO functionality.
Figure 22-60. GPIO Functionality
Output enable
Data out

Device pin

Data in
Input enable
Pull control disable
Pull selectPull control
logic

Output enable
Data out

Device pin

Data in
Input enable

Pull control disable

Pull control
logic

22.12.2 Under Reset
The following apply if a device is under reset:• Pull control. The reset pull control on the pins is enabled.
• Input buffer. The input buffer is enabled.
• Output buffer. The output buffer is disabled.

SPNU517C – March 2018
Submit Documentation Feedback

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

1041

GPIO Functionality

www.ti.com

22.12.3 Out of Reset
The following apply if the device is out of reset:• Pull control. The pull control is enabled by clearing the PD (pull control disable) bit in the SCIPIO7
register (Section 22.11.21). In this case, if the PSL (pull select) bit in the SCIPIO8 register(Section 22.11.22) is set, the pin will have a pull-up. If the PSL bit is cleared, the pin will have a pulldown. If the PD bit is set in the control register, there is no pull-up or pull-down on the pin.
• Input buffer. The input buffer is permanently enabled in this device.
NOTE: The pull-disable logic depends on the pin direction. It is independent of whether the device isin I/O or functional mode. If the pin is configured as output or transmit, then the pulls are
disabled automatically.

•

Output buffer. A pin can be driven as an output pin if the TX DIR bit is set in the pin direction control
register (SCIPIO1; Section 22.11.15) AND the open-drain feature is not enabled in the SCIPIO6
register (Section 22.11.20).

22.12.4 Open-Drain Feature Enabled on a Pin
The following apply if the open-drain feature is enabled on a pin:
• The output buffer is enabled if a low signal is being driven on to the pin.
• The output buffer is disabled (the direction control signal DIR is internally forced low) if a high signal isbeing driven on to the pin.
NOTE: The open-drain feature is available only in I/O mode (SCIPIO0; Section 22.11.14).

22.12.5 Summary
The behavior of the input buffer, output buffer, and the pull control is summarized in Table 22-48.
Table 22-48. Input Buffer, Output Buffer, and Pull Control Behavior as GPIO Pins

(1)
(2)
(3)
(4)

1042

Deviceunder
Reset?

Pin Direction(DIR) (1) (2)Pull Disable(PULDIS) (1) (3)Pull Select(PULSEL) (1) (4)Pull Control

Output Buffer

Input Buffer

Yes

X

X

X

EnabledDisabled

Enabled

No

0

0

0

Pull down

Disabled

Enabled

No

0

0

1

Pull up

Disabled

Enabled

No

0

1

0

Disabled

Disabled

Enabled

No

0

1

1

Disabled

Disabled

Enabled

No

1

X

X

Disabled

EnabledEnabled

X = Don’t care
DIR = 0 for input, = 1 for output
PULDIS = 0 for enabling pull control, = 1 for disabling pull control
PULSEL= 0 for pull-down functionality, = 1 for pull-up functionality

Serial Communication Interface (SCI)/Local Interconnect Network (LIN)
ModuleCopyright © 2018, Texas Instruments Incorporated

SPNU517C – March 2018
Submit Documentation Feedback

Chapter 23
SPNU517C – March 2018

eFuse Controller
This chapter describes the eFuse controller.
Topic

23.1
23.2
23.3
23.4

...........................................................................................................................

Page

Overview........................................................................................................ 1044
Introduction ................................................................................................... 1044
eFuse Controller Testing ................................................................................. 1044
eFuse Controller Registers .............................................................................. 1047

SPNU517C – March 2018
Submit Documentation Feedback

eFuse Controller
Copyright © 2018, Texas Instruments Incorporated

1043

Overviewwww.ti.com

23.1 Overview
Electrically programmable fuses (eFuses) are used to configure the device after deassertion of PORRST.
The eFuse values are read and loaded into internal registers as part of the power-on-reset sequence. The
eFuse values are protected with single bit error correction, double bit error detection (SECDED) codes.
These fuses are programmed during the initial factory test of the device. The eFuse controller is designed
so that the state of the eFuses cannot be changed once the device is packaged.

23.2 Introduction
The eFuse controller automatically reads the values of the eFuses and shifts them into registers during thepower-on reset sequence. No action is required from the application code. However, in a safety criticalapplication, the user code should check to see if a correctable or an uncorrectable error was detectedduring the reset sequence and then preform a self-test on the eFuse controller ECC logic.

23.3 eFuse Controller Testing
23.3.1 eFuse Controller Connections to ESM
There are three connections from the eFuse controller to the Error Signaling Module (ESM). If an
uncorrectable error occurs during the loading of the eFuse values after reset, a group three, channel one
error and a group one channel 40 error are sent to the ESM. The group three error will cause the ERROR
pin to go low. If during the eFuse loading a correctable error occurs, only a group one channel 40 error issent to the ESM. If an error occurs during the eFuse controller self test, then a group one channel 41 error
and a group one channel 40 error are sent to the ESM. After reset, by default, the group one errors do notaffect the ERROR pin. If the software enables the appropriate bit in the appropriate ESM Influence Error
Pin Set/Status Register (ESMIEPSRn) while the group one error is set, the ERROR pin will go low.
Table 23-1. ESM Signals Set by eFuse Controller
Self Test
ESM Signal

Uncorrected Load
FailureGroup 3 Channel 1

X

Group 1 Channel 40

X

Correctable LoadError

eFuse Self Test

X

X

eFuse stuck at 0 Test
Version a:with Error pin

Version b:
without Error pin

XGroup 1 Channel 41

X

X

X

23.3.2 Checking for eFuse Errors After Power Up
For safety critical systems, it is required that you check the status of the eFuse controller after a device
reset. A suggested flow chart for checking the eFuse controller after device reset is shown in Figure 23-1.
Failures during the eFuse self test can be grouped into three levels of severity. Depending on the safety
critical application, the error handling for each error type may be different.
23.3.2.1 Class 1 Error
A class 1 error of the eFuse controller means that there was a failure during the autoload sequence. The
values read from the eFuses cannot be relied on. All device operation is suspect. A class 1 error isindicated by a signal to group 3 channel 1 of the ESM. This will cause the ERROR pin to go active low.
23.3.2.2 Class 2 Errors
A class 2 error is an indication that the safety checks of the eFuse controller did not work. These are also
serious errors because you can no longer guarantee that a more severe error did not occur.

1044

eFuse Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

eFuse Controller Testing

www.ti.com

23.3.2.3 Class 3 Error
A class 3 error indicates that there was a single bit failure reading the eFuses that was corrected by ECC
bits. Proper operation is still likely, but the system is now at a higher risk for a future non-correctable error.
When a correctable error occurs, ESM group 1, channel 40 will be set. In the suggested flow chart shownin Figure 23-1 below, the single bit error is determined by directly reading the eFuse error status register,and not depending on the integrity of the connections between the eFuse controller and the ESM.
23.3.2.4 Stuck at Zero Test
The purpose of the stuck at zero test is to verify that the eFuse controller could signal the ESM if anautoload error did occur. It basically verifies the path through the eFuse controller and to the ESM. This isdone by writing a special instruction to the eFuse controller boundary register, then verifying that theproper bits are set in the eFuse controller pins register. Upon successful completion of this test ESM
group 1 channel 41 and ESM group 3 channel 1 will be set. This will force the ERROR pin low.
• Version A– Write boundary register (address 0xFFF8C01C) with 0x003FC000 to set the error signals.
– Read pins register (address 0xFFF8C02C) and verify that bits 14, 12, 11 and 10 are set.
– Write boundary register (address 0xFFF8C01C) with 0x003C0000, to clear the error signals.
– Verify that ESM group 1 channel 41 and group 3 channel 1 are set, then clear them.
If the system cannot support a test which causes the ERROR pin to go low, then the stuck at zero test canbe modified as follows:• Version B– Write boundary register (address 0xFFF8C01C) with 0x003BC000.
– Read pins register (address 0xFFF8C02C) and verify that bits 14, 12, and 11 are set.
– Write boundary register (address 0xFFF8C01C) with 0x003C0000, to clear the error signals.
– Verify that ESM group 1 channel 41 is set, then clear it.
This alternate method provides less test coverage because the path from the uncorrectable error signal
from the eFuse controller to the ESM is not specifically tested. However, even if this path is broken,
reading the five eFuse error status bits will indicate that an error occurred.
23.3.2.5 eFuse ECC Logic Self Test
The eFuse controller self test performs extensive validation of the ECC logic in the eFuse controller. This
test should only be performed once for every device PORRST cycle. Perform the self test by following
these steps:• Write 0x00000258 to the self test cycles register (EFCSTCY) at address 0xFFF8C048.
• Write 0x5362F97F to the self test signature register (EFCSTSIG) at address 0xFFF8C04C.
• Write 0x0000200F to the boundary register at address 0xFFF8C01C. This triggers the self test. The
test takes 610 VCLK cycles to complete. The application can poll bit 15 of the pins register at address
0xFFF8C02C to wait for the test to complete.
• Check ESM group 1 channels 40 and 41 for any errors, neither should be set.
• Verify that bits 4 to 0 of the eFuse Error Status register at address 0xFFF8C03C are zero.

SPNU517C – March 2018
Submit Documentation Feedback

eFuse Controller
Copyright © 2018, Texas Instruments Incorporated

1045

eFuse Controller Testing

www.ti.com

Figure 23-1. eFuse Self Test Flow CharteFuse Controller
Test

Is ESM group 3
channel 1 set?

Class 1error
routineYN

Test bits 4-0 of
eFuse Error
status register

Are all 5 bits
zero?

N

Y

Run stuckat zero test

Are the 5 bits =0x15?

NStuck at zerotest pass?

Y

Run eFuse
self testN

Did self test
pass?

Y

Run eFuse
self test

Did self test
pass?
Y

N

Y

Class 3error
routineN

Class 2error
routine

PASS

1046

eFuse Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

eFuse Controller Registers

www.ti.com

23.4 eFuse Controller Registers
All registers in the eFuse Controller module are 32-bit, word-aligned; 8-bit, 16-bit and 32-bit accesses areallowed. Table 23-2 provides a quick reference to each of these registers. Specific bit descriptions are
discussed in the following subsections. The base address for the control registers is FFF8 C000h.
Table 23-2. eFuse Controller Registers
OffsetAcronym

Register Description

1Ch

EFCBOUND

EFC Boundary Control Register

Section 23.4.1

Section2Ch

EFCPINSEFC Pins Register

Section 23.4.2

3Ch

EFCERRSTATEFC Error Status Register

Section 23.4.3

48h

EFCSTCYEFC Self Test Cycles Register

Section 23.4.4

4Ch

EFCSTSIG

EFC Self Test Signature Register

Section 23.4.5

23.4.1 EFC Boundary Control Register (EFCBOUND)
Figure 23-2 and Table 23-3 describe the EFCBOUND register. The eFuse Boundary Control Register isused to test the connections between the eFuse controller and the ESM module. The eFuse Boundary
Control Register is also used to initiate an eFuse controller ECC self-test.
Figure 23-2. EFC Boundary Control Register (EFCBOUND) [offset = 1Ch]
31

24
Reserved
R-0

23

21

20

19

18

17

16

Reserved

22

EFC Self Test
Error

EFC Single Bit
Error

EFC Instruction
Error

EFC Autoload
Error

Self Test
Error OE

Single Bit
Error OE

R-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

12

15

14

13

Instruction
Error OE

Autoload
Error OE

EFC ECC Selftest
EnableReserved

R/W-0

R/W-0

R/W-0

R-0

7

4

8

3

0

Reserved

Input Enable

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after power-on reset (nPORRST)

Table 23-3. EFC Boundary Register (EFCBOUND) Field Descriptions
Bit

Field

31-22

Reserved

21

20

Value
0

EFC Self Test Error

Description
Read returns 0. Writes have no effect.
This bit drives the self test error signal when bit 17 (Self Test Error OE) is high. This signal
is attached to ESM error Group 1, Channel 41.

0

Drives the self test error signal low, if Self Test OE is high.

1

Drives the self test error signal high, if Self Test OE is high.

EFC Single Bit Error

This bit drives the single bit error signal when bit 16 (Single bit Error OE) is high. This signal
is attached to ESM error Group 1, Channel 40.
0

Drives the self test error signal low, if Single Bit Error OE is high.

1

Drives the self test error signal high, if Single Bit Error OE is high.

SPNU517C – March 2018
Submit Documentation Feedback

eFuse Controller
Copyright © 2018, Texas Instruments Incorporated

1047

eFuse Controller Registers

www.ti.com

Table 23-3. EFC Boundary Register (EFCBOUND) Field Descriptions (continued)
Bit

Field

19

EFC Instruction Error

18

17

16

15

14

13

Value

This bit drives the instruction error signal when bit 15 (Instruction Error OE) is high. Thissignal is used to denote an error occurred during e-fuse programming. This signal is not
attached to the ESM.
0

Drives the Instruction Error signal low, if Instruction Error OE is high.

1

Drives the Instruction Error signal high, if Instruction Error OE is high.

EFC Autoload Error

This bit drives the Autoload Error signal when bit 14 (Autoload Error OE) is high. This signal
is attached to ESM error Group 3, Channel 1.
0

Drives the Autoload Error signal low, if Autoload Error OE is high.

1

Drives the Autoload Error signal high, if Autoload Error OE is high.

Self Test Error OE

The Self Test Error Output Enable bit determines if the EFC Self Test signal comes from theeFuse controller or from bit 21 of the boundary register.
0

EFC Self Test Error comes from eFuse controller.

1

EFC Self Test Error comes from the boundary register.

Single Bit Error OE

The single bit error output enable signal determines if the EFC Single Bit Error signal comesfrom the eFuse controller or from bit 20 of the boundary register.
0

EFC Single Bit Error comes from eFuse controller.

1

EFC Single Bit Error comes from the boundary register.

Instruction Error OE

The instruction error output enable signal determines if the EFC Instruction Error signal
comes from the eFuse controller or from bit 19 of the boundary register.
0

EFC Instruction Error comes from eFuse controller.

1

EFC Instruction Error comes from the boundary register.

Autoload Error OE

The autoload error output enable signal determines if the EFC Autoload Error signal comesfrom the eFuse controller or from bit 18 of the boundary register.
0

EFC Autoload Error comes from eFuse controller.

1

EFC Autoload Error comes from the boundary register.

EFC ECC Selftest
Enable12-4

Reserved

3-0

Input Enable

The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four
input enable bits (EFCBOUND[3:0) are all 1s.
0

No action

1

Start ECC selftest if EFCBOUND[3:0] are Fh.

0Read returns 0. Writes have no effect.
The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four
input enable bits (EFCBOUND[3:0) are all 1s.

Fh
All others

1048

Description

ECC selftest can be started if EFC ECC Selftest Enable, bit 13, is set
ECC selftest cannot be started.

eFuse Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

eFuse Controller Registers

www.ti.com

23.4.2 EFC Pins Register (EFCPINS)
Figure 23-3 and Figure 23-3 describe the EFCPINS register.
Figure 23-3. EFC Pins Register (EFCPINS) [offset = 2Ch]
31

16
Reserved
R-0
15

14

13

12

11

10

EFC Selftest
Done

EFC Selftest
Error

Reserved

EFC Single Bit
Error

EFC Instruction
Error

EFC Autoload
Error

9
Reserved

8

R-0

R-0

R-0

R-x

R-0

R-x

R-x

7

0
Reserved
R-x

LEGEND: R = Read only; -n = value after power-on reset (nPORRST); x = Indeterminate

Table 23-4. EFC Pins Register (EFCPINS) Field Descriptions
Bit
31–16
15

14

Name
Reserved

12

EFC Single Bit Error

9-0

Reads return zeros, writes have no effect.

0

EFC ECC selftest is not complete.

1

EFC ECC selftest is complete.
This bit indicates the pass/fail status of the EFC ECC Selftest once the EFC Selftest Donebit (bit 15) is set.

0

EFC ECC Selftest passed.

1

EFC ECC Selftest failed.

0

Reads return zeros. Do NOT write a 1 to this bit.
This bit indicates if a single bit error was corrected by the ECC logic during the autoload
after reset.

0

No single bit error was detected.

1

A single bit error was detected and corrected.

EFC Instruction Error

This bit indicates an error occurred during a factory test or program operation. This bit
should not be set from normal use.
0

No instruction error detected.

1

An error occurred during a factory test or program operation.

EFC Autoload Error

Reserved

Description
This bit can be polled to determine when the EFC ECC selftest is complete

EFC Selftest Error

Reserved

100

EFC Selftest Done

13

11

Value

This bit indicates that some non-correctable error occurred during the autoload sequence
after reset. This bit also sets ESM group 3, channel 1.
0

The autoload function completed successfully.

1

There were non-correctable errors during the autoload sequence.

0-1

After reset, these bits are indeterminate and reads return either a 1 or 0.

SPNU517C – March 2018
Submit Documentation Feedback

eFuse Controller
Copyright © 2018, Texas Instruments Incorporated

1049

eFuse Controller Registers

www.ti.com

23.4.3 EFC Error Status Register (EFCERRSTAT)
Figure 23-4 and Table 23-5 describe the EFCERRSTAT register.
Figure 23-4. EFC Error Status Register (EFCERRSTAT) [offset = 3Ch]
31

8
Reserved
R-0
7

6

5

4

0

Reserved

Instruc Done

Error Code

R-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after power-on reset (nPORRST)

Table 23-5. EFC Error Status Register (EFCERRSTAT) Field Descriptions
Bit

Name

31–6

Reserved

5

4-0

Value
0

Instruc Done

Description
Reads return zeros, writes have no effect.
Instruction done. Used to indicate that the eFuse self test has completed

0

The eFuse controller is still executing.

1

The eFuse controller has completed executing.

Error CodeThe error status of the last instruction executed by the eFuse Controller
0

No error.

5h

An uncorrectable (multibit) error was detected during the power-on autoload sequence.

15h

At least one single bit error was detected and corrected during the power-on autoload
sequence.

18h

The signature generated by the ECC self-test logic did not match the golden signature
written in the EFCSTSIG register. The EDAC circuitry might have a fault.

All othervaluesAll other values are reserved for e-fuse system tests and are not expected to occur innormal system use.

23.4.4 EFC Self Test Cycles Register (EFCSTCY)
Figure 23-5 and Table 23-6 describe the EFCSTCY register.
Figure 23-5. EFC Self Test Cycles Register (EFCSTCY) [offset = 48h]31

16CyclesR/W-0

150
Cycles
R/W-0

LEGEND: R/W = Read/Write; -n = value after power-on reset (nPORRST)

Table 23-6. EFC Self Test Cycles Register (EFCSTCY) Field Descriptions
Bit

Name

Description

31–0

CyclesThis register is used to determine the number of cycles to run the eFuse controller ECC logic self test. It is
recommended to use a value of 600 (0x00000258).

1050

eFuse Controller

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

eFuse Controller Registers

www.ti.com

23.4.5 EFC Self Test Signature Register (EFCSTSIG)
Figure 23-6 and Table 23-7 describe the EFCSTSIG register.
Figure 23-6. EFC Self Test Cycles Register (EFCSTSIG) [offset = 4Ch]
31

16
Signature
R/W-0

15

0
Signature
R/W-0

LEGEND: R/W = Read/Write; -n = value after power-on reset (nPORRST)

Table 23-7. EFC Self Test Cycles Register (EFCSTSIG) Field Descriptions
Bit

Name

Description

31–0

Signature

This register is used to hold the expected signature for the eFuse ECC logic self test. It is recommended towrite a value of 0x5362F97F to this register and a value of 600 (0x00000258) to the EFCSTCY register. If
after running the eFuse ECC logic self test, the calculated signature does not match the expectedsignature in the EFCSTSIG register, then a value of 18h is stored in the EFCERRSTAT register.

SPNU517C – March 2018
Submit Documentation Feedback

eFuse Controller
Copyright © 2018, Texas Instruments Incorporated

1051

Revision History

www.ti.com

Revision History
Changes from January 9, 2016 to February 28, 2018 ..................................................................................................... Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Chapter 1: Introduction ............................................................................................................... 57
Chapter 2: Architecture ............................................................................................................... 62
Table 2-2: Changed table. Added Access Mode column ........................................................................... 65
Table 2-6: Corrected value in Valid RAM Groups column for number 13 ........................................................ 73
Table 2-6: Corrected value in Valid RINFO Register Value column for numbers 31 and 32 .................................. 73
Section 2.3.1: Updated third sentence in second paragraph. Changed to minimum of 32 peripheral clock (VCLK)
cycles ...................................................................................................................................... 76
Table 2-28: Changed Description of bits for Value = 0 (Read) to enabled....................................................... 94
Section 2.5.1.13: Added second paragraph to NOTE .............................................................................. 95
Table 2-42: Corrected Description of PLLMUL bit. Value = 0h is ×1, Value = 100h is ×2 ................................... 110
Table 2-52: Changed Description of PLL1_FBSLIP_FILTER_ COUNT and PLL1_FBSLIP_FILTER_ KEY bits .......... 122
Section 2.5.1.44: Changed paragraph............................................................................................... 129
Section 2.5.1.44: Added NOTE....................................................................................................... 129
Section 2.5.1.45: Changed NOTE ................................................................................................... 130
Table 2-62: Added Note to VCLK2R and VCLKR bits ............................................................................ 130
Section 2.5.1.48: Added NOTE....................................................................................................... 132
Figure 2-52: Changed Reserved bits to 2-0 ........................................................................................ 133
Figure 2-52: Deleted MPMODE bit .................................................................................................. 133
Table 2-66: Changed Reserved bits to 2-0 ......................................................................................... 133
Table 2-66: Deleted MPMODE bit ................................................................................................... 133
Table 2-74: Changed Description of PLL1_SLIP_FILTER_COUNT and PLL1_SLIP_FILTER_KEY bits .................. 140
Section 2.5.2.4: Changed paragraph ................................................................................................ 141
Figure 2-61: Corrected register bit fields ............................................................................................ 141
Table 2-76: Changed table to reflect updated register bit fields ................................................................. 141
Section 2.5.2.5: Changed paragraph ................................................................................................ 142
Figure 2-62: Corrected register bit fields ............................................................................................ 142
Table 2-77: Changed table to reflect updated register bit fields ................................................................. 142
Table 2-85: Corrected register names in Description of PROTSET bit for Value = 1 (Write) ................................ 147
Table 2-86: Corrected register names in Description of PROTSET bit for Value = 1 (Write) ................................ 148
Table 2-87: Corrected register names in Description of PROTSET bit for Value = 1 (Write) ................................ 148
Table 2-88: Corrected register names in Description of PROTSET bit for Value = 1 (Write) ................................ 149
Table 2-89: Corrected register names in Description of PROTCLR bit for Value = 1 (Write) ................................ 149
Table 2-90: Corrected register names in Description of PROTCLR bit for Value = 1 (Write) ................................ 150
Table 2-91: Corrected register names in Description of PROTCLR bit for Value = 1 (Write) ................................ 150
Table 2-92: Corrected register names in Description of PROTCLR bit for Value = 1 (Write) ................................ 151
Chapter 3: I/O Multiplexing and Control Module (IOMM) ..................................................................... 159
Chapter 4: F021 Flash Module Controller........................................................................................ 173
Section 4.1.2: Added definition for ATCM........................................................................................... 174
Section 4.6.2: Updated second paragraph.......................................................................................... 184
Table 4-8: Updated Description of test modes ..................................................................................... 184
Section 4.6.2.1: Updated eighth sentence in second paragraph. Changed ECC_MUL_ERR to ERR_PRF_FLG ........ 185
Section 4.6.2.5: Added NOTE ........................................................................................................ 186
Section 4.6.2.5: Updated second paragraph ....................................................................................... 186
Section 4.6.2.6: Updated second sentence in second paragraph. Corrected the value. ..................................... 187
Section 4.6.2.6: Updated first sentence in fourth paragraph. Changed ECC_MUL_ERR to B1_UNC_ERR .............. 187
Section 4.6.2.6: Updated steps in fifth paragraph.................................................................................. 187
Table 4-9: Updated Name of test modes ........................................................................................... 187
Table 4-9: Updated test mode 7. Changed ECC_MUL_ERR to B1_UNC_ERR .............................................. 187
Table 4-10: Updated Name of test modes .......................................................................................... 188

1052

Revision History

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Revision History

www.ti.com

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Table 4-10: Updated test mode 1. Deleted D_MUL_ERR ........................................................................ 188
Table 4-10: Updated test mode 1. Changed ERR_MUL_FLG to ERR_PRF_FLG ............................................ 188
Table 4-10: Updated test mode 1. Deleted EE_D_MUL_ERR ................................................................... 188
Table 4-10: Updated test mode 1. Changed EE_ERR_MUL_FLG to EE_ERR_PRF_FLG .................................. 188
Table 4-10: Updated test mode 3. Changed EE_MAL_ERR to EE_CME ...................................................... 188
Table 4-10: Updated test mode 4. Changed EE_COM_MAL_GOOD to EE_CMG and EE_MAL_ERR to EE_CME .... 188
Table 4-11: Updated Name of test modes .......................................................................................... 189
Table 4-14: Changed Description of EDACMODE bit ............................................................................. 192
Table 4-24: Changed Description of PROTL1DIS bit ............................................................................. 204
Section 4.7.22: Added paragraph .................................................................................................... 213
Table 4-34: Changed Description of EMU_DMSW bit ............................................................................ 213
Section 4.7.23: Added paragraph .................................................................................................... 213
Table 4-35: Changed Description of EMU_DLSW bit ............................................................................. 213
Section 4.7.24: Added paragraph .................................................................................................... 214
Table 4-36: Changed Description of EMU_ECC bit ............................................................................... 214
Section 4.7.25: Added paragraph .................................................................................................... 215
Table 4-37: Changed Description of EMU_ADDR bit ............................................................................. 215
Section 4.7.26: Deleted second paragraph ......................................................................................... 216
Table 4-38: Updated Description of DIAG_MODE bit ............................................................................. 216
Section 4.7.30: Deleted paragraph .................................................................................................. 220
Section 4.7.35: Changed paragraph ................................................................................................. 225
Table 4-47: Changed Description of EE_EDACMODE bit ........................................................................ 225
Table 4-52: Changed Description of EE_CMG bit ................................................................................. 229
Table 4-52: Added Description for bit 4, EE_CME................................................................................. 229
Chapter 5: Tightly-Coupled RAM (TCRAM) Module ........................................................................... 232
Table 5-2: Updated Description of EMU_TRACE_DIS bit. Tracing of read data to RAM Trace Port (RTP) module during
emulation mode access ............................................................................................................... 238
Chapter 6: Programmable Built-In Self-Test (PBIST) Module................................................................ 246
Section 6.3.1: Changed step 6. Deleted ROM interface clock ................................................................... 250
Section 6.5: Changed second paragraph (write 1h) ............................................................................... 253
Section 6.6.1: Changed step 5. Deleted ROM interface clock ................................................................... 265
Section 6.6.1: Changed step 12. Deleted ROM clock ............................................................................. 265
Section 6.6.2: Changed step 5. Deleted ROM interface clock ................................................................... 266
Section 6.6.2: Changed step 11. Deleted ROM clock ............................................................................. 266
Chapter 7: CPU Self-Test Controller (STC) Module ............................................................................ 267
Chapter 8: CPU Compare Module for Cortex-R4 (CCM-R4) .................................................................. 283
Chapter 9: Oscillator, PLL, and Clock Monitoring ............................................................................. 291
Section 9.5: Updated third paragraph. Changed f(HCLK) to f(GCLK)................................................................... 300
Table 9-1: Updated Frequency Limit value to f(GCLK)for fPLL CLK ..................................................................... 300
Table 9-2: Updated formula for NF .................................................................................................. 301
Section 9.5.4: Added last sentence to step 3....................................................................................... 307
Section 9.8: Changed step 3, second sentence ................................................................................... 315
Chapter 10: Dual-Clock Comparator (DCC) Module ........................................................................... 317
Table 10-13: Changed Description of KEY bit for Value = All other values .................................................... 330
Chapter 11: Error Signaling Module (ESM) ...................................................................................... 331
Section 11.1.2: Changed first paragraph ............................................................................................ 332
Chapter 12: Real-Time Interrupt (RTI) Module .................................................................................. 353
Equation 24: Corrected first eqution (if RTICPUCy ≠ 0) .......................................................................... 357
Figure 12-13: Updated Read/Write value of bits to R/WP-0 ...................................................................... 367
Figure 12-13: Updated LEGEND to include WP ................................................................................... 367
Chapter 13: Cyclic Redundancy Check (CRC) Controller Module .......................................................... 390
Chapter 14: Vectored Interrupt Manager (VIM) Module ....................................................................... 403
Section 14.4: Added NOTE ........................................................................................................... 411
Chapter 15: Enhanced Quadrature Encoder Pulse (eQEP) Module ........................................................ 433

SPNU517C – March 2018
Submit Documentation Feedback

Revision History
Copyright © 2018, Texas Instruments Incorporated

1053

Revision History
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

www.ti.com

Chapter 16: Analog To Digital Converter (ADC) Module ..................................................................... 471
Figure 16-9: Corrected bit range of the EV_CURRENT_COUNT, EV_MAX_COUNT, G1_CURRENT_COUNT,G1_MAX_COUNT, G2_CURRENT_COUNT, and G2_MAX_COUNT bits to 4-0 ............................................. 482
Table 16-11: Changed Description of FRZ_EV bit. (The Event Group conversion is kept frozen while the Group1 orGroup2 conversion is active,) ......................................................................................................... 508
Table 16-12: Changed Description of FRZ_G1 bit. (The Group1 conversion is kept frozen while the Event Group orGroup2 conversion is active,) ......................................................................................................... 511
Table 16-13: Changed Description of FRZ_G2 bit. (The Group2 conversion is kept frozen while the Event Group orGroup1 conversion is active,) ......................................................................................................... 514
Chapter 17: High-End Timer (N2HET) Module .................................................................................. 566
Table 17-9: Changed Pull Control = Enabled when device is under reset ..................................................... 596
Table 17-9: Added Input Buffer column ............................................................................................. 596
Table 17-24: Changed Description of HETPRY bit ................................................................................ 615
Chapter 18: High-End Timer Transfer Unit (HTU) Module .................................................................... 703
Figure 18-13: Changed position of third rising edge in waveform ............................................................... 717
Chapter 19: General-Purpose Input/Output (GIO) Module.................................................................... 755
Table 19-22: Changed Pull Control = Enabled when device is under reset .................................................... 781
Chapter 20: Controller Area Network (DCAN) Module ........................................................................ 782
Section 20.2.3.2.3: Changed tq = 1 µs ............................................................................................... 789
Section 20.2.16: Changed subsection ............................................................................................... 818
Table 20-6: Added Core Release Register ......................................................................................... 818
Section 20.3.8: Added subsection. Subsequent subsections, figures, and tables renumbered ............................. 828
Table 20-31: Changed the Func Bit description for Value = 1. (as an input to receive CAN data) ......................... 854
Chapter 21: Multi-Buffered Serial Peripheral Interface Module (MibSPI) .................................................. 856
Chapter 21: Global: Changed SPISCS to SPICS .................................................................................. 856
Section 21.2: Changed first sentence in second paragraph ...................................................................... 858
Table 21-1: Changed SPIENA enabled description in Slave Mode ............................................................. 859
Figure 21-6: Corrected figure title .................................................................................................... 865
Figure 21-6: Corrected bits D11-D8 to 1110........................................................................................ 865
Figure 21-7: Corrected figure title .................................................................................................... 865
Section 21.7.1: Changed second sentence ......................................................................................... 877
Section 21.7.1: Changed second sentence ......................................................................................... 878
Section 21.8: Global: Updated all VBUSPCLK signals to VCLK ................................................................. 879
Table 21-3: Added SPIPC9 at address offset 68h ................................................................................. 879
Table 21-10: Corrected Description of SIMODIR0 bit ............................................................................. 889
Section 21.8.16: Added NOTE ....................................................................................................... 901
Table 21-19: Updated Description of CSNR and TXDATA bits .................................................................. 901
Table 21-20: Added table. Subsequent tables renumbered ...................................................................... 903
Table 21-21: Corrected Description of RXEMPTY bit. (SPIBUF to RXDATA) ................................................. 904
Table 21-23: Corrected Value column for all bits to 0-FFh ....................................................................... 906
Table 21-23: Updated Description of C2TDELAY bit. Deleted first NOTE ..................................................... 906
Section 21.8.24: Added subsection. Subsequent subsections, figures, and tables renumbered ............................ 915
Table 21-30: Updated bit Descriptions to clarify register bit number corresponding to TG number ........................ 917
Table 21-31: Updated bit Descriptions to clarify register bit number corresponding to TG number ........................ 918
Table 21-31: Changed Description of CLRINTENRDY and CLRINTENSUS bits for Value = 1 (Write). The interrupt does
not get generated ...................................................................................................................... 918
Table 21-32: Updated bit Descriptions to clarify register bit number corresponding to TG number ........................ 919
Table 21-33: Updated bit Descriptions to clarify register bit number corresponding to TG number ........................ 920
Table 21-33: Changed Description of CLRINTLVLRDY and CLRINTLVLSUS bits for Value = 1 (Write). Clear the TGxinterrupt INT0 ........................................................................................................................... 920
Table 21-34: Updated bit Descriptions to clarify register bit number corresponding to TG number ........................ 921
Table 21-35: Changed Description of TICKENA bit for Value = 1. Deleted second sentence ............................... 922
Table 21-36: Changed Note in LPEND bit .......................................................................................... 923
Table 21-43: Changed Description of ERR SCS PIN bit .......................................................................... 932
Figure 21-61: Changed format ....................................................................................................... 934

1054

Revision History

SPNU517C – March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated

Revision History

www.ti.com

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Figure 21-62: Changed format ....................................................................................................... 936
Section 21.9.3: Added NOTE ......................................................................................................... 940
Table 21-47: Updated Description of CSHOLD and TXDATA bits .............................................................. 940
Table 21-48: Added table. Subsequent tables renumbered ...................................................................... 942
Table 21-49: Corrected bits descriptions (SPIBUF to RXRAM) .................................................................. 943
Chapter 22: Serial Communication Interface (SCI)/Local Interconnect Network (LIN) Module ....................... 952
Section 22.4: Updated both paragraphs ............................................................................................ 969
Section 22.4: Updated procedure in second paragraph .......................................................................... 969
Section 22.4.1.1: Updated first and last paragraphs............................................................................... 969
Section 22.4.1.2: Updated paragraph ............................................................................................... 970
Section 22.4.2.1: Updated first and last paragraphs............................................................................... 970
Section 22.4.2.1: Changed number 2 in second paragraph to Transmit Interrupt ............................................. 970
Section 22.4.2.2: Updated paragraph ............................................................................................... 970
Section 22.8: Updated paragraph .................................................................................................... 990
Section 22.8: Updated procedure .................................................................................................... 990
Section 22.8.1.1: Updated first and last paragraphs............................................................................... 990
Section 22.8.1.2: Updated paragraph ............................................................................................... 991
Section 22.8.2.1: Updated first and last paragraphs............................................................................... 991
Section 22.8.2.1: Changed number 2 in second paragraph to Transmit Interrupt ............................................. 991
Section 22.8.2.2: Updated paragraph ............................................................................................... 991
Section 22.12.2: Changed first bullet............................................................................................... 1041
Table 22-48: Changed Pull Control = Enabled when device is under reset .................................................. 1042
Chapter 23: eFuse Controller ..................................................................................................... 1043

SPNU517C – March 2018
Submit Documentation Feedback

Revision History
Copyright © 2018, Texas Instruments Incorporated

1055

IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES
Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to,reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who aredeveloping applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you(individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms ofthis Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,enhancements, improvements and other changes to its TI Resources.
You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing yourapplications and that you have full and exclusive responsibility to assure the safety of your applications and compliance of your applications(and of all TI products used in or for your applications) with all applicable regulations, laws and other applicable requirements. You
represent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1)anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures thatmight cause harm and take appropriate actions. You agree that prior to using or distributing any applications that include TI products, youwill thoroughly test such applications and the functionality of such TI products as used in such applications. TI has not conducted any
testing other than that specifically described in the published documentation for a particular TI Resource.
You are authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include
the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TOANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTYRIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING TI RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS.
TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY YOU AGAINST ANY CLAIM, INCLUDING BUT NOT
LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF
DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL,COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR
ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
You agree to fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of your noncompliance with the terms and provisions of this Notice.
This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services.
These include; without limitation, TI’s standard terms for semiconductor products http://www.ti.com/sc/docs/stdterms.htm), evaluation
modules, and samples (http://www.ti.com/sc/docs/sampterms.htm).

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated