TMS320F28P550SJ, TMS320F28P559SJ-Q1SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

TMS320F28P55x Real-Time Microcontrollers
1 Features
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Real-time processing:– 150MHz C28x 32-bit DSP CPU– Equivalent to 300MHz Arm® Cortex®-M7
based device on real-time signal chain
performance (see the Real-time Benchmarks
Showcasing C2000™ Control MCU's Optimized
Signal Chain Application Note
– IEEE 754 single-precision Floating-Point Unit
(FPU32)– Trigonometric Math Unit (TMU)• Support for Nonlinear Proportional Integral
Derivative (NLPID) control– CRC Engine and Instructions (VCRC)
Programmable Control Law Accelerator (CLA)– 150MHz– Equivalent to 200MHz Arm® Cortex®-M7
based device on real-time signal chain
performance (see the Real-time Benchmarks
Showcasing C2000™ Control MCU's Optimized
Signal Chain Application Note
– IEEE 754 single-precision floating-point
instructions– Executes code independently of main CPU
On-chip memory– 1088KB of flash (ECC-protected) across fiveindependent banks• Four 256KB banks• One 64KB bank, ideal of LFU/Bootloaders/data– 8KB of OTP (One Time Programmable flash
memory)– 133KB of RAM (ECC/Parity protected)
Security– Secure Boot
– JTAG Lock
– Advanced Encryption Standard (AES)
accelerator– Unique Identification (UID) number
Clock and system control– Two internal 10MHz oscillators– Crystal oscillator or external clock input– Windowed watchdog timer module– Missing clock detection circuitry– Dual-clock Comparator (DCC)
3.3V I/O design– Internal VREG generation allows for singlesupply design– Brownout reset (BOR) circuit

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– 5V failsafe and tolerant capability on 4 GPIOs
for PMBUS/I2C support– Configurable 1.35V VIH on 4 GPIOs
System peripherals– 6-channel Direct Memory Access (DMA)
controller– 91 individually programmable multiplexed
General-Purpose Input/Output (GPIO) pins
(22 shared with Analog)– 17 digital inputs on analog pins
– Enhanced Peripheral Interrupt Expansion(ePIE)– Multiple low-power mode (LPM) support
Communications peripherals– One Power-Management Bus (PMBus)interface• Fast Plus Mode Support - 1MHz SCL• 5V/3.3V/1.35V VIH support on select pins
– Two Inter-integrated Circuit (I2C) interfaces– Two Controller Area Network with Flexible
Data-Rate (CAN FD/MCAN) bus port
• 4KB message RAM per MCAN module,
independent of system memory• Ability to re-use RAM for CPU data variables
if MCAN is not used
– One Universal Serial Bus (USB 2.0 MAC +PHY)– Two Serial Peripheral Interface (SPI) ports– Three UART-compatible Serial Communication
Interface (SCI)– One UART-compatible Local Interconnect
Network (LIN) interface– Fast Serial Interface (FSI) with one transmitterand one receiver (up to 200Mbps)
Analog system– Five 3.9MSPS, 12-bit Analog-to-Digital
Converters (ADCs)• Up to 39 external channels (includes one
gpdac output)• Four integrated Post-Processing Blocks(PPB) per ADC– Four windowed comparators (CMPSS) with
12-bit reference Digital-to-Analog Converters(DACs)• Digital glitch filters• Low DAC output to pin capability on
CMPSS1– One 12-bit buffered DAC output

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTIONDATA.

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2

– Three Programmable Gain Amplifiers (PGAs)• Unity gain support• Inverting and non-inverting gain mode
support• Programmable output filtering
Enhanced control peripherals– 24 ePWM channels with 12 channels that havehigh-resolution capability (150ps resolution)• Integrated dead-band support• Integrated hardware trip zones (TZs)– Two Enhanced Capture (eCAP) modules– Three Enhanced Quadrature Encoder Pulse(eQEP) modules with support for CW/CCW
operation modes– Embedded Pattern Generator (EPG)
Configurable Logic Block (CLB)– 2 tiles– Augments existing peripheral capability– Supports position manager solutions
Neural-network Processing Unit (NPU)– Highly Optimized for Deep Convolutional
Neural Networks (CNN)– Variable weights and data lengths• 8-bit and 4-bit weights• 8-bit and 4-bit data
– 600MOPS (Mega Operations Per Second) at
75MHz on 8bWx8bD– 1200MOPS at 75MHz on 4bWx8bD– Up to 10x NN inferencing performance
improvement vs SW techniques– No direct coding required, TI AI tools generate
FW libraries– Real-time control focused Edge AI Models• ARC fault example• Motor fault example
Live Firmware Update (LFU)
Diagnostic features– Memory Power-On Self-Test (MPOST)
Functional Safety-Compliant targeted– Developed for functional safety applications– Documentation available to aid ISO 26262 andIEC 61508 system design– Systematic capability up to ASIL D and SIL 3targeted– Hardware integrity up to ASIL B targeted
Safety-related certification– ISO 26262 certification up to ASIL B by TÜVSÜD planned
Package options:– 128-pin Thin Quad Flatpack (TQFP)[PDT suffix]– 100-pin Low-profile Quad Flatpack (LQFP)[PZ suffix]
Submit Document Feedback•– 80-pin TQFP [PNA suffix]– 64-pin LQFP [PM suffix]– 56-pin Very Thin Quad Flatpack No-Lead(VQFN) [RSH suffix]
Temperature options:– Junction (TJ): –40°C to 150°C

2 Applications
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Appliances– Air conditioner outdoor unit
Building automation– Door operator drive control
Industrial machine & machine tools– Automated sorting equipment– Textile machine
AC inverter & VF drives– AC drive control module– AC drive position feedback– AC drive power stage module
Linear motor transport systems– Linear motor power stage
Single & multi axis servo drives– Servo drive position feedback– Servo drive power stage module
Speed controlled BLDC drives– AC-input BLDC motor drive– DC-input BLDC motor drive
Factory automation– Robot servo drive– Mobile robot motor control– Position sensor
Industrial power– Industrial AC-DC
UPS– Three-phase UPS– Single-phase online UPS
Telecom & server power– Merchant DC/DC– Merchant network & server PSU– Merchant telecom rectifiersHybrids, electric & powertrain systems– DC/DC converter– Inverter & motor control– On-board (OBC) & wireless charger– Virtual engine sound system (VESS)– Engine fan– eTurbo/charger– Pump– Electric power steering (EPS)
Infotainment and cluster– Head-up display– Automotive head unit
– Automotive external amplifier
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Body electronics & lighting– Automotive HVAC compressor module– DC/AC inverter– Headlight
ADAS– Mechanically scanning LIDAREV charging infrastructure– AC charging (pile) station– DC charging (pile) station– EV charging station power module– Wireless EV charging station••

Renewable energy storage– Energy storage power conversion system(PCS)– Portable Power Station
Solar energy– Central inverter– Micro inverter– Solar power optimizer– Solar arc protection– Rapid shutdown– String inverter

3 Description
The TMS320F28P55x (F28P55x) is a member of the C2000™ real-time microcontroller family of scalable,
ultra-low latency devices designed for efficiency in power electronics, including but not limited to: high power
density, high switching frequencies, and supporting the use of GaN and SiC technologies.
These include such applications as:
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Motor drives
AppliancesHybrid, electric & powertrain systems
Solar & EV charging
Digital power
Body electronics & lighting
Test & measurement

The real-time control subsystem is based on TI’s 32-bit C28x DSP core, which provides 150MHz of signalprocessing performance for floating- or fixed-point code running from either on-chip flash or SRAM. The
C28x CPU is further boosted by the Floating-Point Unit (FPU), Trigonometric Math Unit (TMU), and VCRC
(Cyclical Redundancy Check) extended instruction sets, speeding up common algorithms key to real-time control
systems.
The CLA allows significant offloading of common tasks from the main C28x CPU. The CLA is an independent32-bit floating-point math accelerator that executes in parallel with the CPU. Additionally, the CLA has its own
dedicated memory resources and it can directly access the key peripherals that are required in a typical control
system. Support of a subset of ANSI C is standard, as are key features like hardware breakpoints and hardware
task-switching.
The Neural-network Processing Unit (NPU) can support machine-learning inferencing using pre-trained models.
Capable of 600–1200MOPS (Mega Operations Per Second) with model support for ARC fault detection orMotor Fault detection, the NPU provides up to 10x NN inferencing cycle improvement versus a SW-only-based
implementation. Load and train models with the Model Composer GUI from TI or with the Tiny ML Modelmakerfor an advanced set of capabilities. Source code for the C28x is generated by these tools, no manual coding isnecessary. For customers who rely on their own AI training framework, TI's Neural Network Compiler can help
port your AI model to be compatible with many C28x-based MCUs. For those interested in reference solutions,request access to TI's Arc Fault Detection Project or the Motor Bearing Fault Detection Project.
The F28P55x supports up to 1088KB of flash memory divided into four 256KB banks plus one 64KB bank, whichenable programming one bank and execution in another bank in parallel. Up to 133KB of on-chip SRAM is alsoavailable to supplement the flash memory.
The Live Firmware Update hardware enhancements on F28P55x allow fast context switching from the oldfirmware to the new firmware to minimize application downtime when updating the device firmware.
High-performance analog blocks are integrated on the F28P55x real-time microcontroller (MCU) and are closely
coupled with the processing and PWM units to provide optimal real-time signal chain performance. Twenty-four

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PWM channels, all supporting frequency-independent resolution modes, enable control of various power stages
from a 3-phase inverter to power factor correction and advanced multilevel power topologies.
The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate
FPGA-like functions into the C2000 real-time MCU.
Interfacing is supported through various industry-standard communication ports (such as SPI, SCI, I2C, PMBus,
LIN, and CAN FD) and offers multiple pin-muxing options for optimal signal placement.
Want to learn more about features that make C2000 Real-Time MCUs the right choice for your real-time control
system? Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit theC2000™ real-time control MCUs page.
The Getting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guide covers all
aspects of development with C2000 devices from hardware to support resources. In addition to key reference
documents, each section provides relevant links and resources to further expand on the information covered.
Ready to get started? Check out the TMDSCNCD28P55X evaluation board or the LAUNCHXL-F28P55X
development kit, and download C2000Ware.
Package Information
PART NUMBER(1)TMS320F28P559SJ-Q1(4)TMS320F28P550SJ

TMS320F28P559SG-Q1(4)TMS320F28P550SG(4)PACKAGE(2)PACKAGE SIZE(3)PDT (QFP, 128)

16mm x 16mm

PZ (QFP, 100)

16mm x 16mm

PNA (QFP, 80)

12mm x 12mm

PM (QFP, 64)

12mm x 12mm

PDT (QFP, 128)

16mm x 16mm

PZ (QFP, 100)

16mm x 16mm

PNA (QFP, 80)

12mm x 12mm

PM (QFP, 64)

12mm x 12mm

RSH (VQFN, 56)

7mm x 7mm

PDT (QFP, 128)

16mm x 16mm

PZ (QFP, 100)

16mm x 16mm

PNA (QFP, 80)

12mm x 12mm

PM (QFP, 64)

12mm x 12mm

PDT (QFP, 128)

16mm x 16mm

PZ (QFP, 100)

16mm x 16mm

PNA (QFP, 80)

12mm x 12mm

PM (QFP, 64)

12mm x 12mm

RSH (VQFN, 56)

7mm x 7mm

(1)
(2)
(3)
(4)

For more information on these devices, see the Device Comparison table.
For more information, see the Mechanical, Packaging and Orderable Information section.
Package size (length x width) is a nominal value and includes pins, where applicable
Preview information (not Production Data).

4

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3.1 Functional Block Diagram
C28x CPU(150 MHz)
FPU32
TMU
VCRC

CLA
(150 MHz)

Boot ROM
Secure ROM
Flash Bank0128 Sectors, 256KB

SYSTEM CONTROLCPU Timers
XTAL
INTOSC1, INTOSC2
PLLePIE
Windowed WD
NMI WD

CLA to CPU MSG RAM
CPU to CLA MSG RAM

Flash Bank1
128 Sectors, 256KB
Flash Bank2
128 Sectors, 256KB

CLA Data ROM
CLA Program ROM

Flash Bank3
128 Sectors, 256KB
SECURITYJTAG Lock
Secure Boot

CLA to DMA MSG RAM

Flash Bank4
32 Sectors, 64 KB

DMA to CLA MSG RAM
M0-M1 RAM4KB
DIAGNOSTICS
DCC
MPOST
ERAD
JTAG/cJTAG

Buses Legend
LS0-LS9 RAM
64KB

CPU
CLA

NPU

DMA
NPU

GS0-GS3 RAM
64KB

OTHERS
EPG

PF1

PF3

Result24x ePWM Channels(12Ch Hi-Res Capable)

4x CMPSS

2x eCAP

1x Buffered DAC

5x 12-Bit ADC

PF4

Data
65x GPIO
Input XBAR
Output XBAR

DMA
6 Channels

PF2

PF7

PF8

PF9

PF10

1x PMBUS

2x CAN FD

1x LIN

3x SCI

2x CLB

2x SPINPU

Secure Memories Shown in Red

PF11

1x USBPF12

1x AESLFU

2x I2C

1x FSI RX
1x FSI TX

ePWM XBAR
3x eQEP(CW/CCW Support)

CLB XBAR

3x PGA

CLB Input XBARCLB Output XBARA.
B.

The internal DAC from one of the CMPSS modules can be configured as an output DAC.
The LIN module can also be used as a SCI module.

Figure 3-1. Functional Block Diagram

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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 2
3 Description.......................................................................3
3.1 Functional Block Diagram........................................... 5
4 Device Comparison......................................................... 7
4.1 Related Products........................................................ 9
5 Pin Configuration and Functions.................................10
5.1 Pin Diagrams............................................................ 10
5.2 Pin Attributes.............................................................15
5.3 Signal Descriptions................................................... 40
5.4 Pin Multiplexing.........................................................52
5.5 Pins With Internal Pullup and Pulldown.................... 64
5.6 Connections for Unused Pins................................... 65
6 Specifications................................................................ 67
6.1 Absolute Maximum Ratings...................................... 67
6.2 ESD Ratings – Commercial...................................... 68
6.3 ESD Ratings – Automotive....................................... 69
6.4 Recommended Operating Conditions.......................70
6.5 Power Consumption Summary................................. 71
6.6 Electrical Characteristics...........................................76
6.7 Special Considerations for 5V Fail-Safe Pins........... 78
6.8 Thermal Resistance Characteristics for PDT
Package...................................................................... 79
6.9 Thermal Resistance Characteristics for PZ
Package...................................................................... 79
6.10 Thermal Resistance Characteristics for PNA
Package...................................................................... 79
6.11 Thermal Resistance Characteristics for PM
Package...................................................................... 80
6.12 Thermal Resistance Characteristics for RSH
Package...................................................................... 80
6.13 Thermal Design Considerations..............................80
6.14 System.................................................................... 81
6.15 Analog Peripherals................................................124
6.16 Control Peripherals............................................... 168

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6.17 Communications Peripherals................................ 179
7 Detailed Description....................................................212
7.1 Overview................................................................. 212
7.2 Functional Block Diagram....................................... 213
7.3 Memory................................................................... 214
7.4 Identification............................................................225
7.5 Bus Architecture – Peripheral Connectivity.............226
7.6 C28x Processor...................................................... 227
7.7 Control Law Accelerator (CLA)............................... 229
7.8 Embedded Real-Time Analysis and Diagnostic(ERAD)...................................................................... 231
7.9 Direct Memory Access (DMA).................................2327.10 Device Boot Modes...............................................233
7.11 Security................................................................. 240
7.12 Watchdog.............................................................. 241
7.13 C28x Timers..........................................................242
7.14 Dual-Clock Comparator (DCC)............................. 243
7.15 Configurable Logic Block (CLB)............................244
8 Reference Design........................................................ 246
9 Device and Documentation Support..........................248
9.1 Device Nomenclature..............................................248
9.2 Markings................................................................. 249
9.3 Tools and Software................................................. 252
9.4 Documentation Support.......................................... 253
9.5 Support Resources................................................. 255
9.6 Trademarks............................................................. 255
9.7 Electrostatic Discharge Caution..............................255
9.8 Glossary..................................................................255
10 Revision History........................................................ 256
11 Mechanical, Packaging, and Orderable
Information.................................................................. 259
11.1 Package Option Addendum.................................. 260
TAPE AND REEL INFORMATION................................ 262
TRAY.............................................................................264

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4 Device Comparison
Table 4-1. Device Comparison
FEATURE(1) (4)

F28P559SJ-Q1(3) (6)

F28P559SG-Q1(3) (6)

F28P550SJ

F28P550SG(6)C28x Subsystem
Frequency (MHz)150
32-bit Floating-Point Unit (FPU)

C28x

Yes

VCRC

Yes

TMU - Type 1

CLA - Type 2

Yes - Type 1 - NLPID Instruction Supported
1: F28P559SJ9-Q1,
F28P559SJ6-Q1
0: F28P559SJ2-Q1

Number1: F28P559SG9-Q1,
F28P559SG8-Q1
0: F28P559SG2-Q1

1

Frequency (MHz)1

150

6-Channel DMA - Type 0

1

External Interrupts

5

MIPS

300 (CPU + CLA)
MemoryMain Array

Flash

1MB (4 x 256KB Banks)

User OTP

RAM

Message RAM Types

512KB (2 x 256KB Banks)

F28P559SJ9-Q1, F28P550SJ9, F28P559SJ6-Q1, F28P550SJ6, F28P559SG9-Q1,
F28P550SG964KB Bank

8KB

2KB

Dedicated

4KB

Local Shared RAM

64KB

Message

1KB

Global Shared RAM

64KB

32KB

Total RAM

133KB

101KB

C28x CPUs and CLAs

512 bytes (256 bytes per direction)

DMAs and CLAs

512 bytes (256 bytes per direction)

ECC

FLASH, Mx RAM

ParityROM, CAN RAM, Message RAM, LSx RAM, GSx RAM
System2 tiles - F28P559SJ9-Q1, F28P559SJ6-Q1, F28P550SJ9, F28P550SJ6, F28P559SG9-Q1,
F28P550SG9, F28P559SG8-Q1, F28P550SG8

Configurable Logic Block (CLB)
Neural-Network Processing Unit (NPU)

1 - F28P559SJ9-Q1, F28P550SJ9, F28P559SG9-Q1, F28P550SG9

Embedded Pattern Generator (EPG)

132-bit CPU Timers

3

Advanced Encryption Standard (AES) Accelerator

1

Live Firmware Update (LFU) Support

Yes, with enhancements and flash bank erase time improvements

Security for on-chip flash and RAM

Yes

Zero-pin Boot

Yes

Secure Boot

Yes

JTAG Lock

Yes

MPOST

Yes

Embedded Real-time Analysis and Diagnostic (ERAD) - Type 2

1

Non-maskable Interrupt Watchdog (NMIWD) timers

1

Watchdog (WD) timers

1

Crystal oscillator/External clock input

1

Internal Oscillator (Optional External Precision Resistor)

2

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Table 4-1. Device Comparison (continued)
FEATURE(1) (4)

F28P559SJ-Q1(3) (6)

F28P559SG-Q1(3) (6)

F28P550SJ

F28P550SG(6)Digital and Analog Pin Counts
128-pin PDT

GPIO

65

65 - F28P559SG9-Q1, F28P550SG9

100-pin PZ

4380-pin PNA

3264-pin PM

1756-pin RSH-

15

Additional GPIO
128-pin PDT

AIO (analog with digital inputs)-

17

17 - F28P559SG9-Q1, F28P550SG9

100-pin PZ

1680-pin PNA

1264-pin PM

1256-pin RSH-

128-pin PDT

AGPIO (analog with digital inputs and outputs)15

4 (2 from cJTAG and 2 from X1/X2)

12

-

22

12

22 - F28P559SG9-Q1, F28P550SG9

100-pin PZ

1980-pin PNA

1664-pin PM

1656-pin RSH

-

14

-

14

C28x Analog Peripherals(5)Analog-to-Digital Converter (ADC) (12-bit) - Type 6

Number of ADCs

5

MSPS

3.9

Conversion Time(ns)(2)

187

128-pin PDT
ADC Input channels (single-ended) (includes the two DAC
outputs)

39

39 - F28P559SG9-Q1, F28P550SG9

100-pin PZ

3580-pin PNA

28

64-pin PM

2856-pin RSH

26

26

PGA - Type 2

3

Temperature Sensor

1Comparator subsystem (CMPSS) (each CMPSS has two comparators and two internal
DACs) - Type 6

4Buffered Digital-to-Analog Converter (DAC) - Type 2

1

DAC Out from CMPSS

1
C28x Control Peripherals(5)eCAP - Type 2

Total inputs

2

Total channels

24 - F28P559SJ9-Q1,
F28P559SJ6-Q1
16 - F28P559J2-Q1(ePWM1-ePWM8)24

24 - F28P559SG9-Q1,
F28P559SG8-Q1
16 - F28P559SG2-Q1(ePWM1-ePWM8)24Channels with high-resolution capability

12- F28P559SJ9-Q1,
F28P559SJ6-Q1
8 - F28P559SJ2-Q1(HRPWM1-HRPWM4)

1212 - F28P559SG9-Q1,
F28P559SG8-Q1
8 - F28P559SG2-Q1(HRPWM1-HRPWM4)

12ePWM/HRPWM - Type 4

eQEP modules - Type 2

3
C28x Communications Peripherals(5)CAN with Flexible Data-Rate (CAN-FD) - Type 2

2

Fast Serial Interface (FSI) RX - Type 2

1

Fast Serial Interface (FSI) TX - Type 2

1

Inter-Integrated Circuit (I2C) - Type 22

Local Interconnect Network (LIN) - Type 1

1

Power Management Bus (PMBus) - Type 1

1

Serial Communications Interface (SCI) - Type 0 (UART-compatible)

3

Serial Peripheral Interface (SPI) - Type 2
Universal Serial Bus (USB) - Type 08

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1 - F28P559SJ9-Q1, F28P550SJ9,
F28P559SJ6-Q1, F28P550SJ6

1 - F28P559SG9-Q1, F28P550SG9

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Table 4-1. Device Comparison (continued)
FEATURE(1) (4)

F28P559SJ-Q1(3) (6)

F28P550SJ

F28P559SG-Q1(3) (6)

F28P550SG(6)Temperature and Qualification
Junction temperature (TJ)

-40°C to 150°C

Free-Air temperature (TA)-40°C to 125°C

Package Options

128-pin PDT

F28P559SJ9-Q1, F28P559SJ6-Q1, F28P559SJ2-Q1, F28P550SJ9, F28P550SJ6,
F28P559SG9-Q1, F28P550SG9

100-pin PZ

F28P559SJ9-Q1, F28P559SJ6-Q1, F28P559SJ2-Q1, F28P550SJ9, F28P550SJ6,
F28P559SG9-Q1, F28P559SG8-Q1, F28P559SG2-Q1, F28P550SG9, F28P550SG880-pin PNA

F28P559SJ9-Q1, F28P559SJ6-Q1, F28P559SJ2-Q1, F28P550SJ9, F28P550SJ6,
F28P559SG9-Q1, F28P559SG8-Q1, F28P559SG2-Q1, F28P550SG9, F28P550SG864-pin PM

F28P559SJ9-Q1, F28P559SJ6-Q1, F28P559SJ2-Q1, F28P550SJ9, F28P550SJ6,
F28P559SG9-Q1, F28P559SG8-Q1, F28P559SG2-Q1, F28P550SG9, F28P550SG8

56-pin RSH

(1)
(2)
(3)
(4)
(5)
(6)

-

F28P550SJ9,
F28P550SJ6-

F28P550SG9,
F28P550SG8

A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. For more information, see the C2000 Real-Time
Control Peripherals Reference Guide.
Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion.
The suffix -Q1 refers to AEC Q100 qualification for automotive applications.
"-" on the feature entry indicates that the corresponding package type in not available.
For devices that are available in more than one package, the peripheral count listed in the smaller package is reduced because thesmaller package has less device pins available. The number of peripherals internally present on the device is not reduced compared to
the largest package offered within a part number.
Preview information (not Production Data).

4.1 Related Products
TMS320F280013x Real-Time Microcontrollers
The F280013x has common pinouts with the F28P55x series of devices. The F28P55x series adds CLA andDMA support, in addition to faster CPU clock speed and increased memory size. Additionally the F28P55x has
Programmable Gain Amplifiers(PGA), USB, CLB and supports live FW update.
TMS320F28015x Real-Time Microcontrollers
The F280015x has common pinouts with the F28P55x series of devices. The F28P55x series adds CLA andDMA support, in addition to faster CPU clock speed and increased memory size. Additionally the F28P55x
has Programmable Gain Amplifiers(PGA), USB, CLB and supports live FW update. The F280015x series has
lockstep C28x CPUs for safety related systems.
TMS320F28003x Real-Time Microcontrollers
The F28003x has common pinouts with the F28P55x series of devices. The F28P55x series has a faster overall
CPU clock and increased memory options in addition to Programmable Gain Amplifiers(PGA) and USB support.
The F28003x series offers SDFM support, along with BGCRC and HWBIST.

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5 Pin Configuration and Functions
5.1 Pin Diagrams

GPIO40

GPIO0

GPIO1

GPIO2

GPIO3

101

100

99

98

97

GPIO41

GPIO23

103

102

GPIO7

GPIO22

105

104

VSS

GPIO44
106

VDD
108

107

GPIO45

VDDIO

110

109

GPIO76

GPIO75

112

111

GPIO78GPIO77

114

113

GPIO80

GPIO79115

GPIO81
117

116

GPIO9

GPIO5

119

118

GPIO59GPIO61

121

120

GPIO34

GPIO10123

122

GPIO14

GPIO15
124

GPIO6
126

125

GPIO31

GPIO30128

127

Figure 5-1 shows the pin assignments on the 128-pin PDT thin quad flatpack. Figure 5-2 shows the pin
assignments on the 100-pin PZ low-profile quad flatpack. Figure 5-3 shows the pin assignments on the 80-pin
PNA thin quad flatpack. Figure 5-4 shows the pin assignments on the 64-pin PM low-profile quad flatpack.
Figure 5-5 shows the pin assignments on the 56-pin RSH very thin quad flatpack no-lead.

GPIO74

GPIO4912

85

GPIO73

GPIO5013

84

GPIO72

GPIO51

14

83

GPIO71

GPIO5215

82

GPIO58GPIO53

16

81

GPIO57GPIO54

17

80

GPIO56

A6,D14,E14,GPIO228

18

79

GPIO32

B2,C6,E12,GPIO226

19

78

GPIO35/TDI

A3,B3,C5,GPIO242,PGA2_INP

20

77

TMS

A2,B6,C9,GPIO224,PGA1_INP

21

76

GPIO37/TDO

A15,B9,C7,PGA1_INM

22

75

TCK

C25,D5,E5

23

74

GPIO70

A26,D6,E6

24

73

GPIO69

B26,D7,E7

25

72

GPIO68

A14,B14,C4,PGA1_OUT

26

71

GPIO27

A11,B10,C0,PGA2_OUT

27

70

GPIO26

A5,B12,C2,PGA2_INM

28

69

GPIO25

A1,B7,CMP1_DACL,D1129

68

B25,D4,E4,GPIO24

A0,B15,C15,DACA_OUT

30

67

A25,D3,E3,GPIO17

D20,E20,VREFHI

31

66

C24,D2,E2,GPIO16

D20,E20,VREFHI

32

65

B24,D1,E1,GPIO33

A24,D0,E0,GPIO11

A19,B19,C19,GPIO13

A20,B20,C20,GPIO12

A17,B17,C17,GPIO20

A18,B18,C18,GPIO21

GPIO62

GPIO63

GPIO65GPIO64

VDDIO

VSS

VDD

GPIO55GPIO60

B4,C8,GPIO236

A10,B1,C10,GPIO230

A9,GPIO227

A28,D19,E19,GPIO215

C27,D18,E18,GPIO214

A27,D9,E9,GPIO212

B27,D10,E10,GPIO213

A4,B8,C14

C26,D8,E8,GPIO211

VSSA

VDDA

A8,B0,C11

B5,D15,E15,PGA3_OUT

A7,B30,C3,D12,E30

35
A12,C1,E11,PGA3_INP

B11,D16,E16,PGA3_INM

A13,B13,C13,D13,E13,VREFLO

A13,B13,C13,D13,E13,VREFLO

A.

64

86

63

11

62

GPIO18,X2

GPIO48

60

87

61

10

58

GPIO19,X1

GPIO67

59

88

56

9

57

VDDIO

GPIO66

55

89

54

8

53

VDD

GPIO47

51

90

52

7

49

GPIO43

VSS

50

91

47

6

48

VSS

VDD

46

92

45

5

44

VREGENZ

VDDIO

42

93

43

4

40

GPIO42

GPIO46

41

94

38

3

39

GPIO8

XRSn

37

GPIO4

95

36

96

2

33

1

34

GPIO29A16,B16,C16,GPIO28

Not to scale

Only the GPIO function is shown on GPIO pins. See the Pin Attributes table for the complete, muxed signal name.

Figure 5-1. 128-pin PDT Thin Quad Flatpack (Top View)

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GPIO0

GPIO1

GPIO2

GPIO3

78

77

76

GPIO4080

79

GPIO41

GPIO23

82

81

GPIO7

GPIO22

84

83

VSS

GPIO44

86

85

VDDIO

VDD
87

GPIO5
89

88

GPIO61

GPIO9

91

90

GPIO10

GPIO5993

92

GPIO15

GPIO34

95

94

GPIO6

GPIO14

98

96

GPIO30

99

97

GPIO29GPIO31100

SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

GPIO58GPIO51

10

66

GPIO57GPIO52

11

65

GPIO56

GPIO53

12

64

GPIO32

GPIO54

13

63

GPIO35/TDI

A6,D14,E14,GPIO228

14

62

TMS

B2,C6,E12,GPIO226

15

61

GPIO37/TDO

B3,GPIO242,PGA2_INP

16

60

TCK

A2,B6,C9,GPIO224,PGA1_INP

17

59

GPIO27

A3,B9,C7,PGA1_INM

18

58

GPIO26

A14,B14,C4,PGA1_OUT

19

57

GPIO25

A11,B10,C0,PGA2_OUT

20

56

B25,D4,E4,GPIO24

B12,C2,PGA2_INM

21

55

A25,D3,E3,GPIO17

A1,B7,CMP1_DACL,D11

22

54

C24,D2,E2,GPIO16

A0,B15,C15,DACA_OUT

23

53

B24,D1,E1,GPIO33

D20,E20,VREFHI

24

52

A24,D0,E0,GPIO11

D20,E20,VREFHI

25

51

A20,B20,C20,GPIO12

A18,B18,C18,GPIO21

A19,B19,C19,GPIO13

A17,B17,C17,GPIO20

GPIO62

GPIO63VSS

GPIO60

GPIO55

C14,GPIO247

B0,C11,GPIO253

A10,B1,C10,GPIO230

B4,C8,GPIO236

A8

A9,GPIO227

A5

A4,B8

VSSA

VDDA

A7,B30,C3,D12,E30

B5,D15,E15,PGA3_OUT

B11,D16,E16,PGA3_INM

A12,C5

C1,E11,PGA3_INP

A13,B13,C13,D13,E13,VREFLO

A13,B13,C13,D13,E13,VREFLO

A.

49

67

50

9

48

GPIO18,X2

GPIO50

47

68

46

8

44

GPIO19,X1

GPIO49

45

69

42

7

43

VDDIO

GPIO48

40

70

41

6

39

VDD

GPIO47

38

71

37

5

35

VSS

VSS

36

72

33

4

34

VREGENZ

VDD

31

73

32

3

30

GPIO8

VDDIO

29

GPIO4

74

28

75

2

26

1

XRSn

27

A16,B16,C16,GPIO28

Not to scale

Only the GPIO function is shown on GPIO pins. See the Pin Attributes table for the complete, muxed signal name.

Figure 5-2. 100-Pin PZ Low-Profile Quad Flatpack (Top View)

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GPIO40

GPIO0

GPIO1

GPIO2

64

62

61

GPIO23
65

63

GPIO22

GPIO41

67

GPIO7
68

66

VSS

GPIO44

70

VDD
71

69

GPIO45

VDDIO

73

GPIO5
74

72

GPIO10

GPIO976

GPIO34
77

75

GPIO14

GPIO15

79

78

GPIO6
80

SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

GPIO30

1

60

GPIO3

GPIO31

2

59

GPIO4

GPIO29

3

58

GPIO8

A16,B16,C16,GPIO28

4

57

GPIO42

XRSn

5

56

VREGENZ

GPIO46

6

55

VSS

VDDIO

7

54

GPIO43

VDD

8

53

VDD

VSS

9

52

VDDIO

A6,D14,E14,GPIO228

1051

GPIO19,X1

B2,C6,E12,GPIO226

11

50

GPIO18,X2

A3,B3,C5,GPIO242,PGA2_INP

1249

GPIO32

A2,B6,C9,GPIO224,PGA1_INP

13

48

GPIO35/TDI

A15,B9,C7,PGA1_INM

14

47

TMS

A14,B14,C4,PGA1_OUT

15

46

GPIO37/TDO

A11,B10,C0,PGA2_OUT

16

45

TCK

40
A25,D3,E3,GPIO17

39
C24,D2,E2,GPIO16

38

37
A24,D0,E0,GPIO11

B24,D1,E1,GPIO33

36
A20,B20,C20,GPIO12

35

34
A18,B18,C18,GPIO21

A19,B19,C19,GPIO13

31

33
A17,B17,C17,GPIO20

GPIO63

GPIO62VSS

A10,B1,C10,GPIO230

A9,B4,C8,GPIO227,GPIO236

A4,B8,C14

VSSA

VDDA

A8,B0,C11,PGA3_OUT

A12,C1,E11,PGA3_INP

A7,B30,C3,D12,E30,PGA3_INM

A13,B13,C13,D13,E13,VREFLO

A.

32

B25,D4,E4,GPIO24

30

41
28

20
29

GPIO25

D20,E20,VREFHI

27

42

25

19

26

GPIO26

A0,B15,C15,DACA_OUT

24

GPIO27

43

22

44

18

23

17

21

A5,B12,C2,PGA2_INM
A1,B7,CMP1_DACL,D11

Not to scale

Only the GPIO function is shown on GPIO pins. See the Pin Attributes table for the complete, muxed signal name.

Figure 5-3. 80-Pin PNA Thin Quad Flatpack (Top View)

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GPIO6

GPIO10

GPIO9

GPIO5

VDDIO

VDD

VSS

GPIO7

GPIO22

GPIO41

GPIO23

GPIO40

GPIO0

GPIO1

GPIO2

GPIO3

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

VSS

5

44

VDD

A6,D14,E14,GPIO228

6

43

VDDIO

B2,C6,E12,GPIO226

7

42

GPIO19,X1

A3,B3,C5,GPIO242,PGA2_INP

8

41

GPIO18,X2

A2,B6,C9,GPIO224,PGA1_INP

940

GPIO32

A15,B9,C7,PGA1_INM

10

39

GPIO35/TDI

A14,B14,C4,PGA1_OUT

11

38

TMS

A11,B10,C0,PGA2_OUT

12

37

GPIO37/TDO

A5,B12,C2,PGA2_INM

13

36

TCK

A1,B7,CMP1_DACL,D11

14

35

B25,D4,E4,GPIO24

A0,B15,C15,DACA_OUT

15

34

A25,D3,E3,GPIO17

D20,E20,VREFHI

16

33

C24,D2,E2,GPIO16

B24,D1,E1,GPIO33

A24,D0,E0,GPIO11

A20,B20,C20,GPIO12

A19,B19,C19,GPIO13

A18,B18,C18,GPIO21

A17,B17,C17,GPIO20

VSS

A10,B1,C10,GPIO230

A9,B4,C8,GPIO227,GPIO236

A4,B8,C14

VDDA

VSSA

A8,B0,C11,PGA3_OUT

A7,B30,C3,D12,E30,PGA3_INM

A12,C1,E11,PGA3_INP

A13,B13,C13,D13,E13,VREFLO

A.

32

VSS

31

45

30

4

29

VDD

28

VREGENZ

27

46

26

3

25

XRSn

24

GPIO8

23

47

22

2

21

A16,B16,C16,GPIO28

20

GPIO4

19

48

18

1

17

GPIO29Not to scale

Only the GPIO function is shown on GPIO pins. See the Pin Attributes table for the complete, muxed signal name.

Figure 5-4. 64-Pin PM Low-Profile Quad Flatpack (Top View)

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A.

GPIO9

GPIO5

VDDIO

VDD

GPIO7

GPIO22

GPIO41

GPIO23

GPIO40

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

56

55

54

53

52

51

50

49

48

47

46

45

44

43

SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

GPIO6

1

42

VREGENZ

GPIO292

41

VDD

A16,B16,C16,GPIO28

3

40

VDDIO

XRSn

4

39

GPIO19,X1

VDD

5

38

GPIO18,X2

A3,B3,C5,GPIO242,PGA2_INP

6

37

GPIO32

A2,B6,C9,GPIO224,PGA1_INP

7

36

GPIO35/TDI

A15,B9,C7,PGA1_INM

8

35

TMS

A14,B14,C4,PGA1_OUT

9

34

GPIO37/TDO

A11,B10,C0,PGA2_OUT

10

33

TCK

A5,B12,C2,PGA2_INM

1132

B25,D4,E4,GPIO24

A1,B7,CMP1_DACL,D11

12

31

A25,D3,E3,GPIO17

A0,B15,C15,DACA_OUT

13

30

C24,D2,E2,GPIO16

D20,E20,VREFHI

1429

B24,D1,E1,GPIO33

15

16

17

18

19

20

21

22

23

24

25

26

27

28

A13,B13,C13,D13,E13,VREFLO

A12,C1,E11,PGA3_INP

A7,B30,C3,D12,E30,PGA3_INM

A8,B0,C11,PGA3_OUT

VSSA

VDDA

A4,B8,C14

A9,B4,C8,GPIO227,GPIO236

A10,B1,C10,GPIO230

A17,B17,C17,GPIO20

A18,B18,C18,GPIO21

A19,B19,C19,GPIO13

A20,B20,C20,GPIO12

A24,D0,E0,GPIO11

VSS

Not to scale

Only the GPIO function is shown on GPIO pins. See the Pin Attributes table for the complete, muxed signal name.

Figure 5-5. 56-Pin RSH Very Thin Quad Flatpack No-Lead (Top View)

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5.2 Pin Attributes
Table 5-1. Pin Attributes
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTIONANALOG
A0I

ADC-A Input 0

B15

I

ADC-B Input 15

C15

IADC-C Input 15

I

CMPSS-3 High Comparator Positive Input 2

CMP3_LP2ICMPSS-3 Low Comparator Positive Input 2

DACA_OUTO

Buffered DAC-A Output.

I

Analog Pin Used For Digital Input 231

A1

I

ADC-A Input 1

B7

I

ADC-B Input 7

CMP1_DACLICMPSS-1 Low DAC Output

I

CMPSS-1 High Comparator Positive Input 4

CMP1_LP4I

CMPSS-1 Low Comparator Positive Input 4

D11

I

ADC-D Input 11

I

Analog Pin Used For Digital Input 232

A2

I

ADC-A Input 2

B6

I

ADC-B Input 6

C9I

ADC-C Input 9

I

CMPSS-1 High Comparator Positive Input 0

I

CMPSS-1 Low Comparator Positive Input 0

GPIO224

I/O

General-Purpose Input Output 224 This pin also has
digital mux functions which are described in the GPIO
section of this table.

PGA1_INPI

PGA-1 Plus

A3I

ADC-A Input 3

CMP3_HP5I

CMPSS-3 High Comparator Positive Input 5

I

CMPSS-3 Low Comparator Positive Input 5

I

Analog Pin Used For Digital Input 229

I

ADC-A Input 3

I

CMPSS-3 High Comparator Positive Input 5

CMP3_LP5I

CMPSS-3 Low Comparator Positive Input 5

A4I

ADC-A Input 4

B8I

ADC-B Input 8

I

CMPSS-2 High Comparator Positive Input 0

I

CMPSS-2 Low Comparator Positive Input 0

CMP3_HP2

AIO231

30

19

15

13

0, 4, 8, 12

CMP1_HP4

AIO232

23

29

22

18

14

12

0, 4, 8, 12

CMP1_HP021

CMP1_LP0

13

9

7

18

CMP3_LP5
AIO22917

0, 4, 8, 12

A3
CMP3_HP52042

CMP2_HP0

12

36

27

8

23

6

21

CMP2_LP0
AIO225

I

Analog Pin Used For Digital Input 225

A5

0, 4, 8, 12

I

ADC-A Input 5

CMP2_HP5I

CMPSS-2 High Comparator Positive Input 5

I

CMPSS-2 Low Comparator Positive Input 5

I

Analog Pin Used For Digital Input 249

I

ADC-A Input 5

I

CMPSS-2 High Comparator Positive Input 5

I

CMPSS-2 Low Comparator Positive Input 5

35

CMP2_LP5
AIO2490, 4, 8, 12

A528

CMP2_HP5
CMP2_LP5

17

13

11

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Table 5-1. Pin Attributes (continued)
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTION

A6I

ADC-A Input 6

CMP1_HP2I

CMPSS-1 High Comparator Positive Input 2

CMP1_LP2ICMPSS-1 Low Comparator Positive Input 2

D14

I

ADC-D Input 14

E14

I

ADC-E Input 14

GPIO228

I/O

General-Purpose Input Output 228 This pin also has
digital mux functions which are described in the GPIO
section of this table.

A7

I

ADC-A Input 7

B30

I

ADC-B Input 30

C3

I

ADC-C Input 3

CMP4_HN1ICMPSS-4 High Comparator Negative Input 1

CMP4_HP1I

CMPSS-4 High Comparator Positive Input 1

I

CMPSS-4 Low Comparator Negative Input 1

CMP4_LP1ICMPSS-4 Low Comparator Positive Input 1

D12

I

ADC-D Input 12

E30

IADC-E Input 30

I

Analog Pin Used For Digital Input 245

A8I

ADC-A Input 8

CMP4_HP4I

CMPSS-4 High Comparator Positive Input 4

I

CMPSS-4 Low Comparator Positive Input 4

I

Analog Pin Used For Digital Input 240

A8I

ADC-A Input 8

B0I

ADC-B Input 0

I

ADC-C Input 11

I

CMPSS-4 High Comparator Positive Input 4

I

CMPSS-4 Low Comparator Positive Input 4

I

Analog Pin Used For Digital Input 241

A9I

ADC-A Input 9

CMP2_HP2I

CMPSS-2 High Comparator Positive Input 2

CMP2_LP2ICMPSS-2 Low Comparator Positive Input 2

GPIO227

I/O

General-Purpose Input Output 227 This pin also has
digital mux functions which are described in the GPIO
section of this table.

A10

I

ADC-A Input 10

B1

I

ADC-B Input 1

C10I

ADC-C Input 10

CMP2_HN0I

CMPSS-2 High Comparator Negative Input 0

CMP2_HP3I

CMPSS-2 High Comparator Positive Input 3

CMP2_LN0I

CMPSS-2 Low Comparator Negative Input 0

CMP2_LP3I

CMPSS-2 Low Comparator Positive Input 3

GPIO230

I/O

General-Purpose Input Output 230 This pin also has
digital mux functions which are described in the GPIO
section of this table.

18

37

CMP4_LN1

AIO245

31

10

23

6

19

17

0, 4, 8, 12

37

CMP4_LP4
AIO24014

0, 4, 8, 12

C11

39

CMP4_HP4

24

20

18

CMP4_LP4
AIO241

16

0, 4, 8, 12

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50

38

40

28

29

24

25

22

23

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTION

A11I

ADC-A Input 11

B10

I

ADC-B Input 10

C0

I

ADC-C Input 0

CMP1_HN1ICMPSS-1 High Comparator Negative Input 1

I

CMPSS-1 High Comparator Positive Input 1

I

CMPSS-1 Low Comparator Negative Input 1

CMP1_LP1ICMPSS-1 Low Comparator Positive Input 1

PGA2_OUTO

PGA-2 Output

I

Analog Pin Used For Digital Input 237

A12

I

ADC-A Input 12

CMP2_HN1ICMPSS-2 High Comparator Negative Input 1

CMP2_HP1I

CMPSS-2 High Comparator Positive Input 1

I

CMPSS-2 Low Comparator Negative Input 1

I

CMPSS-2 Low Comparator Positive Input 1

I

Analog Pin Used For Digital Input 238

A13

I

ADC-A Input 13

B13

I

ADC-B Input 13

C13

I

ADC-C Input 13

I

ADC-D Input 13

E13

I

ADC-E Input 13

VREFLO(1)I

ADC Low Reference

I

Analog Pin Used For Digital Input 235

A13

I

ADC-A Input 13

B13

I

ADC-B Input 13

I

ADC-C Input 13

I

ADC-D Input 13

E13

I

ADC-E Input 13

VREFLO(1)I

ADC Low Reference

I

Analog Pin Used For Digital Input 235

A14

I

ADC-A Input 14

B14

I

ADC-B Input 14

C4

I

ADC-C Input 4

I

CMPSS-3 High Comparator Positive Input 4

CMP3_LP4I

CMPSS-3 Low Comparator Positive Input 4

PGA1_OUTO

PGA-1 Output

I

Analog Pin Used For Digital Input 239

A15

I

ADC-A Input 15

CMP1_HN0I

CMPSS-1 High Comparator Negative Input 0

CMP1_HP3I

CMPSS-1 High Comparator Positive Input 3

I

CMPSS-1 Low Comparator Negative Input 0

I

CMPSS-1 Low Comparator Positive Input 3

I

Analog Pin Used For Digital Input 233

A16

I

ADC-A Input 16

B16

I

ADC-B Input 16

I

ADC-C Input 16

I/O

General-Purpose Input Output 28 This pin also has
digital mux functions which are described in the GPIO
section of this table.

CMP1_HP1

27

20

16

12

10

CMP1_LN1

AIO2370, 4, 8, 12

35

CMP2_LN1

28

22

18

16

CMP2_LP1
AIO2380, 4, 8, 12

D13

AIO235

34

26

21

17

15

0, 4, 8, 12

C13
D13

AIO23533, 34

21

17

15

ALT

CMP3_HP4

AIO23926, 27

26

19

15

11

9

0, 4, 8, 12

22

CMP1_LN0

14

10

8

CMP1_LP3
AIO2330, 4, 8, 12

C162

GPIO281

4

2

3

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTION

A17

I

ADC-A Input 17

B17

I

ADC-B Input 17

C17

I

ADC-C Input 17

GPIO20I/O

General-Purpose Input Output 20 This pin also has
digital mux functions which are described in the GPIO
section of this table.

A18

I

ADC-A Input 18

B18

I

ADC-B Input 18

I

ADC-C Input 18

GPIO21

I/O

General-Purpose Input Output 21 This pin also has
digital mux functions which are described in the GPIO
section of this table.

A19

I

ADC-A Input 19

B19

I

ADC-B Input 19

I

ADC-C Input 19

GPIO13

I/O

General-Purpose Input Output 13 This pin also has
digital mux functions which are described in the GPIO
section of this table.

A20

I

ADC-A Input 20

B20

I

ADC-B Input 20

C20

IADC-C Input 20

GPIO12

I/O

General-Purpose Input Output 12 This pin also has
digital mux functions which are described in the GPIO
section of this table.

A24

I

ADC-A Input 24

D0

I

ADC-D Input 0I

ADC-E Input 0

GPIO11

I/O

General-Purpose Input Output 11 This pin also has
digital mux functions which are described in the GPIO
section of this table.

A25

I

ADC-A Input 25

D3

I

ADC-D Input 3

I

ADC-E Input 3

GPIO17

I/O

General-Purpose Input Output 17 This pin also has
digital mux functions which are described in the GPIO
section of this table.

A26

I

ADC-A Input 26

D6

I

ADC-D Input 6

I

ADC-E Input 6

IAnalog Pin Used For Digital Input 209

A27

I

ADC-A Input 27

AIO227

I

Analog Pin Used For Digital Input 227

I

ADC-D Input 9

E9I

ADC-E Input 9

A28

I

ADC-A Input 28

AIO243

I

Analog Pin Used For Digital Input 243

I

ADC-D Input 19

E19

I

ADC-E Input 19

B0

I

ADC-B Input 0

C11I

ADC-C Input 11

CMP2_HP3I

CMPSS-2 High Comparator Positive Input 3

I

CMPSS-2 Low Comparator Positive Input 3

I/O

General-Purpose Input Output 231 This pin also has
digital mux functions which are described in the GPIO
section of this table.

60

C18

61

C19

62

63

E0

64

E3

67

49

50

51

52

55

24

E6
AIO2090, 4, 8, 12

D9

D19

CMP2_LP3
GPIO23118

48

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47

41

33

34

35

36

37

40

27

28

29

30

31

34

24

25

26

27

28

31

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTION

B2I

ADC-B Input 2

C6

I

ADC-C Input 6

CMP3_HP0I

CMPSS-3 High Comparator Positive Input 0

CMP3_LP0I

CMPSS-3 Low Comparator Positive Input 0

E12I

ADC-E Input 12

GPIO226

I/O

General-Purpose Input Output 226 This pin also has
digital mux functions which are described in the GPIO
section of this table.

B3

I

ADC-B Input 3

CMP3_HN0I

CMPSS-3 High Comparator Negative Input 0

CMP3_HP3I

CMPSS-3 High Comparator Positive Input 3

CMP3_LN0I

CMPSS-3 Low Comparator Negative Input 0

I

CMPSS-3 Low Comparator Positive Input 3

GPIO242

I/O

General-Purpose Input Output 242 This pin also has
digital mux functions which are described in the GPIO
section of this table.

PGA2_INPI

PGA-2 Plus

B4I

ADC-B Input 4

C8I

ADC-C Input 8

CMP4_HP0I

CMPSS-4 High Comparator Positive Input 0

I

CMPSS-4 Low Comparator Positive Input 0

I/O

General-Purpose Input Output 236 This pin also has
digital mux functions which are described in the GPIO
section of this table.

B5

I

ADC-B Input 5

CMP1_HP5I

CMPSS-1 High Comparator Positive Input 5

CMP1_LP5I

CMPSS-1 Low Comparator Positive Input 5I

ADC-D Input 15

I

ADC-E Input 15

I

Analog Pin Used For Digital Input 252

I

ADC-B Input 9

I

ADC-C Input 7

PGA1_INM

I

PGA-1 Minus

B11

I

ADC-B Input 11

CMP4_HP5I

CMPSS-4 High Comparator Positive Input 5

CMP4_LP5I

CMPSS-4 Low Comparator Positive Input 5I

ADC-D Input 16

I

ADC-E Input 16

I

Analog Pin Used For Digital Input 251

B12I

ADC-B Input 12

C2

I

ADC-C Input 2

CMP3_HN1ICMPSS-3 High Comparator Negative Input 1

CMP3_HP1I

CMPSS-3 High Comparator Positive Input 1

I

CMPSS-3 Low Comparator Negative Input 1

CMP3_LP1ICMPSS-3 Low Comparator Positive Input 1

PGA2_INM

I

PGA-2 Minus

I

Analog Pin Used For Digital Input 244

B24

I

ADC-B Input 24

D1

I

ADC-D Input 1

E1

I

ADC-E Input 1

I/O

General-Purpose Input Output 33 This pin also has
digital mux functions which are described in the GPIO
section of this table.

19

20

CMP3_LP349

CMP4_LP0
GPIO236

15

16

39

11

12

28

7

8

24

6

22

0, 4, 8, 12

38

D15

32

E15
AIO2520, 4, 8, 12

B9
C7

22

36

D16

18

14

10

8

30

E16
AIO2510, 4, 8, 12

28

CMP3_LN1

AIO244

21

17

13

11

0, 4, 8, 12

65

GPIO33

53

38

32

29

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTION

B25

I

ADC-B Input 25

D4

I

ADC-D Input 4

E4

I

ADC-E Input 4

GPIO24

I/O

General-Purpose Input Output 24 This pin also has
digital mux functions which are described in the GPIO
section of this table.

B26

I

ADC-B Input 26

D7

I

ADC-D Input 7

I

ADC-E Input 7

I

Analog Pin Used For Digital Input 210

AIO228I

Analog Pin Used For Digital Input 228

B27

I

ADC-B Input 27

I

ADC-D Input 10

E10

IADC-E Input 10

C1

I

ADC-C Input 1

CMP4_HP2I

CMPSS-4 High Comparator Positive Input 2

CMP4_LP2ICMPSS-4 Low Comparator Positive Input 2

I

ADC-E Input 11

I

PGA-3 PlusI

Analog Pin Used For Digital Input 248

I

ADC-C Input 5

C14I

ADC-C Input 14

CMP4_HN0I

CMPSS-4 High Comparator Negative Input 0

CMP4_HP3I

CMPSS-4 High Comparator Positive Input 3

I

CMPSS-4 Low Comparator Negative Input 0

CMP4_LP3I

CMPSS-4 Low Comparator Positive Input 3

GPIO247

I/O

General-Purpose Input Output 247 This pin also has
digital mux functions which are described in the GPIO
section of this table.

C14

I

ADC-C Input 14

CMP4_HN0I

CMPSS-4 High Comparator Negative Input 0

68

56

41

35

32

25

E7
AIO2100, 4, 8, 12

45

D10

35

E11

29

22

18

16

PGA3_INP
AIO2480, 4, 8, 12

C520

CMP4_LN0

28

12

8

6

42

CMP4_HP3I

CMPSS-4 High Comparator Positive Input 3

CMP4_LN042

I

CMPSS-4 Low Comparator Negative Input 0

CMP4_LP3I

CMPSS-4 Low Comparator Positive Input 3

C24

I

ADC-C Input 24

D2

I

ADC-D Input 2

E2

I

ADC-E Input 2

GPIO16

I/O

General-Purpose Input Output 16 This pin also has
digital mux functions which are described in the GPIO
section of this table.

AIO253

I

Analog Pin Used For Digital Input 253

C25

I

ADC-C Input 25

I

ADC-D Input 5

I

ADC-E Input 5

I

Analog Pin Used For Digital Input 208

AIO226

I

Analog Pin Used For Digital Input 226

C26

I

ADC-C Input 26

I

ADC-D Input 8

I

ADC-E Input 8

66

23

D5
E5
AIO2080, 4, 8, 12

43

D8
E8

20

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27

54

39

23

33

21

30

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTION

AIO242

I

Analog Pin Used For Digital Input 242

C27

I

ADC-C Input 27

I

ADC-D Input 18

E18

I

ADC-E Input 18

D20

I

ADC-D Input 20

E20

I

ADC-E Input 20

I

ADC High Reference. In external reference mode,
externally drive the high reference voltage onto thispin. In internal reference mode, a voltage is driven
onto this pin by the device. In either mode, place atleast a 2.2-µF capacitor on this pin. This capacitor
should be placed as close to the device as possible
between the VREFHI and VREFLO pins.

I

Analog Pin Used For Digital Input 234

D20I

ADC-D Input 20

E20

I

ADC-E Input 20

I

ADC High Reference. In external reference mode,
externally drive the high reference voltage onto thispin. In internal reference mode, a voltage is driven
onto this pin by the device. In either mode, place atleast a 2.2-µF capacitor on this pin. This capacitor
should be placed as close to the device as possible
between the VREFHI and VREFLO pins.

I

Analog Pin Used For Digital Input 234

46

D18

31

VREFHI(2)AIO23420

16

14

0, 4, 8, 12

32

VREFHI(2)AIO234

24

25

20

16

14

ALT

PGA3_INM

36

30

23

19

17

I

PGA-3 Minus

PGA3_OUT

38

32

24

20

18

O

PGA-3 Output

I/O

General-Purpose Input Output 236 This pin also has
analog functions which are described in the ANALOG
section of this table.

O

ePWM-7 Output A

GPIO
GPIO2360, 4, 8, 12

EPWM7_A1

EQEP1_INDEX

5I/O

eQEP-1 Index

EPWM12_A

9O

ePWM-12 Output A

0, 4, 8, 12

I/O

General-Purpose Input Output 0

EPWM1_A

1O

ePWM-1 Output A

OUTPUTXBAR7

3

O

Output X-BAR Output 7

SCIA_RX5I

SCI-A Receive Data

I2CA_SDA

6

I/OD

I2C-A Open-Drain Bidirectional Data

SPIA_PTE

7

I/O

SPI-A Peripheral Transmit Enable (PTE)FSIRXA_CLK9IFSIRX-A Input ClockMCANA_RX10I

CAN/CAN FD Receive

CLB_OUTPUTXBAR811OCLB Output X-BAR Output 8

EQEP1_INDEX

13

I/O

eQEP-1 Index

EPWM3_A15

O

ePWM-3 Output A

0, 4, 8, 12

I/O

General-Purpose Input Output 1

EPWM1_B

1O

ePWM-1 Output B

SCIA_TX

5O

SCI-A Transmit Data

I2CA_SCL

6

I/OD

I2C-A Open-Drain Bidirectional Clock

SPIA_POCI7

I/O

SPI-A Peripheral Out, Controller In (POCI)

GPIO0

GPIO1

49

100

99

39

79

78

28

63

62

24

52

51

22

47

46

EQEP1_STROBE

9I/O

eQEP-1 Strobe

MCANA_TX

10O

CAN/CAN FD Transmit

CLB_OUTPUTXBAR7

11OCLB Output X-BAR Output 7

EPWM10_B

13

O

ePWM-10 Output B

EPWM3_B

15

O

ePWM-3 Output B

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAMEGPIO2

MUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTION

0, 4, 8, 12

I/O

General-Purpose Input Output 2

EPWM2_A

1O

ePWM-2 Output A

OUTPUTXBAR1

5

O

Output X-BAR Output 1

PMBUSA_SDA

6

I/OD

PMBus-A Open-Drain Bidirectional Data

SPIA_PICO

7

I/O

SPI-A Peripheral In, Controller Out (PICO)SCIA_TX

9O

SCI-A Transmit Data

FSIRXA_D1

10IFSIRX-A Optional Additional Data Input

I2CB_SDA

11

I/OD

I2C-B Open-Drain Bidirectional Data

EPWM10_A

13

O

ePWM-10 Output A

MCANB_TX

14O

CAN/CAN FD Transmit

EPWM4_A15

O

ePWM-4 Output A

0, 4, 8, 12

I/O

General-Purpose Input Output 3

EPWM2_B

1O

ePWM-2 Output B

OUTPUTXBAR2

2, 5

O

Output X-BAR Output 2

PMBUSA_SCL

6

I/OD

PMBus-A Open-Drain Bidirectional Clock

SPIA_CLK

7

I/O

SPI-A Clock

SCIA_RX9I

SCI-A Receive Data

FSIRXA_D0

10IFSIRX-A Primary Data Input

I2CB_SCL11

I/OD

MCANB_RX14

I

CAN/CAN FD Receive

EPWM4_B

15

O

ePWM-4 Output B

0, 4, 8, 12

I/O

General-Purpose Input Output 4

EPWM3_A

1O

ePWM-3 Output A

I2CA_SCL

2I/OD

I2C-A Open-Drain Bidirectional ClockMCANA_TX

3O

CAN/CAN FD Transmit

OUTPUTXBAR3

5

O

Output X-BAR Output 3

SPIB_CLK

7

I/O

SPI-B Clock

EQEP2_STROBE

9I/O

eQEP-2 Strobe

FSIRXA_CLK10IFSIRX-A Input Clock

CLB_OUTPUTXBAR6

11OCLB Output X-BAR Output 6

EPWM11_B

13

O

ePWM-11 Output B

SPIA_POCI14

I/O

SPI-A Peripheral Out, Controller In (POCI)EPWM1_A15

O

ePWM-1 Output A

0, 4, 8, 12

I/O

General-Purpose Input Output 5

GPIO3

GPIO4

GPIO5

98

97

96

77

76

75

61

60

59

50

49

48

45

44

43

I2C-B Open-Drain Bidirectional Clock

EPWM3_B

1O

ePWM-3 Output B

I2CA_SDA

2

I/OD

I2C-A Open-Drain Bidirectional Data

OUTPUTXBAR3

3

O

Output X-BAR Output 3

MCANA_RX5I

CAN/CAN FD Receive

SPIA_PTE

7

I/O

SPI-A Peripheral Transmit Enable (PTE)FSITXA_D1

9O

FSITX-A Optional Additional Data Output

CLB_OUTPUTXBAR510OCLB Output X-BAR Output 5

SCIA_RX11

I

SCI-A Receive Data

EPWM1_B

15

O

ePWM-1 Output B

22

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118

89

74

61

55

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAMEGPIO6

MUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTION

0, 4, 8, 12

I/O

General-Purpose Input Output 6

EPWM4_A

1O

ePWM-4 Output A

OUTPUTXBAR4

2

O

Output X-BAR Output 4

SYNCOUT

3

O

External ePWM Synchronization Pulse

EQEP1_A5

I

eQEP-1 Input A

SPIB_POCI7

I/O

SPI-B Peripheral Out, Controller In (POCI)

126

97

80

64

1

FSITXA_D0

9O

FSITX-A Primary Data Output

FSITXA_D1

11

O

FSITX-A Optional Additional Data Output

CLB_OUTPUTXBAR814OCLB Output X-BAR Output 8

EPWM2_A15

O

ePWM-2 Output A

0, 4, 8, 12

I/O

General-Purpose Input Output 7

EPWM4_B

1O

ePWM-4 Output B

EPWM2_A2

O

ePWM-2 Output A

OUTPUTXBAR5

3

O

Output X-BAR Output 5

EQEP1_B

5

I

eQEP-1 Input B

SPIB_PICO

7

I/O

SPI-B Peripheral In, Controller Out (PICO)FSITXA_CLK

9OFSITX-A Output Clock

CLB_OUTPUTXBAR210OCLB Output X-BAR Output 2

SCIA_TX

11O

SCI-A Transmit Data

MCANA_TX

14O

CAN/CAN FD Transmit

EPWM2_B

15

O

ePWM-2 Output B

0, 4, 8, 12

I/O

General-Purpose Input Output 8

EPWM5_A

1O

ePWM-5 Output A

ADCSOCAO3O

ADC Start of Conversion A for External ADC

EQEP1_STROBE

5

I/O

eQEP-1 Strobe

SCIA_TX

6O

SCI-A Transmit Data

SPIA_PICO

7

I/O

SPI-A Peripheral In, Controller Out (PICO)

I2CA_SCL

9I/OD

I2C-A Open-Drain Bidirectional ClockFSITXA_D1

10O

FSITX-A Optional Additional Data Output

CLB_OUTPUTXBAR5

11OCLB Output X-BAR Output 5

EPWM11_A

13

O

ePWM-11 Output A

0, 4, 8, 12

I/O

General-Purpose Input Output 9

EPWM5_B

1O

ePWM-5 Output B

SCIB_TX

2O

SCI-B Transmit Data

OUTPUTXBAR6

3

O

Output X-BAR Output 6

EQEP1_INDEX

5I/O

eQEP-1 Index

SCIA_RX6I

SCI-A Receive Data

SPIA_CLK

7

I/O

SPI-A Clock

I2CA_SCL

9I/OD

I2C-A Open-Drain Bidirectional ClockFSITXA_D0

10OFSITX-A Primary Data Output

LINA_RX11I

LIN-A Receive

PMBUSA_SCL

13

I/OD

PMBus-A Open-Drain Bidirectional Clock

I2CB_SCL

14

I/OD

I2C-B Open-Drain Bidirectional Clock

EQEP3_B

15

I

GPIO7

GPIO8

GPIO9

105

95

119

84

74

90

68

58

75

57

52

47

62

56

eQEP-3 Input B

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTIONGPIO100, 4, 8, 12

I/O

General-Purpose Input Output 10

EPWM6_A

1O

ePWM-6 Output A

ADCSOCBO3O

ADC Start of Conversion B for External ADC

EQEP1_A5

I

eQEP-1 Input A

SCIB_TX

6O

SCI-B Transmit Data

SPIA_POCI7

I/O

SPI-A Peripheral Out, Controller In (POCI)

122

93

76

63

I2CA_SDA

9

I/OD

I2C-A Open-Drain Bidirectional Data

FSITXA_CLK

10OFSITX-A Output Clock

LINA_TX

11O

LIN-A Transmit

EQEP3_STROBE

13

I/O

eQEP-3 Strobe

CLB_OUTPUTXBAR415OCLB Output X-BAR Output 4

GPIO110, 4, 8, 12

I/O

General-Purpose Input Output 11 This pin also has
analog functions which are described in the ANALOG
section of this table.

EPWM6_B

1O

ePWM-6 Output B

MCANA_RX2

I

CAN/CAN FD Receive

OUTPUTXBAR7

3

O

Output X-BAR Output 7

EQEP1_B

5

I

eQEP-1 Input B

SCIB_RX

6I

SCI-B Receive Data

SPIA_PTE

7

I/O

SPI-A Peripheral Transmit Enable (PTE)FSIRXA_D1

9I

FSIRX-A Optional Additional Data Input

LINA_RX10I

LIN-A Receive

EQEP2_A11

I

eQEP-2 Input A

SPIA_PICO

13

I/O

SPI-A Peripheral In, Controller Out (PICO)

EQEP3_INDEX

15

I/O

eQEP-3 Index

GPIO120, 4, 8, 12

I/O

General-Purpose Input Output 12 This pin also has
analog functions which are described in the ANALOG
section of this table.

EPWM7_A

1O

ePWM-7 Output A

MCANA_RX3

I

CAN/CAN FD Receive

EQEP1_STROBE

5

I/O

eQEP-1 Strobe

SCIB_TX

6O

SCI-B Transmit Data

PMBUSA_CTL

7

I/O

PMBus-A Control Signal - Target Input/Controller
Output

64

63

52

51

37

36

31

30

28

27

FSIRXA_D0

9I

FSIRX-A Primary Data Input

LINA_TX

10O

LIN-A Transmit

SPIA_CLK

11

I/O

SPI-A Clock

GPIO130, 4, 8, 12

I/O

General-Purpose Input Output 13 This pin also has
analog functions which are described in the ANALOG
section of this table.

EPWM7_B

1O

ePWM-7 Output B

MCANA_TX

3O

CAN/CAN FD Transmit

EQEP1_INDEX

5I/O

eQEP-1 Index

SCIB_RX

6I

SCI-B Receive Data

PMBUSA_ALERT

7

I/OD

FSIRXA_CLK9IFSIRX-A Input Clock

LINA_RX10I

LIN-A Receive

SPIA_POCI11

I/O

SPI-A Peripheral Out, Controller In (POCI)24

Submit Document Feedback

62

50

35

29

26

PMBus-A Open-Drain Bidirectional Alert Signal

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTIONGPIO140, 4, 8, 12

I/O

General-Purpose Input Output 14

EPWM8_A

1O

ePWM-8 Output A

SCIB_TX

2O

SCI-B Transmit Data

I2CB_SDA

5

I/OD

I2C-B Open-Drain Bidirectional Data

OUTPUTXBAR3

6

O

Output X-BAR Output 3

PMBUSA_SDA

7

I/OD

PMBus-A Open-Drain Bidirectional Data

125

96

79

SPIB_CLK

9I/O

SPI-B Clock

EQEP2_A10

I

eQEP-2 Input A

LINA_TX

11O

LIN-A Transmit

EPWM3_A13

O

ePWM-3 Output A

CLB_OUTPUTXBAR714OCLB Output X-BAR Output 7

GPIO150, 4, 8, 12

I/O

General-Purpose Input Output 15

EPWM8_B

1O

ePWM-8 Output B

SCIB_RX2I

SCI-B Receive Data

I2CB_SCL

5I/OD

I2C-B Open-Drain Bidirectional ClockOUTPUTXBAR4

6

PMBUSA_SCL

7

SPIB_PTE

O

Output X-BAR Output 4

I/OD

PMBus-A Open-Drain Bidirectional Clock9

I/O

SPI-B Peripheral Transmit Enable (PTE)EQEP2_B

10

I

eQEP-2 Input B

LINA_RX11I

LIN-A Receive

EPWM3_B

13

O

ePWM-3 Output B

CLB_OUTPUTXBAR614OCLB Output X-BAR Output 6

0, 4, 8, 12

I/O

General-Purpose Input Output 16 This pin also has
analog functions which are described in the ANALOG
section of this table.

SPIA_PICO

1

I/O

SPI-A Peripheral In, Controller Out (PICO)OUTPUTXBAR7

3

O

Output X-BAR Output 7

EPWM9_A5O

ePWM-9 Output A

SCIA_TX

6O

SCI-A Transmit Data

EQEP1_STROBE

9I/O

eQEP-1 Strobe

PMBUSA_SCL

10

I/OD

PMBus-A Open-Drain Bidirectional ClockXCLKOUT

11

O

External Clock Output. This pin outputs a divideddown version of a chosen clock signal from within thedevice.

EQEP2_B

13

I

eQEP-2 Input B

SPIB_POCI14

I/O

SPI-B Peripheral Out, Controller In (POCI)

EQEP3_STROBE

15

I/O

eQEP-3 Strobe

0, 4, 8, 12

I/O

General-Purpose Input Output 17 This pin also has
analog functions which are described in the ANALOG
section of this table.

SPIA_POCI1

I/O

SPI-A Peripheral Out, Controller In (POCI)OUTPUTXBAR8

3

O

Output X-BAR Output 8

EPWM9_B

5O

ePWM-9 Output B

SCIA_RX6I

SCI-A Receive Data

GPIO16

GPIO17

124

66

67

95

54

55

78

39

40

33

34

30

31

EQEP1_INDEX

9I/O

eQEP-1 Index

PMBUSA_SDA

10

I/OD

PMBus-A Open-Drain Bidirectional Data

MCANA_TX

11O

CAN/CAN FD Transmit

EPWM6_A14

O

ePWM-6 Output A

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTIONGPIO180, 4, 8, 12

I/O

General-Purpose Input Output 18

SPIA_CLK

1

I/O

SPI-A Clock

SCIB_TX

2O

SCI-B Transmit Data

MCANB_RX3

I

CAN/CAN FD Receive

EPWM6_A5O

ePWM-6 Output A

I2CA_SCL

6

I/OD

I2C-A Open-Drain Bidirectional Clock

EQEP2_A

9

PMBUSA_CTL

I

eQEP-2 Input A

10

I/O

PMBus-A Control Signal - Target Input/Controller
OutputXCLKOUT

11

O

External Clock Output. This pin outputs a divideddown version of a chosen clock signal from within thedevice.

LINA_TX

13O

LIN-A Transmit

EQEP3_INDEX

15

I/O

eQEP-3 Index

X2

ALT

I/O

Crystal oscillator output.

GPIO190, 4, 8, 12

I/O

General-Purpose Input Output 19

SPIA_PTE

1

I/O

SPI-A Peripheral Transmit Enable (PTE)

SCIB_RX2I

SCI-B Receive Data

MCANB_TX

3O

CAN/CAN FD Transmit

EPWM6_B

5O

ePWM-6 Output B

I2CA_SDA

6

I/OD

I2C-A Open-Drain Bidirectional Data

EQEP2_B

9I

PMBUSA_ALERT10

CLB_OUTPUTXBAR1
LINA_RX

87

88

68

69

50

51

41

42

38

39

eQEP-2 Input B

I/OD

PMBus-A Open-Drain Bidirectional Alert Signal

11

O

CLB Output X-BAR Output 1

13

I

LIN-A Receive

ALT

I/O

Crystal oscillator input or single-ended clock input. The
device initialization software must configure this pin
before the crystal oscillator is enabled. To use thisoscillator, a quartz crystal circuit must be connected
to X1 and X2. This pin can also be used to feed asingle-ended 3.3-V level clock.

GPIO200, 4, 8, 12

I/O

General-Purpose Input Output 20 This pin also has
analog functions which are described in the ANALOG
section of this table.

EQEP1_A1

I

eQEP-1 Input A

EPWM12_A

5O

ePWM-12 Output A

SPIB_PICO

6

I/O

SPI-B Peripheral In, Controller Out (PICO)MCANA_TX

9O

CAN/CAN FD Transmit

ADCE_EXTMUXSEL010OADCE external mux selection pin for position 0

I2CA_SCL

11

I/OD

I2C-A Open-Drain Bidirectional Clock

SCIC_TX

15O

SCI-C Transmit Data

GPIO210, 4, 8, 12

I/O

General-Purpose Input Output 21 This pin also has
analog functions which are described in the ANALOG
section of this table.

EQEP1_B

1

I

eQEP-1 Input B

EPWM12_B

5O

ePWM-12 Output B

SPIB_POCI6

I/O

SPI-B Peripheral Out, Controller In (POCI)MCANA_RX9I

CAN/CAN FD Receive

ADCE_EXTMUXSEL1

10OADCE external mux selection pin for position 1

I2CA_SDA

11

I/OD

I2C-A Open-Drain Bidirectional Data

SCIC_RX

15

I

X1

26

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60

61

48

49

33

34

27

28

24

25

SCI-C Receive Data

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAME
GPIO22MUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTION

0, 4, 8, 12

I/O

General-Purpose Input Output 22

EQEP1_STROBE

1

I/O

eQEP-1 Strobe

SCIB_TX

3O

SCI-B Transmit Data

SPIB_CLK

6

I/O

SPI-B Clock

LINA_TX

9, 11O

LIN-A Transmit

CLB_OUTPUTXBAR110OCLB Output X-BAR Output 1

EPWM4_A14

O

ePWM-4 Output A

EQEP3_A15

I

eQEP-3 Input A

GPIO230, 4, 8, 12

I/O

General-Purpose Input Output 23

EQEP1_INDEX

1

I/O

eQEP-1 Index

SCIB_RX3I

SCI-B Receive Data

SPIB_PTE

6I/O

SPI-B Peripheral Transmit Enable (PTE)

LINA_RX

9, 11

I

LIN-A Receive

CLB_OUTPUTXBAR310OCLB Output X-BAR Output 3

EPWM12_A

13

O

ePWM-12 Output A

EPWM4_B

14

O

ePWM-4 Output B

USB0DM

ALT

O

USB-0 PHY differential data

GPIO240, 4, 8, 12

I/O

General-Purpose Input Output 24 This pin also has
analog functions which are described in the ANALOG
section of this table.

OUTPUTXBAR1

1

O

Output X-BAR Output 1

EQEP2_A2

I

eQEP-2 Input A

SPIA_PTE

3I/O

SPI-A Peripheral Transmit Enable (PTE)EPWM8_A5O

ePWM-8 Output A

104

102

68

83

81

56

67

65

41

56

54

35

51

49

32

SPIB_PICO

6

I/O

SPI-B Peripheral In, Controller Out (PICO)

LINA_TX

9O

LIN-A Transmit

PMBUSA_SCL

10

I/OD

PMBus-A Open-Drain Bidirectional Clock

SCIA_TX

11O

SCI-A Transmit Data

ERRORSTS

13

O

Error Status Output. This signal requires an external
pulldown.

EPWM9_A14

O

ePWM-9 Output A

GPIO250, 4, 8, 12

I/O

General-Purpose Input Output 25

OUTPUTXBAR2

1

O

Output X-BAR Output 2

EQEP2_B

2

I

eQEP-2 Input B

EQEP1_A

5

SPIB_POCI6FSITXA_D1

I

eQEP-1 Input A

I/O

SPI-B Peripheral Out, Controller In (POCI)9OFSITX-A Optional Additional Data Output

PMBUSA_SDA

10

I/OD

PMBus-A Open-Drain Bidirectional Data

SCIA_RX11

I

SCI-A Receive Data

EQEP3_A13

I

eQEP-3 Input A

GPIO260, 4, 8, 12

I/O

General-Purpose Input Output 26

OUTPUTXBAR3

1, 5

O

Output X-BAR Output 3

EQEP2_INDEX

2

I/O

eQEP-2 Index

SPIB_CLK

6

I/O

SPI-B ClockFSITXA_D0

9O

FSITX-A Primary Data Output

PMBUSA_CTL

10

I/O

PMBus-A Control Signal - Target Input/Controller
OutputI2CA_SDA

11

I/OD

I2C-A Open-Drain Bidirectional Data

EQEP3_B

13

I

69

70

57

58

42

43

eQEP-3 Input B

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAME
GPIO27

MUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTION

0, 4, 8, 12

I/O

General-Purpose Input Output 27

OUTPUTXBAR4

1, 5

O

Output X-BAR Output 4

EQEP2_STROBE

2

I/O

eQEP-2 Strobe

SPIB_PTE

6I/O

SPI-B Peripheral Transmit Enable (PTE)FSITXA_CLK

9OFSITX-A Output Clock

PMBUSA_ALERT

10

I/OD

PMBus-A Open-Drain Bidirectional Alert Signal

I2CA_SCL

11

I/OD

I2C-A Open-Drain Bidirectional Clock

EQEP3_STROBE

13

I/O

eQEP-3 Strobe

GPIO280, 4, 8, 12

I/O

General-Purpose Input Output 28 This pin also has
analog functions which are described in the ANALOG
section of this table.

SCIA_RX1I

SCI-A Receive Data

EPWM7_A3

O

ePWM-7 Output A

OUTPUTXBAR5

5O

Output X-BAR Output 5

EQEP1_A6

I

eQEP-1 Input A

71

2

59

1

44

4

2

3

EQEP2_STROBE

9I/O

eQEP-2 Strobe

LINA_TX

10O

LIN-A Transmit

SPIB_CLK

11

I/O

SPI-B ClockERRORSTS

13

O

Error Status Output. This signal requires an external
pulldown.

I2CB_SDA

14

I/OD

I2C-B Open-Drain Bidirectional Data

GPIO290, 4, 8, 12

I/O

General-Purpose Input Output 29

SCIA_TX

1O

SCI-A Transmit Data

EPWM7_B

3O

ePWM-7 Output B

OUTPUTXBAR6

5

O

Output X-BAR Output 6

EQEP1_B

6I

eQEP-1 Input B

EQEP2_INDEX

9I/O

eQEP-2 Index

LINA_RX10I

LIN-A Receive

SPIB_PTE

11

I/O

SPI-B Peripheral Transmit Enable (PTE)

ERRORSTS

13

O

Error Status Output. This signal requires an external
pulldown.

I2CB_SCL

14

I/OD

I2C-B Open-Drain Bidirectional ClockAUXCLKIN

ALT

I

Auxiliary Clock Input

GPIO300, 4, 8, 12

I/O

General-Purpose Input Output 30

SPIB_PICO

3

I/O

SPI-B Peripheral In, Controller Out (PICO)OUTPUTXBAR7

5

O

Output X-BAR Output 7

EQEP1_STROBE

6

I/O

eQEP-1 Strobe

FSIRXA_CLK9IFSIRX-A Input ClockMCANA_RX10I

CAN/CAN FD Receive

EPWM1_A11

O

ePWM-1 Output A

EQEP3_INDEX

13

I/O

eQEP-3 Index0, 4, 8, 12

I/O

General-Purpose Input Output 31

SPIB_POCI3

I/O

SPI-B Peripheral Out, Controller In (POCI)OUTPUTXBAR85

EQEP1_INDEX

6FSIRXA_D1

GPIO31

1

127

100

98

3

1

1

2

O

Output X-BAR Output 8

I/O

eQEP-1 Index

9

I

FSIRX-A Optional Additional Data Input

MCANA_TX

10O

CAN/CAN FD Transmit

EPWM1_B

11

O

ePWM-1 Output B

28

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128

99

2

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTIONGPIO320, 4, 8, 12

I/O

General-Purpose Input Output 32

I2CA_SDA

1

I/OD

I2C-A Open-Drain Bidirectional Data

EQEP1_INDEX

2

I/O

eQEP-1 Index

SPIB_CLK

3

I/O

SPI-B Clock

EPWM8_B

5O

ePWM-8 Output B

LINA_TX

6O

LIN-A Transmit

79

64

49

40

37

FSIRXA_D0

9I

FSIRX-A Primary Data Input

MCANB_TX

10O

CAN/CAN FD Transmit

PMBUSA_SDA

11

I/OD

PMBus-A Open-Drain Bidirectional Data

ADCSOCBO

13O

ADC Start of Conversion B for External ADC

GPIO330, 4, 8, 12

I/O

General-Purpose Input Output 33 This pin also has
analog functions which are described in the ANALOG
section of this table.

I2CA_SCL

1

I/OD

I2C-A Open-Drain Bidirectional Clock

SPIB_PTE

3I/O

SPI-B Peripheral Transmit Enable (PTE)

OUTPUTXBAR4

5

O

Output X-BAR Output 4

LINA_RX6I

LIN-A Receive

FSIRXA_CLK9IFSIRX-A Input ClockMCANB_RX10I

CAN/CAN FD Receive

EQEP2_B

11

I

eQEP-2 Input B

ADCSOCAO

13O

ADC Start of Conversion A for External ADC

SCIC_RX15

I

SCI-C Receive Data

GPIO340, 4, 8, 12

I/O

General-Purpose Input Output 34

1

O

Output X-BAR Output 1

OUTPUTXBAR1

65

123

53

94

38

32

29

77

PMBUSA_SDA

6

I/OD

PMBus-A Open-Drain Bidirectional Data

I2CB_SDA

14

I/OD

I2C-B Open-Drain Bidirectional Data

GPIO350, 4, 8, 12

I/O

General-Purpose Input Output 35

SCIA_RX1I

SCI-A Receive Data

SPIA_POCI2

I/O

SPI-A Peripheral Out, Controller In (POCI)I2CA_SDA

3

I/OD

I2C-A Open-Drain Bidirectional Data

MCANB_RX

5

I

PMBUSA_SCL

6

I/OD

LINA_RX7I

LIN-A Receive

EQEP1_A9I

eQEP-1 Input A

PMBUSA_CTL

10

I/O

PMBus-A Control Signal - Target Input/Controller
OutputEPWM5_B

11

O

ePWM-5 Output B

I

JTAG Test Data Input (TDI) - TDI is the default mux
selection for the pin. The internal pullup is disabled bydefault. The internal pullup should be enabled or an
external pullup added on the board if this pin is used
as JTAG TDI to avoid a floating input.

TDI

78

15

63

48

39

36

CAN/CAN FD Receive
PMBus-A Open-Drain Bidirectional Clock

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAME
GPIO37

MUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTION

0, 4, 8, 12

I/O

General-Purpose Input Output 37

OUTPUTXBAR2

1

O

Output X-BAR Output 2

SPIA_PTE

2

I/O

SPI-A Peripheral Transmit Enable (PTE)

I2CA_SCL

3

I/OD

I2C-A Open-Drain Bidirectional Clock

SCIA_TX

5O

SCI-A Transmit Data

MCANB_TX

6O

CAN/CAN FD Transmit

LINA_TX

7O

LIN-A Transmit

EQEP1_B

9I

eQEP-1 Input B

PMBUSA_ALERT

10

I/OD

PMBus-A Open-Drain Bidirectional Alert Signal

EPWM5_A11

O

ePWM-5 Output A

15

O

JTAG Test Data Output (TDO) - TDO is the default
mux selection for the pin. The internal pullup isdisabled by default. The TDO function will be in a tristate condition when there is no JTAG activity, leaving
this pin floating; the internal pullup should be enabledor an external pullup added on the board to avoid afloating GPIO input.

TDO

GPIO40

76

61

46

37

34

0, 4, 8, 12

I/O

General-Purpose Input Output 40

SPIB_PICO

1

I/O

SPI-B Peripheral In, Controller Out (PICO)EPWM2_B

5O

ePWM-2 Output B

PMBUSA_SDA

6

I/OD

PMBus-A Open-Drain Bidirectional Data

FSIRXA_D0

7

I

FSIRX-A Primary Data Input

SCIB_TX

9O

SCI-B Transmit Data

EQEP1_A10

I

eQEP-1 Input A

LINA_TX

11O

LIN-A Transmit

CLB_OUTPUTXBAR414OCLB Output X-BAR Output 4

EQEP3_STROBE

15

I/O

eQEP-3 Strobe

GPIO410, 4, 8, 12

I/O

General-Purpose Input Output 41

EPWM7_A

1O

ePWM-7 Output A

EPWM2_A5O

ePWM-2 Output A

PMBUSA_SCL

6

I/OD

PMBus-A Open-Drain Bidirectional Clock

FSIRXA_D1

7

I

FSIRX-A Optional Additional Data Input

SCIB_RX

9I

SCI-B Receive Data

EQEP1_B

10

I

eQEP-1 Input B

101

103

80

82

64

66

53

55

48

50

LINA_RX11I

LIN-A Receive

EPWM12_B

13

O

ePWM-12 Output B

SPIB_POCI14

I/O

SPI-B Peripheral Out, Controller In (POCI)

USB0DP

ALT

O

USB-0 PHY differential data

GPIO420, 4, 8, 12

I/O

General-Purpose Input Output 42

LINA_RX2I

LIN-A Receive

OUTPUTXBAR5

3

O

Output X-BAR Output 5

PMBUSA_CTL

5

I/O

PMBus-A Control Signal - Target Input/Controller
OutputI2CA_SDA

6

I/OD

I2C-A Open-Drain Bidirectional Data

9457

SCIC_RX7

I

SCI-C Receive Data

EQEP1_STROBE

10

I/O

eQEP-1 Strobe

CLB_OUTPUTXBAR3

11OCLB Output X-BAR Output 330

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAME
GPIO43

MUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTION

0, 4, 8, 12

I/O

General-Purpose Input Output 43

OUTPUTXBAR6

3

O

Output X-BAR Output 6

PMBUSA_ALERT

5, 9

I/OD

PMBus-A Open-Drain Bidirectional Alert Signal

I2CA_SCL

6

I/OD

I2C-A Open-Drain Bidirectional Clock

SCIC_TX

7O

SCI-C Transmit Data

EQEP1_INDEX

10

I/O

eQEP-1 Index

CLB_OUTPUTXBAR4

91

54

11

O

CLB Output X-BAR Output 4

0, 4, 8, 12

I/O

General-Purpose Input Output 44

OUTPUTXBAR7

3

O

Output X-BAR Output 7

EQEP1_A5

I

eQEP-1 Input A

PMBUSA_SDA

6

I/OD

PMBus-A Open-Drain Bidirectional Data

FSITXA_CLK

7OFSITX-A Output Clock

PMBUSA_CTL

9

I/O

PMBus-A Control Signal - Target Input/Controller
Output

CLB_OUTPUTXBAR310OCLB Output X-BAR Output 3

GPIO44

106

85

69

FSIRXA_D0

11

IFSIRX-A Primary Data Input

LINA_TX

14O

LIN-A Transmit

GPIO450, 4, 8, 12

I/O

General-Purpose Input Output 45

OUTPUTXBAR8

3

O

Output X-BAR Output 8

FSITXA_D0

7

O

FSITX-A Primary Data Output

PMBUSA_ALERT

9

I/OD

PMBus-A Open-Drain Bidirectional Alert Signal

CLB_OUTPUTXBAR410OCLB Output X-BAR Output 4

GPIO460, 4, 8, 12

I/O

General-Purpose Input Output 46

LINA_TX

3O

LIN-A Transmit

MCANA_TX

5O

CAN/CAN FD Transmit

FSITXA_D1

7

O

FSITX-A Optional Additional Data Output

PMBUSA_SDA

9

I/OD

PMBus-A Open-Drain Bidirectional Data

GPIO470, 4, 8, 12

I/O

General-Purpose Input Output 47

LINA_RX3I

LIN-A Receive

MCANA_RX5I

CAN/CAN FD Receive

CLB_OUTPUTXBAR27OCLB Output X-BAR Output 2

PMBUSA_SCL

9

I/OD

PMBus-A Open-Drain Bidirectional Clock

GPIO48

110

73

4

8

6

6

0, 4, 8, 12

I/O

General-Purpose Input Output 48

OUTPUTXBAR3

1

O

Output X-BAR Output 3

MCANA_TX

5O

CAN/CAN FD Transmit

SCIA_TX

6O

SCI-A Transmit Data

PMBUSA_SDA

9

I/OD

PMBus-A Open-Drain Bidirectional Data0, 4, 8, 12

I/O

General-Purpose Input Output 49

OUTPUTXBAR4

1

O

Output X-BAR Output 4

MCANA_RX5I

CAN/CAN FD Receive

SCIA_RX6I

SCI-A Receive Data

GPIO49

11

12

7

8

LINA_RX9I

LIN-A Receive

FSITXA_D0

14

O

FSITX-A Primary Data Output

GPIO500, 4, 8, 12

I/O

General-Purpose Input Output 50

EQEP1_A1

I

eQEP-1 Input A

MCANA_TX

5O

CAN/CAN FD Transmit

SPIB_PICO

6

I/O

SPI-B Peripheral In, Controller Out (PICO)I2CB_SDA

9

I/OD

I2C-B Open-Drain Bidirectional Data

FSITXA_D1

14O

FSITX-A Optional Additional Data Output

13

9

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Table 5-1. Pin Attributes (continued)
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTIONGPIO510, 4, 8, 12

I/O

General-Purpose Input Output 51

EQEP1_B

1

I

eQEP-1 Input B

MCANA_RX5I

CAN/CAN FD Receive

SPIB_POCI6

I/O

SPI-B Peripheral Out, Controller In (POCI)I2CB_SCL

9

I/OD

I2C-B Open-Drain Bidirectional ClockFSITXA_CLK

14OFSITX-A Output Clock

GPIO5214

10

0, 4, 8, 12

I/O

General-Purpose Input Output 52

EQEP1_STROBE

1

I/O

eQEP-1 Strobe

CLB_OUTPUTXBAR55O

CLB Output X-BAR Output 5

SPIB_CLK

6

I/O

SPI-B ClockSYNCOUT

9O

External ePWM Synchronization Pulse

FSIRXA_D0

14

I

FSIRX-A Primary Data Input

0, 4, 8, 12

I/O

General-Purpose Input Output 53

EQEP1_INDEX

1

I/O

eQEP-1 Index

CLB_OUTPUTXBAR6

5

SPIB_PTE

6

ADCSOCAO

GPIO5315

11O

CLB Output X-BAR Output 6

I/O

SPI-B Peripheral Transmit Enable (PTE)9O

ADC Start of Conversion A for External ADC

MCANB_RX10I

CAN/CAN FD Receive

FSIRXA_D1

14I

FSIRX-A Optional Additional Data Input

0, 4, 8, 12

I/O

General-Purpose Input Output 54

SPIA_PICO

1

I/O

SPI-A Peripheral In, Controller Out (PICO)

EQEP2_A5

I

eQEP-2 Input A

OUTPUTXBAR2

6

O

Output X-BAR Output 2

ADCSOCBO

9O

ADC Start of Conversion B for External ADC

LINA_TX

10O

LIN-A Transmit

FSIRXA_CLK14IFSIRX-A Input Clock0, 4, 8, 12

I/O

General-Purpose Input Output 55

SPIA_POCI1

I/O

SPI-A Peripheral Out, Controller In (POCI)EQEP2_B

5

I

eQEP-2 Input B

OUTPUTXBAR3

6

O

Output X-BAR Output 3

ERRORSTS

9O

Error Status Output. This signal requires an external
pulldown.

LINA_RX10I

LIN-A Receive

GPIO560, 4, 8, 12

I/O

General-Purpose Input Output 56

SPIA_CLK

1

I/O

SPI-A Clock

CLB_OUTPUTXBAR72OCLB Output X-BAR Output 7

MCANA_TX

3O

CAN/CAN FD Transmit

EQEP2_STROBE

5

I/O

eQEP-2 Strobe

SCIB_TX

6O

SCI-B Transmit Data

SPIB_PICO

9

I/O

SPI-B Peripheral In, Controller Out (PICO)

I2CA_SDA

10

I/OD

I2C-A Open-Drain Bidirectional Data

EQEP1_A11

I

eQEP-1 Input A

FSIRXA_D1

14I

FSIRX-A Optional Additional Data Input

GPIO54

GPIO5532

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17

51

80

12

13

43

65

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTIONGPIO570, 4, 8, 12

I/O

General-Purpose Input Output 57

SPIA_PTE

1

I/O

SPI-A Peripheral Transmit Enable (PTE)

CLB_OUTPUTXBAR82OCLB Output X-BAR Output 8

MCANA_RX3

I

CAN/CAN FD Receive

EQEP2_INDEX

5I/O

eQEP-2 Index

SCIB_RX

6I

SCI-B Receive Data

81

66

SPIB_POCI9I/O

SPI-B Peripheral Out, Controller In (POCI)I2CA_SCL

10I/OD

I2C-A Open-Drain Bidirectional Clock

EQEP1_B

11

I

eQEP-1 Input B

FSIRXA_CLK14IFSIRX-A Input Clock0, 4, 8, 12

I/O

General-Purpose Input Output 58

OUTPUTXBAR1

5

O

Output X-BAR Output 1

SPIB_CLK

6

I/O

SPI-B Clock

LINA_TX

9O

LIN-A Transmit

MCANB_TX

10O

CAN/CAN FD Transmit

EQEP1_STROBE

11

I/O

eQEP-1 Strobe

FSIRXA_D0

14

I

FSIRX-A Primary Data Input

0, 4, 8, 12

I/O

General-Purpose Input Output 59

OUTPUTXBAR2

5

O

Output X-BAR Output 2

SPIB_PTE

6I/O

SPI-B Peripheral Transmit Enable (PTE)

LINA_RX9I

LIN-A Receive

MCANB_RX10I

CAN/CAN FD Receive

EQEP1_INDEX

11

I/O

eQEP-1 Index0, 4, 8, 12

I/O

General-Purpose Input Output 60

O

ePWM-12 Output B

O

CAN/CAN FD Transmit

GPIO58GPIO59GPIO60

82

121

67

92

EPWM12_B

1

MCANA_TX

3

OUTPUTXBAR3

5

O

Output X-BAR Output 3

SPIB_PICO

6

I/O

SPI-B Peripheral In, Controller Out (PICO)

0, 4, 8, 12

I/O

General-Purpose Input Output 61

MCANA_RX3

I

CAN/CAN FD Receive

OUTPUTXBAR4

5

O

Output X-BAR Output 4

SPIB_POCI6

I/O

SPI-B Peripheral Out, Controller In (POCI)MCANB_RX14

I

CAN/CAN FD Receive

GPIO61

GPIO62

52

120

44

91

0, 4, 8, 12

I/O

General-Purpose Input Output 62

EPWM10_A

1

O

ePWM-10 Output A

OUTPUTXBAR3

2

O

Output X-BAR Output 3

MCANA_TX

5O

CAN/CAN FD Transmit

SCIA_TX

6O

SCI-A Transmit Data

PMBUSA_SDA

9

I/OD

PMBus-A Open-Drain Bidirectional Data0, 4, 8, 12

I/O

General-Purpose Input Output 63

EPWM10_B

1O

ePWM-10 Output B

OUTPUTXBAR4

2

O

Output X-BAR Output 4

MCANA_RX5I

CAN/CAN FD Receive

SCIA_RX6I

SCI-A Receive Data

LINA_RX9I

LIN-A Receive

GPIO63

58

59

46

47

31

32

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTIONGPIO640, 4, 8, 12

I/O

General-Purpose Input Output 64

SCIA_RX1I

SCI-A Receive Data

EPWM11_A

2O

ePWM-11 Output A

EPWM7_A3

O

ePWM-7 Output A

OUTPUTXBAR5

5O

Output X-BAR Output 5

EQEP1_A6

I

eQEP-1 Input A

56

EQEP2_STROBE

9I/O

eQEP-2 Strobe

LINA_TX

10O

LIN-A Transmit

SPIB_CLK

11

I/O

SPI-B ClockERRORSTS

13

O

Error Status Output. This signal requires an external
pulldown.

I2CB_SDA

14

I/OD

I2C-B Open-Drain Bidirectional Data

GPIO650, 4, 8, 12

I/O

General-Purpose Input Output 65

EQEP1_A1

I

eQEP-1 Input A

EPWM11_B

2O

ePWM-11 Output B

SPIB_PICO

6

I/O

SPI-B Peripheral In, Controller Out (PICO)MCANA_TX

9O

CAN/CAN FD Transmit

I2CA_SCL

11

I/OD

I2C-A Open-Drain Bidirectional Clock

GPIO660, 4, 8, 12

I/O

General-Purpose Input Output 66

EQEP1_B

1

I

eQEP-1 Input B

EPWM12_A

2O

ePWM-12 Output A

SPIB_POCI6

I/O

SPI-B Peripheral Out, Controller In (POCI)MCANA_RX9I

CAN/CAN FD Receive

I2CA_SDA

11

I/OD

I2C-A Open-Drain Bidirectional Data

GPIO670, 4, 8, 12

I/O

General-Purpose Input Output 67

EPWM7_B

1O

ePWM-7 Output B

EPWM12_B

2O

ePWM-12 Output B

MCANA_TX

3O

CAN/CAN FD Transmit

EQEP1_INDEX

5I/O

eQEP-1 Index

SCIB_RX

6I

SCI-B Receive Data

PMBUSA_ALERT

7

I/OD

FSIRXA_CLK9IFSIRX-A Input Clock

LINA_RX10I

LIN-A Receive

SPIA_POCI11

I/O

SPI-A Peripheral Out, Controller In (POCI)

57

9

10

PMBus-A Open-Drain Bidirectional Alert Signal

SCIC_RX15

I

SCI-C Receive Data

GPIO680, 4, 8, 12

I/O

General-Purpose Input Output 68

EPWM7_A

1O

ePWM-7 Output A

EPWM3_A2

O

ePWM-3 Output A

MCANA_RX3

I

CAN/CAN FD Receive

EQEP1_STROBE

5

I/O

eQEP-1 Strobe

SCIB_TX

6O

SCI-B Transmit Data

PMBUSA_CTL

7

I/O

PMBus-A Control Signal - Target Input/Controller
Output72

FSIRXA_D0

9I

FSIRX-A Primary Data Input

LINA_TX

10O

LIN-A Transmit

SPIA_CLK

11

I/O

SPI-A Clock

SCIC_TX

15O

SCI-C Transmit Data

34

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTIONGPIO690, 4, 8, 12

I/O

General-Purpose Input Output 69

EPWM6_B

1O

ePWM-6 Output B

EPWM3_B

2O

ePWM-3 Output B

OUTPUTXBAR7

3

O

Output X-BAR Output 7

EQEP1_B

5

I

eQEP-1 Input B

SCIB_RX

6I

SCI-B Receive Data

SPIA_PTE

7

I/O

SPI-A Peripheral Transmit Enable (PTE)FSIRXA_D1

9I

FSIRX-A Optional Additional Data Input

LINA_RX10I

LIN-A Receive

EQEP2_A11

I

eQEP-2 Input A

SPIA_PICO

13

I/O

SPI-A Peripheral In, Controller Out (PICO)

EQEP3_INDEX

15

I/O

eQEP-3 Index

GPIO700, 4, 8, 12

I/O

General-Purpose Input Output 70

I2CA_SCL

1

I/OD

I2C-A Open-Drain Bidirectional Clock

SPIB_PTE

3I/O

SPI-B Peripheral Transmit Enable (PTE)

OUTPUTXBAR4

5

O

Output X-BAR Output 4

LINA_RX6I

LIN-A Receive

FSIRXA_CLK9IFSIRX-A Input ClockMCANA_RX10I

CAN/CAN FD Receive

EQEP2_B

11

I

eQEP-2 Input B

ADCSOCAO

13O

ADC Start of Conversion A for External ADC

EQEP3_A15

I

eQEP-3 Input A

GPIO710, 4, 8, 12

I/O

General-Purpose Input Output 71

SPIA_PICO

1

I/O

SPI-A Peripheral In, Controller Out (PICO)EPWM4_B

2O

ePWM-4 Output B

OUTPUTXBAR7

3

O

Output X-BAR Output 7

EPWM9_A5O

ePWM-9 Output A

SCIA_TX

6O

SCI-A Transmit Data

EQEP1_STROBE

9I/O

eQEP-1 Strobe

PMBUSA_SCL

10

I/OD

PMBus-A Open-Drain Bidirectional ClockXCLKOUT

11

O

External Clock Output. This pin outputs a divideddown version of a chosen clock signal from within thedevice.

EQEP2_INDEX

13

I/O

eQEP-2 Index

SPIB_POCI14

I/O

SPI-B Peripheral Out, Controller In (POCI)

EQEP3_STROBE

15

I/O

eQEP-3 Strobe

0, 4, 8, 12

I/O

General-Purpose Input Output 72

SPIA_POCI1

I/O

SPI-A Peripheral Out, Controller In (POCI)EPWM5_A2

O

ePWM-5 Output A

OUTPUTXBAR8

3

O

Output X-BAR Output 8

EPWM9_B

5O

ePWM-9 Output B

SCIA_RX6I

SCI-A Receive Data

EQEP1_INDEX

9I/O

eQEP-1 Index

PMBUSA_SDA

10

I/OD

PMBus-A Open-Drain Bidirectional Data

MCANA_TX

11O

CAN/CAN FD Transmit

EPWM6_A14

O

ePWM-6 Output A

EQEP3_B

15

I

eQEP-3 Input B

GPIO72

73

74

83

84

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAME
GPIO73

MUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTION

0, 4, 8, 12

I/O

General-Purpose Input Output 73

OUTPUTXBAR1

1

O

Output X-BAR Output 1

EPWM5_B

2O

ePWM-5 Output B

SPIA_PTE

3I/O

SPI-A Peripheral Transmit Enable (PTE)EPWM8_A5O

ePWM-8 Output A

SPIB_PICO

6

I/O

SPI-B Peripheral In, Controller Out (PICO)

85

LINA_TX

9O

LIN-A Transmit

PMBUSA_SCL

10

I/OD

PMBus-A Open-Drain Bidirectional Clock

SCIA_TX

11O

SCI-A Transmit Data

ERRORSTS

13

O

Error Status Output. This signal requires an external
pulldown.

EPWM9_A14

O

ePWM-9 Output A

GPIO740, 4, 8, 12

I/O

General-Purpose Input Output 74

EPWM2_B

1O

ePWM-2 Output B

ADCSOCAO3O

ADC Start of Conversion A for External ADC

MCANA_TX

5O

CAN/CAN FD Transmit

SPIA_POCI6

I/O

SPI-A Peripheral Out, Controller In (POCI)EQEP1_B

11

I

eQEP-1 Input B

GPIO750, 4, 8, 12

I/O

General-Purpose Input Output 75

EPWM1_B

1O

ePWM-1 Output B

LINA_RX3I

LIN-A Receive

EPWM6_A5O

ePWM-6 Output A

SPIA_CLK

6

I/O

SPI-A Clock

EQEP1_STROBE

11

I/O

eQEP-1 Strobe

86

111

SCIC_RX14

I

SCI-C Receive Data

GPIO760, 4, 8, 12

I/O

General-Purpose Input Output 76

EPWM4_A

1O

ePWM-4 Output A

OUTPUTXBAR2

5

O

Output X-BAR Output 2

SPIA_PTE

6I/O

SPI-A Peripheral Transmit Enable (PTE)MCANA_RX10I

CAN/CAN FD Receive

EQEP1_INDEX

11

I/O

eQEP-1 Index

GPIO770, 4, 8, 12

I/O

General-Purpose Input Output 77

EPWM1_A

1O

ePWM-1 Output A

OUTPUTXBAR3

5

SPIA_PICO6MCANA_TX

112

O

Output X-BAR Output 3

I/O

SPI-A Peripheral In, Controller Out (PICO)

10O

CAN/CAN FD Transmit

EQEP1_A11

I

eQEP-1 Input A

SCIC_TX

14O

SCI-C Transmit Data

GPIO780, 4, 8, 12

I/O

General-Purpose Input Output 78

EPWM8_A2

O

ePWM-8 Output A

EPWM3_A3

O

ePWM-3 Output A

OUTPUTXBAR1

5

O

Output X-BAR Output 1

EPWM2_B

6O

ePWM-2 Output B

FSITXA_CLK

9OFSITX-A Output Clock36

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTIONGPIO790, 4, 8, 12

I/O

General-Purpose Input Output 79

EPWM8_B

2O

ePWM-8 Output B

EPWM3_B

3O

ePWM-3 Output B

MCANA_RX5I

CAN/CAN FD Receive

EPWM2_A6O

ePWM-2 Output A

I2CA_SDA

7

I/OD

I2C-A Open-Drain Bidirectional Data

PMBUSA_SCL

115

9

I/OD

PMBus-A Open-Drain Bidirectional Clock

GPIO800, 4, 8, 12

I/O

General-Purpose Input Output 80

EPWM1_A

1O

ePWM-1 Output A

OUTPUTXBAR7

3

O

Output X-BAR Output 7

SCIA_RX5I

SCI-A Receive Data

I2CB_SDA

6

I/OD

I2C-B Open-Drain Bidirectional Data

SPIA_PTE

7

I/O

SPI-A Peripheral Transmit Enable (PTE)FSITXA_D0

9O

FSITX-A Primary Data Output

MCANA_RX10I

CAN/CAN FD Receive116

CLB_OUTPUTXBAR811OCLB Output X-BAR Output 8

EQEP1_INDEX

13

I/O

eQEP-1 Index

EPWM3_A15

O

ePWM-3 Output A

GPIO810, 4, 8, 12

I/O

General-Purpose Input Output 81

EPWM1_B

1O

ePWM-1 Output B

OUTPUTXBAR6

2

O

Output X-BAR Output 6

SCIC_RX3

I

SCI-C Receive Data

SPIB_CLK

5I/O

SPI-B Clock

I2CB_SCL

6

I/OD

I2C-B Open-Drain Bidirectional ClockFSITXA_D1

9O

FSITX-A Optional Additional Data Output

MCANA_TX

10O

CAN/CAN FD Transmit

EQEP3_INDEX

11

I/O

eQEP-3 Index

GPIO2110, 4, 8, 12

I/O

General-Purpose Input Output 211

EPWM10_A

1

O

ePWM-10 Output A

EQEP3_A5

I

eQEP-3 Input A

GPIO2120, 4, 8, 12

I/O

General-Purpose Input Output 212

EPWM10_B

1O

ePWM-10 Output B

EQEP3_B

5

I

eQEP-3 Input B

GPIO2130, 4, 8, 12

I/O

General-Purpose Input Output 213

EPWM11_A

1O

ePWM-11 Output A

EQEP3_STROBE

5

I/O

eQEP-3 Strobe

GPIO2140, 4, 8, 12

I/O

General-Purpose Input Output 214

EPWM11_B

1O

ePWM-11 Output B

EQEP3_INDEX

5I/O

eQEP-3 Index

GPIO2150, 4, 8, 12

I/O

General-Purpose Input Output 215

EPWM7_B

1O

ePWM-7 Output B

EQEP2_A5

I

eQEP-2 Input A

117

43

44

45

46

47

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Table 5-1. Pin Attributes (continued)
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTIONGPIO2240, 4, 8, 12

I/O

General-Purpose Input Output 224 This pin also has
analog functions which are described in the ANALOG
section of this table.

EPWM11_B

1O

ePWM-11 Output B

OUTPUTXBAR3

5

O

Output X-BAR Output 3

SPIA_PICO

6

I/O

SPI-A Peripheral In, Controller Out (PICO)

21

17

13

9

7

EPWM1_A9O

ePWM-1 Output A

MCANA_TX

10O

CAN/CAN FD Transmit

EQEP1_A11

I

eQEP-1 Input A

ADCE_EXTMUXSEL3

13OADCE external mux selection pin for position 3

SCIC_TX

14O

SCI-C Transmit Data

GPIO226

0, 4, 8, 12

I/O

General-Purpose Input Output 226 This pin also has
analog functions which are described in the ANALOG
section of this table.

EPWM10_B

1O

ePWM-10 Output B

LINA_RX3I

LIN-A Receive

EPWM6_A5O

ePWM-6 Output A

SPIA_CLK

6

I/O

SPI-A Clock

EPWM1_B

9O

ePWM-1 Output B

EQEP1_STROBE

11

I/O

eQEP-1 Strobe

ADCE_EXTMUXSEL1

13OADCE external mux selection pin for position 1

SCIC_RX14

I

SCI-C Receive Data

GPIO2270, 4, 8, 12

I/O

General-Purpose Input Output 227 This pin also has
analog functions which are described in the ANALOG
section of this table.

I2CB_SCL

1

I/OD

I2C-B Open-Drain Bidirectional Clock

EPWM3_A3

O

ePWM-3 Output A

OUTPUTXBAR1

5

O

Output X-BAR Output 1

EPWM2_B

6O

ePWM-2 Output B

GPIO228

0, 4, 8, 12

I/O

General-Purpose Input Output 228 This pin also has
analog functions which are described in the ANALOG
section of this table.

EPWM10_A

1

O

ePWM-10 Output A

ADCSOCAO3O

ADC Start of Conversion A for External ADC

19

48

18

15

38

14

11

28

10

7

24

22

6

MCANA_TX

5O

CAN/CAN FD Transmit

SPIA_POCI6

I/O

SPI-A Peripheral Out, Controller In (POCI)EPWM2_B

9O

ePWM-2 Output B

EQEP1_B

11

I

eQEP-1 Input B

ADCE_EXTMUXSEL0

13OADCE external mux selection pin for position 0

GPIO230

0, 4, 8, 12

I/O

General-Purpose Input Output 230 This pin also has
analog functions which are described in the ANALOG
section of this table.

I2CB_SDA

1

I/OD

I2C-B Open-Drain Bidirectional Data

EPWM3_B

3O

ePWM-3 Output B

MCANA_RX5I

CAN/CAN FD Receive

EPWM2_A6O

ePWM-2 Output A

I2CA_SDA

7

I/OD

I2C-A Open-Drain Bidirectional Data

PMBUSA_SCL

9

I/OD

PMBus-A Open-Drain Bidirectional Clock

38

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50

40

29

25

23

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-1. Pin Attributes (continued)
SIGNAL NAMEMUX POSITION

128
PDT

100
PZ

80 PNA

64
PM

56 RSHPIN
TYPE

DESCRIPTIONGPIO2420, 4, 8, 12

I/O

General-Purpose Input Output 242 This pin also has
analog functions which are described in the ANALOG
section of this table.

EPWM11_A

1O

ePWM-11 Output A

OUTPUTXBAR2

5

O

Output X-BAR Output 2

SPIA_PTE

6I/O

SPI-A Peripheral Transmit Enable (PTE)

20

16

12

8

6

EPWM4_A9O

ePWM-4 Output A

MCANA_RX10I

CAN/CAN FD Receive

EQEP1_INDEX

11

I/O

eQEP-1 Index

ADCE_EXTMUXSEL2

13OADCE external mux selection pin for position 2

GPIO247

0, 4, 8, 12

I/O

General-Purpose Input Output 247 This pin also has
analog functions which are described in the ANALOG
section of this table.

EPWM12_B

1O

ePWM-12 Output B

GPIO253

0, 4, 8, 12

I/O

General-Purpose Input Output 253

EPWM12_A

1O

ePWM-12 Output A

I

JTAG test clock with internal pullup.

I/O

JTAG test-mode select (TMS) with internal pullup. This
serial control input is clocked into the TAP controller on
the rising edge of TCK. This device does not have a
TRSTn pin. An external pullup resistor (recommended
2.2 kΩ) on the TMS pin to VDDIO should be placedon the board to keep JTAG in reset during normal
operation.

I/OD

Device Reset (in) and Watchdog Reset (out). During
a power-on condition, this pin is driven low by thedevice. An external circuit may also drive this pin toassert a device reset. This pin is also driven low by the
MCU when a watchdog reset occurs. During watchdog
reset, the XRSn pin is driven low for the watchdog
reset duration of 512 OSCCLK cycles. A resistor
between 2.2 kΩ and 10 kΩ should be placed between
XRSn and VDDIO. If a capacitor is placed between
XRSn and VSS for noise filtering, it should be 100
nF or smaller. These values will allow the watchdog
to properly drive the XRSn pin to VOL within 512
OSCCLK cycles when the watchdog reset is asserted.
This pin is an open-drain output with an internal pullup.
If this pin is driven by an external device, it should bedone using an open-drain device.

42

41
TEST, JTAG, AND RESET

TCK

75

TMS

77

XRSn

3

60

62

2

45

47

5

36

38

3

33

35

4

POWER AND GROUND

VDD

VDDA

VREGENZ

5, 41,
53

1.2-V Digital Logic Power Pins. TI recommends
placing a decoupling capacitor near each VDD pin witha minimum total capacitance of approximately 10 µF.
It is also recommended that all VDD pins be externallyconnected to each other when internal VREG is used.

34

26

22

20

3.3-V Analog Power Pins. Place a minimum 2.2-µF
decoupling capacitor on each pin.

5, 55, 3, 70,
89, 10988

7, 52,
72

43, 6040, 54

3.3-V Digital I/O Power Pins. Place a minimum 0.1-µF
decoupling capacitor on each pin.

56

46

42

9, 30,
55, 705, 26,
45, 58

PAD

Digital Ground

25

21

19

Analog Ground93

73

7, 53, 5, 45,
92, 107 72, 86

VSS
VSSA

(2)

4, 44,
59

41

VDDIO

(1)

8, 53,
71

6, 54, 4, 71,
90, 108
87

40

33

I

Internal voltage regulator enable with internal
pulldown. Tie low to VSS to enable internal VREG. Tie
high to VDDIO to use an external supply.

On the 128-PDT package, VREFLO is assigned to pins 33 and 34; these pins should be tied together at the PCB level. On the 100-PZ
package, VREFLO is assigned to pins 26 and 27; these pins should be tied together at the PCB level.
On the 128-PDT package, VREFHI is assigned to pins 31 and 32; these pins should be tied together at the PCB level. On the 100-PZ
package, VREFHI is assigned to pins 24 and 25; these pins should be tied together at the PCB level.

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

5.3 Signal Descriptions
5.3.1 Analog Signals
Table 5-2. Analog Signals
SIGNAL NAME

PIN
TYPE

DESCRIPTION

128 PDT

100 PZ

80 PNA

64 PM

56 RSHA0I

ADC-A Input 0

30

23

19

15

13

A1

I

ADC-A Input 1

29

22

18

14

12

A2

I

ADC-A Input 2

21

17

13

9

7

A3

I

ADC-A Input 3

20

18

12

8

6

A4

I

ADC-A Input 4

42

36

27

23

21

A5

I

ADC-A Input 5

28

35

17

13

11

A6

I

ADC-A Input 6

18

14

10

6

A7

I

ADC-A Input 7

37

31

23

19

17

A8

I

ADC-A Input 8

39

37

24

20

18

A9

I

ADC-A Input 9

48

38

28

24

22

A10

I

ADC-A Input 10

50

40

29

25

23

A11

I

ADC-A Input 11

27

20

16

12

10

A12

I

ADC-A Input 12

35

28

22

18

16

A13

I

ADC-A Input 13

33, 3426, 27

21

17

15

A14

I

ADC-A Input 14

26

19

15

11

9

A15

I

ADC-A Input 15

22

14

10

8

A16

I

ADC-A Input 16

2

1

4

2

3

A17

I

ADC-A Input 17

60

48

33

27

24

A18

I

ADC-A Input 18

61

49

34

28

25

A19

I

ADC-A Input 19

62

50

35

29

26

A20

I

ADC-A Input 20

63

51

36

30

27

A24

I

ADC-A Input 24

64

52

37

31

28

A25

I

ADC-A Input 25

67

55

40

34

31

A26

I

ADC-A Input 26

24

A27

I

ADC-A Input 27

44

A28

I

ADC-A Input 28

47

AIO208I

Analog Pin Used For Digital Input 208

23

AIO209I

Analog Pin Used For Digital Input 209

24

AIO210I

Analog Pin Used For Digital Input 210

25

AIO225

I

Analog Pin Used For Digital Input 225

42

36

27

23

21

AIO226

I

Analog Pin Used For Digital Input 226

43

AIO227

I

Analog Pin Used For Digital Input 227

44

AIO228I

Analog Pin Used For Digital Input 228

45

AIO229I

Analog Pin Used For Digital Input 229

AIO231

I

Analog Pin Used For Digital Input 231

30

23

19

15

13

AIO232

I

Analog Pin Used For Digital Input 232

29

22

18

14

12

AIO233

I

Analog Pin Used For Digital Input 233

22

14

10

8

AIO234I

Analog Pin Used For Digital Input 234

31, 3224, 2520

16

14

AIO235

I

Analog Pin Used For Digital Input 235

33, 3426, 27

21

17

15

AIO237

I

Analog Pin Used For Digital Input 237

27

20

16

12

10

AIO238I

Analog Pin Used For Digital Input 238

35

28

22

18

16

AIO239I

Analog Pin Used For Digital Input 239

26

19

15

11

9

40

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-2. Analog Signals (continued)
SIGNAL NAME

PIN
TYPE

DESCRIPTION

128 PDT

100 PZ

AIO240I

Analog Pin Used For Digital Input 240

AIO241

I

Analog Pin Used For Digital Input 241

39

AIO242

I

Analog Pin Used For Digital Input 242

46

AIO243

I

Analog Pin Used For Digital Input 243

47

AIO244I

Analog Pin Used For Digital Input 244

28

AIO245

I

Analog Pin Used For Digital Input 245

37

AIO248I

Analog Pin Used For Digital Input 248

35

AIO249I

Analog Pin Used For Digital Input 249

AIO251

I

Analog Pin Used For Digital Input 251

36

30

AIO252

I

Analog Pin Used For Digital Input 252

38

32

AIO253

I

Analog Pin Used For Digital Input 253

23

B0

I

ADC-B Input 0

39

B1

I

ADC-B Input 1

B2

I

ADC-B Input 2

B3

I

B4

I

B5
B6

80 PNA

64 PM

56 RSH

37
24

20

18

21

17

13

11

31

23

19

17

29

22

18

16

41

24

20

18

50

40

29

25

23

19

15

11

7

ADC-B Input 3

20

16

12

8

6

ADC-B Input 4

49

39

28

24

22

I

ADC-B Input 5

38

32

I

ADC-B Input 6

21

17

13

9

7

B7

I

ADC-B Input 7

29

22

18

14

12

B8

I

ADC-B Input 8

42

36

27

23

21

B9

I

ADC-B Input 9

22

18

14

10

8

B10

I

ADC-B Input 10

27

20

16

12

10

B11

I

ADC-B Input 11

36

30

B12

I

ADC-B Input 12

28

21

17

13

11

B13

I

ADC-B Input 13

33, 3426, 27

21

17

15

B14

I

ADC-B Input 14

26

19

15

11

9

B15

I

ADC-B Input 15

30

23

19

15

13

B16

I

ADC-B Input 16

2

1

4

2

3

B17

I

ADC-B Input 17

60

48

33

27

24

B18

I

ADC-B Input 18

61

49

34

28

25

B19

I

ADC-B Input 19

62

50

35

29

26

B20

I

ADC-B Input 20

63

51

36

30

27

B24

I

ADC-B Input 24

65

53

38

32

29

B25

I

ADC-B Input 25

68

56

41

35

32

B26

I

ADC-B Input 26

25

B27

I

ADC-B Input 27

45

B30

I

ADC-B Input 30

37

31

23

19

17

C0

I

ADC-C Input 0

27

20

16

12

10

C1

I

ADC-C Input 1

35

29

22

18

16

C2

I

ADC-C Input 2

28

21

17

13

11

C3

I

ADC-C Input 3

37

31

23

19

17

C4

I

ADC-C Input 4

26

19

15

11

9

C5

I

ADC-C Input 5

20

28

12

8

6

C6

I

ADC-C Input 6

19

15

11

7

35

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Table 5-2. Analog Signals (continued)
SIGNAL NAME

PIN
TYPE

DESCRIPTION

128 PDT

100 PZ

80 PNA

64 PM

56 RSHC7I

ADC-C Input 7

22

18

14

10

8

C8

I

ADC-C Input 8

49

39

28

24

22

C9

I

ADC-C Input 9

21

17

13

9

7

C10

I

ADC-C Input 10

50

40

29

25

23

C11

I

ADC-C Input 11

39

41

24

20

18

C13

I

ADC-C Input 13

33, 3426, 27

21

17

15

C14

I

ADC-C Input 14

42

42

27

23

21

C15

I

ADC-C Input 15

30

23

19

15

13

C16

I

ADC-C Input 16

2

1

4

2

3

C17

I

ADC-C Input 17

60

48

33

27

24

C18

I

ADC-C Input 18

61

49

34

28

25

C19

I

ADC-C Input 19

62

50

35

29

26

C20

I

ADC-C Input 20

63

51

36

30

27

C24

I

ADC-C Input 24

66

54

39

33

30

C25

I

ADC-C Input 25

23

C26

I

ADC-C Input 26

43

C27

I

ADC-C Input 27

46

CMP1_DACLICMPSS-1 Low DAC Output

29

22

18

14

12

CMP1_HN0I

CMPSS-1 High Comparator Negative Input 0

22

14

10

8

CMP1_HN1ICMPSS-1 High Comparator Negative Input 1

27

20

16

12

10

CMP1_HP0I

CMPSS-1 High Comparator Positive Input 0

21

17

13

9

7

CMP1_HP1I

CMPSS-1 High Comparator Positive Input 1

27

20

16

12

10

CMP1_HP2I

CMPSS-1 High Comparator Positive Input 2

18

14

10

6

CMP1_HP3I

CMPSS-1 High Comparator Positive Input 3

22

14

10

8

CMP1_HP4I

CMPSS-1 High Comparator Positive Input 4

29

22

18

14

12

CMP1_HP5I

CMPSS-1 High Comparator Positive Input 5

38

32

CMP1_LN0I

CMPSS-1 Low Comparator Negative Input 0

22

14

10

8

CMP1_LN1I

CMPSS-1 Low Comparator Negative Input 1

27

20

16

12

10

CMP1_LP0I

CMPSS-1 Low Comparator Positive Input 0

21

17

13

9

7

CMP1_LP1ICMPSS-1 Low Comparator Positive Input 1

27

20

16

12

10

CMP1_LP2ICMPSS-1 Low Comparator Positive Input 2

18

14

10

6

CMP1_LP3I

CMPSS-1 Low Comparator Positive Input 3

22

14

10

8

CMP1_LP4I

CMPSS-1 Low Comparator Positive Input 4

29

22

18

14

12

CMP1_LP5I

CMPSS-1 Low Comparator Positive Input 5

38

32

CMP2_HN0I

CMPSS-2 High Comparator Negative Input 0

50

40

29

25

23

CMP2_HN1ICMPSS-2 High Comparator Negative Input 1

35

28

22

18

16

CMP2_HP0I

CMPSS-2 High Comparator Positive Input 0

42

36

27

23

21

CMP2_HP1I

CMPSS-2 High Comparator Positive Input 1

35

28

22

18

16

CMP2_HP2I

CMPSS-2 High Comparator Positive Input 2

48

38

28

24

22

CMP2_HP3I

CMPSS-2 High Comparator Positive Input 3

50

40, 41

29

25

23

CMP2_HP5I

CMPSS-2 High Comparator Positive Input 5

28

35

17

13

11

CMP2_LN0I

CMPSS-2 Low Comparator Negative Input 0

50

40

29

25

23

CMP2_LN1I

CMPSS-2 Low Comparator Negative Input 1

35

28

22

18

16

CMP2_LP0I

CMPSS-2 Low Comparator Positive Input 0

42

36

27

23

21

42

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 5-2. Analog Signals (continued)
SIGNAL NAME

PIN
TYPE

DESCRIPTION

128 PDT

100 PZ

80 PNA

64 PM

56 RSH

CMP2_LP1ICMPSS-2 Low Comparator Positive Input 1

35

28

22

18

16

CMP2_LP2ICMPSS-2 Low Comparator Positive Input 2

48

38

28

24

22

CMP2_LP3I

CMPSS-2 Low Comparator Positive Input 3

50

40, 41

29

25

23

CMP2_LP5I

CMPSS-2 Low Comparator Positive Input 5

28

35

17

13

11

CMP3_HN0I

CMPSS-3 High Comparator Negative Input 0

20

16

12

8

6

CMP3_HN1ICMPSS-3 High Comparator Negative Input 1

28

21

17

13

11

CMP3_HP0I

CMPSS-3 High Comparator Positive Input 0

19

15

11

7

CMP3_HP1I

CMPSS-3 High Comparator Positive Input 1

28

21

17

13

11

CMP3_HP2I

CMPSS-3 High Comparator Positive Input 2

30

23

19

15

13

CMP3_HP3I

CMPSS-3 High Comparator Positive Input 3

20

16

12

8

6

CMP3_HP4I

CMPSS-3 High Comparator Positive Input 4

26

19

15

11

9

CMP3_HP5I

CMPSS-3 High Comparator Positive Input 5

20

18

12

8

6

CMP3_LN0I

CMPSS-3 Low Comparator Negative Input 0

20

16

12

8

6

CMP3_LN1I

CMPSS-3 Low Comparator Negative Input 1

28

21

17

13

11

CMP3_LP0I

CMPSS-3 Low Comparator Positive Input 0

19

15

11

7

CMP3_LP1ICMPSS-3 Low Comparator Positive Input 1

28

21

17

13

11

CMP3_LP2ICMPSS-3 Low Comparator Positive Input 2

30

23

19

15

13

CMP3_LP3I

CMPSS-3 Low Comparator Positive Input 3

20

16

12

8

6

CMP3_LP4I

CMPSS-3 Low Comparator Positive Input 4

26

19

15

11

9

CMP3_LP5I

CMPSS-3 Low Comparator Positive Input 5

20

18

12

8

6

CMP4_HN0I

CMPSS-4 High Comparator Negative Input 0

42

42

27

23

21

CMP4_HN1ICMPSS-4 High Comparator Negative Input 1

37

31

23

19

17

CMP4_HP0I

CMPSS-4 High Comparator Positive Input 0

49

39

28

24

22

CMP4_HP1I

CMPSS-4 High Comparator Positive Input 1

37

31

23

19

17

CMP4_HP2I

CMPSS-4 High Comparator Positive Input 2

35

29

22

18

16

CMP4_HP3I

CMPSS-4 High Comparator Positive Input 3

42

42

27

23

21

CMP4_HP4I

CMPSS-4 High Comparator Positive Input 4

39

37

24

20

18

CMP4_HP5I

CMPSS-4 High Comparator Positive Input 5

3630

CMP4_LN0I

CMPSS-4 Low Comparator Negative Input 0

42

42

27

23

21

CMP4_LN1I

CMPSS-4 Low Comparator Negative Input 1

37

31

23

19

17

CMP4_LP0I

CMPSS-4 Low Comparator Positive Input 0

49

39

28

24

22

CMP4_LP1ICMPSS-4 Low Comparator Positive Input 1

37

31

23

19

17

CMP4_LP2ICMPSS-4 Low Comparator Positive Input 2

35

29

22

18

16

CMP4_LP3I

CMPSS-4 Low Comparator Positive Input 3

42

42

27

23

21

CMP4_LP4I

CMPSS-4 Low Comparator Positive Input 4

39

37

24

20

18

CMP4_LP5I

CMPSS-4 Low Comparator Positive Input 5

36

30

D0

I

ADC-D Input 0

64

52

37

31

28

D1

I

ADC-D Input 1

65

53

38

32

29

D2

I

ADC-D Input 2

66

54

39

33

30

D3

I

ADC-D Input 3

67

55

40

34

31

D4

I

ADC-D Input 4

68

56

41

35

32

D5

I

ADC-D Input 5

23

D6

I

ADC-D Input 6

24

D7

I

ADC-D Input 7

25

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Table 5-2. Analog Signals (continued)
SIGNAL NAME

PIN
TYPE

DESCRIPTION

128 PDT

100 PZ

80 PNA

64 PM

56 RSH

D8I

ADC-D Input 8

43

D9

I

ADC-D Input 9

44

D10

I

ADC-D Input 10

45

D11

I

ADC-D Input 11

29

22

18

14

12

D12

I

ADC-D Input 12

37

31

23

19

17

D13

I

ADC-D Input 13

33, 3426, 27

21

17

15

D14

I

ADC-D Input 14

18

14

10

6

D15

I

ADC-D Input 15

38

32

D16

I

ADC-D Input 16

36

30

D18

I

ADC-D Input 18

46

D19

I

ADC-D Input 19

47

D20

I

ADC-D Input 20

31, 3224, 2520

16

14DACA_OUTO

Buffered DAC-A Output.

30

23

19

15

13

E0

I

ADC-E Input 0

64

52

37

31

28

E1

I

ADC-E Input 1

65

53

38

32

29

E2

I

ADC-E Input 2

66

54

39

33

30

E3

I

ADC-E Input 3

67

55

40

34

31

E4

I

ADC-E Input 4

68

56

41

35

32

E5

I

ADC-E Input 5

23

E6

I

ADC-E Input 6

24

E7

I

ADC-E Input 7

25

E8

I

ADC-E Input 8

43

E9

I

ADC-E Input 9

44

E10

I

ADC-E Input 10

45

E11

I

ADC-E Input 11

35

29

22

18

16

E12

I

ADC-E Input 12

19

15

11

7

E13

I

ADC-E Input 13

33, 3426, 27

21

17

E14

I

ADC-E Input 14

18

14

10

6

E15

I

ADC-E Input 15

38

32

E16

I

ADC-E Input 16

36

30

E18

I

ADC-E Input 18

46

E19

I

ADC-E Input 19

47

E20

I

ADC-E Input 20

31, 3224, 25

20

16

14

E30

I

ADC-E Input 30

37

31

23

19

17

PGA1_INM

I

PGA-1 Minus

22

18

14

10

8

PGA1_INPI

PGA-1 Plus

21

17

13

9

7

PGA1_OUTO

PGA-1 Output

26

19

15

11

9

PGA2_INM

I

PGA-2 Minus

28

21

17

13

11

PGA2_INPI

PGA-2 Plus

20

16

12

8

6

PGA2_OUTO

PGA-2 Output

27

20

16

12

10

PGA3_INM

I

PGA-3 Minus

36

30

23

19

17

PGA3_INPI

PGA-3 Plus

35

29

22

18

16

PGA3_OUTO

PGA-3 Output

38

32

24

20

18

44

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Table 5-2. Analog Signals (continued)
SIGNAL NAME

PIN
TYPE

DESCRIPTION

128 PDT

VREFHI(1)I

ADC High Reference. In external referencemode, externally drive the high reference
voltage onto this pin. In internal referencemode, a voltage is driven onto this pin by the31, 32
device. In either mode, place at least a 2.2-µF
capacitor on this pin. This capacitor shouldbe placed as close to the device as possible
between the VREFHI and VREFLO pins.

VREFLO(2)I

ADC Low Reference

(1)
(2)

33, 34

100 PZ

80 PNA

64 PM

56 RSH24, 2520

16

14

26, 2721

17

15

On the 128-PDT package, VREFHI is assigned to pins 31 and 32; these pins should be tied together at the PCB level. On the 100-PZ
package, VREFHI is assigned to pins 24 and 25; these pins should be tied together at the PCB level.
On the 128-PDT package, VREFLO is assigned to pins 33 and 34; these pins should be tied together at the PCB level. On the 100-PZ
package, VREFLO is assigned to pins 26 and 27; these pins should be tied together at the PCB level.

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5.3.2 Digital Signals
Table 5-3. Digital Signals
SIGNAL NAME

PIN
TYPE

DESCRIPTIONGPIO

128 PDT

100 PZ

80 PNA

64 PM

56 RSH

ADCE_EXTMUXSEL0OADCE external mux selection pin for position 0 20, 228

18, 6014, 4810, 336, 27

24

ADCE_EXTMUXSEL1OADCE external mux selection pin for position 1 21, 226

19, 61

15, 4911, 347, 28

25

ADCE_EXTMUXSEL2OADCE external mux selection pin for position 2 242

20

16

12

8

6

ADCE_EXTMUXSEL3OADCE external mux selection pin for position 3 224

21

17

13

9

7

16, 18, 65, 74,
86, 9512, 14, 53, 74

10, 38, 58

6, 32, 47

29

ADCSOCAOOADC Start of Conversion A for External ADC

8, 33, 53, 70,
74, 228

ADCSOCBOOADC Start of Conversion B for External ADC

10, 32, 54

17, 79, 122

13, 64, 93

49, 7640, 6337

AUXCLKIN

I

Auxiliary Clock Input

29

1

100

3

1

2

CLB_OUTPUTXBAR1OCLB Output X-BAR Output 1

19, 2288, 104

69, 8351, 6742, 5639, 51

CLB_OUTPUTXBAR2OCLB Output X-BAR Output 2

7, 47

8, 105

6, 84

68

57

52

CLB_OUTPUTXBAR3OCLB Output X-BAR Output 3

23, 42, 44

94, 102, 106

81, 8557, 65, 69

54

49

80, 9354, 64, 73, 76

53, 6348

CLB_OUTPUTXBAR4OCLB Output X-BAR Output 4

10, 40, 43, 45

91, 101, 110,122

CLB_OUTPUTXBAR5OCLB Output X-BAR Output 5

5, 8, 52

15, 95, 118

11, 74, 89

58, 7447, 6155

CLB_OUTPUTXBAR6OCLB Output X-BAR Output 6

4, 15, 53

16, 96, 124

12, 75, 95

59, 7848

43

CLB_OUTPUTXBAR7OCLB Output X-BAR Output 7

1, 14, 56

80, 99, 125

65, 78, 96

62, 7951

46

66, 79, 97

63, 8052, 64

1, 47

CLB_OUTPUTXBAR8OCLB Output X-BAR Output 8

0, 6, 57, 80

81, 100, 116,
126

EPWM1_AO

ePWM-1 Output A

0, 4, 30, 77,
80, 224

21, 96, 100,
113, 116, 127

17, 75, 79, 98

1, 13, 59, 63

9, 48, 52

7, 43, 47

EPWM1_BO

ePWM-1 Output B

1, 5, 31, 75,
81, 226

19, 99, 111,
117, 118, 128

15, 78, 89, 99

2, 11, 62, 74

7, 51, 61

46, 5550, 98, 103,
105, 115, 126

40, 77, 82, 84,
97

29, 61, 66, 68,
80

25, 50, 55, 57,
64

1, 23, 45, 50,
52

EPWM2_AO

ePWM-2 Output A

2, 6, 7, 41, 79,230

EPWM2_BO

ePWM-2 Output B

3, 7, 40, 74,
78, 227, 228

18, 48, 86, 97,
101, 105, 114

14, 38, 76, 80,
84

10, 28, 60, 64,
68

6, 24, 49, 53,
57

22, 44, 48, 52

EPWM3_AO

ePWM-3 Output A

0, 4, 14, 68,
78, 80, 227

48, 72, 96,
100, 114, 116,
125

38, 75, 79, 96

28, 59, 63, 79

24, 48, 52

22, 43, 47

EPWM3_BO

ePWM-3 Output B

1, 5, 15, 69,
79, 230

50, 73, 99,
115, 118, 124

40, 78, 89, 95

29, 62, 74, 78

25, 51, 61

23, 46, 55

EPWM4_AO

ePWM-4 Output A

2, 6, 22, 76,242

20, 98, 104,
112, 126

16, 77, 83, 97

12, 61, 67, 80

8, 50, 56, 64

1, 6, 45, 51

EPWM4_BO

ePWM-4 Output B

3, 7, 23, 71

83, 97, 102,105

76, 81, 84

60, 65, 68

49, 54, 57

44, 49, 52

EPWM5_AO

ePWM-5 Output A

8, 37, 72

76, 84, 95

61, 7446, 5837, 4734

EPWM5_BO

ePWM-5 Output B

9, 35, 73

78, 85, 119

63, 9048, 7539, 6236, 5619, 67, 84, 87,
111, 122

15, 55, 68, 93

11, 40, 50, 76

7, 34, 41, 63

31, 38EPWM6_AO

ePWM-6 Output A

10, 17, 18, 72,
75, 226

EPWM6_BO

ePWM-6 Output B

11, 19, 69

64, 73, 88

52, 6937, 51

31, 4228, 392, 49, 56, 63,
72, 103

EPWM7_AO

ePWM-7 Output A

12, 28, 41, 64,
68, 236

1, 39, 51, 82

4, 28, 36, 66

2, 24, 30, 55

3, 22, 27, 50

EPWM7_BO

ePWM-7 Output B

13, 29, 67, 215 1, 10, 47, 62

50, 100

3, 35

1, 29

2, 26

56, 9641, 7935

32

EPWM8_AO

ePWM-8 Output A

14, 24, 73, 78

68, 85, 114,
125

EPWM8_BO

ePWM-8 Output B

15, 32, 79

79, 115, 124

64, 9549, 784037

EPWM9_AO

ePWM-9 Output A

16, 24, 71, 73

66, 68, 83, 85

54, 5639, 4133, 3530, 32EPWM9_BO

ePWM-9 Output B

17, 7267, 84

55

40

34

31

EPWM10_A

O

ePWM-10 Output A

2, 62, 211, 228 18, 43, 58, 98

14, 46, 77

10, 31, 61

6, 50

45

EPWM10_B

O

ePWM-10 Output B

1, 63, 212, 226 19, 44, 59, 99

15, 47, 78

11, 32, 62

7, 51

46

EPWM11_AO

ePWM-11 Output A

8, 64, 213, 242 20, 45, 56, 95

16, 7412, 588, 47

6EPWM11_B

O

ePWM-11 Output B

4, 65, 214, 224 21, 46, 57, 96

17, 7513, 59

9, 48

7, 43

9, 49, 60, 102

39, 41, 48, 81

28, 33, 65

24, 27, 54

22, 24, 49

EPWM12_AO

ePWM-12 Output A

20, 23, 66,
236, 253

EPWM12_B

O

ePWM-12 Output B

21, 41, 60, 67,
247

10, 52, 61, 103 42, 44, 49, 82

34, 6628, 5525, 50

EQEP1_AI

eQEP-1 Input A

6, 10, 20, 25,
28, 35, 40, 44,
50, 56, 64, 65,
77, 224

2, 13, 21, 56,
57, 60, 69, 78,
80, 101, 106,
113, 122, 126

4, 13, 33, 42,
48, 64, 69, 76,
80

2, 9, 27, 39,
53, 63, 64

1, 3, 7, 24, 36,
48

46

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57, 63, 65, 80,
85, 93, 97

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Table 5-3. Digital Signals (continued)
SIGNAL NAME

EQEP1_B

PIN
TYPE

I

DESCRIPTIONGPIO

128 PDT

100 PZ

80 PNA

64 PM

56 RSHeQEP-1 Input B

1, 9, 14, 18,
7, 11, 21, 29,
61, 64, 73, 76,
37, 41, 51, 57,
81, 86, 103,
66, 69, 74, 228
105

10, 14, 49, 52,
61, 66, 82, 84,
100

3, 10, 34, 37,
46, 66, 68

1, 6, 28, 31,
37, 55, 57

2, 25, 28, 34,
50, 52

10, 16, 20, 49,
62, 67, 79, 84,
91, 100, 102,
112, 116, 119,
121, 128

12, 16, 39, 50,
55, 64, 79, 81,
90, 92, 99

2, 12, 28, 35,
40, 49, 54, 63,
65, 758, 24, 29, 34,
40, 52, 54, 62

6, 22, 26, 31,
37, 47, 49, 56

EQEP1_INDEX

I/O

eQEP-1 Index

0, 9, 13, 17,
23, 31, 32, 43,
53, 59, 67, 72,
76, 80, 236,
242

EQEP1_STROBE

I/O

eQEP-1 Strobe

1, 8, 12, 16,
22, 30, 42, 52,
58, 68, 71, 75,
226

15, 19, 63, 66,
72, 82, 83, 94,
95, 99, 104,
111, 127

11, 15, 51, 54,
67, 74, 78, 83,
98

1, 11, 36, 39,
57, 58, 62, 67

7, 30, 33, 47,
51, 5627, 30, 46, 51

EQEP2_AI

eQEP-2 Input A

11, 14, 18, 24,
54, 69, 215

17, 47, 64, 68,
73, 87, 125

13, 52, 56, 68,
96

37, 41, 50, 79

31, 35, 41

28, 32, 38

51, 65, 66, 69,
74, 88, 124

43, 53, 54, 57,
69, 9538, 39, 42, 51,
78

32, 33, 42

29, 30, 39

EQEP2_BI

eQEP-2 Input B

15, 16, 19, 25,
33, 55, 70

EQEP2_INDEX

I/O

eQEP-2 Index

26, 29, 57, 71

1, 70, 81, 83

58, 66, 100

3, 43

1

2

2, 56, 71, 80,
96

1, 59, 65, 75

4, 44, 59

2, 48

3, 43

EQEP2_STROBE

I/O

eQEP-2 Strobe

4, 27, 28, 56,
64

EQEP3_AI

eQEP-3 Input A

22, 25, 70, 211 43, 69, 74, 104 57, 83

42, 67

56

51

EQEP3_BI

eQEP-3 Input B

9, 26, 72, 212

44, 70, 84, 119 58, 90

43, 75

62

56

EQEP3_INDEX

I/O

eQEP-3 Index

11, 18, 30, 69,
81, 21446, 64, 73, 87,
117, 127

52, 68, 98

1, 37, 50

31, 4128, 38

EQEP3_STROBE

I/O

eQEP-3 Strobe

10, 16, 27, 40,
71, 21345, 66, 71, 83,
101, 122

54, 59, 80, 93

39, 44, 64, 76

33, 53, 63

30, 48ERRORSTSO

Error Status Output. This signal requires anexternal pulldown.

24, 28, 29, 55,
64, 73

1, 2, 51, 56,
68, 85

1, 43, 56, 100

3, 4, 41

1, 2, 35

2, 3, 32

FSIRXA_CLKI

FSIRX-A Input Clock0, 4, 13, 30,
33, 54, 57, 67,
70

10, 17, 62, 65,
74, 81, 96,
100, 127

13, 50, 53, 66,
75, 79, 98

1, 35, 38, 59,
63

29, 32, 48, 52

26, 29, 43, 47

FSIRXA_D0

I

FSIRX-A Primary Data Input

3, 12, 32, 40,
44, 52, 58, 68

15, 63, 72, 79,
82, 97, 101,
106

11, 51, 64, 67,
76, 80, 85

36, 49, 60, 64,
69

30, 40, 49, 53

27, 37, 44, 48

FSIRXA_D1

I

FSIRX-A Optional Additional Data Input

2, 11, 31, 41,
53, 56, 69

16, 64, 73, 80,
98, 103, 128

12, 52, 65, 77,
82, 992, 37, 61, 66

31, 50, 55

28, 45, 50

FSITXA_CLKOFSITX-A Output Clock7, 10, 27, 44,
51, 7814, 71, 105,
106, 114, 122

10, 59, 84, 85,
93

44, 68, 69, 76

57, 6352

FSITXA_D0

O

FSITX-A Primary Data Output

6, 9, 26, 45,
49, 8012, 70, 110,
116, 119, 126

8, 58, 90, 97

43, 73, 75, 80

62, 64

1, 56

FSITXA_D1

O

FSITX-A Optional Additional Data Output

5, 6, 8, 25, 46,
50, 814, 13, 69, 95,
117, 118, 126

9, 57, 74, 89,
97

6, 42, 58, 74,
80

47, 61, 64

1, 55

GPIO0

I/O

General-Purpose Input Output 0

0

100

79

63

52

47

GPIO1

I/O

General-Purpose Input Output 1

1

99

78

62

51

46

GPIO2

I/O

General-Purpose Input Output 2

2

98

77

61

50

45

GPIO3

I/O

General-Purpose Input Output 3

3

97

76

60

49

44

GPIO4

I/O

General-Purpose Input Output 4

4

96

75

59

48

43

GPIO5

I/O

General-Purpose Input Output 5

5

118

89

74

61

55

GPIO6

I/O

General-Purpose Input Output 6

6

126

97

80

64

1

GPIO7

I/O

General-Purpose Input Output 7

7

105

84

68

57

52

GPIO8

I/O

General-Purpose Input Output 8

8

95

74

58

47

GPIO9

I/O

General-Purpose Input Output 9

9

119

90

75

62

GPIO10I/O

General-Purpose Input Output 10

10

122

93

76

63

GPIO11

I/O

General-Purpose Input Output 11

11

64

52

37

31

28

GPIO12

I/O

General-Purpose Input Output 12

12

63

51

36

30

27

GPIO13

I/O

General-Purpose Input Output 13

13

62

50

35

29

26

GPIO14

I/O

General-Purpose Input Output 14

14

125

96

79

GPIO15

I/O

General-Purpose Input Output 15

15

124

95

78

GPIO16

I/O

General-Purpose Input Output 16

16

66

54

39

33

30

GPIO17

I/O

General-Purpose Input Output 17

17

67

55

40

34

31

GPIO18I/O

General-Purpose Input Output 18

18

87

68

50

41

38

GPIO19I/O

General-Purpose Input Output 19

19

88

69

51

42

39

GPIO20I/O

General-Purpose Input Output 20

20

60

48

33

27

24

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Table 5-3. Digital Signals (continued)
SIGNAL NAME

PIN
TYPE

DESCRIPTIONGPIO

128 PDT

100 PZ

80 PNA

64 PM

56 RSHGPIO21

I/O

General-Purpose Input Output 21

21

61

49

34

28

25

GPIO22

I/O

General-Purpose Input Output 22

22

104

83

67

56

51

GPIO23

I/O

General-Purpose Input Output 23

23

102

81

65

54

49

GPIO24

I/O

General-Purpose Input Output 24

24

68

56

41

35

32

GPIO25

I/O

General-Purpose Input Output 25

25

69

57

42

GPIO26

I/O

General-Purpose Input Output 26

26

70

58

43

GPIO27

I/O

General-Purpose Input Output 27

27

71

59

44

GPIO28I/O

General-Purpose Input Output 28

28

2

1

4

2

3

GPIO29I/O

General-Purpose Input Output 29

29

1

100

3

1

2

GPIO30I/O

General-Purpose Input Output 30

30

127

98

1

GPIO31

I/O

General-Purpose Input Output 31

31

128

99

2

GPIO32

I/O

General-Purpose Input Output 32

32

79

64

49

40

37

GPIO33

I/O

General-Purpose Input Output 33

33

65

53

38

32

29

GPIO34

I/O

General-Purpose Input Output 34

34

123

94

77

GPIO35

I/O

General-Purpose Input Output 35

35

78

63

48

39

36

GPIO37

I/O

General-Purpose Input Output 37

37

76

61

46

37

34

GPIO40I/O

General-Purpose Input Output 40

40

101

80

64

53

48

GPIO41

I/O

General-Purpose Input Output 41

41

103

82

66

55

50

GPIO42

I/O

General-Purpose Input Output 42

42

94

GPIO43

I/O

General-Purpose Input Output 43

43

91

GPIO44

I/O

General-Purpose Input Output 44

44

106

GPIO45

I/O

General-Purpose Input Output 45

45

110

GPIO46

I/O

General-Purpose Input Output 46

46

4

GPIO47

I/O

General-Purpose Input Output 47

47

8

6

GPIO48I/O

General-Purpose Input Output 48

48

11

7

GPIO49I/O

General-Purpose Input Output 49

49

12

8

GPIO50I/O

General-Purpose Input Output 50

50

13

9

GPIO51

I/O

General-Purpose Input Output 51

51

14

10

GPIO52

I/O

General-Purpose Input Output 52

52

15

11

GPIO53

I/O

General-Purpose Input Output 53

53

16

12

GPIO54

I/O

General-Purpose Input Output 54

54

17

13

GPIO55

I/O

General-Purpose Input Output 55

55

51

43

GPIO56

I/O

General-Purpose Input Output 56

56

80

65

GPIO57

I/O

General-Purpose Input Output 57

57

81

66

GPIO58I/O

General-Purpose Input Output 58

58

82

67

GPIO59I/O

General-Purpose Input Output 59

59

121

92

GPIO60I/O

General-Purpose Input Output 60

60

52

44

GPIO61

I/O

General-Purpose Input Output 61

61

120

91

GPIO62

I/O

General-Purpose Input Output 62

62

58

46

31

GPIO63

I/O

General-Purpose Input Output 63

63

59

47

32

GPIO64

I/O

General-Purpose Input Output 64

64

56

GPIO65

I/O

General-Purpose Input Output 65

65

57

GPIO66

I/O

General-Purpose Input Output 66

66

9

GPIO67

I/O

General-Purpose Input Output 67

67

10

GPIO68I/O

General-Purpose Input Output 68

68

72

GPIO69I/O

General-Purpose Input Output 69

69

73

GPIO70I/O

General-Purpose Input Output 70

70

74

GPIO71

I/O

General-Purpose Input Output 71

71

83

GPIO72

I/O

General-Purpose Input Output 72

72

84

GPIO73

I/O

General-Purpose Input Output 73

73

85

GPIO74

I/O

General-Purpose Input Output 74

74

86

GPIO75

I/O

General-Purpose Input Output 75

75

111

GPIO76

I/O

General-Purpose Input Output 76

76

112

GPIO77

I/O

General-Purpose Input Output 77

77

113

48

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Table 5-3. Digital Signals (continued)
SIGNAL NAME

PIN
TYPE

DESCRIPTIONGPIO

128 PDT

100 PZ

80 PNA

64 PM

56 RSHGPIO78I/O

General-Purpose Input Output 78

78

114

GPIO79I/O

General-Purpose Input Output 79

79

115

GPIO80I/O

General-Purpose Input Output 80

80

116

GPIO81

I/O

General-Purpose Input Output 81

81

117

GPIO211

I/O

General-Purpose Input Output 211

211

43

GPIO212

I/O

General-Purpose Input Output 212

212

44

GPIO213

I/O

General-Purpose Input Output 213

213

45

GPIO214

I/O

General-Purpose Input Output 214

214

46

GPIO215

I/O

General-Purpose Input Output 215

215

47

GPIO224

I/O

General-Purpose Input Output 224

224

21

17

13

9

GPIO226

I/O

General-Purpose Input Output 226

226

19

15

11

7

GPIO227

I/O

General-Purpose Input Output 227

227

48

38

28

24

GPIO228

I/O

General-Purpose Input Output 228

228

18

14

10

6

GPIO230

I/O

General-Purpose Input Output 230

230

50

40

29

25

23

GPIO236

I/O

General-Purpose Input Output 236

236

49

39

28

24

22

GPIO242

I/O

General-Purpose Input Output 242

242

20

16

12

8

6

GPIO247

I/O

General-Purpose Input Output 247

247

GPIO253

I/O

General-Purpose Input Output 253

253

7

22

42
41

I2CA_SCL

I/OD

I2C-A Open-Drain Bidirectional Clock

1, 4, 8, 9, 18,
20, 27, 33, 37,
43, 57, 65, 70

57, 60, 65, 71,
74, 76, 81, 87,
91, 95, 96, 99,
119

I2CA_SDA

I/OD

I2C-A Open-Drain Bidirectional Data0, 5, 10, 19,
21, 26, 32, 35,
42, 56, 66, 79,
230

9, 50, 61, 70,
78, 79, 80, 88,
94, 100, 115,
118, 122

40, 49, 58, 63,
64, 65, 69, 79,
89, 9329, 34, 43, 48,
49, 51, 57, 63,
74, 7625, 28, 39, 40,
42, 52, 61, 63

23, 25, 36, 37,
39, 47, 55

I2CB_SCL

I/OD

I2C-B Open-Drain Bidirectional Clock3, 9, 15, 29,
51, 81, 227

1, 14, 48, 97,
117, 119, 124

10, 38, 76, 90,
95, 100

3, 28, 60, 75,
78

1, 24, 49, 62

2, 22, 44, 56

I2C-B Open-Drain Bidirectional Data2, 13, 50, 56,
2, 14, 28, 34,
98, 116, 123,
50, 64, 80, 230
125

1, 9, 40, 77,
94, 964, 29, 61, 77,
79

2, 25, 50

3, 23, 45

1, 8, 10, 12,
19, 51, 59, 62,
64, 65, 73, 74,
78, 88, 94,
102, 103, 111,
119, 121, 124

6, 8, 15, 43,
47, 50, 52, 53,
63, 69, 81, 82,
90, 92, 95, 100

3, 11, 32, 35,
37, 38, 48, 51,
57, 65, 66, 75,
78

1, 7, 29, 31,
32, 39, 42, 54,
55, 62

2, 26, 28, 29,
36, 39, 49, 50,
56

I2CB_SDA

I/OD

48, 53, 59, 61,
66, 68, 74, 75,
78, 9033, 38, 44, 46,
50, 54, 58, 59,
62, 7527, 32, 37, 41,
47, 48, 51, 62

24, 29, 34, 38,
43, 46, 56

LINA_RXI

LIN-A Receive

9, 11, 13, 15,
19, 23, 29, 33,
35, 41, 42, 47,
49, 55, 59, 63,
67, 69, 70, 75,
226

LINA_TXO

LIN-A Transmit

10, 12, 14, 18,
22, 24, 28, 32,
37, 40, 44, 46,
54, 58, 64, 68,
73

2, 4, 17, 56,
63, 68, 72, 76,
79, 82, 85, 87,
101, 104, 106,
122, 125

1, 13, 51, 56,
61, 64, 67, 68,
80, 83, 85, 93,
96

4, 6, 36, 41,
46, 49, 50, 64,
67, 69, 76, 79

2, 30, 35, 37,
40, 41, 53, 56,
63

3, 27, 32, 34,
37, 38, 48, 51

CAN/CAN FD Receive

0, 5, 11, 12,
21, 30, 47, 49,
51, 57, 61, 63,
66, 68, 70, 76,
79, 80, 230,
242

8, 9, 12, 14,
20, 50, 59, 61,
63, 64, 72, 74,
81, 100, 112,
115, 116, 118,
120, 127

6, 8, 10, 16,
40, 47, 49, 51,
52, 66, 79, 89,
91, 981, 12, 29, 32,
34, 36, 37, 63,
74

8, 25, 28, 30,
31, 52, 61

6, 23, 25, 27,
28, 47, 55

4, 10, 11, 13,
18, 21, 52, 57,
58, 60, 62, 67,
80, 84, 86, 96,
99, 105, 113,
117, 128

7, 9, 14, 17,
44, 46, 48, 50,
55, 65, 75, 78,
84, 992, 6, 10, 13,
31, 33, 35, 40,
59, 62, 68

6, 9, 27, 29,
34, 48, 51, 57

7, 24, 26, 31,
43, 46, 52

MCANA_RXI

MCANA_TXO

CAN/CAN FD Transmit

1, 4, 7, 13, 17,
20, 31, 46, 48,
50, 56, 60, 62,
65, 67, 72, 74,
77, 81, 224,228

MCANB_RXI

CAN/CAN FD Receive

3, 18, 33, 35,
53, 59, 61

16, 65, 78, 87,
97, 120, 121

12, 53, 63, 68,
76, 91, 92

38, 48, 50, 60

32, 39, 41, 49

29, 36, 38, 44

MCANB_TXO

CAN/CAN FD Transmit

2, 19, 32, 37,
58

76, 79, 82, 88,
98

61, 64, 67, 69,
77

46, 49, 51, 61

37, 40, 42, 50

34, 37, 39, 45

OUTPUTXBAR1

O

Output X-BAR Output 1

2, 24, 34, 58,
73, 78, 227

48, 68, 82, 85,
98, 114, 123

38, 56, 67, 77,
94

28, 41, 61, 77

24, 35, 50

22, 32, 45

OUTPUTXBAR2

O

Output X-BAR Output 2

3, 25, 37, 54,
59, 76, 242

17, 20, 69, 76,
97, 112, 121

13, 16, 57, 61,
76, 92

12, 42, 46, 60

8, 37, 49

6, 34, 44

11, 21, 51, 52,
58, 70, 96,
113, 118, 125

7, 17, 43, 44,
46, 58, 75, 89,
96

13, 31, 43, 59,
74, 799, 48, 61

7, 43, 55

12, 59, 65, 71,
74, 120, 124,
126

8, 47, 53, 59,
91, 95, 97

32, 38, 44, 78,
80

32, 64

1, 29

OUTPUTXBAR3

O

Output X-BAR Output 3

4, 5, 14, 26,
48, 55, 60, 62,
77, 224OUTPUTXBAR4

O

Output X-BAR Output 4

6, 15, 27, 33,
49, 61, 63, 70

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Table 5-3. Digital Signals (continued)
SIGNAL NAME

PIN
TYPE

DESCRIPTIONGPIO

128 PDT

100 PZ
1, 84

80 PNA

64 PM

56 RSHOUTPUTXBAR5

O

Output X-BAR Output 5

7, 28, 42, 64

2, 56, 94, 105

4, 57, 68

2, 57

3, 52

OUTPUTXBAR6

O

Output X-BAR Output 6

9, 29, 43, 81

1, 91, 117, 119 90, 100

3, 54, 75

1, 62

2, 56

52, 54, 79, 85,
98

1, 37, 39, 63,
69

31, 33, 52

28, 30, 47

OUTPUTXBAR7

O

Output X-BAR Output 7

0, 11, 16, 30,
44, 69, 71, 80

64, 66, 73, 83,
100, 106, 116,127

OUTPUTXBAR8

O

Output X-BAR Output 8

17, 31, 45, 72

67, 84, 110,
128

55, 992, 40, 73

34

31

PMBUSA_ALERTI/OD

PMBus-A Open-Drain Bidirectional Alert Signal

13, 19, 27, 37,
43, 45, 67

10, 62, 71, 76,
88, 91, 110

50, 59, 61, 69

35, 44, 46, 51,
54, 7329, 37, 42

26, 34, 39

PMBUSA_CTL

I/O

PMBus-A Control Signal - Target Input/
Controller Output

12, 18, 26, 35,
42, 44, 68

63, 70, 72, 78,
87, 94, 106

51, 58, 63, 68,
85

36, 43, 48, 50,
57, 6930, 39, 41

27, 36, 38

6, 40, 54, 56,
63, 76, 82, 90,
95

29, 39, 41, 48,
60, 66, 75, 78

25, 33, 35, 39,
49, 55, 62

23, 30, 32, 36,
44, 50, 56

PMBUSA_SCL

I/OD

PMBus-A Open-Drain Bidirectional Clock8, 50, 66, 68,
3, 9, 15, 16,
78, 83, 85, 97,
24, 35, 41, 47,
103, 115, 119,71, 73, 79, 230
124

PMBUSA_SDA

I/OD

PMBus-A Open-Drain Bidirectional Data2, 14, 17, 25,
32, 34, 40, 44,
46, 48, 62, 72

4, 11, 58, 67,
69, 79, 84, 98,
101, 106, 123,
125

7, 46, 55, 57,
64, 77, 80, 85,
94, 96

6, 31, 40, 42,
49, 61, 64, 69,
77, 7934, 40, 50, 53

31, 37, 45, 48

SCIA_RXI

SCI-A Receive Data0, 3, 5, 9, 17,
25, 28, 35, 49,
63, 64, 72, 80

2, 12, 56, 59,
67, 69, 78, 84,
97, 100, 116,
118, 119

1, 8, 47, 55,
57, 63, 76, 79,
89, 904, 32, 40, 42,
48, 60, 63, 74,
75

2, 34, 39, 49,
52, 61, 62

3, 31, 36, 44,
47, 55, 56

SCIA_TXOSCI-A Transmit Data

1, 2, 7, 8, 16,
24, 29, 37, 48,
62, 71, 73

1, 11, 58, 66,
7, 46, 54, 56,
68, 76, 83, 85, 61, 74, 77, 78,
95, 98, 99, 105 84, 100

3, 31, 39, 41,
46, 58, 61, 62,
68

1, 33, 35, 37,
47, 50, 51, 57

2, 30, 32, 34,
45, 46, 52

SCIB_RXI

SCI-B Receive Data

11, 13, 15, 19,
23, 41, 57, 67,
69

10, 62, 64, 73,
81, 88, 102,
103, 124

50, 52, 66, 69,
81, 82, 95

35, 37, 51, 65,
66, 7829, 31, 42, 54,
55

26, 28, 39, 49,
50

SCIB_TXO

SCI-B Transmit Data

9, 10, 12, 14,
18, 22, 40, 56,
68

63, 72, 80, 87,
101, 104, 119,122, 125

51, 65, 68, 80,
83, 90, 93, 96

36, 50, 64, 67,
75, 76, 79

30, 41, 53, 56,
62, 6327, 38, 48, 51,
56

SCIC_RXI

SCI-C Receive Data21, 33, 42, 67,
75, 81, 226

10, 19, 61, 65,
94, 111, 117

15, 49, 53

11, 34, 38, 57

7, 28, 32

25, 2921, 60, 72, 91,
113

17, 4813, 33, 54

9, 27

7, 24

SCIC_TXOSCI-C Transmit Data20, 43, 68, 77,
224

SPIA_CLK

I/O

SPI-A Clock19, 63, 72, 80,
3, 9, 12, 18,
87, 97, 111,
56, 68, 75, 226
119

15, 51, 65, 68,
76, 9011, 36, 50, 60,
75

7, 30, 41, 49,
6227, 38, 44, 56

SPIA_PICOI/O

SPI-A Peripheral In, Controller Out (PICO)

2, 8, 11, 16,
54, 69, 71, 77,
224

17, 21, 64, 66,
73, 83, 95, 98,
113

13, 17, 52, 54,
74, 7713, 37, 39, 58,
61

9, 31, 33, 47,
50

7, 28, 30, 45

SPIA_POCII/OSPI-A Peripheral Out, Controller In (POCI)

1, 4, 10, 13,
17, 35, 55, 67,
72, 74, 228

10, 18, 51, 62,
67, 78, 84, 86,
96, 99, 122

14, 43, 50, 55,
63, 75, 78, 93

10, 35, 40, 48,
59, 62, 76

6, 29, 34, 39,
48, 51, 63

26, 31, 36, 43,
46

SPIA_PTE

I/O

SPI-A Peripheral Transmit Enable (PTE)

20, 64, 68, 73,
0, 5, 11, 19,
76, 81, 85, 88,
24, 37, 57, 69,
100, 112, 116,
73, 76, 80, 242
118

16, 52, 56, 61,
66, 69, 79, 89

12, 37, 41, 46,
51, 63, 74

8, 31, 35, 37,
42, 52, 61

6, 28, 32, 34,
39, 47, 55

SPIB_CLK

I/O

SPI-B Clock4, 14, 22, 26,
28, 32, 52, 58,
64, 81

2, 15, 56, 70,
79, 82, 96,
104, 117, 125

1, 11, 58, 64,
67, 75, 83, 96

4, 43, 49, 59,
67, 792, 40, 48, 56

3, 37, 43, 51

SPIB_PICO

I/O

SPI-B Peripheral In, Controller Out (PICO)

7, 20, 24, 30,
40, 50, 56, 60,
65, 7313, 52, 57, 60,
68, 80, 85,
101, 105, 127

9, 44, 48, 56,
65, 80, 84, 98

1, 33, 41, 64,
68

27, 35, 53, 57

24, 32, 48, 52

SPIB_POCII/O

SPI-B Peripheral Out, Controller In (POCI)6, 16, 21, 25,
31, 41, 51, 57,
61, 66, 71

9, 14, 61, 66,
69, 81, 83,
103, 120, 126,
128

10, 49, 54, 57,
66, 82, 91, 97,
99

2, 34, 39, 42,
66, 8028, 33, 55, 64

1, 25, 30, 50

SPIB_PTE

I/O

SPI-B Peripheral Transmit Enable (PTE)

15, 23, 27, 29,
33, 53, 59, 70

1, 16, 65, 71,
74, 102, 121,
124

12, 53, 59, 81,
92, 95, 100

3, 38, 44, 65,
78

1, 32, 54

2, 29, 49

SYNCOUTO

External ePWM Synchronization Pulse

6, 52

15, 126

11, 97

80

64

1

I

JTAG Test Data Input (TDI) - TDI is the default
mux selection for the pin. The internal pullup isdisabled by default. The internal pullup should
35
be enabled or an external pullup added on theboard if this pin is used as JTAG TDI to avoid afloating input.

78

63

48

39

36

TDI

50

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Table 5-3. Digital Signals (continued)
PIN
TYPE

SIGNAL NAMEDESCRIPTIONGPIO

128 PDT

100 PZ

80 PNA

64 PM

56 RSHTDOOJTAG Test Data Output (TDO) - TDO is thedefault mux selection for the pin. The internal
pullup is disabled by default. The TDO function
will be in a tri-state condition when there37
is no JTAG activity, leaving this pin floating;the internal pullup should be enabled or an
external pullup added on the board to avoid afloating GPIO input.

USB0DMO

USB-0 PHY differential data

23

102

81

65

54

49

USB0DPO

USB-0 PHY differential data

41

103

82

66

55

50

X1

I/O

Crystal oscillator input or single-ended clock
input. The device initialization software must
configure this pin before the crystal oscillator isenabled. To use this oscillator, a quartz crystal 19
circuit must be connected to X1 and X2. Thispin can also be used to feed a single-ended
3.3-V level clock.

88

69

51

42

39

X2

I/O

Crystal oscillator output.

18

87

68

50

41

38

O

External Clock Output. This pin outputs a
divided-down version of a chosen clock signal
from within the device.

16, 18, 71

66, 83, 87

54, 6839, 5033, 4130, 38100 PZ

80 PNAXCLKOUT

76

61

46

37

34

5.3.3 Power and Ground
Table 5-4. Power and Ground
SIGNALNAME

DESCRIPTION

128 PDT

VDD

1.2-V Digital Logic Power Pins. TI recommends
placing a decoupling capacitor near each
VDD pin with a minimum total capacitance ofapproximately 10 µF. It is also recommended thatall VDD pins be externally connected to eachother when internal VREG is used.

6, 54, 90, 108

4, 71, 87

8, 53, 71

4, 44, 59

5, 41, 53

VDDA

3.3-V Analog Power Pins. Place a minimum
2.2‑µF decoupling capacitor on each pin.

41

34

26

22

20

VDDIO

3.3-V Digital I/O Power Pins. Place a minimum
0.1-µF decoupling capacitor on each pin.

5, 55, 89, 109

3, 70, 88

7, 52, 72

43, 6040, 54

Internal voltage regulator enable with internal
pulldown. Tie low to VSS to enable internal
VREG. Tie high to VDDIO to use an external
supply.

93

73

56

46

42

VSS

Digital Ground

7, 53, 92, 107

5, 45, 72, 86

9, 30, 55, 70

5, 26, 45, 58

PAD

VSSA

Analog Ground

40

33

25

21

19

VREGENZPIN TYPEI

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64 PM

56 RSH

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5.3.4 Test, JTAG, and Reset
Table 5-5. Test, JTAG, and Reset
SIGNAL
NAME
TCK

TMS

XRSn

PIN
TYPE

DESCRIPTION

128 PDT

100 PZ

80 PNA

64 PM

56 RSHI

JTAG test clock with internal pullup.

75

60

45

36

33

I/O

JTAG test-mode select (TMS) with internal
pullup. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
This device does not have a TRSTn pin.
77
An external pullup resistor (recommended
2.2‑kΩ) on the TMS pin to VDDIO should beplaced on the board to keep JTAG in reset
during normal operation.

62

47

38

35

I/OD

Device Reset (in) and Watchdog Reset (out).
During a power-on condition, this pin is driven
low by the device. An external circuit may
also drive this pin to assert a device reset.
This pin is also driven low by the MCU whena watchdog reset occurs. During watchdog
reset, the XRSn pin is driven low for thewatchdog reset duration of 512 OSCCLK
cycles. A resistor between 2.2 kΩ and 10 kΩshould be placed between XRSn and VDDIO. 3
If a capacitor is placed between XRSn and
VSS for noise filtering, it should be 100 nF or
smaller. These values will allow the watchdog
to properly drive the XRSn pin to VOL within
512 OSCCLK cycles when the watchdog
reset is asserted. This pin is an open-drain
output with an internal pullup. If this pin isdriven by an external device, it should bedone using an open-drain device.

2

5

3

4

5.4 Pin Multiplexing

52

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5.4.1 GPIO Muxed Pins
Table 5-6. GPIO Muxed Pins
0, 4, 8,
12

1

2

3
OUTPUTXBA
R7

5

6

7

9

10

11

13

14

15

EQEP1_INDEXEPWM3_AEPWM3_B

SCIA_RXI2CA_SDASPIA_PTEFSIRXA_CLKMCANA_RX

CLB_OUTPUTXB
AR8SCIA_TX

I2CA_SCLSPIA_POCIEQEP1_STROBEMCANA_TX

CLB_OUTPUTXBAR7

EPWM10_B

OUTPUTXBAR1

PMBUSA_SDA

SPIA_PICOSCIA_TX

FSIRXA_D1

I2CB_SDAEPWM10_A

OUTPUTXBAR2

PMBUSA_SCL

SPIA_CLKSCIA_RXFSIRXA_D0

I2CB_SCLOUTPUTXBAR3SPIB_CLKEQEP2_STROBEFSIRXA_CLK

CLB_OUTPUTXBAR6OUTPUTXBA
R3MCANA_RX

SPIA_PTEFSITXA_D1

CLB_OUTPUTXB
AR5

SCIA_RXOUTPUTXBAR4SYNCOUTEQEP1_A

SPIB_POCIFSITXA_D0

EPWM2_AOUTPUTXBA
R5

EQEP1_B

SPIB_PICOFSITXA_CLK

ADCSOCAO

EQEP1_STROBESCIA_TX

SPIA_PICOOUTPUTXBA
R6

EQEP1_INDEXSCIA_RXADCSOCBOEQEP1_AOUTPUTXBA
R7

EQEP1_B

EPWM7_AMCANA_RX

EQEP1_STROBESCIB_TX

PMBUSA_CTL

FSIRXA_D0

LINA_TX

SPIA_CLKEPWM7_B

MCANA_TX

EQEP1_INDEXSCIB_RX

PMBUSA_ALERTFSIRXA_CLK

LINA_RXSPIA_POCISCIB_TX

I2CB_SDAOUTPUTXBAR
3

PMBUSA_SDA

SPIB_CLKEQEP2_A

LINA_TX

EPWM3_A

CLB_OUTPUTXB
AR7

SCIB_RXI2CB_SCLOUTPUTXBAR
4

PMBUSA_SCL

SPIB_PTE

EQEP2_B

LINA_RXEPWM3_B

CLB_OUTPUTXBAR6OUTPUTXBA
R7

EPWM9_A

SCIA_TX

EQEP1_STROBE

PMBUSA_SCL

XCLKOUTEQEP2_B

SPIB_POCIOUTPUTXBA
R8

EPWM9_B

SCIA_RXEQEP1_INDEX

PMBUSA_SDAMCANA_TX

SCIB_TXMCANB_RX

EPWM6_A

I2CA_SCL

EQEP2_A

PMBUSA_CTL

XCLKOUT

LINA_TXSCIB_RXMCANB_TX

EPWM6_B

I2CA_SDA

EQEP2_B

PMBUSA_ALERTCLB_OUTPUTXB
AR1

LINA_RXEQEP1_AEPWM12_A

SPIB_PICOMCANA_TX

ADCE_EXTMUXS
EL0

I2CA_SCL

SCIC_TX

GPIO21

EQEP1_B

EPWM12_B

SPIB_POCIMCANA_RX

ADCE_EXTMUXS
EL1I2CA_SDASCIC_RXGPIO22

EQEP1_STROBE

SCIB_TXSPIB_CLK

LINA_TX

CLB_OUTPUTXB
AR1

LINA_TX

GPIO23

EQEP1_INDEX

SCIB_RXSPIB_PTE

LINA_RX

CLB_OUTPUTXB
AR3

LINA_RXGPIO0

EPWM1_AGPIO1

EPWM1_B

GPIO2

EPWM2_AGPIO3

EPWM2_B

OUTPUTXBAR2

GPIO4

EPWM3_A

I2CA_SCLMCANA_TX

GPIO5

EPWM3_B

I2CA_SDAGPIO6

EPWM4_AGPIO7

EPWM4_B

GPIO8

EPWM5_AGPIO9

EPWM5_B

GPIO10EPWM6_AGPIO11EPWM6_B

GPIO12
GPIO13
GPIO14EPWM8_AGPIO15EPWM8_B

GPIO16

SPIA_PICO

GPIO17

SPIA_POCIGPIO18SPIA_CLK

GPIO19SPIA_PTE

GPIO20

SCIB_TXMCANA_RX

EPWM11_B

MCANB_TX

EPWM4_AMCANB_RX

EPWM4_B

SPIA_POCIEPWM1_AEPWM1_B

FSITXA_D1

CLB_OUTPUTXBAR8EPWM2_A

CLB_OUTPUTXB
AR2

SCIA_TXMCANA_TX

EPWM2_B

I2CA_SCLFSITXA_D1

CLB_OUTPUTXB
AR5

EPWM11_A

SPIA_CLK

I2CA_SCLFSITXA_D0

LINA_RX

PMBUSA_SCL

I2CB_SCL

EQEP3_B

SCIB_TX

SPIA_POCII2CA_SDAFSITXA_CLK

LINA_TX

EQEP3_STROBE

CLB_OUTPUTXB
AR4SCIB_RXSPIA_PTEFSIRXA_D1

LINA_RXEQEP2_A

SPIA_PICO

EQEP3_INDEXEQEP3_STROBE

EPWM6_AEQEP3_INDEXEPWM4_AEPWM12_A

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X2
X1

EQEP3_AEPWM4_B

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Table 5-6. GPIO Muxed Pins (continued)
0, 4, 8,
12

1

2

3

5

6

GPIO24OUTPUTXBAR
1

EQEP2_A

SPIA_PTE

EPWM8_AGPIO25OUTPUTXBAR
2

EQEP2_B

GPIO26OUTPUTXBAR
3

GPIO27

7

9

10

11

13

14

SPIB_PICO

LINA_TX

PMBUSA_SCL

SCIA_TXERRORSTS

EPWM9_AEQEP1_A

SPIB_POCIFSITXA_D1

PMBUSA_SDA

SCIA_RXEQEP3_AEQEP2_INDEXOUTPUTXBAR3SPIB_CLKFSITXA_D0

PMBUSA_CTL

I2CA_SDA

EQEP3_B

OUTPUTXBAR
EQEP2_STROBE
4OUTPUTXBAR4SPIB_PTEFSITXA_CLK

PMBUSA_ALERTI2CA_SCL

EQEP3_STROBEGPIO28SCIA_RXEPWM7_AOUTPUTXBAR5

EQEP1_AEQEP2_STROBE

LINA_TXSPIB_CLKERRORSTS

I2CB_SDAGPIO29SCIA_TX

EPWM7_B

OUTPUTXBAR6

EQEP1_B

EQEP2_INDE
X

LINA_RXSPIB_PTEERRORSTS

I2CB_SCL

GPIO30

SPIB_PICOOUTPUTXBAR7

EQEP1_STROBEFSIRXA_CLKMCANA_RX

EPWM1_AEQEP3_INDEXGPIO31

SPIB_POCIOUTPUTXBAR8

EQEP1_INDEXFSIRXA_D1

MCANA_TX

EPWM1_B

GPIO32

I2CA_SDAGPIO33

I2CA_SCL

GPIO34OUTPUTXBAR
1

EQEP1_INDEXSPIB_CLKEPWM8_B

LINA_TX

FSIRXA_D0

MCANB_TX

PMBUSA_SDA

ADCSOCBOSPIB_PTEOUTPUTXBAR4

LINA_RXFSIRXA_CLKMCANB_RX

EQEP2_B

ADCSOCAO

PMBUSA_SDA

15

AUXCLKIN

SCIC_RXI2CB_SDAGPIO35

SCIA_RXSPIA_POCII2CA_SDAMCANB_RX

PMBUSA_SCL

LINA_RXEQEP1_A

PMBUSA_CTL

EPWM5_B

TDI

GPIO37OUTPUTXBAR
2

SPIA_PTE

I2CA_SCLSCIA_TXMCANB_TX

LINA_TX

EQEP1_B

PMBUSA_ALERTEPWM5_ATDO

GPIO40

SPIB_PICOEPWM2_B

PMBUSA_SDAFSIRXA_D0

SCIB_TX

EQEP1_A

LINA_TX

GPIO41EPWM7_AEPWM2_A

PMBUSA_SCLFSIRXA_D1

SCIB_RXEQEP1_B

LINA_RXEQEP1_STROBE

CLB_OUTPUTXBAR3OUTPUTXBA
R5

PMBUSA_CTL

I2CA_SDASCIC_RXGPIO43OUTPUTXBA
R6

PMBUSA_ALERTI2CA_SCL

SCIC_TX

PMBUSA_ALE
RT

EQEP1_INDEXCLB_OUTPUTXB
AR4

GPIO44OUTPUTXBA
R7

EQEP1_A

PMBUSA_SDAFSITXA_CLK

PMBUSA_CTL

CLB_OUTPUTXB
AR3FSIRXA_D0

GPIO45OUTPUTXBA
R8FSITXA_D0

PMBUSA_ALE
RT

CLB_OUTPUTXB
AR4

GPIO46

LINA_TXMCANA_TX

FSITXA_D1

PMBUSA_SDAMCANA_RX

CLB_OUTPUTXB
AR2

PMBUSA_SCL

GPIO42

LINA_RXGPIO47

LINA_RX

CLB_OUTPUTXB
AR4
EPWM12_B

SPIB_POCIOUTPUTXBAR
3MCANA_TX

SCIA_TX

PMBUSA_SDA

GPIO49OUTPUTXBAR
4MCANA_RX

SCIA_RX

LINA_RXGPIO50

EQEP1_AMCANA_TXSPIB_PICOI2CB_SDAFSITXA_D1

GPIO51

EQEP1_B

MCANA_RX

SPIB_POCII2CB_SCLFSITXA_CLKGPIO52

EQEP1_STROBE

CLB_OUTPUTXB
AR5

SPIB_CLKSYNCOUTFSIRXA_D0

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EQEP3_STROBE
USB0DP

LINA_TX

GPIO4854

ALT

FSITXA_D0

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Table 5-6. GPIO Muxed Pins (continued)
0, 4, 8,12

1

GPIO53
GPIO542

3

5

6

EQEP1_INDEX

CLB_OUTPUTXBAR6

SPIA_PICO

7

9

10

11

13

14

SPIB_PTE

ADCSOCAOMCANB_RXFSIRXA_D1

EQEP2_AOUTPUTXBAR
2

ADCSOCBO

LINA_TX

FSIRXA_CLK

EQEP2_B

OUTPUTXBAR
3

ERRORSTS

LINA_RXGPIO55

SPIA_POCIGPIO56

SPIA_CLK

CLB_OUTPUTXB
AR7MCANA_TX

EQEP2_STROBESCIB_TXSPIB_PICO

I2CA_SDA

EQEP1_AFSIRXA_D1

GPIO57

SPIA_PTE

CLB_OUTPUTXB
AR8MCANA_RX

EQEP2_INDEXSCIB_RXSPIB_POCII2CA_SCL

EQEP1_B

FSIRXA_CLKGPIO58OUTPUTXBAR1SPIB_CLK

LINA_TXMCANB_TX

EQEP1_STROBEFSIRXA_D0

GPIO59OUTPUTXBAR2SPIB_PTE

LINA_RXMCANB_RX

EQEP1_INDEXMCANA_TXOUTPUTXBAR3SPIB_PICOMCANA_RXOUTPUTXBAR4SPIB_POCIGPIO60

EPWM12_B

GPIO61
EPWM10_A

OUTPUTXBAR3MCANA_TX

SCIA_TX

GPIO63EPWM10_B

OUTPUTXBAR4MCANA_RX

SCIA_RX

LINA_RXEQEP1_AEQEP2_STROBE

EPWM7_AOUTPUTXBAR5

PMBUSA_SDA

GPIO64

SCIA_RXGPIO65

EQEP1_AEPWM11_B

SPIB_PICOMCANA_TX

I2CA_SCLGPIO66

EQEP1_B

EPWM12_A

SPIB_POCIMCANA_RX

I2CA_SDAGPIO67EPWM7_B

EPWM12_B

MCANA_TX

EQEP1_INDEXSCIB_RX

PMBUSA_ALERTFSIRXA_CLK

LINA_RXSPIA_POCISCIC_RXGPIO68EPWM7_AEPWM3_AMCANA_RX

EQEP1_STROBESCIB_TX

PMBUSA_CTL

FSIRXA_D0

LINA_TX

SPIA_CLK

SCIC_TX

EPWM3_B

OUTPUTXBA
R7

EQEP1_B

SCIB_RXSPIA_PTEFSIRXA_D1

LINA_RXEQEP2_A

SPIA_PICO

EQEP3_INDEXOUTPUTXBAR4

LINA_RXFSIRXA_CLKMCANA_RX

EQEP2_B

ADCSOCAO

EQEP3_A

SCIA_TX

EQEP1_STROBE

PMBUSA_SCL

XCLKOUTEQEP2_INDEX

PMBUSA_SDAMCANA_TX

PMBUSA_SCL

SCIA_TX

GPIO69EPWM6_B

GPIO70I2CA_SCLSPIB_PTE

SPIA_PICOEPWM4_B

OUTPUTXBA
R7

EPWM9_B

SCIA_RXEQEP1_INDE
X
LINA_TX

GPIO71EPWM9_A

LINA_TXSPIB_CLK

GPIO72

SPIA_POCIEPWM5_AOUTPUTXBA
R8

GPIO73OUTPUTXBAR
1

EPWM5_B

SPIA_PTE

EPWM8_A

SPIB_PICO

GPIO74EPWM2_B

ADCSOCAOMCANA_TX

SPIA_POCIEQEP1_B

GPIO75EPWM1_B

LINA_RXEPWM6_A

SPIA_CLKEQEP1_STROBEGPIO76EPWM4_AOUTPUTXBAR2SPIA_PTE

GPIO77EPWM1_AGPIO78EPWM8_AGPIO79EPWM8_B

GPIO80

EPWM1_AOUTPUTXBAR6OUTPUTXBAR3

SPIA_PICOEPWM3_AOUTPUTXBAR1

EPWM2_B

MCANA_RX

EQEP1_INDEXMCANA_TX

EQEP1_AEPWM3_B

MCANA_RX

EPWM2_A

I2CA_SDA

PMBUSA_SCL

SCIA_RXI2CB_SDASPIA_PTEFSITXA_D0

MCANA_RX

CLB_OUTPUTXB
AR8

SCIC_RXSPIB_CLK

I2CB_SCLFSITXA_D1

MCANA_TX

EQEP3_INDEXEPWM1_B

GPIO211EPWM10_A

EQEP3_AGPIO21
2

EPWM10_B

EQEP3_B

ERRORSTSERRORSTS

I2CB_SDASPIB_POCI

EQEP3_STROBE

EPWM6_AEQEP3_B

EPWM9_A

SCIC_RXSCIC_TX

FSITXA_CLKOUTPUTXBA
R7

GPIO81ALTMCANB_RXGPIO62EPWM11_A

15

EQEP1_INDEXEPWM3_A

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Table 5-6. GPIO Muxed Pins (continued)
0, 4, 8,121

GPIO21
3

EPWM11_A

EQEP3_STROBEGPIO21
4

EPWM11_B

EQEP3_INDEXGPIO215

EPWM7_B

EQEP2_AGPIO22
4

EPWM11_B

OUTPUTXBAR3

GPIO22
6

EPWM10_B

LINA_RXGPIO227

I2CB_SCLGPIO22
8

2

3

5

6

7

9

10

11

13

14

SPIA_PICOEPWM1_AMCANA_TX

EQEP1_A

ADCE_EXTMUXSEL3SCIC_TX

EPWM6_A

SPIA_CLKEPWM1_B

EQEP1_STROBE

ADCE_EXTMUXSEL1SCIC_RXEPWM3_AOUTPUTXBAR1

EPWM2_B

EPWM10_A

ADCSOCAOMCANA_TX

SPIA_POCIEPWM2_B

EQEP1_B

ADCE_EXTMUXSEL0GPIO230

I2CB_SDAEPWM3_B

MCANA_RX

EPWM2_AGPIO236

EPWM7_AEQEP1_INDEXGPIO242

EPWM11_A

OUTPUTXBAR2

EQEP1_INDEXADCE_EXTMUXS
EL2

GPIO24
7

EPWM12_B

GPIO253

EPWM12_A

I2CA_SDA

15

ALT

PMBUSA_SCL
EPWM12_A

SPIA_PTE

EPWM4_AMCANA_RX

AIO208
AIO209
AIO210
AIO225
AIO229
AIO231
AIO232
AIO233
AIO234
AIO235
AIO237
AIO238
AIO239
AIO240
AIO241
AIO244
AIO245
AIO248
AIO24956

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Table 5-6. GPIO Muxed Pins (continued)
0, 4, 8,
12

1

2

3

5

6

7

9

10

11

13

14

15

ALT

AIO251
AIO252

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5.4.2 Digital Inputs on ADC Pins (AIOs)
Some GPIOs are multiplexed with analog pins and only have digital input functionality. These are also referred toas AIOs. Pins with only an AIO option on this port can only function in input mode. See the device data sheet forlist of AIO signals. By default, these pins function as analog pins and the GPIOs are in a high-impedance state.
The GPyAMSEL register is used to configure these pins for digital or analog operation.
Note
If digital signals with sharp edges (high dv/dt) are connected to the AIOs, cross-talk can occur withadjacent analog signals. Therefore, limit the edge rate of signals connected to AIOs if adjacentchannels are being used for analog functions.
5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
Some GPIOs are multiplexed with analog pins and have digital input and output functionality. These are also
referred to as AGPIOs. Unlike AIOs, AGPIOs have full input and output capability. By default, the AGPIOs are
not connected and must be configured. Table 5-7 shows how to configure the AGPIOs. To enable the analog
functionality, set the register AGPIOCTRLx from analog subsystem. To enable the digital functionality, set theregister GPxAMSEL from the General-Purpose Input/Output (GPIO) chapter.
Table 5-7. AGPIO Configuration(1)

Pin Connected To:

AGPIOCTRLx.GPIOy(Default = 0)

GPxAMSEL.GPIOy(Default = 1)

ADC

GPIOy

0

0

-

Yes

0

1

(1)

-

1

0

-

Yes

1

1

Yes

-

-

(1)

By default there are no signals connected to AGPIO pins. One of the other rows in the table must be chosen for pin functionality.

Note
If digital signals with sharp edges (high dv/dt) are connected to the AGPIOs, cross-talk can occur withadjacent analog signals. The user must therefore limit the edge rate of signals connected to AGPIOs,
if adjacent channels are being used for analog functions.
The general schematic of analog subsystem with AGPIO implementation is illustrated in Figure 5-6. The
combinations of use cases for a specific analog input pin need special consideration are shown in Table 5-8.
The AGPIO analog pin path contains an extra series switch of 53Ω. This creates a low capacitance isolated
node shared by the ADC and CMPSS Comparator as shown in Figure 5-6. This node can be disturbed
when the ADC samples the channel (depending on the prior voltage stored on the ADC sample and holdcapacitor), and this disturbance can cause a false CMPSS event of up to 50ns. As shown in Table 5-8, special
considerations or workarounds need to be used for the combination of CMPSS Input, ADC Sampling, and
AGPIO. To accommodate this potential disturbance the following workarounds can be implemented:
1. Use a different pin (that is AIO pin type) for analog channels which need both ADC and CMPSS together.
2. Use the CMPSS Digital Filter with a setting of 50ns or greater, which filters the temporary disturbance.
3. Precondition the sample and hold capacitor of the ADC so the disturbance does not cause a false trip. For
example, perform a dummy read of a 3.3V connection from a different channel on the ADC immediately
before the impacted channel is read so the disturbance is in the positive direction, away from the false trip.
The opposite dummy read of a 0V signal can be used if the false trip is inverted in polarity.

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Table 5-8. The Combinations of Use Cases for a Specific Analog Input Pin
Function Used on a Specific Analog Pin

Component Used

CMPSS Comparator Input

Yes

-

Yes

-

Yes

ADC Sampling

Yes

Yes

-

Yes

Yes

AGPIO Analog Pin Type

Yes

Yes

Yes

-

-

AIO Analog Pin Type

-

-

-

Yes

Yes

ResultWorkaround needed

No special analysis or workaround needed

AnalogInterconnect

C2000 Device

AGPIO pin

GPIO Logic

ADC MUXAGPIO switch
AIO pinGPIO+

CMPSS MUX

GPIO

CMPSS
–
+
–

Switch RON
Cp

ADC
Ch

VREFLOGPIO Logic

Figure 5-6. Analog Subsystem Block Diagram with AGPIO Implementation

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5.4.4 GPIO Input X-BAR
The Input X-BAR is used to route signals from a GPIO to many different IP blocks such as the ADCs, eCAPs,
ePWMs, and external interrupts (see the Input X-BAR figure). The Input X-BAR Destinations table lists the
input X-BAR destinations. For details on configuring the Input X-BAR, see the Crossbar (X-BAR) chapter of the
TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual.
GPIO0

Asynchronous
Synchronous
Sync. + Qual.

Input X-BAR

INPUT16
INPUT15INPUT14INPUT13INPUT12INPUT11INPUT10INPUT9INPUT8INPUT7INPUT6
INPUT5
INPUT4
INPUT3
INPUT2
INPUT1GPIOx

EPG1IN1
EPG1IN2
EPG1IN3
EPG1IN4

EPG

Other Sources
127:16

INPUT[16:1]

eCAP1
eCAP2

15:0

TZ1,TRIP1
TZ2,TRIP2
TZ3,TRIP3

DCCx Clock Source-0

ePWM
Modules

TRIP6
DCCx Clock Source-1

XINT1
XINT2
XINT3
XINT4
XINT5

CPU PIE
CLA

CMPSS

INPUT[1-14]

CLB X-BAR

INPUT[1-16]

ERAD

INPUT[1-14]

ePWM
X-BAR

CMPSS1/3 FILINIT HighCMPSS1/3 FILINIT Low
CMPSS2/4 FILINIT HighCMPSS2/4 FILINIT Low

ADCEXTSOC

ADC

EXTSYNCIN1

ePWM andeCAP Sync
Scheme

EXTSYNCIN2Other Sources

Output X-BAR

Figure 5-7. Input X-BAR
Table 5-9. Input X-BAR Destinations

60

Input

ECAP

EPWM
XBAR

CLB
XBAR

OUTPU
T XBAR

EPWM
TRIP

ERAD

INPUTXBAR1

Yes

Yes

Yes

Yes

TZ1,
TRIP1

Yes

INPUTXBAR2

Yes

Yes

Yes

Yes

TZ2,
TRIP2

Yes

INPUTXBAR3

Yes

Yes

Yes

Yes

TZ3,
TRIP3

Yes

INPUTXBAR4

Yes

Yes

Yes

Yes

Yes

XINT1

INPUTXBAR5

Yes

Yes

Yes

Yes

Yes

XINT2

INPUTXBAR6

Yes

Yes

Yes

Yes

Yes

XINT3

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TRIP6

CPU
XINT

ADC
SOC

EPWM /
ECAP
SYNC

ADCE
XTSO
C

EXTSY
NCIN1

CMPSS

DCCx

EPG

EXTSY
NCIN2
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Table 5-9. Input X-BAR Destinations (continued)
Input

ECAP

EPWM
XBAR

CLB
XBAR

OUTPU
T XBAR

EPWM
TRIP

ERAD

CPU
XINT

ADC
SOC

EPWM /
ECAP
SYNC

CMPSS

INPUTXBAR7

Yes

Yes

Yes

Yes

CMPSS1/3.
EXT_FILTI
N_H

INPUTXBAR8

Yes

Yes

Yes

Yes

CMPSS1/3.
EXT_FILTI
N_L

INPUTXBAR9

Yes

Yes

Yes

Yes

CMPSS2/4.
EXT_FILTI
N_H
CMPSS2/4.
EXT_FILTI
N_L

INPUTXBAR10

Yes

Yes

Yes

Yes

DCCx

EPG

INPUTXBAR11

Yes

Yes

Yes

Yes

CLK1

INPUTXBAR12

Yes

Yes

Yes

Yes

CLK1

INPUTXBAR13

Yes

Yes

Yes

Yes

XINT4

EPGAI
N1

INPUTXBAR14

Yes

Yes

Yes

Yes

XINT5

EPGAI
N2

INPUTXBAR15

Yes

Yes

CLK1

EPGAI
N3

INPUTXBAR16

Yes

Yes

CLK0

EPGAI
N4

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5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
The Output X-BAR has eight outputs that can be selected on the GPIO mux as OUTPUTXBARx. The CLB
X-BAR has eight outputs that are connected to the CLB global mux as AUXSIGx. The CLB Output X-BAR has
eight outputs that can be selected on the GPIO mux as CLB_OUTPUTXBARx. The ePWM X-BAR has eight
outputs that are connected to the TRIPx inputs of the ePWM. The sources for the Output X-BAR, CLB X-BAR,
CLB Output X-BAR, and ePWM X-BAR are shown in Figure 5-8. For details on the Output X-BAR, CLB X-BAR,
CLB Output X-BAR, and ePWM X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F28P55x Real-Time
Microcontrollers Technical Reference Manual.

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EPG

EPG1.EPGOUTCTRIPOUTHCTRIPOUTLCMPSSxCTRIPHCTRIPL

Input X-BAR

INPUT1-14

FSI

RXTRIG[1-3]

CLB

CLBx_OUT[0-7]ePWM and eCAP
Sync Chain

EXTSYNCOUTADCSOCA0
Select Circuit

ADCSOCA0

ADCSOCB0
Select Circuit

ADCSOCB0eCAPx

ECAPxOUT

ADCx

EVT1
EVT2
EVT3
EVT4

CLAHALT

CLAHALTERAD

EVT[8-11]MCANx

FEVT[0-2]

CLB Input X-BAR

CLB
X-BAR

ePWM
X-BAR

AUXSIG1AUXSIG2AUXSIG3AUXSIG4AUXSIG5AUXSIG6AUXSIG7AUXSIG8
TRIP1
TRIP2
TRIP3
TRIP4
TRIP5
TRIP6
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
TRIP14
TRIP15

CLB
Global
Mux

All
ePWM
Modules

eQEPx

OutputX-BAR

X-BAR Flags(shared)

CLB
OutputX-BAR

OUTPUTXBAR1OUTPUTXBAR2OUTPUTXBAR3OUTPUTXBAR4OUTPUTXBAR5OUTPUTXBAR6OUTPUTXBAR7OUTPUTXBAR8

GPIO
Mux

CLB_OUTPUTXBAR1
CLB_OUTPUTXBAR2
CLB_OUTPUTXBAR3
CLB_OUTPUTXBAR4
CLB_OUTPUTXBAR5
CLB_OUTPUTXBAR6
CLB_OUTPUTXBAR7
CLB_OUTPUTXBAR8

CLB TILEx

Figure 5-8. Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR Sources

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5.5 Pins With Internal Pullup and Pulldown
Some pins on the device have internal pullups or pulldowns. Table 5-10 lists the pull direction and when it isactive. The pullups on GPIO pins are disabled by default and can be enabled through software. To avoid any
floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not bonded out ina particular package. Other pins noted in Table 5-10 with pullups and pulldowns are always on and cannot bedisabled.
Table 5-10. Pins With Internal Pullup and Pulldown
PIN
GPIOx

RESET
(XRSn = 0)

DEVICE BOOTAPPLICATION

Pullup disabled

Pullup disabled(1)Application defined

GPIO35/TDI

Pullup disabled

GPIO37/TDO

Pullup disabled

Application defined
Application defined

TCK

Pullup active

TMS

Pullup active

XRSn

Pullup active

Other pins (including AIOs)

No pullup or pulldown present(1)Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM.

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5.6 Connections for Unused Pins
For applications that do not need to use all functions of the device, Table 5-11 lists acceptable conditioning for
any unused pins. When multiple options are listed in Table 5-11, any option is acceptable. Pins not listed in Table
5-11 must be connected according to Section 5.
Table 5-11. Connections for Unused Pins
SIGNAL NAMEACCEPTABLE PRACTICEANALOG

VREFHI

Tie to VDDA (applies only if ADC is not used in the application)

VREFLO

Tie to VSSA

Analog input pins with
DACx_OUT••No Connect
Tie to VSSA through 4.7-kΩ or larger resistor

Analog input pins (except
DACx_OUT)•••No Connect
Tie to VSSA
Tie to VSSA through resistor

Analog input pins (shared withGPIOs)(1)•••

No connection (digital input mode with internal pullup enabled)
No connection (digital output mode with internal pullup disabled)
Pullup or pulldown resistor (any value resistor, digital input mode, and with internal pullup disabled)
DIGITAL

GPIOx

•
•
•

No connection (input mode with internal pullup enabled)
No connection (output mode with internal pullup disabled)
Pullup or pulldown resistor (any value resistor, input mode, and with internal pullup disabled)

When TDI mux option is selected (default), the GPIO is in Input mode.
GPIO35/TDI••Internal pullup enabled
External pullup resistor

When TDO mux option is selected (default), the GPIO is in Output mode only during JTAG activity;
otherwise, it is in a tri-state condition. The pin must be biased to avoid extra current on the input buffer.
GPIO37/TDO••

Internal pullup enabled
External pullup resistor

TCK

•
•

No Connect
Pullup resistor

TMS

Pullup resistor
Turn XTAL off and:GPIO19/X1•••

Input mode with internal pullup enabled
Input mode with external pullup or pulldown resistor
Output mode with internal pullup disabled

Turn XTAL off and:GPIO18/X2•••

Input mode with internal pullup enabled
Input mode with external pullup or pulldown resistor
Output mode with internal pullup disabled

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Table 5-11. Connections for Unused Pins (continued)
SIGNAL NAMEACCEPTABLE PRACTICE
POWER AND GROUND

VDD

All VDD pins must be connected per Section 5.3. Pins should not be used to bias any external circuits.

VDDA

If a dedicated analog supply is not used, tie to VDDIO.

VDDIOAll VDDIO pins must be connected per Section 5.3.

VSS

All VSS pins must be connected to board ground.

VSSA

If an analog ground is not used, tie to VSS.

(1)AGPIO pins share analog and digital functionality. The actions here only apply if these pins are also not being used for analog
functions.

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6 Specifications
6.1 Absolute Maximum Ratings
over recommended operating conditions (unless otherwise noted)(1) (2)
MIN

MAX

VDD with respect to VSS

–0.3

1.5

VDDIO with respect to VSS

–0.3

4.6

VDDA with respect to VSSA

–0.3

4.6

VIN (3.3 V)

–0.3

4.6

V

VIN (5.0 V) (5)

–0.3

6.0

V

Output voltage

VO

–0.3

4.6

V

Input clamp current - per pin (4) (6)IIK- VIN < VSS/VSSA- VIN > VDDIO/VDDA

–20

20

Input clamp current - per pin:
GPIO2/3/9/32

IIK- VIN < VSS–20

Input clamp current - total for all inputs (6)IIKTOTAL- VIN < VSS/VSSA- VIN > VDDIO/VDDA

–20

20

Output current

Digital output (per pin), IOUT

–20

20

mA

Operating junction temperature

TJ

–40

155

°C

Storage temperature(3)

Tstg

–65

150

°C

Supply voltage

Input voltage (7)

(1)

(2)
(3)
(4)
(5)
(6)
(7)

UNIT

V

mA

Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
All voltage values are with respect to VSS, unless otherwise noted.
Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see the Semiconductor and IC Package Thermal Metrics Application Note.
Continuous clamp current per pin is ±2mA
GPIO2, GPIO3, GPIO9, GPIO32 Only
Applying a VIN greater than VDDIO/VDDA or less than VSS/VSSA will turn on the ESD current clamping diode causing additional
current flow to the respective supply rail. If this occurs, the current must be kept within the MIN/MAX listed to prevent permanent
damage to the device.
Input clamp current must also be observed.

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6.2 ESD Ratings – Commercial
VALUE

UNIT

All F28P550Sxx devices in 128-pin PDT package
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)V(ESD)

Electrostatic discharge

All pins±2000

5V FS Pins:
79, 97, 98, 119±500

Charged-device model (CDM),
All pins
per ANSI/ESDA/JEDEC JS-002(2)Corner pins on 128-pin PDT:
1, 32, 33, 64, 65, 96, 97, 128

±500

V

±750

All F28P550Sxx devices in 100-pin PZ package
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)V(ESD)

Electrostatic discharge

All pins±2000

5V FS Pins:
64, 76, 77, 90±500

Charged-device model (CDM),
All pins
per ANSI/ESDA/JEDEC JS-002(2)Corner pins on 100-pin PZ:
1, 25, 26, 50, 51, 75, 76, 100

±500

V

±750

All F28P550Sxx devices in 80-pin PNA package
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)V(ESD)

Electrostatic discharge

All pins±2000

5V FS Pins:
49, 60, 61, 75±500

Charged-device model (CDM),
All pins
per ANSI/ESDA/JEDEC JS-002(2)Corner pins on 80-pin PNA:
1, 20, 21, 40, 41, 60, 61, 80

±500

V

±750

All F28P550Sxx devices in 64-pin PM package
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)V(ESD)

Electrostatic discharge

All pins±2000

5V FS Pins:
40, 49, 50, 62±500Charged-device model (CDM),
All pins
per ANSI/ESDA/JEDEC JS-002(2)Corner pins on 64-pin PM:
1, 16, 17, 32, 33, 48, 49, 64

±500

V

±750

All F28P550Sxx devices in 56-pin RSH package
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)V(ESD)

Electrostatic discharge

All pins±2000

5V FS Pins:
37, 44, 45, 56±500

Charged-device model (CDM),
All pins
per ANSI/ESDA/JEDEC JS-002(2)Corner pins on 56-pin RSH:
1, 14, 15, 28, 29, 42, 43, 56

±500

V

±750

(1)
(2)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 ESD Ratings – Automotive
VALUE

UNIT

All F28P559Sxx-Q1 devices in 128-pin PDT package

V(ESD)

Electrostatic discharge

Human body model (HBM), per
AEC Q100-002(1)All pins±2000

5V FS Pins:
79, 97, 98, 119±500

Charged device model (CDM),
per AEC Q100-011

All pins±500

Corner pins on 128-pin PDT:
1, 32, 33, 64, 65, 96, 97, 128±750

Human body model (HBM), per
AEC Q100-002(1)All pins±2000

5V FS Pins:
64, 76,77, 90±500

Charged device model (CDM),
per AEC Q100-011

All pins±500

Corner pins on 100-pin PZ:
1, 25, 26, 50, 51, 75, 76, 100±750

Human body model (HBM), per
AEC Q100-002(1)All pins±2000

5V FS Pins:
49, 60,61, 75±500

Charged device model (CDM),
per AEC Q100-011

All pins±500

Corner pins on 80-pin PNA:
1, 20, 21, 40, 41, 60, 61, 80±750

Human body model (HBM), per
AEC Q100-002(1)All pins±2000

5V FS Pins:
40, 49,50, 62±500Charged device model (CDM),
per AEC Q100-011

All pins±500

Corner pins on 64-pin PM:
1, 16, 17, 32, 33, 48, 49, 64

±750

V

All F28P559Sxx-Q1 devices in 100-pin PZ package

V(ESD)

Electrostatic discharge

V

All F28P559Sxx-Q1 devices in 80-pin PNA package

V(ESD)

Electrostatic discharge

V

All F28P559Sxx-Q1 devices in 64-pin PM package

V(ESD)(1)

Electrostatic discharge

V

AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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6.4 Recommended Operating Conditions
Device supply voltage, VDDIO and VDDA

Internal BOR enabled(3)Internal BOR disabled

Device supply voltage, VDD

MIN

NOM

MAX

VBOR-VDDIO(MAX) + VBOR-GB (2)

3.3

3.63

2.8

3.3

3.63

1.14

1.2

1.32

UNIT
V
V

Device ground, VSS

0V

Analog ground, VSSA

0V

SRSUPPLY

VIN

Supply ramp rate of VDDIO, VDD,VDDA with respect to VSS.(4)Digital input voltage(6)VSS – 0.3

VDDIO + 0.3

V

Digital input voltage(GPIO2, 3, 9, and32)(5)

VSS – 0.3

5.5

V

Analog input voltage(6)VSSA – 0.3

VDDA + 0.3

VJunction temperature, TJ (1)

–40

150

°C

Free-Air temperature, TA

–40

125

°C

(1)
(2)
(3)
(4)
(5)
(6)

70

Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded
Processors for more information.
See the Power Management Module (PMM) section.
Internal BOR is enabled by default.
See the Power Management Module Operating Conditions table.
These pins support applied voltage prior to the device being powered
Applying a VIN greater than VDDIO/VDDA or less than VSS/VSSA will turn on the ESD current clamping diode causing additional
current flow to the respective supply rail. VDDIO/VDDA voltage will internally rise and could impact other electrical characteristics.

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6.5 Power Consumption Summary
Current values listed in this section are representative for the test conditions given and not the absolute
maximum possible. The actual device currents in an application will vary with application code and pin
configurations.
6.5.1 System Current Consumption - VREG Enable - Internal Supply
Over recommended operating conditions (unless otherwise noted)
TYP : Vnom, Temperatures shown are TJ
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

OPERATING MODE
IDDIO

IDDA

This is an estimation of
30°C
current for a typical heavily
85°C
loaded application. Actual
currents will vary depending 125°C
on system activity, I/O
electrical loading andswitching frequency. This
includes Core supply current
with Internal Vreg Enabled.
- CPU is running from RAM- Flash is powered up- X1/X2 crystal is powered up- PLL is enabled,
125°C
SYSCLK=Max Device
frequency- Analog modules are
powered up- Outputs are static without
DC Load- Inputs are static high or low

92- CPU is in IDLE mode
30°C
- Flash is powered down
85°C
- PLL is Enabled,
125°C
SYSCLK=Max Device
Frequency, CPUCLK is gated- X1/X2 crystal is powered up- Analog Modules are
VDDA current consumption while powered down
125°C
device is in Idle mode
- Outputs are static without
DC Load- Inputs are static high or low

30

VDDIO current consumption
during operational usage

VDDA current consumption
during operational usage

mA
105

mA

115

mA

14

mA

IDLE MODE
IDDIO

IDDA

VDDIO current consumption
while device is in Idle mode

mA
36

mA

54

mA

3

mA

STANDBY MODE (PLL Enabled)
IDDIO

IDDA

- CPU is in STANDBY mode
- Flash is powered down
- PLL is Enabled, SYSCLK &CPUCLK are gated- X1/X2 crystal is powered
down- Analog Modules are
VDDA current consumption while powered down
device is in Standby mode
- Outputs are static without
DC Load- Inputs are static high or low
VDDIO current consumption
while device is in Standby mode

30°C

8

mA

85°C

14

mA

125°C

29

mA

125°C

3

mA

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6.5.1 System Current Consumption - VREG Enable - Internal Supply (continued)
Over recommended operating conditions (unless otherwise noted)
TYP : Vnom, Temperatures shown are TJ
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

STANDBY MODE (PLL Disabled)- CPU is in STANDBY mode 30°C
- Flash is powered down
85°C
- PLL is Disabled, SYSCLK &125°C
CPUCLK are gated- X1/X2 crystal is powered
down- Analog Modules are
VDDA current consumption while powered down
125°C
device is in Standby mode
- Outputs are static without
DC Load- Inputs are static high or low

4- CPU is in HALT mode
- Flash is powered down
- PLL is Disabled, SYSCLK
and CPUCLK are gated- X1/X2 crystal is powered
down- Analog Modules are
VDDA current consumption while powered down
device is in Halt mode
- Outputs are static without
DC Load- Inputs are static high or low

4

VDDIO current consumption
while device is in Standby mode

IDDIO

IDDA

mA
10

mA

24

mA

3

mA

HALT MODEVDDIO current consumption
while device is in Halt mode

IDDIO

IDDA

30°C

mA

85°C

10

mA

125°C

25

mA

125°C

3

mA

91

128

mA

0.1

8

mA

FLASH ERASE/PROGRAMIDDIOVDDIO current consumption
during Erase/Program cycle(1)IDDA

VDDA current consumption
during Erase/Program cycle- CPU is running from RAM- Flash going throughcontinuous Program/Erase
operation- PLL is enabled, SYSCLK at
120 MHz.
- Peripheral clocks are turnedOFF.
- X1/X2 crystal is powered up- Analog is powered down
- Outputs are static without
DC Load- Inputs are static high or low

RESET MODE
IDDIO

IDDA
(1)

VDDIO current consumption
while reset is active(2)VDDA current consumption while
reset is active(2)Device is under Reset

30°C

10

mA

85°C

13

mA

125°C

20

mA

125°C

0.01

mA

(2)

Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using
alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other systemcomponents with sufficient margin to avoid supply brownout conditions.
This is the current consumption while reset is active, that is XRSn is low.

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6.5.2 System Current Consumption - VREG Disable - External Supply
Over recommended operating conditions (unless otherwise noted)
TYP : Vnom, Temperatures shown are TJ
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

OPERATING MODE
IDD

IDDIO

IDDA

This is an estimation of
30°C
current for a typical heavily
85°C
loaded application. Actual
currents will vary depending 125°C
on system activity, I/O
30°C
electrical loading and
85°C
switching frequency. This
includes Core supply current 125°C
with Internal Vreg Enabled.
- CPU is running from RAM- Flash is powered up- X1/X2 crystal is powered up- PLL is enabled,
SYSCLK=Max Device
frequency
125°C- Analog modules are
powered up- Outputs are static without
DC Load- Inputs are static high or low

85- CPU is in IDLE mode
30°C
- Flash is powered down
85°C
- PLL is Enabled,
125°C
SYSCLK=Max Device
Frequency, CPUCLK is gated 30°C
- X1/X2 crystal is powered up
VDDIO current consumption
85°C- Analog Modules arewhile device is in Idle mode
powered down
125°C
- Outputs are static without
VDDA current consumption while DC Load
125°C
device is in Idle mode
- Inputs are static high or low

28

VDD current consumption during
operational usage

VDDIO current consumption
during operational usage

VDDA current consumption
during operational usage

mA
96

mA

115

mA

13

mA
17

mA

18

mA

14

mA

IDLE MODE
IDD

IDDIO

IDDA

VDD current consumption whiledevice is in Idle mode

mA
35

mA

54

mA

3

mA
6

mA

7

mA

3

mA

STANDBY MODE (PLL Enabled)
IDD

IDDIO

IDDA

- CPU is in STANDBY mode
- Flash is powered down
- PLL is Enabled, SYSCLK &CPUCLK are gated- X1/X2 crystal is powered
down
VDDIO current consumption
while device is in Standby mode - Analog Modules are
powered down
- Outputs are static without
VDDA current consumption while DC Loaddevice is in Standby mode
- Inputs are static high or low
VDD current consumption whiledevice is in Standby mode

30°C

6

85°C
125°C
30°C

mA
12

mA

32

mA

3

mA

85°C

6

mA

125°C

7

mA

125°C

3

mA

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6.5.2 System Current Consumption - VREG Disable - External Supply (continued)
Over recommended operating conditions (unless otherwise noted)
TYP : Vnom, Temperatures shown are TJ
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

STANDBY MODE (PLL Disabled)- CPU is in STANDBY mode 30°C
- Flash is powered down
85°C
- PLL is Disabled, SYSCLK &125°C
CPUCLK are gated- X1/X2 crystal is powered
30°C
down
VDDIO current consumption
85°C
while device is in Standby mode - Analog Modules are
powered down
125°C
- Outputs are static without
VDDA current consumption while DC Load
125°C
device is in Standby mode
- Inputs are static high or low

3- CPU is in HALT mode
- Flash is powered down
- PLL is Disabled, SYSCLK
and CPUCLK are gated- X1/X2 crystal is powered
down
VDDIO current consumption- Analog Modules arewhile device is in Halt mode
powered down
- Outputs are static without
VDDA current consumption while DC Loaddevice is in Halt mode
- Inputs are static high or low

2

VDD current consumption whiledevice is in Standby mode

IDD

IDDIO

IDDA

mA
8

mA

29

mA

2

mA
5

mA

6

mA

8

mA

HALT MODEVDD current consumption whiledevice is in Halt mode

IDD

IDDIO

IDDA

30°C

mA

85°C

8

mA

125°C

29

mA

30°C

2

mA

85°C

5

mA

125°C

6

mA

125°C

3

mA

80

108

mA

11

20

mA

0.1

8

mA

FLASH ERASE/PROGRAM
IDD

VDD current consumption during
Erase/Program cycle(1)IDDIO

VDDIO current consumption
during Erase/Program cycle(1)IDDA

VDDA current consumption
during Erase/Program cycle- CPU is running from RAM- Flash going throughcontinuous Program/Erase
operation- PLL is enabled, SYSCLK at
100 MHz.
- Peripheral clocks are turnedOFF.
- X1/X2 crystal is powered up- Analog is powered down
- Outputs are static without
DC Load- Inputs are static high or low

RESET MODE
IDD

IDDIO

IDDA
(1)

VDD current consumption while
reset is active(2)VDDIO current consumption
while reset is active(2)VDDA current consumption while
reset is active(2)Device is under Reset

30°C

5

mA

85°C

8

mA

125°C

15

mA

30°C

5

mA

85°C

5

mA

125°C

5

mA

125°C

0.01

mA

(2)

Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using
alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other systemcomponents with sufficient margin to avoid supply brownout conditions.
This is the current consumption while reset is active, that is XRSn is low.

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6.5.3 Operating Mode Test Description
The System Current Consumption - VREG Enable - Internal Supply table, System Current Consumption - VREG
Disable - External Supply table, and Section 6.5.4 list the current consumption values for the operational modeof the device. The operational mode provides an estimation of what an application might encounter. The test
condition for these measurements has the following properties:• Code is executing from RAM.
• FLASH is read and kept in active state.
• No external components are driven by I/O pins.
• All peripherals have clocks enabled.
• The CPU is actively executing code.
• All analog peripherals are powered up. ADCs and DACs are periodically converting.
6.5.4 Reducing Current Consumption
The F28P55x devices provide some methods to reduce the device current consumption:• One of the two low-power modes—IDLE or STANDBY—could be entered during idle periods in theapplication.
• The flash module may be powered down if the code is run from RAM.
• Disable the pullups on pins that assume an output function.
• Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may beachieved by turning off the clock to any peripheral that is not used in a given application. The Typical Current
Reduction per Disabled Peripheral table lists the typical current reduction that may be achieved by disabling
the clocks using the PCLKCRx register.
• To realize the lowest VDDA current consumption in an LPM, see the Analog-to-Digital Converter (ADC)
chapter of the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual to ensure each
module is powered down as well.
6.5.4.1 Typical Current Reduction per Disabled Peripheral
For peripherals with multiple instances, the current quoted is for all modules combined.
PERIPHERALIDDIO CURRENT REDUCTION (mA)

ADC(1)

1.0

CLA

0.56

CLB

1.41

CMPSS(1)0.31

CPU TIMER

0.06

GPDAC

0.12

MCAN

1.01

DCC

0.08

eCAP

0.12

ERAD

1.56

EPG

0.32

ePWM (for 1 ePWM)

0.95

eQEP

0.18

SCI

0.50

I2C

0.51

SPI

0.11

FSI RX

0.34

FSI TX

0.27

PMBUS

0.28

(1)

This current represents the current drawn by the digital portion of the each module.

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6.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONSPARAMETER

MIN

TYP

MAX

UNIT

Digital and Analog IO
VOHHigh-level output voltage

VOL

Low-level output voltage

IOH

High-level output source current for all output pins

IOH = IOH MINVDDIO * 0.8

IOH = –100 μA

VDDIO – 0.2

V

IOL = IOL MAX

0.4

IOL = 100 µA

0.2
–4

mA

Low-level output sinkcurrent for all output
pins
IOL

Low-level output
sink current for
GPIO2/3/9/32

ROH

4

mA

IO_DRVSEL:DRVSELG
PIOx = 0

4mA

IO_DRVSEL:DRVSELG
PIOx = 1

12mA

High-level output impedance for all output pins

VOH=VDDS-0.4V

50

66

96

Ω

48

60

84

Ω

IO_DRVSEL:DRVSELG VOL=0.4V
PIOx = 0

48

60

84

Ω

IO_DRVSEL:DRVSELG
PIOx = 1

15

21

33

Ω

Low-level output
impedance for all output
pins
ROL

Low-level output
impedance for
GPIO2/3/9/32
High-level input voltage

2.0VHigh-level input voltage- GPIO23/41

2.21

V

IO_MODSEL:MODSELGPIOx = 0

0.7*VDDIOV

IO_MODSEL:MODSELGPIOx = 1

1.35

V

VIH
High-level input voltage- GPIO2/3/9/32
Low-level input voltage

IO_MODSEL:MODSEL
Low-level input voltage - GPIOx = 0
GPIO2/3/9/32
IO_MODSEL:MODSELGPIOx = 1

VIL

VHYSTERESIS

V

Input hysteresis (AIO)

115

Input hysteresis (GPIO)

115

0.8

V

0.3*VDDIO

V

0.8

V
mV

IPULLDOWN

Input current

Pins with pulldown

VDDIO = 3.3 V
VIN = VDDIO

120

µA

IPULLUP

Input current

Digital inputs with pullup VDDIO = 3.3 V
enabled(1)VIN = 0 V

160

µA

RPULLDOWN

Weak pulldown resistance

RPULLUP

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GPIO2/3/9/32

22

31

62

kΩ

19

29

54

kΩ

20

31

65

kΩ

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6.6 Electrical Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONSPARAMETER

ILEAK

CI

MIN

TYP

MAX

Pin leakage

Digital inputs(all inputs except
GPIO2/3/9/32)

Pullups and outputs
disabled
0 V ≤ VIN ≤ VDDIO

0.150

Pin leakage(Device-powered).
See the Special
Considerations for 5V
Fail-Safe Pins section.

Digital inputs(GPIO2/3/9/32)

Pullups and outputs
disabled
0 V ≤ VIN ≤ 5.5 V
VDDIO = 3.3 V

30

Pin leakage(Device-unpowered)

Digital inputs(GPIO2/3/9/32)

Pullups and outputs
disabled
0 V ≤ VIN ≤ 5.5 V
VDDIO = 0 V

5Pin leakage

Analog pins

Analog drivers
disabled
0 V ≤ VIN ≤ VDDA

Digital inputs

Input capacitance

UNIT

µA

0.150
2

Analog pins(2)pF

VREG and BOR
VREG, POR,
BOR(3)(1)(2)(3)

See the Pins With Internal Pullup and Pulldown table for a list of pins with a pullup or pulldown.
The analog pins are specified separately; see the Per-Channel Parasitic Capacitance tables that are in the ADC Input Model section.
See the Power Management Module (PMM) section.

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6.7 Special Considerations for 5V Fail-Safe Pins
GPIO2, GPIO3, GPIO9, and GPIO32 are 5V Fail-Safe (5V FS) pins on this device. This means two things:• These pins can accept a voltage input of up to 5.5V, regardless of the supply voltage (VDDIO) level.
• These pins are also "Fail-Safe", meaning they can also have voltage applied to them prior to the device being
powered.
In order to achieve the above characteristics, the construction of the input buffer of these GPIOs is different
from the other GPIOs on this device. As such, there is both an additional leakage current parameter defined(unpowered leakage), and a behavioral difference for the powered leakage current when the device is powered.
Figure 6-1 shows the typical leakage current profile for these pins. As shown in the figure, there is an increased
leakage current present as the voltage on the pin exceeds the device's supply (VDDIO) voltage. It is during
this transition phase that the highest leakage current is observed. Once the input pin voltage is greater thanapproximately 4V, the current settles to a nominal value through the remainder of the input voltage range.

Figure 6-1. Leakage Current vs Input Voltage (Device Powered)

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6.8 Thermal Resistance Characteristics for PDT Package°C/W(1)RΘJC

Junction-to-case thermal resistance

10.6

RΘJB

Junction-to-board thermal resistance

24.9

RΘJA (High k PCB)

Junction-to-free air thermal resistance

42.5

PsiJT

Junction-to-package top

0.4

PsiJB

Junction-to-board

24.4

(1)

These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:••••

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

6.9 Thermal Resistance Characteristics for PZ Package°C/W(1)RΘJC

Junction-to-case thermal resistance

11

RΘJB

Junction-to-board thermal resistance

28.8

RΘJA (High k PCB)

Junction-to-free air thermal resistance

46.4

PsiJT

Junction-to-package top

0.4

PsiJB

Junction-to-board

28.2

(1)

These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:••••

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

6.10 Thermal Resistance Characteristics for PNA Package°C/W(1)RΘJC

Junction-to-case thermal resistance

14.5

RΘJB

Junction-to-board thermal resistance

29.5

RΘJA (High k PCB)

Junction-to-free air thermal resistance

51.7

PsiJT

Junction-to-package top

0.5

PsiJB

Junction-to-board

29.4

(1)

These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:••••

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

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6.11 Thermal Resistance Characteristics for PM Package°C/W(1)RΘJC

Junction-to-case thermal resistance

11.6

RΘJB

Junction-to-board thermal resistance

24.9

RΘJA (High k PCB)

Junction-to-free air thermal resistance

45

PsiJT

Junction-to-package top

0.4

PsiJB

Junction-to-board

24.5

(1)

These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:••••

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

6.12 Thermal Resistance Characteristics for RSH Package°C/W(1)RΘJC

Junction-to-case thermal resistance(top)11.6

Junction-to-case thermal resistance(bottom)

1.2

RΘJB

Junction-to-board thermal resistance

6.7

RΘJA (High k PCB)

Junction-to-free air thermal resistance

23.7

PsiJT

Junction-to-package top

0.1

PsiJB

Junction-to-board

6.7

(1)

These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:••••

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

6.13 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems
that exceed the recommended maximum power dissipation in the end product may require additional thermalenhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, careshould be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application note Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics anddefinitions.

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6.14 System
6.14.1 Power Management Module (PMM)
6.14.1.1 Introduction

The Power Management Module (PMM) handles all the power management functions required for device
operation.
6.14.1.2 Overview

The block diagram of the PMM is shown in Figure 6-2. As can be seen, the PMM comprises of various
subcomponents, which are described in the subsequent sections.

MCU

To Rest of Chip

PMM
I/O
POR

CPU Reset
ReleaseRISE
DELAY(80us)I/O
BORInternalAll
Monitors
ReleaseSignalRISE DELAY(Ext VREG = 320us)(Int VREG = 40us)EN
VMONCTL.bit.BORLVMONDIS

CVDDIOXRSn

VREGENZVSSInternal

VDD

1.2v LDOVREG

VSS

External

VDDIOInternal

VDD
POR

OUT

IN

EN

External

CVDD

Figure 6-2. PMM Block Diagram
6.14.1.2.1 Power Rail Monitors

The PMM has voltage monitors on the supply rails that release the XRSn signal high once the voltages cross theset threshold during power up. They also function to trip the XRSn signal low if any of the voltages drop below
the programmed levels. The various voltage monitors are described in subsequent sections.
Note
Not all the voltage monitors are supported for device operation in an application after boot up. In thecase where a voltage monitor is not supported, an external supervisor is recommended if the device
needs supply voltage monitoring while the application is running.
The three voltage monitors (I/O POR, I/O BOR, VDD POR) all have to release their respective outputs before thedevice begins operation (that is, XRSn goes high). However, if any of the voltage monitors trips, XRSn is driven
low. The I/Os are held in high impedance when any of the voltage monitors trip.
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6.14.1.2.1.1 I/O POR (Power-On Reset) Monitor

The I/O POR monitor supervises the VDDIO rail. During power up, this is the first monitor to release (that is, firstto untrip) on VDDIO.
6.14.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor

The I/O BOR monitor also supervises the VDDIO rail. During power up, this is the second monitor to release(that is, second to untrip) on VDDIO. This monitor has a tighter tolerance compared to the I/O POR.
Any drop in voltage below the recommended operating voltages will trip the I/O BOR and reset the device but
this can be disabled by setting VMONCTL.bit.BORLVMONDIS to 1. The I/O BOR can only be disabled after thedevice has fully booted up. If the I/O BOR is disabled, the I/O POR will reset the device for voltage drops.
Note
The level at which the I/O POR trips is well below the minimum recommended voltage for VDDIO, andtherefore should not be used for device supervision.
Figure 6-3 shows the operating region of the I/O BOR.

3.63 V

+10%

0%

3.3 V

Recommended
System Voltage
Regulator Range
VDDIO
Operating
Range

3.1 V

–6.1%

3.0 V

–9.1%

VBOR-GBBOR Guard Band
VBOR-VDDIOInternal BOR Threshold2.81 V
2.80 V–14.8%–15.1%

Figure 6-3. I/O BOR Operating Region
6.14.1.2.1.3 VDD POR (Power-On Reset) Monitor

The VDD POR monitor supervises the VDD rail. During power up, this monitor releases (that is, untrips) once thevoltage crosses the programmed trip level on VDD.
Note
VDD POR is programmed at a level below the minimum recommended voltage for VDD, and therefore
it should not be relied upon for VDD supervision if that is required in the application.
6.14.1.2.2 External Supervisor UsageVDDIO Monitoring: The I/O BOR is supported for application use, so an external supervisor is not required tomonitor the I/O rail.

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VDD Monitoring:• VDD supplied from the internal VREG: The VDD supply is derived from the VDDIO supply. The VREG is
designed in such a way that a valid VDDIO supply(monitored by the IO BOR) implies a valid VDD supply.
• VDD supplied from an external supply: The VDD POR is not supported for application use. If VDD monitoringis required by the application, an external supervisor can be used to monitor the VDD rail.
Note
The use of an external supervisor with the internal VREG is not supported.If VDD monitoring isrequired by the application, a package with a VREGENZ pin must be used to power VDD externally.
6.14.1.2.3 Delay Blocks

The delay blocks in the path of the voltage monitors work together to delay the release time between the voltage
monitors and XRSn. This is to ensure that the voltages are stable when XRSn releases. The delay blocks are
only active during power up (that is, when VDDIO and VDD are ramping up).
The delay blocks contribute to the minimum slew rates specified in Power Management Module Electrical Data
and Timing for the power rails.
Note
The delay numbers specified in the block diagram are typical numbers.
6.14.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)

The internal VREG is supplied by the VDDIO rail and can generate the 1.2 V required to power the VDD pins.
Although the internal VREG eliminates the need to use an external supply for VDD, decoupling capacitors arestill required on the VDD pins for VREG stability and transients. See the VDD Decoupling section for details.
6.14.1.2.5 VREGENZThe VREGENZ (VREG disable) pin controls the state of the internal VREG. To enable the internal VREG,
connect the VREGENZ pin to a logic low voltage. For applications supplying VDD externally (external VREG),
disable the internal VREG by tying the VREGENZ pin high.
Note
Not all device packages have VREGENZ pinned out. For packages without VREGENZ, external
VREG mode is not supported.
6.14.1.3 External Components
6.14.1.3.1 Decoupling Capacitors

VDDIO and VDD require decoupling capacitors for correct operation. The requirements are outlined insubsequent sections.
6.14.1.3.1.1 VDDIO Decoupling

Place a minimum amount of decoupling capacitance on VDDIO. See the CVDDIO parameter in PowerManagement Module Electrical Data and Timing. The actual amount of decoupling capacitance to use is arequirement of the power supply driving VDDIO. Either of the configurations outlined below is acceptable:• Configuration 1: Place a decoupling capacitor on each VDDIO pin per the CVDDIO parameter.
• Configuration 2: Install a single decoupling capacitor that is the equivalent of CVDDIO * VDDIO pins.
Note
Having the decoupling capacitor or capacitors close to the device pins is critical.

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6.14.1.3.1.2 VDD Decoupling

Place a minimum amount of decoupling capacitance on VDD. See the CVDD TOTAL parameter in PowerManagement Module Electrical Data and Timing.
In external VREG mode, the actual amount of decoupling capacitance to use is a requirement of the power
supply driving VDD.
Either of the configurations outlined below is acceptable:••

Configuration 1: Divide CVDD TOTAL equally across the VDD pins. In this configuration, the VDD pins may
be separated at the PCB level.
Configuration 2: Install a single decoupling capacitor with value of CVDD TOTAL. In this configuration, all
VDD pins must be connected to each other on the PCB.
Note
Having the decoupling capacitor or capacitors close to the device pins is critical.

6.14.1.4 Power Sequencing
6.14.1.4.1 Supply Pins Ganging

Connecting all 3.3-V rails together and supplying from a single source are strongly recommended. This list
includes:• VDDIO• VDDAIn addition, connect all power pins to avoid leaving any unconnected.
In external VREG mode, the VDD pins should be tied together and supplied from a single source.
In internal VREG mode, tying the VDD pins together is optional as long as each VDD pin has a capacitor
connected to pin. See the VDD Decoupling section for VDD decoupling configurations.
The analog modules on the device have fairly high PSRR; therefore, in most cases, noise on VDDA will
have to exceed the recommended operating conditions of the supply rails before the analog modules see
performance degradation. Therefore, supplying VDDA separately typically offers minimal benefits. Nevertheless,for the purposes of noise improvement, placing a pi filter between VDDIO and VDDA is acceptable.
Note
All the supply pins per rail are tied together internally. For example, all VDDIO pins are tied together
internally, all VDD pins are tied together internally, and so forth.
6.14.1.4.2 Signal Pins Power Sequence

Before powering the device, do not apply voltage larger than 0.3 V above VDDIO or 0.3 V below VSS to any
digital pin and 0.3 V above VDDA or 0.3 V below VSSA to any analog pin (including VREFHI). Simply, the signal
pins should only be driven after XRSn goes high, provided all the 3.3-V rails are tied together. This sequencing is
still required even if VDDIO and VDDA are not tied together.
CAUTION
If the above sequence is violated, device malfunction and possibly damage can occur as current willflow through unintended parasitic paths in the device.

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6.14.1.4.3 Supply Pins Power Sequence
6.14.1.4.3.1 External VREG/VDD Mode Sequence

Figure 6-4 depicts the power sequencing requirements for external VREG mode. The values for all theparameters indicated can be found in Power Management Module Electrical Data and Timing.
VDDIO

VBOR-VDDIO-UP(A)

SRVDDIO-UP

VPOR-VDDIOSRVDD-UP

VDDInternal
All Monitors Release
Signal(C)
XRSn

VDDIO

VBOR-VDDIO-DN(B)VDDInternal All
Monitors Release
Signal(D)

SRVDD-DN

VPOR-VDD-DN(B)VPOR-VDD-UP(A)XRSn

SRVDDIO-DN

VPOR-VDDIOVDDIO - VDD
Delay
VDDIO-MON-TOT-DELAY

A.
B.
C.
D.

VXRSn-PU-DELAY

VXRSn-PD-DELAY

This trip point is the trip point before XRSn releases. See the Power Management Module Characteristics table.
This trip point is the trip point after XRSn releases. See the Power Management Module Characteristics table.
During power up, the All Monitors Release Signal goes high after all POR and BOR monitors are released. See the PMM Block
Diagram.
During power down, the All Monitors Release Signal goes low if any of the POR or BOR monitors are tripped. See the PMM Block
Diagram.

Figure 6-4. External VREG Power Up Sequence••

For Power Up:
1. VDDIO (that is, the 3.3-V rail) should come up first with the minimum slew rate specified.
2. VDD (that is, the 1.2-V rail) should come up next with the minimum slew rate specified.
3. The time delta between the VDDIO rail coming up and when the VDD rail can come up is also specified.
4. After the times specified by VDDIO-MON-TOT-DELAY and VXRSN-PD-DELAY, XRSn will be released and thedevice starts the boot-up sequence.
5. The I/O BOR monitor has different release points during power up and power down.
6. During power up, both VDDIO and VDD rails have to be up before XRSn releases.
For Power Down:
1. There is no requirement between VDDIO and VDD on which should power down first; however, there is aminimum slew rate specification.
2. The I/O BOR monitor has different release points during power up and power down.
3. Any of the POR or BOR monitors that trips during power down will cause XRSn to go low after
VXRSN-PD-DELAY.
Note
The All Monitors Release Signal is an internal signal.
Note
If there is an external circuit driving XRSn (for example, a supervisor), the boot-up sequence does notstart until the XRSn pin is released by all internal and external sources.

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6.14.1.4.3.2 Internal VREG/VDD Mode Sequence

Figure 6-5 depicts the power sequencing requirements for internal VREG mode. The values for all theparameters indicated can be found in Power Management Module Electrical Data and Timing.
VDDIO

VDDIO

VBOR-VDDIO-UP(A)VBOR-VDDIO-DN(B)Internal
All Monitors Release
Signal(C)XRSn

SRVDDIO-UP

Internal All
Monitors Release
Signal(D)XRSn

SRVDDIO-DN

VPOR-VDDIOVPOR-VDDIOVDDIO-MON-TOT-DELAY

A.
B.
C.
D.

VXRSn-PU-DELAY

VXRSn-PD-DELAY

This trip point is the trip point before XRSn releases. See the Power Management Module Characteristics table.
This trip point is the trip point after XRSn releases. See the Power Management Module Characteristics table.
During power up, the All Monitors Release Signal goes high after all POR and BOR monitors are released. See the PMM Block
Diagram.
During power down, the All Monitors Release Signal goes low if any of the POR or BOR monitors are tripped. See the PMM Block
Diagram.

Figure 6-5. Internal VREG Power Up Sequence••

For Power Up:
1. VDDIO (that is, the 3.3-V rail) should come up with the minimum slew rate specified.
2. The Internal VREG powers up after the I/O monitors (I/O POR and I/O BOR) are released.
3. After the times specified by VDDIO-MON-TOT-DELAY and VXRSN-PU-DELAY, XRSn will be released and thedevice starts the boot-up sequence.
4. The I/O BOR monitor has different release points during power up and power down.
For Power Down:
1. The only requirement on VDDIO during power down is the slew rate.
2. The I/O BOR monitor has different release points during power up and power down.
3. The I/O BOR tripping will cause XRSn to go low after VXRSN-PD-DELAY and also power down the Internal
VREG.
Note
The All Monitors Release Signal is an internal signal.
Note
If there is an external circuit driving XRSn (for example, a supervisor), the boot-up sequence does notstart until the XRSn pin is released by all internal and external sources.

6.14.1.4.3.3 Supply Sequencing Summary and Effects of Violations

The acceptable power-up sequence for the rails is summarized below. "Power up" here means the rail inquestion has reached the minimum recommended operating voltage.
CAUTION
Non-acceptable sequences leads to reliability concerns and possibly damage.
For simplicity, connecting all 3.3-V rails together and following the descriptions in Supply Pins Power Sequenceis recommended.
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Table 6-1. External VREG Sequence Summary
CASE

RAILS POWER-UP ORDERACCEPTABLE

VDDIO

VDDA

VDD

A

1

2

3

Yes

B

1

3

2

Yes

C

2

1

3

No

D

2

3

1

No

E

3

2

1

No

F

3

1

2

No

G

1

1

2

Yes

H

2

2

1

No

Table 6-2. Internal VREG Sequence Summary
RAILS POWER-UP ORDER

CASE

ACCEPTABLE

VDDIO

VDDA

A

1

2

B

2

1

No

C

1

1

Yes

Yes

Note
The analog modules on the device should only be powered after VDDA has reached the minimum
recommended operating voltage.
6.14.1.4.3.4 Supply Slew RateVDDIO has a minimum slew rate requirement. If the minimum slew rate is not met, XRSn might toggle a few
times until VDDIO crosses the I/O BOR region.
Note
The toggling on XRSn has no adverse effect on the device as boot only starts once XRSn is steadilyhigh. However if XRSn from the device is used to gate the reset signal of other ICs, then the slew raterequirement should be met to prevent this toggling.
VDD has a minimum slew rate requirement in external VREG mode. If the minimum slew rate is not met, theVDD POR may release before the VDD operational minimum voltage is met and the device may not start in aproperly reset state.

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6.14.1.5 Power Management Module Electrical Data and Timing
6.14.1.5.1 Power Management Module Operating Conditions
over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

General
CVDDIO (1) (2)VDDIO Capacitance Per
Pin(7)0.1

uF

CVDDA (1) (2)VDDA Capacitance Per Pin(7)

2.2

uF

SRVDD33 (3)Supply Ramp Rate of 3.3V
Rails (VDDIO, VDDA)

20

100

VBOR-VDDIO-GB VDDIO Brown Out Reset(5)
Voltage Guardband

0.1

mV/us
V

External VREG
CVDD
TOTAL(1) (4)Total VDD Capacitance(7)10SRVDD12 (3)Supply Ramp Rate of 1.2V
Rail (VDD)

10

VDDIO - VDD
Delay(6)Ramp Delay Between VDDIO
and VDD

0

Total Nominal VDD
Capacitance(7)

10

uF
100

mV/us
us

Internal VREG
CVDD
TOTAL(1) (4)
(1)
(2)
(3)
(4)
(5)

(6)
(7)

22

uF

A bulk capacitor should also be used. The exact value of the decoupling capacitance depends on the system voltage regulation
solution that is supplying these pins.
It is recommended to tie the 3.3V rails (VDDIO, VDDA) together and supply them from a single source.
See the Supply Slew Rate section. Supply ramp rate faster than the maximum can trigger the on-chip ESD protection.
See the Power Management Module (PMM) section on possible configurations for the total decoupling capacitance.
TI recommends VBOR-VDDIO-GB to avoid BOR-VDDIO resets due to normal supply noise or load-transient events on the 3.3-V VDDIO
system regulator. Good system regulator design and decoupling capacitance (following the system regulator specifications) are
important to prevent activation of the BOR-VDDIO during normal device operation. The value of VBOR-VDDIO-GB is a system-level design
consideration; the voltage listed here is typical for many applications.
Delay between when the 3.3-V rail ramps up and when the 1.2-V rail ramps up. See the VREG Sequence Summary table for theallowable supply ramp sequences.
Max capacitor tolerance should be 20%.

6.14.1.5.2 Power Management Module Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSVVREGInternal Voltage Regulator
OutputVVREG-PU

Internal Voltage Regulator
Power Up Time

VVREG-INRUSH(4)Internal Voltage Regulator
Inrush Current

VPOR-VDDIOVDDIO Power on Reset
Voltage

VBOR-VDDIO-UP VDDIO Brown Out Reset(1)
Voltage on Ramp Up
VBOR-VDDIODOWN(1)VXRSn-PUDELAY(2)

VXRSn-PDDELAY

88

(3)

VDDIO Brown Out Reset
Voltage on Ramp Down

MIN

TYP

MAX

UNIT

1.152

1.2

1.248

V

350

us

650

mA

Before and After XRSn
Release

2.3

V

Before XRSn Release

2.7

V

After XRSn Release

2.81

3.0

V

XRSn Release Delay after
Supplies are Ramped Up
During Power-Up

40

us

XRSn Trip Delay after
Supplies are Ramped Down
During Power-Down

2

us

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6.14.1.5.2 Power Management Module Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETERVDDIO-MONTOT-DELAY

VXRSn-MONRELEASE-DELAY

TEST CONDITIONS

MIN

(3)
(4)

MAX

UNIT

Total Delays in Path of
VDDIO Monitors (POR, BOR)80

us

XRSn Release Delay after a
VDD POR Event

40

us

40

us

120

us

XRSn Release Delay after a
VDDIO BOR Event

Supplies Within Operating
Range

XRSn Release Delay after a
VDDIO POR Event
(1)
(2)

TYP

See the I/O BOR Operating Region figure.
Supplies are considered fully ramped up after they cross the minimum recommended operating conditions for the respective rail. All
POR and BOR monitors need to be released before this delay takes effect.
On power down, any of the POR or BOR monitors that trips will immediately trip XRSn. This delay is the time between any of the POR,
BOR monitors tripping and XRSn going low. It is variable and depends on the ramp down rate of the supply.
This is the transient current drawn on the VDDIO rail when the internal VREG turns on. Due to this, there might be some voltage dropson the VDDIO rail when the VREG turns on which could cause the VREG to ramp up in steps. There is no detriment to the device fromthis but the effect can be reduced if desired by using sufficient decoupling capacitors on VDDIO or picking an LDO/DC-DC that can
supply this transient current.

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6.14.2 Reset Timing
XRSn is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on
reset (POR) and brown-out reset (BOR) monitors. During power up, the monitor circuits keep the XRSn pin low.
For more details, see the Power Management Module (PMM) section. A watchdog or NMI watchdog reset will
also drive the pin low. An external open-drain circuit may drive the pin to assert a device reset.
A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRSn and VDDIO. A capacitor shouldbe placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow
the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset isasserted. Figure 6-6 shows the recommended reset circuit.
VDDIO
2.2 kW to 10 kW
Optional open-drain
Reset source

XRSn£100 nF

Figure 6-6. Reset Circuit
6.14.2.1 Reset Sources

The Reset Signals table summarizes the various reset signals and their effect on the device.
Table 6-3. Reset Signals
Reset Source

CPU Core Reset(C28x, FPU, TMU)

Peripherals
Reset

JTAG / Debug
Logic ResetIOs

XRS Output

POR

Yes

Yes

Yes

Hi-Z

Yes

BOR

Yes

Yes

Yes

Hi-Z

Yes

XRS Pin

Yes

Yes

No

Hi-Z

-

WDRS

Yes

Yes

No

Hi-Z

Yes

NMIWDRS

Yes

Yes

No

Hi-Z

Yes

SYSRS (Debugger Reset)

Yes

Yes

No

Hi-Z

No

SCCRESET

Yes

Yes

No

Hi-Z

No

SIMRESET. XRS

Yes

Yes

No

Hi-Z

Yes

SIMRESET. CPU1RS

Yes

Yes

No

Hi-Z

No

The parameter th(boot-mode) must account for a reset initiated from any of these sources.
See the Resets section of the System Control chapter in the TMS320F28P55x Real-Time Microcontrollers
Technical Reference Manual.
CAUTION
Some reset sources are internally driven by the device. Some of these sources will drive XRSn low,
use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset
sources do not drive XRSn; therefore, the pins used for boot mode should not be actively driven byother devices in the system. The boot configuration has a provision for changing the boot pins in
OTP.

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6.14.2.2 Reset Electrical Data and Timing
6.14.2.2.1 Reset - XRSn - Timing Requirements
MIN

MAX

UNIT

th(boot-mode)

Hold time for boot-mode pins

1.5

ms

tw(RSL2)

Pulse duration, XRSn low on warm reset

3.2

µs

6.14.2.2.2 Reset - XRSn - Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETERMIN

tw(RSL1)

Pulse duration, XRSn driven low by device after supplies are stabletw(WDRS)

Pulse duration, reset pulse generated by watchdog

tboot-flash

Boot-ROM execution time to first instruction fetch in flash

TYP

MAX

100

UNIT
µs

512tc(OSCCLK)

cycles1.2

ms

6.14.2.2.3 Reset Timing Diagrams

VDDIO VDDA
(3.3V)VDD (1.2V)
tw(RSL1)
XRSn(A)
tboot-flash
Boot ROMCPU
Execution
Phase

User codeth(boot-mode)(B)

Boot-Mode
Pins

User code dependent

GPIO pins as input
Peripheral/GPIO function
Based on boot code

Boot-ROM execution starts

GPIO pins as input (pullups are disabled)

I/O Pins

User code dependentA.
B.

The XRSn pin can be driven externally by a supervisor or an external pullup resistor, see the Pin Attributes table. On-chip monitors willhold this pin low until the supplies are in a valid range.
After reset from any source (see the Reset Sources section), the boot ROM code samples Boot Mode pins. Based on the status of
the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on
conditions (in debugger environment), the boot code execution time is based on the current SYSCLK speed. The SYSCLK will be basedon user environment and could be with or without PLL enabled.

Figure 6-7. Power-on Reset

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tw(RSL2)
XRSn
User code
CPU
Execution
Phase

Boot ROM

User code
Boot ROM execution starts(initiated by any reset source)

Boot-Mode
Pins

Peripheral/GPIO function

GPIO Pins as Inputth(boot-mode)(A)Peripheral/GPIO function
User-Code Execution Starts

I/O Pins

User-Code Dependent

GPIO Pins as Input (Pullups are Disabled)
User-Code DependentA.

After reset from any source (see the Reset Sources section), the Boot ROM code samples BOOT Mode pins. Based on the status of
the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on
conditions (in debugger environment), the Boot code execution time is based on the current SYSCLK speed. The SYSCLK will bebased on user environment and could be with or without PLL enabled.

Figure 6-8. Warm Reset

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6.14.3 Clock Specifications
6.14.3.1 Clock Sources

Table 6-4. Possible Reference Clock Sources
CLOCK SOURCEDESCRIPTIONINTOSC1

Internal oscillator 1.
10-MHz internal oscillator.

INTOSC2(1)Internal oscillator 2.
10-MHz internal oscillator.

X1 (XTAL)

External crystal or resonator connected between the X1 and X2 pins or single-ended clock connected to the X1
pin.

(1)

On reset, internal oscillator 2 (INTOSC2) is the default clock source for the PLL (OSCCLK).

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WDCLK

Watchdog
Timer

PERCLKDIVSEL.USBCLKDIV
/1
/2
.
.
.
/8

CLBCLKCTLSYSCLK

USBBITCLK

/1
/2
.
.
.
/8

PLLCLKSYSCLKDIVSEL

CLB_TILE_CLK/1 or /2

CLB_REG_CLKSYSCLK
SYS
Divider

SYSPLL PLLRAWCLKINTOSC1PLLSYSCLKNMIWDOSCCLKINTOSC2PLLCLKEN
X1 (XTAL)OSCCLKRCSELCPUCLKCPUSYSCLKFPU
TMU

Boot ROM
ePIE
FLASH
GPIO

SYSCLK

CLA ROM
DCSM
XINT
WD

GSx RAMs
LSx RAMs
Mx RAMs
Message RAM
System Control

KDIV
Flash Wrapper Clock
Divider

FLCLK

Flash Wrapper

One per SYSCLK peripheral
CLA
CPUTIMERs
EPWM
ECAP
EQEP
HRCAL

PCLKCRx
PERx.SYSCLK

ADC
CMPSS
GPDAC
PGA
DCC
PMBUS
USB

AES
CLB
ERAD
EPG
FSI
I2C

One per SYSCLK peripheral
LSPCLKDIVPCLKCRx
LSP
Divider

LSPCLK

PERx.LSPCLK

SCI
SPI

PLLRAWCLKLIN Xmit
Clock Gen

One per SYSCLK peripheral
LINACLKDIVPCLKCRx
LIN Clock
Divider

PERx.LINACLK

LINACLKLIN

One per SYSCLK peripheral
NPUCLKDIVPCLKCRx
NPU Clock
Divider

PERx.NPUCLKNPUCLKNPU

AUXCLKDIVSEL.MCANxCLKDIVReserved

01

AUXCLKIN(GPIO29)
PLLRAWCLK

2
3

/1
/2
.
.
.
/20

MCAN Bit Clock

CLKSRCCTL2.MCANxBCLKSEL

Figure 6-9. Clocking System

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SYSPLLOSCCLKINTCLK÷VCO(REFDIV+1)

VCOCLK

PLLRAWCLK÷(ODIV+1)÷
IMULT

Figure 6-10. System PLL
In the System PLL figure,
fPLLRAWCLK =fOSCCLK× IMULT
REFDIV + 1
ODIV + 1

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6.14.3.2 Clock Frequencies, Requirements, and Characteristics

This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of
the internal clocks, and the frequency and switching characteristics of the output clock.
6.14.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
6.14.3.2.1.1 Input Clock Frequency
MIN

MAX

UNIT

f(XTAL)

Frequency, X1/X2, from external crystal or resonator

10

20

MHz

f(X1)

Frequency, X1, from external oscillator

10

25

MHz

6.14.3.2.1.2 XTAL Oscillator Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER

MIN

TYP

MAX

UNIT

X1 VIL

Valid low-level input voltage–0.3

0.3 * VDDIOV

X1 VIH

Valid high-level input voltage

0.7 * VDDIOVDDIO + 0.3

V

6.14.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
over recommended operating conditions (unless otherwise noted)
MIN

MAX

X1 VIL

Valid low-level input voltage (Buffer)

PARAMETER–0.3

0.3 * VDDIO

UNIT
V

X1 VIH

Valid high-level input voltage (Buffer)

0.7 * VDDIOVDDIO + 0.3

V

6.14.3.2.1.4 X1 Timing Requirements
MAX

UNIT

tf(X1)

Fall time, X1

MIN

6

ns

tr(X1)

Rise time, X1

6nstw(X1L)

Pulse duration, X1 low as a percentage of tc(X1)

45%

55%

tw(X1H)

Pulse duration, X1 high as a percentage of tc(X1)

45%

55%

MIN

MAX

UNIT

6

ns

6

ns

6.14.3.2.1.5 AUXCLKIN Timing Requirementstf(AUXI)

Fall time, AUXCLKIN

tr(AUXI)

Rise time, AUXCLKIN

tw(AUXL)

Pulse duration, AUXCLKIN low as a percentage of tc(XCI)

45%

55%

tw(AUXH)

Pulse duration, AUXCLKIN high as a percentage of tc(XCI)

45%

55%

6.14.3.2.1.6 APLL Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER

MIN

TYP

MAX

UNIT

5µs + (1024 * (REFDIV + 1) * tc(OSCCLK))us

PLL Lock time
SYS PLL Lock Time(1)(1)

The PLL lock time here defines the typical time that takes for the PLL to lock once PLL is enabled (SYSPLLCTL1[PLLENA]=1).
Additional time to verify the PLL clock using Dual Clock Comparator (DCC) is not accounted here. TI recommends using the latest
example software from C2000Ware for initializing the PLLs. For the system PLL, see InitSysPll() or SysCtl_setClock().

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6.14.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabledover recommended operating conditions (unless otherwise noted)
PARAMETER(1)

MIN

MAX

UNIT

tf(XCO)

Fall time, XCLKOUT

6

nstr(XCO)

Rise time, XCLKOUT

6

ns

tw(XCOL)

Pulse duration, XCLKOUT low

H – 2(2)H + 2(2)ns

tw(XCOH)

Pulse duration, XCLKOUT highH – 2(2)H + 2(2)nsf(XCO)

Frequency, XCLKOUT

50

MHz

MAX

UNIT
MHz

(1)
(2)

A load of 6 pF is assumed for these parameters.
H = 0.5tc(XCO)

6.14.3.2.1.8 Internal Clock Frequencies
MIN
f(SYSCLK)

Frequency, device (system) clocktc(SYSCLK)Period, device (system) clockf(INTCLK)

Frequency, system PLL going into VCO (after REFDIV)

f(VCOCLK)

Frequency, system PLL VCO (before ODIV)f(PLLRAWCLK)Frequency, system PLL output (before SYSCLK divider)f(PLL)

Frequency, PLLSYSCLK

2f(PLL_LIMP)

Frequency, PLL Limp Frequency (1)f(LSP)

Frequency, LSPCLK

tc(LSPCLK)Period, LSPCLKf(OSCCLK)

Frequency, OSCCLK (INTOSC1 or INTOSC2 or XTAL or
X1)

f(EPWM)

Frequency, EPWMCLK

f(HRPWM)

Frequency, HRPWMCLK

f(NPU)

Frequency, NPUCLK

(1)

NOM

2

150

6.67

500

ns

2

20

MHz

220

600

MHz

6

300

MHz

150

MHz

45/(ODIV+1)

MHz

2

150

MHz

6.67

500

ns

See respective clock

MHz
150

MHz

60

150

MHz

37.5

75

MHz

PLL output frequency when OSCCLK is dead (Loss of OSCCLK causes PLL to Limp).

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6.14.3.3 Input Clocks and PLLs

In addition to the internal 0-pin oscillators, three types of external clock sources are supported:• A single-ended 3.3-V external clock. The clock signal should be connected to X1, as shown in Figure 6-11,
with the XTALCR.SE bit set to 1.
• An external crystal. The crystal should be connected across X1 and X2 with its load capacitors connected to
VSS as shown in Figure 6-12.
• An external resonator. The resonator should be connected across X1 and X2 with its ground connected to
VSS as shown in Figure 6-13.
Microcontroller

Microcontroller

VSS

GPIO19GPIO18*X1

X2

GPIO19GPIO18

X1

X2* Available as a
GPIO when X1 isused as a clock+3.3 V

VDD

VSS

Out

3.3-V Oscillator
Gnd

Figure 6-12. External Crystal
Figure 6-11. Single-ended 3.3-V External Clock
Microcontroller

VSS

GPIO19GPIO18

X1

X2

Figure 6-13. External Resonator
6.14.3.4 XTAL Oscillator
6.14.3.4.1 Introduction

The crystal oscillator in this device is an embedded electrical oscillator that, when paired with a compatible
quartz crystal (or a ceramic resonator), can generate the system clock required by the device.
6.14.3.4.2 Overview

The following sections describe the components of the electrical oscillator and crystal.
6.14.3.4.2.1 Electrical Oscillator

The electrical oscillator in this device is a Pierce oscillator. It is a positive feedback inverter circuit that requires atuning circuit in order to oscillate. When this oscillator is paired with a compatible crystal, a tank circuit is formed.
This tank circuit oscillates at the fundamental frequency of the crystal. On this device, the oscillator is designed
to operate in parallel resonance mode due to the shunt capacitor (C0) and required load capacitors (CL). Figure
6-14 illustrates the components of the electrical oscillator and the tank circuit.

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MCU

To Rest of ChipXTAL Oscillator
Buffer
0

Comp
1
XCLKOUT
Circuit[XTAL On]
Rbias

XCLKOUT

Pierce Inverter

GPIO

External

X2

X1

Internal

External

Rd

Crystal

CL1Internal

CL2
GND

GND

Figure 6-14. Electrical Oscillator Block Diagram
6.14.3.4.2.1.1 Modes of Operation

The electrical oscillator in this device has two modes of operation: crystal mode and single-ended mode.
6.14.3.4.2.1.1.1 Crystal Mode of Operation

In the crystal mode of operation, a quartz crystal with load capacitors has to be connected to X1 and X2.
This mode of operation is engaged when [XTAL On] = 1, which is achieved by setting XTALCR.OSCOFF = 0
and XTALCR.SE = 0. There is an internal bias resistor for the feedback loop so an external one should not be
used. Adding an external bias resistor will create a parallel resistance with the internal Rbias, moving the bias
point of operation and possibly leading to clipped waveforms, out-of-specification duty cycle, and reduction in theeffective negative resistance.
In this mode of operation, the resultant clock on X1 is passed through a comparator (Comp) to the rest of thechip. The clock on X1 needs to meet the VIH and VIL of the comparator. See the XTAL Oscillator Characteristics
table for the VIH and VIL requirements of the comparator.
6.14.3.4.2.1.1.2 Single-Ended Mode of Operation

In the single-ended mode of operation, a clock signal is connected to X1 with X2 left unconnected. A quartz
crystal should not be used in this mode.
This mode is enabled when [XTAL On] = 0, which can be achieved by setting XTALCR.OSCOFF = 1 and
XTALCR.SE = 1.

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In this mode of operation, the clock on X1 is passed through a buffer (Buffer) to the rest of the chip. See
the X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal) table for the input
requirements of the buffer.
6.14.3.4.2.1.2 XTAL Output on XCLKOUT

The output of the electrical oscillator that is fed to the rest of the chip can be brought out on XCLKOUT for
observation by configuring the CLKSRCCTL3.XCLKOUTSEL and XCLKOUTDIVSEL.XCLKOUTDIV registers.
See the GPIO Muxed Pins table for a list of GPIOs that XCLKOUT comes out on.
6.14.3.4.2.2 Quartz Crystal

Electrically, a quartz crystal can be represented by an LCR (Inductor-Capacitor-Resistor) circuit. However, unlike
an LCR circuit, crystals have very high Q due to the low motional resistance and are also very underdamped.
Components of the crystal are shown in Figure 6-15 and explained below.

Quartz Crystal
Internal

External

Cm
Rm

C0

CL

Lm

Figure 6-15. Crystal Electrical Representation
Cm (Motional capacitance): Denotes the elasticity of the crystal.
Rm (Motional resistance): Denotes the resistive losses within the crystal. This is not the ESR of the crystal but
can be approximated as such depending on the values of the other crystal components.
Lm (Motional inductance): Denotes the vibrating mass of the crystal.
C0 (Shunt capacitance): The capacitance formed from the two crystal electrodes and stray package
capacitance.
CL (Load capacitance): This is the effective capacitance seen by the crystal at its electrodes. It is external tothe crystal. The frequency ppm specified in the crystal data sheet is usually tied to the CL parameter.
Note that most crystal manufacturers specify CL as the effective capacitance seen at the crystal pins, whilesome crystal manufacturers specify CL as the capacitance on just one of the crystal pins. Check with the crystal
manufacturer for how the CL is specified in order to use the correct values in calculations.
From Figure 6-14, CL1 and CL2 are in series; so, to find the equivalent total capacitance seen by the crystal, thecapacitance series formula has to be applied which simply evaluates to [CL1]/2 if CL1 = CL2.
It is recommended that a stray PCB capacitance be added to this value. 3 pF to 5 pF are reasonable estimates,
but the actual value will depend on the PCB in question.
Note that the load capacitance is a requirement of both the electrical oscillator and crystal. The value chosen has
to satisfy both the electrical oscillator and the crystal.

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The effect of CL on the crystal is frequency-pulling. If the effective load capacitance is lower than the target, thecrystal frequency will increase and vice versa. However, the effect of frequency-pulling is usually very minimal
and typically results in less than 10-ppm variation from the nominal frequency.
6.14.3.4.2.3 GPIO Modes of Operation

On this device, X1 and X2 can be used as GPIO19 and GPIO18, respectively, depending on the operating modeof the XTAL. Refer to the External Oscillator (XTAL) section of the TMS320F28P55x Real-Time Microcontrollers
Technical Reference Manual .
6.14.3.4.3 Functional Operation
6.14.3.4.3.1 ESR – Effective Series Resistance

Effective Series Resistance is the resistive load the crystal presents to the electrical oscillator at resonance. The
higher the ESR, the lower the Q, and less likely the crystal will start up or maintain oscillation. The relationshipbetween ESR and the crystal components is indicated below.
ESR = Rm * 1 + C0
CL

2

(2)

Note that ESR is not the same as motional resistance of the crystal, but can be approximated as such if theeffective load capacitance is much greater than the shunt capacitance.
6.14.3.4.3.2 Rneg – Negative Resistance

Negative resistance is the impedance presented by the electrical oscillator to the crystal. It is the amount ofenergy the electrical oscillator must supply to the crystal to overcome the losses incurred during oscillation. Rneg
depicts a circuit that provides rather than consume energy and can also be viewed as the overall gain of thecircuit.
The generally accepted practice is to have Rneg > 3x ESR to 5x ESR to ensure the crystal starts up under
all conditions. Note that it takes slightly more energy to start up the crystal than it does to sustain oscillation;
therefore, if it can be ensured that the negative resistance requirement is met at start-up, then oscillationsustenance will not be an issue.
Figure 6-16 and Figure 6-17 show the variation between negative resistance and the crystal components for thisdevice. As can be seen from the graphs, the crystal shunt capacitance (C0) and effective load capacitance (CL)greatly influence the negative resistance of the electrical oscillator. Note that these are typical graphs; so, refer toTable 6-5 for minimum and maximum values for design considerations.
6.14.3.4.3.3 Start-up Time

Start-up time is an important consideration when selecting the components of the crystal circuit. As mentioned
in the Rneg – Negative Resistance section, for reliable start-up across all conditions, it is recommended that the
Rneg > 3x ESR to 5x ESR of the crystal.
Crystal ESR and the dampening resistor (Rd) greatly affect the start-up time. The higher the two values, thelonger the crystal takes to start up. Longer start-up times are usually a sign that the crystal and components are
not a correct match.
Refer to Crystal Oscillator Specifications for the typical start-up times. Note that the numbers specified here are
typical numbers provided for guidance only. Actual start-up time depends heavily on the crystal in question andthe external components.
6.14.3.4.3.3.1 X1/X2 Precondition

On this device, the GPIO19/18 alternate functionality on X1/X2 can be used to speed up the start-up time of thecrystal if needed. This functionality is achieved by preconditioning the load capacitors CL1 and CL2 to a known
state before the XTAL is turned on. See the TMS320F28P55x Real-Time Microcontrollers Technical Reference
Manual for details.

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6.14.3.4.3.4 DL – Drive Level

Drive level refers to how much power is provided by the electrical oscillator and dissipated by the crystal. The
maximum drive level specified in the crystal manufacturer’s data sheet is usually the maximum the crystal candissipate without damage or significant reduction in operating life. On the other hand, the drive level specified
by the electrical oscillator is the maximum power it can provide. The actual power provided by the electricaloscillator is not necessarily the maximum power and depends on the crystal and board components.
For cases where the actual drive level from the electrical oscillator exceeds the maximum drive levelspecification of the crystal, a dampening resistor (Rd) should be installed to limit the current and reduce thepower dissipated by the crystal. Note that Rd reduces the circuit gain; and therefore, the actual value to use
should be evaluated to make sure all other conditions for start-up and sustained oscillation are met.
6.14.3.4.4 How to Choose a Crystal

Using Crystal Oscillator Specifications as a reference:
1. Pick a crystal frequency (for example, 20 MHz).
2. Check that the ESR of the crystal <=50 Ω per specifications for 20 MHz.
3. Check that the load capacitance requirement of the crystal manufacturer is within 6 pF and 12 pF per
specifications for 20 MHz.
• As mentioned, CL1 and CL2 are in series; so, provided CL1 = CL2, effective load capacitance CL =[CL1]/2.
• Adding board parasitics to this results in CL = [CL1]/2 + Cstray
4. Check that the maximum drive level of the crystal >= 1 mW. If this requirement is not met, a dampening
resistor Rd can be used. Refer to DL – Drive Level on other points to consider when using Rd.
6.14.3.4.5 Testing

It is recommended that the user have the crystal manufacturer completely characterize the crystal with theirboard to ensure the crystal always starts up and maintains oscillation.
Below is a brief overview of some measurements that can be performed:
Due to how sensitive the crystal circuit is to capacitance, it is recommended that scope probes not be connected
to X1 and X2. If scope probes must be used to monitor X1/X2, an active probe with less than 1-pF input
capacitance should be used.
Frequency
1. Bring out the XTAL on XCLKOUT.
2. Measure this frequency as the crystal frequency.
Negative Resistance
1.
2.
3.
4.

Bring out the XTAL on XCLKOUT.
Place a potentiometer in series with the crystal between the load capacitors.
Increase the resistance of the potentiometer until the clock on XCLKOUT stops.
This resistance plus the crystal’s actual ESR is the negative resistance of the electrical oscillator.

Start-Up Time
1. Turn off the XTAL.
2. Bring out the XTAL on XCLKOUT.
3. Turn on the XTAL and measure how long it takes the clock on XCLKOUT to stay within 45% and 55% duty
cycle.

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6.14.3.4.6 Common Problems and Debug Tips

Crystal Fails to Start Up• Go through the How to Choose a Crystal section and make sure there are no violations.
Crystal Takes a Long Time to Start Up• If a dampening resistor Rd is installed, it is too high.
• If no dampening resistor is installed, either the crystal ESR is too high or the overall circuit gain is too low due
to high load capacitance.
6.14.3.4.7 Crystal Oscillator Specifications
6.14.3.4.7.1 Crystal Oscillator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

UNIT

f = 10 MHz

4ms

f = 20 MHz

ESR MAX = 50 Ω
CL1 = CL2 = 24 pF
C0 = 7 pF

2

ms

Start-uptime(1)

Crystal drive level (DL)

(1)

MAX

ESR MAX = 110 Ω
CL1 = CL2 = 24 pF
C0 = 7 pF

1mW

Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize theapplication with the chosen crystal.

6.14.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements

For the Crystal Equivalent Series Resistance (ESR) Requirements table:
1. Crystal shunt capacitance (C0) should be less than or equal to 7 pF.
2. ESR = Negative Resistance/3
Table 6-5. Crystal Equivalent Series Resistance (ESR) Requirements
CRYSTAL FREQUENCY (MHz)MAXIMUM ESR (Ω)(CL1 = CL2 = 12 pF)

MAXIMUM ESR (Ω)(CL1 = CL2 = 24 pF)

10

55

110

12

50

95

14

50

90

16

45

75

18

45

65

20

45

50

Negative Resistance vs. 10MHz Crystal
3000
C0 (pF)13
5
7
9Rneg (Ohms)

2500
2000
1500
1000
500
0
2

4

6

8

10

12

14

16

Effective CL (pF)

Figure 6-16. Negative Resistance Variation at 10 MHz

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Negative Resistance vs. 20MHz Crystal
1600
C0 (pF)
1
3
5
7
9

1400

Rneg (Ohms)

1200
1000
800
600
400
200
0
2

4

6

8

10

12

14

16

Effective CL (pF)

Figure 6-17. Negative Resistance Variation at 20 MHz
6.14.3.4.7.3 Crystal Oscillator Parameters
CL1, CL2

Load capacitance

C0

Crystal shunt capacitance104

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MIN

MAX

UNIT

12

24

pF

7

pF

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6.14.3.5 Internal Oscillators

To reduce production board costs and application development time, all devices contain two independent internal
oscillators, referred to as INTOSC1 and INTOSC2. By default, INTOSC2 is set as the source for the systemreference clock (OSCCLK) and INTOSC1 is set as the backup clock source.
Applications requiring tighter SCI baud rate matching can use the SCI baud tuning example(baud_tune_via_uart) available in C2000Ware.
6.14.3.5.1 INTOSC Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER

fINTOSCfINTOSC-

PACKAGESUFFIXPART

Frequency, INTOSC1 and
INTOSC2(1)

All

All

STABILITY

Frequency stability at room
temperature

All

All

tINTOSC-ST

Start-up and settling time

All

All

(1)

TEST
CONDITIONSMIN TYPMAX UNIT-40°C to 125°C

9.82 (–1.8%)

10 10.1 (1.0%)-30°C to 90°C

9.86 (–1.4%)

10 10.1 (1.0%) MHz-10°C to 85°C

9.9 (–1.0%)

10 10.1 (1.0%)

30°C, Nominal VDD

±0.1

%
20

µs

INTOSC frequency may shift due to the thermal and mechanical stress of solder reflow. A post-reflow bake can restore the unit to its
original data sheet performance.

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6.14.4 Flash Parameters
Table 6-6 lists the minimum required Flash wait states with different clock sources and frequencies. Wait state is
the value set in register FRDCNTL[RWAIT].
Table 6-6. Minimum Required Flash Wait States with Different Clock Sources and Frequencies(1)

CPUCLK (MHz)

Wait States(FRDCNTL[RWAIT](1))

120 < CPUCLK ≤ 150

380 < CPUCLK ≤ 120

2

0 < CPUCLK ≤ 80

1

Minimum required FRDCNTL[RWAIT] is 1, RWAIT=0 is not supported.

The F28P55x devices have a 128-bit prefetch buffer that provides high flash code execution efficiency acrosswait states. Figure 6-18 and Figure 6-19 illustrate typical efficiency across wait-state settings compared toprevious-generation devices with a 64-bit prefetch buffer. Wait-state execution efficiency with a prefetch buffer
will depend on how many branches are present in application software. Two examples of linear code andif-then-else code are provided.
100%

100%
95%

90%

Efficiency (%)

Efficiency (%)

90%
80%
70%
60%
Flash with 64-Bit Prefetch
Flash with 128-Bit Prefetch

50%

85%
80%
75%
Flash with 64-Bit Prefetch
Flash with 128-Bit Prefetch

70%
65%

40%

60%

30%

55%
0

1

2

3

Wait State

4

5

0

1

2

3

4

Wait State

D005

Figure 6-18. Application Code With Heavy 32-Bit
Floating-Point Math Instructions

5
D006

Figure 6-19. Application Code With 16-Bit If-Else
Instructions

Note
The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit
word may only be programmed once per write/erase cycle.

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6.14.4.1 Flash Parameters
PARAMETER
Program Time(1)Erase Time(2) (3) at < 25 cycles

Erase Time(2) (3) at 1000 cycles

Erase Time(2) (3) at 2000 cycles

Erase Time(2) (3) at 20K cycles

Nwec

(2)
(3)
(4)

TYP

MAX

UNIT

62.5

625

µs

2KB (Sector)

8

80

µs

2KB (Sector)

15

55

ms

64KB

17

61

ms

128KB

18

66

ms

256KB

21

78

ms

2KB (Sector)

25

130

ms

64KB

28

143

ms

128KB

30

157

ms

256KB

35

183

ms

2KB (Sector)

30

221

ms

64KB

33

243

ms

128KB

36

265

ms

256KB

42

310

ms

2KB (Sector)

120

1003

ms

64KB

132

1102

ms

128KB

145

1205

ms

256KB

169

1410

ms

100000cyclesWrite/Erase Cycles per Bank (4)tretention Data retention duration at TJ = 85oC
(1)

MIN
128 data bits + 16 ECC bits

20

years

Program time is at the maximum device frequency. Program time includes overhead of the flash state machine but does not include
the time to transfer the following into RAM:
• Code that uses flash API to program the flash• Flash API itself• Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
Erase time includes Erase verify by the CPU.
The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
The combined total of bank and sector write/erase cycles is limited to this number

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6.14.5 RAM Specifications
All volatile memory (RAM and ROM) on the F28P55x device is 0 Wait-state for both reads and writes, meaning
the memory operates at the same speed as SYSCLK. Table 6-7 and Table 6-8 summarize the characteristics ofthe different RAM instances on the device.
Table 6-7. RAM Parameters – F28P55xSJ
RAM TYPE

SIZE

FETCH
TIME(1)(CYCLES)READ
TIME(1)(CYCLES)STORE TIME(CYCLES)

BUS WIDTH

LS RAM

64KB

2

2

1

16/32 bits

2

0

No

M0

2KB

2

2

1

16/32 bits

1

0

No

M1

2KB

2

2

1

16/32 bits

1

0

No

GS RAM

64KB

2

2

1

16/32 bits

3

0

No

CLA-to-CPU
Message
RAM

256B

2

2

1

16/32 bits

2

0

No

CPU-to-CLA
Message
RAM

256B

2

2

1

16/32 bits

2

0

No

CLA-to-DMA
Message
RAM

256B

2

2

1

16/32 bits

3

0

No

DMA-to-CLA
Message
RAM

256B

2

2

1

16/32 bits

3

0

No

(1)

NUMBER OF NUMBER OF
BUSES
WAIT
AVAILABLE
STATESBURSTACCESS

Without arbitration between read/write/fetch. Access completes in 2 cycles; otherwise, arbitration priority (Write/Read/Fetch) is
followed.

Table 6-8. RAM Parameters – F28P55xSG
RAM TYPE

SIZE

FETCH
TIME(1)(CYCLES)READ
TIME(1)(CYCLES)STORE TIME(CYCLES)

BUS WIDTHNUMBER OF NUMBER OF
BUSES
WAIT
AVAILABLE
STATESLS RAM

64KB

2

2

1

16/32 bits

2

0

No

M0

2KB

2

2

1

16/32 bits

1

0

No

M1

2KB

2

2

1

16/32 bits

1

0

No

GS RAM

32KB

2

2

1

16/32 bits

2

0

No

CLA-to-CPU
Message
RAM

256B

2

2

1

16/32 bits

2

0

No

CPU-to-CLA
Message
RAM

256B

2

2

1

16/32 bits

2

0

No

CLA-to-DMA
Message
RAM

256B

2

2

1

16/32 bits

3

0

No

DMA-to-CLA
Message
RAM

256B

2

2

1

16/32 bits

3

0

No

BURST
ACCESS(1)

Without arbitration between read/write/fetch. Access completes in 2 cycles; otherwise, arbitration priority (Write/Read/Fetch) is
followed.

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6.14.6 ROM Specifications
All volatile memory (RAM and ROM) on the F28P55x device is 0 Wait-state for both reads and writes, meaning
the memory operates at the same speed as SYSCLK. Table 6-9 summarizes the aspects of the ROM instanceson the device.
Table 6-9. ROM Parameters – F28P55xSJ and F28P55xSG
ROM TYPE

SIZE

FETCH
TIME(1)(CYCLES)READ
TIME(1)(CYCLES)STORE TIME(CYCLES)

BUS WIDTH

Boot ROM +Secure ROM

96KB

2

2

1

16/32 bits

1

0

No

CLA Data
ROM

8KB

2

2

1

16/32 bits

2

0

No

(1)

NUMBER OF NUMBER OF
BUSES
WAIT
AVAILABLE
STATESBURSTACCESS

Without arbitration between read/write/fetch. Access completes in 2 cycles; otherwise, arbitration priority (Write/Read/Fetch) is
followed.

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6.14.7 Emulation/JTAGThe JTAG (IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture) port has
four dedicated pins: TMS, TDI, TDO, and TCK. The cJTAG (IEEE Standard 1149.7-2009 for Reduced-Pin andEnhanced-Functionality Test Access Port and Boundary-Scan Architecture) port is a compact JTAG interface
requiring only two pins (TMS and TCK), which allows other device functionality to be muxed to the traditional
GPIO35 (TDI) and GPIO37 (TDO) pins.
Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the JTAG
header is smaller than 6 inches (15.24 cm), and no other devices are present on the JTAG chain. Otherwise,
each signal should be buffered. Additionally, for most JTAG debug probe operations at 10 MHz, no series
resistors are needed on the JTAG signals. However, if high emulation speeds are expected (35 MHz or so), 22-Ω
resistors should be placed in series on each JTAG signal.
The PD (Power Detect) pin of the JTAG debug probe header should be connected to the board's 3.3-V supply.
Header GND pins should be connected to board ground. TDIS (Cable Disconnect Sense) should also beconnected to board ground. The JTAG clock should be looped from the header TCK output pin back to the
RTCK input pin of the header (to sense clock continuity by the JTAG debug probe). This MCU does not support
the EMU0 and EMU1 signals that are present on 14-pin and 20-pin emulation headers. These signals should
always be pulled up at the emulation header through a pair of board pullup resistors ranging from 2.2 kΩ to
4.7 kΩ (depending on the drive strength of the debugger ports). Typically, a 2.2-kΩ value is used.
Header pin RESET is an open-drain output from the JTAG debug probe header that enables board components
to be reset through JTAG debug probe commands (available only through the 20-pin header). Figure 6-20 shows
how the 14-pin JTAG header connects to the MCU’s JTAG port signals. Figure 6-21 shows how to connect tothe 20-pin JTAG header. The 20-pin JTAG header pins EMU2, EMU3, and EMU4 are not used and should begrounded.
For more information about hardware breakpoints and watchpoints, see Hardware Breakpoints and Watchpoints
in CCS for C2000 devices.
For more information about JTAG emulation, see the XDS Target Connection Guide.
Note
JTAG Test Data Input (TDI) is the default mux selection for the pin. The internal pullup is disabled bydefault. If this pin is used as JTAG TDI, the internal pullup should be enabled or an external pullup
added on the board to avoid a floating input. In the cJTAG option, this pin can be used as GPIO.
JTAG Test Data Output (TDO) is the default mux selection for the pin. The internal pullup is disabled
by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving thispin floating. The internal pullup should be enabled or an external pullup added on the board to avoid afloating GPIO input. In the cJTAG option, this pin can be used as GPIO.

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Distance between the header and the target
should be less than 6 inches (15.24 cm).
3.3 V
2.2 kΩ
TMS

10 kΩ

(A)

MCU

1

3.3 V

TDO

100 Ω

10 kΩ

(A)

3.3 V

TDI

TDIS

PD

KEY

TDO

GND

9

RTCK

GND 10

11

TCK

GND 12

13

EMU0

EMU1 1457TCK
4.7 kΩ
3.3 V
A.

TRST

3

TDI

2

TMS

3.3 V

4

GND

6
8

4.7 kΩ
3.3 V

TDI and TDO connections are not required for cJTAG option and these pins can be used as GPIOs instead.

Figure 6-20. Connecting to the 14-Pin JTAG Header
Distance between the header and the target
should be less than 6 inches (15.24 cm).
3.3 V
2.2 kΩ

MCU

TDI

TMS

TRST

3

TDI

TDIS 4

5

PD

KEY 6

7

TDO

GND 8

9

RTCK

GND 10

11

TCK

GND 12

13

EMU0

EMU1 14

15RESET

GND 1617

EMU2

EMU3 18

19
A low pulse from the JTAG debug probe
can be tied with other reset sources
to reset the board.
GND

EMU4

GND 20

3.3 V
10 kΩ

(A)

3.3 V

TDO

10 kΩ

(A)

100 Ω
3.3V

TCK
4.7 kΩ
3.3 V
Open
Drain

A.

2

1

TMS

GND

4.7 kΩ
3.3 V

GND

TDI and TDO connections are not required for cJTAG option and these pins can be used as GPIOs instead.

Figure 6-21. Connecting to the 20-Pin JTAG Header

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6.14.7.1 JTAG Electrical Data and Timing
6.14.7.1.1 JTAG Timing Requirements
NO.

MIN

MAX

UNIT

1

tc(TCK)

Cycle time, TCK

66.66

ns

1a

tw(TCKH)

Pulse duration, TCK high (40% of tc)

26.66

ns

1b

tw(TCKL)

Pulse duration, TCK low (40% of tc)

26.66

ns

tsu(TDI-TCKH)

Input setup time, TDI valid to TCK high7tsu(TMS-TCKH)

Input setup time, TMS valid to TCK high7th(TCKH-TDI)

Input hold time, TDI valid from TCK high7th(TCKH-TMS)

Input hold time, TMS valid from TCK high

7

3

4

ns

ns

6.14.7.1.2 JTAG Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
2

PARAMETER
td(TCKL-TDO)

Delay time, TCK low to TDO valid

MIN

MAX

UNIT

6

20

ns

6.14.7.1.3 JTAG Timing Diagram
1
1a

1b

TCK
2
TDO
3

4

TDI/TMS

Figure 6-22. JTAG Timing

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6.14.7.2 cJTAG Electrical Data and Timing
6.14.7.2.1 cJTAG Timing Requirements
NO.

MIN

MAX

UNIT

1

tc(TCK)

Cycle time, TCK

100

ns

1a

tw(TCKH)

Pulse duration, TCK high (40% of tc)

40

ns

1b

tw(TCKL)

Pulse duration, TCK low (40% of tc)

40

nstsu(TMS-TCKH)

Input setup time, TMS valid to TCK high7nstsu(TMS-TCKL)

Input setup time, TMS valid to TCK low

7nsth(TCKH-TMS)

Input hold time, TMS valid from TCK high2nsth(TCKL-TMS)

Input hold time, TMS valid from TCK low

2

ns

3

4

6.14.7.2.2 cJTAG Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.

PARAMETER

2td(TCKL-TMS)

Delay time, TCK low to TMS valid

5tdis(TCKH-TMS)

Delay time, TCK high to TMS disable

MIN

MAX

UNIT

6

20

ns

20

ns

6.14.7.2.3 cJTAG Timing Diagram
1
1a
TCK

TMS

1b
3

4

3

4

TMS Input

TMS Input

2

5

TMS Output

Figure 6-23. cJTAG Timing

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6.14.8 GPIO Electrical Data and Timing
The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO pinsare configured as inputs. For specific inputs, the user can also select the number of input qualification cycles tofilter unwanted noise glitches.
Many GPIOs have mux options for Output X-BAR which allows an assortment of internal signals to be routed toa GPIO. All of the GPIOs are connected to each Input X-BAR which can route the GPIO's high or low state todifferent IP blocks, such as the ADCs, eCAPs, ePWMs, and external interrupts. For more details, see the X-BAR
chapter in the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual.
6.14.8.1 GPIO – Output Timing
6.14.8.1.1 General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
tr(GPO)tf(GPO)

tfGPO

(1)

Rise time, GPIO switching low to highFall time, GPIO switching high to low

Toggling frequency, GPIO pins

MAX

UNIT

All GPIOs

MIN

6(1)

ns

All GPIOs

6(1)

ns

All GPIOs not listed
below

50

GPIO 2, 3, 9, and 32

40

GPIO 23 and 41

25

MHz

Rise time and fall time vary with load. These values assume a 6-pF load.

6.14.8.1.2 General-Purpose Output Timing Diagram
GPIO
tr(GPO)tf(GPO)

Figure 6-24. General-Purpose Output Timing

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6.14.8.2 GPIO – Input Timing
6.14.8.2.1 General-Purpose Input Timing Requirements
MIN
tw(SP)

Sampling periodtw(IQSW)

Input qualifier sampling window

tw(GPI) (2)Pulse duration, GPIO low/high

(1)
(2)

MAX

UNIT

QUALPRD = 0

1tc(SYSCLK)

cyclesQUALPRD ≠ 0

2tc(SYSCLK) * QUALPRD

cyclestw(SP) * (n(1) – 1)

cyclesSynchronous mode

2tc(SYSCLK)

cyclesWith input qualifiertw(IQSW) + tw(SP) + 1tc(SYSCLK)

cycles"n" represents the number of qualification samples as defined by GPxQSELn register.
For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.

6.14.8.2.2 Sampling Mode(A)
GPIO Signal

GPxQSELn = 1,0 (6 samples)

1

1

0

0

0

0

0

0

0

1

tw(SP)

0

0

0

1

1

1

1

tw(IQSW)

1

1

1

1

Sampling Period determinedby GPxCTRL[QUALPRD]

Sampling Window

1(SYSCLK cycle * 2 * QUALPRD) * 5

(B)

(C)

SYSCLKQUALPRD = 1(SYSCLK/2)(D)

Output From
Qualifier

A.

B.
C.
D.

This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n", the qualification sampling period in 2n
SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be sampled).
The qualification period selected through the GPxCTRL register applies to groups of eight GPIO pins.
The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or greater. In other words,
the inputs should be stable for (5 × QUALPRD × 2) SYSCLK cycles. This would ensure 5 sampling periods for detection to occur.
Because external signals are driven asynchronously, an 13-SYSCLK-wide pulse ensures reliable recognition.

Figure 6-25. Sampling Mode

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6.14.8.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.
Sampling frequency = SYSCLK/(2 × QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLK, if QUALPRD = 0
Sampling period = SYSCLK cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the previous equations, SYSCLK cycle indicates the time period of SYSCLK.
Sampling period = SYSCLK cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of thesignal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0
SYSCLK

GPIOxntw(GPI)

Figure 6-26. General-Purpose Input Timing

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6.14.9 Interrupts
The C28x CPU has fourteen peripheral interrupt lines. Two of them (INT13 and INT14) are connected directly
to CPU timers 1 and 2, respectively. The remaining twelve are connected to peripheral interrupt signals throughthe enhanced Peripheral Interrupt Expansion (ePIE) module. The ePIE multiplexes up to sixteen peripheral
interrupts into each CPU interrupt line. It also expands the vector table to allow each interrupt to have its own
ISR. This allows the CPU to support a large number of peripherals.
An interrupt path is divided into three stages—the peripheral, the ePIE, and the CPU. Each stage has its
own enable and flag registers. This system allows the CPU to handle one interrupt while others are pending,
implement and prioritize nested interrupts in software, and disable interrupts during certain critical tasks.
Figure 6-27 shows the interrupt architecture for this device.
TIMER0

LPM Logic
WD

GPIO0
to
GPIOx

Input
X-BAR

LPMINT

TINT0

WAKEINTNMI module

WDINT

INPUTXBAR4

XINT1 Control

INPUTXBAR5

XINT2 Control

INPUTXBAR6

XINT3 Control

INPUTXBAR13

XINT4 Control

INPUTXBAR14

XINT5 Control

Peripherals
See ePIE Table

NMI

CPU
ePIE

INT1
to
INT12

TIMER1INT13

TIMER2

INT14

Figure 6-27. Device Interrupt Architecture

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6.14.9.1 External Interrupt (XINT) Electrical Data and Timing

For an explanation of the input qualifier parameters, see the General-Purpose Input Timing Requirements table.
6.14.9.1.1 External Interrupt Timing Requirements
MIN
tw(INT)

Pulse duration, INT input low/high

MAX

UNIT

Synchronous

2tc(SYSCLK)

cyclesWith qualifiertw(IQSW) + tw(SP) + 1tc(SYSCLK)

cycles6.14.9.1.2 External Interrupt Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
td(INT)(1)

Delay time, INT low/high to interrupt-vector fetch(1)

MIN

MAX

UNIT

tw(IQSW) + 14tc(SYSCLK)

tw(IQSW) + tw(SP) + 14tc(SYSCLK)

cyclesThis assumes that the ISR is in a single-cycle memory.

6.14.9.1.3 External Interrupt Timingtw(INT)
XINT1, XINT2, XINT3,
XINT4, XINT5
td(INT)
Address bus(internal)

Interrupt Vector

Figure 6-28. External Interrupt Timing

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6.14.10 Low-Power Modes
This device has HALT, IDLE and STANDBY as clock-gating low-power modes.
Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the
Low-Power Modes section of the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual.
6.14.10.1 Clock-Gating Low-Power Modes

IDLE and HALT modes on this device are similar to those on other C28x devices. Table 6-10 describes the effecton the system when any of the clock-gating low-power modes are entered.
Table 6-10. Effect of Clock-Gating Low-Power Modes on the Device
MODULES/
CLOCK DOMAIN

IDLE

STANDBY

HALT

SYSCLK

Active

Gated

Gated

CPUCLK

Gated

Gated

Gated

Clock to modules connected
to PERx.SYSCLKActive

Gated

Gated

WDCLK

ActiveActiveGated if CLKSRCCTL1.WDHALTI = 0

PLLPoweredPoweredSoftware must power down PLL before entering HALT.

INTOSC1

PoweredPoweredPowered down if CLKSRCCTL1.WDHALTI = 0

INTOSC2PoweredPoweredPowered down if CLKSRCCTL1.WDHALTI = 0

Flash(1)PoweredPoweredPoweredXTAL(2)

PoweredPoweredPowered(1)(2)

The Flash module is not powered down by hardware in any LPM. It may be powered down using software if required by theapplication.
The XTAL is not powered down by hardware in any LPM. It may be powered down by software setting the XTALCR.OSCOFF bit to 1.
This can be done at any time during the application if the XTAL is not required.

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6.14.10.2 Low-Power Mode Wake-up Timing

For an explanation of the input qualifier parameters, see the General-Purpose Input Timing Requirements table.
6.14.10.2.1 IDLE Mode Timing Requirements
MIN
tw(WAKE)

Pulse duration, external wake-up signal

Without input qualifier
With input qualifier2tc(SYSCLK)
2tc(SYSCLK) + tw(IQSW)

MAX

UNIT
cycles6.14.10.2.2 IDLE Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONS
From Flash (active state)

Delay time, external wake signal toprogram execution resume(1)td(WAKE-IDLE)

MIN

MAX

UNIT

40tc(SYSCLK) cycles

With input qualifier

40tc(SYSCLK) + tw(WAKE) cycles

Without input qualifier

From RAM(1)

Without input qualifier

25tc(SYSCLK) cycles

With input qualifier

25tc(SYSCLK) + tw(WAKE) cycles

This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggeredby the wake-up signal) involves additional latency.

6.14.10.2.3 IDLE Entry and Exit Timing Diagramtd(WAKE-IDLE)
Address/Data(internal)
XCLKOUT
tw(WAKE)
WAKE

A.

(A)

WAKE can be any enabled interrupt, WDINT or XRSn. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum)is needed before the wake-up signal could be asserted.

Figure 6-29. IDLE Entry and Exit Timing Diagram120

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6.14.10.2.4 STANDBY Mode Timing Requirements
MIN
tw(WAKE-INT)(1)

Pulse duration, external
wake-up signal

QUALSTDBY = 0 | 2tc(OSCCLK)

3tc(OSCCLK)QUALSTDBY > 0 |(2 + QUALSTDBY)tc(OSCCLK) (1)(2 + QUALSTDBY) * tc(OSCCLK)

MAX

UNIT
cyclesQUALSTDBY is a 6-bit field in the LPMCR register.

6.14.10.2.5 STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
td(IDLE-XCOS)TEST CONDITIONSMAXDelay time, IDLE instruction executed to
XCLKOUT stopUNIT

16tc(INTOSC1) cycles

td(WAKE-STBY) Delay time, external wake signal to program
execution resume(1)td(WAKE-STBY)
(1)

MIN

Wakeup from flash(Flash module inactive state)

175tc(SYSCLK) + tw(WAKE-INT) cycles

Wakeup from RAM

3tc(OSC) + 15tc(SYSCLK) + tw(WAKE-INT) cycles

This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggeredby the wake-up signal) involves additional latency.

6.14.10.2.6 STANDBY Entry and Exit Timing Diagram
(C)

(A)
(B)
DeviceStatusSTANDBY(F)(D)(E)(G)

STANDBY

Normal Execution

Flushing Pipeline
Wake-up
Signaltw(WAKE-INT)
td(WAKE-STBY)OSCCLKXCLKOUT
td(IDLE-XCOS)

A.
B.
C.
D.
E.

F.
G.

IDLE instruction is executed to put the device into STANDBY mode.
The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off.
This delay enables the CPU pipeline and any other pending operations to flush properly.
Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. Afterthe IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
The external wake-up signal is driven active.
The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and thedevice may not exit low-power mode for subsequent wake-up pulses.
After a latency period, the STANDBY mode is exited.
Normal execution resumes. The device will respond to the interrupt (if enabled).

Figure 6-30. STANDBY Entry and Exit Timing Diagram

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6.14.10.2.7 HALT Mode Timing Requirements
MIN

MAX

UNIT

tw(WAKE-GPIO)

Pulse duration, GPIO wake-up signal(1)toscst + 2tc(OSCCLK)

cyclestw(WAKE-XRS)

Pulse duration, XRS wake-up signal(1)toscst + 8tc(OSCCLK)

cycles(1)

For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on
circuit/layout external to the device. See the Crystal Oscillator (XTAL) section for more information. For applications using INTOSC1
or INTOSC2 for OSCCLK, see the Internal Oscillators section for toscst. Oscillator start-up time does not apply to applications using asingle-ended crystal on the X1 pin, as it is powered externally to the device.

6.14.10.2.8 HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
td(IDLE-XCOS)MINDelay time, IDLE instruction executed to XCLKOUT
stop

MAX

UNIT

16tc(INTOSC1)

cyclesDelay time, external wake signal end to CPU1 program
execution resumetd(WAKE-HALT)

122

Wakeup from Flash - Flash module in active state75tc(OSCCLK)

Wakeup from RAM

75tc(OSCCLK)

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6.14.10.2.9 HALT Entry and Exit Timing Diagram
(C)

(A)
(B)
DeviceStatus(F)(D)(E)

HALT

(G)

HALT

Flushing Pipeline

NormalExecution

GPIOn
td(WAKE-HALT)
tw(WAKE-GPIO)OSCCLK
Oscillator Start-up TimeXCLKOUT
td(IDLE-XCOS)

A.
B.
C.

D.

E.

F.
G.
H.

IDLE instruction is executed to put the device into HALT mode.
The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. Thisdelay enables the CPU pipeline and any other pending operations to flush properly.
Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock
source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes very little power. It is possible
to keep the internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT MODE. This is done by writing 1 to
CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before thewake-up signal could be asserted.
When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up
sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean
clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wake-up procedure,care should be taken to maintain a low noise environment before entering and during HALT mode.
The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and thedevice may not exit low-power mode for subsequent wake-up pulses.
When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The HALT mode is now
exited.
Normal operation resumes.
The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.

Figure 6-31. HALT Entry and Exit Timing Diagram

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6.15 Analog Peripherals
The analog subsystem module is described in this section.
The analog modules on this device include the Analog-to-Digital Converter (ADC), temperature sensor,
Comparator Subsystem (CMPSS), Programmable Gain Amplifier (PGA), and buffered Digital-to-Analog
Converter (DAC).
The analog subsystem has the following features:••

Flexible voltage references– The ADCs are referenced to VREFHIx and VSSA pins
• VREFHIx pin voltage can be driven in externally or can be generated by an internal bandgap voltage
reference• The internal voltage reference range can be selected to be 0 V to 3.3 V or 0 V to 2.5 V– The buffered DACs are referenced to VREFHIx and VSSA
– The comparator DACs are referenced to VDDA and VSSA
Flexible pin usage– Buffered DAC outputs, comparator subsystem inputs, and digital inputs (AIOs)/outputs (AGPIOs) are
multiplexed with ADC inputs– Internal connection to VREFLO on all ADCs for offset self-calibration

6.15.1 Block Diagram
The following analog subsystem block diagrams show the connections between the different integrated analog
modules to the device pins. These pins fall into two categories: analog module inputs/outputs and referencepins.
The reference pins, VREFHI and VREFLO, can be used to supply an external voltage reference to theassociated ADCs. VREFHI can also be used to supply the voltage reference to buffered DAC. The choiceof reference is configurable per module for each CMPSS or buffered DAC; the selection is made using themodule's configuration registers.
Some analog pins support digital functionality through muxed AIOs and AGPIOs. AIOs only support digital input
functionality, while AGPIOs support full digital input and output functionality.
The following notes apply to all packages:• Not all analog pins are available on all devices. See the device data manual to determine which pins areavailable.
• See the device data manual to determine the allowable voltage range for VREFHI and VREFLO.
• An external capacitor is required on the VREFHI pins. See the device data manual for the specific value
required.
Figure 6-32 shows the Analog Subsystem Block Diagram for the 128-/80-pin TQFP, the 64-pin LQFP, and the56-pin VQFN.
Figure 6-33 shows the Analog Subsystem Block Diagram for the 100-pin LQFP.
Figure 6-34 shows the general overview of the analog group connections.
The analog pins and internal connections are given in Analog Pins and Internal Connections. Analog Signal
Descriptions lists descriptions of analog signals.

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VREFHI

CMP1_HP

VREFLO
CMP1_HN
Reference Circuit
Misc. Analog

CMPSS Module
CTRIP1HCTRIPOUT1H

CMP1_LN

DAC12

Vref

DigitalFilterCTRIP1LCTRIPOUT1L

CMP2_HP
HPMXSEL3/HNMXSEL0 /LPMXSEL3/LNMXSEL0HPMXSEL4//LPMXSEL4/

HPMXSEL2//LPMXSEL2/

HPMXSEL0//LPMXSEL0//LPMXSEL5/
AGPIO
AGPIO
AGPIO
AIO
AIO
AIO

HPMXSEL2/HNMXSEL0/LPMXSEL2/LNMXSEL0HPMXSEL1//LPMXSEL1/
HPMXSEL0/HNMXSEL1/LPMXSEL0/LNMXSEL1/LPMXSEL4/
HPMXSEL4/HPMXSEL0//LPMXSEL0/
HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0HPMXSEL4//LPMXSEL4/

12-bits
REFLO

CMP2_LN

HPMXSEL5//LPMXSEL5/

HPMXSEL2//LPMXSEL2/

CMP3_HP/LPMXSEL0/

CMP3_LN

Reference Circuit

DigitalFilterCTRIP2LCTRIPOUT2L

Comparator Subsystem 3
DigitalFilterVDDA

CTRIP3HCTRIPOUT3H

DAC12DigitalFilterCTRIP3L
CTRIPOUT3L

Comparator Subsystem 4
DigitalFilterVDDA

CTRIP4H
CTRIPOUT4H

CMP3_LP
CMP4_HP

REFLO
CMP4_HNDAC12ADC Inputs
C0 to C30

HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0HPMXSEL2//LPMXSEL2/
HPMXSEL4/HPMXSEL5/CTRIP2HCTRIPOUT2H

DAC12

REFHI

Input MUXHPMXSEL0/

AGPIO
AGPIO
AGPIO
AIO
AIO
AIO

DAC12

ADC-B
12-bits

Analog Interconnect

CMP2_LP

CMP3_HN

ADC Inputs
B0 to B30

Comparator Subsystem 2
DigitalFilterVDDA
DAC12HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1CMPSS3 Input MUX

B4/C8
C14
C1/E11/PGA3_INP
A8/B0/C11(128-pin) B11/D16/E16
A7/C3/D12/B30/E30

ADC-A

Input MUX

AGPIO
AGPIO
AGPIO
AIO
AIO
AIO

Analog Interconnect

HPMXSEL5/CMPSS2 Input MUX(64/80/128-pin) B2/C6/E12
B3/PGA2_INP
A14/B14/C4/PGA1_OUT
B12/C2/PGA2_INM
A3
A0/B15/C15/DACA_OUT

ADC Inputs
A0 to A30

HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1CMPSS1 Input MUX

A10/B1/C10
A9
A12
A5

CMP2_HN
REFHI
Input MUX

A15
A1/B7/D11/CMP1_DACL(64/80/128-pin) A6/D14/E14
A2/B6/C9/PGA1_INP
A11/B10/C0/PGA2_OUT(128-pin) B5/D15/E15

CMPSS Input MUXTemp Sensor

CMP1_LPREFLO

ADC Module
Buffered DAC Module

DAC12

ANAREFSEL

Temp Sensor(C12)Comparator Subsystem 1
DigitalFilter
VDDA

REFHI

CMP4_LN

ADC-C

CMP4_LP

DAC12DigitalFilterCTRIP4L
CTRIPOUT4L

12-bits/LPMXSEL4//LPMXSEL5/REFLO

HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
AGPIO
AGPIO
AGPIO
CMPSS4 Input MUX

AIO
AIO
AIO

REFHI
Input MUXADC Inputs
D0 to D30

ADC-D
12-bits
REFLO

REFHI
Input MUXADC Inputs
E0 to E30

ADC-E
12-bits
REFLO

CMPSS Inputs
VREFHIDACA_OUT

12-bitBuffered
DAC-A

Figure 6-32. Analog Subsystem Block Diagram (128-/80-/64-/56-Pin Packages)

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VREFHI

CMP1_HP

VREFLO
CMP1_HN
Reference Circuit
Misc. Analog

CMP1_LN

CMP2_HN
HPMXSEL4//LPMXSEL4/

HPMXSEL2//LPMXSEL2//LPMXSEL0/

HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1/LPMXSEL5/
AGPIO
AGPIO
AGPIO
AIO
AIO
AIO

HPMXSEL2/HNMXSEL0/LPMXSEL2/LNMXSEL0HPMXSEL1//LPMXSEL1/
HPMXSEL3//LPMXSEL3/

AIO
AIO
AIO

CMPSS2 Input MUX

B2/C6/E12
B3/PGA2_INP
A14/B14/C4/PGA1_OUT
B12/C2/PGA2_INM
A3
A0/B15/C15/DACA_OUT

HPMXSEL0//LPMXSEL0/
HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0HPMXSEL4//LPMXSEL4/
HPMXSEL5//LPMXSEL5/

HPMXSEL2//LPMXSEL2/

Comparator Subsystem 2
DigitalFilterVDDA

CTRIP2HCTRIPOUT2H

CMP2_LN

CMP3_HP
CMP3_HN

Temp Sensor

AGPIO
AGPIO
AGPIO
AIO
AIO
AIO

/LPMXSEL0/

Analog Interconnect
Reference Circuit

DAC12

DigitalFilterCTRIP2LCTRIPOUT2L

Comparator Subsystem 3
DigitalFilterVDDA

CTRIP3HCTRIPOUT3H

DAC12

REFHI
ADC Inputs
B0 to B30

CMPSS Input MUX

CMP2_LP
REFLO

CMP3_LN

DAC12DigitalFilterCTRIP3L
CTRIPOUT3L

Comparator Subsystem 4
DigitalFilterVDDA

CTRIP4H
CTRIPOUT4H

ADC-B
12-bits

CMP3_LP
CMP4_HP

REFLO
CMP4_HNDAC12ADC Inputs
C0 to C30

HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0HPMXSEL2//LPMXSEL2/
HPMXSEL4/HPMXSEL5/CTRIP1LCTRIPOUT1L

12-bits

Input MUXHPMXSEL0/

DigitalFilterDAC12HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1CMPSS3 Input MUX

B4/C8
C14
C1/E11/PGA3_INP
A8/B0/C11
B11/D16/E16
A7/B30/C3/D12/E30

ADC-A

Input MUXHPMXSEL0/HNMXSEL1/LPMXSEL0/LNMXSEL1HPMXSEL5//LPMXSEL5/
AGPIO
AGPIO
AGPIO

Analog Interconnect

HPMXSEL5/CMPSS1 Input MUX

A10/B1/C10
A9
B0/C11
A12
A5

REFHI
ADC Inputs
A0 to A30

Input MUXHPMXSEL0/DAC12

CMP1_LP
CMP2_HP

ADC Module
Buffered DAC Module

Vref
REFLO

A1/B7/D11/CMP1_DACL
A6/D14/E14
A2/B6/C9/PGA1_INP
A11/B10/C0/PGA2_OUT
B5/D15/E15

CMPSS Module
CTRIP1HCTRIPOUT1HDAC12ANAREFSEL

Temp Sensor(C12)Comparator Subsystem 1
DigitalFilter
VDDA

REFHI

CMP4_LN

ADC-C

CMP4_LP

DAC12DigitalFilterCTRIP4L
CTRIPOUT4L

12-bits/LPMXSEL4//LPMXSEL5/REFLO

HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
AGPIO
AGPIO
AGPIO
CMPSS4 Input MUX

AIO
AIO
AIO

REFHI
Input MUXADC Inputs
D0 to D30

ADC-D
12-bits
REFLO

REFHI
Input MUXADC Inputs
E0 to E30

ADC-E
12-bits
REFLO

CMPSS Inputs

VREFHIDACA_OUT

12-bitBuffered
DAC-A

Figure 6-33. Analog Subsystem Block Diagram (100-Pin Package)

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PGA Module

CMPSSx Input MUXCMPSS Input MUXCMPxHPMX
CMPx_HP0
CMPx_HP1
CMPx_HP2
CMPx_HP3
CMPx_HP4

AGPIO

2
3

CMPx_HP64
5
6

CMPx_HN00

CMPx_HN1

1

CMPx_LN00

CMPx_LN1

1

CMPx_HP5AIO

01
CMPx_HP

CMPxHNMXCMPx_HN

CMPx_LN

To CMPSSxCMPxLNMXCMPxLPMX
CMPx_LP0
CMPx_LP1
CMPx_LP2
CMPx_LP3
CMPx_LP4
CMPx_LP5
CMPx_LP601
2
3

CMPx_LP

4
5
6

ADCA

ADCA

AIO
AGPIO
ADCB

ADCB

AIO
AGPIO
ADCC

ADCC

AIO

ADCD

To ADCsTO Device Pins

AGPIO
ADCD

AIO
AGPIO
ADCE

ADCE

AIO
PGAx_OUT

AGPIO
VDDA

PGAx_OUT_INT
PGAx_INP+

PGAx_INM-

PGAx_OUT

VSSA

Figure 6-34. Analog Group Connections

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Input connections to the CMPSS modules are selectable through a programmable input mux. Figure 6-34
demonstrates the connection between the input MUX of CMPSS modules, PGA modules, and ADC modules.
Table 6-11 shows the mapping of ADC input signals and PGA input and output signals to CMPSS mux inputs.
•

To configure the CMPx_HP input mux for CMPSSx, write to the CMPxHPMXSEL field in the CMPHPMXSEL
analog subsystem register.
To configure the CMPx_HN input mux for CMPSSx, write to the CMPxHNMXSEL field in the CMPHNMXSEL
analog subsystem register.
To configure the CMPx_LP input mux for CMPSSx, write to the CMPxLPMXSEL field in the CMPLPMXSEL
analog subsystem register.
To configure the CMPx_LN input mux for CMPSSx, write to the CMPxLNMXSEL field in the CMPLNMXSEL
analog subsystem register.

•••

Table 6-11. CMPSS Input Mux Options
CMPSSx Input MUX

CMP1

CMP2

HP0

A2, B6, C9, PGA1_INP

A4, B8

B2,C6, E12

B4, C8HP1

A11, B10, C0, PGA2_OUT

A12

B12, C2, PGA2_INM

A7, C3, D12, B30, E30,

HP2

A6, D14, E14(3)A9A0, B15, C15, DACA_OUT

C1, E11, PGA3_INP

B3, PGA2_INP

C14

A10, B1, C10

CMP3

HP3

A15(2)HP4

A1, B7, D11, CMP1_DACL

HP5

B5, D15, E15(4)

A5(1)

A3

HP6

PGA1_OUT_INT

PGA3_OUT_INT

PGA2_OUT_INT

HP7

B0, C11(1)A14, B14, C4, PGA1_OUT

CMP4

A8
B0, C11(2)B11, D16, E16(4)TEMP SENSOR

HN0

A15(2)

A10, B1, C10

B3, PGA2_INP

C14

HN1

A11, B10, C0, PGA2_OUT

A12

B12, C2, PGA2_INM

A7, B30, C3, D12, E30

LP0A2, B6, C9, PGA1_INP

A4, B8

B2, C6, E12

B4, C8LP1

A11, B10, C0, PGA2_OUT

A12

B12, C2, PGA2_INM

A7, B30, C3, D12, E30

LP2

A6, D14, E14(3)A9A0, B15, C15, DACA_OUT

C1, E11, PGA3_INP

B3, PGA2_INP

C14

A10, B1, C10

LP3

A15(2)LP4

A1, B7, D11, CMP1_DACL

LP5

B5, D15, E15(4)

A5(1)

A3

B0, C11(1)A14, B14, C4, PGA1_OUT

A8
B0, C11(2)B11, D16, E16(4)LP6PGA1_OUT_INT

PGA3_OUT_INT

PGA2_OUT_INT

LN0

A15

A10, B1, C10

B3, PGA2_INP

C14

LN1

A11, B10, C0, PGA2_OUT

A12

B12, C2, PGA2_INM

A7, C3, D12, B30,E30

(1)
(2)
(3)
(4)

These MUX options are available only on 100 QFP package.
This MUX option is available only on 56 QFN, 64 QFP, 80 QFP, and 128 QFP packages.
This MUX option is available only on 64 QFP, 80 QFP, 100 QFP, and 128 QFP packages.
This MUX option is available only on 100 QFP and 128 QFP packages.

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6.15.2 Analog Pins and Internal Connections
Table 6-12. Analog Pins and Internal Connections
Pins/Package
Pin Name

ADC

Comparator Subsystem (MUX)

128
QFP

100
QFP

80
QFP

64
QFP

56
QFN

A

B

C

D

E

VREFHI

31
32

24
25

20

16

14

-

-

-

D20

E20

VREFLO

33
34

26
27

21

17

15

A13

B13

C13

D13

E13

DAC

PGA

High
PositiveHigh
Negative

Analog Group 1
A6/D14/E14
A2/B6/C9/PGA1_INP
A15

18
21

22

B9/C7/PGA1_INM

14
17
-

10

6

-

13

9

7

14

10

8

18

A6

-

-

A2

B6

C9

A15

-

-

-

B9

C7

E14

-

-

-

-

D14

PGA1_INP

20

16

12

10

A11

B10

C0

-

-

A1/B7/D11/CMP1_DACL

29

22

18

14

12

A1

B7

-

D11

-

38

32

-

-

-

-

B5

D15

E15

-

24

20

18

-

-

PGA3_OUT

-

-

-

CMP1
(LPMXSEL=2)

CMP1(HPMXSEL=0)-CMP1(LPMXSEL=0)-

CMP1(HPMXSEL=3)

CMP1(HNMXSEL=0)CMP1(LPMXSEL=3)

CMP1(LNMXSEL=0)

PGA2_OUTCMP1(HPMXSEL=1)

CMP1(HNMXSEL=1)

CMP1(LPMXSEL=1)

CMP1(LNMXSEL=1)

AIO237

CMP1_DACLCMP1(HPMXSEL=4)-

CMP1(LPMXSEL=4)-

AIO232CMP1(HPMXSEL=5)-

Analog Group 2-

CMP1(LPMXSEL=5)-

AGPIO228(3)

AGPIO224(3)

AGPIO233(3)

AIO252

CMP2

A4/B8

42

36

27

23

21

A4

B8

-

-

-

CMP2
(HPMXSEL=0)

A12

35

28

22

18

16

A12

-

-

-

-

CMP2
(HPMXSEL=1)-

CMP2(LPMXSEL=1)

-

A9

48

38

28

24

22

A9

-

-

-

-

CMP2
(HPMXSEL=2)-

CMP2(LPMXSEL=2)

-

-

CMP2
(HPMXSEL=3)

CMP2(HNMXSEL=0)CMP2(LPMXSEL=3)

CMP2(LNMXSEL=0)

CMP2(HPMXSEL=3)-

CMP2(LPMXSEL=3)

-

-

CMP2
(HPMXSEL=5)-CMP2(LPMXSEL=5)-

CMP3(HPMXSEL=0)-CMP3(LPMXSEL=0)-

CMP3(HPMXSEL=1)

CMP3(HNMXSEL=1)

CMP3(LPMXSEL=1)

CMP3(LNMXSEL=1)

A10/B1/C10

50

40

29

25

23

A10

B1

C10

B0/C11

-

41

-

-

-

-

B0

C11

28

-

17

13

11

-

35

-

-

-

A5

-

-

A5

AIO Input/
AGPIO

PGA1_INM

27

PGA3_OUT

Low
Negative

CMP1
CMP1(HPMXSEL=2)

A11/B10/C0/PGA2_OUT

B5/D15/E15

Low
Positive

-

-

-

CMP2
(LPMXSEL=0)-

AIO225
AIO238

Analog Group 3

AGPIO227(3)

AGPIO230(3)

AGPIO231(3)

AIO249

CMP3

B2/C6/E12

19

15

11

7

-

-

B2

C6

-

E12

B12/C2/PGA2_INM

28

21

17

13

11

-

B12

C2

-

-

PGA2_INM

AGPIO226(3)

AIO244

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Table 6-12. Analog Pins and Internal Connections (continued)
Pins/Package

ADC

Comparator Subsystem (MUX)

Pin Name

128
QFP

100
QFP

80
QFP

64
QFP

56
QFN

A

B

C

D

E

A0/B15/C15/DACA_OUT

30

23

19

15

13

A0

B15

C15

-

-

12

8

6

-

B3

-

-

-

PGA2_INP

-

C5

A14

B14

C4

-

-

PGA1_OUT

A3

-

-

-

B3/PGA2_INP

20

C5

16
28

A14/B14/C4/PGA1_OUT
A3

26

19

15

11

9

20

-

12

8

6

-

18

-

-

-

DAC

PGA

AIO Input/
AGPIO

High
PositiveHigh
Negative

Low
Positive

Low
Negative

CMP3(HPMXSEL=2)-

CMP3(LPMXSEL=2)-

AIO231CMP3(HPMXSEL=3)

CMP3(HNMXSEL=0)CMP3(LPMXSEL=3)

CMP3(LNMXSEL=0)

AGPIO242

CMP3(HPMXSEL=4)-CMP3(LPMXSEL=4)-

AIO239-CMP3(HPMXSEL=5)-CMP3(LPMXSEL=5)-

CMP4(HPMXSEL=0)-CMP4(LPMXSEL=0)-

CMP4(HPMXSEL=2)-

CMP4(LPMXSEL=2)-

AGPIO247

DACA_OUT

Analog Group 4(3)

AIO229CMP4AGPIO236

B4/C8

49

39

28

24

22

-

B4

C8

-

-

C1/E11/PGA3_INP

35

29

22

18

16

-

-

C1

-

E11

C14

42

42

27

23

21

-

-

C14

-

-

CMP4
(HPMXSEL=3)

CMP4(HNMXSEL=0)CMP4(LPMXSEL=3)

CMP4(LNMXSEL=0)

B0/C11

39

-

24

20

18

-

B0

C11

A8

-

37

-

-

-

A8

-

-

-

-

CMP4
(HPMXSEL=4)-CMP4(LPMXSEL=4)-

CMP4(HPMXSEL=5)-CMP4(LPMXSEL=5)-

AIO251

B11/D16/E163630

PGA3_INM

36(1)

30(1)
23

19

17

AIO240

-

D16

E16

-

-

-

-

-

A7

B30

C3

D12

E30

CMP4
(HPMXSEL=1)

CMP4(HNMXSEL=1)

CMP4(LPMXSEL=1)

CMP4(LNMXSEL=1)

AIO245

-

-

C12

-

-

CMP2
(HPMXSEL=7)

-

-

-

-

PGA1_OUT_INT(2)

A21

B21

-

-

-

PGA1_OUT_I
NT

CMP1(HPMXSEL=6)-CMP1(LPMXSEL=6)--

PGA2_OUT_INT(2)

-

B22

C21

-

-

PGA2_OUT_I
NT

CMP3(HPMXSEL=6)-CMP3(LPMXSEL=6)--

PGA3_OUT_INT(2)

A22

-

C22

-

-

PGA3_OUT_I
NT

CMP2(HPMXSEL=6)-CMP2(LPMXSEL=6)

-

-

31

-

AIO241

B11

37

-

(3)

-

A7/B30/C3/D12/E30-

PGA3_INP(3)

PGA3_INM

Other Analog
TempSensor(2)

(1)
(2)
(3)

130

Signal is bonded together with another signal as a single pin on this package.
Internal connection only; does not come to a device pin.
Only on 100 QFP package, AGPIO 247 is available.

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Note
The GPIOs on the analog pins support full digital input and output functionality and are referred to as AGPIOs. By default, the AGPIOs areunconnected; that is, the analog and digital functions are both disabled. For configuration details, see the Digital Inputs and Outputs on ADC
Pins (AGPIOs) section.

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6.15.3 Analog Signal Descriptions
Table 6-13. Analog Signal Descriptions
Signal Name
AIOx

Description
Digital input on ADC pin

AGPIOxADCINAx, Ax

Digital input/output pin with ADC functionality
ADC A Input

ADCINBx, Bx

ADC B Input

ADCINCx, Cx

ADC C Input

ADCINDx, Dx

ADC D Input

ADCINEx, Ex

ADC E Input

CMPx_HP

Comparator subsystem high comparator positive input

CMPx_HN

Comparator subsystem high comparator negative input

CMPx_LP

Comparator subsystem low comparator positive input

CMPx_LN

Comparator subsystem low comparator negative input

DACA_OUT

Buffered DAC Output

CMP1_DACLCMPSS1 DAC Output

PGAx_INP

PGA module non-inverting pin

PGAx_INM

PGA module inverting pin

PGAx_OUT

PGA module output

PGAx_OUT_INT
TEMP SENSOR, TS

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PGA module internal output connected to CMPSS and ADC modules
Internal temperature sensor

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6.15.4 Analog-to-Digital Converter (ADC)The ADC module described here is a successive approximation (SAR) style ADC with resolution of 12 bits.
This section refers to the analog circuits of the converter as the “core,” and includes the channel-select MUX,
the sample-and-hold (S/H) circuit, the successive approximation circuits, voltage reference circuits, and otheranalog support circuits. The digital circuits of the converter are referred to as the “wrapper” and include logic
for programmable conversions, result registers, interfaces to analog circuits, interfaces to the peripheral buses,
post-processing circuits, and interfaces to other on-chip modules.
Each ADC module consists of a single sample-and-hold (S/H) circuit. The ADC module is designed to be
duplicated multiple times on the same chip, allowing simultaneous sampling or independent operation of multiple
ADCs. The ADC wrapper is start-of-conversion (SOC)-based (see the SOC Principle of Operation section of
the Analog-to-Digital Converter (ADC) chapter in the TMS320F28P55x Real-Time Microcontrollers Technical
Reference Manual).
Each ADC has the following features:• Resolution of 12 bits
• Ratiometric external reference set by VREFHI/VREFLO• Selectable internal reference of 2.5 V or 3.3 V• Single-ended signal mode
• Input multiplexer with up to 32 channels• 16 configurable SOCs
• 16 individually addressable result registers• External analog input mux selection per SOC, up to 4 bits
• Sample cap reset feature for memory crosstalk mitigation• Multiple trigger sources– Software immediate start– All ePWMs: ADCSOC A or B
– GPIO XINT2– CPU Timers 0/1/2– ADCINT1/2– ECAP events in capture mode (CEVT1, CEVT2, CEVT3, and CEVT4) and APWM mode (period match,compare match, or both).
– Global software trigger for multiple ADCs
• Four flexible PIE interrupts• Burst-mode triggering option• Hardware oversampling mode up to 128x, with configurable trigger spread delay• Hardware undersampling mode
• Trigger phase delay function• Four post-processing blocks, each with:– Saturating offset calibration– Error from setpoint calculation– High, low, and zero-crossing compare, with interrupt and ePWM trip capability– Configurable digital filter for high/low/zero-crossing compare– Trigger-to-sample delay capture– Absolute value calculation– 24-bit accumulation register for oversampling, with configurable binary shift– Minimum/maximum calculation for outlier rejection
Note
Not every channel can be pinned out from all ADCs. See the Pin Configuration and Functions section
to determine which channels are available.

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The block diagram for the ADC core and ADC wrapper are shown in Figure 6-35.
ADCEXTMUX[3:0]

SYSCLKADCCLKRESOLUTION

Post Processing BlockRESOLUTION

CHSEL[15:0][15:0]SOC Arbitration&
Control

ADCSOC

ACQPS[15:0]

Analog to Digital Core
Reference Voltage Generator
REPEATx (1-2)[15:0]

Analog System Control

TRIGSEL
MODE
NSEL
PHASE
SPREADCHSEL
EXTCHSEL

Input Circuit
Converter
REPEATx (1-2)

...

...

VIN+

SOCxSTART[15:0]

DOUT

SOCx (0-15)

TRIGGER[15:0]

VIN-

Input Circuit
Analog to Digital Core

VREFHI

Bandgap
Reference
CircuitEOCx[15:0]
FREECOUNTADCRESULT 0–15 Regs

Converter

Conversion Start Delay
Calculation
Sample Correction(OFFCAL, OFFREF, INV, ABS,
last-sample delta)
Oversampling and
Accumulation(COUNT, SUM, MAX, MIN)PPBxRESULT

S/H
CircuitRESULT
EOCx[15:0]

ADCIN29
ADCIN30ADCIN31

0
1
2
3
4
5
6
7
8
9
10
11
...
29
30
31

TRIGSEL

SOCx (0-15)

ADCIN0ADCIN1ADCIN2ADCIN3ADCIN4ADCIN5ADCIN6ADCIN7ADCIN8ADCIN9ADCIN10ADCIN11...

Analog to Digital Control Logic

Clock Prescaler
SIGNALMODE

Triggers

SIGNALMODE

Sync
Logic

ADCEVTINT

Limit Compare and Event
Logic, Digital Filters

10

Post Processing Block (1-4)

ADCEVTADCOSINT1

Interrupt Block (1-4)
Analog to Digital Control Logic

VREFLOADCINT1-4
ADCINT1-4_DMA

REFPMUXSELANAREFx1P65SEL

Reference Voltage Generator

Analog System Control

Figure 6-35. ADC Module Block Diagram

134

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6.15.4.1 ADC Configurability

Some ADC configurations are individually controlled by the SOCs, while others are globally controlled per ADC
module. Table 6-14 summarizes the basic ADC options and their level of configurability.
Table 6-14. ADC Options and Configuration Levels(1)

OPTIONSCONFIGURABILITYClock

Per module(1)Resolution

Not configurable (12-bit resolution only)

Signal modeNot configurable (single-ended signal mode only)

Reference voltage source

Either external or internal for all modules

Trigger source

Per SOC(1)Converted channel

Per SOC

Acquisition window duration

Per SOC(1)EOC location

Per module

Burst mode

Per module(1)Writing these values differently to different ADC modules could cause the ADCs to operate
asynchronously. For guidance on when the ADCs are operating synchronously or asynchronously,
see the Ensuring Synchronous Operation section of the Analog-to-Digital Converter (ADC) chapter
in the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual .

6.15.4.1.1 Signal Mode

The ADC supports single-ended signaling. The input voltage to the converter is sampled through a single pin(ADCINx), referenced to VREFLO.
VREFHI

Pin Voltage
VREFHIADCINxADCINxADC

VREFHI/2

VREFLO
VREFLO(VSSA)

2n - 1

Digital Output

ADC Vin0

Figure 6-36. Single-ended Signaling Mode

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6.15.4.2 ADC Electrical Data and Timing

Note
The ADC inputs should be kept below VDDA + 0.3 V. If an ADC input goes above this level, ADC
disturbances to other channels may occur by two mechanisms:• ADC input overvoltage will overdrive the CMPSS mux, disturbing all other channels which share acommon CMPSS mux. This disturbance will be continuous regardless of if the overvoltage input issampled by the ADC• When the ADC samples the overvoltage ADC input, VREFHI will be pulled up to a higher level.
This will disturb subsequent ADC conversions on any channel until the VREF stabilizes
Note
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the
VREFHI pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may
float to 0 V internally, giving improper ADC conversion.
6.15.4.2.1 ADC Operating Conditions
over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSADCCLK (derived from PERx.SYSCLK)

TYP

5150-MHz SYSCLKSample rate
Sample window duration (set by ACQPS andPERx.SYSCLK)(1)With 50 Ω or less Rs

VREFHI

External Reference

VREFHI - VREFLO
Conversion range

Internal Reference = 3.3 V Range

Conversion range

Internal Reference = 2.5 V Range

Conversion range

External Reference

Conversion range

Analog Supply as Reference

UNIT

75

MHz

3.9

MSPS
ns

1.55 1.65 or 2.50

VDDA

1.65

Internal Reference = 2.5V Range

VREFLOMAX

67

Internal Reference = 3.3V Range

VREFHI(2)

(1)
(2)

MIN

V
V

2.50

V

VSSA

VSSA

V

2.4

VDDA

V

0

3.3

V

0

2.5

V

VREFLOVREFHI

V

VSSA

VDDA

V

The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
In internal reference mode, the reference voltage is driven out of the VREFHI pin by the device. The user should not drive a voltage
into the pin in this mode.

6.15.4.2.2 ADC Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

GeneralADCCLK Conversion Cycles

Power Up Time

150-MHz SYSCLK

14 ADCCLKs

External Reference mode

500

µs

Internal Reference mode

5000

µs

Internal Reference mode, when switching between
2.5-V range and 3.3-V range.

5000

µs

VREFHI input current(1)Internal Reference Capacitor
Value(2)136

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40
2.2

µA
µF

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6.15.4.2.2 ADC Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONS

External Reference Capacitor
Value(2)

MIN

TYP

MAX

2.2

UNIT
µF

DC Characteristics
Gain Error

Internal reference–45

External reference

–5

±3

5

–5

±2

5

Offset Error

45

LSB
LSB

Channel-to-Channel Gain Error(4)2LSBChannel-to-Channel Offset
Error(4)2LSB

ADC-to-ADC Gain Error(5)Identical VREFHI and VREFLO for all ADCs

4

LSB

ADC-to-ADC Offset Error(5)Identical VREFHI and VREFLO for all ADCs2

LSB

DNL Error

>–1

±0.5

1

LSB

INL Error

–2

±1.5

2

LSB

1

LSBs

ADC-to-ADC Isolation

VREFHI = 2.5 V, synchronous ADCs

–1

AC Characteristics
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1

69.2

SNR(3)

VREFHI = 2.5 V, fin = 100 kHz, SYSCLK fromINTOSC(6)60.1

THD(3)

VREFHI = 2.5 V, fin = 100 kHz

-83

dB

SFDR(3)

VREFHI = 2.5 V, fin = 100 kHz

79.2

dB

VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1

68.5

VREFHI = 2.5 V, fin = 100 kHz, SYSCLK fromINTOSC(6)60.0

VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
X1, Single ADC

11.2

VREFHI = 2.5 V, fin = 100 kHz, SYSCLK fromX1, synchronous ADCs11

VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
X1, asynchronous ADCs

Not
Supported

SINAD(3)

ENOB(3)

PSRR

(1)
(2)
(3)
(4)
(5)
(6)

VDD = 1.2-V DC + 100mV
DC up to Sine at 1 kHz

105

VDD = 1.2-V DC + 100 mV
DC up to Sine at 300 kHz

102

VDDA = 3.3-V DC + 200 mV
DC up to Sine at 1 kHz

97

VDDA = 3.3-V DC + 200 mV
Sine at 900 kHz

85

dB

dB

bits

dB

Load current on VREFHI increases when ADC input is greater than VDDA. This causes inaccurate conversions.
A ceramic capacitor with package size of 0805 or smaller is preferred. Up to ±20% tolerance is acceptable.
IO activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling andcrosstalk.
Variation across all channels belonging to the same ADC module.
Worst case variation compared to other ADC modules.
Frequency tolerance over temperature of the INTOSC results in lower SNR versus external clock, due to FFT uncertainty

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6.15.4.2.3 ADC INL and DNL
0x006

0x005

Digital Output Code

0x004

0x003

0x002

0x001

0x000

DNL Error

Analog Input Voltage= Ideal Transfer Function= Transfer Function (Low)= INL Error

R=

VREFHI – VREFLO
2^nFigure 6-37. ADC INL and DNL

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6.15.4.2.4 ADC Performance Per Pin

ADC performance of each pin is affected by adjacent pins. The following plots provide details on how these pins
differ in performance.

Figure 6-38. Per-Channel ENOB for 128-Pin PDT

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Figure 6-39. Per-Channel ENOB for 100-pin PZ

140

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Figure 6-40. Per-Channel ENOB for 80-Pin PNA

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Figure 6-41. Per-Channel ENOB for 64-Pin PM

142

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Figure 6-42. Per-Channel ENOB for 56-Pin RSH
6.15.4.2.5 ADC Input Model

Table 6-15. Input Model Parameters
DESCRIPTIONCp
Ron

REFERENCE MODE

VALUE

Parasitic input capacitanceAll

Sampling switch resistance

External Reference, 2.5-V Internal
Reference1000 Ω

3.3-V Internal Reference

1700 Ω

External Reference, 2.5-V Internal
Reference

4 pF

3.3-V Internal Reference

2.5 pF

All

50 Ω

Ch

Sampling capacitor

Rs

Nominal source impedance

See Table 6-16 to Table 6-20

ADC
Rs

ADCINx
Switch

AC

Cp

Ron
Ch

VREFLO

Figure 6-43. Input Model

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This input model should be used with actual signal source impedance to determine the acquisition window
duration. For more information, see the Choosing an Acquisition Window Duration section of the Analogto-Digital Converter (ADC) chapter in the TMS320F28P55x Real-Time Microcontrollers Technical Reference
Manual. For recommendations on improving ADC input circuits, see the ADC Input Circuit Evaluation for C2000
MCUs Application Note.
Table 6-16. Per-Channel Parasitic Capacitance for 128-Pin QFPCp (pF)ADC CHANNEL

144

COMPARATOR DISABLED

COMPARATOR ENABLED

A0, B15, C15, DACA_OUT

6.1

9.6

A1, B7, D11, CMP1_DACL

4.1

7.6

A2, B6, C9, PGA1_INP

6.1

9.4

A4, B86.0

7.9

A6, D14, E14

4.2

7.6

A7, C3, D12, B30, E30

7.5

10.3

A8, B0, C11

3.4

7.8

A9

3.7

8.7

A10, B1, C10

3.2

10.5

A11, B10, C0,PGA2_OUT

9.4

13.0

A12

6.5

11.5

A14, B14, C4, PGA1_OUT

5.8

8.0

A15

3.3

11.2

A16, B16, C16

5.0

5.6

A17,B17,C17

6.6

6.8

A18,B18,C18

5.2

5.9

A19,B19,C19

4.6

6.0

A20,B20,C20

6.7

6.2

B2, C6, E12

4.6

6.8

A3, B3, C5, PGA2_INP

14.0

20.3

B4, C84.3

7.9

B5, D15, E15

6.2

8.8

A15, B9, C7, PGA1_INM

3.8

11.2

B11, D16, E16

4.0

7.4

A5, B12, C2, PGA2_INM

8.6

12.8

A12, C1, E11, PGA3_INP

10.2

10.2

C5

5.4

5.4

C14

4.9

6.4

D0,E0,A24

5.6

6.3

D1,E1,B24

5.5

6.4

D2,E2,C24

4.2

4.3

D3,E3,A25

6.0

6.6

D4,E4,B25

7.2

7.8

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Table 6-16. Per-Channel Parasitic Capacitance for 128-Pin QFP (continued)
Cp (pF)ADC CHANNELCOMPARATOR DISABLED

COMPARATOR ENABLED

D5,E5,C25

2.3

2.3

D6,E6,A26

5.0

5.0

D7,E7,B26

5.0

5.0

D8, E8, C26

3.3

3.3

D9,E9, A27

3.6

3.6

D10,E10,B27

3.0

3.8

D18,E18,C27

3.0

3.5

D19,E19,A28

2.1

3.6

Table 6-17. Per-Channel Parasitic Capacitance for 100-Pin QFPCp (pF)ADC CHANNELCOMPARATOR DISABLED

COMPARATOR ENABLED

A0, B15, C15, DACA_OUT

6.1

9.6

A1, B7, D11, CMP1_DACL

4.1

7.4

A2, B6, C9, PGA1_INP

6.1

9.4

A4, B8

6.0

7.9

A5

4.2

7.6

A6, D14, E14

7.5

10.3

A7, C3, D12, B30, E30

3.4

7.8

A8, B0, C11

3.7

8.7

A9

3.7

8.7

A10, B1, C10

3.2

10.5

A11, B10, C0, PGA2_OUT

9.4

13.0

A12

6.5

11.5

A14, B14, C4, PGA1_OUT

5.8

8.0

A16/B16/C16

5.0

5.6

A17,B17,C17

6.6

6.8

A18,B18,C18

5.2

5.9

A19,B19,C19

4.6

6.0

A20,B20,C20

6.7

6.2

B2, C6, E12

4.6

6.8

B3, PGA2_INP

14.0

20.3

B4, C84.3

7.9

B5, D15, E15

6.2

8.8

A3, B9, C7, PGA1_INM

7.0

7.6

B11, D16, E16

4.0

7.4

B12, C2, PGA2_INM

8.6

12.8

C1,E11,PGA3_INP

10.2

10.2

C5

5.4

5.4

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Table 6-17. Per-Channel Parasitic Capacitance for 100-Pin QFP (continued)
Cp (pF)ADC CHANNELCOMPARATOR DISABLED

COMPARATOR ENABLED

C14

4.9

6.4

D0,E0,A24

5.6

6.3

D1,E1,B24

5.5

6.4

D2,E2,C24

4.2

4.3

D3,E3,A25

6.0

6.6

D4,E4,B25

7.2

7.8

Table 6-18. Per-Channel Parasitic Capacitance for 80-Pin QFPCp (pF)ADC CHANNEL

146

COMPARATOR DISABLED

COMPARATOR ENABLED

A0, B15, C15, DACA_OUT

6.1

9.6

A1, B7, D11, CMP1_DACL

4.1

7.6

A2, B6, C9, PGA1_INP

6.1

9.4

A4, B86.0

7.9

A6, D14, E14

4.2

7.6

A7, C3, D12, B30,E30

7.5

10.3

A8, B0, C11

3.4

7.8

A9

3.7

8.7

A10, B1, C10

3.2

10.5

A11, B10, C0,PGA2_OUT

9.4

13.0

A14, B14, C4, PGA1_OUT

5.8

8.0

A16/B16/C16

5.0

5.6

A17,B17,C17

6.6

6.8

A18,B18,C18

5.2

5.9

A19,B19,C19

4.6

6.0

A20,B20,C20

6.7

6.1

B2, C6, E12

4.6

6.8

A3, B3, C9, PGA2_INP

14.0

20.3

B4, C8

4.3

7.9

A15, B9, C7, PGA1_INM

3.8

11.2

A5, B12, C2, PGA2_INM

8.6

12.8

A12, C1,E11,PGA3_INP

10.2

10.2

C5

5.4

5.4

C14

4.9

6.4

D0,E0,A24

5.6

6.3

D1,E1,B24

5.5

6.4

D2,E2,C24

4.2

4.3

D3,E3,A25

6.0

6.6

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Table 6-18. Per-Channel Parasitic Capacitance for 80-Pin QFP (continued)
Cp (pF)ADC CHANNEL
D4,E4,B25

COMPARATOR DISABLED

COMPARATOR ENABLED

7.2

7.8

Table 6-19. Per-Channel Parasitic Capacitance for 64-Pin QFPCp (pF)ADC CHANNELCOMPARATOR DISABLED

COMPARATOR ENABLED

A0, B15, C15, DACA_OUT

6.1

9.6

A1, B7, D11, CMP1_DACL

4.1

7.6

A2, B6, C9, PGA1_INP

6.1

9.4

A4, B86.0

7.9

A6, D14, E14

4.2

7.6

A7, C3, D12, B30, E30

7.5

10.3

A8, B0, C11

3.4

7.8

A9

3.7

8.7

A10, B1, C10

3.2

10.5

A11, B10, C0,PGA2_OUT

9.4

13.0

A14, B14, C4, PGA1_OUT

5.8

8.0

A16, B16, C16

5.0

5.6

A17,B17,C17

6.6

6.8

A18,B18,C18

5.2

5.9

A19,B19,C19

4.6

6.0

A20,B20,C20

6.7

6.1

B2, C6, E12

4.6

6.8

A3, B3, PGA2_INP

14.0

20.3

B4, C8

4.3

7.9

A15, B9, C7, PGA1_INM

3.8

11.2

A5, B12, C2, PGA2_INM

8.6

12.8

A12, C1, E11, PGA3_INP

10.2

10.2

C5

5.4

5.4

C14

4.9

6.4

D0,E0,A24

5.6

6.3

D1,E1,B24

5.5

6.4

D2,E2,C24

4.2

4.3

D3,E3,A25

6.0

6.6

D4,E4,B25

7.2

7.8

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Table 6-20. Per-Channel Parasitic Capacitance for 56-Pin QFNCp (pF)ADC CHANNEL

148

COMPARATOR DISABLED

COMPARATOR ENABLED

A0, B15, C15, DACA_OUT

6.1

9.6

A1, B7, D11, CMP1_DACL

4.1

7.6

A2, B6, C9, PGA1_INP

6.1

9.4

A4, B86.0

7.9

A7, C3, D12, B30,E30

7.5

10.3

A8, B0, C11

3.4

7.8

A9

3.7

8.7

A10, B1, C10

3.2

10.5

A11, B10, C0,PGA2_OUT

9.4

13.0

A14, B14, C4, PGA1_OUT

5.8

8.0

A16,B16,C16

5.0

5.6

A17,B17,C17

6.6

6.8

A18,B18,C18

5.2

5.9

A19,B19,C19

4.6

6.0

A20,B20,C20

6.7

6.1

A3, B3, PGA2_INP

14.0

20.3

B4, C8

4.3

7.9

A15, B9, C7, PGA1_INM

3.8

11.2

A5, B12, C2, PGA2_INM

8.6

12.8

A12, C1, E11, PGA3_INP

10.2

10.2

C5

5.4

5.4

C14

4.9

6.4

D0,E0,A24

5.6

6.3

D1,E1,B24

5.5

6.4

D2,E2,C24

4.2

4.3

D3,E3,A25

6.0

6.6

D4,E4,B25

7.2

7.8

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6.15.4.2.6 ADC Timing Diagrams

The following diagrams show the ADC conversion timings for two SOCs given the following assumptions:• SOC0 and SOC1 are configured to use the same trigger.
• No other SOCs are converting or pending when the trigger occurs.
• The round-robin pointer is in a state that causes SOC0 to convert first.
• ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag
propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE module).
Table 6-21 lists the descriptions of the ADC timing parameters. Table 6-22 and Table 6-23 list the ADC timings.
Sample n

Input on SOC0.CHSEL
Input on SOC1.CHSEL
Sample n+1

ADC S+H

SOC0

SOC1

SYSCLKADCCLKADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0(old data)

ADCRESULT1(old data)

Sample n

Sample n+1

ADCINTFLG.ADCINTx
tSH

tLAT
tEOC
tINT

Figure 6-44. ADC Timings for 12-bit Mode in Early Interrupt Mode

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Sample n
Input on SOC0.CHSEL

Input on SOC1.CHSEL
Sample n+1
ADC S+H

SOC0

SOC1

SYSCLKADCCLKADCTRIG

ADCSOCFLG.SOC0

ADCSOCFLG.SOC1

ADCRESULT0(old data)

ADCRESULT1(old data)

Sample n

Sample n+1

ADCINTFLG.ADCINTx

tSH

tLAT

tEOC

tINT

Figure 6-45. ADC Timings for 12-bit Mode in Late Interrupt Mode

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Table 6-21. ADC Timing Parameter Descriptions
PARAMETERDESCRIPTION
The duration of the S+H window.

tSH

At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital value. The
duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each SOC, so tSH is notnecessarily the same for different SOCs.
Note: The value on the S+H capacitor is captured approximately 5 ns before the end of the S+H window regardless ofdevice clock settings.

tLAT
tEOC

The time from the end of the S+H window until the ADC results latch in the ADCRESULTx register.
If the ADCRESULTx register is read before this time, the previous conversion results are returned.
The time from the end of the S+H window until the S+H window for the next ADC conversion can begin. The
subsequent sample can start before the conversion results are latched.
The time from the end of the S+H window until an ADCINT flag is set (if configured).
If the INTPULSEPOS bit in the ADCCTL1 register is set, tINT coincides with the end of conversion (EOC) signal.

tINT

If the INTPULSEPOS bit is 0, tINT coincides with the end of the S+H window. If tINT triggers a read of the ADC result
register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be taken to make sure
the read occurs after the results latch (otherwise, the previous results are read).
If the INTPULSEPOS bit is 0, and the OFFSET field in the ADCINTCYCLE register is not 0, then there is a delay of
OFFSET SYSCLK cycles before the ADCINT flag is set. This delay can be used to enter the ISR or trigger the DMA
exactly when the sample is ready.
The time from the end of the S+H window until a DMA read of the ADC conversion result is triggered, when
ADCCTL1.TDMAEN = 1.

tDMA

If TDMAEN is set to 0, then the DMA trigger occurs at TINT. In certain conditions, the ADCINT flag can be set before the
ADCRESULT value is latched. To make sure that the DMA read occurs after the ADCRESULT value has been latched,write 1 to ADCCTL1.TDMAEN to enable DMA timings.

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Table 6-22. ADC Timings in 12-bit Mode with SAMPCAPRESETSEL = 0
ADCCLK Prescale(1)

SYSCLK Cycles

ADCCTL2.
PRESCALE

Prescale Ratio

tEOC

tLAT

tINT
(Early)(1)tINT(Late)

tDMA

0

1

15

20

1

15

20

2

2

30

35

1

30

35

3

2.5

38

46

1

38

46

4

3

45

50

1

45

50

5

3.5

53

58

1

53

58

6

4

60

65

1

60

65

7

4.5

68

73

1

68

73

8

5

75

80

1

75

80

9

5.5

83

88

1

83

88

10

6

90

95

1

90

95

11

6.5

98

103

1

98

103

12

7

105

110

1

105

110

13

7.5

113

118

1

113

118

14

8

120

125

1

120

125

15

8.5

128

133

1

128

133

By default, tINT occurs one SYSCLK cycle after the S+H window if INTPULSEPOS is 0. This can be changed by writing to the OFFSET
field in the ADCINTCYCLE register.

Table 6-23. ADC Timings in 12-bit Mode with SAMPCAPRESETSEL = 1
ADCCLK Prescale

SYSCLK Cycles

ADCCTL2.
PRESCALE

Prescale Ratio

tEOC

tLAT

tINT
(Early)(1)tINT(Late)

tDMA

0

1

14

19

1

14

19

2

2

28

33

1

28

33

3

2.5

35

40

1

35

40

4

3

42

47

1

42

47

5

3.5

49

54

1

49

54

6

4

56

61

1

56

61

7

4.5

63

68

1

63

68

8

5

70

75

1

70

75

9

5.5

77

82

1

77

82

10

6

84

89

1

84

89

11

6.5

91

96

1

91

96

12

7

98

103

1

98

103

13

7.5

105

110

1

105

110

14

8

112

117

1

112

117

15

8.5

119

124

1

119

124

(1)

By default, tINT occurs one SYSCLK cycle after the S+H window if INTPULSEPOS is 0. This can be changed by writing to the OFFSET
field in the ADCINTCYCLE register.

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6.15.5 Temperature Sensor
6.15.5.1 Temperature Sensor Electrical Data and Timing

The temperature sensor can be used to measure the device junction temperature. The temperature sensor
is sampled through an internal connection to the ADC and translated into a temperature through TI-provided
software. When sampling the temperature sensor, the ADC must meet the acquisition time in the Temperature
Sensor Characteristics table.
6.15.5.1.1 Temperature Sensor Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONS

Tacc

Temperature Accuracy

tstartup

Start-up time
(TSNSCTL[ENABLE] tosampling temperature sensor)

tacq

ADC acquisition time

MIN

External reference

450

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TYP

MAX

UNIT

±15

°C

500

µs
ns

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6.15.6 Comparator Subsystem (CMPSS)
The Comparator Subsystem (CMPSS) consists of analog comparators and supporting circuits that are useful for
power applications such as peak current mode control, switched-mode power supply, power factor correction,
voltage trip monitoring, and so forth.
The comparator subsystem is built around a number of modules. Each subsystem contains two comparators,
two reference 12-bit DACs, and two digital filters. The subsystem also includes two ramp generators. The
ramp generators ramp up and down. Comparators are denoted "H" or "L" within each module where “H” and“L” represent high and low, respectively. Each comparator generates a digital output which indicates whether
the voltage on the positive input is greater than the voltage on the negative input. The positive input of
the comparator is driven from an external pin (see the Analog Subsystem chapter of the TMS320F28P55x
Real-Time Microcontrollers Technical Reference Manual for mux options available to the CMPSS). The negative
input can be driven by an external pin or by the programmable reference 12-bit DAC. Each comparator output
passes through a programmable digital filter that can remove spurious trip signals. An unfiltered output is alsoavailable if filtering is not required. Two ramp generator circuits are optionally available to control the reference
12-bit DAC values for the high and low comparators in the subsystem. The DAC along with a wrapper can beused to generate a ramp which is used for slope compensation in Peak Current Mode Control (PCMC) and otherapplications.
Each CMPSS includes:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Two analog comparators
Two independently programmable reference 12-bit DACs
Dual decrementing/incrementing ramp generators
Two digital filters with max filter clock prescale of 224
Ability to synchronize submodules with EPWMSYNCPER
Ability to extend clear signal with EPWMBLANK
Ability to synchronize output with SYSCLK
Ability to latch output
Ability to invert output
Option to use hysteresis on the input
Option for negative input of comparator to be driven by an external signal or by the reference DAC
Option for positive input of comparator to be driven by an external signal or by the PGA
Option to use the low comparator DAC output, CMPx_DACL, on an external pin (select instances only,
mutually exclusive with use of compare functionality)
External connection to CMPSS filters
Supports connection with ePWM for diode emulation
Ramp generator prescaler
Wake-up from standby and halt LPM (Low Power Modes) triggered by CMPSS trip outputs

6.15.6.1 CMPx_DACL

Some CMPSS module instances have support for DAC output buffered to a pin. This CMPx_DACL output fromthe CMPSS module uses the low-side DAC of the CMPSS module specified. When using DAC output from a
CMPSS instance, all other CMPSS module features for that instance are unavailable.
For CMPx_DACL instances available for a particular device, please see the DAC column of the Analog Pins andInternal Connections table.
See the Buffered Output from CMPx_DACL Electrical Characteristics section for DAC output capabilities.

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6.15.6.2 CMPSS Connectivity Diagram
CMPSS Module
GPIO Mux
CMP1_HP

Comparator Subsystem 1

CMP1_HN

VDDA

DigitalFilter

DAC12

CMP1_LN

DAC12DigitalFilterCTRIP1H

ePWM X-BAR

CTRIPOUT1H

CTRIP1L

ePWMs

CMP1_DACLCTRIP1LCTRIP2H

Output X-BAR

CTRIP1HCTRIP2LCTRIPOUT1L
CTRIP3H

CMP1_LP
CMP2_HP
CMP2_HN

Comparator Subsystem 2
VDDA

DigitalFilter

DAC12

CMP2_LNDAC12CTRIP2HCTRIP3L

CTRIPOUT2HCTRIP4H

CTRIP2L
DigitalFilterePWM X-BAR

ePWMs

Output X-BAR

GPIO Mux

CTRIP4L

CTRIPOUT2L

CMP2_LP
CMP3_HP
CMP3_HN

Comparator Subsystem 3
VDDA

DigitalFilterCTRIP3HCTRIPOUT3H

DigitalFilterCTRIP3L
CTRIPOUT3L

DAC12

CMP3_LNDAC12CTRIPOUT1H

CMP3_LP
CMP4_HP
CMP4_HN

Comparator Subsystem 4
VDDA

DigitalFilterCTRIP4H
CTRIPOUT4H

DAC12

CMP4_LNCTRIPOUT1L
CTRIPOUT2HDAC12CTRIPOUT2L
CTRIPOUT3H
CTRIPOUT3L

DigitalFilterCTRIP4L
CTRIPOUT4L

CMP4_LPCTRIPOUT4H
CTRIPOUT4L

Figure 6-46. CMPSS Connectivity

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6.15.6.3 Block Diagram

The block diagram for the CMPSS is shown in Figure 6-47.
•

CTRIPx(x= "H" or "L") signals are connected to the ePWM X-BAR for ePWM trip response. See theEnhanced Pulse Width Modulator (ePWM) chapter of the TMS320F28P55x Real-Time Microcontrollers
Technical Reference Manual for more details on the ePWM X-BAR mux configuration.
CTRIPxOUTx(x= "H" or "L") signals are connected to the Output X-BAR for external signaling. See theGeneral-Purpose Input/Output (GPIO) chapter of the TMS320F28P55x Real-Time Microcontrollers Technical
Reference Manual for more details on the Output X-BAR mux configuration.

•

To LPM Wakeup

COMPSTS[COMPHSTS]

2

0

D Q

1

DACHVALS

1|00

TRIGSYNCH

12-bitDACH
CMPx_HNDACHVALA

EN

+
0

COMPH

0

0

_

1
.
.
n

1

1
EXT_FILTIN_H

Ramp Generator(H)

1

D RQ

0

EPWMBLANK_H

CMPSS DACCMPSS Buffered DAC

COMPSTS[COMPHLATCH]

OR

0

COMPSTSCLR[HLATCHCLR]COMPSTSCLR[LSYNCCLREN]COMPSTSCLR[LLATCHCLR]
0ORCOMPDACLCTL[BLANKEN]ANDCOMPCTL[ASYNCLEN]

0

0

1

EPWMBLANK_L

12-bitDACL
CMPx_LN

0D Q

1DACLVALA

EN

0

R Q
COMPL

0

0

_

1
.
.
n

1

1
EXT_FILTIN_L

1

COMPDACLCTL[DACSOURCE]>>1COMPSTS[COMPLSTS]

CMPxDACOUTEN(from Analog Subsystem)

SYSCLKCOMPCTL[COMPLSOURCE]COMPCTL[COMPLINV]

0

2|0

D RQ

Digital R
Filter>0+>

DACLVALSCOMPSTS[COMPLLATCH]

1

1

Buer

OR

>

D Q

OR

0

CTRIPLFILCTL[FILTINSEL]

CMPx_LPSYSCLK >

0
1
2
…
n-1

TRIGSYNCL
1

ORRamp generator

1

Ramp Generator(L)COMPSTS[COMPHSTS]COMPCTL[CTRIPOUTHSEL]

Output MUXANDCOMPDACHCTL[BLANKEN]COMPDACLCTL[BLANKSOURCE]+
16*COMPDACLCTL2[BLANKSOURCEUSEL]COMPDACHCTL2[XTRIGCFG]

1 CTRIPOUTH
To OUTPUT X-BAR
0S

Digital Filter

To EPWM X-BAR

COMPCTL[ASYNCHEN]
0

EPWMSYNCPER_H

OR...
EPWMnBLANK

DigitalFilter R

1

COMPDACHCTL[SWLOADSEL]EPWM1BLANKEPWM2BLANKEPWM3BLANK

Comparator

CTRIPH0

CTRIPHFILCTL[FILTINSEL]COMPSTSCLR[HSYNCCLREN]

COMPDACHCTL[DACSOURCE]

EPWMSYNCPER_L
COMPDACLCTL[RAMPSOURCE]+
16*COMPDACLCTL2[RAMPSOURCEUSEL]COMPDACHCTL[BLANKSOURCE]+
16*COMPDACHCTL2[BLANKSOURCEUSEL]SYSCLKR Q

COMPCTL[COMPHSOURCE]

COMPDACHCTL[RAMPSOURCE]+
16*COMPDACHCTL2[RAMPSOURCEUSEL]EPWM1SYNCPER 0
EPWM2SYNCPER 1
EPWM3SYNCPER 2...
…
EPWMnSYNCPER n-1

CMPx_HP

COMPCTL[CTRIPHSEL]ASYNCH
3SYNCH
2COMPSTS[COMPHSTS]>

COMPDACHCTL2[XTRIGCFG]

D Q

COMPCTL[COMPHINV]>EPWMSYNCPER_H
COMPSTS[COMPLSTS]

COMPDACHCTL[SWLOADSEL]>SYSCLK >COMPCTL[CTRIPLSEL]S
3 CTRIPLCOMPSTS[COMPLSTS]
2 To EPWM X-BAR
SYNCL
1 CTRIPOUTLASYNCLTo OUTPUT X-BAR
0
To LPM Wakeup

COMPCTL[CTRIPOUTLSEL]

CMPxDACLTo PinEnableEPWMSYNCPER_L

A.
B.

CMPxDACL only exists for the CMPSS 1 module on this device.
Enabling the DACL to a pin disables all other functionality: DACH, both COMP, the Ramp Generator, and the digital filters.

Figure 6-47. CMPSS Module Block Diagram
Each reference 12-bit DAC can be configured to drive a reference voltage into the negative input of therespective comparator. Some CMPSS instances also allow the low DAC output to be routed to a pin to act as
an external DAC. In this case, all other CMPSS module functionality is not useable, including the high DAC, bothcomparators, ramp generation, and the digital filters. The reference 12-bit DAC is illustrated in Figure 6-48.

VDDA

DACREFDACHVALA

12-bit DACOUTH
DACH To COMPHDACLVALA

12-bit DACOUTL
DACL To COMPLVSSA
Figure 6-48. Reference DAC Block Diagram

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6.15.6.4 CMPSS Electrical Data and Timing
6.15.6.4.1 CMPSS Comparator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETERTPUTEST CONDITIONS

MIN

TYP

MAX

UNIT

500

µs

0

VDDA

V

–20

20

mV

Power-up time

Comparator input (CMPINxx) range
Low common mode, inverting
input set to 50mV

Input referred offset error

Hysteresis(1)

1x

4

12

20

2x

17

24

33

3x

25

36

50

4x

30

48

67

21

60

Step response
Response time (delay from CMPINx input change toRamp response (1.65V/µs)
output on ePWM X-BAR or Output X-BAR)
Ramp response (8.25mV/µs)
PSRR

Power Supply Rejection Ratio

CMRR

Common Mode Rejection Ratio

(1)

26

Up to 250 kHz

LSB

ns

30

ns

46

dB

40

dB

The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the
CMPSS DAC reference voltage. Hysteresis is available for all comparator input source configurations.

CMPSS Comparator Input Referred Offset and Hysteresis
Input Referred Offset
CTRIPx
Logic LevelCTRIPx = 1

CTRIPx = 00

COMPINxP
Voltage

CMPINxN or
DACxVAL

Figure 6-49. CMPSS Comparator Input Referred Offset
Hysteresis
CTRIPx
Logic LevelCTRIPx = 1

CTRIPx = 00

CMPINxN or
DACxVALCOMPINxP
Voltage

Figure 6-50. CMPSS Comparator Hysteresis

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6.15.6.4.2 CMPSS DAC Static Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETERCMPSS DAC output range

TEST CONDITIONSMINInternal reference

TYP

MAX

UNIT

0

VDDA

V

Static offset error(1)

–25

25

mV

Static gain error(1)–22% of FSR

Static DNL

Endpoint corrected

>–1

4

LSB

Static INL

Endpoint corrected

–16

16

LSB

Settling time

Settling to 1LSB after full-scale output change

1

Resolution

12

CMPSS DAC output disturbance(2)Error induced by comparator trip or CMPSSDAC code change within the same CMPSS
module–100

CMPSS DAC disturbance time(2)

(1)
(2)

µs
bits

100

LSB

200

ns

Includes comparator input referred errors.
Disturbance error may be present on the CMPSS DAC output for a certain amount of time after a comparator trip.

6.15.6.4.3 CMPSS Illustrative Graphs

Offset Error

Figure 6-51. CMPSS DAC Static Offset

158

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Ideal Gain
Actual Gain

Actual Linear Range

Figure 6-52. CMPSS DAC Static Gain

Linearity Error

Figure 6-53. CMPSS DAC Static Linearity
6.15.6.4.4 Buffered Output from CMPx_DACL Operating Conditions
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
RL

Resistive Load(2)CLCapacitive Load

TEST CONDITIONS

MIN

TYP

MAX

5

kΩ
100

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UNIT
pF

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6.15.6.4.4 Buffered Output from CMPx_DACL Operating Conditions (continued)
over recommended operating conditions (unless otherwise noted)(1)
PARAMETERTEST CONDITIONSValid Output Voltage Range(3)VOUT

Reference Voltage(4)
(1)
(2)
(3)
(4)

MIN

TYP

MAX

UNIT

RL = 5 kΩ

0.3

VDDA – 0.3

V

RL = 1 kΩ

0.6

VDDA – 0.6

V

VREFHI

2.4

VDDA

V

2.5 or 3.0

Typical values are measured with VREFHI = 3.3 V and VREFLO = 0 V, unless otherwise noted. Minimum and maximum values aretested or characterized with VREFHI = 2.5 V and VREFLO = 0 V.
DAC can drive a minimum resistive load of 1 kΩ, but the output range will be limited.
This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear
due to the buffer.
For best PSRR performance, VREFHI should be less than VDDA.

6.15.6.4.5 Buffered Output from CMPx_DACL Electrical Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

GeneralResolution(4)12Load Regulation

–1

bits
1

Glitch Energy

1.5

mV/V
V-ns

Voltage Output Settling Time Full-Scale

Settling to 2 LSBs after 0.3Vto-3V transition2µs

Voltage Output Settling Time 1/4th Full-Scale

Settling to 2 LSBs after 0.3Vto-0.75V transition

1.6

µs

Voltage Output Slew Rate

Slew rate from 0.3V-to-3V
transition

4.5

V/µs

Load Transient Settling Time5-kΩ Load

328

ns

TPU

Bandgap Not Enabled

500

µs

Power Up Time

2.8

DC Characteristics
OffsetOffset Error

–100

100

mV

Gain

Gain Error(2)

–1.5

1.5

% of FSR

DNL

Differential Non Linearity(4)Endpoint corrected–22

LSB (12-bit)

INL

Integral Non Linearity

Endpoint corrected

–10

10

LSB (12-bit)

AC Characteristics
Output Noise

Integrated noise from 100 Hz
to 100 kHz

600

µVrms

Noise density at 10 kHz

800

nVrms/√Hz

SNR

Signal to Noise Ratio

1 kHz, 200 KSPS

64

dB

THD

Total Harmonic Distortion

1 kHz, 200 KSPS

–64.2

dB

SFDR

Spurious Free Dynamic
Range

1 kHz, 200 KSPS

66

dB

SINAD

Signal to Noise and Distortion
1 kHz, 200 KSPS
Ratio

61.7

dB

PSRR

Power Supply Rejection
Ratio(3)

DC

70

dB

100 kHz

30

dB

(1)
(2)
(3)
(4)

Typical values are measured with VREFHI = 3.3 V and VREFLO = 0 V, unless otherwise noted. Minimum and maximum values aretested or characterized with VREFHI = 2.5 V and VREFLO = 0 V.
Gain error is calculated for linear output range.
VREFHI = 3.2 V, VDDA = 3.3 V DC + 100 mV Sine.
11-bit effective (monotonic response).

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6.15.7 Buffered Digital-to-Analog Converter (DAC)
The buffered DAC module consists of an internal 12-bit DAC and an analog output buffer that can drive an
external load. For driving even higher loads than typical, a trade-off can be made between load size andoutput voltage swing. For the load conditions of the buffered DAC, see the Buffered DAC Electrical Data andTiming section. The buffered DAC is a general-purpose DAC that can be used to generate a DC voltage or AC
waveforms such as sine waves, square waves, triangle waves and so forth. Software writes to the DAC value
register can take effect immediately or can be synchronized with EPWMSYNCO events.
Each buffered DAC has the following features:• 12-bit resolution• Selectable reference voltage source• x1 and x2 gain modes when using internal VREFHI• Ability to synchronize with EPWMSYNCPERDAC Module
Reference Voltage Source
Output Buer
12-Bit DAC
Internal Reference Circuit

DACCTL[DACREFSEL]ANAREFx1P65SEL
0
2.5 V
Internal Reference
Circuit

DACREF01
11.65 V

0

1

ANAREFPCTL[REFPMUXSELx]

VREFHIVDDA

SYSCLKDACVALS

DACCTL[LOADMODE]

>

D

Q

0

D

Q

1

DACVALAEPWM1SYNCPER
EPWM2SYNCPER
EPWM3SYNCPER...
EPWMnSYNCPER

0DACOUT

12-bit
DAC

EN

1
VSSA
2
...

VSSA
DACCTL[MODE](Select x1 or x2 gain)

n-1

DACCTL[SYNCSEL]A.

VDAC is not available for this device; so, VREFHI and VSSA are the reference voltages.

Figure 6-54. DAC Module Block Diagram

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6.15.7.1 Buffered DAC Electrical Data and Timing
6.15.7.1.1 Buffered DAC Operating Conditions
over recommended operating conditions (unless otherwise noted)(1)
PARAMETERTEST CONDITIONSRLResistive Load(2)CLCapacitive Load

VOUT

Valid Output Voltage Range(3)

(2)
(3)
(4)

TYP

MAX

5

Reference Voltage(4)
(1)

MIN

UNIT
kΩ

100

pF

RL = 5 kΩ

0.3

VDDA – 0.3

V

RL = 1 kΩ

0.6

VDDA – 0.6

V

VREFHI

2.4

VDDA

V

2.5 or 3.0

Typical values are measured with VREFHI = 3.3 V and VREFLO = 0 V, unless otherwise noted. Minimum and maximum values aretested or characterized with VREFHI = 2.5 V and VREFLO = 0 V.
DAC can drive a minimum resistive load of 1 kΩ, but the output range will be limited.
This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear
due to the buffer.
For best PSRR performance, VREFHI should be less than VDDA.

6.15.7.1.2 Buffered DAC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

GeneralResolution

12

Load Regulation

–1

bits
1

Glitch Energy

1.5

mV/V
V-ns

Voltage Output Settling Time Full-Scale

Settling to 2 LSBs after 0.3Vto-3V transition2µs

Voltage Output Settling Time 1/4th Full-Scale

Settling to 2 LSBs after 0.3Vto-0.75V transition

1.6

µs

Voltage Output Slew Rate

Slew rate from 0.3V-to-3V
transition

4.5

V/µs

328

ns

5-kΩ Load

Load Transient Settling Time1-kΩ Load

Reference Input Resistance(2)
TPU

2.8

557

ns

240

kΩ

External Reference mode

500

µs

Internal Reference mode

5000

µs

10

mV

VREFHIPower Up Time

160

200

DC Characteristics
OffsetOffset Error

Gain

Gain Error(3)Midpoint–10

2.5% of FSR

DNL

Differential Non Linearity(4)Endpoint corrected

–1

±0.4

1

LSB

INL

Integral Non Linearity

Endpoint corrected

–5

±2

5

LSB

–2.5

AC Characteristics
Output Noise

Integrated noise from 100 Hz
to 100 kHz

600

µVrms

Noise density at 10 kHz

800

nVrms/√Hz

SNR

Signal to Noise Ratio

1 kHz, 200 KSPS

64

dB

THD

Total Harmonic Distortion

1 kHz, 200 KSPS

–64.2

dB

SFDR

Spurious Free Dynamic
Range

1 kHz, 200 KSPS

66

dB

SINAD

Signal to Noise and Distortion
1 kHz, 200 KSPS
Ratio

61.7

dB

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6.15.7.1.2 Buffered DAC Electrical Characteristics (continued)
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
PSRR
(1)
(2)
(3)
(4)
(5)

TEST CONDITIONSPower Supply Rejection
Ratio(5)

MIN

TYP

MAX

UNIT

DC

70

dB

100 kHz30

dB

Typical values are measured with VREFHI = 3.3 V and VREFLO = 0 V, unless otherwise noted. Minimum and maximum values aretested or characterized with VREFHI = 2.5 V and VREFLO = 0 V.
Per active Buffered DAC module.
Gain error is calculated for linear output range.
The DAC output is monotonic.
VREFHI = 3.2 V, VDDA = 3.3 V DC + 100 mV Sine.

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6.15.8 Programmable Gain Amplifier (PGA)The Programmable Gain Amplifier (PGA) is used to amplify an input voltage for the purpose of increasing theeffective resolution of the downstream ADC and CMPSS modules.
The integrated PGA helps to reduce cost and design effort for many control applications that traditionally require
external, stand-alone amplifiers. On-chip integration ensures that the PGA is compatible with the downstream
ADC and CMPSS modules. Software-selectable gain and filter settings make the PGA adaptable to various
performance needs.
The PGA has the following features:• Rail to rail input and output voltage within VDDA and VSSA range• Programmable gain modes including unity gain and other values from 2X - 64X• Standalone gain mode using off-chip passive components• Post-gain filtering using on-chip resistors• Differential input support• Hardware assisted chopping for offset reduction• Support for Kelvin ground connections using PGA_INM pins
The active component in the PGA is an embedded operational amplifier (op amp) that is configured as a
non-inverting or inverting amplifier with internal feedback resistors. These internal feedback resistor values are
paired to produce software selectable voltage gains.
Three PGA signals are available at the device pins:• PGA_INP is the positive input to the PGA op-amp.
• PGA_INM is the negative input to the PGA op-amp. See the device data manual for more information.
• PGA_OUT supports op-amp output filtering with RC components. The filtered signal is available for sampling
and monitoring by on-chip ADC and CMPSS modules.
PGA_OUT_INT is an internal signal at the op amp output. It is available for sampling and monitoring by theinternal ADC and CMPSS modules. Figure 6-55 shows the PGA block diagram.

To ADC and CMPSSPGA_OUTENABLE & FILT_RES_SEL=0

VDDA

FILT_RES_SEL+_

PGA_INP

PGA_OUTRFILT
PGA_OUTENABLE

PGA_OUTENABLE &FILT_RES_SEL

VSSA
Ria

OUT_EN_INTGAIN &FILT_RES_SEL=0
PGA_OUT_INT

To ADC and CMPSSRib

PGA_INM

Figure 6-55. PGA Block Diagram

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6.15.8.1 PGA Electrical Data and Timing
6.15.8.1.1 PGA Operating Conditions
over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSPGA Output Range(1)MIN
VSSA+0.025

Cap Load on PGA Out
(1)

TYP

MAX
VDDA-0.025

40

UNIT
V
pF

This is the linear output range of the PGA. The PGA can output voltages outside this range, but the voltages will not be linear.

6.15.8.1.2 PGA Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

GeneralGain = 1

125

Gain = 2/-1

146

Min ADC S+H Settling within Gain = 4/-3
±1 ADC LSB Accuracy
Gain = 8/-7
(No Filter; All Gain Settings;(4)
Gain = 16/-15
Single ADC Driven)

125

Gain = 32/-31

322

Gain = 64/-63

380

Gain = 1

146

Gain = 2/-1

146

154

ns

227

Min ADC S+H Settling within Gain = 4/-3
±1 ADC LSB Accuracy
Gain = 8/-7
(No Filter; All Gain Settings;
Gain = 16/-15
Two ADC Driven) (4)155

Gain = 32/-31

352

Gain = 64/-63

450

113
ns

230

1
2, 4, 8, 16, 32, 64

Gain Settings-1, -3, -7, -15, -31,
-63
Short Circuit Current (5)Full Scale Step Response(No Filter) Settling within
0.05% Accuracy(4)

41
450

ns

G = 64/-63

370

ns

10

µs

Settling Time: Gain
SwitchingSlew Rate

Slew Rate

mA

G<64

Naked OPA Mode

12

V/µs

Gain = 1

12

V/µsGain = 2/-1

24

V/µs

Gain = 4/-3

43

V/µs

Gain = 8/-7

67

V/µs

Gain = 16/-15

35

V/µs

Gain = 32/-31

29

V/µs

Gain = 64/-63

26

V/µs

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6.15.8.1.2 PGA Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER

Ria

Rib

Filter Resistor Targets

Gain Bandwidth Product(Naked Op-Amp Mode)

Closed Loop -3bd BW

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Gain = 1

256kΩGain = 2/-1

16kΩ

Gain = 4/-38kΩ

Gain = 8/-7

8kΩGain = 16/-15

8kΩ

Gain = 32/-31

8kΩGain = 64/-63

4kΩGain = 10kΩGain = 2/-1

16kΩ

Gain = 4/-324kΩGain = 8/-756kΩGain = 16/-15

120

kΩ

Gain = 32/-31

248

kΩ

Gain = 64/-63

252

kΩ

RFILT = 800 Ω

800Ω

RFILT = 400 Ω

400Ω

RFILT = 200 Ω

200Ω

RFILT = 100 Ω

100Ω

RFILT = 50 Ω

50Gain = 1

7

MHz

Gain = 1

15

MHz

Gain = 2/-1

14

MHz

Gain = 4/-3

13.5

MHz

Gain = 8/-7

12

MHz

Gain = 16/-15

11

MHz

Gain = 32/-31

5.5

MHz

Gain = 64/-63

5.0

MHz

62

Ω

DC Characteristics
Gain Error(1)Gain = 1

–0.18

0.18

%

Gain Error(1)Gain = 2, -1

–0.45

0.45

%

Gain Error(1)Gain = 4, -3

–0.70

0.70

%

Gain Error(1)Gain = 8, -7

–0.84

0.84

%

Gain Error(1)Gain = 16, -15

–0.90

0.90

%

Gain Error(1)Gain = 32, -31

–1.05

1.05

%

Gain Error(1)Gain = 64, -63–1.82

Offset Error(2)Input Referred–3.0

Offset Temp Coefficient

Input Referred

Offset Error - Chopped
Offset Temp Coefficient Chopped
DC Code Spread

166

G<64
G = 64/-63

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1.82

%

3.0

mV

-7.0

7.0

µV/C

-0.8

0.8

mV

+/-1.0

0.3

µV/C

2.5

12b LSB

412b LSB

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6.15.8.1.2 PGA Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

AC Characteristics
Phase Margin
Naked OPA

Cload = 40pF
G=1

45

Deg

Aol (Open loop voltage gain) RL = 7.5kΩ to GND
Naked OPA
0.3V<VO<VDDA-0.3V

94dB

THD + Noise (THD+N)
Naked OPA

fin = 1kHz
G=1

82

dB

Gain = 1

68

Gain = 2, -1

68

Gain = 4, -3

66

Gain = 8, -7

62Gain = 16, -15

58

Gain = 32, -31

55

SNR 10kHz (With ADC)

THD(3)THD(Up to 100kHz) (3)CMRR

PSRR(3)Noise PSD(3)Integrated Noise(Input Referred)(3)
(1)
(2)
(3)
(4)
(5)

dB

Gain = 64, -63

51

DC

–78

Gain = 1–58

Gain = 2, -1–70Gain = 4, -3–70Gain = 8, -7–70Gain = 16, -15–70

Gain = 32, -31–58

Gain = 64, -63–58

DC: VIN <=1.5V

–86

dB

DC: Full Input Range

-77

dB

Up to 100 kHz

–50

dB

DC

–75

dB

Up to 10 kHz

–60

dB

Up to 100 kHz

–40

dB

1 kHz

200

nV/sqrt(Hz)10 kHz100nV/sqrt(Hz)3 Hz to 30 MHz

100

µV

dB

dB

Includes ADC gain error.
Includes ADC offset error.
Performance of PGA alone.
Step response time w filter = tS+H + 7.6*Rfilt* Cfilt
Assumes no filter circuit

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

6.16 Control Peripherals
6.16.1 Enhanced Pulse Width Modulator (ePWM)
The ePWM peripheral is a key element in controlling many of the power electronic systems found in bothcommercial and industrial equipment. The ePWM type-4 module is able to generate complex pulse width
waveforms with minimal CPU overhead by building the peripheral up from smaller modules with separate
resources that can operate together to form a system. Some of the highlights of the ePWM type-4 module
include complex waveform generation, dead-band generation, a flexible synchronization scheme, advanced
trip-zone functionality, and global register reload capabilities.
The ePWM and eCAP synchronization scheme on the device provides flexibility in partitioning the ePWM andeCAP modules and allows localized synchronization within the modules.
Figure 6-56 shows the ePWM module. Figure 6-57 shows the ePWM trip input connectivity.

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Time-Base (TB)
TBPRD Shadow (24)

ePWM
SYNC
Scheme

EXTSYNCINTBPRDHR (8)TBPRD Active (24)

EXTSYNCOUT

CTR=PRD
EPWMxSYNCITBCTL[PHSEN]TBCTL[SWFSYNC]Counter
Up/Down(16 bit)

DCAEVT1/sync(A)DCBEVT1/sync(A)CTR=ZERO

TBCTR
Active (16)

CTR=PRD
CTR=ZERO

CTR_Dir
TBPHSHR (8)

16

Phase
Control

Event
Trigger
And
Interrupt(ET)

CTR=CMPD
CTR_Dir

Counter Compare (CC)CTR=CMPA

EPWMxSOCA

CTR=PRD or ZERO
CTR=CMPA
CTR=CMPB
CTR=CMPC

8TBPHS Active (24)EPWMx_INTActionQualifier(AQ)

EPWMxSOCB

On-chip
ADC

ADCSOCOUTSELECTDCAEVT1.soc(A)DCBEVT1.soc(A)Select and pulse stretch
for external ADC

CMPAHR (8)16

HiRes PWM (HRPWM)
CMPAHR (8)ADCSOCAO
ADCSOCBOCMPA Active (24)EPWMA

CMPA Shadow (24)ePWMxA
Dead
Band
(DB)

CTR=CMPBCMPBHR (8)PWM
Chopper
(DB)

Trip
Zone
(TZ)

16
CMPB Active (16)EPWMB

ePWMxBCMPB Shadow (16)
CMPBHR (8)TBCNT (16)CTR=CMPC

CTR=ZERODCAEVT1.inter

CMPC[15-0]

DCBEVT1.inter16

DCAEVT2.inter
CMPC Active (16)

DCBEVT2.inter

CMPC Shadow (16)EPWMx_TZ_INT
TZ1 to TZ3
EMUSTOP
CLOCKFAIL
EQEPxERRDCAEVT1.force(A)DCBEVT1.force(A)TBCNT (16)CTR=CMPDDCAEVT2.force(A)DCBEVT2.force(A)CMPD[15-0]

16

CMPD Active (16)
CMPD Shadow (16)A.

These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN inputs.

Figure 6-56. ePWM Submodules and Critical Internal Signal Interconnects

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Figure 6-57. ePWM Trip Input Connectivity

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6.16.1.1 Control Peripherals Synchronization

The ePWM and eCAP synchronization scheme on the device provides flexibility in partitioning the ePWM andeCAP modules and allows localized synchronization within the modules. Figure 6-58 shows the synchronization
scheme.

CTR=CMPD

CLR
One Shot
Latch

DCAEVT1.sync
DCBEVT1.sync

0

EPWMSYNCOUTENTBCTL2[OSHTSYNCMODE]

CTR=CMPCTBCTL3[OSSFRCEN]

CTR=ZERO
CTR=CMPB:ULWH ³1´ WR
TBCTL2[OSHTSYNC]:ULWH ³1´ WR
GLDCTL2[OSHTLD]TBCTLSWFSYNC

Set

Q

1

SWEN
ZEROEN0

CMPBEN

1

OR

CMPCEN0
EPWMxSYNCOUT

1
0

CMPDENDCARVT1EN
TBCTL2[SELFCLRTRREM]DCBEVT1EN

Clear
RegisterDisable0

EPWM1SYNCOUT|||

EPWMxSYNCOUT

EPWMxSYNCIN

ECAP1SYNCOUT

HRPCTL[PWMSYNCSELX]CTR=CMPC UP|||

CTR=CMPC DOWN

ECAPySYNCOUTCTR=CMPD UP

Other Sources

CTR=CMPD DOWNHRPCTL[PWMSYNCSEL]EPWMSYNCINSEL

EPWMxSYNCPER
CMPSS
DAC

CTR=PRD
CTR=ZERO

Note: SYNCO and SYNCOUT are used interchangeably

Figure 6-58. Synchronization Chain Architecture

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6.16.1.2 ePWM Electrical Data and Timing

For an explanation of the input qualifier parameters, see the General-Purpose Input Timing Requirements table.
6.16.1.2.1 ePWM Timing Requirements
MIN
Asynchronoustw(SYNCIN)

With input qualifier

UNIT

2tc(EPWMCLK)

Synchronous

Sync input pulse widthMAX

2tc(EPWMCLK)

cycles1tc(EPWMCLK) + tw(IQSW)

6.16.1.2.2 ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER(1)tw(PWM)

Pulse duration, PWMx output high/lowtw(SYNCOUT)

Sync output pulse widthtd(TZ-PWM)

Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
Delay time, trip input active to PWM Hi-Z

(1)

MIN

MAX

UNIT

20

ns

8tc(SYSCLK)

cycles25

ns

20-pF load on pin.

6.16.1.2.3 Trip-Zone Input Timing

For an explanation of the input qualifier parameters, see the General-Purpose Input Timing Requirements table.
6.16.1.2.3.1 Trip-Zone Input Timing Requirements
MIN
Asynchronous
tw(TZ)

Pulse duration, TZx input low

UNIT
cycles2tc(EPWMCLK)

cycles1tc(EPWMCLK) + tw(IQSW)

cyclesSynchronous
With input qualifierMAX

1tc(EPWMCLK)

6.16.1.2.3.2 PWM Hi-Z Characteristics Timing Diagram
EPWMCLK

tw(TZ)(A)

TZ

td(TZ-PWM)
(B)

PWM

A.
B.

TZ: TZ1, TZ2, TZ3, TRIP1–TRIP12
PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery
software.

Figure 6-59. PWM Hi-Z Characteristics

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6.16.2 High-Resolution Pulse Width Modulator (HRPWM)
The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using a
dedicated calibration delay line. For each ePWM module, there are two HR outputs:• HR Duty and Deadband control on Channel A• HR Duty and Deadband control on Channel B
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can beachieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:• Significantly extends the time resolution capabilities of conventionally derived digital PWM• This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual edge
control for frequency/period modulation.
• Finer time granularity control or edge positioning is controlled through extensions to the Compare A, B,
phase, period and deadband registers of the ePWM module.
6.16.2.1 HRPWM Electrical Data and Timing
6.16.2.1.1 High-Resolution PWM Characteristics
PARAMETERMIN

Micro Edge Positioning (MEP) step size(1)
(1)

TYP

MAX UNIT

150

310

ps

The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO functions in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLK period dynamically while the HRPWM is in operation.

6.16.3 External ADC Start-of-Conversion Electrical Data and Timing
6.16.3.1 External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
tw(ADCSOCL)

MIN

Pulse duration, ADCSOCxO low

32tc(SYSCLK)

MAX

UNIT
cycles6.16.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
tw(ADCSOCL)ADCSOCAOorADCSOCBO

Figure 6-60. ADCSOCAO or ADCSOCBO Timing

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6.16.4 Enhanced Capture (eCAP)
The features of the eCAP module include:••••

Speed measurements of rotating machinery (for example, toothed sprockets sensed by way of Hall sensors)
Elapsed time measurements between position sensor pulses
Period and duty cycle measurements of pulse train signals
Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors

The eCAP module features described in this chapter include:
•
•
•
•
•
•
•
•

4-event time-stamp registers (each 32 bits)
Edge polarity selection for up to four sequenced time-stamp capture events
Interrupt on either of the four events
Single-shot capture of up to four event time-stamps
Continuous mode capture of time stamps in a four-deep circular buffer
Absolute time-stamp capture
Difference (Delta) mode time-stamp capture
When not used in capture mode, the eCAP module can be configured as a single-channel PWM output

The capture functionality of the Type 1 eCAP is enhanced from the Type 0 eCAP with the following added
features:• Event filter reset bit– Writing a 1 to ECCTL2[CTRFILTRESET] clears the event filter, the modulo counter, and any pending
interrupts flags. Resetting the bit is useful for initialization and debug.
• Modulo counter status bits
– The modulo counter (ECCTL2 [MODCNTRSTS]) indicates which capture register is loaded next. In theType 0 eCAP, to know the current state of the modulo counter was not possible• DMA trigger source– eCAPxDMA was added as a DMA trigger. CEVT[1-4] can be configured as the source for eCAPxDMA.
• Input multiplexer– ECCTL0 [INPUTSEL] selects one of 128 input signals, which are detailed in the Configuring Device
Pins for the eCAP section of the Enhanced Capture (eCAP) chapter in the TMS320F28P55x Real-Time
Microcontrollers Technical Reference Manual .
• EALLOW protection– EALLOW protection was added to critical registers. To maintain software compatibility with Type-0,
configure DEV_CFG_REGS.ECAPTYPE to make these registers unprotected.
The capture functionality of the Type 2 eCAP is enhanced from the Type 1 eCAP with the following added
features:• Added ECAPxSYNCINSEL register– ECAPxSYNCINSEL register is added for each eCAP to select an external SYNCIN. Every eCAP can havea separate SYNCIN signal.

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6.16.4.1 eCAP Block Diagram
ECCTL2 [ SYNCI_EN, SYNCOSEL, SWSYNC]
ECCTL2[CAP/APWM]

SYNC

CTRPHS(phase register−32 bit)
ECAPxSYNCINAPWM Mode
OVF

TSCTR
(counter−32 bit)

ECAPxSYNCOUTRST

CTR_OVFCTR [0−31]

Delta−Mode

PRD [0−31]

PWM
CompareLogic

OutputX-Bar

CMP [0−31]
32
CTR=PRD

CTR [0−31]

CTR=CMP32
PRD [0−31]
ECCTL1 [ CAPLDEN, CTRRSTx]

HRCTRL[HRE]
32
32

APRD
shadow
HRCTRL[HRE]

LD1

CAP1
(APRD Active)

Polarity
SelectLD

32
CMP [0−31]32

HRCTRL[HRE]

32
32

CAP2
(ACMP Active)

Polarity
Select

LD2
LD

32

Other
Sources[127:16]

EventqualifierACMP
shadow

HRCTRL[HRE]EventPrescale

16
ECCTL1[PRESCALE][15:0]

Input
X-Bar

32
32

Polarity
SelectLD3

CAP3(APRD Shadow)

LD

CAP4
(ACMP Shadow)LD

HRCTRL[HRE]
32
32

LD4

Polarity
SelectEdge Polarity SelectECCTL1[CAPxPOL]

44ECCTL2[CTRFILTRESET]ECAPx(to ePIE)

Interrupt
Trigger
andFlag
Control

CTR_OVF

Continuous /Oneshot
Capture Control

MODCNTRSTSCTR=PRD
CTR=CMPECCTL2 [ REARM, CONT_ONESHT, STOP_WRAP]

Registers: ECEINT, ECFLG, ECCLR, ECFRC
Capture Pulse

SYSCLK
HRCLK

HR Submodule
HR Input

ECAPx_HRCAL(to ePIE)

Figure 6-61. eCAP Block Diagram

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6.16.4.2 eCAP Synchronization

The eCAP modules can be synchronized with each other by selecting a common SYNCIN source. SYNCIN
source for eCAP can be either software sync-in or external sync-in. The external sync-in signal can come from
EPWM, eCAP, or X-Bar. The SYNC signal is defined by the selection in the ECAPxSYNCINSEL[SEL] bit for
ECAPx as shown in Figure 6-62.
ECAPx

Disable0x0
0x1

ECAPxSYNCIN

ECAPxSYNCIN
Signals

ECCTL2[SWSYNC](EPWM, ECAP,INPUTXBAR, «)DisableEPWMxSYNCOUT
EXTSYNCOUT

ECAPxSYNCOUT

CTR=PRDDisableSYNCSELECT[SYNCOUT]

0xn
ECCTL2[SYNCOSEL]ECAPSYNCINSEL[SEL]

Figure 6-62. eCAP Synchronization Scheme
6.16.4.3 eCAP Electrical Data and Timing
6.16.4.3.1 eCAP Timing Requirements
MIN
tw(CAP)

Capture input pulse width

Asynchronous

2tc(SYSCLK)

Synchronous

2tc(SYSCLK)With input qualifier

NOM

MAX

UNIT
ns

1tc(SYSCLK) + tw_(IQSW)

6.16.4.3.2 eCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
tw(APWM)

176

Pulse duration, APWMx output high/low

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MIN

TYP

20

MAX

UNIT
ns

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6.16.5 Enhanced Quadrature Encoder Pulse (eQEP)
The eQEP module on this device is Type-2. The eQEP interfaces directly with linear or rotary incremental
encoders to obtain position, direction, and speed information from rotating machines used in high-performance
motion and position control systems.
The eQEP peripheral contains the following major functional units (see Figure 6-63):• Programmable input qualification for each pin (part of the GPIO MUX)
• Quadrature decoder unit (QDU)• Position counter and control unit for position measurement (PCCU)• Quadrature edge-capture unit for low-speed measurement (QCAP)• Unit time base for speed/frequency measurement (UTIME)• Watchdog timer for detecting stalls (QWDOG)• Quadrature Mode Adapter (QMA)
Systemcontrol registers

To CPU

EQEPxENCLK

Data bus

SYSCLKQCAPCTL

QCPRD
QCTMR

16

16

Enhanced QEP (eQEP) peripheral

16
Quadrature
capture unit
(QCAP)QCTMRLATQCPRDLAT
Registers
used bymultiple units
QEPCTLQEPSTS
QFLG

QUTMR
QUPRD

QWDTMRQWDPRD

32

16

UTIME

UTOUT

QDECCTL16

QWDOG
WDTOUT

PIE

QCLK
QDIR
QI
QS
PHE

EQEPxINT
32

Position counter/
control unit
(PCCU)QPOSLATQPOSSLATQPOSILAT

QMA

Quadrature
decoder(QDU)

PCSOUT

32

32

QPOSCNTQPOSINITQPOSMAXQPOSCMP16

EQEPxAIN

EQEPx_AEQEPxBIN

EQEPx_BEQEPxIIN
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOEGPIO
MUX

EQEPx_INDEXEQEPx_STROBE

QEINT
QFRC
QCLR
QPOSCTL

Figure 6-63. eQEP Block Diagram

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6.16.5.1 eQEP Electrical Data and Timing

For an explanation of the input qualifier parameters, see the General-Purpose Input Timing Requirements table.
6.16.5.1.1 eQEP Timing Requirements
MIN
Synchronous(1)tw(QEPP)QEP input period

tw(INDEXH)QEP Index Input High timetw(INDEXL)QEP Index Input Low timetw(STROBH)QEP Strobe High timetw(STROBL)QEP Strobe Input Low time(1)

Synchronous with input qualifier2tc(SYSCLK)
2tc(SYSCLK)

Synchronous with input qualifier2tc(SYSCLK)
2tc(SYSCLK)

cycles2tc(SYSCLK) + tw(IQSW)

Synchronous(1)Synchronous with input qualifier

cycles2tc(SYSCLK) + tw(IQSW)

Synchronous(1)Synchronous with input qualifier

cycles2tc(SYSCLK) + tw(IQSW)

Synchronous(1)UNIT
cycles2[1tc(SYSCLK) + tw(IQSW)]Synchronous(1)Synchronous with input qualifierMAX

2tc(SYSCLK)

cycles2tc(SYSCLK) + tw(IQSW)The GPIO GPxQSELn Asynchronous mode should not be used for eQEP module input pins.

6.16.5.1.2 eQEP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER

MIN

MAX

UNIT

td(CNTR)xin

Delay time, external clock to counter increment

5tc(SYSCLK)

cyclestd(PCS-OUT)QEP

Delay time, QEP input edge to position compare sync output

7tc(SYSCLK)

cycles178

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6.17 Communications Peripherals
6.17.1 Modular Controller Area Network (MCAN)
The Controller Area Network (CAN) is a serial communications protocol that efficiently supports distributed
real-time control with a high level of reliability. CAN has high immunity to electrical interference and the ability todetect various type of errors. In CAN, many short messages are broadcast to the entire network, which provides
data consistency in every node of the system.
The MCAN module supports both classic CAN and CAN FD (CAN with flexible data-rate) protocols. The CAN FD
feature allows higher throughput and increased payload per data frame. Classic CAN and CAN FD devices may
coexist on the same network without any conflict provided that partial network transceivers, which can detectand ignore CAN FD without generating bus errors, are used by the classic CAN devices. The MCAN module iscompliant to ISO 11898-1:2015.
Note
The availability of the CAN FD feature is dependent on the device's part number. Refer to the device
data sheet for more information.

DeviceMCANSS
NMI

Uncorrectable ECC

PIECorrectable ECC
Configurable Interrupts (2 lines)
Counter Overflow and Clock Stop/
Wakeupmcanss_tx

CPU BUSSYSCLK

Peripheral Clock
Clock disable/
enableMCAN Bit Clockmcanss_rx

Bit Timing Clock
WakeupClock Stop and Wakeup
RESET

Reset

Figure 6-64. MCAN Module Overview
The MCAN module implements the following features:
•
•
•
•

•

Conforms with CAN Protocol 2.0 A, B and ISO 11898-1:2015
Full CAN FD support (up to 64 data bytes)
AUTOSAR and SAE J1939 support
Flexible Message RAM allocation (maximum configuration below is for a device with 4352 32-bit word
message RAM)
– Up to 32 dedicated transmit buffers– Configurable transmit FIFO, up to 32 elements– Configurable transmit queue, up to 32 elements– Configurable transmit Event FIFO, up to 32 elements– Up to 64 dedicated receive buffers– Two configurable receive FIFOs, up to 64 elements each
– Up to 128 filter elements
Loop-back mode for self-test

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•
•
•
•
•
•

Maskable interrupt (two configurable interrupt lines, correctable ECC, counter overflow and clock stop/
wakeup)Non-maskable interrupt (uncorrectable ECC)
Two clock domains (CAN clock/host clock)
ECC check for Message RAM
Clock stop and wake-up support
Timestamp counter

Non-supported features:
•
•
•

180

Host bus firewall
Clock calibration
Debug over CAN

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6.17.2 Inter-Integrated Circuit (I2C)
The I2C module has the following features:• Compliance with the NXP Semiconductors I2C-bus specification (version 2.1):– Support for 8-bit format transfers– 7-bit and 10-bit addressing modes– General call
– START byte mode
– Support for multiple controller-transmitters and target-receivers– Support for multiple target-transmitters and controller-receivers– Combined controller transmit/receive and receive/transmit mode
– Data transfer rate from 10Kbps up to 400Kbps (Fast-mode)• Supports voltage thresholds compatible to:– SMBus 3.0 and below– PMBus 1.3 and below• One 16-byte receive FIFO and one 16-byte transmit FIFO
• Supports two ePIE interrupts– I2Cx interrupt – Any of the below conditions can be configured to generate an I2Cx interrupt:• Transmit Ready• Receive Ready• Register-Access Ready• No-Acknowledgment• Arbitration-Lost• Stop Condition Detected• Addressed-as-Target– I2Cx_FIFO interrupts:• Transmit FIFO interrupt• Receive FIFO interrupt• Module enable and disable capability• Free data format mode
Figure 6-65 shows how the I2C peripheral module interfaces within the device.

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I2C module
I2CXSRI2CDXR

TX FIFOFIFO Interrupt
to CPU/PIE

SDA
RX FIFO

Peripheral bus
I2CRSRSCL

Clocksynchronizer

I2CDRR
Control/status
registers

CPU

Prescaler

Noise filters

Interrupt to
CPU/PIE

I2C INT
Arbitrator

Figure 6-65. I2C Peripheral Module Interfaces

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6.17.2.1 I2C Electrical Data and Timing

Note
To meet all of the I2C protocol timing specifications, the I2C module clock must be configured in therange from 7 MHz to 12 MHz.
A pullup resistor must be chosen to meet the I2C standard timings. In most circumstances, 2.2 kΩ oftotal bus resistance to VDDIO is sufficient. For evaluating pullup resistor values for a particular design,
see the I2C Bus Pullup Resistor Calculation Application Note.
6.17.2.1.1 I2C Timing Requirements
NO.

MIN

MAX

UNIT

7

12

MHz

Standard mode
T0

fmod

I2C module frequency

T1th(SDA-SCL)START

Hold time, START condition, SCL fall delay after
SDA fall

4.0

µs

T2

tsu(SCL-SDA)START

Setup time, Repeated START, SCL rise before SDA
fall delay

4.0

µs

T3

th(SCL-DAT)

Hold time, data after SCL fall

0

µs

T4

tsu(DAT-SCL)

Setup time, data before SCL rise

250

ns

T5

tr(SDA)

Rise time, SDA

1000

ns

T6

tr(SCL)

Rise time, SCL

1000

ns

T7

tf(SDA)

Fall time, SDA

300

ns

T8

tf(SCL)

Fall time, SCL

300

ns

T9

tsu(SCL-SDA)STOP

Setup time, STOP condition, SCL rise before SDA
rise delay

4.0

T10

tw(SP)

Pulse duration of spikes that will be suppressed byfilter0

T11

Cb

capacitance load on each bus line

T0

fmod

I2C module frequency

T1th(SDA-SCL)START

Hold time, START condition, SCL fall delay after
SDA fall

0.6

µs

T2

tsu(SCL-SDA)START

Setup time, Repeated START, SCL rise before SDA
fall delay

0.6

µs

T3

th(SCL-DAT)

Hold time, data after SCL fall

0

µs

T4

tsu(DAT-SCL)

Setup time, data before SCL rise

100

T5

tr(SDA)

Rise time, SDA

20

300

ns

T6

tr(SCL)

Rise time, SCL

20

300

ns

T7

tf(SDA)

Fall time, SDA

11.4

300

ns

T8

tf(SCL)

Fall time, SCL

11.4

300

ns

T9

tsu(SCL-SDA)STOP

Setup time, STOP condition, SCL rise before SDA
rise delay

0.6

T10

tw(SP)

Pulse duration of spikes that will be suppressed byfilter0

T11

Cb

capacitance load on each bus line

µs
50

ns

400

pF

12

MHz

Fast mode

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7

ns

µs
50

ns

400

pF

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6.17.2.1.2 I2C Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.

PARAMETERTEST CONDITIONS

MIN

MAX

UNIT

100

kHz

Standard mode
S1

fSCL

SCL clock frequency

0

S2

TSCL

SCL clock period

10

µs

S3

tw(SCLL)

Pulse duration, SCL clock low

4.7

µs

S4

tw(SCLH)

Pulse duration, SCL clock high

4.0

µs

S5

tBUF

Bus free time between STOP and START
conditions

4.7

µs

S6

tv(SCL-DAT)

Valid time, data after SCL fall

3.45

µs

S7

tv(SCL-ACK)

Valid time, Acknowledge after SCL fall

3.45

µs

S8

II

Input current on pins

–10

10

µA

0

400

kHz

0.1 Vbus < Vi < 0.9 Vbus

Fast mode
S1

fSCL

SCL clock frequency

S2

TSCL

SCL clock period

2.5

µs

S3

tw(SCLL)

Pulse duration, SCL clock low

1.3

µs

S4

tw(SCLH)

Pulse duration, SCL clock high

0.6

µs

S5

tBUF

Bus free time between STOP and START
conditions

1.3

µs

S6

tv(SCL-DAT)

Valid time, data after SCL fall

0.9

µs

S7

tv(SCL-ACK)

Valid time, Acknowledge after SCL fall

0.9

µs

S8

II

Input current on pins

10

µA

0.1 Vbus < Vi < 0.9 Vbus

–10

6.17.2.1.3 I2C Timing Diagram
STOP

START

SDA

ACK
T5

S6

T7

Contd...

S7

T10

S3

SCL

Contd...

S4
T6
Repeated
START

SDA

9th
clock

T8
S2
STOP

S5

ACK
T2
T9
T1

SCL
9th
clock

Figure 6-66. I2C Timing Diagram

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6.17.3 Power Management Bus (PMBus) Interface
The PMBus module has the following features:• Compliance with the SMI Forum PMBus Specification (Part I v1.0 and Part II v1.1)• Supports voltage thresholds compatible to:– PMBus 1.3and below– SMBus 3.0and below• Support for controller and target• Support for I2C mode
• Support for threespeeds:– Standard Mode: Up to 100 kHz– Fast Mode: 400 kHz– Fast Plus Mode: 1MHz
• Packet error checking• CONTROL and ALERT signals• Clock high and low time-outs• Four-byte transmit and receive buffers• One maskable interrupt, which can be generated by several conditions:– Receive data ready– Transmit buffer empty– Target address received– End of message– ALERT input asserted– Clock low time-out– Clock high time-out– Bus free
Note
Please see the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual todetermine which pins support Fast Plus Mode as well as full SMBUS3.0 and PMBUS1.3 specifications
PCLKCR20SYSCLKDiv

PMBCTRL

ALERTDMA
Bit clock

Other registers

CTL
GPIO MuxCPU
PMBTXBUF
SCL
Shift register

PMBRXBUF

SDA

PMBUSA_INT

PIE

PMBus Module

Figure 6-67. PMBus Block Diagram

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6.17.3.1 PMBus Electrical Data and Timing
6.17.3.1.1 PMBus Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSVILValid low-level input voltage

VIH

Valid high-level input voltage

VOL

Low-level output voltage

At Ipullup = 4 mA

IOL

Low-level output current

VOL ≤ 0.4 V

tSP

Pulse width of spikes that must be
suppressed by the input filter

Ii

Input leakage current on each pin

CiCapacitance on each pin

MIN

TYP

2.1

0.1 Vbus < Vi < 0.9 Vbus

MAX

UNIT

0.8

V

VDDIO

V

0.4

V

4

mA

0

50

ns

–10

10

µA

10

pF

MAX

UNIT

20

25

MHz

10

1000(3)kHz

101000(4)kHz

6.17.3.1.2 PMBus Fast Plus Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSPMBus Module Clock Frequency(2)Fmod

3.3V Nominal Bus Voltage

MIN

TYP

fSCL

SCL clock frequency

tBUF

Bus free time between STOP and
START conditions

0.5

µs

tHD;STASTART condition hold time -- SDA fall
to SCL fall delay

0.26

µs

tSU;STA

Repeated START setup time -- SCL
rise to SDA fall delay

0.26

µs

tSU;STOSTOP condition setup time -- SCL rise
to SDA rise delay

0.26

µs

5.0V Nominal Bus Voltage

Data hold time after SCL fall

300

ns

tHD;DAT

Data hold time after SCL fall
PMBCTRL_ZH_EN = 1 (1)0nstSU;DAT

Data setup time before SCL rise50

ns

tTimeout

Clock low time-out

25

tLOW

Low period of the SCL clock

0.5

tHIGH

High period of the SCL clock

0.26

tLOW;SEXT

Cumulative clock low extend time
(target device)tLOW;MEXT

35

ms
µs

50

µs

From START to STOP

25

ms

Cumulative clock low extend time(controller device)

Within each byte

10

ms

tr

Rise time of SDA and SCL

5% to 95%

20

120

ns

tf

Fall time of SDA and SCL

95% to 5%

20

120

ns

(1)
(2)
(3)
(4)

This bit must be set to enable 0ns hold time/SMBUS3.0 Compliance
If the max clock is used all below timings will be met with the default register configurations for the PMBUS
Due to max IO drive strength of 12mA, 1MHz SCL clock is only valid for bus capacitances up to 520pF
Due to max IO drive strength of 12mA, 1MHz SCL clock is only valid for bus capacitances up to 330pF

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6.17.3.1.3 PMBus Fast Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

f(SYSCLK)

MAX

UNIT

10

MHz

400

kHz

Fmod

PMBus Module Clock Frequency (2)fSCL

SCL clock frequency

10

tBUF

Bus free time between STOP and
START conditions

1.3

µs

tHD;STASTART condition hold time -- SDA fall
to SCL fall delay

0.6

µs

tSU;STA

Repeated START setup time -- SCL
rise to SDA fall delay

0.6

µs

tSU;STOSTOP condition setup time -- SCL rise
to SDA rise delay

0.6

µs

Data hold time after SCL fall

300

ns
ns

/ 32

tHD;DAT

Data hold time after SCL fall
PMBCTRL_INC_1[ZH+EN] = 1(1)0tSU;DAT

Data setup time before SCL rise

100

tTimeout

Clock low time-out

25

tLOW

Low period of the SCL clock

1.3

tHIGH

High period of the SCL clock

0.6

tLOW;SEXT

Cumulative clock low extend time
(target device)tLOW;MEXT

ns
35

ms
µs

50

µs

From START to STOP

25

ms

Cumulative clock low extend time(controller device)

Within each byte

10

ms

tr

Rise time of SDA and SCL

5% to 95%

20

300

ns

tf

Fall time of SDA and SCL

95% to 5%

20

300

ns

(1)
(2)

This bit must be set to enable 0ns hold time/SMBUS3.0 Compliance
If the max clock is used all below timings will be met with the default register configurations for the PMBUS

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6.17.3.1.4 PMBus Standard Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

f(SYSCLK)

MAX

UNIT

10

MHz

100

kHz

Fmod

PMBus Module Clock Frequency(2)fSCL

SCL clock frequency

10

tBUF

Bus free time between STOP and
START conditions

4.7

µs

tHD;STASTART condition hold time -- SDA fall
to SCL fall delay

4µs

tSU;STA

Repeated START setup time -- SCL
rise to SDA fall delay

4.7

µs

tSU;STOSTOP condition setup time -- SCL rise
to SDA rise delay

4

µs

300

ns
ns

/ 32

Data hold time after SCL falltHD;DAT

Data hold time after SCL fall
PMBCTRL_INC_1[ZH+EN] = 1 (1)0tSU;DAT

Data setup time before SCL rise

250

tTimeout

Clock low time-out

25

tLOW

Low period of the SCL clock

4.7

tHIGH

High period of the SCL clock

4tLOW;SEXT

Cumulative clock low extend time
(target device)tLOW;MEXT

Cumulative clock low extend time(controller device)

tr
tf

ns
35

ms
µs

50

µs

From START to STOP

25

ms

Within each byte

10

ms

Rise time of SDA and SCL

1000

ns

Fall time of SDA and SCL

300

ns

(1)
(2)

This bit must be set to enable 0ns hold time/SMBUS3.0 Compliance
If the max clock is used all below timings will be met with the default register configurations for the PMBUS

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

6.17.4 Serial Communications Interface (SCI)The SCI is a 2-wire asynchronous serial port, commonly known as a UART. The SCI module supports digitalcommunications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero(NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has
its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication,or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break
detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit
baud-select register.
Features of the SCI module include:• Two external pins:– SCITXD: SCI transmit-output pin– SCIRXD: SCI receive-input pin– Baud rate programmable to 64K different rates• Data-word format– 1 start bit– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit– 1 or 2 stop bits
• Four error-detection flags: parity, overrun, framing, and break detection• Two wake-up multiprocessor modes: idle-line and address bit• Half- or full-duplex operation• Double-buffered receive and transmit functions• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms withstatus flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (breakcondition occurred), and RX ERROR flag (monitoring four interrupt conditions)• Separate enable bits for transmitter and receiver interrupts (except BRKDT)• NRZ format• Auto baud-detect hardware logic• 16-level transmit and receive FIFO
Note
All registers in this module are 8-bit registers. When a register is accessed, the register data is in thelower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the upper byte has noeffect.
Figure 6-68 shows the SCI block diagram.

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TXSHF
Register

SCITXD8
TXENA
SCICTL1.1
Frame
Format and Mode
ParityEven/Odd

01

SCICCR.6
EnableTXEMPTY
SCICTL2.6

8
TX FIFO_0

SCICCR.5
88

TX FIFO_1

TX Interrupt
Logic

TX FIFO Interrupts

TXINT
To CPU

TX FIFO_N
TXINTENA
80

TXWAKESCICTL2.0

TXRDY
1

SCICTL2.7

SCICTL1.3
SCI TX Interrupt Select Logic
8

WUT

Transmit Data
Buffer Register
SCITXBUF.7-0

LSPCLK

Baud Rate
MSB/LSB
Registers

RXSHF
Register

SCIHBAUD.15-8
SCILBAUD.7-0

Auto Baud Detect Logic

SCIRXDRXWAKESCIRXST.1

SCICTL1.0
RXENA
8

0

1
8

SCIFFENA
RX FIFO_0

SCIFFTX.14
8

RX FIFO_1

RX FIFO Interrupts

RX Interrupt
Logic

RXINT
To CPURX FIFO_N
RXFFOVF
80

SCIFFRX.15
1

RXBKINTENASCICTL2.1

RXRDY
SCIRXST.6
RXENA

BRKDT

SCICTL1.0

RXERRINTENASCIRXST.5

8

SCICTL1.6

SCI RX Interrupt Select Logic

SCIRXST.5-2
Receive Data
Buffer Register
SCIRXBUF.7-0

BRKDT

FE OE PE
RXERRORSCIRXST.7

Figure 6-68. SCI Block Diagram

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

6.17.5 Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a high-speed synchronous serial input and output (I/O) port that allows aserial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bittransfer rate. The SPI is normally used for communications between the MCU controller and external peripherals
or another controller. Typical applications include external I/O or peripheral expansion through devices suchas shift registers, display drivers, and analog-to-digital converters (ADCs). Multidevice communications aresupported by the controller or peripheral operation of the SPI. The port supports a 16-level, receive and transmit
FIFO for reducing CPU servicing overhead.
The SPI module features include:• SPIPOCI: SPI peripheral-output/controller-input pin• SPIPICO: SPI peripheral-input/controller-output pin• SPIPTE: SPI peripheral transmit-enable pin• SPICLK: SPI serial-clock pin• Two operational modes: Controller and Peripheral• Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited by the
maximum speed of the I/O buffers used on the SPI pins.
• Data word length: 1 to 16 data bits
• Four clocking schemes (controlled by clock polarity and clock phase bits) include:– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the fallingedge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the risingedge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
• Simultaneous receive and transmit operation (transmit function can be disabled in software)• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithm• 16-level transmit/receive FIFO• DMA support• High-speed mode
• Delayed transmit control• 3-wire SPI mode
• SPIPTE inversion for digital audio interface receive mode on devices with two SPI modules
Figure 6-69 shows the SPI CPU interfaces.

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PCLKCR8LSPCLK

Low-Speed
Prescaler

SYSCLKCPU

Bit Clock
Peripheral BusSYSRSSPIPICOSPIPOCISPIGPIO MUXSPICLKSPIINTSPITXINT

PIE

SPIPTESPIRXDMASPITXDMA

DMA

Figure 6-69. SPI CPU Interface

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6.17.5.1 SPI Controller Mode Timings

The following section contains the SPI Controller Mode Timings.
Note
All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on SPICLK,SPIPICO, and SPIPOCI.
6.17.5.1.1 SPI Controller Mode Timing Requirements
PARAMETER (2)NO.

(BRR + 1)(1)

MIN

MAX

UNIT

High-Speed Mode8tsu(POCI)M

Setup time, SPIPOCI valid before SPICLK

Even, Odd

0.7

ns

8

tsu(POCI)M

Setup time, SPIPOCI valid before
SPICLK(when used on pin muxed with
PMBUS - GPIO2, 3, 9, or 32)

Even, Odd

1.5

ns

8

tsu(POCI)M

Setup time, SPIPOCI valid before
SPICLK(when used on pin muxed with USB- GPIO23, or 41)

Even, Odd

1.5

ns

9

th(POCI)M

Hold time, SPIPOCI valid after SPICLK

Even, Odd

6.5

ns

Normal Mode8tsu(POCI)M

Setup time, SPIPOCI valid before SPICLK

Even, Odd

15

ns

8

tsu(POCI)M

Setup time, SPIPOCI valid before
SPICLK(when used on pin muxed with
PMBUS - GPIO2, 3, 9, or 32)

Even, Odd

16.5

ns

9

th(POCI)M

Hold time, SPIPOCI valid after SPICLK

Even, Odd

0

ns

(1)
(2)

The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR isgreater than 3.
GPIOs 2, 3, 9, 23, 32, or 41 do not support full High-Speed Mode(37.5MHz) SPI operation

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6.17.5.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0
over recommended operating conditions (unless otherwise noted)
PARAMETER (1) (2) (4)NO.

(BRR + 1)(3)

MIN

MAX

UNIT

Even

4tc(LSPCLK)

128tc(LSPCLK)

Odd

5tc(LSPCLK)

127tc(LSPCLK)

Even

0.5tc(SPC)M – 1

0.5tc(SPC)M + 1

Odd

0.5tc(SPC)M + 0.5tc(LSPCLK) – 1

0.5tc(SPC)M +0.5tc(LSPCLK) + 1

Even

0.5tc(SPC)M – 1

0.5tc(SPC)M + 1

Odd

0.5tc(SPC)M – 0.5tc(LSPCLK) – 1

0.5tc(SPC)M –0.5tc(LSPCLK) + 1

Even

1.5tc(SPC)M – 3tc(SYSCLK) – 3

1.5tc(SPC)M –3tc(SYSCLK) + 3

Odd

1.5tc(SPC)M – 4tc(SYSCLK) – 3

1.5tc(SPC)M –4tc(SYSCLK) + 3

Even
Delay time, SPIPTE active to
SPICLK(when used on pin muxed with
PMBUS - GPIO2, 3, 9, or 32)
Odd

1.5tc(SPC)M – 3tc(SYSCLK) – 4

1.5tc(SPC)M –3tc(SYSCLK) + 3

1.5tc(SPC)M – 4tc(SYSCLK) – 4

1.5tc(SPC)M –4tc(SYSCLK) + 3

Even

1.5tc(SPC)M – 3tc(SYSCLK) – 3

1.5tc(SPC)M –3tc(SYSCLK) +
5.5

Odd

1.5tc(SPC)M – 4tc(SYSCLK) – 3

1.5tc(SPC)M –4tc(SYSCLK) +
5.5

Even

0.5tc(SPC)M – 3

0.5tc(SPC)M + 3

Odd

0.5tc(SPC)M – 0.5tc(LSPCLK) – 3

0.5tc(SPC)M –0.5tc(LSPCLK) + 3

Even

0.5tc(SPC)M – 4

0.5tc(SPC)M + 3

Odd

0.5tc(SPC)M – 0.5tc(LSPCLK) – 4

0.5tc(SPC)M –0.5tc(LSPCLK) + 3

Even

0.5tc(SPC)M – 3

0.5tc(SPC)M +5.5

0.5tc(SPC)M – 0.5tc(LSPCLK) – 3

0.5tc(SPC)M –0.5tc(LSPCLK) +
5.5

ns

Odd

General1

tc(SPC)M

Cycle time, SPICLK

2

tw(SPC1)M

Pulse duration, SPICLK, first pulse3tw(SPC2)M

Pulse duration, SPICLK, second pulse

23

23

23

td(SPC)M

td(SPC)M

td(SPC)M

Delay time, SPIPTE active to SPICLK

Delay time, SPIPTE active to
SPICLK(when used on pin muxed with
USB - GPIO23 or GPIO41)

24

tv(STE)M

Valid time, SPICLK to SPIPTE inactive

24

tv(STE)M

Valid time, SPICLK to SPIPTE
inactive(when used on pin muxed with
PMBUS - GPIO2, 3, 9, or 32)

tv(STE)M

Valid time, SPICLK to SPIPTE
inactive(when used on pin muxed with
USB - GPIO23 or GPIO41)

24

ns

ns

ns

ns

ns

ns

ns

ns

High-Speed Mode4td(PICO)M

Delay time, SPICLK to SPIPICO valid

Even, Odd

1

ns

4

td(PICO)M

Delay time, SPICLK to SPIPICO
valid(when used on pin muxed with
PMBUS - GPIO2, 3, 9, or 32)

Even, Odd

2

ns

5

tv(PICO)M

Valid time, SPIPICO valid after SPICLK

5

tv(PICO)M

Even

0.5tc(SPC)M – 3

Odd

0.5tc(SPC)M – 0.5tc(LSPCLK) – 3

Valid time, SPIPICO valid after
Even
SPICLK(when used on pin muxed withOdd
PMBUS - GPIO2, 3, 9, or 32)

0.5tc(SPC)M – 4.5nsns

0.5tc(SPC)M – 0.5tc(LSPCLK) – 4.5

Normal Mode4td(PICO)M

Delay time, SPICLK to SPIPICO valid

5

tv(PICO)M

Valid time, SPIPICO valid after SPICLK

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Even, Odd2

Even

0.5tc(SPC)M – 3

Odd

0.5tc(SPC)M – 0.5tc(LSPCLK) – 3

nsns

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

6.17.5.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0 (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER (1) (2) (4)

NO.
5
(1)
(2)
(3)
(4)

tv(PICO)M(BRR + 1)(3)

Valid time, SPIPICO valid after
Even
SPICLK(when used on pin muxed withOdd
PMBUS - GPIO2, 3, 9, or 32)

MIN

MAX

UNIT

0.5tc(SPC)M – 4.5
0.5tc(SPC)M – 0.5tc(LSPCLK) – 4.5

ns

10-pF load on pin for High-Speed Mode.
20-pF load on pin for Normal Mode.
The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR isgreater than 3.
GPIOs 2, 3, 9, 23, 32, or 41 do not support full High-Speed Mode(37.5MHz) SPI operation

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6.17.5.1.3 SPI Controller Mode Switching Characteristics - Clock Phase 1
over recommended operating conditions (unless otherwise noted)
PARAMETER(1) (2) (4)NO.

(BRR + 1) (3)

MIN

MAX

Even

4tc(LSPCLK)

128tc(LSPCLK)

Odd

5tc(LSPCLK)

127tc(LSPCLK)

Even

0.5tc(SPC)M – 1

0.5tc(SPC)M + 1

Odd

0.5tc(SPC)M – 0.5tc(LSPCLK) – 1

0.5tc(SPC)M –0.5tc(LSPCLK) + 1

Even

0.5tc(SPC)M – 1

0.5tc(SPC)M + 1

Odd

0.5tc(SPC)M + 0.5tc(LSPCLK) – 1

0.5tc(SPC)M +0.5tc(LSPCLK) + 1

UNIT

General1

tc(SPC)M

Cycle time, SPICLKns

2

tw(SPCH)M

Pulse duration, SPICLK, first pulse3tw(SPC2)M

Pulse duration, SPICLK, second pulse

23

td(SPC)M

Delay time, SPIPTE valid to SPICLK

Even, Odd

2tc(SPC)M – 3tc(SYSCLK) – 3

2tc(SPC)M –3tc(SYSCLK) + 3

ns23

td(SPC)M

Delay time, SPIPTE valid to
SPICLK(when used on pin muxed with Even, Odd
PMBUS - GPIO2, 3, 9, or 32)

2tc(SPC)M – 3tc(SYSCLK) – 4

2tc(SPC)M –3tc(SYSCLK) + 3

ns23

td(SPC)M

Delay time, SPIPTE valid to
SPICLK(when used on pin muxed with Even, Odd
USB - GPIO23 or GPIO41)

2tc(SPC)M – 3tc(SYSCLK) – 3

2tc(SPC)M –3tc(SYSCLK) +
5.5

ns

24

td(STE)M

Delay time, SPICLK to SPIPTE invalid

Even

–3

3

Odd

–3

3

-4

3

td(STE)M

Delay time, SPICLK to SPIPTE
invalid(when used on pin muxed with
PMBUS - GPIO2, 3, 9, or 32)

Even

24

Odd

-4

3

–3

5.5

td(STE)M

Delay time, SPICLK to SPIPTE
invalid(when used on pin muxed with
USB - GPIO23 or GPIO41)

Even

24

Odd

–3

5.5

Even

0.5tc(SPC)M – 2

ns

ns

ns

ns

ns

High-Speed Mode4td(PICO)M

Delay time, SPIPICO valid to SPICLK

Odd

0.5tc(SPC)M + 0.5tc(LSPCLK) – 2

4td(PICO)M

Delay time, SPIPICO valid to SPICLK Even
(when used on pin muxed with PMBUS
Odd- GPIO2, 3, 9, or 32)

0.5tc(SPC)M – 3
0.5tc(SPC)M + 0.5tc(LSPCLK) – 3

5

tv(PICO)M

Valid time, SPIPICO valid after SPICLK

Even

0.5tc(SPC)M – 3

Odd

0.5tc(SPC)M – 0.5tc(LSPCLK) – 3

5

tv(PICO)M

Valid time, SPIPICO valid after SPICLK Even
(when used on pin muxed with PMBUS
Odd- GPIO2, 3, 9, or 32)

0.5tc(SPC)M – 4.5
0.5tc(SPC)M – 0.5tc(LSPCLK) – 4.5

Even

0.5tc(SPC)M – 2

Odd

0.5tc(SPC)M + 0.5tc(LSPCLK) – 2

Even

0.5tc(SPC)M – 3

ns

ns

ns

ns

Normal Mode4td(PICO)M

Delay time, SPIPICO valid to SPICLK

5

tv(PICO)M

Valid time, SPIPICO valid after SPICLK

Odd

0.5tc(SPC)M – 0.5tc(LSPCLK) – 3

5

tv(PICO)M

Valid time, SPIPICO valid after SPICLK Even
(when used on pin muxed with PMBUS
Odd- GPIO2, 3, 9, or 32)

0.5tc(SPC)M – 4.5

(1)
(2)
(3)

0.5tc(SPC)M – 0.5tc(LSPCLK) – 4.5

ns
ns

ns

(4)

10-pF load on pin for High-Speed Mode.
20-pF load on pin for Normal Mode.
The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR isgreater than 3.
GPIOs 2, 3, 9, 23, 32, or 41 do not support full High-Speed Mode(37.5MHz) SPI operation

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6.17.5.1.4 SPI Controller Mode Timing Diagrams

1

SPICLK(clock polarity = 0)2
3

SPICLK(clock polarity = 1)
4
5
Controller out data
is valid

SPIPICO

8
9Controller out
data must be valid

SPIPOCI

24

23

SPIPTEA.

On the trailing end of the word, SPIPTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO
modes.

Figure 6-70. SPI Controller Mode External Timing (Clock Phase = 0)
1

SPICLK(clock polarity = 0)2
3

SPICLK(clock polarity = 1)
4
5
Controller out data
is valid

SPIPICO

8
9Controller out
data must be valid

SPIPOCI

24

23

SPIPTEA.

On the trailing end of the word, SPIPTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO
modes.

Figure 6-71. SPI Controller Mode External Timing (Clock Phase = 1)
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6.17.5.2 SPI Peripheral Mode Timings

The following section contains the SPI Peripheral Mode Timings.
6.17.5.2.1 SPI Peripheral Mode Timing Requirements
NO.

MIN

MAX

UNIT

12

tc(SPC)SCycle time, SPICLK

4tc(SYSCLK)

ns

13

tw(SPC1)S

Pulse duration, SPICLK, first pulse

2tc(SYSCLK) – 1ns

14tw(SPC2)S

Pulse duration, SPICLK, second pulse

2tc(SYSCLK) – 1

ns19

tsu(PICO)S

Setup time, SPIPICO valid before SPICLK

1.5tc(SYSCLK)ns

20th(PICO)S

Hold time, SPIPICO valid after SPICLK

1.5tc(SYSCLK)

ns

Setup time, SPIPTE valid before SPICLK(Clock Phase = 0)

2tc(SYSCLK) + 15

ns

Setup time, SPIPTE valid before SPICLK(Clock Phase = 1)

2tc(SYSCLK) + 15

ns

Hold time, SPIPTE invalid after SPICLK

1.5tc(SYSCLK)

ns

25

26

tsu(STE)Sth(STE)S

6.17.5.2.2 SPI Peripheral Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER(1)

NO.
15

15

16

td(POCI)S

td(POCI)Stv(POCI)S

MAX

UNIT

Delay time, SPICLK to SPIPOCI valid(non-high speed mode)

17

ns

Delay time, SPICLK to SPIPOCI valid(high-speed mode)

12.5

ns

Delay time, SPICLK to SPIPOCI valid(high-speed mode)(when used on pins
muxed with PMBUS - GPIO2, 3, 9, or 32)

14

ns

Delay time, SPICLK to SPIPOCI valid(high-speed mode)(when used on pins
muxed with USB - GPIO23 or 41)

16.7

ns

Valid time, SPIPOCI valid after SPICLK(1)

20-pF load on pin.

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0

ns

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6.17.5.2.3 SPI Peripheral Mode Timing Diagrams

12

SPICLK(clock polarity = 0)13
14

SPICLK(clock polarity = 1)
15

16
SPIPOCI data is valid

SPIPOCI
19

20
SPIPICO data
must be valid

SPIPICO25

26

SPIPTE
Figure 6-72. SPI Peripheral Mode External Timing (Clock Phase = 0)
12

SPICLK(clock polarity = 0)13

14

SPICLK(clock polarity = 1)
15

SPIPOCI

Data valid

SPIPOCI data is valid

Data valid

16

19
20
SPIPICO data
must be valid

SPIPICO25

26

SPIPTE
Figure 6-73. SPI Peripheral Mode External Timing (Clock Phase = 1)

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6.17.6 Local Interconnect Network (LIN)
This device contains one Local Interconnect Network (LIN) module. The LIN module adheres to the LIN 2.1
standard as defined by the LIN Specification Package Revision 2.1. The LIN is a low-cost serial interface
designed for applications where the CAN protocol may be too expensive to implement, such as small
subnetworks for cabin comfort functions like interior lighting or window control in an automotive application.
The LIN standard is based on the SCI (UART) serial data link format. The communication concept is singlecommander and multiple-responder with a message identification for multicast transmission between any
network nodes.
The LIN module can be programmed to work either as an SCI or as a LIN as the core of the module is an SCI.
The hardware features of the SCI are augmented to achieve LIN compatibility. The SCI module is a universal
asynchronous receiver-transmitter (UART) that implements the standard non-return-to-zero format.
Though the registers are common for LIN and SCI, the register descriptions have notes to identify the register/bit
usage in different modes. Because of this, code written for this module cannot be directly ported to the standalone SCI module and vice versa.
The LIN module has the following features:• Compatibility with LIN 1.3, 2.0 and 2.1 protocols• Configurable baud rate up to 20 kbps (as per LIN 2.1 protocol)• Two external pins: LINRX and LINTX• Multibuffered receive and transmit units• Identification masks for message filtering• Automatic commander header generation– Programmable synchronization break field– Synchronization field– Identifier field• Responder automatic synchronization– Synchronization break detection– Optional baud rate update– Synchronization validation• 231 programmable transmission rates with 7 fractional bits
• Wakeup on LINRX dominant level from transceiver• Automatic wake-up support– Wakeup signal generation– Expiration times on wakeup signals• Automatic bus idle detection• Error detection– Bit error– Bus error– No-response error– Checksum error– Synchronization field error– Parity error• Capability to use direct memory access (DMA) for transmit and receive data
• Two interrupt lines with priority encoding for:– Receive– Transmit– ID, error, and status• Support for LIN 2.0 checksum• Enhanced synchronizer finite state machine (FSM) support for frame processing• Enhanced handling of extended frames• Enhanced baud rate generator

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Update wakeup/go to sleep
READ DATA BUS
WRITE DATA BUS
ADDRESS BUS

CHECKSUMCALCULATORINTERFACE

ID PARTYCHECKERBITMONITORTXRX ERRORDETECTOR (TED)

TIME-OUTCONTROL

COUNTERLINRX/SCIRXCOMPARELINTX/
SCITX

FSM

MASK
FILTERSYNCHRONIZER

8 RECEIVEBUFFERSDMA
CONTROL

8 TRANSMITBUFFERS

Figure 6-74. LIN Block Diagram

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6.17.7 Fast Serial Interface (FSI)The Fast Serial Interface (FSI) module is a serial communication peripheral capable of reliable and robust
high-speed communications. The FSI is designed to ensure data robustness across many system conditions
such as chip-to-chip as well as board-to-board across an isolation barrier. Payload integrity checks such as
CRC, start- and end-of-frame patterns, and user-defined tags, are encoded before transmit and then verified
after receipt without additional CPU interaction. Line breaks can be detected using periodic transmissions, allmanaged and monitored by hardware. The FSI is also tightly integrated with other control peripherals on thedevice. To ensure that the latest sensor data or control parameters are available, frames can be transmitted on
every control loop period. An integrated skew-compensation block has been added on the receiver to handle
skew that may occur between the clock and data signals due to a variety of factors, including trace-length
mismatch and skews induced by an isolation chip. With embedded data robustness checks, data-link integrity
checks, skew compensation, and integration with control peripherals, the FSI can enable high-speed, robust
communication in any system. These and many other features of the FSI follow.
The FSI module includes the following features:• Independent transmitter and receiver cores• Source-synchronous transmission• Dual data rate (DDR)• One or two data lines• Programmable data length• Skew adjustment block to compensate for board and system delay mismatches• Frame error detection• Programmable frame tagging for message filtering• Hardware ping to detect line breaks during communication (ping watchdog)• Two interrupts per FSI core
• Externally triggered frame generation• Hardware- or software-calculated CRC• Embedded ECC computation module• Register write protection• DMA support• SPI compatibility mode (limited features available)
Operating the FSI at maximum speed (60 MHz) at dual data rate (120Mbps) may require the integrated skew
compensation block to be configured according to the specific operating conditions on a case-by-case basis. The
Fast Serial Interface (FSI) Skew Compensation Application Note provides example software on how to configureand set up the integrated skew compensation block on the Fast Serial Interface.
The FSI consists of independent transmitter (FSITX) and receiver (FSIRX) cores. The FSITX and FSIRX cores
are configured and operated independently. The features available on the FSITX and FSIRX are described in
the FSI Transmitter section and the FSI Receiver section of the TMS320F28P55x Real-Time Microcontrollers
Technical Reference Manual, respectively.

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6.17.7.1 FSI Transmitter

The FSI transmitter module handles the framing of data, CRC generation, signal generation of TXCLK, TXD0,
and TXD1, as well as interrupt generation. The operation of the transmitter core is controlled and configured
through programmable control registers. The transmitter control registers let the CPU (or the CLA) program,
control, and monitor the operation of the FSI transmitter. The transmit data buffer is accessible by the CPU, CLA,
and the DMA.
The transmitter has the following features:• Automated ping frame generation• Externally triggered ping frames• Externally triggered data frames• Software-configurable frame lengths• 16-word data buffer• Data buffer underrun and overrun detection• Hardware-generated CRC on data bits
• Software ECC calculation on select data
• DMA support• CLA task triggering
Figure 6-75 shows the FSITX CPU interface. Figure 6-76 shows the high-level block diagram of the FSITX. Not
all data paths and internal connections are shown. This diagram provides a high-level overview of the internal
modules present in the FSITX.
PLLRAWCLKPCLKCR18
SYSCLKSYSRSN

C28x

ePIE

FSITXyINT1
FSITXyINT2

FSITXyCLKFSITXFSITXyD0
FSITXyD1

FSITXyDMAA.

Trigger Muxes(A)32GPIO MUXDMARegisters

Register Interface

CLA

The signals connected to the trigger muxes are described in the External Frame Trigger Mux section of the Fast Serial Interface (FSI)
chapter in the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual.

Figure 6-75. FSITX CPU Interface

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PLLRAWCLKFSITXSYSRSNSYSCLK
Transmit Clock
Generator

TXCLKIN

Register Interface

FSI Mode:
TXCLK = TXCLKIN/2
SPI Signaling Mode:TXCLK = TXCLKIN

Core ResetFSITXINT1FSITXINT2

Control Registers,
Interrupt Management

TXCLK
Ping Time-out Counter

FSITX_DMA_EVTTransmitter Core
External Frame Triggers

TXD0

TXD1

Transmit Data
Buffer
ECC Logic

Figure 6-76. FSITX Block Diagram
6.17.7.1.1 FSITX Electrical Data and Timing
6.17.7.1.1.1 FSITX Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER(1)

NO.
1

MIN

MAX

UNIT

tc(TXCLK)

Cycle time, TXCLK

16.67

ns

1

tc(TXCLK)

Cycle time, TXCLK(when any FSI signal isused on pins muxed with PMBUS - GPIO2, 3,
9, or 32)

26.67

ns

2

tw(TXCLK)

Pulse width, TXCLK low or TXCLK high(0.5tc(TXCLK)) – 1(0.5tc(TXCLK)) + 1

ns3

td(TXCLK–TXD)

Delay time, TXCLK rising or falling toTXD
valid(0.25tc(TXCLK)) – 2(0.25tc(TXCLK)) + 2

ns3

td(TXCLK–TXD)

Delay time, TXCLK rising or falling toTXD
valid(when used on pin muxed with PMBUS GPIO2, 3, 9, or 32)(0.25tc(TXCLK)) – 2(0.25tc(TXCLK)) + 2.5

ns4

td(TXCLK)TXCLK delay compensation at
TX_DLYLINE_CTRL[TXCLK_DLY]=31

9.4

30

ns

5

td(TXD0)

TXD0 delay compensation at
TX_DLYLINE_CTRL[TXD0_DLY]=31

9.4

30

ns

6

td(TXD1)

TXD1 delay compensation at
TX_DLYLINE_CTRL[TXD1_DLY]=31

9.4

30

ns

7

td(DELAY_ELEMENT)

Incremental delay of each delay line element
for TXCLK, TXD0, and TXD1

0.29

1

ns

(1)

10-pF load on pin.

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6.17.7.1.1.2 FSITX Timings
1
2

FSITXCLKFSITXD0

FSITXD1
3

Figure 6-77. FSITX Timings

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6.17.7.2 FSI Receiver

The receiver module interfaces to the FSI clock (RXCLK), and data lines (RXD0 and RXD1) after they passthrough an optional programmable delay line. The receiver core handles the data framing, CRC computation,and frame-related error checking. The receiver bit clock and state machine are run by the RXCLK input, which isasynchronous to the device system clock.
The receiver control registers let the CPU program (or the CLA), control, and monitor the operation of the FSIRX.
The receive data buffer is accessible by the CPU, CLA, and the DMA.
The receiver core has the following features:• 16-word data buffer• Multiple supported frame types• Ping frame watchdog• Frame watchdog• CRC calculation and comparison in hardware• ECC detection• Programmable delay line control on incoming signals• DMA support• SPI compatibility mode
• CLA task triggering
Figure 6-78 shows the FSIRX CPU interface. Figure 6-79 provides a high-level overview of the internal modules
present in the FSIRX. Not all data paths and internal connections are shown.
PCLKCR18
SYSCLKSYSRSN

C28x

ePIE

FSIRXyINT1
FSIRXyINT2

FSIRXyCLKFSIRXFSIRXyD0
FSIRXyD1

GPIO MUXRegisters

DMA

Register Interface

CLA

FSIRXyDMA

Figure 6-78. FSIRX CPU Interface

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024FSIRX
SYSRSnSYSCLK
Frame Watchdog
Register Interface
Core Reset
FSIRXINT1
FSIRXINT2

Control Registers,
Interrupt Management

RXCLK

Ping Watchdog

FSIRX_DMA_EVT

Receiver Core

Skew
Control

RXD0
RXD1

Receive Data
Buffer
ECC Check
Logic

Figure 6-79. FSIRX Block Diagram
6.17.7.2.1 FSIRX Electrical Data and Timing
6.17.7.2.1.1 FSIRX Timing Requirements
NO.
1

MIN

MAX

UNIT

tc(RXCLK)

Cycle time, RXCLK

16.67

ns

1

tc(RXCLK)

Cycle time, RXCLK(when any FSI signal isused on pins muxed with PMBUS - GPIO2, 3,
9, or 32)

26.67

ns

2

tw(RXCLK)

Pulse width, RXCLK low or RXCLK high.

0.65tc(RXCLK)

ns

3

tsu(RXCLK–RXD)

Setup time with respect to RXCLK, applies toboth edges of the clock

1.7

ns

3

tsu(RXCLK–RXD)

Setup time with respect to RXCLK, applies
to both edges of the clock(when used on pin
muxed with PMBUS - GPIO2, 3, 9, or 32)

2.6

ns

4

th(RXCLK–RXD)

Hold time with respect to RXCLK, applies toboth edges of the clock2

ns

0.35tc(RXCLK)

6.17.7.2.1.2 FSIRX Switching Characteristics
PARAMETER(1)

NO.

MIN

MAX

UNIT

1

td(RXCLK)RXCLK delay compensation at
RX_DLYLINE_CTRL[RXCLK_DLY]=31

9.7

30

ns

2

td(RXD0)

RXD0 delay compensation at
RX_DLYLINE_CTRL[RXD0_DLY]=31

9.7

30

ns

3

td(RXD1)

RXD1 delay compensation
at RX_DLYLINE_CTRL[RXD1_DLY]=31

9.7

30

ns

4

td(DELAY_ELEMENT)

Incremental delay of each delay line elementfor RXCLK, RXD0, and RXD1

0.29

1

ns

TDM1

tskew(TDM_CLK-TDM_Dx )Delay skew introduced between RXCLKTDM_CLK delay and RXDx-TDM_Dx delays

-3

3

ns

TDM1

td(RXCLK-TDM_CLK )Delay time, RXCLK input to TDM_CLK output

2

14.5

ns

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6.17.7.2.1.2 FSIRX Switching Characteristics (continued)
PARAMETER(1)

NO.

MIN

MAX

UNIT

TDM2

td(RXD0-TXD0)

Delay time, RXD0 input to TXD0 output

2

14.5

ns

TDM3

td(RXD1-TXD1)

Delay time, RXD1 input to TXD1 output

2

14.5

ns

(1)

10-pF load on pin.

6.17.7.2.1.3 FSIRX Timings
1

FSIRXCLK

2FSIRXD0

FSIRXD1
3
4

Figure 6-80. FSIRX Timings

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6.17.7.3 FSI SPI Compatibility Mode

The FSI supports a SPI compatibility mode to enable communication with programmable SPI devices. In thismode, the FSI transmits its data in the same manner as a SPI in a single clock configuration mode. While the
FSI is able to physically interface with a SPI in this mode, the external device must be able to encode anddecode an FSI frame to communicate successfully. This is because the FSI transmits all SPI frame phases withthe exception of the preamble and postamble. The FSI provides the same data validation and frame checking
as if it was in standard FSI mode, allowing for more robust communication without consuming CPU cycles. The
external SPI is required to send all relevant information and can access standard FSI features such as the pingframe watchdog on the FSIRX, frame tagging, or custom CRC values. The list of features of SPI compatibility
mode follows:• Data will transmit on rising edge and receive on falling edge of the clock.
• Only 16-bit word size is supported.
• TXD1 will be driven like an active-low chip-select signal. The signal will be low for the duration of the full
frame transmission.
• No receiver chip-select input is required. RXD1 is not used. Data is shifted into the receiver on every active
clock edge.
• No preamble or postamble clocks will be transmitted. All signals return to the idle state after the frame phaseis finished.
• It is not possible to transmit in the SPI peripheral configuration because the FSI TXCLK cannot take anexternal clock source.
6.17.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing

Special timings are not required for the FSIRX in SPI signaling mode. FSIRX timings listed in the FSIRX Timing
Requirements table are applicable in SPI compatibility mode. Setup and Hold times are only valid on the fallingedge of FSIRXCLK because this is the active edge in SPI signaling mode.
6.17.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER(1)

NO.

MAX

UNIT

1

tc(TXCLK)

Cycle time, TXCLK

16.67

ns

1

tc(TXCLK)

Cycle time, TXCLK(when any FSI signal isused on pins muxed with PMBUS - GPIO2, 3,
9, or 32)

26.67

ns

2

tw(TXCLK)

Pulse width, TXCLK low or TXCLK high(0.5tc(TXCLK)) + 1

ns3

td(TXCLKH–TXD0)

Delay time, TXD0 valid after TXCLK high

3

ns

4

td(TXD1-TXCLK)Delay time, TXCLK high after TXD1 low

tw(TXCLK) – 3ns5td(TXCLK-TXD1)

Delay time, TXD1 high after TXCLK low

tw(TXCLK)

ns

(1)

MIN

(0.5tc(TXCLK)) – 1

10-pF load on pin

6.17.7.3.1.2 FSITX SPI Signaling Mode Timings
1
2
FSITXCLK
3
FSITXD0
5

4
FSITXD1

Figure 6-81. FSITX SPI Signaling Mode Timings

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6.17.8 Universal Serial Bus (USB)The USB controller operates as a full-speed or low-speed function controller during point-to-point
communications with USB host or device functions.
The USB module has the following features:• USB 2.0 full-speed and low-speed operation• Integrated PHY• Three transfer types: control, interrupt, and bulk
• 32 endpoints– One dedicated control IN endpoint and one dedicated control OUT endpoint– 15 configurable IN endpoints and 15 configurable OUT endpoints• 4KB of dedicated endpoint memory
Figure 6-82 shows the USB block diagram.
Endpoint Control
Transmit
EP0 –31
Control
Receive
CPU Interface
CombineEndpoints

Interrupt
Control

Host
Transaction
SchedulerInterrupts

EP Reg.
Decoder
UTM
Synchronization

PacketEncode/Decode

Data Sync

Packet Encode

HNP/SRP

Packet Decode

Tx
Buff

TimersCRC Gen/Check

Cycle Control

USB FS/LSPHY

FIFO RAM
Controller
Rx
Rx
Buff
Buff

CPU Bus

CommonRegs
Cycle
Control

Tx
Buff
FIFO
Decoder

USB DataLines
D+ andD-

Figure 6-82. USB Block Diagram
Note
The accuracy of the on-chip zero-pin oscillator (see the INTOSC Characteristics section) will notmeet the accuracy requirements of the USB protocol. An external clock source must be used for
applications using USB. For applications using the USB boot mode, see the Boot ROM and Peripheral
Booting section for clock frequency requirements.
6.17.8.1 USB Electrical Data and Timing
6.17.8.1.1 USB Input Ports DP and DM Timing Requirements
MIN

MAX

V(CM)

Differential input common mode range

0.8

2.5

Z(IN)

Input impedance

300

VCRS

Crossover voltage

1.3

VIL

Static SE input logic-low level

0.8

VIH

Static SE input logic-high level

2.0

V

VDI

Differential input voltage

0.2

V

210

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UNIT
V
kΩ

2.0

V
V

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6.17.8.1.2 USB Output Ports DP and DM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
MIN

MAX

UNIT

VOH

D+, D– single-ended

PARAMETER

USB 2.0 load conditions

TEST CONDITIONS

2.8

3.6

V

VOL

D+, D– single-ended

USB 2.0 load conditions

0

0.3

V

Z(DRV)

D+, D– impedance

28

44

Ω

tr

Rise time

Full speed, differential, CL = 50 pF, 10%/90%,
Rpu on D+

4

20

ns

tf

Fall time

Full speed, differential, CL = 50 pF, 10%/90%,
Rpu on D+

4

20

ns

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7 Detailed Description
7.1 Overview
The TMS320F28P55x (F28P55x) is a member of the C2000™ real-time microcontroller family of scalable,
ultra-low latency devices designed for efficiency in power electronics, including but not limited to: high power
density, high switching frequencies, and supporting the use of GaN and SiC technologies.
These include such applications as:
•
•

•

•
•
•

Industrial motor drives
Motor control– Traction inverter motor control– HVAC motor control– Mobile robot motor control
Solar inverters– Central inverter– Micro inverter– String inverter
Digital power
Electrical vehicles and transportation
EV charging infrastructure

The real-time control subsystem is based on TI’s 32-bit C28x DSP core, which provides 150 MIPS of signalprocessing performance in each core for floating- or fixed-point code running from either on-chip flash or SRAM.
The C28x CPU is further boosted by the Trigonometric Math Unit (TMU) and VCRC (Cyclical Redundancy
Check) extended instruction sets, speeding up common algorithms key to real-time control systems. Extended
instruction sets enable IEEE double-precision 32-bit floating-point math. Finally, the Control Law Accelerator(CLA) enables an additional 150 MIPS per core of independent processing ability. Machine learning is supportedwith the addition of the Neural-network Processing Unit (NPU), capable of 600 MOPS on 8-bit weight/8-bit data
across multiple NN layers.
To allow fast context switching from existing to new firmware, hardware enhancements for Live Firmware Update(LFU) have been added to F28P55x.
High-performance analog blocks are tightly integrated with the processing and control units to provide optimalreal-time signal chain performance. The Analog-to-Digital Converter (ADC) has been enhanced with up to
39 analog channels, 22 of which have general-purpose input/output (GPIO) capability. Implementation ofoversampling is greatly simplified with hardware improvement. For safety-critical ADC conversions, a hardware
redundancy checker has been added. The hardware redundancy checker provides the ability to compare
ADC conversion results from multiple ADC modules for consistency without additional CPU cycles. Three
Programmable Gain Amplifiers (PGAs) are present, supporting unity gain as well as up to 64x of non-inverting
gain. Twenty-four frequency-independent PWMs, 16 with high-resolution capability, enable control of multiple
power stages, from 3-phase inverters to advanced multilevel power topologies.
The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate
FPGA-like functions into the C2000 real-time MCU.
Industry-standard protocols like CAN FD and USB 2.0 are available on this device. The Fast Serial Interface(FSI) enables up to 200 Mbps of robust communications across an isolation boundary. Enhancements havebeen made to the PMBUS module to support Fast Plus mode.
Want to learn more about features that make C2000 MCUs the right choice for your real-time control system?
Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit the C2000™
real-time control MCUs page.

212

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7.2 Functional Block Diagram
Figure 7-1 shows the CPU system and associated peripherals.
C28x CPU(150 MHz)
FPU32
TMU
VCRC

CLA
(150 MHz)

Boot ROM
Secure ROM
Flash Bank0128 Sectors, 256KB

SYSTEM CONTROLCPU Timers
XTAL
INTOSC1, INTOSC2
PLLePIE
Windowed WD
NMI WD

CLA to CPU MSG RAM
CPU to CLA MSG RAM

Flash Bank1
128 Sectors, 256KB
Flash Bank2
128 Sectors, 256KB

CLA Data ROM
CLA Program ROM

Flash Bank3
128 Sectors, 256KB
SECURITYJTAG Lock
Secure Boot

CLA to DMA MSG RAM

Flash Bank4
32 Sectors, 64 KB

DMA to CLA MSG RAM
M0-M1 RAM4KB
DIAGNOSTICS
DCC
MPOST
ERAD
JTAG/cJTAG

Buses Legend
LS0-LS9 RAM
64KB

NPU

GS0-GS3 RAM
64KB

PF1

PF3

Result4x CMPSS

5x 12-Bit ADC

PF4

Data
65x GPIO
Input XBAR

2x eCAPCLADMAOTHERSEPG

24x ePWM Channels(12Ch Hi-Res Capable)

CPU
NPU

1x Buffered DAC

Output XBAR

DMA
6 Channels

PF2

PF7

PF8

PF9

PF10

1x PMBUS

2x CAN FD

1x LIN

3x SCI

2x CLB

2x SPINPU

Secure Memories Shown in Red

PF11

1x USBPF12

1x AESLFU

2x I2C

1x FSI RX
1x FSI TX

ePWM XBAR
3x eQEP(CW/CCW Support)

CLB XBAR

3x PGA

CLB Input XBARCLB Output XBARA.
B.

The internal DAC from one of the CMPSS modules can be configured as an output DAC.
The LIN module can also be used as a SCI module.

Figure 7-1. Functional Block Diagram

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7.3 Memory
7.3.1 Memory Map
The Memory Map table describes the memory map. See the Memory Controller Module section of the System
Control chapter in the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual.
Table 7-1. Memory Map
SIZE (x16)START
ADDRESSEND
ADDRESS

CPU1.DMAACCESS

CPU1.CLA1DATA
ACCESS

CPU1.CLA1
PROGRAMACCESS

ECC/
ParitySECURITY

PART NUMBER

M0 RAM

1024

0x0000_0000

0x0000_03FF

-

-

-

ECC

-

-

M1 RAM

1024

0x0000_0400

0x0000_07FF

-

-

-

ECC

-

-

PIE Vector Table

512

0x0000_0D00

0x0000_0EFF

-

-

-

Parity--

CLAtoCPU MSG
RAM

128

0x0000_1480

0x0000_14FF

-

YES

-

Parity--CPUtoCLA MSG
RAM

128

0x0000_1500

0x0000_157F

-

YES

-

Parity--

CLAtoDMA MSG
RAM

128

0x0000_1680

0x0000_16FF

YES

YES

-

Parity--DMAtoCLA MSG
RAM

128

0x0000_1700

0x0000_177F

YES

YES

-

Parity--YES

F28P559SJ9-Q1,
F28P550SJ9,
F28P559SG9-Q1,
F28P550SG9,
F28P550SG8,
F28P559SG8-Q1,
F28P559SJ6-Q1,
F28P550SJ6MEMORY

LS8 RAM - CLA
Prog

8192

0x0000_4000

0x0000_5FFF

-

-

YES

ParityLS9 RAM - CLA
Prog

8192

0x0000_6000

0x0000_7FFF

-

-

YES

ParityYES

F28P559SJ9-Q1,
F28P550SJ9,
F28P559SG9-Q1,
F28P550SG9,
F28P550SG8,
F28P559SG8-Q1,
F28P559SJ6-Q1,
F28P550SJ6

LS0 RAM

2048

0x0000_8000

0x0000_87FF

-

YES

YES

ParityYES-

LS1 RAM

2048

0x0000_8800

0x0000_8FFF

-

YES

YES

ParityYES-LS2 RAM

2048

0x0000_9000

0x0000_97FF

-

YES

YES

ParityYES-

LS3 RAM

2048

0x0000_9800

0x0000_9FFF

-

YES

YES

ParityYES-

LS4 RAM

2048

0x0000_A000

0x0000_A7FF

-

YES

YES

ParityYES-

LS5 RAM

2048

0x0000_A800

0x0000_AFFF

-

YES

YES

ParityYES-

LS6 RAM

2048

0x0000_B000

0x0000_B7FF

-

YES

YES

ParityYES-

LS7 RAM

2048

0x0000_B800

0x0000_BFFF

-

YES

YES

ParityYES-

GS0 RAM

8192

0x0000_C000

0x0000_DFFF

YES

-

-

Parity--GS1 RAM

8192

0x0000_E000

0x0000_FFFF

YES

-

-

Parity---F28P559SJ9-Q1,
F28P550SJ9,
F28P559SG9-Q1,
F28P550SG9,
F28P550SG8,
F28P559SG8-Q1,
F28P559SJ6-Q1,
F28P550SJ6-

F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6

CLA Data ROM

GS2 RAM

214

4096

8192

0x0000_F000

0x0001_0000

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0x0000_FFFF

0x0001_1FFF

-

YES

YES

-

-

-

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Table 7-1. Memory Map (continued)
MEMORY

GS3 RAM

LS8 RAM - CPU

LS9 RAM - CPU

SIZE (x16)

8192

8192

8192

START
ADDRESS

0x0001_2000

0x0001_4000

0x0001_6000

END
ADDRESS

0x0001_3FFF

0x0001_5FFF

0x0001_7FFF

CPU1.DMAACCESS

YES--

CPU1.CLA1DATA
ACCESS---

CPU1.CLA1
PROGRAMACCESS

-

-

-

ECC/
ParityParityParityParitySECURITY

PART NUMBER-

F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6YES

F28P559SJ9-Q1,
F28P550SJ9,
F28P559SG9-Q1,
F28P550SG9,
F28P559SG8-Q1,
F28P559SG2-Q1,
F28P559SJ2-Q1,
F28P550SG8,
F28P559SJ6-Q1,
F28P550SJ6YES

F28P559SJ9-Q1,
F28P550SJ9,
F28P559SG9-Q1,
F28P550SG9,
F28P559SG8-Q1,
F28P559SG2-Q1,
F28P559SJ2-Q1,
F28P550SG8,
F28P559SJ6-Q1,
F28P550SJ6USB RAM

2048

0x0004_1000

0x0004_17FF

YES

-

-

-

-

F28P559SJ9-Q1,
F28P550SJ9,
F28P559SG9-Q1,
F28P550SG9,
F28P559SJ6-Q1,
F28P550SJ6MCANA Message
RAM (CPU Access
mode)

2048

0x0005_8000

0x0005_87FF

YES

-

-

ECC

-

-

MCANA Message
RAM (Peripheral
mode)

4096

0x0005_8000

0x0005_8FFF

YES

-

-

ECC

-

-

MCANB Message
RAM (Peripheral
mode)

4096

0x0005_A000

0x0005_AFFF

YES

-

-

ECC

-

-

MCANB Message
RAM (CPU Access
mode)

2048

0x0005_A000

0x0005_A7FF

YES

-

-

ECC

-

-

TI OTP Bank 015360x0007_2000

0x0007_25FF

-

-

-

ECC

-

-

UID_REGS

160x0007_2168

0x0007_2177

-

-

-

ECC

-

F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6TI OTP Bank 1

1536

0x0007_3000

0x0007_35FF

-

-

-

ECC

-

TI OTP Bank 21536

0x0007_4000

0x0007_45FF

-

-

-

ECC

-

-

-

F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6TI OTP Bank 31536

0x0007_5000

0x0007_55FF

-

-

-

ECC

TI OTP Bank 41536

0x0007_6000

0x0007_65FF

-

-

-

ECC

-

F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6DCSM BANK0 Z1
OTP

512

0x0007_8000

0x0007_81FF

-

-

-

ECC

YES

-

DCSM BANK0 Z2
OTP

512

0x0007_8200

0x0007_83FF

-

-

-

ECC

YES

-

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Table 7-1. Memory Map (continued)
MEMORYSIZE (x16)START
ADDRESSEND
ADDRESS

CPU1.DMAACCESS

CPU1.CLA1DATA
ACCESS

CPU1.CLA1
PROGRAMACCESS

ECC/
ParitySECURITY

PART NUMBER
F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6User OTP Bank 110240x0007_8800

0x0007_8BFF

-

-

-

ECC

-

User OTP Bank 210240x0007_9000

0x0007_93FF

-

-

-

ECC

-

-

-

F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6
F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6User OTP Bank 310240x0007_9800

0x0007_9BFF

-

-

-

ECC

User OTP Bank 410240x0007_A000

0x0007_A3FF

-

-

-

ECC

-

Flash Bank 01310720x0008_0000

0x0009_FFFF

-

-

-

ECC

YES

F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6Flash Bank 1

1310720x000A_0000

0x000B_FFFF

-

-

-

ECC

YES

Flash Bank 21310720x000C_0000

0x000D_FFFF

-

-

-

ECC

YES

-

YES

F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6Flash Bank 31310720x000E_0000

0x000F_FFFF

-

-

-

ECC

Flash Bank 432768

0x0010_0000

0x0010_7FFF

-

-

-

ECC

YES

F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6

Z1-SecureBoot
Functions3072

0x003F_4000

0x003F_4BFF

-

-

-

ParityYES-

Z1-Safe Functions

1536

0x003F_4C00

0x003F_51FF

-

-

-

ParityYES-

Z2-Safe Functions

1536

0x003F_5600

0x003F_5BFF

-

-

-

ParityYES-CPU STL

9216

0x003F_5C00

0x003F_7FFF

-

-

-

Parity--Boot ROM

32768

0x003F_8000

0x003F_FFFF

-

-

-

Parity--PIE Vector Table
Swap

512

0x0100_0900

0x0100_0AFF

-

-

-

Parity--

CLA Data ROM(CPU Mapped)

4096

0x0100_1000

0x0100_1FFF

-

-

-

Parity-F28P559SJ9-Q1,
F28P550SJ9,
F28P559SG9-Q1,
F28P550SG9,
F28P550SG8,
F28P559SG8-Q1,
F28P559SJ6-Q1,
F28P550SJ6TI OTP Bank 0
ECC

192

0x0107_0400

0x0107_04BF

-

-

-

-

-

-

TI OTP Bank 1
ECC

192

0x0107_0600

0x0107_06BF

-

-

-

-

-

F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6TI OTP Bank 2
ECC

192

0x0107_0800

0x0107_08BF

-

-

-

-

-

-

-

F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6TI OTP Bank 3
ECC

216

192

0x0107_0A00

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0x0107_0ABF

-

-

-

-

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Table 7-1. Memory Map (continued)
MEMORYTI OTP Bank 4
ECC

START
ADDRESSSIZE (x16)192

0x0107_0C00

END
ADDRESS

CPU1.DMAACCESS

0x0107_0CBF

CPU1.CLA1DATA
ACCESS--

CPU1.CLA1
PROGRAMACCESS

ECC/
Parity--SECURITY

PART NUMBER-

F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ2-Q1,
F28P559SJ6-Q1,
F28P550SJ6

7.3.1.1 Dedicated RAM (Mx RAM)The CPU subsystem has two dedicated ECC-capable RAM blocks: M0 and M1. These memories are small
nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has access to them).
7.3.1.2 Local Shared RAM (LSx RAM)

Local shared RAMs (LSx RAMs) are accessible to the CPU and CLA. All LSx RAM blocks have parity. These
memories are secure and have CPU access protection (CPU write/CPU fetch).
7.3.1.3 Global Shared RAM (GSx RAM)

Global shared RAMs (GSx RAMs) are accessible from the CPU and DMA. The CPU and DMA have full read
and write access to these memories. All GSx RAM blocks have parity. The GSx RAMs have access protection(CPU write/CPU fetch/DMA write/HIC write).
7.3.1.4 Message RAM

There are two types of message RAMs on this device that can be used to share between CPU, CLA and DMA.
CLA-CPU message RAM shares data between the CLA and CPU while the CLA-DMA message RAM sharesdata between the CLA and DMA.
7.3.2 Control Law Accelerator (CLA) Memory Map
Table 7-2 shows the CLA data ROM memory map.
Table 7-2. CLA Data ROM Memory Map
MEMORYSTART ADDRESSLENGTHFFT Tables (Load)

0x0100 1070

0x0800

Data (Load)

0x0100 1870

0x078A

Version (Load)

0x0100 1FFA

0x0006FFT Tables (Run)

0x0000 F070

0x0800

Data (Run)

0x0000 F870

0x078A

Version (Run)

0x0000 FFFA

0x0006

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7.3.3 Flash Memory Map
On the F28P55x devices, five flash banks (1084KB) are available. 4 banks are 256KB and the 5th bank is 64KB
in size. Flash operations (erase and program) are performed at the bank level. Code cannot be executed fromthe same bank as an operation is being performed. Code can be allocated in a different flash bank, SRAM, or
ROM while these operations are in progress. The Addresses of Flash Sectors table lists the addresses of flash
sectors available for each part number.
7.3.3.1 Addresses of Flash Sectors

Table 7-3. Flash Memory Map
PART
NUMBERSECTORADDRESS
SIZE

START

ECC ADDRESS
END

SIZE

START

END

OTP Sectors

All F28P55x

F28P55xSJx
F28P55xSJx,
F28P55xSGx

All F28P55x

F28P55xSJx

F28P55xSJx,
F28P55xSGx

TI OTP Bank 0(Unsecure)1520 x 16

0x0007 2000

0x0007 25EF

190 x 160x0107 0400

0x0107 04BD

TI OTP Bank 0(Secure)16 x 160x0007 25F00x0007 25FF

2 x 160x0107 04BE

0x0107 04BE

TI OTP Bank 21536 x 16

0x0007 4000

0x0007 45FF

192 x 160x0107 0800

0x0107 08BF

TI OTP Bank 11536 x 16

0x0007 3000

0x0007 35FF

192 x 160x0107 0600

0x0107 06BF

TI OTP Bank 31536 x 16

0x0007 5000

0x0007 55FF

192 x 160x0107 0A00

0x0107 0ABF

TI OTP Bank 41536 x 16

0x0007 6000

0x0007 65FF

192 x 160x0107 0C00

0x0107 0CBF

User
configurable
DCSM Z1 OTP
Bank 0512 x 160x0007 8000

0x0007 81FF

64 x 160x0107 1000

0x0107 103F

User
configurable
DCSM Z2 OTP
Bank 0512 x 160x0007 8200

0x0007 83FF

64 x 160x0107 1040

0x0107 107F

User
configurable
OTP Bank 2

1K x 160x0007 9000

0x0007 93FF

128 x 160x0107 1100

0x0107 117F

User
configurable
OTP Bank 1

1K x 160x0007 8800

0x0007 8BFF

128 x 160x0107 1080

0x0107 10FF

User
configurable
OTP Bank 3

1K x 160x0007 9800

0x0007 9BFF

128 x 160x0107 1180

0x0107 11FF

User
configurable
OTP Bank 4

1K x 160x0007 A000

0x0007 A3FF

128 x 160x0107 1200

0x0107 127F

Sector 0

1K x 160x0008 0000

0x0008 03FF

128 x 160x0108 0000

0x0108 007F

Sector 1

1K x 160x0008 0400

0x0008 07FF

128 x 160x0108 0080

0x0108 00FF

Sector 2

1K x 160x000800800

0x0008 0BFF

128 x 160x0108 0100

0x0108 017F

Bank 0 Sectors

All

218

...

...

...

...

...

...

...

Sector 125

1K x 160x0009 F400

0x0009 F7FF

128 x 160x0108 3E80

0x0108 3EFF

Sector 126

1K x 160x0009 F800

0x0009 FBFF

128 x 160x0108 3F00

0x0108 3F7F

Sector 127

1K x 160x0009 FC00

0x0009 FFFF

128 x 160x0108 3F80

0x0108 3FFF

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Table 7-3. Flash Memory Map (continued)
PART
NUMBERSECTORADDRESS
SIZE

START

Sector 0

1K x 160x000A 0000

Sector 1

1K x 16

Sector 2

1K x 16

ECC ADDRESS
END

SIZE

START

END

0x000A 03FF

128 x 160x0108 4000

0x0108 407F

0x000A 0400

0x000A 07FF

128 x 160x0108 4080

0x0108 40FF

0x000A 0800

0x000A 0BFF

128 x 160x0108 4100

0x0108 417F

Bank 1 Sectors

F28P55xSJx

...

...

...

...

...

...

...

Sector 125

1K x 160x000B F400

0x000B F7FF

128 x 160x0108 7E80

0x0108 7EFF

Sector 126

1K x 160x000B F800

0x000B FBFF

128 x 160x0108 7F00

0x0108 7F7F

Sector 127

1K x 160x000B FC00

0x000B FFFF

128 x 160x0108 7F80

0x0108 7FFF

Sector 0

1K x 160x000C 0000

0x000C 03FF

128 x 160x0108 8000

0x0108 807F

Sector 1

1K x 160x000C 0400

0x000C 07FF

128 x 160x0108 8080

0x0108 80FF

Sector 2

1K x 160x000C 0800

0x000C 0BFF

128 x 160x0108 8100

0x0108 817F

Bank 2 Sectors

All

...

...

...

...

...

...

...

Sector 125

1K x 160x000D F400

0x000D F7FF

128 x 160x0108 BE80

0x0108 BEFF

Sector 126

1K x 160x000D F800

0x000D FBFF

128 x 160x0108 BF00

0x0108 BF7F

Sector 127

1K x 160x000D FC00

0x000D FFFF

128 x 160x0108 BF80

0x0108 BFFF

Sector 0

1K x 160x000E 0000

0x000E 03FF

128 x 160x0108 C000

0x0108 C07F

Sector 1

1K x 160x000E 0400

0x000E 07FF

128 x 160x0108 C080

0x0108 C0FF

Sector 2

1K x 160x000E 0800

0x000E 0BFF

128 x 160x0108 C100

0x0108 C17F

Bank 3 Sectors

F28P55xSJx

...

...

...

...

...

...

...

Sector 125

1K x 160x000F F400

0x000F F7FF

128 x 160x0108 FE800x0108 FEFF

Sector 126

1K x 160x000F F800

0x000F FBFF

128 x 160x0108 FF00

0x0108 FF7F

Sector 127

1K x 160x000F FC00

0x000F FFFF

128 x 160x0108F F80

0x0108 FFFF

Sector 0

1K x 160x0010 0000

0x0010 03FF

128 x 160x0109 0000

0x0109 007F

Sector 1

1K x 160x0010 0400

0x0010 07FF

128 x 160x0109 0080

0x0190 00FF

Sector 2

1K x 160x0010 0800

0x0010 0BFF

128 x 160x0109 0100

0x0109 0180

...

...

...

...

...

...

...

Sector 29

1K x 160x0010 7400

0x0010 77FF

128 x 160x0109 0E80

0x0109 0EFF

Sector 30

1K x 160x0010 7800

0x0010 7BFF

128 x 160x0109 0F00

0x0109 0F7F

Sector 31

1K x 160x0010 7C00

0x0010 7FFF

128 x 160x0109 0F80

0x0109 0FFF

Bank 4 Sectors

F28P55xSJ9,F2
8P55xSJ6,
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7.3.4 Peripheral Registers Memory Map
Table 7-4. Peripheral Registers Memory Map
Structure

DriverLib Name

Base Address

CPU1

CPU1.DMA

CPU1.CLA1

Pipeline Protected

Peripheral Frame 0 (PF0)
CPUTIMER_REGS

CPUTIMER0_BASE

0x0000_0C00

YES

-

-

-

CLA_ONLY_REGS

CLA1_ONLY_BASE

0x0000_0C00

-

-

YES

-

CPUTIMER_REGS

CPUTIMER1_BASE

0x0000_0C08

YES

-

-

-

CPUTIMER_REGS

CPUTIMER2_BASE

0x0000_0C10

YES

-

-

-

PIE_CTRL_REGSPIECTRL_BASE

0x0000_0CE0

YES

-

-

-

CLA_SOFTINT_REGS

CLA1_SOFTINT_BASE

0x0000_0CE0

-

-

YES

-

PIE_VECT_TABLEPIEVECTTABLE_BASE

0x0000_0D00

YES

-

-

-

DMA_REGSDMA_BASE

0x0000_1000

YES

-

-

-

DMA_CH_REGS

DMA_CH1_BASE

0x0000_1020

YES

-

-

-

DMA_CH_REGS

DMA_CH2_BASE

0x0000_1040

YES

-

-

-

DMA_CH_REGS

DMA_CH3_BASE

0x0000_1060

YES

-

-

-

DMA_CH_REGS

DMA_CH4_BASE

0x0000_1080

YES

-

-

-

DMA_CH_REGS

DMA_CH5_BASE

0x0000_10A0

YES

-

-

-

DMA_CH_REGS

DMA_CH6_BASE

0x0000_10C0

YES

-

-

-

CLA1_BASE

0x0000_1400

YES

-

-

-

ADC_RESULT_REGSADCARESULT_BASE

0x0000_1800

YES

YES

YES

-

ADC_RESULT_REGSADCBRESULT_BASE

0x0000_1880

YES

YES

YES

-

ADC_RESULT_REGSADCCRESULT_BASE

0x0000_1900

YES

YES

YES

-

ADC_RESULT_REGSADCDRESULT_BASE

0x0000_1980

YES

YES

YES

-

ADC_RESULT_REGSADCERESULT_BASE

0x0000_1A00

YES

YES

YES

-

ERAD_PCTRACE_BUFFER_BASE

0x0005_FE00

YES

-

-

YES

CLA_REGSPCTRACE_BUFFER_REGSUID_REGSUID_BASE

0x0007_2168

YES

-

-

-

DCSM_Z1_OTP

DCSM_Z1OTP_BASE

0x0007_8000

YES

-

-

-

DCSM_Z2_OTP

DCSM_Z2OTP_BASE

0x0007_8200

YES

-

-

-

Peripheral Frame 1 (PF1)EPWM_REGSEPWM1_BASE

0x0000_4000

YES

YES

YES

YES

EPWM_REGSEPWM2_BASE

0x0000_4100

YES

YES

YES

YES

EPWM_REGSEPWM3_BASE

0x0000_4200

YES

YES

YES

YES

EPWM_REGSEPWM4_BASE

0x0000_4300

YES

YES

YES

YES

EPWM_REGSEPWM5_BASE

0x0000_4400

YES

YES

YES

YES

EPWM_REGSEPWM6_BASE

0x0000_4500

YES

YES

YES

YES

EPWM_REGSEPWM7_BASE

0x0000_4600

YES

YES

YES

YES

EPWM_REGSEPWM8_BASE

0x0000_4700

YES

YES

YES

YES

220

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Table 7-4. Peripheral Registers Memory Map (continued)
Structure

DriverLib Name

Base Address

CPU1

CPU1.DMA

CPU1.CLA1

Pipeline Protected

EPWM_REGSEPWM9_BASE

0x0000_4800

YES

YES

YES

YES

EPWM_REGSEPWM10_BASE

0x0000_4900

YES

YES

YES

YES

EPWM_REGSEPWM11_BASE

0x0000_4A00

YES

YES

YES

YES

EPWM_REGSEPWM12_BASE

0x0000_4B00

YES

YES

YES

YES

EQEP_REGS

EQEP1_BASE

0x0000_5100

YES

YES

YES

YES

EQEP_REGS

EQEP2_BASE

0x0000_5140

YES

YES

YES

YES

EQEP_REGS

EQEP3_BASE

0x0000_5180

YES

YES

YES

YES

ECAP_REGSECAP1_BASE

0x0000_5200

YES

YES

YES

YES

ECAP_REGSECAP2_BASE

0x0000_5240

YES

YES

YES

YES

CMPSS_REGSCMPSS1_BASE

0x0000_5500

YES

YES

YES

YES

CMPSS_REGSCMPSS2_BASE

0x0000_5540

YES

YES

YES

YES

CMPSS_REGSCMPSS3_BASE

0x0000_5580

YES

YES

YES

YES

CMPSS_REGSCMPSS4_BASE

0x0000_55C0

YES

YES

YES

YES

PGA_REGS

PGA1_BASE

0x0000_5B00

YES

YES

YES

YES

PGA_REGS

PGA2_BASE

0x0000_5B10

YES

YES

YES

YES

PGA_REGS

PGA3_BASE

0x0000_5B20

YES

YES

YES

YES

DAC_REGSDACA_BASE

0x0000_5C00

YES

YES

YES

YES

Peripheral Frame 2 (PF2)SPI_REGSSPIA_BASE

0x0000_6100

YES

YES

YES

YES

SPI_REGSSPIB_BASE

0x0000_6110

YES

YES

YES

YES

PMBUS_REGS

PMBUSA_BASE

0x0000_6400

YES

YES

YES

YES

FSI_TX_REGSFSITXA_BASE

0x0000_6600

YES

YES

YES

YES

FSI_RX_REGSFSIRXA_BASE

0x0000_6680

YES

YES

YES

YES

Peripheral Frame 3 (PF3)ADC_REGSADCC_BASE

0x0000_6A00

YES

-

YES

YES

ADC_REGSADCD_BASE

0x0000_6C00

YES

-

YES

YES

ADC_REGS

ADCE_BASE

0x0000_6E00

YES

-

YES

YES

ADC_REGS

ADCA_BASE

0x0000_7400

YES

-

YES

YES

ADC_REGSADCB_BASE

0x0000_7600

YES

-

YES

YES

Peripheral Frame 4 (PF4)INPUT_XBAR_REGSXBAR_REGSINPUTXBAR_BASE

0x0000_7900

YES

-

-

YES

XBAR_BASE

0x0000_7920

YES

-

-

YES

SYNC_SOC_REGSSYNCSOC_BASE

0x0000_7940

YES

-

-

YES

INPUT_XBAR_REGS

CLBINPUTXBAR_BASE

0x0000_7960

YES

-

-

YES

DMA_CLA_SRC_SEL_REGSDMACLASRCSEL_BASE

0x0000_7980

YES

-

-

YES

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Table 7-4. Peripheral Registers Memory Map (continued)
Structure

DriverLib Name

Base Address

CPU1

CPU1.DMA

CPU1.CLA1

Pipeline Protected

EPWM_XBAR_REGSEPWMXBAR_BASE

0x0000_7A00

YES

-

-

YES

CLB_XBAR_REGS

CLBXBAR_BASE

0x0000_7A40

YES

-

-

YES

OUTPUT_XBAR_REGSOUTPUTXBAR_BASE

0x0000_7A80

YES

-

-

YES

OUTPUT_XBAR_REGS

CLBOUTPUTXBAR_BASE

0x0000_7BC0

YES

-

-

YES

GPIO_CTRL_REGSGPIOCTRL_BASE

0x0000_7C00

YES

-

-

YES

GPIO_DATA_REGSGPIODATA_BASE

0x0000_7F00

YES

-

YES

YES

GPIODATAREAD_BASE

0x0000_7F80

YES

-

YES

YES

DEV_CFG_REGSDEVCFG_BASE

0x0005_D000

YES

-

-

YES

CLK_CFG_REGSCLKCFG_BASE

0x0005_D200

YES

-

-

YES

CPU_SYS_REGSCPUSYS_BASE

0x0005_D300

YES

-

-

YES

SYS_STATUS_REGSSYSSTAT_BASE

0x0005_D400

YES

-

-

YES

PERIPH_AC_REGSPERIPHAC_BASE

0x0005_D500

YES

-

-

YES

ANALOGSUBSYS_BASE

0x0005_D700

YES

-

-

YES

GPIO_DATA_READ_REGSANALOG_SUBSYS_REGS

Peripheral Frame 6 (PF6)
ERAD_GLOBAL_REGS

ERAD_GLOBAL_BASE

0x0005_E800

YES

-

-

YES

ERAD_HWBP_REGS

ERAD_HWBP1_BASE

0x0005_E900

YES

-

-

YES

ERAD_HWBP_REGS

ERAD_HWBP2_BASE

0x0005_E908

YES

-

-

YES

ERAD_HWBP_REGS

ERAD_HWBP3_BASE

0x0005_E910

YES

-

-

YES

ERAD_HWBP_REGS

ERAD_HWBP4_BASE

0x0005_E918

YES

-

-

YES

ERAD_HWBP_REGS

ERAD_HWBP5_BASE

0x0005_E920

YES

-

-

YES

ERAD_HWBP_REGS

ERAD_HWBP6_BASE

0x0005_E928

YES

-

-

YES

ERAD_HWBP_REGS

ERAD_HWBP7_BASE

0x0005_E930

YES

-

-

YES

ERAD_HWBP_REGS

ERAD_HWBP8_BASE

0x0005_E938

YES

-

-

YES

ERAD_COUNTER_REGS

ERAD_COUNTER1_BASE

0x0005_E980

YES

-

-

YES

ERAD_COUNTER_REGS

ERAD_COUNTER2_BASE

0x0005_E990

YES

-

-

YES

ERAD_COUNTER_REGS

ERAD_COUNTER3_BASE

0x0005_E9A0

YES

-

-

YES

ERAD_COUNTER_REGS

ERAD_COUNTER4_BASE

0x0005_E9B0

YES

-

-

YES

ERAD_CRC_GLOBAL_REGS

ERAD_CRC_GLOBAL_BASE

0x0005_EA00

YES

-

-

YES

ERAD_CRC_REGS

ERAD_CRC1_BASE

0x0005_EA10

YES

-

-

YES

ERAD_CRC_REGS

ERAD_CRC2_BASE

0x0005_EA20

YES

-

-

YES

ERAD_CRC_REGS

ERAD_CRC3_BASE

0x0005_EA30

YES

-

-

YES

ERAD_CRC_REGS

ERAD_CRC4_BASE

0x0005_EA40

YES

-

-

YES

ERAD_CRC_REGS

ERAD_CRC5_BASE

0x0005_EA50

YES

-

-

YES

ERAD_CRC_REGS

ERAD_CRC6_BASE

0x0005_EA60

YES

-

-

YES

ERAD_CRC_REGS

ERAD_CRC7_BASE

0x0005_EA70

YES

-

-

YES

222

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Table 7-4. Peripheral Registers Memory Map (continued)
Structure

DriverLib Name

Base Address

CPU1

CPU1.DMA

CPU1.CLA1

Pipeline Protected

ERAD_CRC_REGS

ERAD_CRC8_BASE

0x0005_EA80

YES

-

-

YES

PCTRACE_REGS

ERAD_PCTRACE_BASE

0x0005_EAD0

YES

-

-

YES

EPG1_BASE

0x0005_EC00

YES

-

-

YES

EPG_MUX_REGSEPG1MUX_BASE

0x0005_ECD0

YES

-

-

YES

DCSM_Z1_REGS

DCSM_Z1_BASE

0x0005_F000

YES

-

-

YES

DCSM_Z2_REGS

DCSM_Z2_BASE

0x0005_F080

YES

-

-

YES

DCSMCOMMON_BASE

0x0005_F0C0

YES

-

-

YES

MEMCFG_BASE

0x0005_F400

YES

-

-

YES

ACCESSPROTECTION_BASE

0x0005_F500

YES

-

-

YES

EPG_REGSDCSM_COMMON_REGS
MEM_CFG_REGSACCESS_PROTECTION_REGSMEMORY_ERROR_REGSMEMORYERROR_BASE

0x0005_F540

YES

-

-

YES

TEST_ERROR_REGSTESTERROR_BASE

0x0005_F590

YES

-

-

YES

FLASH_CTRL_REGS

FLASH0CTRL_BASE

0x0005_F800

YES

-

-

YES

FLASH_ECC_REGS

FLASH0ECC_BASE

0x0005_FB00

YES

-

-

YES

Peripheral Frame 7 (PF7)
EXT_EVT_REGS

EXTEVT_BASE

0x0005_4000

YES

-

-

YES

EXT_GPRCM_REGS

EXTGPRCM_BASE

0x0005_400A

YES

-

-

YES

IPSTANDARD_REGSIPSTANDARD_BASE

0x0005_4020

YES

-

-

YES

IPSPECIFIC_REGSIPSPECIFIC_BASE

0x0005_4100

YES

-

-

YES

DATA_REGSDATA_BASE

0x0005_4700

YES

-

-

YES

ACC_REGSACC_BASE

0x0005_4C00

YES

-

-

YES

INSTRUCTION_REGS

INSTRUCTION_BASE

0x0005_5000

YES

-

-

YES

RFDATA_REGS

RFDATA_BASE

0x0005_5800

YES

-

-

YES

MCANSS_REGSMCANASS_BASE

0x0005_9400

YES

-

-

YES

MCAN_REGSMCANA_BASE

0x0005_9600

YES

-

-

YES

MCANA_ERROR_BASE

0x0005_9800

YES

-

-

YES

MCANSS_REGSMCANBSS_BASE

0x0005_B400

YES

-

-

YES

MCAN_REGSMCANB_BASE

0x0005_B600

YES

-

-

YES

MCANB_ERROR_BASE

0x0005_B800

YES

-

-

YES

DCC_REGS

DCC0_BASE

0x0005_E700

YES

-

-

YES

DCC_REGS

DCC1_BASE

0x0005_E740

YES

-

-

YES

YES

YES

YES

YES

MCAN_ERROR_REGS

MCAN_ERROR_REGS

Peripheral Frame 8 (PF8)
LIN_REGS

LINA_BASE

0x0000_6800
Peripheral Frame 9 (PF9)

WD_REGS

WD_BASE

0x0000_7000

YES

-

-

YES

NMI_INTRUPT_REGS

NMI_BASE

0x0000_7060

YES

-

-

YES

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Table 7-4. Peripheral Registers Memory Map (continued)
Structure

DriverLib Name

Base Address

CPU1

CPU1.DMA

CPU1.CLA1

Pipeline Protected

XINT_REGSXINT_BASE

0x0000_7070

YES

-

-

YES

SCI_REGSSCIA_BASE

0x0000_7200

YES

-

-

YES

SCI_REGSSCIB_BASE

0x0000_7210

YES

-

-

YES

SCI_REGSSCIC_BASE

0x0000_7220

YES

-

-

YES

I2C_REGS

I2CA_BASE

0x0000_7300

YES

-

-

YES

I2C_REGS

I2CB_BASE

0x0000_7340

YES

-

-

YES

Peripheral Frame 10 (PF10)
CLB_LOGIC_CONFIG_REGS

CLB1_LOGICCFG_BASE

0x0000_3000

YES

-

YES

YES

CLB_LOGIC_CONTROL_REGS

CLB1_LOGICCTRL_BASE

0x0000_3100

YES

-

YES

YES

CLB_DATA_EXCHANGE_REGS

CLB1_DATAEXCH_BASE

0x0000_3180

YES

-

YES

YES

CLB_LOGIC_CONFIG_REGS

CLB2_LOGICCFG_BASE

0x0000_3400

YES

-

YES

YES

CLB_LOGIC_CONTROL_REGS

CLB2_LOGICCTRL_BASE

0x0000_3500

YES

-

YES

YES

CLB_DATA_EXCHANGE_REGS

CLB2_DATAEXCH_BASE

0x0000_3580

YES

-

YES

YES

0x0004_0000

YES

YES

-

YES

AESA_BASE

0x0004_2000

YES

YES

-

YES

AESA_SS_BASE

0x0004_2C00

YES

YES

-

YES

YES

-

YES

YES

Peripheral Frame 11 (PF11)
USB_REGSAES_REGSAES_SS_REGS

USBA_BASE

Peripheral Frame 12 (PF12)
LFU_REGS224

LFU_BASE

0x0000_7FE0

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7.4 Identification
Table 7-5 lists the Device Identification Registers. Additional information on these device identification registers
can be found in the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual. See the register
descriptions of PARTIDH and PARTIDL for identification of production status (TMX or TMS) and other device
information.
Table 7-5. Device Identification Registers
NAME

ADDRESSSIZE (x16)

DESCRIPTION
Bits

Options

14-13

1 = InstaSPIN-FOC

INSTASPIN

2 = NONE
3 = NONEPARTIDL

0x0005 D008

2

10-8

0 = 56 pin (QFN)

PIN_COUNT

1 = 64 pin (QFP)
2 = 80 pin (QFP)
3 = 100 pin (QFP)
4 = 128 pin (QFP)

7-6

0 = Engineering Sample (TMX)

QUAL

1 = Pilot Production (TMP)
2 = Fully Qualified (TMS)

Device part identification number

PARTIDH

0x0005 D00A

2

TMS320F28P55xSJ9

0x09FF 0500

TMS320F28P55xSJ60x09FC 0500

TMS320F28P55xSJ2

0x09F8 0500

TMS320F28P55xSG9

0x09F5 0500

TMS320F28P55xSG8

0x09F4 0500

TMS320F28P55xSG2

0x09EE 0500

Silicon revision number
REVID

UID_UNIQUE

0x0005 D00C

0x0007 2172

2

4

Revision 00x0000 0001

Revision A

0x0000 0002

Unique identification number. This number is different on eachindividual device with the same PARTIDH. This unique number
can be used as a serial number in the application. This number
is present only on TMS devices.

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7.5 Bus Architecture – Peripheral Connectivity
The Peripheral Connectivity table lists a broad view of the peripheral and configuration register accessibility fromeach bus controller.
Table 7-6. Peripheral Connectivity
PERIPHERAL

DMA

CLA

C28

SYSTEM PERIPHERALSCPU Timers

Y

ERAD

Y

GPIO DataY

Y

GPIO Pin Mapping and ConfigurationY

XBAR Configuration

Y

System Configuration

Y

AES

Y

Y

EPG

Y

LFU

Y

DCC

Y
Y

MEMORY
M0/M1

Y

LSx

Y

GSx

Y

Y
Y

ROM

Y

FLASH

Y
CONTROL PERIPHERALSePWM/HRPWM

Y

Y

Y

eCAP

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

eQEP

(1)

CLB
ANALOG PERIPHERALS
CMPSS
DAC

(1)

(1)

ADC Configuration
ADC Results
PGA

(1)

(1)

Y

Y

Y

Y

Y

Y

Y

Y

COMMUNICATION PERIPHERALSMCAN(CAN-FD)(1)

FSITX/FSIRX

Y

Y

Y

Y

LIN

Y

Y

Y

PMBus

Y

Y

Y

Y

Y

I2C

Y
Y

SCI

Y

SPI
USB

(1)

(1)

These modules are accessible from DMA but cannot trigger a DMA transfer.

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7.6 C28x Processor
The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal processing;
reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets.
The CPU features include a modified Harvard architecture and circular addressing. The RISC featuresare single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking,and bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be
performed in parallel. The CPU can read instructions and data while it writes data simultaneously to maintain the
single-cycle instruction operation across the pipeline. The CPU does this over six separate address/data buses.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set
Reference Guide.
7.6.1 Floating-Point Unit (FPU)
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU byadding registers and instructions to support IEEE single-precision floating-point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point unit
registers. The additional floating-point unit registers are the following:• Eight floating-point result registers, RnH (where n = 0–7)
• Floating-point Status Register (STF)• Repeat Block Register (RB)All of the floating-point registers, except the RB, are shadowed. This shadowing can be used in high-priority
interrupts for fast context save and restore of the floating-point registers.
For more information on the C28x Floating Point Unit (FPU), see the TMS320C28x Extended Instruction Sets
Technical Reference Manual.
7.6.2 Trigonometric Math Unit (TMU)
The trigonometric math unit (TMU) extends the capabilities of a C28x+FPU by adding instructions andleveraging existing FPU instructions to speed up the execution of common trigonometric and arithmetic
operations listed in Table 7-7.
Table 7-7. TMU Supported Instructions
Instructions

C Equivalent Operation

MPY2PIF32 RaH,RbH

a = b * 2pi

Pipeline Cycles
2/3

DIV2PIF32 RaH,RbH

a = b / 2pi

2/3

DIVF32 RaH,RbH,RcH

a = b/c5

SQRTF32 RaH,RbH

a = sqrt(b)5

SINPUF32 RaH,RbH

a = sin(b*2pi)

4

COSPUF32 RaH,RbH

a = cos(b*2pi)

4

ATANPUF32 RaH,RbH

a = atan(b)/2pi

4

QUADF32 RaH,RbH,RcH,RdH

Operation to assist in calculating ATANPU2

5

Exponent instruction IEXP2F32 and logarithmic instruction LOG2F32 have been added to support computationof floating-point power function for the nonlinear proportional integral derivative control (NLPID) component of
the C2000 Digital Control Library. These two added instructions reduce the power function calculations from atypical of 300 cycles using library emulation to less than 10 cycles.
No changes have been made to existing instructions, pipeline, or memory bus architecture. All TMU instructions
use the existing FPU register set (R0H to R7H) to carry out the operations.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.

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7.6.3 VCRC Unit
Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity overlarge data blocks, communication packets, or code sections. The C28x+VCRC can perform 8-bit, 16-bit, 24-bit,
and 32-bit CRCs. For example, the VCRC can compute the CRC for a block length of 10 bytes in 10 cycles. A
CRC result register contains the current CRC, which is updated whenever a CRC instruction is executed.
The following are the CRC polynomials used by the CRC calculation logic of the VCRC:• CRC8 polynomial = 0x07
• CRC16 polynomial 1 = 0x8005• CRC16 polynomial 2 = 0x1021• CRC24 polynomial = 0x5d6dcb• CRC32 polynomial 1 = 0x04c11db7• CRC32 polynomial 2 = 0x1edc6f41
This module can calculate CRCs for a byte of data in a single cycle. The CRC calculation for CRC8, CRC16,
CRC24, and CRC32 is done byte-wise (instead of computing on a complete 16-bit or 32-bit data read by theC28x core) to match the byte-wise computation requirement mandated by various standards.
The VCRC Unit also allows the user to provide the size (1b-32b) and value of any polynomial to fit custom CRC
requirements. The CRC execution time increases to three cycles when using a custom polynomial.
For more information on the Cyclic Redundancy Check (VCRC) instruction sets, see the TMS320C28x Extended
Instruction Sets Technical Reference Manual.

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7.7 Control Law Accelerator (CLA)The CLA Type-2 is an independent, fully programmable, 32-bit floating-point math processor that brings
concurrent control-loop execution to the C28x family. The low interrupt-latency of the CLA allows it to read
ADC samples "just-in-time." This significantly reduces the ADC sample to output delay to enable faster system
response and higher MHz control loops. By using the CLA to service time-critical control loops, the main CPU isfree to perform other system tasks such as communications and diagnostics.
The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-criticalcontrol loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables fastersystem response and higher frequency control loops. Using the CLA for time-critical tasks frees up the main
CPU to perform other system and communication functions concurrently.
The following is a list of major features of the CLA:
• C compilers are available for CLA software development• Clocked at the same rate as the main CPU (SYSCLKOUT).
• An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:• Program Address Bus (PAB) and Program Data Bus (PDB)• Data Read Address Bus (DRAB), Data Read Data Bus (DRDB), Data Write Address Bus (DWAB), andData Write Data Bus (DWDB)– Independent 8-stage pipeline.
– 16-bit program counter (MPC)– Four 32-bit result registers (MR0 to MR3)
– Two 16-bit auxiliary registers (MAR0, MAR1)– Status register (MSTF)• Instruction set includes:– IEEE single-precision (32-bit) floating-point math operations– Floating-point math with parallel load or store– Floating-point multiply with parallel add or subtract– 1/X and 1/sqrt(X) estimations– Data type conversions– Conditional branch and call
– Data load/store operations• The CLA program code can consist of up to eight tasks or interrupt service routines, or seven tasks and amain background task.
– The start address of each task is specified by the MVECT registers.
– No limit on task size as long as the tasks fit within the configurable CLA program memory space.
– One task is serviced at a time until its completion. There is no nesting of tasks.
– Upon task completion a task-specific interrupt is flagged within the PIE.
– When a task finishes the next highest-priority pending task is automatically started.
– The Type-2 CLA can have a main task that runs continuously in the background, while other high-priority
events trigger a foreground task.
• Task trigger mechanisms:– C28x CPU through the IACK instruction– Task1 to Task8: up to 256 possible trigger sources from peripherals connected to the shared bus on which
the CLA assumes secondary ownership.
– Task8 can be set to be the background task, while Tasks 1 to 7 take peripheral triggers.
• Memory and Shared Peripherals:– Two dedicated message RAMs for communication between the CLA and the main CPU.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
– Two dedicated message RAMs for communication between the CLA and the DMA

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CLA Control
Register Set

MIFR(16)

From Shared
Peripherals

MPERINT1toMPERINT8

CLA_INT1
to
CLA_INT8

MIOVF(16)MICLR(16)MICLROVF(16)PIE

MIFRC(16)
MIER(16)MIRUN(16)MCTLBGRND(16)MSTSBGRND(16)
CLA1SOFTINTEN(16)CLA1INTFRC(16)

INT11
INT12

C28x
CPU

LVF
LUF

SYSCLK
CLA Clock Enable
SYSRS

MVECT1(16)MVECT2(16)MVECT3(16)CPU Read/Write Data Bus

MVECT4(16)MVECT5(16)MVECT6(16)MVECT7(16)MVECT8(16)

CLA Program
Memory (LSx)

CLA Program Bus

LSxMSEL[MSEL_LSx]
LSxCLAPGM[CLAPGM_LSx]

MVECTBGRND(16)MVECTBGRNDACTIVE(16)MPSA1(32)MPSA2(32)

CLA Data
Memory (LSx)

CLA Data Bus

MCTL(16)

CLA Execution
Register Set

CPU Data BusMPSACTL(16)

CLA Message
RAMs

MPC(16)
MSTF(32)
MR0(32)
MR1(32)
MR2(32)MR3(32)

SharedPeripherals

MEALLOW
MAR0(16)MAR1(16)
CPU Read Data Bus

Figure 7-2. CLA Block Diagram

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7.8 Embedded Real-Time Analysis and Diagnostic (ERAD)
The ERAD module enhances the debug and system-analysis capabilities of the device. The debug and systemanalysis enhancements provided by the ERAD module is done outside of the CPU. The ERAD module consistsof the Enhanced Bus Comparator units and the System Event Counter units. The Enhanced Bus Comparator
units are used to generate hardware breakpoints, hardware watch points, and other output events. The System
Event Counter units are used to analyze and profile the system. The ERAD module is accessible by the
debugger and by the application software, which significantly increases the debug capabilities of many real-timesystems, especially in situations where debuggers are not connected. In the TMS320F28P55x devices, theERAD module contains eight Enhanced Bus Comparator units (which increases the number of Hardware
breakpoints from two to ten) and four Benchmark System Event Counter units.

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7.9 Direct Memory Access (DMA)The DMA module provides a hardware method of transferring data between peripherals and/or memory without
intervention from the CPU, thereby freeing up bandwidth for other system functions. Additionally, the DMA has
the capability to orthogonally rearrange the data as it is transferred as well as “ping-pong” data between buffers.
These features are useful for structuring data into blocks for optimal CPU processing. Figure 7-3 shows adevice-level block diagram of the DMA.
DMA features include:• Six channels with independent PIE interrupts• Peripheral interrupt trigger sources– ADC interrupts and EVT signals– External Interrupts– ePWM SOC signals– CPU timers– eCAP– SPI transmit and receive– LIN transmit and receive• Data sources and destinations:– GSx RAM
– ADC result registers– Control peripheral registers (ePWM, eQEP, eCAP)– SPI, LIN, CAN, and PMBus registers– USB– PGA control registers• Word Size: 16-bit or 32-bit (SPI limited to 16-bit)• Throughput: Four cycles per word without arbitration
CAN

LIN

USB

AES

ADC
WRAPPERADC
RESULTS

XINT

TIMER

Global Shared (GS03) RAM

DMA busC28x bus

TINT (0-2)
XINT(1-5)
ADCx.INT(1-5), ADCx.EVT
DMA_CHx(1-6)

AESA_ContextIn, AESA_ContextOut, AESA_DataIn, AESA_DataOut
LINxTXDMA, LINxRXDMADMA Trigger
Source Selection
ECAP(1-2)DMAEPWM(1-12).SOCA, EPWM(1-12).SOCB
CLB1-2INTEPGAINTDMACHSRCSEL1.CHx
DMACHSRCSEL2.CHx
CHx.MODE.PERINTSEL(x = 1 to 6)

DMA

C28x

PIE

SPITXDMA(A-B)
SPIRXDMA(A-B)

FSITXADMA, FSIRXADMAFSI_DATA_TAG_MATCH,
FSI_PING_TAG_MATCH

PGA

DAC

CMPSS

eQEP

eCAP

EPWM

EPG

CLB

SPI

PM
Bus

FSI

Figure 7-3. DMA Block Diagram

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7.10 Device Boot Modes
This section explains the default boot modes, as well as all the available boot modes supported on this device.
The boot ROM uses the boot mode select, general-purpose input/output (GPIO) pins to determine the bootmode configuration.
Table 7-8 shows the boot mode options available for selection by the default boot mode select pins. Users havethe option to program the device to customize the boot modes selectable in the boot-up table as well as the bootmode select pin GPIOs used.
All the peripheral boot modes that are supported use the first instance of the peripheral module (SCIA, SPIA,
I2CA, CANA, and so forth). Whenever these boot modes are referred to in this chapter, such as SCI boot, it isactually referring to the first module instance, which means the SCI boot on the SCIA port. The same applies tothe other peripheral boots.
See the Reset - XRSn - Switching Characteristics table and the Power-on Reset figure for tboot-flash, the bootROM execution time to first instruction fetch in flash.
Table 7-8. Device Default Boot Modes
BOOT MODE
Parallel IO
SCI / Wait Boot

(1)

CAN(MCAN-NONFD)
Flash(USB)
(1)
(2)

(2)

GPIO24(DEFAULT BOOT MODE SELECT PIN 1)

GPIO32(DEFAULT BOOT MODE SELECT PIN 0)

0

0

0

1

1

0

1

1

SCI boot mode can be used as a wait boot mode as long as SCI continues to wait for an 'A' or 'a' during the SCI autobaud lockprocess.
If the default flash entry address is not programmed, the boot mode will switch to USB Boot for those devices that include the USB
peripheral. On devices without a USB, the action will be to enter the ITRAP ISR if the default flash entry address is not programmed.
The switch to USB boot is only supported for the default flash entry address option and not all entry address options.

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7.10.1 Device Boot Configurations
This section details what boot configurations are available and how to configure them. This device supports
from 0 boot mode select pins up to 3 boot mode select pins as well as from 1 configured boot mode up to 8
configured boot modes.
To change and configure the device from the default settings to custom settings for your application, use thefollowing process:1. Determine all the various ways you want application to be able to boot. (For example: Primary boot option ofFlash boot for your main application, secondary boot option of CAN boot for firmware updates, tertiary bootoption of SCI boot for debugging, etc)
2. Based on the number of boot modes needed, determine how many boot mode select pins (BMSPs) are
required to select between your selected boot modes. (For example: 2 BMSPs are required to selectbetween 3 boot mode options)
3. Assign the required BMSPs to a physical GPIO pin. (For example, BMSP0 to GPIO10, BMSP1 to GPIO51,
and BMSP2 left as default which is disabled). Refer to Section 7.10.1.1 for all the details on performing these
configurations.
4. Assign the determined boot mode definitions to indexes in your custom boot table that correlate to
the decoded value of the BMSPs. For example, BOOTDEF0=Boot to Flash, BOOTDEF1=CAN Boot,
BOOTDEF2=SCI Boot; all other BOOTDEFx are left as default/nothing). Refer to Section 7.10.1.2 for all
the details on setting up and configuring the custom boot mode table.
Additionally, the Boot Mode Example Use Cases section of the TMS320F28P55x Real-Time Microcontrollers
Technical Reference Manual provides some example use cases on how to configure the BMSPs and custom
boot tables.
Note
The CAN boot mode turns on the XTAL. Be sure an XTAL is installed in the application before using
CAN boot mode.

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7.10.1.1 Configuring Boot Mode Pins

This section explains how the boot mode select pins can be customized by the user, by programming
the BOOTPIN-CONFIG location (refer to Table 7-9) in the user-configurable dual-zone security module(DCSM) OTP. The location in the DCSM OTP is Z1-OTP-BOOTPIN-CONFIG or Z2-OTP-BOOTPIN-CONFIG.
When debugging, EMU-BOOTPIN-CONFIG is the emulation equivalent of Z1-OTP-BOOTPIN-CONFIG/Z2-OTPBOOTPIN-CONFIG, and can be programmed to experiment with different boot modes without writing to OTP.
The device can be programmed to use 0, 1, 2, or 3 boot mode select pins as needed.
Note
When using Z2-OTP-BOOTPIN-CONFIG, the configurations programmed in this location will takepriority over the configurations in Z1-OTP-BOOTPIN-CONFIG. It is recommended to use Z1-OTPBOOTPIN-CONFIG first and then if OTP configurations need to be altered, switch to using Z2-OTPBOOTPIN-CONFIG.
Table 7-9. BOOTPIN-CONFIG Bit Fields
BIT

NAME

DESCRIPTION

31:24

Key

Write 0x5A to these 8-bits to indicate the bits in this register are valid

23:16

Boot Mode Select Pin 2 (BMSP2)

Refer to BMSP0 description except for BMSP2

15:8

Boot Mode Select Pin 1 (BMSP1)

Refer to BMSP0 description except for BMSP1

Boot Mode Select Pin 0 (BMSP0)

Set to the GPIO pin to be used during boot (up to 255):- 0x0 = GPIO0- 0x01 = GPIO1- and so on
Writing 0xFF disables BMSP0 and this pin is no longer used to selectthe boot mode.

7:0

The following GPIOs cannot be used as a BMSP. If selected for a particular BMSP, the boot ROM automaticallyselects the factory default GPIO (the factory default for BMSP2 is 0xFF, which disables the BMSP).
• GPIO 20 and GPIO 21• GPIO 36 and GPIO 38• GPIO 62 to GPIO 223

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Table 7-10. Standalone Boot Mode Select Pin Decoding
BOOTPIN_CONFIG
KEY

BMSP0

BMSP1

BMSP2

REALIZED BOOT MODE!= 0x5A

Don’t Care

Don’t Care

Don’t Care

Boot as defined by the factory default BMSPs

0xFF

0xFF

0xFF

Boot as defined in the boot table for boot mode0
(All BMSPs disabled)

Valid GPIO

0xFF

0xFF

Boot as defined by the value of BMSP0(BMSP1 and BMSP2 disabled)

0xFF

Valid GPIO

0xFF

Boot as defined by the value of BMSP1(BMSP0 and BMSP2 disabled)

0xFF

0xFF

Valid GPIO

Boot as defined by the value of BMSP2(BMSP0 and BMSP1 disabled)

Valid GPIO

Valid GPIO

0xFF

Boot as defined by the values of BMSP0 and
BMSP1(BMSP2 disabled)

Valid GPIO

0xFF

Valid GPIO

Boot as defined by the values of BMSP0 and
BMSP2(BMSP1 disabled)

0xFF

Valid GPIO

Valid GPIO

Boot as defined by the values of BMSP1 andBMSP2(BMSP0 disabled)

Valid GPIO

Valid GPIO

Valid GPIO

Boot as defined by the values of BMSP0,
BMSP1, and BMSP2= 0x5A

Invalid GPIO

Valid GPIO

Valid GPIOBMSP0 is reset to the factory default BMSP0GPIOBoot as defined by the values of BMSP0,
BMSP1, and BMSP2Valid GPIO

Invalid GPIO

Valid GPIOBMSP1 is reset to the factory default BMSP1GPIOBoot as defined by the values of BMSP0,
BMSP1, and BMSP2

Invalid GPIOBMSP2 is reset to the factory default state,
which is disabled
Boot as defined by the values of BMSP0 and
BMSP1Valid GPIO

Valid GPIO

Note
When decoding the boot mode, BMSP0 is the least-significant-bit and BMSP2 is the most-significantbit of the boot table index value. It is recommended when disabling BMSPs to start with disabling
BMSP2. For example, in an instance when only using BMSP2 (BMSP1 and BMSP0 are disabled),
then only the boot table indexes of 0 and 4 will be selectable. In the instance when using only BMSP0,
then the selectable boot table indexes are 0 and 1.

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7.10.1.2 Configuring Boot Mode Table Options

This section explains how to configure the boot definition table, BOOTDEF, for the device and the associatedboot options. The 64-bit location is located in user-configurable DCSM OTP in the Z1-OTP-BOOTDEF-LOW and
Z1-OTP-BOOTDEF-HIGH locations. When debugging, EMU-BOOTDEF-LOW and EMU-BOOTDEF-HIGH are
the emulation equivalents of Z1-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH, and can be programmed
to experiment with different boot mode options without writing to OTP. The range of customization to the bootdefinition table depends on how many boot mode select pins (BMSP) are being used. For example, 0 BMSPs
equals to 1 table entry, 1 BMSP equals to 2 table entries, 2 BMSPs equals to 4 table entries, and 3 BMSPs
equals to 8 table entries. Refer to the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manualfor examples on how to set up the BOOTPIN_CONFIG and BOOTDEF values.
Note
The locations Z2-OTP-BOOTDEF-LOW and Z2-OTP-BOOTDEF-HIGH will be used instead of Z1OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH locations when Z2-OTP-BOOTPIN-CONFIG isconfigured. Refer to Configuring Boot Mode Pins for more details on BOOTPIN_CONFIG usage.
Table 7-11. BOOTDEF Bit Fields
BOOTDEF NAMEBYTEPOSITIONNAME

DESCRIPTION
Set the boot mode for index 0 of the boot table.

BOOT_DEF0

7:0

BOOT_DEF0 Mode/Options

Different boot modes and their options can include,for example, a boot mode that uses different GPIOs
for a specific bootloader or a different flash entry
point address. Any unsupported boot mode willcause the device to either go to wait boot or boot toflash.
Refer to GPIO Assignments for valid BOOTDEF
values to set in the table.

BOOT_DEF1

15:8

BOOT_DEF1 Mode/Options

BOOT_DEF2

23:16

BOOT_DEF2 Mode/Options

BOOT_DEF3

31:24

BOOT_DEF3 Mode/Options

BOOT_DEF4

39:32

BOOT_DEF4 Mode/Options

BOOT_DEF5

47:40

BOOT_DEF5 Mode/Options

BOOT_DEF6

55:48

BOOT_DEF6 Mode/Options

BOOT_DEF7

63:56

BOOT_DEF7 Mode/Options

Refer to BOOT_DEF0 description

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7.10.2 GPIO Assignments
This section details the GPIOs and boot option values used for boot mode set in the BOOT_DEF memory
location located at Z1-OTP-BOOTDEF-LOW/ Z2-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH/ Z2-OTPBOOTDEF-HIGH. Refer to Configuring Boot Mode Table Options on how to configure BOOT_DEF. Whenselecting a boot mode option, make sure to verify that the necessary pins are available in the pin mux options forthe specific device package being used.
Table 7-12. SCI Boot Options
OPTION

BOOTDEF VALUESCITXDA GPIOSCIRXDA GPIO

0 (default)

0x01

GPIO29GPIO281

0x21

GPIO16

GPIO17

2

0x41

GPIO8

GPIO9

3

0x61

GPIO2

GPIO3

4

0x81

GPIO16GPIO3OPTION

BOOTDEF VALUECANTXA GPIOCANRXA GPIO

0 (default)

0x08

GPIO4

GPIO5

1

0x28

GPIO1

GPIO0

2

0x48

GPIO13

GPIO12

Table 7-13. MCAN Boot Options

Table 7-14. CAN(MCAN in non-FD mode) Boot Options
OPTION

BOOTDEF VALUECANTXA GPIOCANRXA GPIO

0 (default)

0x02

GPIO4

GPIO5

1

0x22

GPIO1

GPIO0

2

0x42

GPIO13

GPIO12OPTION

BOOTDEF VALUE

0

0x07

GPIO0

GPIO1

1

0x27

GPIO32

GPIO33

2

0x47

GPIO5

GPIO4

Table 7-15. I2C Boot Options
SDAA GPIOSCLA GPIO

Table 7-16. RAM Boot Options
OPTION

BOOTDEF VALUERAM ENTRY POINT(ADDRESS)

00x05

0x0000 0000

Table 7-17. Flash/Secure Flash Boot Options

238

OPTION

BOOTDEF VALUEFLASH ENTRY POINT(ADDRESS)FLASH SECTOR

0 (default)

0x03

0x0008 0000

Bank0 Sector 0

1

0x23

0x0008 8000

Bank 0 Sector 32

2

0x43

0x000C 0000

Bank 2 Sector 0

3

0x63

0x000C 8000

Bank 2, Sector 32

4

0x83

0x0010 0000

Bank 4, Sector 0

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Table 7-18. LFU Flash Boot Options
OPTION

BOOTDEF VALUE

0 (default)

0x0B

1

FLASH ENTRY POINT(ADDRESS)

BANK

0x2B

0x0008 0000

Bank00x000C 0000

Bank20x0008 8000

Bank00x000C 8000

Bank2

Table 7-19. Wait Boot Options
OPTION

BOOTDEF VALUE

WATCHDOG00x04

Enabled1

0x24

Disabled

Table 7-20. SPI Boot Options
OPTION

BOOTDEF VALUESPIPICOASPIPOCIASPICLKASPISPTE

0

0x06

GPIO2

GPIO1

GPIO3

GPIO5

1

0x26

GPIO16

GPIO1

GPIO3

GPIO0

2

0x46

GPIO8

GPIO10GPIO9GPIO11

3

0x66

GPIO8

GPIO17GPIO9GPIO11

Table 7-21. Parallel Boot Options
OPTION

BOOTDEF VALUE

D0-D7 GPIO

28x(DSP) CONTROLGPIOHOST CONTROL GPIO

0 (default)

0x00

D0 - GPIO0

GPIO16

GPIO29GPIO12

GPIO13

D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7
1

0x20

D0 - GPIO0
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7

Table 7-22. USB Boot Options
OPTION

BOOTDEF VALUE

USB0 DM

USB0 DP0 (default)

0x09

GPIO23

GPIO41

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7.11 Security
Security features are enforced by the Dual Code Security Module (DCSM). The primary layer of defense is
securing the boundary of the chip, which should always be enabled. Additionally, the Dual Zone Security feature
is available to support code partitioning.
7.11.1 Securing the Boundary of the Chip
The following two features, along with authentication in the firmware update code, should be used to help toprevent unauthorized code from running on the device.
7.11.1.1 JTAGLOCK

Enabling the JTAGLOCK feature in the USER OTP disables JTAG access (for example, debug probe) toresources on the device.
7.11.1.2 Zero-pin Boot

Enabling the Zero-pin Boot option along with Flash Boot in the USER OTP blocks all pin-based external
bootloader options (for example, SCI, CAN, Parallel).
7.11.2 Dual-Zone Security
The dual-zone security mechanism offers protection for two zones: Zone 1 (Z1) and Zone 2 (Z2). The security
implementation for both zones is identical. Each zone has its own dedicated secure resource (OTP memory andsecure ROM) and allocated secure resource (LSx RAM and flash sectors).
7.11.3 Disclaimer
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNEDTO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY AND IS
WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS
AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTYPERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BECOMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORYCANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTHABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITEDTO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.

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7.12 Watchdog
The watchdog module is the same as the one on previous TMS320C2000™ microcontrollers, but with an
optional lower limit on the time between software resets of the counter. This windowed countdown is disabled bydefault, so the watchdog is fully backward-compatible.
The watchdog generates either a reset or an interrupt. It is clocked from the internal oscillator with a selectablefrequency divider.
Figure 7-4 shows the various functional blocks within the watchdog module.
WDCR.WDPRECLKDIVWDCR.WDPS

WDCR.WDDISWDCNTR

WDCLK(INTOSC1)

Overflow
WDCLK
Divider

8-bit
Watchdog
Counter

Watchdog
Prescaler

1-count
delay

SYSRSnClear
Count

WDWCR.MIN

WDKEY (7:0)
Watchdog
Key Detector
55 + AA

WDCR(WDCHK(2:0))

Good KeyOut of Window

Watchdog
WindowDetector

Bad Key
WDRSTn1

0

1
WDINTnGenerate
512-WDCLK
Output Pulse

Watchdog Time-out

SCSR.WDENINT

Figure 7-4. Windowed Watchdog

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7.13 C28x Timers
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count-down register that generates an interrupt when the counter reaches zero. The counteris decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it
is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and isconnected to INT13 of the CPU. CPU-Timer 2 is reserved for TI-RTOS. It is connected to INT14 of the CPU. If
TI-RTOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:• SYSCLK (default)• Internal zero-pin oscillator 1 (INTOSC1)• Internal zero-pin oscillator 2 (INTOSC2)• X1 (XTAL)

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7.14 Dual-Clock Comparator (DCC)
The DCC module is used for evaluating and monitoring the clock input based on a second clock, which canbe a more accurate and reliable version. This instrumentation is used to detect faults in clock source or clock
structures, thereby enhancing the system's safety metrics.
7.14.1 Features
The DCC has the following features:• Allows the application to ensure that a fixed ratio is maintained between frequencies of two clock signals.
• Supports the definition of a programmable tolerance window in terms of the number of reference clock cycles.
• Supports continuous monitoring without requiring application intervention.
• Supports a single-sequence mode for spot measurements.
• Allows the selection of a clock source for each of the counters, resulting in several specific use cases.
7.14.2 Mapping of DCCx Clock Source Inputs
Table 7-23. DCCx Clock Source0 Table
DCCxCLKSRC0[3:0]

CLOCK NAME

0x0

XTAL/X1

0x1

INTOSC1

0x2

INTOSC2

0x4

TCK

0x5

CPU1.SYSCLK

0x8

AUXCLKIN

0xC

INPUT XBAR (Output16 of input-xbar)

othersReserved

Table 7-24. DCCx Clock Source1 Table
DCCxCLKSRC1[4:0]

CLOCK NAME

0x0

PLLRAWCLK

0x2

INTOSC1

0x3

INTOSC2

0x6

CPU1.SYSCLK

0x9

Input XBAR (Output15 of the input-xbar)

0xA

AUXCLKIN

0xB

EPWMCLK

0xC

LSPCLK

0xD

ADCCLK

0xE

WDCLK

0xF

CAN0BITCLK

othersReserved

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7.15 Configurable Logic Block (CLB)The C2000 configurable logic block (CLB) is a collection of blocks that can be interconnected using software to
implement custom digital logic functions or enhance existing on-chip peripherals. The CLB is able to enhanceexisting peripherals through a set of crossbar interconnections, which provide a high level of connectivity toexisting control peripherals such as enhanced pulse width modulators (ePWM), enhanced capture modules(eCAP), and enhanced quadrature encoder pulse modules (eQEP). The crossbars also allow the CLB to beconnected to external GPIO pins. In this way, the CLB can be configured to interact with device peripherals toperform small logical functions such as comparators, or to implement custom serial data exchange protocols.
Through the CLB, functions that would otherwise be accomplished using external logic devices can now be
implemented inside the MCU.
The CLB peripheral is configured through the CLB tool. For more information on the CLB tool, available
examples, application notes and users guide, please refer to the following location in your C2000Ware for C2000
MCUs package (C2000Ware_2_00_00_03 and higher):••••C2000WARE_INSTALL_LOCATION\utilities\clb_tool\clb_syscfg\doc
CLB Tool User's Guide
Designing With the C2000™ Configurable Logic Block (CLB) Application Note
How to Migrate Custom Logic From an FPGA/CPLD to C2000™ Microcontrollers Application Note

The CLB module and its interconnections are shown in Figure 7-5.
GPIO0
to
GPIOx

Asynchronous
Synchronous
Sync. + Qual

Input X-BAR

IN P U T 1 – IN P U T 6
O t h erS o u rc es

CLBx T ILEOU T 4 /5

CLB X-BAR

CLB INPUT X-BAR

O t her
So u rc es

AU XSIG 0 – AU XSIG 7

CLB
CLB TILE1
CLB Global Signals

CELL

GPREG

IN0-7

Local
Signals

OUT 0-7.
.
.

I N P U T 1 – IN P U T 1 6

C L B T i l e O ut p ut s
I nte rs ec t o t he r
Pe r i ph eral s
O U T P U T X-BAR

CLB TILEx
CELL

GPREG

IN0-7

Local
Signals

OUT 0-7

All C LB T i l e
Ou t p u t s

CLB OUTPUT X-BARGP IO M U X

Figure 7-5. GPIO to CLB Tile Connections
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Absolute encoder protocol interfaces are now provided as Position Manager solutions in the C2000Ware
MotorControl SDK. Configuration files, application programmer interface (API), and use examples for such
solutions are provided with C2000Ware MotorControl SDK. In some solutions, the TI-configured CLB is usedwith other on-chip resources, such as the SPI port or the C28x CPU, to perform more complex functionality.

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8 Reference Design
The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all reference designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at the Select TI reference designs page.
Below is a partial list of applicable reference designs. A full listing of supported reference designs for this device,
as well as other C2000 MCUs, is maintained inside TI resource explorer.
3-kW, 180-W/in3 single-phase totem-pole bridgeless PFC reference design with 16-A max inputThis reference design demonstrates a method to control a continuous conduction mode Totem pole power factor
correction converter (PFC) using C2000™ microcontrollers. The PFC also works as inverter in grid connected(current controlled) mode. The converter is designed to support a maximum input current of 16-ARMS and peak
power of 3.6 kW.
Bidirectional 400-V/12-V DC/DC Converter Reference Design
The Bidirectional 400V-12V DC/DC Converter Reference Design is a microcontroller-based implementation of
an isolated bi-directional DC-DC converter. A phase shifted full-bridge (PSFB) with synchronous rectification
controls power flow from a 400V bus/battery to the 12V battery in step-down mode, while a push-pull stage
controls the reverse power flow from the low voltage battery to the high voltage bus/battery in boost mode.
GaN-based, 6.6-kW, bidirectional, onboard charger reference design
The PMP22650 reference design is a 6.6-kW, bidirectional, onboard charger. The design employs a two-phase
totem pole PFC and a full-bridge CLLLC converter with synchronous rectification. The CLLLC utilizes both
frequency and phase modulation to regulate the output across the required regulation range.
Bidirectional CLLLC resonant dual active bridge (DAB) reference design for HEV/EV onboard charger
CLLLC resonant DAB with bidirectional power flow capability and soft switching characteristics is an ideal
candidate for Hybrid Electric Vehicle/Electric Vehicle (HEV/EV) on-board chargers and energy storage
applications. This design illustrates control of this power topology using a C2000™ MCU in closed voltage
and closed current-loop mode.
7.4-kW on-board charger reference design with CCM totem pole PFC and CLLLC DC/DC using C2000™ MCU
TIDM-02013 is a bidirectional onboard charger reference design. The design consists of an interleaved
continuous conduction mode (CCM) totem-pole (TTPL) bridgeless power-factor correction (PFC) power stage
followed by a CLLLC DCDC power stage all controlled using a single C2000™ real-time control microcontroller(MCU), while utilizing a TI gallium nitride (GaN) power module.
48-V Three-Phase Inverter With Shunt-Based In-Line Motor Phase Current Sensing Evaluation Module
The BOOSTXL-3PHGANINV evaluation module features a 48-V/10-A three-phase GaN inverter with precisionin-line shunt-based phase current sensing for accurate control of precision drives such as servo drives.
C2000 DesignDRIVE position manager BoosterPack™ plug-in module
The PositionManager BoosterPack is a flexible low voltage platform intended for evaluating interfaces toabsolute encoders and analog sensors like resolvers and SinCos transducers. When combined with thec
DesignDRIVE Position Manager software solutions this low-cost evaluation module becomes a powerful toolfor interfacing many popular position encoder types such as EnDat, BiSS and T-format with C2000 Real-Time
Control devices. C2000 Position Manager technology integrates interfaces to the most popular digital and analog
position sensors onto C2000 Real-Time Controller, thus eliminating the need for external FPGAs for thesefunctions.
Distributed multi-axis servo drive over fast serial interface (FSI) reference design
This reference design presents an example distributed or decentralized multi-axis servo drive over Fast SerialInterface (FSI) using C2000™ real-time controllers. Multi-axis servo drives are used in many applications suchas factory automation and robots. The cost per axis, performance and ease of use are always high concerns forsuch systems. FSI is a cost-optimized and reliable high speed communication interface with low jitter that candaisy-chain multiple C2000 microcontrollers.

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10-kW, bidirectional three-phase three-level (T-type) inverter and PFC reference design
This verified reference design provides an overview on how to implement a three-level three-phase SiC based
DC:AC T-type inverter stage. Higher switching frequency of 50KHz reduces the size of magnetics for the filter
design and enables higher power density. The use of SiC MOSFETs with switching loss ensures higher DC
bus voltages of up to 1000V and lower switching losses with a peak efficiency of 99 percent. This design isconfigurable to work as a two-level or three-level inverter.
Bi-directional, dual active bridge reference design for level 3 electric vehicle charging stations
This reference design provides an overview on the implementation of a single-phase dual active bridge (DAB)
DC/DC converter. DAB topology offers advantages like soft-switching commutations, a decreased number ofdevices and high efficiency. The design is beneficial where power density, cost, weight, galvanic isolation, highvoltage conversion ratio and reliability are critical factors, making it ideal for EV charging stations and energy
storage applications. Modularity and symmetrical structure in DAB allow for stacking converters to achieve highpower throughput and facilitate a bidirectional mode of operation to support battery charging and discharging
applications.
1.6kW, bidirectional micro inverter based on GaN reference design
This reference design shows a four-input bidirectional 1.6kW GaN-based microinverter with energy storage
capability.

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9 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,generate code, and develop solutions are listed below.

9.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MCU
devices and support tools. Each TMS320 ™ MCU commercial family member has one of three prefixes: TMX,
TMP, or TMS (for example, TMS320F28P559SJ-Q1). Texas Instruments recommends two of three possible
prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX and TMDX) through fully qualified production devices
and tools (TMS and TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical specifications andmay not use production assembly flow.
TMP Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
TMS Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality andreliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type(for example, PZ).
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI
sales representative.

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Generic Part Number:

TMS

Orderable Part Number:

X

320

F28

P

559

S

J

F28

P

559

S

J

-Q1
9

R

PDT

Q1

PREFIX(A)AUTOMOTIVE AEC-Q100 QUALIFICATION

TMX (X) = experimental device
TMS (blank) = qualified device(blank) = Not AEC-Q100 qualified
Q1 = AEC-Q100 qualification

DEVICE FAMILYSHIPPING OPTIONS

320 = TMS320 MCU Family(blank) = Tray
R = Tape and Reel
CPU ARCHITECTURE
F28 = C28 CPU
PACKAGE TYPEPDT = 128-pin Thin Quad Flatpack (TQFP)PZ = 100-pin Low-profile Quad Flatpack (LQFP)PNA = 80-pin TQFP
PM = 64-pin LQFP
RSH = 56-pin Very Thin Quad Flatpack No-Lead (VQFN)SERIESP = Performance (150 MIPS to 600 MIPS)

MAJOR FAMILY (PLATFORM)
P = 30x to 69x
Industrial = Third digit is between 0 and 4
Automotive = Third digit is between 5 and 9

CORE

SPECIAL FEATURES CODE
2 = Base + 8 PWM pairs
6 = Base + CLA + CLB + USB + 12 PWM pairs + 64KB Flash
7 = Base + CLA + CLB + 12 PWM pairs + 24KB RAM
8 = Base + CLA + CLB + 12 PWM pairs
9 = Base + CLA + CLB + USB + NPU + 12 PWM pairs + 64KB Flash

S=1
MEMORYJ = 1MB Flash, 133KB RAM
G = 512KB Flash, 101KB RAM

A.

Prefix X is used in orderable part numbers.

Figure 9-1. Device Nomenclature

9.2 Markings
Figure 9-2, Figure 9-3, Figure 9-4, Figure 9-5, Figure 9-6, Figure 9-7, Figure 9-8, and Figure 9-9 show the
package symbolization. Table 9-1 lists the silicon revision codes.
YMLLLLS = Lot Trace CodeXF28P559
SJ9PDTQ$$#-YMLLLLSG4

YM = 2-digit Year/Month CodeLLLL = Assembly Lot CodeS = Assembly Site Code$$ = Wafer Fab Code (one or two characters) as applicable# = Silicon Revision CodeG4 = Green (Low Halogen and RoHS-compliant)

PackagePin 1

Figure 9-2. Package Symbolization for PDT Package – Automotive

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YMLLLLS = Lot Trace CodeXF28P559
SJ9PZQ$$#-YMLLLLSG4

YM = 2-digit Year/Month CodeLLLL = Assembly Lot CodeS = Assembly Site Code$$ = Wafer Fab Code (one or two characters) as applicable# = Silicon Revision CodeG4 = Green (Low Halogen and RoHS-compliant)

PackagePin 1

Figure 9-3. Package Symbolization for PZ Package – Automotive
YMLLLLS = Lot Trace CodeF28P550SJ9PZ$$#-YMLLLLSG4

YM = 2-digit Year/Month CodeLLLL = Assembly Lot CodeS = Assembly Site Code$$ = Wafer Fab Code (one or two characters) as applicable# = Silicon Revision CodeG4 = Green (Low Halogen and RoHS-compliant)

PackagePin 1

Figure 9-4. Package Symbolization for PZ Package – Non-Automotive
YMLLLLS = Lot Trace CodeXF28P559
SJ9PNAQ$$#-YMLLLLSG4

YM = 2-digit Year/Month CodeLLLL = Assembly Lot CodeS = Assembly Site Code$$ = Wafer Fab Code (one or two characters) as applicable# = Silicon Revision CodeG4 = Green (Low Halogen and RoHS-compliant)

PackagePin 1

Figure 9-5. Package Symbolization for PNA Package – Automotive

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YMLLLLS = Lot Trace CodeF28P550SJ9PNA$$#-YMLLLLSG4

YM = 2-digit Year/Month CodeLLLL = Assembly Lot CodeS = Assembly Site Code$$ = Wafer Fab Code (one or two characters) as applicable# = Silicon Revision CodeG4 = Green (Low Halogen and RoHS-compliant)

PackagePin 1

Figure 9-6. Package Symbolization for PNA Package – Non-Automotive
YMLLLLS = Lot Trace CodeXF28P559
SJ9PMQ$$#-YMLLLLSG4

YM = 2-digit Year/Month CodeLLLL = Assembly Lot CodeS = Assembly Site Code$$ = Wafer Fab Code (one or two characters) as applicable# = Silicon Revision CodeG4 = Green (Low Halogen and RoHS-compliant)

PackagePin 1

Figure 9-7. Package Symbolization for PM Package – Automotive
YMLLLLS = Lot Trace CodeF28P550
SJ9PM$$#-YMLLLLSG4

YM = 2-digit Year/Month CodeLLLL = Assembly Lot CodeS = Assembly Site Code$$ = Wafer Fab Code (one or two characters) as applicable# = Silicon Revision CodeG4 = Green (Low Halogen and RoHS-compliant)

PackagePin 1

Figure 9-8. Package Symbolization for PM Package – Non-Automotive

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YMLLLLS = Lot Trace CodeYM = 2-digit Year/Month CodeLLLL = Assembly Lot CodeS = Assembly Site Code$$ = Wafer Fab Code (one or two characters) as applicable# = Silicon Revision CodeF28P550
SJ9RSH$$#YMLLLLS
TI
G4

G4 = Green (Low Halogen and RoHS-compliant)
PackagePin 1

Figure 9-9. Package Symbolization for RSH Package – Non-Automotive
Table 9-1. Revision Identification
SILICON REVISION CODESILICON REVISIONREVID(1)ADDRESS: 0x5D00C

Blank

0

0x0000 0001

This silicon revision is available as TMX.

A

A

0x0000 0002

This silicon revision is available as TMS.

(1)COMMENTS

Silicon Revision ID

9.3 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performanceof the device, generate code, and develop solutions follow. To view all available tools and software for C2000™
real-time control MCUs, visit the C2000 real-time control MCUs – Design & development page.
Development Tools
TI Resource Explorer
To enhance your experience, be sure to check out the TI Resource Explorer to browse examples, libraries, anddocumentation for your applications.
Software Tools
C2000Ware for C2000 MCUs
C2000Ware for C2000™ MCUs is a cohesive set of software and documentation created to minimize
development time. It includes device-specific drivers, libraries, and peripheral examples.
DigitalPower SDK
DigitalPower SDK is a cohesive set of software infrastructure, tools, and documentation designed to minimize
C2000 MCU-based digital power system development time targeted for various AC-DC, DC-DC and DC-AC
power supply applications. The software includes firmware that runs on C2000 digital power evaluation modules(EVMs) and TI designs (TIDs), which are targeted for solar, telecom, server, electric vehicle chargers andindustrial power delivery applications. DigitalPower SDK provides all the needed resources at every stage ofdevelopment and evaluation in a digital power applications.
MotorControl SDK
MotorControl SDK is a cohesive set of software infrastructure, tools, and documentation designed to minimize
C2000 MCU-based motor control system development time targeted for various three-phase motor control
applications. The software includes firmware that runs on C2000 motor control evaluation modules (EVMs) and
TI designs (TIDs), which are targeted for industrial drive and other motor control, MotorControl SDK provides
all the needed resources at every stage of development and evaluation for high-performance motor control
applications.
Code Composer Studio™ integrated development environment (IDE)
Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers andprocessors. It comprises a suite of tools used to develop and debug embedded applications. Code Composer
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Studio is available for download across Windows®, Linux® and macOS® desktops. It can also be used in
the cloud by visiting https://dev.ti.com. Code Composer Studio includes an optimizing C/C++ compiler, sourcecode editor, project build environment, debugger, profiler and many other features. The intuitive IDE takes you
through each step of the application development flow. Familiar tools and interfaces make getting started fasterthan ever before. The desktop version of Code Composer Studio combines the advantages of the Eclipse
software framework with advanced capabilities from TI resulting in a compelling feature-rich environment. The
cloud-based Code Composer Studio leverages the Theia application framework enabling development in thecloud without needing to download and install large amounts of software.
SysConfig System configuration tool
SysConfig is a comprehensive collection of graphical utilities for configuring pins, peripherals, radios,
subsystems, and other components. SysConfig helps you manage, expose and resolve conflicts visually sothat you have more time to create differentiated applications. The tool's output includes C header and code files
that can be used with software development kit (SDK) examples or used to configure custom software. The
SysConfig tool automatically selects the pinmux settings that satisfy the entered requirements. The SysConfig
tool is delivered integrated in CCS, as a standalone installer, or can be used via the dev.ti.com cloud tools portal.
For more information about the SysConfig system configuration tool, visit the System configuration tool page.
C2000 Third-party search tool
TI has partnered with multiple companies to offer a wide range of solutions and services for TI C2000 devices.
These companies can accelerate your path to production using C2000 devices. Download this search tool toquickly browse third-party details and find the right third-party to meet your needs.
UniFlash Standalone Flash Tool
UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scriptinginterface.
ModelsVarious models are available for download from the product Design & development pages. These models
include I/O Buffer Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL)
Models. To view all available models, visit the Design tools & simulation section of the Design & development
page for each device.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,
TI has developed a variety of training resources. Utilizing the online training materials and downloadable
hands-on workshops provides an easy means for gaining a complete working knowledge of the C2000
microcontroller family. These training resources have been designed to decrease the learning curve, while
reducing development time, and accelerating product time to market. For more information on the various
training resources, visit the C2000™ real-time control MCUs – Support & training site.

9.4 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For changedetails, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateralfollows.
Note
TI is transitioning to use more inclusive terminology. Some language may be different than what you
would expect to see for certain technology areas.

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ErrataTMS320F28P55x Real-Time MCUs Silicon Errata describes known advisories on silicon and provides
workarounds.
Technical Reference Manual
TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual details the integration, theenvironment, the functional description, and the programming models for each peripheral and subsystem in
the F28P55x real-time microcontrollers.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and theassembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This Reference
Guide also describes emulation features available on these DSPs.
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline, andinstruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x
DSPs.
Tools Guides
TMS320C28x Assembly Language Tools v22.6.0.LTS User’s Guide describes the assembly language tools(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v22.6.0.LTS User’s Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Notes
The SMT & packaging application notes website lists documentation on TI’s surface mount technology (SMT)and application notes on a variety of packaging-related topics.
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetimeof TI embedded processors (EPs) under power when used in electronic systems. It is aimed at generalengineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures, and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders forserial programming a device.
The Essential Guide for Developing With C2000™ Real-Time Microcontrollers provides a deeper look into thecomponents that differentiate the C2000 Microcontroller Unit (MCU) as it pertains to Real-Time Control Systems.
Migrating Software From 8-Bit (Byte) Addressable CPUs to C28x CPU discusses common scenarios of
migrating software from 8-bit (byte) addressable CPUs to C28x CPU, and provides a guide on how to develop
application irrespective of the addressability.
The Hardware Design Guide for F2800x C2000™ Real-Time MCU Series Application Note is an essential guidefor hardware developers using C2000 devices, and helps to streamline the design process while mitigating thepotential for faulty designs. Key topics discussed include: power requirements; general-purpose input/output
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(GPIO) connections; analog inputs and ADC; clocking generation and requirements; and JTAG debugging
among many others.

9.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straightfrom the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

9.6 Trademarks
C2000™, TMS320C2000™, Code Composer Studio™, and TI E2E™ are trademarks of Texas Instruments.
Windows® is a registered trademark of Microsoft Corporation.
Linux® is a registered trademark of Linus Torvalds.
macOS® is a registered trademark of Apple Inc.
All trademarks are the property of their respective owners.

9.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handledwith appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.

9.8 Glossary
TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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10 Revision History
Changes from April 2, 2024 to September 19, 2024
Page
• This Revision History lists the changes from SPRSP85 to SPRSP85A. .................................................... 1• Global: TI is transitioning to use more inclusive terminology. Some language may be different than what you
would expect to see for certain technology areas. For SPI, all instances of legacy terminology have beenchanged to controller and peripheral. All instances of legacy pin names have been changed to: POCI
(Peripheral OUT Controller IN); PICO (Peripheral IN Controller OUT); and CS (Chip Select). For the I2C Bus
Interface, all instances of legacy terminology have been changed to controller and target. For the CAN and
LIN Interface/BUS, all instances of legacy terminology have been changed to commander and responder.
For the EtherCAT Controller, all instances of legacy terminology have been changed to MainDevice (orMDevice) and SubordinateDevice (or SubDevice)............................................................................................. 1• Global: Changed document status statement from "ADVANCE INFORMATION for preproduction products;
subject to change without notice" to "UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA"..................................................................................................................................................................1• Global: Information on the TMS320F28P550SJ device is Production Data...................................................... 1• Global: Information on the TMS320F28P559SJ-Q1, TMS320F28P559SG-Q1, and TMS320F28P550SG
devices is preview information only (not Production Data),................................................................................1• Global: Removed TMS320F28P550SD device................................................................................................. 1• Global: Changed "NNPU" to "NPU"...................................................................................................................1• Global: Changed DACB_OUT to CMP1_DACL................................................................................................ 1• Features section: Removed "Neural-Network Processing Unit (NNPU)" from "Real-time processing"features...............................................................................................................................................................1• Features section: Added Fast Serial Interface (FSI) to Communications peripherals........................................1• Features section: Changed "24 ePWM channels with 16 channels that have high-resolution capability (150ps
resolution)" to "24 ePWM channels with 12 channels that have high-resolution capability (150ps
resolution)"..........................................................................................................................................................1• Features section: Added "Neural-network Processing Unit (NPU)" features..................................................... 1• Description section: Updated applications link in "These include such applications as". Added paragraphabout Neural-network Processing Unit (NPU).................................................................................................... 3• Package Information table: Added "Preview information (not Production Data)" footnote................................. 3• Functional Block Diagram figure: Changed "24x ePWM Channels (16Ch Hi-Res Capable)" to "24x ePWM
Channels (12Ch Hi-Res Capable)".....................................................................................................................5• Device Comparison table: Added "Preview information (not Production Data)" footnote...................................7• Pin Attributes table: Changed DACB_OUT to CMP1_DACL. Added footnotes about VREFLO and VREFHI. 10• 128-pin PDT Thin Quad Flatpack (Top View) figure: Changed DACB_OUT to CMP1_DACL on Pin 29......... 10• 100-Pin PZ Low-Profile Quad Flatpack (Top View) figure: Changed DACB_OUT to CMP1_DACL on
Pin 22............................................................................................................................................................... 10• 80-Pin PNA Thin Quad Flatpack (Top View) figure: Changed DACB_OUT to CMP1_DACL on Pin 18.......... 10• 64-Pin PM Low-Profile Quad Flatpack (Top View) figure: Changed DACB_OUT to CMP1_DACL on Pin 14..10• 56-Pin RSH Very Thin Quad Flatpack No-Lead (Top View) figure: Changed DACB_OUT to CMP1_DACL on
Pin 12............................................................................................................................................................... 10• Analog Signals table: Removed DACB_OUT. Added footnotes about VREFLO and VREFHI........................ 40• Digital Inputs and Outputs on ADC Pins (AGPIOs) section: Updated section..................................................52• Absolute Maximum Ratings table: Removed reference to "Continuous clamp current per pin is ±2mA"
footnote from "Input clamp current - total for all inputs"....................................................................................67• Electrical Characteristics table: Updated IOL, ROL, and ILEAK. Added VIH (High-level input voltage GPIO23/41). Updated MIN values of VHYSTERESIS........................................................................................... 67• ESD Ratings – Commercial table: Added HBM value for 5V FS (fail-safe) pins.............................................. 68• ESD Ratings – Automotive table: Added HBM value for 5V FS (fail-safe) pins............................................... 69• System Current Consumption - VREG Enable - Internal Supply table: Updated table.................................... 71• System Current Consumption - VREG Disable - External Supply table: Updated table.................................. 71

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SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Typical Current Reduction per Disabled Peripheral table: Changed "ePWM(per)" to "ePWM (for 1 ePWM)"..75
Special Considerations for 5V Fail-Safe Pins section: Added section..............................................................78
Clocking System figure: Updated figure........................................................................................................... 93
Internal Clock Frequencies table: Added f(NPU), NPUCLK frequency............................................................... 96
Crystal Oscillator Specifications section: Removed duplicate Crystal Oscillator Electrical Characteristics
table................................................................................................................................................................ 103
RAM Specifications section: Removed RAM Parameters – F28P55xSD table..............................................108
ROM Specifications section: Changed table title from ROM Parameters – F28P55xSJ, F28P55xSG, andF28P55xSD to ROM Parameters – F28P55xSJ and F28P55xSG................................................................. 109
GPIO Electrical Data and Timing section: Updated section........................................................................... 114
Analog Subsystem Block Diagram (128-/80-/64-/56-Pin Packages) figure: Changed A1/B7/D11/DACB_OUT
to A1/B7/D11/CMP1_DACL............................................................................................................................124
Analog Subsystem Block Diagram (100-Pin Package) figure: Changed A1/B7/D11/DACB_OUT to A1/B7/D11/
CMP1_DACL..................................................................................................................................................124
CMPSS Input Mux Options table: Changed "A1, B7, D11, DACB_OUT" to "A1, B7, D11, CMP1_DACL" forHP4 and LP4.................................................................................................................................................. 124
Analog Pins and Internal Connections table: Changed "A1/B7/D11/DACB_OUT" to "A1/B7/D11/
CMP1_DACL" in Analog Group 1. Changed DACB_OUT to CMP1_DACL in Analog Group 1. ..................129
Analog Signal Descriptions table: Changed DACB_OUT to CMP1_DACL. ................................................. 132
ADC Characteristics table: Updated Offset Error, SNR, THD, ENOB, and PSRR. Added "Frequency tolerance
over temperature of the INTOSC ..." footnote. .............................................................................................. 136
ADC Performance Per Pin section: Added section........................................................................................ 139
Per-Channel Parasitic Capacitance for 128-Pin QFP table: Updated table................................................... 143
Per-Channel Parasitic Capacitance for 100-Pin QFP table: Updated table................................................... 143
Per-Channel Parasitic Capacitance for 80-Pin QFP table: Updated table..................................................... 143
Per-Channel Parasitic Capacitance for 64-Pin QFP table: Updated table..................................................... 143
Per-Channel Parasitic Capacitance for 56-Pin QFN table: Updated table..................................................... 143
Buffered Output from CMPx_DACL Electrical Characteristics table: Updated MIN and MAX values of INL..157
PGA Characteristics table: Updated table and footnotes............................................................................... 165
Overview section: Updated section................................................................................................................ 212
Functional Block Diagram figure: Changed "24x ePWM Channels (16Ch Hi-Res Capable)" to "24x ePWM
Channels (12Ch Hi-Res Capable)".................................................................................................................213
Flash Memory Map table: Updated table........................................................................................................218
Peripheral Registers Memory Map table: Updated table................................................................................220
Device Identification Registers table: Removed PARTIDH for TMS320F28P55xSD7. Added REVID for siliconrevision A........................................................................................................................................................225
Reference Design section: Updated section.................................................................................................. 246
Device Nomenclature figure: Updated figure..................................................................................................248
Package Symbolization for PDT Package – Automotive figure: Updated definition of G4............................. 249
Package Symbolization for PZ Package – Automotive figure: Updated definition of G4................................249
Package Symbolization for PZ Package – Non-Automotive figure: Updated definition of G4. Updated device
number............................................................................................................................................................249
Package Symbolization for PNA Package – Automotive figure: Updated definition of G4.............................249
Package Symbolization for PNA Package – Non-Automotive figure: Updated definition of G4. Updated device
number............................................................................................................................................................249
Package Symbolization for PM Package – Automotive figure: Updated definition of G4...............................249
Package Symbolization for PM Package – Non-Automotive figure: Updated definition of G4. Updated device
number............................................................................................................................................................249
Package Symbolization for RSH Package – Non-Automotive figure: Updated definition of G4. Updated device
number............................................................................................................................................................249
Revision Identification table: Changed REVID of Silicon Revision 0 to 0x0000 0001. Added siliconrevision A........................................................................................................................................................ 249

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•
•

258

Documentation Support section: Added Migrating Software From 8-Bit (Byte) Addressable CPUs to C28x
CPU to Application Notes section...................................................................................................................253
Documentation Support section: Added Hardware Design Guide for F2800x C2000™ Real-Time MCU Series
Application Note..............................................................................................................................................253

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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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11.1 Package Option Addendum
Packaging Information
Status(1)Package Type

Package
Drawing

Pins

Package
Qty

Eco Plan(2)Lead/Ball
Finish(6)MSL PeakTemp(3)

F28P550SJ9PDTACTIVE

TQFP

PDT

128

90

Green (RoHS &no Sb/Br)NIPDAU

Level-3260C168 HR–40 to 125

F28P550SJ9PDT

F28P550SJ9PDTRACTIVE

TQFP

PDT

128

Call TI

Green (RoHS &no Sb/Br)NIPDAU

Level-3260C168 HR–40 to 125

F28P550SJ9PDTXF28P559SJ9PDTQ1

ACTIVE

TQFP

PDT

128

90

Green (RoHS &no Sb/Br)NIPDAU

Level-3260C168 HR–40 to 125

XF28P559SJ9PDTQ

XF28P559SJ9PDTRQ1

ACTIVE

TQFP

PDT

128

Call TI

Green (RoHS &no Sb/Br)NIPDAU

Level-3260C168 HR–40 to 125

XF28P559SJ9PDTQ

F28P550SJ9PZ

ACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)NIPDAU

Level-3260C168 HR–40 to 125

F28P550SJ9PZ

F28P550SJ9PZRACTIVE

LQFP

PZ

100

1000

Green (RoHS &no Sb/Br)NIPDAU

Level-3260C168 HR–40 to 125

F28P550SJ9PZ

XF28P559SJ9PZQ1ACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)NIPDAU

Level-3260C168 HR–40 to 125

XF28P559SJ9PZQXF28P559SJ9PZRQ1ACTIVE

LQFP

PZ

100

1000

Green (RoHS &no Sb/Br)NIPDAU

Level-3260C168 HR–40 to 125

XF28P559SJ9PZQ

F28P550SJ9PNAACTIVE

TQFP

PNA

80

160

Green (RoHS &no Sb/Br)NIPDAU

Level-3260C168 HR–40 to 125

F28P550SJ9PNA

F28P550SJ9PNAR

ACTIVE

TQFP

PNA

80

1000

Green (RoHS &no Sb/Br)NIPDAU

Level-3260C168 HR–40 to 125

F28P550SJ9PNAXF28P559SJ9PNAQ1ACTIVE

TQFP

PNA

80

160

Green (RoHS &no Sb/Br)NIPDAU

Level-3260C168 HR–40 to 125

XF28P559SJ9PNAQ

XF28P559SJ9PNARQ1

ACTIVE

TQFP

PNA

80

1000

Green (RoHS &no Sb/Br)NIPDAU

Level-3260C168 HR–40 to 125

XF28P559SJ9PNAQ

F28P550SJ9PM

ACTIVE

LQFP

PM

64

160

Green (RoHS &no Sb/Br)NIPDAU

Level-3260C168 HR–40 to 125

F28P550SJ9PM

F28P550SJ9PMR

ACTIVE

LQFP

PM

64

1000

Green (RoHS &no Sb/Br)NIPDAU

Level-3260C168 HR–40 to 125

F28P550SJ9PM

XF28P559SJ9PMQ1

ACTIVE

LQFP

PM

64

160

Green (RoHS &no Sb/Br)NIPDAU

Level-3260C168 HR–40 to 125

XF28P559SJ9PMQ

XF28P559SJ9PMRQ1

ACTIVE

LQFP

PM

64

1000

Green (RoHS &no Sb/Br)NIPDAU

Level-3260C168 HR–40 to 125

XF28P559SJ9PMQ

Orderable Device

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Orderable Device
F28P550SJ9RSHRSPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

Status(1)Package Type

Package
Drawing

Pins

Package
Qty

Eco Plan(2)Lead/Ball
Finish(6)MSL PeakTemp(3)

ACTIVE

VQFN

RSH

56

2500

Green (RoHS &no Sb/Br)NIPDAU

Level-3260C168 HR

Op Temp (°C)
–40 to 125

Device Marking(4) (5)F28P550SJ9RSH(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including therequirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1%
by weight in homogeneous material).
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is acontinuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if thefinish value exceeds the maximum column width.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on
information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming
materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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TAPE AND REEL INFORMATIONREEL DIMENSIONSTAPE DIMENSIONS
K0

P1

B0 W
Reel
DiameterCavity
A0
B0
K0
W
P1

A0

Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers

Reel Width (W1)QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes

Q1

Q2

Q1

Q2

Q3

Q4

Q3

Q4

User Direction of Feed

Pocket Quadrants

All dimensions are nominal.
SPQ

Reel
Diameter(mm)

Reel
Width W1
(mm)

56

4000

330.0

16.4

64

1000

330.0

24.4

PM

64

1000

330.0

24.4

TQFP

PNA

80

1000

330.0

F28P550SJ9PNAR

TQFP

PNA

80

1000

XF28P559SJ9PZRQ1

LQFP

PZ

100

F28P550SJ9PZR

LQFP

PZ

XF28P559SJ9PDTRQ1

TQFP

F28P550SJ9PDTR

TQFPPackage
Type

Package
Drawing

Pins

F28P550SJ9RSHR

VQFN

RSH

XF28P559SJ9PMRQ1

LQFP

PM

F28P550SJ9PMR

LQFP

XF28P559SJ9PNARQ1

Device

262

B0
(mm)

K0
(mm)

P1
(mm)

W
(mm)

Pin1
Quadrant

7.3

7.3

1.1

12.0

16.0

Q2

13.0

13.0

2.1

16.0

24.0

Q2

13.0

13.0

2.1

16.0

24.0

Q2

24.4

13.0

13.0

2.1

16.0

24.0

Q2

330.0

24.4

13.0

13.0

2.1

16.0

24.0

Q2

1000

330.0

32.4

16.9

16.9

2.0

24.0

32.0

Q2

100

1000

330.0

32.4

16.9

16.9

2.0

24.0

32.0

Q2

PDT

128

1000

330.0

32.4

16.9

16.9

2.0

24.0

32.0

Q2

PDT

128

1000

330.0

32.4

16.9

16.9

2.0

24.0

32.0

Q2

Submit Document Feedback

A0
(mm)

Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TMS320F28P550SJ TMS320F28P559SJ-Q1

TMS320F28P550SJ, TMS320F28P559SJ-Q1

www.ti.com

SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)

W

L

H

All dimensions are nominal.
DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)F28P550SJ9RSHR

VQFN

RSH

56

4000

367.0

367.0

35.0

XF28P559SJ9PMRQ1

LQFP

PM

64

1000

336.6

336.6

41.3

F28P550SJ9PMR

LQFP

PM

64

1000

336.6

336.6

41.3

XF28P559SJ9PNARQ1

TQFP

PNA

80

1000

336.6

336.6

41.3

F28P550SJ9PNAR

TQFP

PNA

80

1000

336.6

336.6

41.3

XF28P559SJ9PZRQ1

LQFP

PZ

100

1000

367.0

367.0

55.0

F28P550SJ9PZR

LQFP

PZ

100

1000

367.0

367.0

55.0

XF28P559SJ9PDTRQ1

TQFP

PDT

128

1000

367.0

367.0

55.0

F28P550SJ9PDTR

TQFP

PDT

128

1000

367.0

367.0

55.0

Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TMS320F28P550SJ TMS320F28P559SJ-Q1

Submit Document Feedback

263

TMS320F28P550SJ, TMS320F28P559SJ-Q1

www.ti.com

SPRSP85A – APRIL 2024 – REVISED SEPTEMBER 2024

TRAY
L - Outer tray length without tabs

KO Outertray
height

WOuter
tray
width
Text

P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.

All dimensions are nominal.
Package
Type

Package
Name

Pins

SPQ

Unit Array
MatrixMax
Temp.
(Deg C)L (mm)W (mm)K0 (μm)

P1 (mm)

CL(mm)

CW (mm)F28P550SJ9PDT

TQFP

PDT

128

90

6 x 15

150

315

135.9

7620

15.4

20.3

21

XF28P559SJ9PDTQ1

TQFP

PDT

128

90

6 x 15

150

315

135.9

7620

15.4

20.3

21

F28P550SJ9PZ

LQFP

PZ

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

DeviceXF28P559SJ9PZQ1

LQFP

PZ

100

90

6 x 15

150

315

135.9

7620

20.3

15.4

15.4

F28P550SJ9PNA

TQFP

PNA

80

119

7 x 17

150

315

135.9

7620

17.9

14.3

13.95

XF28P559SJ9PNAQ1

TQFP

PNA

80

119

7 x 17

150

315

135.9

7620

17.9

14.3

13.95

F28P550SJ9PM

LQFP

PM

64

160

8 x 20

150

315

135.9

7620

15.2

13.1

13

XF28P559SJ9PMQ1

LQFP

PM

64

160

8 x 20

150

315

135.9

7620

15.2

13.1

13

264

Submit Document Feedback

Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TMS320F28P550SJ TMS320F28P559SJ-Q1

PACKAGE OUTLINE

PDT0128A

TQFP - 1.2 mm max height
SCALE 1.000

PLASTIC QUAD FLATPACK

14.05
13.95

PIN 1 ID

B

128

A

97

96

1

14.05
13.95

16.1
TYP
15.9

32

65
33

64

124X 0.4

0.23
0.13
0.05

128X
4X 12.4
SEE DETAIL A

C A B

1.2 MAXC(0.13) TYP

SEATING PLANE
0.08 C

0.25
GAGE PLANE

0 -5

(1)

0.05 MIN

0.75
0.45

DETAIL A
TYPICALDETAIL A
SCALE: 124215171/A 10/2023

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

PDT0128A

TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

SYMM
128

97

128X (1.45)
196
128X (0.2)

124X (0.4)(R0.05) TYP
SYMM(15.35)32

65

SEE DETAILS
64

33(15.35)LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:6X

0.05 MIN
ALL AROUND

0.05 MAXALL AROUNDEXPOSEDMETALEXPOSED
METAL
METAL

SOLDER MASKOPENINGMETAL UNDERSOLDER MASKSOLDER MASKNON SOLDER MASKDEFINEDSOLDER MASKDEFINEDSOLDER MASK DETAILS
4215171/A 10/2023

NOTES: (continued)
3. Publication IPC-7351 may have alternate designs.
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
5. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and
SLMA004 (www.ti.com/lit/slma004).

www.ti.com

EXAMPLE STENCIL DESIGNPDT0128A

TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

SYMM
97

128
128X (1.45)
196
128X (0.2)
124X (0.4)

SYMM(15.35)(R0.05) TYP

32

65

33

64
(15.35)SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCILSCALE:6X

4215171/A 10/2023

NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

www.ti.com

MECHANICAL DATAMTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996

PZ (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27
0,17

0,50
75

0,08 M

51

76

50

100

26

1

0,13 NOM

25
12,00 TYP

Gage Plane

14,20
SQ
13,80
16,20
SQ
15,80

0,05 MIN

1,45
1,35

0,25
0°– 7°

0,75
0,45
Seating Plane
0,08

1,60 MAX

4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026

POST OFFICE BOX 655303• DALLAS, TEXAS 75265

1

PACKAGE OUTLINE

PNA0080A

TQFP - 1.2 mm max height
SCALE 1.500

PLASTIC QUAD FLATPACK

10.1
9.9

PIN 1 ID

B
61

80

A

1

60

12.2
TYP
11.8
10.1
9.9

20

41

21

40
80X

76X 0.4
4X 7.6

0.21
0.15
0.05

C A B

SEE DETAIL A
1.2 MAXC(0.13) TYP

SEATING PLANE
0.08 C

0.25
GAGE PLANE

0 -5

(1)

0.15
0.05

0.7
0.5

DETAIL A
DETAIL A
SCALE: 14

TYPICAL
4229169/E 09/2024

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.

www.ti.com

EXAMPLE BOARD LAYOUT

PNA0080A

TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

SYMM
80

61

80X (1.45)

160
80X (0.2)

SYMM

76X (0.4)(11.4)(R0.05) TYP

41

20

40

21
(11.4)LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:8X
0.05 MAXALL AROUNDEXPOSED METALMETALSOLDER MASKOPENINGEXPOSED METALMETAL UNDERSOLDER MASKSOLDER MASKNON SOLDER MASKDEFINED

0.05 MIN
ALL AROUNDSOLDER MASKDEFINEDSOLDER MASK DETAILS
4229169/E 09/2024

NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
6. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).

www.ti.com

EXAMPLE STENCIL DESIGN

PNA0080A

TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

SYMM
80

61

80X (1.45)

160
80X (0.2)

SYMM

76X (0.4)(11.4)(R0.05) TYP

41

20

21

40
(11.4)SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCILSCALE:8X

4229169/E 09/2024

NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

PM0064A

LQFP - 1.6 mm max height
SCALE 1.400

PLASTIC QUAD FLATPACK64

PIN 1 ID

10.2
9.8
NOTE 3

B
49

48

1

10.2
9.8
NOTE 3

12.2
TYP
11.8

33

16

32

17

A

64X

60X 0.5
4X 7.5

0.27
0.17
0.08

C A B

C
(0.13) TYP
SEATING PLANE
0.08

SEE DETAIL A

0.25
GAGE PLANE

0 -7(1.4) 1.6 MAX

0.75
0.45

0.05 MINDETAIL A
DETAIL A
SCALE: 14

TYPICAL
4215162/A 03/2017

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-026.

www.ti.com

EXAMPLE BOARD LAYOUT

PM0064A

LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

SYMM
49

64

64X (1.5)
148
64X (0.3)

SYMM
60X (0.5)(11.4)(R0.05) TYP

33

16

17

32
(11.4)LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:8X

0.05 MAXALL AROUNDEXPOSED METALMETALSOLDER MASKOPENINGEXPOSED METALMETAL UNDERSOLDER MASKSOLDER MASKNON SOLDER MASKDEFINED

0.05 MIN
ALL AROUNDSOLDER MASKDEFINEDSOLDER MASK DETAILS
4215162/A 03/2017

NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).

www.ti.com

EXAMPLE STENCIL DESIGN

PM0064A

LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

SYMM
49

64

64X (1.5)
148
64X (0.3)

SYMM
60X (0.5)(11.4)(R0.05) TYP

16

33

32

17
(11.4)SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCILSCALE:8X

4215162/A 03/2017

NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

RSH0056GVQFN - 1 mm max height
SCALE 2.000

PLASTIC QUAD FLATPACK - NO LEAD

7.1
6.9

B

A

PIN 1 INDEX AREA
0.25
0.15

45
7.1
6.9

(0.17)(0.175)DETAIL A
A35.000

1.0
0.8

TYPICALCSEATING PLANE

0.05
0.00

0.08 C
2X 5.2SYMM

EXPOSEDTHERMAL PAD(0.1) TYP

15

28
29

14

SYMM

57

2X 5.2

5.3 0.1

1

42

52X 0.4
PIN 1 ID
(45 X 0.3)

56X
43

56
56X
SEE DETAIL A

0.65
0.45

0.225
0.125
0.1
0.05

C A B
C
4229539/B 08/2023

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RSH0056GVQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(

5.3)

SYMM
56

43

56X (0.75)

SEE SOLDER MASKDETAIL56X (0.2)
142(1.12) TYP
52X (0.4)(R0.05) TYP(1.28) TYP
57

SYMM

(6.65)( 0.2) TYP
VIA

29

14

15

28
(1.28) TYP(1.12)
TYP(6.65)LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 12X
0.05 MIN
ALL AROUND

0.05 MAXALL AROUNDMETAL UNDERSOLDER MASKMETAL EDGEEXPOSED METALSOLDER MASKOPENINGEXPOSEDMETALNON SOLDER MASKDEFINED(PREFERRED)SOLDER MASKOPENINGSOLDER MASK DEFINEDSOLDER MASK DETAILS
4229539/B 08/2023
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shownon this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RSH0056GVQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(0.64) TYP(1.28) TYP

56

43

56X (0.75)
56X (0.2)
142

52X (0.4)(1.28) TYP(0.64) TYP(6.65)

57
SYMM(R0.05) TYP
16X (1.08)
29

14

15
SYMM

16X
(1.08)

28(6.65)SOLDER PASTE EXAMPLE
BASED ON 0.100 MM THICK STENCILSCALE: 12X
EXPOSED PAD 57
66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4229539/B 08/2023

NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com

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