参考資料
MSP430FR4133, MSP430FR4132, MSP430FR4131
JAJSG11F – OCTOBER 2014 – REVISED DECEMBER 2021

MSP430FR413x ミクスト・シグナル・マイクロコントローラ
1 特長
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組み込みマイクロコントローラ– 最高 16MHz の 16 ビット RISC アーキテクチャ– 1.8V～3.6V の広い電源電圧範囲 (最小電源電圧
は SVS レベルにより制限されます。「セクション
8.12.1.1」を参照)
最適化された低消費電力モード (3V 時)– アクティブ・モード：126 µA/MHz– スタンバイ・モード：リアルタイムクロック (RTC) カウ
ンタと液晶ディスプレイ (LCD) で 1µA 未満– シャットダウン (LPM4.5)：15nA
高性能アナログ– 10 チャネル、10 ビットの A/D コンバータ (ADC)• 内蔵の 1.5V 基準電圧
• サンプル・アンド・ホールド 200ksps– 低消費電力 LCD ドライバ
• 最大 4×36 または 8×32 セグメントの LCD 構成
をサポート• オンチップ・チャージ・ポンプによりスタンバイ・モード (LPM3.5) で LCD をアクティブに維持• 各 LCD ピンはソフトウェアで SEG またはCOM に構成可能• 0.06V ステップで 2.6V～3.5V のコントラスト制
御低消費電力の強誘電体 RAM (FRAM)– 最大 15.5KB の不揮発性メモリ– エラー訂正コード (ECC) 搭載– 書き込み保護を構成可能– プログラム、定数、ストレージのユニファイド・メモリ– 書き込みサイクルの耐久性：1015 回– 放射線耐性と非磁性
インテリジェントなデジタル・ペリフェラル– IR 変調ロジック– 2 つの 16 ビット・タイマ、それぞれに 3 つのキャプ
チャ / 比較レジスタを搭載 (Timer_A3)– 1 つの 16 ビット・カウンタ専用 RTC カウンタ
– 16 ビットの巡回冗長性検査 (CRC)
拡張シリアル通信– 拡張 USCI A (eUSCI_A) により UART、IrDA、
SPI をサポート– 拡張 USCI B (eUSCI_B) により SPI および I2C を
サポート

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クロック・システム (CS)– オンチップの 32kHz RC 発振器 (REFO)– オンチップの 16MHz デジタル制御発振器(DCO)、周波数ロック・ループ (FLL) 付き• オンチップの基準電圧は室温で ±1% 精度– オンチップの超低周波数 10kHz 発振器 (VLO)– オンチップの高周波数変調発振器クロック(MODCLK)– 外付けの 32kHz 水晶発振器 (XT1)– 1～128 にプログラム可能な MCLK プリスケーラ– 1、2、4、8 にプログラム可能なプリスケーラを使って MCLK から SMCLK を生成
汎用入出力およびピン機能– 64 ピンのパッケージに 60 の I/O を搭載– 16 本の割り込みピン (P1、P2) により、MCU を
LPM からウェイクアップ可能– すべての I/O で静電容量式タッチ機能をサポート
開発ツールとソフトウェア– 開発キット (MSP-EXP430FR4133 LaunchPad™
開発キットおよび MSP‑TS430PM64D ターゲット
開発ボード)– 無償ソフトウェア (MSP430Ware™ ソフトウェア)
ファミリ・メンバー(「セクション 6」も参照)– MSP430FR4133：15KB のプログラム FRAM +512 バイトの情報 FRAM + 2KB の RAM– MSP430FR4132：8KB のプログラム FRAM + 512
バイトの情報 FRAM + 1KB の RAM– MSP430FR4131：4KB のプログラム FRAM + 512
バイトの情報 FRAM + 512B の RAM
パッケージ・オプション– 64 ピン：LQFP (PM)– 56 ピン：TSSOP (G56)– 48 ピン：TSSOP (G48)

2 アプリケーション
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リモート・コントロール
サーモスタット
水道メータ
温水メータ
ガス・メータワンタイム・パスワード・トークン
血糖値測定器血圧計

3 概要
超低消費電力 (ULP) の MSP430FR41xx マイクロコントローラ・ファミリは、リモート・コントローラ、サーモスタット、スマー
ト・メータ、血糖値測定器、血圧計など、内蔵した 10 ビット ADC を活用する低コストの LCD 機器に対応します。このMCU には強力な 16 ビット RISC CPU、16 ビット・レジスタ、および定数ジェネレータが搭載されているため、最高水準の英語版の TI 製品についての情報を翻訳したこの資料は、製品の概要を確認する目的で便宜的に提供しているものです。該当する正式な英語版の最新情報は、
www.ti.com で閲覧でき、その内容が常に優先されます。TI では翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、必ず最新版の英語版をご参照くださいますようお願いいたします。

English Data Sheet: SLAS865

MSP430FR4133, MSP430FR4132, MSP430FR4131

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JAJSG11F – OCTOBER 2014 – REVISED DECEMBER 2021

コード効率を実現できます。また、デジタル制御発振器 (DCO) により、低消費電力モードからアクティブ・モードへ 10µs
未満でウェイクアップできます。アーキテクチャに多様な低消費電力モードを組み合わせ、携帯型測定機器で長いバッテリ駆動時間を実現するように最適化されています。
MSP430™ FRAM マイクロコントローラ・プラットフォームは、独自の組み込み FRAM (強誘導体メモリ) と包括的な超低消費電力のシステム・アーキテクチャを組み合わせたものであり、システム設計において性能の向上と消費電力の削減を両立できます。FRAM テクノロジーは、RAM の低消費電力で高速な書き込み、柔軟性、耐久性と、フラッシュの不揮発性動作を併せ持つものです。
MSP430FR41x MCU は、ハードウェアおよびソフトウェアの大規模なエコシステムによってサポートされており、リファレン
ス・デザインやコード・サンプルを利用して設計をすぐに開始できます。MSP430FR41xx 用の開発キットには、MSPEXP430FR4133 LaunchPad™ 開発キットと MSP-TS430PM64D 64 ピン・ターゲット開発ボードがあります。また、テキサス・インスツルメンツは無償の MSP430Ware™ ソフトウェアも提供しており、Code Composer Studio™ IDE デスクトップのコンポーネントとして利用できます。TI Resource Explorer ではクラウド・バージョンも利用可能です。MSP430 MCU
は、テキサス・インスツルメンツのハウスキーピング・サンプル・シリーズ、MSP Academy トレーニング、TI E2E™ サポー
ト・フォーラムによるオンライン・サポートなどの豊富なオンライン資料によってもサポートされています。
モジュールの詳細な説明については、『MSP430FR4xx and MSP430FR2xx family User's Guide』(英語) を参照してく
ださい。
製品情報
部品番号(1)

本体サイズ(2)

MSP430FR4133IPM

LQFP (64)10mm×10mm

MSP430FR4133IG56

TSSOP (56)14mm×6.1mm

MSP430FR4133IG48

TSSOP (48)12.5mm×6.1mm

(1)
(2)

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パッケージ

最新の製品、パッケージ、および注文情報については、セクション 12 の「付録：パッケージ・オプション」または www.tij.co.jp のテキサス・インスツルメンツ Web サイトを参照してください。
ここに記載されているサイズは概略です。許容公差を含めたパッケージの寸法については、セクション 12の「メカニカル・データ」を参照してください。

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JAJSG11F – OCTOBER 2014 – REVISED DECEMBER 2021

4 機能ブロック図
機能ブロック図を、図 4-1 に示します。

XT1
DVCC
DVSS

Clock
SystemControl

PowerManagement
ModuleP1.x/P2.x

XOUT

XIN

RST/NMI

P3.x/P4.x

P5.x/P6.x

P7.x/P8.x

Capacitive Touch I/O
ADC

FRAM

RAM

Up to 10-ch
Single-end
10-bit200 ksps

15KB+512B
8KB+512B
4KB+512B

2KB
1KB
512B

CRC16

TA0

TA1

I/O Ports
P1, P2
2×8 IOsInterrupt
and Wakeup
PA
1×16 IOs

I/O Ports
P3, P42×8 IOsI/O Ports
P5, P62×8 IOs

PB
1×16 IOs

PC
1×16 IOs

eUSCI_B0

RTC
Counter

I/O Ports
P7, P81×8 IOs
1×4 IOsPD
1×12 IOs

MAB
16-MHZ CPU
inc.
16 Registers

MDB

EEM
TCK
TMS
TDI/TCLKTDO
SBWTCK
SBWTDIO

SYS

JTAG

SBW

Watchdog

16-bitCyclicRedundancy
Check

Timer_A
3 CC
Registers

Timer_A
3 CC
Registers

eUSCI_A0(UART,
IrDA, SPI)

16-bitReal-Time
Clock

LCD
4×36
8×32
Segments

2(SPI, I C)

LPM3.5 Domain

図 4-1. 機能ブロック図
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このデバイスには、DVCC および DVSS からなる 1 つの主電源ペアがあり、デジタルとアナログの両方のモジュールへ電力を供給します。バイパスおよびデカップリング・コンデンサとしては、それぞれ 4.7µF～10µF および 0.1µF、精度±5% が推奨されます。
P1 および P2 にはピン割り込み機能があり、LPM3.5 から MCU をウェイクアップできます。
各 Timer_A3 には 3 つの CC レジスタがありますが、外部的に接続されているのは CCR1 および CCR2 のみです。
CCR0 レジスタは、内部的な期間のタイミングと割り込みの生成にのみ使用できます。
LPM3.5 では、RTC カウンタと LCD が動作し、他のペリフェラルはオフです。
すべての I/O は、静電容量式タッチ I/O として構成可能です。

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JAJSG11F – OCTOBER 2014 – REVISED DECEMBER 2021

Table of Contents
1 特長................................................................................... 1
2 アプリケーション...................................................................1
3 概要................................................................................... 1
4 機能ブロック図.................................................................... 3
5 Revision History.............................................................. 5
6 Device Comparison......................................................... 7
6.1 Related Products........................................................ 7
7 Terminal Configuration and Functions..........................8
7.1 Pin Diagrams ............................................................. 8
7.2 Signal Descriptions................................................... 11
7.3 Pin Multiplexing.........................................................13
7.4 Connection of Unused Pins...................................... 14
8 Specifications................................................................ 15
8.1 Absolute Maximum Ratings...................................... 15
8.2 ESD Ratings............................................................. 15
8.3 Recommended Operating Conditions.......................15
8.4 Active Mode Supply Current Into VCC Excluding
External Current.......................................................... 16
8.5 Active Mode Supply Current Per MHz...................... 16
8.6 Low-Power Mode LPM0 Supply Currents IntoVCC Excluding External Current.................................. 16
8.7 Low-Power Mode LPM3, LPM4 Supply Currents(Into VCC) Excluding External Current......................... 17
8.8 Low-Power Mode LPMx.5 Supply Currents (Into
VCC) Excluding External Current................................. 18
8.9 Typical Characteristics, Low-Power Mode
Supply Currents...........................................................19
8.10 Current Consumption Per Module.......................... 20
8.11 Thermal Characteristics.......................................... 20
8.12 Timing and Switching Characteristics..................... 21

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9 Detailed Description......................................................37
9.1 CPU.......................................................................... 37
9.2 Operating Modes...................................................... 37
9.3 Interrupt Vector Addresses....................................... 38
9.4 Bootloader (BSL)...................................................... 39
9.5 JTAG Standard Interface.......................................... 39
9.6 Spy-Bi-Wire Interface (SBW).................................... 40
9.7 FRAM........................................................................40
9.8 Memory Protection....................................................40
9.9 Peripherals................................................................41
9.10 Device Descriptors (TLV)........................................ 67
9.11 Memory................................................................... 68
9.12 Identification............................................................76
10 Applications, Implementation, and Layout............... 77
10.1 Device Connection and Layout Fundamentals....... 77
10.2 Peripheral- and Interface-Specific Design
Information.................................................................. 80
10.3 Typical Applications................................................ 84
11 Device and Documentation Support..........................85
11.1 Getting Started........................................................ 85
11.2 Device Nomenclature..............................................85
11.3 Tools and Software..................................................86
11.4 Documentation Support.......................................... 88
11.5 サポート・リソース.......................................................89
11.6 Trademarks............................................................. 90
11.7 Electrostatic Discharge Caution.............................. 90
11.8 Export Control Notice.............................................. 90
11.9 Glossary.................................................................. 90
12 Mechanical, Packaging, and Orderable
Information.................................................................... 91

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5 Revision History
資料番号末尾の英字は改訂を表しています。その改訂履歴は英語版に準じています。
Changes from revision E to revision F
Changes from December 9, 2019 to December 8, 2021
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文書全体にわたって表、図、相互参照の採番方法を更新.......................................................................................1
Added セクション 10.2.3.1 Generate Accurate PWM Using Internal Oscillator .................................................83

Changes from revision D to revision E
Changes from January 22, 2019 to December 9, 2019
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Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in セク
ション 8.3, Recommended Operating Conditions ............................................................................................. 15
Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in セク
ション 8.3, Recommended Operating Conditions ............................................................................................. 15
Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in セクション 8.3,
Recommended Operating Conditions ..............................................................................................................15
Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" toセクション 8.12.3.1, XT1 Crystal Oscillator (Low Frequency) ............................................................................23
Changed the note that begins "Requires external capacitors at both terminals..." in セクション 8.12.3.1, XT1
Crystal Oscillator (Low Frequency) ..................................................................................................................23
Added the t(int) parameter in セクション 8.12.4.1, Digital Inputs ........................................................................ 26
Added the tTA,capparameter in セクション 8.12.5.1, Timer_A .............................................................................27
Corrected the test conditions for the RI,MUX parameter in セクション 8.12.7.1, ADC, Power Supply and Input
Range Conditions ............................................................................................................................................ 33
Added the note that begins "tSample = ln(2n+1) × τ ..." in セクション 8.12.7.2, ADC, 10-Bit Timing Parameters ....
33

Changes from revision C to revision D
Changes from August 30, 2018 to January 21, 2019
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ドキュメント全体を通して、「変調発振器 (MODOSC)」を「変調発振器クロック (MODCLK)」に変更........................... 1
Added "or memory corruption" in table that starts "Stresses beyond those listed..." of セクション 8.1, Absolute
Maximum Ratings ............................................................................................................................................ 15
Added note of VLO clock frequency shift in LPM3 and LPM4 mode in セクション 8.12.3.4, Internal Very-LowPower Low-Frequency Oscillator (VLO) .......................................................................................................... 24
Changed from RI to RI,MUX in セクション 8.12.7.1, ADC, Power Supply and Input Range Conditions ..............33
Added RI,Misc TYP value 34kΩ in セクション 8.12.7.1, ADC, Power Supply and Input Range Conditions ........ 33
Removed ADCDIV from the conversion time formula because ADCCLK is after division in セクション 8.12.7.2,
ADC, 10-Bit Timing Parameters ...................................................................................................................... 33
Added formula for RI calculation in セクション 8.12.7.2, ADC, 10-Bit Timing Parameters ................................ 33
Remove description of "±3°C" in table note that starts "The device descriptor structure ..." of セクション
8.12.7.3, ADC, 10-Bit Linearity Parameters .....................................................................................................34
Add "10b" for ADCSSEL bit in 表 9-6, Clock Distribution ................................................................................ 41
Added "Clock Distribution Block Diagram" in セクション 9.9.2, Clock System (CS) and Clock Distribution ......41
Corrected bitfield from IRDSEL to IRDSSEL in セクション 9.9.8, Timers (Timer0_A3, Timer1_A3), in thedescription that starts "The interconnection of Timer0_A3 and ..."................................................................... 46
Corrected the ADCINCHx column heading in 表 9-12, ADC Channel Connections ........................................48
Added word "Sensor" in 表 9-27, Device Descriptors ......................................................................................67
Added word "Sensor" in 表 9-27, Device Descriptors ......................................................................................67

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Changes from revision B to revision C
Changes from August 15, 2015 to August 29, 2018
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セクション 1「特長」、セクション 2「アプリケーション」、セクション 3「概要」に編集上の変更および追加情報................ 1
Updated セクション 6.1, Related Products .......................................................................................................... 7
Added note to VSVSH- and VSVSH+ parameters in セクション 8.12.1.1, PMM, SVS and BOR ............................21
Changed all instances of "bootstrap loader" to "bootloader"............................................................................ 39
Updates to text and figure in セクション 11.2, Device Nomenclature ................................................................ 85

Changes from revision A to revision B
Changes from December 20, 2014 to August 14, 2015
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「スタンバイ・モード」の消費電流を 770nA から 1µA に変更................................................................................... 1
Added セクション 8.2, ESD Ratings .................................................................................................................. 15
Added ILPM3.5, LCD, CP TYP values at –40°C (0.90 µA) and at 85°C (1.27 µA)..................................................18
Added the paragraph that starts "The graphs in this section..."........................................................................19
Changed all graphs in セクション 8.9, Typical Characteristics, Low-Power Mode Supply Currents, for new
measurements ................................................................................................................................................. 19
Added VREF, 1.2V parameter to セクション 8.12.1.1, PMM, SVS and BOR .........................................................21
Changed tSTE,LEAD MIN value at 2 V from 40 ns to 50 ns.................................................................................30
Changed tSTE,LEAD MIN value at 3 V from 24 ns to 45 ns.................................................................................30
Changed tVALID,SO MAX value at 2 V from 55 ns to 65 ns................................................................................ 30
Changed tVALID,SO MAX value at 3 V from 30 ns to 40 ns................................................................................ 30
Changed fADCOSC TYP value from 4.5 MHz to 5.0 MHz................................................................................... 33
In 表 9-1, Operating Modes, changed the entry for "Power Consumption at 25°C, 3 V" in AM from100 µA/MHz to 126 µA/MHz............................................................................................................................. 37
In 表 9-1, Operating Modes, added "with RTC only" to the entry for "Power Consumption at 25°C, 3 V" in
LPM3.5............................................................................................................................................................. 37
In 表 9-2, Interrupt Sources, Flags, and Vectors, removed "FRAM access time error" (ACCTEIFG) from the"System NMI" row ............................................................................................................................................38
In 表 9-8, System Module Interrupt Vector Registers, changed the interrupt event in the SYSSNIV row with a
VALUE of 06h from "ACCTEIFG access time error" to "Reserved"..................................................................43
In 表 9-27, Device Descriptors, added note to "CRC value".............................................................................67

Changes from initial release to revision A
Changes from October 3, 2014 to December 19, 2014
Page
• Moved Tstg to Absolute Maximum Ratings table and added note (3)............................................................... 15• Changed link to BSL user's guide in セクション 9.4 .......................................................................................... 39• Added note (1) to 表 9-6 .................................................................................................................................. 41• Changed the values of ADC Calibration Tag and ADC Calibration Length in the ADC Calibration row........... 67• Added Calibration Tag, Calibration Length, and 1.5-V Reference in the Reference and DCO Calibration row....
67• Added row for BSL memory to 表 9-28 ............................................................................................................68

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6 Device Comparison
表 6-1 summarizes the features of the available family members.
表 6-1. Device Comparison
DEVICE(1) (2)

PROGRAM FRAMSRAM
+ INFORMATION(BYTES)FRAM (BYTES)TA0, TA1

eUSCI_A

eUSCI_B

10-BIT ADC
CHANNELSLCD
SEGMENTS

I/O

PACKAGETYPE

MSP430FR4133IPM

15360 + 512

2048

3 × CCR(3)

1

1

10

4 × 36
8 × 3260

64 PM(LQFP)MSP430FR4132IPM

8192 + 512

1024

3 × CCR(3)

1

1

10

4 × 36
8 × 3260

64 PM(LQFP)MSP430FR4131IPM

4096 + 512

512

3 × CCR(3)

1

1

10

4 × 36
8 × 3260

64 PM(LQFP)MSP430FR4133IG56

15360 + 512

2048

3 × CCR(3)

1

1

8

4 × 30
8 × 2652

56 DGG(TSSOP56)

MSP430FR4132IG56

8192 + 512

1024

3 × CCR(3)

1

1

8

4 × 30
8 × 2652

56 DGG(TSSOP56)

MSP430FR4131IG56

4096 + 512

512

3 × CCR(3)

1

1

8

4 × 30
8 × 2652

56 DGG(TSSOP56)

MSP430FR4133IG48

15360 + 512

2048

3 × CCR(3)

1

1

8

4 × 248 × 2044

48 DGG(TSSOP48)

MSP430FR4132IG48

8192 + 512

1024

3 × CCR(3)

1

1

8

4 × 248 × 2044

48 DGG(TSSOP48)

MSP430FR4131IG48

4096 + 512

512

3 × CCR(3)

1

1

8

4 × 248 × 2044

48 DGG(TSSOP48)

(1)
(2)
(3)

For the most current device, package, and ordering information, see the Package Option Addendum in セクション 12, or see the TI
website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/
packaging.
A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM
outputs.

6.1 Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers
High-performance, low-power solutions to enable the autonomous future
Products for MSP430 ultra-low-power sensing and measurement microcontrollers
One platform. One ecosystem. Endless possibilities.
Reference designs for MSP430FR4133
Find reference designs leveraging the best in TI technology – from analog and power management to embedded
processors

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7 Terminal Configuration and Functions
7.1 Pin Diagrams

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

P7.0/L0
P7.1/L1
P7.2/L2
P7.3/L3
P7.4/L4
P7.5/L5
P7.6/L6
P7.7/L7
P3.0/L8
P3.1/L9
P3.2/L10
P3.3/L11
P3.4/L12
P3.5/L13
P3.6/L14
P3.7/L15

図 7-1 shows the pinout of the 64-pin PM package.

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

P6.0/L16
P6.1/L17
P6.2/L18
P6.3/L19
P6.4/L20
P6.5/L21
P6.6/L22
P6.7/L23
P2.0/L24
P2.1/L25
P2.2/L26
P2.3/L27
P2.4/L28
P2.5/L29
P2.6/L30
P2.7/L31

P1.7/TA0.1/TDO/A7
P1.6/TA0.2/TDI/TCLK/A6
P1.5/TA0CLK/TMS/A5
P1.4/MCLK/TCK/A4/VREF+
P1.3/UCA0STE/A3
P1.2/UCA0CLK/A2
P1.1/UCA0RXD/UCA0SOMI/A1/Veref+
P1.0/UCA0TXD/UCA0SIMO/A0/Veref–
P5.7/L39
P5.6/L38
P5.5/L37
P5.4/L36
P5.3/UCB0SOMI/UCB0SCL/L35
P5.2/UCB0SIMO/UCB0SDA/L34
P5.1/UCB0CLK/L33
P5.0/UCB0STE/L32

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

P4.7/R13
P4.6/R23
P4.5/R33
P4.4/LCDCAP1
P4.3/LCDCAP0P4.2/XOUT
P4.1/XIN
DVSS
DVCC
RST/NMI/SBWTDIOTEST/SBWTCK
P4.0/TA1.1
P8.3/TA1.2
P8.2/TA1CLK
P8.1/ACLK/A9
P8.0/SMCLK/A8

図 7-1. 64-Pin PM (LQFP) (Top View)

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図 7-2 shows the pinout of the 56-pin DGG package.

P7.5/L5
P7.4/L4
P7.3/L3
P7.2/L2
P7.1/L1
P7.0/L0
P4.7/R13
P4.6/R23
P4.5/R33
P4.4/LCDCAP1
P4.3/LCDCAP0P4.2/XOUT
P4.1/XIN
DVSS
DVCC
RST/NMI/SBWTDIOTEST/SBWTCK
P4.0/TA1.1
P8.3/TA1.2
P8.2/TA1CLK
P1.7/TA0.1/TDO/A7
P1.6/TA0.2/TDI/TCLK/A6
P1.5/TA0CLK/TMS/A5
P1.4/MCLK/TCK/A4/VREF+
P1.3/UCA0STE/A3
P1.2/UCA0CLK/A2
P1.1/UCA0RXD/UCA0SOMI/A1/Veref+
P1.0/UCA0TXD/UCA0SIMO/A0/Veref–

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

P3.0/L8
P3.1/L9
P3.2/L10
P3.3/L11
P3.4/L12
P3.5/L13
P3.6/L14
P3.7/L15
P6.0/L16
P6.1/L17
P6.2/L18
P6.3/L19
P6.4/L20
P6.5/L21
P2.0/L24
P2.1/L25
P2.2/L26
P2.3/L27
P2.4/L28
P2.5/L29
P2.6/L30
P2.7/L31
P5.0/UCB0STE/L32
P5.1/UCB0CLK/L33
P5.2/UCB0SIMO/UCB0SDA/L34
P5.3/UCB0SOMI/UCB0SCL/L35
P5.4/L36
P5.5/L37

図 7-2. 56-Pin DGG (TSSOP) (Top View)

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図 7-3 shows the pinout of the 48-pin DGG package.

P3.1/L9
P3.0/L8
P7.3/L3
P7.2/L2
P7.1/L1
P7.0/L0
P4.7/R13
P4.6/R23
P4.5/R33
P4.4/LCDCAP1
P4.3/LCDCAP0P4.2/XOUT
P4.1/XIN
DVSS
DVCC
RST/NMI/SBWTDIOTEST/SBWTCK
P4.0/TA1.1
P1.7/TA0.1/TDO/A7
P1.6/TA0.2/TDI/TCLK/A6
P1.5/TA0CLK/TMS/A5
P1.4/MCLK/TCK/A4/VREF+
P1.3/UCA0STE/A3
P1.2/UCA0CLK/A2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

P3.2/L10
P3.3/L11
P3.4/L12
P3.5/L13
P3.6/L14
P3.7/L15
P6.0/L16
P6.1/L17
P6.2/L18
P6.3/L19
P2.0/L24
P2.1/L25
P2.2/L26
P2.3/L27
P2.4/L28
P2.5/L29
P2.6/L30
P2.7/L31
P5.0/UCB0STE/L32
P5.1/UCB0CLK/L33
P5.2/UCB0SIMO/UCB0SDA/L34
P5.3/UCB0SOMI/UCB0SCL/L35
P1.0/UCA0TXD/UCA0SIMO/A0/Veref–
P1.1/UCA0RXD/UCA0SOMI/A1/Veref+

図 7-3. 48-Pin DGG (TSSOP) Designation

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7.2 Signal Descriptions
セクション 7.2 describes the signals for all device variants and package options.
表 7-1. Signal Descriptions
TERMINAL
NAME

PACKAGE SUFFIXI/O

DESCRIPTION

PM

G56

G48

P4.7/R13

1

7

7

I/O

General-purpose I/O
Input/output port of third most positive analog LCD voltage V4

P4.6/R23

2

8

8

I/O

General-purpose I/O
Input/output port of second most positive analog LCD voltage V2

P4.5/R33

3

9

9

I/O

General-purpose I/O
Input/output port of first most positive analog LCD voltage V1

P4.4/LCDCAP1

4

10

10

I/O

General-purpose I/O
LCD charge pump external port connecting to LCDCAP0 pin by 0.1‑µF
capacitor

P4.3/LCDCAP0

5

11

11

I/O

General-purpose I/O
LCD charge pump external port connecting to LCDCAP1 pin by 0.1‑µF
capacitor

P4.2/XOUT

6

12

12

I/O

General-purpose I/O
Output terminal for crystal oscillator

P4.1/XIN

7

13

13

I/O

General-purpose I/O
Input terminal for crystal oscillator

DVSS

8

14

14

Power ground

DVCC

9

15

15

Power supply

RST/NMI/SBWTDIO

10

16

16

I/O

Reset input active low
Nonmaskable interrupt input
Spy-Bi-Wire data input/output

TEST/SBWTCK

11

17

17

I

Test Mode pin – selected digital I/O on JTAG pins
Spy-Bi-Wire input clock

P4.0/TA1.1

12

18

18

I/O

General-purpose I/OTimer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs

P8.3/TA1.2(1)

13

19

–

I/O

General-purpose I/OTimer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs

P8.2/TA1CLK(1)

14

20

–

I/O

General-purpose I/OTimer clock input TACLK for TA1

P8.1/ACLK/A9(1)

15

–

–

I/O

General-purpose I/O
ACLK output
Analog input A9

P8.0/SMCLK/A8(1)

16

–

–

I/O

General-purpose I/O
SMCLK output
Analog input A8

P1.7/TA0.1/TDO/A7

17

21

19

I/O

General-purpose I/O(2)Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs
Test data output
Analog input A7

P1.6/TA0.2/TDI/TCLK/A6

18

22

20

I/O

General-purpose I/O(2)Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs
Test data input or test clock input
Analog input A6

I/O

General-purpose I/O(2)Timer clock input TACLK for TA0
Test mode selectAnalog input A5

P1.5/TA0CLK/TMS/A5

19

23

21

P1.4/MCLK/TCK/A4/VREF+

20

24

22

I/O

General-purpose I/O(2)MCLK output
Test clock
Analog input A4
Output of positive reference voltage with ground as reference

P1.3/UCA0STE/A3

21

25

23

I/O

General-purpose I/O
eUSCI_A0 SPI slave transmit enable
Analog input A3

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表 7-1. Signal Descriptions (continued)
TERMINAL
PACKAGE SUFFIX

NAME

I/O

DESCRIPTION

PM

G56

G48

P1.2/UCA0CLK/A2

22

26

24

I/O

General-purpose I/O
eUSCI_A0 SPI clock input/output
Analog input A2

P1.1/UCA0RXD/UCA0SOMI/ A1/
Veref+

23

27

25

I/O

General-purpose I/O
eUSCI_A0 UART receive data
eUSCI_A0 SPI slave out/master in
Analog input A1, and ADC positive reference

P1.0/UCA0TXD/UCA0SIMO/ A0/
Veref-

24

28

26

I/O

General-purpose I/O
eUSCI_A0 UART transmit data
eUSCI_A0 SPI slave in/master out
Analog input A0, and ADC negative reference

P5.7/L39(1)

25

–

–

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P5.6/L38(1)

26

–

–

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P5.5/L37(1)

27

29

–

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P5.4/L36(1)

28

30

–

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P5.3/UCB0SOMI/UCB0SCL/L35

29

31

27

I/O

General-purpose I/O
eUSCI_B0 SPI slave out/master in; eUSCI_B0 I2C clock
LCD drive pin; either segment or common output

P5.2/UCB0SIMO/UCB0SDA/L34

30

32

28

I/O

General-purpose I/O
eUSCI_B0 SPI slave in/master out; eUSCI_B0 I2C data
LCD drive pin; either segment or common output

P5.1/UCB0CLK/L33

31

33

29

I/O

General-purpose I/O
eUSCI_B0 clock input/output
LCD drive pin; either segment or common output

P5.0/UCB0STE/L32

32

34

30

I/O

General-purpose I/O
eUSCI_B0 slave transmit enable
LCD drive pin; either segment or common output

P2.7/L31

33

35

31

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P2.6/L30

34

36

32

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P2.5/L29

35

37

33

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P2.4/L28

36

38

34

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P2.3/L27

37

39

35

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P2.2/L26

38

40

36

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P2.1/L25

39

41

37

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P2.0/L24

40

42

38

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P6.7/L23(1)

41

–

–

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P6.6/L22(1)

42

–

–

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P6.5/L21(1)

43

43

–

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P6.4/L20(1)

44

44

–

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P6.3/L19

45

45

39

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P6.2/L18

46

46

40

I/O

General-purpose I/O
LCD drive pin; either segment or common output

12

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表 7-1. Signal Descriptions (continued)
TERMINAL
I/O

DESCRIPTION

41

I/O

General-purpose I/O
LCD drive pin; either segment or common output

48

42

I/O

General-purpose I/O
LCD drive pin; either segment or common output

49

49

43

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P3.6/L14

50

50

44

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P3.5/L13

51

51

45

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P3.4/L12

52

52

46

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P3.3/L11

53

53

47

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P3.2/L10

54

54

48

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P3.1/L9

55

55

1

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P3.0/L8

56

56

2

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P7.7/L7(1)

57

–

–

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P7.6/L6(1)

58

–

–

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P7.5/L5(1)

59

1

–

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P7.4/L4(1)

60

2

–

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P7.3/L3

61

3

3

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P7.2/L2

62

4

4

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P7.1/L1

63

5

5

I/O

General-purpose I/O
LCD drive pin; either segment or common output

P7.0/L0

64

6

6

I/O

General-purpose I/O
LCD drive pin; either segment or common output

NAME

PACKAGE SUFFIX
PM

G56

G48

P6.1/L1747

47

P6.0/L16

48

P3.7/L15(1)(2)

Any pin that is not bonded out in a smaller package must be initialized by software after reset to achieve the lowest leakage current.
Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug toprevent collisions.

7.3 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if thedevice is in test mode). For details of the settings for each pin and schematics of the multiplexed ports, see セク
ション 9.9.13.

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7.4 Connection of Unused Pins
表 7-2 shows the correct termination of unused pins.
表 7-2. Connection of Unused Pins
PIN(1)

(1)
(2)

14

POTENTIAL

COMMENT

Px.0 to Px.7

Open

Switched to port function, output direction (PxDIR.n = 1)

RST/NMI

DVCC

47-kΩ pullup or internal pullup selected with 10-nF (1.1-nF) pulldown(2)

TEST

Open

This pin always has an internal pulldown enabled.

Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
The pulldown capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like
FET interfaces or GANG programmers.

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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN

MAX

UNIT

Voltage applied at DVCC pin to VSS

–0.3

4.1

V

Voltage applied to any pin(2)–0.3

VCC + 0.3
(4.1 Max)

V

±2

mA

85

°C

125

°C

Diode current at any device pin
Maximum junction temperature, TJ
Storage temperature, Tstg (3)
(1)

(2)
(3)

–40

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage or memory corruption to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated underRecommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affectdevice reliability.
All voltages referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.

8.2 ESD Ratings
VALUE
V(ESD)(1)(2)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±1000

Charged-device model (CDM), per JEDEC specification JESD22-C101(2)

±250

UNIT
V

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as±250 V may actually have higher performance.

8.3 Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
VCC

Supply voltage applied at DVCC pin(1) (2) (3)VSS

Supply voltage applied at DVSS pin

TAOperating free-air temperature

–40

TJ

Operating junction temperature

–40

CDVCC

Recommended capacitor at DVCC(5)4.7

fSYSTEM

Processor frequency (maximum MCLK frequency)(6) (4)fACLK
fSMCLK
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)

NOM

1.8(6)

MAX

UNIT

3.6

V

85

°C

0

V
85

10

°C
µF

No FRAM wait states(NWAITSx = 0)08With FRAM wait states(NWAITSx = 1)(7)

0

16(8)

MHz

Maximum ACLK frequency

40

kHz

Maximum SMCLK frequency

16(8)

MHz

Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range. Following
the data sheet recommendation for capacitor CDVCC limits the slopes accordingly.
Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
TI recommends that power to the DVCC pin must not exceed the limits specified in Recommended Operating Conditions. Exceeding
the specified limits can cause malfunction of the device including erroneous writes to RAM and FRAM.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
A capacitor tolerance of ±20% or better is required. A low-ESR ceramic capacitor of 100 nF (minimum) should be placed as close as
possible (within a few millimeters) to the respective pin pair.
The minimum supply voltage is defined by the SVS levels. See the SVS threshold parameters in セクション 8.12.1.1.
Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executedwithout wait states.
If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system tocomply with this operating condition.

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8.4 Active Mode Supply Current Into VCC Excluding External Current
See (1)Frequency (fMCLK = fSMCLK)
1 MHz
0 WAIT STATES(NWAITSx = 0)8 MHz
0 WAIT STATES(NWAITSx = 0)

16 MHz
1 WAIT STATE(NWAITSx = 1)

EXECUTIONMEMORYTESTCONDITIONS

TYP

MAX

IAM, FRAM(0%)

FRAM
0% cache hit ratio

3 V, 25°C

504

2874

3156

3700

3 V, 85°C

516

2919

3205

IAM, FRAM(100%)

FRAM
100% cache hit ratio

3 V, 25°C

209

633

1056

3 V, 85°C

217

647

1074

RAM

3 V, 25°C

231

809

1450

PARAMETER

TYP

IAM, RAM (2)
(1)

(2)

MAX

TYP

MAX

UNIT

µA

1298

µA
µA

All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Characterized with program executing typical dataprocessing.
fACLK = 32786 Hz, fMCLK = fSMCLK = fDCO at specified frequency
Program and data entirely reside in FRAM. All execution is from FRAM.
Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM.

8.5 Active Mode Supply Current Per MHz
VCC = 3 V, TA = 25°C (unless otherwise noted)
PARAMETER
dIAM,FRAM/df(1)

Active mode current consumption per MHz,
execution from FRAM, no wait states(1)TEST CONDITIONS

TYP

UNIT

((IAM, 75% cache hit rate at 8 MHz) –(IAM, 75% cache hit rate at 1 MHz))/ 7 MHz126µA/MHzAll peripherals are turned on in default settings.

8.6 Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
VCC = 3 V, TA = 25°C (unless otherwise noted)(1) (2)
FREQUENCY (fSMCLK)PARAMETER

VCC

1 MHz
TYP

ILPM0

Low-power mode LPM0 supply current

8 MHz
MAX

TYP

16 MHz
MAX

TYP

2V

158

307

415

3V

169

318

427

(1)
(2)

All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Current for watchdog timer clocked by SMCLK included.
fACLK = 32786 Hz, fMCLK = 0 MHz, fSMCLK at specified frequency.

16

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UNIT

MAX
µA

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8.7 Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER

VCC

–40°C
TYP

25°C
MAX

85°C

TYP

MAX

TYP

1.99

3.00

MAX

UNIT

3V

1.13

1.31

2V

1.06

1.21

3V

0.92

1.00

2V

0.86

1.00

2.75

Low-power mode 3, LCD, excludes SVS(6)

3V

1.07

1.25

3.04

µA

ILPM3, RTC

Low-power mode 3, RTC, excludes SVS(7)

3V

1.08

1.25

3.04

µA

ILPM4, SVS

Low-power mode 4, includes SVS

3V

0.65

0.75

1.88

2V

0.63

0.73

1.85

ILPM4

Low-power mode 4, excludes SVS

3V

0.51

0.58

1.51

2V

0.50

0.57

1.49

ILPM3,XT1

Low-power mode 3, includes SVS(2) (3) (4)

ILPM3,VLO

Low-power mode 3, VLO, excludes SVS(5)ILPM3, LCD, CP

(1)
(2)
(3)
(4)

(5)

(6)
(7)

2.94
1.75

2.89

µA
µA

µA
µA

All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current
Not applicable for devices with HF crystal oscillator only.
Characterized with a Golledge MS1V-TK/I_32.768KHZ crystal with a load capacitance chosen to closely match the required load.
Low-power mode 3, includes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
LCD works in LPM3 if internal charge pump and VREF switch mode are enabled. LCD driver pins are configured as 4 × 36 at 32‑Hz
frame frequency with external 32768‑Hz clock source.
RTC periodically wakes up every second with external 32768‑Hz as source.

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8.8 Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER

VCC

–40°C
TYP

25°C
MAX

TYP

MAX

TYP

MAX

1.25

1.06

2.06

ILPM3.5, XT1

Low-power mode 3.5, includes SVS(1) (2) (3)(also see 図 8-3)

3V

0.71

0.77

2V

0.66

0.70

ILPM3.5, LCD, CP

Low-power mode 3.5, excludes SVS(6)

3V

0.90

0.94

3V

0.23

0.25

2V

0.20

0.20

3V

0.010

0.015

2V

0.008

0.013

ILPM4.5, SVS

Low-power mode 4.5, includes SVS(4)ILPM4.5

Low-power mode 4.5, excludes SVS(5)

(1)
(2)
(3)

(4)

(5)

(6)

18

85°C

0.95
1.27
0.375

0.32
0.073
0.060

µA
µA

0.43

0.24
0.070

UNIT

0.140

µA
µA

Not applicable for devices with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance chosen to closely match the required load.
Low-power mode 3.5, includes SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5, includes SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5, excludes SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
LCD works in LPM3.5 if the internal charge pump and VREF switch mode are enabled. The LCD driver pins are configured as 4x36 at
32‑Hz frame frequency with an external 32768‑Hz clock source.

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8.9 Typical Characteristics, Low-Power Mode Supply Currents

5

5

4.5

4.5

LPM3 Supply Current (µA)

LPM3 Supply Current (µA)

The graphs in this section show only board-level test result on a small number of samples. A MS1V-T1K crystal from MicroCrystal was populated for 32-kHz clock generation. LCD is configured in 4xCOM mode without LCD panel populated.

4
3.5
3
2.5
2
1.5
1

4
3.5
3
2.5
2
1.5
1
0.5

0.5

0

0
-40

-30

-20

-10

0

10 20 30 40
Temperature (°C)

50

LPM3
LCD on

60

70

-40

80

-20

-10

0

10 20 30 40
Temperature (°C)

50

LPM3
RTC counter on

DVCC = 3 V
SVS disabled

60

70

80

DVCC = 3 V
SVS disabled

図 8-2. LPM3 Supply Current vs Temperature

図 8-1. LPM3 Supply Current vs Temperature
3

0.5
LPM4.5 Supply Current (µA)

LPM3.5 Supply Current (µA)

-30

2.5
2
1.5
1
0.5

0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0

0
-40

-30

-20

-10

0

10 20 30 40
Temperature (°C)

LPM3.5
12.5-pF crystal on XT1

50

60

70

80

DVCC = 3 V
SVS enabled

図 8-3. LPM3.5 Supply Current vs Temperature

-40

-30

-20

-10

0

10 20 30 40
Temperature (°C)

LPM4.5

50

60

70

80

DVCC = 3 V
SVS enabled

図 8-4. LPM4.5 Supply Current vs Temperature

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8.10 Current Consumption Per Module
MODULETEST CONDITIONS

Timer_AREFERENCE CLOCK

TYP

UNIT

Module input clock

5µA/MHzeUSCI_AUART mode

Module input clock

7µA/MHzeUSCI_A

SPI mode

Module input clock

5µA/MHzeUSCI_B

SPI mode

Module input clock

5µA/MHzeUSCI_B

I2C mode, 100 kbaud

Module input clock

5µA/MHz32 kHz

85

nA

MCLK

8.5

µA/MHz

RTC
CRC

From start to end of operation

8.11 Thermal Characteristics
PARAMETER

VALUE

UNIT

θJA

Junction-to-ambient thermal resistance, still air(1)

61.7

°C/W

θJC, (TOP)Junction-to-case (top) thermal resistance(2)

25.4

°C/W

θJB

Junction-to-board thermal resistance(3)

32.7

°C/W

ΨJB

Junction-to-board thermal characterization parameter

32.4

°C/W

ΨJT

Junction-to-top thermal characterization parameter

2.5

°C/W

θJA

Junction-to-ambient thermal resistance, still air((1)

62.4

°C/W

θJC, (TOP)Junction-to-case (top) thermal resistance(2)

18.7

°C/W

θJB

Junction-to-board thermal resistance(3)

31.4

°C/W

ΨJB

Junction-to-board thermal characterization parameter

31.1

°C/W

ΨJT

Junction-to-top thermal characterization parameter

0.8

°C/W

θJA

Junction-to-ambient thermal resistance, still air((1)

68.9

°C/W

θJC, (TOP)Junction-to-case (top) thermal resistance(2)θJB

Junction-to-board thermal resistance(3)

ΨJB
ΨJT
(1)
(2)
(3)

20

LQFP-64 (PM)TSSOP-56 (DGG56)

23

°C/W

35.8

°C/W

Junction-to-board thermal characterization parameter

35.3

°C/W

Junction-to-top thermal characterization parameter

1.1

°C/W

TSSOP-48 (DGG48)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board,as specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold place test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold place fixture to control the PCB
temperature, as described in JESD51-8.

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8.12 Timing and Switching Characteristics
8.12.1 Power Supply Sequencing
図 8-5 shows the power cycle, SVS, and BOR reset conditions.
V
Power Cycle ResetV SVS+SVS Reset

BOR Reset

V SVS–

V BOR
t BOR

t

図 8-5. Power Cycle, SVS, and BOR Reset Conditions
セクション 8.12.1.1 lists the characteristics of the SVS and BOR.
8.12.1.1 PMM, SVS and BORover recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX UNIT

VBOR, safe

Safe BOR power-down level(1)0.1VtBOR, safe

Safe BOR reset delay(2)10ms

ISVSH,AM

SVSH current consumption, active mode

VCC = 3.6 V

ISVSH,LPM

SVSH current consumption, low-power modes

VCC = 3.6 V

power-down level(4)VSVSH-SVSH

VSVSH+SVSH power-up level(4)VSVSH_hys

SVSH hysteresis

tPD,SVSH, AM

SVSH propagation delay, active modetPD,SVSH, LPM

SVSH propagation delay, low-power modes

VREF, 1.2V

1.2-V REF voltage(3)

(1)
(2)
(3)
(4)

1.5
240

µA
nA

1.71

1.81

1.87

V

1.76

1.88

1.99

V

70

1.158

1.20

mV
10

µs

100

µs

1.242

V

A safe BOR can be correctly generated only if DVCC drops below this voltage before it rises.
When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches
VSVSH+.
This is a characterized result with external 1-mA load to ground from –40°C to 85°C.
For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO reference
design.

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8.12.2 Reset Timing
セクション 8.12.2.1 lists the device wake-up times.
8.12.2.1 Wake-up Times From Low-Power Modes and Resetover recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTESTCONDITIONSVCCtWAKE-UP FRAM

Additional wake-up time to activate the FRAM in
AM if previously disabled by the FRAM controller orfrom a LPM if immediate activation is selected for
wake-up(1)3V

tWAKE-UP LPM0

Wake-up time from LPM0 to active mode (1)3V

tWAKE-UP LPM3

Wake-up time from LPM3 to active mode (2)3V

tWAKE-UP LPM4

Wake-up time from LPM4 to active modetWAKE-UP LPM3.5

Wake-up time from LPM3.5 to active mode (2)tWAKE-UP LPM4.5

Wake-up time from LPM4.5 to active mode (2)tWAKE-UP-RESETtRESET
(1)
(2)

22

MIN

TYP

MAX

10

UNIT

µs
200 ns +2.5/fDCO

10

µs

3V

10

µs

3V

350

µs

SVSHE = 1

3V

350

µs

SVSHE = 0

3V

1

ms

Wake-up time from RST or BOR event to activemode (2)

3V

1

ms

Pulse duration required at RST/NMI pin to accept a
reset

3V

2

µs

The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the firstexternally observable MCLK clock edge.
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.

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8.12.3 Clock Specifications
セクション 8.12.3.1 lists the characteristics of XT1.
8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)PARAMETERTEST CONDITIONS

fXT1, LF

XT1 oscillator crystal, lowfrequency

LFXTBYPASS = 0

DCXT1, LF

XT1 oscillator LF duty cycle

Measured at MCLK,fLFXT = 32768 Hz

fXT1,SW

XT1 oscillator logic-level squarewave input frequency

LFXTBYPASS = 1(3) (4)

DCXT1, SW

LFXT oscillator logic-levelsquare-wave input duty cycle

LFXTBYPASS = 1

OALFXT

Oscillation allowance for
LF crystals (5)LFXTBYPASS = 0, LFXTDRIVE = {3},fLFXT = 32768 Hz, CL,eff = 12.5 pF

CL,effIntegrated effective load
capacitance (6)See (7)tSTART,LFXT

Start-up time (9)fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},TA = 25°C, CL,eff = 12.5 pF

fFault,LFXT

Oscillator fault frequency (10)

XTS = 0(8)

(1)

(2)
(3)
(4)
(5)

VCC

MIN

TYP

MAX

UNIT

32768
30%

Hz
70%

32768
40%

0

Hz
60%

200

kΩ

1

pF

1000

ms
3500

Hz

To improve EMI on the LFXT oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing.
When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:• For LFXTDRIVE = {0}, CL,eff = 3.7 pF.
• For LFXTDRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF.
• For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF.
• For LFXTDRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF.
(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
(7) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers.
Recommended effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF.
The PCB adds additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective
load capacitance of the selected crystal is met.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
(9) Includes startup counter of 1024 clock cycles.
(10) Frequencies above the MAX specification do not set the fault flag. Frequencies in between the MIN and MAX specification may set theflag. A static condition or stuck at fault condition sets the flag.

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8.12.3.2 DCO FLL, Frequency
Over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
FLL lock frequency, 16 MHz, 25°C
fDCO, FLLFLL lock frequency, 16 MHz, –40°C to 85°C
FLL lock frequency, 16 MHz, –40°C to 85°C

fDUTY

Duty cycle

Jittercc

Cycle-to-cycle jitter, 16 MHz

Jitterlong

Long-term jitter, 16 MHz

tFLL, lock

FLL lock time

TEST CONDITIONS

VCC

MIN

Measured at MCLK, Internal
trimmed REFO as reference

3V

–1.0%

1.0%

3V

–2.0%

2.0%

3V

–0.5%

0.5%

3V

40%

Measured at MCLK, XT1
crystal as reference

Measured at MCLK, XT1
crystal as reference

TYP

MAX

50%

3V

0.25%

3V

0.022%

3V

120

UNIT

60%

ms

セクション 8.12.3.3 lists the characteristics of the REFO.
8.12.3.3 REFO
Over recommended operating free-air temperature (unless otherwise noted)
PARAMETERIREFOTEST CONDITIONS

VCC

MIN

TYP

UNIT

TA = 25°C

REFO calibrated frequency

Measured at MCLK

3V

REFO absolute calibrated tolerance

TA = –40°C to 85°C

1.8 V to 3.6 V

REFO frequency temperature drift

Measured at MCLK(1)

3V

0.01

%/°C

dfREFO/dVCC

REFO frequency supply voltage drift

Measured at MCLK at
25°C(2)

1.8 V to 3.6 V

1

%/V

fDC

REFO duty cycle

Measured at MCLK

1.8 V to 3.6 V

tSTARTREFO startup time

40% to 60% duty cycle

fREFO
dfREFO/dT

(1)
(2)

3V

MAX

REFO oscillator current consumption

15

µA

32768
–3.5%

40%

Hz
+3.5%

50%

60%

50

µs

Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

セクション 8.12.3.4 lists the characteristics of the VLO.
8.12.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fVLO

TEST CONDITIONSVLO frequency temperature drift

MIN

TYP

MAX

UNIT

10

kHz

Measured at MCLK(1)

3V

0.5

%/°C

dfVLO/dVCC VLO frequency supply voltage drift

Measured at MCLK(2)1.8 V to 3.6 V

4%/V

fVLO,DC

Measured at MCLK

3V

(1)
(2)

Measured at MCLK

VCC
3V

dfVLO/dT

VLO frequency

Duty cycle

50%

Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

Note
The VLO clock frequency is reduced by 15% (typical) when the device switches from active mode to
LPM3 or LPM4, because the reference changes. This lower frequency is not a violation of the VLO
specifications (see セクション 8.12.3.4).

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セクション 8.12.3.5 lists the characteristics of the MODCLK.
8.12.3.5 Module Oscillator Clock (MODCLK)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER

VCC

MIN

TYP

MAX

UNIT

3V

3.8

4.8

5.8

MHz

fMODCLKMODCLK frequency

fMODCLK/dT

MODCLK frequency temperature drift

3V

0.102

%/℃

fMODCLK/dVCC

MODCLK frequency supply voltage drift

1.8 V to 3.6 V

1.02

%/V

fMODCLK,DC

Duty cycle

3V

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40%

50%

60%

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8.12.4 Digital I/Os
セクション 8.12.4.1 lists the characteristics of the digital inputs.
8.12.4.1 Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCC

MIN

2V

0.90

TYP

MAX
1.50

3V

1.35

2.25

2V

0.50

1.10

3V

0.75

1.65

2V

0.3

0.8

3V

0.4

1.2

UNIT

VIT+

Positive-going input threshold voltage

VIT–

Negative-going input threshold voltage

Vhys

Input voltage hysteresis (VIT+ – VIT–)

RPull

Pullup or pulldown resistor

For pullup: VIN = VSS
For pulldown: VIN = VCC

CI,digInput capacitance, digital only port pins

VIN = VSS or VCC

3pF

CI,anaInput capacitance, port pins with shared analog
VIN = VSS or VCC
functions5pF

Ilkg(Px.y)

High-impedance leakage current (also see (1)and (2))

2 V, 3 V–20t(int)

Ports with interrupt capability
External interrupt timing (external trigger pulse (see block diagram andduration to set interrupt flag)(3)terminal function
descriptions)

2 V, 3 V

50

(1)
(2)
(3)

20

35

50

+20

V
V
V
kΩ

nA

ns

The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor isdisabled.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).

セクション 8.12.4.2 lists the characteristics of the digital outputs.
8.12.4.2 Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER

VCC

MIN

I(OHmax) = –3 mA(1)TEST CONDITIONS

2V

1.4

2.0

I(OHmax) = –5 mA(1)

3V

2.4

3.0

I(OLmax) = 3 mA(1)

2V

0.0

0.60

= 5 mA(1)

3V

0.0

0.60

2V

16

3V

16

VOH

High-level output voltage

VOL

Low-level output voltage

fPort_CLKClock output frequency

CL = 20 pF(2)trise,digPort output rise time, digital only port pins

CL = 20 pF

tfall,digPort output fall time, digital only port pins

CL = 20 pF(1)

I(OHmax)

TYP

MAX

UNIT
V
V
MHz

2V

10

3V

7

2V

10

3V

5

ns
ns

(2)

The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage
drop specified.
The port can output frequencies at least up to the specified limit and might support higher frequencies.

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8.12.4.3 Digital I/O Typical Characteristics
10

Low-Level Output Current (mA)

Low-Level Output Current (mA)25
T A = 85°C
20

T A = 25°C

15

10

5

0

T A = 85°C
T A = 25°C

7.5

5

2.5

0
0

0.5

1
1.5
2
Low-Level Output Voltage (V)

2.5

3

0

DVCC = 3 V

0.5

0.75
1
1.25
1.5
Low-Level Output Voltage (V)

1.75

2

DVCC = 2 V

図 8-6. Typical Low-Level Output Current vs Low-Level Output
Voltage

図 8-7. Typical Low-Level Output Current vs Low-Level Output
Voltage00High-Level Output Current (mA)

High-Level Output Current (mA)

0.25

T A = 85°C
-5

T A = 25°C

-10

-15

-20

-25

T A = 85°C
T A = 25°C

-2.5

-5

-7.5

-10
0

0.5

1
1.5
2
High-Level Output Voltage (V)

2.5

3

0

DVCC = 3 V

0.25

0.5

0.75
1
1.25
1.5
High-Level Output Voltage (V)

1.75

2

DVCC = 2 V

図 8-8. Typical High-Level Output Current vs High-Level Output
Voltage

図 8-9. Typical High-Level Output Current vs High-Level Output
Voltage

8.12.5 Timer_A
セクション 8.12.5.1 lists the operating frequency of Timer_A.
8.12.5.1 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fTA

Timer_A input clock frequency

tTA,cap Timer_A capture timing

TEST CONDITIONSVCCInternal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ±10%

2 V, 3 V

All capture inputs, minimum pulse
duration required for capture

2 V, 3 V

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MIN

20

MAX

UNIT

16

MHz
ns

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8.12.6 eUSCIセクション 8.12.6.1 lists the operating conditions of the eUSCI in UART mode.
8.12.6.1 eUSCI (UART Mode) Operating Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCInternal: SMCLK, MODCLKExternal: UCLK
Duty cycle = 50% ±10%

feUSCIeUSCI input clock frequency

fBITCLKBITCLK clock frequency (equals baud rate in Mbaud)

MIN

MAX

UNIT

2 V, 3 V

16MHz

2 V, 3 V

5MHzセクション 8.12.6.2 lists the switching characteristics of the eUSCI in UART mode.
8.12.6.2 eUSCI (UART Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSVCCTYP UNITUCGLITx = 0
UART receive deglitch time (1)tt

12

UCGLITx = 1

40

2 V, 3 V

UCGLITx = 2
UCGLITx = 3

(1)

ns

68
110

Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses arecorrectly recognized their width should exceed the maximum specification of the deglitch time.

セクション 8.12.6.3 lists the operating conditions of the eUSCI in SPI master mode.
8.12.6.3 eUSCI (SPI Master Mode) Operating Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
feUSCIeUSCI input clock frequency

TEST CONDITIONSMINInternal: SMCLK, MODCLK
Duty cycle = 50% ±10%

MAX

UNIT

8

MHz

セクション 8.12.6.4 lists the switching characteristics of the eUSCI in SPI master mode.
8.12.6.4 eUSCI (SPI Master Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETERTEST CONDITIONS

VCC

MIN

MAX

UNIT

tSTE,LEAD

STE lead time, STE active to clock

UCSTEM = 1, UCMODEx = 01 or 10

1

UCxCLK
cyclestSTE,LAG

STE lag time, Last clock to STE inactive UCSTEM = 1, UCMODEx = 01 or 10

1

UCxCLK
cyclestSU,MISOMI input data setup time

tHD,MISOMI input data hold timetVALID,MO

SIMO output data valid time(2)UCLK edge to SIMO valid,
CL = 20 pF

tHD,MOSIMO output data hold time(3)CL = 20 pF

(1)
(2)

28

2V

45

3V

35

2V

0

3V

0

ns
ns

2V

20

3V

20

2V

0

3V

0

ns
ns

fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagramsin 図 8-10 and 図 8-11.
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Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the dataon the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in 図 8-10
and 図 8-11.
1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLOW/HIGHtLOW/HIGH

tSU,MI
tHD,MISOMI

tVALID,MOSIMO

図 8-10. SPI Master Mode, CKPH = 0
1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLOW/HIGHtLOW/HIGH
tSU,MI

tHD,MISOMI

tVALID,MOSIMO

図 8-11. SPI Master Mode, CKPH = 1

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セクション 8.12.6.5 lists the switching characteristics of the eUSCI in SPI slave mode.
8.12.6.5 eUSCI (SPI Slave Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETERTEST CONDITIONStSTE,LEAD

STE lead time, STE active to clocktSTE,LAG

STE lag time, Last clock to STE inactivetSTE,ACC

STE access time, STE active to SOMI data outtSTE,DIS

STE disable time, STE inactive to SOMI highimpedancetSU,SISIMO input data setup time

tHD,SISIMO input data hold timetVALID,SO

SOMI output data valid time(2)UCLK edge to SOMI valid,
CL = 20 pF

tHD,SOSOMI output data hold time (3)CL = 20 pF

(1)
(2)
(3)

30

VCC

MIN

2V

55

3V

45

2V

20

3V

20

MAX

ns
ns

2V

65

3V

40

2V

40

3V

35

2V

4

3V

4

2V

12

3V

12

3V

40

3V

5

ns

ns
65

5

ns

ns

2V
2V

UNIT

ns
ns

fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagramsin 図 8-12 and 図 8-13.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in 図 8-12
and 図 8-13.

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UCMODEx = 01
tSTE,LEAD

STEtSTE,LAGUCMODEx = 10
1/fUCxCLKCKPL = 0UCLKCKPL = 1
tSU,SIMOtLOW/HIGHtLOW/HIGHtHD,SIMOSIMO

tVALID,SOMI

tACC

tDIS

SOMI

図 8-12. SPI Slave Mode, CKPH = 0
tSTE,LAG

tSTE,LEAD
STE
1/fUCxCLKCKPL = 0UCLKCKPL = 1
tLOW/HIGHtLOW/HIGHtHD,SItSU,SISIMO

tACC

tVALID,SO

tDIS

SOMI

図 8-13. SPI Slave Mode, CKPH = 1

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セクション 8.12.6.6 lists the switching characteristics of the eUSCI in I2C mode.
8.12.6.6 eUSCI (I2C Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 図 8-14)
PARAMETERTEST CONDITIONS

feUSCIeUSCI input clock frequencyfSCL

SCL clock frequency

MIN

2 V, 3 V

tHD,STA

Hold time (repeated) STARTtSU,STA

Setup time for a repeated STARTtHD,DAT

Data hold time

tSU,DAT

Data setup time

tSU,STO

VCC

fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz

fSCL = 100 kHz

Setup time for STOPfSCL > 100 kHz

0Pulse duration of spikes suppressed by
input filter

UCGLITx = 1
UCGLITx = 2

2 V, 3 V

UCCLTOx = 2

tSU,STA

MHz

400

kHz
µs
µs

0.6

2 V, 3 V0ns

2 V, 3 V

250

ns

4.0

2 V, 3 Vµs

0.6

2 V, 3 V

50

600

25

300

12.5

150

6.3

ns

75
27
30

2 V, 3 V

UCCLTOx = 3

tHD,STA

16

4.7

2 V, 3 V

UCCLTOx = 1
Clock low time-out

UNIT

0.6

UCGLITx = 3
tTIMEOUT

MAX

4.0

UCGLITx = 0
tSP

TYP

Internal: SMCLK, MODCLKExternal: UCLK
Duty cycle = 50% ±10%ms

33

tHD,STA

tBUF

SDA
tLOW

tHIGH

tSP

SCL

tSU,DATtSU,STOtHD,DAT

図 8-14. I2C Mode Timing

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8.12.7 ADC
セクション 8.12.7.1 lists the power supply and input conditions of the ADC.
8.12.7.1 ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONS

DVCC

ADC supply voltage

V(Ax)Analog input voltage range

IADC

Operating supply current into
DVCC terminal, reference
current not included, repeatsingle-channel modefADCCLK = 5 MHz, ADCON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0, ADCDIV= 0, ADCCONSEQx = 10b

CI

Input capacitance

Only one terminal Ax can be selected at one
time from the pad to the ADC capacitor array,including wiring and pad

RI,MUX

Input MUX ON resistance

DVCC = 2 V, 0 V ≤ VAx ≤ DVCC

RI,Misc

Input miscellaneous resistance

VCC

MIN

TYP

2.0
All ADC pins

0
2V

185

3V

207

2.2 V

1.6

MAX

UNIT

3.6

V

DVCC

V
µA

2.0

pF

2

kΩ

34

kΩ

セクション 8.12.7.2 lists the timing parameters of the ADC.
8.12.7.2 ADC, 10-Bit Timing Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

For specified performance of ADC linearity
parameters

2 V to 3.6 V

0.45

5

5.5

MHz

Internal ADC oscillator(MODCLK)ADCDIV = 0, fADCCLK = fADCOSC

2 V to 3.6 V

4.5

5.0

5.5

MHz

2 V to 3.6 V

2.18

Conversion time

REFON = 0, Internal oscillator,
10 ADCCLK cycles, 10-bit mode,fADCOSC = 4.5 MHz to 5.5 MHz

fADCCLKfADCOSCtCONVERT

External fADCCLK from ACLK, MCLK, or SMCLK,ADCSSEL ≠ 0
tADCON

Turn-on settling time of
the ADCThe error in a conversion started after tADCON isless than ±0.5 LSB,
Reference and input signal already settled

tSampleSampling time

RS = 1000 Ω, RI (2) = 36000 Ω, CI = 3.5 pF,
Approximately 8 Tau (t) are required for an error ofless than ±0.5 LSB(3)

(1)
(2)
(3)

2.67
µs
(1)

2 V to 3.6 V

100
2V

1.5

3V

2.0

ns

µs

12 × 1/fADCCLKRI = RI,MUX + RI,Misc
tSample = ln(2n+1) × τ, where n = ADC resolution, τ = (RI + RS) × CI

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セクション 8.12.7.3 lists the linearity parameters of the ADC.
8.12.7.3 ADC, 10-Bit Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONS

VCC

MIN

2.4 V to
3.6 V

–2

2

Integral linearity error (8-bit mode)

2 V to
3.6 V

–2

2

Differential linearity error (10-bit mode)

2.4 V to
3.6 V

–1

1

Differential linearity error (8-bit mode)

2 V to
3.6 V

–1

1

Offset error (10-bit mode)

2.4 V to
3.6 V

–6.5

6.5

2 V to
3.6 V

–6.5

6.5

Integral linearity error (10-bit mode)
EI

VDVCC as referenceED

VDVCC as reference

EO

VDVCC as reference
Offset error (8-bit mode)
Gain error (10-bit mode)

EG
Gain error (8-bit mode)
Total unadjusted error (10-bit mode)ET

VDVCC as reference
Internal 1.5-V reference
VDVCC as reference
Internal 1.5-V reference
VDVCC as reference
Internal 1.5-V reference
VDVCC as reference

TYP

MAX

UNIT

LSB

LSB

mV

2.4 V to
3.6 V

–2.0

2.0

–3.0%

3.0%

2 V to
3.6 V

–2.0

2.0

–3.0%

3.0%

2.4 V to
3.6 V

–2.0

2.0

–3.0%

3.0%

–2.0

2.0

LSB
LSB
LSB
LSB

Internal 1.5-V reference

2 V to
3.6 V

VSENSORSee (1)ADCON = 1, INCH = 0Ch, TA = 0°C

3V

1.013

mV

TCSENSOR

See (2)ADCON = 1, INCH = 0Ch

3V

3.35

mV/°C

ADCON = 1, INCH = 0Ch, Error of
conversion result ≤ 1 LSB, AM and all
LPM above LPM33V

ADCON = 1, INCH = 0Ch, Error of
conversion result ≤ 1 LSB, LPM3

3V

Total unadjusted error (8-bit mode)tSENSOR(sample)(1)

Sample time required if channel 12 isselected(3)

–3.0%

3.0%

30
µs
100

(3)

The temperature sensor offset can vary significantly. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
The device descriptor structure contains calibration values for 30°C and 85°C for each of the available reference voltage levels. The
sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR can becomputed from the calibration values for higher accuracy.
The typical equivalent impedance of the sensor is 700 kΩ. The sample time required includes the sensor-on time tSENSOR(on).

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8.12.8 LCD Controller
セクション 8.12.8.1 lists the operating conditions of the LCD controller.
8.12.8.1 LCD Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

NOM

MAX

UNIT

1.8

3.6

V

VCC,LCD,CP en,3.6

Supply voltage range, charge
pump enabled, VLCD ≤ 3.6 V

LCDCPEN = 1, 0000 < VLCDx ≤ 1111,
LCDREFEN = 1 (charge pump enabled,
VLCD ≤ 3.6 V)

VCC,LCD,ext. bias

Supply voltage range, externalbiasing, charge pump enabled

LCDCPEN = 1, LCDREFEN = 0

1.8

3.6

V

VCC,LCD,VLCDEXT

Supply voltage range, external
LCD voltage, external biasing,charge pump disabled

LCDCPEN = 0, LCDSELVDD = 0

1.8

3.6

V

VR33

External LCD voltage at LCDCAP/
R33, external biasing, charge
LCDCPEN = 0, LCDSELVDD = 0
pump disabled

2.4

3.6

V

CLCDCAP

0.1

µF

CR33

0.1

µF

CR23

0.1

µF

0.1

µF

CR13
fLCD = 2 × mux × fFRAME with
mux = 1 (static), 2, 3, 4

fFrame

LCD frame frequency range

fACLK,in

ACLK input frequency range

CPanelPanel capacitance

32-Hz frame frequency

VR33

Analog input voltage at R33

LCDCPEN = 0, LCDSELVDD = 0,
LCDREFEN = 0

VR23,1/3bias

Analog input voltage at R23

LCDCPEN = 0, LCDSELVDD = 0,
LCDREFEN = 0

VR13,1/3bias

Analog input voltage at R13 with
1/3 biasing

VLCDREF/R13

External LCD reference voltage
applied at LCDREF/R13

LCDCPEN = 1, LCDSELVDD = 0,
LCDREFEN = 0

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16

32

64

Hz

30

32

40

kHz

8000

pF

2.4

3.6

V

1.2

2.4

V

0.0

1.2

V

1.2

V

0.8

1.0

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8.12.9 FRAM
セクション 8.12.9.1 lists the characteristics of the FRAM.
8.12.9.1 FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONSMIN

tRetention

Data retention duration

MAX

1015

Read and write endurance
TJ = 25°C

100

TJ = 70°C

40

TJ = 85°C

10

UNIT
cyclesyears

8.12.10 Emulation and Debugセクション 8.12.10.1 lists the characteristics of the JTAG and SBW interface.
8.12.10.1 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC

MIN

fSBW

Spy-Bi-Wire input frequency

PARAMETER

2 V, 3 V

0tSBW,Low

Spy-Bi-Wire low clock pulse duration

2 V, 3 V

0.028

tSBW, En

Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1)2 V, 3 V

tSBW,Rst

Spy-Bi-Wire return to normal operation time

fTCK

TCK input frequency, 4-wire JTAG (2)Rinternal

Internal pulldown resistance on TEST

(1)

2V

TYP

MAX

UNIT

10

MHz

15

µs

110

µs

15

100

µs

0

16

MHz

16

MHz

50

kΩ

3V

0

2 V, 3 V

20

35

(2)

Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying thefirst SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.

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9 Detailed Description
9.1 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register (SR),and constant generator (CG), respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.

9.2 Operating Modes
The devices have one active mode and several software-selectable low-power modes of operation. An interrupt
event can wake up the device from low-power mode LPM0 or LPM3, service the request, and restore back to the
low-power mode on return from the interrupt program. Low-power modes LPM3.5 and LPM4.5 disable the coresupply to minimize power consumption.
表 9-1. Operating Modes
MODE

Maximum System Clock
Power Consumption at 25°C, 3 V
Wake-up time
Wake-up events

Power

Clock

Core

AM

LPM0

LPM3

LPM4

LPM3.5LPM4.5ACTIVEMODE

CPU OFF

STANDBYOFF

ONLY RTC
COUNTERAND LCD

SHUTDOWN

16 MHz16 MHz40 kHz040 kHz0

126 µA/MHz

20 µA/MHz

1.2 µA

0.6 µA
without SVS

0.77 µA with
RTC only

13 nA
without SVS

N/AInstant

10 µs

10 µs

150 µs150 µsI/O

RTC Counter
I/O

I/O

N/A

All

All

Regulator

Full
Regulation

Full
Regulation

SVS

On

On

Optional

Optional

Optional

Optional

Brown Out

On

On

On

On

On

On

Partial Power Partial Power Partial Power
Down
Down
Down

Power Down

MCLK

Active

Off

Off

Off

Off

Off

SMCLK

Optional

Optional

Off

Off

Off

Off

FLL

Optional

Optional

Off

Off

Off

Off

DCO

Optional

Optional

Off

Off

Off

Off

MODCLK

Optional

Optional

Off

Off

Off

Off

REFO

Optional

Optional

Optional

Off

Off

Off

ACLK

Optional

Optional

Optional

Off

Off

Off

XT1CLK

Optional

Optional

Optional

Off

OptionalOffVLOCLK

Optional

Optional

Optional

Off

Optional

Off

CPU

On

Off

Off

Off

Off

Off

FRAM

On

On

Off

Off

Off

Off

RAM

On

On

On

On

Off

Off

Backup Memory(1)

On

On

On

On

On

Off

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表 9-1. Operating Modes (continued)
AM

LPM0

LPM3

LPM4

LPM3.5LPM4.5ACTIVEMODE

CPU OFF

STANDBYOFF

ONLY RTC
COUNTERAND LCD

SHUTDOWN

Timer0_A3

Optional

Optional

Optional

Off

Off

Off

Timer1_A3

Optional

Optional

Optional

Off

Off

Off

MODE

Peripherals

I/O

(1)

WDT

Optional

Optional

Optional

Off

Off

Off

eUSCI_A0

Optional

Optional

Off

Off

Off

Off

eUSCI_B0

Optional

Optional

Off

Off

Off

Off

CRC

Optional

Optional

Off

Off

Off

Off

ADC

Optional

Optional

Optional

Off

Off

Off

LCD

Optional

Optional

Optional

Off

OptionalOff

RTC Counter

Optional

Optional

Optional

Off

Optional

Off

General Digital Input/
OutputOn

Optional

State Held

State Held

State Held

State Held

Capacitive Touch I/O

Optional

Optional

Optional

Off

Off

Off

Backup memory contains one 32-byte register in the peripheral memory space. See 表 9-29 and 表 9-48 for its memory allocation.

9.3 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
表 9-2. Interrupt Sources, Flags, and Vectors

38

SYSTEM
INTERRUPT

WORD
ADDRESSPRIORITY

Reset

FFFEh

63, Highest

Nonmaskable

FFFCh

62

NMIIFG
OFIFG

Nonmaskable

FFFAh

61

Timer0_A3

TA0CCR0 CCIFG0

Maskable

FFF8h

60

Timer0_A3

TA0CCR1 CCIFG1, TA0CCR2
CCIFG2, TA0IFG (TA0IV)

Maskable

FFF6h

59

Timer1_A3

TA1CCR0 CCIFG0

Maskable

FFF4h

58

Timer1_A3

TA1CCR1 CCIFG1, TA1CCR2CCIFG2, TA1IFG (TA1IV)

Maskable

FFF2h

57

RTC Counter

RTCIFG

Maskable

FFF0h

56

Watchdog Timer Interval mode

WDTIFG

Maskable

FFEEh

55

eUSCI_A0 Receive or Transmit

UCTXCPTIFG, UCSTTIFG, UCRXIFG,UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)(UCA0IV))

Maskable

FFECh

54

INTERRUPT SOURCEINTERRUPT FLAG

System Reset
Power-up, Brownout, Supply Supervisor
External Reset RST
Watchdog Time-out, Key Violation
FRAM uncorrectable bit error detection
Software POR,FLL unlock error

SVSHIFGPMMRSTIFG
WDTIFGPMMPORIFG, PMMBORIFGSYSRSTIVFLLUNLOCKIFG

System NMI
Vacant Memory Access
JTAG Mailbox
FRAM bit error detection

VMAIFGJMBINIFG, JMBOUTIFG
CBDIFG, UBDIFG

User NMI
External NMI
Oscillator Fault

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表 9-2. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCEINTERRUPT FLAGSYSTEM
INTERRUPT

WORD
ADDRESSPRIORITY

eUSCI_B0 Receive or Transmit

UCB0RXIFG, UCB0TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG,UCSTPIFG, UCRXIFG0, UCTXIFG0,UCRXIFG1, UCTXIFG1, UCRXIFG2,UCTXIFG2, UCRXIFG3, UCTXIFG3,UCCNTIFG, UCBIT9IFG (I2C mode)(UCB0IV)

Maskable

FFEAh

53

ADC

ADCIFG0, ADCINIFG, ADCLOIFG,ADCHIIFG, ADCTOVIFG, ADCOVIFG(ADCIV)

Maskable

FFE8h

52

P1

P1IFG.0 to P1IFG.7 (P1IV)

Maskable

FFE6h

51

P2

P2IFG.0 to P2IFG.7 (P2IV)

Maskable

FFE4h

50

LCD

LCDBLKOFFIFG, LCDBLKONIFG,LCDFRMIFG (LCDEIV)

Maskable

FFE2h49, Lowest

Reserved

Reserved

Maskable

FFE0h to FF88h

Signatures

BSL Signature 2

0FF86hBSL Signature 1

0FF84hJTAG Signature 2

0FF82hJTAG Signature 1

0FF80h

9.4 Bootloader (BSL)
The BSL lets users program the FRAM or RAM using a UART serial interface. Access to the device memory
through the BSL is protected by an user-defined password. Use of the BSL requires four pins as shown in 表
9-3. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For acomplete description of the features of the BSL and its implementation, see the MSP430 FRAM Devices
Bootloader (BSL) User's Guide.
表 9-3. BSL Pin Requirements and Functions
DEVICE SIGNALBSL FUNCTION

RST/NMI/SBWTDIO

Entry sequence signal

TEST/SBWTCK

Entry sequence signal

P1.0

Data transmit

P1.1

Data receive

VCC

Power supply

VSS

Ground supply

9.5 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. The JTAG pin requirements are shown in
表 9-4. For further details on interfacing to development tools and device programmers, see the MSP430
Hardware Tools User's Guide. For a complete description of the features of the JTAG interface and its
implementation, see MSP430 Programming With the JTAG Interface.

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表 9-4. JTAG Pin Requirements and Function
DEVICE SIGNAL

DIRECTIONJTAG FUNCTION

P1.4/MCLK/TCK/A4/VREF+

IN

JTAG clock input

P1.5/TA0CLK/TMS/A5

IN

JTAG state control

P1.6/TA0.2/TDI/TCLK/A6

IN

JTAG data input/TCLK input

P1.7/TA0.1/TDO/A7

OUT

JTAG data output

TEST/SBWTCKIN

Enable JTAG pins

RST/NMI/SBWTDIO

IN

External reset

VCC

Power supply

VSS

Ground supply

9.6 Spy-Bi-Wire Interface (SBW)The MSP430 family supports the 2-wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with
MSP430 development tools and device programmers. 表 9-5 shows the Spy-Bi-Wire interface pin requirements.
For further details on interfacing to development tools and device programmers, see the MSP430 Hardware
Tools User's Guide.
表 9-5. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL

DIRECTION

SBW FUNCTION

TEST/SBWTCKIN

Spy-Bi-Wire clock input

RST/NMI/SBWTDIO

IN, OUT

Spy-Bi-Wire data input/output

VCC

Power supply

VSS

Ground supply

9.7 FRAMThe FRAM can be programmed using the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU.
Features of the FRAM include:•••

Byte and word access capability
Programmable wait state generation
Error correction code (ECC) generation

9.8 Memory Protection
The device features memory protection that can restrict user access and enable write protection:••

Securing the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing JTAG
and BSL signatures using the JTAG port, SBW, the BSL, or in-system by the CPU.
Write protection enabled to prevent unwanted write operation to FRAM contents by setting the control bits in
System Configuration register 0. For more detailed information, see the SYS chapter in the MSP430FR4xx
and MSP430FR2xx Family User's Guide.
Note
The FRAM is protected by default on PUC. To write to FRAM during code execution, the applicationmust first clear the corresponding PFWP or DFWP bit in System Configuration Register 0 to unprotect
the FRAM.

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9.9 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be handled
by using all instructions in the memory map. For complete module description, see the MSP430FR4xx and
MSP430FR2xx Family User's Guide.
9.9.1 Power Management Module (PMM) and On-Chip Reference Voltages
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM also
includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR) is
implemented to provide the proper internal reset signal to the device during power on and power off. The SVS
circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is available on the
primary supply.
The device contains two on-chip reference: 1.5 V for internal reference and 1.2 V for external reference.
The 1.5-V reference is internally connected to ADC channel 13. DVCC is internally connected to ADC channel
15. When DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily represent as 式 1
by using ADC sampling 1.5-V reference without any external components support.
DVCC = (1023 × 1.5 V) ÷ 1.5-V reference ADC result(1)

A 1.2-V reference voltage can be buffered and output to P1.4/MCLK/TCK/A4/VREF+, when the ADC channel 4
is selected as the function. For more detailed information, see the MSP430FR4xx and MSP430FR2xx Family
User's Guide.
9.9.2 Clock System (CS) and Clock Distribution
The clock system includes a 32-kHz crystal oscillator (XT1), an internal very low-power low-frequency oscillator(VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled oscillator (DCO) that
may use frequency-locked loop (FLL) locking with internal or external 32-kHz reference clock, and on-chip
asynchronous high-speed clock (MODCLK). The clock system is designed to target cost-effective designs withminimal external components. A fail-safe mechanism is designed for XT1. The clock system module offers thefollowing clock signals.
•••

Main Clock (MCLK): the system clock used by the CPU and all relevant peripherals accessed by the bus. All
clock sources except MODCLK can be selected as the source with a predivider of 1, 2, 4, 8, 16, 32, 64, or
128.
Sub-Main Clock (SMCLK): the subsystem clock used by the peripheral modules. SMCLK derives from the
MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.
Auxiliary Clock (ACLK): this clock is derived from the external XT1 clock or internal REFO clock up to 40 kHz.

All peripherals may have one or several clock sources depending on specific functionality. 表 9-6 shows theclock distribution used in this device.

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表 9-6. Clock Distribution
CLOCK
SOURCE
SELECT
BITS
Frequency
Range

MCLK

SMCLK

DC to
16 MHzDC to
16 MHzCPU

N/A

Default

FRAM

N/A

Default

RAM

N/A

Default

CRC

N/A

Default

I/O

N/A

Default

TA0

TASSELACLK

VLOCLK

EXTERNAL PIN

DC to 40 kHz 5 MHz ±10% DC to 40 kHz 10 kHz ±50%

10b

01b
01b

TA1

TASSEL

10b

eUSCI_A0

UCSSELx

10b or 11b

eUSCI_B0

UCSSELx

10b or 11b

WDT

WDTSSEL

00b

01b

ADC

ADCSSEL10b or 11b

01b

LCD

LCDSSEL

RTC

RTCSS

(1)

XT1CLK(1)MODCLK00b (TA0CLK pin)00b (TA1CLK pin)
01b00b (UCA0CLK pin)

01b00b (UCB0CLK pin)
10b

00b

01b
01b

00b

10b

10b

11b

To enable XT1 functionality, configure P4SEL0.1 (XIN) and P4SEL0.2 (XOUT) before configuring the Clock System registers.

CPU

FRAM

SRAM

CRC

I/O

Timer_A0

Timer_A
1

eUSCI_A0

eUSCI_
B0

WDT

10

01

LCD_E
00

01

10/11

00

ADC10
11

10

01

RTC
10

01

00

01

10/11

00

01

10/11

00

10

01

00

10

01

Clock System (CS)

00

MCLK

SMCLK
ACLK

VLOCLK
MODCLK

UB0CLK

UA0CLK

TA0CLK

TA1CLK

XT1CLK

図 9-1. Clock Distribution Block Diagram
9.9.3 General-Purpose Input/Output Port (I/O)
Up to 60 I/O ports are implemented.
• P1, P2, P3, P4, P5, P6, and P7 are full 8-bit ports; P8 has 4 bits implemented.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for P1 and P2.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
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Capacitive Touch IO functionality is supported on all pins.
Note
Configuration of digital I/Os after BOR reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance with
Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR reset, theports must be configured first and then the LOCKLPM5 bit must be cleared. For details, see theConfiguration After Reset section in the Digital I/O chapter of the MSP430FR4xx and MSP430FR2xx
Family User's Guide.

9.9.4 Watchdog Timer (WDT)The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not neededin an application, the module can be configured as interval timer and can generate interrupts at selected timeintervals.
表 9-7. WDT Clocks
WDTSSELNORMAL OPERATION(WATCHDOG AND INTERVAL TIMER
MODE)

00

SMCLK

01

ACLK

10

VLOCLK

11

VLOCLK9.9.5 System Module (SYS)The SYS module handles many of the system functions within the device. These include Power-On Reset (POR)
and Power-Up Clear (PUC) handling, NMI source selection and management, reset interrupt vector generators,
bootloader entry mechanisms, and configuration management (device descriptors). SYS also includes a dataexchange mechanism through SBW called a JTAG mailbox mail box that can be used in the application.

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表 9-8. System Module Interrupt Vector Registers
INTERRUPT VECTORREGISTERADDRESSSYSRSTIV, System Reset

015Eh

SYSSNIV, System NMI

015Ch

SYSUNIV, User NMI

015Ah

INTERRUPT EVENT

VALUE

No interrupt pending

00h

Brownout (BOR)

02h

RSTIFG RST/NMI (BOR)

04h

PMMSWBOR software BOR (BOR)

06h

LPMx.5 wakeup (BOR)

08h

Security violation (BOR)

0AhReserved

0Ch

SVSHIFG SVSH event (BOR)

0EhReserved

10h

Reserved

12h

PMMSWPOR software POR (POR)

14h

WDTIFG watchdog time-out (PUC)16h

WDTPW password violation (PUC)18h

FRCTLPW password violation (PUC)

1Ah

Uncorrectable FRAM bit error detection

1Ch

Peripheral area fetch (PUC)

1Eh

PMMPW PMM password violation (PUC)

20h

Reserved

22h

FLL unlock (PUC)

24h

Reserved

26h to 3Eh

No interrupt pending

00h

SVS low-power reset entry

02h

Uncorrectable FRAM bit error detection

04h

Reserved

06h

Reserved

08h

Reserved

0Ah

Reserved

0Ch

Reserved

0Eh

Reserved

10h

VMAIFG Vacant memory access

12h

JMBINIFG JTAG mailbox input

14h

JMBOUTIFG JTAG mailbox output

16h

Correctable FRAM bit error detection

18h

Reserved

1Ah to 1Eh

No interrupt pending

00h

NMIIFG NMI pin or SVSH event

02h

OFIFG oscillator fault

04h

Reserved

06h to 1Eh

PRIORITY

HighestLowestHighestLowestHighestLowest9.9.6 Cyclic Redundancy Check (CRC)
The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data values
and can be used for data checking purposes. The CRC generation polynomial is compliant with CRC-16-CCITT
standard of x16 + x12 + x5 + 1.

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9.9.7 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
The eUSCI modules are used for serial data communications. The eUSCI_A module supports either UART or
SPI communications. The eUSCI_B module supports either SPI or I2C communications. Additionally, eUSCI_A
supports automatic baud-rate detection and IrDA.
表 9-9. eUSCI Pin Configurations

eUSCI_A0

PIN

UART

SPI

P1.0

TXD

SIMO

P1.1

RXD

P1.2
P1.3
PIN
eUSCI_B0

SOMI
SCLK
STE

I2C

SPI

P5.0

STE

P5.1

SCLK

P5.2

SDA

SIMO

P5.3

SCL

SOMI

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9.9.8 Timers (Timer0_A3, Timer1_A3)
The Timer0_A3 and Timer1_A3 modules are 16-bit timers and counters with three capture/compare registers
each. Each can support multiple captures or compares, PWM outputs, and interval timing. Each has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of thecapture/compare registers. The CCR0 registers on both TA0 and TA1 are not externally connected and can only
be used for hardware period timing and interrupt generation. In Up Mode, they can be used to set the overflow
value of the counter.
表 9-10. Timer0_A3 Signal Connections
PORT PIN
P1.5

DEVICE INPUTSIGNAL

MODULE INPUTNAME

TA0CLKTACLK

ACLK (internal)

ACLK

SMCLK (internal)

SMCLK

from Capacitive
Touch IO (internal)

INCLK

MODULE BLOCKMODULE OUTPUT
SIGNAL

Timer

N/A

CCR0

TA0

DEVICE OUTPUT
SIGNAL

CCI0A
CCI0B
DVSS
P1.7

P1.6

46

Timer1_A3 CCI0B
input

GND

DVCC

VCC

TA0.1

CCI1A

from RTC (internal)

CCI1B

TA0.1
CCR1

TA1

Timer1_A3 CCI1B
input

DVSS

GND

DVCC

VCC

TA0.2

CCI2A

TA0.2

from Capacitive
Touch I/O (internal)

CCI2B

Timer1_A3 INCLK
Timer1_A3 CCI2B
input,IR Input

DVSS

GND

DVCC

VCC

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CCR2

TA2

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表 9-11. Timer1_A3 Signal Connections
PORT PIN
P8.2

DEVICE INPUTSIGNAL

MODULE INPUT
NAME

TA1CLKTACLK

ACLK (internal)

ACLK

SMCLK (internal)

SMCLK

Timer0_A3 CCR2B
output (internal)

INCLK

MODULE BLOCKMODULE OUTPUT
SIGNAL

Timer

N/A

CCR0

TA0

DEVICE OUTPUT
SIGNAL

CCI0A

P4.0

P8.3

Timer0_A3 CCR0B
output (internal)

CCI0B

DVSS

GND

DVCC

VCC

TA1.1

CCI1A

Timer0_A3 CCR1B
output (internal)

CCI1B

DVSS

GND

DVCC

VCC

TA1.2

CCI2A

Timer0_A3 CCR2B
output (internal)

CCI2B

DVSS

GND

DVCC

VCC

TA1.1
CCR1

TA1

to ADC trigger

TA1.2
CCR2

TA2

IR Input

The interconnection of Timer0_A3 and Timer1_A3 can be used to modulate the eUSCI_A pin of UCA0TXD/
UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated infrared command for
directly driving an external IR diode. The IR functions are fully controlled by SYS configuration registers 1
including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select), IRDSSEL (data select), and IRDATA(data) bits. For more information, see the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family User's
Guide.

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9.9.9 Real-Time Clock (RTC) Counter
The RTC counter is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, and LPM3.5. This module
may periodically wake up the CPU from LPM0, LPM3, and LPM3.5 based on timing from a low-power clock
source such as the XT1 and VLO clocks. In AM, RTC can be driven by SMCLK to generate high-frequency
timing events and interrupts. The RTC overflow events trigger:• Timer0_A3 CCR1B• ADC conversion trigger when ADCSHSx bits are set as 01b
9.9.10 10-Bit Analog Digital Converter (ADC)
The 10-bit ADC module supports fast 10-bit analog-to-digital conversions with single-ended input. The module
implements a 10-bit SAR core, sample select control, reference generator and a conversion result buffer. A
window comparator with a lower and upper limit allows CPU independent result monitoring with three window
comparator interrupt flags.
The ADC supports 10 external inputs and four internal inputs (see 表 9-12).
表 9-12. ADC Channel Connections

(1)
(2)

ADCINCHx

ADC CHANNELS

EXTERNAL PIN OUT

0

A0/Veref–P1.0

1A1/Veref+

P1.1

2

A2

P1.2

3

A3

P1.3

4

A4(2)

P1.4

5

A5

P1.5

6

A6

P1.6

7

A7

P1.7

8

A8

P8.0(1)

9A9P8.1(1)

10

Not Used

N/A

11

Not Used

N/A

12

On-chip Temperature Sensor

N/A

13

Reference Voltage (1.5 V)

N/A

14

DVSS

N/A

15

DVCC

N/A

P8.0 and P8.1 are only available in the LQFP-64 package.
When A4 is used, the PMM 1.2-V reference voltage can be output to this pin by setting the PMM
control register. The 1.2-V voltage can be directly measured by A4 channel.

The AD conversion can be started by software or a hardware trigger. 表 9-13 shows the trigger sources that areavailable.
表 9-13. ADC Trigger Signal Connections
ADCSHSx

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TRIGGER SOURCE

BinaryDecimal00

0

ADCSC bit (software trigger)

01

1

RTC event10

2

TA1.1B

113

TA1.2B

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9.9.11 Liquid Crystal Display (LCD)
The LCD driver generates the segment and common signals to drive segment liquid crystal display (LCD) glass.
The LCD controller has dedicated data memories to hold segment drive information. Common and segment
signals are generated as defined by the mode. Static, 2-mux, 3-mux, up to 8-mux LCDs are supported. The
module can provide an LCD voltage independent from the main supply voltage with its integrated charge pump.
The LCD display contrast can be trimmed by setting the LCD drive voltage. The LCD module can be fully
functional in any power mode from AM to LPM3.5.
When supplied by the on-chip charge pump with on-chip regulator reference, the LCD driver needs five pins andfour external 0.1-µF capacitors to achieve low-power consumption during operation. 図 9-2 shows therecommended connections.

R13

R23

R33

0.1 μF0.1 μF0.1 μF0.1 μFLCDCAP1

LCDCAP0

図 9-2. LCD Power Supply Configuration With On-Chip Charge Pump and Regulator Reference
The LCD contains 20 16-bit words (40 bytes) display memory. The use of memory is flexible, depending on theselected mode:••

4-mux mode
– LCDM0 to LCDM19 can be used for LCD display contents. If it is not used as LCD drive pin, thecorresponding LCDMx can be used for user data (up to 20 bytes).
– LCDBM0 to LCDBM19 can be used for LCD blinking contents. If it is not used as blinking, thecorresponding LCDBMx can be used for user data (up to 20 bytes).
8-mux mode
– LCDM0 to LCDM39 can be used for LCD display contents. If it is not used as LCD drive pin, thecorresponding LCDMx can be used for user data (up to 40 bytes).

9.9.12 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The EEM on these devices has the following features:
•
•
•
•
•

Three hardware triggers or breakpoints on memory access
One hardware trigger or breakpoint on CPU register write access
Up to four hardware triggers can be combined to form complex triggers or breakpoints
One cycle counter
Clock control on module level

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9.9.13 Input/Output Schematics
9.9.13.1 Port P1 Input/Output With Schmitt Trigger
図 9-3 shows the port schematic. 表 9-14 summarizes the selection of the pin functions.

A0 to A7

From ADC A
P1REN.x
P1DIR.x0

From Module

1

DVSS

0

DVCC

1

P1OUT.x0

From Module

1

P1SEL0.x
END

To module
P1IN.xP1IE.xP1 Interrupt

Q

DS

P1IFG.x
Edge
SelectP1IES.x
From JTAGBus
Keeper
P1.0/UCA0TXD/UCA0SIMO/A0
P1.1/UCA0RXD/UCA0SOMI/A1
P1.2/UCA0CLK/A2
P1.3/UCA0STE/A3
P1.4/MCLK/TCK/A4/VREF+
P1.5/TA0CLK/TMS/A5
P1.6/TA0.2/TDI/TCLK/A6
P1.7/TA0.1/TDO/A7

To JTAG

図 9-3. Port P1 Input/Output With Schmitt Trigger

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表 9-14. Port P1 Pin Functions
PIN NAME (P1.x)

x

FUNCTION
P1.0 (I/O)

P1.0/UCA0TXD/
UCA0SIMO/A0

0 UCA0TXD/UCA0SIMO
A0
P1.1 (I/O)

P1.1/UCA0RXD/
UCA0SOMI/A1

1 UCA0RXD/UCA0SOMI
A1

P1.2/UCA0CLK/A2

(1)
(2)

0

0

N/A

X

1

0

N/A

X

X

1 (x = 0)

N/A

I: 0; O: 1

0

0

N/A

X

1

0

N/A

1 (x = 1)

N/A

0

0

N/A

2 UCA0CLK

X

1

0

N/A

X

X

1 (x = 2)

N/A

P1.3 (I/O)

I: 0; O: 1

0

0

N/A

3 UCA0STE

X

1

0

N/A

X

X

1 (x = 3)

N/A

I: 0; O: 100

Disabled

10

DisabledXX

1 (x = 4)

Disabled

JTAG TCK

X

X

X

TCK

P1.5 (I/O)

I: 0; O: 100

Disabled

TA0CLK0

1

0

Disabled

VSS

0

4 MCLK

1

5 VSS

1

A5

X

X

1 (x = 5)

Disabled

JTAG TMS

X

X

X

TMS

P1.6 (I/O)

I: 0; O: 100

Disabled

TA0.CCI2A0

1

0

Disabled

6 TA0.2

1

A6

X

X

1 (x = 6)

Disabled

JTAG TDI/TCLK

P1.7/TA0.1/TDO/A7

JTAG

I: 0; O: 1

X

A4, VREF+

P1.6/TA0.2/TDI/TCLK/ A6

ADCPCTLx(1)X

P1.4 (I/O)

P1.5/TA0CLK/TMS/A5

P1SEL0.x

I: 0; O: 1

A3

P1.4/MCLK/TCK/A4/
VREF+

P1DIR.x

P1.2 (I/O)
A2
P1.3/UCA0STE/A3

CONTROL BITS AND SIGNALS(2)

X

X

X

TDI/TCLK

P1.7 (I/O)

I: 0; O: 100

Disabled

TA0.CCI1A0

10

Disabled

7 TA0.1

1

A7

X

X

1 (x = 7)

Disabled

JTAG TDO

X

X

X

TDO

Setting the ADCPCTLx bit in SYSCFG2 register will disable both the output driver and input Schmitt trigger to prevent leakage when
analog signals are applied.
X = don't care

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9.9.13.2 Port P2 Input/Output With Schmitt Trigger
図 9-4 shows the port schematic. 表 9-15 summarizes the selection of the pin functions.

L24 to L31

From LCDP2REN.x
P2DIR.x

DVSS

0

DVCC

1

P2OUT.x

P2IN.xP2IE.xP2 Interrupt
Q

DS

P2IFG.x
1
P2IES.x

Edge
Select1

Bus
Keeper
P2.0/L24
P2.1/L25
P2.2/L26
P2.3/L27
P2.4/L28
P2.5/L29
P2.6/L30
P2.7/L31

図 9-4. Port P2 Input/Output With Schmitt Trigger

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表 9-15. Port P2 Pin Functions
PIN NAME (P2.x)
P2.0/L24
P2.1/L25
P2.2/L26

x

CONTROL BITS AND SIGNALS(1)P2DIR.x

LCDSy

I: 0; O: 1

0

L24

X

1 (y = 24)

1 P2.1 (I/O)

I: 0; O: 10

0

P2.0 (I/O)

L25
2

P2.3/L27

3

P2.4/L28

4

P2.5/L29

5

P2.6/L30

6

P2.7/L31

7(1)

FUNCTION

P2.2 (I/O)
L26
P2.3 (I/O)
L27
P2.4 (I/O)
L28
P2.5 (I/O)
L29
P2.6 (I/O)
L30
P2.7 (I/O)
L31

X

1 (y = 25)

I: 0; O: 10X

1 (y = 26)

I: 0; O: 10X

1 (y = 27)

I: 0; O: 10X

1 (y = 28)

I: 0; O: 10X

1 (y = 29)

I: 0; O: 10X

1 (y = 30)

I: 0; O: 10X

1 (y = 31)

X= don't care

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9.9.13.3 Port P3 Input/Output With Schmitt Trigger
図 9-5 shows the port schematic. 表 9-16 summarizes the selection of the pin functions.

L8 to L15

From LCD E
P3REN.x
P3DIR.x

DVSS

0

DVCC

1

P3OUT.x

P3IN.xBus
Keeper
P3.0/L8
P3.1/L9
P3.2/L10
P3.3/L11
P3.4/L12
P3.5/L13
P3.6/L14
P3.7/L15

図 9-5. Port P3 Input/Output With Schmitt Trigger

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表 9-16. Port P3 Pin Functions
PIN NAME (P3.x)
P3.0/L8
P3.1/L9
P3.2/L10x0
1
2

P3.3/L11

3

P3.4/L12

4

P3.5/L13

5

P3.6/L14

6

P3.7/L15

7(1)

FUNCTION
P3.0 (I/O)
L8
P3.1 (I/O)
L9
P3.2 (I/O)
L10
P3.3 (I/O)
L11
P3.4 (I/O)
L12
P3.5 (I/O)
L13
P3.6 (I/O)
L14
P3.7 (I/O)
L15

CONTROL BITS AND SIGNALS(1)P3DIR.x

LCDSy

I: 0; O: 10X

1 (y = 8)

I: 0; O: 10X

1 (y = 9)

I: 0; O: 10X

1 (y = 10)

I: 0; O: 10X

1 (y = 11)

I: 0; O: 10X

1 (y = 12)

I: 0; O: 10X

1 (y = 13)

I: 0; O: 10X

1 (y = 14)

I: 0; O: 10X

1 (y = 15)

X= don't care

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9.9.13.4 Port P4.0 Input/Output With Schmitt Trigger
図 9-6 shows the port schematic. 表 9-17 summarizes the selection of the pin functions.
P4REN.x
P4DIR.x0

From Module

1

DVSS

0

DVCC

1

P4OUT.x0

From Module

1

P4SEL0.x
END

To module
P4IN.xBus
Keeper
P4.0/TA1.1

図 9-6. Port P4.0 Input/Output With Schmitt Trigger
表 9-17. Port P4.0 Pin Functions
PIN NAME (P4.x)

P4.0/TA1.1

56x

FUNCTIONCONTROL BITS AND SIGNALSP4DIR.x

P4SEL0.x
0

P4.0 (I/O)

I: 0; O: 1

0 TA1.CCI1A

0

TA1.1

1

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9.9.13.5 Port P4.1 and P4.2 Input/Output With Schmitt Trigger
図 9-7 shows the port schematic. 表 9-18 summarizes the selection of the pin functions.

XIN, XOUTP4REN.x
P4DIR.x

DVSS

0

DVCC

1

P4OUT.x

P4SEL0.x

P4IN.xBus
Keeper
P4.1/XIN
P4.2/XOUT

図 9-7. Port P4.1 and P4.2 Input/Output With Schmitt Trigger
表 9-18. Port P4.1 and P4.2 Pin Functions
PIN NAME (P4.x)
P4.1/XIN
P4.2/XOUT
(1)

x
1
2

FUNCTION
P4.1 (I/O)
XIN
P4.2 (I/O)
XOUT

CONTROL BITS AND SIGNALS(1)P4DIR.x

P4SEL0.x

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

X= don't care

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9.9.13.6 Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
図 9-8 shows the port schematic. 表 9-19 summarizes the selection of the pin functions.
LCDCAP0, LCDCAP1
R13, R23, R33

From LCD
P4REN.x
P4DIR.x

DVSS

0

DVCC

1

P4OUT.x

P4IN.xBus
Keeper
P4.3/LCDCAP0P4.4/LCDCAP1
P4.5/R33
P4.6/R23
P4.7/R13

図 9-8. Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
表 9-19. Port P4.3, P4.4, P4.5, P4.6, and P4.7 Pin Functions
PIN NAME (P4.x)
P4.3/LCDCAP0P4.4/LCDCAP1
P4.5/R33
P4.6/R23
P4.7/R13x

FUNCTION

P4DIR.x

LCDPCTL(2)I: 0; O: 1

X

LCDCAP0

X

1

P4.4 (I/O)

I: 0; O: 1

0

LCDCAP1

X

1

P4.5 (I/O)

I: 0; O: 1

0

P4.3 (I/O)

3
4
5

R33
P4.6 (I/O)

6

R23
P4.7 (I/O)

7

CONTROL BITS AND SIGNALS(1)

R13

X

1

I: 0; O: 1

0

X

1

I: 0; O: 1

0

X

1

(1)
(2)

X= don't care
Setting the LCDPCTL bit in SYSCFG2 register will disable both the output driver and input Schmitt trigger to prevent leakage when
analog signals are applied.

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9.9.13.7 Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
図 9-9 shows the port schematic. 表 9-20 summarizes the selection of the pin functions.

L32 to L35

From LCD E
P5REN.x
P5DIR.x0

From Module

1

DVSS

0

DVCC

1

P5OUT.x0

From Module

1

P5SEL0.x
END

To module
P5IN.xBus
Keeper
P5.0/UCB0STE/L32
P5.1/UCB0CLK/L33
P5.2/UCB0SIMO/UCB0SDA/L34
P5.3/UCB0SOMI/UCB0SCL/L35

図 9-9. Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
表 9-20. Port P5.0, P5.1, P5.2, and P5.3 Pin Functions
PIN NAME (P5.x)x

FUNCTION
P5.0 (I/O)

P5.0/UCB0STE/L32

0 UCB0STE

01

01 (y = 32)

P5.1 (I/O)

I: 0; O: 10

0

1 UCB0CLK

0

1

0

X

X

1 (y = 33)

I: 0; O: 10

0

2 UCB0SIMO/UCB0SDA
L34
P5.3 (I/O)
3 UCB0SOMI/UCB0SCL
L35

(1)

LCDSy

0
X

P5.2 (I/O)

P5.3/UCB0SOMI/
UCB0SCL/L35

P5SEL0.x

0L33
P5.2/UCB0SIMO/UCB0SDA/L34

P5DIR.x
I: 0; O: 1
X

L32
P5.1/UCB0CLK/L33

CONTROL BITS AND SIGNALS(1)

0

1

0

X

X

1 (y = 34)

I: 0; O: 1

0

0

0

1

0

X

X

1 (y = 35)

X= don't care

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9.9.13.8 Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
図 9-10 shows the port schematic. 表 9-21 summarizes the selection of the pin functions.

L36 to L39

From LCD E
P5REN.x
P5DIR.x

DVSS

0

DVCC

1

P5OUT.x

P5IN.xBus
Keeper
P5.4/L36
P5.5/L37
P5.6/L38
P5.7/L39

図 9-10. Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
表 9-21. Port P5.4, P5.5, P5.6, and P5.7 Pin Functions
PIN NAME (P5.x)
P5.4/L36
P5.5/L37
P5.6/L38
P5.7/L39x

FUNCTION
P5.4 (I/O)

4

L36
P5.5 (I/O)

5

L37
P5.6 (I/O)

6

L38
P5.7 (I/O)

7

L39

(1)

X= don't care

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CONTROL BITS AND SIGNALS(1)P5DIR.x

LCDSy

I: 0; O: 10X

1 (y = 36)

I: 0; O: 10X

1 (y = 37)

I: 0; O: 10X

1 (y = 38)

I: 0; O: 10X

1 (y = 39)

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JAJSG11F – OCTOBER 2014 – REVISED DECEMBER 2021

9.9.13.9 Port P6 Input/Output With Schmitt Trigger
図 9-11 shows the port schematic. 表 9-22 summarizes the selection of the pin functions.

L16 to L23

From LCD E
P6REN.x
P6DIR.x

DVSS

0

DVCC

1

P6OUT.x

P6IN.xBus
Keeper
P6.0/L16
P6.1/L17
P6.2/L18
P6.3/L19
P6.4/L20
P6.5/L21
P6.6/L22
P6.7/L23

図 9-11. Port P6 Input/Output With Schmitt Trigger

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表 9-22. Port P6 Pin Functions
PIN NAME (P6.x)
P6.0/L16
P6.1/L17
P6.2/L18x

FUNCTION
P6.0 (I/O)

0

L16
P6.1 (I/O)

1

L17
P6.2 (I/O)

2

P6.3/L19

3

P6.4/L20

4

P6.5/L21

5

P6.6/L22

6

P6.7/L237

L18
P6.3 (I/O)
L19
P6.4 (I/O)
L20
P6.5 (I/O)
L21
P6.6 (I/O)
L22
P6.7 (I/O)
L23

(1)

X= don't care

62

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CONTROL BITS AND SIGNALS(1)P6DIR.x

LCDSy

I: 0; O: 10X

1 (y = 16)

I: 0; O: 10X

1 (y = 17)

I: 0; O: 10X

1 (y = 18)

I: 0; O: 10X

1 (y = 19)

I: 0; O: 10X

1 (y = 20)

I: 0; O: 10X

1 (y = 21)

I: 0; O: 10X

1 (y = 22)

I: 0; O: 10X

1 (y = 23)

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9.9.13.10 Port P7 Input/Output With Schmitt Trigger
図 9-12 shows the port schematic. 表 9-23 summarizes the selection of the pin functions.

L0 to L7

From LCD_E
P7REN.x
P7DIR.x

DVSS

0

DVCC

1

P7OUT.x

P7IN.xBus
Keeper
P7.0/L0
P7.1/L1
P7.2/L2
P7.3/L3
P7.4/L4
P7.5/L5
P7.6/L6
P7.7/L7

図 9-12. Port P7 Input/Output With Schmitt Trigger

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表 9-23. Port P7 Pin Functions
PIN NAME (P7.x)
P7.0/L0
P7.1/L1
P7.2/L2x

FUNCTION
P7.0 (I/O)

0

L0
P7.1 (I/O)

1

L1
P7.2 (I/O)

2

P7.3/L3

3

P7.4/L4

4

P7.5/L5

5

P7.6/L6

6

P7.7/L7

7

L2
P7.3 (I/O)
L3
P7.4 (I/O)
L4
P7.5 (I/O)
L5
P7.6 (I/O)
L6
P7.7 (I/O)
L7(1)

X= don't care

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CONTROL BITS AND SIGNALS(1)P7DIR.x

LCDSy

I: 0; O: 10X

1 (y = 0)

I: 0; O: 10X

1 (y = 1)

I: 0; O: 10X

1 (y = 2)

I: 0; O: 10X

1 (y = 3)

I: 0; O: 10X

1 (y = 4)

I: 0; O: 10X

1 (y = 5)

I: 0; O: 10X

1 (y = 6)

I: 0; O: 10X

1 (y = 7)

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JAJSG11F – OCTOBER 2014 – REVISED DECEMBER 2021

9.9.13.11 Port P8.0 and P8.1 Input/Output With Schmitt Trigger
図 9-13 shows the port schematic. 表 9-24 summarizes the selection of the pin functions.

A8, A9From ADC A
P8REN.x
P8DIR.x0

From Module

1

DVSS

0

DVCC

1

P8OUT.x0

From MCLK, ACLK

1

P8SEL0.x
END

To module
P8IN.xBus
Keeper
P8.0/SMCLK/A8
P8.1/ACLK/A9

図 9-13. Port P8.0 and P8.1 Input/Output With Schmitt Trigger
表 9-24. Port P8.0 and P8.1 Pin Functions
PIN NAME (P8.x)x

FUNCTION
P8.0 (I/O)

P8.0/SMCLK/A8

0

(1)
(2)

P8SEL0.x

ADCPCTLx(2)I: 0; O: 1

0

0

1

0

X

X

1 (x = 8)

I: 0; O: 1

0

0

1

0

X

1 (x = 9)

0

SMCLK

1

P8.1 (I/O)
1

P8DIR.x

VSS
A8

P8.1/ACLK/A9

CONTROL BITS AND SIGNALS(1)

VSS

0

ACLK

1

A9

X

X= don't care
Setting the ADCPCTLx bit in SYSCFG2 register will disable both the output driver and input Schmitt trigger to prevent leakage when
analog signals are applied.

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9.9.13.12 Port P8.2 and P8.3 Input/Output With Schmitt Trigger
図 9-14 shows the port schematic. 表 9-25 summarizes the selection of the pin functions.
P8REN.x
P8DIR.x0

From Module

1

DVSS

0

DVCC

1

P8OUT.x0

From Module

1

P8SEL0.x
END

To module
P8IN.xBus
Keeper
P8.2/TA1CLK
P8.3/TA1.2

図 9-14. Port P8.2 and P8.3 Input/Output With Schmitt Trigger
表 9-25. Port P8.2 and P8.3 Pin Functions
PIN NAME (P8.x)x

FUNCTION
P8.2 (I/O)

P8.2/TA1CLK

P8.3/TA1.2

66

CONTROL BITS AND SIGNALSP8DIR.x

P8SEL0.x

I: 0; O: 1

0

2 TA1 CLK

0

VSS

1

P8.3 (I/O)

I: 0; O: 1

3 TA1.CCI2A

0

TA1.2

1

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9.10 Device Descriptors (TLV)
表 9-26 lists the Device IDs of the MSP430FR413x devices. 表 9-27 lists the contents of the device descriptor
tag-length-value (TLV) structure for the MSP430FR413x devices.
表 9-26. Device IDs
DEVICE ID

DEVICE

1A04h

1A05h

MSP430FR4133

F0h

81h

MSP430FR4132

F1h

81h

MSP430FR4131

F2h

81h

表 9-27. Device Descriptors
DESCRIPTIONVALUE

Info length

1A00h

06h

CRC length

1A01h

06h

1A02h

Per unit

1A03h

Per unit

CRC value(2)Information Block
Device ID

1A04h
1A05h

See 表 9-26

Hardware revision

1A06h

Per unit

Firmware revision

1A07h

Per unit

Die Record Tag

1A08h

08h

Die Record length

1A09h

0Ah

1A0Ah

Per unit

1A0Bh

Per unit

1A0Ch

Per unit

1A0Dh

Per unit

1A0Eh

Per unit

1A0Fh

Per unit

1A10h

Per unit

Lot Wafer ID
Die Record
Die X position
Die Y position
Test Result

1A11h

Per unit

1A12h

Per unit

1A13h

Per unit

ADC Calibration Tag

1A14h

11h

ADC Calibration Length

1A15h

08h

1A16h

Per unit

1A17h

Per unit

1A18h

Per unit

ADC Gain Factor
ADC Calibration

MSP430FR413x
ADDRESSADC Offset
ADC 1.5-V Reference Temperature Sensor 30°C
ADC 1.5-V Reference Temperature Sensor 85°C

1A19h

Per unit

1A1Ah

Per unit

1A1Bh

Per unit

1A1Ch

Per unit

1A1Dh

Per unit

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表 9-27. Device Descriptors (continued)
DESCRIPTIONADDRESS

VALUE

Calibration Tag

1A1Eh

12h

Calibration Length

1A1Fh

04h

1A20h

Per unit

1A21h

Per unit

1A22h

Per unit

1A23h

Per unit

Reference and DCO Calibration 1.5-V Reference Factor
DCO Tap Settings for 16 MHz, Temperature 30°C(1)(1)(2)

MSP430FR413x

This value can be directly loaded into DCO bits in CSCTL0 register to get accurate 16-MHz frequency at room temperature, especiallywhen MCU exits from LPM3 and below. It is also suggested to use predivider to decrease the frequency if the temperature drift might
result an overshoot beyond 16 MHz.
The CRC value covers the checksum from 1A04h to 1A77h by applying the CRC-CCITT-16 polynomial of x16 + x12 + x5 + 1.

9.11 Memory
表 9-28 shows the memory organization of the MSP430FR413x devices.
表 9-28. Memory Organization
Memory (FRAM)
Main: interrupt vectors andsignatures
Main: code memory

ACCESSMSP430FR4133

MSP430FR4132

MSP430FR4131

Read/Write(Optional Write Protect)

15KB
FFFFh to FF80h
FFFFh to C400h

8KB
FFFFh to FF80h
FFFFh to E000h

4KB
FFFFh to FF80h
FFFFh to F000h

2KB
27FFh to 2000h

1KB
23FFh to 2000h

512 bytes
21FFh to 2000h

512 bytes
19FFh to 1800h

512 bytes
19FFh to 1800h

512 bytes
19FFh to 1800h

(1)

RAM

Read/Write
Read/Write(Optional Write Protect)

Information Memory (FRAM)(2)

Bootloader (BSL) Memory (ROM)

Read only

1KB
13FFh to 1000h

1KB
13FFh to 1000h

1KB
13FFh to 1000h

Peripherals

Read/Write

4KB
0FFFh to 0000h

4KB
0FFFh to 0000h

4KB
0FFFh to 0000h

(1)
(2)

68

The Program FRAM can be write protected by setting PFWP bit in SYSCFG0 register. See the SYS chapter in the MSP430FR4xx and
MSP430FR2xx Family User's Guide for more details.
The Information FRAM can be write protected by setting DFWP bit in SYSCFG0 register. See the SYS chapter in the MSP430FR4xx
and MSP430FR2xx Family User's Guide for more details.

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9.11.1 Peripheral File Map
表 9-29 shows the base address and the memory size of the registers of each peripheral, and 表 9-30 through 表
9-49 show all of the available registers for each peripheral and their address offsets.
表 9-29. Peripherals Summary
MODULE NAMEBASE ADDRESSSIZESpecial Functions (see 表 9-30)

0100h

0010h

PMM (see 表 9-31)

0120h

0020h

SYS (see 表 9-32)

0140h

0030h

CS (see 表 9-33)

0180h

0020h

FRAM (see 表 9-34)

01A0h

0010h

CRC (see 表 9-35)

01C0h

0008h

WDT (see 表 9-36)

01CCh

0002h

Port P1, P2 (see 表 9-37)

0200h

0020h

Port P3, P4 (see 表 9-38)

0220h

0020h

Port P5, P6 (see 表 9-39)

0240h

0020h

Port P7, P8 (see 表 9-40)

0260h

0020h

Capacitive Touch I/O (see 表 9-41)

02E0h

0010h

Timer0_A3 (see 表 9-42)

0300h

0030h

Timer1_A3 (see 表 9-43)

0340h

0030h

RTC (see 表 9-44)

03C0h

0010h

eUSCI_A0 (see 表 9-45)

0500h

0020h

eUSCI_B0 (see 表 9-46)

0540h

0030h

LCD (see 表 9-47)

0600h

0060h

Backup Memory (see 表 9-48)

0660h

0020h

ADC (see 表 9-49)

0700h

0040h

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表 9-30. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTIONREGISTEROFFSETSFR interrupt enable

SFRIE100h

SFR interrupt flag

SFRIFG102h

SFR reset pin control

SFRRPCR04h

表 9-31. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTIONREGISTEROFFSET

PMM control 0

PMMCTL000h

PMM control 1

PMMCTL102h

PMM control 2

PMMCTL204h

PMM interrupt flags

PMMIFG

0Ah

PM5 Control 0

PM5CTL010h

表 9-32. SYS Registers (Base Address: 0140h)
REGISTER DESCRIPTIONREGISTEROFFSET

SYSCTL00h

Bootloader configuration area

SYSBSLC

02h

JTAG mailbox control

SYSJMBC

06h

JTAG mailbox input 0

SYSJMBI008h

JTAG mailbox input 1

SYSJMBI1

0Ah

JTAG mailbox output 0

SYSJMBO00Ch

JTAG mailbox output 1

SYSJMBO1

0Eh

Bus Error vector generator

SYSBERRIV

18h

User NMI vector generator

SYSUNIV

1Ah

System NMI vector generator

SYSSNIV

1Ch

Reset vector generator

SYSRSTIV

1Eh

System configuration 0

SYSCFG020h

System configuration 1

SYSCFG1

22h

System configuration 2

SYSCFG2

24h

System control

表 9-33. CS Registers (Base Address: 0180h)
REGISTER DESCRIPTIONREGISTEROFFSET

CS control register 0

CSCTL000h

CS control register 1

CSCTL102h

CS control register 2

CSCTL204h

CS control register 3

CSCTL306h

CS control register 4

CSCTL408h

CS control register 5

CSCTL50Ah

CS control register 6

CSCTL60Ch

CS control register 7

CSCTL70Eh

CS control register 8

CSCTL810h

表 9-34. FRAM Registers (Base Address: 01A0h)
REGISTEROFFSET

FRAM control 0

REGISTER DESCRIPTIONFRCTL000h

General control 0

GCCTL004h

General control 1

GCCTL106h

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表 9-35. CRC Registers (Base Address: 01C0h)
REGISTER DESCRIPTIONREGISTEROFFSET

CRC data input

CRC16DI00h

CRC data input reverse byte

CRCDIRB

02h

CRC initialization and result

CRCINIRES

04h

CRC result reverse byte

CRCRESR06h

表 9-36. WDT Registers (Base Address: 01CCh)
REGISTER DESCRIPTION
Watchdog timer control

REGISTEROFFSET

WDTCTL00h

表 9-37. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P1 input

P1IN

00h

Port P1 output

P1OUT

02h

Port P1 direction

P1DIR

04h

Port P1 pulling register enable

P1REN

06h

Port P1 selection 0

P1SEL0

0Ah

Port P1 interrupt vector word

P1IV

0Eh

Port P1 interrupt edge select

P1IES

18h

Port P1 interrupt enable

P1IE

1Ah

Port P1 interrupt flag

P1IFG

1Ch

Port P2 input

P2IN

01h

Port P2 output

P2OUT

03h

Port P2 direction

P2DIR

05h

Port P2 pulling register enable

P2REN

07h

Port P2 selection 0(1)P2SEL0

0Bh

Port P2 interrupt vector word

P2IV

1Eh

Port P2 interrupt edge select

P2IES

19h

Port P2 interrupt enable

P2IE

1Bh

Port P2 interrupt flag

P2IFG

1Dh

(1)

Port P2 selection register does not feature any valid bits. P2SEL0 presents for 16-bit Port A operation with P1SEL0.

表 9-38. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P3 input

P3IN

00h

Port P3 output

P3OUT

02h

Port P3 direction

P3DIR

04h

Port P3 pulling register enable

P3REN

06h

Port P3 selection 0(1)P3SEL0

0Ah

Port P4 input

P4IN

01h

Port P4 output

P4OUT

03h

Port P4 direction

P4DIR

05h

Port P4 pulling register enable

P4REN

07h

Port P4 selection 0

P4SEL00Bh(1)Port P3 selection register does not feature any valid bits. P3SEL0 presents for 16-bit Port B operation with P4SEL0.

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表 9-39. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P5 input

P5IN

00h

Port P5 output

P5OUT

02h

Port P5 direction

P5DIR

04h

Port P5 pulling register enable

P5REN

06h

Port P5 selection 0

P5SEL0

0Ah

Port P6 input

P6IN

01h

Port P6 output

P6OUT

03h

Port P6 direction

P6DIR

05h

Port P6 pulling register enable

P6REN

07h

Port P6 selection 0(1)P6SEL00Bh(1)Port P6 selection register does not feature any valid bits. P6SEL0 presents for 16-bit Port C operation with P5SEL0.

表 9-40. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTIONREGISTEROFFSET

Port P7 input

P7IN

00h

Port P7 output

P7OUT

02h

Port P7 direction

P7DIR

04h

Port P7 pulling register enable

P7REN

06h

Port P7 selection 0(1)P7SEL0

0Ah

Port P8 input

P8IN

01h

Port P8 output

P8OUT

03h

Port P8 direction

P8DIR

05h

Port P8 pulling register enable

P8REN

07h

Port P8 selection 0

P8SEL00Bh(1)Port P7 selection register does not feature any valid bits. P7SEL0 presents for 16-bit Port D operation with P8SEL0.

表 9-41. Capacitive Touch IO Registers (Base Address: 02E0h)
REGISTER DESCRIPTION
Capacitive Touch IO 0 control

REGISTEROFFSETCAPTIO0CTL

0Eh

表 9-42. Timer0_A3 Registers (Base Address: 0300h)
REGISTEROFFSETTA0 control

REGISTER DESCRIPTION

TA0CTL00h

Capture/compare control 0

TA0CCTL002h

Capture/compare control 1

TA0CCTL1

04h

Capture/compare control 2

TA0CCTL2

06h

TA0R

10h

Capture/compare register 0

TA0CCR012h

Capture/compare register 1

TA0CCR1

14h

Capture/compare register 2

TA0CCR216h

TA0 expansion register 0

TA0EX020h

TA0 interrupt vector

TA0IV

2Eh

TA0 counter register

表 9-43. Timer1_A3 Registers (Base Address: 0340h)
REGISTER DESCRIPTIONREGISTEROFFSETTA1 control

TA1CTL00h

Capture/compare control 0

TA1CCTL002h72

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表 9-43. Timer1_A3 Registers (Base Address: 0340h) (continued)
REGISTER DESCRIPTIONREGISTEROFFSET

Capture/compare control 1

TA1CCTL1

04h

Capture/compare control 2

TA1CCTL2

06h

TA1 counter register

TA1R

10h

Capture/compare register 0

TA1CCR012h

Capture/compare register 1

TA1CCR1

14h

Capture/compare register 2

TA1CCR216h

TA1 expansion register 0

TA1EX020h

TA1 interrupt vector

TA1IV

2Eh

表 9-44. RTC Registers (Base Address: 03C0h)
REGISTER DESCRIPTIONREGISTEROFFSET

RTC control

RTCCTL00h

RTC interrupt vector

RTCIV

04h

RTC modulo

RTCMOD08h

RTC counter

RTCCNT0Ch

表 9-45. eUSCI_A0 Registers (Base Address: 0500h)
REGISTEROFFSET

eUSCI_A control word 0

REGISTER DESCRIPTIONUCA0CTLW000h

eUSCI_A control word 1

UCA0CTLW1

02h

eUSCI_A control rate 0

UCA0BR006h

UCA0BR107h

UCA0MCTLW

08h

eUSCI_A control rate 1
eUSCI_A modulation control
eUSCI_A status

UCA0STAT

0Ah

eUSCI_A receive buffer

UCA0RXBUF

0Ch

eUSCI_A transmit buffer

UCA0TXBUF

0Eh

eUSCI_A LIN control

UCA0ABCTL

10h

eUSCI_A IrDA transmit control

lUCA0IRTCTL

12h

eUSCI_A IrDA receive control

IUCA0IRRCTL

13h

eUSCI_A interrupt enable

UCA0IE

1Ah

eUSCI_A interrupt flags

UCA0IFG

1Ch

eUSCI_A interrupt vector word

UCA0IV

1Eh

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表 9-46. eUSCI_B0 Registers (Base Address: 0540h)
REGISTER DESCRIPTIONREGISTEROFFSET

eUSCI_B control word 0

UCB0CTLW000h

eUSCI_B control word 1

UCB0CTLW1

02h

eUSCI_B bit rate 0

UCB0BR006h

eUSCI_B bit rate 1

UCB0BR1

07h

eUSCI_B status word

UCB0STATW

08h

eUSCI_B byte counter threshold

UCB0TBCNT

0Ah

eUSCI_B receive buffer

UCB0RXBUF

0Ch

eUSCI_B transmit buffer

UCB0TXBUF

0Eh

eUSCI_B I2C own address 0

UCB0I2COA014h

eUSCI_B I2C own address 1

UCB0I2COA1

16h

eUSCI_B I2C own address 2

UCB0I2COA218h

eUSCI_B I2C own address 3

UCB0I2COA3

1Ah

eUSCI_B receive address

UCB0ADDRX

1Ch

eUSCI_B address mask

UCB0ADDMASK1Eh

UCB0I2CSA

20h

eUSCI_B I2C slave address
eUSCI_B interrupt enable

UCB0IE

2Ah

eUSCI_B interrupt flags

UCB0IFG

2Ch

eUSCI_B interrupt vector word

UCB0IV2Eh

表 9-47. LCD Registers (Base Address: 0600h)
REGISTER DESCRIPTIONREGISTEROFFSET

LCD control register 0

LCDCTL000h

LCD control register 1

LCDCTL102h

LCD blink control register

LCDBLKCTL

04h

LCD memory control register

LCDMEMCTL

06h

LCD voltage control register

LCDVCTL

08h

LCD port control 0

LCDPCTL00Ah

LCD port control 1

LCDPCTL1

0Ch

LCD port control 2

LCDPCTL2

0Eh

LCD COM/SEG select register

LCDCSS0

14h

LCD COM/SEG select register

LCDCSS1

16h

LCD COM/SEG select register

LCDCSS2

18h

LCDIV

1Eh

LCD memory 0

LCDM0

20h

LCD memory 1

LCDM1

21h

LCD memory 2

LCDM2

22h

LCD interrupt vector
Display memory Static and 2 to 4 mux modes⋮
LCD memory 19⋮⋮

LCDM1933h

Reserved(1)

34h

⋮

⋮

⋮

Reserved(1)

74

3Fh

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表 9-47. LCD Registers (Base Address: 0600h) (continued)
REGISTER DESCRIPTIONREGISTEROFFSET

LCD blinking memory 0

LCDBM040h

LCD blinking memory 1

LCDBM141h⋮⋮

LCDBM1953h

Blinking memory for Static and 2 to 4 mux modes⋮
LCD blinking memory 19
Reserved(1)

54h

⋮

⋮

⋮

Reserved(1)5FhDisplay memory for 5 to 8 mux modes
LCD memory 0

LCDM0

20h

LCD memory 1

LCDM1

21h

LCD memory 2

LCDM2

22h

⋮

⋮

LCDM3947h⋮
LCD memory 39
Reserved(2)

48h

⋮

⋮

⋮

Reserved(2)
(1)
(2)

5Fh

In static and 2-mux to 4-mux modes, LCD memory and blink memory 40 to 63 are not physically implemented.
In 5-mux to 8-mux modes, LCD memory and blink memory 40 to 63 are not physically implemented.

表 9-48. Backup Memory Registers (Base Address: 0660h)
REGISTER DESCRIPTIONREGISTEROFFSET

Backup memory 0

BAKMEM000h

Backup memory 1

BAKMEM1

02h

Backup memory 2

BAKMEM2

04h

Backup memory 3

BAKMEM3

06h

Backup memory 4

BAKMEM4

08h

Backup memory 5

BAKMEM5

0Ah

Backup memory 6

BAKMEM6

0Ch

Backup memory 7

BAKMEM7

0Eh

Backup memory 8

BAKMEM810h

Backup memory 9

BAKMEM912h

Backup memory 10

BAKMEM10

14h

Backup memory 11

BAKMEM11

16h

Backup memory 12

BAKMEM12

18h

Backup memory 13

BAKMEM13

1Ah

Backup memory 14

BAKMEM14

1Ch

Backup memory 15

BAKMEM15

1Eh

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表 9-49. ADC Registers (Base Address: 0700h)
REGISTER DESCRIPTIONREGISTEROFFSET

ADC control register 0

ADCCTL000h

ADC control register 1

ADCCTL102h

ADC control register 2

ADCCTL204h

ADC window comparator low threshold

ADCLO

06h

ADC window comparator high threshold

ADCHI

08h

ADC memory control register 0

ADCMCTL00Ah

ADC conversion memory register

ADCMEM012h

ADC interrupt enable

ADCIE

1Ah

ADC interrupt flags

ADCIFG1Ch

ADC interrupt vector word

ADCIV

1Eh

9.12 Identification
9.12.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The devicespecific errata sheet describes these markings. For links to all of the errata sheets for the devices in this data
sheet, see セクション 11.4.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For details on
this value, see the "Hardware Revision" entries in セクション 9.10.
9.12.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific errata
sheet describes these markings. For links to all of the errata sheets for the devices in this data sheet, see セクシ
ョン 11.4.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For details
on this value, see the "Device ID" entries in セクション 9.10.
9.12.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in MSP430
Programming With the JTAG Interface.

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10 Applications, Implementation, and LayoutNote
以下のアプリケーション情報は、TI の製品仕様に含まれるものではなく、TI ではその正確性または完全性を保証いたしません。個々の目的に対する製品の適合性については、お客様の責任で判断していただくことになります。お客様は自身の設計実装を検証しテストすることで、システムの機能を確認する必要があります。

10.1 Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP430FR413x devices. These
guidelines are to make sure that the device has proper connections for powering, programming, debugging, andoptimum analog performance.
10.1.1 Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 10-µF plus a 100-nF low-ESR ceramic decoupling capacitor to
the DVCC and DVSS pins (see 図 10-1). Higher-value capacitors may be used but can impact supply rail rampup time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few
millimeters).

DVCC+

Power Supply
Decoupling

10 µF

100 nFDVSS

図 10-1. Power Supply Decoupling
10.1.2 External Oscillator
This device supports only a low-frequency crystal (32 kHz) on the XIN and XOUT pins. External bypass
capacitors for the crystal oscillator pins are required.
It is also possible to apply digital clock signals to the XIN input pin that meet the specifications of the respective
oscillator if the appropriate XT1BYPASS mode is selected. In this case, the associated XOUT pin can be used
for other purposes. If they are left unused, they must be terminated according to セクション 7.4.
図 10-2 shows a typical connection diagram.
XIN

CL1

XOUT

CL2

図 10-2. Typical Crystal Connection
See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal
oscillator with the MSP430 devices.
10.1.3 JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or MSPFET430UIF) can be used to program and debug code on the target board. In addition, the connections also
support the MSP-GANG production programmers, thus providing an easy way to program prototype boards, if
desired. 図 10-3 shows the connections between the 14-pin JTAG connector and the target device required to
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support in-system programming and debugging for 4-wire JTAG communication. 図 10-4 shows the connectionsfor 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are identical.
Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSP-FET430UIF
interface modules and MSP-GANG have a VCC-sense feature that, if used, requires an alternate connection (pin4 instead of pin 2). The VCC-sense feature senses the local VCC present on the target board (that is, a battery orother local power supply) and adjusts the output signals accordingly. 図 10-3 and 図 10-4 show a jumper blockthat supports both scenarios of supplying VCC to the target board. If this flexibility is not required, the desired VCC
connections may be hard-wired to eliminate the jumper block. Pins 2 and 4 must not be connected at the sametime.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s Guide.
VCC

Important to connect

MSP430FRxxx

J1 (see Note A)
DVCC

J2 (see Note A)
R1
47 kW

JTAG

VCC TOOLVCC TARGETTEST

RST/NMI/SBWTDIO

2

1

4

3

6

5

8

7

10

9

12

11

14

13

TDO/TDI
TDI

TDO/TDI
TDI

TMS

TMS

TCK

TCK

GND
RST

TEST/SBWTCK
C1
1 nF(see Note B)

A.
B.

DVSS

If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used, make connection
J2.
The upper limit for C1 is 1.1 nF when using current TI tools.

図 10-3. Signal Connections for 4-Wire JTAG Communication

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VCC

Important to connect

MSP430FRxxx
J1 (see Note A)
DVCC

J2 (see Note A)
R1
47 kΩ(see Note B)
JTAG
VCC TOOLVCC TARGET

2

1

4

3

6

5

8

7

10

9

12

11

14

13

TDO/TDI

RST/NMI/SBWTDIO

TCK
GND

TEST/SBWTCK
C1
1 nF(see Note B)

A.
B.

DVSS

Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the debug or
programming adapter.
The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during JTAG access, andany capacitance that is attached to this signal may affect the ability to establish a connection with the device. The upper limit for C1 is
1.1 nF when using current TI tools.

図 10-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
10.1.4 Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is edge
sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the external NMI.
When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either pullup or
pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not. If the RST/NMI
pin is unused, it is required either to select and enable the internal pullup or to connect an external 47-kΩ pullup
resistor to the RST/NMI pin with a 1.1-nF pulldown capacitor. The pulldown capacitor should not exceed 1.1 nF
when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like
FET interfaces or GANG programmers.
See the MSP430FR4xx and MSP430FR2xx Family User's Guide for more information on the referenced control
registers and bits.
10.1.5 Unused Pins
For details on the connection of unused pins, see セクション 7.4.

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10.1.6 General Layout Recommendations••••

Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430 32-kHz
Crystal Oscillators for recommended layout guidelines.
Proper bypass capacitors on DVCC and reference pins, if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital switching
signals such as PWM or JTAG signals away from the oscillator circuit.
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.

10.1.7 Do's and Don'ts
During power up, power down, and device operation, DVCC must not exceed the limits specified in セクション
8.1. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and
FRAM.

10.2 Peripheral- and Interface-Specific Design Information
10.2.1 ADC Peripheral
10.2.1.1 Partial Schematic
図 10-5 shows the recommended circuit for ADC grounding and noise reduction.
DVSS
Using an external
positive reference

VREF+/VEREF++
10 µF

100 nF

Using an external
negative reference

VEREF+
10 µF

100 nF

図 10-5. ADC Grounding and Noise Considerations
10.2.1.2 Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be
followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with otheranalog or digital circuitry. If care is not taken, this current can generate small unwanted offset voltages that can
add to or subtract from the reference or input voltages of the ADC. The general guidelines in セクション 10.1.1
combined with the connections shown in セクション 10.2.1.1 prevent this.
In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital switching or
switching power supplies can corrupt the conversion result. TI recommends a noise-free design using separate
analog and digital ground planes with a single-point connection to achieve high accuracy.
図 10-5 shows the recommended decoupling circuit when an external voltage reference is used. The internalreference module has a maximum drive current as described in the sections ADC Pin Enable and 1.2-V
Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide.
The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-μF capacitor buffers the reference pin and filters low-frequency ripple. A
100-nF bypass capacitor filters out high-frequency noise.
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10.2.1.3 Layout Guidelines
Components that are shown in the partial schematic (see 図 10-5) should be placed as close as possible to therespective device pins to avoid long traces, because they add additional parasitic capacitance, inductance, andresistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM), because
the high-frequency switching can be coupled into the analog signal.
10.2.2 LCD_E Peripheral
10.2.2.1 Partial Schematic
Required LCD connections greatly vary by the type of display that is used (static or multiplexed), whether
external or internal biasing is used, and also whether the on-chip charge pump is employed. For any display
used, LCD_E has configurable segment (Sx) or common (COMx) signals connected to the MCU which allows
optimal PCB layout and for the design of the application software.
Because LCD connections are application specific, it is difficult to provide a single one-fits-all schematic.
However, for an example of connecting a 4-mux LCD with 27 segment lines that has a total of 4 × 27 = 108
individually addressable LCD segments to an MSP430FR4133, see the MSP-EXP430FR4133 LaunchPad ™
development kit as a reference.
10.2.2.2 Design Requirements
Due to the flexibility of the LCD_E peripheral module to accommodate various segment-based LCDs, selecting
the right display for the application in combination with determining specific design requirements is often an
iterative process. There can be well-defined requirements in terms of how many individually addressable LCD
segments must be controlled, what the requirements for LCD contrast are, which device pins are available for
LCD use and which are required by other application functions, and what the power budget is, to name just afew. TI strongly recommends reviewing the LCD_E peripheral module chapter in the MSP430FR4xx and
MSP430FR2xx Family User's Guide during the initial design requirements and decision process. 表 10-1
provides a brief overview over different choices that can be made and their impact.

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表 10-1. LCD_E Design Options
OPTION OR FEATURE

IMPACT OR USE CASE

Multiplexed LCD

•
•
•
•
•

Enable displays with more segments
Use fewer device pins
LCD contrast decreases as mux level increases
Power consumption increases with mux level
Requires multiple intermediate bias voltages

Static LCD

•
•
•
•

Limited number of segments that can be addressed
Use a relatively large number of device pins
Use the least amount of power
Use only VCC and GND to drive LCD signals

Internal Bias Generation•••

Simpler solution – no external circuitry
Independent of VLCD source
Somewhat higher power consumption

External Bias Generation•••

Requires external resistor ladder divider
Resistor size depends on display
Ability to adjust drive strength to optimize tradeoff between power consumption and good drive of large
segments (high capacitive load)
External resistor ladder divider can be stabilized through capacitors to reduce ripple•
Internal Charge Pump•

Helps ensure a constant level of contrast despite decaying supply voltage conditions (battery-powered
applications)
Programmable voltage levels allow software-driven contrast control
Requires an external capacitor on the LCDCAP pins
Higher current consumption than simply using VCC for the LCD driver•••

10.2.2.3 Detailed Design Procedure
A major component in designing the LCD solution is determining the exact connections between the LCD_E
peripheral module and the display itself. Two basic design processes can be employed for this step, althoughoften a balanced co-design approach is recommended:••

PCB layout-driven design
Software-driven design

In the PCB layout-driven design process, LCD_E offers configurable segment Sx and common COMx signals
which are connected to the respective MSP430 device pins so that the routing of the PCB can be optimized tominimize signal crossings and to keep signals on one side of the PCB only, typically the top layer. For example,
using a multiplexed LCD, it is possible to arbitrarily connect the Sx and COMx signals between the LCD and the
MSP430 device as long as segment lines are swapped with segment lines and common lines are swapped with
common lines. It is also possible to not contiguously connect all segment lines but rather skip LCD_E module
segment connections to optimize layout or to allow access to other functions that may be multiplexed on aparticular device port pin. Employing a purely layout-driven design approach, however, can result in the LCD_E
module control bits that are responsible for turning on and off segments to appear scattered throughout the
memory map of the LCD controller (LCDMx registers). This approach potentially places a rather large burden on
the software design that may also result in increased energy consumption due to the computational overhead
required to work with the LCD.
The other extreme is a purely software-driven approach that starts with the idea that control bits for LCD
segments that are frequently turned on and off together should be co-located in memory in the same LCDMx
register or in adjacent registers. For example, in case of a 4-mux display that contains several 7-segment digits,from a software perspective it can be very desirable to control all 7 segments of each digit though a single bytewide access to an LCDMx register. And consecutive segments are mapped to consecutive LCDMx registers.
This allows use of simple look-up tables or software loops to output numbers on an LCD, reducing computational82

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overhead and optimizing the energy consumption of an application. Establishing of the most convenient memory
layout needs to be performed in conjunction with the specific LCD that is being used to understand its design
constraints in terms of which segment and which common signals are connected to, for example, a digit.
For design information regarding the LCD controller input voltage selection including internal and external
options, contrast control, and bias generation, see the LCD_E controller chapter in the MSP430FR4xx and
MSP430FR2xx Family User's Guide.
10.2.2.4 Layout Guidelines
LCD segment (Sx) and common (COMx) signal traces are continuously switching while the LCD is enabled andshould, therefore, be kept away from sensitive analog signals such as ADC inputs to prevent any noise coupling.
TI recommends keeping the LCD signal traces on one side of the PCB grouped together in a bus-like fashion. A
ground plane underneath the LCD traces and guard traces employed alongside the LCD traces can provide
shielding.
If the internal charge pump of the LCD module is used, the externally provided capacitor on the LCDCAP0 and
LCDCAP1 pins should be located as close as possible to the MCU. The capacitor should be connected to thedevice using a short and direct trace.
For an example layout of connecting a 4-mux LCD with 27 segments to an MSP430FR4133 and using thecharge pump feature, see the MSP-EXP430FR4133 LaunchPad development kit.
10.2.3 Timer
10.2.3.1 Generate Accurate PWM Using Internal Oscillator
Generating an accurate PWM signal using the device internal oscillator is an important feature for many costsensitive applications in which an external crystal is not desired. The MSP430FR4133 uses an on-chip 32-kHz
RC oscillator (REFO) combined with the 16-MHz digitally controlled oscillator (DCO) with frequency-locked loop
(FLL) to provide the clock source for the timer peripheral to generate the PWM. The REFO frequency may
change across different temperatures. To achieve improved PWM accuracy, application software may
periodically measure the device temperature and compute an appropriate timer capture/compare correction
value to offset for REFO temperature drift. For more information on how to implement this algorithm refer to How
to Achieve Higher Accuracy Timer with Internal Oscillator on MSP430 . 図 10-6 shows the absolute value of atypical error percentage for a 44-kHz PWM signal over the temperature range.
The absolute value error percentages shown below can be interpreted as either positive or negative resulting ina slightly faster or slower PWM frequency.

図 10-6. Calibrated 44-kHz Timer PWM Error Magnitude
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10.3 Typical Applications
表 10-2 lists reference designs that demonstrate use of the MSP430FR413x family of devices in different realworld application scenarios. Consult these designs for additional guidance regarding schematic, layout, andsoftware implementation. For the most up-to-date list of available reference designs, visit TI reference designs.
表 10-2. Reference Designs
DESIGN NAME

LINK

Thermostat Implementation With MSP430FR4xx

TIDM-FRAM-THERMOSTAT

Water Meter Implementation With MSP430FR4xx

TIDM-FRAM-WATERMETER

Remote Controller of Air Conditioner Using Low-Power Microcontroller

TIDM-REMOTE-CONTROLLER-FOR-AC

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11 Device and Documentation Support
11.1 Getting Started
For an introduction to the MSP430 family of devices and the tools and libraries that are available to help withyour development, visit the MSP430™ ultra-low-power sensing & measurement MCUs overview.

11.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP
MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These
prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully
qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated
fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.
TI recommends that these devices not be used in any production system because their expected end-use failure
rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature
range, package type, and distribution format. 図 11-1 provides a legend for reading the complete device name.
MSP

430

FR

4

133

I

PM

R
Distribution Format

Processor Family

Packaging

Platform
Memory Type

Temperature Range
SeriesProcessor Family

Feature Set

MSP = Mixed-Signal Processor
XMS = Experimental Silicon

Platform

430 = TI’s 16-Bit MSP430 Low-Power Microcontroller Platform

Memory Type

FR = FRAM

Series

4 = FRAM 4 series up to 16 MHz with LCD

Feature Set

First and Second Digits: ADC Channels / 16-bit Timers / I/Os
13 = Up to 10 / 3 / Up to 60

Temperature Range

I = –40°C to 85°C

Packaging

http://www.ti.com/packaging

Distribution Format

T = Small reel
R = Large reel
No marking = Tube or tray

Third Digit: FRAM (KB) / SRAM (KB)
3 = 16 / 2
2=8/1
1 = 4 / 0.5

図 11-1. Device Nomenclature

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11.3 Tools and Software
表 11-1 lists the debug features supported by the MSP430FR413x microcontrollers. See the Code Composer
Studio IDE for MSP430 MCUs User's Guide for details on the available features.
表 11-1. Hardware Features
MSP430
ARCHITECTURE

4-WIRE
JTAG

2-WIREJTAG

BREAKPOINTS(N)MSP430Xv2

Yes

Yes

3

RANGE
BREAKPOINTSCLOCK
CONTROLSTATESEQUENCER

TRACE
BUFFER

LPMX.5DEBUGGINGSUPPORT

Yes

Yes

No

No

No

Design Kits and Evaluation Modules
MSP430FR4133 LaunchPad Development Kit
The MSP-EXP430FR4133 LaunchPad development kit is an easy-to-use Evaluation Module (EVM) for the
MSP430FR4133 microcontroller. It contains everything needed to start developing on the MSP430 ultra-lowpower (ULP) FRAM-based microcontroller (MCU) platform, including on-board emulation for programming,
debugging, and energy measurements.
MSP-TS430PM64D Target Development Board for MSP430FR2x/4x MCUs
The MSP-TS430PM64D is a stand-alone 64-pin ZIF socket target board used to program and debug the
MSP430 MCU in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol.
MSP-FET430U64D Target Development Board (64-pin) and MSP-FET Programmer Bundle for MSP430FR2x/4x
MCUs
The MSP-FET430U64D is a bundle containing the MSP-FET emulator and MSP-TS430PM64D 64-pin ZIF
socket target board to program and debug the MSP430 MCU in-system through the JTAG interface or the Spy
Bi-Wire (2-wire JTAG) protocol.
Software
MSP430Ware™ Software
MSP430Ware software is a collection of code examples, data sheets, and other design resources for all
MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 MCU design resources, MSP430Ware software also includes a high-level API called MSP Driver
Library. This library makes it easy to program MSP430 hardware. MSP430Ware software is available as acomponent of CCS or as a stand-alone package.
MSP430FR413x, MSP430FR203x Code Examples
C code examples are available for every MSP device that configures each of the integrated peripherals forvarious application needs.
FRAM Embedded Software Utilities for MSP Ultra-Low-Power Microcontrollers
The TI FRAM Utilities software is designed to grow as a collection of embedded software utilities that leverage
the ultra-low-power and virtually unlimited write endurance of FRAM. The utilities are available for MSP430FRxx
FRAM microcontrollers and provide example code to help start application development.
MSP430 Touch Pro GUI
The MSP430 Touch Pro Tool is a PC-based tool that can be used to verify capacitive touch button, slider, andwheel designs. The tool receives and visualizes captouch sensor data to help the user quickly and easily
evaluate, diagnose, and tune button, slider, and wheel designs.

86

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MSP430 Touch Power Designer GUI
The MSP430 Capacitive Touch Power Designer enables the calculation of the estimated average current draw
for a given MSP430 capacitive touch system. By entering system parameters such as operating voltage,
frequency, number of buttons, and button gate time, the user can have a power estimate for a given capacitive
touch configuration on a given device family in minutes.
Digital Signal Processing (DSP) Library for MSP Microcontrollers
The Digital Signal Processing library is a set of highly optimized functions to perform many common signal
processing operations on fixed-point numbers for MSP430 and MSP432 microcontrollers. This function set istypically used for applications where processing-intensive transforms are done in real-time for minimal energy
and with very high accuracy. This optimal use of the MSP intrinsic hardware for fixed-point math allows for
significant performance gains.
MSP Driver Library
The abstracted API of MSP Driver Library provides easy-to-use function calls that free you from directly
manipulating the bits and bytes of the MSP430 hardware. Thorough documentation is delivered through ahelpful API Guide, which includes details on each function call and the recognized parameters. Developers canuse Driver Library functions to write complete projects with minimal overhead.
MSP EnergyTrace Technology
EnergyTrace technology for MSP430 microcontrollers is an energy-based code analysis tool that measures anddisplays the energy profile of the application and helps to optimize it for ultra-low-power consumption.
ULP (Ultra-Low Power) Advisor
ULP Advisor™ software is a tool for guiding developers to write more efficient code to fully use the unique ultralow-power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new microcontroller
developers, ULP Advisor checks your code against a thorough ULP checklist to help minimize the energy
consumption of your application. At build time, ULP Advisor provides notifications and remarks to highlight areasof your code that can be further optimized for lower power.
Fixed Point Math Library for MSP
The MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical
functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and
MSP432 devices. These routines are typically used in computationally intensive real-time applications where
optimal execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmathlibraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably
lower than equivalent code written using floating-point math.
Floating Point Math Library for MSP430
Continuing to innovate in the low-power and low-cost microcontroller space, TI provides MSPMATHLIB.
Leveraging the intelligent peripherals of our devices, this floating-point math library of scalar functions is up to 26
times faster than the standard MSP430 math functions. Mathlib is easy to integrate into your designs. This libraryis free and is integrated in both Code Composer Studio IDE and IAR Embedded Workbench IDE.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code Composer Studio (CCS) integrated development environment (IDE) supports all MSP microcontroller
devices. CCS comprises a suite of embedded software utilities used to develop and debug embedded
applications. CCS includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features.

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Command-Line Programmer
MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET
programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary
files (.txt or .hex) directly to the MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger
The MSP-FET is a powerful emulation development tool – often called a debug probe – which lets users quickly
begin application development on MSP low-power MCUs. Creating MCU software usually requires downloading
the resulting binary program to the MSP device for validation and debugging.
MSP-GANG Production Programmer
The MSP Gang Programmer is an MSP430 or MSP432 device programmer that can program up to eight
identical MSP430 or MSP432 flash or FRAM devices at the same time. The MSP Gang Programmer connects toa host PC using a standard RS-232 or USB connection and provides flexible programming options that let theuser fully customize the process.

11.4 Documentation Support
The following documents describe the MSP430FR413x microcontrollers. Copies of these documents areavailable on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for yourdevice on ti.com. In the upper right corner, click the "Alert me" button. This registers you to receive a weekly
digest of product information that has changed (if any). For change details, check the revision history of any
revised document.
Errata
MSP430FR4133 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430FR4132 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430FR4131 Device Erratasheet
Describes the known exceptions to the functional specifications.
User's Guides
MSP430FR4xx and MSP430FR2xx Family User's Guide
Detailed description of all modules and peripherals available in this device family.
MSP430 FRAM Device Bootloader (BSL) User's Guide
The bootloader (BSL) on MSP430 MCUs lets users communicate with embedded memory in the MSP430 MCU
during the prototyping phase, final production, and in service. Both the programmable memory (FRAM memory)and the data memory (RAM) can be modified as required.
MSP430 Programming With the JTAG Interface
This document describes the functions that are required to erase, program, and verify the memory module of the
MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition,
it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This
document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG
interface, which is also referred to as Spy-Bi-Wire (SBW).

88

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MSP430 Hardware Tools User's Guide
This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the
program development tool for the MSP430 ultra-low-power microcontroller. Both available interface types, theparallel port interface and the USB interface, are described.
Application Reports
MSP430 FRAM Technology – How To and Best Practices
FRAM is a nonvolatile memory technology that behaves similar to SRAM while enabling a whole host of new
applications, but also changing the way firmware should be designed. This application report outlines the how to
and best practices of using FRAM technology in MSP430 from an embedded software development perspective.
It discusses how to implement a memory layout according to application-specific code, constant, data spacerequirements, and the use of FRAM to optimize application energy consumption.
MSP430 32-kHz Crystal Oscillators
Selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal
oscillator. This application report summarizes crystal oscillator function and explains the parameters to select thecorrect crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout
are given. The document also contains detailed information on the possible oscillator tests to ensure stableoscillator operation in mass production.
MSP430 System-Level ESD Considerations
System-level ESD has become increasingly demanding with silicon technology scaling towards lower voltages
and the need for designing cost-effective and ultra-low-power components. This application report addresses
three different ESD topics to help board designers and OEMs understand and design robust system-level
designs.

11.5 サポート・リソース
TI E2E™ サポート ・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。
リンクされているコンテンツは、該当する貢献者により、現状のまま提供されるものです。これらは TI の仕様を構成するものではなく、必ずしも TI の見解を反映したものではありません。TI の使用条件を参照してください。

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JAJSG11F – OCTOBER 2014 – REVISED DECEMBER 2021

11.6 Trademarks
LaunchPad™, MSP430Ware™, MSP430™, Code Composer Studio™, TI E2E™, and ULP Advisor™ are
trademarks of Texas Instruments.
すべての商標は、それぞれの所有者に帰属します。

11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handledwith appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.

11.8 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (asdefined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.

11.9 Glossary
TI Glossary

90This glossary lists and explains terms, acronyms, and definitions.

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JAJSG11F – OCTOBER 2014 – REVISED DECEMBER 2021

12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2022 Texas Instruments Incorporated

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PACKAGE OPTION ADDENDUM
www.ti.com

8-Dec-2021

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

(3)

(4/5)

(6)

MSP430FR4131IG48

ACTIVE

TSSOP

DGG

48

40

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

FR4131

MSP430FR4131IG48R

ACTIVE

TSSOP

DGG

48

2000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

FR4131

MSP430FR4131IG56

ACTIVE

TSSOP

DGG

56

35

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

FR4131

MSP430FR4131IG56R

ACTIVE

TSSOP

DGG

56

2000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

FR4131

MSP430FR4131IPMR

ACTIVE

LQFP

PM

64

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

FR4131

MSP430FR4132IG48

ACTIVE

TSSOP

DGG

48

40

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

FR4132

MSP430FR4132IG48R

ACTIVE

TSSOP

DGG

48

2000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

FR4132

MSP430FR4132IG56

ACTIVE

TSSOP

DGG

56

35

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

FR4132

MSP430FR4132IG56R

ACTIVE

TSSOP

DGG

56

2000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

FR4132

MSP430FR4132IPMR

ACTIVE

LQFP

PM

64

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

FR4132

MSP430FR4133IG48

ACTIVE

TSSOP

DGG

48

40

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

FR4133

MSP430FR4133IG48R

ACTIVE

TSSOP

DGG

48

2000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

FR4133

MSP430FR4133IG56

ACTIVE

TSSOP

DGG

56

35

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

FR4133

MSP430FR4133IG56R

ACTIVE

TSSOP

DGG

56

2000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

FR4133

MSP430FR4133IPM

ACTIVE

LQFP

PM

64

160

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

FR4133

MSP430FR4133IPMR

ACTIVE

LQFP

PM

64

1000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 85

FR4133(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1

SamplesPACKAGE OPTION ADDENDUM
www.ti.com

8-Dec-2021(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

1-Feb-2024

TAPE AND REEL INFORMATIONREEL DIMENSIONSTAPE DIMENSIONS
K0

P1

B0 W
Reel
DiameterCavity
A0
B0
K0
W
P1

A0

Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers

Reel Width (W1)QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes

Q1

Q2

Q1

Q2

Q3

Q4

Q3

Q4

User Direction of Feed

Pocket Quadrants*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

MSP430FR4131IG48R

TSSOP

DGG

48

2000

330.0

24.4

8.6

13.0

1.8

12.0

24.0

Q1

MSP430FR4131IG56R

TSSOP

DGG

56

2000

330.0

MSP430FR4131IPMR

LQFP

PM

64

1000

330.0

24.4

8.6

15.6

1.8

12.0

24.0

Q1

24.4

13.0

13.0

2.1

16.0

24.0

Q2

MSP430FR4132IG48R

TSSOP

DGG

48

2000

MSP430FR4132IG56R

TSSOP

DGG

56

2000

330.0

24.4

8.6

13.0

1.8

12.0

24.0

Q1

330.0

24.4

8.6

15.6

1.8

12.0

24.0

MSP430FR4132IPMR

LQFP

PM

64

Q1

1000

330.0

24.4

13.0

13.0

2.1

16.0

24.0

Q2

MSP430FR4133IG48R

TSSOP

DGG

MSP430FR4133IG56R

TSSOP

DGG

48

2000

330.0

24.4

8.6

13.0

1.8

12.0

24.0

Q1

56

2000

330.0

24.4

8.6

15.6

1.8

12.0

24.0

MSP430FR4133IPMR

LQFP

PM

Q1

64

1000

330.0

24.4

13.0

13.0

2.1

16.0

24.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

1-Feb-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)

W

L

H

*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)

MSP430FR4131IG48R

TSSOP

DGG

48

2000

350.0

350.0

43.0

MSP430FR4131IG56R

TSSOP

DGG

56

2000

350.0

350.0

43.0

MSP430FR4131IPMR

LQFP

PM

64

1000

350.0

350.0

43.0

MSP430FR4132IG48R

TSSOP

DGG

48

2000

350.0

350.0

43.0

MSP430FR4132IG56R

TSSOP

DGG

56

2000

350.0

350.0

43.0

MSP430FR4132IPMR

LQFP

PM

64

1000

350.0

350.0

43.0

MSP430FR4133IG48R

TSSOP

DGG

48

2000

350.0

350.0

43.0

MSP430FR4133IG56R

TSSOP

DGG

56

2000

350.0

350.0

43.0

MSP430FR4133IPMR

LQFP

PM

64

1000

350.0

350.0

43.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

1-Feb-2024

TUBE
T - TubeheightL - Tube length

W - Tubewidth

B - Alignment groove width*All dimensions are nominal

DevicePackage Name

Package Type

Pins

SPQ

L (mm)W (mm)

T (µm)B (mm)MSP430FR4131IG48

DGG

TSSOP

48

40

530

11.89

3600

4.9

MSP430FR4131IG56

DGG

TSSOP

56

35

530

11.89

3600

4.9

MSP430FR4132IG48

DGG

TSSOP

48

40

530

11.89

3600

4.9

MSP430FR4132IG56

DGG

TSSOP

56

35

530

11.89

3600

4.9

MSP430FR4133IG48

DGG

TSSOP

48

40

530

11.89

3600

4.9

MSP430FR4133IG56

DGG

TSSOP

56

35

530

11.89

3600

4.9

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION
www.ti.com

1-Feb-2024

TRAY
L - Outer tray length without tabs

KO Outertray
height

WOuter
tray
width
Text

P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

DevicePackage
Name

Package
Type

Pins

SPQ

MSP430FR4133IPM

PM

LQFP

64

160

Unit arrayMax
L (mm) W
matrix temperature
(mm)
(°C)
8 x 20150

Pack Materials-Page 4

315

135.9

K0
(µm)

P1
(mm)

CL
(mm)

CW
(mm)

7620

15.2

13.1

13

PACKAGE OUTLINE

DGG0056ATSSOP - 1.2 mm max height
SCALE 1.200

SMALL OUTLINE PACKAGE

C
8.3
TYP
7.9

SEATING PLANE

PIN 1 ID
AREA

A

0.1 C

54X 0.5
56

1

14.1
13.9
NOTE 3

2X
13.5

28
B

6.2
6.0

29

56X

0.27
0.17
0.08

1.2 MAX
C A

B(0.15) TYP

SEE DETAIL A

0.25
GAGE PLANE

0 -8

0.15
0.05

0.75
0.50

DETAIL A
TYPICAL

4222167/A 07/2015

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.

www.ti.com

EXAMPLE BOARD LAYOUT

DGG0056ATSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

56X (1.5)

SYMM
1

56

56X (0.3)

54X (0.5)(R0.05)
TYP

SYMM

28

29
(7.5)

LAND PATTERN EXAMPLESCALE:6X

SOLDER MASKOPENINGMETALSOLDER MASKOPENINGMETAL UNDERSOLDER MASK

0.05 MAXALL AROUND

0.05 MIN
ALL AROUNDSOLDER MASKDEFINEDNON SOLDER MASKDEFINEDSOLDER MASK DETAILS
4222167/A 07/2015

NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGNDGG0056ATSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

56X (1.5)

SYMM
1

56

56X (0.3)

54X (0.5)(R0.05) TYP

SYMM

29

28
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCILSCALE:6X

4222167/A 07/2015

NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DGG0048ATSSOP - 1.2 mm max height
SCALE 1.350

SMALL OUTLINE PACKAGE

C
8.3
TYP
7.9

SEATING PLANE

PIN 1 ID
AREA

A

0.1 C
46X 0.5
48

1

12.6
12.4
NOTE 3

2X
11.5

24
B

25
6.2
6.0

48X

0.27
0.17
0.08

C A B

1.2
1.0

(0.15) TYP

SEE DETAIL A

0.25
GAGE PLANE

0 -8

0.15
0.05

0.75
0.50

DETAIL A
TYPICAL
4214859/B 11/2020

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.

www.ti.com

EXAMPLE BOARD LAYOUT

DGG0048ATSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

48X (1.5)

SYMM
1
48

48X (0.3)

46X (0.5)(R0.05)
TYP

SYMM

24

25
(7.5)

LAND PATTERN EXAMPLESCALE:6X

SOLDER MASKOPENINGMETALSOLDER MASKOPENINGMETAL UNDERSOLDER MASK

0.05 MAXALL AROUND

0.05 MIN
ALL AROUNDSOLDER MASKDEFINEDNON SOLDER MASKDEFINEDSOLDER MASK DETAILS
4214859/B 11/2020

NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGNDGG0048ATSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

48X (1.5)

SYMM
1
48

48X (0.3)

46X (0.5)
SYMM(R0.05) TYP

24

25
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCILSCALE:6X

4214859/B 11/2020

NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com

MECHANICAL DATAMTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,27
0,17

0,50
48

0,08 M
25

6,20
6,00

8,30
7,90

0,15 NOM

Gage Plane

1

0,25

24
0°– 8°
A

0,75
0,50

Seating Plane
0,15
0,05

1,20 MAXPINS **

0,10

48

56

64

A MAX

12,60

14,10

17,10

A MIN

12,40

13,90

16,90

DIM

4040078 / F 12/97
NOTES: A.
B.
C.
D.

All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153

POST OFFICE BOX 655303• DALLAS, TEXAS 75265

PACKAGE OUTLINE

PM0064A

LQFP - 1.6 mm max height
SCALE 1.400

PLASTIC QUAD FLATPACK64

PIN 1 ID

10.2
9.8
NOTE 3

B
49

48

1

10.2
9.8
NOTE 3

12.2
TYP
11.8

33

16

32

17

A

64X

60X 0.5
4X 7.5

0.27
0.17
0.08

C A B

C
(0.13) TYP
SEATING PLANE
0.08

SEE DETAIL A

0.25
GAGE PLANE

0 -7(1.4) 1.6 MAX

0.75
0.45

0.05 MINDETAIL A
DETAIL A
SCALE: 14

TYPICAL
4215162/A 03/2017

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-026.

www.ti.com

EXAMPLE BOARD LAYOUT

PM0064A

LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

SYMM
49

64

64X (1.5)
148
64X (0.3)

SYMM
60X (0.5)(11.4)(R0.05) TYP

33

16

17

32
(11.4)LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:8X

0.05 MAXALL AROUNDEXPOSED METALMETALSOLDER MASKOPENINGEXPOSED METALMETAL UNDERSOLDER MASKSOLDER MASKNON SOLDER MASKDEFINED

0.05 MIN
ALL AROUNDSOLDER MASKDEFINEDSOLDER MASK DETAILS
4215162/A 03/2017

NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).

www.ti.com

EXAMPLE STENCIL DESIGN

PM0064A

LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

SYMM
49

64

64X (1.5)
148
64X (0.3)

SYMM
60X (0.5)(11.4)(R0.05) TYP

16

33

32

17
(11.4)SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCILSCALE:8X

4215162/A 03/2017

NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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