APPLICATION NOTE
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onsemi M 1 1200 V SiC
MOSFETs & Modules:
Characteristics and Driving
Recommendations
AND90103/D
ABSTRACTSiC MOSFETs are quickly proliferating in the power
semiconductor market as some of the initial reliability
concerns have been resolved and the price level has reacheda very attractive point. As more devices become available
in the market, it is important to understand boththe commonalities and the differences with IGBTs so thatthe user can get the most out of each device. This paper
provides an overview on the key characteristics of onsemi
M 1 1200 V SiC MOSFETs and how they can be influenced
by the driving conditions. As part of the full wide bandgap
ecosystem that onsemi offers, this article also provides
a guideline on the usage of the NCP51705 an isolated gate
driver for SiC MOSFETs.

The RDS(ON) for a specific required breakdown voltage
considering one part of a MOSFET [1] is inversely
proportional to the product of the mobility times the cube of
the critical breakdown field. Even if SiC has a lower
mobility than silicon, the critical breakdown field is ten
times higher, resulting in a much lower RDS(ON) for a given
breakdown voltage.
The guaranteed maximum operating temperature
for commerciallyavailable
SiC
MOSFETsis
150°C < TJ < 200°C. Comparatively, SiC junction
temperatures as high as 600°C are attainable but mostly
limited by bonding and packaging techniques. This makes
SiC the superior WBG semiconductor material
for high−voltage,high−speed,high−current,high−temperature, switching power applications.

INTRODUCTION
Silicon carbide (SiC) is part of the wide bandgap (WBG)
family of semiconductor materials used to fabricate discrete
power semiconductors. As shown in Table 1, conventional
silicon (Si) MOSFETs have a bandgap energy of 1.12 eVcompared to SiC MOSFETs possessing 3.26 eV.
The wider bandgap energy associated with SiC and (GaN)
Gallium Nitride means that it takes approximately 3 times
the energy to move electrons from their valence bandto the conduction band, resulting in a material that behaves
more like an insulator and less like a conductor. This allows
WBG semiconductors to withstand much higher breakdown
voltages, highlighted by their breakdown field robustness
being 10 times that of silicon. A higher breakdown fieldenables a reduction in device thickness for a given voltage
rating which translates to lower on−resistance and higher
current capability. SiC and GaN each have mobility
parameters on the same order of magnitude as silicon,
making both materials well suited for high−frequency
switching applications. The thermal conductivity of SiC isthree times greater than that of silicon and GaN. Higher
thermal conductivity translates to lower temperature risefor a given power dissipation.

© Semiconductor Components Industries, LLC, 2021

June, 2022 − Rev. 3

Table 1. SEMICONDUCTOR MATERIAL PROPERTIES
PropertiesSi

4H − SiC

GaN

Band Energy (eV)

1.12

3.26

3.50

Electron Mobility (cm2/Vs)

1400

900

1250

Hole Mobility (cm2/Vs)

600

100

200

Breakdown Filed (MV/cm)

0.3

3.0

3.0

Thermal Conductivity(W/cm °C)

1.5

4.9

1.3

Maximum Junction
Temperature (°C)

150

600

400

SiC MOSFETs are commonly available in the rangeof 650 V < BVDSS < 1.7 kV. Although the dynamic
switching behavior of SiC MOSFETs is quite similar
to standard silicon MOSFETs, there are unique gate drive
requirements dictated by their device characteristics thatmust be taken into consideration.

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Publication Order Number:AND90103/D

AND90103/D
Table of Contents
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Static Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
NCP51705 SiC Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

STATIC CHARACTERISTICS
Blocking Voltage Capability

onsemi M 1 1200 V SiC MOSFETs are rated at 1200 V
with a maximum Zero Gate Voltage Drain Current (IDSS)
that is specified in the datasheet of each specific device.
However, the blocking voltage capability of a SiC MOSFET
will reduce with temperature. Taking as an example a 1200
V 20 mW SiC MOSFET power module, the typical deratingin the blocking voltage (VDS) at −40°C is around 11%
compared to the value at 25°C. Even if onsemi devices havetypically some margin, the derating in the VDS should beconsidered during the design, especially if the device will
operate at extremely low temperatures. In Figure 1 thetypical distribution of the breakdown voltages vs.
temperature can be seen.
Important note: These are typical reference values andnot guaranteed, please refer to datasheet values or contact
your local technical support.

means that a SiC MOSFET behaves more like a variable
resistance rather than a non−ideal current source.

Figure 2. Typical Static Characteristics of a SJ
MOSFETID, Drain Current (A)140.00120.00100.00

20 V
19 V
18 V
17 V
16 V
15 V
14 V

13 V
12 V

80.00
Vge = 10 V

60.00
40.00
20.00
0.00

Figure 1. Typical Distribution of VDS vs. Temperature

0.00

TJ = 125°C
2.00

4.00

6.00

8.00

10.00

VDS, Drain−Source Voltage (V)Figure 3. Typical Static Characteristics
of onsemi 1200 V SiC MOSFET M 1

RDS(ON) Characteristics and Recommended VGS to
Drive onsemi M 1 1200 V SiC MOSFETs

One of the key differentiators of a SiC MOSFET
compared to their Si relatives is the dependency of the Drain
to Source Voltage (VDS) vs. the Gate Source Voltage (VGS)
for a specific Drin Current (ID) and in this onsemi 1200 V
SiC MOSFETs are no exception. Figure 2 shows thattraditional Si MOSFETs show a clear transition between thelinear (ohmic) and the active region (saturation). On theother hand, looking at Figure 3, SiC MOSFETs do not show
this behavior and in fact, there is no saturation region, which

One important aspect to consider when selecting theappropriate VGS is that unlike their Si counterpart, SiC
MOSFETs will continue to show a significant improvementin the RDS(ON) when the VGS is increased even at relatively
high voltages. This can be observed in Figure 3: the curve
moves to the left as VGS is increased. If we take look at
Figure 2, the RDS(ON) of the Si MOSFET does not show
a significant improvement when VGS >> VTh, for this reason

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most Si MOSFET are typically driven with a VGS ≤ 10 V. For
this reason, if were to replace a Si MOSFET by a SiC one,a modification of the driving voltage is recommended.
Although 10 V is above the typical threshold voltage ofa SiC MOSFET, the conduction losses at such a low VGS
would most likely lead to a thermal runaway of the device.
This is one of the reasons why a VGS ≥ 18 V is recommended
to drive onsemi 1200 V M 1 SiC MOSFETs.
If the voltage selected is too high, that would introduce
a higher stress in the gate oxide that might lead to long−termreliability issues or the change in critical characteristics suchas a drift in the VTH. During the qualification phase, onsemi
M 1 1200 V SiC MOSFETs have gone through an extensive
set of tests in order to specify a maximum gate voltage of +25 V. As an example, in Figure 4 the results of the positive
gate bias stress test can be observed in green. Compared toother vendors, onsemi M 1 1200 V SiC MOSFETs show agood stability when + 25 V is constantly applied.

can be observed. If we look at the curve at VGS = 15 V, the
NTC is very steep at negative temperatures and remains
dominant up to 50°C approximately which leads to the factthat the RDS(ON) for high temperatures remains in all cases
lower than the RDS(ON) at negative temperatures. If two
components are switched in parallel, like it is the case ofmany of our power modules, one of the components could
end up being overloaded, especially if the device starts at
negative ambient temperatures, leading to a possible
thermal runaway. This phenomenon is corrected if the VGS
is increased. At 18 V, the turning point of the temperature
coefficient is at approximately 25°C and at 100°C theRDS(ON) value is already higher than at −40°C, what makes
it a safe voltage to switch devices in parallel even if they areused in cold environments.

Figure 5. Temperature Dependency of RDS(ON)at Different VGS

In order to calculate the static losses of a SiC MOSFET
device or when different vendors are compared, it isimportant to look at the RDS(ON) of the device not only at
25°C, often used to define the devices for marketing
purposes, but at the RDS(ON) at the target application
temperature. As explained in the previous paragraph, after
a certain turning point, SiC MOSFETs have a PTC. The
benefits of this have been already explained, however, if thecoefficient is very high, the difference between the RDS(ON)at 25°C and real temperature in the application can become
critical, leading to significantly higher conduction losses at
the target operating temperatures. This needs to beconsidered when selecting a SiC MOSFET.
onsemi M 1 1200 V SiC MOSFETs show a good stability
in the RDS(ON) when the temperature is increased. Figure 6
shows the difference at 25°C and 150°C of a 20 mW devicefor different Drain currents (ID). At ID = 50 A, there is a 33%
increase in the RDS(ON), which is enough to ensure goodparallel operation without drastically increasing the static
losses.

Figure 4. Positive Gate Bias Stress Test. Test
Conditions: VGS = 25 V, T = 175C

Even in the best layouts and the least inductive packages,
transient voltage spikes at the gate of the die cannot be
avoided. In order to not surpass the barrier of + 25 V, it isrecommended that a maximum constant voltage of
VGS ≤ 20 V is applied to the MOSFET.
RDS(ON), Temperature Dependency

Another factor to consider is the temperature coefficientof SiC MOSFETs. At low temperatures, a SiC MOSFET
typically presents a negative temperature coefficient (NTC)
until it reaches a certain temperature in which it starts having
a positive temperature coefficient (PTC). This turning point
is influenced by the VGS, At lower VGS the NTC is dominant
up to higher temperatures, while if this voltage is increased,
the turning point will happen at lower temperatures. In
Figure 5 the typical dependency of the RDS(ON) vs.
temperature at different VGS of onsemi M 1 SiC MOSFETs

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design and has done extensive static and dynamic tests of theM 1 1200 V SiC MOSFETs to confirm there is no drift.
Figure 7 shows as example the results of the static negativegate bias and its influence in the VTH. On top of this, burn−intests are conducted in our production line to limit premature
failures.

Figure 6. VDS vs. ID at Different Temperaturesof a 1200 V, 20 m SiC MOSFET Power Module
Selecting the Negative Gate Bias Voltage

So far, the different parameters to define the positive gatebias have been discussed. The conclusion is that the VGS for
onsemi M 1 1200 V SiC MOSFETs should be set to + 18 V
≤ VGS ≤ 20 V during static operation and that it should notsurpass + 25 V in the dynamic transients, but how to define
the negative gate bias? Certainly, this value should be low
enough to guarantee that the device switches off properly,
but also to avoid a parasitic turn on in those topologies thatare susceptible to shoot−through like a half−bridge.
Currently two types of SiC MOSFETs can be found in themarket in terms of VTH, high threshold voltage SiC
MOSFETs with typical values above 3.5 V and lower
threshold voltage SiC MOSFETs with typical values below
3 V to 3.5 V. onsemi M 1 1200 V SiC MOSFETs belong to
the second group with a typical VTH values in the range of
2.75 V (see datasheet for specific values of each device).
This value varies with the temperature and could go as low
as 1.8 V and as high as 4.3 V.
In those applications in which shoot−through could
happen a negative gate bias of − 5 V is recommended to haveenough safety margin to avoid parasitic turn on, especiallyat high switching frequencies. Setting the negative VTH to− 5 V should also give enough margin to avoid transient gate
voltages below the minimum limit which is set at −15 V.
In those cases in which the risk of shoot−through isnon−existing, i.e. a booster topology, or has been reduced by
one of the many existing techniques, i.e. decoupling theoutput of a half−bridge with a parasitic inductance, then thenegative gate bias could be increased to any safe value goingas high as 0 V. This has other effects on the performance ofthe device that will be discussed in the next chapter.
Just like with the positive gate bias, having a very low
negative gate bias might trigger defects of the SiC crystal,leading to reliability issues or the modification of key
parameters such as a drift in the VTH or the RDS(ON), this isespecially critical when talking about negative gate bias andthe currently available SiC trench MOSFETs. In order toprevent these issues, onsemi has considered this in the

Figure 7. Negative Gate Bias Stress Test.
Test Conditions: VGS = −20 V, T = 175 C
Body Diode Forward Voltage (Vf) vs. VGS

The body diode of SiC MOSFETs is well−known forhaving a high forward voltage compared to other types ofdiodes. This characteristic should be considered when using
a SiC MOSFET and in general, it is not recommended to use
it outside the dead time in many topologies to avoid highlosses. One effective way to reduce the usage of the body
diode is to activate the channel of the MOSFET whenreverse conduction is needed. By doing this the losses will
be drastically reduced.
However, in those topologies in which a dead time isneeded before activating the channel, i.e. a typicalhalf−bridge in synchronous rectification, the de−activationof the body diode becomes ineffective as additional devices
and/or modifications in the current path would be required.
Moreover, even taking many precautions the utilization of
the body diode during the dead time might not be fully
avoided. In case of onsemi M 1 1200 V SiC MOSFETs, thebody diode can be used without a penalty in reliability ora big drift in the main parameters of the MOSFET.
Having this in mind, it is important to know that the VGS
will have an influence in the static performance of the body
diode. Figure 8 shows the Vf dependency of onsemi M 1
1200 V SiC MOSFET’s body diode vs. the forward current(If), when a different VGS is applied. As it can be observed,
the Vf increases slightly when the negative gate bias is
reduced. This graphic is a bit misleading as it could bring theuser to the conclusion that setting a VGS to 0 V is the bestsolution. However, the reason for this lower Vf is that thechannel of the MOSFET turns slightly on, so what it looks
externally like a lower Vf is actually the channel taking partof the current from the body diode. When the diode stops
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on the switching topology, this could have a negative effectin the total losses with an increased leakage. On top of this,and as it will be explained later on, at 0 V the switchinglosses will increase drastically. This phenomenon iscommon in SiC technologies [2] and can be avoided by
reducing the VGS to for instance −5 V.

for a 40 mW device. This has to be considered when
designing the gate driver circuit to avoid unwanted parasitic
turn on. Once again, the data should be considered at the realapplication temperature. For instance, a 2 V voltage spike at
the gate at room temperature is less likely to trigger aparasitic turn on than at 125°C.

Figure 8. Vf vs. If for Different VGS in a 20 m 1200 V
SiC MOSFET Module

Figure 9. Typical VTH Values vs. Temperature
in a 40 m, 1200 V SiC MOSFETIn order to keep a safety margin in topologies sensitive toparasitic turn on, like a half−bridge. It is recommended to set
a negative VGS when the device is turned off.

VTH, Temperature Dependency

During previous chapters, the drift in the VTH has beenpresented, when both a positive or negative gate bias is
applied. An additional factor that influences the VTH is thetemperature. Like all MOSFETs, onsemi M 1 1200 V SiC
MOSFETs, have a negative temperature coefficient. The
consequence is that the VTH could be reduced from a typicalvalue around 2.6 V at 25°C to as low as 1.8 V at 175°C.
Figure 9 shows typical VTH values at different temperatures

DYNAMIC CHARACTERISTICS
For the characterization of the dynamic characteristics ofonsemi M 1 SiC MOSFETs, a 20 mW half−bridge moduleusing two 40 mW devices in paralleled has been used. Figure
10 illustrate the test set−up.

Figure 10. Block Diagram of Test Setup for the Dynamic Characterizationwww.onsemi.com
5AND90103/D
Figure 11 shows the turn on waveform of the mentioned
test device. The magenta curve is the drain voltage of the low
side MOSFET. The green curve is the current through thelow side MOSFET.
The switching sequence starts when the gate driver isswitched to 18 V at time t = 0. After an initial ramp up, thegate drive current starts off high and reduces as the gate
voltage increases. The gate voltage rises until the thresholdvoltage is reached. The current increases until it reaches thecurrent flowing through the diode: the load current +reverse recovery current + capacitive current.
The plateau voltage for a SiC MOSFET is highly
dependent on load current. In Figure 11, the plateau voltage
is approximately 10 V. The VGS for a given ID is given by
the following equation.

ID

VDD
D
CDD
RHI

CGD
CDS

RGI

RGATE
G

CGS
S
VEE

Figure 12. SiC MOSFET Source Current

Figure 13 shows the switch off waveform for a 20 mohm,
1200 V half−bridge module using two 40 mohm devices.
The switching sequence starts when the gate driver isswitched to −5 V at time t = 0. After an initial ramp up, thegate drive sink current starts off high and reduces as the gate
voltage increases. The gate voltage falls until the plateau
voltage is reached. The plateau is lower than during turn ON
as there is no reverse recovery current. The voltage rises as
the QGD is discharged. Some of the drain current is used todischarge the non−linear COSS capacitance which shows up
as a negative slope in the drain current.
The gate voltage overshoot is caused by the loop
inductance in the circuit: nearest capacitor to the DC bus –DC + contact of module – DC − contact of module – backto the DC bus capacitor. The connection between the moduleand the capacitor should be made as low inductance aspossible to minimize the ringing voltage.
When the peak voltage is reached, the gate driverdischarges the gate from the plateau voltage to the thresholdvoltage, bringing the current down to zero. The gate drivercontinues to discharge the gate until it reaches −5 V.

iD + k(VGS * VT) 2

So the slope will vary with time as follows:
diD + 2k(vGS * VT) @ d(vGS * VT)dt
dt

As the gate voltage changes approximately linearly withtime, di/dt changes linearly with time. The voltage drop on
Vds caused by L di/dt linearly decreasing with time starts
from when the current reaches the threshold voltage andfinishes when the current peak is reached.
The gate current and voltage reaches the plateau voltage.
The gate current charges up the QGD and the drain voltage
decreases to almost zero.
The drain current falls towards the load current with someringing.
Finally, the gate voltage rises up to 18 V. The drain voltage
reduces to the load current times RDS(ON) at 18 V.

Figure 11. Turn On Waveform for 20 mohm, 1200 V
Half Bridge Module

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Figure 15. Switching Losses vs. Tj in a 20 m 1200 V
SiC MOSFET Module

Figure 13. Turn OFF Waveform for 20 mohm, 1200 V
Half Bridge Module

Switching Losses Scaling with Drain Current (ID)

ID

VDD

The switching losses of any MOSFET are by definition
the result of the time integral of voltage multiplied by thecurrent during any of the switching event.

D
CDD
RLO

CGD

E SW +

CDS

RGI

RGATE

ŕ V (t) @ I (t)dt
t

G

DS

D

0

Therefore, it is to be expected that the losses increase as
the current increases. However, comparing the behavior of
M 1 1200 V SiC MOSFETs to an IGBT there are somedifferences. As it can be observed in Figure 16, the behavior
of EON versus ID for a 20 mW, 1200 V SiC module inhalf−bridge configuration is linear, these losses will dependon the recovery of the corresponding diode in thecommutation loop. The recovery losses of the body diodealso behave in a linear mode. On the other hand, the EOFF
losses start with a quadratic increase until a certain point inwhich they also become linear.

CGS
S
V

Figure 14. SiC MOSFET Sink Current
Switching Losses Scaling with Temperature

Just like in the static characteristics, the temperature atwhich the SiC MOSFET operates will have an impact in theswitching performance. However, as it can be observed in
Figure 15, EON and EOFF show nearly a flat temperature
coefficient and the switching performance at 150°C will bevery close to the characteristics at 25°C. This is however not
the case for the reverse recovery losses (Err), which are
negligible at 25°C, but as the temperature increases, theymight reach a point in which they should be considered in theloss calculation. For these reasons as already explained in
the previous chapter, it is crucial to consider any parameterat the real working temperature and not just at 25°C.
In case of the Err it is worth noticing that according to Lutz
et. al [3] a significant portion of these losses are capacitive
and not pn junction losses. These capacitive losses will look
like losses on an oscilloscope but will not cause heating in
the body diode. The effect of these losses and magnitude are
dependent on voltage and current, but could represent asmuch as 40% of the Err losses shown in a typical datasheet.
That is why, taking directly the Err losses from the datasheet
is a conservative approach. The overall losses can then only
be measured by comparing the system input power and thesystem output power in the real application.

Figure 16. Switching Losses vs. ID Characteristics ina 20 m, 1200 V SiC MOSFET Module

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Switching Losses vs. Drain Source Voltage (VDS)

Another direct factor in the switching losses is as
explained in the previous point the VDS in this case, as
shown in Figure 17 the EON and EOFF and Err behave ina linear manner although with a different slope.

Figure 18. Switching Losses vs. RG in a 20 m,1200 V SiC MOSFET Module

The obvious conclusion is to keep the RG as low as
possible. On the other hand, any circuit has parasitic
inductances and capacitances that might lead to a criticalvoltage overshoot or oscillations that generate potential
Electromagnetic Interferences (EMI) if a device is turned on
too quickly, this does not only concern the main current
commutation path, but also the gate circuit. On top of this,in some applications the dV/dt might be limited for safety
reasons. For these reasons, it is important that the speed ofthe device can be easily adjustable with the RG or eventuallya gate capacitance (CG), although the latter is notrecommended as it could create severe oscillations in thegate. Figure 19 shows the influence that the RG has on thedV/dt in a 1200 V, 20 mW half−bridge module using onsemi
M 1 SiC MOSFETs. The graphic shows that themodification in the RG enables the user to have a strong
influence in the dV/dt, making it possible to adapt theswitching behavior to the requirements of the circuit and theapplication. In this way, each user can easily find the best
trade−off between switching losses and switching speed fortheir own application.

Figure 17. Switching Losses vs. VDS in a 20 m,1200 V SiC MOSFET Module
Gate Resistance (RG) Impact on the Switching
Performance

The controllability of a switching device by externalmeans is a key factor in the design of any circuit. In case ofa MOSFET or an IGBT, despite being voltage−controlled
devices, one of the most common ways to influence theirswitching behavior is to modify the external gate resistance
RG that, among other things, regulates how quickly thedifferent capacitances involved in the switching event will
be charged or discharged. Thus, directly influencing theswitching times as well as di/dt or dv/dt.
In a first stage, the influence of the RG on the losses needs
to be considered when selecting the appropriate value.
A higher RG will slow down the device leading to higher
EON and EOFF losses. Figure 18 shows the behavior of theswitching losses vs. RG in a 20 mW, 1200 V SiC MOSFET
module with M 1. The positive effect of a higher RG is thedecrease of the Err losses due to the smoother behavior of the
MOSFET body diode at slower switching speeds.
However, this does not compensate the increase in the ON
and OFF losses.

Figure 19. dV/dt Controllability with RG in a 20 m,1200 V SiC MOSFET Module

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Effect of VGS on the Switching Losses

Looking at the negative gate bias, previously it was
highlighted the importance of using a negative voltage tofully close the channel during when the body diode issupposed to conduct. This will also have an impact on theswitching losses. As it can be observed in Figure 22, while
the negative gate voltage has nearly no impact on the EONor Err losses, the EOFF losses can be drastically impacted.
While the difference between – 5 V and −3 V is around 25%,
if a 0 V negative gate bias is used, the EOFF losses could
double.

During the first chapters of this application note, theeffects of the VGS over the static characteristics of onsemi
M 1 1200 V SiC MOSFETs were discussed. The conclusion
was to use the device at least at + 18 V and that a higher
voltage up to + 20 V could be beneficial. If the switching
performance is now being considered, the conclusion will be
the same. Figure 20 shows the dependency of the switchinglosses vs. VGS. The EOFF is independent of the positive VGS: in the graph, the three EOFF curves overlap. On the other
hand, the VGS will have a significant impact on the EON and
Err behavior. If the VGS is increased and the same RG is used,the current charging the CGD and CGS. The consequence will
be a faster switching of the device thus reducing the EON
losses, this has the opposite effect on the Err as the increased
speed will induce higher recovery losses in the body diodeof the opposite MOSFET.

Figure 22. Influence of Negative VGS over Switching
Losses in a 20 m, 1200 V SiC MOSFET ModuleThis effect can be also observed in Figure 23 where thetotal losses are shown.

Figure 20. Influence of Positive VGS over Switching
Losses in a 20 m, 1200 V SiC MOSFET Module

If the total losses are considered, like shown in Figure 21,
the decrease in EON losses at higher VGS overcompensates
the increase in the Err, making it more efficient to switch thedevice at a higher VGS. Of course other considerations suchas EMI or dV/dt should be consider as well.

Figure 23. Total Losses for Different VGS in a 20 m,1200 V SiC MOSFET Module
Short Circuit with Stand Time (SCWT)

In some applications, the SCWT of a device is an
important requirement during the selection process. Thisfeature does not come without a penalty though. Having alonger SCWT will have an impact on the static and dynamic
performance. That is why in many devices in order toachieve a better performance this feature is neglected.

Figure 21. Total Losses for Different Positive VGS
in a 20 m, 1200 V SiC MOSFET Module

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In case of onsemi 1200 V M 1 SiC MOSFETs, a certain
design margin has been left to provide short circuitwithstand capability. The time that the device will be able tosurvive a short circuit will depend on many factors, the mostimportant ones being the VDS and the reference temperature
at which the device might suffer the short circuit event. Likein many other parameters discussed in this application note,
it is important to look at the characteristics at the righttemperature, while the difference between 125°C and 150°C
is not significant, the SCWT of the SiC MOSFET could besignificantly better at 25°C. In order to provide relevant datafor common operation temperatures, a starting temperatureof 150°C has been selected for this document. Figure 24
shows the typical SCWT for different VDS.
Important note: These are typical reference values andnot guaranteed, please refer to datasheet values or contact
your local technical support.

Dynamic Characteristics of the Body DiodeAs mentioned in previous chapters, even if it is notrecommended to use the body diode of the SiC MOSFET
due to its high conduction losses, this cannot always be
avoided. One possibility to improve the total losses was asmentioned to activate the channel of the MOSFET to
improve the static behavior, this will however have little
influence on the dynamic performance. An additional
method would be to have an external SiC diode in parallelto the SiC MOSFET. However, in order to fully disable thebody diode, this should be decoupled from the maincommutation path as shown in Figure 26 for a half−bridge.

Figure 26. Half−bridge with Split Output

This split introduces not only the additional SiC diode, butalso adds complexity in the layout. Comparing the dynamic
behavior of the external SiC diode with the body diode,shown in Figure 27, it can be observed the external SiC diodedoes improve the reverse recovery behavior. This
improvement could be marginal though; especially taking
into account that part of the body diode losses arenon−dissipative. Therefore, the user needs to consider
whether it pays off to add this additional component with thecorresponding increase in cost and complexity.

Figure 24. Short Circuit with Stand Time vs. VDS
in a 20 m, 1200 V Half−bridge SiC MOSFET
ModuleFigure 25 shows the short circuit behavior of a realmeasurement in a 20 mW, 1200 V SiC MOSFET module at
150°C.

Figure 27. Recovery Behavior of an External SiC
Diode (Dashed Line) vs. the Body Diode of the SiC
MOSFET (Continuous Line)

Figure 25. Short Circuit Behavior in a 20 m 1200 V
Half−bridge SiC MOSFET Module

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10AND90103/D
Effects of Adding a Snubber Capacitor Inside thePower Module

experienced designer will not be able to avoid certain
parasitic intrinsic to the package and a the minimum PCB
rooting required.
Figure 28, shows the schematic of the main components
in the critical switching loop in a standard half−bridge
configuration. In order to reduce the length of the criticalloop, a low ESR capacitor should be placed as close as
possible to the module. However, this will not prevent from
including in the loop the inductance of the pins, the PCB
trace and the leads of the capacitor.

The stray inductance in any design will play a key role inthe switching performance of the device, not only in termsof efficiency, but also contributing to unwanted behaviors,such as ringing or high voltage overshoot. Considering that
SiC devices are mainly used in fast switching applications,the risk to have unwanted effects of the stray inductancebecomes even higher. That is why one of the firstrecommendations in any design is to keep the parasitic
inductance as low as possible. Nevertheless, even the mostFigure 28. Schematics of a Half−bridge Module with External Capacitor

In order to reduce even more the length of the critical loop,
an additional capacitor could be integrated inside to module.
This is illustrated in Figure 29. In that way, we can reduceeven further the parasitic inductance by eliminating to someextent the effects of the pin, trace and lead inductances. The
size of the integrated capacitor is limited by the space
available inside the module, for instance for this study a
100 nF capacitor has been used.

Figure 29. Schematics of a Half−bridge Module with Integrated Capacitor
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11

AND90103/D
The result of reducing the inductance of the critical loop
will be an improvement on the switching behavior. In thefirst place, and as it can be seen in Figure 30, the voltage
overshoot at turn−off can be reduced from nearly 150% tobarely 120%.

An immediate consequence of this reduced voltage
overshoot will be a reduction in the Eoff losses as indicatedin Figure 31. On the other hand as we increase the current,
the Eon losses might increase. In any case, the total losses
will see an improvement in the common current capabilityof the device.

Figure 30. Turn−off Behavior of a Half−bridge with
Integrated Versus External Capacitor

Figure 31. Switching Losses with and without
Integrated Capacitor

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AND90103/D
NCP51705 SiC GATE DRIVER
The NCP51705 is a SiC gate driver that includes a highlevel of flexibility and integration making it fullycompatible with any SiC MOSFET in the market. The
NCP51705 top level block diagram, shown in Figure 32,
includes many basic functions common to what might be
expected from any general purpose gate driver, including:
1. VDD positive supply voltage up to 28 V
2. High peak output current of 6 A source and 10 A
sink
3. Internal 5 V reference made accessible for biasing
5 V, low−power loads up to 20 mA (digitalisolator, opto−coupler, μC, etc)
4. Separate signal and power ground connections
5. Separate source and sink output pins
6. Internal thermal shutdown protection
7. Separate non−inverting and inverting TTL, PWM
inputs

NCP51705
DESAT Function
200 μΑDESAT 22

23

100 k
Q S
Q R
1.25 VDESAT /CURRENT

25 μA
UVSET 24

TSD
5V_OK
VDD_OK
VEE_OK

IN+

1

IN−

2

20

DESAT
/CS
VDD

19

VDD

22

UVLO

DESAT_FLT
RUN_OKVDD UVLOVEE UVLO
V5V_OK

INPUT
LOGIC

XEN 3

17 OUTSRC
14 OUTSNK
13 OUTSNK
16 PGND

CHARGE PUMP
POWER STAGE

7

8

VCH

C+

C−

VEE

9

10

PGND

6

12

PGND

5

VEESET

15 PGND
11VEE

CHARGE
PUMP REG CPCLKSGND 4

I
500ns
Timer

18

OUTSRCSiC
Drive

OUTSNK

17

VDS
Q1

14
13

During the time that Q1 is off several hundred volts canappear across the drain−source terminals. Once Q1 is turned
on, the drain−source voltage rapidly falls and this transition
from high−voltage to near zero voltage is expected tohappen in less than a few hundred nano−seconds. During theturn−on transition, the leading edge of the DESAT signal isblanked by a 500−ns timer, consisting of a 5−Ω, low
impedance pull−down resistance. This allows sufficient
time for VDS to fall while at the same time ensuring DESAT
is not inadvertently activated. After 500 ns, the DESAT pin
is released and the 200−μA current source provides aconstant current through R1, D1 and the SiC MOSFET
on−resistance. During the on−time, if the DESAT pin rises
above 7.5 V, the DESAT comparator output goes HIGH
which triggers the clock input of an RS latch. Such a fault
will automatically terminate the trailing edge of the Q_NOT
output on a cycle−by−cycle basis. The gate drive to the SiC
MOSFET is thereby effectively reduced by an amount oftime proportional to the de−saturation fault time.
The 200−μA current source is sufficient to ensure
a predictable forward voltage drop across D1 while also
allowing the voltage drop across R1 to be independent of
VDS during the on−time of the SiC MOSFET. If desired,
DESAT protection can be disabled by connecting the
DESAT pin to ground. Conversely, if the DESAT pin is left
floating, or R1 fails open, the 200−μA current source
flowing through the 20−kΩ resistor, puts a constant 4 V on
the non−inverting input of the DESAT comparator. Thiscondition essentially disables the gate drive to the SiC

18 OUTSRC

DRIVER
LOGIC
&
LEVEL
SHIFT

D1

Figure 33. NCP51705 DESAT Function

RUN

PROTECTION
LOGIC

20 k
Remove(Option)5IN

21 SVDD

5V REG

R1

3.3 V

NCP51705
V5V

VDD

Figure 32. NCP51705 SiC Gate Driver Block Diagram

In addition, the NCP51705 is differentiated by several
unique features (listed at the beginning of section Discrete
SIC Gate Drive in TND6237/D ) necessary for designing a
reliable SiC MOSFET gate drive circuit using minimal
external components. The advantages of the NCP51705
distinguishing features are detailed in the following section.
Over−Current Protection − DESAT

The implementation of the NCP51705 DESAT function
can be realized using only two external components. As
shown in Figure 33, the drain−source voltage of the SiC
MOSFET, Q1 is monitored via the DESAT pin through R1
and D1.

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13

AND90103/D
MOSFET. Some applications may prefer to sense the draincurrent using a current sense transformer and drive the
DESAT pin externally. In this case the NCP51705 includes
an IC metal option to remove the 20−kΩ resistor, allowing
the DESAT pin to be used as a traditional pulse−by−pulse,over−current protection function.
The voltage on the DESAT pin, VDESAT, is determined byequation (1) as:
V DESAT + (200 mA

R 1) ) V D1 ) (I D

5

V DESAT ) V D * (I D1
200 mAR DS)

VEESET
VDD

GLDO

LDO
9V
6

CCH

VCH
P

P

N

N

ID

R DS) (eq. 1)

SiC
Drive

After assigning the maximum value for ID (plus allowing
any additional design margin) R1 and ID are selected suchthat VDESAT < 7.5 V. Rearranging equation (1) and solving
for R1 gives:
R1 +NCP51705
VEE Charge
Pump(SINK)OUTSNK
C

C

7

8

CF

(eq. 2)

In addition to setting the maximum allowable VDESAT
voltage, R1 also serves the dual purpose of limiting the
instantaneous current through the junction capacitance of
D1. Because the drain voltage on the SiC MOSFET sees
extremely high dV/dt, the current through the p−n junction
capacitance of D1 can become very high if R1 is not sized
appropriately. Therefore, selecting a fast, high−voltage
diode with lowest junction capacitance should be a priority.
Typical values for R1 will be near the range of5 kΩ< R1 < 10 kΩ but this can vary according to the ID and
RDS parameters of the selected SiC MOSFET. If R1 is muchsmaller than 5 kΩ, the instantaneous current into the DESAT
pin can be hundreds of milliamps. Conversely, if R1 is muchlarger than 10 kΩ, a RC delay ensues as a product of R1 andthe junction capacitance of D1. The delay can be on the orderof 100 μs, resulting in an additional delay time responding
to a DESAT fault.

11

VEE

14

Q1

VDS

13

12

CVEE

Figure 34. NCP51705 VEE Charge Pump

An external flying capacitor, CF, is connected between the
midpoints of each leg of the bridge as shown. The switch
timing is such that whenever the two upper PMOS devices
are conducting simultaneously, VDD appears across CF.
Similarly whenever, the two lower NMOS devices are
conducting simultaneously, −VEE appears across CF. The
switching frequency is internally set at 390 kHz, with thetwo upper PMOS devices switching asynchronous withrespect to the two lower NMOS devices. A 290 kHz, IC
metal option is also available for applications desiring alower charge pump switching frequency.
VEE is regulated to the voltage set at VCH which isdetermined by the internal low dropout regulator (LDO)
voltage, programmable by VEESET. The voltage present at
VEESET varies the gain (GLDO) seen by the internal LDO.
If VEESET is left floating (a 100−pF bypass capacitor fromVEESET to SGND is recommended), then VEE is set toregulate at −3 V. For a −5−V VEE voltage, the VEESET pinshould be connected directly to V5V (pin 23). If VEESET
is connected to any voltage between 9 V and VDD, then VEE
is clamped and set to regulate at the minimum charge pumpvoltage of −8 V. The charge pump starts when VDD > 7.5 V
and the VEE voltage rail includes an internally fixed UVLO
set to 80% of the programmed VEE value. Since VDD and
VEE are each monitored by independent UVLO circuits, theNCP51705 is smart enough to realize when both voltage
rails are within limits deemed safe for a given SiC MOSFET
load.
Alternatively, 0 V < OUT < VDD switching can beachieved by disabling the charge pump entirely. WhenVEESET is connected to SGND the charge pump is
disabled. With the charge pump disabled and VEE tied

Charge Pump – VEE (VEESET)The NCP51705 operates from a single, positive supply
voltage. Operating from a single VDD supply voltage
implies the negative VEE voltage must be generated from thegate driver IC. The use of a switched capacitor charge pumpis a natural choice for producing the required negative VEE
voltage rail. There are many different options forarchitecting a charge pump. The main challenges aremaintaining accurate voltage regulation during transientconditions, switching at a frequency to decrease the size ofcapacitors and minimize external component count, thereby
reducing cost and increasing reliability.
As can be seen from the charge pump functional block
diagram shown in Figure 34, only three external capacitors
are required to establish the negative VEE voltage rail. The
charge pump power stage essentially consists of two PMOS
and two NMOS switches arranged in a bridge configuration.

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AND90103/D
have a dedicated, housekeeping, bias supply while others
might rely on a VDD bootstrapping technique similar to
Figure 36.
The NCP51705 addresses this need through a
programmable UVLO turn−on threshold that can be set witha single resistor between UVSET and SGND. As shown in
Figure 35, the UVSET pin is internally driven by a 25−μA
current source with a series gain of 6.
The UVSET resistor, RUVSET, is chosen according toa desired UVLO turn−on voltage, VON, as defined inequation (3).

directly to PGND, the output switches between 0 V < OUT< VDD. It is important to note that whenever VEESET is tied
to SGND, VEE must be tied to PGND. During this mode ofoperation the internal VEE UVLO function is also disabledaccordingly.
Another possible configuration is to disable the charge
pump but allow the use of an external negative VEE voltage
rail. This option permits –VEE < OUT < VDD switching witha slight savings in IC power dissipation, since the charge
pump is not switching. With VEESET connected to SGND,
an external negative voltage rail can be connected directly
between VEE and PGND. A word of caution, since VEESET
is 0 V, the internal VEE UVLO is disabled and therefore the
NCP51705 is unaware if the VEE voltage level is within the
expected range.
This simple VEESET adjustment enables the highest
degree of flexibility using the fewest external components
while meeting the broadest range of SiC MOSFET voltage
requirements. For convenience, the configurability of
VEESET is summarized in Table 2.

R UVSET+

V5V
25 μΑ

VEE

(UVLO)

VDD

9 V < VEESET < VDD−8 V−6.4 V

−5 V

−4 V

V5V

GUVSET=6

VEE

COMMENTOPEN

Add CVEE≤100 pF
from VEESET to
SGND

−3 V

−2.4 V

GND

Remove CVEE andconnect VEE to PGND

0V

NA

GND

Connect VEE toexternal negative
voltage supply

−VEXT

NA

(eq. 3)25 mA

NCP51705
UVSET Function

Table 2. SEMICONDUCTOR MATERIALPROPERTIESVEESET

V ON
6

UVLO

UVSET

24

RUVSET

Figure 35. NCP51705 UVSET Programmable UVLO

The value for VON is typically determined from the SiC
MOSFET output characteristic curves, such as thosehighlighted in Figure 1 from TND6237/D. Because theon−resistance of a SiC MOSFET dramatically increases
even for a slight decrease in VGS, the allowable UVLO
hysteresis must be small. For this reason, the NCP51705 has
a fixed 1−V hysteresis so that the turn−off voltage, VOFF, isalways 1 V less than the set VON.
For power supplies that include a dedicated housekeeping
bias supply, VDD is assumed to be above the desired VON
threshold before the power system initiates soft−start or
restart due to a fault recovery. For such systems, having
a 1−V UVLO hysteresis is desirable and should not have any
impact due to start−up considerations. However, somepower systems start from a high−voltage and then rely on
VDD from a bootstrap winding as shown in Figure 36.

Programmable Under Voltage Lockout − UVSETUVLO for a gate driver IC is important for protecting the
MOSFET by disabling the output until VDD is above aknown threshold. This not only protects the load but verifies
to the controller that the applied VDD voltage is above theturn−on threshold. Because of the low gm value associatedwith SiC MOSFETs, the optimal UVLO turn−on threshold
is not a “one size fits all.” Allowing the driver output toswitch at low VDD can be detrimental for one SiC MOSFET
but may be acceptable for another depending onheat−sinking, cooling and VDD start−up time. The optimal
UVLO turn−on threshold can also vary depending on how
the VDD voltage rail is derived. Some power systems may

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AND90103/D
HV

is allowed to discharge over a wider ΔV (17 V − 11 V) anda much smaller capacitor value can be used. Given the same
1 mA, Δt = 3 ms and allowing ΔV = 6 V, the required CVCC
capacitor value is reduced to 500 nF; a reduction by a factorof 6. However, the incurred penalty can be quite severe as the
SiC MOSFET will be switching with VGS = 11 V. Clearly,
having the NCP51705 biased prior to start−up is thepreferred approach.

VCC/VDD

HV

VCC

PWM
17 VON9 VOFF

VDD
NCP51705
VON<VON(PWM)
VOFF=VON−1 V Q1

CDigital Synchronization and Fault Reporting – XEN

The XEN signal is a 5 V digital representation of theinverse of VGS. For the purpose of reporting driver “status”,
it is considered more accurate that the PWM input since it isderived from the SiC gate voltage, propagation delays are
greatly decreased. The intent of this signal is that it can beused in half−bridge power topologies as a fault flag andsynchronization signal as the basis for implementing crossconduction (overlap) protection. Whenever XEN is HIGH,
VGS is LOW and the SiC MOSFET is OFF. Therefore if
XEN and the PWM input signal are both HIGH, a fault
condition is detected and can be digitally assigned to takewhatever precautions might be desired.

Figure 36. PWM Bootstrap Start−Up Example

A PWM controller with high−voltage (HV) start−up
capability and fixed UVLO thresholds of VON = 17 V and
VOFF = 9 V is shown. As HV is applied, the internal pass
switch opens when HV = VON = 17 V and the PWM
controller draws start−up current from CVCC. During thistime, CVCC is discharging and Q1 must begin switching tobuild up voltage in the transformer bootstrap winding. This
imposes a restriction on the allowable VON that can be
programmed from RUVSET. UVSET must be set to a valueless than the UVLO VON of the PWM controller. These
start−up details are further illustrated in Figure 37 where thePWM voltage thresholds are shown in blue and the
NCP51705 in red.
V

Packaging

WBG semiconductors have enabled high−voltage
converters to operate much closer to low−voltage (less than
100 V) switching frequencies. For low−voltage converters,
the evolution of semiconductor packaging played a key role
toward the modern achievement of switching performance
seen today. Dual−sided cooling, clip bonding, thermallyenhanced power packages and lower inductance, leadlesspackages are a few examples of silicon MOSFET packaging
advancements. Similarly, the size of gate driver IC packages
has undergone a tremendous size reduction. Shorter die tolead, bond wire connections combined with molded leadlesspackages (MLP) have been essential for minimizing
parasitic inductance from the driver side. The co−packagingof the driver and MOSFET (DrMOS) is the latest step
toward reducing parasitic inductance, raising efficiency andreducing board area. Advancements such as DrMOS areachievable because of the comparable low−voltages
involved.
In the high−voltage converter realm, minimum spacing
requirements such as creepage and clearance have left highperformance SiC MOSFETs stuck in low−performanceTO−220 and TO−247 type packages. These packages arewell established and have long been an industry standard.
They are well suited for industrial applications, robust andeasy to heat sink but have higher parasitic inductance due totheir long leads and internal bond wires. SiC MOSFETs
have now subjected these parasitic inductances to thermal
stresses, frequencies and dV/dt rates never before
envisioned with high−voltage, silicon transistors. Suffice tosay, SiC is providing the stimulus for rethinking
high−voltage discrete packaging.

V PWM(MAX)27

VSIC(MAX)
VBOOT(REG)2220
V PWM(ON)1716

17 VON/16 VOFF
12 VON /11 VOFF

12
11
9

V BOOT(MIN)0t1

V PWM(OFF)t2tFigure 37. Bootstrap Start−Up Timing

For the purpose of switching the SiC MOSFET with thehighest possible VGS, it is desired to set VON as close to the
UVLO turn−on of the PWM controller as possible. The trade
off in doing so means ΔV = 1 V during Δt (t2−t1). The
discharge of CVCC is very shallow so a large capacitor value
is required. For example, assuming the start−up current to be
1 mA, Δt = 3 ms and ΔV = 1 V, a 3−μF capacitor for CVCC
is required. Conversely, if VON is set to 1 V above theminimum bootstrap discharge voltage, VBOOT(MIN), CVCC

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AND90103/D

IN+

1

18 OUTSRC

2

17 OUTSRC

XEN

3

SGND

4

15 PGNDVEESET 5

14 OUTSNKVCH

13 OUTSNK

25
20

VEE 1215

VDD (V)VEE 11

PGND 10

9
PGND

8

7

6

C+

NCP51705, VDD vs IDD
I_V5V = 0 mA, OUT_Load = 3 Ω + 4.99 Ω + 2.2 nF

16 PGND

NCP51705(Top View)

C−

applied (non−switching), VDD(UVLO) = 12 V and no load on
the V5V regulator. For 7 V < VDD < 22 V, IDD was measured
to be 0.6 mA < IDD < 2.3 mA. The flat line across the middle
is a ~1−mA increase in IDD current when VDD crosses the
UVLO threshold.
The red trace represent the case where a 100 kHz, 50%
pulsed input was applied to IN+ while the internal charge
pump is disabled. A 4.99 Ω + 2.2 nF load was used which isthe equivalent input for a typical SiC MOSFET. The externalsource and sink resistance was 3Ω.. For 12 V < VDD < 22 V,
IDD was measured to be 3.7 mA < IDD < 5.5 mA.

19 VDD

20 VDD

21 SVDD

22 DESAT / CS

23 V5V

24 UVSET

Although not the case with discrete components, a SiC
gate driver is able to take full advantage of the same
packaging advancements used with drivers intended forlow−voltage converters. The NCP5170 die is packaged intoa 24 pin, 4 × 4 mm, thermally−enhanced MLP as shown in
Figure 38.

10

Figure 38. NCP51705 24 pin, 4  4 mm, MLP
Packaging and Pin Out

Non− Switching
0 V<OUT<VDD, 100 kHz, 50%

50

All the high−current, power pins are doubled and locatedon the right−half of the IC. In addition to doubling the pins,
each doubled pin connects to the die through internal doublebond wires for achieving the lowest possible inductance. All
low−power, digital signals are single pins only and arelocated on the left−half of the IC, providing a convenient,direct interface to the PWM or digital controller.
The bottom of the NCP51705 package consists of anelectrically isolated, thermally conductive, exposed pad.
This pad is not connected to PGND or SGND but is intended
to be connected through thermal vias to an isolated copper
PCB land for heat−sinking.
If thermal dissipation becomes a concern, specificattention should be paid to four dominant power dissipation
contributors:
1. OUTSRC and OUTSNK losses associated withdriving the external SiC MOSFET. These are gatecharge related losses proportional to switchingfrequency. Reducing switching frequency will
decrease power dissipation
2. LDO between VDD and V5V, capable of sourcing
up to 20 mA. Do not load the V5V any more thanbiasing a digital isolator or optocoupler
3. LDO between VDD and VCH which is part of theinternal charge pump
4. Internal charge pump power switches which canbe disabled and replaced with an external negative
bias, as mentioned in section Charge Pump–VEE

0.0

1.0

2.0

3.0

4.0

5.0

6.0

IDD(mA)

Figure 39. VDD versus IDD,
Non−Switching versus Switching

The start−up waveform shown in Figure 40 shows IN +appearing prior to VDD. VDD is rising from 0 V to 20 V, withUVSET = 2 V (not shown) which equates to VDD(UVLO) =12 V. VEE is set to regulate at −5 V with VEESET = V5V (notshown) which equates to VEE(UVLO) = −4 V. The output isenabled when VEE = −4 V, even though VDD > 12 V (VDD
= 15 V). Notice also that OUT (VGS) is less than 20 V for
almost 100 μs. Depending on the dV/dt rate of VDD start−up,
this time could be longer and therefore, the thermal stress to
the SiC MOSFET should be taken into consideration when
programming UVSET.

(VEESET)SYSTEM PERFORMANCEFor VDD > 7 V, the quiescent current ramps up linearly
until the set UVLO threshold is crossed. The blue trace
shown in Figure 39, represents VDD versus IDD with no input

Figure 40. CH1−IN+, CH2−VDD, CH3−OUT, CH4−VEE;
VDD(UVLO) = 12 V, VEE(UVLO) = −4 V

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AND90103/D
The same start−up waveform is shown in Figure 41 but
UVSET = 3 V (not shown) which equates to VDD(UVLO) =18 V. In this case, OUT (VGS) is enabled when VDD = 18 V,
even though VEE < −4 V (VEE = −5 V). Which UVLO isdominant will depend on the dV/dt rate of VDD versus VEE.
The key point is that the NCP51705 output is disabled until
both, VDD and VEE are above and below their respective
UVLO thresholds. Compared to Figure 40, notice the effectthat a higher UVLO setting has on OUT (VGS), where thefirst OUT pulse appears near 20 V and −5 V.

is unloaded. The discharge time from −5 V to 0 V for VEE
is approximately 300 ms.

Figure 43. CH1−IN+, CH2−VDD,
CH3−OUT, CH4−VEE; Shut−Down

A zoom of the time base from Figure 43 is shown in

Figure 44. UVSET is configured for 3 V (VDD(UVLO) = 18

V) and the internal VDD UVLO hysteresis is internally fixedat 1 V. The curser position reveals that VDD = 17 V (18 V−1
V hysteresis), when the output is disabled, even though VEE= −4.5 V (VEESET = V5V) and is still active according it’s
−4 V UVLO. Although the decay of VDD is slow, a clean
termination of the last output pulse can also be observed withno spurious pulses or glitches after UVLO_OFF.

Figure 41. CH1−IN+, CH2−VDD, CH3−OUT, CH4−VEE;
VDD(UVLO) = 18 V, VEE(UVLO) = −4 V

The NCP51705 internal charge pump has a slow control
loop and the effect of this is seen by the slight undershoot and<400 μs correction observed during VEE start−up shown in
Figure 42. Beyond 400 μs, the VEE voltage settles to theregulation set point of −3 V, −5 V or −8 V.

Figure 44. CH1−IN+, CH2−VDD, CH3−OUT, CH4−VEE;
Shut−Down, VDD_UVLO(OFF) = 17 V

The turn−on propagation delay is measured from 90%
IN+ rising to 10% OUT rising. Although a SiC driver will
operate at higher VDD, most MOSFET propagation delays
are specified switching into a 1−nF load with VDD = 12 V.

Figure 42. VEE Start−Up

Shutdown operation is smooth with no glitches. As shownin Figure 43, OUT ceases switching and tracks VEE whichwww.onsemi.com
18

AND90103/D
external capacitor can be used on the DESAT pin forhigh−frequency noise filtering.
The XEN signal is the inverse of the OUT signal. Whether
the driver is operating normal or under a DESAT fault, theXEN signal is shown to accurately track the inverse OUT
signal for either case.

Figure 45 shows the measured turn−on, propagation delay,
under these standard test conditions, to be 19 ns.

Figure 45. CH1−IN+, CH2−VDD, CH4−OUT;
Rising Edge Prop Delay

Similarly, the turn−off propagation delay is measured
from 10% IN+ falling to 90% OUT falling. Figure 46 shows
the measured turn−off, propagation delay under the same
standard test conditions is 22 ns. The output rise and falltimes for each edge are approximately 5 ns.

Figure 47. CH1−IN+, CH2−OUT, CH3−DESAT,
CH4−XEN; VDESAT < 7.5 V

Figure 48. CH1−IN+, CH2−OUT, CH3−DESAT,
CH4−XEN; VDESAT = 7.5 V

Figure 46. CH1−IN+, CH2−VDD, CH4−OUT;
Falling Edge Prop Delay

APPLICATIONS
SiC MOSFETs can penetrate any application spaces
where IGBTs are presently used. Some of the more common
uses include high−voltage switching power supplies, hybrid
and electric vehicle chargers, electric railway
transportation, welders, lasers, industrial equipment andenvironments where high−temperature operation is critical.
Two areas that are particularly interesting for SiC are solar
inverters and high−voltage data centers. Higher dc voltages
are beneficial for reducing wire gauge thickness, junction
boxes, interconnections and ultimately minimizing
conduction loss thereby increasing efficiency. Most
large−scale, photovoltaic systems currently operate from a
1−kV dc bus and the trend is moving toward a 1.5−kV bus.
Similarly, data centers using a 380−V distribution network
can boost dc voltages as high as 800 V.

The DESAT and XEN waveforms are shown in Figure 47
and Figure 48 respectively. Since testing was done to verify
IC validation only (no power stage), a 100−pF, fixedcapacitor is connected to the DESAT pin. The waveforms
shown in Figure 47 indicate DESAT is below the 7.5 V
threshold and the output is switching under normal
operation. If the IN+ frequency is decreased (increased
on−time), the 100−pF DESAT capacitor will be allowed tocharge to a higher voltage. This is shown in Figure 48 where
the DESAT voltage has reached the 7.5−V threshold. The
output trailing edge is terminated before the input voltage
switches LOW. A shallow DESAT ramp is used to highlightthe fact that no glitches appear on the terminated OUT pulse.
In a switching power supply application, a small (<100 pF)

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AND90103/D
the need for two digital isolators. Depending on the amountof IO crossing the isolation boundary, a strong debate forsecondary−side control could be made for such applications.
In this simplified example, IN+ and IN− (Enable) are theonly two signals sourced from the digital controller and
XEN is read back from the NCP51705. XEN is can be usedas the timing information basis for developing gate drive
timing, cross conduction prevention, dead−time adjustment
and fault detection. In addition, temperature sensing,thermal management (fan control) and higher levels of fault
response may also be done by the digital controller. The
V5V from the NCP51705 can be used to power thesecondary side of each digital isolator as shown Figure 50.

Several fundamental application examples highlighting
the NCP5170 are shown as follows.
Low−Side Switching

Figure 49 shows a top level schematic highlighting the
NCP51705 used in a low−side switching application. No
isolation is shown so the interface between the controller anddriver is direct, though this may not always be the case. This
schematic is shown to raise awareness of how few external
components are required to provide a fully functional,
reliable and robust SiC gate drive circuit. It should also bementioned that although only a single VDD voltage rail isrequired it should be rated for at least 50 V/ns to prevent
spurious current pulses described in the discrete gate drive
description in section Discrete SIC Gate Drive in
TND6237/D. If the VDD voltage rail is provided by a
dedicated auxiliary housekeeping power supply, special
attention should be given to design a transformer featuring
ultra−low, primary−secondary stray capacitance.

CONTROLLER BIAS (3.3 V or 5 V)

Digital Controller
FAULT_HSVEESET

VDD

VDD
19

SVDD

20

22

17
16

NCP51705(Top View)

15

XEN_LSOUTSRC
PGND
PGND

11

12

Isolation
Boundary

Figure 50. Half−Bridge Concept

VEE

VEE

9

10

PGND

PGND

8

7
C+

OFF
−3.5 V
−5 V
−8 V

C−

VCH 6
VEESET=SGND
VEESET=OPEN
VEESET=V5V
VEESET=SVDD

OUTSRC

14 OUTSNKOUTSNK
13

5

DigitalIsolators ISOLATOR BIAS

FAULT_LS

18

SGND 4

XEN_HSENABLEPWM_LS

21

V5V

23

DESAT

UVSET
24
IN+ 1
IN−
2
XEN 3

20 V BIAS (isolated)

PWM_HS

20 V

Controller

ISOLATOR BIAS

Quasi Resonant (QR) Flyback

A 100−W, QR flyback converter operating from a wide
input range of 300 V < VIN < 1 kV was designed using the
NCP1340B1 controller and NCP51705 SiC driver.
Converters of this class can typically be found inphotovoltaic and industrial applications but when based on
IGBT power stages, switching frequencies are in the rangeof 65 kHz. The schematic shown in Figure 51 is a QR
flyback and the frequency is varying between 377 kHz < FS
< 430 kHz, from 100% to 25% load, at VIN = 300 V.

Figure 49. Low−Side Switching Example
Half−Bridge Concept

A more realistic use of SiC MOSFETs can be found inhalf−bridge power topologies such as the one shown in
Figure 50. High power applications tend to prefer isolated
drivers for both, the high−side and low−side. This implies

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Figure 51. 1000 V to 24 V, 100 W, 400 kHz, QR Flyback
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QR FLYBACKFor VIN = 300 V, the drain−source voltage waveform is thesum of the input voltage and the reflected output voltage.
The waveform shown in Figure 52 highlights the converter
operating at full duty cycle operation (VIN = 300 V) with 720
V appearing on drain−source of the SiC MOSFET. The VDS
rising transition is ~30 ns which equates to dVDS/dt = 24
V/ns. The NCP1340B1, QR control enables a soft, resonanttransition and valley switching (“near ZVS” turn−on atminimum VDS resonance) on the VDS falling edge and thisis clearly visible on the blue waveform. Because the
QR−flyback is a low−side only application and the fallingdVDS/dt edge is resonant, it may be possible for the SiC
MOSFET to reliably switch between 0 V < VGS < 20 V.
Nonetheless, the design shown in Figure 51 opted forswitching between −5 V < VGS < 20 V resulting in morerobust switching at the slight penalty of increased gatecharge.

The focus is to provide an ultra−compact design, where
the leads of a TO−247 SiC MOSFET can be connected
directly to the printed circuit board (PCB). Figure 54 shows
simultaneous, top and bottom views of the EVB next to an
adjacent TO−247 package for size scaling.

Figure 53. NCP5170 Mini EVB Schematic

Figure 52. CH3 = VDS, CH4 = VGS; VIN = 300 V,
VOUT = 24 V, IOUT = 4 A, FS = 377 kHz
General Purpose NCP5170 Customer EVB

A general purpose evaluation board (EVB) has been
designed for the purpose of evaluating the NCP51705
performance in new or existing designs. The EVB does notinclude a power stage and is generic from the point of viewthat it is not dedicated to any particular topology. It can beused in any low−side or high−side power switching
application. For bridge configurations two or more of these
EVBs can be used at each SiC MOSFET in a totem pole typedrive configuration. The EVB can be considered as an
isolator + driver + TO−247 discrete module. The EVB
schematic is shown in Figure 53.

Figure 54. NCP5170 Mini EVB –Top View (35 mm x 15 mm)

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VIN

When mounting into an existing power supply design andthere is available PCB area in front of the TO−247, the EVB
can be installed horizontally to the main power board, as
shown in Figure 55. If possible, this should is the preferred
mounting method.

L1

VAFG

Side View

S

Main
PCB

T0−247SiC
Mini EVB
Kapton tapeS D GMini EVB
Main
PCB

U1

VAFG

VDD (20 V)
VGS

T0−247SiC

Mini EVB

Mini EVB
Main
PCB

S D G

t

VEE (−5 V)

IL1

t

IDS

t

VDS

t
tOFF

Mini EVB T0−247
SiC

T0−247SiC(Turn−Off)S D G

Option – Cut T0−247 gate lead

S
Side View

DUT(Turn−On)

If large components on the main power board prevent
horizontal installation, a second option is to install the EVB
vertically so that it is parallel to the T0−247 package, or
angled slightly away. Installing this way is less preferred dueto the close proximity of the driver to the high dV/dt emitted
from the TO−247 drain tab. In either case, the back tab of the
TO−247 package remains exposed and can be attached to aheat−sink if necessary. Installation and operation details areavailable in the EVB User Guide.

Main
PCB

U1

D1

T0−247SiC

Figure 55. Horizontal EVB InstallationPWM Input(flying lead)

VL1

D1

DUT

T0−247SiC

Mini EVB

L1
VL1

Option – Cut T0−247 gate lead

PWM Input(flying lead)
Kapton
tape

VIN

t ON

Figure 57. Double Pulse Test Circuit
and Waveforms

T0−247SiC

The on−time of the first pulse is adjusted to achieve adesired peak drain−source current. The inductor is large andthe off−time is short enough such that IL1 remains nearly
constant during the off−time, freewheeling period. As aresult, a second, shorter pulse is applied with the same
amplitude of drain−source current. This test method allows
precise control of ID and VDS necessary for establishing
dynamic switching, parametric performance as well as
benchmarking one device against another.
The double pulse test method can also be used tocharacterize gate driver performance. Leaving the SiC,
DUT fixed, various gate drive circuits can be characterized
as U1 becomes the new “DUT.” dV/dt and dI/dt switching
performance is compared between the NCP5170 EVB
shown in Figure 53 and Figure 54 and the simple
optocoupler gate drive circuit shown in Figure 58.

S D G

Figure 56. Vertical EVB Installation

The EVB comes initially configured to accept a PWM
signal that is positive input logic (IN− connected to GND1).
However, IN− can easily be used as an active enable orreconfigured for inverting input logic if desired. The driver
output comes preconfigured for 0 V < VOUT < VDD
switching. All the connections and resistor placeholders areavailable to reconfigure VEESET for −3 V, −5 V or −8 V VEE
switching. Finally, the UVSET option is preprogrammed for
17−V turn−on operation which is considered a safe level for
SiC MOSFETs.
PARAMETRIC PERFORMANCE
MOSFETs and IGBTs are parametrically characterizedusing the well know double pulse test platform. The double
pulse test method essentially applies two pulses to thegate−source of a low−side SiC MOSFET considered to be
the device under test (DUT). The DUT is inserted into asocket connected to a clamped inductive switching circuit
similar to the one shown in Figure 57.

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Figure 58. FOD8384 SiC Opto Gate Drive Circuit

The FOD8384 optocoupler driver is capable ofwithstanding VDD bias up to 30 V, making it well suited for−5 V < VGS < 20 V switching. Similar to the example shownin Figure 58, the FOD8384 driver is not a complete SiC
MOSFET gate drive circuit. Therefore, since features
between the two circuits are not comparable, test results andcomparisons are limited to dynamic switching only.
The rising and falling VGS waveforms for both circuits
are show for comparison in Figure 59 and Figure 60
respectively. Both circuits are using 1 Ω source and sink gate
resistors. These gate drive edges are shown driving a 1.2 kV,
SiC MOSFET with 600 V present on VDS and 30 A flowing
through ID. The NCP51705, VGS rising edge appears as
purely resistive from −5 V < VGS < 10 V and then capacitive
RC charging from 10 V < VGS < 20 V. This is indicative of
the NCP51705, 6 APK sourcing current compared to the 1
APK sourcing current from the FOD8384. As a result the
NCP51705 has a VGS rise time of 37.5 ns, compared to 57.6
ns for the FOD8384 switching under the same test
conditions. Similarly, the VGS fall time for the NCP51705
is 25.2 ns, compared to 34.5 ns for the FOD8384.

Figure 60. VGS Falling Edge Comparison

A well designed gate driver IC includes low source andsink impedance so that the SiC MOSFET drain can be
accurately controlled by the gate. Secondly, minimizing
driver output impedance is essential for allowing the highest
natural dV/dt of the SiC MOSFET. The natural dV/dt limitof a SiC MOSFET is inversely proportional to RLO + RGATE+ RGI. When RLO is higher than necessary, the natural dV/dt
limit of the SiC MOSFET is lowered. This makes the device
more susceptible to dV/dt induced turn−on and limits theamount of dVDS/dt control that can be achieved by theselection of RGATE. The NCP51705 VDS waveforms shownin Figure 61 reveal the high degree of dVDS/dt control thatis possible by simply varying RGATE. For RGATE = 1 Ω,
dVDS/dt = 72 V/ns. Increasing RGATE from 1 Ω to 15 Ω
reduces dVDS/dt from 72 V/ns to 68 V/ns. This demonstrates
that a much higher RGATE can be used to obtain very fineincremental steps toward reducing dVDS/dt, if desired.

Figure 59. VGS Rising Edge Comparison

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Figure 61. NCP51705 VDS Rising Edge,
Vary Gate Resistance

Figure 63. VDS Rising Edge Compare,
1 W Gate Resistance

The same experiment was completed using the FOD8384
opto gate driver. Notice from the waveforms shown in
Figure 62, a change in RGATE from 1 Ω to 15 Ω, results in adVDS/dt rate change by more than 2:1. dVDS/dt control ismore influenced by smaller changes in RGATE due to thehigher output impedance of the FOD8384 driver. Also,
notice the dVDS/dt rise of the NCP51705 is more linear
comparatively.

Another way the NCP51705 enables dVDS/dt control is byvarying the level of negative amplitude of VEE. This can bedone by configuring the VEESET pin according to Table 2
or by using an external negative DC power supply applied
to VEE. The waveforms in Figure 64 show the change in
dVDS/dt as VEE is varied between −6 V < VEE < 0 V. Noticethe strong inflection and capacitive nature at low VDS, forthe case that 0 V < VGS < 20 V. This is due to some residualgate charge from the SiC MOSFET not being fully turned off
and highlights the importance of driving VGS negative
during turn−off.

Figure 62. FOD8384 VDS Rising Edge,
Vary Gate Resistance

The waveforms shown in Figure 63 compare VDS for eachdriver switching the same load from −5 V < VGS < 20 V withRGATE = 1 Ω. The dVDS/dt rates are comparable at 72 V/ns
verses 64 V/ns. The NCP51705 shows better damping andlower amplitude ringing.

Figure 64. NCP51705 VDS Rising Edge, Vary VEE

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The drain current measurements shown in Figure 65 weretaken using a Pearson current probe. The NCP51705 current
is falling at dID/dt = 3.2 A/ns yet exhibits less ringing
compared to the FOD8384 drive circuit. The faster dID/dt of
the NCP51705 correlates well to the VGS falling edge
waveforms shown in Figure 60.

The double pulse test methodology is a test procedure
traditionally used to characterize dynamic switching
performance of discrete power semiconductor devices.
Since the applied VDS and initial ID can be accurately
controlled during turn−on and turn−off, this measuring
technique has been shown to be a reliable method forcharacterizing gate driver IC performance in a clamped
inductive switching application circuit.
References[1] Baliga 2ed p14−15[2] Lutz[3] Lutz et. al; 2017; 377−378

Figure 65. ID Falling Edge Comparison

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