2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture

Register Cache System not for Latency Reduction Purpose
Ryota Shioya∗† , Kazuo Horio‡ , Masahiro Goshima∗ and Shuichi Sakai∗∗ Department of Information and Communication Engineering, University of Tokyo† Research fellow of the Japan Society for the Promotion of Science‡ Fujitsu Laboratories Ltd.

Email: {shioya, horio, goshima, sakai}@mtl.t.u-tokyo.ac.jp

file consists of a multi-port RAM, and its circuit area is
proportional to the square of the number of ports [1], [2].
Figure 1, a chip photograph of an Intel Pentium 4 processor,
shows that the circuit area of the register file is comparable
to that of the level-1 data cache despite that the capacities
are different by more than an order of magnitude. This holds
true for more recent processor cores.
The circuit area of the register file is comparable to that of
the level-1 data cache, and the access latency of the register
file is nearly equal to that of the level-1 data cache. Just likethe level-1 data cache, the register file cannot be accessedin 1 cycle, and about 2 or 3 pipeline stages are assigned toit [3], [4]. This pipelining of the register file access causes
the following two problems.
The first, IPC degradation, is a general problem withdeeper pipelines. Increase in the latency of the register
file increases miss penalties of speculations such as branchprediction. Moreover, deeper pipelines are susceptible toresource shortage and it results in pipeline stalls [5], [6].
However, these effects are indirect, and don’t degrade the
IPC so seriously. The IPC degradation for every 1 stage
increase is no more than 2% even in the worst cases [7].
The second problem is specific to the register file latency,
and is more serious than the IPC problem. The pipeliningof the register file access requires a large bypass network.
Instruction results produced in the last 2l cycles have to
be forwarded through the bypass where l is the register
file latency. The bypass network consists of long wires andseries of wide multiplexers. A larger bypass network could
limit the clock frequency, and consumes a larger amount ofenergy.
In addition to that of the bypass network, energy consumption of the register file itself is also serious. Energy
consumption of a RAM is proportional to the circuit area andthe access frequency [1], [2]. Only load/store instructions
access the level-1 data cache just once. On the other hand,almost all the instructions access the register file more than
twice (once for read and once for write). Thus, the register
file, which has the circuit area comparable to that of thelevel-1 data cache, consumes much more energy than thelevel-1 data cache. In addition, SMT increases the accessfrequency in proportion to increase in throughput.
The energy consumption and resulting heat are ones of

Abstract—A register cache has been proposed to solve theproblems of the huge register files of recent superscalar
processors. The register cache reduces the effective accesslatency of the register file for IPC improvement, simplifies the
bypass network, and reduces the ports of the main register
file. Though the primary purpose of the previous works is toimprove IPC, the misses on the register cache may degrade
the IPC. We propose Non-Latency-Oriented Register Cache
System (NORCS). Though the effects of NORCS are the sameas the conventional systems, it is free from register cache
miss penalties that the conventional systems suffer from. In
NORCS, the register cache itself is not different from that of
the conventional systems. The difference is that the instruction
pipeline has stages to read the main register file, which all
instructions go through regardless of register cache hit /miss. Therefore, the instruction pipeline of NORCS is not
immediately disturbed by the register cache misses. For arealistic 4-way superscalar processor, NORCS can simplify thebypass network to the same complexity as a 1-cycle-latency
register file, and reduce the ports of the main register filefrom 12 to 4. CACTI simulation shows that the area and power
consumption are reduced to 24.9% and 31.9% compared to thebaseline model without register cache. Though these results are
not different from the conventional systems, IPCs differ greatly.
IPC of the conventional system decreases to 83.1% because of
the cache miss penalties, while that of NORCS is retained at
98.0%.
Keywords-Register file, Register Cache, Instruction pipeline,
Instruction level parallelism, Low-energy Technologies

I. I NTRODUCTION
Programs essentially contain fragments that cannot beparallelized. As Amdahl’s law suggests, speed-up of a single
core which executes sequential portion of programs willremain to be important even in the era of many-core processors. In fact, the major processor vendors are maintaining thewidths of each core of mainstream multi-core processors.
The physical register file and the bypass network havebeen ones of the most serious bottlenecks of recent superscalar processor cores.
In order to achieve high IPC, superscalar processor cores
require a physical register file of high capacity to meetthe number of in-flight instructions. In addition, SMT cores
require a register file whose capacity is proportional to thenumber of threads.
A 4-issue superscalar processor core generally requiresa register file with 8 read and 4 write ports. The register1072-4451/10 $26.00 © 2010 IEEE
DOI 10.1109/MICRO.2010.43

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of superscalar processor cores does not have capability tohide the main register file access latency on register cache
misses. To make matters worse, the effective miss rate,
which is given by the probability of the pipeline disturbance,
is much worse than the miss rate of the register cacheitself. The instruction pipeline is disturbed if any one of theoperands that simultaneously access the register cache causea miss. For example, the evaluation result of 456.hmmerof SPEC2006 in Section VI shows that the register cache
hit rate is as high as 94.2%, but an average number ofoperands that access the register cache a cycles is 2.49, thentheoretical effective miss rate is 1 − 0.9422.49 ≈ 13.9%, andthe IPC degradation is as high as 10.2%.
This paper proposes a Non-latency-Oriented Register
Cache System (NORCS). The register cache system refers
to a system of accessing the register cache, and consists of
the register cache, the main register file, and the instruction
pipeline stages to access them. For simplicity, we refer to aconventional register cache system as a Latency-Oriented
Register Cache System (LORCS). As its name suggests,
NORCS is a register cache system that does not reduce
the latency. The register cache and the main register file of
NORCS are almost the same as those of LORCS. NORCS
is characterized by its unique instruction pipeline.
LORCS has a pipeline that assumes hit. The pipeline
has a stage to access the register cache but no stages toaccess the main register file. This is the same as the level-1
cache. A conventional instruction pipeline has the stages toaccess the level-1 cache but not the level-2 cache. On level1 cache misses, pipeline stall or flush is usually introduced
to make time to access the level-2 cache. It is because therelative positions of instructions in the pipeline cannot bechanged after they are issued. This holds true for LORCS.
Since LORCS reduces the latency, it results in considerable
performance degradation caused by pipeline disturbance.
In contrast, NORCS has a pipeline that assumes miss. The
pipeline has stages to access the main register file, and all
instructions pass through the main register file access stages
regardless of register cache hit or miss. On a miss, the main
register file provides a value in the end of the main register
file access stages. While on a hit, the register cache provides
the value also in the end of the main register file accessstages. Thus, NORCS doesn’t reduce the access latency of
the register file, and the IPC is not improved by nature.
Instead, NORCS is free from such pipeline disturbance as
LORCS does, because time to access the main register fileis provided as stages in the pipeline. That is, the IPC is
not necessarily improved, but nor considerably degraded.
While maintaining IPC, NORCS reduces the complexity inbasically the same way as LORCS.
The idea of a cache that doesn’t reduce the latency mightsound weird. For example, a level-1 cache that has the samelatency as a level-2 cache is perfectly meaningless. One
leading textbook defines a cache as “a small, fast memory lo-

L1 Data cache
16 KB 1 read/1 write

Register file
32 bits 256 entries
12 read/6 write (double pumped 6 read/3 write)

Figure 1. Integer execution core of Intel Pentium 4 Processor [11]. Pentium
4 processor uses a double-pumped 6-read/3-write register file as a 12-read/6-write register file [3].

the most serious problems of recent processor cores. The
region including the register file and the bypass network is
a hot spot in a core, and limits the clock frequency.
Naı̈ve Methods to Reduce Complexity: To simply reduce the complexity of the register file or the bypass
network, some naı̈ve methods to reduce the number of theresources can be considered.
As for the bypass network, techniques of incomplete
bypass have been proposed [8], [9], [10]. An incomplete
bypass only provides results in the last m < 2l cycles.
After m cycles have passed from the cycle when a producer
instruction is executed, the consumer have to wait to beissued so that it can obtain the result from the register file.
If the ports of the register file is reduced, the latency of
the register file is reduced, and then the complexity of the
bypass network is also reduced. In this case, the pipeline isdisturbed when the ports fall short.
These techniques result in a trade-off between complexity
and IPC. Section VI shows that the IPC degradation is ashigh as 20% in the worst cases.
A register cache is a better solution for these problems[12], [9], [10]. As its name suggests, a register cache is acache to the main register file. The capacity of the registercache is small enough to limit the access latency generally
to 1 cycle. As far as the register cache hits, it is equivalent toa conventional register file with 1-cycle latency. This bringsin the following two effects.
Firstly, the register cache is free from the IPC degradation
stated before because the register cache is equivalent to a
1-cycle-latency register file. However, this effect is minor
because this IPC degradation is small as stated before.
Secondly, the register cache reduces the complexity, energy consumption, and heat in the following ways:
1) Simplifying bypass network: The bypass is necessary not for the main register file but for the registercache. Thus, the bypass network is almost the sameas that of a 1-cycle-latency register file (Section II).
2) Reducing main register file ports: The number ofports of the main register file can be reduced because
only operands that miss the register cache access themain register file. Section VI shows that the numberof the ports can be reduced from 12 to 4.
Though the register cache can solve these problems, it suffers from IPC degradation for yet another reason than stated
before. As described in Section III, out-of-order scheduling
302

Ip :

SC

Ic1:

IS
SC

Ic2:

cycle

CR
CR

EX

IS

CR
CR

EX

RW/
CW

SC

IS

CR
CR

EX

RW/
CW

SC

IS

CR
CR

EX

Ic3:

RW/
CW

I1 :
I2:
I3:

RW/
CW

SC

IS
SC

EX

IS

CR
CR

EX

RW/
CW

SC

IS

CR
CR

EX

RW/
CW

SC

IS

CR
CR

EX

I4:

Backend Pipeline of LORCS (Hit)

I1:
I2:

SC

IS
SC

I3:

Figure 4.

cycle

RR/CR
RR/CR

EX

IS

RS
RS

RR/CR
RR/CR

EX

IS

RS
RS

RR/CR
RR/CR

EX

RW/
CW

SC

IS

RS
RS

RR/CR
RR/CR

EX

miss

RR

(a) Stall
Figure 3.

RS
RS

SC

I4:

RW/
CW

RW/
CW

I1 :
I2:
I3:

RW/
CW

I4:

SC

IS
SC

CR
CR

EX

IS

CR
CR

RR

SC

IS

SC

cycle

RW/
CW

EX

RW/
CW

IS

CR
CR

EX

RW/
CW

IS

CR
CR

EX

flush

stall

miss

Figure 2.

cycle

CR
CR

SC

SC

miss

(b) Flush
Backend Pipeline of LORCS (Miss)

B. Register Write
Instruction results written to the main register file aretemporarily held in a write buffer before they are moved
to the main register file.
This write to the main register file through the write buffer
uses the write-through policy; that is, the results are written
both to the register cache and to the write buffer in parallelon the RW/CW stage right after the execution stage.
Unlike usual data caches, the use of the write-back policy
does not reduce the number of accesses to the main register
file. In usual data caches, stores to the same addresses
often occur, making the number of write-backs less than thenumber of the stores. While in the register cache system,
writes to the same entry seldom occurs because the register
renaming of out-of-order superscalar processors eliminates
such overwrites to the same entries.

RW/
CW

RW/
CW

Backend Pipeline of NORCS

cated close to the CPU that holds the most recently accessed
code or data”[13]. According to this definition, NORCS isn’ta cache because NORCS is not fast. Non-latency-oriented
cache system is useful only if applied to the register file, andNORCS is the only cache system that doesn’t reduce latency.
The precise reason why a non-latency-oriented cache system
is only applicable to the register file is complicated, anddiscussed in Section V.
The rest of the paper is organized as follows. Section II
and III introduces LORCS. After Section IV describes
detailed design of NORCS, Section V gives considerations
on NORCS. Then, Section VI presents evaluation results.

C. Simplifying Bypass Network
The results of instructions are written both to the registercache and to the main register file (through the write buffer)in the RW/CW stage. Thus, the results of recently executed
instructions are most likely to be found in the register cache,which means that it is not necessary for the main register
file, the write buffer or the bypass network to provide suchrecent results.
In Figure 2, the instructions from Ic1 to Ic3 depend on Ip .
Ic3 can receive the result through the register cache because
Ic3 reads the register cache after Ip writes the result to theregister cache. Therefore, only Ic1 and Ic2 have to receive
the result of Ip through the bypass network. The bypass
network is required to provide the results executed in thelast 2 cycles only, which is the same as a register file with
1-cycle latency.

II. LORCS
This section describes LORCS (Latency-Oriented Register Cache System) focusing on its behavior on the registercache hit, in order to explain how it solve the problems
caused by a large register file, especially increase in thecomplexity, energy consumption, and heat of the register
file and the bypass network [12], [9], [10]. The behavior on
the register cache miss is described in the next section.
A. Instruction Pipeline of LORCS
Figure 2 shows the behavior of the backend pipeline of
LORCS. The LORCS in this figure has a register cache anda main register file with 1-cycle latency, respectively. SC,
IS, EX, CR, CW, and RW indicate the stages for instruction
scheduling, issue, execute, register cache read, register cache
write, and, main register file write, respectively. RW/CW
indicates that main register file write and cache write is
performed at the same stage. CR stages are horizontally
divided into 2 to indicate that each instruction has 2 source
operands, which access the register cache in parallel.
In so far as the accesses hit the register cache, it behaves
as a register file with 1-cycle latency, and cycles to read themain register file don’t appear in the figure. The instruction
pipeline is disturbed on a register cache miss for the same
reason as a usual level-1 data cache. We describe details of
the cache miss in the next section.

D. Reducing Main Register File Ports
The register cache in LORCS can reduce the number ofread ports of main register file by allowing only the missed
operands to access the main register file. The register cache
can also reduce the number of write ports of main register
file by using a write buffer without any additional forwarding
paths. The use of the write buffer reduces the number ofthe write ports to the average throughput of instruction
execution. This method only works on register writes anddoes not work on reads, because writes are not critical andcan be delayed like a general store buffer in memory access,however reads are critical and cannot be delayed by using
such buffer.

303

The evaluation results in Section VI show that 2 read and2 write ports of the main register file are sufficient to meetthe requirement.
The area of a main register file with a few ports is considerably small, because the area of a RAM is proportional to
the square of the number of the ports [1], [2]. The evaluation
results (Section VI) show that the area of the main register
file is almost the same as that of the register cache, and thesum of the areas of the register cache and main register fileis reduced to 30.7% of a full-port register file.
The reduction in area consequently reduces the latency ofthe main register file. The area of the main register file isalmost the same as that of the register cache, thus the main
register file can also be accessed in 1 cycle.

Main Register File

Ipmisses RC

Register Cache
Instruction Window

I2

Ip

Iｃ

I1

IS

EX

CR

(a) Block diagram
Ipmisses RC

Ip:
I1:
I2:
Ic:

III. R EGISTER C ACHE M ISS IN LORCS

SC
SC

IS

CR
CR

RR

IS

CR
CR

EX

RW/
CW

IS

CR
CR

EX

RW/
CW

CR
CR

EX

SC
SC

IS

EX

cycle

RW/
CW

RW/
CW

(b) pipeline chart
Figure 5. Selective stall

As Butts et al. pointed out, there are only two pragmatic
options to read the main register file on a register cachemiss, that is, stall and flush [10].

Ic is dependent on Ip . Figure 5 (a) is a snapshot of the point
in time indicated by the down arrow in (b). At this point,
Ip misses the register cache.
Only from Figure 5 (b), the selective stall, which would
mean stalling Ip and Ic while continuing the execution of
I1 and I2 , might seem possible. This, however, is because
this kind of chart doesn’t have the capability to represent
resource conflict. Figure 5 (a) shows I2 actually cannot
proceed because it is blocked by Ip in the same lane of thepipeline. Ic , which must be stalled because it is dependent
on Ip , blocks the other lane of any further issue. Thus, no
instruction can be issued until Ip finally moves on. In thissituation, only I1 may avoid being stalled actually.
For an instruction to proceed, it is necessary to check notonly that it is independent on the cache-missed instruction
but also that the cache-missed instruction and its dependent
instructions don’t exist ahead in the same lane. This requiresa recursive search of dependent instructions every cycle.
After all, selective stall is difficult because the backend ofa out-of-order superscalar processor core is also a pipeline,
and it does not have the capability to re-schedule instructions. Instructions are primarily scheduled in the instruction
window so that they can flow through the backend pipeline.

A. Stall or Flush
Figure 3(a) shows the behavior of the backend pipelineon the register cache with stall. In this model, executionof instructions is delayed by the main register file latency,
which is 1 cycle in the figure.
Figure 3(b) shows the behavior with flush. The flush
model flushes and re-issues all the instructions that havebeen issued in the same or later cycles as the instructionthat cause a register cache miss. In this case, execution isdelayed by the issue latency, which is given by the numberof cycles from the schedule stage to the stage where theflush occurs minus 1, because flushed instructions need tobe replayed from the schedule stage. In this figure, 1 cycle isassigned to the schedule, issue, and the register cache readstages, and the issue latency adds up to 3 − 1 = 2 cycles.
In general, the main register file latency is shorter than
the issue latency, and the stall model works better than the
flush model as evaluation results in Section VI show1 .
As Butts et al. pointed out [10], stall and flush are
only pragmatic options on the register cache miss. We
want to stress this point, because we have been asked so
frequently why different options cannot be used to improve
LORCS performance, which are selective stall and hit/missprediction. Though they might seem to reduce the misspenalty of LORCS easily, they turn out to be either very
difficult to implement or have serious side effects becauseof resource conflicts.

C. Hit/Miss Prediction
There have been proposal on hit/miss prediction for ausual data cache [14]. In these proposals, when a producer
instruction is predicted to miss the cache, the issue of theconsumer is delayed to avoid pipeline disturbance.
Hit/miss prediction for the register cache is slightly different from that for the data cache. Figure 6 (a) and (b)show pipeline charts of LORCS. As shown in Figure 6 (a),instructions predicted to miss the register cache should be
issued twice as follows:
1) First issue: Ip , which is predicted to miss the registercache, is issued at regular timing. Ip will miss theregister cache as predicted, and start the main register
file access in the same way as usual.

B. Selective Stall
Figure 5 (a) and (b) show the block diagram and thepipeline chart of LORCS, respectively. In these figures, Ip ,I1 , I2 , and Ic have been issued to the backend pipeline, and
1 Usual level-1 data caches work better with flush. This is because thestall penalties, given by the level-2 cache latency in this case, are longer
than the flush penalties, given by the issue latencies.

304Ip (1st):IS

Ip (2nd):

RR

IS

CR
CR

EX

IS

CR
CR

EX

IS

CR
CR

I1:
Ipmisses RC

Ic:

Ip:

IS

CR
CR

RW /

No conflict
CW
RW /

CW

EX

RW /

CW

(a) With issuing twice cycle
RR

EX

RW /

CW

EX

RW /

CW

CR
CR

I1:

IS

CR
CR

Ic:

Ipmisses RC

IS

Figure 6.

port of the bypass). This conflict, however, can be resolved
by adding a write port (and an input port of the bypass) for
the data from the level-2 cache [14]. This, however, is notapplicable for the register cache, because it is not realistic
to add dedicated functional units for all the instructions thatare predicted to miss the register cache.
As a result, issuing twice is the only practical way toimplement hit/miss prediction in the register cache. This,
however, consumes the issue width twice, and results inworse IPC than stall model, as is shown in Section VI.

cycle

CR
CR

EX

Resource
conflict
RW /CW

IV. NORCS(b) Without issuing twice
Hit/miss prediction with and without issuing twice

We propose a NORCS (Non-latency-Oriented Register
Cache System). Since NORCS doesn’t reduce the accesslatency of the register file, and the IPC is not improved bynature. Instead, NORCS is free from such pipeline disturbance as LORCS does. That is, the IPC is not necessarily
improved, but nor considerably degraded. While maintaining
IPC, NORCS reduces the complexity in basically the same
way as LORCS.

2) Second issue: Ip is issued again just after the latencyof the main register file. Then, the data arrives fromthe main register file just in time for the instruction to
be used for execution.
The purpose of the first issue is to start main register fileaccess. In order to start the main register file access, thephysical register number of the source operand is needed.
Issuing the instruction is the most reasonable way to obtain
the physical register number.
The purpose of the second issue is to actually execute theinstruction and to resolve resource conflict.
Figure 6 (b) shows the pipeline without issuing twice. In
this figure, Ip , which is predicted to miss, is issued and starts
the main register file access, and then waits there (by somemeans) for the data from the main register file. In this case,
Ip and I2 cause conflict for the functional unit (if they try
to use the same type of functional unit).
In Figure 6 (a), the instruction scheduler selects Ip forthe second issue and the issue of I1 is delayed to the next
cycle, resolving the resource conflict between Ip and I1 in
the usual way. Issuing the instruction is the most reasonable
way to resolve the resource conflict.
In the case of hit/miss prediction for the data cache, thesecond issue can be avoided. Suppose a load instruction
Im is predicted to miss the level-1 cache, and another load
instruction Ih is issued later. Im and Ih do not use the samefunctional unit, that is, Im obtains its own data from thelevel-2 cache, while Ih from the level-1 cache. Both of thedata items must be written to the register file (and passed tothe consumer instructions through the bypass), and this may
cause a conflict on the register file write port (and an input

A. Structure of NORCS
Figures 7 and 8 show block diagrams of LORCS andNORCS, respectively. In these figures, 2 pipeline stages is
assigned to accessing the main register file. NORCS has
a similar structure to LORCS; the register cache and themain register file themselves are almost the same as thoseof LORCS.
The pipeline latches highlighted in Figure 8 are small but
the most important difference between them. These latches
are placed between the tag and the data arrays of the registercache, and the tag and the data arrays are accessed on
different stages.
As shown in these figures, the difference in the logic isquite small, but it makes a great difference to the performance as described in the following sections.
B. Instruction Pipeline of NORCSNORCS has a pipeline that assumes miss, and all instructions go through the stage(s) to read the main register fileregardless of hit/miss to the register cache.
Figure 4 shows the pipeline chart of the NORCS. In thisfigure, the main register file, the tag and the data arrays
WritebufferArbiterWrite
reg num/dataWritebufferArbiterWrite
reg num/data

Out of instruction pipeline

hit/miss

Main register file

Main register file
Added latches

Instruction pipeline

Figure 8.
Figure 7.

Data array

Register cache

ALU
Register cache

Write data

Write
reg num/dataWrite
reg num/dataReadreg numTag array

Readreg num

hit/miss

Block diagram of LORCS

305

Block diagram of NORCSALU

of the register cache have 1-cycle latency, respectively. RS(Register Scheduling) indicates a stage for hit/miss detectionof the register cache. In this figure, only the lower operandof the instruction I2 causes the register cache miss. RR/CR
indicates the stage to read either the main register file or thedata array of the register cache depending on the result of
the hit/miss detection on RS stage.
An issued instruction accesses the tag array of the registercache on the RS stage only for hit/miss detection. If its
operands are found on the register cache (e.g., I1 ) the
instruction simply sends the result of the tag-matching to
the following stages. On the non-painted RR/CR stage
right before the execution stage, the data array is accessed
depending on the tag-match result. If an operand is not foundin the register cache (e.g., the lower operand I2 ), the main
register file is read on RR/CR stages painted in Figure 4 .
Pipeline Stall: Since the instruction pipeline of NORCS
has RR stage to read the main register file, it is not disturbed
only on a single register cache miss.
When the read ports of main register file fall short, thatis, more operands than the number of the read ports of themain register file miss the register cache in a single cycle,
the pipeline is disturbed. The pipeline must produce enoughcycles to read the main register file by stalling the pipeline.
The conditions for the pipeline disturbance of LORCS andNORCS are summarized as follows:• LORCS: If a single register cache miss occurs.
• NORCS: If register cache misses more than main
register file read ports occur at a single cycle.

Ip :

IS

Ic :

need bypass

Figure 9.
Ip :
Ic :

IS

cycle

CR RR EX CWIS

CR RR EX CW

Bypass of NORCS (Naive implementation)
RS RR/CR EX CW
need bypass

IS

Figure 10.

cycle

RS RR/CR EX CW

Bypass of NORCS

until the end of the main register file access stages. On the
RR/CR stage right before the execution stage, the data arrayis accessed depending on the tag-match result detected on
the RS stage. The bypass network only provides the resultof Ip for the period of 2 cycles after its issue, because the
RR/CR stage comes the cycle after the CW stage of Ip .
This is shorter than the usual implementation by 1 cycle,
and is the same as the register file with 1-cycle latency.
V. C ONSIDERATIONSThis section gives consideration on NORCS. Section V-A
explains why a cache system that doesn’t a reduce latency
works for a register cache but not for a usual data cache.
Section V-B explains why NORCS outperforms LORCS.
A. Cache System That Doesn’t Reduce Latency
The pipeline of NORCS works only for a register cache
but not for a usual data cache. We try to explain this byusing data dependency and the data flow graph (DFG). A
cache system that doesn’t reduce latency works if the latency
doesn’t affect the height of the graph.
Data dependencies can be categorized into “value–value”
and “via–index”. In a data cache, an index refers to a memory
address; while in a register cache, an index refers to a register
number. Data dependencies and the height of the DFG aresummarized as follows:• Data Cache– Value–value: Value–value dependency refers to one
from a store to a dependent load instruction. In
this case, increase in the latency of the data cachepossibly heightens the DFG, because the data cacheusually doesn’t bypass values.
– Via–index: Via–index dependency refers to one
from load instruction to another instruction. Also inthis case, increase in the latency of the data cachepossibly heightens the DFG. One example of ”viaindex” dependency is pointer chasing. On the pointerchasing of the linked list, increase in the latency ofthe data cache can heightens the DFG.
• Register Cache– Value–value: Since the bypass network can immediately pass the data, the register cache latency is
independent of the DFG height.
– Via–index An index — register number is staticallydetermined, that is, not calculated by other instructions. Therefore, there are no value–index dependencies in a register cache.

C. Simplifying Bypass Network
As described in Section II, LORCS can simplify thebypass network because the register cache of LORCS isequivalent to a 1-cycle-latency register file as far as theregister cache hits. NORCS do so not in the same ways as
LORCS because it doesn’t reduce the latency of the register
file, but by delaying the data array access of the registercache until the end of the main register file access stages.
We describe this by comparing our technique with usual
implementation of NORCS.
In usual implementation of a cache, the tag and thedata arrays are accessed in parallel in order to obtain thedata faster. Figure 9 shows the pipeline chart of the usual
implementation of NORCS, in which the data array and the
tag array are accessed in parallel on CR stage. The stages
are denoted by the same labels used in Figure 4. In thisfigure, Ic is dependent on Ip . Ic can receive the result of
Ip through the register cache, because the CR stage comesa cycle after CW stage of Ip . If Ic had been issued in theearlier cycles, it must receive the result through the bypass.
That is, the bypass must provide the result of Ip for 3 cycles
after its issue.
Figure 10 shows the pipeline chart of proposed technique,in which the data array access of the register cache is delayed306

As a result, a cache system that doesn’t reduce the latency
works only for a register cache but not for a usual data cache.

LORCS

B. Pipeline That Assumes MissNORCS achieves better performance than LORCS. The
reason is, in short, this is a pipeline.
In a modern instruction pipeline with speculations, thelatencies only degrade IPC indirectly through miss penalties.
If there were no prediction misses or pipeline disturbance,
longer latencies do not affect the IPC.
In the rest of this section, for simplicity, only branchprediction is taken into account, but the same is true forother predictions. On a branch prediction miss, the numberof execution cycles is extended (approximately) by the misspenalty of the branch prediction. On a register cache miss,the number of execution cycles is extended (approximately)by the miss penalty of the register cache.
The total penalty cycles of LORCS are:I 3:

penaltybpred × βbpred + latencyMRF × βRC ,

I 1:

cycle

IS CR
CR EX
IF

•••
IF

•••
IF

I 5:

IF

I 1:

IS CR
CR EX
IS CR
CR RR EX
CR
•••
IS
CR EX
•••
IS CR
CR EX

penaltybpred

NORCS
IF

•••

I 2:

IS RS
RS

latencyMRF
RR
RR

EX

latencyMRFIF

I 3:
I 4:

IS RS
RS

•••
•••

IF
IF

I 5:

•••
IF

RR
RR

EX

RR
IS RS
RS RR EXRR
IS RS
RS RR EXRS•••
IS RS RR
RR EX

penaltybpred + latencyMRF

Figure 11.

Pipeline of LORCS and NORCS

VI. E VALUATION
A. Evaluation environment
We evaluated LORCS and NORCS using a cycle accurate
processor simulator Onikiri 2[15] developed in our laboratory. Unlike SimpleScalar Tool set [16], which is usedwidely for researches on processor architecture, Onikiri 2
replays execution of instruction in the exact cycle when it ison the execution stage. Thus, Onikiri 2 can simulate more
precisely than SimpleScalar Tool set, when adopting data
predictions such as address match/mismatch prediction.
We used 29 programs from the SPEC CPU2006 [17]benchmark with ref data sets. The programs were compiledusing gcc 4.2.2 with the “−O3” option. We skipped the first
1G instructions and evaluated the next 100M instructions.
The left column of Table I, labeled “Baseline”, gives theconfiguration of the baseline processor. This basic structure
is based on MIPS R10000 out-of-order superscalar processor, which can issue up to 6 instructions per cycle. Someconfigurations such as the branch predictor and the caches
are set to match modern processors. We implemented both
LORCS and NORCS on the baseline processor.
1) Evaluation models: We evaluated the following models:• PRF: The baseline model with Pipelined Register Fileswith complete bypass networks.
• PRF-IB: Pipelined Register Files with Incomplete Bypass networks. If operands are produced within 2 cycles,
they are sent through the bypass network. Otherwise,
the backend pipeline is stalled until the operands canbe obtained through the register files [8]. The bypass
networks have the same complexity as those for LORCS,NORCS, and register files with 1-cycle latency.
• NORCS: A model of NORCS. The register caches are
adopted to the integer register files. Each register cachein the “infinite” model has the same number of entries
as the corresponding register file.
• LORCS: A model of LORCS. The configuration of theregister caches is the same as in NORCS model. Several

(1)

(2)

In the lower half of Figure 11, the surrounding lightershaded region and the surrounded darker-shadowed region
correspond, respectively, to latencyMRF and penaltybpred in
the expression.
Therefore, the difference between the total penalty cycles
of LORCS and that of NORCS is:(1) − (2) = latencyMRF (βRC − βbpred ).

•••

I 4:

where penaltybpred is the miss penalty of the branch prediction, latencyMRF is the latency of the main register file, βbpredand βRC are the effective miss rate of a branch prediction
and register cache, respectively2 . Note that βbpred is not“branch prediction miss rate” for a branch instruction, but
the effective miss rate given by the probability of the branchmiss in each cycle. The same is true for βRC .
The upper half of Figure 11 shows the behavior on theregister cache miss of LORCS. The stages are denoted by
the same labels used in Figure 2 and 4. In the figure, thelower operand of the instruction I3 misses the register cache.
In the upper half of Figure 11, the lighter- and the darkershaded regions correspond to latencyMRF and penaltybpred in
the expression, respectively.
The branch miss penalty of NORCS is longer than that of
LORCS by the latency of the main register file. Thus, thetotal penalty of NORCS is:(penaltybpred + latencyMRF ) × βbpred .

IF

I 2:

(3)

Thus, if βRC > βbpred , NORCS outperforms LORCS. This
expression can be interpreted as follows: NORCS moves
the register cache miss penalty of LORCS (latencyMRF ) into
the miss penalty of the branch prediction. βRC is muchhigher than βbpred , and this is the reason why NORCS canoutperform LORCS.
2 In the flush model, the register cache miss penalty is given by the issuelatency, which is usually not shorter than latencyMRF .

307

options on register cache miss are implemented; detailsof these are described later.
The left column of Table II, labeled “Baseline”, summarizes the other parameters for the register file system foreach model. “PRF”, “RC”, and “MRF” in the table mean
the pipelined register file, the register cache, and the main
register file, respectively.
2) Replacement Policy of Register Cache: In addition
to LRU, we evaluated USE-B model that is a use-based
replacement policy proposed by Butts et al. [10]. They useda use-predictor that predicts how many times a register will
be referenced before its release [18] for replacement. The
configuration of the use-predictor is shown in Table II. These
parameters are the same as those given in [10].
3) Miss Model of LORCS: Regarding the behavior on aregister cache miss in LORCS, STALL and FLUSH models
implement backend stall and backend flush, respectively,
as described in Section III-A. In addition to STALL and
FLUSH, we evaluated the following idealized models:• SELECTIVE-FLUSH: This model selectively flushes
and re-issues only those instructions that miss the registercache and its dependent instructions.
• PRED-PERFECT: This model is extremely idealized.
It uses hit/miss prediction described in Section III-C witha 100% hit rate. This removes absolutely any possible
pipeline disturbance caused by register cache misses.
Thus, the performance degradation from a model with“infinite” register cache only comes from consuming
twice the issue width and delaying the execution of
instructions that caused the register cache misses (Section III).

As described in Section V-B, Both NORCS and LORCS
have the same benefit that is to reduce the circuit area andthe energy consumption of the register file. However, performance of both model is significantly different. Therefore,
it is important to compare areas and energy consumption
per performance of each model. First, we show evaluation

results of performance, area and energy consumption, andthen we show relationship among them.
1) Register Cache Hit Rate: In addition to LRU andthe use-based policy, we show evaluation results of pseudo
optimal replacement policy in this section. OPT replacement
policy is known as an ideal replacement policy, which
replaces the entry that will not be referred to for the longest
time by any instructions. POPT replaces the entry that will
not be referred until the furthest future only by the in-flight
instructions.
Figure 12 shows the average register cache hit rates in
LORCS over all the benchmark programs. POPT and USE-B
indicate models with the pseudo optimal replacement policy
and the use-based policy, respectively. The number of themain register file ports is fixed at 2-read/2-write and theregister cache miss model is fixed to STALL, because theresults are strongly influenced only by the number of entries
and replacement policies of the register cache. We also
evaluated register cache hit rates in NORCS, but we only
show the results for LORCS because there are no significant
differences between these 2 models.
USE-B models show considerably high hit rates. The
hit rates of USE-B models are higher than those of LRU
models by about 3–4%, and as high as those of ideal POPT
models. Hereafter, we use USE-B for LORCS while LRU
for NORCS. NORCS shows better performance in spite of
the lower hit rates of LRU.
2) Configuration of LORCS: LORCS has more parameters than NORCS. For the remainder of this section, we
limit the search space for LORCS.
The Number of the main register file Ports: First,
we evaluated the IPC of LORCS and NORCS models
changing the number of the ports of the main register file.
Figures 13(a) and 13(b) show average relative IPCs to themodel with a full-port main register file, that is 8 read /4
write. Figure 13(a) changes the number of the write ports
while fixing the number of the read ports at 2. On thecontrary, Figure 13(b) changes the number of the read ports
fixing the number of the write ports at 2. We only show the

Table IS IMULATION C ONFIGURATIONSNameBaseline
Ultra-wide
ISA
Alpha
←
pipeline stages fetch:3, rename:2,
fetch:4, rename:5,
dispatch:2, issue:2
dispatch:2, issue:1
fetch width
4 inst.
8 inst.
execution unit
int:2, fp:2, mem:2.
int:6, fp:4, mem:2.
inst. window
int:32, fp:16, mem:16
unified:128ROB
128 entries
512 entries
branch pred.
8 KB g-share
16 KB g-sharemiss penalty
11∼12 cycles
14∼15 cycles
BTB
2 K entries, 4 way
4 K entries, 4 way
RAS
8entries
64entries
L1C
32 KB, 4 way,←
64 B/line,3 cycles
L2C
4 MB, 8 way,←
64 B/line, 10 cycles
main memory
200 cycles←

Table IIPARAMETERS OF REGISTER FILE SYSTEMSNameBaseline
Ultra-wide
PRF latency
2 cycles←PRF capacity
int:128, fp:128
int:512, fp:512
PRF ports
12 ports
24 ports
RC latency
1 cycle←RC capacity
4, 8, 16, 32, 64 entries 16, 32, 64 entries
RC associativity full
2-way
MRF latency
1 cycle←MRF capacity
int:128, fp:128
int:512, fp:512
MRF ports
read:1-3
read:4
write:1-3 ports
write:4 ports
write buffer
8 entries←
use predictor
4 K entries, 4 way,←
4 bits/pred,
2 bits/conf,
6 bits/tag,
6 bits/future ctl

B. Evaluation Result

308

80
75
70

Figure 12.
(LORCS)

4

8
16
32
64
Register cache capacity (entries)

LRU

Relative IPC

PRF-IBNORCS

LRU

8 entires
min

USE-B

LORCS

(a) Fixing read ports at 2

LRU
NORCS

464.h264ref

Figure 15.

LRU

USE-B

LORCS

LRU

0.3
R2/W2 R3/W2 R8/W4
Read ports / write ports(b) Fixing write ports at 2
NORCS infinite
LORCS
infinite
R8/W4

max

LORCS

infinite

PRF-IBminaverage

Average relative IPC

4

8
16
32
64 infinite
Register cache capacity (entries)

1
SELECTIVE-FLUSH
PRED-PERFECT
0.9
0.8
0.7
0.6
0.5
0.4
0.3
STALL 4816 FLUSH
32
64 infinite
Read ports / write ports

Figure 14. Avg. relative IPC (LORCSUSE-B)

1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0

NORCS LORCS NORCS

32 entires
433.milc

N/A

0.6
0.4

Avg. relative IPC (fixing MRF ports)

N/A

0.7
0.5

1.05
NORCS
NORCS 16 entries
NORCS 32 entries
1 8 entries
0.95
0.9
0.85
0.8
0.75
0.7
0.65
LORCS 8 entries R2/W1 LORCS 16 entries
LORCS 32
entries
R2/W2
R2/W3
Read ports / write ports

16 entires
456.hmmer

0.85

R1/W2

Relative IPC
USE-B

0.8

0.9

R2/W2 R2/W3 R8/W4
Read ports / write ports

1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
LORCS

0.95

0.75

Figure 13.

LRU

0.9

0.8
R2/W1

Register cache hit rate

1

1

Relative IPC

POPT
USE-B
LRU

1.05

Rel
ativ
e…

85

1.05
1
0.95
0.9
0.85
0.8
0.75
0.7
0.65

Relative IPC

90

Relative IPC

95

Rel
ativ
e
IPC

Register cache hit rate (%)

100

Figure 16.

NORCS

16 entires
456.hmmer 465.tonto

LORCS

NORCS

32 entires
464.h264ref 401.bzip2

LORCS

NORCS

64 entires
max

average

Average relative IPC of ultra-wide superscalar processor

such as “456.hmmer” are specific programs that show thelowest and the highest performance.
The IPC degradation of NORCS models is considerably
small; it is only 2.0%, even with an 8-entry register cache.
Furthermore, the variations of the IPC of the various programs are also small. The performance of NORCS is notsensitive to the register cache hit rates (Section V-B).
The LORCS models with an “infinite”-entry register cacheand of 32-entry register cache with USE-B policy show theperformance improvement relative to the baseline model dueto the shortened pipeline, although this is only 2.1% and0.2%, respectively.
On the other hand, LORCS models with the other configurations show significant performance degradation. Even
with USE-B policy, the average degradation is 16.9% and7.3% for an 8- and 16-entry register cache, respectively. WithLRU policy, the degradation is more marked — the averagedegradation is 20.8%, 10.0%, and 3.6% for an 8-, 16-, and
32-entry register cache, respectively.
In addition, the degradations of LORCS largely vary fromprogram to program. In particular, the IPC degradation of
LORCS with LRU for 456.hmmer is no less than 25% evenwith a 32-entry register cache.
This is because the performance of LORCS is moresensitive to the register cache hit rates (Section V-B). The
register cache hit rates depends highly on the replacement
policy, and largely varies from program to program. It is
undesirable to show such low performances for specificprograms even if the average performance is acceptable.
On the whole, in order to overachieve the PRF-IB model,
only 8-entry register cache is necessary for NORCS, while
32-entry register cache and USE-B policy is necessary
for LORCS. Moreover, these configurations are adequate

results for models with for an 8-, 16-, 32- and “infinite”entry register cache because models with a 4- and 64 entry
register cache show the same tendency.
These graphs show that 2 read ports and 2 write ports
in the main register file are sufficient to maintain theperformance of the full-port main register file. Hereafter,
we fix the number of the ports of the main register file at2-read/2-write.
Behavior on a Register Cache Miss of LORCS: Figure 14 shows the average relative IPCs of the models withdifferent behaviors on a register cache miss, while changing
the number of entries in each register cache. The IPCs are
given relative to a model with “infinite” register caches.
As we explained in Section III, the graph shows that
FLUSH models have the worst performance. On the other
hand, the realistic STALL models have almost the same
performance as the ideal SELECTIVE-FLUSH and PREDPERFECT models. The ideal SELECTIVE-FLUSH model
selectively flushes dependent instructions, however, a register cache miss penalty of each flushed instruction is muchlarger than that of STALL model, as described in Section III.
Therefore, there are no significant differences between these2 models.
Thus, hereafter, we fix the behavior on the register cache
miss to STALL.
3) IPC: Figure 15 shows the IPCs for each model
relative to the baseline PRF model for an 8-, 16-, 32- and“infinite”- entry register cache. We only show the results
for these models because models with a 4- and 64 entry
register cache show the same tendency. We evaluated PRFIB model, LORCS model with LRU and USE-B policy, andNORCS model with LRU policy. The “min”, “max” and“average” bars are the minimum, maximum, and average ofthe programs in the benchmark, respectively. The other bars309

Table III
E FFECTIVE MISS RATE
Issued
0.44
1.88
1.91
1.48

429.mcf
456.hmmer
464.h264refaverage

LORCS with 32 entry-RC (USE-B)
Read RC Hit(%)
Effc Miss(%)
0.53
92.2
3.4
2.49
94.2
15.7
2.57
99.0
8.8
1.90
98.6
2.7

IPC
0.99
0.90
0.95
1.00

4

8
16
Register cache capacity (entries)

Figure 17.

32

64

0.4

Main register
file

4

Relative areas

8
16
Register cache capacity (entries)

Figure 18.

32

NORCS

NORCS

0

LORCS

0.2
LORCS

NORCS

LORCS

NORCS

LORCS

NORCS

LORCS

NORCS

LORCS

NORCS

LORCS

PRF

0.2

Register cache

0.6

NORCS

Main register
file

LORCS

0.4

Use predicto

NORCS

Register cache

0.6

1
0.8

LORCS

0.8

1.2

NORCS

Use predictor

LORCS

Relative Energy consumption

Relative Area

1

0

IPC
1.00
0.90
0.92
0.98

1.4

1.2

PRF-IB

1.4

NORCS with 8 entry-RC (LRU)
Read RC Hit(%)
Effc Miss(%)
0.60
82.83
0.98
2.53
62.95
11.7
2.51
73.14
8.7
1.89
79.91
2.3

Issued
0.49
1.90
1.87
1.46

64

Relative energy consumption

are the same in both NORCS and LORCS because they havethe same number of entries and ports. The area of the main
register file is reduced to 12.2%, because the number of theports of the main register file is reduced from 12 to 4, andthe area of a register file is proportional to the square of thenumber of the ports.
The area of use-predictor is 36.1% of that of the register
file in PRF-IB model. The area of use-predictor is relatively
large compared with that of the register cache and the main
register file, because the use-predictor has many ports. Generally speaking, a predictor like the use-predictor requires
the same number of read ports as the fetch width and thesame number of write ports as the retirement width. The
read ports are used to get predicted data on the frontend
stages, while the write ports are used to write training dataon the retirement stages [18]. In the evaluated configuration,
the use-predictor requires 4-read/4-write ports.
In NORCS, the total area of the main register file and theregister cache is reduced to 19.9%, 24.9%, 34.7%, 42.0%,
and 98.0% of the register file of PRF model for a 4-, 8-, 16-,32- and 64-entry register cache, respectively. In LORCS, thetotal area of the main register file and the register cache is
the same as that of NORCS, but the total area including usepredictor is much larger than that of NORCS. The total areas
including use-predictors are 56.1%, 61.0%, 70.8%, 90.3%,
and 134.1% of the register file of PRF model for a 4-, 8-,16-, 32-, and 64-entry register cache, respectively.
Energy Consumption: Figure 18 shows the energy
consumption of the register cache, main register file anduse-predictor in each model relative to the register filein PRF model. The energy consumption is evaluated foreach benchmark programs, and then averaged over all the
programs.
The total energy consumption of the register cache andthe main register file is reduced to about 28.2%, 31.9%,
40.6%, 59.0%, 96.3% for a 4-, 8-, 16-, 32-, and 64-entry
register caches. In LORCS and NORCS, the total energy
consumption of the register cache and the main register filebecause they achieve almost the same performance as themodels with “infinite”-entry register cache.
4) Effective miss rate: Table III shows the effective missrates, which is given by the probability of the pipeline
disturbance. This table shows the results for LORCS with32 entry USE-B register cache and NORCS with 8 entry
LRU register cache. These 2 models show almost same
performance in Section VI-B3. This table shows the resultsof characteristic benchmark programs and average of the all
benchmark programs. “Issued ” and “Read” are the number
of issued instructions per cycle and the number of operands
reading the register cache per cycle, respectively. “RC Hit”
and “Effec Miss” are register cache hit rate per access andeffective miss rate, respectively.
As described in Section V-B, effective miss rate in
LORCS is much worse than the miss rate of the registercache itself. 464.h264ref shows that the register cache hit
rate is as high as 99.0%, but an average number of operands
that access the register cache a cycles is 2.57 and theeffective miss rate is 8.8%. As a result, the IPC degradationfor 464.h264ref is 5.1%.
As described in Section V-B, effective miss rate in
NORCS is not sensitive to the register cache hit rates. thetable show that the register cache hit rates for the NORCS
model is much worse than those of the LORCS model, because register cache capacities of these models are different.
However, the effective miss rates and IPC degradations are
not much different from those of the LORCS model.
5) Circuit Area and Energy Consumption: We evaluatedthe area and the energy consumption of each model using
CACTI 5.3 model [2]. We evaluated ITRS 45nm and 32nm
technology nodes [19], but we only show the results for
32nm node because both show the same tendency.
Circuit Area: Figure 17 shows the circuit areas relative
to that of PRF model. The areas include those of the registercache, main register file and use-predictor.
The areas of the register cache and the main register file

310

0.8
0.75
0.7
0

0.25

0.5
0.75
1
Energy consumption

1.25

1.5

Energy -71.9%

0

0.25

PRF-IB
0.25

NORCS LRULORCS LRULORCS USE-B
0.5
0.75
1
1.25
1.5
Energy consumption
Trade-off
between IPC and energy

1.25

1.5

(b) Worst
IPC(a) Average

0.5
0.75
1
Energy consumption

0.5
0.6
0.7
0.8
0.91
PRF

0

Figure 19.

differs slightly, because the number of accesses and the time
to execute the programs differ slightly.
The energy consumption of the use-predictor is 48.1%of that of the register file in PRF-IB model. In LORCS, thetotal energy consumption of the register cache, main register
file and use-predictor is 77.4%, 79.8%, 86.7%, 103.8%, and140.1% for a 4-, 8-, 16-, 32- ,and 64-entry register caches.
6) Trade-off between IPC and Energy Consumption:
Figure 19(a) shows the relative IPC per energy consumptionin each model. Each IPC and energy consumption is relative
to the register file in PRF model and is the same as those in
Figures 15 and 18. Each data point of the line in this figure
indicates a value of the model with a 4-, 8-, 16-, 32-, and64- entries register cache from left to right.
The figure shows that NORCS reduces energy consumption without large performance degradation. On the other
hand, in LORCS with LRU and USE-B, performance andenergy consumption are trade-offs. LORCS with fewer entries of a register cache reduces energy consumption, but
performance also degrades.
There are no significant difference of IPCs between
NORCS with 8-entry LRU register cache and LORCS with
64-entry register cache of LRU policy, and the differenceis 1.8%. However, the energy consumption of the model of
NORCS is reduced by 69.3% from the model of LORCS.
NORCS and LORCS with 8 entries LRU register cache show
almost the same energy consumption. However, the model of
NORCS improves IPC by 18.7% from the model of LORCS.
Figure 19(b) shows the relative IPC per energy consumption in the benchmark with the worst IPC in Figure 15.
This figure shows the properties of NORCS and LORCS
more clearly. NORCS with a 8-entry LRU register cacheand LORCS with a 32-entry USE-B register cache show
almost the same IPCs, but the former reduces the energy
consumption by 71.9% from the latter. NORCS with thesame configuration and LORCS with 8-entries LRU registercache show almost the same energy consumption, but themodel of NORCS improves IPC by 31.1% from the modelof LORCS.

1.05
1
0.95
0.9
0.85
0.8
0.75
0.7
0.65
0.6

Energy -71.6%
IPC 23.0%

0.9
0.85

IPC

IPC 18.7%

IPC

0.95

1.05
1
0.95
0.9
0.85
0.8
0.75
0.7
0.65
0.6
0.55
0.5

IPC

Energy -69.3%

1

IPC 31.1%

1.05

0

0.25

0.5
0.75
1
Energy consumption

1.25

1.5

(c) Average (SMT)

this subsection, we evaluated the register cache system onthese ultra-wide superscalar processors.
The right columns of Tables I and II, labeled “Ultrawide”, show the configurations of an 8-wide superscalar
processor, used as the baseline model in this section. Thisconfiguration is almost the same as that used in [10]. The
models of the register cache systems are almost the same as
those described before, but some parameters are changed tomatch the evaluation of Butts et al. Specifically, the numberof the ports of the main register file is 4-read/4-write, andthe register cache is 2-way set-associative that uses a uniqueindexing policy proposed by Butts et al. [10].
Figure 16 shows the IPCs for each model relative tothe baseline PRF. The labels are the same as the ones in
Figure 15. The results show a similar tendency to those in
Section VI-B3. The IPC degradation of NORCS models is
small — 0.12%, 0.6%, and 0.03% for a 16-, 32-, and 64entry register cache, respectively. On the other hand, the
LORCS show significant performance degradation — 16%,
9.7%, and 4.3% for a 16, 32, and 64-entry register cache,respectively.
Butts et al. evaluated the performance improvement of
LORCS compared to PRF-IB models, and showed that a 64entry register cache with USE-B policy outperforms PRF-IB[10]. Our evaluation results show that LORCS with a 64entry register cache and the same parameters outperforms
PRF-IB by 6.6%, and this closely matches their result of
6%. NORCS with a 16-entry register cache, on the other
hand, outperforms PRF-IB by 10.1%.
These results show that NORCS also works well on ultrawide superscalar processors. Specifically, NORCS with a 16entry register cache with LRU policy outperforms LORCS
with a 64-entry register cache with USE-B policy in thisconfiguration.
D. Evaluation on SMT Processor
As described in Section I, SMT suffers from a need fora larger register file. We evaluate our proposal on a SMT
with the same configuration given in Table I and a 2-way
SMT feature. Figure 19(c) shows the relative IPC per energy
consumption in each model. We executed 2 threads for all
the combinations from 29 programs in SPEC CPU2006.
The IPC degradations in whole models are worse thanthose in single thread execution (Section VI-B3). However,C. Evaluation on Wide Superscalar Processor
Previous researchers have targeted ultra-wide superscalar
processors with 8-wide and 512-entry register files [10]. In

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the IPC degradation in NORCS models is still small; theaverage degradation is 4.1% and 1.8% for an 8- and 16entry register cache. On the other hand, LORCS models
show significant performance degradation. Even with USE-B
policy, the average degradation is 26.0%, 16.5%, and 3.1%
for an 8-, 16-, and 32-entry register cache.
There are no significant difference of IPCs between
NORCS with 8-entry LRU register cache and LORCS with
32-entry register cache of USE-B policy, and the difference is 0.94%. However, the energy consumption of the
NORCS model is reduced by 71.6% from the LORCS
model. NORCS and LORCS with 8 entry LRU registercache show almost same energy consumption. However, theNORCS improves IPC by 23.0% from the LORCS.

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Processing, 2006, pp. 337–346.

VII. C ONCLUSION
A register file is one of the most costly units in the recent
superscalar processors. A large register file causes many
problems as described in Section I. This paper introduces
NORCS, a new technique of the register cache system that
does not reduce the latency. NORCS is characterized by aunique pipeline that assumes miss of the register cache. We
just add a set of pipeline latches to a conventional registercache system in order to add pipeline stages to read themain register file. This minimum modification causes a great
difference in performance, because the pipeline of NORCS
is not disturbed only on register cache misses.
We evaluated the IPC, area, and energy consumption of
NORCS, LORCS, and pipelined register file on a practical
4-way and an ultra-wide 8-way superscalar processor. The
evaluation results show the area and the energy consumptionof NORCS is reduced to 24.9% and 31.9% of the pipelined
register file, respectively, at a minimum cost of 2.1% IPC
degradation. NORCS using the small 8-entry register cachewith LRU policy achieves the same level performance as
conventional LORCS using a 32-entry register cache withuse-based policy, which shows very high hit rates that are
as high as the ideal model, and in this configuration, thearea and the energy consumption of NORCS is reduced to27.6% and 31.9% of LORCS, respectively.

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ACKNOWLEDGMENT
This research is partially supported by Grant-in-Aid for
Scientific Research B #20300015 from Ministry of Education, Culture, Sports, Science and Technology Japan,
Grant-in-Aid for JSPS Fellows #219259, from the Japan
Society for the Promotion of Science, and Semiconductor
Technology Academic Research Center (STARC) Japan.

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[17] SPEC CPU2006 suite, The Standard Performance Evaluation
Corporation. http://www.spec.org/cpu2006/

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