S i T C P Manual
Version 3.0

26th May 2021

Tomohisa UchidaElectronics system group, IPNS, KEK

Revised/Edited by Bee Beans Technologies Co.,Ltd.

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1. History
Date of
Modifications

Version Contents

2011/01/18
2011/01/19
2011/04/14
2012/10/24

1.0
1.1
1.2
1.3

Enacted Version 1.0.
Version 1.1 Correction of errata.
Added detailed descriptions about internal register.
Added supplementary descriptions to “10. SiTCP Internal Register/Detailed Procedures”.

2012/11/12

1.4

Corrected the errata on User I/F Signal Input/Output (TCP_CLOSE_REQ,
TCP_CLOSE_ACK).

2012/11/21

1.5

Added description about TCP_CLOSE_REQ/ACK.

2014/08/11
2016/04/18

1.6
2.0

Typographical correction in Figure 6.
Added FIFO capacity condition for data reception.

After that, this document is revised by Bee Beans Technologies Co., Ltd., for maintenance.
2021/05/26

3.0"2. Introduction"⚫ Newly added, and the subsequent chapter numbers are moved up.
“10. SiTCP Internal Register /Detailed Procedures”⚫ Added to the internal register map (+ 0x10 bit6-3, + 0x3C-3F).
“12. References ”⚫ Deleted the URL of Web site of SiTCP and BBT.

2. Introduction
This document is the revised version of "SiTCP Manual"(created by Dr. Tomohisa Uchida) by Bee
Beans Technologies Co., Ltd. (BBT). SiTCP is the Network Processor developed by Dr. Tomohisa
Uchida and managed/distributed by BBT.

3. Contents
This document describes the introduction of the Network Processor (SiTCP) and the outline of how to
use it. For concrete implementation methods using the SiTCP Library, see the separate document“SiTCP Library” after reading this document.

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4. What is SiTCP?
SiTCP is the technology to connect a physical experiment frontend to PC via Ethernet.

Board developed by user

Measurement data

User
circuit
Detector

User circuit and SiTCP can be
implemented on a same FPGA

Slow control

Fig.1 An example of SiTCP standard use
In the experimental electronics development, we often develop a read-out circuit close to the detector.
This is because there is no generic instrument available that can be used in such near-detector parts.
The data from the detector needs to be transferred to PC by any means. SiTCP can use the Ethernet
for such data transfer.
The measurement data is transferred to the PC with SiTCP by writing the data in SiTCP along theprocedure to write in a synchronous FIFO. SiTCP can be described as the technology to provide adata pipe between the user circuit and the PC. The data written in SiTCP will appear on the PC.
The slow control from the PC to the user circuit is a remote bus control. SiTCP has a bus operable ona simple protocol for the user circuit control, like the VME bus. Sending the UDP packet to SiTCP
with its packet format pre-determined by the PC generates a bus signal to control the user circuit.
Since SiTCP supports the read/write function, the slow control can be implemented by adding any
simple circuit to the user circuit.

5. Advantages in Ethernet connection
The advantages in using Ethernet include the following.
⚫
⚫
⚫
⚫
⚫

You do not need to create the device driver on PC side.
➢ In many cases, it is implemented as standard in your OS.
You can write programs only with standard functions.
➢ Socket programming➢ Many OSs support socket functions.
You can build a virtual and flexible system structure.
➢ Connected to HUB, the structure is configurable only on the software.
Long distance communication is possible.
Ethernet particularly has the following advantages.
➢ High connectability between different technology generations (compatibility)➢ Technological evolution corresponding to any technological development (Latest is
40G/100Gbps)➢ Low cost and wide varieties of the commercially available products➢ Multiple media (Optical, UTP etc.)

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6. Features
SiTCP features the following.
⚫

⚫

Hardware TCP/IP/Ethernet communication➢ 10Mbps to 1Gbps Ethernet➢ High speed communication stable at the upper limit of TCP➢ Slow control function (Using UDP)
Easy implementation➢ Small circuit scale➢ Provided as FPGA library (Xilinx)➢ Simple user I/F easy to handle

7. Standard implementation example
SiTCP provided as Xilinx library is usually implemented to FPGA. Below shows the examples forwhich the standard twisted cable (UTP) is adopted for the Ethernet port as well as with optical cables.
When using UTP
Ethernet standard I/F

Commercially available IC

When using Optical I/F

Optical I/F can be implemented within FPGA

Fig.2 Standard implementation example
An example with a standard twisted cable is shown in the upper figure and with an optical cable in thelower.
When using the twisted cable, I/F chip for the Ethernet connection is required. Since SiTCP adopts astandard I/F, MII/GMII, you can use any standard chips available from the manufacturers. Use theproven and recommended devices if there are no particular problems, in using SiTCP library. Whenusing the devices other than the recommendations, you need to fabricate a new register initialization
circuit for your PHY devices.
The parts and user I/F required to operate SiTCP are shown in the figure below.

4 / 27FPGA data
IF signal provided from Xilinx
Two types of I/Fs fordifferent applications
Externally provided when using UTP
FIFO I/F for TCP

Only connecting the signals from SiTCP
ROM for storing network parameters
MAC address, etc.

Fig.3 Required parts and user I/F
The following four parts are required to operate SiTCP.
1. FPGA from Xilinx: The FPGA to implement SiTCP
2. ROM for FPGA: The ROM to store FPGA data
3. EEPROM：The ROM to store the network parameters such as MAC address etc.
4. Ethernet PHY device: required when UTP adopted
Items 1 and 2 are required to implement SiTCP. Choose FPGA capacity with some allowance. You
can find SiTCP size by synthesizing the library. Estimate and choose the FPGA capacity by presynthesizing the library.
Item 3 is the ROM to store the network parameters for SiTCP. Here, many parameters such as IP
address, MAC address, TCP operational parameter are stored. SiTCP sets the parameters from this
ROM to the read-out circuit only once after its launch. It also has the mode to read default values, i.e.,
standard values, compulsorily for directly after the manufacturing, or the case with abnormal values
written in. This mode is normally used to re-write the contents of EEPROM or assess libraries.
Item 4 is pre-requisite when UTP used. Since SiTCP adopts a standard I/F, MII/GMII, you can use
any standard chips available from the manufacturers. Use the proven and recommended devices when
there are no particular problems, in the SiTCP library. When using devices other than therecommendations, you need to fabricate a new register initialization circuit for PHY devices.
Since the products incorporated with the PHY device for optical I/F are available, the external PHY
devices are not always required when using optical I/F.
There are two types of user I/F to connect SiTCP and the user circuit. These are TCP FIFO I/F used
for data transfer and the slow control I/F used for register control etc. SiTCP adopts simple interfaces
since it has been developed assuming the users are non-expert for circuit development. Since TCPFIFO I/F for data transfer is the I/F similar to the synchronous FIFO, the data written in SiTCP
sequentially is transferred to the PC automatically. The slow control I/F is the control I/F adopting asimple bus access protocol that consists of address signal, data signal, read/write signal and etc. Since
this is a synchronous circuit, you can design it more easily than the standard bus systems such as VME
bus etc. For detailed descriptions about the user I/F, refer to the later sections.

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8. I/F Signal
Each of the following I/F signals for SiTCP library are described here.
⚫
⚫
⚫
⚫

System I/F
MII / GMII
User I/F
Network parameter setting I/F

System I/F
The following system I/Fs are associated with the entire SiTCP operation.
Signal name

I/O Description

CLKI

The system clock over 130MHz is recommended.
Over 15MHz is recommended to operate Ethernet below 100Mbps.
RST
I System reset
TIM_1USI 1us Periodic pulse (*1)
TIM_1MSI 1ms Periodic pulse (*1)
TIM_1SI 1 sec Periodic pulse (*1)
TIM_1MI 1 min Periodic pulse (*1)
EEPROM_CS
O Connected to CS terminal of AT93C46D
EEPROM_SK
O Connected to SK terminal of AT93C46D
EEPROM_DI
O Connected to DI terminal of AT93C46D
EEPROM_DO
I Connected to DO terminal of AT93C46D
SiTCP_RSTO SiTCP internal reset output (*2)
All the signals are synchronous signals of the system clock CLK(*1) The periodic signal with its system clock 1 pulse width H. All the TIM* signals must be
synchronized in their phases.
(*2) The reset signal output when SiTCP is in reset state. Usable as a reset of the external circuit.
Since, inside SiTCP, the system reset RST is extended along the internal circuit, it keeps reset for acertain period of time after the system reset is released.

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MII/GMII
There are some notices concerning MII/GMII interface connection to SiTCP.
MII is the standard used in Ethernet up to 100Mbps. GMII is the standard used in Gigabit Ethernet.
These two standards are quite similar but have some differences. Since they have much in common,
the PHY signal is compliant for both of them. It needs to be switched for MII or GMII according to
the Ethernet speed.
GigaSiTCP can be used exclusively for MII.

I/F Signal
The signals associated with MII/GMII are shown below.
Signal name
MODE_GMII

I/O DescriptionI
Set this signal to 1 when using GMII-compliant PHY or 0 with
PHY for MII only.

GMII_1000M
GMII_RSTn
GTX_CLKIOOGMII_TX_CLKI

GMII_TX_EN
GMII_TXD
GMII_TX_ER
GMII_RX_CLK
GMII_RX_DV
GMII_RXD
GMII_RX_ER
GMII_CRS
GMII_COL
GMII_MDC
GMII_MDIO_IN
GMII_MDIO_OUT
GMII_MDIO_OE

O
O
O
I
I
I
I
I
I
O
I
O
O

Generated from SPEED LED of PHY device (Notice 1)
Connected to the reset of PHY device.
This is not a SiTCP signal but needed for GMII connection.
Connected to GTX_CLK of PHY device.
Generating 125MHz inside FPGA (Notice 2)
Input TX_CLK of PHY devices on MII operation or 125MHz
same as GTX_CLK generated in FPGA on GMII operation.
Connect to TX_EN of PHY device.
Connect to TXD of PHY device.
Connect to TX_ER of PHY device.
Connect to RX_CLK of PHY device.
Connect to RX_DV of PHY device.
Connect to RXD of PHY device.
Connect to RX_ER of PHY device.
Connect to RX_CRS of PHY device.
Connect to RX_COL of PHY device.
Connect to MDC of PHY device.
Connect to MDIO of PHY device.
Connect to MDIO of PHY device via 3 state buffer.
3 state buffer control signal for GMII_MDIO_OUT(Notice 1) The signal to switch MII/GMII operation, generated from LED that displays the PHY
output speed. 1 for Gigabit Ethernet (GMII) and 0 for 100Mbps Ethernet (MII). Notice that the logic
may be reversed when using LED.
(Notice 2) The transmission clock for Gigabit Ethernet. FPGA outputs 125MHz towards PHY.
Although PHY outputs the transmission clock when using MII, FPGA must output it with GMII.

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Connection for GIGABIT ETHERNET compliant PHY devices
The connections between SiTCP and MII/GMII when using Gigabit Ethernet compliant PHY devices
are shown in the figure below.

System clock
generation

125MHz clock
generation

Fig.4 Connections between SiTCP and MII/GMII (Gigabit Ethernet compliant)Some notices are listed below.
⚫
⚫
⚫

Connect TX_CLK and RX_CLK to the global clock input pins of FPGA
Connect MDIO via 3 state buffer
Use primitive BUFGMUX or any equivalent primitives to switch GMII_TX_CLK

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Connection for GIGABIT ETHERNET non-compliant PHY devices
The connections between SiTCP and MII when using Gigabit Ethernet non-compliant PHY devices
are shown in the figure below.

System clock
generation

Unconnected

Fig.5 Connections between SiTCP and MII/GMII (Gigabit Ethernet non-compliant)Some notices are listed below.
⚫
⚫
⚫
⚫
⚫

Connect TX_CLK and RX_CLK to the global clock input pins of FPGA.
Connect MDIO via 3 state buffer.
Input 0 to GMII_1000M
Leave GMII_TXD[7:4] unconnected since it is not used.
Input 0 to GMII_RXD[7:4] since it is not used.

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User I/F
SiTCP has the following two user I/Fs.
⚫
⚫

TCP I/F (for data transfer)
Slow control I/F (for control of register access etc.)

TCP I/FTCP I/F has the following features.
⚫
⚫
⚫
⚫
⚫
⚫
⚫

Used for data transfer with PC
High speed transfer is possible.
All the signals are synchronized to the system clock.
All the signals are in positive logic.
I/F similar to the synchronous FIFO
Transmission/reception independent
It transitions to a usable state when the TCP connection is established.

TCP I/F can transmit or receive signals independently. FIFO memory needs to be inserted between
SiTCP and the user circuit when using the reception function. The TCP reception function is notneeded when the data transfer from PC to the user circuit is not required. However, when the transfer
is required and the slow control function described in the next chapter does well for it, use the slow
control function instead of TCP reception function. The reasons for not using the reception function
include difficulty in simultaneous control of transmission/reception processed at a high-speed using
socket programming as well as the need for FIFO memory addition.

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I/F Signals
I/F signals are shown in below. I/Os are the input/output viewed from SiTCP. The signal given to
SiTCP is I and the one output by SiTCP is O.
Signal name

I/O Description

TCP_OPEN_ACK
TCP_CLOSE_REQ

OO

Indicates the communicable state
Indicates the reception of communication-termination
demand from PC

TCP_CLOSE_ACK
TCP_TX_DATA[7:0]
TCP_TX_WR
TCP_TX_FULL
TCP_RX_DATA[7:0]
TCP_RX_WR
TCP_RX_WC[15:0]

I
I
I
O
O
O
I

Communication-termination response
Transmission byte data
Transmission data write enable
Transmission buffer full flag
Reception data
Reception data valid
The number of data bytes stored in reception buffer

Communication state control
In TCP communication, both sender and receiver ensure the data transfer by notifying the data transfer
status to each other.
First, each counterpart is checked if communicable. After the check (establishment of TCP
connection), the data transfer is started. The establishment of TCP connection is equivalent to thenormal termination of the ‘connect’ function in the socket programming.
A communication-stop demand is issued to the counterpart when the communication needs to beterminated. The communication is terminated on the reception of the communication-termination
response from the counterpart.
As above, the TCP communication must be done while the TCP connection is established. Also, on
the reception of communication-termination demand from the PC, the data transfer must be quickly
terminated, and the communication-termination response must be transmitted. SiTCP has the control
signals for the communication according to the above TCP provisions. The time-chart for the control
signals from the TCP connection establishment to its termination, is shown below.

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Becomes H on TCP connection established

OPEN_ACK becomes L earlier
than CLOSE_REQ

Becomes H on reception of ‘close’ from PC
Make this H after user sends data up to any terminable point.
Once making the H, retain the H while TCP_CLOSE_REQ=H.
Usually OK in directly connecting TCP_CLOSE_REQ to TCP_CLOSE_ACK
Fig.6 Time-chart for TCP control signals
TCP communication is permitted while TCP_OPEN_ACK is set to H and TCP_CLOSE_REQ set to L.
After TCP_CLOSE_REQ is set to H, the user circuit must finish its data-writing up to any
terminatable point and then set TCP_CLOSE_ACK to H in order to issue a termination-response.
SiTCP sends a connection termination confirmation when all the transmitted data has been sent.
However, since the PC has stored the received data already up to when it receives TCP_CLOSE_REQ,
the data transmitted thereafter will be discarded by the PC. Therefore, it works well without any
problems if the user circuit directly connects TCP_CLOSE_REQ and TCP_CLOSE_ACK, andterminates the transmission immediately when TCP_CLOSE_REQ=H. If TCP_CLOSE_REQ=H is
set and then TCP_CLOSE_ACK=H is answered and transmission data is continuously written, SiTCP
will continue to transmit data to the PC. Therefore, in this state, the connection will not be closed even
if TCP_CLOSE_ACK=H. Be sure to stop sending the data when TCP_CLOSE_REQ is set to H.
Retain TCP_CLOSE_ACK to H while TCP_CLOSE_REQ=H.
As above, TCP_OPEN_ACK signal is equivalent to the data receivable state of PC.
TCP_OPEN_ACK can be used as a negative logic reset signal of the user circuit when the PC is notreceivable and the user circuit is preferred unoperated. TCP_OPEN_ACK becomes L earlier than
TCP_CLOSE_REQ. So, when using TCP_OPEN_ACK as a reset, design it very carefully so that
TCP_CLOSE_ACK does not become L on the reset while TCP_CLOSE_REQ is H.

Data Transmission
The data can be transmitted only in the communicable state where the TCP connection has been
established. When writing in the transmission data, notice that the writing operation needs to be
stopped when the transmission buffer becomes full. The time-chart for the transmission data write-in
is shown below.

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Write data with WR=H on FULL=L

Stop writing within
8 clocks
Fig.7 Time-chart for transmission data write-inThis is the same interface as that for the synchronous FIFO memory.
TCP_TX_WR and TCP_TX_DATA[7:0] are used to write-in the transmission data. Putting thetransmission data in TCP_TX_DATA with a synchronization to the system clock and setting
TCP_TX_WR=H, will make the transmission. Since the circuit is synchronous, every leading edge of
CLK is regarded as a byte data.
Now, it is in the state where the TCP connection has been established, and possible to write in the data
on TCP_TX_FULL=L. In the course of the transmission, whenever TCP_TX_FULL=H, stops thetransmission operation within 8 clocks and set TCP_TX_WR=L. The transmission operation can beresumed when TCP_TX_FULL=L. Repeat the above while the TCP connection is established.

Data Reception
When using the TCP reception function, place a reception buffer FIFO between the user circuit and
SiTCP. The TCP data reception signal of SiTCP is set connectable directly to the FIFO generated by
Xilinx Core Generator.
When generating FIFO memory using Core Generator, configure it as follows.
⚫
⚫
⚫

Write-in data bit width = 8bit
Word count option enabled, Word count bit width maximized
Condition of FIFO capacity➢ 65536 ≥ FIFO capacity (bytes)> 2 × (SiTCP TCP MSS +58)
➢ The default value of MSS for SiTCP is 1460 (see Chapter 10. “SiTCP Internal Register”).

The time-chart for the data reception is shown below.

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Valid data when TCP_RX_WR=H

Reflect within 8 clocks
Fig.8 Data reception time-chart
When SiTCP receives the data, it puts it to TCP_RX_DATA[7:0] in the received order and sets
TCP_RX_WR=H to notify the reception of the valid data.
Connect TCP_RX_DATA[7:0] to the write-in data terminal and TCP_RX_WR to the write-in enableterminal, of the synchronous FIFO, respectively.
Since the receiver must always notify to the sender how many bytes are receivable, notify using
TCP_RX_WC[15:0] how many bytes of data are stored in the reception buffer, within 8 clocks after
the data reception. Connect TCP_RX_WC to Word count terminal of the synchronous FIFO from its
lower bit. Set 1 to all the unused bits. For example, when the capacity of reception FIFO is 2Kbyte,
Word count terminal is 11bit. So, connect TCP_RX_WC[10:0]=Word count[10:0] and set 1 to all thebits of TCP_RX_WC[15:11]. In Verilog HDL, this is coded as “TCP_RX_WC[15:11] = 5’b11111;”.
Refer to the next section when not using the TCP reception function.

When not using TCP reception function
Set 0 to TCP_RX_WC[15:0] when not using the TCP reception function. Setting 0 is recommended
although it works with the other value setting.

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Slow control I/F
This I/F is controlled with UDP packets. Here, we describe its operation and how to use it from theview of the user circuit. The control on the PC side will be described in the next chapter.

Controlling with UDP packet
Sending Command packet
Receiving Acknowledge packet

Internal bus

Register

Control
circuit

SiTCP becomes the bus master.

Composed of commonly used address bus, data bus, etc.
Fig.9 Schematics of slow control
The schematics of the slow control is shown in the above figure. The UDP packet is transmitted fromPC to SiTCP in order to control the internal bus for which SiTCP works as its bus master. Theinternal bus consists of the address, data and control signal, and adopts a simple bus access protocol.
When the PC writes data into the user circuit, it stores the address and write-data in the UDP packet to
be transferred to SiTCP, and then the bus master in SiTCP operates to write data into the user circuit
via the internal bus. When the PC reads data, it designates the address to make SiTCP send the dataread in from the user circuit, back to the PC.

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Notice Concerning Address Space
RBCP addresses from 0xFFFF0000 to 0xFFFFFFFF are reserved for the SiTCP internal register andcannot be used. Use the address other than the above mentioned.

Control Signals
Signal name

I/O Description

CLK

I

System clockSame signal as CLK of TCP IF

RBCT_ACTRBCT_ADDR[31:0]
RBCT_WE
RBCT_WD[7:0]
RBCT_RE
RBCT_RD[7:0]
RBCT_ACK

O
O
O
O
O
I
I

Indicates the bus operating.
Address in access
Write enable
Write data
Read enable
Read data
Access response

Write (From PC to User circuit)
When writing data from the PC to the user circuit, SiTCP sets the access address and write-data to
RBCP_ADDR while setting RBCP_WE=H to notify that the operation is write-in.
When the user circuit receives the corresponding address, it must carry out a write-in operation andafter finishing the operation, respond by setting RBCP_ACK to H. In the cases including an access tothe address having no corresponding circuit, RBCP_ACK remains L although SiTCP judges thewaiting time beyond approx. 100msec as an error and terminates the bus cycle. A packet to notify theerror will be sent to the PC.

Dependent on access

Valid when WE/RE=H

Valid when WE=H

Set ACK to H only for 1 clock
after writing correctly

Max. 100ms
Processed as a bus error when exceeding the max.

Fig.10 Data write-in by slow control
The time-chart for data write-in is shown in the above figure.

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Read-out (From User circuit to PC)
When the PC reads data from the user circuit, SiTCP sets the access address to RBCP_ADDR whilesetting RBCP_RE=H to notify the user circuit that the operation is read-out.
The user circuit must set the data in corresponding address to RBCP_RD[7:0] while it responds bysetting RBCP_ACK to H only for 1 clock. Also in read-out, SiTCP judges the ACK response time
beyond approx. 100msec as an error, terminates the bus cycle and sends the packet to notify the error
to the PC.

Dependent on access

Valid when WE/RE=H

Outputs read-data when ACK=H(Can output in the vicinity but ignored)
Set ACK to H only for 1 clock
after reading correctly

Max. 100ms
Processed as a bus error when exceeding the max.

Fig.11 Data-read by slow control
The time-chart for the data-read is shown in the above figure.

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Network parameters settings I/F
Although the network parameters such as IP address etc. are operated using the values stored in
EEPROM, it can be used by the external input signals including DIP SW. Also, the I/F includes theterminal to read the default values compulsorily for the circuit operation, on re-writing EEPROM or
any abnormality.
Signal name
FORCE_DEFAULTn (*1)

I/O
Description
I 0: Compulsorily uses default value
1: Uses EEPROM value

IP_ADDR_IN (*2)

I

IP address input terminal

IP_ADDR_DEFAULTTCP_MAIN_PORT_IN (*2)
TCP_MAIN_PORT_DEFAULTTCP_SUB_PORT_IN (*2)
TCP_SUB_PORT_DEFAULTRBCP_PORT_IN (*2)
RBCP_PORT_DEFAULT
PHY_ADDR (*3)

O
I
O
I
O
I
O
I

IP address value set to the register
TCP port number input terminal (main port)
TCP port number set to register (main port)
TCP port number input terminal (sub port)
TCP port number set to register (sub port)
RBCP port number input terminal
RBCP port number set to register
Sets MIF address of PHY device(*1) Normally, it connects DIP_SW, jumper pins or etc.
(*2) Normally, connect this to the same signal name having _DEFAULT at its end. When setting the
network parameters configurable by the external signal (e.g. DIP SW, etc.), refer to “How to set
network parameters by external signals including DIP SW” in the next section.
(*3) Read the data sheet of your PHY device for this setting. In many cases, this is determinedaccording to the state of PHY device terminal on a power-on. How to set the address of the PHY
device is different for each device.

How to set network parameters by external signals including DIP SW
The following network parameters can be set by the external signals, using DIP SW etc.
⚫
⚫
⚫
⚫

IP address
TCP main port number
TCP sub port number
RBCP port number

Below, we explain about IP address. For the other values, the same explanation is applied.
SiTCP always uses the value input in IP_ADDR_IN as IP address to operate. It does not depend on
the value in FORCE_DEFAULTn. When setting the IP address by DIP SW, connect DIP SW to
IP_ADDR_IN.
The register value corresponding to the IP address is output to IP_ADDR_DEFAULT. When
FORCE_DEFAULTn =0, a default value is output. With FORCE_DEFAULTn=1, the value read out
from EEPROM is set. Some bits of this IP_ADDR_DEFAULT and the DIP SW can be combined andinput to IP_ADDR_IN. For example, the register value and DIP SW value can be set to its upper andlower bits, respectively.

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9. RBCP
Here, we describe a control protocol for slow control, Remote Bus Control Protocol (RBCP).
RBCP is the protocol to provide a remote control over the bus for which SiTCP becomes its bus
master. RBCP packet encapsulated in the UDP packet is used.

Transmission of RBCP CMD packet

PC process

Analysis of RBCP CMD packet

Command execution

SiTCP process

Transmission of RBCP ACK packet

Reception of RBCP ACK packet

PC process

Fig.12 RBCP process flow
The process flow is shown in the above figure. First, the command packet generated according to theprocess contents is sent from the PC to SiTCP. The SiTCP waiting port at this moment is the value
stored in EEPROM or the default value, 4660. The command packet is processed by SiTCP and aninternal bus access is executed. When the bus access terminates, the ACK packet is sent back to the
PC as a response. The PC can recognize that the access is terminated on the reception of the ACK
packet.
Since RBCP packet is transferred using UDP, it can be lost within the network. So, the PC must moveon to its next process after receiving the ACK packet and confirming the access termination. Ensure
the access termination by having the PC set a timer while waiting for the ACK packet and, on its timeout, re-send the command packet.
The time-out duration should be set to the value over 200msc, considering that the bus time-out of
SiTCP is set to 100ms. Confirm the time-out duration by an actual operation since it depends on the
PC’s processing time and the transfer-time within the network. If slower operation is allowed, set the
time-out to approx. 1sec. Speaking from our practical use experiences, it is rare to lose the packet. In
many cases, the ACK packet is returned normally.
For the concrete implementation of RBCP, see the attached sample program “RBCP_sample.zip”. Its
operation has been confirmed with Cygwin and Linux.

RBCP Packet Format
Here, we encapsulate the RBCP packet with UDP.
In your socket programming, transmit the RBCP packets shown below by the ‘send’ function.

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Fig. 13 RBCP Packet format
The packet format is shown in the above figure. The meaning of every field is explained below.

VER
This is the version of the RBCP Packet. Currently, only 15(0xF) is accepted for it. Always, set 15 to
it. Packets with other values will be discarded.

TYPE
This is ‘Packet type’. Currently, only 15 (0xF) is accepted. Always, set 15 to it. Packets with othervalues will be discarded.

CMD
This is the code indicating the access type. The following two values are currently used.
● 0xc: Read
● 0x8: Write
Refer to ‘CMD bit’ listed on the right side in the figure.

FLAG
This indicates the packet type and execution result. It is the field valid only for the ACK packet. For
the command packet, always set bit3=0. With a bus error to occur, the ACK packet with its bit0 set to
1 will be returned.
Also, refer to ‘Flag bit’ listed on the right side of the figure.

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ID
This is the packet ID. It is used for an execution confirmation.
The ACK packet has its ID same as that of the corresponding command packet. Set an arbitrary value
to this field since SiTCP does not confirm nor operate it.
Changing this ID every time allows a judgment if the packet is the ACK packet corresponding to thecommand packet.

DATA LENGTH
For the command packet: The Read/Write-data length is set to this field in bytes. Since setting this to
0 will not work, set any length other than 0.
For the ACK packet: It is the length of the data executed actually and normally. On an error
interruption, the number of data normally executed is stored here. With an error occurrence, this valuetells in which address the error occurred.
Since this is an 8bit length field, the byte length accessible at a time is limited to 255 bytes. When
accessing over 255bytes, divide it into the multiple accesses for which the data length of an access is
no more than 255.

ADDRESS
This is the address of the bus to access. The data of their length stored in ‘Data Length’ field isaccessed from their starting address stored in this field.

DATA
This means differently for the command packet or the ACK packet.
Command packet⚫ On write: Store the data of the byte length equivalent to ‘Data Length’. If the data shorter thanthe value in the ‘Data Length’ is transmitted, the data remaining in the internal memory will be
written in and the write-value becomes undefined.
⚫ On read: Do not use this field.
ACK Packet⚫ On write: The data actually written is stored. Here, the data are not the ones read from theequivalent address. These are the data used on the write. For example, when writing data in theread-only register, the write-operation is not actually valid but the written data will be stored inthis field.
⚫ On read: The data read-out is stored here.

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RBCP sample program
For an implementation example of the RBCP program, a sample program used for debugging is
distributed as an attachment “RBCP_sample.zip”.
Compile ‘rbcp.c’ with ‘gcc’ or alike for your use. Its operation has been confirmed on Linux. For theother OSs, you need to modify any necessary parts.
Here, a compiled executable file “rbcpWin.exe” for Windows is stored. Execute it from the commandprompt of Windows.
The start screen of the sample program is shown below.

Designates IP address and Port No.
Read-command
Reads 16 bytes from address 0.
Read-out result
Command list

1 byte-write command
Write 1 in address 0x8.

This may display differently for the latest version.
Fig.14 Sample program start screen
It is executed as follows.
Executable file name [IP address][Port No.]The figure shows the case with its IP address 192.168.10.16 and port No. 4660. On its start, theprompt changes to ‘SiTCP-RBCP$’. The input number is in decimal or hexadecimal expressions.
When using the hexadecimal expression, add ‘0x’ to the head of the number. Each command is
described below.
⚫

wrb [address] [write-data]➢ 1 byte write➢ Writes the write-data to the designated address.

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⚫
⚫
⚫
⚫
⚫

wrs [address] [write-data]➢ 2-byte write, big-endian
wrw [address] [write-data]➢ 4-byte write, big-endianrd [address] [length]➢ Reads and displays the data of the byte length [length] from start address [address].
help➢ A list of the available commands
quit➢ Terminates the program

Test example⚫

⚫

Read of DIP SW value➢ Read from the address 0 for 16 bytes.
➢ Re-read the value by manipulating the DIP SW.
 The value on the address 0x8 changes according to the DIP SW value.
LED light on/off➢ Write ‘0xFF’ to the address ‘0x7’.
 The seven LEDs will light on.
➢ Write ‘0x0’ to the address ‘0x7’.
 The seven LEDs will light off.

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10.SiTCP Internal Register
SiTCP has its internal registers for storing the network parameters and controlling the PHYs. They
are accessible using RBCP.

Address space map
RBCP address
0xFFFF_0000 – 0xFFFF_FBFF
0xFFFF_FC00 – 0xFFFF_FCFF
0xFFFF_FD00 – 0xFFFF_FDFF
0xFFFF_FE00 – 0xFFFF_FEFF
0xFFFF_FF00 – 0xFFFF_FFFF
Do not access ‘Reserved’ spaces.

Description
Reserved
EEPROM
Reserved
Ethernet PHY MIF I/FInternal register, SiTCP control register

Internal register map
Access them in big-endian.
The addresses in the table are shown in the differentiation from the base address ‘0xFFFFFF00’.
Address+0x00-03

R/W
Standard value
R SiTCP synthesis date-time: YY MM DD NN (binarycoded decimal expression)
Y=Last two figures of A.D., M=Month, D=Date,
N=Number of synthesis on the same date.

+0x04-0F+0x10

R ID: A specific number is stored here.
R/W SiTCP and TCP control[7] SiTCP reset (1: Reset / 0: Normal)[6] Client ARP (1: ON / 0: OFF)[5] Dup Ack (1: ON / 0: OFF)[4] MIF Initializer (1: ON / 0: OFF)[3] MAC flow control (1: ON / 0: OFF)[2] Keep alive packet (1: ON / 0: OFF)[1] Fast retrains. (1: ON / 0: OFF)[0] Nagle buffering (1: ON / 0: OFF)24 / 270x01

+0x11+0x12-17+0x18-1B+0x1C-1D+0x1E-1F+0x20-21+0x22-23+0x24-25+0x26-27+0x28-29+0x2A-2B+0x2C-2D+0x2E-2F+0x30-3B+0x3C-3F+0x40-FF

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Reserved
MAC address (Notice 1)
IP address
TCP Port No. (main port)
0x18
TCP Port No. (alternative port)
0x17
TCP MSS (the number of bytes)
0x05B4
RBCP Port No.
0x1234
TCP keep-alive-packet transmission timer (with data in 0x03E8transmission buffer) (msec unit)
R/W TCP keep-alive-packet transmission timer (with 0xEA60
transmission buffer empty) (msec unit)
R/W Time-out duration when TCP open (msec unit)
0x1388R/W Time-out duration when TCP close
0x2BF2(256msec unit)
R/W Waiting-time between TCP connections (msec unit)
0x01F4R/W Time-out duration of TCP re-transmission time (msec 0x01F4
unit)
R/W Reserved
R/W User area (Notice 2)
Access-forbidden area (Notice 1)0x00x00000000(Notice 1) Work very carefully not to write any value in the MAC address(+0x12-17) and the accessforbidden area(+0x40-FF), otherwise the system will corrupt and not operate normally.
(Notice 2) This area allows the user to write any value.

Re-write of EEPROM
We describe below how to change the network parameters with an example of changing IP address.
To change the IP address, the SiTCP parameters stored in EEPROM need to be changed. Work very
carefully not to write any improper parameters to EEPROM, otherwise SiTCP will corrupt leading to
the abnormal operation and communication.
The memory map of the parameters stored in EEPROM is the one in the previous section “Internalregister map” but with its base address substituted with ‘0xFFFFFC00’ (excluding from +0x00 to+0x0F). For example, the IP address is stored in ‘0xFFFFFC18-1B’.

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Work procedure outline
Start SiTCP in its default-value compulsory setting mode to make it communicable with the following
fixed address.
⚫
⚫

IP address: 192.168.10.16
RBCP Port No.: 4660

This mode operates with always the same parameters regardless of the EEPROM contents.
Then, set the mode for re-writing, by RBCP, the IP address stored in EEPROM back to normal, andre-boot the system.

Detailed procedures
1.

2.

3.

4.

Start in the default modeA) Power off
B) Switch to the default-value compulsory setting mode (FORCE_DEFAULTn=0). Normally,
this is often done with a jumper or DIPSW.
C) Power on.
D) Confirm SiTCP operating with Ping command.(*1)
Re-write EEPROM
A) Write ‘0x00’ of a byte to ‘0xFFFFFCFF’ using RBCP.
B) Write the IP address to ‘0xFFFFFC18-1B’.
(1) ‘0xFFFFFC18’ is equivalent to the upper bytes which are the bit31-24 of the IP address.
C) Read ‘0xFFFFFC18-1B’ by RBCP to confirm the set value.
D) Power off.
Operation checkA) Set the operation mode to the normal mode (FORCE_DEFAULTn=1).
B) Power on.
C) After the FPGA download is finished, confirm that the IP address has been changed to thedesired one, using Ping command.
Terminate.
(*1) The IP address is determined with the value input in ‘IP_ADDR_IN’ of the library. It does notdepend on the value of ‘FORCE_DEFAULTn’. When using SiTCP library with a wrapper, thisdepends on the signal connections within the wrapper. Study the value from the signal connectionsof the wrapper or ask the distributor of the SiTCP library.

(Notice) When changing the IP address, it may be necessary to change the network settings on PC side.

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11.Appendix
100Mbps Ethernet reference circuit diagram (mii.pdf)
Gigabit Ethernet reference circuit diagram (gmii.pdf)
RBCP control program for debugging (RBCP.zip)

12.References

1.

A paper on SiTCP : T. Uchida, “Hardware-Based TCP Processor for Gigabit Ethernet,”
http://hdl.handle.net/2261/15490

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