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EMC Tests and PCB
Guidelines for Automotive
Linear Regulators
Introduction

www.onsemi.com

Electromagnetic compatibility (EMC) is important for thefunctionality and security of electronic devices. Today’s
designers must deal with steadily increasing systemfrequencies, changing power limits, high-density layouts
required by more complex systems, and the ever-present
need for low manufacturing cost. Therefore, it is necessary
to optimize EMC.
Linear regulators supply several types of loads including
microcontrollers, one of the key devices in automotive
applications.
This document concentrates on EMC for automotive
basic knowledge, test methods at the IC level and
ON Semiconductor standards. PCB guide lines are included
to prevent any board effect or external coupling.

APPLICATION NOTE

The Linear Regulators Architecture

The linear approach is often considered for low output
noise generation.
Linear Pass Element

+
VIN
12 V

Electromagnetic compatibility (EMC) is the capacity of apiece of equipment to work properly in its normal
environment, and not create electrical disturbances thatwould interfere with other equipment.
Electromagnetic susceptibility (EMS) is the level ofresistance to electrical disturbances such as electromagnetic
fields and conducted electrical noise.
Electromagnetic interference (EMI) is the level of
conducted/radiated electrical noise created by theequipment.
Standards are addressing EMS or EMI issues for every
type of application area. These standards apply to finishedequipment.
EMC tests must be performed on the sub-systems in orderto evaluate and optimize applications for EMC
performances. Standards for IC-level EMC testing haveexisted since 2003. Two Standards are commonly used:
IEC62132−4 (Direct Power Injection or DPI) for EMS andthe IEC61967−4 (1 W/150 W method)

Rup

ErrAmp
+

Rload

5V

+
Vref

Rlow

Figure 1. Linear Power Supply

However, efficiency is one of the limitations of the linear
approach.
Intrinsically, linear regulators do not generate noise and
EMC disturbances, but they can be susceptible to noise
generated by other components like microcontrollers,
SMPS, and logic circuits.
According to the IEC standards, Linear regulators aretested using the Direct Power Injection method(IEC62132−4).
Direct Power Injection

The RF disturbance (a sinusoidal waveform from 150 kHz
to 1 GHz CW (Continuous Wave)) or AM (Amplitude
Modulation, 1 kHz, 80%) is injected on the component pin
under test through a decoupling block as shown on Figure 2.
The DC block is realized by a capacitor. The RF disturbanceis monitored through the directional coupler by measuring
the forward power and the reflected power.
The continuous wave means the successive oscillations
are identical under steady state conditions. The amplitude
modulation (AM) is the process by which a continuous highfrequency wave is caused to vary in amplitude by the actionof another wave containing information.

Definition of Noise

Susceptibility to radio frequency interference is becoming
a major concern for integrated circuits, with the propagationof new and powerful electromagnetic sources. Electrostatic
discharges, mains transients, switching of high currents andvoltages or radio frequency (RF) generators are just some of
the causes of electromagnetic interference. EMI can betransferred by electromagnetic waves, conduction, andinductive/capacitive coupling.

April, 2015 − Rev. 1

1A

1A

Definition of EMC© Semiconductor Components Industries, LLC, 2015

VOUT

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The basic requirement when an amplitude modulation isapplied is the peak power shall have the same value as thepeak power when a continuous wave is applied, regardlessthe modulation index m.

The following algorithm is used to test components with
the DPI method.
F = Fstart

P AM*Peak + P CW*Peakand2
P AM + P CW 2 ) m 2
2(1 ) m)P = Pmax

For example, 80% Amplitude Modulation, 1 kHz (m = 0.8)
result is
P AM + 0.407 @ P CW

Increase F

DUT Fail

Reduce P
by 1 dB

YESNO
Record P
and F

F = Fstop

YES

END

NO

The forward power is the amount of power that is sentfrom the RF source towards the DUT without considering
the RF power that is being reflected backwards by the DUT.
To reduce the reflection effects, the set up is built with
50 W cable and 50 W adapted printed circuit board tracks, sothat the injection path is 50 W almost all the way from the RF
generator to the DUT. However, the DUT impedance isstrongly dependant on frequency, therefore creatingreflections and resonant effects. An attenuator (3 dB) is
inserted just before the capacitor to avoid errors due to cableeffects.

Figure 3. DPI Flowchart

For each frequency step, power is set to the specified
power limit. If the device fails, the power is decreased in
1 dBm steps until the DUT exhibits correct performance.
Linear Regulators Tested with DPI Method

The usual limit is 1 W (30 dBm, Forward power CW) for
global pins and 17 dBm, Forward power CW for local pins.
A global pin carries a signal or power which enters or leaves
the application board. A local pin carries a signal or power
which does not leave the application board. It remains on theapplication board as a signal between two components. For
linear regulators, the Input and Output pins are considered
as global pins and are tested at the 30 dBm compliance limit.
Some linear regulators have added features, such as Resetand Delay circuitry. In this case, associated pins are
considered as local pins and tested to the 17 dBmcompliance limit.
The usual failure condition is the Output voltage. For
linear regulators with additional features, other pins aremonitored and must maintain their correct state (logic pins).

Figure 2. DPI Set Up

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Figure 6. Maximizing Ground on PCB
Connection to Ground• Connect Each Component Directly to Plane• Use a via for Each Component-Pin for
GND-Connection Instead of GND-Traces• Connections to Ground must be Shorter than 0.5 mm(20 mils)
35
30
25
L (nH)

Figure 4. Typical Test Conditions
General Golden Rules for PCB

All components should be placed with an appropriate
functional group and their tracks routed within theirdesignated PCB area. A recommended arrangement offunctional groups on PCB is shown in Figure 8.

20
6 mils12 mils
15
10

48 mils5
24 mils00AnalogGroup

Digital
Group

30
20
LENGTH (mm)

10

40

50

Figure 7. Inductance and Capacitance Values of
a Strip Line Above a Ground Plane

Trace widths should be around 20 mils to reduce partial
parasitic inductance.

Power
Supply
Group

20

I/O
Connector

1 cm

18
16
14

Figure 5. Arrangement of Functional Groups on PCB

2 cm

12
L (nH)

Place ground plane(s) under all components and all theirassociated tracks. A continuous ground plane with noavoidance is recommended.
• A Good Ground Plane is Achieved by Using aComplete Layer for Ground• Do Not Cut the Ground Plane by Routing Signal Linesin GND Plane• Provide a Length/Width Ratio less than 5 for the PCB(At a Ratio > 5 the Inductance of the Ground Plane
Increases)

10
8
3 cm

6
4
2
0
0

1

2

3

4
5
6
LENGTH (mm)78Figure 8. Effect of the Trace’s Width on Parasitic
Inductancewww.onsemi.com
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AND8299/D
Particular Linear Regulator Guidelines

Printed circuit board traces which carry high switchingcurrent with fast rise/fall times (5−10 ns) should maintain atleast 3 mm spacing from other signal traces which runparallel to them, and/or ground guard traces should beplaced between them.
Corresponding power and ground signals should always
be routed in parallel to minimize loop area thus reducing
loop impedance (Figure 10).

Power supplies should be located as close to the power
entry point to the PCB, and as close as possible to powered
circuitry. Closely routed tracks (to minimize the area
between conductors, and hence the inductance) should be
used to connect the power source to the local power
distribution system.
Power feeds should always be decoupled at their entry
points onto the PCB.
Bulk capacitors should always be parallel decoupled with
one or more lower valued high frequency capacitors withlow ESL (equivalent series inductance). Place the smallest
value decoupling capacitor closest to a device to be
decoupled.
Power Supply
VOUT

IN
+

Not Acceptable

OUT
+

GND

Acceptable

Figure 10. PS Routing
Layout Example

Two boards have been made. The first one follows the
EMC design guidelines listed above. The second one isa typical applications board without consideration of EMC
rules. A linear regulator with reset function has been tested
with the DPI method.

Figure 9. Power System

High-frequency, low-inductance ceramic capacitors
should be used for IC decoupling at each power pin. Use
0.1 mF for up to 15 MHz, and 0.01 mF over 15 MHz.
The decoupling capacitor should be located as close as
physically possible to the IC’s power pin.

L3

L1
X1
VIN_DC

FerriteFerriteX2
VIN_HF
C2
10 mF

C4
22 nF

C1
100 nF

C5
22 mF

X5
VOUT_DCX6
VOUT_HF

U1
1

2

L2
X3
R0_DC
X4
R0_HF

I

Q

Q

D

5
VOUT
4

L4

3 GND

FerriteFerriteR1
4.99 K

C6
47 nF

X7
D_DC
X8
D_HF

VOUT

Figure 11. Board Schematic

The board schematic includes tantalum capacitors on the
input and output. Two small ceramic capacitors have been
added.

Figure 4 shows the failure criteria used for this example.
4% variation for the output voltage and 2 V for the reset
considered as a logic output pin are considered acceptable.

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Good EMC Test Board

The Device passes 33 dBm injection on VIN pin with
Reset and VOUT pins monitored.
PCB Without Consideration of EMC Rules

The second PCB is a demo board. The same components
are used with a different layout.

Figure 12. Assembly Top Good Layout
Figure 15. Top Layer Typ Layout

The demo board is a two layer board with ground plane.
The trace widths are bigger than 20 mils which increases
parasitic inductance. The distance from capacitor to the
DUT pins is more than 1 cm. The layout does not follow thepower supply guide lines.
40

30
DPI Application Board
RF Coupling VIN
Failure Criteria RST VOUT

20

Figure 13. Top Layer EMC Layout
10

20 mils trace widths are used with short connections. Input
and output capacitors are located as close as possible to the
DUT pin. It is a four layer board with ground plane.

0
1

40

10
100
FREQUENCY (MHz)Figure 16. DPI on VIN Pin
VIN Pass 33 dBm

30

20

10

0
1

10
100
FREQUENCY (MHz)1000

Figure 14. DPI on VIN Pin

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AND8299/D
Conclusion

In the same test condition, the device is not compliant with
33 dBm power limit in the whole frequency range. Issues
appear between 100 MHz and 1 GHz. The lower limit isaround 25 dBm @ 205 MHz The RF signal perturbed theoutput signal and created a reset.

As started in the introduction, EMC takes into accountSusceptibility and Emission of the components. Due to the
PCB connections, the coupling paths have to be consideredsuch as another way for EMC improvement at system level.
Obviously, EMI must reach the traces in order to disturb
the components. This means that the loops, long length andlarge surface of the conductors are vulnerable to EMI,making the PCB the principal subject of EMC
improvements.
Following EMC rules will reduce design costs andtime-to-market, while improving reliability andperformance of the design.
References[1] S. Ben Dhia, M. Ramdani, E. Sicard,“Electromagnetic Compatibility of Integrated
Circuits”, Spinger 2006
[2] A. E. Ruehli, “Inductance calculation on a complex
integrated circuit environment”, IBM Journal, 1972,
p470−481.
[3] M. Gondon “Parasitics elements associated to theprinted circuits board tracks”, ON Semiconductor
2006[4] IEC 62132, 2003, “Characterization of integrated
circuits electromagnetic immunity”, IEC standard;
www.iec.ch[5] M Montrose, “Printed Circuit Board Design
Techniques for EMC Compliance”, 1996 IEEE
Press

Figure 17. VOUT and Reset Errors

33 dBm is 2 W injection; 25 dBm is 0.3 W injection
which is a large performance difference for the same bill ofmaterials.

ON Semiconductor and theare registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessedat www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, andspecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for eachcustomer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, andexpenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.

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