ON Semiconductor
Is Now

To learn more about onsemi™, please visit our website atwww.onsemi.com

onsemi andand other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.

AND90006/D
Recommendations for
Reliable Switching
Performance using
ONSemiconductor 40V
and 80V Automotive Power
Modules Using
Shielded-Gate MOSFETs

www.onsemi.com

APPLICATION NOTE

Summary

The ON Semiconductor automotive qualified power module family(AutoSPM) was introduced in 2008 and since then has experienced
steady improvements, including most recently shielded−gate
MOSFETs in the 40 V and 80 V nodes. These MOSFETs further
optimize the figure of merit between on resistance RDS(on) and gatecharge Qg, and thus extends the modules’ capability for highfrequency and high current switching. This application note provides
recommendations on the selection of gate resistors and limits to the dc
link bus inductance necessary to obtain the full benefit of this new
MOSFET technology while maintaining safe operation inhard−switched inverter system designs.
Safe switching of the very fast shielded−gate MOSFETs requires agood balance of speed and external stray inductance to ensure safe
operation, especially as inverter output current levels are pushed to thefull capability of the modules. To explore the most effective use of
these modules for high current and high speed switching applications,
ON Semiconductor has utilized extensive bench testing to provide
guidance to our customers. This application note describes the processused to arrive at our guidance, including:• Running an experimental benchtop inverter system to explore
operating limits and create failures to define the critical parametersthat lead to the failures• Identify the root cause of the failures• Provide guidance on selection of gate resistors for (especially)turn−off and the impact of dc capacitor and bus bar parasitic
inductance in order to ensure safe operation at the limits of the data
sheet performance
Careful adherence to the guidance provided herein will ensure
reliable operation of inverters employing the AutoSPM line ofshielded−gate MOSFET power modules.

Figure 1. AutoSPM Module Photo

Figure 2. Pin Configuration

Figure 3. Internal Equivalent Circuit© Semiconductor Components Industries, LLC, 2020

January, 2020 − Rev. 0

1

Publication Order Number:AND90006/D

AND90006/D• A failure determined to be “EOS” may occur on any

1. What Can Possibly Go Wrong?

Improper integration of the AutoSPM power modules into
an automotive accessory inverter drive can result inexceeding the safe operating limits of the power MOSFETs.
Without attention to system level considerations, a user may
experience failures during development, with distinctive
characteristics, such as:• The module may operate normally for some time (fromminutes to days) until unexpectedly it fails on startup,
at relatively low current

one of the six MOSFETs inside the 3−phase module.
Through X−Ray scan and microscopy upon
decapsulation of the module, the burn mark on the
MOSFET may show up at various locations without aregular pattern (Figure 4).

Figure 4. Microscopy Photo of Damaged MOSFET Die

The root cause of such failures can be difficult todetermine. When otherwise operating within the data sheet
limits, the root cause is likely repetitive avalanche. This canoccur under conditions of phase current and junction
temperature that are thought to be within the safe operatingarea of the MOSFET, but actually exceed the avalanche
rating of the part. Some comments on this situation are
given below:• Because the failures occur after only a few minutes ordays of operation, it is not a normal lifetime reliability
issue. These failures typically occur during startup of
the inverter, when the electrical stress is not very high.
• Because the damaged MOSFET can be in any location
within the module, it does not look like package
fabrication (such as bonding wire, die soldering, etc.).
• It does not appear like a failure due to packageparasitics or package thermal performance, since thesecharacteristics remain unchanged from part to part andover time.
• For these shielded−gate power trench MOSFETs, themajor improvement is reduction in RDS(on) and Qg,
making the module capable of conducting higher
current and switching faster. Both of these traits willlead to higher di/dt during the switching event.
Meanwhile, it is known that damage related toavalanche occurs due to excessive di/dt interacting withthe power loop inductance.

and can be expressed as in Equation [1]. Together, they may
elevate the voltage across the device (VDS) up to theavalanche break down voltage, which is ~1.3 times thebreakdown voltage from device’s data sheet (for safetymargin). Table 1 lists parameters that have been extracted
from an benchtop inverter design. The calculation of VDS
during turn off, shown in Equations [2] and [3],demonstrates the danger that the device can be operated very
close to the avalanche voltage.

Figure 5. Voltage Polarity of Stray Inductance(same as the polarity of di/dt) during Upper FET
Switching Off

The simplified schematic of one phase of the module
shown in Figure 5 illustrates the key parasitic elements, bothinternal and external to the module. As indicated, the voltage
across these parasitic inductances add to the DC bus voltage,

V ds + V bus ) L s

www.onsemi.com
2

dI
dt

(eq. 1)

AND90006/D
V ds + 12 ) (10 ) 15)
V avalanche + 40

1.5 + 49.5

enough. It should be mentioned that most modern powertrench MOSFETs are designed to repetitively avalanche
without failing, as long as the avalanche energy remains
sufficiently low to avoid excessive junction temperature.
Many combinations of inductance, phase current amplitude,
and di/dt may be encountered in module applications that arein the control of the end user. To illustrate a process by which
a user can ensure safe operation of the module, anexperimental inverter system has been implemented torepresent typical automotive accessory inverters to find thesafe limits via long−term tests. This is shown in Figure 6.
An open loop space vector PWM (SVPWM) algorithm
was implemented which is sufficient to generate sinusoidal
currents through the manipulation of modulation index withan inductive load.
A wye−connected 3−phase line filter was used torepresent a set of balanced motor windings, without thecomplexity of a fully functional motor dyno. The key
requirement is for the power module carry reactive andactive power. The only difference is that a rotating motor
will also generate back EMF which will result in a higher
modulation index during motor operation. Such behavior is
not accounted here, and is not pertinent to the failure
mechanism, so long as the phase current amplitude isrepresentative of a realistic automotive auxiliary motor.
The complete test system is shown in Figure 6. Three
inverter systems run concurrently, sharing the same DC
power supply while having their own dedicated DC link
capacitor bank and busbar structure. This is to increase thenumber of AutoSPM samples that can be tested at one time.

(eq. 2)

1..3 + 52(eq. 3)

Table 1. PARAMETERS FROM AN EXISTING
INVERTER DESIGNDC bus voltage [V]12

MOSFET breakdown voltage [V]40

Module inductance [nH]~10Power loop inductance [nH]~15

Turn off di/dt [A/ns]~1.5

In the following sections, to reveal the relationshipbetween excessive repetitive avalanche and module failure,
an experimental test setup with fixed loop inductance with
controllable di/dt is shown. The di/dt directly determines theamplitude of overshoot voltage during device switching off
and the associated avalanche energy. Thus, the setup willallow investigation of the limits of safe operation duringswitching off, as controlled by the gate resistors, theamplitude of the phase current, and the value of stray bus
inductance.
2. Reproduction of Failure Mode and Suggestion of
Minimum Gate ResistanceCalculations from the previous section confirm that underworst case operating conditions the device may enter theavalanche region during turn off if stray inductance is highFigure 6. Benchtop Test Setup
Description of the Inverter System & Test Procedure

MOSFET instantaneous switching current is varying at thesinusoidal frequency (motor fundamental). Given thatswitching time of the device is relatively constant, theIn a SVPWM inverter, assuming constant torque andconstant speed, the phase current is sinusoidal, so thewww.onsemi.com
3

AND90006/D
8. Replace with 3 new modules and then start all overfrom step (1).

resulting di/dt varies across each switching event according
to a rectified sinewave. In this test, the VDS waveform has
been continuously captured since the purpose of the test is
to answer two questions: (1) do the MOSFETs enter
avalanche during turn off, and (2) how often do the
MOSFETs enter avalanche?
In order to increase progressively the stress on the
MOSFETs until failures were observed, our test procedure
followed these steps:
1. Choose Rg(on) and Rg(off) of the gate driver,
starting from conservative 50 Ω for low di/dt.
2. Raise the coolant temperature to 80°C
(representing automotive cooling conditions) andconfirm that the module case temperature reaches
80°C by reading the module’s NTC thermistor.
3. Start the inverter, gradually increase modulationindex until target load current been reached. Run
continuously for 4 hours.
4. Stop the system, set coolant temperature as 20°C,
and monitor Tcase until it cools to 20°C.
5. Re−start the inverter as shown in step (3), and ifeverything functions correctly, increase coolant
temperature up to 80°C again, and continue run the
inverter.
6. Repeat (4) and (5). If all 3 modules still function
correctly after the total running time reaches 24hours, then this round of the test will berecognized as a “pass”.
7. For the next round, if no failure occurred, reduce
Rg(on) and Rg(off). If current Rg(on) and Rg(off)value is larger than 10 Ω, then reduce by 10 Ωeach time; if current Rg(on) and Rg(off) value issmaller than 10 Ω, then reduce by half each time.
If the module failed during this round, then thegate resistors are increased according to the same
logic.

Sample Test Results

Two typical turn off events are shown in Figures 7 and 8.
The flat top VDS waveform from Figure 7 is a clear sign of
the MOSFET entering avalanche, due to the voltage
clamping effect of avalanche breakdown. But in Figure 8,
we see the peak VDS voltage does not reach avalanche
voltage, hence VDS is not clamped. For longer time scales,
as show in Figure 9, we see the amplitude of turn off
overshoot varies during different switching events,
according the sinusoidal phase current. In addition, one
interesting finding here is when the sinusoidal phase current
reaches its peak value the switching off overshoot is notnecessary to reach its peak as well, in other words, the di/dt
it not high despite the current is at its peak value. One
reasonable explanation here it, since the load is inductive,
freewheeling current can leads to soft switching on or off
with help of device’s body diode.
During the sequence of tests, Rg(on) and Rg(off) values
were reduced round after round until some modules failed tocomplete the whole 24 hours duration. With this failure
information, the last known Rg value for all modules to pass
the test should be its minimum allowed value. After adding
necessary margin, the recommended minimum Rg values
for several AutoSPM part numbers are shown in Table 2.
One thing to be mentioned here is, based on the customer’s
design, they may reduce Rg(on) for higher turn on di/dt andreduced loss, but for the value of stray bus bar inductancetested, it is required not to reduce Rg(off) below the statedvalue. To do so will lead to MOSFET failure due to high turnoff di/dt and associated repetitive avalanche. If higher di/dt
is required then efforts must be made to reduce strayinductance. This is a system constraint, not a weakness of the
MOSFET.

Figure 7. Flat Top Vds Waveform, due to Clamping Effect of Avalanche Breakdown

www.onsemi.com
4

AND90006/D

Figure 8. Device does not Enter Avalanche Region

Figure 9. VDS Variation Over Multiple (~200) Switching Periods

Table 2. MINIMUM REQUIRED Rg(off) VALUES FOR AutoSPM SHIELDED−GATE TRENCH MOSFET MODULE
FAMILY
ModuleBreakdown Voltage [V]Peak Current Rating [A]Minimum Rg(off) [W]

NXV04V120DB1

40

160

7.5

NXV08V080DB1

80

130

2.5

NXV08V110DB1

80

190

2.5

3. Recommendations for Bus Structure Improvement

always be considered first while improving bus structure
design.
First, series resistance and inductance are the two major
aspects for the bus structure designer to consider, since
lowering these values will be beneficial for the wholesystem’s efficiency and reliability. From Equations [4] and[5], it is clear that shorter length and larger cross−sectional
area will be preferable.

In this application note, by means of a specific bench test
setup, we are able to provide guidance and emphasis on
some critical aspects that should always be consideredduring an inverter system design, particularly the selectionof suitable turn off gate resistors and dc link filter capacitors
and bus bar. But, in realistic automotive applications, somesuggestions here may not be feasible due to space and costlimitations, thus system designers will have to rely on theirown judgement and detailed analysis of their bus structure.
As a general and theoretical instruction, which is based onwell known design rules, the following aspects should

L series +mL
A(eq. 4)m: Permeability, L: Length of conductor, A: Cross section
area of conductor.

www.onsemi.com
5AND90006/D
R series +rLAkeep the welding spot as close to the module bodyas possible.
2. In addition to the bulk storage electrolytic
capacitors, add a few smaller ceramic capacitors(~10 uF each) very close to the module, between
the longer (hence higher inductive) connection of
the electrolytic capacitors to the module. This way
is more efficient in keeping the DC voltage stiff
during the high frequency switching transient.
3. A common−mode line filter was added to each bus
structure when connected to the common DC bus,
to avoid noise from each module being coupled
into the common DC bus, and causing interference
to other systems sharing the same bus.
4. By choosing plate shaped bus bar, the series
inductance can be reduced through overlaying thepositive plate and the negative plate. The reason iscurrent flow in opposite directions through a pairof conductors will also generate opposite
electromagnetic fields, and the two fields willcancel out each other when closely coupled. Thismeans the current does not generate any
electromagnetic field or, equivalently, that the pairof conductors have zero series inductance.
Alternatively, if viewing from transformer designprinciples, the self−inductances of perfectly
coupled windings will be decoupled by theirmutual inductances.

(eq. 5)

r: Resistivity, L: Length of conductor, A: Cross section areaof conductor.
Second, in shielded gate MOSFETs, the switching time
can be as low as ~50 ns. Combined with their current ratingover 100 Amps, a di/dt higher than 2A/ns can be expected
in real applications. Referring to Equations [1] to [3], it isclear that by using existing bus structure design andswitching off at 2 A/ns, the avalanche voltage will definitely
be reached. To avoid this outcome the bus inductance must
be reduced, mainly by downsizing it. But, as the most visible
component in a bus structure, the electrolytic capacitors
dominate the geometry. They are intended to supply lower
frequency, higher power (i.e. DC−AC inverter outputs
60 Hz/160 A sinusoidal current) to stabilize DC bus voltage.
However, the negative effect is that the bus bar connecting
them to the module will add length, which leads to higher
series inductance. By comparison, to stabilize the DC
voltage during the very short (~50 ns) switching transientwhen avalanche occurs, small ceramic capacitors with low
ESR/ESL are more suitable, and should be placed very close
to the module.
Finally, system assembly such as alignment of switching
devices is also important. The hardware setup which
provided data for this document had to be renovated several
times during the failure investigation to achieve minimal
stray inductance. Without any surprise, the Rg values
provided in Table 2 were based on results from the final
version of bus structure design. It achieved the lowest loop
inductance (~7.5 nH, measurement shows in Table 3). In
comparison, the previous version was much higher(~20 nH), and the VDS waveforms captured on theoscilloscope proved that the MOSFET entered avalanche
region during every turn off event. Under such conditions,
if we want the module to pass the test, turn off di/dt had tobe reduced through increased Rg(off) values. However,following this strategy, test results showed the requiredRg(off) to be at least 50 Ω, which is impractical for realapplications, due to unacceptably high switching loss.
In specific, the following steps were taken to improve thistest setup, the final version of which is shown in Figure 10.
These recommendations are valid for user’s inverters as
well.
1. Maximize the contacting surface area between themodule’s power leads and bus bar and keep themnear to reduce series inductance. In automotive
assembles, the module power leads are usuallywelded to the busbar. So the suggestion here is toenlarge the surface area of the welding spot, andTable 3. LOOP INDUCTANCE FROM THE
IMPROVED BUS STRUCTURE
ParameterdI (A)

Sample 1

Sample 2

Sample 3

118

118

116

dt (ns)

50

58

51

VDS (V)

50.4

49.6

53.2

16.3

18.5

Vbus (V)
Lloop (nH)12

Lstray (nH)
Lbus (nH)

18.1
11

5.3

7.5

7.1

Conclusions

In this document, reasons of potential EOS failure havebeen investigated, solutions to avoid similar failure havebeen provided, and additionally, recommendations forinverter system design and implementation have also been
provided, as the foundation of further application level
optimizations.

www.onsemi.com
6

AND90006/D

Improved bus structure showing: (1) Enlarged contacting surface area between module pins andbus structure to reduce stray inductance from lead pins, (2) Overlay coupled positive and negative
power plate to decouple series inductance from bus bar, (3) Parallel multiple electrolytic capacitors
for lower ESR and ESL, (4) Ceramic snubber capacitors been put close to module, strengthen DC
voltage stiffness during switching transient. (5) Common mode filter to reduce noise interference
among different systems.

Figure 10. Improved Bus Structure

ON Semiconductor andare trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are notdesigned, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, andexpenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if suchclaim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com◊

TECHNICAL SUPPORTNorth American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910

www.onsemi.com
7

Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative