JAERI-Conf 95-021

PB17
HIGH ACCURATE TIMING SYSTEM FOR THE SPRING- 8 SYNCHROTRON
Hiromitsu SUZUKI, Hirota YONEHARA, Tsuyoshi AOKI, Norio TANI, Soichiro HAYASHITakeji MIYAOKA*, Yuzou SHIMOUCHI*, Takao YAGI*, Eiji TOYODA*
JAERI- RIKEN SPring- 8 Project team, Kamigori, Ako- gun, Hyougo, 678- 12, Japan* : Toshiba Co., 1-1-6, Uchisaiwai- cho, Chiyoda- ku, Tokyo, 100, Japan

Abstract
For the single bunch mode operation, the timing
system for SPring- 8 synchrotron is required highaccuracy (low jitter) and high resolution. Prior to thetiming system for SPring- 8, we made a test timing
system as a prototype. It achieved target specifications(jitter a. 20ps, resolution a. 20ps). In this paper, we'll
report about the construction and some acquired data ofsynchrotron is approximately 2nsec. (It's equal to thewave length of rf ( =508.58MHz).)So, the injection timing (from the linac ro thesynchrotron) has to be adjustable in 100psec ordertiming with accuracy around 1/10 of the bucket length(2nsec).

the test timing system.
41. Introduction
SPring- 8 has a "single bunch mode". In the single
bunch mode, the injector (linac and synchrotron) injects
8 beam pulses into the storage ring. To make a single
bunch, the beam pulse #2- #8 have to be injected at
the timing when the bucket (which the beam pulse #1
is in) comes to the injection position of the storage ring.
The storage ring has 2436 buckets and thesynchrotron has 672. So, the bunch in the synchrotronrounds 3 and 5/8 turns in the time the bunch in thestorage ring rounds 1 turn. It means that for theeffective single bunch injection, 8 beam bunchs have toexist in interval of 84 buckets (1/8 of 672) in thea) Bunch #1 is injected to Storage Ring.

1b) Bunch #6 is injected when the bunch cometo the injection point. Thus, 8 bunchs are
injected to the same bucket. The order will bebunch #1, #6, #3, #8, #5, #2, #7, #4.
Fig.1 Single bunch injection

synchrotron. (Fig.1)

2. Requiremen t for the timing system
For this single bunch mode operation, following
conditions are required.
(1) RF phase of the synchrotron and the storage ringare synchronized.
(2) Eight bunchs in the synchrotron are located insame interval correctly.
The 1st requirement is achieved, because the rf
signal of the synchrotron is provided by the storage ringsystem. The 2nd one is satisfied if beam extracted fromthe linac is injected into the designed bucket in thesynchrotron. The pulse length of the beam from thelinac is 1nsec and the length of the bucket in the3. Constructio n of the test system
Prior to the product for SPring- 8, the test timing
system was constructed. Specifications are:Input signal
One- cycle signal (1Hz)(508.58MHz)
Master clock(1Hz)
Reset signal
Output signal
Linac trigger signals (8 pulses)-295-JAERI-Conf 95-021

Synchronized start pulse (for monitor)
Synchronized clock (for monitor)
Jitter:less than +/- l()()psec
Resolution : lOOpsec
Function : Generate 8 linac trigger signals (fromthe linac to the synchrotron.) every
16.7msec triggered by !-cycle signal.
(16.7msec : Cycle of the linac extraction)
To adjust ''linac trigger signals" with low jitter andhigh resolution is the target of this test system. Major
components of this test systems are:(1) Synchronize circuit
Make synchronized clock signals from external
clock (508.58:MHz) and one- cycle signal.

Ont--QwJe-1n. Q ~Syn.Start

M. Oock--c!CK R Q
ResetM. Clock
One-Cycle
Syn. Clock
Syn. Start

f~Syn.Oock

Fig.2 Synchronize circuit(2) Counter circuit(a) Bunch interval counter
Generate ''bunch interval clock" every 84
synchronized clocks. 1 cycle of this clock (6.05:MHz)is equal to the interval time of the bunch of thesynchrotron in the single bunch mode.
(b) One-turn counter
Generate 8 signals which represent bunch number(#1-#8) which beam from linac will be injected into.

This signals are· rotated from #1 to #8 switched by''bunch interval clock". This signals are used in thelogic circuit to make linac trigger signals. This ·counter has its own delay-line for its fineadjustment(c) Tum-number counter(d) Injection- number counter
Both counters ((c) and (d)) are decreased by ''bunchinterval clocks". And they are also used in the logiccircuit.
(3) Logic circuit
Generate 8 linac trigger signals. There are 8 logiccircuits (#1- #8) and each logic circuit represents theorder of linac trigger (#1- #8). To select logic circuit#1- #8, counter (b),(c) and (d) are used.
(4) Output circuit
Final sequence of the system. It generates lOnsec
width pulses at the monomulti vibrator. It has adelay-line. Range of this delay-line is selected fromO.lnsec to 6.3nsec by O.lnsec step. Ut's selected bydipswitches.) The resolution of this system depends on
this delay-line.
The feature of this timing system are:(1) Frequency down converter isn't used, it minimizes
jitter and gets fine resolution.
(2) One high speed counter (ECL element) and somecascade linked counters are used. These counters selectthe logic circuit and control the timing of the linac
trigger pulse. This construction also minimizes jitterand high accuracy.
(3) A delay-line is used in the output circuit. This
makes the adjustment of the delay timing easy.

1 Cycle
(1Hz)
Reset

ResetSystem

Linact---+--:J> Trigger

Signal:·Lo ·c #2 !
----------~--------~ ': Logic #8 _....._~

Fig.3 Construction of test timing system-296-JAERI-Conf 95-021

OSCTest System

4. Result of test system
To confirm reliability, miscounts were checked andjitter through the timing system was measured.
(1) Miscounts
The measurement system is shown in Fig.4. With auniversal time- interval counter, time intervals between
every linac trigger signals are measured. If there are
N- times miscounts, time difference between maximum
data and minimum data will be:
N x (cycle of clock) = N x (1/508.58MHz)= N x 1.966nsec
are less than 1.96nsec. It1)
(Tabledata
Acquiredmeans there were not any miscounts.

Clock

Linac r---.-----3!!Trig.

Ch.A

1Cycle RST.----~Ch.B

SYN:Synthesizer
OSC:Oscilloscope
SG:Signal Generator
Fig.5 Measurement system for jitter
1VI

II

Test Systemu.c.

Clock lCycle f------;.~EXTMon

Linac
1Cycle RST

2BBmV/d lv

START

I·I

~f---------~--~~~~!

SYN:Synthesizer
UC:Universal Counter
SG:Signal Generator
Fig.4 Measurement system for miscounts
Table 1 Data for miscount testTmax- Tmin
Signal
0.45nsec#1- #20.49#3#20.55#3- #40.45#4- #50.55#5- #60.53#6- #70.45#7- #8Fig.6 Acqired jitter data
5. Conclusion(2) Jitter
A measurement system is shown in Fig.5. A digital
sampling oscilloscope is used for the measurement(connect "linac trigger signal" to the trigger channel andmaster clock (508.58MHz) to the channel formeasurement).
Acquired data is shown in Fig.6. The width of thesine-curve represents jitter. Jitter is about 20psec after
fine adjustment of the delay line, so this system
satisfies the required specification for the single bunchmode operation.

The required specifications for timing system areachieved through the test system. The accuracy isaround 20psec, and the resolution is less than 200psec.
Now, the timing system for SPring- 8 synchrotron are
under manufacturing. The element for the delay-line in
the output circuit will be changed in this machine. And
this change will make the resolution higher up to20psec.

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