Stacked SOI Pixel Detector using Versatile Fine
Pitch μ-Bump Technology
Makoto Motoyoshi1, Junichi Takanohashi1, Takafumi Fukushima2, Yasuo Arai3,and Mitsumasa Koyanagi2
1Tohoku-MicroTec Co., Ltd. (T-Micro)#203, 6-6-40 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan
E-mail: motoyoshi@t-microtec.com
2Tohoku University, New Industry Creation Hatchery Center
6-6 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan
3
KEK, High Energy Accelerator Research Organization
Institute of Particle and Nuclear Studies
1-1 Oho, Tsukuba, Ibaraki 305-0801, Japan
Abstract— This Paper presents on 3D stacking technology with
2.5μm x 2.5μm In (Indium) bump connections with adhesive
injection [1].
Instead of using the simple test device, thistechnology has been verified using the actual circuit level test
chip. And it was found that the completion of stacking process
is affected by the layout pattern of stacked each tier. In orderto minimize those effects, we have optimized the layout, processparameter and device structure.

get high yield in mass production especially μ-bump with few
μm dimension. So we have chosen the bump bonding with
soft metal, such as In, and adhesive injection. One moremerit of this structure is relaxing bonding stress.
The
highest process temperature is less than 200°C and pairs of
opposite bumps are melted completely and make the robustelectrical connections.

I. INTRODUCTION
LSI technology has been widely spread in two dimensional
over the past three decades and now, it moves into the era ofsub-20nm node. In order to keep up the scaling trend, newtransistors with 3D structure, new materials and processes
have been introduced it. From economical view point, thedevelopment and manufacturing cost for SOC (System onChip) has become sky-rocketing. The 3D-LSI is the one solution to suppress the increasing cost without degradation ofperformances [2]. By separating 3D-LSI technology intoelementary technologies such as (1) through silicon via (TSV)
formation, (2) bump formation, (3) wafer thinning, (4)chip/wafer alignment, and (5) chip/wafer bonding, manymethods to realize 3D-LSI devices can be developed.
We
have been studying the 3D integration with μ-TSV andμ-bump with few μm dimension using simple test device andconfirm the basic properties and reliability. In this paper,
we focused on applying this technology to real circuit test
device, SOI pixel detectors [3]. The simplest structure of
3D-pixel detectors are the two-tile face-to -face stacking devices with fine pitch μ-bump bonding, which requires bumpformation, wafer thinning, chip/wafer alignment with smallalignment error, and chip/wafer stacking techniques. As forbump connection, several methods were reported, such as
Cu-Cu bonding, intermetallic-compound bonding with Cu/Snbump, Au bump bonding, etc.[4],[5],[6],[7],[8]. The Cu-Cu
direct bonding can provide good and robust connection, but itneeds completely clean and surface flatness. Putting wafer/chip stacking with bump bonding process into the actual production, it is difficult to make particle free environment. We
think there must be a sort of redundancy in process in order toII. PIXEL DETECTOR
Pixel detector at collider is designed to collect information
on particles come from the points where particles collide.
Differ from the image sensors for digital camera, this device
needs to detect fewer and much higher energy particles whichpass through. The required key features of a pixel detector
are high sensitivity and high signal processing speed. Fig.1
illustrates the schematic birds-view of silicon base SOI pixel
detector [3]. SOI device provides both a high sensitivity

Fig.1 SOI pixel detector

sensor area in high resistivity bulk substrate and a high speed
RO (readout) circuit area in SOI. Incident charged particle
generates a bunch of hole-electron pairs along the trajectoryin Si sensor and does not stop at all. The generated holes arecollected by p+ diffusion layer in high resistivity Si substrateand sensed by the readout electronics circuits in SOI layer.

As the performance improvement, 3D integration is expected to increase space and time resolution, functionality
without increase of pixel size. And 3D structure solves theback-gate effect for high voltage SOI device completely.
For example, Sensors and analog circuits are fabricated inlower tier and digital circuits and I/Os are in upper tier.

less than 0.6μm. The gap between tiers is about 1.5μm.
An array of In μ-bump junctions does not have enough mechanical strength. So combining gap fill with adhesive isindispensable and injection method is the key of this process.
Fig.3 shows the pixel detector chip before bonding and afterbulk-silicon of upper tier removal.

III. PROCESS
Fig. 2 illustrates the process flow for SOI-3D chip stacking.

Fig. 3 Pixel detector chip before bonding and after Si removal

To avoid the agglomeration of small volume of In bumps,
substrate must be keep low temperature during evaporation.
After silicon removal, CMOS circuits and interconnects oflower tier can be observed by optical microscope through thinupper tier. We have been developing adhesive injection
process using test wafers and test chips with relatively simple
test pattern. But differ from using simple test chip, the space
between tiers in an actual circuit test chip, which must befilled with adhesive is not uniform on entire chip. Checking
the layout pattern where voids have been observed, the particular points of voids formation is found to be occur at thepoints where rapid pressure loss occurs (Fig.4) and near theadhesive flow passes which wrap around spaces.

Fig. 2 Process flow for stacked SOI Pixel Detector

Base SOI chips as upper and lower tiers are fabricated using8” φ 0.20um FD (Fully Depleted)-SOI process. Minimum
bump pad opening size is 3μm x 3μm. Thickness of BOX(buried oxide) layer and SOI layer are 200nm and 40nm, respectively. After forming UBM, In bumps are formed using
evaporation and lift-off technique. The minimum bump sizeand pitch are 2.5μm sq. and 5μm, respectively. Lower tierand upper tier are aligned using IR microscope. Initialalignment error before welding bumps must be kept less than
1.0μm in order to obtain stable electrical connection. After
fusing into one connection, the tiers are self-aligned to below

Fig. 4 Void formation Mechanism

Based on this mechanism, by optimizing bump and bump padlayout, process parameters with combining new injection
method, such as controlled differential pressure assisted capillary action, the voids formation was completely suppressed,
as shown in Fig.5.

Fig.7 shows the two types of pixel detectors. B pattern haslarge TEG area and therefore it has larger dispersion of M4line projection density than that of A pattern. So in adhesive
injection, careful process adjustment was needed. After silicon of upper tier removal, we checked the chip surface by
optical microscope and found no void. The surface of both
detector chips is covered by bond pads and back gate metalelectrodes.

Fig.5 Result of counter measurement of void formation

It is also note about chip alignment, stacked tiers moveslightly during adhesive curing. This occurs because theviscosity of adhesive decrease and In μ-bump became soft
simultaneously in the early stage of curing. Reconsidering
temperature profile of curing, alignment error could be minimized. Fig. 6 shows the bonding alignment marks at chipcorner before and after improvement.

Fig. 7 Two type of pixel detector, (a) after Si removal,(b) after finishing process

Fig. 8 shows SEM cross sectional image of pixel array.
Thickness of upper tier is about 7μm. Top metal layer acts asback gate for FD-SOI MOS transistors in upper tier. If thebump pitch need to shrink to less than 5μm, it might be necessary to optimize the gap between tiers and volume of bumpmetal.

Fig. 8 Cross sectional SEM image of pixel array
Fig. 6 Chip alignment after adhesive curing

Ⅳ. ELECTRICAL MEASUREMENT
In this device, there is new structure, bond pad connections
with W-plug which we had not developed. Through interlayer and BOX via is formed during wafer process. W isexposed Si etchant and damaged. To checking this structure,
the resistance between bond pads with same potential (eg.
GND pads or VDD pads etc.) are evaluated. Although themeasured resistance include resistances of vias and M1-M4
interconnect, these parasitic resistance are sufficient-low tojudge good or not about the bond pad connection. Fig. 9shows the result before and after cleaning.

Instr. and Meth. A636, 2011, S31-36[4] P. Enquist, “Scalability and Low Cost of Ownership Advantages of Direct
Bond Interconnect (DBI) as Drivers for Volume Commercialization of3-D Integration Architectures and Applications,” Mater. Res. Soc. Symp.
Proc., Vol.1112 , 2009, 33-41[5] K. Sakuma, et al., ”Fluxless Bonding for Fine-pitch and Low-volume
Solder 3-D Interconnections,” Proc. 61th Electronic Components andTechnology Conference, 2011, 7-13
[6] A. Huffman, et al., “Fabrication and Characterization of Metal-to Metal
Interconnect Structures for 3-D Integration,” Mater. Res. Soc. Symp.
Proc., Vol.1112 , 2009, 107-119[7] A. Shigetou and T. Suga, “Homo/Heterogeneous Bonding of Cu, SiO2,and Polyimide by Low Temperature Vapor-Assisted Surface Activation
Method,” Proc. 61th Electronic Components and Technology Conference,
2011, 32-36[8] M. Aoyagi, et al., “Micro-cone-shaped Au-bump by gas deposition method for 3D-LSI stacking technology,” Proc. 3D-SIC Conf., 2008, 185-186

Fig. 9 Dispersion of Resistance between Bond Pads

As for μ-bump junction, the average bump resistance obtainedfor 2000 stages bump chain is about 30mΩ. This value
closes to theoretical value calculated from the resistivity of In.
Ⅴ. CONCLUSION
3D LSI Integration technology using minimum 5μm pitch
bump is verified using SOI stacked pixel detector as circuit
level test device. In this technology, adhesive injection isfound the key technology. Optimizing layout, process parameter and adhesive injection method, this process havecompleted without void. If the bump pitch need to shrink toless than 5μm, it might be necessary to optimize the gap between tiers and volume of bump metal.

References[1] M. Motoyoshi, at al., “Current and Future 3D-LSI Technology for Image
Sensor Devices,”

Mater. Res. Soc. Symp. Proc.,Vol.1112 , 2009, 25-32[2] M. Motoyoshi and M. Koyanagi, “3D-LSI technology for image sensor,”
2009 JINST 4 P03009[2] M. Koyanagi, T. Fukushima, and T. Tanaka, “High-Density ThroughSilicon Vias for 3-D LSIs,” Proceeding of the IEEE, 2009, 49-59[3] Y. Arai et al., “Development of SOI pixel process technology,” Nucl.