Design for nanoimprint lithography:
Hot spot modification
through total NIL process simulation
Sachiko Kobayashi*, Kodera Katsuyoshi, Arisawa Yukiyasu, Hirotaka Tsuda,
Ryoichi Inanami, Motofumi Komori, Takuya Kono, Tetsuro Nakasugi andTatsuhiko Higashiki
Institute of Memory Technology Research & Development,Toshiba Memory Corporation
YOKOHAMA, KANAGAWA JAPANE-mail: sachiko1.kobayashi@toshiba.co.jp

Nano-imprint lithography (NIL) has been developed targeting various devices, and for its
pattern fidelity toward the fabrication of fine pattern without using multiple patterning (Figure1)1-3) steps, extensions into fine pattern devices such as semiconductor memories have beenexpected. Layout and process dependent hotspots extraction and modification has become asignificant issue for high volume manufacturing (HVM) of devices with smaller pattern size
and, design for manufacturing (DFM) flow utilizing NIL process simulation incorporating amodel of the nano-imprint process has become necessary.
Process simulation models those are utilized in NIL have been summarized in Figure 2 (a). In
the case of Jet and Flash Imprint Lithography (J-FIL), in which resist drops are dispensed using
ink-jet method, major NIL process steps are, resist drop placement through inkjet nozzle,template imprinting, UV curing and de-molding. NIL process simulations corresponding toeach steps are needed. Dominant resist related factors and corresponding size scale issummarized in Figure 2 (b). The major issue is that the resist flow behavior in the nanometerscale, which is still very unclear, must be considered in the simulation of NIL. In the smaller
sized space under 15 nm, resist viscosity has been observed to be increased. To elucidate themechanism, detailed measurement of resist behavior and characteristics in the finer space isnecessary4-5). An example of pattern collapse analysis using resist fluid simulation is illustrated
in Figure 3.
In this paper, various NIL process simulation6-8) methods, system flow, comparison ofsimulation and experimental data, issues and development prospects are elaborated.
Reference:[1]
Higashiki, T.; Nakasugi, T.; Yoneda, I.; “Nanoimprint lithography and future patterningfor semiconductor devices”, Journal of Micro/Nanolithography, MEMS, and MOEMS 10(04),043008 (2011), https://doi.org/10.1021/nl048355u[2]Kono, T; Hatano, M; Tokue, H.; Kato, H.; Fukuhara, K.; Nakasugi, T.; “Half-pitch
14nm direct patterning with nanoimprint lithography, Proc. SPIE 10958 109580H (26 March2019), https://doi.org/10.1117/12.2514685[3]
Kobayashi, S., Inanami, R., Tsuda, T., Washida, K., Komori, M., Yamashita, K. JiYoung Im; Kono, T. and Maeda, S., “RLT uniformity improvement utilizing multi-scale NIL
process simulation”, Proc. SPIE 10144, Emerging Patterning Technologies, 101440X (31March 2017), https://doi.org/10.1117/12.2258172[5]Itoh, S.; Takahashi, K.; Fukuzawa, K.; Zhang, H.; " Measurement of viscoelasticity ofUV photoresist used for nanoimprint lithography under confinement in nanometer-sized gaps",
Jpn. J. Appl. Phys. 56 06GL02 (2017),

https://doi.org/10.1021/acs.langmuir.5b02713[6]
Ueno, K.; Kasuya, M.; Watanabe, M.; Mizukami, M.; Kurihara, K.; “Resonance shear
measurement of nanoconfined ionic liquids”, Phys. Chem. Chem. Phys., 2010, 12, 4066–4071[7]
Shiotsu, T., Nishikura, N., Yasuda, M., Kawata, H. and Hirai, Y., "Simulation study on
the template release mechanism and damage estimation for various release methods innanoimprint lithography", 06FB07-1 J. Vac. Sci. Technol. B 31(6), Nov/Dec(2013), https://doi.org/10.1116/1.4832215[8]
Taylor, H.K.; Boning, D.S.; "Towards nanoimprint lithography-aware layout design
checking," Proc. SPIE, vol. 7641, 764129, 2010, https://doi.org/10.1117/12.2297361
1x nm HP
Diagonal lines
dense pattern (1)Template1x nm HP
dense pattern (2)3D Structure

ResistdropImprint &Substrate

Template

Alignment

Substrate

2x nm f holes

1x nm f pillars

1x nm holes

Exposure
Substrate

Separation

Template
Substrate© 2019 Toshiba Memory Corporation(a)(b)
Institute of Memory Technology Research & Development
Figure 1. (a) Jet and Flash Imprint Lithography process, (b) Examples of experimental result patterned
by NIL.

(a)(b)
Figure 2. (a) Simulation model utilized in NIL. (b) Physical modes for resist behavior depending on
the size.

Figure 3. Pattern collapse occurs partially caused by bubble trap on the substrate. The resist flow
behavior is shown using resin fluid simulator.