T-MicroInductor

3D Integration Technology for Pixel Detector
and Image Sensor
using 3-μmφ Au Cone Bump Junctions
Capacitor

M. Motoyoshi
LSI(2)(Processor)
T-MicroT. Miyoshi and Y. AraiKEK
M. Ikebe
LSI(1)（demodulator）
Hokkaido University

T-MicroContents
1. Background-previous work

2． Au cone bump using NpD
3. ３D Cost reduction approach

4. Summary
NpD: Nano-particle deposition
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Stacked SOI Pixel detector
Mother particle (p, p)

Back gateelectrode

Detector array
Bond PadBOX(upper tier)

Metal interconnect
Bump junction
BOX(lower tier)p+n+++buried p-well+++
Si sensor+ (high resistivity Substrate)+ ----n--

Charged Particle
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Cross sectional SEM image of pixel arrayusing Indium micro-bump
Back gate Metal MOS Tr

BOX(UT)
M1(UT)UT

M2(UT)
M3(UT)

In bumpM4(UT)
Adhesive
M4 (LT)
M3(LT)
M2(LT)
M1(LT)
BOX(LT)LT

5μｍ
UT: upper tier
LT: lower tierPixel2014 @ Niagara Falls Sept. 4, 2014

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2． Au cone bump using NpD

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T-MicroNano-particle Deposition (NpD) Systemcone bumpNp carrier tube

D chamber

G chambercommutation unit

CCD Camera
Np nozzle

photoresist

shutterAu
crucible
evac. pump

inductive coupling coilsampleHe gas inlet

sample holder
movable stage

evacuation

Courtesy of MIKUNI KOGYO Co., Ltd
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Pros & cons of Au cone bumpPros- good scalability-bump size and height are only determined by lithography process
AuPhotoresist

Sub-no extrusion

In μ-bump

Au cone bumppitch:20μm

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Pros & cons of Au cone bumpPros
- good scalability-bump size and height are only determined by lithography process-no extrusion
conventional Au bump- large bonding margin

SubSubSubSubNpD Au cone bumpeasy to deform
Au   oxidation resistant material

Au cone bumpPixel2014 @ Niagara Falls Sept. 4, 20148SubSubSubSubT-Micro/Motoyoshi

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Pros & cons of Au cone bumpPros- good scalability-bump size and height are only determined by lithography process-no extrusion- large bonding margin

NpD Au cone bumpeasy to deform
Au   oxidation resistant material- low temperature processless than 200 ℃  120℃(our target）

Cons- low throughput

Current process time for 5mm x 5mm chip is around 1hour
An improvement of deposition speed is now in progress

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2.5/5.0μmφ Au Cone Bump
2.5μmφ5μm
5.0μmφTEG cross section
2.5μm cone bump
Au padBarrier metal
AL pad (LSI)
5μm

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Process flow for SOI Pixel detector(1)< Lower Tier >(a) Start with FD-SOI
device wafer
Active Si~50 nm
BOX:200 nm*FD: Fully Depleteｄ

M4< Upper Tier >
M3

M2

M1

BOX
Si R-SiHighBOX
MOS TrSi

bump-landing pad(b) cone bump/landing-pad forming

cone-bump

HighSi R-SiPixel2014 @ Niagara Falls Sept. 4, 2014Si

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After cone bump formation (@ pixel array area)

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Process flow for SOI Pixel detector(1)< Lower Tier >(a) Start with FD-SOI
device wafer

M4

M3

M2

M1

Active Si~50 nm
BOX:200 nm*FD: Fully Depleteｄ< Upper Tier >BOX
Si R-SiHighBOX
MOS TrSi

bump-landing pad(b) cone bump/landing-pad forming

cone-bump

HighSi R-Si

Upper tierSiSiadhesive(c) Chip bonding- face to face infrared alignment- bonding (<200℃)-Adhesive injection

Lower tier

HighSiR-Si
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Process flow for SOI Pixel detector(２)8μm(d) Bulk-Si removal

SiHigh R-Si

Bond PadPassivation

Back gate adjust electrode(e) Pad patterningand passivation

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Cross section of Au cone bump junction
Back gate adjust electrode

FIB prepared region

M5 (upper tier)M5 (lower tier)Pixel2014 @ Niagara Falls Sept. 4, 201415

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Daisy Chain Resistance
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Daisy chain resistance (kΩ)

12108Sample #1Sample #2

6~6Ω/bump4200500

1000
1500
# of bump connection

2000

2500

Ref. ～５Ω ｂｙ 4 terminal resistance
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T-MicroStress evaluation

Evaluate the fluctuation of MOS Transistor caused by thestress of bump bonding
Device dimension N/P MOS Transistor W/L=2/0.2um
Y３
Y２

NMOS
W/L=0.2/2
Ｘ＝2.68um
Ｙ＝3.4um

Y1

cone bump

０X1 X24um

4um

X3

PMOSW/L=0.2/2
Ｘ＝2.88um
Ｙ＝3.4um

4um

4um

μ-bump0X1

X2

X3

adhesive

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MOST IDS vs VDS Characteristics

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