Journal of Mechanical and Electrical Intelligent System (JMEIS)

Short-Time INL Testing Methodology
for High-Resolution ΔΣ ADC
Jianglin Wei1,a, Nene Kushita1,b, Keno Sato2,c, Takashi Ishida2,d,Toshiyuki Okamoto2,e, Tamotsu Ichikawa2,f , Hirotaka Arai1,g, Lei Sha1,h,Anna Kuwana1,i, Takayuki Nakatani1,j, Kazumi Hatayama1,k,and Haruo Kobayashi1,l,*1Division of Electronics and Informatics, Faculty of Science and Technology, Gunma University

1-5-1 Tenjin-cho, Kiryu, Gunma 376-8515, Japan
2ROHM Co., Ltd., 2-4-8 Shin-Yokohama, Kohoku-ku, Yokohama 222-0033, Japan*Corresponding authora<t192d601@gunma-u.ac.jp>, b<t181d024@gunma-u.ac.jp >, c<keno.sato@dsn.rohm.co.jp>
d<takashi.ishida@lsi.rohm.co.jp>, e<toshiyuki.okamoto@lsi.rohm.co.jp>
f<tamotsu.ichikawa@lsi.rohm.co.jp>, g<t1334006@gunma-u.ac.jp>, h<t191d031@gunma-u.ac.jp>
i<kuwana.anna@gunma-u.ac.jp>, j<takayuki.nakatani1017@gmail.com>
k<hatayama@oak.gunma-u.ac.jp>, l<koba@gunma-u.ac.jp >Keywords: ΔΣ ADC, integral-nonlinearity, semiconductor test, polynomial modeling, FFT

Abstract. This paper describes a mass production testing methodology for integral nonlinearity (INL)of a high precision ΔΣ analog-to-digital converter (ADC) in short time. We consider its INL testing byseparating its analog and digital parts: ΔΣ AD modulator and digital filter. The digital filter can betested with the scan-path method. For the AD modulator part, its nonlinear curve of the DC inputoutput characteristics can be obtained using a DC input varying with a fine step, but it takes anenormously long time; it is not practical for mass production testing. So we consider a polynomial
model of the ΔΣ AD modulator input-output characteristics and estimate its coefficient values fromthe fundamental and harmonics power by applying a cosine input and obtaining the modulator 1-bit
output power spectrum with FFT. Its INL can be estimated from the coefficients accurately when themodulator I/O characteristics is continuous. Our simulation and experimental results show thatsignificant testing time reduction can be achieved with the proposed method.
1. Introduction
In recent years, Internet of Things (IoT) has attracted much attention, and the testing of IoT-related
devices in short time with high quality has become more important at mass production shipping for
the IoT system reliability [1-3]. This paper focuses on high-resolution low-sampling-rate ΔΣ ADCs,
which are widely used with sensor interface circuits, such as air flow, temperature, pressure and strain
gauge sensors as well as communication circuits [4-9]. However, its integral nonlinearity (INL) testingtakes extraordinary long time; for example, let us consider the case of a 7 sample-per-second (sps) 24bit ΔΣ ADC and 4 samples for each code used in its INL testing. Then its testing takes 111 days, which
is not acceptable at all because the reasonable testing time is 1 second for 1 US dollar chip.
Therefore, in most cases, the INL testing for the ΔΣ ADC is omitted at mass production shipping.
However, recently high quality and high reliable systems are demanded. Then we have developed its
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Journal of Mechanical and Electrical Intelligent System (JMEIS)INL testing algorithm with drastically reduced testing time as well as keeping good testing accuracy,
and here we present its algorithm as well as simulation and experimental verifications.

Analoginput

DUT: ΔΣADC

Digital output
Decimation
filterDelta-Sigma
modulator
1bit
32ksps24bit 6.8sps

Fig.1. Configuration of a ΔΣ AD converter.

2. ΔΣADCThe ΔΣ AD converter is composed of a ΔΣ AD modulator in the analog section and a digital filter(decimator) in the subsequent stage [4-9]. The ΔΣ AD modulator performs ΔΣ modulation for the
analog input with oversampling, so that noise shaping for the quantization noise is realized. Then 1bit digital data stream is provided as the modulator output, which is fed to the following digital filter
for low-pass filtering and decimation; its output is the entire ADC digital output (Fig. 1).
3. Proposed ΔΣ ADC Linearity Test Method
We consider a 7-sps 24-bit discrete-time ΔΣADC for the target application. Notice that only 7 digital
output data can be obtained in 1 second, and hence the direct INL testing is not acceptable at all (Fig.
2). Hence, we consider here to observe the 32-sps 1-bit data stream of the ΔΣAD modulator for the
INL testing. Notice also that the INL of the overall ΔΣADC is determined only by the ΔΣAD modulator,
and the digital filter does not affect the overall ADC INL if it is well-designed and functional (i.e.,
without any catastrophic faults). Then we propose the following INL testing method (Fig. 3):(1) Separate the AD modulator and the digital filter parts, and test them individually.
(2) The digital filter part is tested by the scan path method whether there are fatal faults. Notice thatthe digital filter part does not cause the overall ΔΣAD linearity deterioration unless it is faulty.
(3) The 1-bit output data stream of the ΔΣAD modulator is externally outputted through a test pin
in test mode (Fig. 3), and it is observed during the test. Its output rate is 32ksps, which is much fasterthan the digital filter (decimator) output rate (7sps).
(4) Since the ΔΣ AD modulator contains an analog circuit, then even if there is not a fatal fault, its
linearity may be degraded by parametric faults such as parasitic circuit components, which should bechecked by the testing. It is assumed here that the input /output characteristics of the ΔΣ AD modulator
do not have jumps (discontinuities), which is different from pipelined ADCs and SAR ADCs (Fig. 4).
(5) We model the input/output characteristics of the ΔΣ AD modulator including nonlinearity
characteristics model with polynomials.
Let 𝑥(𝑡) be an input of the modulator and 𝑦(𝑡) be its output data stream, and then we model its
input/output characteristics with the following n-th order polynomial model:𝑦(𝑡) = 𝑎 + 𝑎 𝑥(𝑡) + 𝑎 𝑥(𝑡) + ⋯ +𝑎 𝑥(𝑡)(1)88
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Journal of Mechanical and Electrical Intelligent System (JMEIS)(6) We apply a cosine wave to the modulator as follows:
𝑥(𝑡) = 𝐴𝑐𝑜𝑠(𝜔𝑡)(2)Here, the amplitude of A is known, and the input signal frequency ω as well as the sampling clock
frequency ωs are low so that the modulator does not show high-frequency performance degradation.
Then substituting Eq. (2) into Eq. (5), the modulator 1-bit output data stream is modeled by𝑦(𝑡) = 𝑏 + 𝑏 𝑐𝑜𝑠(𝜔𝑡) + 𝑏 𝑐𝑜𝑠(2𝜔𝑡) + ⋯ + 𝑏 𝑐𝑜𝑠(𝑛𝜔𝑡)(3)Using the coefficients 𝑎 , 𝑎 , 𝑎 , ⋯ , 𝑎 , the coefficients 𝑏 , 𝑏 , 𝑏 , ⋯ , 𝑏 can be expressed as follows[10, 11]:𝑏 =𝑎 + 𝑎 𝐴 + 𝑎 𝐴 +⋯⎫⎪⎪𝑏 = 𝑎 𝐴 + 𝑎 𝐴 + 𝑎 𝐴 +⋯ ⎪⎪𝑏 = 𝑎 𝐴 + 𝑎 𝐴 + 𝑎 𝐴 + ⋯⎪𝑏 =𝑎 𝐴+𝑎 𝐴 +𝑎 𝐴 +⋯

𝑏 =

𝑎 𝐴 +

𝑎 𝐴 +

𝑏 =

𝑎 𝐴 +

𝑎 𝐴 +
⋮

𝑏

=

𝐴

𝑏 =

𝐴

𝑎 𝐴 + ⋯⎬
𝑎 𝐴 + ⋯⎪
⎪
⎪
⎪
⎪
⎭

(4)

(7) We perform FFT to the1-bit output data stream of the modulator and obtain 𝑏 , 𝑏 , 𝑏 , ⋯ , 𝑏 ;then we derive 𝑎 , 𝑎 , 𝑎 , ⋯ , 𝑎 from the relation in Eq. (4). Now we have the following DC
input/output characteristics:
𝑦(𝑡) = 𝑎 + 𝑎 + 𝑎 𝑥 + ⋯ +𝑎 𝑥
(5)(8) Finally we calculate the INL of the modulator from Eq. (5) using the end-point method or the
best-straight-line method [1].
Remark: In this paper, we use the end-point method for obtain INL.
Example: Consider the case that the 3rd-order nonlinearity is the dominant distortion for the modulator.
Then we model its input/output characteristics as follows:𝑦(𝑡) = 𝑎 𝑥(𝑡) + 𝑎 𝑥(𝑡)(6)Provide to the modulator a cosine wave input 𝑥(𝑡) whose amplitude A is known.
𝑥(𝑡) = 𝐴cos (𝜔𝑡)Then the modulator output 𝑦(𝑡) modeled in Eq. (6) is given as follows:𝑦(𝑡) = 𝑎 𝑥(𝑡) + 𝑎 𝑥(𝑡) = 𝑎 ∙ 𝐴 + 𝑎 ∙ 𝐴

cos (𝜔𝑡) + 𝑎 ∙ 𝐴 cos(3𝜔𝑡)(7)89
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We perform FFT to y(t) and obtain its power spectrum. Then its fundamental spectrum power is given
as follows:𝑏 =𝑎 ∙𝐴+ 𝑎 ∙𝐴
(8)
Its third harmonic spectrum power is expressed as follows:𝑏 = 𝑎 ∙𝐴

(9)

We can estimate the polynomial coefficients 𝑎 , 𝑎 in Eq. (6) from 𝑏 , 𝑏 , and 𝐴, using therelationship among 𝑎 , 𝑎 , 𝑏 , 𝑏 , and 𝐴 in Eqs. (8), (9). Now we can estimate the AD ΔΣ
modulator characteristics given by Eq. (6) and then calculate the overall ADC INL with the end-point
method.
Analog input

DUT: ΔΣADC
Delta-Sigma
modulator

Decimation
filter1bit
32kspsINL Computation

Digital output

Step ramp

Digital output
100101⋯110101⋯010101⋯
24bit 6.8sps
Digital data

Ideal line
Actual line
Analog input [V]Fig. 2. All code testing for INL testing.
Analog input

Sin wave

DUT
Delta-Sigma
modulator
32kspsScan test
Decimation
filter6.8spsDigital output
10101010 ⋯1bit 32ksps
Digital data

FFT Based INL Prediction

Digital output

Prediction (𝑎 , 𝑎 , 𝑎 , 𝑎 , ⋯)Polynomial
𝑦 = 𝑎 +𝑎 𝑥+𝑎 𝑥 +𝑎 𝑥 +⋯Predicted INL
Ideal line
Actual line
Analog input [V]Power [dB]

FFT Result (P1 ,P2 ,P3 ,⋯)
100.0
50.0
0.0
-50.0

P1

FFT power
spectrum
P3⋯
P2
1.0 2.0 3.0⋯
Frequency [Hz]Fig.3. Proposed FFT-based INL prediction method.
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Digital output

INL Computation

Ideal line
Actual line
Analog input [V]Fig. 4. Input/output characteristics of the ΔΣAD modulator without jumps.
4. Simulation Verification of Proposed Integral Linearity Test for ΔΣ AD modulator
4.1 Simulation Conditions
Section 4 shows simulation verifications of the proposed method in Section 3, in the following cases:(i) Discrete-time 1st-order and 2nd-order modulators.
(ii) 3rd-order and 5th-oder nonlinearities.
(iii) Several nonlinearity strength variations.
(iv) Several input cosine wave amplitudes.
(v) Several cases for the number of acquired 1-bit data stream of the modulator output.
Fig. 5 shows our simulation model of the 1st-order ΔΣ AD modulator with nonlinearities.
𝑽𝒊𝒏

+

𝑬
-

𝑽𝒎

M

𝑽𝟎

𝑫𝒐𝒖𝒕
𝜔

𝑽𝒇
𝐃𝐀𝐂
𝜔

Fig.5. Simulation model of the 1st - order ΔΣAD modulator with nonlinearity.
Here

E(n) = V (n) − V (n)V (n) = V (n − 1) + V (n)If V (n) ≥ 0, thenD (n + 1) = 1; V (n + 1) = 1
Else D (n + 1) = 0; V (n + 1) = −1

The block M models the modulator nonlinearity and its nonlinearity strength can be controlled by
the parameter 𝑘. Also notice that the block diagram in Fig. 5 is for system level simulation with
MATLAB; in the actual circuit, the DAC output (Vf) is Vref for Dout =1, or – Vref for Dout = 0, and therange of the ADC input (Vin) is from -Vref to Vref.
In case that 3rd-order nonlinearity is dominant, we use
V (n) = E(n) − 𝑘 ∗ E(n) (𝑘 > 0)

(10)

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In case that 5th-order nonlinearity is dominant, we use
V (n) = E(n) − 𝑘 ∗ E(n) (𝑘 > 0)(11)

In subsections 4.2 - 4.6, we consider the 3rd - order harmonics is dominant and use Eq. (10), whereas
in subsection 4.6 we consider also 5th-order harmonics is dominant and use Eq. (11).
4. 2 DC Input-Output Characteristics with Curve Fitting
In our first simulation, we apply a DC input to the 1st-order modulator input Vin in Fig. 5, from -1
to 1 with 0.05 step and obtain its input/output characteristics as a reference, even though it takes quitea large number of AD modulator samplings. The number of 1’s (𝐷= 1) for each DC value isobtained using 2 data for a given DC input: the input DC value is changed with 0.05 step so thatthe total sampling number to obtain the whole input/output is enormous. The value of k representing
the strength of the nonlinearity is varied as 0.0000, 0.0001, 0.0005, 0.0010, 0.0050, 0.0100, and theis plotted in Fig. 6, which is the DC input/output characteristics and the INL of
number of 1's at 𝐷
the modulator in Fig. 5.
The input/output characteristics in Fig. 5 are polynomial approximated by the following formula:𝑦 = 𝑎 +𝑎 ∙𝑥+𝑎 ∙𝑥 +𝑎 ∙𝑥(12)(a) Modulator output number of 1’s(b) Difference between the ideal and actual modulator output numbers of 1’s.

Fig. 6. Simulation results of the DC input/output characteristics and the INL of the ΔΣAD
modulator in Fig. 5 when the number of the modulator output is 2 .
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Journal of Mechanical and Electrical Intelligent System (JMEIS)
Table 1 shows the values 𝑎 , 𝑎 obtained from the simulation results in Fig. 6 using the curve
fitting for each 𝑘, 𝑎 , and 𝑎 , are relatively very small due to the nonlinearity model usage of Eq.
(10). So they can be ignored and are not written in Table 1. We see the followings from Table 1:(1) As the value of 𝑘 increases, the value of a1 slightly decreases.
(2) As the value of 𝑘 increases, the value of a3 increases.

𝑎𝑎0.0001524180104.840.0005523760524.480.00105232401050.50

0.00505190005282.50

0.010051361010643.00

0.015
0.012
0.009
0.006
0.003
0.000
0.1

k=0.0001
k=0.0050

0.4
0.7
Normalized amplitude[Ampulitude/Vref ]k=0.0005
k=0.01001.0

k=0.0010

a1 Estimation error [%](a) 𝑎 estimation error (input: 0.1 ~ 1.0)

0.012
0.009
0.006
0.003
0.000

k=0.0001
k=0.0050

0.6
0.7
0.8
Normalized amplitude[ Ampulitude/Vref ]k=0.0005
k=0.01000.9

k=0.0010(c) 𝑎 estimation error (input: 0.5 ~ 0.9)

50.0
40.0
30.0
20.0
10.0
0.0
0.1

0.4
0.7
Normalized amplitude[Ampulitude/Vref ]k=0.0001

k=0.0005

k=0.0050

k=0.01001.0

k=0.0010(b) 𝑎 estimation error (input: 0.1 ~ 1.0)

0.015

0.5

a3 Estimation error [%]k

a3 Estimation error [%]a1 Esitimation error [%]Table.1 Estimated coefficient values in the polynomial model of the ΔΣ modulator DC
input/input characteristics.

3.0
2.4
1.8
1.2
0.6
0.0
0.5

0.6
0.7
0.8
Normalized amplitude[ Ampulitude/Vref ]k=0.0001

k=0.0005

k=0.0050

k=0.01000.9

k=0.0010(d) 𝑎 estimation error (Input: 0.5 ~ 0.9)

Fig. 7. Estimation errors of the polynomial coefficients obtained from the 1st-ordermodulator output power spectrum.
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4.3 Cosine Wave Input and Output Power Spectrum
Next, we consider to provide a cosine wave to the AD modulator as Vin (Eq. (2), Fig. 3), and obtainits 1-bit output stream of 2 data. Then we perform FFT for the 1-bit output data stream and obtainits power spectrum; the fundamental wave power P1 and the third harmonic power P3 (Fig. 7). Here
ωin/ωs = 1/2 , ωin is an input angular frequency and ωs is a sampling angular frequency.
As the number of the acquired modulator output data is large, the estimation accuracy for 𝑎 , 𝑎improves; we found that 2 is a reasonable compromise between testing time and accuracy for both
the1st-order and 2nd-order modulators.
4.4 Estimation of Polynomial Coefficients with Proposed Method

Power [dB]

Polynomial modeling is performed for the DC input/output characteristics of the ΔΣ AD modulator,
based on Eq. (6). Then we estimate the values of 𝑎 , 𝑎 from P1 and P3 obtained in Fig. 8, using Eqs.
(8) and (9). Fig. 7 shows the errors of 𝑎 , 𝑎 between these estimates and the ones in Table 1.
Fundamental component power P1

100.0
50.0
0.0

3rd-order harmonic power P3
⋯

-50.0

1.0 2.0 3.0 4.0 ⋯Normalized frequency 2 [ω/ωs]

Fig. 8. Simulation result of the ΔΣ modulator output power spectrum obtained by FFT for acosine wave input.
4.5 2nd-order Modulator CaseA 2nd-order modulator in Fig. 9 with 220 samples is also simulated with the same method. Fig. 10shows the estimation errors of the fundamental and 3rd harmonics for the input with the amplitude of
0.5 to 0.9 from the 2nd-order modulator output power spectrum. We see the following from Fig. 8 andFig. 10:(1) Estimation error for a1 is small for all the input amplitude A.
(2) When the input amplitude A increases to 0.9, then the estimation error for a3 is reduced. Noticethat the input amplitude A is controllable during testing time.
(3) Notice that if the number of data is reduced compared to 2 , the estimation error becomeslarger than the one as shown in Fig. 6 and Fig. 7.
(4) By comparing the 1st-order modulator with the 2nd-order modulator, the estimation errors of theboth models are small. So we expect that this method is applicable for testing also high-ordermodulators.
V

+

E
-

V

V
M

+

V

V

V

D
ω

DAC
𝜔

Fig. 9. Simulation model of the 2nd -order ΔΣAD modulator with nonlinearity.
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Journal of Mechanical and Electrical Intelligent System (JMEIS)
Here
E(n) = V (n) − V (n)𝑉 (𝑛) = 𝑉 (𝑛 − 1) + 𝑉 (𝑛)𝑉 (𝑛) = 𝑉 (𝑛) − 𝑉 (𝑛)V (n) = V (n − 1) + V (n)If V (n) ≥ 0, thenD (n + 1) = 1; V (n + 1) = 1
Else D (n + 1) = 0; V (n + 1) = −1.

0.012

a3 Estimation error [%]a1 Estimation error [%]The block M models the modulator nonlinearity and its nonlinearity strength can be controlled by
the parameter k. In case that 3rd-order or 5th - order nonlinearity is dominant, we use Eq. (10) or Eq.
(11) respectively.

0.010
0.008
0.006
0.004
0.002
0.000
0.5

0.6

0.7

0.8

0.9

3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.5

Normalized amplitude[ Ampulitude/Vref ]k-0.0001

k-0.0005

k-0.0050

k-0.0100

0.6

0.7

0.8

0.9

Normalized amplitude[ Ampulitude/Vref ]k-0.0010(a) 𝑎 estimation error (Input: 0.5 ~ 0.9)

k-0.0001

k-0.0005

k-0.0050

k-0.0100k-0.0010(b) 𝑎 estimation error (input: 0.5 ~ 0.9)

Fig. 10. Estimation errors of the polynomial coefficients obtained from the 2nd - ordermodulator output power spectrum.
4.6 Estimation of INL with Proposed Method
In this subsection, the INL is estimated based on our prosed FFT method and compared with thereference INL obtained by the curve fitting method using simulations. We found that the amplitude
0.9 is the best value for the accurate INL estimation, and notice that during test, the input to the ΔΣADC
under test can be controlled so that the input of 0.9 cos(ωt) can be provided. Table 2 shows the 3rdorder and 5th-order harmonics comparison. Fig. 11 shows their comparison for the amplitude of 0.9
when the 3rd-order harmonics is dominant (Eq. (10) is used), while Fig. 12 is the one when the 5thorder harmonics is dominant (Eq. (11) is used). The vertical axes in Fig. 11 (a), (b) and Fig. 12 (a), (b)show errors of the modulator output 1’s number for 2 data when 1LB is considered as 1/ 2 . We
see in Fig. 11 (c), Fig. 12 (c) that estimated INL errors with our proposed method are sufficiently small.
Fig. 13 shows INL errors as a function of the number of the modulator output data for the amplitudeof 0.9 and k=0.0005; 2 , 2 , 2 , 2 and 2 . We see that the number of the data is larger, theerror is smaller.
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Table. 2 3rd and 5th harmonics estimation maximum error.
k

3rd harmonic estimation error [%]5th harmonic estimation error [%]0.00010.01870.14210.00050.02130.10370.00100.07840.01420.00500.23420.45160.00920.02760.01005. Experimental Verification

6000.04000.02000.00.0-2000.0-4000.0-6000.0

INL [LSB]

INL [LSB]

We have performed experiments with a real ΔΣ ADC chip using the proposed algorithm. Our target
INL test accuracy is within
1ppm, so that requirements for the input signal source are that THD <-120dB and SN > 130dB and synchronization between the signal source and the DUT (Device Under
Test) of the ΔΣADC in Fig. 14. Then we have developed a precise arbitrary waveform generator(AWG) whose performance is shown in Fig.15. and the NI PXI system in Fig. 16. is used and test
environment in Fig. 17. The modulator output FFT results are obtained in Fig. 18, and the INL
prediction is shown in Fig. 19. These results show that our proposed method can estimate the INL at
ppm level.

-1.0 -0.6 -0.2
0.2
0.6
1.0
Analog input normalized with full scale
k=0.00010
k=0.0050

k=0.00050
k=0.01000

k=0.00100

Estimation error [%](a) INL obtained by our proposed FFT method6000.04000.02000.00.0-2000.0-4000.0-6000.0
-1.0
-0.6
-0.2
0.2
0.6
1.0
Analog input normalized with full scale
k=0.00010
k=0.0050

k=0.00050
k=0.01000

k=0.00100(b) INL obtained by the curve fitting method

0.5
0.4
0.3
0.2
0.1
0.0
0.000 0.002 0.004 0.006 0.008 0.010k(c) INL error between the FFT and curve fitting methods

Fig. 11. INL comparison between the FFT and curve fitting methods when the 3rd-orderharmonics is dominant.
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6,000.0
4,000.0
2,000.0
0.0-2,000.0-4,000.0-6,000.0

INL [LSB]

INL [LSB]

Journal of Mechanical and Electrical Intelligent System (JMEIS)

-1.0

-0.6

-0.2

0.2

0.6

6,000.0
4,000.0
2,000.0
0.0-2,000.0-4,000.0-6,000.0

1.0

-1.0

k=0.00050
k=0.01000

k=0.00100

k=0.00010
k=0.0050

Estimation error[%](a) INL obtained by our proposed FFT method0.00150.00120.00090.00060.00030.0000
0.000

-0.2

0.2

0.6

1.0

Analog input normalized with full scale

Analog input normalized with full scale
k=0.00010
k=0.0050-0.6

k=0.00050
k=0.01000

k=0.00100(b) INL obtained by the curve fitting method

0.002

0.004

0.006

0.008

0.010

k
(c) INL error between the FFT and curve fitting methods

0.016

Estimation error[%]

Estimation error[%]

Fig. 12. INL comparison between the FFT and curve fitting methods when the 5th - orderharmonics is dominant.
0.012
0.008
0.004
0

2^14
2

22^16

2^18
2

5.0
4.0
3.0
2.0
1.0
0.0

2^20
2

2
2^14

Estimation error[%]

Number of modulator output data(a) 𝑎 estimation error

2
2^16

2
2^18

22^20

Number of modulator output data(b) 𝑎 estimation error

2.5
2.0
1.5
1.0
0.5
0.0

2
2^16

2
2^18

2
2^20

2
2^22

Number of modulator output data(c) 𝑎 estimation error

Fig.13. Number of the modulator output data and estimation errors for a1, a3, a5 with theproposed FFT method.
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Journal of Mechanical and Electrical Intelligent System (JMEIS)

Output: 1kHz 44.1ksps
THD: 122dB (~5th-order harmonics)
SN: 131dB (Filter:20kHz LPF)

Fig. 14. Signal from our developed AWG.

(a) PXI compatible module(b) ROHM 32bit audio DAC

Fig. 15. Development of precise AWG.

Fig.16. Use of NI PXI system for experiment.
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Journal of Mechanical and Electrical Intelligent System (JMEIS)(a) PXI setup(b) DUT board

Fig. 17. Test environment.

Input amplitude A= 2.252Vpp (differential)

Fig. 18. Experimental result of the modulator output FFT.

Fig. 19. Obtained INL prediction with the proposed method.

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Journal of Mechanical and Electrical Intelligent System (JMEIS)
6. Discussions(i) Integral nonlinearity test time estimation:
Suppose that the ΔΣAD modulator operates with 32ksps and the required number of data for INL
test is 2 . Then the required testing time is 32 seconds. If 32 chips are tested in parallel, theequivalent test time per chip is 1 second; this test time may be acceptable for industry applications.
The following are calculation equations:a) The INL testing time with the direct method for a 7-sps 24-bit ΔΣADC is calculated by
Test Time = 2∗ ∗ 𝑛 [sec] = 666 h ∗ 𝑛Here, 𝑛 =In case n=4, its testing time is 111 days.
b) On the other hand, when the proposed method is used, the testing time is given by
Test Time = 2∗,= 32 sec(ii) One might claim that if the gain of the operational amplifier inside the modulator is not highenough, the input/output characteristics of the ΔΣ AD modulator can have jumps and it is notcontinuous [4]. However, our target ΔΣ ADC does not have the jumps with some circuit techniques.
(iii) For the direct INL method, a precise DC signal generator with more than 24-bit resolution isrequired for the modulator input. However, for the proposed method, a low distortion signal generator
and a low-pass filter such as [12] are enough. Recently 32-bit ΔΣ ADCs are commercially announced
and there would not be a DC signal generator for their INL testing with the direct method; an ultrahigh-precision DC signal source is difficult to realize.
(iv) The proposed method can be applied for high-order modulators, continuous-time modulatorsand multi-bit modulators; this is under investigation.
(v) The proposed method can be considered as solving so-called an inverse problem. The modulator
nonlinearity is modeled as a polynomial and its coefficients are estimated by the FFT method; themodulator INL is indirectly measured by its output power spectrum.
7. Conclusion
We have proposed a short-time high-accuracy integral linearity test method/algorithm of the highresolution low-sampling-rate ΔΣADC for mass production. We have conducted its modeling andsimulation as well as experimental verification. For the next step, we will take higher-order distortions
into account, and apply the proposed method to higher-order modulators. We will also perform further
experiments with real ΔΣADC chips and verify the test time in the ATE environment.
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Journal of Mechanical and Electrical Intelligent System (JMEIS)[4] Understanding Delta-Sigma Data Converters, 2nd Edition, R. Schreier, S. Pavan, G. C. Temes(New Jersey, USA), 2017.
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