2024

2024 IEEE SYMPOSIUM

ON VLSI TECHNOLOGY AND CIRCUITSBRIDGING THE DIGITAL& PHYSICAL WORLDS

with efficiency & intelligence
H ILTON H AWAIIAN VILL AGE
H O N O LULU, H AWAIIJUN E 1 6 - 2 0 , 2 0 2 2

ProgramThis information is current as of June 14. For more up to date information,please log onto MYS https://vlsi24.mapyourshow.com/8_0/sessions/#/
Workshops
Sunday, June 16, 1:00 PM – 5:30 PM
Standing Workshop: Open-Source Design
1:00 PM, Tapa 1
Advancing SoC Design: Open-Source and ML-Driven Approaches in the Cloud
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Cloud bursting an EDA workload with ML-driven technique for future SoC development, by Dr.
Wachirawit Ponghiran and Dr. Jinwook Jung (IBM Research)
Generative AI-based EDA for SoC, by Dr. Rangharajan Venkatesan (NVIDIA)
Chipyard: An Open-Source Design, Simulation, and Implementation Framework for Custom
RISC-V SoCs, by Sagar Karandikar (UC Berkeley)
ESP: An Open-Source Platform for Agile SoC Design, by Dr. Luca Carloni (Columbia University)
AMS generation frameworks: an industry perspective, by Dr. Cooper Levy (Intel)
Agile SoC Design With OpenROAD and Proprietary Flows: A Retrospective, by Dr. Austin Rovinski(NYU)
Agile-X: democratization base of innovative semiconductor technology, by Dr. Makoto Ikeda(University of Tokyo)
Freshmen through Ph.D. students experience open-source tape-out: successes and pitfalls, by
Dr. Mark Johnson (Purdue University)

Circuits Workshop 1: High-Performance Mixed-Signal Circuits: Recent Art Balancing the Analog vs.
Digital
1:00 PM, Tapa 3
The aim of this workshop is to gather prominent figures in the field to discuss recent advancements inmixed-signal circuits for high-speed / high-accuracy applications, including PLLs, ADCs, DACs, andmore. Our focus lies on high-performance systems, specifically on achieving the optimal balance between
pure analog performance and the integration of digital assistance / calibration to maximize system-level
performance. We strive to provide the audience with a view and examples of how real-world designs(ADCs, PLLs, DACs) partition/budget their performance between raw-analog and digitally-assisted,showing what criteria are normally followed in these decisions. A secondary goal would be to commenton some of the techniques that are exploited on each side (analog, digital) to enable and realize suchpartitioning.
Moderators: Jorge Lagos, imec and Tetsuya Iizuka, The University of Tokyo•••

PLLs, Tetsuya Iizuka, The University of Tokyo
DACs, Martin Clara. Intel
ADCs, Huseyin Dinc, Analog Devices

Technology Workshop 2: Novel Metals and Advanced Interconnects
3:15 PM, Tapa 2Organizers: Christoph Adelmann, Zsolt Tőkei, imec

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Novel Metals for Advanced Interconnects, Christoph Adelmann, Imec
An industry perspective of beyond Cu, alternative metal interconnects, Christopher Jezewski,Intel
Replacing Tungsten and Copper by Molybdenum in logic technology, Vamsi Paruchuri, ASM
International
The search for new materials for interconnects < 10 nm, Daniel Gall, Rensselaer Polytechnic
Institute
Opportunities and challenges of intermetallic compounds for future interconnects, Junichi Koike,
Tohoku University
Intercalated Graphene for Advanced Interconnects, Kaustav Banerjee, Destination 2D and
University of California Santa BarbaraInterconnect Technology/System Co-Design for VLSI Logic and Memory Systems, Chenyun Pan
University of Texas at Arlington

Circuits Worshop 2: BioSensory Breakthroughs: Pioneering the Future of Health Tech
3:30 PM, Tapa 3This workshop session discusses the forefront of sensor technology and bioelectronics integration. Dr.
Drew Hall (UCSD) explores the future of injectable biosensors, while Dr. Mahsa Shoaran (EPFL) discusses
low-power AI-driven neural interfaces. Dr. Minkyu Je (KAIST) presents low-power bioimpedance
measurement techniques, and Dr. Suﬁ Zafar (IBM) focuses on miniaturized biosensors. Dr. Ken Shepard(Columbia University) explores CMOS bioelectronics for eﬃcient implantables, and Dr. Ada Poon (Stanford
University) introduces a battery-free sticker-like reader for wireless passive sensors. These presentations
collectively highlight the transformative potential of sensor technologies across diverse applications.
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Injectable Biosensors: Is there a future? Drew Hall, UCSD
Low-Power AI-Driven Neural Interfaces for Treating Brain Disorders, Mahsa Shoaran, EPFL
Low-Power Bioimpedance Measurement Techniques for Sensing and Imaging, Minkyu Je, KAIST
Silicon Device based miniaturized biosensors for Healthcare & IoT, Suﬁ Zafar, IBM
CMOS bioelectronics for volumetrically eﬃcient implantables, Ken Shepard, Columbia University
A Battery-free Sticker-like Reader for Wireless Passive Sensors, Ada Poon, Stanford University
Short Courses
Circuits Short Course
Monday, June 17, 8:20 a.m. – 5:00 p.m.
Tapa 3Circuits and Systems for Heterogeneous Integration
Organizers:
N. Kocaman, Broadcom
K. Nii, TSMC
8:30 a.m.
Advanced Packaging Enabling Heterogeneous Integration, Liwei Wang, AMD
Abstract: The exploding demand for computation spans from the cloud to the edge, and from artiﬁcial
intelligence (AI) to 5G communications, is driving the technology and design innovations beyond what
Moore’s law can support with raw silicon scaling. As is widely known, silicon technology node introductions

have been slowing down and simultaneously delivering less beneﬁt, while at the same time the costs per
yielded mm2 of silicon are going up. This is particularly challenging because the semiconductor industry
has thrived on delivering more performance and features in each Si node generation. With these trends,
the cost per transistor will stop scaling in the next few years, which creates notable economic headwinds
to meeting the demand. The next aspect of the slowdown in node introductions is that scaling factors arediverging between diﬀerent intellectual property (IP) types, with static random-access memory (SRAM)
and especially analog circuits lagging well behind the scale factors of logic. This leads to the chip-level viewof area scaling where, with a mix of logic, SRAM, and analog content, it’s not feasible to shrink chip designs
appreciably toward the end of this decade. The trillion-dollar question is how to architect, design, andbuild future systems that solve these challenges. The answer is increasingly clear that heterogeneous
integration of the modular, multi-chip design/chiplets is a fundamental enabler.
9:20 a.m.
I/O design considerations for die-to-die interface, Yoshinori Nishi, NVIDIA
Abstract: Today's advanced systems feature multiple chips and chiplets on interposers, using technologies
commercially known as EMIB, CoWoS, InFO, FOCoS, and several others from multiple sources. These
2D/2.5D structures require ultra-dense I/O PHYs to deliver a large amount of data between dies over a
distance of a few millimeters without adding much power and area penalty to each die. In this talk, we will
highlight several important use-cases of chiplets for AI and data centers, along with ongoingstandardization eﬀorts and the latest trends in I/O circuit designs for die-die interface.
10:10 a.m.

Break

10:30 a.m.
Directions, Challenges and Opportunities in Heterogeneous Integration and Packaging, Chris Pelto, Intel
Abstract: In this tutorial we will focus on the evolution, current value and future scaling opportunities ofheterogeneously integrated (HI) advanced packaging architectures which continue to deﬁne technology
envelopes. HI is a powerful, crucial enabler for the continued growth of computing and communication
performance. Advanced packaging technologies are critical enablers of HI because of their importance ascompact, power eﬃcient platforms. A roadmap of the future generated as part of an industry-academic
collaboration will be discussed in this context to highlight the opportunities generated by
HI. Opportunities in physical interconnect scaling, an important part of the HI Roadmap will be discussed
in detail. We will also discuss the impact of package features on high speed IO and broadly describe
challenges in power delivery, cooling, manufacturing and design.

11:20 a.m.
Heterogenous integration for automotive ICs, Hubert Bode, NXP
Abstract: Heterogenous integrated systems have a long history in automotive electronics. Automotive
system requirements are illustrated and examples of heterogenous systems are given. Factors inﬂuencing(heterogenous) systems and their architectures are discussed. Formerly monolithic devices are now more
and more build as heterogenous systems. This is caused by car architecture evolvement inﬂuencing whatsilicon technologies can be used eﬀectively. Examples of heterogenous systems with partitioning and subsystem interfaces are shown. System aspects versus the automotive requirements and considerations
arising out of the heterogeneous integration are discussed. An outlook is given about the car OEM’s visionof future car control systems.

12:10 p.m.

Lunch

1:20 p.m.
Wafer Scale System Integration Technology, Kuo-Chung Yee, TSMC
Abstract:
In recent years, advanced packaging has taken center stage of the semiconductor industry to pursue evermore energy eﬃcient, high-performance, and cost-eﬀective electronic systems. While wafer scale system
integration technology (WSSIT) is going through revolutionary technology advances across mobile
computing and HPC/AI computing applications. Such wafer scale system integration technologies include
wafer scale fan-out PoP in smart mobile system, wafer scale fan-out on substrate in networking, wafer
scale 2.5D interposer package in HPC/AI, wafer scale 3D chip on wafer stack in HBM, 3D V-cache, and 3D
wafer on wafer stack in CIS and power delivery. Wafer scale integration features high yield, ﬁne pitch, highdensity interconnects and tight integration between chiplets, leveraging installed capacity of advanced
wafer-based tools & materials, design & process know-hows to enable IC-ized manufacturing with ﬁneprocess control, monitor, and robust integrity. This presentation will introduce the main wafer scale
integration technologies in mobile and HPC/AI applications, featuring the ﬁgure of merits (aka EEPAC) onarchitecture, integration process, and interconnect of various electronics compute systems. Design
considerations and process challenges of WSSIT will also be discussed.
2:10 p.m.
Advancements in Co-Packaging and Co-Integration Technologies for High-Performance Memory
Systems, Kyungryun Kim, Samsung and Wonkyoung Choi, Samsung
Abstract:This course presents a comprehensive examination of co-packaging and co-integration
technologies for high-performance memory systems, highlighting their pivotal roles in system
performance and eﬃciency. Due to advancements in 2.5D packaging technologies, memory andcomputation dies are co-packaged and connected with higher bandwidth than ever. Silicon interposer
technology enables a higher bandwidth connection between memory and computation dies via densely
integrated I/O lines, while die stacking technology, using through-silicon vias (TSVs) and micro-bumps,
brings a large amount of memory closer to a computation die. These solutions not only provide higher
performance and density but also better power eﬃciency via tight memory connections. As a next step,
3D packaging technologies are being developed to allow even tighter connections between memory andcomputation dies. In this conﬁguration, multiple memory dies will be mounted on and connected to acomputation die via TSVs and micro-bumps, and this architecture possibly enables the shortest and widest
connection path between memory and computation dies. The ﬁnal step of co-packaging and cointegration will involve integrating computational logic into a memory die, a so-called Processing-inMemory (PIM) technology. This technology has emerged as a pivotal, promising solution to reduce latency
and power consumption by oﬄoading logic operations to memory. As an interim solution, the concept ofcustom High Bandwidth Memory (CHBM), where custom computation logic is integrated into an HBM
buﬀer die, has emerged. Many companies are actively exploring the potential diﬀerentiation via cointegration of logic and memory based on the CHBM architecture.
3:00 p.m.

Break

3:20 p.m.
Evolution and Future of Heterogenous 3D Integrated Circuits and their Design using EDA Tools, David
Stratman, CadenceAbstract: The past twenty years have introduced multiple waves of novel 2.5D/3D integrated circuitdesign, implementation, fabrication, and packaging techniques to the semiconductor industry. While someapproaches have found commercial adoption and success, others remain niche and seemingly forever
waiting for mainstream deployment. This paper is an introduction to the layered history of why thesethree-dimensional constructs have evolved to help overcome the slowing scaling of Moore’s law, thegrowing cost of manufacturing advanced ICs, and the increasing complexity of chip design. In addition tocataloging the various 3DIC approaches, we will also discuss the electronic design automation (EDA)
industry’s role in enabling the current state of the art, and goals towards driving the future. The pace ofinnovation in the 3DIC space has accelerated over the last ﬁve years with the industry’s embrace of chipletsand growing ability to stack or bridge integrated circuits from diﬀerent process nodes and even diﬀerent
foundries. These exciting trends and the advent of new EDA platforms and AI-driven design techniques are
shaping the future of 3DIC.
4:10 p.m.
Integrated Power Delivery and Management Technologies for Heterogenous Integrated Systems, HanhPhuc Le, UCSD
Abstract: The semiconductor industry is betting its future of next generation microelectronic systems onheterogeneous integration (HI) for more performance density, particularly in in data center, autonomousvehicle, and mobile applications. To support this irreversible direction, it is very important to haveadequate advanced technologies that can help meet the increasingly demanding requirements for
integrated power delivery in terms of eﬃciency, size, reliability, and cost while addressing the need tosimultaneously support many supply rails, large input/output voltage diﬀerences, and high output current
density. In this talk, the speaker will describe a set of integrated power delivery and management
techniques and technologies that could be strong candidates to address this need, including integrated
power delivery architectures, advanced converter topologies, integrated passive devices, packaging
strategies, and other technologies on the horizon. An example of a 2-stage HI power delivery will also be
included.
Technology Short Course
Monday, June 17, 8:25 a.m. – 4:50 p.m.
Tapa 2
Advanced VLSI Technologies for Next Generation Computing
Organizers:
Y. Liang, Nvidia
S. Fujii, Kioxia
8:30 a.m.
CMOS Device Scaling for Power-Performance - Key Physics and Challenges, Jeﬀ Wu, TSMC
Abstract: Along with doubling of components on a microchip every two years following Moore’s law, theoverall performance and power eﬃciency have also improved exponentially over the years, thanks to
CMOS device scaling which has been the work horse behind the phenomenal performance gain. Key
considerations in device architecture and design to optimize power-performance are discussed. Physics
emerging or becoming more important in the extremely scaled devices will be highlighted and illustrated.
9:20 a.m.
Innovations of Material and Process Engineering in the Angstrom Era for Advanced CMOS Logic
Technology, Veeraraghavan Basker, Applied Materials

Abstract: The relentless pursuit of Moore's Law scaling has led to the emergence of the Angstrom era. 3D
device architectures, such as gate-all-around (GAA) transistors, provide enhanced control and scalability.
Process advancements include EUV lithography, atomic layer deposition & etching, and directed selfassembly deposition enabling precise control at the atomic scale. These innovations overcome
fundamental limitations, delivering signiﬁcant improvements in power, performance, area & cost (PPAC)
as well as facilitating continuous advancement in CMOS technology for next generation computing
applications.
This short course explores the pivotal role of material and process advancements in the Angstrom era
pushing the boundaries of advanced logic CMOS technology. Firstly, it delves into the current state-of-art
GAA nanosheet (NS) technology and the key challenges. Various process and device solutions to extend
GAA NS for upcoming technology nodes will be discussed. The synergistic eﬀects of integrating material
and process innovations leading to enhanced device performance, reduced power consumption and areascaling in GAA NS technology will be addressed. Furthermore, this course will examine the 3D
CFET/Stacked-FET architecture and its fabrication options. It will also highlight the recent progress ofmonolithic-CFET (m-CFET) in the industry. Lastly, key unit process bottlenecks will be illustrated in a generic
m-CFET ﬂow.
10:10 a.m.

Break

10:30 a.m.
Integration Challenges for Pitch Scaling in Advanced BEOL Interconnects, Hirokazu Aizawa, TEL
Abstract: Since the introduction of device chips with copper (Cu) interconnects in 1997, this technology
has been the backbone for Back-End-of-Line (BEOL) of logic devices, and it has evolved with improved
metallization and integration schemes to keep pace with Moore’s law. However, concerns have arisen
regarding the technological constraints of Cu damascene interconnects due to continuous pitch scaling.
Consequently, intensive research and development eﬀorts are underway for the next generation ofinterconnect technology, exploring alternative metals and subtractive interconnect methods.
This short course aims to provide a comprehensive overview of the technical challenges associated withCu damascene interconnects amid advanced pitch scaling. It will also discuss potential technical solutions
and oﬀer insights into the future of interconnect technology.
11:20 a.m.
Functional Backside: past, present, and STCO future, James Myers, IMEC
Abstract: Since the end of Dennard scaling, power density has become a prime concern in futuretechnology roadmaps. Design technology co-optimization (DTCO) research has shown that using thebackside of the wafer to bring power delivery networks (PDNs) closer to the transistors has signiﬁcantbeneﬁts for logic density and power integrity. Now that foundries have announced support for backside
PDN in future nodes, what additional functionality could be migrated or added to the backside? Whatsystem level problems could this solve? System technology co-optimization (STCO) is required to answer
these questions and can propose new technology options tailored to the diﬀering requirements of mobile,
GPU, server or wearables. Eventually, the roadmap may evolve towards a complex heterogeneous device
stack that is very disruptive to future designs – CMOS 2.0.
12:10 p.m.
1:20 p.m.

LunchIn-memory-computing with emerging memories, J. Joshua Yang, University of Southern California
Abstract: The rapid advancement of machine learning and artiﬁcial intelligence is propelling a pressing
need for dramatically enhanced computing power, prompting the exploration of innovative computing
paradigms such as in-memory computing (IMC). IMC oﬀers a solution to the diminishing cost-eﬀectivenessof transistor scaling and the inherent ineﬃciencies of traditional non-von Neumann computing
architectures in dealing with big data. This short course will discuss the special requirements on memory
devices for IMC applications. It evaluates various resistive switching materials (RSMs) based on diﬀerent
physical principles, including redox reactions, phase transitions, spin-polarized tunneling, and ferroelectric
polarization, to discern their suitability for IMC applications. Redox-reaction-based RSMs, as the mostadvanced among these four for IMC, will be used as an example to reveal insights into the fundamental
concepts, existing challenges, and potential solutions. Additionally, it oﬀers glimpses into chip-level
demonstrations showcasing the practical implications of these emerging memories.
2:10 p.m.
Opportunities to break through limit and to enable prolongation of DRAM, Hui-Jung Kim, Samsung
Electronics
Abstract:For several decades, many eﬀorts on a VLSI technology have been made to increase the bitdensity of the dynamic random access memory (DRAM), which successfully enabled a scaling down of the
DRAM nodes to sub-20 nm. The success relies on structural innovations in a small dimension, among themost critical examples as (I) a recessed channel array transistor (RCAT) and a buried channel arraytransistor (BCAT) have facilitated vertical channel length with reliable switching performances in a small
dimension, (II) an implement of BL isolation from other electrodes in one pitch of cell array structure, (III)storage capacitors, a hexagonal arrays and supporter structure expands the charge storage eﬃciency
without a leaning of capacitor nodes in high-aspect-ratio-capacitor. However, as the scaling down
continues the further reduction of the design rule to sub-10nm, DRAM will be threatened because theallowed lateral space has a limitation on characteristics of cell transistors, coupling noises of inter-wires
resulting in RC delay, and charge isolation in storage capacitors.
This presentation will explore challenges in scaling of conventional 6F2 as mentioned above, andinnovative opportunities which are 4F2 vertical channel transistor (VCT), vertically stacked DRAM(VSDRAM) cell structure and other candidates as structural solutions to break through scaling limit,
including essential technologies on integration processes to implement.
3:00 p.m.

Break

3:20 p.m.
Metrology & Inspection: Past, Present, and Future, Byoungho Lee, Hitachi High-Tech
Abstract: Metrology&Inspection was “a good to have” process until the late 2000s. However, as process
miniaturization entered below 100nm and NAND devices became 3D structures, the perception of the MIprocess changed to “a must have”. Currently, device development research and major process monitoringin HVM cannot be carried out without the help of MI. However, many people still do not understandexactly what MI is, and even if they do, it is very basic and often leads to misunderstandings. This training
seeks to understand the basic concept of MI and its evolution. Based on this, we would like to analyze
trends in MI technology and explain future directions.
4:10 p.m.
Silicon photonics for high bandwidth optical I/O, Haisheng Rong, Intel Labs

Abstract:Traditional electrical oﬀ-package I/O solutions for high-value compute silicon (e.g., CPUs, GPUs,
FPGAs, and ASICs) are facing enormous scaling challenges in meeting the ever-increasing bandwidth
demands. Silicon Photonics is one of the most promising technologies to circumvent these challenges andprovides a viable path for high bandwidth density and energy-eﬃcient optical-compute-interconnect. This
talk will focus on high-speed silicon photonic DWDM transceivers with integrated lasers, optical ampliﬁers,
silicon modulators, and photodetectors co-packaged with CMOS electronic drivers and receivers to meet
future optical I/O demands for AI/ML.
Demo Session & Reception
5:30 PM, Tapa 1
Opening and Plenary I
Tuesday, June 18
8:00 AM, Tapa 1-3

Chairpersons: V. Narayanan, IBM
R. Kapusta, Analog Devices
8:00 a.m.

Welcome and Opening Remarks and Awards
G. Jurczak, Lam Research
B. Nikolić, University of California, Berkeley

P1.1 – 8:35 AM
Making Sense at the Edge (Invited). Ahmad Bahai, Texas Instruments, SVP & CTO
Semiconductor technology provides the foundation for advanced embedded sensing and actuating
technologies across a broad range of applications enabling data driven intelligent systems. Advances innanotechnology, analog and digital signal processing, embedded/edge machine learning algorithms,
connectivity and battery technology have enabled high performance sensing and actuation which was
inaccessible a decade ago. Yet in many sensing and actuating modalities, nature offers a significantly more
efficient edge computing sensory solution leveraging the hierarchical physical, analog and digital signal
processing to optimize performance and energy consumption. In this talk, we review some examples oflow power adaptive biosensors as well as bio inspired sensor fusion and how they inspire innovative newdevices, circuits and ML systems for intelligent sensing and actuating.
P1.2 - 9:15 AM
Mobility Evolution: Electrification and Automation (Invited), Kazuoki Matsugatani, DENSO Corporation,
Senior Director, R&D Center
The automotive industry faces two challenges: environmental impact reduction and safety enhancement.
Particularly, efforts to achieve zero CO2 emissions and zero traffic fatalities are urgent issues for the
coming decade. Electrification, the transition from internal combustion engines to electric motors,
profoundly alters vehicle mechanics. Automation, transferring driving control from humans to computers,
integrates software and information technologies into the vehicle system. In both electrification andautomation, semiconductor devices’ evolution is key. For electrification, the power device managing
current from the battery to the motor is crucial for inverter operation. Additionally, an analog sensing
device measuring current to and from the battery delivers essential data regarding the battery’s state ofcharge and health. As for automation, various sensors – including camera, radar, lidar and sonar – that

monitor outside and inside of the vehicle are required. Furthermore, high-performance computers andwireless communication devices are required to process sensor data, establish a connection between thevehicle and an external network, and control the vehicle on behalf of the human driver. This plenary talkwill introduce and explain the functions of these semiconductor devices.
Session T1: Technology Highlights
10:15 AM, Tapa 1-3
Co-Chairs:

Ben Colombeau, Applied Materials
Toshifumi Irisawa, National Institute of AIST

10:15 AM
T1.1 An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC
Product Applications, Walid Hafez1, D Abanulo1, M Abdelkader1, S An1, C Auth1, D Bahr1, V Balakrishnan1,
R Bambery1, M Beck1, S Bhowmick1, J Biggs-houck1, J Birdsall1, D Caselli1, H.-Y. Chang1, Y Chang1, R
Chaudhuri1, S Chauhan1, C Chen1, V Chikarmane1, K Chikkadi1, T Chu1, C Connor1, R DeAlba1, Y Deng1, D
Diana1, Y Dong1, P Elfick1, T Elko-hansen1, B Fallahazad1, Y Fang1, D Gala1, C Geppert1, S Govindaraju1, H
Grunes1, L Guler1, Z Guo1, A Gupta1, M Hattendorf1, S Havelia1, J Hazra1, A Islam1, A Jain1, S Jaloviar1, M
Jamil1, M Jang1, M Kabir1, J Kameswaran1, E Karl1, S Kelgeri1, A Kennedy1, C Kilroy1, J Kim1, Y Kim1, D
Krishnan1, G Lee1, H.-P. Lee1, Q Li1, H Lin1, A Luk1, Y Luo1, P Macfarlane1, A Mamun1, K Marla1, D Mayeri1,
E Mckenna1, A Miah1, K Mistry1, M Mleczko1, S Moon1, D Nardi1, S Natarajan1, J Nathawat1, C Nolph1, C
Nugroho1, P Nyhus1, A Oni1, P Packan1, D Pak1, A Paliwal1, R Pandey1, I Paredes1, K Park1, L Paulson1, A
Pierre1, P Plekhanov1, C Prasad1, R Ramaswamy1, J Riley1, J Rode1, R Russell1, S Ryu1, H Saavedra1, T
Salisbury1, J Sandford1, F Shah1, K Shang1, P Shekhar1, A Shu1, E Skoug1, J Sohn1, J Song1, M Sprinkle1, J Su1,
A Tan1, T Troeger1, R Tsao1, A Vaidya1, C Wallace1, X Wang1, H Wang1, C Ward1, S Wickramaratne1, T Wu1,
Z Xia-hua1, S Xu1, P Yashar1, J Yaung1, Y Yu1, M Zilm1, B Grimm1, M Bhargava1, M Wills1, C Destefano1, D
Garg1, B Sell1 1IntelAn advanced Intel 3 FinFET technology is presented that has been optimized to provide 10% logic scaling,a full node of performance improvement and improved reliability compared to Intel 4. Through transistor
enhancements, interconnect optimization, and design co-optimizations up to 18% performance gain at
iso-power is achieved over Intel 4.
10:40 AM
T1.2 Highly Manufacturable Self-Aligned Direct Backside Contact (SA-DBC) and Backside Gate
Contact (BGC) for 3-dimensional Stacked FET at 48nm Gate Pitch, Jaehyun Park1, Juhun Park1, Kyuman
Hwang1, Jinchan Yun1, Dahye Kim1, Sungil Park1, Jejune Park1, Jinwook Yang1, Jae Won Jeong1, Chuljin Yun1,
Jinho Bae1, Sam Park1, Daihong Huh1, Sanghyeon Kim1, Seungeun Baek1, Suk Yang1, Inhae Zoh1, Junghan
Lee1, Tae-sun Kim1, Younsu Ha1, Sun-Jung Lee1, Sang Wuk Park1, Bong Jin Kuh1, Daewon Ha1, Sangjin Hyun1,
Su Jin Ahn1, Jaihyuk Song1 Samsung Electronics
In this study, we have demonstrated 3-Dimensional Stacked FET (3DSFET) with Self-Aligned Direct Backside Contact (SA-DBC) and Back-side Gate Contact (BGC) in 48nm gate pitch, which is the smallest
dimension and the world's first demonstration reported so far. Simultaneous threshold voltage (Vt)targeting for both n- and pFET in common gate and n/pconnection with vertical common contact werealso verified in addition to our previous report [1]. As a result, we believe that the most of key components
for ultimate cell height scaling of 3DSFET has been verified to continue the logic technology scaling beyond
1nm node.

11:05 AM
T1.3 A confined storage nitride 3D-NAND cell with WL airgap for cell-to-cell interference reduction
and improved program performances, Davide Resnati1, Gianpietro Carnevale1, Shyam Surthi1, Chris
Carlson1, Matthew Thorum1, Terry Kim1, Emilio Camerlenghi1, Richard Hill1 1Micron Technology, Inc.
We demonstrated a confined storage nitride (SN) 3D-NAND cell with an innovative process flow including
WL airgap formation. Airgaps strongly reduced WL parasitic capacitance which translates into better
program time (tprog) performances. A complete device characterization has been carried out on a test
memory array. We measured substantial cell-to-cell interference (C2C) improvements and lateral charge
loss (LCL) reduction, which make this cell a key enabler of further tier pitch (TP) scaling in future 3D-NAND
arrays. Program-erase (PE) window limitations due to trapped charge confinement were also addressedby TCAD modeling, showing that PE window can be recovered by SN film thickness changes with no C2C
penalty.
11:30 AM
T1.4 On the extreme scaling of transistors with monolayer MoS2 channel, Terry Y.T. Hung1, Wen-Chia
Wu1,2, D. Mahaveer Sathaiya1, Edward Chen1, Chen-Feng Hsu1, Walker Yun1, Hsiang-Chi Hu2, Bo-Heng Liu3,
T.Y. Lee1, Chi-Chung Kei3, Wen-Hao Chang2, Jin Cai1, Jeff Wu1, Chung-Cheng Wu1, H.-S. Philip Wong1, ChaoHsin Chien2, Chao-Ching Cheng1, Iuliana P. Radu1 1TSMC, 2NYCU, 3TIRI
2D transition metal dichalcogenides (TMDs) show promise for transistor scaling, but their on-scale
performance had not been proven yet. This work demonstrates contact length (LC) scaling while holding
a low contact resistance (RC) down to 11 nm. Channel length (LCH) scaling shows ION can increase down toat least 12 nm with low RC. The very scaled (LCH = 19 nm and LC = 12 nm) MoS2 transistor with Sb-based
metal contact has current density of ~1130 mA/mm at VDS = 1 V, and a low RC of ~190 Ω·mm. These scaledtransistors, processed within a back-end-of-line (BEOL) thermal budget, do not exhibit subthreshold swing(S.S.) degradation or observable drain-induced barrier lowering (DIBL) down to LCH = 12 nm.
11:55 AM
T1.5 First Demonstration of Fully Integrated 16 nm Half-Pitch Selector Only Memory (SOM) for
Emerging CXL Memory, Myoungsub Kim1, Yooncheol Bae1, Jaehyuk Park1, Jeongho Yeon1, Hyungjoon
Shim1, Sehyun Jin1, Hyunsoo Kim1, Sangchul Oh1, Gapsok Do1, Dongyeol Yun1, Hyung Dong Lee1, David
Ahn1, Junghun Lee1, Muhui Park2, Junghyuk Yoon2, Jeongho Yi2, Taekseung Kim2, Gain Park2, Seoungju
Chung2, Junho Cheon2, Sujin Chae1, Namkyun Park1, Kyunghoon Kim2, Dongyean Oh1, Jaeyun Yi1, Seonyong
Cha1 1R&D, SK hynix Inc., 2DRAM Development, SK hynix Inc.
In this study, understanding the switching mechanisms of selector only memory (SOM) led to
implementation of TCAD, and advanced materials and processes were developed based on the optimized
core circuit design and write-read scheme in the first fully integrated 16 nm half-pitch SOM for emerging
Compute Express Link™ (CXL) memory. We have achieved read window margin (RWM, 750 mV) including
product-level raw bit error rate (RBER) and reliability such as drift-related persistency, read disturbance(RDT), high temperature data retention (>10 years at 125 ℃) and cycle endurance (For median values,
read >109, write >108, and write >107 cycles for RBER 200 ppm).
Session C1: Wireline Circuits
10:15 AM, Honolulu 1
Co-Chairs:

Harold Pilo, Synopsys
Hisakatsu Yamaguchi, Fujitsu Ltd.

10:15 AM
C1.1 A 246-fJ/b 13.3-Tb/s/mm Single-Ended Current-Mode Transceiver with Crosstalk Cancellationfor Shield-Less Short-Reach Interconnect, Jaeho Lee1, Kyongsu Lee1, Jae-Yoon Sim1, Seon-Kyoo Lee1
1
POSTECHThis paper presents a 20-Gb/s/line current-mode transceiver for dense short-reach on-chip interconnect.
The transceiver achieves a systematic crosstalk cancellation by balancing the crosstalk induced bycapacitive and inductive coupling. The transceiver implemented in a 40nm CMOS technology shows anenergy efficiency of 246fJ/b and an edge bandwidth density of 13.3Tb/s/mm.
10:40 AM
C1.2 A 2 X 56 Gb/s Single-Ended Orthogonal PAM-7 Transceiver with Encoder-Based ChannelIndependent Crosstalk Cancellation in 28-nm CMOS, Xuxu Cheng1, Hongzhi Wu1, Liping Zhong1, Weitao
Wu1, Quan Pan1 1Southern University of Science and Technology
This paper presents a 2 × 56 Gb/s single-ended transceiver (TRX) with a channel-independent crosstalkcancellation scheme. The encoder-based crosstalk cancellation scheme (EB-XTC) encodes 2 uncorrelated
PAM-4 signals to a pair of orthogonal PAM-7 signals that eliminates strong crosstalk noise in the closely
coupled differential channel. The proposed TRX consists of an encoding transmitter (TX) that transmits
the orthogonal PAM-7 signal with crosstalk immunity, and a decoding receiver (RX) that recovers the PAM7 signal to PAM-4 signals. A tailless push-pull driver is proposed to enhance the linearity and signal-tonoise ratio (SNR) of the PAM-7 signal. The prototype chips are fabricated in 28-nm CMOS and achieve 56
Gb/s/pin with crosstalk immunity up to –2 dB and insertion loss compensation up to 35 dB. The overall
power efficiency is 1.8 pJ/b.
11:05 AM
C1.3 A 56-Gb/s 17-mW NRZ Receiver in 0.018 mm2, Kshitiz Tyagi1, Behzad Razavi1 1University ofCalifornia Los Angeles
An NRZ receiver incorporates new architecture and circuit techniques to achieve a low power and area
consumption. Realized in 28-nm CMOS technology, the full-rate RX operates at 56 Gb/s with a bit error
rate less than 10-12 for a channel loss of over 25 dB at 28 GHz.
11:30 AM
C1.4 A 200-Gb/s PAM-4 transmitter with 1.6-Vppd output swing and clock skew correction in 12-nm
FinFET, Boyang Zhang*1,2, Zhifei Wang*1,2, Zeze Feng1,2, Tianchen Ye1,2, Bingyi Ye1,2, Zixu Wang1,2, Weixin
Gai1,2
1Peking University, 2Beijing Advanced Innovation Center for Integrated Circuits
This work demonstrates a 200-Gb/s PAM-4 transmitter with 1.6-Vppd output swing in 12-nm FinFET
technology. Novel pulse generators are proposed to reduce jitter by two orders of magnitude. The
quadrature clock generator is capable of detecting and correcting three types of clock skews including
duty-cycle error, quadrature error, and differential error. The power efficiency of the transmitter is 3.32
pJ/bit and the active area is 0.116 mm2.
11:55 AM
C1.5 A 0.88pJ/bit 112Gb/s PAM4 Transmitter with 1Vppd Output Swing and 5-Tap Analog FFE in 7nm
FinFET CMOS, Zeynep Toprak Deniz1, Timothy O. Dickson1, Martin Cochet1, Jonathan Proesel2, John F.
Bulzacchelli1, Herschel Ainspan1, Matthias Braendli1, Thomas Morf1, Michael Beakes1, Mounir Meghelli1
1
IBM Reserach, 2Nubis Communications
A 0.88pJ/bit 112Gb/s PAM4 transmitter is reported in 7nm FinFET CMOS with 1Vppd output amplitude. The
quarter-rate TX architecture implements a 5-tap analog FFE using tap extension circuitry, which permitshigher FFE tap count than conventional quarter-rate architectures without requiring complex clocking. A
key feature of the FFE construction is the use of fully re-assignable CML driver segments among FFE taps,
which allows a reduced number of segments for lower capacitance and higher driver bandwidth.
Session C2: Power at High Voltage and Current
10:15 AM, Honolulu 2
Co-Chairs:

Stephen Brink, Texas Instruments
Shuichi Nagai, Panasonic Industry Co., LTD

10:15 AM
C2.1 A Monolithic Low-ILEAK Cross-Coupled GaN Driver with ∆Φ-Reduced EMI-Rejecter for21.51dBµV-EMI-Reduction and 1/10x filter-capacitor, Shi-Jun Zeng1, Hsing-Yen Tsai1, Yu-Teng Liang1, KeHorng Chen1, Kuo-Lin Zheng2, Chih-Chen Li3 1EE, National Yang Ming Chiao Tung University, 2Chip-GaN
Power Semiconductor Corporation, 3MediaTek, Hsinchu, Taiwan
The proposed ΔΦ-reduced EMI rejecter reduces the EMI amplitude of 21.51dBμV, passes CISPR25
specification, and reduces the filter capacitor by 1/10 times, thereby reducing the PCB size. The peakefficiency is 94.5%. In a 400V-to-48V conversion, the output power is 240W (=48V*5A) and meets the USB
PD 3.1 standard.
10:40 AM
C2.2 A Monolithic GaN-based Gate Driver for LLC-SRC with Three-Phase Startup Clamping Achieving
23.2µA IQ and 98.6% Peak Efficiency, Chi-Yu Chen1, Tz-Wun Wang1, Po-Jui Chiu1, Sheng-Hsi Hung1, ChangLin Go1, Xiao-Quan Wu1, Yu-Ting Huang1, Ke-Horng Chen1, Kuo-Lin Zheng2, Ying-Hsi Lin3, Shian-Ru Lin3,
Tsung-Yen Tsai3 1EE, National Yang Ming Chiao Tung University, 2Chip-GaN Power Semiconductor
Corporation, 3Realtek Semiconductor
To meet Energy Star and 80 Plus Titanium standards, the hybrid gate driver reduces the quiescentcurrent to 23.2μA by reducing GaN leakage current. The auto-precharge technique can reduce the leakage
current from a few milliamperes to 60.4μA, resulting in an efficiency greater than 92% at the entire output
load.
11:05 AM
C2.3 A Fully Integrated 48-V GaN Driver Using Parallel-Multistep-Series Reconfigurable SwitchedCapacitor Bank Achieving 7.7nC/mm2 On-Chip Bootstrap Driving Density, Xuchu Mu1, Yang Jiang1, Rui
Martins1, Pui-In Mak1 1University of Macau
This work presents a fully integrated switched-capacitor (SC) floating-domain gate driver with enhanced
driving capability and reduced charge-sharing loss. The proposed driver employs a reconfigurable SC bank
(RSCB) to achieve multistep gate driving and minimized bootstrapping capacitance (CBST) area cost. An
autonomous switching control determines the reconfiguration of the proposed RSCB by comparing thesensed gate-to-source transient voltage with a triggering level. Fabricated using a 180-nm SOI BCD
process, the prototype supports a switching frequency of up to 6MHz and a 48V input for a half-bridge
GaN testbench, occupying only 0.048mm2 of on-chip bootstrap capacitance. The measured delivered gatecharge over the CBST area reaches up to 7.7nC/mm2, making a 38-fold improvement over conventional
techniques, also achieving a 16.2 times reduction in the required CBST area compared to prior designs
when driving the same power devices.
11:30 AM

C2.4 A ±100A Auto-Calibration Current Sensor with 80V Pulse-Width Modulation Attenuation and
0.15% Gain Error, Yu-Teng Liang1, Shi-Jun Zeng1, Yu-Tse Shih1, Ke-Horng Chen1, Kuo-Lin Zheng2, ChihChen Li3 1EE, National Yang Ming Chiao Tung University, 2Chip-GaN Power Semiconductor
Corporation, 3MediaTek, Hsinchu, Taiwan
The proposed in-line current sensor uses a 0.1mΩ sense resistor to achieve high efficiency.It can withstandinput voltages up to 80V through a high-voltage chopper and handle large common-mode transients(20V/ns) through enhanced pulse-width-modulation attenuation stage. The gain error is reduced to within±0.15%. Input noise density reduces to 12nV/√Hz.
11:55 AM
C2.5 A 12V-to-1V 100A Inverted Pyramid Trans-Inductor Voltage Regulator Converter with 93.6%
High Efficiency and Fast Transient Response, Yu-Chen Kuo1, Ke-Horng Chen1, Hong-Teng Wu1, Guan-Ye
Chen1, Kuo-Lin Zheng2, Chih-Chen Li3 1EE, National Yang Ming Chiao Tung University, 2Chip-GaN Power
Semiconductor Corporation, 3MediaTek, Hsinchu, Taiwan
This paper proposes an inverted pyramid trans-inductor voltage regulator converter that can offer
significant benefits, including extended duty cycle, reduced power loss, and lower voltage stress. It
achieves a peak efficiency of 93.6%, a maximum output current of 100A, and attains an 8μs recovery time
for a 90A/1μs load transition.
Session C3: AI/ML Accelerators and CiM
10:15 AM, Honolulu 3
Co-Chairs:

Jaydeep Kulkarni, University of Texas at Austin
Masanao Yamaoka, Hitachi, Ltd.

10:15 AMC3.1
122.7 TOPS/W Stdcell-Based DNN Accelerator Based on Transition Density Data
Representation, Clock-Less MAC Operation, Pseudo-Sparsity Exploitation in 40 nm, Animesh Gupta1,
Japesh Vohra1, Viveka Konandur Rajanna1, Massimo Alioto1 1National University of Singapore
A DNN whose activation magnitude is represented by digital transition density is introduced for low
energy, under the proposed Dyadic Digital Transition Modulation (DDTM). MAC operations are simplified
into transition counting, enabling 1) activation pseudo-sparsity for lower energy, 2) clock-less neuron
operation via simple up-down asynchronous counters. >100 TOPS/W in 40 nm stdcell design is on par withrecent in-memory DNNs.
10:40 AM
C3.2 FSNAP: An Ultra-Energy-Efficient Few-Spikes-Neuron based Reconfigurable SNN Processor
Enabling Unified On-Chip Learning and Accuracy-Driven Adaptive Time-Window Tuning, Ruixin Mao1,
Lin Tang1, Zihan Xia1, Zhaomin Zhang1, Aoyu Shen1, Yu Long1, Jinhong Guo2, Yunpeng He3, Lai Zhang3,
Shujuan Wang3, Liang Zhou1, Liang Chang1, Shanshan Liu1, Jun Zhou1 1University of Electronic Science andTechnology of China, 2Shanghai Jiao Tong University, 3Chipintelli Technology Co., Ltd
This paper presents an ultra-energy-efficient few-spikes-neuron (FSN) based reconfigurable spiking neuralnetwork (SNN) processor enabling unified on-chip learning and accuracy-driven adaptive time-windowtuning. Fabricated in 55nm CMOS process, the proposed design outperforms state-of-the-art designs inaccuracy, energy efficiency (up to ×84) and speedup (up to ×740) for same or similar application tasks.
11:05 AM
C3.3 ETCIM: An Error-Tolerant Digital-CIM Processor with Redundancy-Free Repair and Run-Time
MAC and Cell Error Correction, Yiqi Wang1, Zhen He1, Chenggang Zhao1, Zihan Wu1, Mingyu Gao1, HuimingHan1, Shaojun Wei1, Yang Hu1, Fengbin Tu2, Shouyi Yin1 1Tsinghua University, 2The Hong Kong Universityof Science and Technology
This work presents an Error-Tolerant digital Computing-in-Memory (CIM) processor ETCIM. It has three
key features to solve the hard error correction overhead, soft error correction incompatibility and latency
problem of traditional methods on digital CIM: 1) A Fault-Adaptive CIM Initializer (FACI) and input feeder
reduce the hard error repair overhead by up to 8.47x power and 18.16x area savings. 2) A Block-wise ECC(BW-ECC) CIM suits digital CIM’s structure and corrects soft multiply-accumulation (MAC) errors; 3) A
Progressive Cell Error Corrector (PCEC) hides soft cell error correction latency during computation,
reducing the total latency by up to 96.8%.
11:30 AM
C3.4 A 28nm 4170-TFLOPS/W/b and 195-TFLOPS/mm2/b Multiply-Free Fully-Digital Floating-Point
Compute-In-Memory Macro with Mitchell's Approximation, Ruiqi Guo1, Xiaofeng Chen1, Lei Wang1,
Fengbin Tu2, Shaojun Wei1, Yang Hu1, Shouyi Yin1 1Tsinghua University, 2Hong Kong University of Scienceand Technology
This work presents a SRAM-based digital-domain compute-in-memory (DCIM) macro with threecontributions: 1) A floating-point DCIM structure to convert bit-serial multiplication into bit-parallel
addition by Mitchell Approximate Multiply (MAM); 2) A Mitchell MAC unit with optimized full-adder,
adder-tree and 2’s complement unit to achieve higher area efficiency; 3) A DCIM bank with latches to save
dynamic power by exploiting sparse MAM results. The fabricated 28-nm DCIM achieves 65.15 TFLOPS/W
energy efficiency and 3.04 TFLOPS/mm2 area efficiency for BF16; it is 4170TFLOPS/W/b,
195TFLOPS/mm2/b, normalized per bit.
11:55 AM
C3.5 A 278-514M Event/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for
Event Camera, Jiyue Yang1, Alexander Graening1, Wojciech Romaszkan1, Vinod Kurian Jacob1, Puneet
Gupta1, Sudhakar Pamarti1 1University of California, Los Angeles
We present a Compute-In-Memory (CIM) convolution accelerator for object tracking applications using
event camera, which is a new imaging technology that significantly improves latency and dynamic range
over conventional cameras. Previous works proposed an efficient ADC-less Stochastic CIM for deeplearning but need to store 2N stochastic bits for an n-bit number. We propose to store binary numbers inmemory and convert them to stochastic bits by in-situ Stochastic Number Generators on the fly, which
reduce the storage requirement by >10x. The CIM macro embeds 32 tiny MAC units per weight and uses
an early termination technique to skip unnecessary computation of zeros. The accelerator achieves energy
efficiency of 485 TOPS/W and throughput of 278-514 Mevent/s. The proposed SCIM macro can also be
used to accelerate convolution in most deep learning applications.
Session T2: Non-Volatile Memory Technology - Hafnia Based Ferroelectrics-1
1:30 PM, Tapa 1
Co-Chairs:

Elisa Vianello, CEA-Leti
Deoksin Kil, SK hynix Inc.

1:30 PMT2.1 HZO-based Nonvolatile SRAM Array with 100% Bit Recall Yield and Sufficient Retention Time at
85 &[deg]C, Yusuke Shuto1, Jun Okuno1, Tsubasa Yonai1, Ryo Ono1, Peter Reinig2, Maximilian Lederer2,
Konrad Seidel2, Ruben Alcala3, Thomas Mikolajick3,4, Uwe Schroeder3, Taku Umebayashi1, Kentaro
Akiyama1 1Sony Semiconductor Solutions Corp., 2Fraunhofer IPMS, 3NaMLab gGmbH, 4TU DresdenFor the first time, a 16-Kbit nonvolatile SRAM (NVSRAM) array based on a metal/ferroelectric/metal
capacitor using a sub-10-nm-thick HfZrOx (HZO) layer has been experimentally demonstrated to obtain
100% bit yield. This capacitor is formed using the same integration process as that of a previously
developed ferroelectric random-access memory (FeRAM) array on the same wafer. Its sequential
operations of nonvolatile data store (Store), cutoff of power supply (power-gating: PG), and data recall(Recall) are completely executed employing a robust Recall sequence, achieving 100%-bit recall after a
200-s PG period at 85 °C even with sufficiently low operation voltage. The results indicate that our HZObased NVSRAM and FeRAM hybrid memory system can provide ultra-low power advantages in a Systemon-Chip for Internet of Things edge computing.
1:55 PMT2.2 Polar axis orientation control of hafnium-based ferroelectric capacitors with in-situ AC electricbias during rapid thermal annealing, Zhaomeng Gao1, Tianjiao Xin1,2, Kai Du3, Qiwendong Zhao1, Yiwei
Wang1, Cheng Liu1, Yilin Xu1, Rui Wang1, Guangjie Shi1, Yunzhe Zheng1, Yonghui Zheng1,4, Yan Cheng1,2,4,
Hangbing
Lyu3,51
2
East China Normal University, Shanghai Institute of Microsystem and Information Technology(CAS), 3Huawei Technologies Co., 4Hualu Technologies Co., 5Institute of Microelectronics (CAS)Hafnium-based ferroelectric (FE) thin films, prepared via atomic layer deposition (ALD), suffered fromrandom oriented polar axis (PA), posing challenges and complexities for device scaling and variation. To
effectively control the PA orientation and enhance polarization, we employed in-situ AC electric bias (E)during rapid thermal annealing (RTA) treatment (i.e. RTA+E). The main findings are as follows: (1) The PAof the FE phase is stochastic formed during RTA cooling stage from tetragonal (T-) to orthogonal (O-)
transition; (2) Applying E during cooling significantly enhances polarization in hafnium-based FE capacitors
up to ~121.6% increase; (3) The RTA+E method effectively controls the O-PA orientation towards the outof-plane E direction. These findings solidly demonstrate that the PA orientation of O-grain can becontrolled in fluorite-type FE thin films.
2:20 PMT2.3 In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND
Beyond 1K Layers: Experimental Demonstration and Modeling, Giuk Kim1, Hyojun Choi1, Hunbeom Shin1,
Sangho Lee1, Sangmok Lee1, Yunseok Nam1, Minhyun Jung1, Ilho Myeong2, Kijoon Kim2, Suhwan Lim2,
Kwangsoo Kim2, Wanki Kim2, Daewon Ha2, Jinho Ahn3, Sanghun Jeon1 1KAIST, 2Samsung
Electronics, 3Hanyang University
In this work, we experimentally demonstrate a remarkable performance improvement, boosted by theinteraction of charge trapping & ferroelectric (FE) switching effects in metal-band engineered gateinterlayer (BE-G.IL)-FE-channel interlayer (Ch.IL)-Si (MIFIS) FeFET. The MIFIS with BE-G.IL (BE-MIFIS)
facilitates the maximized ‘positive feedback’ (Posi. FB.) of dual effects, leading to low operation voltage(VPGM/VERS: +17/-15 V), a wide memory window (MW: 10.5 V) and negligible disturb at a biased voltage of
9 V. Furthermore, our proposed model verifies that the performance enhancement of the BE-MIFIS FeFET
is attributed to the intensified posi. FB. This work proves that the hafnia FE can play as a key enabler in
extending the technology development of 3D VNAND, which is currently approaching a state ofstagnation.
2:45 PM
T2.4
Unveiling Cryogenic Performance (4 to 300 K) towards Ultra-thin Ferroelectric HZO: Novel
Kinetic Barrier Engineering and Underlying Mechanism, Dong Zhang1, Yang Feng1,2, Zijie Zheng1, Chen
Sun1, Qiwen Kong1, Gan Liu1, Zuopu Zhou1, Jixuan Wu2, Jiezhi Chen2, Xiao Gong1 1Department of Electricaland Computer Engineering, National University of Singapore (NUS), 117576, Singapore, 2School ofInformation Science and Engineering, Shandong University, 266237 Qingdao, China
We perform comprehensive and in-depth investigation into the cryogenic characteristics of FE HZO thinfilms with varying thicknesses (3/5/7/10 nm) across a temperature range (4~300 K), assisted by firstprinciple calculations as well as extensive material and electrical characterizations. We propose andexperimentally demonstrated, for the first time, an innovative cryogenic barrier engineering
approach for Pr enhancement, particularly valuable for ultra-thin HZO films.
Session JFS1: RF, mmWave, and THz Technologies
1:30 PM, Tapa 2
Co-Chairs:

Vanessa Chen, Carnegie Mellon University
Rihito Kuroda, Tohoku University

1:30 PM
JFS1.1 First Radio-Frequency Circuits fabricated in top-tier of a full 3D Sequential Integration Process
at mmW for 5G applications, Jose Lugo-Alvarez1, Jean-Baptiste David1, Alexandre Siligaris1, Vincent
Puyal1, Guillaume Moritz1, Tadeu Mota-Frutuoso1, Valerie Lapras1, Claire Fenouillet-beranger1, Laurent
Brunet1, Pierre Vincent1, Didier Lattard1, Xavier Garros1, Francois Andrieu1, Perrine Batude1 1CEA-LetiThis work describes for the first time, RFIC stacked at the top-tier of a 3D sequential integration. The
analog silicon RF circuits, sequentially fabricated at 500°C above a digital circuit layer with 28nm FDSOI
industrial platform, present performance in line with standard thermal budget FDSOI devices. Thanks tothis advanced 3DSI stack, top-tier VCO and LNA functional demonstrators are designed in the 30 GHz
band. Additionally, a signal integrity study is carried out using a ring oscillator aggressor, integrated onbottom-tier below the VCO core, highlighting the interoperability of an aggressive vertical co-integration
between fast digital and RF blocks. This work provides insights into the crosstalk issue arising from theultra-thin distance between tiers, a characteristic feature of 3DSI.
1:55 PM
JFS1.2 A 140-Gbps 1-to-21GHz Ultra-Wideband LNA Achieving 1.95-to-3dB NF Using Gm-AssistedFeedback Noise Suppression Technique in 40nm Bulk CMOS, Sicheng Han1, Yun Wang1, Yunhao Li1, Wen
Zuo1, Wei Li1, Yue Lin2, Hongtao Xu1 1Fudan University, 2ICLegend MicroThis paper presents an ultra-wideband low-noise amplifier (LNA) with gm-assisted-feedback noise
suppression technique for ultra-wideband RF front-end. Compared to the traditional resistive feedback
wideband LNAs, the proposed LNA blocks the noise current from the feedback resistor with a simple
additional gm-cell, thus achieving a lower overall NF. A source coupling transformer is also utilized tomaintain a wideband flat gain. Fabricated in a 40-nm bulk CMOS process, the LNA prototype achieves ameasured bandwidth of 1-to-21-GHz, NF of 1.95-to-3-dB, S21 of 20.6-to-22.4-dB, while consuming 21.6
mA from a 1.2 V power supply. It reports the lowest and the flattest NF among the recent-published bulk
CMOS ultra-wideband LNAs, it also supports ultra-wideband modulation signal with a date rate of 140
Gbps.
2:20 PM
JFS1.3 First Heterogeneous and Monolithic 3D (HM3D) Integration of InGaAs HEMTs and InP/InGaAs
DHBTs on Si CMOS for Next-Generation Wireless Communication, Nahyun Rheem1, Jaeyong Jeong1,
Yoonje Suh1, Chanjik Lee1, Bong Ho Kim1, Joon Pyo Kim1, Seong Kwang Kim1,2, Hyeong-Rak Lim1, Jongmin
Kim3, Dae-Hwan Ahn4, Jae-Hoon Han4, Jongwon Lee5, Sanghyeon Kim1 1KAIST, 2Semiconductor R&D
Center, Samsung Electronics, Co. Ltd, 3KANC, 4KIST, 5Chungnam National University

Heterogeneous and monolithic 3D (HM3D) integration of III-V and Si CMOS technologies enables highfrequency, multifunctionality, and power-efficient RF systems for nextgeneration wireless communicationsuch as 6G and beyond. In this work, for the first time, we demonstrate HM3D integration of InGaAs
HEMTs (for LNAs) and InP/InGaAs DHBTs (for PAs) on Si CMOS by direct wafer bonding. The top InGaAs
HEMTs exhibit fT and fMAX of 354 GHz and 611 GHz with a high gm of 1.5 S/mm. Concurrently, the top
InP/InGaAs DHBTs show fT and fMAX of 129 GHz and 47 GHz with a DC gain of 29 and a breakdown voltageof 5.9V. Notably, these results are obtained without any degradation of the bottom Si CMOS. This
innovative HM3D integration, combining III-V technologies for PAs and LNAs with Si CMOS technology foranalog/digital functionalities will play an essential role in next-generation wireless communication
systems.
2:45 PM
JFS1.4 Terahertz Sensing with CMOS-RFIC - Feasibility Verification for Short-Range Imaging using
300GHz MIMO Radar (Invited), Ichiro Somada1, Akihito Hirai1, Akinori Taira1, Keigo Nakatani1, Kazuaki
Ishioka1, Takuma Nishimura1, Koji Yamanaka1 1Mitsubishi Electric Corp.
For solving various social issues, sensing technology has gained significant interest. Terahertz waves,which combine the high resolution of light and transparency of radio waves, enable visualization of
obstacles behind internal structures. So, it offers potential for new solutions. This paper introduces
the overview of a short-distance sensing system based on the full digital MIMO radar concept, the design
and fundamental evaluation results of 300GHz terahertz CMOS devices, as well as the achievements ofimaging using 300GHz terahertz wave based on actual measurements. Since the terahertz band can obtainan ultra-wideband spectrum, several milli-meter resolution imaging can be performed in azimuth,
elevation, and depth direction. We show the feasibility of the security gate application with the measured
high-resolution tomographic images.
Session JFS2: Processors & Compute
1:30 PM, Tapa 3
Co-Chairs:

Yan Li, Western Digital
Noriyuki Miura, Osaka University

1:30 PM
JFS2.1 CogniVision: End-to-End SoC for Always-on Smart Vision with mW Power in 40nm, Animesh
Gupta1,1, Japesh Vohra1, Massimo Alioto1 1National University of Singapore
A full vision system on chip with hierarchical execution from sensor to AI and communications ispresented. Always-on system power is aggressively reduced to the mW level through activity reduction,
gating any subsequent vision pipeline stage starting from the lowest semantic level of the scene. The
system comprises an imager with dual-architecture in/near-sensor saliency detection, on-the-fly novelty
detection, DNN with on-chip scheduler for weight memory reduction, WiFi transmitter, wake-up receiverfor cloud-pushed DNN model update and software programmable orchestration via RISC-V. Average 2.1mW power at 30 fps is achieved with a SqueezeNet V1.0 model running entirely on chip.
1:55 PM
JFS2.2 NeRF-Navi: A 93.6-202.9µJ/task Switchable Approximate-Accurate NeRF Path Planning
Processor with Dual Attention Engine and Outlier Bit-Offloading Core, Seryeong Kim1, Seokchan Song1,
Wonhoon Park1, Junha Ryu1, Sangyeob Kim1, Gwangtae Park1, Soyeon Kim1, Hoi-Jun Yoo11KAISTA Neural Radiance Field-based Path Planning (NeRF-PP) processor (NeRF-Navi) is proposed for fast andenergy-efficient 3D navigation with 3 key features: 1) Dual Attention Neural Path Planning (DANP) engine

for fast and energy-efficient NeRF-PP acceleration, 2) Approximate-Accurate (A2) core with error
compensation reduction tree (ECRT) and bit sparsity boosting logic (BSBL) for low power computation, 3)
Outlier Channel Bit Offloading Core (OCBOC) for throughput enhancement. NeRF-Navi is fabricated in a
28nm CMOS process and evaluated in the 3D real-world map. As a result, NeRF-Navi successfully
demonstrates real-time NeRF-PP on edge devices consuming only 93.6-202.9 μJ/task with 0.57-1.39 ms
latency at 0.9V and 200MHz.
2:20 PM
JFS2.3 A Quad-Core AI Processing Unit for Generative AI in 4nm 5G Smartphone SoC (Invited), ChienHung Lin1, Jeng-Yun Hsu1, Cheng-Ying Yu1, Chia-Wei Hsu1, Yi-Min Tsai1, Kuo-Sheng Wu1, Chung-Lun Huang1,
Meng-Han Hsieh1, Tsung-Yao Lin1 1MediaTek Inc.
This work presents the quad-core AI processing unit (APU) for efficient execution of generative artificial
intelligence (GenAI) applications on smartphones. GenAI applications featured with billions ofcomputations and memory accesses are out of tune with smartphone platforms. The APU applies mixedprecision and hybrid-precision operations, inter-core direct data link, zero-overhead layer fusion, and databroadcasting to reduce 50% of dram footprint and 90% of dram BW. The 4nm 5G smartphone poweredby the APU takes less than 1 second to generate an image with optimized stable diffusion (SD) and outputs
more than 20 tokens per second with 7B speculative large language model (LLM).
2:45 PM
JFS2.4 AMD Instinct MI300X Accelerator: Packaging and Architecture Co-Optimization (Invited), Alan
Smith1, Gabriel Loh1, John Wuu1, Samuel Naffziger1, Tyrone Huang1, Hugh McIntyre1, Ramon Mangaser1,
Wonjun Jung1, Raja Swaminathan1 1AMD
The AMD Instinct™ MI300X accelerator utilizes multiple advanced packaging technologies for aheterogeneous integration solution for emerging AI/ML and HPC workloads. These include microbump 3D
memory stacks, 2.5D silicon interposers, and 3D hybrid bonding. The combination of these advanced
packaging technologies enabled architectural innovations and generational performance uplifts thatcannot be achieved with traditional technologies and Moore’s Law scaling A modular 3D chiplet design
also enables reuse of the MI300X components to enable the MI300A APU.
Session C4: Biomedical Stimulation and Imaging
1:30 PM, Honolulu 1
Co-Chairs:

Carolina Mora Lopez, imec
Kenichi Matsunaga, NTT Corporation

1:30 PMC4.1 A Wireless Neurostimulator using Body-Coupled Link for Multisite Stimulation in Freely
Behaving Animals, Taejune Jeon1, Byeongseol Kim2, Changuk Lee3, Danbi Ahn4, Daerl Park1, Jaesuk Sung5,
Hee Young Kim6, Heon-Jin Choi1,5, Joonsung Bae2, Youngcheol Chae1 1Yonsei University, 2Kangwon
National University, 3University of California, 4Daegu Haany University, 5NFormare, 6Yonsei University
College of Medicine
This paper presents a wireless neurostimulators for multisite stimulation in freely behaving animals. The
neurostimulator IC is wirelessly powered via a 16MHz body-coupled link, and controlled by forward
telemetry, which provides stimulation parameters via amplitude shift keying (ASK) modulation. It can
provide various stimulation protocols with a maximum current of 225μA, achieving the highest end-to-end efficiency of 1.72% at a TX/RX distance of 10cm. Moreover, multisite stimulation is fully validated
through in vivo experiments.
1:55 PMC4.2 A Current-Source-Free Constant-Current Wireless Adiabatic Neural Stimulator Achieving a 5.527.7x Improved RF-to-Electrode Stimulation Efficiency Factor, Siddharth Agarwal1, Gael Pillonnet2,
Hongyu Lu1, Nader Sherif Kassem Fathy1, Patrick P. Mercier1 1University of California, San Diego, La Jolla,CA, 2Univ. Grenoble Alpes, CEA, Leti, Grenoble
This paper presents a wireless neurostimulator that combines the features of rectification, regulation,
voltage boosting, and current generation into a single inductor-less power stage, which eliminates bothcascaded losses and current source losses while enabling direct adiabatic driving of a wide range ofelectrode impedances (80nF-to-2μF + 10Ω-to-2kΩ). The stimulator replenishes 99.5% of the energy stored
in the inherent electrode capacitance and balances pre-shorting residual charge to under 0.5% (0.6nC) for
50μA-to-2mA stimulation currents. It achieves an RF-to-Electrode Stimulation Efficiency Factor (SEFRF-toElectrode) of 11.1, which exceeds prior art by 5.5-27.7x.
2:20 PMC4.3 A 5.7kfps Fast Neural Electrical Impedance Tomography IC Based on Incremental Zoom
Structure with Baseline Cancellation for Peripheral Nerve Monitoring Systems, Ji-Hoon Suh1, Haidam
Choi1, Yoontae Jung1, Sohmyung Ha2, Minkyu Je1 1KAIST, 2New York University Abu Dhabi
Fast electrical impedance tomography (EIT) can localize and record neural activities of peripheral nerves
in real time, but prior EIT systems do not support high enough frame rate (<500fps) to catch neuralactivities. Towards the real-time neural EIT, we propose a power- and hardware-efficient EIT system basedon baseline-cancelling incremental zoom structure with 47μW and 0.055mm2/ch, and a novel image
update scheme, focused refresh, boosting the frame rate to 5.7kfps.
2:45 PMC4.4 A Fully Dynamic 1st-Order 1st-Order Δ-ΔΣ Modulator with a 468mVInput Range for Electrical
Impedance Tomography Systems, Haidam Choi1, Gichan Yun1, Ji-Hoon Suh1, Sein Oh1, Song-I Cheon1,
Yoontae Jung1, Sohmyung Ha2, Minkyu Je1 1KAIST, 2New York University Abu Dhabi
This paper presents an imaging IC with readout front-ends (RFEs) based on a 1st-order Δ-ΔΣ modulator (ΔΔΣM) for electrical-impedance-tomography (EIT) systems. This allows the utilization of the readout datafrom all the electrodes, including even the current-injecting electrodes, without saturation, thus achieving
much higher imaging contrast. The proposed EIT system achieves an input range of 468 mVpp,
corresponding to 1.56 kΩ when using a maximum current of 150 μA.
Session C5: Analog Techniques
1:30 PM, Honolulu 2
Co-Chairs:

Axel Thomsen, Cirrus Logic
Chun Shiah, Etron Technology

1:30 PMC5.1 A 15.4ppm/ºC GaN-based Voltage Reference with Process-Variation-Immunity and High PSR for
EV Power Systems, Po-Jui Chiu1, Tz-Wun Wang1, Chi-Yu Chen1, Sheng-Hsi Hung1, Yu-Ting Huang1, XiaoQuan Wu1, Ke-Horng Chen1, Kuo-Lin Zheng2, Chih-Chen Li3 1EE, National Yang Ming Chiao Tung
University, 2Chip-GaN Power Semiconductor Corporation, 3MediaTek, Hsinchu, Taiwan

The proposed GaN-based voltage reference generator has a low temperature coefficient (TC) of
15.4ppm/°C, a small deviation of VREF at different process corners with a standard deviation of 0.22%, agreat line sensitivity of 0.0023%/V, and a great power-supply rejection (PSR) of -187dB and -114dB at
100Hz and 50MHz, and10.9μW.
1:55 PMC5.2 A 97.3dB SNR Bioimpedance AFE with -84dB THD Segmented-ΔΣM Sinusoidal Current Generator
and Passing-Through Instrumentation Amplifier, Qinjing Pan1, Qi Luo1, Tianxiang Qu1, Liheng Liu1, Xiao
Li2, Min Chen2, Zhiliang Hong1, Jiawei Xu1 1Fudan University, Shanghai, China, 2CHIPSEA, Shenzhen, China
This paper presents a high-precision bioimpedance (BioZ) analog front-end (AFE) to detect changes intissue electrical properties as prognostic indicators for heart failure, cancer, and chronic pulmonary
disease. To increase the BioZ measurement accuracy, a low-distortion sinusoidal current generator (CG)is proposed. It utilizes a lookup table (LUT) with segmented delta-sigma modulator (ΔΣM) for efficient bits
extension of the IDAC, and a current amplifier (CA) to isolate the IDAC from dynamic load (e.g., BioZ,
electrode impedance, and parasitic capacitors) without nonlinearity penalty. The BioZ readout proposesa pass-through IA (PT-IA) to optimize the noise performance for large and complex BioZ. Manufactured ina 0.18μm CMOS process, the overall AFE, including the CG and readout, achieves -84dB THD, 97.3dB SNR(BW=4Hz), and 0.57mΩ/√Hz sensitivity at 1Hz, while the CG and readout consume 86.7-196.5μW and54.8μW, respectively. Impedance cardiography (ICG) has been successfully demonstrated with dryelectrodes.
2:20 PMC5.3 A 5.8W, 0.00086% THD+N, 118dB PSRR Class-D Audio Amplifier with Passive Output CommonMode Compensation Technique for Wide Output Power Range, Inhwan Cho1, Moo-Yeol Choi1, Jaehyeok
Byun1, Ji-Hun Lee1, Myungjin Lee1, Dongsu Kim1, Jongwoo Lee1 1Samsung Electronics
This paper presents a Class-D audio amplifier (CDA) with a passive output common-mode compensation(POCMC) technique for high linearity over a wide output power range. Moreover, a complementary triwave common-mode feedback (CTRI-CMFB) is also proposed to improve PSRR. The CDA achieves
0.00086% THD+N, 118dB PSRR, and a maximum output power of 5.8W (THD+N=1%) with an efficiency of
93.2% on an 8Ω load. The chip was fabricated in a 0.13μm BCD process and occupies an active area of
1.46mm2.
2:45 PMC5.4 Current Mirrors with Tapered Stacked-Gates for Area Saving or Noise Improvement in 3nm
FinFET Process, Chu-En Hsia1, Yung-Shun Chen1, Chin-Ho Chang1, Benny Lai1, Ching Lin Jen1, Yung-Chow
Peng1, Victor Li1 1Taiwan Semiconductor Manufacturing Company
A tapered stacked-gates device offers the advantages of saving area and reducing noise and mismatch,and it is universally applicable to many circuits. The proposed current-mirror design in bandgap reference(BGR) and current control oscillator (ICO) circuits use tapered stacked-gates for current mirror. Different
numbers of transistors are used in the stacked stages, which reduces the number of source-side
transistors and results in a 24% area reduction while maintaining the same mismatch and noise
performance according to experimental result. In addition, using the same number of devices, this design
can achieve better performance with almost 45% noise and 28% mismatch reduction in simulation.
Overall, this non-formal stacked-gates transistor circuit design shows promising potential for analog
circuit applications.
Session C6: SPAD Sensors
1:30 PM, Honolulu 3

Co-Chairs:

Bruce Rae, STMicroelectronics
Tomohiro Takahashi, Sony Semiconductor

1:30 PMC6.1 3D-Stacked 1Megapixel Time-Gated SPAD Image Sensor with 2D Interactive Gating Network for
Image Alignment-Free Sensor Fusion, Kazuhiro Morimoto1, Naoki Isoda1, Hiroshi Sekine1, Tomoya
Sasago1, Yu Maehashi1, Satoru Mikajiri1, Kenzo Tojima1, Mahito Shinohara1, Ayman Tarek Abdelghafar1,
Hiroyuki Tsuchiya1, Kazuma Inoue1, Satoshi Omodani1, Kazuma Chida1, Alice Ehara1, Junji Iwata1, Tetsuya
Itano1, Yasushi Matsuno1, Katsuhito Sakurai1, Takeshi Ichikawa1 1Canon Inc.
We present a 5μm-pitch, 3D-BSI 1Mpixel time-gated SPAD image sensor with 2D interactive gating
network, enabling image alignment-free sensor fusion. The SPAD image sensor operates at 1,310fps for
global shutter 2D imaging, and event vision sensing with 0.76ms temporal resolution under 0.02lux.
Range-gated imaging result demonstrates a feasibility of robust imaging under harsh environments. The
proposed gating network architecture enables background suppression in 3D depth measurement under
50klux ambient light.
1:55 PMC6.2 A 512 x 512 SPAD Laser Speckle Autocorrelation Imager in Stacked 65/40nm CMOS, Robert K.
Henderson1, Francesco Mattioli Della Rocca1,2, Edbert J. Sie3, Ahmet T. Erdogan1, Lars Fisher1, Andrew B
Matheson1, Neil Finlayson1, Alistair Gorman1, Istvan Gyongy1, Hanning Mai1,2, Thierry Lachaud4, Russell
Forsyth4, Francesco Marsili3 1University of Edinburgh, 2now with Sony Europe Technology Centre, 3Meta
Platforms Inc., 4STMicroelectronics
We present a single-photon avalanche diode (SPAD) autocorrelation imager implemented in 65/40nm 3Dstacked CMOS for laser speckle blood flow monitoring. The shared per-pixel SRAM architecture provides
a compact 41.68 mm pitch 128x128 resolution parallel autocorrelation function operating at 0.5T Op/s
and a lag-time of 1ms. SNR gains due to high BSI SPAD NIR sensitivity and on-chip averaging extends
source-detector separation to 40 mm indicative of the sensitivity required to discriminate extracerebral
artifacts from deep-tissue blood flow in future wearable neuromonitoring systems.
2:20 PMC6.3 A Digital Dynamic Vision Sensor with SPAD pixels and Multi-Event Generation for
Motion/Vibration-Adaptive Detection, Houk Lee*1, Jinpyo Han*1, Junhee Cho2, Heesung Lee2, Seong-Jin
Kim3, Jung-Hoon Chun1,2, Jaehyuk Choi1,2 1Sungkyunkwan University, 2SolidVue, 3UNISTThis paper introduces a digital dynamic vision sensor (DVS) with single-photon avalanche diode (SPAD).
The sensor operates in a fully digital manner, eliminating circuit noise and non-uniformity. To provide amotion-adaptive optimum frame rate and minimize vibration-event noise (VEN) caused by sensor
vibrations, the sensor generates multiple events via quantized delta (QD) signal. Thanks to the QD, thesensor detects the relative speed of moving objects, adjust the frame rate accordingly, and filter out VEN,
thereby allowing only essential events from the objects. Furthermore, the sensor incorporates eventdriven threshold control (EDTC) logic to ensure the optimal number of events. The EDTC and VEN filter
offers data reduction of 72.8% and 64.5%, respectively.
2:45 PMC6.4 A 7.2 inch 5.5M pixel 600mW SPAD X-ray Detector with 116.7 dB Dynamic Range, Byungchoul
Park1, Hyun-seung Choi2, Jinwoong Jeong3, Jimin Cheon4, Myung-Jae Lee2, Youngcheol Chae1 1Yonsei
University, 2Korea Institute of Science and Technology, 3Rayence, 4Kumoh National Institute ofTechnology

This paper presents the first 7.2-inch wafer-level SPAD X-ray detector for radiography and industrial
applications. A digital SPAD pixel achieves high SNR at low dose and wide DR. Large power consumptionof the photon counting at high dose is effectively mitigated by using an extrapolation method, and theoverflow flag of the photon counter is flexibly selected for further power reduction. High throughput isachieved with a pipelined readout chain of the pixel output. Implemented in a 65nm CMOS process, thedetector consists of 3296×1680 pixels with a pixel pitch of 49.5μm, corresponding to an area of 16.5×
8.9cm2, and consumes only 600mW at 13frames/s, while achieving a DR of 116.7dB. The detector’s global
shutter operation delivers high-quality images without motion artifacts. Excellent radiation hardness of
up to 10,000Gy is also achieved.
Session JFS3: Thermal Management and Power Delivery in 3D Integration
3:25 PM, Tapa 1
Co-Chairs:

Russell McMullan, AMD
Sun-Wan Hong, Sogang University

3:25 PM
JFS3.1 Co-Optimization for Robust Power Delivery Design in 3D-Heterogeneous Integration ofCompute In-Memory Accelerators (Invited), Madison Manley1, Ankit Kaul1, James Read1, Yandong Luo1,
Xiaochen Peng1, Shimeng Yu1, Muhannad Bakir1 1Georgia Institute of Technology
In this work, we quantify the impact of power supply noise (PSN) in 3D-HI architectures on the errors in
ADC and RRAM array outputs and optimize the 3D PDN and ADC designs to maximize inference accuracy
in compute-in-memory (CIM) hardware. We propose a device-HI-application-level evaluation
methodology to evaluate the impact of PDN design parameters on CIM inference accuracy. For ourassumed 3D CIM hardware, an areal distribution of through-silicon vias (TSVs) and μ-bumps, and a finetuned PSN-aware successive approximation register-ADC (SAR-ADC) achieves a 90% inference accuracy
compared to 47% with a baseline 3D design at iso-power and iso-area. These insights can be useful for
multi-die design convergence for edge intelligent CIM chips.
3:50 PM
JFS3.2 3DIC System-Technology Co-Optimization with a Focus on the Interplay of Thermal, Power,
Timing, and Stress Effects (Invited), Victor Moroz1, Xiaopeng Xu1, Alexei Svizhenko1, Xi-Wei Lin1, Sergey
Popov1, Henry Sheng1, Kenneth Larsen1 1Synopsys
3DIC chiplet stacking is taking the industry by storm. It provides huge benefits in terms of logic-to-memory
connection bandwidth expansion, power reduction, and manufacturing cost reduction. However, it brings
a number of new challenges that have to be addressed to make 3DIC solutions successful. First, we lookat the bigger picture of diverse STCO factors that have to be resolved, and then focus on the interplay offour effects that play a key role in 3DIC designs: thermal, power, timing, and stress, and show theirinterplay. Careful analysis and balance of all four major factors are necessary to pull off a successful 3DIC
solution.
4:15 PM
JFS3.3 Package - System Thermal Modeling and New Material (Invited), Tsung-Yu Chen1, Tsung-Yu
Chen1, Kris Chuang1, Wensen Hung1, Tsung-Shu Lin1, Yen-Ming Chen1 1Taiwan Semiconductor
Manufacturing Company
A holistic Die-Package-System level thermal modeling methodology incorporating local details, globalfeatures and new material adoption are undoubtedly a key enabler to unleash the innovations of futureadvanced packaging technology development. Three key aspects were addressed to demonstrate such

capabilities to guide the future 3D Fabric technology roadmap in HPC/AI industry applications such as
instance level thermal modeling technique, Lid/Ring package type evaluation and advanced
material/process impact to the die-package-system thermal performance. In summary, new material withprocess-friendly & better thermal conductivity from die level FEoL (front-end) & BEoL dielectric material,
package level TIM1 and lid as well as system level TIM1.5 and TIM2 are key knobs to boost overall DiePackage-System thermal performance.
4:40 PM
JFS3.4 Integration and Characterization of High Thermal Conductivity Materials for Heat Dissipationin Stacked Devices, W.-Y. Woon1, J.-H. Jhang1, K.-K. Hu1, C.-C. Shih1, J.-F. Hsu1, J.-P. Lin1, Y. Wu2, A.
Kasperovich3, M. Malakoutian3, R. Soman3, J. Kim3, H.-K. Wei1, M. Nomura2, S. Chowdhury3, S. Sandy Liao1
1
TSMC, 2University of Tokyo, 3Stanford University
Heat dissipation is one of the most imminent performance limiting challenges in new device architectures
involving backside power delivery network and 3D-stacking. In this work, we evaluate integration schemes
and propose high thermal conductivity materials as heat spreader bonding layer for heat dissipation
improvement. Analysis of potential integration issues, investigation of process solutions, and thermal
characterization for complex film stacks are presented.
5:05 PM
JFS3.5 High thermal conductivity AlN films for advanced 3D Chiplets, Takeshi Takagi1, Takeki Ninomiya1,
Masaaki Niwa1, Soken Obara1, Takeshi Momose1, Yukihiro Shimogaki1, Kasahiro Nomura1, Hiroshi Fujioka1,
Masakazu Mori2, Tadahiro Kuroda1 1The Univ. of Tokyo, 2Ryukoku Univ.
A novel “Cool 3D chiplet” concept is proposed, showcasing remarkable heat dissipation through the
integration of aluminum nitride (AlN), an insulating material with high thermal conductivity. We
conducted simulations analyzing the thermal impact of AlN as an interlayer dielectric (ILD) for the backside power delivery network (BSPDN), a TSV insulating film, and a molding material for the packaging.
Furthermore, we explored appropriate AlN deposition techniques for each application. The results
demonstrate the feasibility of building advanced 3D chiplets with enhanced heat dissipation by employing
the AlN in each layer that makes up the 3D chiplet, from the device level to the packaging level.
Session T3: Novel Channel Materials for Advanced CMOS
3:25 PM, Tapa 2
Co-Chairs:

Anabela Veloso, imec
Masahiko Kanda, Toshiba Electronic Devices & Storage Corporation

3:25 PMT3.1 Record Performance in GAA 2D NMOS and PMOS using Monolayer MoS2 and WSe2 with scaled
contact and gate length, Wouter Mortelmans1, Pratyush Buragohain1, Carly Rogan1, Ande Kitamura1,
Chelsey Dorow1, Kevin O'Brien1, Rahul Ramamurthy1, Jennifer Lux1, Ting Zhong1, Shane Harlson1, Eric
Gillispie1, Tyrone Wilson1, Adedapo Oni1, Ashish Penumatcha1, Mahmut Kavrik1, Kirby Maxey1, Azimkhan
Kozhakhmetov1, Chia-Ching Lin1, Sudarat Lee1, Andrey Vyatskikh1, Nazmul Arefin1, Paul Fischer1, Joshua
Kevek1, Tristan Tronic1, Matthew Metz1, Scott Clendenning1, Uygar Avci1 1Intel
2D transition metal dichalcogenides are promising candidates as channel material choice in ultimately
scaled CMOS. We report record performance in GAA 2D NMOS transistors using monolayer MoS2 withthree advances: scaled gate length (Lg) down to 25nm, scaled contact length (Lc) of 38nm, and theelimination of the low-k “inter-layer” in the gate stack enabling the first fully high-k GAA 2D device. We
achieve 90% yield for scaled Lg <50nm with SS of 86mV/dec and on-currents reaching 485µA/µm. Drive
currents of 342µA/µm are maintained after contact length scaling down to ~40nm. We report the first BTI

on any 2D GAA device and deposited high-k interface, showing HfO2 may be advantageous for 2D
reliability compared to typical Al2O3 inter-layers. Signs of short-channel effects are observed at the
shortest Lg, identifying EOT scaling as essential area of improvement. We also report record
ION=92µA/µm in scaled Lg GAA PMOS transistors with monolayer WSe2.
3:50 PMT3.2 EOT scaling via 300mm MX2 dry transfer - Steps toward a manufacturable process development
and device integration., Souvik Ghosh1, Anastasiia Kruv1, Quentin Smets1, Tom Schram1, Damien Leech1,
Taotao Ding2, Vikram Turkani3, Benjamin Groven1, Anish Dangol1, Gernot Probst2, Thomas Uhrmann2,
Marcus Wimplinger2, Inge Asselberghs1, Cesar Lockhart de la Rosa1, Steven Brems1, Gouri Sankar Kar1
1
IMEC, 2EV Group, 3PulseForge
We demonstrate a low-temperature automation-compatible, and reproducible 300mm MX2 dry transfer
process. We have successfully transferred 300mm WS2 in a repeatable process flow with >99.5%
morphological yield. In-FAB integrated transistors fabricated via this route have >99% electrical yield onbest wafers and is comparable to that obtained from analogous direct-grown WS2 integrated wafers.
Further, we also demonstrate back-EOT scaling down to 2nm that is otherwise out of scope via hightemperature direct growth. This transfer process facilitates a viable route to implement scaled
MX2 devices for FEOL CFET, and BEOL active circuits.
4:15 PMT3.3 High Performance Transistor of Aligned Carbon Nanotubes in a Nanosheet Structure, Gregory
Pitner1, Nathaniel Safron1, Tzu-Ang Chao1,2, Shengman Li3, Shreyam Natani4, San-Lin Liew1, Carlo Gilardi1,3,
Hsin-Yuan Chiu1,2, Sheng-Kai Su1, Andrew Bechdolt5, Gilad Zeevi5, Zichen Zhang4, Matthias Passlack1,
Vincent D.-H. Hou1, Harshil Kashyap4, Chao-Hsin Chien2, Prabhakar Bandaru4, Andrew Kummel4, H.-S.
Philip Wong1,3, Subhasish Mitra3, Iuliana Radu1 1TSMC, 2NYCU, 3Stanford University, 4U.C. San
Diego, 5Stanford
This work demonstrates the first nanosheet FET built on an array of dense aligned carbon nanotubes. In
this device structure, the gate surrounds an aligned array of CNTs with ≈3 nm pitch. At a channel lengthof 70 nm the drive current exceeds 1 mA/μm at -0.5 V VDS with sub-VT slope of 135 mV/dec, and an IMIN of
76 nA/μm. RC of 20.5 Ω-μm is extracted by transmission line method. This is record-high performance fortransistors with CNT channel. However, reducing DIT and channel variability are necessary to enableenergy-efficient CMOS applications.
4:40 PMT3.4 Achieving 1-nm-Scale Equivalent Oxide Thickness Top Gate Dielectric on Monolayer Transition
Metal Dichalcogenide Transistors with CMOS-Friendly Approaches, Jung-Soo Ko1, Alex Shearer1, Sol Lee2,
Kathryn Neilson1, Marc Jaikissoon1, Kwanpyo Kim2, Stacey Bent1, Krishna Saraswat1, Eric Pop1 1Stanford
University, 2Yonsei University
Two-dimensional (2D) transition metal dichalcogenides (TMDs) are promising for future nanoscaletransistors but reducing their gate dielectric equivalent oxide thickness (EOT) remains a key challenge.
Here, we report ultrathin top-gate dielectrics on monolayer (1L) TMDs using industry-compatible
approaches, achieving 1-nm-scale EOT. We show atomic layer deposition (ALD) of HfO2 on both 1L
MoS2 and WSe2 using Si seed, realizing 0.9 nm EOT with subthreshold swing SS ≈ 70 mV/dec, low leakage,and negligible hysteresis on MoS2. We also demonstrate direct ALD of ultrathin alumina (AlOx) on 1L
MoS2 with good uniformity and quality by engineering the precursor. Combining our findings, we showthat the threshold voltage can be controlled by the thickness of the interfacial dielectric layer on the 2D
transistor channel.

5:05 PMT3.5 Single-crystalline monolayer MoS2 arrays based high-performance transistors via selective-area
CVD growth directly on silicon wafers, Guixu Zhu1, Xiaodong Zhang1, Haotian Fang1, Dongdong Sun1,
Luyang Wang2, Zujian Dai1, Lizi Wei1, Qiuyang Lin3, Ao Li1, Yufeng Min1, Qiuxia Lu1, Lixin He1, Dongsheng
Song2, Yuanyuan Shi1 1University of Science and Technology of China (USTC), 2Anhui University, 3imec,
Leuven, Belgium
Here we present a method that fabricates massive arrays of single-crystalline monolayer (ML) MoS2-basedtransistors directly on silicon wafers without a 2D-layer transfer process (2D-LTP). Inspired by epitaxial
growth, quasi-terrace Al2O3 triangle-arrays are designed on silicon wafers, facilitating selective-area
growth (SAG) of single-crystalline ML MoS2 arrays. The SAG MoS2 arrays based back-gate (BG) transistors
show a maximum mobility of 62.8 cm2/Vs and Ion/Ioff ratio of 2.5×108. The study paves the way for highthroughput, Si-compatible, transfer-free, and controllable integration of single-crystalline transition metal
dichalcogenides (TMDs) based transistors.
Session T4: Oxide Channel FET for Logic and Memory Applications-1
3:25 PM, Tapa 3
Co-Chairs:

Max Shulaker, MIT
Masaharu Kobayashi, The University of Tokyo

3:25 PMT4.1 Highly Robust All-Oxide Transistors with Ultrathin In2O3 as Channel and Thick In2O3 as Metal
Gate Towards Vertical Logic and Memory, Zehao Lin1, Zhuocheng Zhang1, Chang Niu1, Hongyi Dou1, Ke
Xu1, Mir Md Fahimul Islam1, Jian-Yu Lin1, Changhyuck Sung2, Minji Hong2, Daewon Ha2, Haiyan Wang1,
Muhammad Ashraful Alam1, Peide Ye1 1Purdue University, 2Samsung Electronics Co.
In this work, we report for the first time atomic-layer-deposited (ALD) all-oxide transistors toward 3-Dvertical integration, with thick ALD In2O3 as gate electrodes, and In2O3 itself as contact. The all-oxide thinfilm transistors (TFTs) show an on/off ratio over 106, high uniformity, and very robust reliability with athreshold voltage shift (ΔVTH) of 5 mV and 50 mV in positive and negative bias stress (PBS and NBS) tests.
The vertically all-oxide TFTs demonstrate good control from side wall with on/off ratio over 105 andmaximum current (Imax) over 160 μA/μm. And vertically all-oxide ferroelectric field-effect transistors (FeFETs) exhibit a memory window (MW) of 1.85 V, with an endurance and retention extended to 1012 cycles
and 10 years. This illustrates the vertically all-oxide device based on ALD oxide semiconductor (OS) is agood candidate toward future high-density integrated circuits.
3:50 PMT4.2 Scaling Potential of Nanosheet Oxide Semiconductor FETs for Monolithic 3D Integration - ALD
Material Engineering, High-Field Transport, Statistical Variability, Kaito Hikake1, Sung-hun Kim1, Xingyu
Huang1, Kota Sakai1, Zhuo Li1, Tomoko Mizutani1, Takuya Saraya1, Toshiro Hiramoto1, Takanori Takahashi2,
Mutsunori Uenuma2, Yukiharu Uraoka2, Masaharu Kobayashi1,3 1Institute of Industrial Science, The
University of Tokyo, 2Nara Institute of Science and Technology, 3d. lab, The University of Tokyo
We have investigated the scaling potential of nanosheet oxide semiconductor FETs (NS OS FETs) for 3D
LSI application in terms of ALD material engineering, high-field transport, and statistical variability, for the
first time. We have developed and systematically compared ALD-grown InGaO, InZnO and InGaZnO FETs.
We have fabricated sub-100nm gate length NS OS FETs and demonstrated unsaturated carrier velocity
behavior. We have obtained statistical variability data of NS OS FETs and showed a comparable variability
against Si CMOS. This work provides an evidence of scalability of NS OS FETs for 3D LSI application.
4:15 PMT4.3
Enhancement of In2O3 Field-Effect Mobility Up To 152 cm2·V-1·s-11 Using HZO-Based Higher-kLinear Dielectric, Zehao Lin1, Chang Niu1, Hyeongjun Jang2, Taehyun Kim2, Yizhi Zhang1, Haiyan Wang1,
Changwook Jeong2, Peide Ye1 1Purdue University, 2Ulsan National Institute of Science and Technology
In this work, we report high-performance ALD In2O3 TFTs using HZO as a linear higher-k dielectric. By
properly inserting a thin Al2O3 layer between two asymmetric HZO layers and annealing the HZO-Al2O3HZO stack capped with In2O3, the k value of the linear dielectric is boosted to 30. This results in an EOT of
1.9 nm with physical thickness of 15.5 nm and meanwhile In2O3 field-effect mobility is boosted to 152
cm2·V-1·s-1, simultaneously. Such enhancements enable high-performance TFTs with record saturation
current exceeding 2 mA/μm with a Lch of 1 μm, and maximum current reaches 7 mA/μm with Lch of 30 nm.
Higher-k dielectrics also enhance the electrostatic control of the channel with negligible hysteresis, on/off
ratio over 1011, and DIBL less than 40 mV/V at Lch of 35 nm. This work demonstrates a promising andstraightforward methodology to enhance the mobility of oxide semiconductor channel by using linear
higher-k dielectrics.
4:40 PM
T4.4
Highly Enhanced Memory Window of 17.8V in Ferroelectric FET with IGZO Channel via
Introduction of Intermediate Oxygen-deficient Channel and Gate Interlayer, Sijung Yoo1, Donghoon
Kim1, Duk-Hyun Choe1, Hyun Jae Lee1, Yunseong Lee1, Sanghyun Jo1, Yoonsang Park1, Ki Hong Kim1, Kyooho
Jung1, Moonil Jung1, Kwang-Hee Lee1, Jee-Eun Yang1, Sangwook Kim1, Seung-Geol Nam1 1Samsung
Advanced Institute of Technology
We demonstrated a novel Ferroelectric Field-Effect Transistor (FeFET) with an IGZO channel, featuring arecord-high memory window (MW) of up to 17.8V. A significant advancement is achieved by two
strategies. Firstly, the introduction of an intermediate oxygen-deficient channel, which offers sufficient
depletion charge to ensure full-loop polarization switching. Secondly, inserting a thin gate interlayer (G.IL),
which further increases the MW by the contribution of injected charge through G.IL. With a sub-12nm
gate stack thickness and an operation voltage below 15V, the device exhibits promising potential for highdensity, low-power non-volatile memory applications.
5:05 PMT4.5 A-IGZO FETs with High Current and Remarkable Stability for Vertical Channel Transistor(VCT)DRAM Applications, Younjin Jang1, Jee-Eun Yang1, Na-Rae Han1, Ha-Jun Sung1, Jung-kyun Kim1,
Youngkwan Cha1, Kwang-Hee Lee1, Kyooho Jung1, Moonil Jung1, Wonsok Lee2, Min Hee Cho2, Sangwook
Kim1 1Samsung Advanced Institute of Technology, 2Samsung Electronics
We report the a-IGZO channel FET exhibited high Ion (22 μA/μm with VGS = Vth+1 V and VDS = 1 V ) andexcellent NBTI characteristics ( ∆Vth < 1 mV at 3 MV/cm, 85°C). In order to realize such a high performancedevice, there are several considerations, one of which is finding the optimal composition that increases
mobility and keeps device reliability characteristics stable, and the next is to understand the effects ofvarious process conditions on channel behavior and effectively suppress oxygen vacancies (VO) while
lowering hydrogen (H) concentration. Specifically, we tried to apply an interlayer to contact metal,
reduced the H in the bottom oxide, and finally optimized the condition of a gate oxide (Gox) process andO2 treatment method that could efficiently minimize defect states in the device.
Session C7: Processors I
3:25 PM, Honolulu 1
Co-Chairs:
3:25 PMBen Keller, Nvidia
Chia-Hsiang Yang, National Taiwan University

C7.1 Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense andSparse Applications, Kalhan Koul1, Maxwell Strange1, Jackson Melchert1, Alex Carsello1, Yuchen Mei1,
Olivia Hsu1, Taeyoung Kong1, Po-Han Chen1, Huifeng Ke1, Keyi Zhang1, Qiaoyi Liu1, Gedeon Nyengele1,
Akhilesh Balasingam1, Jayashree Adivarahan1, Ritvik Sharma1, Zhouhua Xie1, Christopher Torng2, Joel
Emer3, Fredrik Kjolstad1, Mark Horowitz1, Priyanka Raina1 1Stanford University, 2University of Southern
California,3Massachusetts Institute of Technology
This work presents Onyx, the first coarse-grained reconfigurable array for both dense and sparse
applications. We add composable sparse primitives that accelerate arbitrary sparse tensor algebra kernels
with support for higher-order tensors, multiple inputs, and fusion. Onyx also has application-specialized
compute and area-optimized memory tiles for image processing and machine learning applications. We
achieve up to 565x better energy-delay product (EDP) for sparse kernels vs. CPUs with sparse libraries,
and up to 76% and 85% lower EDP for image processing and ML, respectively, vs. state-of-the-art.
3:50 PMC7.2
A 52.01TFLOPS/W Diffusion Model Processor with Inter-Time-Step Convolution-AttentionRedundancy Elimination and Bipolar Floating-Point Multiplication, Yubin Qin1, Yang Wang1, Xiaolong
Yang1, Zhiren Zhao1, Shaojun Wei1, Yang Hu1, Shouyi Yin1 1Tsinghua University
This paper proposes an energy-efficient diffusion model processor with three features: 1) a semanticsegment sparse convolution engine removes 88.5% of duplicated convolution layer (CL) computations. 2)
a resemble trivial attention exponent inheritance design improves attention layer (AL) computation
efficiency by 16.7×. 3) a bipolar floating-point multiplier saves 25.4% multiplication effort by avoiding
ineffective mantissa multiplication for both CL and AL. It achieves a peak efficiency of 52.01TFLOPS/W andreduces energy by 23.14× and 3.94× compared to state-of-the-art CL and AL processors.
4:15 PM
C7.3 A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6. .6μs Average Solution Time with
100% Solvability for Hard 3-SAT Problems, Qiaochu Zhang1,2, Shiyu Su1,3, Zerui Liu1, Hsiang-Chun Cheng1,
Zhengyi Qiu1,3, Mayank Palaria1, Jiacheng Ye1, Deming Meng1, Buyun Chen1, Sushmit Hossain1, Wei Wu1,
Mike Shuo-Wei Chen1 1University of Southern California, 2University of Virginia, 3University of Waterloo
This paper presents a stochastic analog SAT solver, featuring a fast open-loop architecture with
continuous-time self-loopback pull-up switches, a discrete-time scrambling scheme, and a cost-efficienthybrid random code generator. The SAT prototype in 65nm achieves orders of magnitude improvementin speed and energy efficiency compared to prior ASIC SAT solvers.
4:40 PMC7.4 Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISCV-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point
Support in 12nm FinFET, Gianna Paulin1, Paul Scheffler1, Thomas Benz1, Matheus Cavalcante2, Tim
Fischer1, Manuel Eggimann1, Yichao Zhang1, Nils Wistoff1, Luca Bertaccini1, Luca Colagrande1, Gianmarco
Ottavi3, Frank Kagan Gürkaynak1, Davide Rossi3, Luca Benini1,3 1ETH Zurich, Switzerland, 2Stanford
University, USA, 3University of Bologna, Italy
We present Occamy, a 432-core RISC-V dual-chiplet 2.5D system for efficient sparse linear algebra andstencil computations on FP64 and narrow ( 32-, 16-, 8-bit) SIMD FP data. Occamy features 48 clusters of
RISC-V cores with custom extensions, two 64-bit host cores, and a latency-tolerant multi-chiplet
interconnect and memory system with 32 GiB of HBM2E. It achieves leading-edge utilization on stencils(83 %), sparse-dense (42 %), and sparse-sparse (49 %) matrix multiply.

Session C8: Oversampled Converters
3:25 PM, Honolulu 2
Co-Chairs:

Stacy Ho, MediaTek
Tetsuya Iizuka, The University of Tokyo

3:25 PMC8.1 A 97dB-PSRR 178.4dB-FOMDR Calibration-Free VCOΔΣ ADC Using a PVT-Insensitive FrequencyLocked Differential Regulation Scheme for Multi-Channel ExG Acquisition, Sehwan Lee1,2, Taeryoung
Seol1, Geunha Kim1, Minyoung Song1, Gain Kim1, Jong-Hyeok Yoon1, Arup K. George1, Junghyup Lee1
1
DGIST, 2Samsung Electronics
This paper proposes a 97dB-PSRR, 178.4dB-FOMDR calibration-free 16-channel VCO-ΔΣ ADC system usinga PVT-insensitive frequency-locked differential regulation (FLDR) scheme suitable for wireless ExG
Acquisition. Thanks to the FLDR, the SNDR degradation in all 16 channels is less than 1dB over 1.4-2V
supply and 20-60°C temperature ranges. Implemented in a 0.18µm standard CMOS process, the proposedsystem consumes 172µW from a 1.4V supply and occupies 2.7mm2 active area, while a single channel
consumes 4.2µW and 0.12mm2, respectively.
3:50 PMC8.2 A 470μW, 102.6dB-DR, 20kHz BW calibration-free ΔΣ Modulator with SFDR in excess of 110dBc
using an Intrinsically Linear 13-Level DAC, Matteo Dalla Longa1,2, Francesco Conzatti1, Omar Ismail2, John
Gabriel Kauffman2, Maurits Ortmanns2 1Infineon Technologies Austria AG, 2Ulm University
This paper presents the first true multibit Discrete Time ΔΣ Modulator (DTΔΣM) to achieve a SFDR in excess
of 110dBc without the need for Dynamic Element Matching (DEM) or calibration. The high linearity is
obtained using a 13-level intrinsically linear DAC in the feedback loop. Over Process-Voltage-Temperature(PVT) variations, the SFDR is consistently between 105 and 115dBc for all measured devices. The
prototype achieves a DR of 102.3dB and an SNDR of 100.7dB in a 20kHz BW, consuming 500μW from a
1.8V supply, resulting in a Schreier FoM of 178.3dB.
4:15 PM
C8.3 A Beyond-the-rail Audio CTDSM with a Passive Input Stage and 99.2dB SNDR, Shenyang Li1,
Sundeep Javvaji1, Victor Pecanins-Martínez1, Eren Aydin1, Robert Van Veldhoven2, Kofi Makinwa1 1Delft
University of Technology, 2NXP Semiconductors
This paper presents a 3rd order continuous-time delta-sigma modulator (CTDSM) for audio applications.
Its loop filter efficiently realizes complex conjugate NTF zeros by combining a passive RC filter and a GmC based resonator. The latter is built around a capacitively-coupled chopper OTA, which enables a beyondthe-rail input range. Implemented in 65nm CMOS, the proposed CTDSM achieves 99.2dB SNDR and 100dB
DR in a 24kHz BW while consuming only 80.7μW. This results in a state-of-the-art Schreier FoMSNDR of
184dB.
4:40 PMC8.4 A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-order Continuous-Time Delta-Sigma
Modulator with 3rd-order Noise Coupling, Kent Edrian Lozada1, Ye-Dam Kim1, Ho-Jim Kim2, Youngjae Cho2,
Michael Choi2, Seung-Tak Ryu1 1Korea Advanced Institute of Science and Technology, 2Samsung
Electronics
This work proposes a digital-intensive 4th-order continuous-time delta-sigma modulator (CTDSM) realizing
3rd-order noise-shaping through digital noise coupling (DNC), while the remaining 1st-order noise-shaping
is done by an analog loop filter (LF). Fabricated in 28-nm CMOS, the proposed architecture achieves 89.0-

dB SNDR, 92.1-dB DR, and 103.9-dB SFDR in a 200-kHz bandwidth (BW), while consuming only 0.38mW at
12.8MS/s. This results in a state-of-the-art Schreier Figure of Merit (FoMS) of 179.3dB and Walden
FoMW of 41.2fJ/conv.-step.
5:05 PM
C8.5
A 10.8GS/s, 84MHz-BW RF Bandpass ΣΔ ADC with a 89dB-SFDR and a 62dB-SNDR for LTE/5G
Receivers, Alhassan Sayed1, Michel Vasilevski1, Mahmoud Tarek Abdelmomen1, Shadi Turk1, Ahmed
Ghoniem2, Cristobal Perez3, Cyril Voillequin4, Haralampos Stratigopoulos5, Marie-Minerve Louerat5, Eric
Wantiez3, Hassan Aboushady1 1Seamless Waves, 2insspectrum, 3Nokia, 4Thales, 5Sorbonne University,
LIP6, CNRS
The LTE/5G multi-standard RF BP ΣΔ ADC reported in this paper achieves an SFDR of 89dB and an SNDR of
62dB on a 84MHz-BW centered at F0=2.7GHz. The ADC, sampled at Fs=10.8GHz, has an RF Noise Figureof 29dB, and an Input Intercept Point of +8dBm. When OFDM modulated signals are applied to the ADC,
the measured EVM is 1.25% for a 10MHz/64-QAM/LTE, 1.6% for a 20MHz/64-QAM/LTE, and 2.0% for a
40MHz/64-QAM/5G signal.
Session C9: Wireless Transceivers
3:25 PM, Honolulu 3
Co-Chairs:

Vanessa Chen, Carnegie Mellon University
Wei Deng, Tsinghua University

3:25 PM
C9.1 A 132-to-163 GHz 4TX/4RX Distributed MIMO FMCW Radar Transceiver with Real-time
Reference-Clock Synchronization Enabling Cooperative Coherent Multistatic Imaging System, Ruichen
Wan1, Wei Deng1, Qixiu Wu1, Haikun Jia1, Rui Wu2, Angxiao Yan1, Haowen Cai3, Sanming Hu3, Zhihua
Wang1, Baoyong Chi1
1
Tsinghua University, 2National Key Laboratory of Microwave Imaging Technology, Aerospace Information
Research Institute, Chinese Academy of Science, 3Southeast University
This work introduces a D-band 4TX/4RX distributed MIMO radar transceiver with real-time referenceclock synchronization for multistatic imaging system. The proposed synchronized radar system eliminates
the time error, frequency error, and slope error of local oscillator (LO) signals between radar stations toensure the correct acquisition and analysis of radar signals, which enables the combination of target datafrom multitude of transmitting and receiving stations coherently. In addition, several circuit design
techniques including harmonic extraction series power synthesis and harmonic suppression frequency
doubling are investigated. This work achieves better detection performance than the traditional MIMO
radar with the same number of channels, demonstrating its advantages in future cooperative coherent
multistatic imaging system.
3:50 PM
C9.2
A 640-Gb/s 4 X 4-MIMO D-Band CMOS Transceiver Chipset, Chenxin Liu1, Zheng Li1, Yudai
Yamazaki1, Hans Herdian1, Chun Wang1, Anyi Tian1, Jun Sakamaki1, Han Nie1, Xi Fu1, Sena Kato1, Wenqian
Wang1, Hongye Huang1, Shinsuke Hara2, Akifumi Kasamatsu2, Hiroyuki Sakai1, Kazuaki Kunihiro1, Atsushi
Shirane1, Kenichi Okada1 1Tokyo Institute of Technology, 2National Institute of Information andCommunications Technology
This work presents a D-band (114-170GHz) CMOS transceiver (TRX) chipset covering a 56GHz signal-chain
bandwidth. An 8-way low-Q power-combined power amplifier (PA), a 2-way low-Q power-combined low
noise amplifier (LNA), wideband-impedance-transformation mixers, and common-source-based cascaded

distributed amplifiers (DA) are proposed to improve bandwidth and linearity. The proposed TRX chipset
achieves 200-Gb/s data rate by 32QAM in the single-input single-output (SISO) over-the-air (OTA)
measurement. A 120-Gb/s data rate by 16QAM is realized with a 15m distance. A 640-Gb/s 4×4 multiinput multi-output (MIMO) is also demonstrated in this work.
4:15 PM
C9.3 A -96.5 dBm-Sensitivity, 14 dBm peak power, Self-Interference Resistant IR-UWB Radar
Transceiver Supporting Child Presence Detection and Precision Positioning, Hyun-Gi Seok1, Wan Kim1,
Sinyoung Kim1, Jae-Keun Lee1, Chanho Kim1, Chanbin Ko2, Junseong Park2, Wonkang Kim1, Jongpill Cho1,
Seungyoung Bae1, Youngsea Cho1, Wonjun Jung1, Junhyeong Kim1, Sumin Kang1, Hyeokju Na1,
Byoungjoong Kang1, Honggul Han1, Hoon Kang1, Minki Ahn1, Chiyoung Ahn1, Sukjin Jung1, Hyukjun Sung1,
Seunghyun Oh1, Jae-Eun Lee2, Jongwoo Lee1, Joonsuk Kim1 1Samsung Electronics, 2Bitsensing
This paper presents a radar-enabled IR-UWB system by adopting a self-interference resistant RFtransceiver. It shows that child presence detection using IR-UWB radar is possible by implementing a radarsystem including PHY, MAC, and APP processor. RF transceiver shows high receiver sensitivity andtransmitter peak power with low power. Furthermore, a radar dedicated transmitter is used to improve
the transmitter signal isolation to the receiver. Proposed notch pulse shaping filter is adopted to satisfy
the spectrum emission mask specification. Additionally, a low noise amplifier with wide gain ranges is
proposed to improve the sensitivity and support various applications such as radar and positioning
detection application. The UWB transceiver achieves -96.5 dBm sensitivity at BPRF 6.81 Mb/s and 14 dBm
transmitter peak power and supports the UWB channel 5 and 9.
4:40 PM
C9.4 A 28GHz 5G NR Wirelessly Powered Relay Transceiver Using Rectifier-Type 4th-Order SubHarmonic Mixer, Sena Kato1, Shu Date1, Tao Ruoxin1, Yasuto Narukiyo1, Hiroki Hayashi1, Keito Yuasa1,
Michihiro Ide1, Takashi Tomura1, Kenichi Okada1, Atsushi Shirane1 1Tokyo Institute of Technology
In this paper, a wirelessly powered 28GHz phased-array relay transceiver for 5G networks is proposed.
The transceiver operates by rectifying a 5.7GHz WPT signal to generate DC power. The transceiver consistsof a circuit that performs 4th-order sub-harmonic mixer operation while rectifying the WPT signal. The
proposed circuit rectifies with efficiency of up to 54.9% and a maximum frequency conversion gain of 19.3dB. The 4×2-array antenna board implementing the chips can steer beam from -50° to +50° and theboard is capable of sending and receiving 5G NR modulated signal with 400MHz bandwidth using 64QAM(MCS17).
5:05 PM
C9.5 A 28GHz 4-Stream Time-Division MIMO Phased-Array Receiver Utilizing Nyquist-Rate Fast Beam
Switching for 5G and Beyond (Late News), Yi Zhang1, Minzhe Tang1, Jian Pang1, Zheng Li1, Dongfan Xu1,
Dingxin Xu1, Yuncheng Zhang1, Kazuaki Kunihiro1, Hiroyuki Sakai1, Atsushi Shirane1, Kenichi Okada1 1Tokyo
Institute of Technology
This work proposes an area-efficient 28-GHz time-division MIMO beamformer supporting multi-beam
MIMO (MB-MIMO) without additional hardware cost. RF signal paths can be reused for different MIMO
streams by a time-division beam-switching operation, which is realized by oversampled fast-switching RFphase shifter and clock-based synchronization. A prototype fabricated in 65nm CMOS achieves 64-QAM
4x4 MIMO reception in OTA measurement using four 5G NR spatial data streams with 400MHz channel
bandwidth.
Panel Session
Tuesday, June 18, 8:00 pm – 10:00 pm

Tapa 1-3
Organizers:

Stacy Ho, Mediatek
Stanley SC Song, Google
Noriyuki Miura, Osaka Univ
Kazuyuki Tomida, Rapidus
C. Patrick Yue, HKUSTWill AI Bite the Industry That Feeds It?
Moderators: Masato Motomura, Tokyo Institute of Technology
Chris Mangelsdorf, Analog Devices (retired)
It's time to talk about the scary elephant in the room. The powerful new technology of AI is only possible
because of the high-performance semiconductors that WE make. But is this new beast about to turn on
us? Are our jobs at stake because of it, or will it usher in a new golden age of semiconductors withbreakthrough innovations and countless new applications?
This Panel discussion will have two parts. Part 1 for discussion of moderated questions among panelists
followed by Q&A with the audience and Part 2 for game-show competition between Chip heroes(panelists and audience) and gen-AI.
Don't miss this thought-provoking and entertaining panel discussion!
Panelists:
Azalia Mirhoseini, Stanford Univ
Rangharajan Venkatesan, Nvidia
Hoi-Jun Yoo, KAIST

Serge Biesemans, IMEC
Chidi Chidambaram, Qualcomm
Chet Lenox, KLA
Euicheol Lim, SKHynix

Wednesday, June 19, 2024
Session PL2: Plenary Session II
8:00 AM, Tapa 1-3
8:00 a.m.

Opening Remarks
T. Tsunomura, Tokyo Electron Ltd.
M. Hamada, The University of Tokyo

P2.1 - 8:35 AM
Wireless and Future Hyperconnected World, Maryam Rofougaran, Movandi Corporation, CEO and CoFounder
Wireless networks will become the backbone of our hyper-connected world by providing high-speed, lowlatency data transmission. Through a fusion of terrestrial cellular networks, satellite communication, andlocal wireless area networks, this infrastructure will seamlessly support continuous connectivity forbillions of devices and cater to essential needs such as emergency response, remote work, automation,and operational efficiency. The integration of sensing technologies enriches wireless networks withcontextual awareness and environmental intelligence. With billions of sensors capturing real-time data,
these networks empower AI-driven algorithms to optimize performance, anticipate user requirements,and overcome potential obstacles. Semiconductor breakthroughs are pivotal in realizing intelligent
wireless connectivity. Advanced chip sets, featuring embedded AI accelerators, empower AI algorithms toprocess data locally and make informed decisions in near real-time. Energy-efficient semiconductor
designs also extend device battery life. This presentation will review key advances of wireless technology
and present emerging technologies that will shape its evolution.
P2-2 9:15 AM
Photonics-Electronics Convergence Devices to Accelerate IOWN, Hidehiro Tsukano, NTT Corporation,
Senior Vice President of Research and Development
IOWN (Innovative Optical Wireless Network) is an initiative to create a sustainable society that cannot be
achieved with current network infrastructure. By taking advantage of optical technology for across-theboard network communications and computing, NTT is aiming to provide a new ICT platform that featureshigh-capacity, high-quality, low-latency, and low-power consumption. The primary requirements fordevice technology are ultra-fine semiconductor manufacturing processes, ultra-high density assembly,
and photonics-electronics convergence. Thus, NTT is promoting research and development in accordancewith the roadmap to incorporate optical communications technology into the details of computing
components step by step. This challenge could lead to the ultimate computing capacity that extends
Moore’s law, and we believe it can resolve the ever-increasing power consumption problem of
information processing and contribute to the realization of carbon neutrality.
Session T5: Advanced CMOS Devices and Technology-1
10:15 AM, Tapa 1-3
Co-Chairs:

Anabela Veloso, ImecJin Cai, TSMC

10:15 AM
T5.1 Product Performance Aware 3rd Generation GAA Platform Transistor Design with Extreme
Small Local Layout Effect and Transistor Variation, Dongchan Jeong1, Seungkwon Kim1, Seulki Park1, Sang
Hyeon Lee1, Sada-aki Masuoka1, Byungha Choi1, Shincheol Min1, Sanghoon Lee1, Minseong Lee1, ChangWoo Sohn1, Jaehun Jeong1, Yuri Yasuda-Masuoka1, Ja-Hum Ku1,1 1Samsung Electronics
A product performance aware 3rd generation MBCFETTM (SF2) is revealed to maximize Gate-All-Aroundbenefit fully by introducing unique epitaxial and integration process, which overcomes the scaling and
GAA structure conflict with a product gain. The product major narrow NS Tr was boosted by N/PFET+29/+46%, as well as a wide NS Tr +11/+23%. In addition, through Tr global variation reduction by 26%
from FinFET, a product leakage distribution was significantly scaled by ~50%. The process can enable
another level of DTCO collaboration in MBCFETTM for the future technology.
10:40 AM
T5.2 Monolithic Complementary Field Effect Transistors (CFET) demonstrated using Middle Dielectric
Isolation and Stacked Contacts, Steven Demuynck1, Victor Vega Gonzalez1, Camila Toledo de Carvalho
Cavalcante1, Lucas Petersen Barbosa Lima1, Karen Stiers1, Cassie Sheng1, Anne Vandooren1, Maryam
Hosseini1, Daisy Zhou1, Hans Mertens1, Thomas Chiarella1, Juergen Boemmels1, Roger Loo1, Erik Rosseel1,
Clement Porret1, Yosuke Shimura1, Anjani Akula1, Geert Mannaert1, Subhobroto Choudhury1, Vincent
Brissonneau1, Emmanuel Dupuy1, Tanushree Sarkar1, Nathali Franchina Vergel1, Antony Peter1, Nicolas
Jourdan1, Jean-Philippe Soulie1, Kevin Vandersmissen1, Farid Sebaai1, Pallavi Putarame Gowda1, Kenneth

Lai1, Andrea Mingardi1, Sujan Sumar Sarkar1, Koen Dhave1, BT Chan1, Alfonso Sepulveda Marquez1, RobertLanger1, Il Gyo Koo1, Efrain Altamirano Sanchez1, Katia Devriendt1, Paulina Rincon Delgadillo1, Frederic
Lazzarino1, Jerome Mitard1, Jef Geypen1, Eva Grieten1, Dmitry Batuk1, Yi-Fan Chen1, Frederik Verbeek1,
Frank Holsteyns1, Sujith Subramanian1, Naoto Horiguchi1, Serge Biesemans1 1imec
This work reports on the first demonstration of monolithic CFET CMOS co-integrating Middle Dielectric
Isolation (MDI), Inner Spacers (ISP) and Stacked frontside patterned Contacts. The flow results infunctional CMOS devices on a common gate architecture. The MDI formation is done before source drain(SD) recess for optimal bottom junction (BJ) formation. The paper discusses the challenges of using
stacked contacts to form the top device junction (TJ). Finite accuracy of bottom device contact (BC)registration from frontside results in a limited process latitude to access the top device channel for TJ
formation while keeping the integrity of MDI and ISP. Top device survival rate increases from 11% to 79%
by eliminating the frontside BC. We show feasibility of moving BC to the wafer backside with registration
accuracy below 3nm.
11:05 AM
T5.3 Ge(110) GAA Nanosheet / Si(100) Tri-gate Nanosheet Monolithic CFETs Featuring Record-highHole Mobility, Seong Kwang Kim1,2, Hyeong-Rak Lim1, Jaeyong Jeong1, Youngkeun Park1, Jejune Park2,
Sungil Park2, Jaehyun Park2, Daewon Ha2, Byung Jin Cho1, Sanghyeon Kim1 1KAIST, 2Samsung Electronics
In this study, we demonstrated heterogeneous 3D monolithic CFETs (mCFETs) by utilizing Ge (110)/<110>gate-all-around (GAA) nanosheet p-FETs as the top-tier transistors and Si (100)/<110> tri-gate n-FETs as
the bottom-tier transistors. By minimizing the mobility difference between electrons and holes throughthis transport combination of heterogeneous channels, we demonstrated its potential for the nextgeneration logic. Notably, we achieved a record-high hole mobility of 1200 cm2/V∙s (normalized by
footprint to account CFET drivability) in the Ge (110)/<110> GAA nanosheet p-FETs with flat top andbottom surfaces. These channels were successfully employed in heterogeneous mCFETs to see thefeasibility for high-performance logic devices.
11:30 AM
T5.4 Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison
Study of Nanosheet FETs (A10) & Complementary FETs (A5), Subrat Mishra1, Bjorn Vermeersch1,
Venkateswarlu Sankatali1, Halil Kukner1, Gioele Mirabelli1, Fabian Bufler1, Moritz Brunion1, Dawit Burusie
Abdi1, Herman Oprins1, Dwaipayan Biswas1, Odysseas Zografos1, Francky Catthoor1, Pieter Weckx1, Geert
Hellings1, James Myers1, Julien Ryckaert1 1IMECIn this paper, we make a thermal-aware block-level PPA comparison study for nanosheet transistors andcomplementary field effect transistors, expected to be used in future Angstrom nodes, namely A10 and
A5 respectively. We report block-level scaling results from A10 to A5 node on an open-source many-corearchitecture: 2.5% increase in Fmax, 25% reduction in power, 27% reduction in energy per cycle, achieved
with 35% area reduction and a consequent increase in power density by 15% under nominal 0.7V/25C.
The PPA analysis methodology has been augmented with a fast package-level thermal simulator to enable
early self-consistent thermal estimation that accounts for exponential leakage power increase withtemperature, which is important for dynamic thermal management applications. The analysis reveals a
reduction of 64mV in Vdd and 10% in frequency required for A5 node to maintain same Tj,max as A10 nodeoperating at 0.7V, still resulting in a 40% gain in system throughput.
Session C10: Transformer Processors
10:15 AM, Honolulu 1
Co-Chairs:

Ben Keller, NVIDIA

Vinayak Honkote, Intel Corp.
10:15 AM
C10.1 MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip
Resistive RAM and Fine-Grained Spatiotemporal Power Gating, Kartik Prabhu1, Robert M. Radway1,
Jeffrey Yu1, Kai Bartolone1, Massimo Giordano1, Fabian Peddinghaus1, Yonatan Urman1, Win-San Khwa2,
Yu-Der Chih2, Meng-Fan Chang2, Subhasish Mitra1, Priyanka Raina1 1Stanford University, 2TSMC
MINOTAUR is the first energy-efficient edge SoC for inference and training of Transformers (and othernetworks, e.g., CNNs) with all memory on-chip. MINOTAUR leverages a configurable 8-bit posit-based
accelerator, fine-grained spatiotemporal power gating enabled by on-chip resistive-RAM (RRAM) for
dynamically adjustable bandwidth, and on-chip fine-tuning through full-network low-rank
adaptation (LoRA). MINOTAUR achieves an average utilization of 93% and 74% and energy of 8.1 mJ and7.3 mJ on ResNet-18 and MobileBERTTINY inference respectively, and on-chip fine-tuning within 1.7% ofoff-line training without RRAM-induced energy limitations or endurance degradations.
10:40 AM
C10.2 A 28nm 4.35TOPS/mm2 Transformer Accelerator with Basis-vector Based Ultra Storage
Compression, Decomposed Computation and Unified LUT-assisted Cores, Chen Tang1, Xinyuan Lin1,
Zongle Huang1, Wenyu Sun1, Hongyang Jia1, Yongpan Liu1,1 1Tsinghua University
The area-efficient Transformer accelerator exploiting matrix redundancy is presented with four features:
1) A proposed basis-vector decomposition sparing 25.5x model storage for Transformer like Bert-Base,allowing full on-chip inference on devices with about 13MB memory like smartphones, at only 1.28%
accuracy loss. 2) An area-efficient self-programming LUT-assisted computing cell by result prefetch; 3) A
unified task-insensitive core supporting fast decomposed computing, resulting in a remarkable 73%
energy saving; 4) A NoC design facilitating hybrid data reuse to reduce communication. It achieves 4.35
TOPS/mm2 dense area efficiency, 4 times than the state-of-the-art counterpart at same fabrication level.
It also demonstrates 213%-429% higher overall energy efficiency.
11:05 AM
C10.3 A 99.2TOPS/W Transformer Learning Processor with Approximated Attention Score GradientComputation and Ternary Vector-based Speculation, Ping-Sheng Wu1, Yu-Cheng Lin1, Chia-Hsiang Yang1
1
Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
This work presents the first Transformer learning processor supporting both inference and training
acceleration. By applying algorithm-architecture optimizations, including approximated gradientcomputation and ternary vector-based speculation, the training complexity is reduced by up to 94.2%.
Adoption of the 8-bit block floating-point (Block-FP) format enables a 39-to-60% power reduction for
multiply-accumulate (MAC) operations. The chip delivers a peak energy efficiency of 99.2TOPS/W,
outperforming the state-of-the-art Transformer inference-only processors by 2.6-to-162×.
11:30 AM
C10.4 A 22nm 54.94TFLOPS/W Transformer Fine-Tuning Processor with Exponent-Stationary Recomputing, Aggressive Linear Fitting, and Logarithmic Domain Multiplicating, yang wang1, Xiaolong
Yang1, Yubin Qin1, Zhiren Zhao1, ruiqi guo1, zhiheng yue1, Huiming Han1, Shaojun Wei1, Yang Hu1, Shouyi
Yin1,2 1Tsinghua University, 2Shanghai AI Laboratory
This paper proposes a Transformer-based processor supporting energy-efficient fine-tuning with batchiteration-matrix multi-level optimizations. It has three key features: 1) An exponent-stationary recomputing scheduler (ESRC) reduces 44.2% of the storage requirement for each batch. 2) An aggressive
linear fitting unit (ALFU) saves 47.4% of the computations in each iteration. 3) A logarithmic domain
processing element (LDPE) decreases 36.3% of energy for matrix multiplications (MM) in fine-tuning. The

proposed Transformer processor achieves an energy efficiency of 54.94TFLOPS/W. It reduces fine-tuning
energy by 4.27× and offers 3.57× speedup for GPT-2.
Session C11: Clocking Techniques
10:15 AM, Honolulu 2
Co-Chairs:

Erik Olieman, NXP Semiconductors
Satoshi Kondo, Toshiba Corp.

10:15 AM
C11.1 A 0.9V Rail-to-Rail Ultra-Low-Power Fully Integrated Clock Generator Achieving 23fJ/Cycle in
28nm CMOS, Sander Derksen1, Maël Demarets2,3, Gerard Villar Piqué1, Fabio Sebastiano3 1NXP
Semiconductors, 2KU Leuven, 3Delft University of Technology
The proposed VCO comprises two voltage-stacked coupled ring oscillators, one tied to vdd and one tied
to gnd, each driving part of a level-shifter circuit to prevent short-circuit currents, thus generating a railto-rail clock with high energy efficiency. As a potential application, the VCO is embedded in a duty-cycled
RC-based FLL. In 28nm CMOS, the VCO and the FLL draw 7.4nA and 26nA from the nominal 0.9V supply,
respectively, while delivering a 1MHz rail-to-rail output clock.
10:40 AM

C11.2 A 94fsrms-Jitter and −249.3dB FoM 4.0GHz Ring-Oscillator-based MDLL with
Background Calibration of Phase Offset and Injection Slope Mismatch, Dongjun Park,
Heesung Roh, Seon-Kyoo Lee, and Jae-Yoon Sim, POSTECHThis paper presents a ring oscillator (RO)-based multiplying delay-locked loop (MDLL) with frequency andslope detector (FSD) that can control both the oscillation frequency and the injection signal slope. By
comparing characteristics of two consecutive transitions of the RO before and after the injection, the FSD
distinguishes the cause of error, i.e., mismatch in period or slope. Hence, it can individually drive twoloops; 1) for locking the steady-state frequency of the RO and 2) for matching the transition slope of thereference edge to that of the internal node of the RO. As the proposed FSD efficiently mitigates each jittersource, the chip, implemented in 40nm CMOS, shows an integrated rms jitter of 94fsrms at 4GHz,
achieving a FoM of -249.3dB.
11:05 AM
C11.3 A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit
Reference Frequency Doubling, Sayan Kumar1, Patchara Sawakewang1, Teerachot Siriburanon1, Robert
Bogdan Staszewski1 1University College Dublin
We propose a ping-pong charge-sharing locking (PP-CSL) PLL which injects charge into the oscillator tank
employing complemen- tary charge-sharing capacitors (Cshared) during both positive and negativereference clock (fREF) transitions, resulting in an implicit 2x multiplication. The proposed frequencytracking loop (FTL) and duty-cycle calibrations (DCC) are achieved simultaneously by monitoring thecharge residue on Cshared. Implemented in 28 nm CMOS, the ∼27 GHz PLL achieves 42 fs of rms jitter
while consuming only 14 mW with fREF of 250 MHz, leading to FoMjitter−N of -276.6 dB.
11:30 AM
C11.4 A 3.2GHz-15GHz Low Jitter Resonant Clock Featuring Rotary Traveling Wave Oscillators in Intel
4 CMOS for 3D Heterogeneous Multi-Die Systems, Vinayak Honkote1, Ragh Kuttappa1, Jainaveen
Sundaram1, Satish Yada1, Chinnusamy Kalimuthu1, Juhi Patil1, Richard Lee1, Cristan Paulino1, Paolo

Aseron1, Trang Nguyen1, Amreesh Rao1, Dileep Kurian1, Mingming Xu1, Yan Song1, Tanay Karnik1, Anuradha
Srinivasan1, Vivek De1 1Intel Corporation.
We present a resonant clocking technique featuring rotary traveling wave oscillators (RTWOs) and a rotary
oscillatory array (ROA) in Intel 4 CMOS for high-frequency, low-jitter, low-power and low-skew clock
generation and distribution in 3D heterogeneous multi-die systems. The active base die incorporates anarray of four coupled RTWOs capable of dynamic frequency tuning. Three independent resonant rotaryrings are implemented to demonstrate the range of native resonant frequencies with very low jitter. The
circuits operate across a wide frequency (3.2GHz-15GHz) and voltage (0.55V-1.2V) range with very low
measured period jitter (107fs-705fs) and minimal duty-cycle distortion (50±0.8%) suitable for multi-die
high-performance GPUs.
Session C12: Sensors for Audio and Video
10:15 AM, Honolulu 3
Co-Chairs:

Inhee Lee, University of Pittsburgh
Noriyuki Miura, Osaka University

10:15 AM
C12.1 23,000-Exposures/s 360fps-Readout Software-Defined Image Sensor with Motion-Adaptive
Spatially Varying Imaging Speed, Roberto Rangel1, Xiaonong Sun1, Ayandev Barman1, Rahul Gulve1, Savo
Bajic1, Jingmin Wang1, Harry Wang1, David B. Lindell1, Kiriakos N. Kutulakos1, Roman Genov1 1University ofTorontoThe software-defined VGA image sensor adapts to fast changes in the scene, both locally and globally, by
taking advantage of programmable-size/speed super-pixels and scalable-rate SAR ADCs, respectively.
Each super-pixel includes up to 8x8 pixels exposed in a rapid sequence within one frame period, yielding
a 64x maximum boost of the exposure rate over the output rate, without the corresponding increase in
the ADC power. At 360fps readout, this corresponds to over 23,000 exposures/s while using only 24.5mW,
and comes at the cost of moderately lower local resolution, only in the regions with the fast changes inthe scene. The 54fJ-FoM SAR ADC allows for scaling down to the 30fps ‘slow’ mode, yielding an additional
factor of 12x savings in the output data and camera digital power, and 30% savings in the ADC power.
10:40 AM
C12.2 A 450μW@50fps Wake-Up Module Featuring Auto-Bracketed 3-Scale Log-Corrected Pattern
Recognition and Motion Detection in a 1.5Mpix 8T Global Shutter Imager, Arnaud Verdant1, William
Guicquero1, David Coriat1, Guillaume Moritz1, Nicolas Royer1, Sébastien Thuries1, Anaïs Mollard2, Vincent
Teil2, Yann Desprez2, Gilles Monnot2, Pierre Malinge2, Bruno Paille2, Guillaume Caubit2, Arnaud Bourge2,
Laurent Tardif2, Stéphanie Bigault2, Jérôme Chossat2 1CEA Leti, 2STMicroelectronics
Megapixel imagers with computer vision capabilities exhibit high acquisition performance at the expenseof a power consumption preventing always-on usage. This paper presents ATIM, a wake-up solution forboth 3-scale pattern recognition and motion detection, that is added to a 1360×1120 Global-Shutter
commercial CIS without impairing image quality in standard readout modes. ATIM relies on selfadaptation to ambient light conditions, to improve algorithmic robustness for real-world scenarios. This
module captures 9×9-downsampled 8b images using a dedicated readout and processes 6b 152×112
frames, under an overall power budget of ~450µW at 50fps.
11:05 AM
C12.3 A 430-μA 68.2-dB-SNR 133-dBSPL-AOP CMOS-MEMS Digital Microphone based on Electrostatic
Force Feedback Control, Qi Zhang1, Jiaqi Dong1,2, Xinwen Zhang1, Yekan Chen1,2,3, Zipeng Cheng1, Bo Zhao1,

Yuxuan Luo1,2,4 1Zhejiang University, 2ZJU-Hangzhou Global Scientific and Technological Innovation
Center, 3Microaiot, 4Stomatology Hospital, School of Medicine, Zhejiang University
This paper presents a high-dynamic-range CMOS-MEMS digital microphone based on electrostatic force
feedback control (EFFC). We propose to adjust the sensitivity of the capacitive acoustic transducer
according to the input acoustic volume by adaptively biasing it at different voltages, so its acoustic
dynamic range (DR) can be extended. A sub-sampling amplitude detector (SSAD) is proposed to achieve
fast and efficient acoustic volume detection. The volume detection result controls a fast-settling predictive
referenced charge pump (PRCP) to provide closed-loop EFFC. The proposed solution achieves a signal-tonoise ratio (SNR) of 68.2 dB at 94 dBSPL and an acoustic overload point (AOP) of 133 dBSPL with 430 μA
at CLKIN= 3.072 MHz. The measured acoustic DR is 107.2 dB.
11:30 AM
C12.4 A 1.5 V 132 dBSPL AOP Digital Readout Circuit for MEMS Microphone Using Self-Adaption
Loop, Ling Wang1, Longjie Zhong1, Zhangming Zhu1 1Key Laboratory of Analog Integrated Circuits andSystems (Ministry of Education), School of Integrated Circuits, Xidian University
This work presents a digital readout integrate circuit (IC) for capacitive MEMS microphone, which features
a self-adaption loop (SAL), allowing the single-ended system to process high sound pressure signals. A
prototype is realized in a 0.153 μm CMOS process, performing 67.34 dB-A SNR at 94 dB SoundPressureLevel (SPL) with an acoustic overload point (AOP) of 132 dB SPL, consuming 738 μA at 1.5 V supply voltage.
Session TFS1: Oxide Semiconductor Applications in BEOL
1:00 PM, Tapa 1
Co-Chairs:

Srabanti Chowdhury, Stanford University
Tuo-Hung Hou, National Yang Ming Chiao Tung University

1:00 PM
TFS1.1 Amorphous Oxide Semiconductors for Monolithic 3D Integrated Circuits (Invited), Suman
Datta1, Shimeng Yu1, Asif Khan1, Sunbin Deng1, Khandker Akif Aabrar1, Jungyoun Kwak1 1Georgia Tech
AOS FETs, with low leakage current, satisfactory carrier mobility and BEOL compatibility can enable dense
memory on top of CMOS. Redesigned AOS FETs with high breakdown voltage can support efficient power
delivery solutions. Such versatility positions AOS FETs to meet the evolving demands of heterogeneouscompute, reshaping the technology landscape of memory and power delivery.
1:25 PM
TFS1.2 P-type SnO Semiconductor Transistor and Application (Invited), Chun-Chen Wang1,2, ChengChen Kuo1, Cheng-Hsien Wu1, Anni Lu1,3, Heng-Yuan Lee1, Chen-Feng Hsu1, Pei-Jer Tzeng1, Tung-Ying Lee1,
Fa-Rong Hou4, Ming-Han Chang5, Sheng-Chih Lai1, Ken-Ichi Goto1, Shimeng Yu3, Chih-I Wu2,4,5, C.T. Lin1, YuMing Lin1, Xin-Yu Bao1 1Taiwan Semiconductor Manufacturing Company, Ltd., 2Graduate School of
Advanced Technology, National Taiwan University, 3Georgia Institute of Technology, 4Graduate Instituteof Electronics Engineering, National Taiwan University, 5Graduate Institute of Photonics andOptoelectronics, National Taiwan University
In this work, high-quality p-type SnO material is developed by PVD deposition. Sub-100 nm short channel
p-SnO devices are first demonstrated with current density 10~20 μA/μm, Ion/Ioff over 104, SS ~0.4 V/dec
and hole mobility ~2 cm2/Vs. The benefits of monolithic 3D integration with oxide transistors in BEOL areprojected using FPGA as example.
1:50 PMTFS1.3 Demonstration of On-Chip Switched-Capacitor DC-DC Converters using BEOL Compatible Oxide
Power Transistors and Superlattice MIM Capacitors, Sunbin Deng1, Jungyoun Kwak1, Junmo Lee1,
Dyutimoy Chakraborty1, Jaewon Shin1, Omkar Phadke1, Sharadindu Gopal Kirtania1, Chengyang Zhang1,
Khandker Akif Aabrar1, Shimeng Yu1, Suman Datta1 1Georgia Institute of Technology
Through monolithic integration of back-end-of-line (BEOL) compatible enhancement and depletion-mode
tungsten-doped indium oxide (IWO) power transistors and high-voltage (HV) superlattice capacitors, we
experimentally demonstrate, for the first time, an on-chip switched-capacitor (SC) DC-DC converter tosupport efficient power delivery in heterogeneous integrated circuits. A novel oxygen anneal treatment
to the power transistors markedly improved the reliability of the transistors with a >4× reduction inVth shift. The fabricated converter circuit achieved 12V-to-6V conversion with an efficiency of 82.8%. A
projected power density of 1.03 W/mm2 could be achieved by transitioning to 3D trench capacitors fromcurrent planar form.
2:15 PM
TFS1.4 First Experimental Demonstration of Hybrid Gain Cell Memory with Si PMOS and ITO FET for
High-speed On-chip Memory, Shuhan Liu1, Shengjun Qin1, Koustav Jana1, Jian Chen1, Kasidit
Toprasertpong1, H.-S. Philip Wong1 1Stanford University
This work experimentally demonstrates hybrid gain cell memory with Si PMOS as read transistor and ITO
FET as write transistor integrated monolithically on the same chip. With Si PMOS as the read transistor,
hybrid gain cell memory has the benefits of high read speed, counterbalanced capacitive coupling,
optimized state allocation, and superb bias stress stability. Fabricated Si PMOS has mobility of 86.4 cm2/Vs
and the ALD ITO FET has positive VTH = 0.75 V and excellent SS = 65 mV/dec. Hybrid gain cell shows
measured retention of 5,000 sec under 0V WWL standby voltage. Excellent stability of < 12 mV shift for Si
PMOS and ITO FET under 1,000 sec bias stress in standby mode is achieved.
2:40 PM
TFS1.5 On the Reliability of High-Performance Dual Gate (DG) W-doped In2O3 FET, Khandker Akif
Aabrar1, Hyeonwoo Park1, Suman Datta1, Sharadindu Kirtania Gopal1, Sunbin Deng1, Chengyang Zhang1,
Md Abdullah Al Mamun2, Kyeongjae Cho2, Gilbert B. Rayner Jr3 1Georgia Institute ofTechnology, 2University of Texas at Dallas, 3Kurt J Lesker
We demonstrate a high performance back-end-of-line (BEOL) compatible tungsten (W)-doped
In2O3 channel (IWO) dual gate (DG) field-effect transistor (FET) with ultra low-leakage current <10-15 A/µm
and high ION/IOFF ratio of 5.8x1011 at 2.5V overdrive (Vov). In addition, the IWO DG FET demonstrates arecord low negative bias temperature instability (NBTI) of 7.2mV, record low hot carrier degradation(HCD) of 63mV and a low positive bias temperature instability (PBTI) of 85mV at 1V Vov which makes IWO
DG FET a potential candidate for realizing high density embedded-DRAM for last-level cache (LLC).
Furthermore, we develop a comprehensive modeling framework for assesing the reliability of amorphousoxide semiconductor (AOS) channel FETs which can provide insights into the threshold voltage (VT)instability mechanisms and help design appropriate mitigation strategies.
Session T6: Memory Technology: NAND, DRAM-1
1:00 PM, Tapa 2
Co-Chairs:
1:00 PM

Jixin Yu, Western Digital Corp
Yuri Masuoka, Samsung Electronics

T6.1 Fluorine-free Word Line Molybdenum Process for Enhancing Scalability and Reliability in 3D
Flash Memory, Takashi Fukushima1, Takayuki Kashima1, Satoshi Seto1, Hiroyuki Ohtori1, Masaki Kato1,
Kaihei Katou1, Hiroshi Takehira1, Yohei Sugawara1, Zhiyao Zhu1, Kazushi Hara1, Ryota Osanai1, Takayuki
Beppu1, Hiroko Tahara1, Tatsuya Ishiku1, Kensei Takahashi1, Tomotaka Ariga1, Yu Ueda2, Yuya Matamura2,
Yusuke Mukae2, Naoki Takeguchi2, Yosuke Maruyama1, Ryo Nishikawa1, Hakuba Kitagawa1, Jun Asakawa1,
Yasuhiro Uchiyama1, Kazuya Ohuchi1, Katsuyuki Sekine1 1Kioxia Corporation, 2Western Digital Corporation
A state-of-the-art fluorine-free word line (WL) molybdenum (Mo) process has been established for future
3D flash memory. Application of Mo to WLs can accelerate scaling of cells in both the vertical andhorizontal directions with lower RC delay and lower leakage failure rates compared to traditional
tungsten. In addition to being fluorine-free, key attributes of the process are optimization of Mo recess
by innovative chemical and improvement of Mo filling to remove oxygen residue in Mo voids. These
techniques can extend the scaling limit of 3D flash memory.
1:25 PMT6.2 Innovative Barrier Metal-less Metal Gate Scheme leading to Highly Reliable Cell Characteristics
for 8th Generation 512Gb 3D NAND Flash Memory, Hang-Ah Park1, Sejun Park1, Min-Tai Yu1, Ye-Chan
Kim1, Cheon Ho Park1, Jung Hoon Lee1, Jun Eon Jin1, Dawoon Jeung1, Hauk Han1, Tai-Soo Lim1, Min-Kyu
Jeong1, Mincheol Park1, Bong-Tae Park1, Sung Hoi Hur1 1Samsung Electronics Co., Ltd.
We have successfully developed an innovative barrier metal (BM)-less metal gate scheme with high cellreliability for the 8th generation 3D NAND flash memory. This scheme allows the memory cells tosignificantly lower the wordline resistance by 30%, enabling a dramatic scale-down in the lateraldimension of a multi-pillar block architecture in 3D NAND. In addition, both cell interference and verticalcharge loss can be enhanced by increasing fluorine (F) passivation at the trap sites in the blocking oxide(BOX). Ingenious technologies are developed to suppress degradations originating from the work functionchange and increased F concentration in tungsten (W) gates. Finally, enhanced cell reliabilities, inclusiveof high cycle endurance and long term retention, can be acquired for the 8th generation 512Gb 3D NAND
product. Our BM-less metal gate structure provides a novel approach to designing highly competitive
future-generation 3D NAND flash memory.
1:50 PMT6.3 Mechanical Stress Effects on Dielectric Leakage and Interconnection Integrity in 3D NAND Flash
Memory, Se Hoon Lee1 1Samsung Electronics Co., Ltd.
This paper presents a comprehensive study of stress-induced leakage in dielectrics, combining structural
analysis with electrical transport properties in the latest 3D NAND Flash memory products. Stress-induced
leakage is prominently observed near wide aluminum metal patterns, as changes in stress and strain
significantly influence the dielectric properties. Through electrical analysis and DFT simulations, we
successfully analyzed electrical transport phenomenon, which is explained by Schottky emission withdecreased electrical barrier height in amorphous SiO2 under tensile stress. We also proposed process
improvements, including adjustments in annealing temperature and air-gap to mitigate leakage issues.
2:15 PMT6.4 Up to 57% Reduction in Effective Resistivity of Word Lines of 3D-NAND Memory by Grain-size
Control, Material Selection, and Seam Removal, Hiroshi Terada1, Katsumasa Yamaguchi2, Tsubasa Yokoi2,
Takashi Sameshima2, Keisuke Suzuki2, Genji Nakamura1, Hiroyuki Nagai1 1Tokyo Electron Ltd., 2Tokyo
Electron Technology Solutions Ltd.
In this work, we systematically studied the effective resistivity of word lines (WLs) of 3D NAND memory.
We fabricated narrow and high-aspect-ratio wires in the similar way to the WL forming process of
replacement-gate NAND and measured the resistivity of the wires. By using TiAlN liner, we increased grain

size of W and achieved resistivity reduction. In addition, we found that the resistivities of the wires areequal to that of the blanket with half thickness, which indicates that the influence of electron scattering
at a seam cannot be ignored in WL resistance. We demonstrated the resistivity reduction by closing seams
with post-metal anneal and achieved 57% reduction in resistivity at liner-less and seam-less Mo compared
to conventional W/TiN.
2:40 PMT6.5 A Metal Dual Work-function Gate (MDWG) for the continuous scaling of DRAM Cell
Transistors, Junsoo Kim1 1Samsung Electronics
For the continuous scale-down of DRAM cell transistors, we have demonstrated, for the first time, a metal
dual work function gate (MDWG) by replacing n+ Poly Si with an Oxide/La/TiN structure in a fully
integrated DRAM.
Session TFS2: Backside of Silicon: From Power Delivery to Signaling
1:00 PM, Tapa 3
Co-Chairs:

Seung-Chul Song, Google
Aaron Thean, National University of Singapore

1:00 PM
TFS2.1 Expanding Design Technology Co-Optimization Potentials with Back-Side Interconnect
Innovation (Invited), Byung-Sung Kim1, Subin Choi1, Jung Han Lee1, Kwangmuk Lee1, Jisoo Park1, Jiwook
Kwon1, Saehan Park1, Kwanyoung Chun1, Harsono Simka1, Aravindh Kumar1, Muhammed Ahosan Ul
Karim1, Ken Rim1, Jaihyuk Song1 1Samsung Electronics
This report analyzes the benefits obtained through Back-Side Interconnect (BSI) technology,
encompassing Back-Side Power Delivery Network (BSPDN) and Back-Side Signal (BSS), from theperspective of Design-Technology Co-Optimization (DTCO). Through BSPDN, benefits such as metal pitch
relaxation and/or cell height reduction can be achieved. Additionally, the implementation of BSS
technology allows for intra-cell and inter-cell routing on the back side, leading to improved speed andgreater reduction in cell area.
1:25 PM
TFS2.2 A Design Methodology for Back-side Power and Clock Routing Co-Optimization (Invited), Pruek
Vanna-iampikul1, Hang Yang1, Jungyoun Kwak1, Joyce X Hu1, Amaan Rahman1, Nesara Eranna Bethur1,
Cong Hao1, Shimeng Yu1, Sung Kyu Lim1 1Georgia Institute of Technology
This paper presents a backside (BS) design methodology for optimizing both power delivery network(PDN) and clock routing in 3nm. A unit converter (UC) has been integrated on the backside with BS-PDN
to minimize dynamic IR-drop. Additionally, our backside buffer cell with backside contact enables backside
clock routing. Experimental results show that BS-PDN mitigates 57.7% IR-drop compared to FS-PDN, andUC integration further reduces IR-drop by 10.3% and package IR-drop by 83.9%. Our backside clock routing
improves clock power by 32% and full-chip power-delay product by 13.6%.
1:50 PM
TFS2.3 Backside power distribution for nanosheet technologies beyond 2nm, Ruilong Xie1, Wonhyuk
Hong2, Chen Zhang1, Jongjin Lee2, Kevin Brew1, Richard Johnson1, Nicholas Lanzillo1, Hosadurga Shobha1,
Taesun Kim2, Panjae Park2, Shogo Mochizuki1, Iqbal Saraf1, Chanro Park1, Lei Zhuang1, Clifford Osborn1,
Wai Kin Li1, Feng Liu1, Muthumanickam Sankarapandian1, Chung Ju Yang1, Juntao Li1, Lukas Tierney1,
Ruturaj Pujari1, Yasir Sulehria1, Yuncheng Song1, Huimei Zhou1, Miaomiao Wang1, Michael Belyansky1,

Somnath Ghosh1, Haojun Zhang1, Koichi Motoyama1, Debarghya Sarkar1, Wukang Kim1, Albert Chu1, Tao
Li1, Fabio Carta1, Oleg Gluschenkov1, Joongsuk Oh2, Matthew Malley1, Pinlei Chu1, Son Nguyen1, Katherine
Luedders1, Joe Lee1, Shahrukh Khan1, Prabudhya Roy Chowdhury1, Huai Huang1, Abir Shadman1, Stuart
Sieg1, Daniel Dechene1, Daniel Edelstein1, John Arnold1, Tenko Yamashita1, Kisik Choi1, Kang-ill Seo2,
Dechao Guo1, Huiming Bu1 1IBM, 2Samsung
This paper examines various approaches for integrating backside power distribution network (BSPDN)
with nanosheet transistor technologies. Deep Trench Via (DTV) based BSPDN schemes, except for Shifted
Frontside Via Backside Power rail (SFVBP), do not offer cell level scaling benefits, but via resistance of
SFVBP could remain a bottleneck. Direct Backside Contact (DBC) based schemes offer best cell levelscaling. A novel self-aligned backside contact (SABC) scheme integrated with nanosheet transistors isdemonstrated with immunity to misalignments in backside contact formation. The structure exhibits good
device characteristics and satisfactory reliability.
2:15 PM
TFS2.4 Demonstration of Logic-Block Performance-Power Gain by 1st Generation Back Side Power
Delivery Network for SoC and HPC Applications beyond 2nm Node, Hidenobu Fukutome1, Jinkyu Kim1,
Jaehoon Shin1, Jeewoong Kim1, Yongwoo Lee1, Yoonbeom Park1, Darong Oh1, Soohang Chae1, Byeolhae
Eom1, Yun Suk Nam1, Minsung Lee1, Seungseok Ha1, Eun Guk Chung1, J. Kim1, M. Jo1, S. H. Lee1, S. Kim1,
Keun Hwi Cho1, Kyoung-Woo Lee1, Dong-won Kim1, Hag-Ju Cho1, Ken Rim1, San Duk Kwon1, Jaihyuk Song1
1
Samsung Electronics Co., Ltd.
We have experimentally demonstrated effects of BSPDN on performance-power of standard cell featuringGate-all-around (GAA) FETs scaled down for SoC technology beyond 2nm node for the first time.
1st generation (Gen) BSPDN provides high immunity of cell-level leakage with ultra-scaled cell height andwe achieve 6% speed gain by optimizing metal routing. As a result, 1st Gen BSPDN could make it possible
to achieve 7.5% performance or 5% power gain compared to FSPDN with logic and SRAM test chip
verification.
2:40 PM
TFS2.5 Backside Power Delivery in High Density and High Performance Context: IR-drop and Block-level
Power-Performance-Area Benefits, Yun Zhou1, S.C. Song2, Halil Kukner1, Giuliano Sisto1, Sheng Yang1,
Anita Farokhnejad1, Mohamed Naeim1,3, Moritz Brunion1, Ji-Yung Lin1, Odysseas Zografos1, Pieter Weckx1,
Shashank Ekbote2, Nick Stevens-Yu2, David Greenlawn2, Steve Molloy2, Geert Hellings1, Julien Ryckaert1
1
imec, 2Google LLC, 3Cadence Design Systems
We evaluate block-level power-performance-area (PPA) tradeoffs of two backside power (BSPDN)
options: Through Silicon Via in the Middle of Line (TSVM) and Backside Contact (BSC) in an A10 (10Å)
nanosheet technology node. The benchmarking was conducted for high-performance designs in both
high-performance and high-density technology scenarios taking the traditional frontside power option as
the baseline. HP technology clearly benefits most since its dense PDN consumes a lot of metal routing
resources on the frontside to keep an acceptable IR-drop. Introducing BSPDN frees up those metals formore efficient signal routing, resulting in 19% smaller area (8% for HD). Continued standard cell scaling bymeans of BSC translates into a further -25% core area, with only the densest 4.5T HD results showing signsof congestion at high frequencies.
Session C13: Security
1:00 PM, Honolulu 1
Co-Chairs:

Kevin Kornegay, Morgan State University
Makoto Takamiya, The University of Tokyo1:00 PM
C13.1 Empowering Local Differential Privacy: A 5718 TOPS/W Analog PUF-based In-Memory
Encryption Macro for Dynamic Edge Security, Chih-Sheng Lin1, Bo-Cheng Chiou1, Yin-Jia Yang2, Jian-Wei
Su1, Kuo-Hua Tseng1, Yun-Ting Ho1, Chih-Ming Lai1, Sih-Han Li1, Tian-Sheuan Chang2, Shan-Ming Chang1,
Shyh-Shyuan Sheu1, Wei-Chung Lo1, Shih-Chieh Chang1, Tuo-Hung Hou2 1Industrial Technology ResearchInstitute, 2National Yang Ming Chiao Tung University
In the realm of artificial intelligence (AI), data privacy is crucial. This study demonstrates the first InMemory Encryption (IME) macro utilizing analog Physical Unclonable Function (aPUF) for efficient local
differential privacy (LDP). The hardware utilizes a highly parallel 22-nm SRAM 4b/4b/5b (I/W/O) analog
in-memory computation (aIMC) macro. Sense amplifier (SA) variation and a time-based confusion (TBC)
circuit generate time-varying noise, enhancing dynamic LDP protecting strength to 4.2. Furthermore, theenergy efficiency of 5718 TOPS/W underscores significant advancements in robust protection withoutcompromising high energy efficiency, particularly benefiting edge LDP security.
1:25 PM
C13.2 A 4.7-to-5.3Gbps Fault-Injection Attack Resistant AES-256 Engine Using Isomorphic Composite
Fields in Intel 4 CMOS, Raghavan Kumar1, Sachin Taneja1, Vivek De1, Sanu Mathew1 1IntelA fault-injection attack (FIA) resistant AES-256 engine with 100% exploitable fault coverage is fabricatedin Intel 4 CMOS. Redundant round computations using isomorphic GF(24)2 composite-field
implementations and reconfigurable byte dataflow enable real-time detection of corrupted ciphertexts,
while limiting area overhead to 12%. Additive masking circuits with redundant round computations show
no side-channel information leakage from 1B traces.
1:50 PM
C13.3 A 67F2 Reconfigurable PUF Using 1T2R RRAM Switching Competition in 28nm CMOS with 5e-9
Bit Error Rate, Yue Cao1, Honghu Yang2, Jianguo Yang3, Qi Liu1, Ming Liu1 1Fudan University, 2ZhangjiangLab, 3Institute of Microelectronics of the Chinese Academy of Sciences
Aiming at low-cost, high-reliability hardware security in IoT applications, we demonstrated a 1Mb 1T2R
RRAM Reconfigurable PUF design. A 1T2R PUF cell with a smaller size utilizes the switch time variation in
the RRAM device as the entropy source, and an initialization-extraction process that exploits the cycle-tocycle switch time variation is proposed to enable PUF reconfiguration. A self-adaptive extraction circuit
and a reprogram calibration scheme are designed to improve operation power and native BER. Moreover,a symmetrical read scheme is employed to enhance power analysis resilience, by balancing the power
during PUF readout. The test chip achieves a cell size of 67F2 and a native (calibrated) BER of 0.021% (<5e-9) with good resilience to machine learning attacks.
2:15 PM
C13.4 An In-Sensor PUF Featuring Optical Reconfigurability and Near-100% Hardware Reuse Ratio for
Trustworthy Sensing, Xiaojin Zhao1, Haibiao Zuo1, Xiaoliang Huang1, Shiqiao Zhang1, Chip-Hong Chang2
1
Shenzhen University, 2Nanyang Technological University
Mainstream CMOS image sensors are in dire need of having built-in security primitive to facilitate on-chiptrustworthy sensing for the attestation of the visual content integrity against photo-realistic spoofing
attacks made feasible by the emerging generative artificial intelligence (AI) tools. This paper presents an
optically reconfigurable in-sensor strong physically unclonable function (PUF) leveraging both intrinsic
dark signal non-uniformity (DSNU) and photo response non-uniformity (PRNU) of photo sensing pixels as
entropy sources. The fabricated 128×128 in-sensor PUF chip features 99.735% hardware reuse ratio,

~1×1036bit/F2 area efficiency, ≈2.77×1042 challenge-response pairs (CRP) and high resistance against
several well-known machine-learning attacks.
2:40 PM
C13.5 A 65nm Delta-Sigma ADC based VDD-Variation-Tolerant Power-Side-Channel-Attack Monitor
with Detection Capability down to 0.25Ω, Shota Konno1,2, Zachary J Ellis2, Anupam Golder2, Sigang Ryu2,
Daniel Dinu3, Avinash Varna3, Sanu Mathew3, Arijit Raychowdhury2 1Asahi Kasei Microdevices
Corporation, 2Georgia Institute of Technology, 3Intel Corporation
In this work, a Delta-Sigma ADC based Power Side Channel Attack Monitor is proposed to accurately detect
insertion of less than 1Ω. A differential conversion method utilizing Dual Integrate CAP provides signal
processing to compensate for drift due to VDD variations, achieving a minimum detectable resistance of
0.25Ω including VDD variations. The ultra-low power consumption of 50uW during operation makes itsuitable for IoT-secure devices.
Session C14: Very High-Speed Wireline
1:00 PM, Honolulu 2
Co-Chairs:

Zhipeng Li, Marvell Semiconductor
C. Patrick Yue, Hong Kong University of Science and Technology

1:00 PM
C14.1 A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9µm-pitch 3D Package
Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4, Mu-Shan Lin1, Chien-Chun Tsai1, Shenggao Li1, TzeChiang Huang1, Wen-Hung Huang1, Kate Huang1, Yu-Chi Chen1, Alex Liu1, Yu-Jie Huang1, Jimmy Wang1,
Shu-Chun Yang1, Nai-Chen Cheng1, Chao-Chieh Li1, Hsin-Hung Kuo1, Wei-Chih Chen1, C.H. Wen1, Kevin Lin1,
Po-Yi Huang1, Kenny Cheng-Hsiang Hsieh1, Frank Lee1 1TSMC
This paper presents a die-to-die link with a compute die in 5nm FinFET and a SRAM die in 6nm FinFET,
with a face-to-back 3D stacking at a 9μm bond pitch. Modular design that supports full scalability isdemonstrated, achieving a 10.24Tb/s aggregate bandwidth for 320 Tx lanes and 320 Rx lanes, at a PAM-4
16Gb/s per lane data rate. Each data cluster is designed with 80 Tx/Rx lanes in a 378μm*378μm footprint,
achieving a bandwidth density of 17.9Tb/s/mm2 and an energy efficiency of 0.296pJ/bit per link.
1:25 PMC14.2 A 1.1pJ/b/lane, 1.8Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with
Signal Equalization and Envelope Adaptation using TX-FFE in 5nm CMOS, Gautam Gangasani1, A
Mostafa1, A Singh1, D storaska1, D Prabakaran1, K mohammad1, M baecher1, M shannon1, M sorna1, M
wielgos1, P Jenkins1, P Ramakrishna1, U Shukla1 1Marvell Technology Inc.
This paper uses 113Gb/s PAM4 transceiver in 5nm CMOS to demonstrate a 1.8Tb/s chiplet, over die-todie extremely short-reach (XSR) intra-package links, in a 8-port configuration. The 16-channels range from
1dB-12dB of loss at Fbaud/2 The chiplet performance over these channels is better than BER<10-9, while
consuming <1.1pJ/b power and 0.22mm2 area per lane.
1:50 PM
C14.3 A 0.9pj/b 9.8-113Gb/s XSR Serdes with 6-tap TX FFE and AC coupling RX in 3nm FinFet
Technology, A. Chowdhury1, J. Ma2, Y. Li2, J. Guo2, X. Zhang2, P. Ramakrishna3, J. Gu2, Y. Wang2, L. Liang2,
U. Shukla3, K. Mohammad3, H. Yan2, Y. Sun2, M. Lin2, Z. Jiang2, F. Khan2, M. Yeoh2, C. Su2, J. Ding2, M.

Baecher4, S. Parker4, H. Wang2, M. Seymour4, M. Wielgos4, Ken Chang2 1Marvell Technology, 2Marvell
Technology, Santa Clara, CA, 3Marvell Technology Inc., 4Marvell Technology
This paper presents an OIF CEI-1125G-XSR compliant short-reach SerDes with data rate from 9.8 to113Gb/s PAM4/NRZ, implemented in 3nm finfet technology. The quarter-rate source-series terminated(SST) transmitter is implemented with 2UI-delay based MUX, supply adjusted and impedance calibrated
DAC driver to maintain constant TX swing across PVT. The receiver utilizes a unique AC-coupling-based
method before and after single-stage CTLE with 4 edge and 12 data samplers. The design has a standard
3 taps FFE and an optional 6 taps FFE, as well as continuous adapted RX CTLE to track temperature drift
and achieve BER<1e-14 below 8dB and <1e-12 for loss up to 10dB on both 2D and advanced 2.5D CoWoS
package.
2:15 PM
C14.4 A 4x50Gb/s NRZ 1.5pJ/b Co-Packaged and Fiber-Terminated 4-Channel Optical RX, Sashank
Krishnamurthy1, Susnata Mondal1, Junyi Qiu1, Joseph Kennedy1, Soumya Bose1, Tolga Acikalin1, Shuhei
Yamada1, James Jaussi1, Mozhgan Mansuri1 1Intel Corporation
This paper presents a 4-channel co-packaged optical RX that integrates a photodiode array, fiber
termination and a transimpedance amplifier front end (TIA-FE) IC on the same package as an RX data-path
IC. To achieve high sensitivity, the TIA-FE employs bandwidth extension and in-band group delay
compensation techniques that are co-optimized with a ¼-rate 2-tap feed-forward equalizer (FFE) in the
RX data-path. A StrongArm latch that improves noise variance by 3.5x for iso-power is introduced.
Modulated by its VCSEL-based optical TX counterpart, the optical RX demonstrates 4x50Gb/s NRZ at
1.5pJ/b with BER<1e-12 and a sensitivity of -6dBm.
2:40 PM
C14.5 A 800Gb/s Transceiver for PAM-4 Optical Direct-Detection applications in 5nm FinFet
Process, Marco Sosio1, Fabio Giunco1, Claudio Nani1, Ivan Fabiano1, Travis Lovitt1, Victor Karam1,
Domenico Albano1, Claudio Salvatore Asero1, Nicola Codega2, Marco Garampazzi1, Nicola Ghittori1,
Stanley Ho1, Enrico Monaco1, Benjamin Reyes1, Paolo Rossi1, Enrico Temporiti1, Paolo Pascale1, Fernando
De Bernardinis1, Shawn Scouten1, Stephen Jantzi1 1Marvell Technology, 2Marvell
This paper presents a 5nm Finfet 8x100Gb/s electro-optical transceiver for PAM-4 optical interconnects
covering DR8/2xFR4/LR8 QSFP-DD/OSFP applications. Three chip flavors, differing in only few top metalmasks on TXs, have been implemented providing fully integrated 3Vpp Silicon Photonics (SiPho), 3V Open
Drain (OD) and 1.5Vpp EML drivers. External VCSEL drivers are supported as well. The optical receivers
are DSP based, with the analog consisting of a variable gain amplifier (VGA) and an ADC. The electricalinterface, common to all chips, is compliant with the OIF CEI 112G VSR and IEEE C2M standards. The chip
is available both in package and as a bare die. Both versions meet the form factor and power requirements
for QSFP-DD MSA enabling less than 12W 800G modules
Session C15: Interfaces to the Human Body and Sequencing
1:00 PM, Honolulu 3
Co-Chairs:

1:00 PMArun Manickam, Cepheid
Kenichi Okada, Tokyo Institute of Technology

C15.1 A 76 X 55 X-Ray Energy Binning Dosimeter for Closed-Loop Cancer Radiotherapy, Rahul Lall1,
Kyoungtae Lee2, Adam Cunha2, Rebecca Abergel1, Youngho Seo1,2, Ali Niknejad1, Mekhail Anwar1,2
1
University of California, Berkeley, 2University of California, San Francisco
X-ray radiation dose delivered during cancer radiotherapy is nonlinear with biological effect on cancer
cells and healthy tissues, necessitating an understanding of X-ray energy deposition at the single photon
level. Here we present a single X-ray sensitive, energy binning ASIC to enable closed-loop cancer
radiotherapy to personalize patient treatment. We use deep n-well (DNWELL) diodes designed at low
capacitive nodes (Cdiode), such that the miniscule energy deposition from single X-rays at these nodes
generates a voltage signal large enough to be sensed (Vdiode=Qdep/Cdiode), where Vdiode ∝ energy deposited.
To enable single photon energy resolution without the significant power and area of high resolution ADCs,
we implement an analog voltage supply (AVDDH) ~log resistor grid to create a pixel sensitivity gradientfor X-ray energy binning. The ASIC is highly linear with radiation dose (10–250 cGy) and accurately tracks
dose up to 3 cm deep in tissue.
1:25 PM
C15.2 A 2000-Volumes/s 3D Ultrasound Imaging Chip with Monolithically-Integrated
11.7x23.4mm2 2048-Element CMUT Array and Arbitrary-Wave TX Beamformer, Nuriel N.M. Rozsa1, Zhao
Chen2, Taehoon Kim1, Peng Guo1, Yannick Hopf1,3, Jason Voorneveld4, Djalma Simoes dos Santos1, Emile
Noothout1, Zu-Yao Chang1, Chao Chen1,3, Vincent A. Henneken2, Nico de Jong1,4, Hendrik J. Vos1,4, Johan
G. Bosch4, Martin D. Verweij1,4, Michiel A.P. Pertijs1 1Delft University of Technology, 2Philips Innovation &Strategy, 3Sonosilicon, 4Erasmus MC University Medical Center
This work presents an ultrasound imaging chip with monolithically integrated 32×64 element CMUT array,capable of imaging a large field-of-view (FoV) of 60°×60°×10 cm at 2000 vol/s, the highest 3D volume ratereported to date. By combining 2× time-division multiplexing (TDM) with 2×2-element microbeamforming, it reduces the output channelcount 8×. Equalization (EQ), trained using a pseudo-random
bit-sequence (PRBS) generated on-chip, reduces crosstalk caused by TDM by 19 dB, allowing for powerefficient scaling of the on-chip cable drivers. A novel transmit (TX) beamformer, implemented as aprogrammable digital pipeline, enables arbitrary TX beamforming with arbitrary pulse-density modulated(PDM) waveforms and drives element-level 65 V unipolar pulsers. The chip features a layout matched tothe 365- μm-pitch CMUT array, and consumes 1.30 mW/ch.
1:50 PM
C15.3 A Smart Contact Lens System with 433MHz Wireless Power and Data Transfer at a Modulation
Index Down to 0.02%, Heesung Roh1, Hyun Jin Yoo2, Si-Youl Yoo2, Seung Hee Pyen3, Cheonhoo Jeon4, JaeYoon Sim1 1POSTECH, 2Optroth, 3Biiogence, 4Dankook University
This paper presents a wireless power and data transfer system for a low modulation index (MI) of smart
contact lens (SCL). Two chips, Reader and Transponder, co-optimized in a full chain of 433MHz systemenable data communication even at an MI of 0.02%. The bit error rate (BER) at 0.1% MI is less than 4x106, representing an improvement over 250 times compared to the previous best. The full system wasverified in vitro and in vivo with a live rabbit.
2:15 PM
C15.4 An Intra-Body-Power-Transfer System Energized by an Electromagnetic Energy Harvester forPowering Wearable Sensor Nodes, Hyungjoo Cho1, Dongyoon Lee1, Hoyong Sung1, Heewon Choee1, JiHoon Suh1, Injun Choi2, Donghee Cho2, Sohmyung Ha3, Minkyu Je1 1KAIST, 2Samsung Electronics, 3New
York University Abu Dhabi
We present an intra-body-power-transfer (IBPT) system energized by an electromagnetic (EM) energy
harvester (EH). The proposed maximum-power-point-tracking (MPPT) method for EMEH offers simple

implementation and fast MPPT response (or tracking) time. Also, maximum-resonant-power-tracking(MRPT) is employed for the IBPT transmitter (TX) to track the optimal resonance frequency, which varies
by the environment. A demonstration with a shoe-mounted wearable node with the proposed EMEH and
IBPT TX validates the proposed whole IBPT system.
2:40 PM
C15.5 A 28nm Approximate / Binary 6T CAM for Sequence Alignment, Brian Alexander Crafton1,
Samuel Spetalnick1, Muya Chang1, Arijit Raychowdhury1 1Georgia Institute of Technology
A dense 6T CAM implementing exact and approximate search for sequence alignment is presented.
Conventional binary CAM (BCAM) returns a match when the search and stored strings match exactly,
approximate CAM (ACAM) returns a match when the hamming distance (HD) between the search andstored strings is within some tolerance. Using a 6T 28nm SRAM bitcell, high density (2.54 Mb/mm2) isachieved, the macro operates up to 200MHz and consumes 0.77fJ/search/bit (BCAM) and
2.37fJ/search/bit (ACAM).
Session T7: Reliability, Characterization & Modeling of Oxide Semiconductor and Si Devices-1
3:20 PM, Honolulu 1
Co-Chairs:

Ashish Agrawal, Intel Corp
Tetsu Ohtou, Tokyo Electron Ltd.

3:20 PMT7.1 A New Industry Standard Compact Model Integrating TCAD into SPICE, Sanghoon Myung1,
Donggwan Shin1, Kyeyeop Kim1, Yunji Choi1, Gijae Kang1, Songyi Han1, Jaehoon Jeong1, Dae Sin Kim1
1
Samsung Electronics
We present a complete neural compact model (NCM) that can be used in industry for the first time. This
supports not only the features of the standard PDK but also the new features that can vary the process
conditions in SPICE, similar to TCAD simulation. Hence, we dub this “Technology Design Kit (TDK)” todistinguish it from standard PDK. With TDK, we enhanced AC performance by 5% and reduces the
optimization time by 45,000 times compared to traditional DTCO. TDK will be a new industry standard forthe emerging devices in the future.
3:45 PMT7.2 Hot-Carrier-Degradation Characterization for Accurate End-of-Life Prediction with 3nm GAA
Logic Technology Featuring Multi-Bridge-Channel FET, Seongkyung Kim1, Junkyo Jeong1, Eunyu Choi1,
Jinyoung Kim1, Hyewon Shim1, Shinyoung Chung1, Paul Jung1 1Samsung Electronics
In this paper, we report the hot-carrier-degradation characterization of 3nm gate-all-around (GAA) logic
technology featuring multi-bridge-channel ﬁeld-eﬀect transistor (FET) for accurate end-of-life (EOL)
prediction. The commonly used power-law model is compared to the saturation model in wafer level
reliability (WLR). For testing devices over EOL, a long-term hot-carrier-injection (HCI) test is conducted byusing package methodology. The EOL HCI Si degradation value is revealed to be less than half of thecalculated value by the power-law model. The saturation model, predicted from WLR, ﬁts to the long-term
HCI test result. EOL Vmax and %Id show that the saturation model is more accurate for predicting HCI EOL.
AC HCI is conducted to verify width and delay time eﬀects on Id degradation. Id degradation from AC HCIshows that the total width time aﬀects HCI degradation more compared to frequency.
4:10 PMT7.3 Assessment of the transient self-heating effect and its impact on the performance of Watt-level
RF power amplifier in a FinFET technology, Thanh Viet Dinh1, Sai-Wang Tam1, Andries Scholten1, Lisa

Tondelli2, Ralf Pijper1, Sri Kondapalli1, Juan Xie1, Alden Wong1, Ivan To1, Ruben Asanovski2, Luca Selmi2
1
NXP Semiconductors, 2University of Modena and Reggio Emilia
The dynamic behavior of self-heating effect in FinFET devices has a profound impact on the performanceof RF circuits. Hence an accurate assessment of such transient thermal response is critical for designingsuccessfully thermal-sensitive RF blocks in FinFET technology. This work shows, for the first time, aphysics-based multi-stage approach to evaluate the thermal network of a single RF multi-fin multi-finger
FinFET transistor and the power cell comprised of such multiple transistors. This thermal assessment
approach, which has been verified by intensive characterization of both on-wafer and in-packaged RF test
chips, enables the first Watt-level RF power amplifier design in a baseline FinFET node.
4:35 PMT7.4 Unlimited Bi-directional Back-Bias in FD-SOI Technology With New Dual Isolation
Integration, Remy Berthelon1, Olivier Weber1, Frederic Ibars1, Bertrand Revel1, Celine Borowiak1, JeanChristophe Grenier1, Benjamin Dumont1, Simon Desmoulins1, Pierre-Olivier Sassoulas1, Paul Ferreira1,
Stephan Niel1, Stephanie Chouteau1, Rossella Ranica1, Franck Arnaud1, Roberto Gonella1
1
STMicroelectronics
We present a novel dual isolation scheme with standard STI and + a single diffusion break local oxidationof the film in FD-SOI technology, extending its highly efficient back-bias capability. For the first time, both
Forward and Reverse modes are demonstrated on the same ring-oscillator devices from 28nm FD-SOI
technology. A large range of performance/leakage tuning is achieved with record voltage drop across
NMOS and PMOS wells ranging [-3V,+5V]. Leveraging this capability, we experimentally demonstrate aprocess-induced variability reduction of ~50% on Frequency using independent NMOS/PMOS backbiasing in several regimes.
5:00 PMT7.5 First Observation of Time Exponent Variations under Positive Bias Stress on a-IGZO Transistors
Utilizing Ultrafast On-the-Fly Technique with 1 &[micro]s Delay , TAEWON SEO1, CHANGEON JIN1,
Yoonyoung Chung1 1POSTECH
For the first time, we characterized the transition in time exponent (n) of the ∆VTH under positive bias
stress (PBS) on a-IGZO transistors by utilizing the ultrafast on-the-fly (UF-OTF) technique to minimize themeasurement delay (t0) to be 1 µs. Due to the significant noise induced by multiple trap and release (MTR)
conductions in a-IGZO, the precise reliability measurements were not conducted in the sub-millisecond
range. By utilizing the UF-OTF technique with identical measurement and stress voltages, we minimized
the noise and reduced the delay to 1 µs. Our study reveals the transition in n value from 0.2 to 0.4 under
PBS below 4 MV/cm, which was not observed in conventional measurements (t0: ~ 30 ms). Throughcomprehensive analyses, we attribute this behavior to the creation of deep-level states and the transitionof VO2+ to VO inside a-IGZO, respectively.
Session T8: Emerging Non-Volatile Memories - RRAM, FeRAM, PCM, MRAM-1
3:20 PM, Tapa 2
Co-Chairs:

Shimeng Yu, Georgia Institute of Technology
Hang-Ting Lue, Macronix

3:20 PMT8.1 Highly Scalable Vertical Bypass RRAM (VB-RRAM) for 3D V-NAND Memory , Geonhui Han1,
Youngdong Kim1, Jeaseon Kim1, Dongmin Kim1, Yoori Seo1, Jinmyung Choi2, Jinwoo Lee2, Donho Ahn2,
Sechung Oh2, Donghwa Lee1, Hyunsang Hwang1 1POSTECH, 2Samsung electronics

We firstly demonstrate highly scalable interface type RRAM based 3D V-NAND memory with
WOx resistivity switching (RS) layer and IGZO selector transistor (Tr). 3D vertical interface type RRAM
integrated with IGZO Tr (VB-RRAM), utilizing bypass reading between Tr and RS layer, exhibits low voltage
operation (< 5 V), multi-bit (4 bit) capability, and high uniformity of the RS layer while improving thelimitations of on/off ratio. Furthermore, with scaling the channel length down to 30 nm, we achieved fastswitching speed (~ 50 us), stable endurance (> 107 cycles), and low switching energy consumption (5 fJ).
Finally, critical V-NAND issues like read disturbance and interface layer were also evaluated.
3:45 PMT8.2 A Vertical Channel-All-Around FeFET with Thermally Stable Oxide Semiconductor Achieving
High ∆Ion > 2µA/cell for 3D Stackable 4F2 High Speed Memory, Shoichi Kabuyanagi1, Takamasa Hamai1,
Masayuki Murase1, Takeru Maeda1, Masumi Saitoh1, Shosuke Fujii1 1Kioxia Corporation
We demonstrate, for the first time, a 30nm-diameter vertical Channel-All-Around (CAA) ferroelectric FET(FeFET) with TiO2 channel, aiming at 4F2 high speed memory application. Thanks to Gate-Source/Drain
overlap of CAA structure and interface-layer-free nature of oxide semiconductor channel, high ΔIon andstable endurance are simultaneously achieved in the smallest footprint ever (707nm2). Low aspect ratio
FeFET with thermally stable crystallized TiO2 channel facilitates multiple memory stacking. We also show
the scalability of CAA FeFET without performance degradation by contact electrode optimization andspacer oxide engineering, providing a new path for future high density and high speed memory.
4:10 PMT8.3 A Novel Chalcogenide Based CuGeSe Selector Only Memory (SOM) for 3D Xpoint and 3D Vertical
Memory Applications, Wei-Chih Chien1, J.X. Zheng1, C.W. Yeh1, L.M. Gignac2, H.Y. Cheng1, Z.L. Liu1, A.
Grun1, C.L. Sung1, E.K. Lai1, S. Cheng1, C.W. Cheng2, L. Buzi2, A. Ray2, D. Bishop2, R.L. Bruce2, M. BrightSky2,
H.L. Lung1 1Macronix, 2IBM
We present a new selector only memory material, CuGeSe, with low program current, fast switch speed
properties and good endurance. The switching mechanism is studied in depth and element migration isverified during the switching of the material. We also discuss application of the material for 3D Xpoint and3D vertical memory, as well as propose a modified 1/3 V testing scheme for 3D vertical memory to
mitigate leakage current and improve scaling.
4:35 PM
T8.4
First Demonstration of BEOL-Compatible Vertical Fe-NOR, Yang Feng1,2, Dong Zhang1, Zijie
1
Zheng , Chen Sun1, Gan Liu1, Zuopu Zhou1, Jixuan Wu2, Jiezhi Chen2, Xiao Gong1 1Department of Electricaland Computer Engineering, National University of Singapore (NUS), 2School of Information Science andEngineering, Shandong University
For the first time, we present and experimentally demonstrate a Fe-NOR memory unit cell featuring a 3D
stacked structure and side-Fin with the back-end-of-line (BEOL) vertical ZnO channel ferroelectric-metalinsulator-semiconductor (MFMIS) transistor. Capitalizing on the MFMIS architecture's advantages withside-Fin, the proposed unit cell offers a tunable and substantial memory window (MW) accompanied byan on/off ratio (Ion/Ioff) of five orders of magnitude. The utilization of ferroelectric (FE) enables low
switching voltage, leading to low programming voltage (4V) and fast programming speed (200ns) within
the 3D NOR structure. Inspired by computing in memory (CIM) applications, great linearity and endurance
are achieved. Benefiting from the 3D monolithic integration capability of FeFET along with the highdensity flexible structure of 3D FeNOR architecture, this technology holds promise for a diverse array of
applications, including storage-class memory (SCM) and CIM.
5:00 PMT8.5 Reliable Low-voltage FeRAM Capacitors for High-speed Dense Embedded Memory in Advanced
CMOS, Sou-Chi Chang1, Christopher Neumann1, Bernal Granados Alpizar1, Sarah Atanasov1, Jason Peck1,
Nafee Kabir1, Yu-Ching Liao1, Shriram Shivaraman1, Wriddhi Chakraborty1, Nazila Haratipour1, I-Cheng
Tung1, Vladimir Nikitin1, Gary Allen1, Thomas Hoff1, Adedapo Oni1, Tristan Tronic1, Anandi Roy1, Hai Li1,
Fatih Hamzaoglu1, Matthew Metz1, Ian Young1, Jack Kavalieros1, Uygar Avci1 1IntelFor the first time, anti-ferroelectric (AFE) hafnia-based capacitors compatible to advanced CMOS are
demonstrated by (i) bit-line (BL) and plate-line (PL) WRITE (W) voltage scaling down to 1V and 1.3V,
respectively, (ii) BL READ (R) voltage scaling down 0.6V, and (iii) robust 10yr reliability at elevatedtemperature in both fatigue and breakdown, while delivering switching charge for high-speed dense
embedded memory. Also, frequency-dependent endurance in ferroelectric (FE) or AFE hafnia is shown tounveil the worst-case scenario for cache-level memory application as well as complex interactions
between defects and electric field. Finally, 2.4 to 6.5X cell density over SRAM and sub-100fJ W/R cell
energy are projected for embedded FeRAM, showing integrating low-voltage AFE capacitors withadvanced logic has great performance potential for next-generation low-power and high-speed dense
embedded memory.
Session T9: Monolithic and Heterogeneous Integration
3:20 PM, Tapa 3
Co-Chairs:

Mike DeLaus, Analog Devices
Osbert Cheng, UMC

3:20 PM
T9.1 Integration of Si-Interposer and High Density MIM Capacitor on 2.5D Foveros Face-to-Face
Architecture, Chris Pelto1, Daming Wei1, Ravi Aggarwal1, Ramiz Ahan1, Mark Armstrong1, Mehmet Bebek1,
Mark Blount1, Shafiul A Chowdhury1, Jia Yun Chuah1, Chris Connor1, Thomas DeBonis1, Babita Dhayal1,
Austin Dougless1, Shripad Gokhale1, Amit Jain1, Vishal Javvaji1, Kirankumar Kamisetty1, Gwang-Soo Kim1,
Joel Kpetehoto1, Chin Lee Kuan1, Che-yun Lin1, Guannan Liu1, Yunzhe Ma1, Gray Mcpherson1, Scott
Mokler1, Sanjay Natarajan1, Christopher Perini1, Rahul Ramaswamy1, Bernhard Sell1, Ramesh
Subramaniam1, James Waldemer1, Yang Yang1, Yihong Yang1, Jack Yaung1, Babak Sabi1 1Intel
Integration of different computing elements through silicon interposers enables scaling opportunities
beyond Moore’s law. Intel’s passive Si-Interposer enables interconnections among different chiplets using
Through Silicon Via (TSV) technology along with a refined 36μm micro-bump pitch in a face-to-face die
configuration. The Si-Interposer houses a high-density metal-insulator-metal (HDMIM) integrated
decoupling capacitor for voltage droop reduction and noise suppression. Products can either utilize
HDMIM in the Si-Interposer die, a built in HDMIM in the chiplet die, or both. Paper describes HDMIM
fabrication steps, electrical properties, reliability benchmarks, and performance enhancements byincorporation of Si-Interposer HDMIM.
3:45 PMT9.2 Mitigating line-break defectivity with a sandwiched TiN or W layer for metal pitch 18 nm aspectratio 6 semi-damascene interconnects , Anshul Gupta1, Souvik Kundu1, Stefan Decoster1, Kaushik Sah2,
Gilles Delie1, Brecht Truijen1, Davide Tierno1, Giulio Marti1, Olalla Varela Pedreira1, Bart Kenens1, Yannick
Hermans1, Christoph Adelmann1, Bart de Wachter1, Ivan Ciofi1, Gayle Murdoch1, Andrew Cross1, Seongho
Park1, Zsolt Tokei1 1imec, 2KLA
A novel metal stack scheme with a sub-nm, sandwiched TiN or W layer, a so-called defect mitigation layer(DML) between Ru is proposed and found to be less prone to lateral attack and line-break formation
during direct-metal-etch (DME) of Ru semi-damascene (semi-D) lines compared to those without DML.

With increasing thickness (tk) of TiN-DML, we achieve up to 5x lower defect density and resistance (R)yield >99%, <5% 1σ of R on AR~4-6, CD~6-11 nm, metal pitch (MP)=18-26 nm lines. The improvement ishigher on AR~6 lines than AR~4 which makes DML a promising approach to enable AR≥6 semi-Dinterconnects. No R penalty is found with TiN-DML for the investigated line lengths >10 µm. Thermal shock
reliability test shows good quality of HAR Ru line interfaces with TiN-DML.
4:10 PMT9.3 Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer
thinning and Molybdenum-filled slit nano Through Silicon Vias, Peng Zhao1, Liesbeth Witters1, Anne
Jourdain1, Michele Stucchi1, Nicholas Jourdain1, Jan Willem Maes2, Harsh Vardhan Bana2, Chiyu Zhu2, Rami
Chukka1, Farid Sebaai1, Kevin Vandersmissen1, Nancy Heylen1, Daniel Montero1, Shouhua Wang1, Koen
D'Have1, Filip Schleicher3, Joeri De Vos1, Gerald Beyer1, Andy Miller1, Eric Beyne1 1imec, 2ASM, 3KLA
Long slit nano Through Silicon Vias (nTSV) are used for high density connections between frontside (FS)patterned Burried Power Rails (BPR) and orthogonally patterned metal rails on the wafer backside (BS).
The length of the slits can be tuned to relax overlay requirements for BS patterning that are typicallystringent due to wafer grid distortions in bonding. Extreme wafer thinning stopping on 10nm
Si0.75Ge0.25 etch stop layer (ESL) is enabled using an optimized thinning sequence. For the first time, lowresistance barrier-free Molybdenum (Mo)-filled nTSVs are demonstrated, confirming the potential forfurther scaling compared to TiN/W filled counterparts.
4:35 PM
T9.4 Toward 0 V ESD protection in 2.5D/3D advanced bonding technology, SHIH-HSIANG LIN1, Marko
Simicic1, Nicolas Pantano1, Shih-Hung Chen1, Geert Van der Plas1, Eric Beyne1, Piet Wambacq1 1imec
This paper presents a methodology to help prevent overdesign of Electrostatic Discharge (ESD) protection
circuits for internal I/O in 2.5D/3D bonding technologies. We explore how the voltage suppression effectmitigates voltage-driven gate oxide breakdown during stacking and emphasize the role of series resistancein reducing peak discharge current. Our findings indicate that highly variable non-contact discharges are
not a concern in advanced bonding technologies, shifting the focus to more predictable contact
discharges. Also, we provide guidelines to design efficient ESD protection circuits for internal IO in 2.5D/3D
stacked system.
5:00 PM
T9.5 Material, Process and System Level Analysis for Parasitic Reduction of Next Generation Logic
Technology in conjunction with Backside Power Delivery, Ashish Pal1, Sefa Dag1, Pratik B. Vyas1, Gregory
Costrini1, Vinod Reddy1, Veeraghavan Basker1, Allen Yeong1, Benjamin Colombeau1, Bala Haran1, Subi
Kenegeri1, El Mehdi Bazizi1 1Applied Materials
The first generation of backside power delivery network (BS-PDN Gen-1), implemented with a backside
power via (BPV) has been shown to introduce additional parasitic capacitances, thus degrading thestandard cell performance by 2.5% compared to FS-PDN, and limits the performance benefit at processorlevel. In view of this, we propose an advanced metal gate-cut (MG-cut) process with low-K dielectric gatecut fill for capacitance reduction. Our MSCOTM platform shows that BS-PDN circuit performance can be
fully recovered with these 2 modifications. In addition, these modifications in combination with BSPDN,
also improve SRAM read and write delay by 8% and 17%, thus bringing significant performance benefit
for next generation GAA logic nodes.
Session C16: Memory Circuits
3:20 PM, Tapa 1

Co-Chairs:

Andreas Burg, EPFL
Satoru Takase, KIOXIA Corp.

3:20 PM
C16.1 An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage
DRAM, Kyeongtae Nam1, Jaehyuk Kim1, Dongil Lee1, Kyuchang Kang1, Sangyun Kim1, Changyoung Lee1,
Hyunchul Yoon1, Donggeon Kim1, Bokyeon Won1, Jaejoon Song1, Incheol Nam1, Young-Hun Seo1, JeongDon Ihm1, Changsik Yoo1, Sangjoon Hwang1 1Samsung Electronics
A bit line sense amplifier (BLSA) with offset compensated charge transfer pre-sensing (OC-CTPS) scheme
is implemented using 14nm DRAM process. The offset compensation (OC) is operated by diode connection
without additional size overhead for BLSA. Average fail bit rate (FBR) attributed to a mismatch of chargetransfer transistor is reduced by 94 % after performing OC. Furthermore, OC-CTPS BLSA accomplishes a3sigma window, representing the FBR under 3sigma (=0.1349%) over charge transfer time (tCT). The
3sigma window has widths of 250 ps and 500 ps at temperatures of -25 ℃ and 100 ℃, respectively,
without changing voltages for charge transfer. Moreover, our approach ensures robust and stable sensing
even at operating voltages as low as 0.75 V, compared to conventional OC BLSA.
3:45 PM
C16.2 A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-port 6T SRAM with High-R Wire Tracking andSequential Access Aware Dynamic Power Reduction, Tomotaka Tanaka1, Yuichiro Ishii1, Makoto
Yabuuchi1, Yumito Aoyagi1, Masaya Hamada1, Kazuto Mizutani1, Koji Nii1, Hidehiro Fujiwara2, Isabel
Wang2, Hong-Chen Cheng2, Hung-Jen Liao2, Tsung-Yung Jonathan Chang2 1TSMC Design Technology
Japan, 2TSMC
A 2-read/write (2RW) pseudo dual-port (PDP) 6T SRAM is developed on 3nm Fin-FET technology. To
improve performance, high-R wire tracking is introduced to adjust between margin, obtaining the
optimum speed over various sign-off conditions. In addition, to reduce the dynamic power, the pre-charge
control circuits are newly proposed to be aware of the 1st and 2nd sequential accesses. Meaningless bitline
pre-charges for the 2nd access are eliminated in either all columns or selected columns, reducing the
dynamic power in bitlines by up to 43 %. The fabricated 288-kbit 2RW PDP SRAM macro achieves thehighest world record of 19.87 Mbit/mm2 bit-density thanks to PDP design.
4:10 PM
C16.3 A 7GHz High-Bandwidth 1R-1RW SRAM for Arm HPC Processor in 3nm Technology, Rahul
Mathur1, Rajiv Kumar Sisodia1, Andy W Chen1, Arjun Singh1, Sriram Thyagarajan1, Antonio Cubeta1,
Corentin Andrieux1, Andrew Sowden1, YK Chong1 1Arm
This paper presents an advancement in memory architecture with the introduction of 1Read-1ReadWrite(1R1RW) High Bandwidth Instance (HBI) memory, seamlessly integrated into the Arm flagship High
Performance Computing (HPC) processor. Enhancing the conventional 8T-1R1W memory, HBI features anadditional read port, achieving 1R1RW capability. The utilization of HBI memory in L1-Data cache doubles
the available read bandwidth and results in an improvement in processor IPC, exceeding 1%. Furthermore,leveraging the HBI-1R1RW memory architecture, HBI-Ddata memory is developed to reduce the routing
congestion and delay in the CPU physical design, leading to a 13% reduction in area and a 10-15ps
reduction in routing delay. A test vehicle in the state-of-the-art 3nm process demonstrates 100% yield of
1R1RW HBI and highest reported frequency of more than 7GHz and lowest reported bit density of 11.2
Mbit/mm2 for any 8T SRAM memory.
4:35 PM
C16.4 A 3.3GHz 1048X640 Multi-Bank Single-Port SRAM with Frequency Enhancing Techniques and
0.55V-1.35V Wide Voltage Range Operation in 3nm FinFET for HPC Applications, Ming-Chieh Huang1,

Wei Wing Mar1, Shankar Kanade1, Boris Bai1, Aditya Gayatri1, Krishna Khairnar1, Amy Lai1, Yu-Hao Hsu1,
Hung-Jen Liao1, Yih Wang1, Tsung-Yung Jonathan Chang1 1TSMC
This paper presents high-speed SRAM macros of 0.64Mbit (1024x640) and 1.28Mbit (2048x640)
implemented using a high-current single port 6T bitcell. The macros achieve the best FoM defined as(density × frequency)/(read power + write power). Several performance-enhancing circuit techniques areproposed, including wordline, global clock, and global bitline boosting. Split drivers for decoder signals areproposed to achieve an overall 37% speed improvement while avoiding a repeater area tax. A read assist
circuit is proposed to improve Vmax to 1.35V. Silicon results demonstrate the ability to achieve 3.3GHz at
1.0V/100°C in 3nm FinFET technology.
5:00 PM
C16.5 A 14nm 128Mb eMRAM Implemented with 17.88Mb/mm2 at 0.60V for Auto-G1
Applications, Gyuseong Kang1, Hyunjin Shin1, Sanggyeong Won1, Dohui Kim1, Kyuseong Kim1, Soohoh
Seol1, Sunkyu Lee1, Hangil Lee1, Yeonho Jung1, Jaechul Shim2, Kiseok Suh1, Sohee Hwang1, Daehyun Jang1,
Sangyeop Baeck1, Sei Seung Yoon1 1Foundry Business, Samsung Electronics, 2R&D center, Samsung
Electronics
This paper presents an embedded STT-MRAM with circuit techniques to mitigate read margin degradationin high temperature for automotive grade 1 application. Local read assist circuit (LRA) can minimize
resistance mismatch between data and reference read path. Temperature tracking circuit (TTC) is
employed to change reference resistance adaptively and control negative wordline voltage generator for
reliable read operation in high temperature. The proposed 128Mb 256-IO MRAM macro is implemented
in 14nm FinFET process with 17.88Mb/mm2. Measurements results show successful 11ns read operation
across -40C to 160C with 0.60V core voltage.
Session C17: Power Management Techniques
3:20 PM, Honolulu 2
Co-Chairs:

Stephen Brink, Texas Instruments
Po-Hung Chen, National Yang Ming Chiao Tung University

3:20 PM
C17.1 A Monolithic 5.7A/mm2 91% Peak Efficiency Scalable Multi-Stage Modular Switched Capacitor
Voltage Regulator with Self-Timed Deadtime and Safe Startup for 3D-ICs, Jingshu Yu1, Xiaosen Liu1,
Minxiang Gong1, Nicolas Butzen1, Sheldon Weng1, Harish K Krishnamurthy1, Krishnan Ravichandran1,
Ramez H Ahangharnejhad1, Waldemer Jim1, Pelto Christopher1, James W Tschanz1, Vivek De1 1Intel LabsThis paper presents a monolithic Multi-stage Modular Switched Capacitor Voltage Regulator (MMSCVR)
in 16nm CMOS with scalable design (up to 7A), self-timed deadtime generator, and safe startup for verticalpower delivery in heterogeneous 3D-ICs. The proposed MMSCVR demonstrates 90.6% peak efficiency and5.7A/mm2 peak current density with a 3V-to-1V conversion – 4.9× higher than state-of-the-art. It is also
the first monolithic 4V-to-1V MMSCVR, achieving 7.8× higher current density than prior arts with off-chip
capacitors.
3:45 PMC17.2 A µW Output Power, >100V, Single-Capacitor Switched DC-DC Up/Down Converter, Rohit
Rothe1, Jungho Lee1, Zichen Fan1, Li-Yu Chen1, Donguk Seo2, Yoonmyung Lee2, Dennis Sylvester1, David
Blaauw1 1University of Michigan, Ann Arbor, 2Sungkyunkwan University

This work presents a switched capacitor high voltage (HV) DC-DC converter with a single off-chip flying
capacitor (SOF) for uW current draw applications. This converter is capable of up-conversion as well as
down-conversion using the same ladder. It achieves efficiency of 62% in up-conversion mode (175V
output) and 43% in down-conversion mode (184V input). Up-conversion efficiency is 16× higher thanstate-of-the-art converters with >100V output and nA output load.
4:10 PM
C17.3 A 6.78 MHz Wireless Power and Data Transfer System Achieving Simultaneous 52.6% End-toEnd Efficiency and 4.0 Mb/s Forward Data Delivery with Interference-Free Rectifier, Quanrong Zhuang1,
Junyi Sun1, Xusheng Zhang1, Bo Li1, Yi Shi1, Hao Qiu1 1School of Electronic Science and Engineering, Nanjing
University, China
In this work, we presented a wireless power and data transfer (WPDT) system utilizing the fundamental
and harmonic components of the bridge inverter to transfer power and data, respectively. The
conventional full bridge rectifier (FBR) introduces the interference voltage and could cause the problemof data flipping, which is solved by the proposed interference-free rectifier (IFR). Additionally, a tapped
coil three capacitor (TL3C) topology was proposed to maximize the data channel gain without affecting
the power channel gain. A 6.78 MHz system was implemented with the IFR fabricated in 180 nm CMOS
process. It supported simultaneous 82 mW load power (PLoad) and 4.0 Mb/s forward data rate (DR) at 52.6
% end-to-end efficiency (ηE2E).
4:35 PM
C17.4 A 0.6-1 V VIN Soft-Switching Low Dropout Regulator With 31.3 A/mm2 Current Density, 99.99%
Current Efficiency, and 2.04 fs FoM, Jeongmyeong Kim1, Changjoo Park1, Wanyeong Jung1 1KAISTThis paper presents a soft-switching LDO, which takes advantages of analog and digital LDOs. A soft
quantizer enables smooth switching of power FETs like an analog LDO. Inverter-based buffers provide railto-rail output voltages to power FETs like a digital LDO and offer fast transient response using a push-pull
structure even with a small dropout voltage (VDO) of 50 mV. A test chip fabricated in a 65 nm CMOS
process achieves a high current density of 31.3 A/mm2 at 1 V VIN, a current efficiency of 99.99% at 0.6 V
VIN, and a fast transient response of a 102 mV voltage droop at a 90 mA/4 ns load condition with a 0.6 V
VIN.
5:00 PM
C17.5 A 400-ns-Settling-Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its
Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology, Erik Loscalzo1, Martin
Cochet2, Joseph Zuckerman1, Samira Zaliasl3, Michael Lekas3, Stephen Cahill3, Tianyu Jia4, Karthik
Swaminathan2, Maico Cassel dos Santos1, Davide Giri1, Hesam Sadeghi3, Joseph Meyer3, Noah Sturcken3,
David Brooks4, Gu-Yeon Wei4, Luca Carloni1, Pradip Bose2, Kenneth Shepard1 1Columbia University, 2IBM
Reserach, 3Ferric Inc., 4Harvard University
We have developed a dynamic-voltage-and-frequency- scaling (DVFS) architecture that combines apackage- integrated buck voltage regulator (PIVR) with fully standard- cell-based digital low-dropout
regulators (LDO) to support fine-grained control at the scale of individual cores in a 22-core system-onchip (SoC) with a settling time of 400ns. The PIVR has a power density of 309mW/mm2 and features fullback-end integration of magnetic-core power inductors. During a workload study on the SoC consisting offour general-purpose RISC-V cores and 18 specialized accelerators, our hybrid voltage regulator (HVR)
showed the highest power savings when compared with other power management techniques forworkload durations above 1.3μs and peak power savings of 23% over the baseline without DVFS.

Session C18: Data Converter Techniques
3:20 PM, Honolulu 3
Co-Chairs:

Trevor Caldwell, Alphawave Semi
Yun-Shyiang Shu, MediaTek Inc.

3:20 PM
C18.1 A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain
Switching and Digital NC-FF, Ye-Dam Kim1, Jae-Hyun Chung1, Kent Edrian Lozada1, Chang-Un Park1, KunWoo Park1, Kwan-Hoon Song1, Young-Hoon Moon1, Min-Jae Seo2, Seung-Tak Ryu1 1KAIST, 2University of
Seoul
This paper proposes a continuous-time (CT) tracking-zoom (TZ) incremental ADC (I-ADC) that reuses aquantizer for both the coarse SAR and fine DSM stages. The TZ I-ADC addresses the input bandwidth (BW)limitation issue with simple DAC code update. A residue-gain (RG) switching technique is proposed tomitigate the inconsistent signal transfer function (STF) in the fine CT incremental DSM (I-DSM). A digitalnoise-coupling-feedforward (DNC-FF) architecture is proposed to reduce the out-of-band gain (OBG).
Fabricated in a 180nm CMOS process, the prototype consumes 2.52mW under a 1.8V supply, achieving
99-dB DR, 93.8-dB SNDR, and 102.5-dB SFDR.
3:45 PM
C18.2 A Low-OSR 5th-Order Noise Shaping SAR ADC Using EF-EF-CIFF Structure with PVT-Robust
Differential V-T-V Converter, Yu-Hsiang Huang1, Bao-shu Liu1, Chih-Cheng Hsieh1 1National Tsing Hua
University
This paper presents a low-OSR 5th-order noise-shaping (NS) SAR (NS-SAR) ADC featuring
a differential-Voltage-Time-Voltage (dVTV) converter. It introduces an innovative EF-EF-CIFF structurethat achieves 5th-order NS with only two amplifications using the proposed dVTV converter. The PVTrobust dVTV converter enables the optimization of the Noise Transfer Function (NTF) without the needfor static-power consumption, gain calibration, and trimming banks, thereby reducing circuit complexityand power consumption. The ADC has been prototyped and verified in 40nm CMOS technology with anactive area of 0.059mm2. Operating at a supply voltage of 1.1V and a sampling rate of 5MS/s, it achieves
an SNDR of 81.8dB over a 625kHz bandwidth. The resulting Schreier Figure of Merit (FoMs) and Walden
FoM (FoMw) are 181.8dB and 7.2fJ/conversion-step, respectively.
4:10 PM
C18.3 Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive
Approximate Adder With 0.012mm2 Active Area in 12nm FinFET, Qiaochu Zhang1,2, Shiyu Su1,3, Baishakhi
Biswas1, Sandeep Gupta1, Mike Shuo-Wei Chen1 1University of Southern California, 2University ofVirginia, 3University of Waterloo
This paper presents 10-bit synthesizable stochastic TDC (STDC) with common-mode time dithering andpassive approximate adder for lowering implementation cost while maintaining high linearity. Two STDCs
prototypes achieve energy efficiency of ~160dB, while the one using passive approximation adderachieves area efficiency of 19.1μm2/step.
4:35 PM
C18.4 A 71.5-dB SNDR 475-MS/s Ringamp-Based Pipelined SAR ADC with On-Chip Bit-Weight
Calibration, Chao Chen1, Zhu Yuan1, Peng Cao1, Jiawei Xu1, Zhiliang Hong1 1State Key Laboratory ofIntegrated Chips and Systems, Fudan University, Shanghai, China
This paper presents a 13-bit 475-MS/s single-channel pipelined SAR ADC, which utilizes a ring amplifier(ringamp) for residue amplification through an improved bias scheme and common-mode feedback

(CMFB). Moreover, the ADC exploits an on-chip bit-weight calibration with signal-dependent pseudorandom noise (PN) injection and a window detector to correct the interstage gain error and DAC
mismatch, requiring only 4096 PN-injected samples to calibrate the gain error in the background. As aresult, this work achieves a peak SNDR of 71.5dB and consumes 9.93mW from a 1V supply. This
corresponds to a state-of-the-art FoMs of 175.3dB and FoMw of 6.8fJ/conv-step.
5:00 PM
C18.5 A Single-Channel, 1-GS/s, 10.91-ENOB, 81-dB SFDR, 9.2-fJ/conv.-step, Ringamp-Based Pipelined
ADC with Background Calibration in 16nm CMOS, Jorge Lagos1, Pratap Renukaswamy1, Nereo Markulic1,
Ewout Martens1, Jan Craninckx1 1imec
We present a single-channel ADC that exploits muti-bit pipelined stages based on ring amplification tosimultaneously achieve high linearity, bandwidth, and power efficiency. A very-wide tuning range
comparator is introduced in the stage quantizers, which not only enables multi-bit quantization but is also
leveraged for the injection of dither to calibrate DAC mismatch and inter-stage gain in the background.
Implemented in a 16nm FinFET process, it achieves 10.91 ENOB and 81 dB SFDR at 1 GS/s, consuming 17.8mW from a 0.9 V supply, resulting in a Walden FoM of 9.2 fJ/conv.-step.
Thursday, June 20
Session JFS4: Biomedical Technologies
8:00 AM, Tapa 1
Co-Chairs:

Emmanuel Quevy, Probius
Yuta Shiratori, NTT Corporation

8:00 AM
JFS4.1 Highly Sensitive Multimodal CMOS Antifouling Sensor Array with Multi-Use Electrodes forSingle-Cell-Level Profiling of Biophysical and Biochemical Parameters, Hangxing Liu1, Fuze Jiang1, Adam
Wang1, Zhikai Huang1, Ying Kong1, Marco Saif1, Dongwon Lee1, Thomas Burger1, Jing Wang1, Hua Wang1
1
ETH Zürich
Monitoring cell bio-responses in organ-on-chip platforms is crucial for accurately predicting organ
reactions to medications over time. This work presents an antifouling CMOS sensor platform for in-vitro,
single-cell-level and multimodal sensing of biophysical and biochemical parameters in cell proliferationand inflammation. The chip features 4,096 sensing pixels at 45-μm spatial resolution. Each pixel node
offers four sensing modalities (impedance tomography, electrochemistry, shadow imaging, and pH
sensing) and three actuation functions (dielectrophoresis (DEP) as well as voltage and current
stimulations).
8:25 AM
JFS4.2 A 65nm Neuromorphic Bio-signal Encoder with Compute-in-Entropy Architecture 7.13nJ
Privacy-preserving Encoding and 2.38Mb/mm2 Encoding Memory Density , Boyang Cheng1, Jianbo Liu1,
Steven Davis1, Zephan M. Enciso1, Likai Pei1, Muya Chang1, Ningyuan Cao1 1University of Notre Dame
This paper presents a neuromorphic bio-signal encoder for privacy-critical smart health applications
featuring a novel compute-in-entropy architecture for hardware-efficient, physically-unclonable
hyperdimensional encoding. The test chip achieved privacy-preserving bio-signal encoding with 7.13 nJ
efficiency, 2.38 Mb/mm2 item memory density, and in-situ decision-making and learning capabilities.
8:50 AMJFS4.3 A Subcellular-Resolution Multimodal CMOS Biosensor Array with 16K Ion-Selective Pixels for
Real-Time Monitoring Potassium Dynamics, Hangxing Liu1, Fuze Jiang1, Ying Kong1, Dongwon Lee1, Yuguo
Sheng1, Adam Wang1, Zhikai Huang1, Marco Saif1, Thomas Burger1, Jing Wang1, Hua Wang1 1ETH Zürich
Ion sensing offers an efficient tool for deep understanding of ion channel-related diseases such as K+ for
hyperproliferative tumors. In this work, we present the first biocompatible ion-selective bioimaging arrayfor cellular characterization and modulation, fully integrated in a CMOS chip with 16K multi-modal pixels
at a subcellular 5.4-μm-pitch resolution. This multimodal CMOS cell interfacing array consists of in-pixel
biosensing/actuation circuits for cell localization, ion-selective concentration monitoring, and plasma
membrane stimulation.
9:15 AM
JFS4.4 A Pulsed Electrochemistry Readout IC with Slew-rate Booting Technique and Phase-domain ∆Σ
ADC for Si-Nanowire Electrical Double-layer Capacitance Measurement, Po-Hsun Chu1, Cheng-Tse Tsai1,
Yu-Siang Chou1, Nitish Kumar2, Shu-Ping Lin2, Yu-Te Liao1 1National Yang Ming Chiao Tung
University, 2National Chung Hsing University
This paper presents a pulse-driven method for detecting cardiac Troponin I using an electrical doublelayer (EDL) capacitance sensing readout circuit and an on-chip pattern generator. The pattern generator
is equipped with a slew rate-boosting driver circuit capable of handling EDL capacitance ranging up to 100
nF with a slew rate greater than 6.6 V/μs while consuming only 13.5 μW. Additionally, the design achieves
a dynamic range (DR) of 77.4 dB by implementing an oscillator-based readout circuit and a limit ofdetection (LoD) of 200 fg/mL in an undiluted PBS solution with a total power consumption of 120 μW.
Session JFS5: Image Sensors
8:00 AM, Tapa 2
Co-Chairs:

Bruce Rae, STMicroelectronics
Yoshiaki Kikuchi, Sony Semiconductor Solutions

8:00 AM
JFS5.1 A 336 x 240 backside-illuminated 3D-stacked 7&[mu]m SPAD for LiDAR sensor with PDE 28% at
940nm and under 0.4% depth accuracy up to 10m, Jaehyung Jang1, Jongchae Kim1, Sunho Oh1, Kyungsu
Byun1, Dahwan Park1, Jihee Han1, Hanseung Lee1, Suhyun Yi1, Hoonmoo Choi1, Jongeun Kim1, Namil Kim1,
Yongtae Gim1, Minkyu Kim1, Sangyoung Lee1, Hansang Kim1, Eunchang Lee1, Minsang Yu1, Jeongjoon
Hwang1, Seunghyun Yoon1, Kwang Hwangbo1, Heesang Kim1, Ahyoung Cho1, Taejun Baek1, Sooyoung
Park1, Kwangjun Cho1, Wonje Park1, Kyung-do Kim1, Hoesam Jeong1, Hoon-sang Oh1, Chang-rock Song1 1SK
hynix Inc., CIS Development
Single photon avalanche diode (SPAD) is a key technology in light detection and ranging (LiDAR) sensors,which are gaining prominence as next-generation image sensors. We designed SPAD with high photon
detection efficiency (PDE) using a backside-illuminated hybrid bonding 3D-stacked technology. This is
aimed at developing a LiDAR sensor with good depth accuracy. We achieved a PDE of 28% at λ = 940nm
and a low-level dark count rate (DCR) by applying the trench guide (TG) and the small lens array (SLA)
structure and optimizing pixel design. As a result, we achieved a depth accuracy of less than 0.4% up to
10m.
8:25 AM
JFS5.2 A Temporal Noise Reduction via 40% Enhanced Conversion Gain in Dual-Pixel CMOS Image
Sensor with Full-Depth Deep-Trench Isolation and Locally Lowered-Stack Technology, Seunghwan Lee1,
Jeongjin Cho1, Shinyoung Choi1, Sung Yoon Min1, Eunjung Lee1, Minji Jung1, Kyoungmok Son1, Hyunchaul

Jeong1, Heetak Han1, Sachoun Park1, Sanghyuck Moon1, Seungki Jung1, Junseok Yang1, Taesub Jung1,
Howoo Park1, Bumsuk Kim1, Kyungho Lee1, Jesuk Lee1 1Samsung Electronics
We demonstrate a dual-pixel CMOS image sensor (CIS) with full-depth deep-trench isolation (FDTI) andlocally lowered-stack (LLS) structure. When the LLS structure is adopted, the floating diffusion (FD) metal
capacitance is dramatically reduced, resulting in a 40% increase in conversion gain (CG) and a 25%
improvement in temporal noise (TN). We also present TN analysis from the perspective of the feedback
circuit scheme.
8:50 AM
JFS5.3 High-Resolution and Compact Integrated FMCW-LiDAR Chip with 128 Channels of Slow Light
Grating Antennas, Yuya Maeda1, Yoshiki Ebiko1, Haruhiko Terada1, Ryo Tetsuya1, Shunji Maeda1, Yotaro
Yasu1, Takemasa Tamanuki2, Mikiya Kamata2, Keisuke Hirotani2, Saneyuki Suyama2, Kohei Yamamoto2,
Shota Nawa2, Riku Kubota2, Toshihiko Baba2 1Sony Semiconductor Solutions Corporation, 2Yokohama
National University
This paper introduces compact solid-state optical beam scanning technology, slow light grating (SLG)
based on photonic crystal waveguide. We implemented the successful implementation of a frequency
modulated continuous wave (FMCW) LiDAR chip, featuring 128 channels equipped with the developed
SLG antennas. Our design incorporates an upward radiating structure in an antenna array with a fine pitchof 40 µm and a total footprint of 5.14 mm × 1.20 mm, respectively. Using this chip, we successfully
performed a FMCW measurements and point cloud mapping.
9:15 AM
JFS5.4 A 30fps 64 X 64 CMOS Flash LiDAR Sensor with Push-Pull Analog Counter Achieving 0.1% Depth
Uncertainty at 70m Detection Range, Dongseok Cho1,2, Byungchoul Park1, Hyun-Seung Choi3, Myung-Jae
Lee3, Youngcheol Chae1 1Yonsei University, 2Samsung Electronics, 3KIST
This paper presents a CMOS flash LiDAR sensor based on a time-gated single-photon counting method.
The proposed 64×64 sensor is implemented in a 110nm BSI process and achieves a small pixel pitch of
32mm with a fill factor of 33%. It consumes 29.1mW, while operating at 30fps. It achieves a high PDP of
14.3% at 850nm and a depth uncertainty of 7cm at a depth range of 70m, corresponding to the worstcase depth uncertainty of 0.1%. These results are achieved by the use of a compact SPAD front-end, apush-pull analog counter, and an optimized PDP. The gain mismatch errors in the analog counter are
mitigated by the use of a push-pull gain averaging scheme.
Session T10: Emerging Non-Volatile Memories - RRAM, FeRAM, PCM, MRAM-2
8:00 AM, Tapa 3
Co-Chairs:

Gary Bronner, Rambus
Byoung Hun Lee, Pohang University of Science and Technology

8:00 AM
T10.1 A Novel Phase Change Material RF Switch with 16nm Technology to Achieve Low Voltage and
Low Ron*Coff for mmWave, Hung-Ju Li1, K.P. Chang1, C.E. Chen1, W.T. Hsieh1, H.H. Kuo1, C.C. Huang1, H.C.
Chen1, Z.H. Ya1, H.Y. Chen1, J.D. Jin1, S.H. Yang1, Y.W. Ting1, K.C. Tseng1, K.C. Huang1, Harry Chuang1 1TSMC,
TaiwanWe present an enhanced phase change material (PCMe) RF switch (RFS) to achieve an impressive
Ron*Coff of 11.6fs and operates below 1.8V. The PCMe material has low-resistivity that exhibits 40%
insertion loss (IL) improvement compared to Ge50Te50, which is greater than -0.5dB, and isolation (ISO)less than -28dB at 30GHz. The switch operates 100 million cycles at -40C and 125C with stable Ron, andthe transistor underneath is unaffected after RESET/SET 10Mc operations.

8:25 AM
T10.2 14nm FinFET node embedded MRAM technology for automotive non-volatile RAM applications
with endurance over 1E12-cycles, Joosung Oh1, Jaehyeon Park1, Kiseok Suh1, Kangmoon Lee1, Sohee
Hwang1, Myeongjun Bak1, Honghyun Kim1, Baeseong Kwon1, DongKyu Lee1, Minkwan Kim1, Seungmo
Noh1, Jongmin Lee1, Soomin Cho1, Gyuseong Kang1, Hyun-Jin Shin1, Yongsung Ji1, Atsushi Okada2, UngHwan Pi1, Kwangseok Kim2, Younghyun Kim1, Jeong-Heon Park1, Seungpil Ko1, Tae-Young Lee1, Kyung-Tae
Nam1, Minkwon Cho1, Boyoung Seo1, Shinhee Han1, Yoonjong Song1, Kangho Lee1, Ja-Hum Ku1 1Samsung
Electronics Co., Ltd., 2Samsung Advanced Institute of Technology
We present a 14nm FinFET embedded MRAM (eMRAM) technology for non-volatile RAM (nvRAM)
applications, featuring endurance of 1E12 cycles, 100ns write speed, 150°C retention for 10 years, andmacro density of 18Mb/mm2. With SRAM interface, this macro provides write speed 24 times faster than
flash-type eMRAM and ~50% area saving compared to SRAM. Compared to 28nm nvRAM-type eMRAM,
we have improved retention temperature from 89°C to 150°C at the same endurance characteristics,
which is suitable for automotive-grade products.
8:50 AM
T10.3 Extremely scaled perpendicular SOT-MRAM array integration on 300mm wafer, Farrukh
Qayyum Yasin1, Alvaro Palomino1, Ankit Kumar1, Valerio Pica1, Simon Van Beek1, Giacomo Talmelli1, Van
Dai Nguyen1, Stefan Cosemans1, Davide Crotti1, Kurt Wostyn1, Gouri Sankar Kar1, Sebastien Couet1 1imec
We present a novel integration solution to prevent MTJ pillar damage due to patterning of SOT- MRAM
devices, particularly when targeting the ultimate SOT track scaling. Substantial reduction of switchingcurrent with pulse widths down to 0.3ns is shown in single cell extremely scaled devices versus ourbaseline. We demonstrate, for the first time, the functionality of a perpendicular SOT-MRAM array on
300mm CMOS wafer, comprising of multiple 4kb sub-banks with variations in SOT track size and pitch atour baseline 63nm MTJ CD. Study of the 4kb sub-banks indicates the feasibility of device pitch scaling froma device-to-device gap of 216nm down to 99nm, leading to a 50% increase in the MTJ read window(median Rp to Rap) while obtaining remarkable tailing bits as low as 0.3% for W/CoFeB stack (Wβ SOT
track with CoFeB free layer MTJ).
9:15 AM
T10.4 First demonstration of high retention energy barriers and 2 ns switching, using magnetic
ordered-alloy-based STT MRAM devices, Matthias Gottwald1, Guohan Hu1, Philip Trouilloud1, Laura
Rehm1, Christopher Safranski1, Gukcheon Kim1, Stephen Brown1, John Bruley1, Christopher D'Emic1, Oki
Gunawan1, Hyunsung Jung2, Christian Lavoie1, Joonmyoung Lee2, Jim Liang1, Michael Robbins1, Jonathan
Sun1, Pouya Hashemi1, Daniel Worledge1 1IBM, 2Samsung
Magnetic ordered alloys with low moment and strong bulk perpendicular magnetic anisotropy (PMA)
were successfully developed and integrated on CMOS substrates as a free layer material. Superior device
properties including high Hc (> 8 kOe), high Eb (> 80 kBT) and sub-5 ns switching were achieved
simultaneously, overcoming the fundamental tradeoff between high Eb and high-speed switching inconventional CoFeB-based devices using interface anisotropy. We further demonstrated improved
switching performance at pulse widths down to 2 ns and improved magnetic field sensitivity in theseordered alloy-based devices, compared to the best published results to date.
Session C19: 2.5/3D Die-to-Die Interfaces
8:00 AM, Honolulu 1
Co-Chairs:

John Wuu, AMDKoji Nii, TSMC Design Technology Japan, Inc.
8:00 AM
C19.1 An On-Chip Current-Sink-Free Adaptive-Timing Power Impedance Measurement (PIM) Unit for
3D-IC in 5nm FinFET Technology, Tsung-Che Lu1, Chin-Ming Fu1, Wei-Hsiang Wang1, Fred Kuo1, Chih-Hsien
Chang1, Kenny Hsieh1, King-Ho Tam1, Tze-Chiang Huang1, Tom Chen1, Mei Wong1, Wei-Pin Changchien1,
Frank Lee1 1TSMC
This work presents a power impedance measurement (PIM) architecture for the 3D-IC platform with highperformance computing (HPC) applications. Proposed current-sink-free architecture improves stimulus
current capacity without area overhead. Another adaptive-timing scheme saves 50% testing time. The
PIM IP has been fabricated in 5nm FinFET process with TSMC-SoIC® technology for characterization of anembedded ARM® core. Compared to state-of-the-art works, the 3.6-A stimulus current yields 116x
improvement while the 0.006 mm2 core area achieves 79% reduction.
8:25 AM
C19.2 Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost
Programmable 2.5D/3.5D Packaging Technology, Wei Lu1, Jie Zhang2,2, Yi-Hui Wei2, Hsu-Ming Hsiao2, SihHan Li2, Chao-Kai Hsu2, Chih-Cheng Hsiao2, Feng-Hsiang Lo2, Shyh-Shyuan Sheu2, Chin-Hung Wang2, WeiChung Lo2, Shih-Chieh Chang2, Hung-Ming Chen1, Kuan-Neng Chen1, Po-Tsang Huang1 1National Yang Ming
Chiao Tung University, Hsinchu, Taiwan, 2Electronic and Optoelectronic System Research Laboratories,
Industrial Technology Research Institute, Hsinchu, Taiwan
For realizing low-cost miniaturized 2.5D/3.5D integration, this paper presents scalable embedded multidie active bridge (S-EMAB) chips with integrated LDOs to provide on-demand I/O routing capability andin-package voltage regulation among multiple dies or chiplets. Each S-EMAB chip is a programmablebridge and implemented by an I/O array and MUX I/Os to support various transmission interfaces. The
data rate of I/O array are from 50Mbps to 1Gbps, and MUX I/Os can reach to 8Gbps. Moreover, thenumber of programmable I/O links can be scaled up by connecting multiple S-EMAB chips in a daisy chain
without extra control pins. In addition to miniaturization, LDOs are further integrated in S-EMAB chips toeliminate external LDOs. The proposed work is a fast time-to-market, low-cost, flexible, and miniaturized
3.5D integration solution for various IoT applications.
8:50 AM
C19.3 A 32Gb/s 0.36pJ/bit 3nm Chiplet IO using 2.5D CoWoS Package with Real-Time and Per-Lane
CDR and Bathtub Monitoring, John Ma1, Junhui Gu1, Jianmin Guo1, Dongliang Liang1, Michael Sorna1, Hui
Wang1, Ken Chang1 1Marvell Technology Group
This work presents a high density single-ended NRZ Chiplet IO in 3nm CMOS technology over 2.5D CoWoS
interposer of up to 2mm trace length, with a total of 216 data lanes running simultaneously at
32Gb/s/wire. The 2mm channel insertion loss and crosstalk at Nyquist frequency are -2.4dB and -18.1dB
respectively. The RX features a real-time per-lane CDR and bathtub monitor, enabling optimal sampling
point adaptation as well as tracking of phase drift over voltage and temperature. With all lanes toggling,
the PHY achieves 3.84T/mm beach front density while consuming 0.36pJ/bit. The worst lane measures
0.342UI opening at BER of 1e-12 and interpolated 0.331UI opening at BER of 1e-15 when running at
32Gb/s. 25Gb/s results are also presented as a low power option.
9:15 AM
C19.4 WITHDRAWN - A Customizable Killo-core Processor Architecture by Reusable Chiplets with Lowlatency High-flexibility Die-to-Die Interconnection

Session C20: Processing for AI
8:00 AM, Honolulu 2
Co-Chairs:

Sophia Shao, UC Berkeley
Vinayak Honkote, Intel Corp.

8:00 AM
C20.1 Dyamond: A 1T1C DRAM In-memory Computing Accelerator with Compact MAC-SIMD andAdaptive Column Addition Dataflow, Seongyon Hong1, Wooyoung Jo1, Sangjin Kim1, Sangyeob Kim1,
Kyomin Sohn2, Hoi-Jun Yoo1 1KAIST, 2Samsung Electronics
This paper proposes Dyamond, a 1T1C DRAM in-memory computing accelerator with column addition(CA) dataflow, for high density and energy efficiency. LSB-CA minimizes ADC readouts to increase energy
efficiency. MSB-CA with signal-enhanced MAC and signal-shifted ADC enhances SQNR, improving energy
efficiency. A switchable sense amplifier reduces read energy for low-power in-memory arithmetic SIMD.
Dyamond is fabricated in 28nm CMOS technology, integrating 27Mb eDRAM memory within a 6.48mm2
die area. It achieves 27.2 TOP/W peak energy efficiency and outstanding performance in advanced models(ResNet, BERT, GPT2).
8:25 AM
C20.2 A PVT Robust Signed 8-Bit Analog Compute-In-Memory Accelerator with Integrated Activation
Functions for AI Applications, Hechen Wang1, Renzhi Liu1, Richard Dorrance1, Deepak Dasalukunte2,
Niranjan Gowda1, Brent Carlton1 1Intel Labs, 2IntelThe frequent data conversion in analog CiM reduces the benefits obtained by analog computing. This
paper proposes a signed 8b MAC with hybrid differential capacitor ladders. Then a sparsity-aware DAC
and an embedded SAR-ADC are introduced to lower the data conversion overhead. Finally, two activation
functions (AFs) are included to further improve efficiency: 1) ReLU is realized by SAR-ADC LSB skipping; 2)tanh is built with analog buffers to bypass data converters.
8:50 AM
C20.3 A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb LosslessCompressed-Computing STT-MRAM Near-Memory-Compute Macro, De-Qi You1, Win-San Khwa2, Jui-Jen
Wu2, Chuan-Jia Chang1, Guan-Yi Lin1, Po-Jung Chen1, Ting-Chien Chiu1, Fang-Yi Chen1, Andrew Lee1, YuCheng Hung1, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Yu-Der Chih2, TsungYung Chang2, Meng-Fan Chang2 1National Tsing Hua University, 2TSMC
Battery-powered AI-edge processors require short wakeup-to-response latency (TWR) and high energy
efficiency (EF) for accurate real-time inference. This necessitates high-capacity nvCIM macros to store
floating-point (FP) neural network (NN) data (e.g., BF16) and perform MAC operations with short latency(TCD) and high EF. This paper presents an STT-MRAM nvCIM macro with lossless compression computation,a near-far aware readout scheme, and system-level CIM-friendly hybrid weight mapping. The proposed
22nm nonvolatile processor (nvProcessor) with 47.25-Mb STT-MRAM nvCIM achieved high EF(21.4TFLOPS/W), short TWR (428.58μs), and high macro-level EF (27.6TFLOPS/W).
9:15 AM
C20.4 A ∆ Based Spike Sorting SoC with End-to-End Implementation of Event-Driven Binary
Autoencoder Neural Network in Analog CIM Achieving 94.54% Accuracy and 3.11µW/Ch, Edward
Jongyoon Choi*1, Vincent Lukito*1, Injun Choi1, Seoyoung Lee1, Ik-Joon Chang2, Sohmyung Ha3 Minkyu Je1
1
Korea Advanced Institute of Science and Technology, 2Kyung Hee University, 3New York University

This work presents a Δ-based spike sorting SoC with 3 main key features. 1) Incorporate the first CIM
implementation in spike sorting using an autoencoder neural network feature extraction to increase
clustering accuracy but with low power and latency. 2) Utilize Δ-spikes to suppress the low-frequency
noise of neural signals avoiding false detection and increase overall system accuracy. 3) Reduce digital
data transmission rate by relocating the spike detection and feature extraction to the analog domain using
analog Δ detection and analog CIM. The proposed system achieves the highest measured on-chip spike
sorting classification accuracy of 94.54% and reduced digital data transmission rate by 48.8× on averagecompare to prior spike sorting systems.
Thursday Luncheon Presentation
12:15 PM – 1:15 p.m., Coral 4-5“The CHIPS Program and you: An R&D update for the VLSI Symposia”, Greg Yeric, Director of Research,
CHIPS National Semiconductor Technology Center Program, US Department of Commerce
The U.S. CHIPS and Science act allocated $50B for the advancement of semiconductor technology, which
includes manufacturing incentives, R&D programs, and workforce development. Initial announcements
have primarily involved the $39B directed toward manufacturing incentives. But now, just in time for the
VLSI Symposia, R&D programs that align with the Symposia’s membership are rolling out: the National
Advanced Packaging Manufacturing Program (NAPMP) and the National Semiconductor Technology
Center (NSTC), related workforce development initiatives, and additional programs. Dr. Yeric will
describe the organization, strategy, and vision of the CHIPS R&D programs and discuss how the Symposia
membership, including non-U.S. entities, can expect to participate as these R&D programs fully ramp up.
Session C21: Power Converters
8:00 AM, Honolulu 3
Co-Chairs:

Zeynep Toprak Deniz, IBM
Kouichi Kanda, Fujitsu Research

8:00 AM
C21.1 A 96.4%-Efficiency Single-Duty-Cycled Buck-Boost Converter Achieving 1.9mV Ripple and 2.1mV
Mode-Change Fluctuation for Mobile OLED Displays, Jae-Hyun Kim1, Yousung Park1, Doyoung Kwon1,
Dong-Kyu Kim2, Sung-Chun Park2, Yongjae Lee2, Jung-Bong Lee2, Hyun-Sik Kim1 1KAIST, 2Samsung Display
This paper presents a single-duty-cycled buck-boost (SDC-BB) DC-DC converter for powering mobile
OLEDs. Its features include a low output ripple and the ability to seamlessly cover all conversion ratios
using a single duty-cycle (D), effectively suppressing output fluctuations during transitions between boost
and buck modes. In its implementation, the flying capacitor is reused for the gate drives, thereby
eliminating bootstrap overhead, and an adaptive ramp generator is incorporated to enhance immunity to
TDMA noise. The chip fabricated in 0.18μm achieves output ripples of ≤1.9mV and a peak efficiency of
96.4%. It maintains output fluctuations within 2.1mV during transitions between buck and boost modes,
ensuring flicker-free displays.
8:25 AM
C21.2 A 1.8V-Input 0.2-to-1.5V-Output 2.5A 930mA/mm3 Always-Balanced Dual-Path Hybrid Buck
Converter with Seamlessly All-VCR-Coverable Tri-Mode Operation, Dae-Hyeon Kim1, Jeong-Hyun Cho1,
Hyunki Han1, Hyun-Sik Kim1 1KAISTThis paper presents an always-balanced dual-path hybrid buck converter capable of covering all
conversion ratios with high efficiency. The proposed tri-mode operations ensure seamless, defect-free
dynamic voltage scaling (DVS). Fabricated in 180nm, the chip outputs voltages ranging from 0.2 to 1.5V
with a 1.8V input. It achieves a peak efficiency of 94.2%, even with compact-volume LC parts. Its current
density was measured to be 930mA/mm3 at 2.5A load current.
8:50 AM
C21.3 A 5.4V-Vin, 9.3A/mm2 10MHz Buck IVR Chiplet in 55nm BCD Featuring Self-Timed Bootstrap andSame-Cycle ZVS Control, Harish Kumar Krishnamurthy1, Sally Amin1, Huong Do1, Claudio Alvarez1, Michael
J Hill1, Kaladhar Radhakrishnan1, Vivek De1, Sheldon Weng1, Krishnan Ravichandran1, Jim Tschanz1, Wilfred
Gomes1, Jonathan Douglas1 1Intel Corporation
This paper presents a 5.4V-Vin, 0.6-1.8V Vout, 10MHz LDMOS-based buck IVR chiplet implemented in a
55nm BCD process featuring a self-timed bootstrap technique and same-cycle all-digital ZVS control toachieve 9.3A/mm2 current density and 93.6% peak conversion efficiency, while meeting all reliability
constraints. The IVR chip supports a maximum load current of 80A and occupies 8.6mm2 die area.
9:15 AM
C21.4 730-790mA/mm2 48V-to-1V Integrated Hybrid DC-DC Converters based on a Star-Delta
Switching Network with 5x/8x Duty Expansion, Chen Kong Teh1, Te Bi1, Shuichi Ito1, Takashi Kurihara1
1
Toshiba Electronic Devices & Storage Corporation
We present two 48V-to-1V non-isolated dc-dc converters with up to 790mA/mm2 current density and 88%
peak efficiency, realized by a star-delta topology providing 5x and 8x duty expansion with only 3 and 4
Cfly, respectively.
Session T11: Advanced CMOS Devices and Technology-2
9:55 AM, Tapa 1
Co-Chairs:

Yue Liang, nVidia
Kazuyuki Tomida, Rapidus Corp.

9:55 AM
T11.1 Vt Fine-Tuning in Multi-Vt Gate-All-Around Nanosheet nFETs using Rare-Earth Oxide-based
Dipole-First Gate Stack Compatible with CFET Integration, Hiroaki Arimura1, Hans Mertens1, Jacopo
Franco1, Leo Lukose1, Waleed Maqsood1, Stephan Brus1, Thomas Chiarella1, Andrea Impagnatiello1,
Suvidyakumar Homkar2, Vivek Koladi Mootheri2, Chunhai Yin2, Giuseppe Alessio Verni2, Michael Givens2,
Lucas Petersen Barbosa Lima1, Serge Biesemans1, Naoto Horiguchi1 1imec, 2ASM
This work demonstrates a dipole-induced Vt fine-tuning on scaled Gate-All-Around (GAA) nanosheet (NS)nFETs (48 nm CPP, 16 nm Lg). Thanks to a novel Rare-Earth-Oxide (REO) as a moderate n-type dipole
former, ~50 mV-step Vt modulation is demonstrated even in a drive-in-free dipole-first integration
scheme. Vt shift-dependent slight mobility degradation is seen on long-channel planar RMG nFETs,
however, improved Dit and PBTI max. Vov confirmed the high-quality gate stack. On the scaled NS nFETs,
REO dipole-first demonstrates a gradual Vt modulation with maintained Vt variability and device
performance while outperforming LaO dipole-first and dipole-last multi-Vt options.
10:20 AM
T11.2 Replacement Metal Gate Process Extendible Beyond 2 nm Node with Superior Gate
Conductivity, Naomi Yoshida1, Ilanit Fisher1, He Ren1, Chi-Chou Lin1, Chenfei Shen1, Yongjing Lin1, Yi Xu1,
Michael S-.C. Chen1, Mehul Naik1 1Applied Materials

This paper describes a selective metal cap process on replacement-metal-gate (RMG) for gate scaling withhigh conductivity. Thin highly conductive metal cap on top of RMG is an effective way to maintain highgate conductivity with extremely scaled gate trench. The technology is extendible to 2 nm node GAA-FET
and beyond.
10:45 AM
T11.3 Breakthrough processes for Si CMOS devices with BEOL compatibility for 3D sequential
integrated More than Moore analog applications, Daphnée Bosch1, Abygael Viey1, Tadeu MOTAFRUCTUOSO1, Pierre LHERITIER1, Christophe LICITRA1, Nada Zerhouni ABDOU1, Antoine ALBOUY1, Laurent
BRUNET1, Alexandre MAGALHAES-LUCAS1, Lucas MOTA BARBOSA DA SILVA2, Hervé BOUTRY1, Mohamed
Husien Fahmy Taha Abdelrahman1,3, Fuccio CRISTIANO3, Remy GASSILLOUD1, Michael RIBOTTA1, Giovanni
ROMANO1, William VANDENDAELE1, veronique BENEVENT1, Mathieu OPPRECHT1, Sebastien KERDILES1,
Frederic MILESI1, Frederic MAZEN1, Benoit SKLENARD1, Catherine EUVRAT-COLNAT1, Julien STURM1,
Amelie LAMBERT1, cecile CANDEGABE1, Lucie LARAIGNOU1, Francois BOULARD1, Aurelien SARRAZIN1,Michelly DE SOUZA2, Christoforos THEODOROU4, Xavier GARROS1, Perrine BATUDE1 1Univ. Grenoble Alpes,
CEA, Leti, F-38000 Grenoble, France, 2FEI, São Bernardo do Campo, Brazil, 3LAAS, CNRS and University
Toulouse, France, 4Univ. Grenoble Alpes, Univ. Savoie Mont Blanc, CNRS, Grenoble INP, CROMA, Grenoble
This work unlocks Low Temperature (LT) technological showstoppers in view of versatile analog highvoltage (>2.5V) BEOL (400°C) devices. We demonstrated Silicon (Si) devices with CMOS-compatible polygate thanks to ns laser annealing (NLA) in melt regime and junction dopants activation without diffusion
at 400°C to preserve the engineered junction profile. HPD2 final anneal cures LT gate stack, achieving
performances in line with planar analog CMOS technology: Dit <1e11 cm2.eV-1, Nt <1e17 eV-1.cm3µpMOS >100cm².V-1.s-1 µnMOS >300cm².V-1.s-1.
11:10 AM
T11.4 First Experimental Demonstration of Self-aligned Flip FET (FFET): a Breakthrough Stacked
Transistor Technology with 2.5T Design, Dual-side Active and Interconnects, Haoran Lu1, Yandong Ge1,
Xun Jiang1, Jiacheng Sun1, Wanyue Peng1, Rui Guo1, Ming Li1, Yibo Lin1, Runsheng Wang1, Heng Wu*1, Ru
Huang1 1School of Integrated Circuits, Peking University, Beijing, China
For the first time, the Flip FET (FFET), a novel stacked transistor technology with self-aligned active andinterconnects on both sides of wafer, is proposed and experimentally demonstrated. Two layers oftransistors are formed on the same active and back-to-back stacked, featuring a much moremanufacturing-friendly process flow. Standard cell libraries with minimum 2.5T design are established.
FFET has better design flexibility with no restriction on N/P polarity for each transistor layer, enabling abipolar SRAM with at least 35.9% over FinFET SRAM. Based on fins, FFET outperforms CFET with 21.5%
higher frequency at iso-power and 45.0% lower power at iso-frequency. For nanosheet-based ones, FFET
shows extra benefits over CFET with larger nanosheet width, with 14.5% higher frequency at iso-power.
New concepts of dual-side interconnects are introduced and the P&R result of a RISCV32I core further
validates the superiority of FFET with more than 31.3% area reduction compared with CFET.
11:35 AM
T11.5 3DIC with Stacked FinFET, Inter-level Metal, and Field-Size (25x33mm2) Single-Crystalline Si on
SiO2 by Elevated-Epi, Bo-Jheng Shih1,2, Yu-Ming Pan1, Hao-Tung Chung1, Chieh-Ling Lee1, I-Chun Hsieh1,
Nein-Chih Lin2, Chih-Chao Yang2, Po-Tsang Huang1, Hung-Ming Chen1, Chiao-Yen Wang1, Huan-Yu Chiu1,
Huang-Chung Cheng1, Chang-Hong Shen2, Wen-Fa Wu2, Tuo-Hung Hou2, Kuan-Neng Chen1, Chenming
Hu1,3 1National Yang Ming Chiao Tung University, 2Taiwan Semiconductor Research Institute, 3Department
of Electrical and Computer Science, University of California, Berkeley

The Elevated Epi technique is presented for the fabrication of single-crystal (100) silicon of wafer field size
(25mmx33mm) for monolithic three-dimensional integrated circuits (3DICs). Elevated Epi uses a low
substrate temperature, pulse laser technique to fabricate single-crystal Si on dielectric. We also
demonstrate 3D inverters, with an inter-layer metal M0 positioned between two layers of FinFETs. A
hybrid-3D cell library is presented for improving performance, power, and area of 3DICs.
Session T12: Oxide Channel FET for Logic and Memory Applications-2
9:55 AM, Tapa 2
Co-Chairs:

Vamsi Paruchuri, ASM
Hiroshi Morioka, Socionext Inc.

9:55 AM
T12.1 Overcoming Performance Limitation of IGZO FET by iCVD Fluorine Doping, SEUNG HYUN OH1,CHANG HYEON LEE1, HEE TAE KIM1, JEONG IK PARK1, MIN JU KIM2, SE JUN PARK3, SUNG GAP IM1, SUNG
HAENG CHO4, BYUNG JIN CHO1 1KAIST, 2Dankook University, 3Samsung Electronics, 4ETRI
It has been reported that fluorine (F) doping using initiated chemical vapor deposition (iCVD) doping
technique can significantly improve electrical performance and reliability of IGZO channel FET. This newprocess can overcome the trade-off relationship between μFE and threshold voltage (VTH), as IGZO FET with
iCVD doping provides 2.5 times higher mobility than that without doping, yet maintains enhancementmode (VTH>0) operation. iCVD doping can achieve uniform distribution of F across the entire IGZO channel
thickness, thereby successfully passivating interfaces, achieving excellent stability under electrical andillumination stresses.
10:20 AM
T12.2 Ge-doped In2O3: First Demonstration of Utilizing Ge as Oxygen Vacancy Consumer to Break the
Mobility/Reliability Tradeoff for High Performance Oxide TFTs, Jiayi Wang1,2, Ziheng Bai2, Kuo Zhang1,3,
Zhicheng Wu2, Di Geng2, Yang Xu1,2, Nannan You1,2, Yuxuan Li1,3, Guanhua Yang2, Ling Li2,3, Shengkai
Wang1,3, Ming Liu2 1High-Frequency High-Voltage Device and Integrated Circuits R&D Center, Institute ofMicroelectronics, Chinese Academy of Sciences, 2State Key Lab of Fabrication Technologies for Integrated
Circuits, Institute of Microelectronics, Chinese Academy of Sciences, 3University of Chinese Academy of
Sciences
For the first time, we demonstrated high-performance Ge-doped In2O3 (IGeO) thin film transistors (TFTs).
Through comprehensive understanding of Ge-induced oxygen vacancy (VO) consumption andcrystallization mechanisms, the VO generation is actively suppressed while increased the crystallinity. The
proposed IGeO TFT with fractional Ge doping (atomic concentration ~0.4% by SIMS) presents an enhanced
reliability (ΔVth = 10 m V, +4 V for 3600 s) with high mobility (μFE = 62.7 cm2 V−1 s−1), which makes it apromising way to overcome the mobility/reliability tradeoff in In2O3-based TFTs.
10:45 AM
T12.3 First Demonstration of Monolithic Three-dimensional Integration of Ultra-high Density Hybrid
IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-low Latency (<10ns), Record-low Energy (<10fJ)
of Data Transfer and Ultra-long data retention (>5000s), Menggan Liu1,2, Zhi Li1,2, Wendong Lu1,2, Kaifei
Chen1,2, Jiebin Niu1,2, Fuxi Liao1,2, Zijing Wu1,2, Congyan Lu1, Weizeng Li1, Di Geng1, Nianduan Lu1,
Chunmeng Dou1, Guanhua Yang1, Ling Li1, Ming Liu1 1Laboratory of Microelectronic Devices &Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences(CAS), 2University ofChinese Academy of Sciences
This work firstly demonstrates a monolithic 3D architecture with ultra-high density IGZO/Si SRAM and
IGZO 2T0C DRAM (M3D-SD) integrated in 3-tiers. By incorporating ultra-low leakage IGZO transistor in tier

2 as pass gate and BEOL integration on Si-CMOS cross-coupled inverters (Tier 1), a hybrid IGZO/Si SRAM
is demonstrated with ultra-high density of 4T footprint and 51% reduced static power. In addition, IGZO
2T0C DRAM is integrated in tier 3, which achieves SRAM-DRAM data transfer with record-low latency(<10ns) and energy (2.26fJ). The M3D-SD (with a minimum VDD of 0.35V) can successfully store the data
to IGZO 2T0C DRAM and restore to the hybrid IGZO/Si SRAM after 5000s power off. This work provides anovel M3D platform to boost the memory hierarchy performance.
11:10 AM
T12.4
A Dual-Gate Vertical Channel IGZO Transistor for BEOL Stackable 3D Parallel Integration
for Memory and Computing Applications, Ziyi Liu1, Yiwei Du1, Renrong Liang1, Zhigang Zhang1, Liyang
Pan1, Jianshi Tang1, Bin Gao1, Qi Hu2, Jun Xu1, He Qian1, Huaqiang Wu1, Yuegang Zhang3,4 1School ofIntegrated Circuits, ICFC, BNRist, Tsinghua University, Beijing, China., 2Beijing Superstring Academy ofMemory Technology, Beijing, China, 3State Key Laboratory of Low Dimensional Quantum Physics andDepartment of Physics, Tsinghua University, Beijing, China., 4Frontier Science Center for Quantum
Information, Beijing, China.
In this work, we demonstrate a stackable vertical single/dual-gate(SG/DG) C-shaped-channel field-effecttransistor (VCCFET) based on atomic layer deposition (ALD) In-Ga-Zn-O thin film. with an Ion/Ioff ratio
over1.4×1011 and an on current of 21 μA/μm. And we firstly fabricate vertical dual-gate IGZO transistors,
featuring Gate-All-Around Lateral Gate(LG) and Channel-All-Around Vertical Gate(VG). The dual gates canbe biased simultaneously to enhance gate control ability, Or bias independently to random access andlinearly adjustment threshold voltage(Vth). This makes the transistor broadly applicable of memory andcomputing. Also, this device has future prospect for BEOL(≤300°C) parallel 3D integration, where different
layers of transistors can be formed concurrently with independent source/drain contacts. And the onestep channel formation approach, akin to 3DNAND, reduces lithography costs and eliminates device
performance degradation induced by sequential integration. Keywords: Atomic layer deposition, IGZO,
dual-gate, vertical channel, monolithic 3D integration.
11:35 AM
T12.5 Bit-cost-scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gatearound and Channel-around IGZO FETs, Feng-Min Lee1, Po-Hao Tseng1, Yu-Yu Lin1, Yu-Hsuan Lin1, WeiLung Weng1, Nei-Chih Lin2, Po-Jung Sung2, Chien-Ting Wu2, Chih-Chao Yang2, Wen-Fa Wu2, Chang-HongShen2, Tuo-Hung Hou2, Ming-Hsiu Lee1, Kuang-Yeu Hsieh1, Keh-Chung Wang1, Chih-Yuan Lu1 1Macronix
International Co., Ltd., 2Taiwan Semiconductor Research Inst.
Novel 3D DRAM architectures with 2T0C IGZO gain cell and bit-cost-scalable 3D array are proposed anddemonstrated for the first time. The unit cell is composed of one gate-around (GA) FET and one channelaround (CA) FET to form 2T0C DRAM device, where the GA FET and CA FET serve as the write transistor
and the read transistor, respectively. To verify 3D stacking architecture, we demonstrate the GA IGZO FET
by top metal gate with IGZO channel structure, and the CA IGZO FET by bottom IGZO gate with IGZO
channel. The integrated 3D DRAM memory cell shows excellent device characteristics with >180 second
data retention time and endures >1000 second DC stress on the write and read transistors w/o memory
window closure. The proposed BEoL 2T0C DRAM cell features small footprint, bit-cost scalable 3D array,fast write/read, and good reliability, which is promising for future high density DRAM applications.
Session JFS6: Memory-Centric Computing for LLM
9:55 AM, Tapa 3
Co-Chairs:

Hsinyu Tsai, IBM
Kyomin Sohn, Samsung Electronics Co., Ltd.

9:55 AM
JFS6.1 State-Independent Low Resistance Drift SiSbTe Phase Change Memory for Analog In-Memory
Computing Applications (Invited), HUAI-YU CHENG1, Zhi-Lun Liu1, Amlan Majumdar2, Alexander Grun1,
Asit Ray2, Jeff Su1, Malte J. Rasch2, Fabio Carta2, Lynne Gignac2, Christian Lavoie2, Cheng-Wei Cheng2, Matt
BrightSky2, Hsiang-Lan Lung1 1Macronix International Co., Ltd., 2IBM T. J. Watson Research CenterWe developed a phase-change memory (PCM), with SiSbTe material, that showed state-independent
resistance drift (v~0.04) at 65 oC over the entire analog conductance range. We evaluated this PCM for In
Memory Compute (IMC) applications simulating the performance of BERT model with the IBM Analog
Hardware Acceleration Kit (AIHWKit). Drift and data retention are dependent on the amount of A-type
dopant into SiSbTe materials. Finding a trade-off between the two is important to deliver a balanced
material that can tackle IMC workload without losing in performance. The fabricated SiSbTe PCM devices
maintain the BERT accuracy (<2% loss) for more than 7 days at 65 oC and pass the data retention at
85 oC/48hrs demonstrating a great balance between the two metrics.
10:20 AM
JFS6.2 Cost-effective LLM Accelerator Using Processing in Memory Technology (Invited), hyungdeok
Lee1, guhyun kim1, dayeon yun1, ilkon kim1, yongkee kwon1, Euicheol Lim1 1SK Hynix
Large language model (LLM)-based services continue to improve their performance requires the systemwith both large memory capacity and high memory bandwidth. For the GPT-3 175 billion model to operate
at a minimum, it requires 800GB of storage. In addition, from frequent memory access and limited datareuse also affects memory bandwidth. More powerful memory performance requirements, however,comes with significant costs increase. The expenses associated with operating the necessary equipment
and services to handle these memory and bandwidth requirements are considerable.
SK hynix aims to solve this issue by introducing a Processing in memory (PIM) device and PIM based
accelerator called AiM and AiMX, respectively. By exploiting true bank-level parallelism, AiM and AiMX is
expected to enhance the performance of LLM-based services as a core component of disaggregatedsystem and multi-head attention acceleration. Additionally, AiM also has a potential in on-device AI, in
direction of both performance and energy consumption with low batch size and reducing off-chip data
movement.
10:45 AM
JFS6.3 An Ultra-low Voltage Auger-Recombination Enhanced Hot Hole Injection Scheme in
Implementing a 3 Bits per Cell e-DRAM CIM Macro for Inference Accelerator, T. C. Kao1, M. J. Huang1, Y.
R. Liu1, Y. K. Wang1, J. C. Guo1, Steve Chung1 1National Yang Ming Chiao Tung University
This work proposed a 3 bits per cell e-DRAM Compute-In-Memory (CIM) macro. The programming
mechanism is based on Auger-recombination enhanced hot hole injection (AREHHI). Unlike conventional
SRAM and DRAM architectures, it was designed on the high-performance Logic FinFET platform without
an extra mask. The unit cell was based on three identical transistors, two serving as 1T1C DRAM and theother as computing component. Taking advantage of high linearity and low variability, a 2kb CIM Macrowith untra-small cell size (0.192 µm²) demonstrated high-speed operation (110MHz), significantly lower
programming voltage (0.8V-1.4V), and high endurance, supporting multi-bit operation. Furthermore, we
successfully employed AI inference algorithms to validate the CIM architecture, achieving a test accuracyof 90.07% and an energy efficiency of 56.9 TOPS/W. Overall, this CIM architecture provides an ideal andreliable solution for AI inference in IoT applications.

11:10 AM
JFS6.4 A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM andBlock/Self-Gating CAM for NN/Recommendation Applications, Zhuoyu Dai1, Shengzhe Yan1, Zhaori
Cong1, Zeyu Guo1, Yifan He2, Wenyu Sun2, Chunmeng Dou1, Feng Zhang1, Jinshan Yue1, Yongpan Liu2, Ming
Liu11Institute of Microelectronics of the Chinese Academy of Sciences, 2Tsinghua University
This work presents an energy-efficient CIM-CAM processor for both neural network (NN) andrecommendation system (RecSys) applications. The main contributions include: 1) A reconfigurable ZigZag memory access architecture for diverse convolution/MVM to minimize SRAM access; 2) A backbonesystolic CIM array towards a higher system/macro efficiency ratio; 3) A distribution-aware block/selfgating (DABG) CAM to reduce both off-chip access and on-chip search power for the memory-dominate
embedding layer. The fabricated 28nm chip demonstrates 37.9-81.5TOPS/W system energy efficiency for
NN and 12.3-56.1nJ/request for RecSys. This work achieves 2.4×/3.6× energy/area efficiency for NN and
370× energy reduction for RecSys compared with the state-of-the-art.
11:35 AM
JFS6.5 Monolithic 3D Integration of Analog RRAM-based Fully Weight Stationary and Novel CFET 2T0Cbased Partially Weight Stationary for Accelerating Transformer, H. Yang1, Y. Li1, J. Tang1, R. An1, Y. Zhang1,
L. Gao2, N. Gao2, H. Xu2,3, Y. Du1, Z. Liu1, X. Ma4, G. Wang4, C. Zhao4, J. Xiang4, J. Zhao5, W. Bu6, K. Zheng6,
J. Kang6, B. Gao1, H. Qian1, H. Wu1 1School of Integrated Circuits, Tsinghua University, 2BICIC, Beijing,
China, 3ICTFE, PKU, Taiyuan, China, 4SAMT, Beijing, China, 5DPI, Tsinghua University, 6STIC, Beijing, China
To accelerate transformer with the crucial operation of linear projection and matrix multiplication, we
present the M3D-SFP chip, a monolithic 3D integration of Si-CMOS logic with an analog resistive randomaccess memory (RRAM)-based fully weight stationary (FWS) for linear projections with a weight matrix
fixed to capitalize on its highly efficient matrix-vector multiplication (MVM), complementary FET (CFET)
2T0C-based partially weight stationary (PWS) for data buffer and attention mechanisms with dynamic
matrixes to utilize its easy writing. The novel CFET 2T0C is designed to output a digital voltage, instead of
current, enabling CMOS logic compatibility for CIM, without increasing area due to the stacked nature of
CFET N/P. Futhermore, the functional integrity of the M3D-SFP chip is corroborated by electrical tests withfabricated 128 k-bit RRAM array and CFET 2T0C macro with 164 transistors, while performancebenchmark reveals a 12.9× speed-up over its 2D counterparts.
Session C22: Wireline Circuits II
9:55 AM, Honolulu 1
Co-Chairs:

Trevor Caldwell, Alphawave Semi
Hisakatsu Yamaguchi, Fujitsu Ltd.

9:55 AM
C22.1 A 256Gbps Microring-based WDM Transceiver with Error-free Wide Temperature Operation for
Co-packaged Optical I/O Chiplets, Pavan Bhargava1, Daniel Jeong1, Eric Jan1, Derek Van Orden1, Derek
Kita1, Hayk Gevorgyan1, Sidney Buchbinder1, Anatoly Khilo1, Woorham Bae1, Sung-Jin Kim1, John Fini1,
Norman Chan1, Chen Sun1 1Ayar Labs
We present a 256Gbps WDM transceiver macro for use in co-packaged AI scale-out interconnects. The
macro adopts a 8λ×32Gbps configuration to achieve 256Gbps per fiber. The transceiver macro operates
error-free across a dynamic temperature ramp of 50-110°C, has >4dB optical link margin with 4dBm/𝜆𝜆
input laser power, and consumes 3.45pJ/b (TX+RX). All transmit, receive, thermal control, and opticalcomponents are monolithically integrated in a 45nm SOI process. An optical I/O chiplet with 8 WDM

transceiver macros achieves <1e-15 BER without FEC across 90 hours of operation in a 4Tbps duplex linkconfiguration.
10:20 AM
C22.2 A 48-Gb/s Half-Rate PAM4 Optical Receiver with 0.27-pJ/bit TIA Efficiency, 1.28-pJ/bit RX
Efficiency, and 0.06-mm2 area in 28-nm CMOS, Chongyun Zhang1, Li Wang1, Zilu Liiu1, Fuzhan Chen1,2,Quan Pan2, Xianbo Li3, C. Patrick Yue1 1ECE Department, The Hong Kong University of Science andTechnology, 2School of Microelectronics, Southern University of Science and Technology, 3School ofElectronics and Information Technology, Sun Yat-sen University
This work presents a 48 Gb/s PAM4 optical receiver with TIA and sampler integrated. The proposed TIA
employs transadmittance transimpedance (TAS-TIS) structure to replace conventional CML-based VGA
and post-amplifier, eliminating CTLE and inductive peaking while preserving the linearity and the gainbandwidth product for PAM4 operation. The sampler includes a 2-tap FFE and a 2-tap DFE to compensate
for ISI of the TIA and to recover data. Timing criteria of DFE loop is achieved up to 30 GBaud by optimizing
the clock-to-Q delay of slicers. The RX is implemented in 28 nm CMOS process and wirebonded to acommercial photodiode. Optical measurement results at 48 Gb/s PAM4 show the RX consumes 61.4 mW
with -5.1 dBm sensitivity at 2.4e-4 BER, and the TIA only contributes 13.1 mW, resulting in 1.28 pJ/bit(0.27 pJ/bit for TIA only) efficiency.
10:45 AM
C22.3 A 20Gb/s/pin Single-Ended PAM-4 Transceiver with Pre/Post-Channel Switching Jitter
Compensation and DQS-Driven Biasing for Low-Power Memory Interfaces, Kyunghwan Min1, Jahoon
Jin1, Soo-Min Lee1, Sodam Ju1, Jisu Yook1, Jihoon Lee1, Yunji Hong1, Sung-Sik Park1, Sang-Ho Kim1, Jongwoo
Lee1, Hyungjong Ko1 1Samsung Electronics
This paper presents a 20Gb/s/pin single-ended PAM-4 transceiver with advanced switching jittercompensation (SWJC) technique. The SWJC operates independently of equalization, hence further
improving timing margin from 0.26UI to 0.39UI at a 1e-12 BER. The proposed pre-channel SWJC at atransmitter side minimizes switching jitter (SWJ) of middle eye, modulating the transitions of top andbottom eyes in a beneficial way for SWJC at a receiver side. Ultimately, along with the proposed SWJC
technique, the timing margins improved by SWJC at a receiver side are further increased, having
overheads only 1.6% in power and 0.22% in area.
11:10 AM
C22.4 A 2 X 112 Gb/s 0.34 pJ/b/lane Single-Ended PAM4 Receiver with Multi-Order Crosstalk
Cancellation and Signal Reutilization Technique in 28-nm CMOS, Liping Zhong1,2, Yangyi Zhang1, Xiongshi
Luo1, Hongzhi Wu1,2,2, Xuxu Cheng1, Weitao Wu1, Zhenghao Li1, Quan Pan1 1Southern University of Scienceand Technology, 2southern university of science and technology
This paper presents a 2×112 Gb/s single-ended PAM4 receiver (RX) with multi-order crosstalk cancellationand signal reutilization (MO-XTCR) technique in 28-nm CMOS. An Nth-order far-end crosstalk (FEXT)model is proposed to accurately reveal the intricate FEXT behavior. Based on this model, the MO-XTCR
technique is proposed to minimize the residual FEXT and boost signal reutilization ability. The proposed
RX achieves the horizontal and vertical eye-openings of 53% and 40% for 56 Gb/s NRZ, and 24% and 18%
for 112 Gb/s PAM4, respectively. This work achieves the best energy efficiency of 0.34 pJ/b/lane
compared with state-of-the-art XTC schemes.
Session C23: Neural Recording Interfaces
9:45 AM, Honolulu 2

Co-Chairs:

Phillip Nadeau, Analog Devices
Kenichi Matsunaga, NTT Corporation

9:45 AM
C23.1 SPIRIT: A Seizure Prediction SoC with a 17.2nJ/cls Unsupervised Online-Learning Classifier andZoom Analog Frontends, Adelson Chua1, Aviral Pandey1, Ryan Kaveh1, Sina Faraji Alamouti1, Justin
Doong1, Rikky Muller1 1University of California, Berkeley
This work presents SPIRIT, an SoC integrating an unsupervised online-learning seizure prediction classifier
with eight 14.4μW, 0.057mm2, 90.5dB dynamic range, Zoom Analog Frontends. SPIRIT achieves, on
average, 97.5%/96.2% sensitivity/specificity, predicting seizures an average of 8.4 minutes before theyoccur. Its classifier consumes 17.2μW and occupies 0.14mm2, the lowest reported for a prediction
classifier by >134x in power and >5x in area.
10:10 AM
C23.2 A Highly-Integrated 1536-Channel Quad-Shank Monolithic Neural Probe in 55nm CMOS for FullBand Raw-Signal Recording, Xiaolin Yang1, Joan Aymerich1, Philippe Coppejans1, Wen-Yang Hsu1,
Chutham Sawigun1, Jose Cisneros-Fernández1, Andrea Lodi1, Maribel Caceres Rivera1, Bernardo Tacca1,
Matt McDonald1, Hasan Mahmud-UI1, Barun Dutta1, Jan Putzeys1, Carolina Mora Lopez1 1imec
We present a highly integrated neural probe for in vivo recordings, boasting a record of 1536 channels
and 5120 TiN electrodes. The probe is optimally engineered with integrated capless LDOs and a low-power
LVDS transmitter for energy-efficient data transfer, achieving a high level of integration and minimizing
the number of external components. Innovative block-level optimization techniques result in a total areaof 0.012mm2/ch, a total power of 19.34µW/ch, and the lowest total power-efficiency factor, whileattaining excellent performance uniformity across channels. The probe is fabricated using a fabcompatible 300-mm post-CMOS process and fully validated in saline, demonstrating its ability to record
full-band neural signals.
10:35 AM
C23.3 A 79.2dB-SNDR Slope-Adaptive Dynamic Zoom-and-Track Incremental ΔΣ Neural Recording
Frontend with Resolution-Preservative 192mV/ms Transient Tracking, Sungjin Oh1, Hyunsoo Song1, Jose
R. L. Ruiz1, Wangbo Chen1, Sung-Yun Park1,2, Michael P. Flynn1, Euisik Yoon1 1University of Michigan, 2Pusan
National University
We present an incremental ΔΣ frontend that can resolve µV-level neural signals superimposed with large(>100mV) and fast (>100mV/ms) interferences without quality degradation. Unlike conventional
approaches that stretch conversion range to accept the large input by sacrificing resolution, the proposed
work tracks the large transient with constant high-resolution but variable tracking speed adaptive to its
input slope. Thus, this frontend acquires neural information without quality loss even when exposed tolarge and fast artifacts that overwhelm small neural signals. With the proposed high-resolution tracking
scheme, this work achieves the highest SNDR (79.2dB) and FoMSNDR (165.7dB) among the state-of-the-art
frontends using the conventional transient tracking techniques.
11:00 AM
C23.4 A 3072-Channel Neural Readout IC with Multiplexed Two-Step Incremental-SAR Conversion andBulk-DAC-Based EDO Compensation in 22nm FDSOI, Xiaohua Huang1,2, Xiaolin Yang1, Andrea Lodi1, Chris
Van Hoof1,2, Georges Gielen1,2, Carolina Mora Lopez1 1imec, 2KU Leuven
We introduce a compact neural readout IC (ROIC) for high-resolution, large-scale µECoG arrays able tocapture wideband brain-surface action potentials (APs). It efficiently records from 3072 electrodes via 96

time-multiplexed super-channels. The super-channels feature two-step incremental-SAR (I-SAR)
conversion and area-power-efficient bulk-DACs (BDACs) to handle multiplexed inputs and mitigate
comparator and electrode DC offsets (EDOs). Fabricated in 22nm FDSOI, this prototype achieves thesmallest effective per-channel area to date (0.0004mm2 ) and consumes 0.44µW, while maintaining a low
full-band (1Hz-7.5kHz) input-referred noise (IRN) of 6.38µVrms. The ability to record multiplexed signals
has been successfully demonstrated in saline.
11:25 AM
C23.5 A 16-Ch CMI-Tolerant Neural AFE with Inherent CM Detection and Shared CM Suppression
Achieving 0.006mm2/Ch and 3.1µW/Ch, Joan Aymerich1, Chutham Sawigun1, Jose Cisneros-Fernandez1,
Xiaolin Yang1, Carolina Mora Lopez1,2 1imec, 2Imec
This work introduces a multichannel AFE for compact, low-power bidirectional neural interfaces, capableof tolerating common-mode interferences (CMIs) and capturing action potentials (APs) and local-fieldpotentials (LFPs) with a 10kHz bandwidth (BW). By combining noiseless capacitive common-mode (CM)coupling and intrinsic OTA CM detection, our AFE achieves power- and area-efficient CM suppression(CMS) without input impedance (Zin) nor noise degradations. Our design allows sharing a single CMS loop
across multiple channels, significantly reducing the total area and power. The fabricated proof-of-concept
16-ch AFE prototype tolerates 400mVpp CMIs, consumes 3.1µW/ch, and occupies 0.006mm²/ch, thusachieving the best CMI-tolerance vs. area tradeoff. The CMS capability has been fully demonstrated insaline.
Session C24: High-Speed Data Converters
9:55 AM, Honolulu 3
Co-Chairs:

Namik Kocaman, Broadcom
Yun-Shiang Shu, Mediatek

9:55 AM
C24.1 A 12-bit 16GS/s Single-channel RF-DAC with Hybrid Segmentation for Digital Back-off and Codedependent Free Switch Driver achieving -85dBc IMD3 in 5nm FinFET, Byeongwoo Koo1, Sunghan Do1,
Sangkyu Lee1, Sangpil Nam1, Heewook Shin1, Saemin Im1, Hyochul Shin1, Sungno Lee1, Junsang Park1,
Jungho Lee1, Youngjae Cho1, Michael Choi1, Jongshin Shin1 1Samsung Electronics
This work presents a single-channel 12-bit 16GS/s RF current steering DAC in a 5nm FinFET process. To
achieve high dynamic performance without noise degradation, hybrid segmentation architecture is
implemented with 0.0046mm2 small area. A novel pre-discharge switch drivers remove data dependencyof switching without dynamic element matching (DEM) technique. The prototype DAC shows -85dBc IMD3
and -163dBFS/Hz noise spectral density. The power dissipation is 486mW at 16GS/s sampling with 7.1GHz
output frequency.
10:20 AM
C24.2 A 16GS/s 10b Time-domain ADC using Pipelined-SAR TDC with Delay Variability Compensation
and Background Calibration Achieving 153.8dB FoM in 4nm CMOS, Juzheng Liu1, Ayman Shabra2, Stacy
Ho2, Gabriele Manganaro2, Mike Shuo-Wei Chen1 1University of Southern California, 2MediaTek
The paper presents a 16GS/s 10-bit direct-RF sampling time-domain ADC in 4nm. A background TDC delay
variability calibration scheme and a bottom-plate sampling VTC are proposed. The ADC achieves a 44.48dB
SNDR at Nyquist with 94.2mW power and 8000um2 area, leading to a state-of-the-art 153.8dB FoMS.
10:45 AM

C24.3 A 5nm 60GS/s 7b 64-way Time Interleaved Partial loop unrolled SAR ADC achieving 34dB SNDR
up to 32GHz, Claudio Nani1, Enrico Monaco1, Nicola Ghittori1, Alessandro Bosi1, Domenico Albano1,
Claudio Asero1, Nicola Codega1, Alessio Di Pasquo1, Ivan Fabiano1, Marco Garampazzi1, Fabio Giunco1,
Daniel Burgos1, Gabriele Minoia1, Paolo Rossi1, Marco Sosio1, Leonardo Vignoli1, Enrico Temporiti1, Shawn
Scouten2, Stephen Jantzi3 1Marvell, Pavia, 2Marvell, Ottawa, 3Marvell, Irvine CA
We present a 60GS/s 7b 64-way Time Interleaved (TI) ADC with Analog Front End that features a nonbinary Partial Loop Unrolled (LU) SAR SubADC architecture which enables optimum comparator noise andpower trade off. Comparator offsets among comparators of each SubADC are calibrated in backgroundwithout analog hardware overhead by detecting patterns in the SAR output decisions. Fabricated in 5nm
technology, the prototype AFE and ADC delivers 34.3dB SNDR till 32GHz and draws 109.3mW from 0.9V
supply.
11:10 AM
C24.4 A 12-bit 10GS/s Time-Interleaved SAR ADC with Even/Odd Channel-Correlated Absolute ErrorBased Over-Nyquist Timing-Skew Calibration in 5nm FinFET, Junsang Park1, Jinwoo Park1, Jaemin Hong1,
Sunjae Park1, Dongsuk Lee1, Sungno Lee1, Hyochul Shin1, Kyunghoon Lee1, Byeongwoo Koo1, Youngjae
Cho1, Michael Choi1, Jongshin Shin1 1Samsung Electronics
This paper presents an over-Nyquist 12-bit 10GS/s time-interleaved (TI) ADC with a background timingskew calibration. An absolute error-based auto-correlation algorithm enables calibration of time skew for
both the first and second Nyquist inputs, while an even and odd channel-based auto-correlation algorithm
requires only three calibration steps. A prototype 10GS/s ADC in 5nm FinFET achieves a SNDR of 50.2dB
and 46.2dB at input frequencies of 5GHz and 9GHz, respectively. The ADC consumes 386mW resulting ina FoMWalden and FoMSchreier of 146.0fJ/c-s. and 151.3dB, respectively.
11:35 AM
C24.5 A 10GS/s Hierarchical Time-Interleaved ADC for RF-sampling applications, Nereo Markulic1,
Johan Nguyen1, Jorge Lagos Benites1, Ewout Martens1, Jan Craninckx1 1imec
RF-sampling ADCs above 10GS/s enable modern instrumentation and wireless infrastructure
applications. The key design challenge is to simultaneously guarantee high ENOB and high wide-band
linearity, at moderate power. High ENOB requires large sampling capacitors for low kT/C noise, but theyload the front-end buffer resulting in dynamic distortion at RF. Additionally, substantial power must be
used for low-jitter clock distribution. The presented time-interleaved ADC addresses these challenges with
innovation in (1) front-end and inter-level signal/clock distribution of a hierarchical converter, and (2)wideband-linear signal buffering, delivering higher ENOB than comparable systems [1-3], without theneed for power consuming digital nonlinear distortion correction engines [1,3]. At only 350mW, thepresented 10GS/s ADC delivers 9/8.2 ENOB at low/Nyquist frequencies with SFDR>60dB across 5-GHz BW.
Session T13: Technologies for Power & RF Applications
1:30 PM, Tapa 1
Co-Chairs:

Franck Arnaud, StMicroelectronics
Mitsuru Takenaka, The University of Tokyo

1:30 PM
T13.1 71 GHz-fmax β-Ga2O3-on-SiC RF power MOSFETs with record Pout=3.1 W/mm and
PAE=50.8% at 2 GHz, Pout= 2.3 W/mm at 4 GHz, and low microwave noise figure, Min Zhou1, HongZhou1, Mengwei Si2, Guangjie Gao1, Xiaojin Chen1, Xiaoxiao Zhu1, Kui Dang1, Peijun Ma1, Xiaohua Ma1,
Xuefeng Zheng1, Zhihong Liu1, Jincheng Zhang1, Yuhao Zhang3, Yue Hao1 1Xidian University, 2Shanghai Jiao
Tong University, 3Virginia Polytechnic Institute and State University

In this work, we demonstrate heavily-doped (8×1018 cm-3) and gate-recessed β-Ga2O3 RF power MOSFETs
integrated on a high thermal conductivity SiC substrate to minimize self-heating effect (SHE), high onresistance (Ron) and short-channel effect (SCE). As a result, β-Ga2O3-on-SiC RF power FETs achieve a record
maximum oscillation frequency (fmax) of 71 GHz, output power density (Pout) of 3.1 W/mm and power
added efficiency (PAE) of 50.8% at frequency (f) of 2 GHz and Pout=2.3 W/mm at f=4 GHz. In addition, thiswork for the first time studies the microwave noise performance of the β-Ga2O3 RF MOSFET at f range of
2-18 GHz with low minimum-noise figure (NFmin) of 1.6 dB at f=4 GHz. Remarkably, we have provided aneffective route of oxide RF transistors for future high-f, high-power and low-noise RF power applications.
1:55 PM
T13.2 Field Plate and Package Optimization for GaN Devices and Systems, Tz-Wun Wang1, Sheng-Hsi
Hung1, Chien-Wei Cho1, Po-Jui Chiu1, Chi-Yu Chen1, Ke-Horng Chen1, Kuo-Lin Zheng2, Chih-Chen Li3 1EE,
National Yang Ming Chiao Tung University, 2Chip-GaN Power Semiconductor Corporation, 3MediaTek,
Hsinchu, Taiwan
This work demonstrates the 650V GaN field plate design and the optimized integrated circuit (IC) package.
The source FP length is suggested to be longer but less than three times the split high FP. Longer 1ST FP
and shorter Gap design enhance the Miller ratio and suppress ringing effect.
2:20 PMT13.3 Hybrid Integration of 3D-RF Interconnects on AlGaN/GaN/Si HEMT RF Transistor featuring
2.2W/mm Psat & 41% PAE @28GHz using a Robust and Cost-Effective Chiplet Heterogeneous Bonding
Technique, Alexis Divay1, Olivier Valorge1, Christophe Dubarry1, Mohammed Medbouhi1,1, Rémi
Franiatte1, Daniel Mermin1, Rémi Velard1, Yveline Gobil1, Fanny Morisot1, Erwan Morvan1, Ismaël Charlet1,
Luca Lucci1, José Lugo1, Xavier Garros1 1CEA-LetiThis article presents electrical results of an effective heterogeneous 3D scenario for RF integrated systems:
an AlGaN/GaN/Si HEMT is stacked on Si CPW and interconnected with copper pillars using a high-yield
chiplet heterogeneous integration process. DC and RF measurements confirm the relevance of thisefficient and pragmatic approach regarding electrical performances: copper pillar interconnects exhibit
less than 0.2dB of insertion loss at 28GHz. However, measurements also confirm that the thermal
dissipation of such an integrated system requires special attention in order to maintain valuable system
performance.
2:45 PM
T13.4 Novel Material, Process and Device Innovations for Next Generation Silicon Carbide (SiC) Trench
MOSFET Technology, Pratik B Vyas1, Ludovico Megalini1, Ashish Pal1, Joshua Holt1, Archana Kumar1,
Stephen Weeks1, Charisse Zhao1, Lucien Date1, Hansel Lo1, Michel Khoury1, Safdar Muhammad1, Fabian
Piallat1, Ricky Fang1, William Charles1, Pratim Palit1, Jinghe Yang1, Qintao Zhang1, Jang Seok Oh1, Bryan
Turner1, Samphy Hong1, Aswin Prathap Pitchiya1, Benjamin Briggs1, Jiao Yang1, Dae Yang1, Fengshou
Wang1, Joseph Lee1, Gopal Prabhu1, Dustin Ho1, Carlos Caballero1, Durga Chaturvedula1, Zheng Yuan1, Yi
Zheng1, David A. Britz1, Stephen Krause1, Raghav Sreenivasan1, Michael Chudzik1, Subi Kengeri1, Siddarth
Krishnan1, El Mehdi Bazizi1 1Applied Materials Inc.
New material, process and device design innovations are proposed for next generation SiC trench
MOSFET. Advanced patterning films (APF) are proposed as novel implant hardmask and high temperature
capping material. Novel gate oxide formation processes are demonstrated for improved pattern fidelity& carrier mobility. A novel SiC transistor device design integrating channel counter-implant and pocket
implant is proposed for significant mobility improvement without threshold voltage (VT) loss.
Session T14: Novel Devices for Quantum Computing Applications

1:30 PM, Tapa 2
Co-Chairs:

Thanh Viet Dinh, NXP Semiconductors
Ryuta Tsuchiya, Hitachi Ltd.,

1:30 PMT14.1 Concatenated Continuous Driving for Extending Lifetime of Spin Qubits towards a Scalable
Silicon Quantum Computer, Takuma Kuno1, Takeru Utsugi1, Noriyuki Lee1, Toshiyuki Mine1, Itaru Yanagi1,
Satoshi Muraoka1, Raisei Mizokuchi2, Jun Yoneda2, Tetsuo Kodera2, Takashi Nakajima3, Andrew Ramsay4,
Normann Mertig4, Shinichi Saito1, Digh Hisamoto1, Ryuta Tsuchiya5, Hiroyuki Mizuno1 1Hitachi, Ltd., 2Tokyo
Institute of Technology, 3RIKEN Center for Emergent Matter Science, 4Hitachi Cambridge
Laboratory, 5Hitachi Ltd.
We demonstrate a technique for manipulating silicon spin qubits that will facilitate large-scale integrationof quantum computers. We confirm spin manipulation and evaluate the coherence time of a silicon spin
qubit. The qubit device is fabricated using fully-depleted-silicon-on-insulator (FDSOI) technology. This
promises scalability to large qubit numbers, using commercial semiconductor technology. Furthermore,
we demonstrate concatenated continuous driving (CCD) for spin qubits. This contributes to extending
their coherence time. Specifically, we extend the coherence time of Rabi oscillation from 1.2 µs to over
200 µs. This result shows that spin qubits can be protected against inherent noise in the chip environment,
including fluctuations of magnetic moments of 29Si isotopes in natural Si. This is essential for realizing
quantum computers in silicon.
1:55 PMT14.2 Single-power-supply compatible cryogenic In0.8Ga0.2As quantum-well HEMTs with record
combination of high-frequency and low-noise performance for quantum-computing applications, JiHoon Yoo1, Yong-Soo Jeon1, Seung-Woo Son1, In-Geun Lee1, Hyeon-Bhin Jo1, Su-Min Choi1, Min-Seo Yu1,
Wan-Soo Park1, Hyo-Jin Kim1, Hyeok-Jun Lee1, Sang-Pyeong Son1, Sang-Kuk Kim2, Jacob Yun2, Jae-philShim3, Hyunchul Jang3, Kiwon Lee4, Yongsik Jeong5, Ted Kim2, Chan-Soo Shin3, Tae-Woo Kim6, Jae-Hak Lee1,
Kyunghoon Yang5, Dae-Hyun Kim1 1Kyungpook National University, 2QSI, 3KANC, 4Wonkwang
University, 5KAIST, 6Texax Tech University
We present Lg = 45 nm E-mode cryogenic In0.8Ga0.2As quantum-well (QW) HEMTs with the record
combination of high-frequency and low-noise characteristics. The fabricated devices exhibited a true Emode operation, the best balance between fT = 662 GHz and fmax = 653 GHz, and the lowest √ID/gm = 0.176
at 4 K. Besides, we investigated the temperature-dependent behavior. Three-layer model indicated thatthe reduction of ρbarrier was critical to lower Rs at 4 K. According to the delay time analysis, theimprovement of fT was mainly due to the mitigation of the extrinsic channel charging delay, arising fromthe enhanced carrier transport at 4 K.
2:20 PMT14.3 First Demonstration of Superconducting Nb Contact on Heavily-Doped Group IV
Semiconductor, Gerui Zheng1, Enze Zhang1, Rami Khazaka2, Kaizhen Han1, Haiwen Xu1, Yuxuan Wang1,
Hyunsoo Yang1, Xiao Gong1 1National University of Singapore, 2ASM
We report the first demonstration of superconducting Nb contact on highly boron-doped Si0.35Ge0.65,
achieving an ultra-low contact resistivity (ρc) of 5.22×10-10 Ω-cm2 at 295 K on Si0.35Ge0.65 with active doping
concentration (NA) of 2.80×1021 cm-3. We discover that the contact resistance (Rc) remains low from 295
K to 6 K, with only slight increase from 1.80×10-4 to 2.47×10-4 Ω-cm. However, the superconducting natureof the Nb film at 6 K enables the realization of 28% reduction in total resistance compared with the
Ti/Si0.35Ge0.65 contact. Such property can be obtained with a process thermal budget up to 180 °C,
demonstrating its quantum compatibility.

2:45 PMT14.4 Photon-mediated charge transport and stability of physically-defined and self-organized
germanium quantum dots/SON barriers in few-hole regime at T > 10 K, Chi-Cheng Lai1, Yu-Wen Chiu1, IHsiang Wang1, Ting Tsai1, Jhih-Wei Chen2, Yen-Hsiang Wang2, Mau-Chung Frank Chang2, Horng-Chih Lin1,
Pei-Wen Li1 1National Yang Ming Chiao Tung University, 2University of California, Los Angeles, CA
We report for the first photon-mediated charge transport through physically-defined Ge double quantumdots (DQDs)/Si barrier and QD/Si3N4 single-hole transistor in few-hole regime for high-fidelity qubit
operation at T > 10 K. Engineering strengths of size-tunable QDs, self-organized barriers, and self-aligned
reservoirs enable controllable tunability of charging energy, level spacing and coupling energy of Ge DQDs
by adjusting QD size and barrier width/potential. Hard-wall confinement and photon enhanced carriertransport are facilitated to resolve charge states of DQDs, improve tunneling current properties of SHTs
with high peak-to-valley ratio (~2000), low leakage (~5 fA), large addition energy (~50 meV), low 1/f noise(~10E-26 A2 /Hz), and achieve DQDSHT readout fidelity of 99.92% at T > 10 K.
Session C25: Digital Circuits
1:30 PM, Honolulu 1
Co-Chairs:

Carlos Tokunaga, Intel Corporation
Masanao Yamaoka, Hitachi, Ltd.

1:30 PM
C25.1 A 5.6μW10-Keyword End-to-End Keyword Spotting System Using Passive-Averaging SAR ADC
and Sign-Exponent-Only Layer Fusion with 92.7% Accuracy, Sungjin Park1, Kwanghyun Shin1, Dongkwon
Lee1, Minyoung Kang1, Sunwoo Lee1, Youngmin Park1, Mingoo Seok2, Dongsuk Jeon1 1Seoul National
University, 2Colombia University
This paper presents a 10-keyword end-to-end keyword spotting system. Passive averaging effectively
improves the analog front-end SNR with a small power overhead of 20nW. A sign-exponent-only layer
fusion scheme reduces the model size and multiplication power overhead by 63.5% and 29.8%,
respectively, maintaining the keyword spotting accuracy. Fabricated in 65nm CMOS, the design provides
the highest accuracy of 92.7% and the lowest power consumption of 5.6μW compared to prior arts aimed
at 10 keywords.
1:55 PM
C25.2 An Area-Efficient True Single-Phase Clocked and Conditional Capture Flip-Flop for Ultra-LowPower Operations in 7nm Fin-FET Process, Hyunchul Hwang1, Minsu Kim1, Daeseong Lee1, Yonggeol Kim1,
Byungsu Kim1, Kunhyuk Kang1 1Samsung Electronics
In this paper, we propose a new ultra low-power flip-flop circuit structure that supports true single phaseclock operation and conditional capture characteristics. Simulation results based on 7nm Fin-FET process
shows 63% power reduction while reducing cell area by 7%, compared to the conventional transmissiongate flip-flop. Silicon measure based on a test chip shows successful operation even at 0.33V, proving its
structural robustness near sub-threshold region.
2:20 PM
C25.3 A Mixed-signal 3D Footstep Planning SoC for Motion Control of Humanoid Robots with
Embedded Zero-Moment-Point based Gait Scheduler and Neural Inverse Kinematics, Qiankai Cao1, Juin
Chuen Oh1, Jie Gu1 1Northwestern University
This work presents a footstep planning SoC chip for humanoid robot. A time-domain graph search engine
for 3D footstep planning and mixed-signal zero moment point (ZMP) gait scheduler with neural inverse

kinematics is developed for efficient robot motion control. A 65nm SoC chip is fabricated anddemonstrated in-situ on a humanoid robot with the state-of-the-art search rate and energy efficiency forhumanoid robot control and footstep planning.
2:45 PM
C25.4 A Jammer-Mitigating 267Mb/s 3.78mm2 583mW 32x8 Multi-User MIMO Receiver in
22FDX, Florian Bucheli1, Oscar Castañeda1, Gian Marti1, Christoph Studer1 1ETH Zurich
We present the first multi-user (MU) multiple-input multiple-output (MIMO) receiver ASIC that mitigates
jamming attacks. The ASIC implements a recent nonlinear algorithm that performs joint jammer
mitigation (via spatial filtering) and data detection (using a box prior on the data symbols). Our design
supports 8 user equipments (UEs) and 32 basestation (BS) antennas, QPSK and 16-QAM with soft-outputs,
and enables the mitigation of single-antenna barrage jammers and smart jammers. The fabricated 22nm
FD-SOI ASIC includes preprocessing, has a core area of 3.78mm2, achieves a throughput of 267Mb/s while
consuming 583mW, and is the only existing design that enables reliable data detection under jamming
attacks.
Session C26: Analog Techniques II
1:30 PM, Honolulu 2
Co-Chairs:

Erik Olieman, NXP
Tomohiro Nezuka, MIRISE Technologies Corp.

1:30 PM
C26.1 A Scalable mK Cryo-CMOS Demultiplexer Chip for Voltage Biasing and High-Speed Control of
Silicon Qubit Gates, Sushil Subramanian1, Todor M Mladenov1, Simon Schaal1, Bishnu Patra1, Lester
Lampert1, Nancy K Robinson1, Jeanette Roberts1, Stefano Pellerano1 1Intel Corporation
Large-scale silicon qubit control requires closer integration of control electronics to qubits at the mK stageof the dilution refrigerator to address the wiring bottleneck. We present a mK demultiplexer chip thatuses only two input analog voltages and digital control signals, to provide both DC bias and high-speed
voltage pulsing for up to 64 qubit terminals. Integrated with a foundry qubit chip on the same PCB andcontrolled by a 4 K cryo-CMOS controller, mK cryogenic measurements show multi-terminal
characterization of a qubit device.
1:55 PM
C26.2 A 0.8V Capacitively-Biased BJT-Based Temperature Sensor with an Inaccuracy of ±0.4°C (3σ) from -40°C to 125°C in 22nm CMOS, Zhong Tang1, Haining Wang1, Xiaopeng Yu2, Kofi Makinwa3,
Nick Nianxiong Tan1 1Vango Technologies, Inc, 2Zhejiang University, 3Delft University of Technology
The paper presents a compact sub-1V BJT-based temperature sensor for thermal management
applications. Capacitively-biased PNPs driven by a regulated charge-pump generate PTAT and CTAT
voltages that are readout by an energy and area efficient inverter-based ΣΔ ADC. Fabricated in 22nm
CMOS, the sensor occupies 0.01mm2 and consumes 2.9μW from a 0.8V supply. After a 1-point trim, it
achieves an inaccuracy of ± 0.4 °C (3σ) from -40 °C to 125°C, which is the best reported in sub-65nm CMOS,
as well as high energy efficiency, resulting in a resolution FoM of 0.41pJ∙K2.
2:20 PM
C26.3 A 0.29pJ/step Fully Discrete-Time Charge Domain Bridge-to-Digital Converter for Force Sensingin Spinal Implants Using RC Bridge, Tim Keller1, Rosario Incandela1, Xi Chen1, Hesam Ghiasi1, Mohsen
Khodaee1, Sina Arjmandpour1, Jiawei Liao1, Long He1, Tobias Goetschi2, Jonas Widmer2, Taekwang Jang1

ETH Zurich, 2Spine Biomechanics, Department of Orthopedic Surgery, Balgrist University Hospital,
University of ZurichThis paper proposes a fully discrete-time charge domain bridge-todigital converter for implantable force
sensing after a spinal fusion surgery. We propose an energy-efficient RC bridge to replace the quarter
bridge, reducing power consumption. Further, the sampling capacitor in the bridge is reused in a seriesparallel amplifier (SPA) and charge-injection successive approximation (CI-SAR) analog to digital converter,
thus saving power consumption and reducing the noise. Implemented in 22nm CMOS, the proposed
design achieved an SNR of 55.3dB while consuming 1.38 μW at 10ksps with the lowest reported FoM of
0.29pF/step and the smallest area of 0.07mm2.
1

2:45 PM
C26.4 A 0.72nW, 0.006mm2 32kHz Crystal Oscillator with Adaptive Sub-Harmonic Pulse Injection from
-40°C to 125°C in 22nm FDSOI, Yingjie Zhu1, Yiqing Lan1, Humiao Li1, Haoran Lyu1, Zhen Kong1, Jian Zhao2,
Yida Li1, Guoxing Wang2, Jiamin Li1, Longyang Lin1 1Southern University of Science andTechnology, 2Shanghai jiao Tong University
A sub-nW, single-supply pulse-injection-based crystal oscillator(XO) that operates across a wide
temperature range is presented. The valley-injection timing adaptation circuit achieves <±7% inaccuracy
against PVT variations at 58.8pW. Moreover, the injection distortion compensation and oscillation DC
stabilizing techniques achieve 7× lower peak-injection timing deviation. The IC in 22nm FDSOI achieves a
11ppb Allan deviation floor at 0.72nW and 0.006mm2, and enables the widest reported temperature
range of -40°C to 125°C.
Session C27: Sensors and Displays
1:30 PM, Honolulu 3
Co-Chairs:

Inhee Lee, University of Pittsburgh
Wangyeong Jung, KAIST

1:30 PM
C27.1 An OLED Display Driver IC Embedding -63dB CMR, 80mV/nA Sensitivity, 390pA Detectable, andColumn-Parallel Pixel Current Readout for Real-Time Non-Uniformity Compensation, Gyu-Wan Lim1,
Gyeong-Gu Kang1, Seunghwa Shin1, Kihyun Kim1, Yousung Park1, Won Kim2, Young-Bok Kim2, Hyun-Kyu
Jeon2, Hyun-Sik Kim1 1KAIST, 2LX Semicon
This paper presents a display driver IC that embeds column-parallel 11b pixel-current readouts tocompensate for display non-uniformity. Leveraging the source-driven TFT pixel, the proposed techniques
facilitate real-time current sensing, even while the display is active. Fabricated in 180nm, the chip achievesa -63dB rejection to common noise, a 390pA/LSB resolution, and an 80mV/nA sensitivity. Demonstrations
with real LEDs effectively validated the pixel current sensing.
1:55 PM
C27.2 A 92.8% Power Reduction Event-Driven Dual-Mode Touch Analog Front-End IC Featuring
620&[mu]W Self-Capacitance Sensing and 500fps Mutual-Capacitance Sensing, Jonghang Choi1, Ingu
Jeong1, Seok-Won Jung1, Jun-Eun Park1 1Sungkyunkwan University
This paper presents an energy-efficient dual-mode touch- sensor analog front-end (AFE) IC that supports
an event-driven operation. The proposed AFE consists of 1) an ultralow-power self-capacitance sensing(LP-SCS) and 2) a high-performance mutual-capacitance sensing (HP-MCS). Once the LP-SCS detects atouch input during a standby mode, the HP-MCS is triggered to start the mutual capacitance sensing withhigh SNR and high frame rate. The event-driven dual-mode sensing can reduce the AFE powerconsumption up to 92.8%. The proposed AFE IC was fabricated in an 80nm CMOS process. The measured
power consumptions are 0.62mW and 8.65mW for the LP-SCS and the HP-MCS, respectively. The
measured SNRs of the LP-SCS and the HP-MCS are 52.6dB and 40.2dB with frame rate of 60Hz and 500Hz,
respectively.
2:20 PM
C27.3 A 0.9-2.6pW 0.1-0.25V 22nm 2-bit Supply-to-Digital Converter Using Always-Activated SupplyControlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed
Time-Stamped Bio-Recording, Hiroaki Kitaike1, Masaharu Inada1, Mitsuru Terauchi1, Hironori Tagawa1,
Ryosuke Nagai1, Shufan Xu1, Ruilin Zhang1, Kunyang Liu1, Kiichi Niitsu1 1Kyoto University
This paper presents a low-power supply-to-digital converter for bio-recording system where bio fuel cellprovides both power and sensing data. It is achieved by supply-controlled oscillator, supply-dependent
activation buffers (SDAB), and encoders. A 22-nm prototype chip exhibits its feasibility with a power of
0.9-2.6 pW under 0.1-0.25 V.
2:45 PM
C27.4 E-Textile Battery-Less Walking Step Counting System with <23 pW Power, Dual- Function
Harvesting from Breathing, and No High-Voltage CMOS Process, Anil Kumar Gundu1, Luigi Fassio1,
Massimo Alioto1 1National University of Singapore
An e-textile walking step counting full system (smart Tshirt) is presented. Harvesting from co-designed
low-voltage triboelectric nanogenerator (TENG) pushes over-voltage protection/rectification on chip.
Conformability and minimal off-chip components are achieved via dual-function harvester/sensor reuse
and battery/passive elimination. Always-on power reduction to pWs enables uninterrupted operation
while solely powered by breathing harvesting.
Session T15: Non-Volatile Memory Technology - Hafnia Based Ferroelectrics-2
3:25 PM, Tapa 1
Co-Chairs:

Karl Hofmann, Infineon Technologies
Kenji Tateiwa, TPSCo

3:25 PM
T15.1 Low-Damage Processed and High-Pressure Annealed High-κ Hafnium Zirconium Oxide
Capacitors near Morphotropic Phase Boundary with Record-Low EOT of 2.4Å & high-κ of 70 for DRAM
Technology, Venkateswarlu Gaddam1, Junghyeon Hwang1, Hunbeom Shin1, Chaeheon Kim1, Giuk Kim1,
Hyung-Jun Kim2, Jooho Lee2, Hyun-Cheol Kim3, Bumsu Park3, Suhwan Lim3, Sang Yun Kim3, Kwangsoo Kim3,
Sungho Lee3, Daewon Ha3, Jinho Ahn4, Sanghun Jeon1 1KAIST, 2Samsung Advanced Institute ofTechnology, 3Samsung Electronics, 4Hanyang University
We present record-low equivalent oxide thickness (EOT) of 2.4 Å with a remarkable dielectric constant (κ)
of 64 at 4.1nm-thick hafnium-based films with no wake-up characteristics. In comparison to conventional
HZO films, our remarkable achievement stems from the high-quality crystalline structure with less oxygen
vacancies formed by a low-damage process, as evidenced by high-angle annular dark-field scanningtransmission electron microscopy (HAADF-STEM) images and electron energy-loss spectroscopy (EELS)
analysis. In addition, with high-pressure annealing (HPA), we were able to reduce the annealing
temperature to 450°C leading to a decrease in leakage current (1.5 order). Further, increasing themeasurement temperature from 298K to 389K results in the high-κ from 66 to 70, which is the theoreticallimit of the κ value of t-phase.

3:50 PM
T15.2 Revealing Mechanism of Non-accumulative Disturb and Approach Toward Disturb Suppressionin HZO/Si FeFET Memory, Masaki Otomo1, Kasidit Toprasertpong1, Zuocheng Cai1, Zhenhong Liu1, Mitsuru
Takenaka1, Shinichi Takagi1 1The University of Tokyo
The mechanism of repeated read/write disturb in Hf0.5Zr0.5O2 (HZO)/Si FeFETs is systematically studied.
Disturb in FeFETs, found not to be a simple accumulation of repeated disturbs, is modeled with a
combination of two mechanisms: trap dynamics and polarization dynamics. The amount of polarization
reversed by disturb is evaluated to separate the two dynamics. We show that the suppression of disturb
field in HZO due to de-trapping (trap dynamics model) and the relaxation of partially reversed polarization
during the disturb interval (polarization dynamics model) are the two origins of the non-accumulative
property of disturb, where each mechanism dominates in different disturb voltage and duration. We also
show that the disturb behavior depends on the HZO thickness, and demonstrate a new approach tosuppress disturb by applying substrate bias (Vsub) during disturb intervals.
4:15 PM
T15.3 BEOL Compatible Ultra-Low Operating Voltage (0.5 V) and Preconfigured Switching Polarization
States in Effective 3 nm Ferroelectric HZO Capacitors, Minjong Lee1, Jiyoung Kim1, Jin-Hyun Kim1, Dan N.
Le1, Seojun Lee1, Si-Un Song1, Rino Choi2, Youngbae Ahn3, Seung Wook Ryu3, Pil-Ryung Cha4, Chang-Yong
Nam5, Seongbin Park6, Jongmug Kang6, Si Joon Kim6 1The University of Texas at Dallas, 2Inha University, 3SK
hynix inc. R&D, 4Kookmin University, 5Brookhaven National Laboratory, 6Kangwon National University
We report the record-high remanent polarization value (2Pr ~55 µC/cm2) at an ultra-low operating voltage(0.5 V) with effective 3 nm hafnium zirconium oxide (HZO) capacitors. This exceptional ferroelectric
property is achieved at a back-end-of-line (BEOL) compatible temperature below 400 °C. Moreover, ourdevices demonstrate configurable ferroelectric saturation characteristics, ensuring reliable andreproducible switching polarization states (Psw). These results potentially allow the design of novel
ferroelectric device circuitry. This study highlights the feasibility of extremely low-power ferroelectric
applications beyond 0.5 V operation in BEOL.
4:40 PM
T15.4 Comprehensive Analysis of Duty-cycle Induced Degradations in HfxZr1-xO2-based Ferroelectric
Capacitors: Behavior, Modeling, and Optimization, Guan Feng1,2, Yu Li1, Hao Jiang1, Xiaodong Wang1,2,
Yize Sun1, Yingfen Wei1, Qi Liu1,2, Ming Liu1,2 1State Key Laboratory of Integrated Chips and Systems,
Frontier Institute of Chip and System, Fudan University, Shanghai, 200433, China, 2School ofMicroelectronics, Fudan University, Shanghai, 200433, China
This work systematically studies degradations in HfxZr1-xO2 (HZO)-based ferroelectric (FE) capacitors(FeCaps) under pulses with different duty cycles (DCs): 1) a larger drop in the switchable polarization (Psw)
and shift in the coercive voltage (Vc) by duty-cycling are observed when compared with conventional
endurance and retention tests; 2) through physical modeling, the wider spread of the generated oxygen
vacancies (Vos) during duty-cycling leads to stronger domain pinning and the formation of a larger builtin field (Ebi), which explains the above observation; 3) optimizations through engineering the stack andcomposition of the HZO FE layer are proposed and validated on 128Kbit 2T2C FeRAM chips.
5:05 PM
T15.5 Engineering HZO by Flat Amorphous TiN with 0.3nm Roughness Achieving Uniform c-axis
Alignment, Record High Breakdown Field (~10nm HZO), and Record Final 2Pr of 56 μC/cm² with
Endurance > 4E12, Zefu Zhao1, Yu-Rui Chen1, Yu-Tsung Liao1, Yun-Wen Chen1, Wan-Hsuan Hsieh1, Jer-Fu
Wang1, Yu-An Chen1, Hao-Yi Lu2, Wei-Teng Hsu1, Dai-Ying Lee3, Ming-Hsiu Lee3, C. W. Liu1,2,4 1Graduate
Institute of Electronics Engineering, National Taiwan University, 2Graduate School of Advanced

Technology, National Taiwan University, 3Emerging Central Lab., Macronix International Co., Ltd., Hsinchu,
Taiwan, R.O.C., 4Graduate Institute of Photonics and Optoelectronics, National Taiwan University
Metal-ferroelectric-metal capacitors with flat amorphous TiN are demonstrated to achieve c-axis oforthorhombic phase well-aligned along deposition direction, uniform electric field, negligible fatigue, andhigh remanent polarization (2Pr) of 62 μC/cm2. The large lattice misfit between crystalline TiN and HZOcreates larger barrier to form the o-phase HZO as compared to amorphous TiN underlayer. Usingchemical-mechanical polishing can obtain a 0.3nm roughness flat TiN, measured by AFM. HZO on flat
amorphous TiN exhibits uniform and record breakdown field (EBD) of 4.8/-5.1 MV/cm for
positive/negative voltage. A flat TiN mitigates formation of oxygen vacancies as compared to rough TiNdue to weak and uniform electric field in HZO. After 4E12 endurance cycles, the HZO on flat TiN exhibits arecord final 2Pr of 56 μC/cm2 due to small dipole pinning by Vo2+. This work demonstrates the way toachieve uniformly high 2Pr, large EBD, and high endurance by flat amorphous TiN.
Session T16: Reliability, Characterization & Modeling of Oxide Semiconductor and Si Devices-2
3:25 PM, Tapa 2
Co-Chairs:

Nandakumar Mahalingam, Texas Instruments
Yoshiki Yamamoto, Renesas Electronics

3:25 PM
T16.1 Unveiling the Impact of AC PBTI on Hydrogen Formation in Oxide Semiconductor
Transistors, Gan Liu1, Qiwen Kong1, Zuopu Zhou1, Ying Xu1, Chen Sun1, Kaizhen Han1, Yuye Kang1, Dong
Zhang1, Xiaolin Wang1, Yang Feng1, Wei Shi1, Bich-Yen Nguyen2, Kai Ni3, GengChiau Liang1,4, Xiao Gong1
1
National University of Singapore, 2Soitec, 3University of Notre Dame, 4Industry Academia Innovation
School, National Yang-Ming Chiao Tung University
For the first time, we elucidate the impact of both alternating current (AC) and direct current (DC) positive
bias temperature instability (PBTI) on hydrogen (H) formation of oxide semiconductor FETs (OSFET). Ourinvestigation employs a systematic and holistic analysis on the highly stable co-sputtered Indium-GalliumZinc-Tin-oxide (IGZTO) FETs. Key discoveries include: (1) There are distinctive variations between AC andDC PBTI results at high temperatures (T). (2) In AC PBTI, both frequency (f) and duty factor (DF) play a
crucial role in mitigating the H formation effect. (3) DF exhibits a more influential impact than f. (4) AC
PBTI, particularly at 25% DF and 1 MHz, can alleviate up to 99.2% of the threshold voltage change (ΔVth)induced by H formation from DC PBTI. These findings contribute significant insights into the H formation
mechanism, providing a more relevant and accurate understanding of PBTI reliability across diverse realworld applications.
3:50 PMT16.2 Positive Bias Stress Measurement Guideline and Band Analysis for Evaluating Instability of
Oxide Semiconductor Transistors, Qi Jiang1, Koustav Jana1, Kasidit Toprasertpong1, Shuhan Liu1, H.-S.
Philip Wong1 1Stanford University
Instability of oxide semiconductor field effect transistors (OSFET) under positive bias stress (PBS) is one of
the major hinderances to broad adoption by the semiconductor industry. We present a holistic
understanding of the OSFET behavior under PBS, by comparing OSFETs with different channel doping(NCH), hence different initial threshold voltages (VTH). Our analysis reveals that the band profile of OSFETs
under a given voltage is strongly dependent on their channel doping, resulting in different stress responses
even for the same material properties. This raises the important question of finding the right metric toevaluate the stability of OSFETs. This work makes significant strides in establishing a PBS test guideline toensure a fair benchmark method of OSFETs with vastly different NCH, and understanding of the associatedtrade-off between PBS stability and VTH.

4:15 PMT16.3 Positive to Negative Schottky Barrier Transition in Metal/Oxide Semiconductor Contacts by
Tuning Indium Concentration in IGZO, Sumi Lee1, Chang Niu1, Yizhi Zhang1, Haiyan Wang1, Peide Ye1
1
Purdue University
In this work, we report the tunability of electrical performance and metal-to-semiconductor contact
properties in atomic-layer-deposited (ALD) InGaZnO (IGZO) field-effect transistors (FETs) by precisely
manipulating the In:Ga:Zn ratios. Our fabricated IGZO FETs exhibit well-behaved saturation in the shortchannel length (Lch) of 80 nm and a high on-current of 850 μA/μm. Through temperature-dependent
characterizations, we observed the transition from a negative to a positive Schottky barrier (ΦSB) by
adjusting the indium (In) concentrations. This transition is explained by the changes in the charge
neutrality level (CNL) and Fermi level (EF) at the contact interface. The impact of surface
accumulation/depletion at the metal/semiconductor interface provides the new insight into the realm ofcontact engineering.
4:40 PMT16.4 Fluorine Plasma Treatment-Enabled ITO Transistors: Excellent Reliability and Comprehensive
Understanding of Temperature Dependence from 77 K to 375 K, Xuanqi Chen1, Gan Liu1, Wei Shi1, Yuye
Kang1, Qiwen Kong1, Yuxuan Wang1, Rui Shao1, Bich-Yen Nguyen2, Gengchiau Liang1,3, Kaizhen Han1, Xiao
Gong1 National University of Singapore, 2Soitec, 3National Yang-Ming Chiao Tung University
For the first time, we demonstrated the Fluorine (F) plasma-treated indium-tin-oxide field-effecttransistors (ITO:F FETs) with comprehensive understanding of their electrical characteristics, lowfrequency noise (LFN), and reliability across a broad range of temperatures, spanning from 77 K to 375 K.
Remarkably, the ITO:F FET demonstrates excellent reliability. After 1 ks positive bias stressing under anelectric field (Eov: Vov/Tox) of 2.5 MV/cm, the ITO:F FET performs threshold voltage shifts (∆VTH) of 18 mV(300 K) and less than 3.77 mV (77 K) has been achieved. Furthermore, the ITO:F FET maintains its
performance in other key figure-of-merits (FoMs) compared to its fluorine-free counterpart, including afield-effect mobility (μeff) of ~89 cm²/V·s (Ncarrier of 5×1012 cm-2), a subthreshold swing (SS) of 46
mV/decade at 77 K, and a drive current (ION) exceeding 1500 μA/μm (77 K).
5:05 PMT16.5 A Novel Method for Extracting Asymmetric Source and Drain Resistance in IGZO Vertical
Channel Transistors, Sungwon Yoo1, Yongjin Lee1, WooJe Jung1, Hwan Kim1, Seongjae Byeon1, Miryeon
Kim1, Juho Lee2, Tackhwi Lee1, Minji Hong1, Young Geun Song1, Seungwon Lee1, Masayuki Terai1, Kyongjun
Yoo1, Changhyuk Sung1, Wonsok Lee1, Min Hee Cho1, Dae Sin Kim2, Daewon Ha1, Sujin Ahn1, Jaihyuk Song1
1
Semiconductor R&D Center, Samsung Electronics, 2Computational Science & Engineering group,
Samsung Electronics
Unlike conventional resistance extraction method, a novel method enabling to simply extract thesource/drain resistance including contact resistance is, for the first time, hereby proposed in the IGZO
vertical channel transistor (VCT). IGZO VCT has uneven source and drain structure inducing considerable
asymmetricity in source and drain resistances, thus the extraction of them is very important. This method
is based on the fact that the amount of current varies significantly depending on the direction of electron
injection in the structure forming the schottky contacts. Experimental results show that this method isadequate to evaluate improvements in the contact resistance and thus applicable for source and drain
resistance analysis in oxide semiconductor structures.
Session T17: Memory Technology: NAND, DRAM-2
3:25 PM, Tapa 3

Co-Chairs:

Alessandro Calderoni, Micron Technology
Tomohiko Kudo, Micron

3:25 PM
T17.1 DRAM-peri FinFET – A Thermally-stable High-Performance Advanced CMOS RMG Platform with
Mo-based pWFM for sub-10nm DRAM, Jishnu Ganguly1, Hiroaki Arimura1, Romain Ritzenthaler1, Harsh
Bana2, Jan Willem Maes2, Ju-Geng Lai1, Stephan Brus1, Waleed Maqsood1, Ritam Sarkar1, Balaji Kannan3,
Elena Capogreco1, Vladimir Machkaoutsan4, Seunghwan Yoon5, Alessio Spessot1, Michael Givens2, Naoto
Horiguchi1 1imec, 2ASM Leuven, 3ASM Phoenix, 4Micron Technology, 5SK Hynix
We report on an improved thermally-stable, high-performance CMOS RMG FinFET platform for DRAMperiphery beyond the 10nm node. This is a first demonstration of novel Mo and MoN work-function metal(WFM) integration into a high-performance dual-WFM + dual-dipole logic RMG flow, capable of enduringhigh thermal-budget linked to memory-array fabrication. We demonstrate superior N/P Vt balancecompared to a TiN/TiAl dual-WFM + dual-dipole CMOS reference, as well as 0.12V PMOS Vt with Mo
pWFM coupled with p-dipole down to scaled gate-lengths with excellent short-channel control.
3:50 PMT17.2 4F2 Stackable Polysilicon Channel Access Device for Ultra-Dense NVDRAM, Albert Liao1, Matthew
Jerry1, Kamal Karda1, Matt Hollander1, Pankaj Sharma1, Ruijing Ge1, Ting Zhao1, Gabriel Khalil EL hajjam1,
Marcello Mariani1, Marcello Calabrese1, Davide Raimondi1, Antonino Rigano1, Tommaso Rossi1, Karine
Florent1, Nick Tapias1, Clement Jacob1, Alessandro Calderoni1, Sameer Chhajed1, John Zahurak1, Nirmal
Ramaswamy1 1Micron
We report on the methodology and optimization used to enable a stackable 4F2 polysilicon thin filmtransistor (TFT) for ultra-dense 32 Gb NVDRAM. Several key innovations are implemented to meet thestrict thermal budget constraints required for a dual-layer technology. Confined heating from pulsed laser
annealing is used to crystallize polysilicon and activate source/drain dopants. Material optimization isused to engineer both a gate oxide deposited at low temperatures capable of 10 years equivalentreliability and a Ru wordline (WL) robust to agglomeration and voiding failures. Device performance,robust to top layer processing, is matched across both layers by adjusting process conditions as informed
by a TCAD model that accounts for heat transfer and crystallization dynamics.
4:15 PM
T17.3 A Three Dimensional DRAM (3D DRAM) Technology for the Next Decades (Late News), Joodong
Park1, kangsik Choi1, Seunghwan Kim1, Jungwon Seo1, Hongseong Kang1, Seungwan Chu1, Seokwon Bae1,
Jeonghoon Kwon1, Gilseop Kim1, Yongtaek Park1, Junha Kwak1, Dongil Song1, Sungmean Park1, Yongtaik
Kim1, Kyoungchul Jang1, Jinsun Cho1, Heesun Lee1, Byungho Lee1, Jinwon Park1, Jihye Lee1, Hyuk Kwon1,
Dosun You1, Chansun Hyun1, Jaejung Lee1, Seungcheol Lee1, Ildo Kim1, Juhyun Myung1, Hyungsik Won1,
Junho Cheon1, Kyunghoon Kim1, Jiho Kang1, Seungbum Kim1, Kihong Lee1, Suock Chung1, Seonsoon Kim1,
Byoungki Lee1, Choonhwan Kim1, Seonyong Cha1 1SKhynix
Three dimensional structured DRAM technology has drawn huge attention recently for its potential tofulfill high speed operation and low power consumption. In this paper, 3D DRAM with vertical bit line (BL)architecture is introduced as a promising solution to overcome scaling limitation for future
DRAM technology. Full chip integration with 5-layered cell stacked on peri-core wafer is successfully
demonstrated for the first time, offering superior on-current performance and gate controllability. A
novel process integration scheme using Si/SiGe sacrificial multilayers and hybrid wafer
bonding technique is presented with excellent full chip operation of 3D DRAM.
4:40 PMT17.4 Cell to Core-Periphery Overlap (C2O) based on BCAT for next generation DRAM, Kiseok Lee1,
Hongjun Lee1, Hyungeun Choi1, Jeongsu Kim1, Kyunghwan Kim1, Moonyoung Jeong1, Soohyun Bae1,
Hyebin Kim1, Jiyun Lee1, Minsoo Kim1, Keunnam Kim1, Huijung Kim1, Sungmin Park1, Taejin Park1, Jin-woo
Han1, Jeonghoon Oh1, Yong Kwan Kim1, Sungsoo Yim1, Bongsoo Kim1, Jemin Park1, Jaihyuk Song2 1DRAM
Technology Development, Samsung Electronics Co. Ltd., 2Device Solutions CTO, Samsung Electronics Co.
Ltd.
The ongoing trend of DRAM design rule scaling has faced with serious challenges. This paper focuses onsustaining the scaling momentum by introducing Cell to Core-Periphery Overlap (C2O) based on Buried
Channel Array Transistors (BCAT). This approach enables bit growth and bit cost reduction with less scaling
and introducing wafer bonding technique. Moreover, by expanding the core area and reducing mismatch,
we significantly enhance sensing characteristics, thereby relaxing the storage capacitance burden.
Additionally, stress-induced experiments by the wafer bonding process demonstrate that these
improvements do not adversely affect the performance of DRAM core-periphery transistors.
5:05 PM
T17.5 Single metal BCAT breakthrough to open a new era of 12 nm DRAM and beyond, Kyosuk Chae1,
Taiuk Rim2, Youngwoo Son3, Heejae Choi3,3, Jinseong Lee3,4, Shinwoo Jeong3, Jieun Lee3, DONGIN Lee3,
Byunghyun Lee3,3, Dongsoo Woo3, Seguen Park3, Sangjun Hwang3 1Samsung Electronics, 2Samsung
Elecronics, 3Samsung Elecronics, 4Samsung Electronics
As the transistor area reaches the atomic scale, many technical challenges have occurred, jeopardizing
the lifespan of DRAM scaling, of which word line (WL) resistive defects and Row hammer (R/H) failures
are two of the most important quality problems. This paper introduces an innovative process technology
to realize a high-purity and low-resistance cell WL that can solve two critical hurdles simultaneously,
enabling the DRAM node of 12 nm and beyond. This technology verified a decrease in WL resistance by~50% and a two orders of magnitude improvement in R/H fail bits. In addition, by reducing interface trap
density (Nit), significant enhancements in the on/off characteristic window and air transportation defects
were obtained.
Session C28: Processors II
3:25 PM, Honolulu 1
Co-Chairs:

Lindsey Kostas, Qualcomm
Yukihiro Sasagawa, Socionext Inc.

3:25 PM
C28.1 Medusa: A 0.83/4.6 µ/Frame 86/91.6%-CIFAR-10 tinyML Processor with Pipelined Pixel
Streaming of Bottleneck Layers in 28nm CMOS, Rohan Prashant Doshi1, Massimo Giordano1, Justin Olah1,
Zhidong Cao1, MoonHyung Jang1, Luke R Upton1, Athanasios Ramkaj1, Boris Murmann1 1Stanford
University
Medusa is a 28 nm programmable 8-bit processor that achieves state-of-the-art inference energy acrossa range of always-on tiny Machine Learning (tinyML) tasks. It features custom 6T-latch-based Inner Loop
Memories (ILMs) optimized for tinyML that achieve a read energy of 15 fJ/Byte, and its Pipelined Pixel
Streaming (PPS) architecture leverages ILMs to reduce system-level memory access energy by up to 9.5x.
Medusa performs inference image-to-label, with native support for critical tinyML operations, including
memory-intensive depthwise separable convolution-based bottleneck layers. It achieves 0.83/4.6µJ/Frame at a latency of 0.6/2.6 ms and an accuracy of 86.2/91.6% on CIFAR-10, advancing the state-ofthe art in inference energy by 3.4x/4.9x. In addition, it achieves 0.23 µJ/Frame at 0.27 ms and 90.8% on
Google Speech Commands and 5.0 µJ/Frame and 3.8 ms at 81.5% on Visual Wake Words.

3:50 PM
C28.2 A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management andCompute-in-Memory Two-Stage Event-Driven Wakeup, Yanchi Dong1, Xueping Liu1, Kangbo Bai1,
Guoxiang Li1, Meng Wu1, Yiqi Jing1, Yihan Zhang1, Pixian Zhan2, Yadong Zhang2, Yufei Ma1, Ru Huang1, Le
Ye1,3, Tianyu Jia1 1Peking University, 2Nano Core Chip Electronic Technology, 3Advanced Institute ofInformation Technology of Peking University
This paper presents a heterogeneous TinyML SoC with E2P-aware system-level energy management
achieving a minimum 3.5µW and 30000× peak-to-idle power ratio. The energy-event-performance (E2P)aware management utilizes various fully synthesizable monitors to be aware of the runtime status ofheterogeneous blocks and hierarchical voltage regulation for MEP search at system level, which gains>28% energy saving compared to single block MEP. A 2-stage CIM-based event-driven wakeup scheme isalso developed to reduce the always-on energy by over 87%. The presented TinyML SoC is suitable foredge AI applications with state-of-the-art low-power features.
4:15 PM
C28.3 A 101mW, 280fps Scene Graph Generation Processor for Visual Context Understanding on
Mobile Devices, Chun-Wei Chang1, I-Ting Lin1, Chia-Hsiang Yang1 1Graduate Institute of Electronics
Engineering, National Taiwan University, Taipei, Taiwan
This work presents the first dedicated scene graph generation (SGG) processor for visual context
understanding. Algorithm-architecture co-optimizations are applied to reduce the computational
complexity. The memory usage is minimized through hybrid sparsity encoding and the energy efficiency
is enhanced by utilizing reconfigurable multiply-accumulate (MAC) array architecture. The characteristicof the sigmoid function is leveraged to reduce the computations for edge features. Fabricated in 40-nm
CMOS, the chip achieves a throughput of 280fps with an energy consumption of 0.36mJ/frame. It deliversa 154x higher throughput with 1,800x less power, yielding 2.7x105x higher energy efficiency than GPU.
4:40 PM
C28.4 An 11.4mm2 40.2Gbps 17.4pJ/b/iteration Soft-Decision Open Forward Error Correction Decoder
for Optical Communication, Cheng-Hsun Lu1, Wei Tang1, Jiyoon Han1, Zhengya Zhang1 1University ofMichigan
An iterative soft-decision open Forward Error Correction (oFEC) decoder is presented. The design utilizes
a tile-based architecture, a difference-based soft-decision decoding for oFEC’s component BoseChaudhuri-Hocquenghem (BCH) code, a low-latency general interleaver, and a matrix memory tailored tothe oFEC structure. A dual-core prototype, implemented in Intel 16, occupies 11.4mm² and achieves
40.2Gbps at 17.4pJ/b/iteration.
Session C29: PLLs
3:25 PM, Honolulu 2
Co-Chairs:

Alvin Loke, NXP Semiconductors
Atsushi Motozawa, Renesas Electronics

3:25 PM
C29.1 A 9-GHz Subsampling-Chopper PLL with Charge-Share Cancelling and Achieving 57.8-fs-rms
Jitter with 15dB In-band Noise Improvement, Xiangjian Kong1, Kai Xu2, Robert Bogdan Staszewski3,
Mingchao Jian1, Chunbing Guo1 1Guangdong University of Technology, 2King’s College London, 3University
College Dublin, IrelandA 9-GHz sub-sampling (SS) PLL employs a new chopping charge-pump (CP) with controlled pre-charging
or pre-discharging to cancel the charge sharing during the chopper’s phase swapping, thus eliminating its
1/f noise. Fabricated in 65-nm CMOS, the prototype achieves 57.8-fs rms jitter with -111.9-dBc/Hz in-bandnoise at 1kHz offset.
3:50 PM
C29.2 A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS
Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur, Tianle Chen1,2, Hongyu Ren1,2, Zunsong Yang1,
Yunbo Huang3, Xianghe Meng1, Weiwei Yan1, Weidong Zhang1, Xuqiang Zheng1, Xuan Guo1, Tetsuya
Iizuka4, Pui-In Mak3, Yong Chen3, Bo Li1 1Institute of Microelectronics of the Chinese Academy of Sciences,
Beijing, China, 2University of Chinese Academy of Sciences, Beijing, China, 3University of Macau, Macau,
China, 4The University of Tokyo, Tokyo, Japan
A dual-edge subsampling phase-locked loop (SSPLL) is proposed to reduce the in-band phase noise (PN)of the crystal oscillator (XO) and reference buffer (RBUF) by 3dB without degrading frequency resolution.
It is able to achieve even and odd locking modes by configuring the dual-edge subsampling phase detector(SSPD) to ensure that the PLL can lock in steps of FREF. With a 100-MHz input reference and 6.5-to-6.9-GHz
output, the prototype in 65-nm CMOS achieves an RMS jitter of 44fs, a jitter-power figure-of-merit(FOMJitter) of −260.7-dB, and a spur level of −76.5dBc. The total power consumption is 4.4mW at 6.8GHz.
4:15 PM
C29.3 A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique, Riccardo Moleri1,
Simone Mattia Dartizio1, Michele Rossoni1, Giacomo Castoro1, Francesco Tesolin1, Dmytro Cherniak2, Carlo
Samori1, Andrea Leonardo Lacaita1, Salvatore Levantino1 1Politecnico di Milano, 2Infineon Technologies
This work presents a fractional-N digital PLL leveraging a digital-to-time converter (DTC) chopping
technique to improve spectral purity and jitter. By randomly moving the DTC between the reference anddivider paths of the PLL, the fractional spurs induced by DTC non-linearity and the DTC flicker noise
suppressed. The synthesizer, fabricated in 28nm CMOS, achieves 79.3fsrms jitter and -63.6dBc fractional
spur at 9.275GHz near-integer channels
4:40 PM
C29.4 A 5GHz Fractional-N PLL with 97fsrms Jitter and -255.3dB FoM, Zhiqiang Huang1, Fengjun Chen1,
Shuangfeng Kong1 1The Hong Kong University of Science and Technology
By employing a binary-search-based DTC nonlinearity calibration technique with an auxiliary-DTC-based
TDC, a 5GHz fractional-N PLL with a 100MHz reference is proposed to achieve a calibration time of 8.7us
for DTC nonlinearity correction. With the DTC nonlinearity calibration, a gated LMS-based DTC gain
calibration with DSM-1, and a tree-like DTC to reduce DTC’s delay and jitter, the proposed PLL measures-62dBc in-band fractional spurs and an integrated jitter of 97fs with 3.15mW power consumption,
resulting in a FoM of -255.3dB.