Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT6153-KHM
Dual 2-Channel CTLE with Peak Detectors
High-speed adjustable linear equalizer
Two independent data channels with two independent equalization paths per channel
Independently adjustable 5 zeros and 2 poles in each path AC response
Independent gain adjustment in each equalization path
High-speed CMOS 3-wire interface for chip control
Input peak detectors in both channels



Fully differential CML-type analog input and output interfaces
Two power supplies for the data paths and AC control circuitry
Average power consumption: 1.4W



Fabricated in SiGe for high performance, yield, and reliabilityLimited temperature variation over industrial temperature rangeDie size 1.5x1.5mm2

Custom CQFN 44-pin package

SCLK
vcc
SSnvcc
pkd1
vcc
q11p
vcc
q11n
vcc
v5p0








33 32 31 30 29 28 27 26 25 24 23

2

3456

78veevcc
q12pvcc
q12nvcc
q21p
vcc
q21n
vcc
vee

9 10 11MOSIvccMISO
vcc
pkd2
vcc
q22n
vcc
q22pvccv5p0112 13 14 15 16 17 18 19 20 21 22

44 43 42 41 40 39 38 37 36 35 34

veevccd1pvccd1nvccd2pvccd2nvccvee

Rev.0.4.2

1March 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
Channel 1

Peak Detector
+
-vcc

+-+
-

pkd1
q11p
q11n+
-46
46

crl1x6d1pd1nControl
Block1:3
46

crl2x6vccMOSISCLK
SSnMISOvcc

vcc
46+-+-+-SPI+-q12p
q12n
q21p
q21n
q22p
q22n
pkd2

d2pd2nChannel 2Fig. 1. Functional Block Diagram

The IC shown in Fig. 1 is a two-channel adjustable continuous-time linear equalizer (CTLE)
with two independently controlled analog data equalization paths per channel. Each equalization
path has its own output. The AC response of each path has 6 controls: adjustable DC gain, 3
independently adjustable zeros, and 2 independently adjustable poles.
Input Peak Detectors that represent the input signal amplitude are added to each channel.
The part’s I/Os support CML-type differential interface with on-chip 46Ohm termination to vcc.
Matching external terminations are also required.
All operational modes of the chip are controlled by a Control Block that communicates with an
external computer through a high-speed 3-wire serial interface.
The part operates with a positive supply vcc = +3.3V for the main data paths, and an additional
positive supply v5p0 = +5.0V for the AC control circuitry. The negative supply rail vee should
be connected to external ground as shown in Fig. 2a.
The part can also operate with a negative supply vee = -3.3V for the main data paths, and anadditional positive supply v5p0 = +1.7V for the AC control circuitry. In this case the positive

Rev.0.4.2

2March 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

supply rail vcc should be connected to external ground as shown in Fig. 2b. Also, the SPI input
and output signals should be connected through DC blocks, or optocouplers.

+3.3V- G +vee=gnd vcc

+5.0V
- G +

-3.3V
- G +v5p0

veea.

+1.7V
- G +vcc=gnd v5p0b.

Fig. 2. Power Supply Configurations: Positive (a) and Negative (b)Equalization Path
Typical AC responses of an Equalization Path are shown in Fig. 3.
Zero 1

Zero 2

Zero 3

All Poles=Min, all Zeros=Max
All Poles=Min, all Zeros=Max

All Poles=Max, all Zeros=Min
All Poles=Max, all Zeros=Min

Fig. 3. Typical AC responses of an Equalization Path

Each path has 3 independent adjustable Zeros, and two independent adjustable Poles. For eachsetting, the DC gain can be adjusted between -3dB and +5dB.

Rev.0.4.2

3March 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Additionally, the path’s bandwidth (BW) can be also adjusted as shown by the red and magenta
curves in Fig. 4 that are plotted for the Max Pole, and Min Zero setting.

Fig. 4. DC Gain and BW Control Characteristics

Peak Detector
The Peak Detector block represents the single-ended swing of its input signal as an output
voltage between 1.65V to 2.85V. The typical characteristics for a 1GHz sinusoidal input signal atdifferent PT operational conditions are shown in Fig. 5.

Fig. 5. Peak Detector Typical Simulated Characteristics for Different Tº and Process Corners

Rev.0.4.2

4March 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

As can be seen in the plot, the signal swings below a certain value are represented by the highvoltage above 3.0V. This function can be used as an indication of NO Input Signal (Loss-ofsignal, or LOS). The LOS threshold can be adjusted as desired.
The Peak Detector features a short settling time as shown in Fig. 6 that shows the sinusoidal
input signal, and the Peak Detector output at different operational conditions.

a.

b.
Fig. 6. Peak Detector settling Time (a – Nominal, b – Worst Case Slow)

Rev.0.4.2

5March 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

3-Wire Interface
All functions of the chip are controlled through a 3-wire SPI. The interface includes a 16-byte
internal register, and operates with 3.3V CMOS signals. It provides control signals for any of 2groups of channels: Group A (Channels 1 and 2), and Group B (Channels 3 and 4). Each groupdata can be loaded independently, and the active group is selected by bit1 of byte16 in each data
packet. The bit map of the interface is shown in Table 1.
Table 1. 3-Wire Interface Bit Map

Byte # Bit # Bit order Signal name Default Value
Signal function
From 7 MSB
1zcl1_110000000
to 0
LSB
From 7 MSB
2zcm1_110000000
to 0
LSB
From 7 MSB
3zch1_101000000
to 0
LSB
From 7 MSB
4gc_110000000
to 0
LSB
From 7 MSB
5pc1_110000000
to 0
LSB
From 7 MSB
6pc2_110000000
to 0
LSB
From 7 MSB
7efc110000000
to 0
LSB
From 7 MSB
8zcl1_210000000
to 0
LSB
From 7 MSB
9zcm1_210000000
to 0
LSB
From 7 MSB
10zch1_201000000
to 0
LSB
From 7 MSB
11gc_210000000
to 0
LSB
From 7 MSB
12pc1_2
10000000
to 0
LSB
From 7 MSB
13
pc2_2
10000000
to 0
LSB
From 7 MSB
14efc2
10000000
to 0
LSB
From 7 MSB
15
losth1
10000000
to 0
LSB
From 7 MSB
efc12100000
to 2
LSB
16“0” – write to Group A,
1wraddr0“1” – write to Group B
00Constant “0”Rev.0.4.2

6March 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

The initial registers of the SPI are preset to the above default states at the time of the chip power
supply activation.

TERMINAL FUNCTIONSTERMINAL
Name No.
Typed1pd1nd2pd2nq11p
q11nq12pq12nq21pq21nq22pq22n

3638404227252018161497SSn 31
SCLK 33MOSI 1MISO 3
pkd1 29
pkd2 5

Namev5p0veevcc

Description

High-Speed I/Os
CML-type Differential high-speed channel 1 data inputs with internal SE 46Ohm
Analogtermination to vcc
InputsDifferential high-speed channel 2 data inputs with internal SE 46Ohm
termination to vcc
CML-type Differential high-speed channel 1 path 1 data outputs with internal SEAnalog
46Ohm termination to vcc
Outputs Differential high-speed channel 1 path 2 data outputs with internal SE
46Ohm termination to vcc
Differential high-speed channel 2 path 1 data outputs with internal SE
46Ohm termination to vcc
Differential high-speed channel 2 path 2 data outputs with internal SE
46Ohm termination to vcc
Low-Speed I/Os
3.3V
3-wire interface enable input with internal 474KOhm pull-up to vcc
CMOS
3-wire interface clock input with internal 474KOhm pull-down to vee
I/Os
3-wire interface data input with internal 474KOhm pull-down to vee
3-wire interface data output
CMOS
Error Detector output and below-threshold signal amplitude indicator,
Outputwith internal 6KOhm SE termination to vcc
Supply And Termination Voltages
Description
Pin Number+5.0V positive power supply
11, 23
Negative pin to vee
Ground12, 22, 34, 44+3.3V positive power supply
2, 4, 6, 8, 10, 13, 15, 17, 19, 21, 24, 26, 28,
Negative pin to vee
30, 32, 35, 37, 39, 41, 43ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 2 may cause damage to thisproduct and/or lead to reduced reliability. Functional performance is specified over therecommended operating conditions for power supply and temperature only. AC and DC device
characteristics at or beyond the absolute maximum ratings are not assumed or implied. All minand max voltage limits are referenced to ground (assumed vee).
Rev.0.4.2

7March 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Table 2. Absolute Maximum Ratings

Parameter
Main Supply Voltage (vcc)
Additional Supply Voltage (v5p0)
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max
3.6
5.5
750
+85
+1009898

Units
VVmVºCºC%%

ELECTRICAL CHARACTERISTICSPARAMETERTYP MAX UNIT
COMMENTS
General Parameters
0.0
V
External ground
vee
3.1
3.3
3.5
V
vcc in relation to vee
vcc
4.8
5.0
5.3
V
v5p0 in relation to vee
v5p0
Iv5p0835mA
Depending on the state of
SPI control bytes
Ivcc
300600mA
Power Consumption
1.1
1.4
2.1W
vcc ramp speed
10ms
For reliable SPI preset
Junction temperature
050
125°C
Data input (d1p/d1n, d2p/d2n)
Data Rate
DC32Gb/s
SE Swing (differential300mV
0.3% THD at 1GHz
signal is applied)
500mV
0.9% THD at 1GHzCM Level
vcc-Swing/2
for DC input termination
Data output (q11p/q11n, q12p/q12n, q21p/q21n, q22p/q22n)
Max peaking frequency
1624GHz
Gain from Input-3+5dB
Depending on SPI settings
CM Level
vcc-0.35
Vfor DC output termination
Peak Detector output (pkd1, pkd2)
Voltage range
1.65
2.88
VFor input swing control
3.05
3.25
VFor LOS operation
Settling time
1520
ns3-Wire Interface Port
Clock frequency
0.1
50
MHz
Input low logic levelvee
vee+0.3
V
Input high logic levelvcc-1.3
vcc
V
Output low logic levelvee
vee+0.2
V
Output high logic levelvcc-0.3
vcc
VInput current
9uA
For each input

Rev.0.4.2

MIN

8March 2021Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATIONThe chip die is housed in a custom, 44-pin CQFN package shown in Fig. 7. The package
provides a center heat slug located on the back side of the package to be used for heatdissipation. ADSANTEC recommends using extreme caution when soldering this section to theboard to avoid overheating. It should be connected to the vcc plain that is ground for thenegative supply, or power for the positive supply.
The part’s identification label is ASNT6153-KHM. The first 8 characters of the name before thedash identify the bare die including general circuit family, fabrication technology, specific circuit
type, and part version while the 3 digits after the underscore represent the package’s
manufacturer, type, and pin out count.
This device complies with Commission Delegated Directive (EU) 2015/863 of 4 June 2015
amending Annex II to Directive 2011/65/EU of the European Parliament and of the Council asregards the list of restricted substances (Text with EEA relevance) on the restriction of the use ofcertain hazardous substances in electrical and electronics equipment (RoHS Directive) in
accordance with the definitions set forth in the directives for all ten substances.

Fig. 7. CQFN44 Package Drawing (All Dimensions in mm)

Rev.0.4.2

9March 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
0.4.2

Date
03-2021

0.3.2
0.2.2

12-2020
12-2020

0.1.2
0.0.2

12-2020
12-2020

Rev.0.4.2

ChangesAdded power supply diagrams
Changed recommendation for the package soldering
Corrected temperature specifications
Corrected Absolute Maximum RF swing
Corrected pkd1/2 terminal description
Corrected Electrical Specifications table
Corrected SPI description
Preliminary release

10

March 2021