Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

ASNT8110A-PQB
DC-to-24GHz Programmable Integer Divider with SPI

Adjustable power consumptionEasy 8-bit parallel programming interface compatible with CMOS/LVTTL standards



Optional external reset function

Dynamic division ratio adjustment with a short set-up time (about 20ns after the pulse edge on anycontrol input)

Single +2.8V or -2.8V power supplyIndustrial temperature rangeStandard 40-pin QFN package with a thermal pad

c5

ncnc

c7

c0

vee

vddnc

ncresetvcc

ASNT8110A

3wenin

cop1

vee

icore

vee

iclk

vee

vcc

vcc

chin

3wdin

chip

con

vcc

3wcinspion

vcc

3wdo

vcc

vee

Rev. 1.2.2

vee



c1

Fully differential CML input and output interfaces

c2

vcc

50% duty cycle of the output divided clock signal

c3

c4

Continuous division ratios from 1 to 256

vcc

c6

Wide frequency range from DC to 24GHzvee

October 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

DESCRIPTIONASNT8110A-PQB is a high-speed programmable integer clock divider with dynamic adjustment of thedivision ratio. An optional external active-high CMOS/LVTTL reset signal is also provided. The
functional block diagram of the device is shown in Fig. 1.
iclk
vcc

icore

vcc

vcc
50

50
copchip

÷ 1…256chin
50

50
vcc

vdd

3wenin
3wcin
3wdin
3wdo

reset

vcc

c7
c6
c5c4
c3
c2
c1
c0

Digital Interfacespion

veeconFig. 1. Functional Block Diagram

The divider accepts an input clock signal (chip/chin) with a speed from DC to the maximum specified
frequency and provides a clean 50% duty cycle output divided clock signal (cop/con) in any operationalmode. The divider allows for dynamic adjustment of the division ratio from 1 to 256 with a step of 1
through either full-scale CMOS 8-bit parallel interface or 1.2V CMOS 3-wire SPI. The parallel or serialinterface mode is selected with a full-scale CMOS control signal spion.
In the parallel mode, a binary code on the control inputs (c0-c7) defines the value of the ratio from 1 to255, where c7 is the most significant bit (MSB). All “0”s (“low” state) define the division by 256.
Following any change of any control signal, the divider switches to idle after (64...128) periods of thehigh-speed system clock plus an additional 1.6ns delay, and returns back to normal operation with the
new division ratio after an additional delay equal to 192 periods of the high-speed system clock.
In the serial mode, the 1-byte division coefficient code is supplied through the 3-wire interface with MSB
first as shown in Fig. 2. Input data 3wdin are sampled at rising edges of SPI clock 3wcin and internal
division coefficient value will be updated at a rising edge of the 3wenin signal.
3wcin
3wenin3wdin XC7 C6 C5 C4 C3 C2 C1 C0X

Fig. 2. SPI Bit Order

Rev. 1.2.22October 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

The device automatically resets itself after the initial power-up and any change of the division control
signals. When the optional external reset signal reset is set to “high”, the divider switches to idle (static“0” output) after a 0.7ns delay as shown in the timing diagram in Fig. 3. When reset returns to “low”, thedivider switches back to normal operation after (64...128) periods of the high-speed system clock plus anadditional 1.6ns of delay. The minimum allowed reset pulse must be longer than 64 periods of the highspeed system clock.
T> 64T
0.7ns(64...128)T+1.6nsFig. 3. Timing Diagram

The part’s I/O’s support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (also see POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.

POWER SUPPLY CONFIGURATION
The part can operate with either a negative supply (vcc=0.0V=ground), or a positive supply (vee = 0.0V =ground). In case of the positive supply, all I/Os need AC termination when connected to any devices with50Ohm termination to ground. Different PCB layouts will be needed for each different power supply
combination.
The parts power consumption may be reduce by up to 30% using external resistors to connect the control
ports iclk and icore to vee. It is recommended to activate iclk first and then activate icore if required
because current reduction results in a lower maximum operational frequency and icore has larger
impact than iclk!

All the characteristics detailed below assume vcc = +2.8V and vee = 0V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground.

Rev. 1.2.23October 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vcc)
Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010

Max+3.3
3.2
1.0+90+1009898UnitsVW
VºCºC%%TERMINAL FUNCTIONSTERMINAL
Name No.
Typechipchin
copcon561513reset

35

3wenin
3wcin
3wdin
3wdo

36
38
392spion

3c0c1c2c3c4c5c6c7

1922
23
25
26
28
2932

iclk
icore

Rev. 1.2.2

89DESCRIPTION

High-Speed I/Os
CML input Differential clock inputs with internal SE 50Ohm termination to vcc.
CML output Differential divided clock outputs with internal SE 50Ohm
termination to vcc. Require external SE 50Ohm termination to vcc.
Low-Speed I/Osvee/vcc External active-high reset port
CMOS input
1.2V CMOS 3-wire enable active-low signal (SSn)input
3-wire input clock (SCLK)
3-wire input data (MOSI)
1.2V CMOS 3-wire ouptut data (MISO)
outputDigital Controls
vee/vcc External SPI activation port (active: high, SPI is enabled; default: low,
CMOS input SPI is disabled)vee/vcc Division binary control signals
CMOS input

Analog Controls
Analog input Power control ports with internal 800Ohm termination to vee; require
external resistors between 120Ohm and 6KOhm connected to vee orexternal power supplies with current sinking capability; may be left
not connected
4October 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

Namevccvddveenc

Supply And Termination Voltages
Description
Pin Number
Main positive power supply or ground
4, 7, 12, 14, 16, 24, 27, 37
Digital positive power supply
18
Negative power supply or ground
1, 10-11, 21, 30, 33, 40
Not connected pins
17, 20, 31, 34

ELECTRICAL CHARACTERISTICSPARAMETERveevcc
vddIveePower consumptionJunction temperature
Frequency
Swing
CM Level
Rise/Fall Times
Frequency
Logic “1” level
Logic “0” level
Rise/Fall Times
Additive Jitter
Duty Cycle
Logic “1” level
Logic “0” level

MIN

TYP

MAX UNITCOMMENTS
General Parameters
0.0
V
External ground
2.6
2.8
3.0
V
1.2
1.3
V
very low current consumption
920mA
R=120Ohm between iclk/icore and vee
1250mA
R>6KOhm between iclk/icore and vee
2.6W
R=120Ohm between iclk/icore and vee
3.5
W
R>6KOhm between iclk/icore and vee-2550
125°CInput (chip, chin)
0.024
GHz75
400
1000mV
Differential or SE, p-p; at 6GHz
vcc- (SE swing)/23
ns20%-80%
Output (cop, con)
0.024
GHzVvccvcc-0.6
VWith external 50Ohm DC termination
151719ps
20%-80%TBD
ps
Peak-to-Peak
47% 50% 53%
For clock signal
Select (c0-c7) & Reset (reset)
VCC-0.4
VVEE+0.4
VPACKAGE INFORMATIONThe chip is packaged in a standard 40-pin QFN package shown Fig. 4. It is recommended that the center
heat slug located on the back side of the package is soldered to ground to help dissipate heat generated by
the chip during operation.
The part’s identification label is ASNT8110A-PQB. The first 9 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
Rev. 1.2.2

5October 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402www.adsantec.com

This device complies with the Restriction of Hazardous Substances (RoHS) per EU 2002/95/EC for all sixsubstances.

Fig. 4. QFN 40-Pin Package Drawing (All Dimensions in mm)

REVISION HISTORY
Revision
1.2.2
1.1.2

1.0.1

0.0.1

Rev. 1.2.2

DateChanges
10-2019 Corrected input swing specifications
08-2019 Corrected header
Corrected termination conditions for control ports
Corrected minimum current/power consumption
07-2017 Corrected title
Corrected maximum speed
Corrected power consumption
Corrected package drawing
04-2017 Preliminary release6October 2019