JAERI-Conf 95-021

PB11
Development of a Two-Tap FIR Filter
for Bunch-by-Bunc h Feedback Systems
Makoto Tobiyama, Eiji Kikutani, Takashi Taniguchi and Shin-ichi Kurokawa
National Laboratory for High Energy Physics, 1-1 Oho, Tsukuba 305, Japan
Abstract
Simple digital filter system for bunch-by-bunch feedback
systems have been developed. A two-tap FIR filter madeof pure hardware system realizes the functions of the phaseshift by goo, the suppression of the static (DC) component
and the digital delay of up to a hundred of turns. The
difficulties in circuit board, such as the tuning of the time
skews or the problem of the long-time reliability, have beensolved by the development of custom GaAs LSis which
demultiplex and multiplex the fast digital data comingfrom ADC. The board has the size of 366.71x460 mm andis controlled through a VME interface. An applicationof the filter board, the transient memory recorder with
40 Mbytes of memory, enables us to analyze the oscillation
modes of a multibunch beam with enough time span.
I. Introduction
For a storage ring which accumulate many bunches withhigh beam current, such as KEKB or PEP-II, it is very
likely that it occurs many strong coupled bunch instabilities both in transverse and longitudinal planes. The
methods to analyze and suppress these instabilities havethe key to achieve the designed quality of the accelerators.
As the reduction of the sources of impedance, thestrongest one comes from the higher order modes in theRF cavities, is essential to suppress the instabilities, somekind of special cavities to make impedance of higher ordermodes very low will be employedllJ,[ 2 ].[3 1. However, evenwith these cavities, impedance of some dangerous modes
may remain high. Because of the many bunches withsmall bunch spacing, the frequency view of the instabilities
will be complicated and spread over wide frequency range.
To cure those unexpected instabilities, we are now developing beam feedback systems with the bunch-by-bunch
schemel4 1.
In the bunch-by-bunch feedback system, we detect theindividual bunch oscillations separately, shift the phase of
the signal by goo, then kick the beam to damp the oscillation. In this paper we describe the digital filter system developed for KEKB rings which realize the functionsof phase shift of any desired value, DC suppression andadjustable digital time delay. Related parameters of theKEKB accelerators are listed in Table I and are used without further explanations.

RingEnergy
Circumference
Beam current
RF frequency
Harmonic number
Particles /bunch
Synchrotron tune

LER
3.5EcI

h3016.26
2.6/RF

Nv.

HER
8

1.1
508.8875120
3.3 X 10 10 1.4 X 10 100.01 rv 0.02

GeVmAMHzTable IMain parameters of KEKB.

of a beam, feedback signals must wait the bunch re-arrivalat the kicker after about one revolution of the bunch.
The great progress in the digital circuit technology, suchas the speedy evolution of the digital signal processor(DSP), enables us to design complicated digital filter withconsiderable speed. It is completely programmable andhas amazing flexibility. We can change the code dynamically even in the operation period without spoiling thefunction of the filter. Nevertheless, the present processor
is not capable to handle the signal from the ADC alone.
Demultiplexing and parallel processing with many DSPs
is necessary. Moreover, in many cases we should employ
the down sampling techniquel5 1 to reduce the number ofthe DSPs.
Another approach, which we will employ for KEKBrings, is to make the simplest digital filter with the fast
hardware logic circuits without down sampling technique.
F. Pedersen of CERN has proposed the hardware two-tap
FIR scheme for the filterl 6 1. As shown in Fig. 1, it has
only two taps (-1) and (+1) at -270° and -goo of theoscillation. The frequency response has peaks at j., 3j.,

II. Selection of the filter
As the longitudinal front-end detects the position of abunch in our case, it is necessary to shift the phase of thesignal by goo with the filter. The static (DC) componentof a position signal, which will be a function of the relative
position from the head of a bunch train, has no meaningand should be rejected from the feedback signal because it
spends expensive feedback power in vainly. As the speedof a signal in a circuit or in a cable is far slower than that

Figure. 1. Tap positions for the 2-Tap FIR filter.
· · · and has zeros at 0, 2/., · · ·. The passband around j.
is wide. We expect no filtering effect for noise component
but for the DC. It is not a problem because we have measured the S /N of the detected signal from the ring andfound very low noise components. The phase shift and-278-

JAERI-Conf 95-021

the time delay are tunable with the selection of the tap
positions with keeping the time between the two taps.
The difficulties of the filter lie on the complication of
the high-frequency digital circuits. It accesses memories
three times (one write and two reads) within one data period, in our case, 2 ns. This access speed is completely unreachable without demultiplexin g the digital data in many
parallel lines. Demultiplexi ng part is a fairly complicatedcircuit which needs very skilled treatments on the design
and tuning of the time skews of many lines and the selection of the chips with same characteristic s. The difficultyin the final multiplexing process is also a severe problem.
The reliability of the board will be fairly doubtful. Making this filter with the combination of existing products
seems to be impossible.
The difficulties have been solved by the developmentof custom LSis to demultiplex and multiplex fast digital
data. The small chips contain high speed circuits which
would occupy large area with skilled treatments on theboard. This maintenance- free chips enable us to use dense
memories of CMOS technology and ensures high reliability
for the board.

Figure 2 shows the bottom view of the FDMUX(GHDK4211) and FMUX (GHDK4212) chip.

III. Custom LSis

IV. Design of the filter board

The circuit design and fabrication of the custom LSis forthe fast data demultiplexe r (FDMUX) and the fast data
multiplexe (FMUX) was made by Oki Electric Industry
Co. Ltd. Table II shows the main specifications of theLSis.

Figure 3 shows the block diagram of the filter board.
The size of the mother board is 366.71 mmx460 mm,
where prior size corresponds to the triple height board of
the VME bus. On the mother board, there are FDMUXs,FMUXs, a DAC, field programmabl e gate array (FPGA)
chips for the address control. There are 16 slots of connectors on the board for the memory /subtracter daughter board. An ADC is also mounted on another daughterboard.

TechnologyFunction
Integration
Max. Clock freq.
Supply voltage
1/0Power consump.
Pacl<aging

FMUX
FDMUX
0.5J.tm GaAs DCFL
16:1x 4bit
1:16 x 4bit
rvl.5k gates rv 1.7k gates> 700MHz
3.3V and 2.0V
PECL and Lv-TTL
1.7W
2.5W
136pins ceramic QFPTable II
Main specifications for FDMUX and FMUX.

A. FDMUX

FDMUX demultiplexs 4 bits pseudo-ECL (PECL) signal up to 700 MHz to 16 channels X 4 bits of Lv-TTL signal. Here, PECL means the signal level of shifted by +2 V
from the ordinary ECL level and the Lv-TTL means the
reduced high level (3.3 V) TTL signal. By combining thetwo FDMUXs, we can create a 1:16 demultiplexer of 8 bits
easily using the built-in synchronizer. The timing signal
is also used to synchronize the FDMUX and the FMUX.
All 16 channels 8 bits data are output simultaneously. It
also offers two kinds of basic timing signals of Lv-TTL for
the use of the downstream circuits. These basic timing
signals will be useful and enough for many applications.
B. FMUXFMUX multiplexes 16 channels x 4 bits of Lv-TTL signal to 4 bits PECL signal. Same as FDMUX, we can use
16:1 multiplexer with 8bits. It offes teh basic timing signals of Lv-TTL and PECL levels.

Figure. 2. Bottom view of FDMUX (GHDK4211) andFMUX (GHDK4212)

A. ADC and DAC
We have a few candidates for the ADC which works
under system clock of 508 MHz and has a enough analog
bandwidth. We adopted a MAX101 of MAXIM, whichworks 500 MSPS with an 8 bit accuracy and have 1.1 GHz· of analog bandwidth. It has a 1:2 demultiplexer in thechip so there are 2 channels of outputs.
We have more candidates of DAC for our purpose. We
have chosen a TQ6122-M of TriQuint which works up to
1 GHz with an 8 bit accuracy and have a 2:1 multiplexer
in the chip.
Because of the demultiplexer in MAX101, we will use 4FDMUXs and 4 FMUXs on the board. The output of theADC are therefore demultiplexe d with 32 channels. The
system clock (255 MHz) for upper 16 channels (A) andlower 16 channels (B) are supplied from the ADC. Each16 channel works simultaneously.
B. Memory and ALU daughter board
Each channel handles 160 bunches for the case of KEKBrings. We use two sets of ring memories (A and B) per
each channel to reduce the memory access from three (onewrite and two read) to two (one write and one read). Data
from FDMUX is written in both memories in the sameaddress simultaneously. In the next step, we read -90°
data from memory A, -270° data from memory Bin thesame timing with different memory address. Because thetime period of the data output from FDMUXs are about
64 ns, the use of CMOS SRAM with access speed (WE) of12 ns ensures us enough time margin. As it is necessary to-279-

JAERI-Conf 95-021

Feedback signal

MCM6709A x 4H

64kbh4bit

254M Hz508.5MHz RFSOB.SMHz

CONTEX data

SLCK(16MHzFPGAYXINME lntertace

Figure. 3. Block diagram of the filter board. It has 4 FDMUXs and 4 FMUXs.
accumulate at least 100 turns of revolutions per a bunch,
total memories needed amounts to 5120x100x2 bytes.
We use a FPGA with the function of an subtracter. Italso contains a bit-shift mechanism that shifts the outputof the subtracter from 0 to 3 bit upward. It enables us tochange the gain of the filter up to 20 dB dynamically.

C. Address controller and interface

clearly. This memory board will be completed by the endof 1995.
VI. Summary
For the circular accelerators that accumulate manybunches with fairly high beam current, the bunch-bybunch feedback system will play a great role in the suppression and in the analysis of the instabilities. On the development of the bunch-by-bunch feedback system, however, there lie many difficulties concerning to the bandwidth of the system. In KEKB rings, the use of the custom
LSis for demultiplexing and multiplexing the digital data
enables us to develop the pure hardware two-tap FIR filter
system without downsampling technique, on one board of
tirple-hight of VME. We expect that the board has good
reliability because of the packaged high frequency circuitsin the LISs. The feasibility of the board will be tested withthe feedback experiment at TRISTAN-AR in these years.

We must control three addresses pointers for memory access. One is the write address (WAB) that works
508.8 MHz/32=16 MHz. Other two addresses are used topoint the 90° (RA) and 270° (RB) previous data for thebunch to feedback. We can set the address shifts of (RBRA) and (WAB-RA) through a VME interface. Needlessto say, the value must be multiples of 160 for the correct
feedback. The difference between WAB and RA should
be selected to tune the time delay of the feedback signal
so as to have a maximum gain. We can change the timedelay with the 2 ns step.
This board is now under fabrication and will be completed by the end of the September, 1995 and will be tested
under the operation at TRISTAN-AR.

[2]

V. Application to beam-dynamics studies[3]

The mother board is capable to the application ofa transient memory recorder by replacing the memory /subtracter daughter board with a dense memoryboard and by replacing the address control FPGAs. In ourdesign, the maximum memory we can mount on the board
will be about 40 MB. For the KEKB rings, it will accumulate 8192 turns of bunch positions for all 5120 bunches.
Combining the memory board and the feedback systemenables us to measure the growth of the instability very[4]References[1][5][6]-280-

T. Kageyama et. al., in Proceedings of 1995 IEEE
PAC, Dallas, U.S.A./ KEK Preprint 95-52.
N. Akasaka et. al., in Proceedings of 1995 IEEE PAC,Dallas, U.S.A./ KEK Preprint 95-53.
T. Tajima et. al., in Proceedings of 1995 IEEE PAC,Dallas, U.S.A./ KEK Preprint 95-77.
E. Kikutani, et. al., in Proceedings of 1995 IEEE
PAC, Dallas, U.S.A./ KEK Preprint 95-20.
H. Hindi et. al. SLAC-PUB-5772, March 1992
F. Pedersen, Multibunch Feedback- Transverse, Longitudinal and RF Cavity Feedback, Talk given at
the Workshop "Factories withe+ e- Rings", Benalmadena, Spain, November, 1992.