Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT8121-KMC
DC-34Gbps Linear Phase Detector

Output clock duty cycle indicatorData edge density indicator

Fully differential CML input data and clock interfaces

Fully differential CML-type output phase error interface with 300mV single-ended swingSingle +3.3V or -3.3V power supplyPower consumption: 895mWFabricated in SiGe for high performance, yield, and reliability

Custom CQFP 24-pin packageveeSelectable input clock multiplier by 2 with externally adjustable duty cycle

vcc



pern

Adjustable data input equalizer with a by-pass possibility

vcc



perp

Broadband linear phase detector with differential output

vcc

ed

vcc

vcc

dp

cp

ASNT8121
ASNT5111

vcc

vcc

dncn

vcc

vcc

Rev. 1.0.2

1

vcc

dcyc

vcc

eqadj

vcc

vee

phadj

July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.comDESCRIPTION

dpdnEQ

eqadj

cpcnphadj

SEL
PhaseDet.

perpperned

Duty
Cycle
Cntrl.

dcyc

CMP

Cx2

SEL

CMPFig. 1. Functional Block Diagram

The ASNT8121-KMC SiGe IC shown in Fig. 1 provides a differential phase error signal perp/pern thatindicates the phase difference between the data dp/dn bit transitions and the edges of the input clock
cp/cn. The input data spectrum can be corrected by the equalizer EQ with a frequency response
adjustable by the variation of the control input signal eqadj within the voltage range from vcc to vcc-2V.
The lower values of eqadj disable the equalizer and send the input data signal directly to the phasedetector block PhaseDet. The input clock can be delivered to the phase detector block either directly or
through the multiplier by 2 Cx2 with its output duty cycle adjustable by means of the phadj control
voltage. The phadj control operates similar to eqadj with a tunable range from vcc to vcc-2V and amultiplication enabling threshold value of vcc-2V.
The phase detector also provides two single-ended signals ed and dcyc. The ed output delivers an analog
voltage indicating the number of transitions in the data bit stream. The duty cycle control block
DutyCycleCntrl generates the analog signal dcyc that indicates the clock duty cycle deviation from 50%.
The part’s differential input clock and data ports support the CML logic interface with on chip 50Ohm
termination to vcc and may be used differentially, AC/DC coupled, single-ended, or in any combination(see also POWER SUPPLY CONFIGURATION). In the DC-coupling mode, the input signal’s commonmode voltage should comply with the specifications shown in ELECTRICAL CHARACTERISTICS. In
the AC-coupling mode, the input termination provides the required common mode voltage automatically.
The output phase error port supports a CML-type interface with on chip 100Ohm termination to vcc andmay be used differentially, AC/DC coupled, single-ended, or in any combination (see also POWER
SUPPLY CONFIGURATION). The differential DC signaling mode is recommended for optimalperformance.
Rev. 1.0.2

2July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Equalizer
The simulated equalizer frequency response at different values of the eqadj signal is shown in Fig. 2 andits simulated control characteristic is shown in Fig. 3.

Fig. 2. Equalizer Frequency Response at Full, Half, and No Gain

Equalizer Gain at 15GHz vs. Tunning Voltage
25Gain (dB)

20

15

10

50-2

-1.8

-1.6

-1.4

-1.2

-1-0.8

-0.6

-0.4

-0.2

0Tunning Voltage (V)Fig. 3. Equalizer Control Characteristic

Rev. 1.0.2

3July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Clock Multiplier
The multiplier delivers the input clock applied to the pins cp/cn to the phase detector core. If the phadj
control voltage is below the threshold value, then the block operates as a signal repeater and the frequencyof the clock is not changed. If the phadj control voltage is in the range from the threshold to vcc, then theclock frequency is doubled and its duty cycle can be adjusted by the phadj control voltage.

Phase Detector
The simulated transfer characteristics of the phase detector at 30Gb/s data rates is shown in Fig. 4.
APD Output vs. Phase Shift at 30GHz
800

600

Diff PhErr Signal (V)400

2000-0.5

-0.4

-0.3

-0.2

-0.1

00.1

0.2

0.3

0.4

-200

-400-600

Phase Shift, UIFig. 4. Simulated Phase Detector Characteristic at 30Gb/s Data Rate

POWER SUPPLY CONFIGURATIONThe part can operate with either a negative supply (vcc = 0.0V = ground and vee = −3.3V), or a positivesupply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os need AC termination
when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be neededfor each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.

Rev. 1.0.2

4July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vcc).
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case TemperatureStorage Temperature
Operational Humidity
Storage Humidity

Min-401010Max-3.6
0.98
1.0+90+1009898

UnitsVWVºCºC%%TERMINAL FUNCTIONSTERMINAL
Name
No.
Type

DESCRIPTION

Name
vcc

High-Speed I/Os
21
CML Differential high-speed data input signals with internal SE
input 50Ohm termination to vcc
23
11
CML Differential high-speed clock input signals with internal SE
input 50Ohm termination to vcc
917
Analog Differential phase error output with internal SE 100Ohmoutput terminations to vcc.
153Analog Equalization level adjust / equalizer enableinput
7
Analog Duty cycle adjust / clock multiplier enableinput
5
Analog Duty cycle indicator signal
output19
Analog Edge density indicator signal
outputSupply and Termination Voltages
Description
Pin Number
Positive power supply (+3.3V or 0)2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24vee

Negative power supply (0V or -3.3V)

dp
dncp
cnperpperneqadj
phadj
dcyc
ed

Rev. 1.0.2

51, 13July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERveevcc
Ivee
Power consumption
Junction temperature
Data Rate
Swing
CM Voltage Level
Frequency
Swing
CM Voltage Level
Linear range
CM Voltage Level
Linear control range
Switching threshold
Voltage range

MIN

TYP

MAX UNITCOMMENTS
General Parameters
-3.1
-3.3
-3.5
V
±6%
0.0
V
External ground
270mA
895mW
-40
25125°C
HS Input Data (dp/dn)
DC34Gbps
10300mV
Differential or SE, p-p
vcc-0.3vcc
VMust match for both inputs
HS Input Clock (cp/cn)
DC17GHz
10300
mV
Differential or SE, p-p
vcc-0.3vcc
VMust match for both inputs
Phase Error Output (perp/pern)
300mV
Single-ended
vcc-0.275
V
Tuning ports (eqadj, phadj)-20V-2
VOutput indicators (ed, dcyc)
-3.3
0.0
V

PACKAGE INFORMATIONThe chip die is housed in a custom 24-pin CQFP package shown in Fig. 5. The package provides a center
heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for thissection to be soldered to the vcc plain, which is ground for a negative supply, or power for a positivesupply.
The part’s identification label is ASNT8121-KMC. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin out
count.
The IC complies with the Restriction of Hazardous Substances (RoHS) per EU 2002/95/EC for all 6substances.

Rev. 1.0.2

6July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Fig. 5. CQFP 24-Pin Package Drawing (All Dimensions in mm)

Rev. 1.0.2

7July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.0.2
1.0.1
1.0.0

Rev. 1.0.2

Date07-2019
08-2015
09-2014

Changes
Updated LetterheadFirst release
Preliminary release

8July 2019