Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT8172-KMF
2V Driver with Asynchronous Finite Impulse Response FilterOne differential digital CML input port

One differential analog output port

6-bit tap gain and tap peaking controls

3-bit additional gain control for initial FIR calibration using a tap replica

4-bit output buffer gain and 6-bit output buffer peaking controls

3-wire SPI for loading all control values

Three positive power supplies

Maximum power consumption: 1.24W

Custom CQFP 64-pin package

Rev. 1.1.2

vcc
vee
qrp
vee
qrn
vee
3wenin
3wcin
3wdin
3wdo
vee
vdd
vee
nc
vee
vcc

1

vee
vcc
vee
vdd

ASNT8172

nc
vee
vcc
vee
dp
vee
v1p8
Dmin
Dmax
Dcm
vee
dn

vcc
vee
vccl
vee
vccl
vee
vee
vcscd
vee
rfbo
vee
vee
vee
nc
vee
vcc

vee
vccl
vee
vcc

DC to 10GHz 9-tap finite impulse response filter (FIR)

vcc
vee
vcch
vee
qpveevcchvcchvcch
Dcmtstveeqn

July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION

Fig. 1. Functional Block Diagram

The IC shown in Fig. 1 is a differential driver with an externally controlled 9-tap pre-emphasis. It receives ahigh-speed binary data signal through its differential input port dp/dn. The FIR block processes the input signal
in accordance with nine pre-defined filter coefficients to perform the pre-emphasis operation. The resulting
analog signal is amplified by a linear amplifier-driver LAD, and delivered to the output linear differential port
outp/outn that operates in ECL-type mode and requires external 50Ohm AC terminations. If DC terminations
are desired, a special external resistor network should be designed.
All chip functions are controlled through a 3-wire serial-to-parallel interface (SPI) that operates in combination
with an internal control block CrlB.
The chip includes a 1-tap replica Rpl that can be independently enabled and used for initial gain calibration asdescribed below.

FIR
The FIR block includes 8 dual transmission lines for direct and inverted input data signals with a single-ended
impedance of 50Ohm and matching internal terminations to vcc at their ends. Signals from all 9 nodes areprocessed by tap buffers to deliver 9 delayed copies of the differential input signal with controlled signs andweights to a summation point. The signs and weights are defined by internal binary signals sign and analog
signals ATwt respectively. In addition, frequency response (peaking) of each tap can be adjusted using internal
Rev. 1.1.2

2July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
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analog signals ATpk. The weight of any tap #X can be reduced to exact 0 by a 1-bit digital signal ontapX=”0”,or can be controlled normally with ontapX=”1” as described below in CrlB.
FIR requires initial calibration after which it delivers an optimal signal to its output. The calibration isperformed using a replica block (Rpl) that is described below.

LAD
LAD amplifies the analog signal from FIR, and delivers it to the differential output port outp/outn. This port
operates in ECL-type mode as a current source/sink and requires external 50Ohm AC terminations. A DC
termination scheme is also possible but requires an external resistor network.
The gain and frequency response (peaking) of LAD can be adjusted using internal 4-bit binary signal gain, andsix analog signals ADpk respectively. The LAD’s internal buffer with the gain adjust functionality includes acascode stage for better performance. The reference voltage for the cascode stage can be monitored andadjusted through a control port vcscd to achieve the best output signal.

CrlB
This control block converts binary signals from SPI into binary, and analog control signals delivered to FIR,LAD, and Rpl.
There are 45 input binary signals to CrlB from SPI, 10 output binary signals, and 23 output analog signals fromCrlB. Their logic relations are detailed in Table 1.
Table 1. Control Signals

OutputToBits Signals Input 1 Bits Operation Input 2 Bits Operation Input 3 BitssignX
FIR
1
9ondirX
1ATwtX
FIR
9wcX
6
ontapX
1ffegn3
ANDANDATpkX
FIR
9pkX
6
ontapX
1ffegn3
ANDANDgain
LAD
4
1onmni
4onpb
1
AND
ADpkX LAD
5efi
6Internal DAC threshold adjustment cmcrl
6
The value of ondirX=”1” corresponds to a positive gain of tap #X. The minimum value of wcX=0 corresponds
to a tap #X gain close to 0. The exact 0 gain value for the tap #X is achieved in case of ontapX=”0”. Themaximum value of wcX=63 corresponds to the nominal gain of tap #X specified in ELECTRICAL
CHARACTERISTICS. The initial calibration of this nominal gain should be performed as described in Rpl.
The maximum value of pkX=63 corresponds to maximum bandwidth (and peaking) in the tap #X.
The minimum value of onmni=0 corresponds to a LAD gain close to 0. The exact 0 gain value for LAD isachieved in case of onpb=”0”. The maximum value of onmni=7 corresponds to the highest gain of LAD. The
optimal value of LAD gain depends on the fabrication process variations, and should be defined by the nominal
output swing specified in ELECTRICAL CHARACTERISTICS. The maximum value of efi=63 corresponds tomaximum bandwidth (and peaking) in LAD.
LAD also provides signals to 4 external analog ports for monitoring of its internal DAC operation as shown in
Table 2.
Rev. 1.1.2

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Advanced Science And Novel Technology Company, Inc.
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Offices: 310-530-9400 / Fax: 310-530-9402
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Table 2. DAC Monitoring Signals

Output signal
Dmax
Dmin
DcmDcmtst

Function
Maximum DAC output signal
Minimum DAC output signal
DAC threshold
DAC threshold before downshift

Input signal
Constant 111111 DAC input
Constant 000000 DAC inputcmcrlcmcrl

The values of Dmax and Dmin must be within the ranges specified in ELECTRICAL CHARACTERISTICS.
The value of Dcm should be equal to (Dmux+Dmin)/2. Dcm is a downshifted copy of Dcmtst, and both values
can be adjusted by a 6-bit signal cmcrl delivered through SPI. This adjustment of internal DAC thresholds isrequired for the correct generation of internal differential control signals.

Rpl
The tap replica Rpl can be used for initial tap gain calibration to ensure the optimal maximum data signal swing
at the FIR output over process variations.
Rpl is an exact copy of one tap operating at its maximum weight. In the optimal state, it should generate apredefined DC voltage difference between its outputs qrp and qrn. This difference may be adjusted using the 3bit binary signal ffegn. The same signal is used to adjust the ATwtX and ATpkX analog signals applied toactual taps as shown in Table 1. Rpl is used for initial calibration only, and can be completely disabled by thebinary signal offrep=”1”.

SPI
3-wire SPI operates in slave mode and accepts three CMOS signals: 3wenin (SSn), 3wcin (SCLK), and 3wdin(MOSI) as described in ELECTRICAL CHARACTERISTICS. Additional CMOS data output 3wdo (MISO) isprovided for control purposes.
SPI converts 25 input serial bytes into 45 parallel binary control signals delivered to CrlB, and one binary signalto Rpl. The input package description is presented in Table 3.
Table 3. Control Bytes

Byte
No.
12345678910111213

Signal 1
Name Bit #ontap1
7pk1
7-2
ontap27
pk2
7-2
ontap37
pk3
7-2
ontap47
pk4
7-2
ontap57
pk5
7-2
ontap67
pk6
7-2
ontap7
7Rev. 1.1.2

Signal 2
Name Bit#
ondir16empty1
ondir26empty1
ondir36empty1
ondir46empty1
ondir56empty
1ondir66empty
1ondir7
6

Signal 3
Byte
Signal 1
Name Bit# No. Name Bit #
wc1
5-0
pk7
7-2
14empty
0715 ontap8
wc2
5-0
pk8
7-2
16empty0
7
17 ontap9
wc3
5-0
pk9
7-2
18
empty
0
efi0
7-2
19
wc4
5-0
efi1
7-2
20
empty
0
efi2
7-2
21
wc5
5-0
efi3
7-2
22
empty
0
efi4
7-2
23
wc6
5-0
cmcrl 7-2
24
empty
0
ffegn
7-5
25
wc7
5-0
4

Signal 2
Name Bit#empty
1ondir86empty1
ondir96empty
1empty1empty1empty1empty1empty1offrep1
onpb
4

Signal 3
Name Bit#empty0
wc85-0empty
0wc95-0
empty
0
empty
0
empty
0empty0empty0empty0empty0
onmni 3-0July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
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The bytes are delivered starting from 1 to 25 and bits within a byte are delivered starting from MSB. Bit#7 is
the MSB of a byte as shown in Fig. 2. Internal registers are updated at a rising edge of 3wenin.
3wcin
3weninSampleLatch3wdin

X 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0 X

Byte 1

Byte NFig. 2. SPI Operation

The FIR block is designed in such a way that it requires normalization of tap gains. Assuming that wcMAXequals 63 (or 111111 in binary code), the tap weight control binary signals wcX supplied to the SPI should be
9softly normalized to satisfy the equation  wc(i )  wcMAX .
i 1

POWER SUPPLY CONFIGURATIONThe IC requires four positive external power supplies. The first supply vcc is used for the data input
terminations, and to power all high-speed digital circuitry and reference sources. The second supply vccl
powers the internal analog circuitry. The third supply vcch is used for the output analog driver. The digital
supply vdd is used for the internal CMOS circuits of the SPI.
All supplies are positive in relation to the internal common node vee=0.0V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings may cause damage to this product and/or lead to reduced
reliability. Functional performance is specified over the recommended operating conditions for power supply
and temperature only. AC and DC device characteristics at or beyond the absolute maximum ratings are notassumed or implied. All min and max voltage limits are referenced to ground.
Table 4. Absolute Maximum Ratings

Parameter
Supply Voltages (vcc, vccl, vcch, vdd)
Power Consumption
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity
Rev. 1.1.2

Min-4010105

Max3.0, 4.0, 8.0, 1.5
1.5+90+1009898UnitsVWºCºC%%
July 2019Advanced Science And Novel Technology Company, Inc.
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TERMINAL FUNCTIONSTERMINAL
Name No.
Type

Description

High-Speed I/Os
dp
5
CML-type input Differential high-speed data inputs with internal SE 50Ohmterminations to vcc
dn12
qp
44 ECL-type output Differential high-speed data outputs; require external SE
50Ohm AC terminations
qn37
Low-Speed I/Os3wenin 26 1.2V CMOS input Enable input signal SSn for 3-wire interface
3wcin 25
Clock input signal SCLK for 3-wire interface
3wdin 24
Data input signal MOSI for 3-wire interface
3wdo 23 1.2V CMOS output Data output signal MISO for 3-wire interface
Analog Control Voltages
v1p8
7Internal voltage Internal voltage source of vee+1.8V
vcscd 56 generator output Internal voltage source of vcch-4.0V
rfbo
58
Internal voltage reference nodeAnalog Control Nodes (for DMM measurements only!)
Dmin 8 Analog DC output DAC minimum output indicator
Dmax 9DAC maximum output indicator
Dcm 10DAC common-mode output indicatorDcmtst 39
DAC control output with internal 12.4Ohm termination to vcc
qrp30
Replica differential data outputs with internal SE 42Ohm
terminations to vccl
qrn28

Nameveevcc
vccl
vcch
vddnc

Rev. 1.1.2

Supply And Termination Voltages
Description
Pin Number
External ground2, 4, 6, 11, 13, 15, 18, 20, 22, 27, 29, 31,34, 36, 38, 43, 45, 47, 50, 52, 54, 55, 57,59, 60, 61, 63
Positive power supply (HS digital part)3, 14, 17, 32, 33, 48, 49, 64
Positive power supply (analog part)35, 51, 53
Positive power supply (output driver)40-42, 46
Positive power supply (digital control part)16, 21
not connected pins
1, 19, 62

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Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
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ELECTRICAL CHARACTERISTICSPARAMETER
vcc
vccl
vcch
vddvee
Ivcc
Ivccl
Ivcch
Power consumption
Junction temperature
No. of Taps
Delay between Taps
Voltage gain

Data Rate
Swing
S11
CM Voltage Level
BandwidthSwing
S22
CM Voltage Levelv1p8
vcscd
qrp-qrn
Dmax
Dmin
Dcm
DcmtstClock frequency
Low logic level
High logic level

Rev. 1.1.2

MIN

TYP MAX UNIT
COMMENTS
General Parameters
2.6
V
High-speed digital supply
3.5
VAnalog supply
7.5
V
Analog supply
1.2
V
CMOS digital supply
0.0V
External ground
43mA
40mA
132mA
1.24
W
-25
50
125°C
FIR Parameters
911ps
3.5
dB
From chip input to FIR output, can beverified by Rpl measurements
High Speed Input Data (dp/dn)
DC20Gb/s
220
mV
Differential or SE, p-pTBDdBV
Must match for both inputs
vcc
Analog Output Data (qp/qn)
DC10GHz1200mVon each SE output
TBDdB
2.4
V
DC Control Voltages
vee+1.85
vee+1.75
Vvcch-4.1
vcch-3.9V
330mVwith optimal ffegn
vcc-0.9
vcc-0.7
V
Should be always
Dmax-Dmin=0.4±0.05
vcc-1.3
vcc-1.1
V
vcc-1.1
vcc-0.9
V
Should be Dcm=(Dmux+Dmin)/2vcc-0.25
vcc-0.15
V3-Wire Interface Ports
6MHz0V
1.2
V

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Offices: 310-530-9400 / Fax: 310-530-9402
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PACKAGE INFORMATIONThe chip die is housed in a custom 64-pin CQFP package. The dimensioned drawings are shown in Fig. 3. The
package provides a center heat slug located on its back side to be used for heat dissipation. ADSANTEC
recommends for this section to be soldered to the vee plain, which is ground for a positive supply.
The part’s identification label is ASNT8172-KMF. The first 8 characters of the name before the dash identify
the bare die including general circuit family, fabrication technology, specific circuit type, and part version whilethe 3 digits after the underscore represent the package’s manufacturer, type, and pin out count.
This device complies with the Restriction of Hazardous Substances (RoHS) per EU 2002/95/EC for all six
substances.

Fig. 3. CQFP 64-Pin Package Drawing (All Dimensions in mm)

Rev. 1.1.2

8July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.comREVISION HISTORY
Revision
1.1.2
1.1.1

Date07-2019
08-2017

1.0.1

05-2017

Rev. 1.1.2

Changes
Updated Letterhead
Corrected terminal functions section
Corrected electrical characteristics section
Corrected package information section
Initial Release

9July 2019