Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT5024-PQC
DC-28Gbps/17GHz Signal Distributor 1-to-3
High-speed broadband Data/Clock Amplifier and Distributor



Exhibits low jitter and limited temperature variation over industrial temperature range

One input differential signal port and three differential amplified output signal portsMatched phase delays for all outputs



Fully differential CML input interface

Fully differential CML output interfaces with 600mV single-ended swing

Single +3.3V or -3.3V power supplyPower consumption: 780mWFabricated in SiGe for high performance, yield, and reliabilityStandard MLF/QFN 24-pin package

Rev. 3.4.2

1July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
out0p

out0n

50505050

cp

out1p

cn

out1n
50505050

out2p

out2nFig. 1. Functional Block Diagram

The temperature stable ASNT5024-PQC SiGe IC provides active broadband data/clock signal splitting,and is intended for use in high-speed measurement / test equipment. The IC shown in Fig. 1 can deliver
three phase-matched copies of the broadband data/clock input signal cp/cn to three high-speed
differential outputs out0p/out0n, out1p/out1n, out2p/out2n.
The part’s I/O’s support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.

POWER SUPPLY CONFIGURATION
The part can operate with either negative supply (vcc = 0.0V = ground and vee = −3.3V), or positive
supply (vcc = +3.3V and vee = 0.0V = ground). In case of the positive supply, all I/Os need ACtermination when connected to any devices with 50Ohm termination to ground. Different PCB layouts
will be needed for each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.
Rev. 3.4.2

2July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground.
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max-3.60.86
1.0+90+1009898UnitsVWVºCºC%%TERMINAL FUNCTIONSTERMINAL
NameNo.
Type
cpcn
out0p
out0n
out1p
out1n
out2p
out2n
Namevccvee

Rev. 3.4.2

DESCRIPTION

High-Speed I/Os
Differential high speed data/clock inputs with internal SE 50Ohm
termination to vcc
Differential high speed data/clock outputs with internal SE 50Ohm
termination to vcc. Require external SE 50Ohm termination to vcc
Differential high speed data/clock outputs with internal SE 50Ohm
termination to vcc. Require external SE 50Ohm termination to vcc
Differential high speed data/clock outputs with internal SE 50Ohmtermination to vcc. Require external SE 50Ohm termination to vcc
Supply and Termination Voltages
Description
Pin Number
Positive power supply (+3.3V or 0)
1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23
Negative power supply (0V or -3.3V)
6, 12, 18, 24
20
22
16
14
10
8
4
2

CML
input
CML
outputCML
outputCML
output3July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETER

MIN

TYP

MAX UNITCOMMENTS
General Parameters-3.1-3.3-3.5
V±6%
vee
0.0
V
External ground
vcc
Ivee
235mA
Power consumption
780mW
Junction temperature -40
25125°C
HS Input Data/Clock (cp/cn)
Data Rate
DC28Gbps
Frequency
DC17GHz
Swing
0.05
1.0
V
Differential or SE, p-p
CM Voltage Level
vcc-0.8
vcc
VMust match for both inputs
HS Output Data/Clock (out0p/out0n, out1p/out1n, out2p/out2n)
Data Rate
DC28Gbps
Frequency
DC17GHz
Latency64ps
From any input to any output
Phase mismatch2
ps
Between any two SE outputs
Logic “1” level
Vvcc
Logic “0” levelvcc-0.6
VWith external 50Ohm DC termination
Rise/Fall times
1519
ps
20%-80%Additive Jitter
5ps
Peak-to-peakDuty cycle
45
50
55%
For clock signal

PACKAGE INFORMATIONThe chip die is housed in a standard 24-pin QFN package shown in Fig. 2. It is recommended that thecenter heat slug located on the back side of the package is soldered to the vee plain that is ground for thepositive supply or power for the negative supply.
The part’s identification label is ASNT5024-PQC. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per EU 2002/95/EC for all six
substances.

Rev. 3.4.2

4July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT5024
Fig. 2. QFN 24-Pin Package Drawing (All Dimensions in mm)

Rev. 3.4.2

5July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
3.4.2
3.4.1
3.3.1

Date
07-2019
08-2018
03-20133.2.102-2013

3.1.1
3.1
3.001-2013
05-201201-20122.002-2009

1.001-2009

Rev. 3.4.2

Changes
Updated Letterhead
Added latency specifications
Added phase mismatch specifications
Updated description
Revised title
Revised package pin out drawing
Revised description
Revised power supply configuration
Revised absolute maximum ratings
Revised terminal functions
Revised electrical characteristics
Revised package information
Format correction
Format correction
Corrected description and format
Added Power Supply Configuration text
Added Absolute Maximums Rating table
Revised Electrical Characteristics section
Revised Package Information section
Revised Electrical Characteristics section
Revised Package Information section
Initial release

6July 2019