Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT7113A-KMM
4GSps / 20GHz Differential Track-and-Hold Amplifier

vcc

vcc
vee

vcc
1ngaincrl

rfp_sv2

vcc

varcrlvcc

rfp_obMore than 8-bit accuracy within the full frequency range
Sampling speed up to 4GSps
Nominal 0dB differential gain with manual adjustment
Adjustable duty cycle and delay of the internal sampling clocks
Adjustable output common mode voltage level
Adjustable input bandwidth
Fully differential input and output data and clock buffers with on-chip 50Ohm termination
Dual power supply
Total power consumption of 1.75W
Fabricated in SiGe for high performance, yield, and reliability
Custom CQFP 44-pin package
vcc










vcc
vee
vcc

vcc

vp0p9

vccob

vcc

vcc

dp

qp

ASNT7113A

vcc

vcc

dn

qn

vcc

vcc

vp0p9

ivc

vcc

vcc
vee

Rev. 1.1.2

1vcc

cn

vcc

cp

vcc

t1crl

vcc

t2crl

vcc

vee

vcc

vcc

February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
vp0p9 varcrl

dpdncpcnInput
Data
Equalizer

Sampling
StrobeGenerator

data
Sampling

OutputBlockBuffer

qp
qn

s1
s2

t1crl t2crl ivc

gaincrl

Fig. 1. Functional Block Diagram

The ASNT7113A-KMM SiGe IC is a high-speed, temperature stable, and broadband track-and-hold
amplifier (THA) with improved reliability. The IC shown in Fig. 1 performs sampling of the input
differential analog signal using two internally-generated strobe signals s1 and s2, and delivers a step-like
differential signal to the output. It features an adjustable track period length controlled by two external
voltages t1crl and t2crl that modify the states of internal delay lines. The additional ivc control voltage
can be used to control the range of the delay adjustment (recommended setting is default). This allows for
maximizing the length of the valid output step.
The differential gain of the chip is approximately 0dB, which corresponds to the single-ended-todifferential gain of -6dB. The gain can be adjusted using the external control voltage gaincrl. The chip
supports both AC-coupled and DC-coupled inputs. In the DC-coupled mode, the input common-mode
voltage must be equal to vcc for optimal performance of the chip. The input sampled data path includes
an equalizer that increases the bandwidth of the chip. The level of equalization is controlled by theexternal voltage varcrl.
The frequency response and gain of the part is also controlled by the positive supply voltage vp0p9 thatpowers the input buffers of the Track-and-Hold. This voltage defines the common mode of the data signal
at the input of the sampling switch and thus the frequency response of the device. Lower voltage results inless peaking in the input buffer and less overall gain of the device.
The output buffer features an independent supply voltage vccob which allows for the adjustment of theoutput signal’s common mode voltage. The part’s outputs support the CML-type logic interface with an
on-chip 50Ohm termination to vccob and may be used differentially, AC/DC coupled, single-ended, or inany combination (see also POWER SUPPLY CONFIGURATION). The differential DC signaling is
recommended for the optimal performance.

Rev. 1.1.2

2February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Input Data Equalizer
The bandwidth of the data input can be adjusted by the internal equalizer controlled with the external
voltage varcrl. The equalizer is designed to compensate for the gain drop at high frequencies due to thecharacteristics of the front-end circuitry and the sampling block itself. The measured frequency responseof the IC at maximum (magenta line) and minimum (orange line) values of the varcrl voltage is shown inFig. 2. The measurements have been performed at the intermediate state of the gain control (see Fig. 4).
10Gain, dB-1-2-3-4-5
0.1

1VarMAX

10100F, GHzVarMIN

Fig. 2. Frequency Response of SHA with Max and Min Equalization

Input Clock Buffer
The input clock buffer converts the external clock cp/cn into two internal signals s1 and s2 with
controlled pulse width (PW) and delay () between them as shown in Fig. 3.
TrackHolds2s1PW

Valid output

Fig. 3. Sampling Diagram

This allows for optimization of the hold time and the length of the valid output signal period. The value ofPW is reverse-proportional to the t2crl voltage, while the value of  is proportional to the t1crl voltage.
The range of the delay controls is defined by the external voltage ivc. For the normal operational
conditions, it is recommended to leave the pin ivc not connected.
WARNING: Too high values of the ivc voltage may upset the device operation.

Rev. 1.1.2

3February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Sampling Block and Output Buffer
The sampling block performs conversion of the input signal into a step-like sampled signal under controlof s1 and s2 pulses. The sampled signal is amplified by the output buffer to achieve a total gain ofapproximately 0dB. The output common-mode voltage level can be directly adjusted through changing ofthe vccob supply voltage. The gain can be adjusted using the gaincrl voltage signal. The measured
frequency response of the SHA with the maximum and minimum gain at 2.5GSps rate is shown in Fig. 4.
10Gain, dB-1-2-3-4-5-60.1

110100F, GHzFig. 4. THA Gain at Max and Min gaincrl Values vs. Data Frequency

The harmonic distortion of the THA has been demonstrated by 3rd harmonic as shown in Fig. 5 fordifferential clock and data input signals at the sampling rate of 4GSps. The data amplitude is 125mV
differential or 125mV pk-pk at both direct and inverted pins.

-5 0-5 1-5 2-5 3dBc-5 4-5 5-5 6-5 7-5 8-5 9-6 002468101214161820Fdata, GHzFig. 5. 3-rd Harmonic at 4GHz Input Clock (C) and 125mV Differential Data (D) Amplitude

Rev. 1.1.24February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
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The linearity of the signal conversion is illustrated by Fig. 6 that demonstrates the part’s gain at 2.5GSps.
-0.86
-0.88
-0.9

Gain, dB-0.92
-0.94
-0.96
-0.98
-1
-1.02
-1.04
-1.06
050

100

150200250300

InputAmplitude SE, mV p-p

Fig. 6. THA Gain vs. Input Data Amplitude at Medium State of gaincrl

POWER SUPPLY CONFIGURATION
The part operates with either a negative supply scheme (vcc = 0.0V = ground) or a positive supply scheme(vee = 0V = ground). In case of the positive supply, all I/Os need AC termination when connected to any
devices with 50Ohm termination to ground. Different PCB layouts will be needed for each different
power supply combination.

All the characteristics detailed below assume the negative supply scheme.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vcc).
Table 1. Absolute Maximum Ratings

Parameter
MinMaxUnits
First Supply Voltage (vee)-3.5 (negative scheme) 0 (positive scheme)
V
Second Supply Voltage (vcc)
0 (negative scheme) 3.5 (positive scheme)
V
Third Supply Voltage (vp0p9)
vcc+1.1
V
Power Consumption
2W
RF Input Voltage Swing (Diff)
2.0
V pk-pk
Clock Input Voltage Swing (Diff)
1.0V pk-pk
Case Temperature+90ºC
Storage Temperature-40+100ºC
Operational and storage Humidity
1098%

Rev. 1.1.2

5February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
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TERMINAL FUNCTIONSNameTERMINAL
No.
Type

DESCRIPTION

High-Speed I/Os
cp
8
CML input
Sampling clock inputs with internal SE 50Ohm termination tovcc
cn10
dp
39
AnalogAnalog sampled data inputs with internal SE 50Ohm
input
termination to vcc
dn41
qn17
CML output Differential data outputs with internal SE 50Ohm terminationto vcc. Require external SE 50Ohm termination to vcc
qp19Controls
t1crl
6
Analog voltage Sampling clock duty cycle control
t2crl
4Analog voltage Sampling clock delay control
gaincrl
26 Analog voltage Gain adjustment
varcrl30 Analog voltage Equalizer peaking control
ivc
15 Analog voltage Delay range control
rfp_sv2
28 Analog voltage Special test pins. Leave not connected!
rfp_ob32 Analog voltage
Supply and Termination Voltages
Name
Description
Pin Numberstvcc
1 positive supply voltage
1, 3, 5, 7, 9, 11, 12, 14, 16, 18, 20, 22, 23,25, 27, 29, 31, 33, 34, 36, 38, 40, 42, 44
vee
Negative power supply
2, 13, 24, 35
nd
vp0p9 2 positive power supply
37, 43
vccob Output buffer power supply
21

Please note that pins 28 and 32 should be always left not-connected! Termination of
those pins may result in mal-function or damage of the part.

ELECTRICAL CHARACTERISTICSPARAMETER

MIN-3.3 / 0vee
0 / 3.1
vcc
0.75
vp0p9
-0.3
vccob
Ivcc
Ivp0p9Power consumption
Junction temperature-25

Rev. 1.1.2

TYP MAXUNITGeneral Parameters-3.2 / 0-3.1 / 0
V0 / 3.20 / 3.3
V
0.85
0.95
00.3
V
430mA
100mA
1750mW
50125°C

6COMMENTS
Negative scheme / Positive scheme
Negative scheme / Positive scheme
Above vcc, any scheme
Independent from vcc
Ivee = Ivcc + Ivp0p9February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
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PARAMETER
Input data frequency
Swing, differential,p-p
CM Voltage Level
S11Frequency
Swing
CM Voltage Level
JitterDuty cycle
Voltage range
Adjustment range
Voltage range
Adjustment range
Voltage range
Voltage range
Voltage range
Additional peaking
CM Level
Voltage Range
Voltage Range
3rd HD
Noise
Track period length
Total DC gain
S22

Rev. 1.1.2

MIN

TYP

MAX
UNIT
COMMENTS
Input Data (dp, dn)
0.020
GHz
0300mV
3rd HD<-52dBc in full data bandwidth
0400mV
3rd HD <-48dBc in full data bandwidth
0500mV
3rd HD <-45dBc in full data bandwidth
VFor DC couplingvcc-10dB
DC to 20GHz
Input Clock (cp, cn)
0.05
4.0
GHz80240mV
SE or differential, p-pVvcc
50
fsp-p
4850
52%
Duty Cycle Control Voltage (t1crl)
vcc – 1.4vcc
V50
ps
For the delay of s1 vs. s2
Delay Control Voltage (t2crl)
vcc – 1.4vcc
V20
ps
For the pulse width of s1 and s2
Delay Range Control Voltage (ivc)
vcc – 2.1
vcc – 1.6
VGain Control Voltage (gaincrl)
vcc – 1.8vcc
VEqualizer Control Voltage (varcrl)
vcc – 1.8vcc
V1.5dBAt 20GHz and nominal conditionsOutput Signal Common Mode Control (vccob)
vccob-0.4
VInput Data Common Mode Control (vp0p9)
vcc + 0.7
vcc + 0.9
VHS Output Data (qp, qn)
vcc – 0.5
vcc + 0.8
VSee Fig. 5.
1/2
15nV/HzAt 2.5GSps within full data bandwidth250
ps
At 2.5GSps. Adjustable by t1crl signal.
-2.1
0.1
dB
Adjustable by gaincrl signal.
-20dB
DC to 4GHz

7February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402www.adsantec.com

PACKAGE INFORMATIONThe chip die is housed in a custom 44-pin CQFP package shown in Fig. 7. Even though the package
provides a center heat slug located on the back side of the package to be used for heat dissipation,
ADSANTEC does NOT recommend for this section to be soldered to the board. If the customer wishes
to solder it, it should be connected to vcc plain that is ground for the negative supply or power for thepositive supply.

Fig. 7. CQFP 44-Pin Package Drawing (All Dimensions in mm)

Rev. 1.1.28February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

The part’s identification label is ASNT7113A-KMM. The first 9 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin out
count.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all tensubstances.

REVISION HISTORY
Revision
1.1.2
1.0.2

Date02-2020
11-20190.0.104-2013

Rev. 1.1.2

Changes
Updated Package Information
Updated Letterhead
Corrected absolute Maximum supply values
Corrected vcc supply values
Preliminary release.

9February 2020