Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT8133-KMC
DC-50GHz High-Speed Clock Divider by 1, 2, or 4



Fully differential CML input interface

Fully differential CML output interface with 400mV single-ended swing



CMOS 3.3V control signals

Single +3.3V or -3.3V power supplyPower consumption: 845mW at full operational speed

Fabricated in SiGe for high performance, yield, and reliability

Custom CQFP 24-pin packagevee50% duty cycle of the divided clock signals

vcc

vcc

Selectable Forwarded, Divided-by-2, or Divided-by-4 output

vcc

vcc

Wide input clock frequency range from DC to 50GHz

vcc

vee

vcc

vcc

divcop

ASNT8133

vcc

vcc

div4

convccvcc

Rev. 1.1.2

1vcc

cnvcc

cpvcc

vee

vee

July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION

50cpcndiv div450
copconDIV 1:2:45050Fig. 1. Functional Block Diagram

ASNT8133-KMC is a high-speed, low-power divider by-1, by-2, or by-4 with increased sensitivity. The
part shown in Fig. 1 accepts a CML input clock signal cp/cn with the speed from DC to maximum
operational frequency and provides a clean 50% duty cycle output signal cop/con with its frequency
defined by the states of CMOS level div and div4 control signals as shown in Table 1.
Table 1. Clock frequency division control signals

div div4Output Frequency“0”xForwarded, no division“1” “0” Divided by 2
“1” “1” Divided by 4
The part’s high-speed I/Os support the CML logic interface with on chip 50Ohm termination to vcc andmay be used differentially, AC/DC coupled, single-ended, or in any combination (see also POWER
SUPPLY CONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage
should comply with the specifications shown in ELECTRICAL CHARACTERISTICS. In the ACcoupling mode, the input termination provides the required common mode voltage automatically. Thedifferential DC signaling mode is recommended for optimal performance.

POWER SUPPLY CONFIGURATION
The part can operate with either a negative supply (vcc = 0.0V =ground and vee = -3.3V), or a positivesupply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os need AC termination
when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be neededfor each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.
Rev. 1.1.22July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 2 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vcc).
Table 2. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max-3.6
0.92
1.0+90+10098
98UnitsVW
V°C°C%%TERMINAL FUNCTIONSTERMINAL
Name No.
Typecpcncop
con

3
5119

CML
input
CML
output

div
div4

2123

CMOS
Input

Namevccvee

Rev. 1.1.2

DESCRIPTION
High-Speed I/Os
Differential clock input with internal SE 50Ohm termination
to vccDifferential clock outputs with internal SE 50Ohm termination
to vcc. Require external SE 50Ohm termination to vcc
Static I/Os
Output clock frequency select signals. Pull-up to vcc

Supply and Termination Voltages
Description
Pin Number
Positive power supply (+3.3V or 0V)2, 4, 6, 8, 10, 12, 14, 15, 16, 17, 18,20, 22, 24
Negative power supply (0V or -3.3V)
1, 7, 13, 19

3July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERMIN TYP MAX UNIT
COMMENTS
General Parametersvee-3.1-3.3-3.5
V±6%vcc
0.0
V
External ground
Ivee
255mA
Power consumption
845mW
Junction temperature
-25
50
125°C
HS Input Clock (cp/cn)
Maximum Frequency
50GHz
Swing
120
800
mV
Differential or SE, p-p
CM Voltage Level
vcc-0.8 vcc-0.2 vcc
mVMust match for both inputs
Output Divided Clock (cop/con)
Maximum Forwarded Frequency 25
GHz
div = “0”Maximum Divided Frequency
25GHz
div = “1”Logic “1” level
Vvcc
Logic “0” levelvcc-0.4
V
With external 50Ohm termination
Duty cycle
455055%Additive Jitter
TBD
ps
Peak-to-peak
Divide Ration Control Signals (div, div4)
Logic “1” level
VCC-0.4
V
Logic “0” level
VEE+0.4
V

PACKAGE INFORMATIONThe chip die is housed in a custom 24-pin CQFP package shown in Fig. 2. The package provides a center
heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for thissection to be soldered to the vcc plain, which is ground for a negative supply, or power for a positivesupply.
The part’s identification label is ASNT8133-KMC. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per EU 2002/95/EC for all six
substances.
Rev. 1.1.2

4July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Fig. 2. CQFP 24-Pin Package Drawing (All Dimensions in mm)

Rev. 1.1.2

5July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.1.2
1.1.1
1.0.1
1.0.0

Rev. 1.1.2

Date
Changes
07-2019 Updated Letterhead
01-2016 Revised Description section
Added content to Electrical Characteristics table
07-2015 First release03-2015 Preliminary release

6

July 2019