Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT7113A-KHC
4.0GSps / 20GHz Differential Track-and-Hold Amplifier

gaincrlvcc

varcrlvcc

vp0p9

More than 8-bit accuracy within the full frequency range
Sampling speed from 50MSps to 4GSps
Nominal 0dB differential gain with manual adjustment
Adjustable duty cycle of the internal sampling clocks
Adjustable input bandwidth
Adjustable overall gain
Fully differential input and output data and clock buffers with on-chip 50Ohm termination
Dual power supply
Total power consumption of 1.75W
Fabricated in SiGe for high performance, yield, and reliability
Custom CQFN 24-pin packagevcc







veevcc

vcc

dp

qp

vcc

vcc

1

vcc

cn

vcc

vcc

vcc

cp

qn

vcc

dnt2crlRev. 1.0.2

ASNT7113A

vee

March 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
vp0p9 varcrl

dpdncpcnInput
Data
Equalizer

Sampling
StrobeGenerator

dataSampling

OutputBlockBuffer

qpqns1s2t2crl

gaincrl
Fig. 1. Functional Block Diagram

The ASNT7113A-KHC SiGe IC is a high-speed, temperature stable, and broadband track-and-hold
amplifier (THA) with improved reliability. The IC shown in Fig. 1 performs sampling of an input
differential analog signal using two internally-generated strobe signals s1 and s2, and delivers a step-like
differential signal to the output. It features an adjustable track period length controlled by the t2crl voltagethat modifies the states of internal delay lines. This allows for maximizing the length of the valid output
step.
The differential gain of the chip is approximately 0dB, which corresponds to a single-ended-to-differential
gain of -6dB. The gain can be adjusted using the external control voltage gaincrl. The chip supports both
AC-coupled, and DC-coupled inputs. In the DC-coupled mode, the input common-mode voltage must be
equal to vcc for optimal performance of the chip. The input sampled data path includes an equalizer thatincreases the bandwidth of the chip. The level of equalization is controlled by the external voltage varcrl.
The frequency response, and gain of the part is also controlled by the positive supply voltage vp0p9 thatpowers the input buffers of the Track-and-Hold. This voltage defines the common mode of the data signal
at the input of the sampling switch, and thus the frequency response of the device. Lower voltages resultin less peaking in the input buffer, and less overall gain of the device.
The part’s outputs support the CML-type logic interface with an on-chip 50Ohm termination to vcc, andmay be used differentially, AC/DC coupled, single-ended, or in any combination (also see POWER
SUPPLY CONFIGURATION). The differential DC signaling mode is recommended for optimalperformance.

Rev. 1.0.2

2March 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Input Data Equalizer
The input data’s bandwidth can be adjusted by the internal equalizer controlled with the external voltage
varcrl. The equalizer is designed to compensate for the gain drop at high frequencies due to thecharacteristics of the front-end circuitry, and the sampling block itself. The measured frequency responseof the IC at maximum (magenta line) and minimum (orange line) values of the varcrl voltage is shown inFig. 2. The measurements have been performed at the intermediate setting of the gain control (see Fig. 4).
10Gain, dB-1-2-3-4-50.1

1VarMAX

10100F, GHzVarMIN

Fig. 2. Frequency Response of SHA with Max and Min Equalization

Input Clock Buffer
The input clock buffer converts an external clock cp/cn into two internal signals s1 and s2 withcontrolled pulse width (PW) as shown in Fig. 3.
TrackHolds2s1PW

Valid output

Fig. 3. Sampling Diagram

This allows for optimization of the hold time, and the length of the valid output signal period. The valueof PW is reversely proportional to the t2crl voltage.

Sampling Block with Output Buffer
The sampling block performs conversion of the input signal into a step-like sampled signal under controlof s1 and s2 pulses. The sampled signal is amplified by the output buffer to achieve a total gain ofapproximately 0dB. The gain can be adjusted using the gaincrl voltage signal. The measured frequency
response of the SHA with the maximum and minimum gain at 2.5GSps rate is shown in Fig. 4.
Rev. 1.0.2

3March 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

10Gain, dB-1-2-3-4-5-60.1

110100F, GHzFig. 4. THA Gain at Max and Min gaincrl Values vs. Data Frequency

The harmonic distortion of the THA has been demonstrated by its 3rd harmonic as shown in Fig. 5 fordifferential clock, and data input signals at the sampling rate of 4GSps. The data amplitude is 125mV
differential or 125mV pk-pk at both direct and inverted pins.
-5 0-5 1-5 2-5 3dBc

-5 4-5 5-5 6-5 7-5 8-5 9-6 002468101214

161820Fdata, GHzFig. 5. 3-rd Harmonic at 4GHz Input Clock (C) and 125mV Differential Data (D) Amplitude

The linearity of the signal conversion is illustrated by Fig. 6 that demonstrates the part’s gain at 2.5GSps.
-0.86
-0.88
-0.9

Gain, dB

-0.92
-0.94
-0.96
-0.98
-1-1.02
-1.04
-1.06
050

100

150

200

250

300

InputAmplitude SE, mV p-p

Fig. 6. THA Gain vs. Input Data Amplitude at Medium State of gaincrl

Rev. 1.0.24March 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

POWER SUPPLY CONFIGURATIONThe part operates with either a negative supply scheme (vcc = 0.0V = ground), or a positive supply
scheme (vee = 0V = ground). In case of the positive supply, all I/Os need AC termination whenconnected to any devices with 50Ohm termination to ground. Different PCB layouts will be needed foreach different power supply combination.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied.
Table 1. Absolute Maximum Ratings

Parameter
MinMaxUnits
First Supply Voltage (vee)-3.5 (negative scheme) 0 (positive scheme)
V
Second Supply Voltage (vcc)
0 (negative scheme) 3.5 (positive scheme)
V
Third Supply Voltage (vp0p9)
vcc+1.1
V
Power Consumption
2W
RF Input Voltage Swing (Diff)
2.0
V pk-pk
Clock Input Voltage Swing (Diff)
1.0
V pk-pk
Case Temperature+90ºC
Storage Temperature-40+100ºC
Operational and storage Humidity
1098%

TERMINAL FUNCTIONSTERMINAL
NameNo.
TypeDESCRIPTION

High-Speed I/Os
Sampling clock inputs with internal SE 50Ohm termination tovcc
AnalogAnalog sampled data inputs with internal SE 50Ohm
inputtermination to vcc
CML output Differential data outputs with internal SE 50Ohm termination
to vcc. Require external SE 50Ohm termination to vcc
Controls
t2crl
1Analog voltage Sampling clock delay control
gaincrl
13 Analog voltage Gain adjustmentvarcrl
15 Analog voltage Equalizer peaking control
Supply and Termination Voltages
NameDescription
Pin Numberstvcc
1 positive supply voltage
2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24
vee
Negative power supply
7, 19nd
vp0p9 2 positive power supply
17
cpcndpdnqp
qnRev. 1.0.2

352123119

CML input

5March 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERMAXUNITCOMMENTS
General Parameters-3.3 / 0-3.2 / 0-3.1 / 0V
Negative scheme / Positive scheme
vee0 / 3.10 / 3.20 / 3.3
V
Negative scheme / Positive scheme
vcc
0.75
0.85
0.95
V
Above vcc, any scheme
vp0p9
Ivcc
430mA
Ivee = Ivcc + Ivp0p9
Ivp0p9100mAPower consumption
1750mW
Junction temperature
-2550
125°C
Input Data (dp/dn)
Input data frequency
0.020GHzSwing, differential,
0300mV
3rd HD<-52dBc in full data bandwidthp-p
0400mV
3rd HD <-48dBc in full data bandwidth
0500mV
3rd HD <-45dBc in full data bandwidth
CM Voltage Level
VFor DC couplingvcc
S11-10dB
DC to 20GHz
Input Clock (cp/cn)
Frequency
0.05
4.0GHzSwing
80240mV
SE or differential, p-p
CM Voltage Level
Vvcc
Jitter50fs
p-p
Duty cycle
4550
55%
Lower variation recommended
Delay Control Voltage (t2crl)
Voltage range
vcc – 1.4vcc
V
Adjustment range
20
ps
For the pulse width of s1 and s2
Gain Control Voltage (gaincrl)
Voltage range
vcc – 1.8vcc
V
Equalizer Control Voltage (varcrl)
Voltage range
vcc – 1.8vcc
VAdditional peaking
1.5dB
At 20GHz and nominal conditions
Input Data Common Mode Control (vp0p9)
Voltage Range
vcc + 0.7
vcc + 0.9
VHS Output Data (qp/qn)
CM Level
vcc-0.4
Vrd3 HD
See Fig. 5
Noise12nV/Hz1/2 At 2.5GSps within full data bandwidth
Track period length250
ps
At 2.5GSps
Total DC gain-2.1
0.1
dB
Adjustable by gaincrl signal
S22-20dB
DC to 4GHz

Rev. 1.0.2

MINTYP6March 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATIONThe chip die is housed in a custom 24-pin CQFP package shown in Fig. 7. The package provides a center
heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for thissection to be soldered to the vcc plain, which is ground for a negative supply, or power for a positivesupply.

Fig. 7. CQFP 24-Pin Package Drawing (All Dimensions in mm)

Rev. 1.0.2

7March 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

The part’s identification label is ASNT7113A-KHC. The first 9 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with Commission Delegated Directive (EU) 2015/863 of 4 June 2015 amending Annex
II to Directive 2011/65/EU of the European Parliament and of the Council as regards the list of restrictedsubstances (Text with EEA relevance) on the restriction of the use of certain hazardous substances in electricaland electronics equipment (RoHS Directive) in accordance with the definitions set forth in the directives for
all ten substances.

REVISION HISTORY
Revision
1.0.2

Rev. 1.0.2

Date03-2021

ChangesFirst release

8March 2021