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ASNT6119A-KMF
32.5Gbps Advanced Driver/Amplifier
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High-speed limiting amplifier with selectable built-in pre-emphasis
Four pre-emphasis taps with externally controlled weight and inversion
Adjustable data output amplitude and eye quality
Single-ended output data eye cross point adjustment
Optional main clock frequency multiplier by 2
Main clock duty cycle indicators located before and after the multiplier
Opposite and parallel adjustment of the main clock and data delays
Additional clock input
Fully differential CML input and output data, and clock interfaces
Selectable main or additional clock at the output with adjustable amplitude
High-speed CML 3-wire interface for digital controls
On-chip linear temperature sensor
Two power supplies: negative -4.3V and floating positive +3.5V
Average power consumption: 4.0W
Custom CQFP 64-pin package

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DESCRIPTION
vth

tune1/2/3/4
T1
T2
SB
Delay1

Delay2ci0p/ci0n

Delay1

Delay2

dlypolvddshddcqp/dcqn
qp/qn
xadjp/xadjn

I

cosel

skwpolci1p/ci1n

DOB

I

DCycl

skwadjdlyadj
phadj

3wdin
3wcin
3wening

Clk x2

inv1/2/3/4

dcyc0

T4

I

Digital tap controls

dp/dn

T3

I

COB

vddshccop/concampadj

DCycl

dcyc1

Temp

temp

3-Wire Interface

Fig. 1. Functional Block Diagram

The ASNT6119A-KMF SiGe IC shown in Fig. 1 is an advanced programmable driver-amplifier(ADA) with built-in 4-tap pre-emphasis. The ADA generates a combination of four delayedcopies of its input differential data signal dp/dn with certain user-controlled weights andpolarities. The copies are created in a 4-bit shift register activated by the ADA’s internal highspeed clock signal (see Sampling Block and Taps). This clock signal is a copy of the main input
clock ci0p/ci0n with either matching or doubled (multiplied-by-2) frequency. In the multiplyby-2 clock mode, the duty cycles of the input and internal clock signals are monitored, and theoutput duty cycle can be adjusted through the external control port phadj (see Clock
Multiplier). For the part’s correct operation, the input data rate in Gbps should be equal to theinternal clock frequency in GHz.
Input clock and data signals can be delayed in the same or opposite directions to ensure theircorrect phase relation at the inputs of the shift register and at the chip outputs (see Input Delay
Section). The ADA can accept one additional clock signal ci1p/ci1n and deliver it to the output
port cop/con instead of the main clock ci0p/ci0n, thus operating as a clock buffer (seeAdditional Input Clock and Clock Output Buffer).
The part’s I/Os support CML logic interface with on-chip 50Ohm termination to ground.
External 50Ohm termination is also required. DC-coupling for data and clock output ports is
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strongly recommended. The input ports can use DC or AC coupling. Differential input clock anddata are strongly recommended. Amplitude and peaking in the clock and data output signals canbe externally adjusted. Both single-ended data output signals also have controlled DC commonmode levels and eye crossing points (see Data Output Buffer).
All operational modes of the chip are controlled through a high-speed 3-wire serial interface. For
more details see 3-Wire Interface Control Block.
The chip operates from one negative power supply (positive pin connected to external Ground,negative pin vee = -4.3V) and one floating positive power supply (negative pin connected to vee
and positive pin v3p5 = 3.5V). It is recommended to keep the relative deviation of v3p5 from
Ground within less than ±0.1V.

Input Delay Section
As shown in Fig. 1, the ADA accepts differential input data dp/dn and clock ci0p/ci0n signals
and inserts them both into identical variable delay blocks Delay1 and Delay2 that can be
adjusted in parallel or opposite modes depending on the polarity of internal digital signals
skwpol and dlypol (“0”=parallel, “1”=opposite) provided by the 3-Wire Interface block. The
Delay1 blocks are controlled by the analog voltage skwadj. The Delay2 blocks are controlled
by the analog voltage dlyadj.
It should be noted that the delay settings may affect the multiplied-by-2 clock’s duty cycle andshould be tuned for each specific case.

Clock Multiplier
The clock doubler Clkx2 uses a “delay and XOR” mechanism to create output clock pulses fromeach edge of the input clock ci0p/ci0n. The multiplier is intended for operation with input clock
signals within a certain frequency range specified in ELECTRICAL CHARACTERISTICS.
Analog control voltage phadj performs a dual function of multiplier activation and linear phase
control. Voltages within the linear control range activate the multiplication function and are used
for tuning the block’s internal delay in order to achieve 50% duty cycle of the multiplied clock.
Voltages below the switch-off threshold disable the multiplication function and allow for direct
passing of the input clock to the multiplier’s output.
Two duty cycle control blocks DCycl are used for monitoring the clock pulse shapes before andafter the multiplier. The first block is positioned before the multiplier and delivers single-ended
analog voltage dcyc0 that indicates the input clock’s duty cycle deviation from 50%. The second
block is positioned after the multiplier and delivers a similar signal dcyc1 for the output clock.
Both generated output voltages can be used in combination with phadj input within external
control loops for getting an optimal shape of the multiplied clock.
It should be noted that the duty cycle of the multiplied clock may depend on the delay settings(see Input Delay Section).

Additional Input Clock and Clock Output Buffer
The ADA can also accept an additional input clock signal ci1p/ci1n and deliver it to the clock
output. This allows the IC to operate solely as a clock amplifier where the output clock signal’s
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amplitude supplied by output buffer COB can be adjusted using the analog signal campadj. The
amplitude changes from its minimum value (campadj = switch-off threshold) to its maximum
value (campadj = maximum). COB can also be completely disabled by applying campadj
voltage below the switch-off threshold.
Either ci0 or ci1 clock signals can be processed by the output buffer COB. Selection of the input
clock is accomplished through the digital control signal clock select (“0” - ci0, “1” - ci1)delivered by the 3-wire interface block.
The quality of the output signal’s shape can be optimized using the external control vddshc.
This voltage controls peaking on the falling edge of the output signal. More positive voltages
correspond to higher peaking.

Sampling Block and Taps
Sampling block SB is essentially a 4-bit shift register that generates 4 delayed data streams T1T4 needed for the ADA’s 4-tap pre-emphasis capability. As stated above, the analog control
voltage dlyadj is used to adjust the phase relationship between clock and data to ensure optimum
sampling in SB. The four samples of the data stream with certain weights and polarities aredelivered to the output buffer via four identical channels.
The polarity of the data streams can be independently inverted by circuit blocks I under control
of four signals inv1/inv2/inv3/inv4 (“0”=direct, “1”=inverted) provided by the 3-wire interface.
This version of the ADA has 4 Taps (1, 2, 3, and 4) designed as 11 parallel buffers with acommon load that are combined into a single output driver. Each buffer has its maximum
amplitude equal to 1/8th of the optimal total output amplitude Aout. The first 7 buffers can be
assigned to one of 2 Taps or switched off completely using digital signals provided by the 3-wireinterface as shown in Table 1. For detailed interface mapping, see the 3-Wire Interface Control
Block section below.
Table 1. Buffer’s Assignment to Taps

1
Buffers
1/2
Taps
Amplitude
Control

2
1/2

3
4
5
6
3/2
3/2
3/2
4/2
Constant, 0 or 1/8th of Aout
Digital

7
4/2

8
9
10
11
1
2
3
4
From 0 to Aanalog = Aout/8
Analog

The last 4 buffers are assigned to one Tap each and are linearly controlled by four external
voltages tune1/tune2/tune3/tune4 from minimum (0) to maximum (Aanalog) amplitude that is
approximately equal to 1/8th of Aout. The actual value of the amplitude Aanalog available for the
analog controls can be adjusted through the external control voltage vth. The calibration
procedure is described in the Application Notes.
It should be noted that the output amplitude may exceed the optimal value by up to 3/8th of Aout,
if more than one analog buffer is activated. It is recommended to avoid such situations by theappropriate assignment of Tap weights.

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For example, if all seven digital buffers are activated, the total value of the analog amplitude
should not exceed 1/8th of Aout. This means that one analog buffer can be fully switched on while
the controls of the three remaining analog buffers should stay at minimum. If two analog buffers
are required, then one of them can be assigned a weight of A1 ≤ 1/8th of Aout and the other one canhave a weight of A2 ≤ 1/8th-A1 .
The recommended algorithm of the weight assignment is described in the ASNT6119
Application Notes.

Data Output Buffer
Data output buffer DOB includes several features to tune the output data signal generated by the
ADA.
The quality of the output signal shape can be optimized using the control voltage vddshd similar
to what is described in the Additional Input Clock and Clock Output Buffer section above.
Optimized output eyes with a 625mV amplitude delivered from one Tap at data rates of 28Gb/s
and 32Gb/s are shown in Fig. 2 and Fig. 3 respectively. Fig. 4 to Fig. 6 show this part’s
capabilities for driving a PAM4 signal.
Differential analog control voltage xadjp/xadjn can be utilized to adjust the crossing points ofsingle-ended output eyes. At the default state of xadjp = xadjn = 0V, the crossing points in both
direct and inverted eyes should be centered. The crossing points are moving up in the direct eye
and down in the inverted eye if xadjp = -xadjn > 0, or in the opposite directions if xadjp = xadjn < 0.

Fig. 2. 1-Tap Output Eye at 28Gb/s Data Rate

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Fig. 3. 1-Tap Output Eye at 32Gb/s Data Rate

Fig. 4. PAM4 Output Eye Diagram at 25.8Gb/s Data Rate

Finally, 1.0KOhm resistors are attached to both data outputs qp and qn to provide DC shifting of
the output signals. Access to the resistors is available through control pins dcqp/dcqn.

Temperature Sensor
A linear temperature sensor is included on chip. Its behavior is illustrated in Fig. 7 below. The
demonstrated voltage has been generated on the internal 11KOhm resistor connected to vdd.

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Fig. 5. PAM4 Output Eye Diagram at 28Gb/s Data Rate

Fig. 6. PAM4 Output Eye Diagram at 28Gb/s Data Rate

Fig. 7. Temperature Sensor’s Characteristic

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3-Wire Interface Control BlockTo reduce the physical number of digital control inputs to the ADA, a 32-bit shift register with a
3-wire input interface has been included on chip. The digital control bits applied through 3wdin
input are latched in and shifted down the register by negative edges of low-speed clock 3wcin(Bit 0/MSB first). Write enable signal 3wenin must be set to logic “1” during the data read-inphase and then set to logic “0” to retain the shifted in values after 32 clock periods of 3wcin.
Table 2 below maps the input 32-bit word to the internal digital control signals.
Table 2. 3-Wire Interface Bit Map

Bit #Function

0, MSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31, LSB

Activation of additional 1/2 pre-buffer current in one of the Taps.
Must be ON if the amplitude in the corresponding Tap is morethan half of its maximum value (more than 1/16th of the full output
amplitude, or Aout/16).
Activation of analog-controlled sections of the Taps including thecorresponding output drivers and 1/2 pre-buffer currents.

Rev.1.4.2

Buffer 7 activation (Aout/8 for Tap 2 or Tap 4 as defined by Bit 16)
Buffer 6 activation (Aout/8 for Tap 2 or Tap 4 as defined by Bit 17)
Buffer 5 activation (Aout/8 for Tap 2 or Tap 3 as defined by Bit 18)
Buffer 4 activation (Aout/8 for Tap 2 or Tap 3 as defined by Bit 19)
Buffer 3 activation (Aout/8 for Tap 2 or Tap 3 as defined by Bit 20)
Buffer 2 activation (Aout/8 for Tap 2 or Tap 1 as defined by Bit 21)
Buffer 1 activation (Aout/8 for Tap 2 or Tap 1 as defined by Bit 22)
Not used
Buffer 7 assignment to Tap 2 or Tap 4
Buffer 6 assignment to Tap 2 or Tap 4
Buffer 5 assignment to Tap 2 or Tap 3
Buffer 4 assignment to Tap 2 or Tap 3
Buffer 3 assignment to Tap 2 or Tap 3
Buffer 2 assignment to Tap 2 or Tap 1
Buffer 1 assignment to Tap 2 or Tap 1
Not used
Selection of the clock (C0 or C1) to be sent to the output
Selection of the data and clock short delay (opposite or parallel)
Selection of the data and clock long delay (opposite or parallel)
Activation of the Tap 4 data inversion
Activation of the Tap 3 data inversion
Activation of the Tap 2 data inversion
Activation of the Tap 1 data inversion
Not used

8

State at
Bit=”1”/”0”
ON/OFF in Tap 4
ON/OFF in Tap 3
ON/OFF in Tap 2
ON/OFF in Tap 1
ON/OFF in Tap 4
ON/OFF in Tap 3
ON/OFF in Tap 2
ON/OFF in Tap 1
ON/OFF
ON/OFF
ON/OFF
ON/OFF
ON/OFF
ON/OFF
ON/OFF
Tap 2 / Tap 4
Tap 2 / Tap 4
Tap 2 / Tap 3
Tap 2 / Tap 3
Tap 2 / Tap 3
Tap 2 / Tap 1
Tap 2 / Tap 1
C1 / C0
Parallel/Opposite
Parallel/Opposite
ON/OFF
ON/OFF
ON/OFF
ON/OFF

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This chip includes a high-speed 3-wire interface with 50Ohm terminations to vdd for all
interface inputs. This CML configuration allows for the dynamic Tap reconfiguration inaccordance with PCI control regulations. The total reconfiguration time does not exceed 100ns
from the external assignment of new control signals to the final settling of the output data
amplitude.

TERMINAL FUNCTIONSTERMINAL
Name No.
Type
dp
dn
ci0p
ci0n
ci1p
ci1n
cop
con
qp
qn

Description
High-Speed I/Os
Differential high-speed data inputs

19 CML input with
21 internal SE 50Ohm
28 termination to vcc Differential high-speed main clock input
30
35
Differential high-speed additional clock input
37
46
CML output
Differential high-speed clock output
44 requires external
SE 50Ohm
56
Differential high-speed data output
58 termination to vcc
Low-Speed I/Os
3wenin 39 CML input with Enable input for 3-wire interface
3wcin 40 internal SE 50Ohm Clock input for 3-wire interface
3wdin 41 termination to vcc Data input for 3-wire interface
Analog Control Voltage Inputs
xadjp
5 Analog input with Output data eye cross point adjustment, Differential
100KOhm
xadjn
3
tune4
7 termination to vdd Tap 4 analog weight adjustment, SE
tune3
8
Tap 3 analog weight adjustment, SE
tune2
9
Tap 2 analog weight adjustment, SE
tune1
10
Tap 1 analog weight adjustment, SE
vth12Threshold voltage for the analog maximum value adjustment
dlyadj 24
Adjustment of Delay 2 blocks, SE
skwadj 25
Adjustment of Delay 1 blocks, SE
phadj
26
Clock multiplier delay (output duty cycle) adjustment, SE
campadj 51
Clock output amplitude adjustment, SE
dcqp
61
Analog input
Direct data output common-mode DC shift, SE
dcqn
62
Inverted data output common-mode DC shift, SE
Analog Control Indicators
temp
14
Analog output Linear temperature-dependent voltage output with internal
11KOhm termination to vdd.
dcyc1 50
Linear voltage indicating output clock duty cycle
dcyc0 52
Linear voltage indicating main input clock duty cycle
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Supply And Termination Voltages
Description
Pin Number
External ground2, 4, 6, 11, 13, 15, 18, 20, 22, 27, 29, 31,
34, 36, 38, 43, 45, 47, 54, 55, 57, 59, 60
vee-4.3V negative power supply
17, 32, 33, 48, 64
v3p5 +3.5V positive power supply
1, 16, 23, 49, 63
Negative pin to vee
vddshC Output clock and data peaking adjustment42
vddshD Positive power supply. Negative pin to vee
53
Name
vdd

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 3 may cause damage to thisproduct and/or lead to reduced reliability. Functional performance is specified over therecommended operating conditions for power supply and temperature only. AC and DC device
characteristics at or beyond the absolute maximum ratings are not assumed or implied. All min
and max voltage limits are referenced to ground (assumed vdd).
Table 3. Absolute Maximum Ratings

Parameter
Negative Supply Voltage (vee)Positive Supply Voltage (v3p5)
Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Rev.1.4.2

Min

-40
10
10

10

Max
-4.8
3.8
5.0
1.2
+90
+100
98
98

Units
V
V
W
V
ºC
ºC
%
%

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ELECTRICAL CHARACTERISTICSPARAMETER
vee
vdd
v3p5
I-4.3
Iv3p5
Power
Junction temperature
Rate
SE Swing
CM LevelFrequency (C0 input)

SE Swing
CM LevelRate
SE Swing
CM Level
Rise/Fall TimesMIN

TYP MAX UNIT
COMMENTS
General Parameters
-4.1
-4.3
-4.5
V
0.0
V
External ground
3.4
3.5
3.6
V
“-“ pin to vee
120
220
mA
Depending on the settings ofthe clock multiplier and the
850
1020
mA
clock and data amplitudes1)
3.5
4.0
4.5
W
0
50
100
°C
Data input (dp/dn)
1.032.5 Gb/s
50
200
500
mV
Peak-to-peakvdd-(SE swing)/2
Clock inputs (ci0p/ci0n, ci1p/ci1n)
1.0
17 GHzFx1 mode, any skwadj anddlyadj4.0
16.25 GHzFx2 mode, skwadj anddlyadj need tuning
50
200
500
mV
Peak-to-peakvdd-(SE swing)/2
Data output (qp/qn)
1.0
32.5
Gbps
0.0
1250
mV
Peak-to-peak
vdd-0.1
vdd-0.75
V
Depends on the amplitude2)
12
13
14
ps
20%-80%

Clock output (cop/con)
SE Swing, max
530
920
mV
Pk-pk, 1.0-17GHz
160
400
mV
Pk-pk, 18-32GHz
CM Level
vdd-0.05
vdd-0.55
V
Depends on the amplitude3)
Rise/Fall Times
TBD
ps
20%-80%SE tuning ports (tune1/2/3/4, skwadj, dlyadj, phadj, campadj)
Linear control voltage
vdd-2
vdd
V
Switch-off threshold
vdd-2
V
Cross point control (xadjp/xadjn)
Differential voltage range vdd-8.0
vdd+8.0V±4V at each input
CM Level
vdd
Current in/out of the pin+4 / -4
mA at +4V / -4V
Threshold control (vth)
Voltage range
vdd-2
vdd
V
DC common mode voltage control (dcqp/dcqn)
Voltage range
V
vee
vdd
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PARAMETERMIN TYP MAX UNIT
COMMENTS
Externally Controlled Operational Ranges
Clock-to-Data skew
-30
+30
ps
opposite skwadj control
Clock and Data delay
0+30
psparalllel skwadj control
Clock-to-Data skew
-45
+45
ps
opposite dlyadj control
Clock and Data delay
0+45
psparalllel dlyadj control
Output eye cross point
-25
+25
%
of the eye amplitude

PARAMETERMIN TYP MAX
UNIT
Variable supply voltages (vddshc, vddshd)
Voltage range
2.8
4.3
V
Ivddshd
2.2
mA
Ivddshc
1.1
mA
Duty Cycle Indicator (dcyc0/dcyc1)
Voltage range
vdd-3.3
vdd-0.8
V
Temperature Sensor (temp)
Voltage range
vdd-3.3
vdd-2.3V
3-Wire Inputs (3wdin, 3wcin, 3wenin)
High voltage level
vdd-0.2
vdd
V
Low voltage level
vdd-0.7
V
Clock speed
400
1000
MHz

COMMENTS“-“ pin to vee
All 4 taps active

Power Supply Currents(Preliminary Data, for Reference Only)co amplitude q amplitude Clock multiplier I-4.3, mA Iv3p5, mAminmin
off (Fx1)
120
850
min
min
on (Fx2)
120
920
min
max
off (Fx1)
180
880
min
max
on (Fx2)
180
950
max
min
off (Fx1)
160
930
max
min
on (Fx2)
160
1000
max
max
off (Fx1)
220
950
max
max
on (Fx2)
2201020

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Data Output Common Mode Voltage Levels(Preliminary Data, for Reference Only)
Amplitude
Total, mV Digital Analog, mV
150
0
min
150
Aout/8max
310
Aout/8min
310
2Aout/8max
470
2Aout/8min
470
3Aout/8
max
630
3Aout/8
min
630
4Aout/8max

VCM, V
vdd-0.089
vdd-0.182
vdd-0.182
vdd-0.275
vdd-0.275
vdd-0.368
vdd-0.368
vdd-0.461

Amplitude
Total, mV Digital Analog, mV
790
4Aout/8
min
790
5Aout/8
max
950
5Aout/8min
950
6Aout/8
max
1100
6Aout/8min
1100
7Aout/8
max
1250
7Aout/8min

VCM, V
vdd-0.461
vdd-0.554
vdd-0.554
vdd-0.647
vdd-0.647
vdd-0.740
vdd-0.740

Clock Output Common Mode Voltage Levels(Preliminary Data, for Reference Only)
Amplitude, mV 100
200
300
400
500
600
700
750
VCM, V
vdd-0.07 vdd-0.14 vdd-0.21 vdd-0.28 vdd-0.35 vdd-0.42 vdd-0.49 vdd-0.54

PACKAGE INFORMATIONThe chip die is housed in a custom 64-pin CQFP package. The dimensioned drawings are shownin Fig. 8.
The package provides a center heat slug located on its back side to be used for heat dissipation.
ADSANTEC recommends for this section to be soldered to the vdd plain, which is ground for anegative supply, or power for a positive supply.
The part’s identification label is ASNT6119A-KMF. The first 9 characters of the name before
the dash identify the bare die including general circuit family, fabrication technology, specificcircuit type, and part version while the 3 characters after the dash represent the package’s
manufacturer, type, and pin out count.
This device complies with the Restriction of Hazardous Substances (RoHS) per EU 2002/95/EC
for all six substances.

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Fig. 8. CQFP 64-Pin Package Drawing (All Dimensions in mm)

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REVISION HISTORY
Revision
1.4.2
1.4.1
1.3.1
1.2.1
1.1.1
1.0.1

Rev.1.4.2

Date
07-2019
03-2017
03-2017
07-2016
02-2016
02-2016

Changes
Updated Letterhead
Added PAM4 eye diagrams
Corrected 3-wire clock speed
Corrected Table 2. Bits 8-14
Corrected part description on first page
First release

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