Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT5121D-KMC
DC-35GHz Clock Distributor 1-to-3

Matched phase delays for all outputs



Fully differential CML input interfaces

Fully differential CML output interface with 350mV single-ended swingSingle +3.3V or -3.3V power supplyPower consumption: 760mWFabricated in SiGe for high performance, yield, and reliability

Custom CQFP 24-pin packagevee

One input differential signal port and three differential amplified output signal ports

vcc

c0nExhibits low jitter and limited temperature variation over industrial temperature range

vcc

c0p

High-speed broadband Clock Amplifier and Distributor

vcc

vee

vcc

vcc

cp

c1p

ASNT5121D

vcc

vcc

cn

c1n

vcc

vcc

Rev. 1.0.2

1vcc

c2p

vcc

c2n

vcc

vee

vee

July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
c0pc0n50505050cpc1pcnc1n50505050c2pc2nFig. 1. Functional Block Diagram

The temperature stable ASNT5121D-KMC SiGe IC provides active broadband clock signal splitting, andis intended for use in high-speed measurement / test equipment. The IC shown in Fig. 1 can process abroadband high-speed clock input signal cp/cn and deliver three broadband high-speed clock phasematched output signals c0p/c0n, c1p/c1n, c2p/c2n.
The part’s I/O’s support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.

POWER SUPPLY CONFIGURATIONThe part can operate with either a negative supply (vcc = 0.0V = ground and vee = −3.3V), or a positive
supply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os need AC termination
when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be neededfor each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.
Rev. 1.0.2

2July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402www.adsantec.com

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings may cause damage to this product and/or lead toreduced reliability. Functional performance is specified over the recommended operating conditions for
power supply and temperature only. AC and DC device characteristics at or beyond the absolutemaximum ratings are not assumed or implied. All min and max voltage limits are referenced to ground(vcc).
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max-3.6
0.83
1.0+90+1009898

Units
VW
VºCºC%%TERMINAL FUNCTIONSTERMINAL
Name
No.
Typecpcnc0p
c0n
c1p
c1n
c2p
c2n
Name
vcc
vee

Rev. 1.0.2

DESCRIPTION

High-Speed I/Os
21
CML Differential high speed data/clock inputs with internal SE 50Ohm
input termination to vcc
23
17
CML Differential high speed data/clock outputs with internal SE 50Ohm
output termination to vcc. Require external SE 50Ohm termination to vcc1511
CML Differential high speed data/clock outputs with internal SE 50Ohm
output termination to vcc. Require external SE 50Ohm termination to vcc
95
CML Differential high speed data/clock outputs with internal SE 50Ohm
output termination to vcc. Require external SE 50Ohm termination to vcc
3
Supply and Termination Voltages
Description
Pin Number
Positive power supply (+3.3V or 0)2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24
Negative power supply (0V or -3.3V)
1, 7, 13, 19

3July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERveevcc
Ivee
Power consumption
Junction temperature
Frequency
Swing
CM Voltage Level
Frequency
Logic “1” level
Logic “0” level
Rise/Fall times
Output Jitter
Duty cycle

MIN

TYP

MAX UNITCOMMENTS
General Parameters
-3.1
-3.3
-3.5
V
±6%
0.0
V
External ground
230mA
760
mW
-4025125°C
HS Input Clock (cp/cn)
DC35GHz
0.05
1.0V
Differential or SE, p-pvcc-0.8
vcc
VMust match for both inputs
HS Output Clock (c0p/c0n, c1p/c1n, c2p/c2n)
DC35
GHzVvccvcc-0.35
VWith external 50Ohm DC termination
6810ps20%-80%1ps
Peak-to-peak
455055%
For clock signal

PACKAGE INFORMATIONThe chip die is housed in a custom 24-pin CQFP package shown in Fig. 2. The package provides a center
heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for thissection to be soldered to the vcc plain, which is ground for a negative supply, or power for a positivesupply.
The part’s identification label is ASNT5121D-KMC. The first 9 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
The IC complies with the Restriction of Hazardous Substances (RoHS) per EU 2002/95/EC for all 6substances.

Rev. 1.0.24July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Fig. 2. CQFP 24-Pin Package Drawing (All Dimensions in mm)

Rev. 1.0.2

5July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.0.2
1.0.1
1.0.0

Rev. 1.0.2

Date07-2019
08-2015
09-2014

Changes
Updated LetterheadFirst release
Preliminary release

6July 2019