Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT6152-KMM
8-28Gbps Dual CTLE with Error Detection/Pre-emphasis

Limited temperature variation over industrial temperature rangeDie size 1.2x1.2mm2

Optional custom CQFP 44-pin package

vcc
vee
vcc
amplim
vcc
ampd
vcc

vcc
limadjvcc
errdetASNT6152-KMM

q1n
vcc
q1p
vcc

vcc
q2p
vcc

1d2p
vcc
d2n
vcc

vcc
d1n
vcc

q2n
vcc
veevcc

vcc
vee
vcc
d1p

Rev.1.1.2

vddvccFabricated in SiGe for high performance, yield, and reliability

vcc
3weninvcc

3wdout
vcc
3wdin
vcc
3wcin

High-speed adjustable linear equalizer
Two independent channels and two independent equalization stages per channel
High-speed CMOS 3-wire interface for digital controls
Self-adjusted 0dB DC gain
Additional manual adjustment of DC gain through 3-wire interface
Error detector in the first channel
Adjustable error detector output range through 3-wire interface
Fully differential CML-type analog input and output interface
Two power supplies for the analog section and 3-wire interface
Average power consumption with/without error detector: 1.4W/1.0Wvcc






January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
d1p
d1n3-wire

d2p
d2n

Input
Buffer

EQ
Stage

EQ
Stage

OutputBufferpeakCrl

peakCrl

gainCrl

q1nError
Detector

3-WireInterface

Input
Bufferq1p

peakCrlpeakCrl

gainCrl

EQStage

EQStage

OutputBuffer

ErrDetq2pq2nFig. 1. Functional Block Diagram

The ASNT6152-KMM shown in Fig. 1 is an adaptive continuous-time linear equalizer (CTLE)
with two independently controlled analog data channels, each channel with two identical andindependently controlled equalization stages. The DC-gain in the equalization stages isautomatically adjusted to 0dB. The DC-gain of the Output Buffer (OB) can be externallyadjusted.
The first channel of the ADE features a built-in Error Detector (ED) that generates an outputsignal proportional to the absolute value of the difference between a recovered signal and anideal signal. The ED can be turned off to save power.
The part’s I/Os support CML-type differential interface with on-chip 50Ohm termination to vcc.
External 50Ohm termination is also required. AC-coupling for both analog data channels isrequired.
All operational modes of the chip are controlled through a high-speed 3-wire serial interface (see3-Wire Interface Control Block).
The part operates with a positive supply vcc = +3.3V for the analog section, and a digital supply
vdd = +1.3V for the SPI interface. The negative supply rail vee should be connected to externalground.

Rev.1.1.2

2January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

AC Gain

Equalization Stages

Gain, dB

The bandwidth of the ADE at minimum and maximum equalization is shown in Fig. 2.

87654
3
2
1
0-1-2-3-4-5-6-7-8-9-10
110Frequency, GHzFig. 2. ADE Bandwidth at Minimum Equalization (Blue) and Maximum Equalization (Red)MinPeaking

MaxPeaking

Poly. (MaxPeaking)

Poly. (MinPeaking)Total peaking of two equalization stages is shown in Fig. 3.
1098Peaking, dB765432220Frequency, GHz

Fig. 3. Maximum Peaking of Two Equalization Stages

Rev.1.1.2

3January 2020

AverPea

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

3-Wire Interface Control Block
The interface supports high clock frequencies. The total reconfiguration time does not exceed
140ns from the external assignment of new control signals to the final settling of the internal
controlled blocks.
The bit map of the interface is shown in Table 1
Table 1. 3-Wire Interface Bit Map

Byte # Bit # Bit order Signal nameSignal function
From 1LSB
1e1ch1Channel 1 Stage 1 EQ control
to 8MSB
From 1LSB
2e2ch1Channel 1 Stage 2 EQ control
to 8MSB
From 1LSB3
e1ch2Channel 2 Stage 1 EQ control
to 8MSB
From 1LSB
4e2ch2Channel 2 Stage 2 EQ control
to 8MSB
From 1LSB5
delError Detector delay control
to 8MSB
1MSB
on_fb
Feedback switch: “1” – on, “0” - off
6
From 2LSBamp
Output Buffer gain control
to 8 2nd MSB
1MSB
on_edError Detector switch: “1” – on, “0” - off
7
From 2LSB
eda
Error Detector gain control
to 8 2nd MSB

Rev.1.1.2

4January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

TERMINAL FUNCTIONSTERMINAL
Name No.
Typed1pd1nd2pd2nq1pq1nq2pq2nDescription

High-Speed I/Os
CML-type Differential high-speed channel 1 data inputs
AnalogInputs Differential high-speed channel 2 data inputs

46810
43 CML-type Differential high-speed channel 1 data outputs
41 Analog
17 Outputs Differential high-speed channel 2 data outputs
15
Low-Speed I/Os
3wenin 26
1.2V
Enable input signal for 3-wire interface
CMOS
3wcin 28
Clock input signal for 3-wire interface
Inputs Data input signal for 3-wire interface
3wdin 30
3wdout 32
1.2V
Data output signal for 3-wire interface
CMOS
Outputerrdet 19
CMOS Error Detector output voltage
Output Error detector limited signal amplitude indicator
amplim 37
ampd 39
Error detector linear signal amplitude indicator
limadj 21 CMOS I/O Error detector limiting voltage swing adjustment

Name
vddveevcc

Supply And Termination Voltages
Description
Pin Number+1.2V positive power supply
24
Negative pin to vee
Ground2, 13, 35+3.3V positive power supply
1, 3, 5, 7, 9, 11, 12, 14, 16, 18, 20, 22, 23,
Negative pin to vee
25, 27, 29, 31, 33, 34, 36, 38, 40, 42, 44

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 2 may cause damage to thisproduct and/or lead to reduced reliability. Functional performance is specified over therecommended operating conditions for power supply and temperature only. AC and DC device
characteristics at or beyond the absolute maximum ratings are not assumed or implied. All minand max voltage limits are referenced to ground (assumed vee).
Rev.1.1.2

5January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Table 2. Absolute Maximum Ratings

Parameter
Digital Supply Voltage (vdd)
Analog Supply Voltage (vcc)
Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max
1.5
3.6
1.6
1.0+90+10098
98

Units
VVW
VºC
ºC%%

ELECTRICAL CHARACTERISTICSPARAMETER
vee
vdd
vcc
Ivdd
Ivcc
Power Consumption
Junction temperature
Data Rate
SE Swing
CM LevelRate
SE Swing
CM LevelMax. Swing
Clock frequency
Low logic level
High logic levely

MIN

TYP MAX UNIT
COMMENTS
General Parameters
0.0V
External ground
1.2
1.4Vvdd pin to vee
3.1
3.3
3.5Vvcc pin to vee~0mA
Depending on the state of
the Error Detector (on or300
410mAoff)
1.0
1.4
W
050
100°C
Data input (d1p/d1n, d2p/d2n)
828
Gb/s
220
mV
Peak-to-peak
N/A
Only AC-coupled allowed
Data output (q1p/q1n, q2p/q2n)828Gb/s
220mV
Peak-to-peak
TBDV
Depends on the amplitude
Error Detector output (errdet)
1V
Adjustable via 3-w interface
3-Wire Interface Port
50MHz0V
1.2
VPACKAGE INFORMATIONThe chip die is housed in a custom, 44-pin CQFP package shown in Fig. 4. The package provides
a center heat slug located on its back side to be used for heat dissipation. ADSANTEC
recommends for this section to be soldered to the vcc plain, which is ground for a negative
supply, or power for a positive supply.
Rev.1.1.2

6January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

The part’s identification label is ASNT6152-KMM. The first 8 characters of the name before thedash identify the bare die including general circuit family, fabrication technology, specific circuit
type, and part version while the 3 digits after the underscore represent the package’s
manufacturer, type, and pin out count.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for
all ten substances.

Fig. 4. Package Drawing

Rev.1.1.2

7January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.1.2
1.0.2
1.0.1
0.1.1

Date01-2020
07-2019
01-201708-2016

0.0.1

06-2016

Rev.1.1.2

Changes
Updated Package Information
Updated LetterheadFirst release
Added pin out diagram
Corrected description
Corrected Terminal Functions table
Added 3-wire interface speed to Electrical Characteristics
Preliminary release

8January 2020