Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT8131-PQC
32GHz High-Sensitivity Divider by 2 and by 4vcc

vee

vcc

vee

vcc

vee

cn

vcc

vcc

c4p

ASNT8131cpvcc

1veevccvcc

c2p

veevcc

c4n

c2n

vcc

vcc
Rev. 1.1.2vcc

Wide frequency range from DC to 32GHz
Divided-by-2 and divided-by-4 outputs
50% duty cycle of the divided clock signals
Fully differential CML input interface
Fully differential CML output interfaces
Single +3.3V or -3.3V power supply
Industrial temperature range
Power consumption of 317mW at full operational speed
Standard MLF/QFN 24-pin packagevee

July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
5050

cpc4pcnc4n505050

c2pc2n50

Fig. 1. Functional Block Diagram

ASNT8131-PQC is a high-speed, low-power divider by-2 and by-4 with increased sensitivity. The partshown in Fig. 1 accepts a CML input clock signal (cp/cn) with the speed from DC to maximum
operational frequency and provides clean 50% duty cycle output signals with divided-by-2 (c2p/c2n) anddivided-by-4 (c4p/c4n) frequency. The part’s I/Os support the CML logic interface with on chip 50Ohm
termination to vcc and may be used differentially, AC/DC coupled, single-ended, or in any combination(see also POWER SUPPLY CONFIGURATION).

POWER SUPPLY CONFIGURATION
The part can operate with either negative supply (vcc = 0.0V =ground and vee = -3.3V), or positivesupply (vcc = +3.3V and vee = 0.0V = ground). In case of the positive supply, all I/Os need AC
termination when connected to any devices with 50Ohm termination to ground. Different PCB layouts
will be needed for each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vcc).
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity
Rev. 1.1.2

Min-4010102

Max-3.60.35
1.0+90+1009898UnitsVW
V°C°C%%July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

TERMINAL FUNCTIONSTERMINAL
Name
No.
TypeDESCRIPTION

High-Speed I/Os
CML Differential clock input with internal SE 50Ohm termination toinput vcc.
CML Differential divided clock outputs. Require external SE 50Ohmoutput termination to vcc.

cpcnc2pc2nc4pc4n222042108NamevccveeSupply and Termination Voltages
Description
Pin Number
Positive power supply. (+3.3V or 0V)
1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23
Negative power supply. (0V or -3.3V)
6, 12, 14, 16, 18, 24

ELECTRICAL CHARACTERISTICSPARAMETERTYPMAX UNITCOMMENTS
General Parameters
vee
-3.1
-3.3
-3.5
V
±6%
vcc
0.0V
External ground
Ivee
95mA
Power consumption
317mW
Junction temperature -25
50125°C
HS Input Clock (cp, cn)
Frequency
032 GHz
Swing
40800mV
Differential or SE, p-p
CM Voltage Levelvcc-0.8 vcc-0.2 vcc mV Must match for both inputs
Output Divided Clock (c2p, c2n, c4p, c4n)Frequency f/2016GHzFor c2 out signal
Frequency f/408
GHzFor c4 out signal
Diff. Swing
570
600630mV
Peak-to-peak
CM Levelvcc-(Diff. swing)/4V
Duty cycle
455055%Additive Jitter
TBD
ps
Peak-to-peak

Rev. 1.1.2

MIN

3

July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATIONThe chip die is housed in a standard 24-pin QFN package shown in Fig. 2. It is recommended that thecenter heat slug located on the back side of the package is soldered to ground to help dissipate heatgenerated by the chip during operation.
The part’s identification label is ASNT8131-PQC. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per EU 2002/95/EC for all sixsubstances.

ASNT8131
Fig. 2. QFN 24-Pin Package Drawing (All Dimensions in mm)

Rev. 1.1.2

4July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.1.2
1.1.1

Date
07-2019
01-2013

1.0.101-2013

Rev. 1.1.2

Changes
Updated Letterhead
Correction: output Diff Swing instead of SE
Format correction
First release

5July 2019