Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT5113-KMC
DC-32Gbps High Sensitivity D-Type Flip-Flop

Input data single-ended common mode controlsExhibits low jitter and limited temperature variation over industrial temperature range



4ps set-up/hold time capability

88% clock phase margin for retiming of data input eyeFully differential CML input interfaces

Fully differential CML output interface with 400mV single-ended swingSingle +3.3V or -3.3V power supplyPower consumption: 510mW

Fabricated in SiGe for high performance, yield, and reliability

Custom CQFP 24-pin packageveeSensitive input data buffer with increased CM range that is ideal for sampling applicationsvcc

dcinpAdditional input buffer / level shifter for improved protectionvcc

dcinnHigh speed broadband D-Type Flip-Flop for data retiming with full rate clock

vcc

vee

vcc

vcc

dp

qp

ASNT5113
ASNT6124-KMC

vcc

vcc

dnqnvccvcc

Rev. 1.3.2

1vcc

cnvcc

cp

vcc

veeveeJuly 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
vcc

vcc

dcinp

83

125

50

DFF
core

dp
dn
125
dcinn

qp
qn

83

50

vcc

50

vcc

50

vcc

cp
cn

vcc

Fig. 1. Functional Block Diagram

The temperature stable ASNT5113-KMC SiGe IC provides broadband data retiming functionality and isintended for use in high-speed measurement / test equipment. The IC shown in Fig. 1 can sample a highspeed data signal dp/dn with a full-rate external clock cp/cn to create a full-rate retimed NRZ data output
qp/qn.
The data input buffer is designed to have increased input signal sensitivity, and is able to operate over a
wider range of input common mode (CM) voltages. The actual common mode voltage levels at data
inputs dp/dn can be adjusted by applying voltages between vee and vcc to the corresponding control
inputs dcinp/dcinn. The part’s I/O’s support the CML logic interface with on chip 50Ohm termination tovcc and may be used differentially, AC/DC coupled, single-ended, or in any combination (see alsoPOWER SUPPLY CONFIGURATION). In the DC-coupling mode, the input signal’s common mode
voltage should comply with the specifications shown in ELECTRICAL CHARACTERISTICS. In theAC-coupling mode, the input termination provides the required common mode voltage automatically. The
differential DC signaling mode is recommended for optimal performance.
It should be noted that the control inputs dcinp/dcinn should be always connected to voltage sources toensure correct 50Ohm terminations for the data inputs.

POWER SUPPLY CONFIGURATIONThe part can operate with either a negative supply (vcc = 0.0V = ground and vee = −3.3V), or a positivesupply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os need AC termination
when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be neededfor each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.

Rev. 1.3.2

2July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vcc).
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
Input Data Voltage Swing (SE)Input Clk Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010

Max-3.6
0.56
1.7
1.7
+90
+1009898

Units
VW
VV
ºC
ºC
%%

TERMINAL FUNCTIONSTERMINAL
Name No.
Typedp
dn
cp
cn
qp
qn
dcinp
dcinn
Namevccvee

Rev. 1.3.2

DESCRIPTION

High-Speed I/Os21
CML Differential data inputs with internal SE 50Ohm termination
Input to vcc
23
3CML Differential clock inputs with internal SE 50Ohm termination
Input to vcc
511
CML Differential data outputs with internal SE 50Ohm termination
Output to vcc. Require external SE 50Ohm termination to vcc
9DC Controls
15
Input Input data DC common mode voltage level controls. Shouldbe always connected to voltage sources!
17
Supply and Termination Voltages
Description
Pin Number
Positive power supply
2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24(+3.3V or 0V)
Negative power supply
1, 7, 13, 19(0V or -3.3V)

3July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERMIN

TYP MAXUNIT
COMMENTS
General Parameters
0.0
V
External groundvcc-3.1-3.3-3.5
V±6%veeIvcc
155165mA
Power consumption
510545mW
Junction temperature-25
50125°C
HS Input Data (dp/dn)
Data rate
DC3240Gbps
Swing
0.011.3V
Differential or SE, p-p
CM Voltage Level
vcc-0.7+sw/2 vcc+0.6-sw/2
VMust match for both inputs
HS Input Clock (cp/cn)
Frequency
DC
3240GHzSwing
0.05
1.3
V
Differential or SE, p-p
CM Voltage Level
vcc-0.7+sw/2 vcc+0.6-sw/2
VMust match for both inputs
Duty Cycle
405060%
Clock Phase Margin
868890%
For reliable data latching at full rate
Setup/Hold Times
2.75/1.0
ps
For reliable data latching
HS Output Data (qp/qn)
Data rate
DC
3240Gbps
Logic “1” levelvcc-0.05 vcc-0.03 vcc-0.01VLogic “0” levelvcc-0.46 vcc-0.44 vcc-0.42
VWith external 50Ohm DC termination
Jitter0.15
ps
Peak-to-peak at 32Gbps
DC Input Controls (dcinp/dcinn)
Max level
vcc + 1.0
VMin levelvcc - 1.0
V

PACKAGE INFORMATIONThe chip die is housed in a custom 24-pin CQFP package shown in Fig. 2. The package provides a center
heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for thissection to be soldered to the vcc plain, which is ground for a negative supply, or power for a positive
supply.
The part’s identification label is ASNT5113-KMC. The first 8 characters of the name before theunderscore identify the bare die including general circuit family, fabrication technology, specific circuit
type, and part version while the 3 characters after the underscore represent the package’s manufacturer,type, and pin out count.
This device complies with the Restriction of Hazardous Substances (RoHS) per EU 2002/95/EC for all six
substances.

Rev. 1.3.2

4July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Fig. 2. CQFP 24-Pin Package Drawing (All Dimensions in mm)

Rev. 1.3.2

5July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.3.2
1.3.1
1.2.1
1.1.1

Date
07-2019
07-2015
07-2015
06-2013

1.0.1

02-2013

Rev. 1.3.2

Changes
Updated Letterhead
Revised package information section
Inserted setup and hold times (identical to clock phase margin)
Corrected pin out diagram
Removed data duty cycle specification
First release

6July 2019