OIF-400ZR-01.0

Implementation Agreement 400ZR

OIF-400ZR-01.0

March 10, 2020

Implementation Agreement created and approved
OIF
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OIF-400ZR-01.0
The OIF is an international non-profit organization with over 100 member companies, including the world’s
leading carriers and vendors. Being an industry group uniting representatives of the data and optical worlds,
OIF’s purpose is to accelerate the deployment of interoperable, cost-effective and robust optical internetworks
and their associated technologies. Optical internetworks are data networks composed of routers and dataswitches interconnected by optical networking elements.
With the goal of promoting worldwide compatibility of optical internetworking products, the OIF actively
supports and extends the work of national and international standards bodies. Working relationships or formal
liaisons have been established with CFP-MSA, COBO, EA, ETSI NFV, IEEE 802.3, IETF, INCITS T11, ITU SG-15, MEF,
ONF.

For additional information contact:
OIF
5177 Brandin Ct, Fremont, CA 94538
510-492-4040  info@oiforum.com
www.oiforum.com

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OIF-400ZR-01.0
Working Group:

TITLE:SOURCE:

Physical and Link Layer (PLL) Working Group

Implementation Agreement 400ZRTECHNICAL EDITOR

WORKING GROUP CHAIR
OPTICAL CHAIR

Mike A. Sluyski
Acacia Communications Inc.
3 Mill and Main
Maynard, MA 01754, USA
Phone: +1.978.938-4896 x2773
Email: msluyski@acacia-inc.com

David R. Stauffer, Ph D.
Kandou Bus, SA
QI-I
1015 Lausanne, Switzerland
Phone: +1.802.316.0808
Email: david@kandou.com

WORKING GROUP CHAIR
OPTICAL VICE CHAIR
Karl Gass
Phone: +1.505.301.1511
Email: iamthedonutking@mac.com

ABSTRACT: Implementation Agreement created and approved by the Optical Internetworking Forum for a 400ZR
Coherent Optical interface. The project start was approved at the Q3 Technical Meeting, October 2016 (San Jose
CA, USA). OIF2016.400.04 is the original project start document for this project

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OIF-400ZR-01.0

Notice: This Technical Document has been created by the Optical Internetworking Forum (OIF). This document is offered to the OIF
Membership solely as a basis for agreement and is not a binding proposal on the companies listed as resources above. The OIF reserves therights to at any time to add, amend, or withdraw statements contained herein. Nothing in this document is in any way binding on the OIF or anyof its members.
The user's attention is called to the possibility that implementation of the OIF implementation agreement contained herein may require the useof inventions covered by the patent rights held by third parties. By publication of this OIF implementation agreement, the OIF makes norepresentation or warranty whatsoever, whether expressed or implied, that implementation of the specification will not infringe any third party
rights, nor does the OIF make any representation or warranty whatsoever, whether expressed or implied, with respect to any claim that has
been or may be asserted by any third party, the validity of any patent rights related to any such claim, or the extent to which a license to use
any such rights may or may not be available or the terms hereof.
Copyright © 2020 Optical Internetworking Forum
This document and translations of it may be copied and furnished to others, and derivative works that comment on or otherwise explain it orassist in its implementation may be prepared, copied, published and distributed, in whole or in part, without restriction other than thefollowing, (1) the above copyright notice and this paragraph must be included on all such copies and derivative works, and (2) this document
itself may not be modified in any way, such as by removing the copyright notice or references to the OIF, except as needed for the purpose ofdeveloping OIF Implementation Agreements.
By downloading, copying, or using this document in any manner, the user consents to the terms and conditions of this notice. Unless the terms
and conditions of this notice are breached by the user, the limited permissions granted above are perpetual and will not be revoked by the OIF
or its successors or assigns.
This document and the information contained herein is provided on an “AS IS” basis and THE OIF DISCLAIMS ALL WARRANTIES, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTY THAT THE USE OF THE INFORMATION HEREIN WILL NOT INFRINGE ANY RIGHTS OR
ANY IMPLIED WARRANTIES OF MERCHANTABILITY, TITLE OR FITNESS FOR A PARTICULAR PURPOSE.

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Table of Contents

1

TABLE OF CONTENTS ........................................................................................... 5

2

LIST OF FIGURES ................................................................................................... 9

3

LIST OF TABLES................................................................................................... 114

DOCUMENT REVISION HISTORY ........................................................................ 13

5

INTRODUCTION .................................................................................................... 14

6400ZR INTERFACES ............................................................................................. 15

7

8

6.1

400ZR Clocking Modes ................................................................................................................ 15

6.2

Media Interface - Black Link ........................................................................................................ 15

400ZR USE CASES ............................................................................................... 16
7.1

120 km or less, amplified, point-to-point, DWDM noise limited link ......................................... 16

7.2

Unamplified, single wavelength, loss limited link ....................................................................... 17

HOST TO 400ZR DATA PATH .............................................................................. 18
8.1

400G Host Side Interface ............................................................................................................ 19

8.2

PMA ............................................................................................................................................. 19

8.3

PCS (partial processes) ................................................................................................................ 19

8.3.1

PCS Rx direction (400ZR Tx datapath) ................................................................................. 19

8.3.2

PCS Tx direction (400ZR Rx datapath) ................................................................................. 20

8.4

400ZR frame structure ................................................................................................................ 20

8.4.1
8.5

400ZR Multi-Frame ............................................................................................................. 21

AM/PAD/OH insertion ................................................................................................................ 22

8.5.1

400ZR AM/PAD/OH Transmission order ............................................................................. 23

8.6

400ZR Alignment Markers (AM) ................................................................................................. 24

8.7

400ZR PAD................................................................................................................................... 25

8.8

400ZR OH .................................................................................................................................... 26

8.8.1

Multi-Frame Alignment Signal (MFAS)................................................................................ 26

8.8.2

Link error and Link degrade detection and marking ........................................................... 26

8.8.3

Link status monitoring and signaling (STAT) ....................................................................... 27

8.8.4

Link Degrade Indication (LDI) .............................................................................................. 28

8.8.5

Link Degrade Warning and Alarming. ................................................................................. 28

8.9

GMP mapping processes............................................................................................................. 30

8.9.1

Stuffing Locations................................................................................................................ 34

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8.9.2

GMP overhead Encoding..................................................................................................... 36

8.9.3

GMP OH – CRC8 calculation ................................................................................................ 36

8.9.4

The JC6 OH CRC4 Calculation .............................................................................................. 36

400ZR FRAME TO SC ADAPTATION ................................................................... 37
9.1

Mapping 400ZR Frame Payload to Staircase FEC Blocks ............................................................ 38

9.2

400ZR CRC+MBAS Bit Insertion Block ......................................................................................... 38

9.2.1

10

400ZR Multi Block Alignment Signal (MBAS) ...................................................................... 39

400ZR FORWARD ERROR CORRECTION (FEC)............................................. 42

10.1

SC-FEC ......................................................................................................................................... 42

10.2

Sync Pad Insertion ....................................................................................................................... 42

10.3

Frame Synchronous Scrambling .................................................................................................. 44

10.4

Convolutional Interleave ............................................................................................................. 44

10.5

Inner Hamming Code .................................................................................................................. 46

11DP-16QAM SYMBOL MAPPING AND POLARIZATION DISTRIBUTION ......... 48

11.1

12

Interleaving DP-16QAM Symbols ................................................................................................ 48

DSP FRAMING ................................................................................................... 50

12.1

First DSP sub-Frame .................................................................................................................... 50

12.1.1
12.2

FAW Sequence .................................................................................................................... 51

Subsequent DSP sub-frames. ...................................................................................................... 51

12.2.1

Training Sequence ............................................................................................................... 52

12.3

Pilot Sequence............................................................................................................................. 52

12.4

Channel Mappings ...................................................................................................................... 54

12.5

Frame Expansion Rate................................................................................................................. 55

13

OPTICAL SPECIFICATIONS.............................................................................. 57

13.1

400ZR, DWDM amplified - Application Code (0x01): .................................................................. 57

13.1.1

Optical channel specifications – Black Link ......................................................................... 57

13.1.2

Transmitter Optical Specifications ...................................................................................... 59

13.1.3

Receiver Optical Specifications ........................................................................................... 66

13.1.4Module Requirements Tx - (Informative) ........................................................................... 68

13.1.5Module Requirements Rx - (Informative) ........................................................................... 69

13.2

400ZR, Single wavelength, Unamplified - Application Code (0x02):........................................... 70

13.2.1

Optical channel specifications ............................................................................................ 70

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13.2.2

Transmitter Optical Specifications ...................................................................................... 71

13.2.3

Receiver Optical Specifications ........................................................................................... 77

13.2.4Module Requirements Tx - (Informative) ........................................................................... 78

13.2.5Module Requirements Rx - (Informative) ........................................................................... 79

13.3

Optical Parameter Definitions .................................................................................................... 80

13.3.1The Receiver Optical Signal-to-noise Ratio Tolerance ........................................................ 80

13.3.2

Spectral excursion ............................................................................................................... 80

13.3.3Out-of-Band OSNR (OOB OSNR) ......................................................................................... 80

13.3.4

Ripple .................................................................................................................................. 80

13.3.5

Optical return loss at SS ....................................................................................................... 80

13.3.6Discrete reflectance between SS and RS .............................................................................. 81

13.3.7

Differential Group Delay (DGD) .......................................................................................... 81

13.3.8Polarization Dependent Loss (PDL) ..................................................................................... 81

13.3.9Polarization rotation speed................................................................................................. 81

13.3.10

Inter-channel crosstalk.................................................................................................... 81

13.3.11

Interferometric crosstalk ................................................................................................ 81

14

INTEROPERABILITY TEST METHODOLOGY, DEFINITIONS ......................... 82

14.1

400ZR Test Features .................................................................................................................... 82

14.2

Loopback features, Test Generators and Checkers .................................................................... 82

14.2.1Loopbacks ........................................................................................................................... 84

14.2.2

Test Generators/Checkers .................................................................................................. 85

14.3

Interoperability Test Vectors ...................................................................................................... 85

14.3.1

EVM PRBS ............................................................................................................................ 85

14.3.2TV PRBS ............................................................................................................................... 86

14.3.3

GMP PCS test vectors .......................................................................................................... 86

14.3.1

PCS test vectors................................................................................................................... 87

14.3.1

Media loop testing .............................................................................................................. 88

15

OPERATING FREQUENCY CHANNEL DEFINITIONS...................................... 89

15.1

Normative 48 x 100 GHz DWDM Application Channels.............................................................. 89

15.2

Optional 64 x 75 GHz DWDM Application Channels ................................................................... 89

15.3

Optional Flexible DWDM Grid..................................................................................................... 90

15.3.1

Example 100GHz Flexible Grid Offset ................................................................................. 91

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15.3.2

Example 75GHz Flexible Grid Offset ................................................................................... 91

15.3.3

Flexible Grid Provisioning.................................................................................................... 91

16

SUMMARY .......................................................................................................... 92

17

REFERENCES .................................................................................................... 93

17.1

Normative references ................................................................................................................. 93

17.2

Informative references ............................................................................................................... 93

18

APPENDIX A: GLOSSARY ................................................................................ 94

19

APPENDIX B: FUTURE WORK ITEMS.............................................................. 95

20

APPENDIX C: ERROR VECTOR MAGNITUDE ................................................. 96

20.1

Maximum error vector magnitude ............................................................................................. 96

20.2

Maximum I-Q DC offset .............................................................................................................. 96

20.3

Reference receiver for EVM and I-Q DC offset ........................................................................... 96

20.3.1

Hardware characteristics: ................................................................................................... 96

20.3.2

Processing steps: ................................................................................................................. 96

20.4

EVM evaluation ........................................................................................................................... 97

20.5

Reference Algorithms for EVM Test of 400ZR transmitters. ...................................................... 98

21
APPENDIX D: LIST OF COMPANIES BELONGING TO OIF WHEN DOCUMENTIS APPROVED .............................................................................................................. 99

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List of Figures

Figure 1: 400ZR reference diagram............................................................................................................. 14
Figure 2: Transceiver line card with 400ZR amplified point-to-point interface.......................................... 16
Figure 3: Router switch line card with 400ZR DWDM Interfaces ............................................................... 16
Figure 4: Transceiver line card with 400ZR DWDM interfaces ................................................................... 16
Figure 5: Router/Switch line card with 400ZR unamplified point-to-point Interface................................. 17
Figure 6: Data path detail ........................................................................................................................... 18
Figure 7: 400ZR frame structure without parity bits .................................................................................. 20
Figure 8: 400ZR multi-frame structure with parity bits .............................................................................. 21
Figure 9: 400ZR Frame overhead ................................................................................................................ 22
Figure 10: 400ZR overhead ......................................................................................................................... 23
Figure 11: Alignment Marker transmission order – 10b interleaved ......................................................... 24
Figure 12: Alignment Marker format .......................................................................................................... 24
Figure 13: PAD transmission order – 10b interleaved ................................................................................ 25
Figure 14: Over Head transmission order – 10b interleaved ...................................................................... 26
Figure 15: STAT Over Head byte definitions ............................................................................................... 27
Figure 16: Local/Remote Degrade interworking between Switch/Router and 400ZR transceiver ............ 27
Figure 17: Error marking ............................................................................................................................. 30
Figure 18: GMP mapping/de-mapping process .......................................................................................... 31
Figure 19: GMP mapping over four 400ZR frames with Cm=10216 ............................................................ 35
Figure 20: 400ZR frame to SC-FEC relationship .......................................................................................... 37
Figure 21: CRC32 + MBAS ........................................................................................................................... 39
Figure 22: Multi-block alignment signal overhead ..................................................................................... 39
Figure 23: CRC32 + MBAS transmission order ............................................................................................ 40
Figure 24: 400ZR frame adaptation SC FEC block ....................................................................................... 41
Figure 25: 400ZR HD-FEC processes............................................................................................................ 42
Figure 26: Pad insertion/removal ............................................................................................................... 42
Figure 27: 6 × 119 Pad Insertion ................................................................................................................. 43
Figure 28: Frame synchronous scrambler ................................................................................................... 44
Figure 29: Convolution interleave............................................................................................................... 44
Figure 30: Convolution interleave............................................................................................................... 45
Figure 31: Hamming FEC frame format ...................................................................................................... 46
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Figure 32: Hamming code ........................................................................................................................... 46
Figure 33: Hamming code 8-way interleave ............................................................................................... 49
Figure 34: First DSP sub-frame of super-frame .......................................................................................... 50
Figure 35: DSP sub-frames 2-49 of the DSP super-frame ........................................................................... 51
Figure 36: QPSK mapped Pilot Sequence .................................................................................................... 52
Figure 37: Pilot seed and sequence ............................................................................................................ 53
Figure 38: 400ZR expansion rates ............................................................................................................... 55
Figure 39: 400ZR test features .................................................................................................................... 83
Figure 40: Test vector PRBS31 generator ................................................................................................... 86
Figure 41: Test vector detail ....................................................................................................................... 88
Figure 42: Flexible grid provisioning example ............................................................................................ 90

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3

List of Tables

Table 1: 400ZR IA document revision history ............................................................................................. 13
Table 2: 400ZR host interface ..................................................................................................................... 15
Table 3: 400ZR Alignment Marker encodings ............................................................................................. 25
Table 4: Replacement signal ...................................................................................................................... 26
Table 5: Host interface and its GMP parameter values .............................................................................. 31
Table 6: GMP parameter values ................................................................................................................. 33
Table 7: GMP stuff locations of 400ZR ....................................................................................................... 34
Table 8: In-phase (I) and quadrature phase (Q) symbol amplitude ............................................................ 48
Table 9: FAW sequence............................................................................................................................... 51
Table 10: Training symbol sequence........................................................................................................... 52
Table 11: Pilot polynomial and seed ........................................................................................................... 53
Table 12: Pilot Sequence ............................................................................................................................. 54
Table 13: Channel mappings ....................................................................................................................... 55
Table 14: 400ZR expansion rate table......................................................................................................... 56
Table 15: 400ZR application codes ............................................................................................................. 57
Table 16: Optical channel specifications..................................................................................................... 58
Table 17: Tx optical specifications .............................................................................................................. 65
Table 18: Rx optical specifications .............................................................................................................. 67
Table 19: 400ZR module – Tx specifications ............................................................................................... 68
Table 20: 400ZR module – Rx specifications ............................................................................................... 69
Table 21: Optical channel specifications..................................................................................................... 70
Table 22: Tx Optical specifications .............................................................................................................. 76
Table 23: Rx Optical specifications.............................................................................................................. 77
Table 24: 400ZR module – Tx specifications ............................................................................................... 78
Table 25: 400ZR module – Rx specifications ............................................................................................... 79
Table 26: Loopbacks.................................................................................................................................... 84
Table 27: Test generator/checker descriptions .......................................................................................... 85
Table 28: Test vector PRBS files .................................................................................................................. 86
Table 29: GMP PCS test vector files ............................................................................................................ 87
Table 30: 100GHz channel spacing ............................................................................................................. 89
Table 31: 75GHz channel spacing ............................................................................................................... 89
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Table 32: Example 100GHz flexible grid...................................................................................................... 91
Table 33: Example 75GHz flexible grid........................................................................................................ 91
Table 34: Acronyms..................................................................................................................................... 94
Table 35: EVM algorithms ........................................................................................................................... 98

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4Document Revision History

Table 1 provides the 400ZR Implementation Agreement revision history.

Document
OIF-400ZR-01.0

Date
March 10, 2020

Revisions/Comments
Initial release

Table 1: 400ZR IA document revision history

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5Introduction

This Implementation Agreement (IA) specifies a Digital Coherent 400ZR interface for two applications:••

120 km or less, amplified, point-to-point, DWDM noise limited links.
Unamplified, single wavelength, loss limited links.

The IA aims to enable interoperable, cost-effective, 400Gb/s implementations based on single-carrier
coherent DP-16QAM modulation, low power DSP supporting absolute (Non-Differential) phase
encoding/decoding, and a Concatenated FEC (C-FEC) with a post-FEC error floor <1.0E-15. 400ZR operates
as a 400GBASE-R PHY.
Figure 1 shows the scope of this IA.

Timing and Code Word Transparent Transport of Ethernet signal, including FlexE and SyncE
Single Channel line
interface with +/-20ppm

Ethernet Interface
with +/-100ppm

400ZR Module
400ZR
DSP

HOST

1x400GAUI-8

Single Channel line
interface with +/-20ppm

OpticsRs

400ZR Module

Rs

Ss
Black Link
80 km

Ethernet Interface
with +/-100ppm

OpticsSs

400ZR link

400ZR
DSP

HOST

1x400GAUI-8

Figure 1: 400ZR reference diagram
No restriction on the physical form factor is implied by this IA (QSFP-DD, OSFP, COBO, CFP2, CFP8), but
the specifications target a pluggable DCO architecture with port densities equivalent to grey client optics.
400ZR builds upon the work of other standards bodies including IEEE 802.3TM-2018 and ITU-T SG-15.

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OIF-400ZR-01.0

6400ZR interfaces

The 400ZR IA supports the following host interface functions.

Host protocol support

SublayerIEEE Std 802.3™-2018
400GBASE-R

Capabilities

PCS

FEC coding RS(544,514), lane distribution, AM lockand deskew, per clause 119.1, Extender sublayer.

PMA

Mux’ing, clock and data recovery, clock generation,
modulation.

AUI

Optionally physically instantiated as 400GAUI-8 C2M;
8 x CEI-56G-VSR PAM-4.

Table 2: 400ZR host interface
This IA does NOT define support of other host interfaces, nor the aggregation of multiple host interfaces.
This IA, however, should not limit the ability to extend the host interfaces in the future.

6.1

400ZR Clocking Modes

The 400ZR data path is mapped asynchronously using a local clock reference. Simplified GMP mappingper ITU-T G.709.1 Annex D is used to rate-adapt the payload to the local reference, supporting data andtiming transparency. The local clock tolerance is +/- 20ppm.
For timing transparent applications digital phase-interpolation is used to recover the timing informationfrom the GMP mapped Cm bytes.

6.2

Media Interface - Black Link

400ZR provides timing and codeword transparent transmission of a 400GBASE-R interface. 400ZR uses a"black link" approach, to define the optical interface parameters for a (single-channel) optical tributary as
shown in Figure 1.
The black link may contain neighboring channels and optical amplifiers in the optical path. Black linkspecifications are provided in Sections 13.1.1 and 13.2.1. The black link methodology enables longitudinalmode compatibility at the single-channel points (Ss, Rs), however, it does not enable longitudinal modecompatibility at multichannel points.

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7400ZR use cases

400ZR is intended for the use cases summarized here. The different 400ZR use cases can be addressedwith different 400ZR DCO module implementations.

7.1

120 km or less, amplified, point-to-point, DWDM noise limited link

There are 3 use cases of amplified point-to-point links (no OADM) identified for 400ZR in Figure 2 throughFigure 4. For amplified links the reach is dependent on the OSNR at the receiver (noise limited). The 400ZR
targeted reach for these applications is 80km or more. These use cases are covered by Application Code0x01 in this IA.

Figure 2: Transceiver line card with 400ZR amplified point-to-point interface

Figure 3: Router switch line card with 400ZR DWDM Interfaces

Figure 4: Transceiver line card with 400ZR DWDM interfaces

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7.2

Unamplified, single wavelength, loss limited link

For an unamplified link as shown in Figure 5, the reach is dependent on the transmit output power, input
receive sensitivity, and the channel’s loss characteristics. This use case is covered by Application Code0x02 in this IA.

Figure 5: Router/Switch line card with 400ZR unamplified point-to-point Interface

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8

Host to 400ZR data path

Figure 6 shows the functional blocks in the Tx and Rx data path.
400GBASE-R
8

8

PMA sublayer(*)

(*)

16

16

per IEEE Std.
-

Alignment lock and lane
deskew
Lane reorder and deinterleave

Distribution & Interleave

FEC Decode

FEC Encode

RS-FEC
detected Local
DegradeRx Client
FEC
Degradesignaling

rx_am_sf<2:0>

PHY 400GXS
Post-FEC Interleave

Pre-FEC Distribution

Alignment Removal

Alignment Insertion

Descramble

Tx Client
FEC
Degradesignaling

Scramble

256b/257b blocks

256b/257b blocks
400GAUI-8

256b/257b Transcode

Reverse Transcode
Decode &Error Marking

tx_am_sf<2:0>

No ratematching

No ratematching

PMA

EncodePHY 400GXS

400GMII*

EncodeNo ratematching

No ratematching

256b/257b transcode

GMP Mapping(4*257b stuffing)

tx_oh_sf<2:0>

Reverse transcode
System-side CLOCK DOMAIN(+/- 100 ppm)

256b/257b blocks

Line-Side CLOCK DOMAIN(+/- 20 ppm)

256b/257b blocks

AM/OH detect & removal(20*257b)

CRC-32 Calculation

CRC-32 checking

PCS (ZR)

SC-FEC Adapt, ED &Decoding

Pad Insertion

Pad removal(6*119b)(6*119b)

Scramble

Descramble

Convolution interleaving

Convolution deinterleaving

128b/119b SD-FEC
Hamming encode

128b/119b SD-FEC
Hamming decode

Gray mapping, symbolInterleaving, Pol distribution

Pol combining & Symbol
de-interleaving

2

MEDIUM
rx_oh_sf<2:0>

SC-FEC
detected
Local
Degrade

400ZR*Logical Equivalent Implementaion. The rate matching functions shall bedisabled to/from the 400GMII interface in both directions. No Idle deletion/
insertion shall be performed.

2

Align C-FEC &FAW/TS removal

FAW & TS Insertion
2

2

Pilot removal

Pilot Insertion
2

TX DSPPHY 400ZR

MDI

GMP de-mapping(4*257b de-stuffing)

OH/AM insertion(20*257b)

SC-FEC Adapt, ED &encoding

PCS
PMA
PMD

Decode &Error Marking

2

PMA (ZR)DACRX DSPADC

PMD (ZR)
Photonic Interface

Photonic Interface

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8.1

400G Host Side Interface

The 400GbE data enters the transceiver using the 400GBASE-R PMA sublayer, where the electricalinterface, for example, may be 400GAUI-8 C2M. The characteristic information of the adapted andmapped 400GBASE-R host interface signal consists of a scrambled sequence of 256b/257b encoded blocks
with a nominal bit-rate of 425 000 000 kbit/s, 100 ppm.
NOTE – 425 000 000 kbit/s is the nominal bit-rate of the aggregate 400GBASE-R PCS signal consisting of
16 PCS lanes with 256b/257b encoding and FEC at the PMA service interface.

8.2

PMA

The PMA provides a medium-independent means for the PCS to support the use of a range of physicalmedia. The 400GBASE-R PMA performs the mapping of transmit and receive data streams between the
PCS and PMA via the PMA service interface, and the mapping and multiplexing of transmit and receive
data streams between the PMA and PMD via the PMD service interface. In addition, the PMA performs
retiming of the received data stream when appropriate. The 400GBASE-R PMA service interface is definedin IEEE Std-2018 Clause 120.3 as an instance of the inter-sublayer service interface definition inclause 116.3.

8.3

PCS (partial processes)

The 400ZR application implements only a portion of the full PCS processes defined in IEEE Std
2018 clause 119.

-8.3.1 PCS Rx direction (400ZR Tx datapath)
The 400GBASE-R PCS Rx direction (400ZR Tx data path) is defined for 400ZR to include the following
services:• Alignment lock and lane de-skew (reference IEEE Std-2018 119.2.5.1).
• Lane reorder and de-interleave (reference IEEE Std-2018 119.2.5.2).
• Reed-Solomon FEC decoding the 257-bit blocks and signaling of RS-FEC (544,514) detected local
degrade (Reference IEEE Std-2018 119.2.5.3).
• Post FEC interleave (Reference IEEE Std-2018 119.2.5.4).
• Alignment Marker removal and signaling of Alignment Marker Signal Fail (rx_am_sf<2:0>).
Reference IEEE Std-2018 119.2.5.5.
• Descramble (Reference IEEE Std-2018 119.2.5.5).
• Error Marking – Signaling Tx link degrade (Reference ITU-T G.709/Y.1331 Amendment 2(06/2018) Annex K and Section 8.8.4).
The RS-FEC decoder may provide the option to perform error detection without error correction to reduce
the latency contributed by the RS-FEC sublayer.

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8.3.2 PCS Tx direction (400ZR Rx datapath)
The 400GBASE-R PCSs Tx direction (400ZR Rx data path) defined for 400ZR include the following services:• Scramble (Reference IEEE Std-2018 Clause 119.2.4.3).
• Alignment Marker Insertion and signaling of Alignment Marker Signal Fail (tx_am_sf<2:0>).
(Reference IEEE Std-2018 Clause 119.2.4.4).
• Pre-FEC distribution (Reference IEEE Std-2018 Clause 119.2.4.5).
• Reed-Solomon FEC encoding the 257-bit blocks (reference IEEE Std-2018 Clause
119.2.4.6).
• Distribution and interleave (Reference IEEE Std-2018 Clause 119.2.4.6).
• Error Marking – Signaling Rx link degrade (Reference ITU-T G.709/Y.1331 Amendment 2(06/2018) Annex K and Section 8.8.4).

8.4

400ZR frame structure

rows
1
2
3

10280

5120
5121
5140
5141

Columns
AM

PAD

OH

1920b

1280b

Payload (5140 bits)
20b Pad

Payload (10280 bits)

.
.
.
256

3840
3841

1

1920
1921

400GBASE-R, FlexO-4-DSH, and 400ZR frames have similar structures. They are all block formats, 10280
columns×4096 rows (1×4096 or 16×256). The 400ZR frame OH area is the same as the FlexO-4-DSH,
however, fewer OH fields are defined as required for 400ZR than for FlexO-4-DSH. Bonding across multiple
PHY’s is not supported by the 4 ZR frame structure Figure 7 shows the 400ZR frame structure.

Frame

Payload area

Payload (10280 bits)

Figure 7: 400ZR frame structure without parity bits

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OIF-400ZR-01.0

8.4.1 400ZR Multi-Frame

1

10280

1

ColumnsAM

20×257b
Pad

10970

The 400ZR multi-frame structure with FEC parity field (columns 10281 to 10970) is shown in Figure 8 andcontains a frame Alignment Marker (AM) sequence every 256 rows. Columns are defined as 1-bit wide
and a frame consists of 10970 columns. This results in a bit-oriented structure. The 400ZR multi-frame canbe viewed as a binary matrix with n×256 rows of 10970 bits.

OH

Row

1
Frame

256
1

AM

Pad

OH
2

Frame

FEC
parity
256

1

AM

Pad

OH

n

Frame

256

Figure 8: 400ZR multi-frame structure with parity bits

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OIF-400ZR-01.0

8.5

AM/PAD/OH insertion

5120-bits of AM/PAD/OH, plus 20-bits of additional pad for 257b alignment, are inserted in columns 1 to
5140 of the first row of each 400ZR frame. This leaves 10220 × 257b of additional payload area in theframe. See Figure 9 below.

1

16 × 20-bit AM

1920-bit PAD

5140 payload bits = (20 × 257-bits)

10970

10280
10281

5141

5120

4 × 320-bit OH

FEC

10280 payload bits = (40 × 257 bits)

FEC

255

10280 payload bits = (40 × 257 bits)

FEC

256

10280 payload bits = (40 × 257 bits)

FEC

400ZR
Frame

2

10220 (257b payload)

rows

3840
3841

1

Columns

1920
1921

4 × 5b (20b) pad

Figure 9: 400ZR Frame overhead
The AM field is a set of 16×120-bit blocks that are 10-bit interleaved. PAD is a 1920-bit all-zeros field. The
400ZR OH consists of 4×320b blocks (1280-bits) that are 10b interleaved and transmitted immediately
after the 1920-bits of PAD. Figure 10 details the first 320-bit OH block. The remaining 3×320-bit 400ZR OH
blocks are reserved for future standardization (transmitted as all-zeros and ignored on receipt).
The required 400ZR OH fields are highlighted in black text; the optional fields, in gray text. The 400ZR OH
area includes GMP mapping control bytes (JCx Bytes). See section 8.9 for GMP processing details. The
undefined 400ZR frame OH can provide additional OAM fields, or be set to zero and ignored at the 400ZR
receiver.

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OIF-400ZR-01.0

8.5.1 400ZR AM/PAD/OH Transmission order
The 400ZR frame structure carries 514 blocks of 10-bit interleaved (5140 bits) of AM/PAD/OH + 20-bits ofadditional PAD. The transmission order for each of these fields is defined in Section 8.6 through Section
8.8 and is the same as IEEE Std-2018 and 400G FlexO.
BI TS 1120
{CM0,CM1,CM2}{CM3,CM4,CM5}

UP1{UM0 ,UM1,UM2}

UP2

Common alignment marker
Unique pad
Unique alignment marker

x16

AM

PAD

OH

1920b

1920b

1280b

10970

1

Columns
20 x 257b

rows
1
2
3

{UM3 ,UM4,UM5}

10280

CM:
UP:
UM:

UP0

20b Pad

.
.
.
256
1
2
3

Frame 1AM

PAD

FEC Parity

OH
4x320 b.
.
.

Frame 2

256
MFAS:
STAT:
JC1-JC6:
GID:
PID:
OSMC:
1

2

MFAS

STAT

MFAS

STAT

MFAS

STAT

MFAS

STAT

MFAS

STAT

MFAS

STAT

JC4

MFAS

STAT

MFAS

STAT

Reserved/Unused
PHY Member Map (RES)
Cyclic Redundancy Check (RES)
Frame Communications Channel (RES)

29

123

GID

GID

PID

MAP

CRC

FCC

OSMC

JC4

JC1

MAP

CRC

FCC

OSMC

JC5

JC2

MAP

CRC

FCC

OSMC

JC6

JC3

MAP

CRC

FCC

OSMC

MAP

CRC

FCC

OSMC

JC1

MAP

CRC

FCC

OSMC

JC5

JC2

MAP

CRC

FCC

OSMC

JC6

JC3

MAP

CRC

FCC

OSMC

GI D

RE S

RES

6 7 8
RES

RPF

RES:
MAP:
CRC:
FCC:

Link Status overhead – Carried
only in the 1st OH instance.
Reserved in instances 2
through 4.

40

RES

GMP justification overhead – Carried
only in 1st OH instance. Reserved in
Instances 2 through 4x4

GMP Cm enco din g

1

RES
RD
LD

Byte

Multi-Frame Alignment
RPF
Justification Control
Group Identification(RES)PHY member Identification(RES)
Synchronization Message (RES)

2

3

4

5

6

7

8

JC1

C1 C2 C3 C4 C5 C6 C7 C8JC2

C9 C10 C11 C12 C13 C14 II

DI

CRC8

JC3

4

5

6

7

8

JC4

RES RES RES RES

D1

D2

D3

D4

JC5

RES RES RES RES

D5

D6

D7

RES

JC6

RES RES RES RES

1

2

3

CRC4

14-bit C1028
GMP O verhead &Parameters (4x257b
blocks stuffing granularity

7 -bit S CnD
Pr ovides 7-bit
granularity

Figure 10: 400ZR overheadwww.oiforum.com

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OIF-400ZR-01.0

8.6

400ZR Alignment Markers (AM)The role of AM is to find the FEC block boundary. Alignment markers are inserted before FEC encoding
and removed after FEC decoding. The 400ZR modem operates across two domains. IEEE Std-2018
clause 119 defines the AM requirements at the 400GBASE-R interface. This IA defines the 400ZR frame
AM requirements for the coherent single-carrier media interface.
400ZR frame defines a 16×120 = 1920 bits AM field which contains the 10-bit interleaving result of 16
lane alignment markers of 120-bits each. Frame alignment, however, can be done across a subset ofthese fields. The alignment marker field is carried at the beginning of each frame (1st row). 400ZR AM isprotected by the SC-FEC and its value is scrambled. AM alignment is processed post FEC decode (after
descrambling) to locate the row number corresponding to the start of the 400ZR frame (SC-FEC being
already 10970b row aligned).

1920

1911

21

11

1

Figure 11 illustrates the AM transmission order. The 192×10b (1920 bits total) blocks are transmitted left
to right starting with the 1st 10-bits of am0, followed by the 1st 10-bits of am1, etc.., until the 12th 10-bitsof am14 (1920 bits total).

th

1st 10 bits of am0
1st 10 bits of am1
1st 10 bits of am2
1st 10 bits of am3
1st 10 bits of am4
1st 10 bits of am5
1st 10 bits of am6
1st 10 bits of am7
1st 10 bits of am8
1st 10 bits of am9
1st 10 bits of am10
1st 10 bits of am11
1st 10 bits of am12
1st 10 bits of am13
1st 10 bits of am14
1st 10 bits of am15
2nd 10 bits of am1
2nd 10 bits of am0
2nd 10 bits of am3
2nd 10 bits of am2
2nd 10 bits of am5
2nd 10 bits of am4
2nd 10 bits of am7
2nd 10 bits of am6

12 10 bits of am13
12th 10 bits of am12
12th 10 bits of am15
12th 10 bits of am14

AM

Figure 11: Alignment Marker transmission order – 10b interleaved
The 400ZR AM field consists of 16 logical lane alignment marker indicators (am<i>, where <i> = 0,1...15).
Each lane carries a 120-bit lane alignment marker. Figure 12, and rows of Table 3 give the values of am<i>transmitted over lane <i>.
BITS 1120{ CM0, CM1, CM2}
CM:
UP:
UM:

UP0

{ CM3, CM4, CM5}

UP1

{ UM0, UM1, UM2}

Common alignment marker
Unique pad
Unique alignment marker

UP2{ UM3, UM4, UM5}

x16

Figure 12: Alignment Marker format
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OIF-400ZR-01.0

The alignment marker encoding is shown in Table 3.
LogicalEncoding
Lane am<i>{CM0, CM1, CM2, UP0, CM3, CM4, CM5, UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}
00x59,0x52,0x64,0x6D,0xA6,0xAD,0x9B,0x9B,0x80,0x8E,0xCF,0x64,0x7F,0x71,0x30
10x59,0x52,0x64,0x20,0xA6,0xAD,0x9B,0xE6,0x5A,0x7B,0x7E,0x19,0xA5,0x84,0x81
20x59,0x52,0x64,0x62,0xA6,0xAD,0x9B,0x7F,0x7C,0xCF,0x6A,0x80,0x83,0x30,0x95
30x59,0x52,0x64,0x5A,0xA6,0xAD,0x9B,0x21,0x61,0x01,0x0B,0xDE,0x9E,0xFE,0xF4
40x59,0x52,0x64,0x87,0xA6,0xAD,0x9B,0x98,0x54,0x8A,0x4F,0x67,0xAB,0x75,0xB050x59,0x52,0x64,0x4F,0xA6,0xAD,0x9B,0x72,0x48,0xF2,0x8B,0x8D,0xB7,0x0D,0x74
60x59,0x52,0x64,0xBC,0xA6,0xAD,0x9B,0x77,0x42,0x39,0x85,0x88,0xDB,0xC6,0x7A
7
0x59,0x52,0x64,0x44,0xA6,0xAD,0x9B,0x4C,0x6B,0x6E,0xDA,0xB3,0x94,0x91,0x25
80x59,0x52,0x64,0x06,0xA6,0xAD,0x9B,0xF9,0x87,0xCE,0xAE,0x06,0x78,0x31,0x51
90x59,0x52,0x64,0xD6,0xA6,0xAD,0x9B,0x45,0x8E,0x23,0x3C,0xBA,0x71,0xDC,0xC3
100x59,0x52,0x64,0x5F,0xA6,0xAD,0x9B,0x20,0xA9,0xD7,0x1B,0xDF,0x56,0x28,0xE4
110x59,0x52,0x64,0x36,0xA6,0xAD,0x9B,0x8E,0x44,0x66,0x1C,0x71,0xBB,0x99,0xE3
120x59,0x52,0x64,0x81,0xA6,0xAD,0x9B,0xDA,0x45,0x6F,0xA9,0x25,0xBA,0x90,0x56
130x59,0x52,0x64,0x28,0xA6,0xAD,0x9B,0x33,0x8C,0xE9,0xC3,0xCC,0x73,0x16,0x3C
14
0x59,0x52,0x64,0x0B,0xA6,0xAD,0x9B,0x8D,0x53,0xDF,0x65,0x72,0xAC,0x20,0x9A
15
0x59,0x52,0x64,0x2D,0xA6,0xAD,0x9B,0x6A,0x65,0x5D,0x9E,0x95,0x9A,0xA2,0x61
NOTE – The value in each byte of this table is in MSB-first transmission order. Note that this per-byte
bit ordering is the reverse of AM values found in [IEEE Std-2018], which uses an LSB-first bit
transmission format.

Table 3: 400ZR Alignment Marker encodings
8.7

400ZR PAD

1

1920

Immediately following the 1920-bit AM is a 1920-bit field of PAD, transmitted as all-zeros and ignored onreceipt.

PAD

Figure 13: PAD transmission order – 10b interleavedwww.oiforum.com

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OIF-400ZR-01.0

8.8

400ZR OH

1280

1271

21

11

1

Four 320-bit blocks of overhead are transmitted immediately after the 1920 bit of PAD. These are 10-bit
interleaved.

32nd 10 bits of OH0
32nd 10 bits of OH1
32nd 10 bits of OH2
32nd 10 bits of OH3

1st 10 bits of OH0
1st 10 bits of OH1
1st 10 bits of OH2
1st 10 bits of OH3
2nd 10 bits of OH0
2nd 10 bits of OH1
2nd 10 bits of OH2
2nd 10 bits of OH3
3rd 10 bits of OH0
3rd 10 bits of OH1
3rd 10 bits of OH2
3rd 10 bits of OH3
4th 10 bits of OH0
4th 10 bits of OH1
4th 10 bits of OH2
4th 10 bits of OH3

OH

Figure 14: Over Head transmission order – 10b interleaved
8.8.1 Multi-Frame Alignment Signal (MFAS)
The Multi-frame alignment signal (MFAS) is in the first of the four 320-bit OH instances. It is present andincremented in every 400ZR frame. It counts from 0x00 to 0xFF and provides a 256-frame multi-frame
sequence following [ITU-T G.709.1] Clause 9.2.1 definition.

8.8.2 Link error and Link degrade detection and marking
Table 4 specifies the replacement signal to the host interface in the event of DSP framing or ZR
frame/multi-frame loss.
Host interface signal
400GBASE-R

Replacement signal
Continuous 400GBASE-R local fault sequenceordered sets as 256b/257b encoded blocks

Bit-rate tolerance (ppm)+/- 100

Table 4: Replacement signal
The FEC decoder can also detect a degrading link and signal Link Degrade (LD). A degraded link condition
data may be passing data without error, however, the BER may be high and approaching FEC exhaust.
Causes of link degrade may be component wear-out due to aging or stress. A user may want to take preemptive actions based on programmable BER thresholds. Consequent actions can include re-routing
traffic away from the impaired link.

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8.8.3 Link status monitoring and signaling (STAT)
The status (STAT) overhead byte is present in every 400ZR frame, but only carried in the first of the four
320-bit OH instances. It includes the 1-bit RPF and 3-bit LDI fields:•

The Remote PHY Fault (RPF) bit indicates signal fail status detected at the remote 400ZR sink
function in the upstream direction and follows the definition in [ITU-T G.709.1] Clause 9.2.5.1. RPF
is set to ''1'' to indicate a remote 400ZR PHY defect indication; otherwise, it is set to '' ’ The RPF
field is in bit 1 of the STAT field as per Figure 15.

•

The 3-bit host Link Degrade Indication (LDI) field is defined to indicate to the downstream device
the quality of the host interface signal or the media interface signal.

STAT OH Byte
Bits#

1

2

3

RPF

4

5

6
RES

RES

=Am_
sf<0>

7

8

RD

LD

=Am_
sf<2>

=Am_
sf<1>

LDI

Figure 15: STAT Over Head byte definitions
The 400ZR link shall provide detection and signaling of Link Degrade (LD) for use by switch/routers with
soft reroute capabilities. Figure 16 illustrates the bidirectional signaling between a 400ZR transceiver and
two Routers (A and B). Pre-FEC BER monitors are used to detect and insert link degrade at both the 400ZR
optical link and the 400GBASE-R interface.
400ZR Transponder Application
400ZR Transponder X
Reserved

Reserved

am_sf<0>

STAT[6]am_sf<0>Reserved
am_sf<0>am_sf<2>

STAT[7]

am_sf<2>

am_sf<2>

RD

LD
STAT[8]LD

STAT[8]am_sf<1>

RD

RD

RD

am_sf<2>
Reserved
am_sf<0>

STAT[7]
Reserved
STAT[6]am_sf<2>
Reserved
am_sf<0>

Ethernet FEC

AUI

LD
am_sf<1>

DTE XSFEC FECMIIPHY XSFEC

PCS

FEC FECFEC FEC(De)Mapper

FEC

PCS

FEC

400GBASE-R

FEC

PCS

FEC
FEC

ZR

(De) Mapper+`-

Single opticalspan and FEC

LD

am_sf<1>LD
am_sf<1>

PCS

ZR

LD

LD
am_sf<1>

FEC

LD
am_sf<1>

RD

RD

400GBASE-R

RD

0

Router B

400ZR Transponder Y

Reserved

FEC FEC0FEC FEC

Router A

0RD

am_sf<2>
Reserved
am_sf<0>0

FEC 400ZR FEC

Figure 16: Local/Remote Degrade interworking between Switch/Router and 400ZR
transceiver

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OIF-400ZR-01.0

8.8.4 Link Degrade Indication (LDI)[IEEE 802.3] has specified three bits in the AM field (am_sf<2:0>) to carry Link Degrade Indication (LDI).
Bit am sf<2> is defined as a Remote Degrade (RD) signal, bit am_sf<1> is defined as a Local Degrade (LD)signal and bit am_sf<0> is reserved.
The 400ZR transceiver X and Y shall forward the information in the Reserved (am_sf<0>) and RD(am_sf<2>) bits between transceivers as illustrated in Figure 16. The information in am_sf<0> shall be
carried in 400ZR STAT overhead bit 6. The status information in am_sf<2> shall be carried in 400ZR STAT
overhead bit 7. The status information in the LD (am_sf<1>) bit shall be carried after some additional
processing in the 400ZR STAT overhead, bit 8 to the downstream device.
In the host-to-media datapath, the additional processing consists of ORing the ingress LD status in theam_sf<1> bit of the 400GBASE-R signal with the local host interface RS(544,514) FEC degrade status andsignaling LD in STAT[8] to the media interface. In the media-to-host datapath, the STAT<8> bit from themedia interface is ORed with the 400ZR FEC degrade status and signaled on the am_sf<1> bit to the local
host.

8.8.5 Link Degrade Warning and Alarming.
FEC Detected Degrade (FDD) and FEC Excessive Degrade (FED) is an optional [user configurable] linkmonitoring feature, indicating a link degrade condition to the local host and remote transmitter. It canbe used, for example, to pre-emptively move traffic away from a degraded link (e.g. traffic re-route). Thisfeature requires capturing the pre-FEC BER from the FEC decoder block over a Performance Monitor (PM)interval. Statistics are gathered by HW and reported by SW. FED and FDD are determined by comparing
the HW BER reported statistics against [user configurable] thresholds.
Link Degrade (LD) signaling shall be based on the FEC decoder statistics (number of corrected errored bits,
and uncorrectable blocks). Fault detection calculation and threshold settings may be implementation
dependent (e.g. based on FEC decoder pre-FEC BER detection capabilities).
The following Performance Monitoring (PM) parameters are defined for determining a Link Degrade (LD)condition over a PM interval. The PM interval and the collection of the statistics to determine LD is definedby the Management Interface Spec specific to the module which this IA is implemented.
FEC decoder block, bit counters:• pFECblkcount = FEC blocks counted over PM interval• pFECbitcount = total number of bits counted over PM interval = (pFECblkcount × bits per FEC block), 64bit value• pFECcorrbitblk = FEC corrected bits per block (min., avg., max.) over PM interval• pFECcorrbit = total number of FEC corrected bits over PM interval = ∑pFECcorrbitblk over PM interval.
(64-bit value).
Pre-FEC BER block, bit counters:• pFECblkBER = FEC block BER (min., avg., max.) over PM interval = (pFECcorrbitblk/pFECblkcount)• pFECBER = FEC BER over PM interval = (pFECcorrbit / pFECbitcount)

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OIF-400ZR-01.0
Pre-FEC threshold settings:• FEC_excessive_BER_activate_threshold (programmable)• FEC_excessive_BER_deactivate_threshold (programmable)• FEC_degraded_BER_activate_threshold (programmable)• FEC_degraded_BER_deactivate threshold (programmable)
FEC degrade settings:• FECdetectdegraded = FEC degraded status condition over PM interval.
• FECexcessdegraded = FEC excessively degraded status condition over PM interval.
Each of the above registers shall have a corresponding enable, status, and latch bit settings.
FECdetectdegraded and FECexcessdegraded shall also be a maskable interrupt.
PM interval:• PM_Interval = (programmable); default = 1 second.
The FEC decoder counts and reports the number of bits detected in error over the PM interval per FEC
block (min., max., avg.).

•
•
•
•

When the (avg) number of bit errors exceeds the threshold set in
FEC_degraded_BER_activate_threshold, FECdetectdegraded is set and latched.
When the (avg) number of bit errors falls below the threshold
FEC_degraded_BER_deactivate_threshold, FECdetectdegraded is cleared.
When the (avg) number of bit errors exceeds the threshold set in
FEC_excessive_BER_activate_threshold, FECexcessdegraded is set and latched.
When the (avg) number of bit errors falls below the threshold
FEC_excessive_BER_deactivate_threshold, FECexcessdegraded is cleared.

When errors are detected after C-FEC error correction in the Rx data path (e.g. uncorrected block statusfrom the C-FEC decoder or CRC32 checking), the entire base block of 30592×8 bits is considered corrupted
and all 952×257-bits of information must be marked as being in error using transcoded error control
blocks.
If the link input BER is much lower than C-FEC limit under normal operational conditions, error marking
using post-FEC statistics (i.e. CRC32 checking) could be turned-off to lower Rx latency. In this case, aprogrammable pre-FEC excessive error threshold status could be used for error marking at the FEC
decoder output.
Per 802.3TM-2018 Clause 119.2.5.3, if bypass error indication is not supported or not enabled, when the
Reed-Solomon decoder determines that a codeword contains errors that were not corrected, it shall cause
the PCS receive function to set every 66-bit block within the two associated codewords to an error block(EBLOCK_R) as in Figure 17.

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OIF-400ZR-01.0
The encoding of a 64b/66b error control block is: [sync="10", control block type=0x1e, and eight 7-bit/E/control characters.

257-bit error marking block encoding
0 0000 0xE /E/E/E/E/E/E/E/E/ 0x1E /E/E/E/E/E/E/E/E/ 0x1E /E/E/E/E/E/E/E/E/ 0x1E /E/E/E/E/E/E/E/E/
Error Control Block

Error Control Block

Error Control Block

Error Control Block/E/ control code value (7-bit) = 0x1E →001110000

0111100

8×7-bit

01111000

8×7-bit

01111000

8×7-bit

8×7-bit257-bit error marking block encoding (binary value)

Transmission orderFigure 17: Error marking
8.9

GMP mapping processes

The 400GBASE-R is asynchronously mapped into a 400ZR container using GMP. The timing is de-correlated
from the 400GBASE-R host clock to simplify ASIC design. Even though the mapping is asynchronous, the400GBASE-R stream is treated as CBR data (including preamble, and IPG). Data and timing transparency
shall be supported using information fields which are inserted by the GMP process for use upon demapping.
The GMP Justification Control bytes (JC1-6) are carried in the first of the four 320-bit OH instances, and
nd

rd

th

present in the 2 , 3 , and 4 frames of a 400ZR 4-frame multi-frame to signal the GMP parameters Cmand ∑CnD from mapper to de-mapper. The 4 frames are identified by MFAS bits 7 and 8 being 00, 01, 10
and 11.
Reference ITU-T G.709 annex D for the general principles of the Generic Mapping Procedure (GMP).
For the purpose of 400ZR the GMP parameters shall be defined as:
•
•
•
•
•
•
•

m = GMP data/stuff granularity = 4 × 257 = 1028 bit;n = 1028/128 = 8.03125-bit unit and represents the timing granularity of the GMP mapping
present in Cn and ∑CnD parameters;
Pm,server = maximum number of m-bit data entities in 4-frame multi-frame server payload = 10220.
Cm = number of client m-bit data entities in 4-frame multi-frame server payload. It is encoded with
14 bits and carried in JC1 and JC2 control OH bytes.
Cn = number of equivalent client n-bit data entities in 4-frame multi-frame server payload. Thisvalue provides additional ‘n’-bit timing information.
∑CnD = accumulated value of the remainder of Cn and Cm. It is encoded with 7-bits and carried in
JC4 and JC5 control OH bytes.
Cn and Cm being integer values, then:Cn(t) = 128 × Cm(t) + (∑CnD(t) - ∑CnD(t-1))

The support for n-bit timing information (∑CnD) in the JC4/JC5/JC6 OH is required.
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OIF-400ZR-01.0
The mapper shall first recover the 400GBASE-R stream. The 400GBASE-R is a sequence of 256b/257b
encoded blocks as per IEEE Std-2018 after the partial PCS processing defined in Figure 6 andSection 8.3. The 400ZR frame payload area is a direct multiple of 257 bits (10220×257b).
The 400GBASE-R signal is mapped to the 400ZR frame as a 257b block stream, with 20 blocks of
AM/PAD/OH every 10240 blocks. The payload area for this mapping consists of the payload of a 4-frame
400ZR multi-frame (40880 257b blocks) for host interface data. Groups of 1028 successive bits (4×257b),of the client signal are mapped into a group of 4 successive 257b blocks of the 4-frame 400ZR multi-frame
payload area under control of the GMP data/stuff control mechanism. Each group of 4×257b in the 4frame 400ZR multi-frame payload area may either carry 1028 host interface bits or carry 1028 stuff bits.
The stuff bits shall be set to zero.

No ratematching

No ratematching

Encode256b/257b transcode

GMP Mapping(4*257b stuffing)

Decode &Error Marking

Reverse transcode
System-side CLOCK DOMAIN 256b/257b blocks(+/- 100 ppm)
Line-Side CLOCK DOMAIN(+/- 20 ppm)

OH/AM insertion(20*257b)

GMP de-mapping(4*257b de-stuffing)

AM/OH detect & removal(20*257b)

Figure 18: GMP mapping/de-mapping process
Table 5 specifies the host interface and its GMP m, n and CnD parameter values.

Host nominal bit
rate (kbits/s)
425 000 000

Nominalinformation bit
rate (kbits/s) after
FEC and AM
removal
401 542 892

Bit-rate
tolerance
(ppm)

m

n

CnD

+/- 100

1028

8.03125

Yes

Table 5: Host interface and its GMP parameter values
The server input nominal bit rate of 401 542 892 kbit/s equals the 400GBASE-R interface signal afterRS(544/514) FEC decode and AM removal.

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31

OIF-400ZR-01.0
The de-mapping process decodes Cm(t) and CnD(t) from JC1/JC2/JC3 and JC4/JC5/JC6 and interprets Cm(t)and CnD(t) according to ITU-T G.709 Annex D. CRC8 shall be used to protect against an error in JC1/JC2/JC3
and CRC4 protect against an error in the JC4/JC5/JC6 signals.
Ref

GMP Parameter

FormulaValue

fclient

nominal client information bit rate

425.00 Gbit/s × 514/544
× 20479/20480

401,542,892,456.055

bit/sfclientclient bit rate tolerance

100

ppm

fserverserver nominal bit rate f

402,489,753,309.729

bit/sfserverserver bit rate tolerance

20

ppm

Tserver
Bserver
Oserver
Pserver
fp,server

period of the server multiframe,
number of bits per server
multi-frame
number of overhead bits perserver multi-frame
maximum number of bits inthe server payload area
nominal server payload bit
rate

425.00 Gbit/s × 514/544
× 20479/20480

Bserver / fserverm

GMP data/stuff granularityMm and n ratio

Pm,server

maximum number of (m bits)
data entities in the server
payload area

Bserver - OserverCmnumber of client m-bit data
entities per server multi-frame

fserver × Pserver / Bserver =478.75 × 28/29 ×
119/128 × 5140/5488 ×
511/512

Cm,nomCm,minCm,maxcm value at nominal client andserver bit rates
cm value at minimum clientand maximum server bit rates
cm value at maximum clientand minimum server bit rates

Units

26.154µs

10,526,720

bits

20,560bits

10,506,160

bits

401,703,640,510.296

bits/s(4×257 =) 1,028

bits

128
10220

m bit data entity

10,215.910

m/n

10,214.684

Pserver / m

10,217.136

Cm,mininteger value of cm,min

Cm,maxrounded up value of cm,max(fclient / fp,server) × Pm,server

10,218

GMP justification accuracy, n
bit data entity
maximum number of (n bits)
data entities in the server
payload area

Cm,nom × (1 - fclient) / (1+ fserver)

8.03125

Cm,nom × (1 + fclient) / (1- fserver)

1,308,160.000nPn,server

www.oiforum.com

1028bblocks

10,214bits
8.03125b
blocks32

OIF-400ZR-01.0
Ref

GMP Parameter

Formulanumber of client n-bit data
entities per server multi-frame
Cn value at nominal client andserver bit rates
Cn value at minimum clientand maximum server bit rates
Cn value at maximum clientand minimum server bit rates

Cn
Cn,nomCn,minCn,max

Value

Units

C,min  Cm,max 

1,307,636.519
1,307,479.603

Pserver / nCnD

remainder of Cn and Cm

CnD

integer value of cnD(fclient / fp,server) × Pn,serverƩCnD

accumulated value of CnD

Cn,nom × (1 - fclient) / (1+ fserver)

1,307,793.436
0.910305637

127

Table 6: GMP parameter values
Where,
•
•
•
•
•

•
•
•

•

Client information rate is 400GBASE-R after RS(544,514) FEC and AM removal with fclient nominal
bit rate and ∆fclient bit rate tolerance.
Server is 400ZR 4-frame multi-frame (both payload and overhead) with fserver nominal bit rate
∆fserver bit rate tolerance and Bserver number of bits per server 4-frame multi-frame.
Server payload is 400ZR 4-frame multi-frame payload (before AM/PAD/OH insert) with fp,server
nominal bit rate, ∆fserver bit rate tolerance and Pserver number of bits per server 4-frame multi-frame
payload area.
The maximum number_of_m [=1028] bit GMP data entities per 4-frame multi-frame payload isPm,server [=10220].
For 400ZR, we use n = [m / 128] = [4×257-bit]/128 = 8.03125 UI that is used as a phase unit “n-bit
equivalent” for Cn parameter. Cn indicates the number of “n-bit equivalent” of the 400GBASE-R
client per 400ZR 4-frame multi-frame server payload. It can be used as a finer phase indicator to
encode the client clock at the GMP mapper.
So, Cn, nom = 128 × Cm, nom; Cn, min = 128 × Cm, min; Cn, max = 128 × Cm, max
C = Pm,server × [client_bit_rate / Server_Payload_bit_rate].
m

C is an integer value indicating to every 400ZR frame the number of m-bit client blocks carriedm[m = 4×257b = 1028b] in this 400ZR 4-frameint(Pm,server×[client_bit_rate/Server_Payload_bit_rate]).

servermulti-frame

payload =Cm ≤ Pm,server and is a value varying between Cm,min and Cm,max for the given client andpayload type, due to client and payload bit rate tolerance range (+/- 100 ppm and +/-20
ppm).

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33

OIF-400ZR-01.0

8.9.1 Stuffing Locations
Stuff location determination for GMP uses a delta-sigma algorithm based on the Cm value over the total
number of payload location. GMP is a positional mapping with non-fixed stuff. So, the stuff location willvary on a GMP payload-by-payload basis, based on the Cm(t) value. In the case of 400ZR the GMP payload
covers four 400ZR frames.
Table 7 shows the location of the "stuff" GMP blocks for a few specific Cm values.
Cm

GMP Blocks Number of Stuff Locations

10220

N/A

10219

1

10218

1, 511110217

1, 3407, 6814

10216

1, 2556, 5111, 7666

10215

1, 2045, 4089, 6133, 8177

10214

1, 1704, 3407, 5111, 6814, 8517

Table 7: GMP stuff locations of 400ZR

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34

OIF-400ZR-01.0

PAD

ZR OH

1
2

6

6

5140
5141

1

3841

Columns
Row

6

6

7

7

7

10280

Figure 19 shows an example of GMP stuff opportunities over four 400ZR frames.

ZR OH

7

1

1

1

St uff
4×257b

3

1

2

2

2

2

Dat a
4×257b

5

5

5

5

15

15

15

15

Dat a
4×257b400ZR Frame 1

4

Dat a
4×257b2562554 2554 2554 2554 2555 2555 2555 2555
PAD

257

ZR OH

258

2561 2561 2561 2561 2562 2562 2562 2562

259

Dat a
4×257b

ZR OH

2560 2560 2560 2560

2556 2556 2556 2556 2557 2557 2557 2557
St uff
4×257bDat a
4×257b2600 2600 2600 2600
Dat a
4×257bDat a
4×257b400ZR Frame 2

260

Dat a
4×257bDat a
4×257b5125109 5109 5109 5109 5110 5110 5110 5110

PAD

769

ZR OH

770

7687 7687 7687 7687 7688 7688 7688 7688

771

Dat a
4×257b

ZR OH

7686 7686 7686 7686

7666 7666 7666 7666 7667 7667 7667 7667
Stuff
4×257b7720 7720 7720 7720

Dat a
4×257bDat a
4×257bDat a
4×257b400ZR Frame 4

772

Dat a
4×257bDat a
4×257b1024

Dat a
4×257b10119 10119 10119 10119 10220 10220 10220 10220

Figure 19: GMP mapping over four 400ZR frames with Cm=10216
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35

OIF-400ZR-01.0

8.9.2 GMP overhead Encoding
GMP overhead (JC Bytes OH) is carried once per GMP payload envelope (combining four consecutive
400ZR frame payloads), so once per 4-frame multi-frame. GMP overhead carries the encoded 14-bit Cm(t)(i.e. 4×257b block count value) in C1-14 bits of JC1 & JC2 (C1 = MSB, ..,C14= LSB) and the encoded 7-bitƩCnD(t) (cumulative value of CnD(t)) in D1-D7 bits of JC4 & JC5 (D1=MSB,.. , D7 = LSB) GMP parameters.
Cm(t) is protected by a CRC8 (carried in JC3 OH byte) and ƩCnD(t) is protected by a CRC4 (carried in the four
LSBs of JC6 OH byte).
The JC3 OH CRC8 calculation is described in ITU-T G.709 Annex D.3, and an example of a parallel
implementation can be found in ITU-T G.709 Appendix VI.

8.9.3 GMP OH – CRC8 calculation
The CRC8 located in JC3 is calculated over the JC1 and JC2 bits. The CRC8 uses the generator polynomial:g(x) = x8 + x3 + x2 + 1••••

The JC1 and JC2 octets are taken in order, most significant bit first, to form a 16-bit patternrepresenting the coefficients of a polynomial M(x) of degree 15.
M(x) is multiplied by x8 and divided (modulo 2) by G(x), producing a remainder R(x) of degree 7 orless.
The coefficients of R(x) are considered to be an 8-bit sequence, where x7 is the most significant
bit.
This 8-bit sequence is the CRC8 where the MSB of the CRC8 is the coefficient of x7 and the LSB isthe coefficient of x0.

The de-mapper process performs steps 1-3 in the same manner as the mapper process, except that here,
the M(x) polynomial of step 1 includes the CRC bits of JC3, resulting in M(x) having degree 23. In theabsence of bit errors, the remainder shall be 0000 0000.

8.9.4 The JC6 OH CRC4 Calculation
The CRC4 located in JC6 uses the generator polynomial:g(x) = x4 + x + 1.
••••

The four least significant bits of the JC4 and JC5 octets (JC4 D1-D4 and JC5 D5-D7 + RES) are taken
in order, most significant bit first, to form an 8-bit pattern representing the coefficients of apolynomial M(x) of degree 7.
M(x) is multiplied by x4 and divided (modulo 2) by G(x), producing a remainder R(x) of degree 4 orless.
The coefficients of R(x) are considered to be a 4-bit sequence, where x3 is the most significant bit.
This 4-bit sequence is the CRC4 where the MSB of the CRC4 is the coefficient of x3 and the LSB isthe coefficient of x0.

The de-mapper process performs steps 1-3 in the same manner as the mapper process, except that here,
the M(x) polynomial of step 1 includes the CRC bits of JC6, resulting in M(x) having degree 11. In theabsence of bit errors, the remainder shall be 0000.

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36

OIF-400ZR-01.0

9400ZR frame to SC adaptation

Figure 20 and Figure 24 show the relationship of the 400ZR frame mapping to the SC-FEC block.
•

119 rows×[2×5140-bit] of information (1223320 bits) + 119×[2×345 bit] of FEC parity (81920 bits)
and pad (190 bits) is mapped to 5×SC-FEC Blocks.
One SC-FEC frame [510b×512b] carries 952×257-bit blocks of information + CRC32 + 6-bit MBAS
+ 34-bit zero stuff (261120 bits).

•

rows
1
2

columns
1

5140b =20× 257b
AM
PAD
OH
4× 960b10280 10281 10970

|
10

11

FEC
ParityCRC/
MBAS

Payload area (mapped 400GE)

| |

110
111

Five consecutive Staircase FEC Blocks
510
478

119
1

CRC/
MBAS

229

119

FEC Parity

CRC/
MBAS

Zero
s

Bi+4

CRC/
MBAS

Bi+3

Zero
s

Format 119 rows of
10970- bit into 5
contiguous SC- FEC
blocks (Bi to Bi+4) of 512
bit x 510-bit

72

1

CRC/
MBAS

230

Bi+2

CRC/
MBAS

.

Bi+1

Zero
s

49

Bi

CRC/
MBAS

159

254
255

FEC
Parity

256
1

512

48

Zero
s

158

CRC/
MBAS

FEC
Parity952x257- bit block of
payload (framed/
mapped 400GE) +CRC32 + 6b MBAS +34b all zero (nottransmitted)

Zeros

Payload Area
(400GE 256b/257b host blocksX+x
257b stuff blocks)

5 x SC-FEC
Blocks

24
25

135

CRC/
MBAS

256 rows (400ZR Frame)

134

119 Rows

CRC/
MBAS

Payload Information

AM

PAD

25
26
27

OH
2× 5140bits
2× 5485bits

24

2× 345bits

Figure 20: 400ZR frame to SC-FEC relationshipwww.oiforum.com

37

OIF-400ZR-01.0

9.1

Mapping 400ZR Frame Payload to Staircase FEC Blocks

The payload of a 400ZR frame is mapped into units of 244,664 bits, where 244,664 = 512×478-72
consecutive bits. For every 244,664 consecutive bits a 32-bit CRC (ref. section 9.2) is calculated, plus a 6bit Multi-Block Alignment Signal (MBAS) is added forming the CRC(32B)+MBAS(6b) block. The CRC+MBAS(38b) block is inserted at the end of each parity block (ref. Figure 21).
Each SC-FEC frame contains 261120 bits (244664b of payload + 16384b of FEC parity bits + 32 bits of CRC+ 6b of MBAS + 34b of pad). The 34b of additional pad is not transmitted. In the Figure 23, the 38-bit
CRC+MBAS is shown located at the end of each parity block.
Information and parity bits in 119 400ZR frame rows (119×10970 bits) or (1305430 bits), can be
represented in 5 SC blocks organized as 5×32640x8 bits – 34 bits of pad that is not transmitted). See Figure
24 left and right side.
•
•

9.2

400ZR Information block boundaries are thus located at the 23.8th, 47.6th, 71.4th, 95.2th and 119throws and at columns 8224, 6184, 4112, 2056 and 10280.
Parity block boundaries are thus at parity columns 138, 276, 414, 552 and 690 (or columns 10418,
10556, 10694, 10832 and 10970).

400ZR CRC+MBAS Bit Insertion Block

A 32-bit CRC is calculated over the 244,664 input bits with the generator polynomial IEEE 802.3(Hammond, et.al. [1]).
𝐺(𝑥) = 𝑥 32 + 𝑥 26 + 𝑥 23 + 𝑥 22 + 𝑥 16 + 𝑥 12 + 𝑥 11 + 𝑥 10 + 𝑥 8 + 𝑥 7 + 𝑥 5 + 𝑥 4 + 𝑥 2 + 𝑥 + 1,
appended to the end of the sequence.
Mathematically, the CRC value corresponding to the 244,664 input bits is defined by the following
procedures:
•
•

•
•
•

The first 32 bits of the frame are complemented.
The 244,664 bits of the protected fields are the coefficients of a polynomial 𝑀(𝑥) of degree
244,663. (The first bit of the 244,664 input bits corresponds to the 𝑥 244,663 term and the last bitof the 244,664 input bits corresponds to the 𝑥 0 term).
𝑀(𝑥) is multiplied by 𝑥 32 and divided (modulo 2) by 𝐺(𝑥), producing a remainder R(x) of degree< 31.
The coefficients of R(x) are a 32-bit sequence.
The bit sequence is complemented, and the result is the CRC.

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38

OIF-400ZR-01.0
The 32 bits of the CRC value are placed with the 𝑥 31 term as the left-most bit of the CRC32 field and the𝑥 0 term as the right-most bit of the CRC32 field. (The bits of the CRC are thus transmitted in the order:
𝑥 31 , 𝑥 30 , … , 𝑥 1 , 𝑥 0 ). The 6-bit MBAS is appended after the 32-bit CRC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

CRC32

MBAS

Figure 21: CRC32 + MBAS
9.2.1 400ZR Multi Block Alignment Signal (MBAS)
To synchronize the state of the Error De-correlator (ED) controllers between the receiver and thetransmitter, the Staircase FEC scheme uses a 7-bit SC FEC Multi Block Alignment Signal (MBAS) which
provides a 128-block sequence.
The six most significant bits of the 7-bit MBAS are transferred between source and sink in the 6-bit MBAS
overhead, which is located in bits 33 to 38 in Figure 21.
The numerical value represented in the six MBAS overhead bits will be incremented every two SC FEC
blocks and provides as such a 128-block multi-block as illustrated in Figure 22.

Figure 22: Multi-block alignment signal overheadwww.oiforum.com

39

OIF-400ZR-01.0

10280
10418
10556
10694
10832
10970

8224

6168

4112

1

columnsrows

2056

Figure 23 shows the location and transmission order of the CRC32 and MBAS.

i+1

244664 Information bits of Bj

16384
Parity bitsof Bj-1

i+24

CRC32
CRC32 of Bj

244664 Information bits of Bj+1

16384
Parity bits
of Bj

i+48

CRC32

CRC32 of Bj+1
244664 Information bits of Bj+2

16384
Parity bitsof Bj+1

i+72

CRC32

CRC32 of Bj+2
244664 Information bits of Bj+3

16384
Parity bitsof Bj+2

244664 Information bits of Bj+4

16384
Parity bitsof Bj+3

i+96

CRC32

CRC32 of Bj+3

i+119

CRC32
CRC32 of Bj+4

AM/PAD/OH and payload

SC FEC and
38 PAD1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

CRC32

MBAS

Figure 23: CRC32 + MBAS transmission order

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40

OIF-400ZR-01.0

1.1
1.5
1.9

1.3
1.7
1.11

10280
10418
10556
10694
10832
10970

1.2
1.6
1.10

2.0

1.5
1.9

1.1

1.6
1.10

8.10
1.2

1.7
1.11

8.11*
1.3

1.0
1.4
1.8
2.0

119 rows  5 × FEC Blocks

i+48

8.10
1.2
1.6
1.10

8.11*
1.3
1.7
1.11

1.0
1.4
1.8
2.0

1.1
1.5
1.9

i+72

8.11*

8.11
1.3
1.7
1.11

1.0
1.4
1.8
2.0

1.1
1.5
1.9

1.2
1.6
1.10

i+96

8.11*
1.3
1.7

1.0
1.4
1.8
2.0

8.10
1.2
1.6
1.0
1.11

1.1
1.5
1.9

1.0
1.4
1.8
2.1

8.10
1.2
1.6
1.10

1.1
1.5
1.9

8.11
1.3
1.7
1.11
2.0

244664 Information bits of Bj+5

8.10

8.11*

244664 information
bits of Bj-1

1.10
2.10
3.10
4.10
5.10
6.10
7.10
8.10

1.11
2.11
3.11
4.11
5.11
6.11
7.11
8.11

1.12
2.12
3.12
4.12
5.12
6.12
7.12
8.12
16384 parity
bits of Bj-1

1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0

244664 information
bits of Bj

1.10
2.10
3.10
4.10
5.10
6.10
7.10
8.10

1.11
2.11
3.11
4.11
5.11
6.11
7.11
8.11

1.12
2.12
3.12
4.12
5.12
6.12
7.12
8.12
16384 parity
bits of Bj

1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0

244664 information
bits of B j+1

1.10
2.10
3.10
4.10
5.10
6.10
7.10
8.10

1.11
2.11
3.11
4.11
5.11
6.11
7.11
8.11

1.12
2.12
3.12
4.12
5.12
6.12
7.12
8.12
16384 parity
bits of Bj+1

1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0

244664 information
bits of B j+2

1.10
2.10
3.10
4.10
5.10
6.10
7.10
8.10

1.11
2.11
3.11
4.11
5.11
6.11
7.11
8.11

1.12
2.12
3.12
4.12
5.12
6.12
7.12
8.12
16384 parity
bits of Bj+2

244664 information
bits of B j+3

1.10
2.10
3.10
4.10
5.10
6.10
7.10
8.10

1.11
2.11
3.11
4.11
5.11
6.11
7.11
8.11

1.12
2.12
3.12
4.12
5.12
6.12
7.12
8.12

1.12

8.12

1.12

Information andparity bits in 119
400ZR
frame rows
1.
can be represented
in 5 blocks of
32640×8 bit with 72
XXX bits at the endof subblock 8.12

8.12

1.12

16384
Parity bitsof Bj+3

244664 Information bits of Bj+4

i+119

8.12

16384
Parity bitsof Bj+2

244664 Information bits of Bj+3

1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0

1.12

16384
Parity bitsof Bj+1

244664 Information bits of Bj+2

2048 bit parity
blocks

8.12

16384
Parity bitsof Bj

244664 Information bits of Bj+1

2432 bit information
blocks
32640

1.12

16384
Parity bitsof Bj-1

244664 Information bits of Bj

i+24

2560 bit information
blocks

8

1.0
1.4
1.8
2.0

8224

i+1

6184

1

2056

columnsrows

4112

Figure 24 details the 400ZR frame to SC-FEC adaptation.

1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0

8.12

1.12

16384
Parity bitsof Bj+4CRC32400ZR: 6-bit MBAS

CRC32

6 PAD

8.12

AM/PAD/OH and payload
8.11* block shown in grey contains only
payload bits. The remaining 32-bit CRC and6-bit pad are shown in yellow in the FEC
parity area

1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0

244664 information
bits of B j+4

1.10
2.10
3.10
4.10
5.10
6.10
7.10
8.10

1.11
2.11
3.11
4.11
5.11
6.11
7.11
8.11

34 PAD
16384 parity
bits of Bj+3

1.12
2.12
3.12
4.12
5.12
6.12
7.12
8.12
16384 parity
bits of Bj+4

Figure 24: 400ZR frame adaptation SC FEC block

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10 400ZR Forward Error Correction (FEC)
The 400ZR Forward Error Correction (FEC) algorithm is a Concatenated FEC (C-FEC) that combines a HDFEC (255,239) outer code and an inner double-extended SD-FEC (128,119) Hamming code resulting in~10.8dB of NCG with ~14.8% overhead (e.g. BER_in = 1.25E-2 results in BER_out = 1.0E-15).
The HD-FEC is a (512-bit × 510-bit) generalized staircase code that works in conjunction with an error decorrelator. The error de-correlator function randomizes the position of the symbols to reduce the impact
of correlated errors on the FEC performance.

10.1 SC-FEC
For the purposes of this IA and to minimize the possibility of misinterpretation that might deviate from acommon implementation the SC-FEC, Adapt, ED and Encoding/Decoding processes shown in Figure 25 aredefined by reference [5] Annex A.

CRC-32 Calculation
SC-FEC Adapt, ED &encoding

CRC-32 checking

PCS (ZR)

SC-FEC Adapt, ED &Decoding

Pad Insertion

Pad removal(6*119b)(6*119b)

Figure 25: 400ZR HD-FEC processes
10.2 Sync Pad Insertion
For the purpose of alignment and synchronization 6×119 bits are appended/removed from the tail end of
the 5xSC-FEC block.

SC-FEC Adapt, ED &encoding

PCS (ZR)

SC-FEC Adapt, ED &Decoding

Pad Insertion

Pad removal

Scramble

Descramble(6*119b)(6*119b)

Figure 26: Pad insertion/removal

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Figure 27 shows the location of 6 ×119b pad relative to the 400ZR Frame.
Scrambler reset to 0xFFFF

210280 10281 10970

|

|
10

11

FEC
ParityPayload area (mapped 400GE)

CRC

6x119b

119
1

134

24

CRC

111

25

135

Payload Area
(400GE 256b/257b host blocks + X x
257b stuff blocks)

FEC
Parity

158

48

CRC

256 rows (400ZR Frame)

110

159

49

CRC

229

6x119b

119
1

254

24

CRC

230

255

FEC
Parity256
1

5 x SC-FEC
Blocks1

1|
5140b = 20×257b
AM
PAD
OH
4×960b119 Rows

rows

columns

AM

PAD

26
27

OH
2× 5140 bits
2× 5485 bits

25

2× 345 bits

Figure 27: 6 × 119 Pad Insertion

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10.3 Frame Synchronous Scrambling
The scrambler/descrambler is located after/before the SC-FEC encoding and 6 ×119b pad insertion.
Pad Insertion

Pad removal

Scramble

Descramble

Convolution interleaving

Convolution deinterleaving(6*119b)(6*119b)

Figure 28: Frame synchronous scrambler
The operation of the scrambler shall be functionally equivalent to that of a frame-synchronous scramblerof sequence 65535 and the generating polynomial shall be:
16

12

3

x + x + x + x + 1.
The scrambler/descrambler resets to 0xFFFF on row 1, column 1 of the five SC-FEC block structure andsubsequent 714-bit (6 x 119b) pad insertion and the scrambler state advances during each bit of the 5xSCFEC blocks. In the source function, all payload bits (included SC-FEC parity) are scrambled. At the sink thescrambler is synchronized (initialized) at the start of each payload.

10.4 Convolutional Interleave
The staircase encoded frame + 6 Sync/Pad, which consists of 10976×119 bits, is first interleaved (in unitsof 119 bits) by a convolutional interleave (CI). The CI serves to spread out the transmission order ofconsecutive units of 119 bits from the staircase encoded frame, which increases the resilience of thesystem to bursts of errors.

Figure 29: Convolution interleave

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The CI is of depth 16, that is, it consists of 16 parallel delay lines, as illustrated in Figure 30.

Figure 30: Convolution interleave
Each delay operator “D” represents a storage element of
delays operators are deleted.

9b From one row to the next lower row, two

At time 𝑖, the input and output switches are aligned at row 𝑏𝑖 :••••A block of 119b is read from row 𝑏𝑖
The contents of row 𝑏𝑖 are shifted to the right by 119b
A block of 119b is written to row 𝑏𝑖
The switch position is updated to 𝑏𝑖+1 = 𝑏𝑖 + 1 (𝑚𝑜𝑑 16)

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Initialization of the convolutional interleave switches (to their topmost positions) is defined to occur atthe start of every DSP super frame, which contains 5 SC-FEC blocks (i.e. immediately prior to processing
the first row in Figure 27). Since 10976 is evenly divisible by the depth of the CI (i.e. 16), the switches will
wrap around to this position at the start of every ZR frame. The start of the DSP super frame emitted fromthe CI will align with the first block of data emitted following a re-initialization of the interleaving switches.
119

119

Convolutional
Interleaver

119b

Hamming
Encoder

10976

10970

ZR Frame bits assigned
row-by-row, read out
row-by-row to
convolutional
interleaver

Hamming Payload
Area

Hamming Parity

119b

9

6

6x119 Pad

Figure 31: Hamming FEC frame format
The 119b outputs of the convolutional interleave are encoded by a systematic (128,119) double-extended
Hamming code.

10.5 Inner Hamming CodeThe inner FEC of C-FEC is a double-extended Hamming Code SD-FEC (128,119), increasing NCG from 9.4
dB to ~10.8 dB with ~7.56% added overhead.

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The systematic double-extended Hamming code is most naturally defined in terms of its parity-checkmatrix. Consider the function 𝑔 which maps an integer 𝑖, 0 ≤ 𝑖 ≤ 127, to the column vector:
𝑠0,𝑖
𝑠1,𝑖
𝑔(𝑖) = 𝑠 ⋮ ,
6,𝑖
𝑠7,𝑖
[1]
where,

𝑖 = 64𝑠6,𝑖 + 32𝑠5,𝑖 + ⋯ + 2𝑠1,𝑖 + 𝑠0,𝑖 ,
and,𝑠7,𝑖 = (𝑠0,𝑖 ∧ 𝑠2,𝑖 ) ∨ (𝑠̅̅̅̅𝑠1,𝑖 ∧ ̅̅̅̅)𝑠2,𝑖 ∨ (𝑠0,𝑖 ∧ 𝑠1,𝑖 ∧ ̅̅̅̅).
𝑠2,𝑖0,𝑖 ∧ ̅̅̅̅The parity-check matrix is then a 9×128 binary matrix:
𝐻 = [𝑔(0): 𝑔(62), 𝑔(64): 𝑔(94), 𝑔(96): 𝑔(110), 𝑔(112): 𝑔(118), 𝑔(120), 𝑔(122), 𝑔(124),
𝑔(63), 𝑔(95), 𝑔(111), 𝑔(119), 𝑔(121), 𝑔(123), 𝑔(125): 𝑔(127)]
where g(a):g(b) represents:[g(a),g(a+1),g(a+2),…,g(b)]To obtain the encoder matrix 𝐺, we calculate
𝑃 = 𝐵[𝑔(0): 𝑔(62), 𝑔(64): 𝑔(94), 𝑔(96): 𝑔(110), 𝑔(112): 𝑔(118), 𝑔(120), 𝑔(122), 𝑔(124)]
where,
B=[ 𝑔(63), 𝑔(95), 𝑔(111), 𝑔(119), 𝑔(121), 𝑔(123), 𝑔(125): 𝑔(127)]−1
Finally, the generator matrix of the Hamming code is,
𝐺 = [𝐼; 𝑃𝑇 ],and a 119-bit message,𝑏 = [𝑏0 , 𝑏1 , … , 𝑏118 ]is encoded to the 128-bit code word.
𝑐 = [𝑐0 , 𝑐1 , … , 𝑐127 ] = 𝑏𝐺

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11 DP-16QAM Symbol mapping and polarization distribution
Each 128-bit code word is mapped to 16 DP-16QAM symbols (S),𝑆 = [𝑠0 , 𝑠1 , … , 𝑠15 ],where,••••(𝑐8𝑖 , 𝑐8𝑖+1 ) maps to the in-phase (I) component of the X-pol of 𝑠𝑖(𝑐8𝑖+2 , 𝑐8𝑖+3 ) maps to the quadrature-phase (Q) component of the X-pol of 𝑠𝑖(𝑐8𝑖+4 , 𝑐8𝑖+5 ) maps to the I component of the Y-pol of 𝑠𝑖(𝑐8𝑖+6 , 𝑐8𝑖+7 ) maps to the Q component of the Y-pol of 𝑠𝑖

In each signaling dimension, we define the following mapping from binary label to symbol amplitude:( , )→− ,( , )→− ,( , )→+ ,( , )→+This mapping is further detailed in Table 8 below:(𝒄𝟖𝒊 , 𝒄𝟖𝒊+𝟏, 𝒄𝟖𝒊+𝟐, 𝒄𝟖𝒊+𝟑 ) 𝑜𝑟 (𝒄𝟖𝒊+𝟒 , 𝒄𝟖𝒊+𝟓, 𝒄𝟖𝒊+𝟔, 𝒄𝟖𝒊+𝟕 )(0,0,0,0)(0,0,0,1)(0,0,1,0)(0,0,1,1)(0,1,0,0)(0,1,0,1)(0,1,1,0)(0,1,1,1)(1,0,0,0)(1,0,0,1)(1,0,1,0)(1,0,1,1)(1,1,0,0)(1,1,0,1)(1,1,1,0)(1,1,1,1)

I
-3
-3
-3
-3
-1
-1
-1
-1
3
3
3
3
1
1
1
1

Q
-3
-1
3
1
-3
-1
3
1
-3
-1
3
1
-3
-1
3
1

Table 8: In-phase (I) and quadrature phase (Q) symbol amplitude
11.1 Interleaving DP-16QAM Symbols
The DP-16QAM symbols are time-interleaved, to de-correlate the noise between consecutively received
symbols, as well as to uniformly distribute the symbols (mapped from a single Hamming code word)
between pilot symbols.

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Prior to Fame Alignment Word (FAW) and pilot insertion, each frame consists of 10976×16 DP-16QAM
symbols. The symbol interleave performs an 8-way interleaving of symbols from Hamming code words.

S0,1

.. .

S0,14

S0,15

S1,0

S1,1

.. .

S1,14

S1,15

S2,0

S2,1

.. .

S2,14

S2,15

S7,0

S7,1

.. .

S7,14

S7,15

S8,0

S8,1

. ..

S8,14

S8,15

S9,0

S9,1

. ..

S9,14

S9,15

S10,0

S10,1

. ..

S10,14

S10,15

S15,0

S15,1

S15,14

S15,15

.. .

S0,0

. ..

8-way
interleaved
Hamming
Codewords

. ..

...
Figure 33: Hamming code 8-way interleave

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12 DSP framing
A DSP super-frame is defined as a set of 181888 symbols in each of the X/Y polarization. A DSP sub-frame
consists of 3712 symbols. A DSP super-frame thus consists of 49 DSP sub-frames.
Pilot symbols are inserted every 32 symbols, starting with the first symbol of each DSP super-frame. The
first 11 symbols of the DSP sub-frame can also be used for training (e.g. frame acquisition). The first symbolof the Training Sequence (TS) is a Pilot Symbol (PS).
•••

Every DSP subframe has the same structure based on a fixed TS with the first symbol processed
as a pilot.
The TS includes 11 QPSK symbols for each polarization. The TS is different between X and Y
polarizations
The PS sequence includes (1+115) QPSK symbols based on PRBS. The first TS symbol is also thefirst symbol of the PS sequence.

12.1 First DSP sub-Frame
The first DSP sub-frame of the super-frame includes a 22 symbol Frame Alignment Word (FAW) used toalign to the 5 SC-FEC Frames. 76 additional symbols are reserved for future use/innovation.
The First DSP sub-frame includes:• 22 symbols used as the Super Frame Alignment Word (FAW). The FAW is different between X andY polarizations.
• 76 symbols are reserved to be used for future proofing and for innovation. These symbols shouldbe randomized to avoid strong tones. These symbols should be selected from 16QAM modulation.
Since 1st symbol isknown QPSK symbol it
can be processed as a
Pilot

11 symbols as training sequen ce

Pilot Symbols

22 symbols as sup er-frame alignment word

Information, FEC parity Symbols

76 symbols as reserved for future use

Seeds for pilot PRBS
selected so that this is asequence

FAW + reserved +3 pilot = 98 symbols

11

21

11

32 Symbols

30

32 Symbols

1

31
32 Symbols

1 15

16 1

32 Symbols

31
32 Symbols

1

31
32 Symbols

3712 symbols = 116 × 32 symbols
FAW(22 + 1 Pilot)(76 reserved + 2 pilot) = 78

Figure 34: First DSP sub-frame of super-frame

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12.1.1FAW Sequence
Index FAW X FAW Y Index FAW X FAW Y
1
2
3
4
5
6
7
8
9
10
11

3 - 3j3 + 3j3 + 3j3 + 3j3 - 3j3 - 3j-3 - 3j
3 + 3j-3 - 3j-3 + 3j-3 + 3j

3 + 3j-3 + 3j-3 - 3j-3 + 3j
3 - 3j3 + 3j3 - 3j3 - 3j-3 - 3j
3 - 3j3 + 3j

12
13
14
15
16
17
18
19
20
21
22

3 - 3j-3 - 3j-3 - 3j-3 + 3j
3 + 3j-3 - 3j
3 - 3j-3 + 3j
3 + 3j-3 - 3j-3 + 3j-3 + 3j-3 + 3j
3 + 3j-3 - 3j
3 + 3j-3 - 3j-3 + 3j
3 - 3j-3 - 3j
3 - 3j-3 + 3j

Table 9: FAW sequence
12.2 Subsequent DSP sub-frames.
Each subsequent DSP sub-frame after the first includes an 11 symbol TS, the first symbol of which is a PS.

Since 1 st symbol isknown QPSK symbol it
can be processed as a
Pilot

11 symbols as training sequen ce

Pilot Symbols

Seeds for pilot PRBS
selected so that this is asequence

11

Information, FEC parity Symbols

21

32 Symbols

1

31
32 Symbols

1

31
32 Symbols

Figure 35: DSP sub-frames 2-49 of the DSP super-frame

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12.2.1 Training Sequence
The TS is defined by the following table:

Index
1*
2
3
4
5
6
7
8
9
10
11

Training X-3 + 3j
3 + 3j-3 + 3j
3 + 3j-3 - 3j
3 + 3j-3 - 3j-3 - 3j
3 + 3j3 - 3j3 - 3jTraining Y-3 - 3j-3 - 3j
3 - 3j-3 + 3j-3 + 3j
3 + 3j-3 - 3j-3 + 3j
3 -3j
3 + 3j3 - 3jTable 10: Training symbol sequence*The first symbol of the TS is processed as a pilot

12.3 Pilot Sequence
Training symbols and pilot symbols shall be set at the outer 4 points of the 16QAM constellation. See
Figure 36.
The PS is a fixed PRBS10 sequence mapped to QPSK with different seed values for X/Y.
•••

Seeds are selected so that the pilot and training sequence combined are DC balanced
Seeds are selected so that the first symbol in the training sequence is also the first symbol in
the pilot sequence
The seed is reset at the start of every DSP sub-frame

PRBS10with seed = 0x19E

2 × 116 = 232 bits
are mapped to QPSKPRBS10with seed = 0x0D0

2 × 116 = 232 bits
are mapped to QPSK

01

11

00

10

Figure 36: QPSK mapped Pilot Sequence

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OIF-400ZR-01.0
Table 11 shows the pilot generator polynomial and seed values.
Generator polynomial

Seed X

Seed Y𝒙𝟏𝟎 + 𝒙𝟖 + 𝒙𝟒 + 𝒙𝟑 + 𝟏

0x19E

0x0D0

Table 11: Pilot polynomial and seed

Figure 37 shows the sequencing.

OutputSeed X = 0x19E
Seed Y = 0x0D0

0
0

1
0

1
1

0
1

0
0

1
1

1
0

1
0

1
0

0
0

Out X
0
-3+3i
1
1
+3+3i
1
1
+3 -3i
0
0
-3+3i
1
1
+3-3i
0

Out Y
0
-3-3i
0
0
-3 -3i
0
1
+3-3i
0
1
+3 +3i
1
0
-3-3i
0

1
0
.
.
.

.

1
1

+3-3i

+3+3i

.
.

Figure 37: Pilot seed and sequence

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The complete table is shown below:
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

Pilot X
-3 + 3j
3 + 3j3 - 3j-3 + 3j
3 - 3j3 - 3j-3 - 3j
3 + 3j-3 + 3j
3 + 3j3 + 3j-3 - 3j
3 + 3j3 - 3j3 + 3j3 - 3j3 + 3j3 - 3j-3 + 3j-3 - 3j
3 + 3j-3 + 3j-3 + 3j
3 - 3j-3 + 3j-3 + 3j-3 + 3j-3 + 3j-3 - 3j

Pilot Y
-3-3j
-3-3j
3-3j
3+3j
-3-3j
3+3j
-3+3j
-3+3j
-3-3j
3+3j
3+3j
-3-3j
3+3j
3+3j
3-3j
3+3j
3+3j
-3+3j
-3-3j
3-3j
3-3j
3+3j
-3+3j
3-3j
3-3j
3+3j
-3+3j
3+3j
3+3j

Index
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58

Pilot X3 - 3j-3 - 3j
3 + 3j-3 + 3j-3 + 3j-3 + 3j
3 - 3j3 - 3j-3 - 3j-3 - 3j
3 - 3j-3 - 3j
3 - 3j-3 + 3j-3 + 3j-3 - 3j-3 + 3j-3 - 3j
3 + 3j3 + 3j-3 + 3j
3 - 3j3 - 3j3 - 3j-3 - 3j
3 - 3j3 + 3j-3 + 3j-3 - 3j

Pilot Y
3-3j
-3+3j
-3-3j
3-3j
-3-3j
-3-3j
3-3j
3-3j
-3-3j
3+3j
-3-3j
3-3j
3-3j
-3-3j
-3-3j
3+3j
-3+3j
3+3j
-3+3j
3-3j
-3+3j
3+3j
-3+3j
-3+3j
3+3j
-3+3j
-3+3j
-3-3j
3-3j

Index
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87

Pilot X3 - 3j3 + 3j3 - 3j-3 - 3j
3 - 3j-3 + 3j
3 - 3j3 + 3j3 - 3j-3 + 3j
3 - 3j-3 + 3j
3 + 3j-3 - 3j-3 - 3j
3 - 3j-3 + 3j
3 - 3j-3 + 3j-3 - 3j
3 + 3j3 + 3j3 + 3j-3 - 3j-3 - 3j
3 + 3j3 - 3j-3 + 3j
3 + 3jPilot Y
3-3j
-3+3j
3+3j
-3-3j
3+3j
-3+3j
3-3j
3+3j
-3-3j
3-3j
-3+3j
-3+3j
-3+3j
-3-3j
-3+3j
3+3j
-3-3j
-3-3j
-3-3j
3+3j
-3-3j
-3-3j
3-3j
-3-3j
3+3j
-3-3j
-3-3j
-3-3j
3-3j

Index
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116

Pilot X3 - 3j-3 - 3j
3 - 3j3 - 3j-3 + 3j-3 - 3j
3 + 3j-3 - 3j-3 - 3j
3 + 3j-3 + 3j
3 - 3j-3 - 3j
3 + 3j-3 + 3j-3 - 3j-3 - 3j
3 + 3j3 - 3j3 + 3j-3 + 3j-3 - 3j-3 + 3j-3 - 3j-3 + 3j-3 + 3j
3 + 3j3 + 3j-3 - 3j

Pilot Y
-3+3j
-3+3j
3-3j
3+3j
3-3j
3-3j
-3+3j
3-3j
3-3j
-3+3j
3-3j
-3-3j
3+3j
-3-3j
-3+3j
-3+3j
3+3j
-3+3j
3-3j
3+3j
-3+3j
3+3j
-3-3j
-3+3j
3-3j
-3+3j
3+3j
3-3j
3-3j

Table 12: Pilot Sequence
12.4

Channel Mappings

X and Y indicate a pair of mutually orthogonal polarizations of any orientation and I and Q are mutuallyorthogonal phase channels in each polarization. The four data path channels are therefore labeled XI, XQ,
YI, and YQ.
All coherent channel mappings provided in Table 13 are allowed for the Tx signal. The Rx should work in
all cases because the Rx can unambiguously identify the signals polarization and phase, based on the FAW.
The Tx mapping is specified in Table 13 by two designations: [X:Y ; I,Q], where a “:” is used to separate X& Y, a “,” is used to separate I & Q.
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Table 13 does not allow interleaving of the channels by polarization since this would add a non-essential
level of complexity to the Rx digital processing.
Mapping X:Y
[0,x]

X:Y

[1,x]

Y:X

I,Q

Notes
Pol. cannot be interleaved[x,0]

I,Q:I,Q

Same across Pol.

[x,1]
[x,2]
[x,3]

Q,I:Q,I
I,Q:Q,I
Q,I:I,Q

Flip across Pol.

Table 13: Channel mappings
12.5 Frame Expansion Rate
The 400ZR optical signal is DP-16QAM with a symbol rate of 59.843750000 Gbaud (478.750 Gbps) per
polarization. Figure 38 and Table 14 provide details on expansion for each functional block.
100GE Domain(+/- 100ppm)

400ZR~478 750 Gb/Sec+/- 20ppm

400ZR Domain(+/- 20ppm)~401.562 Gb/Sec+/- 100ppm~402 489 Gb/Sec+/- 20ppm~401.703 Gb/Sec+/- 20ppm

20479/20480

512/511~429 740 Gb/Sec+/- 20ppm~429 505 Gb/Sec+/- 20ppm

5485/5140

5488/5485~462 241 Gb/Sec+/- 20ppm
29/28

128/119514/544
255/239425 000 000
Gb/SecRS FEC
Decode(544/514)

AM
RemoveGMP
map

400ZR Container
AM/PAD/OH+Payload+CRC32+MBAS

5 x 244,702
bits

401 542 892 456
bit/s

401 703 640 510
bit/s

SC-FEC
Encoder&Interleaver

Insert34b(Zero s)5x
401 562 500
bit/s

261 086

244 702244 736

Remove34b(Zero s)5 x 261 086
bits

261 120402 489 753 310
bit/s

1 305 430
Bits
(10970 x 119)5 x 261 086
bits

Insert PAD
6 x 119b

Scrambler

1 306 144
Bits
(10976 x 119)

Convolution
Interleave

1 306 144
Bits
(10976 x 119)

Hamming(128/119)

1 306 144
Bits
(10976 x 119)

32/31

Gray Map
andInterleave

1 404 928
Bits
(10976 x 128)

175 616
Symbols

Insert 588
FAW/TS/RES
Symbols

176 204
Symbols

Insert Pilots

178176X pol

175 616
Symbols

Insert 588
FAW/TS/RES
Symbols

176 204
Symbols

Insert Pilots

178176

Y pol

Polarization
Distribution

351 232
Symbols(3b/Sym)

351 232
Symbols(3b/Sym)

176 204
Symbols(3b/Sym)

181 888
Symbols(3b/Sym)

400GE – ZR bit rate; 156.25Mbit/s x 383 x 8 +/-20ppm

Figure 38: 400ZR expansion rates

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55

OIF-400ZR-01.0
Table 14 details the bit level expansion.
GMP

FlexO/400ZR frame+100ppm
Nominal-100ppm

400GBASE-R
Client -rate[bps]

After Client FEC After 400GE AM
Termination
Removal
[bps]
[bps]

Before 400ZR
AM/PAD/OH
insert [bps]Before SC-FEC +MBAS + CRC32[bps]

425 042 500 000
425 000 000 000
424 957 500 000

401 602 656 250 401 583 046 745
401 562 500 000 401 542 892 456
401 522 343 750 401 502 738 167

401 711 674 583
401 703 640 510
401 695 606 437

402 497 803 105
402 489 753 310
402 481 703 515

Before [6 x119b ] pad
insert [bps]BeforeHamming[bps]

Before
FAW/TS/RES[bps]

429 513 706 231
429 505 116 129
429 496 526 027

429 748 627 128
429 740 032 328
429 731 437 527

462 250 624 138
462 241 379 310
462 232 134 483

Before Pilot
400ZR Bit rate
Symbol insertion
[bps]
[bps]

400ZR Baud rate[bps]

463 798 338 281
463 789 062 500
463 779 786 719

059 844 946 875
059 843 750 000
059 842 553 125

478 759 575 000
478 750 000 000
478 740 425 000

Table 14: 400ZR expansion rate table

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56+20ppmNominal-20ppmOIF-400ZR-01.0

13 Optical Specifications
The 400ZR optical parameters are organized by Application Code (defined in Table 15) for Tx, Rx, and the
Optical Channel (black link).
Ref.

Application Description

Minimum Reach

Application Code - Name

13.0.100120 km or less, amplified, pointto-point, DWDM noise limited
links.

80 km

13.0.110

Unamplified, single wavelength,
loss limited links.

11dB loss budget minus
link impairments

0x01 – 400ZR, DWDM amplified
0x02 – 400ZR, Single wavelength,
Unamplified

Table 15: 400ZR application codes
Note: All specifications are defined after calibration and compensation, at EOL over temperature
and wavelength. All specifications are based on default grid spacing (defined in 13.1.110).
Bold italicized items found in tables indicate a reference to a Coherent Management Interface Spec[1](CMIS) defined function, state, or status condition.

13.1 400ZR, DWDM amplified - Application Code (0x01):
This section defines the optical parameters for the DWDM amplified application code (0x01).

13.1.1 Optical channel specifications – Black Link
Ref.

Parameter

Default

Min

Max

Unit

13.1.100

Channelfrequency

193.7

191.3

196.1

THz

13.1.11013.1.111(optional)
13.1.112(optional)
13.1.120

Channelspacing†

100

GHz

See Section 15.1

75

GHz

See Section 15.2

75

GHz

See Section 15.3km

Pre-FEC BER 1.25E-2 or lower.
Single mode fiber. Specified for linkbudgeting purposes only.
Amplified Link – Noise limited

10-15

Post FEC BER

13.1.130

Fiber type13.1.140

Target reachwww.oiforum.com

Conditions/Comments

G.652
80

-

57

OIF-400ZR-01.0

Ref.

Parameter

Default

Min

Max

Unit

Conditions/Comments
Nominal central
frequency minus
Maximum Spectral
Excursion

Nominal central
Nominal central frequency frequency plus
Maximum Spectral
Excursion

13.1.150

Ripple2.0

dB-10Log(Loss) dB

Maximum
Ripple0Offset from nominal
Central Frequency(GHz)13.1.160
13.1.161

13.1.162

13.1.170

13.1.17113.1.172

Chromatic
Dispersion
Optical Return
Loss at Ss
Discrete
Reflectance
between Ss
and RsMaximum
Instantaneous
Differential
Group Delay(DGD)
Polarization
Dependent
Loss (PDL)
Polarization
Rotation Speed0(See definition 13.3.4)
Frequency dependent change inphase velocity due to fiber.

2400

ps/nm

24

dB

(See definition 13.3.5)

-27

dB

(See definition 13.3.6)

28

ps(See definition 13.3.7)

2

dB(See definition 13.3.8)

50krad/s(See definition 13.3.9)

13.1.180

Inter-channel
Crosstalk at Rs-8dB(See definition 13.3.10)
Ref. Clause 9.6 and Fig 9-17 in ITU-T
G.sup39.

13.1.181

Interferometric
Crosstalk-35

dB(See definition 13.3.11)

Table 16: Optical channel specifications†

For channel spacing of 100 GHz on a fiber, the allowed channel frequencies (in THz) are defined by 193.1 + n × 0.1
where n is a positive or negative integer including 0. For 400ZR modules, n = 30 to -17 in steps of 1. The specified 48
× 100GHz DWDM application channels are as defined in Section 15.1.
†

For channel spacing of 75 GHz or more on a fiber, the allowed channel frequencies (in THz) are defined by 193.1 +3n × 0.025 where n is a positive or negative integer including 0. For 400ZR modules, 3n = 120 to -69. The reference
64 × 75 GHz DWDM application channels are as defined in Section 15.2.

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OIF-400ZR-01.0†

For the flexible DWDM grid, the allowed frequency slots have a nominal central frequency (in THz) defined by 193.1+ n × 0.00625 where n is a positive or negative integer including 0 and 0.00625 is the nominal central frequency
granularity in THz. Slot width is defined by 12.5 × m where m is a positive integer and 12.5 is the slot width granularity
in GHz. Any combination of frequency slots is allowed if no two frequency slots overlap. Example 100 GHz and 75
GHz DWDM applications with offset grid channels are defined in Section 15.3.

13.1.2 Transmitter Optical Specifications
Note: All Tx optical specifications are based on default grid spacing of 100GHz (see 13.1.110). For thisgrid spacing no Tx shaping is required. If optical shaping is applied on Tx (e.g. for operation at other gridsettings) a matched Rx equalizer setting must also be applied on Rx or additional OSNR penalty may be
incurred.
Ref.
13.1.200

ParameterLaserfrequency
accuracy

Min

Max

Unit

-1.8

1.8

GHz

Conditions/Comments
Offset from channel frequency set point.
The receiver LO has the same frequency
accuracy.
Nominal central
frequency minus
Maximum Spectral
Excursion
0Power Relative to Peak (dB)-2Nominal central
Nominal central frequency frequency plus
Maximum Spectral
Excursion
32 GHz32 GHz

-4
-6
-8

-10
-12
-14
-16

13.1.201

Tx Spectral
Excursion

-18

32

GHz

Offset from nominal
Central Frequency(See definition 13.3.2)
Measured between the nominal central
frequency of the channel and the -3.0dB
points of the transmitter spectrum
furthest from the nominal central
frequency measured at point Ss.
Includes Laser frequency accuracy(13.1.200) error value from nominal
center frequency.

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OIF-400ZR-01.0
Ref.

Parameter

Min

Max

Unit

Conditions/Comments

Frequency[Hz]

13.1.210

13.1.212

Laser
frequency
noise

Laser RIN

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1- sided Noise power
spectral density[Hz2/Hz]
1.0e+02
1.0e+111.0e+04
1.0e+09
1.0e+06
1.0e+06
1.0e+076.0e+05
1.0e+08
1.6e+05
1.0e+09
1.6e+05
Mask does not apply to spurs.
Measurement Resolution BW shall be
between 10-1 and 10-6 of the frequency
of interest.

See
Mask

-145
-140

dB/Hz

High frequency component of the phasenoise (100MHz and above) is consistent
with a 500 kHz laser line width. The
receiver LO has the same linewidth.
0.2GHz < f < 10GHz Avg
0.2GHz < f < 10GHz Peak60

OIF-400ZR-01.0
Ref.

Parameter13.2.213a

Tx clock phasenoise (PN):
Maximum PN
mask for low
frequency PN

Min

Max

See
mask

Unit

dBc/HzConditions/Comments

PN [dBc/Hz]
-100
-120
-130
-140

Frequency [Hz]1.00E+04
1.00E+05
1.00E+06
1.00E+07

Phase noise, ℒ(𝑓),
fc =

fbaud
= ~467.53 MHz
128

Mask does not apply to spurs,
broadband phase noise only. Spurs are
considered separately as per 13.1.213b
and 13.1.213c

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OIF-400ZR-01.0
Ref.

Parameter

Min

Max

Unit

Conditions/Comments
rms random jitter:
ℒ(𝑓)

𝑓

1

𝜎𝑟𝑗 = 2𝜋𝑓 √2 ∙ ∫𝑓 2 10 10 𝑑𝑓𝑐1

rms periodic jitter (spurs):
𝜎𝑝𝑗,𝑖 =

13.1.213b

Tx clock phasenoise (PN);
Maximum
total
integrated
RMS phase
jitter between
10kHz and
10MHz

1
√2𝜋𝑓𝑐

𝑠𝑖

⋅ 1020where,

600

fs

f1 = 10kHz,
f2 = 10MHz,
fbaud
fc =
= ~467.53MHz
128ℒ(f) = phase noise (PN)𝑠𝑖 = individual spur in [dBc]rms total jitter:𝑁𝜎𝑡𝑗 = √𝜎𝑟𝑗 2 + ∑ 𝜎𝑝𝑗,𝑖 2
𝑖=1

where,
N = total number of spurs.

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62

OIF-400ZR-01.0
Ref.

Parameter

Min

Max

Unit

Conditions/Comments
rms random jitter:
ℒ(𝑓)

𝑓

1

𝜎𝑟𝑗 = 2𝜋𝑓 √2 ∙ ∫𝑓 2 10 10 𝑑𝑓
1𝑐

rms periodic jitter (spurs):
𝜎𝑝𝑗,𝑖 =

13.1.213c

Tx clock phasenoise (PN):
Maximum
total
integrated
RMS phase
jitter between
1MHz and200MHz) Tx

1
√2𝜋𝑓𝑐

𝑠𝑖

⋅ 1020where,

250

fs

f1 = 1MHz,
f2 = 200MHz,
𝑓𝑏𝑎𝑢𝑑
fc =
= 467.53𝑀𝐻𝑧,
128ℒ(f) = phase noise (PN),𝑠𝑖 = individual spur in [dBc]rms total jitter:𝑁𝜎𝑡𝑗 = √𝜎𝑟𝑗 2 + ∑ 𝜎𝑝𝑗,𝑖 2
𝑖=1
where,
N = total number of spurs.

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63

OIF-400ZR-01.0
Ref.

Parameter

Min

Max

Unit

Conditions/Comments
The baseband Tx spectral shape in thisexcess bandwidth shall meet or exceed
the following conditions:
The magnitude of the spectrum in thefrequency range:
1
9
≤𝑓≤
2𝑇
16𝑇

shall meet187
|𝐻(𝑓)| ≥ 𝐻(0)√ {1 + cos [8𝜋𝑇 ((
)−
)]} ,
2
15𝑇
16𝑇
1
8
≤ |𝑓| ≤
2𝑇
15𝑇

13.1.215

13.1.22013.1.22113.1.222

Minimum
ExcessBandwidth1(See Mask)

Allowable
output signal
power window
Total output
power with Tx
disabled
Total output
power during
wavelengthswitchingwww.oiforum.com

12.5

-10

1
7
|𝐻(𝑓)| ≥ 𝐻(0)√ {1 + cos [8𝜋𝑇 (|𝑓| −
)]} ,
2
16𝑇
8
9
≤ |𝑓| ≤
15𝑇
16𝑇%

where T denotes the symbol period of thesignal.

-6dBm

Measured at optical connector.

-20

dBm

Tx Disable == false

-20

dBm

Applicable to modules with tunableoptics.

64

OIF-400ZR-01.0
Ref.

ParameterMin

13.1.230

Inband (IB)
OSNR

34

dB/0.1nm

13.1.231

Out-of-band(OOB) OSNR

23

dB/0.1nm

13.1.240

Transmitterreflectance

13.1.241

Transmitterback reflection
tolerance

13.1.250
13.1.260

13.1.270a

13.1.270b

13.1.271
13.1.272
13.1.273-20

Transmitterpolarization
dependent
power
X-Y Skew

Unit

Conditions/Comments
Inband OSNR is defined within the
bandwidth of the Tx spectral excursion
given in (13.1.201)
The IB OSNR is referenced to an optical
bandwidth of 0.1nm @ 193.7 THz or 12.5
GHz.
Channel total power over peak noise
power in the whole frequency range
measured with 0.1 nm resolution
bandwidth.
The OOB OSNR is referenced to an
optical bandwidth of 0.1nm @ 193.7 THz
or 12.5 GHz.

dB

Looking into the Tx

-24

dB

Light reflected relative to Tx output
power back to transmitter while still
meeting Tx optical performancerequirements.

1.5

dB

Power difference between X and Y
polarization.

5

ps
𝑷𝒆𝒙𝒄𝒆𝒔𝒔 =DC I-Q offset(mean perpolarization)

-26

dB

𝟐
𝐈𝐦𝐞𝐚𝐧
+ 𝐐𝟐𝐦𝐞𝐚𝐧
𝐏𝐒𝐢𝐠𝐧𝐚𝐥

𝑰𝑸𝒐𝒇𝒇𝒔𝒆𝒕 = 𝟏𝟎 𝐥𝐨𝐠 𝟏𝟎 (𝐏𝐞𝐱𝐜𝐞𝐬𝐬 )I-Q
instantaneous
offsetMean I-Q
amplitude
imbalanceI-Q phase
imbalance
I-Q Skew

Max

-5

-20

dB

1

dB

+5

degrees

0.75

psSame formula definition as 13.1.270a,
however, any averaging period shall be <1us to be consistent with the timescalesof Rx DSP operations. Specification
applies at any point in time. Allows formodulator bias controls/errors.

Table 17: Tx optical specifications
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65

OIF-400ZR-01.0
1

The minimum excess bandwidth is specified to guarantee multi-vendor clock recovery
interoperability. It is required because the Tx spectrum mask is not defined by this IA. For operation on
a 75 GHz grid this specification will be modified or removed and replaced by a Tx spectrum mask.

13.1.3 Receiver Optical Specifications
The receiver optical tolerance specifications include margin for Tx and line impairments.
Note: All Rx optical specifications are based on default grid spacing of 100GHz (see 13.1.110). When
operating at other grid settings additional compensation may be required or additional penalties may be
incurred.
Ref.

13.1.300

Parameter
Frequency
offsetbetweenreceived
carrier and LO

Min

Max

Unit

Conditions/Comments

-3.6

+3.6

GHz

Acquisition Range.

0dBm

13.1.310

Input power
range

-12

13.1.320

Input
sensitivity-1213.1.330

OSNR
Tolerance

13.1.340
13.1.341
13.1.342

Optical returnloss
CD Tolerance
Optical path
OSNR penalty
tolerance

www.oiforum.com

dBm

26

dB/0.1nm

20

dB

2400

ps/nm
0.5

dB

Signal power of the channel at the
OSNR performance defined in(13.1.330).
Input power needed to achieve post
FEC BER per (13.1.120) when OSNR
Tolerance > (13.1.330).
At C-FEC threshold (ref. Section 10).
See Definition in Section 13.3.2
The OSNR tolerance is referenced toan optical bandwidth of 0.1nm @193.7 THz or 12.5 GHz.
Optical reflectance at Rx connector
input.
Tolerance to Chromatic Dispersion.
OSNR penalty tolerance over
(13.1.330) due to interferometriccrosstalk (13.1.181) and chromatic
dispersion (13.1.160).

66

OIF-400ZR-01.0
Ref.

Parameter

Min

Max

Unit

13.1.350

PMD
tolerance(DGD,
SOPMD)

10-ps

13.1.351

Peak PDL
tolerance

3.5

-

dB

13.1.352

Tolerance tochange in SOP

50-

krad/s

13.1.353

Optical input
powertransient
tolerance

+/-2

-

dB

Conditions/Comments
Tolerance to PMD with < 0.5 dB
penalty to OSNR sensitivity (13.1.330).
when change in SP is < 1 rad/ms.
10 ps of average PMD (DGD, SOPMD)
corresponds to:• 33 ps of DGDmax when
SOPMD = 0 ps2.
• 272 ps2 of SOPMD when DGD= 23.3 ps.
Due to the statistical nature of PMD
the DGDmax to DGDmean Ratio is
calculated at 3.3 (4.1 x 10-6 probability
that DGDmean being greater than
DGDmax).
Tolerance to peak PDL with < 1.3 dB
penalty to OSNR sensitivity (13.1.330)
when change in SOP is < =1 rad/ms.
Test configuration - PDL emulator
applied before noise loading.
Tolerance to change in SOP with <0.5
dB additional OSNR penalty over all
PMD and PDL values defined in(13.1.350) and (13.1.351).
Tolerance to change in input powerwith < 0.5 dB penalty to OSNR
sensitivity (13.1.330).
When transient received power iswithin range defined by input power
range (13.1.310).
Rise/fall times of power change
defined by 20-80% of 50 us or slower.

Table 18: Rx optical specifications
1

Italicized items indicate a reference to a Coherent Management Interface Spec [1] (CMIS) defined
function, state, or status condition.

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OIF-400ZR-01.0

13.1.4 Module Requirements Tx - (Informative)
The following specifications provide guidance for modules based on the 400ZR IA.
Ref.

Parameter13.1.400

Min

Max

Unit

Transmitter laser disable
time

100

ms

13.1.410

Transmitter turn-up timefrom warm start180s

13.1.411

Transmitter turn-up timefrom cold start200s

13.1.420

Transmitter wavelengthswitching time180s

13.1.430

Output power monitor Accuracy

2.0

dB

-2.0

Conditions/Comments
The maximum transmitter
turn-off time from any
condition that results in
Tx_Disable==true to reach
the Tx output power given by(13.1.221).
Rx shall remain locked andthus LO must remain
enabled.
The maximum time from
ModuleLowPwr to
DataPathActivated state.
The maximum time from deassertion of ResetS == false to
DataPathActivated state
while LoPwrS == false.
The maximum time to change
wavelengths including turnup time.
Applicable to modules withtunable optics.
Total output power
measurement including all
ASE contribution.
Measurement accuracy does
not contribute to allowable
output power signal window.

Table 19: 400ZR module – Tx specifications

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68

OIF-400ZR-01.0

13.1.5 Module Requirements Rx - (Informative)
The following specifications provide guidance for modules based on the 400ZR IA.
Ref.
Parameter
Default
Min
Max
Unit Conditions/Comments
Upon Rx_LOS de-assert,
Receiver turn-up time
13.1.510
10s
Receiver has been turned
from warm start
up previously.
From module reset, with
Receiver turn-up time
13.1.511
200svalid optical input signal
from cold start
present.
Over the superset of
input power range(13.1.310), receiversensitivity 13.1.320) andthe optical Rx_LOS Assert
Input total power
13.1.530
-4.0
4.0
dB
threshold range (13.1.532
monitor - Accuracy
assuming Min accuracy –i.e. Real input total power
range of 0dBm to -14dBm
at the default Optical
Rx_LOS Assert Threshold.
The module reports the
Input Channel power
13.1.531
-4.0
4.0
dB
channel power asmonitor - Accuracy
received by the module.
13.1.532

Optical Rx_LOS Assert-18
Threshold†13.1.533

Optical Rx_LOS
Hysteresis

-20
1.0

-16

dBm

Channel Power.

2.5

dBm

Rx_LOS cleared.

Table 20: 400ZR module – Rx specifications†

If a module supports both amplified and unamplified use cases, Optical Rx_LOS thresholds must be
programmable to support different ranges for each application.

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OIF-400ZR-01.0

13.2 400ZR, Single wavelength, Unamplified - Application Code (0x02):
This section defines the optical parameters for application code 0x02.

13.2.1 Optical channel specifications
Ref.
13.2.100

Parameter
Channel frequency

13.2.120

Post FEC BER

13.2.130

Fiber type13.2.160

Chromatic
Dispersion

13.2.161
13.2.162

13.2.170

13.2.172

Default
193.7

Min

Max
10-15

G.652
0

Optical Return
Loss at Ss
Discrete
Reflectance
between Ss and Rs
Maximum
Instantaneous
Differential Group
Delay (DGD)
Polarization
Rotation Speed

1200

Unit
THz

Conditions/Comments

Pre-FEC BER 1.25E-2 orlower.
Single mode fiber.
Frequency dependent
ps/nm change in phasevelocity due to fiber

24

dB(See definition 13.3.5)

-27

dB

(See definition 13.3.6)

16

ps(See definition 13.3.7)

50

krad/s(See definition 13.3.9)

Table 21: Optical channel specifications

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OIF-400ZR-01.0

13.2.2 Transmitter Optical Specifications
Ref.
13.2.200

13.2.210

ParameterLaserfrequency
accuracyLaserfrequency
noise

Min

Max

Unit

-1.8

1.8

GHz

Conditions/Comments
Offset from channel frequency set point.
The receiver LO has the same frequency
accuracyFrequency
Frequency[Hz]
Noise [Hz2/Hz]
1.0e+02
1.0e+111.0e+04
1.0e+09
1.0e+06
1.0e+06
1.0e+076.0e+05
1.0e+08
3.2e+05
1.0e+09
3.2e+05
Mask does not apply to spurs.
Measurement Resolution BW shall be
between 10-1 and 10-6 of the frequency ofinterest.

See
Mask

High frequency component of the phasenoise (100MHz and above) is consistent
with a 1 MHz laser line width. The receiver
LO has the same linewidth.
13.2.212

Laser RIN

www.oiforum.com

-145
-140

dBc/Hz0.2GHz < f < 10GHz - Avg
0.2GHz < f < 10GHz - Peak71

OIF-400ZR-01.0
Ref.

Parameter13.2.213a

Tx clockphase noise(PN):
Maximum
PN mask forlowfrequency
PN

Min

Max

See
mask

Unit

dBc/HzConditions/Comments

PN [dBc/Hz]
-100
-120
-130
-140

Frequency [Hz]1.00E+04
1.00E+05
1.00E+06
1.00E+07

Phase noise, ℒ(𝑓),
fc =

fbaud
= ~467.53 MHz
128

Mask does not apply to spurs, broadband
phase noise only. Spurs are consideredseparately as per 13.2.213b and 13.2.213c

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72

OIF-400ZR-01.0
Ref.

Parameter

Min

Max

Unit

Conditions/Comments
rms random jitter:
ℒ(𝑓)

𝑓

1

𝜎𝑟𝑗 = 2𝜋𝑓 √2 ∙ ∫𝑓 2 10 10 𝑑𝑓𝑐1

rms periodic jitter (spurs):
𝜎𝑝𝑗,𝑖 =

13.2.213b

Tx clockphase noise(PN);
Maximum
total
integrated
RMS phase
jitterbetween
10kHz and
10MHz

1
√2𝜋𝑓𝑐

𝑠𝑖

⋅ 1020where,

600

f1 = 10kHz,
f2 = 10MHz,
fbaud
fc =
= ~467.53MHz
128ℒ(f) = phase noise (PN)𝑠𝑖 = individual spur in [dBc]fs

rms total jitter:𝑁𝜎𝑡𝑗 = √𝜎𝑟𝑗 2 + ∑ 𝜎𝑝𝑗,𝑖 2
𝑖=1

where,
N = total number of spurs.

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Ref.

Parameter

Min

Max

Unit

Conditions/Comments
rms random jitter:
ℒ(𝑓)

𝑓

1

𝜎𝑟𝑗 = 2𝜋𝑓 √2 ∙ ∫𝑓 2 10 10 𝑑𝑓
1𝑐

rms periodic jitter (spurs):

13.2.213c

Tx clockphase noise(PN):
Maximum
total
integrated
RMS phase
jitterbetween
1MHz and200MHz) Tx

𝜎𝑝𝑗,𝑖 =

1
√2𝜋𝑓𝑐

𝑠𝑖

⋅ 1020where,

250

fs

f1 = 1MHz,
f2 = 200MHz,
𝑓𝑏𝑎𝑢𝑑
fc =
= 467.53𝑀𝐻𝑧,
128ℒ(f) = phase noise (PN),𝑠𝑖 = individual spur in [dBc]rms total jitter:𝑁𝜎𝑡𝑗 = √𝜎𝑟𝑗 2 + ∑ 𝜎𝑝𝑗,𝑖 2
𝑖=1
where,
N = total number of spurs.

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Ref.

Parameter

Min

Max

Unit

Conditions/Comments
The baseband Tx spectral shape in thisexcess bandwidth shall meet or exceed thefollowing conditions:
The magnitude of the spectrum in thefrequency range:
1
9
≤𝑓≤
2𝑇
16𝑇

shall meet187
|𝐻(𝑓)| ≥ 𝐻(0)√ {1 + cos [8𝜋𝑇 ((
)−
)]} ,
2
15𝑇
16𝑇
1
8
≤ |𝑓| ≤
2𝑇
15𝑇

13.2.215

13.2.22013.2.221

Minimum
ExcessBandwidth1(See Mask)

Allowable
output signal
power
window
Total output
power with
Tx disabled

13.2.230

Inband (IB)
OSNR

13.2.240

Transmitterreflectancewww.oiforum.com

1
7|𝐻(𝑓)| ≥ 𝐻(0)√ {1 + cos [8𝜋𝑇 (|𝑓| −
)]} ,
2
16𝑇
8
9
≤ |𝑓| ≤
15𝑇
16𝑇

12.5

-9

%

where T denotes the symbol period of thesignal.

0dBm

Measured at optical connector.

-20

dBm

Tx Disable == false

dB/0.1nm

The 0.1nm bandwidth for the IB OSNR
refers to 193.7 THz or 12.5 GHz optical
bandwidth.

dB

Looking into the Tx

34
-20

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OIF-400ZR-01.0
Ref.
13.2.24113.2.250
13.2.260

13.2.270a

13.2.270b

13.2.271
13.2.272
13.2.273

Parameter
Transmitterbackreflection
tolerance
Transmitterpolarization
dependent
power
X-Y SkewMin

DC I-Q offset(mean perpolarization)

Unit

Conditions/Comments

-24

dB

Light reflected relative to Tx output power
to transmitter while still meeting Tx optical
performance requirements.

1.5

dB

Power difference between X and Y
polarization.

5

ps

-26

dB

𝟐
𝐈𝐦𝐞𝐚𝐧
+ 𝐐𝟐𝐦𝐞𝐚𝐧
𝑷𝒆𝒙𝒄𝒆𝒔𝒔 =𝐏𝐒𝐢𝐠𝐧𝐚𝐥

𝑰𝑸𝒐𝒇𝒇𝒔𝒆𝒕 = 𝟏𝟎 𝐥𝐨𝐠 𝟏𝟎 (𝐏𝐞𝐱𝐜𝐞𝐬𝐬 )I-Q
instantaneous offsetI-Q
amplitude
imbalanceI-Q phase
imbalance
I-Q Skew

Max

-5

-20

dB

1

dB

+5

degrees

0.75

psSame formula definition as 13.2.270a,
however, any averaging period shall be <1us to be consistent with the timescales ofRx DSP operations. Specification applies atany point in time. Allows for modulator bias
controls/errors.

Table 22: Tx Optical specifications
1

The minimum excess bandwidth is specified to guarantee multi-vendor clock recovery
interoperability. It is required because the Tx spectrum mask is not defined by this IA.

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13.2.3 Receiver Optical Specifications
Ref.

Min

Max

Unit

Conditions/Comments

-3.6

+3.6

GHz

Acquisition Range.

13.2.310

Parameter
Frequency offset
between received
carrier and LO
Input power range

-20

0

dBm

13.2.320

Input sensitivity

-20

dBm

13.2.340
13.2.341

Optical return loss
CD Tolerance

20
1200

dB
ps/nm

13.2.342

Optical pathpower penalty

13.2.350

Average PMD(DGD, SOPMD)
tolerance

13.2.351

13.2.352

Signal power of the channel.
Input power needed to achieve post
FEC BER per (13.2.120) when Inband(IB) OSNR > (13.2.230).
Optical reflectance at connector input.
Tolerance to Chromatic Dispersion.
Rx Sensitivity penalty over (13.2.320)
due to reflections and the combined
effects of dispersion (13.2.341).
Tolerance to PMD with < 0.5dB Rx
sensitivity penalty (13.2.320) whenchange in SOP is <= 1 rad/ms.
7 ps of average PMD (DGD, SOPMD)
corresponds to:• 23 ps of DGDmax when
SOPMD = 0 ps2.
• 132 ps2 of SOPMD when DGD= 16.3 ps.
Due to the statistical nature of PMD
the DGDmax to DGDmean Ratio is
calculated at 3.3 (4.1 x 10-6 probability
that DGDmean being greater than
DGDmax).
Tolerance to change in peak PDL with <0.4dB Rx sensitivity penalty (13.2.320)
when change in SOP is <= 1 rad/ms.
Tolerance to change in SOP with <0.3
dB additional power penalty over all
PMD and PDL values defined in(13.2.350) and (13.2.351).

13.2.300

0.5

dB

7

-

ps

Peak PDL
tolerance

1.5

-

dB

Tolerance tochange in SOP

50-

krad/sTable 23: Rx Optical specifications

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13.2.4 Module Requirements Tx - (Informative)
The following specifications provide guidance for modules based on the 400ZR IA.
Ref.

ParameterMin

13.2.400

Transmitter laser disable
time

Max

Unit

100

ms

13.2.410

Transmitter turn-up timefrom warm start180s

13.2.411

Transmitter turn-up timefrom cold start200s

13.2.430

Output power monitor Accuracy

2.0

dB

-2.0

Conditions/Comments
The maximum transmitter
turn-off time from any
condition that results in
Tx_Disable==true to reach
the Tx output power given by(13.2.221).
Rx shall remain locked andthus LO must remain
enabled.
The maximum time from
ModuleLowPwr to
DataPathActivated state.
The maximum time from deassertion of ResetS == false to
DataPathActivated state
while LoPwrS == false.
Total output power
measurement including all
ASE contribution.
Measurement accuracy does
not contribute to allowable
output power signal window.

Table 24: 400ZR module – Tx specifications

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13.2.5 Module Requirements Rx - (Informative)
The following specifications provide guidance for modules based on the 400ZR IA.
Ref.
13.2.510

13.2.511

Parameter
Receiver turn-up
time from warm
start
Receiver turn-up
time from cold
start

Default

Min

Max

Unit

10

s

200

s

13.2.531

Input Channel orTotal powermonitor Accuracy

-4.0

4.0

dB

13.2.532

Optical Rx_LOS-26
Assert Threshold†

-28

-24

dBm

13.2.533

Optical Rx_LOS
Hysteresis

1.0

2.5

dBm

Conditions/Comments
Upon Rx_LOS de-assert,
Receiver has been
turned up previously.
From module reset,with valid optical input
signal present.
Over the superset of
input power range(13.2.310), receiversensitivity (13.2.320),and the optical Rx_LOS
Assert threshold range(13.2.532) assuming
Min accuracy (i.e. real
input total power rangeof 0dbm to -22dBm at
the default Optical
Rx_LOS Assert
Threshold).
Channel or Total Input
Power.
Rx_LOS cleared.

Table 25: 400ZR module – Rx specifications†

If a module supports both amplified and unamplified use cases, Optical Rx_LOS thresholds must be
programmable to support different ranges for each application.

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13.3 Optical Parameter Definitions
13.3.1 The Receiver Optical Signal-to-noise Ratio Tolerance
The receiver OSNR tolerance is defined as the minimum value of OSNR (referred to 0.1 nm @193.7 THz or
12.5 GHz) that can be tolerated while maintaining the maximum BER of the application. This must be met
for all powers between the maximum and minimum mean input power with a transmitter with worstcase values of:•••Transmitter optical return loss,
Receiver connector degradations
Measurement tolerances

The receiver OSNR tolerance does not have to be met in the presence of chromatic dispersion, non-linear
effects, reflections from the optical path, PMD, and PDL or optical crosstalk. These effects are specified
separately but contribute to total optical path OSNR penalty.
System integrators need to account for these path penalties when evaluating network performance.

13.3.2 Spectral excursion
Spectral excursion is defined as the difference between the nominal central frequency of the channel
and the -3.0 dB points of the transmitter spectrum furthest from the nominal central frequency
measured at point Ss.

13.3.3 Out-of-Band OSNR (OOB OSNR)
Out-of-Band OSNR (OOB OSNR) is the ratio of the peak transmitter power to the integrated poweroutside the transmitter spectral excursion. The spectral resolution of the measurement shall be better
than the maximum spectral width of the peak.

13.3.4 Ripple
Ripple is defined as the peak-to-peak difference in insertion loss between the input and output portsof the black link over that channel in the frequency (or wavelength) range of the channel +/- themaximum spectral excursion.

13.3.5 Optical return loss at SS
Reflections are caused by refractive index discontinuities along the optical path. If not controlled, they
can degrade system performance through their disturbing effect on the operation of the optical source,or through multiple reflections which lead to interferometric noise at the receiver. Reflections from theoptical path are controlled by specifying the:•minimum optical return loss of the cable plant at the source reference point (Ss), including
any connectors; and•maximum discrete reflectance between source reference point (Ss) and receive reference
point (Rs)

Reflectance denotes the reflection from any single discrete reflection point, whereas the optical returnloss is the ratio of the incident optical power to the total returned optical power from the entire fiber
including both discrete reflections and distributed backscattering such as Rayleigh scattering.
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13.3.6 Discrete reflectance between SS and RS
Optical reflectance is defined to be the ratio of the reflected optical power present at a point, to theoptical power incident to that point. The maximum number of connectors or other discrete reflection
points which may be included in the optical path must be such as to allow the specified overall optical
return loss to be achieved.

13.3.7 Differential Group Delay (DGD)
Differential group delay (DGD) is the time difference between the fractions of an optical signal transmitted
in the two principal states of polarization. For distances greater than several kilometers, and assuming
random (strong) polarization mode coupling, DGD in a fiber can be statistically modelled as having a
Maxwellian distribution.
Due to the statistical nature of polarization mode dispersion (PMD), the relationship between maximum
instantaneous DGD and mean DGD can only be defined probabilistically. The probability of theinstantaneous DGD exceeding any given value can be inferred from its Maxwellian statistics.
For purposes of this IA the ratio of maximum instantaneous DGD to mean DGD is defined as 3.3,
corresponding to the probability of exceeding the maximum DGD 4.1 × 10-6.

13.3.8 Polarization Dependent Loss (PDL)
The polarization dependent loss (PDL) is the difference (in dB) between the maximum and minimum
values of the channel insertion loss (or gain) of the black link from point Ss to Rs due to a variation of theState Of Polarization (SOP) over all state of polarizations.

13.3.9 Polarization rotation speed
The polarization rotation speed is the rate of rotation in Stokes space of the two polarizations of the
optical signal at point RS measured in krad/s.

13.3.10

Inter-channel crosstalkInter-channel crosstalk is defined as the ratio of total power in all the disturbing channels to that in thewanted channel, where the wanted and disturbing channels are at different wavelengths.
Specifically, the isolation of the link shall be greater than the amount required to ensure that when any
channel is operating at the minimum mean output power at point Ss and all of the others are at the
maximum mean output power, then the inter-channel crosstalk at the corresponding point Rs is less thanthe maximum inter-channel crosstalk value.

13.3.11

Interferometric crosstalkInterferometric crosstalk is defined as the ratio of the disturbing power to the wanted power within asingle channel, where the disturbing power is the power (not including ASE) within the optical channel
that would remain if the wanted signal were removed from the link while leaving all of the other linkconditions the same.
Specifically, the isolation of the link shall be greater than the amount required to ensure that when any
channel is operating at the minimum mean output power at point Ss and all of the others are at the
maximum mean output power, then the interferometric crosstalk at the corresponding point Rs is lessthan the maximum interferometric crosstalk value.
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14 Interoperability Test Methodology, Definitions
Interoperability is achievable by complying with all required aspects of this IA. Digital datapath verificationis measured through a combination of interoperability Test Vectors and the use of common sets of test
generators and checkers. The generators and checkers can be configure using looped back pairs for selftesting or in a cross-linked configuration.
Optical interworking is achieved through strict adherence to the discrete Tx/Rx optical specifications overa compliant channel (ref Section 13). Error Vector Magnitude Testing (Section 20, Appendix C) is intended
for future integration to the normative sections of this IA.

14.1 400ZR Test Features
To verify the design for interoperability, a full set of test vectors is made available to OIF member
companies. Lower level diagnostic capabilities in the form of loopbacks and insertion points for test
generators/checkers is also described in Section 14.2.

14.2 Loopback features, Test Generators and Checkers
Figure 39 shows the various diagnostic and test capabilities overlaid on the data path. Generators andcheckers are provided and can be used in conjunction with the loopbacks for self-diagnostic, or they canbe used in conjunction with external test equipment to verify the data path.

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8400GBASE-R (400GAUI-8)
PMA sublayer(*)

8

16

Per IEEE 802.3TM-2018
Host Side Rx
Loopback

Alignment lock and lane
deskew

16

Host Side Tx
Loopback

Lane reorder and deinterleave

RS-FEC
detected Local
DegradeRx Client
FEC
Degradesignaling

rx_am_sf<2:0>

RX Datapath

FEC Decode

FEC Encode

PHY 400GXS
Post-FEC Interleave

Pre-FEC Distribution

Alignment Removal

Alignment Insertion

Descramble

256b/257b blocks
400GAUI-8

256b/257b Transcode

Reverse Transcode
Decode &Error Marking

Tx Client
FEC
Degradesignalingtx_am_sf<2:0>

Scramble

256b/257b blocks

PCS
Checker

TX Datapath

Distribution & Interleave

No ratematching

No ratematching

EncodePMA

PCS
Generator

PHY 400GXS

400GMII*

GMP PCS
Generator

Encode256b/257b transcode256b/257b blocks

GMP Mapping(4*257b stuffing)
tx_oh_sf<2:0>

TV PRBS
Generator

OH/AM insertion(20*257b)

No ratematching

No ratematching

Rx Modem Loopback

Line-Side CLOCK DOMAIN(+/- 20 ppm)

Tx Modem Loopback

AM/OH detect & removal(20*257b)

SC-FEC Adapt, ED &Decoding

Pad removal

Scramble

Descramble

Convolution interleaving

Convolution deinterleaving

128b/119b SD-FEC
Hamming encode

128b/119b SD-FEC
Hamming decode

Gray mapping, symbolInterleaving, Pol distribution

Pol combining & Symbol
de-interleaving(6*119b)2*Logical Equivalent Implementaion. The rate matching functions shallbe disabled to/from the 400GMII interface in both directions. No Idle
deletion/insertion shall be performed.

SC-FEC
detected Local
Degrade22

PMA (ZR)Media Side Tx
Loopback

Media Side Rx
Loopback

RX DSP

2

ADC

DAC

Photonic Interface

TV PRBS
Checker

400ZR

Pilot removal

Pilot Insertion2

rx_oh_sf
<2:0>

2

2

TX DSPMEDIUM

Align C-FEC &FAW/TS removal

FAW & TS Insertion2

PHY 400ZR

MDI

GMP de-mapping(4*257b de-stuffing)

Pad Insertion(6*119b)

EVM
PRBS
Generator

Reverse transcode

CRC-32 checking

PCS (ZR)

PCS
PMA
PMD

GMP PCS
Checker

System-side CLOCK DOMAIN 256b/257b blocks(+/- 100 ppm)

CRC-32 Calculation
SC-FEC Adapt, ED &encoding

Decode &Error Marking

PMD (ZR)

Photonic Interface

Figure 39: 400ZR test features
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14.2.1 Loopbacks
A 400ZR module must be capable to minimally support one of the following loopback sets. The sets aredefined such that when two 400ZR modules are cross-connected over a black link a near-end and a farend loopback path exists across the black link. The CMIS supported loopback modes are shown in Italic.
Each set has 1 Rx path and 1 Tx path.
••••

Modem Tx loopback + Modem Rx Loopback
Modem Tx loopback + Host Side Rx Loopback
Media Side Tx loopback + Modem Rx Loopback
Host Side Tx loopback + Host Side Rx Loopback

The specific loopback mode enabled must be coordinated at each end of the link by each host.
The following loopback modes are defined:

Loopback Name
Host Side Tx Loopback
Modem Tx Loopback
Media Side Tx Loopback
Media Side Rx Loopback
Modem Rx Loopback
Host Side Rx Loopback

Description
Loopback after Alignment lock and lane De-skew → PMA sublayer.
Host loop timed.
Loopback after GMP mapping → GMP De-mapping. Data retransmitted relative to local clock
Loopback after Tx DSP processing blocks and before Rx DSP
processing blocks
Loopback in DSP. After polarity split and symbol de-interleave →Grey mapper, symbol Interleave. Media loop timed.
Loopback after GMP De-mapping → GMP mapping. Data
retransmitted relative to local clock.
Loopback after distribution/interleaving block on host ingress path,and before lane reorder and interleave

Table 26: Loopbacks

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14.2.2 Test Generators/Checkers
The test generators and checker requirements are described below: Required modes are highlighted with
Bold text.
Generator/Checker TypeEVM PRBS

Description
Tx Generator only - Used for EVM• PRBS-7 - Optional• PRBS-11 - Optional• PRBS-15 - Optional• PRBS-23 - Optional• PRBS-31 - Optional
Tx Generator, Rx Checker, ZR Frame replacement
to/from SC-FEC, Used for Test Vectors, and FEC
characterization.
• PRBS-7 - Optional• PRBS-11 - Optional• PRBS-15 - Optional• PRBS-23 - Optional• PRBS-31 - Required
Tx Generator, Rx Checker. PCS Test pattern. Data
retransmitted relative to local clock.

TV PRBSGMP PCS

Rx Generator, Tx Checker. PCS Test pattern: IEEE

PCS

Std 802.3™-2018 Clause 119.2.4.9 idle control blocks(block type 0x1E)

Table 27: Test generator/checker descriptions
14.3 Interoperability Test Vectors
The Interoperability generators/checkers are primarily used during design development (e.g. simulation).
Test vectors are used to guarantee the design integrity and the datapath interoperability.

14.3.1 EVM PRBS
The EVM PRBS is intended for EVM measurements. The EVM PRBS will overwrite all transmit symbols. No
specific algorithm, synchronization or seed is required.

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14.3.2 TV PRBS
The TV PRBS is used for validating C-FEC/DSP framing, symbol mapping, and FAW/TS/PS insertion. The
required PRBS31 is per IEEE 802.3 with initial state being all ’s.
••••

Generation/checking is to/from the media interface (see Figure 39).
The PRBS test vector generator is inserted in the Tx data path after the GMP mapper. Test vector
generation data is a PRBS31 sequence replacing the entire 400ZR frame.
The TV PRBS test vector checker is inserted in the Rx data path before the GMP de-mapper. The
TV PRBS checker shall recover and verify the PRBS31 sequence.
The TV PRBS test vector generator can be looped back to the TV PRBS test vector checker as aself-test.

Figure 40: Test vector PRBS31 generator
The TV PRBS test vector files are attached in Table 28.
Order

Polynomial

Seed value

31

Z31+Z28+1

No seed value required.

Test Vector File
testVector.txt

Table 28: Test vector PRBS files
14.3.3 GMP PCS test vectors
The GMP PCS Test Vectors are used for validating the PCS (ZR) datapath. This includes the GMP mapping
process, C-FEC generation and DSP framing. The GMP PCS generator inserts a continuous stream of Idle
control characters /I/ per IEEE Std-2018 Clause 119.2.3.5 prior to GMP mapping on the Tx
datapath. The checker is after the GMP de-mapper on the Rx datapath. See Figure 39.
GMP PCS Test vectors should be longer than 26 super frames. The test vector attached in this document
have a length of 52 super frames. However, 52 super frames may not be enough length to find GMP
stuffing event. The vector of 256 400ZR frames (as input of C-FEC) is also included.
Cm OH value may be mismatched due to Cm fluctuation (between 10215 min. and 10216 max.) dependingon the ppm offset and the initialization process of the Cm calculation.

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Reserved symbols in the super frame are set to (0,0) for the test vectors. Although these symbols are
permitted for the proprietary usage, these symbols must be mapped with the following considerations:•••Randomized,
DC Balanced,
Low cross correlation on the symbol stream of TS, FAW and RES

The GMP PCS test vector files are attached in Table 29.
Description

Test Vector File

ReadmeReadme.txt

Idle test pattern into 400ZR frame

Test Pattern into DSP

400ZR_PCS_test_FlexO_out.txt

400ZR_PCS_test_symbol_out.txt

Table 29: GMP PCS test vector files
14.3.1 PCS test vectors
Generation/checking is to/from host interface (see Figure 39).
The PCS test vector generator is inserted in the Rx data path after the GMP de-mapper. The test patternis based on IEEE Std-2018 Clause 119.2.4.9 (Idle Insert). Downstream logic in the 400ZR data pathshall support transcoding, scrambling, PCS alignment marker insertion and RS(544,514) FEC
encapsulation. The host loop Rx data path vector check monitor point is at the 400GBASE-R PMA sublayer.
The PCS test vector checker is inserted in the Tx data path before the GMP mapper. The test pattern usedwithin the 400GBASE-R PCS sublayer is IEEE Std-2018 Clause 119.2.4.9 idle control blocks (block
type 0x1E). Downstream logic in the 400ZR data path shall support RS(544,514) FEC termination, PCS deskew, descrambling. The host loop Tx data path vector check monitor is pre GMP mapping. The expected
string is per IEEE Std-2018 Clause 119.2.3.5 (Idle Insert).
Once the host loop Rx and Tx data path are confirmed the PCS test vector generator can be looped backto the PCS test vector checker as a self-test.

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14.3.1 Media loop testing
Test vector generation/checking shall be run on the complete data path bypassing the on-board test
vector generators/checkers to verify end-to-end interoperability. Test vector generation/checking in thiscase is done at both the media and host interfaces.

Host Loop

Descramble

Scramble

256b/257b blocks

256b/257b blocks
TX_PHY_FACILITYLOOPBACK

Reverse Transcode
Decode &Error Marking

No ratematching

No ratematching

No ratematching

No ratematching

256b/257b transcode256b/257b blocks

GMP Mapping(4*257b stuffing)Line side PRBS
generator

EncodePCS Test Vector
Generator

PCS Test Vector Checker

Encode256b/257b Transcode

Decode &Error Marking
Reverse transcode

System-side CLOCK DOMAIN 256b/257b blocks(+/- 100 ppm)
Network-side CLOCK DOMAIN(+/- 20 ppm)

GMP de-mapping(4*257b de-stuffing)Line side PRBS Checker

Media Loop

Figure 41: Test vector detailwww.oiforum.com

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15 Operating frequency channel definitions
15.1 Normative 48 x 100 GHz DWDM Application Channels.
Application Code (0x1) requires 400ZR modules at the 48 frequencies provided in Table 30. The Channel
spacing in Table 30 is based on ITU-T G 694 Section 6 “Fixed grid nominal central frequencies for dense
WDM systems”

index

n (from ITU-T G.694.1)

freq. [THz]

1
2
3
…
46
47
48

30
29
28

196.100
196.000
195.900

-15
-16
-17

191.600
191.500
191.400

Table 30: 100GHz channel spacing
15.2 Optional 64 x 75 GHz DWDM Application Channels
The preferred optional Application Code (0x1) 75 GHz Channel spacing in Table 31 is based on ITU-T
G.694 Section 6 “Fixed grid nominal central frequencies for Dense WDM systems ”

index

n (from ITU-T G.694.1)

freq. [THz]

1
2
3
…
62
63
64

120
117
114

196.100
196.025
195.950

-63
-66
-69

191.525
191.450
191.375

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15.3 Optional Flexible DWDM Grid
Flexible DWDM grids are defined in ITU-T G 694 Section 7 “Flexible DWDM grid definition”, where center
frequencies are determined by,(193.1 + n × 0.00625) THz
and each channel occupies a slot width,12.5 GHz × m
Such that adjacent channel’s frequency slots differ in n by,∆n = 2 x m
There are two example grids in Section 15.3.1 and 15.3.2 that allow the maximum channel fill with 100
GHz and 75 GHz spaced channels on a previously defined spectrum of 96 50 GHz spaced channels. This
allows the re-use of previously designed and deployed DWDM hardware such as WSS and amplifiercomponents without wasting spectrum.
The offset in the grids in Table 32 and Table 33 relative to Table 30 and Table 31 allow for channel plans(e.g. 48 channels spaced at 100 GHz or 64 Channels spaced at 75 GHz), which are edge-aligned to the bandof 96 channels spaced at 50 GHz where the center frequencies are not offset.

Figure 42: Flexible grid provisioning example

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15.3.1 Example 100GHz Flexible Grid Offset
This 48-channel grid has 100 GHz frequency slots corresponding to m = 8. The grid is offset by 25 GHz
from the normative fixed 100 GHz grid defined in Section 15.1. The following table shows the values of n
in steps of ∆n = 16, and an offset at 193.1 THz of n = -4 which corresponds to -25 GHz.

n (from ITU-T G.694.1 Sect. 7) center freq. [THz]
476
460
444
…
12
-4
-20

196.075
195.975
195.875
193.175
193.075
193.975

Table 32: Example 100GHz flexible grid15.3.2 Example 75GHz Flexible Grid Offset
This 64-channel grid has 75 GHz frequency slots corresponding to m = 6. The grid is offset by 12.5 GHz
from fixed 75 GHz grid defined in Section 15.2. The following table shows the values of n in steps of ∆n =12, and an offset at 193.1 THz of n = -2 which corresponds to -12.5 GHz.

n (from ITU-T G.694.1 Sect. 7) center freq. [THz]
478
466
454
…
10
-2
-14
…
-254
-266
-278

196.0875
196.0125195.9375
193.1625
193.0875
193.0125191.5125191.4375
191.3625

Table 33: Example 75GHz flexible grid15.3.3 Flexible Grid Provisioning
The 400ZR coherent MIS IA [1] defines an alternate frequency provisioning model to allow a provisioning
method for flexible DWDM grid systems. This alternative frequency provisioning model allows a direct
setting of the frequency (i.e. no grid limitations) once enabled by a control register. The grid provisioning
model remains the default model.

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16 Summary
This 400ZR IA specifies the requirements of a 400GBASE-R PHY. The 400ZR PHY provides timing and codeword transparent transmission of a 400GBASE-R host signal over a single carrier optical interface (BlackLink) with less than 1.0E-15 bit-errors. This coherent interface uses DP-16QAM, non-differential phase
encoding/decoding, and a Concatenated FEC (C-FEC). The two application codes defined for this IA are:••120 km or less, amplified, point-to-point, DWDM noise limited links.
Unamplified, single wavelength, loss limited links.

No restrictions are placed on the physical form factor by this IA. This 400ZR IA builds upon the work ofother standards bodies including IEEE 802.3TM-2018 and ITU-T SG-15.

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17 References
17.1 Normative references[1] Implementation Agreement for Coherent CMIS, IA # oif2019.015.06[2] Standard for Ethernet: IEEE Std 802.3TM-2018[3] ITU-T G.709/Y.1331 (2019), Amendment 3, Interfaces for the optical transport network.
[4] ITU-T G.709.1/Y.1331.1 (2018), Flexible OTN short-reach interfaces.
[5] ITU-T G.709.2/Y.1331.2 (2018), OTU4 long-reach interfaces.
[6] ITU-T G.709.3/Y.1331.3 (2018), Flexible OTN long-reach interfaces.
[7] ITU-T G.sup39 (02/2016), Optical system design and engineering considerations.

17.2 Informative references[8] ITU-T G.694.1 (2012): Spectral grids for WDM applications: DWDM Frequency grid.
[9] EIC/TR 61282-10, Ed. 1.0, 201: Fibre optic communication system design guides- Part 10:
Characterization of the quality of optical vector-modulated signals with the error vector
magnitude ”

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18 Appendix A: Glossary
AcronymAM
BER
CD

Definition
Alignment Marker
Bit Error Ratio
Chromatic Dispersion

Acronym
NA
NCG
OADM

C-FEC

Concatenated FEC(Staircase FEC +Hamming)Differential Group
Delay
Dual Polarization – mstate Quadrature
Amplitude Modulation
Digital Signal
Processing
Dense WavelengthDivision Multiplexing

OSNR

End of Life
Error Vector
Magnitude
Forward Error
Correction

SC-FECSD-FECFor Further Study
Generic Mapping
Procedure
Hard-Decision FEC

SNR
SOP

DGD
DP-mQAM

DSP
DWDM

EOL
EVM
FEC

FFS
GMP
HD-FEC

IA

PDL
PMD

QAM
Rs

Ss

SOPMD

LD

Implementation
Agreement
Local Degrade

TBD
WDM

LO

Local Oscillator

WSS

LOS

Loss of Signal

Definition
Not Applicable
Net Coding Gain
Optical Add/Drop
Multiplexer
Optical Signal-to-Noise
Ratio
Polarization Dependent
Loss
Polarization Mode
Dispersion
Quadrature Amplitude
Modulation
Single-Channel
Reference point at the
DWDM network
element tributary
outputStairCase FEC
Soft-Decision FEC
Single-Channel
Reference point at the
DWDM network
element tributary input
Signal-to-Noise Ratio
State of Polarization
Second Order
Polarization Mode
Dispersion
To Be Decided
Wavelength-Division
Multiplexing
Wavelength Selective
Switching

Table 34: Acronyms
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19 Appendix B: Future work items
These items below will be considered as part of a maintenance update. Additional contributions are
required to define these items.
1. EVM specifications
2. 75 GHz grid operationa. Once the Transmit Spectrum is defined it can replace Minimum Excess Bandwidth.
3. ZR+ definitions and specifications

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20 Appendix C: Error Vector Magnitude
20.1 Maximum error vector magnitude
The Error vector magnitude is measured using a reference receiver as defined in Section 20.3. EVMrms uses
the peak ref. vector (not average) for normalization.

20.2 Maximum I-Q DC offset
The I-Q DC offset of a modulated signal relates to the average signal amplitudes in the I and Q phases ofthat signal. The relative excess (unmodulated) power, Pexcess, is a measure of this impairment and is
obtained from the parameters Imean and Qmean and Psignal, which are intermediate results during theevaluation of the Error Vector Magnitude:
𝑃𝑒𝑥𝑐𝑒𝑠𝑠 =2Imean+ Q2mean
PSignal

𝐼𝑄𝑜𝑓𝑓𝑠𝑒𝑡 = 10 log10 (Pexcess )20.3 Reference receiver for EVM and I-Q DC offset
The reference receiver includes the following hardware characteristics and processing steps:

20.3.1 Hardware characteristics:•

Dual-polarization coherent receiver. Ideally, the receiver should be calibrated over wavelengthfor:o Frequency responseo Channel imbalanceso IQ phase angle erroro Timing skew
Real-time Nyquist sampler with sampling rate equal to or larger than the 400ZR symbol rate.

•

20.3.2 Processing steps1:
•
•
•
•
•
•
•

Polarization demultiplex.
Retime and resample to one sample per symbol using a Gaussian-shaped low pass filter antialiasing filter with a 3-dB bandwidth of 0.5 times the symbol rate.
Clock phase recovery.
Frequency offset estimation and removal assuming a constant frequency offset over the given
block size N.
Carrier phase recovery.
IQ-offset evaluation and compensation.
Noise loading for EQ training and EVM evaluation.
The amplitude ARMS of the noise for each quadrature is calculated from the following equation:

1 The processing is done block wise with block size N = 1000. It is possible to group multiple blocks for some of the processing steps. The

processing steps should perform only the tasks mentioned in the description. Processing steps can be consolidated and changed in order but
not perform any additional signal processing with the purpose of compensating for signal distortions resulting for example from CD, PMD,
skews, crosstalk, etc.

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𝐴𝑅𝑀𝑆 = √where OSNR is 26 dB and,∆𝑓𝑟𝑒𝑓 =

0.814 ∙ 𝑅𝑠𝑦𝑚𝑏𝑜𝑙
𝑂𝑆𝑁𝑅

10 10 ∙ ∆𝑓𝑟𝑒𝑓

𝑐
∙ 𝑅𝐵
𝜆2

where c is the velocity of light in vacuum, λ is the optical wavelength and RB is the resolution
bandwidth that is 0.1 nm.
• Apply a 7-tap T-spaced FIR filter with the tap coefficients optimized for BER
The sum of all filter tap coefficients is equal to one, and the largest coefficient can be for any of
the 7 taps. The individual filter taps are found by minimizing the EVMRMS value.

20.4 EVM evaluation
Find the peak vector normalization scaling factor2:𝛼= √omax (𝐼ref (𝑘)2 + 𝑄ref (𝑘)2 )

2

0≤𝑘<𝐾

1 𝐾−1
∑ (𝐼 (𝑘)2 + 𝑄ref (𝑘)2 )𝐾 𝑘=0 refNormalize the sample pairs Iẟ and Qẟ in each of the polarizations using the average power
multiplied by the peak vector constellation scaling factor3:
𝑁−1

𝛼peak = 𝛼 √1∑(𝐼𝛿 (𝑛)2 + 𝑄𝛿 (𝑛)2 )
𝑁
𝑛=0

o

Find the nearest constellation pair Iref(n) and Qref(n) for each normalized sample pair Iẟ and Qẟin each of the polarizations.

oCalculate the error vector magnitude for each normalized sample pair Iẟ and Qẟ in each of thepolarizations:
EVM(𝑛) = √(𝐼𝛿 (𝑛) − 𝐼ref (𝑛))2 + (𝑄𝛿 (𝑛) − 𝑄ref (𝑛))2owhere n is the symbol number within the block starting at 0
Using all the N samples from the x-polarization calculate EVMRMS,x:
𝑁−1

1
EVMRMS,𝑥 = √ ∑ EVM(𝑛)2
𝑁
𝑛=0

o

2
3

Using all the N samples from the y-polarization and calculate EVMRMS,y:k runs over all points in the constellation
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𝑁−1

1
EVMRMS,𝑦 = √ ∑ EVM(𝑛)2
𝑁
𝑛=0

o

Then calculate EVMRMS in percent from:2
2+ EVMRMS,𝑦(EVMRMS,𝑥)
EVMRMS = √× 100%
2

20.5 Reference Algorithms for EVM Test of 400ZR transmitters.
The EVM algorithms are attached in Table 35.
Description
Error Vector Magnitude Algorithms1

Test Vector File
400ZR EVM Test
Vectors

Table 35: EVM algorithms
1

Only available to OIF members at this time.

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21 Appendix D: List of companies belonging to OIF when document is approved
Acacia Communications

GoogleADVA Optical Networking

Hewlett Packard Enterprise (HPE)

Alibaba

IBM Corporation

Alphawave IP Inc.

Idea Sistemas Electronicos S.A.

Amphenol Corp.

II-VI Incorporated

AnalogX Inc.

Infinera

Applied Optoelectronics, Inc.

InnoLight Technology Limited

Arista Networks

Innovium

BizLink Technology Inc.

Inphi

Broadcom Inc.

Integrated Device Technology

Cadence Design Systems

Intel

China information and communication
technology Group Corporation

IPG Photonics Corporation

China Telecom Global Limited

Juniper Networks

Ciena Corporation

Kandou Bus

Cisco Systems

KDDI Research, Inc.

Corning

Keysight Technologies, Inc.

Credo Semiconductor (HK) LTD

Lumentum

Dell, Inc.

MACOM Technology Solutions

EFFECT Photonics B.V.

Marvell Semiconductor, Inc.

Elenion Technologies, LLC

Maxim Integrated Inc.

Epson Electronics America, Inc.

MaxLinear Inc.

eSilicon Corporation

MediaTek

Facebook

Mellanox Technologies

Foxconn Interconnect Technology, Ltd.

Microsemi Inc.

Fujikura

Microsoft Corporation

Fujitsu

Mitsubishi Electric Corporation

Furukawa Electric Japan

Molex

Global Foundries

Multilane SAL Offshore

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NEC Corporation

SiFotonics Technologies Co., Ltd.

NeoPhotonics

Socionext Inc.

Nokia

Spirent Communications

NTT Corporation

Sumitomo Electric Industries, Ltd.

O-Net Communications (HK) Limited

Sumitomo Osaka Cement

Open Silicon Inc.

Synopsys, Inc.

Optomind Inc.

TE Connectivity

OrangeTektronix

PETRA

Telefonica SA

Precise-ITC, Inc.

TELUS Communications, Inc.

Rambus Inc.

UNH InterOperability Laboratory (UNH-IOL)

Ranovus

Verizon

Rianta Solutions, Inc.

Viavi Solutions Deutschland GmbH

Rosenberger Hochfrequenztechnik GmbH & Co.
KG

Xelic

Samsung Electronics Co. Ltd.

XilinxSamtec Inc.

Yamaichi Electronics Ltd.

Semtech Canada Corporation

ZTE Corporation[EOD] End of Document

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