Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT8110-PQB
DC-to-24GHz Programmable Integer DividerEasy 8-bit parallel programming interface compatible with CMOS/LVTTL standards



Optional external reset function

Dynamic division ratio adjustment with a short set-up time (about 20ns after the pulse edge on anycontrol input)

Single +2.8V or -2.8V power supplyIndustrial temperature rangeStandard 40-pin QFN package with a thermal padveeveeresetvee

vcc

vcc

vcc

copvccvcc

ASNT8110

vcc

con1

vee

icrl

vee

vcc

vee

chinveevcc

vee

chipvcc

vcc

vcc

vee

vcc

vee

vcc

vee

Rev. 1.2.2

vee

Adjustable power consumption

c0



c1

Fully differential CML input and output interfaces

c2



c3

50% duty cycle of the output divided clock signal

vcc

c4

Continuous division ratios from 1 to 256

c5



c6

Wide frequency range from DC to 24GHz

c7



October 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTIONASNT8110-PQB is a high-speed programmable integer clock divider with dynamic adjustment of thedivision ratio through a standard 8-bit parallel LVTTL/CMOS interface and optional external active-high
CMOS/LVTTL reset signal. The functional block diagram of the device is shown in Fig. 1.
icrl
vcc

vcc

vcc
50

50
copchip

÷ 1…256chin
5050
vcc

c7
c6
c5c4
c3c2c1c0vcc

resetveeDigital InterfaceconFig. 1. Functional Block DiagramThe divider accepts an input clock signal chip/chin with a speed from DC to the maximum specified
frequency and provides a clean 50% duty cycle output divided clock signal cop/con in any operationalmode. The divider allows for dynamic adjustment of the division ratio from 1 to 256 with a step of 1. A
binary code on the control inputs c0-c7 defines the value of the ratio from 1 to 255, where c7 is the mostsignificant bit. All “0”s (“low” state) define the division by 256. Following any change of any control
signal, the divider switches to idle after (64...128) periods of the high-speed system clock plus anadditional 1.6ns delay, and returns back to normal operation with the new division ratio after an additional
delay equal to 192 periods of the high-speed system clock.
The device automatically resets itself after the initial power-up and any change of the division control
signals. When the optional external reset signal reset is set to “high”, the divider switches to idle (static“0” output) after a 0.7ns delay as shown in the timing diagram in Fig. 2. When reset returns to “low”, thedivider switches back to normal operation after (64...128) periods of the high-speed system clock plus anadditional 1.6ns of delay. The minimum allowed reset pulse must be longer than 64 periods of the highspeed system clock.
T> 64T
0.7ns(64...128)T+1.6ns

Fig. 2. Timing Diagram

Rev. 1.2.2

2October 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

The part’s I/O’s support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (also see POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.

POWER SUPPLY CONFIGURATIONThe part can operate with either a negative supply (vcc=0.0V=ground), or a positive supply (vee = 0.0V =ground). In case of the positive supply, all I/Os need AC termination when connected to any devices with
50Ohm termination to ground. Different PCB layouts will be needed for each different power supply
combination.
The parts power consumption may be reduce by up to 25% using an external resistor to connect thecontrol port icrl to vee. Please be aware that reduced current may result in lower maximum

frequency!
All the characteristics detailed below assume vcc = +2.8V and vee = 0V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vee).
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vcc)
Power Consumption
RF Input Voltage Swing (SE)
Case TemperatureStorage Temperature
Operational Humidity
Storage Humidity

Rev. 1.2.2

Min-4010103Max+3.3
3.2
1.0+90+10098
98

UnitsVWVºCºC%%October 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

TERMINAL FUNCTIONSTERMINAL
Name
No.
Type
chipchin
cop
con

5
7
1715

reset

32

c0
c1
c2
c3
c4
c5
c6
c7

2223
24
25
2728
2930

icrl

9Name
vccveeRev. 1.2.2

DESCRIPTION

High-Speed I/Os
Differential clock inputs with internal SE 50Ohm termination tovcc
Differential divided clock outputs with internal SE 50Ohmtermination to vcc. Require external SE 50Ohm termination to vcc
Low-Speed I/Os
CMOS External reset signal
input
Digital Controls
CMOS Digital division control signals
input
CML
input
CML
outputAnalog Controls
Power control port; requires external resistor connected to vee orexternal power supply with current sinking capability
Supply And Termination Voltages
Description
Pin Number
Positive power supply or ground
4, 6, 8, 13, 14, 16, 18, 26, 33-38
Negative power supply or ground
1-3, 10-12, 19-21, 31, 39, 40
Input

4October 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETER
veevccIvee
Power consumption
Junction temperature
Frequency
Swing
CM Level
Rise/Fall Times
Frequency
Logic “1” level
Logic “0” level
Rise/Fall Times
Additive Jitter
Duty Cycle
Logic “1” level
Logic “0” level

MIN

TYP

MAX UNITCOMMENTS
General Parameters
0.0V
External ground
2.5
2.8
3.0V
810mA
icrl shorted to vee
1050mA
R>6KOhm between icrl and vee
2.03W
icrl shorted to vee
3.15
W
R>6KOhm between icrl and vee
-25
50
125°C
Input (chip/chin)
0.0
24
GHz75
400
1000mV
Differential or SE, p-p; at 6GHz
vcc- (SE swing)/23
ns
20%-80%
Output (cop/con)
0.024GHzVvcc
vcc-0.6
V
With external 50Ohm DC termination
151719ps
20%-80%TBD
ps
Peak-to-Peak
47% 50% 53%
For clock signal
Select (c0-c7) & Reset (reset)
VCC-0.4
VVEE+0.4
VPACKAGE INFORMATIONThe chip is packaged in a standard 40-pin QFN package shown Fig. 3. It is recommended that the center
heat slug located on the back side of the package is soldered to ground to help dissipate heat generated by
the chip during operation.
The part’s identification label is ASNT8110-PQB. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per EU 2002/95/EC for all sixsubstances.
Rev. 1.2.2

5October 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT 8110
Fig. 3. QFN 40-Pin Package Drawing (All Dimensions in mm)

REVISION HISTORY
Revision
1.2.2
1.1.2
1.1.1
1.0.1
0.0.1

Rev. 1.2.2

Date
10-2019
07-2019
07-2017
07-2017
04-2017

Changes
Added comment about test frequency
Updated Letterhead
Updated frequency of operation
Reversed control bit order
Preliminary release

6

October 2019