Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

ASNT6172A-KMO
Asynchronous FIR Filter and 2x2 Analog Switch

Fully differential CML-type analog input interfaces

Two independent fully differential CML-type analog outputs

Operates as an analog non-blocking 2x2 switch with a possibility to mix weighted input signals

High bandwidth DC-28Gbps / 20GHz



Total gain up to 6dB

Dual-port 3-wire SPI for tap weight and sign adjustment

Additional frequency response and gain adjustment through the SPIIndependent power supplies for analog and digital sections

Power consumption: <1.25W

Fabricated in SiGe for high performance, yield, and reliability

Custom CQFP 64-pin package

ASNT6172A

v2p9
vee
d2p
vee
d2n
vee
3wenin
3wcin
3wdin
3wdo
vee
nc
vee
v4p0
vee
v2p9

v1p2
vee
v2p9
vee
qrepn
vee
v2p9
nc
v2p7
v2p9
vee
q1n
vee
q1p
vee
v1p2

v2p9
vee
d1p
vee
d1n
vee
nc
nc
nc
nc
vee
qrepn
veev2p9veev2p9v2p9veev4p0v4p0v4p0v4p0vee
q2nveeq2pveev2p9

Dual FIR filter with 9 fully controlled taps for each input analog signalv2p9veev4p0veeRev. 0.0.1

1January 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

DESCRIPTION
v2p9

v2p9 v4p0v2p7
50

ch1_1

d1p
d1n
d2p
d2nFIROB

q1pq1nq2pq2n50

50

Requiredexternal
termination

obcrl 2x2

cscIcrl 2x6

CrlB
efIcrl 2x6

Rpl

tap inv crl 36x1
tap off crl 36x1
adder gain crl 36x6

cscIcrl2x1

ch2_2

efcrl 2x1

3wdin
3wcin
3wenin
3wdo

ch1_2
ch2_1

onrep 1x1
repgn 1x6

qrp
qrn

Gnd Gnd Gnd Gnd

50SPI

v1p2

veeFig. 1. Functional Block Diagram

The IC shown in Fig. 1 is a two-channel differential analog 9-tap FIR filter. It receives two high-speed
analog signals through its differential input ports d1p/d1n and d2p/d2n. Each channel of FIR has 9 dual
taps. Each tap provides two copies of its input signal with controlled polarities. The signals are thenprocessed by analog adders with controlled weight coefficients to perform the pre-emphasis operation.
The resulting 4 analog signals (the first and the second signals from the first and the second channels) aresent to the output buffer block that converts them into two output analog signals delivered to linear
differential ports out1p/out1n and out2p/out2n. The first output port presents either individual firstsignal from any channel, or a sum of both first signals. It can be also completely disabled. The secondoutput port presents the second signals from both channels with the same operational modes. Both ports
operate in CML-type mode and require external 50Ohm terminations.
All chip functions are controlled by internal digital signals delivered through a 3-wire serial-to-parallelinterface (SPI) that operates in combination with an internal control block CrlB.
Rev. 0.0.1

2January 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

The chip includes a 1-tap replica Rpl that can be independently enabled and used for initial gain
calibration as described below.

FIR
The FIR consists of two identical channels. At the input of each channel there is a differential
transmission line that includes 10 identical sections connected in series to provide ten equal delays. The
connection nodes of the sections serve as inputs for 9 taps. The ends of the last section have internal
50Ohm terminations to a separate internally generated power supply v2p7. The last section is required forachievement of matching conditions for all taps.
Each tap includes a pair of dual buffers (buf1 and buf2) which allows for generation of two copies of thetap’s input signal with polarities individually selected by 1-bit binary signals chX_inv1 and chX_inv2,
where “0” corresponds to a direct output signal and “1” corresponds to an inverted output signal. Dualbuffers in each tap can be individually disabled by special 1-bit binary signals chX_off1=”0” or
chX_off2=”0”. The buffers of different taps have slightly different gains and internal peaking in order tocompensate for transmission line losses.
The 9 pairs of delayed copies of the differential input signal with set polarities are then processed by two
2-stage adders in order to create two linear sums of weighted tap signals. The first stage of each adderconsists of three 3-to-1 adders and combines 9 input signals into 3 intermediate signals. The second stage
combines those intermediate signals into 1 output signal. Identical 3-to-1 analog adders with digitalcontrols of each input’s weight are used in both stages. The control circuitry of the 3-to-1 adder isdesigned in such a way that the combined weight of all 3 inputs does not exceed the maximum weight ofone tap. The control circuitry receives three 6-bit binary signals: the first weight chX_gncYZ1, thesecond weight chX_gncYZ2, and the maximum possible weight chX_gnmxY, and converts them intoanother three 6-bit binary signals that control the actual weights of all three inputs. Here X is the channel
number 1 or 2; Z is the 2-stage adder number 1 or 2; and Y is the 3-to-1 adder number 1, 2, 3, or 0, where
the adders 1, 2, and 3 represent the first stage and the adder 0 represents the second stage. The
corresponding algorithm is detailed in Table 1.
Table 1. Wight Control Algorithm

Input number Control signal
1chX_crlYZ12

chX_crlYZ23

chX_crlYZ3FormulachX_gncYZ1
chX_gnmxYchX_gncYZ2

Condition
if chX_gncYZ1≤ chX_gnmxY
if chX_gncYZ1> chX_gnmxY
if R1=(chX_gnmxY- chX_gncYZ1)>0 andichX_gncYZ2≤ R1
R1
if R1>0 and chX_gncYZ2>R10
if R1 ≤0
R1-chX_gncYZ2 if R1>0 and R2=R1-chX_gncYZ2>00
if R1≤0 or R2≤0The maximum weight can be adjusted depending on the fabrication process corner. The required valueof the maximum weight is defined during initial calibration. The calibration is performed using a replica
block Rpl that is described below.
Rev. 0.0.1

3January 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

Each tap can be enabled/disabled and its weight and polarity are defined by internal binary signals set
through SPI that is also described below.

OBThe output buffer (OB) takes two pairs of analog signals from the two FIR channels (ch1_out1,ch1_out2, ch2_out1, and ch2_out2) and delivers them to the two output ports q1p/q1n and q2p/q2n
as defined by 2-bit binary control signals obcrl1<1:0> and obcrl2<1:0> according to Table 2. Here X isthe channel number 1 or 2.
Table 2. Output Buffer Operational Modes

obcrlX<1> obcrlX<0>
qX00
Output disabled
01
ch1_outX10
ch2_outX
1
10.5*(ch1_outX)+0.5*(ch2_outX)

CrlB
The control block (CrlB) converts binary signals from SPI into analog voltages that control internal
peaking and linearity parameters of FIR channels. The peaking can be adjusted by 6-bit binary signals
chX_ief<5:0> where higher values corresponding to higher bandwidth with associated high-frequency
peaking of the channel’s frequency response. The linearity can be adjusted by 6-bit binary signals
chX_icsc<5:0> where higher values correspond to higher linearity at low weights.

Rpl
The tap replica (Rpl) is used for initial tap gain calibration to ensure the optimal maximum data signal
swing at the outputs of the first stages of both adders.
Rpl is an exact copy of Tap1. In the optimal state, it should generate a predefined DC voltage difference
between its outputs qrp and qrn. This difference should be adjusted to the value specified in
ELECTRICAL CHARACTERISTICS using the 6-bit binary signal ch1_gnmx1. Rpl is used for initial
calibration only and can be completely disabled by the binary signal onrep=”0”.

SPI
The 3-wire SPI operates in slave mode and accepts three CMOS signals: 3wenin (SSn), 3wcin (SCLK),and 3wdin (MOSI) as described in ELECTRICAL CHARACTERISTICS. Additional CMOS data output
3wdout (MISO) is provided for control purposes.
SPI converts 40 input serial bytes into 115 parallel binary control signals. The SPI byte description ispresented in Table 3.

Rev. 0.0.1

4January 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

Table 3. SPI Control Bytes

SPI
Bit Number
Byte
Section Number 7 (MSB for Left)
65 4 3 2
10 (MSB for Right)
onrepX
ch1_gnmx1
Left1
obcrl1ch1_gnmx02ch1_off1(1)ch1_inv1(1)ch1_gnc1113
ch1_off1(2)ch1_ inv1(2)ch1_ gnc1124
ch1_off1(3)ch1_ inv1(3)ch1_gnc1215
ch1_off1(4)ch1_ inv1(4)ch1_ gnc1226
ch1_off1(5)ch1_ inv1(5)ch1_gnc2117
ch1_off1(6)ch1_ inv1(6)ch1_ gnc2128
ch1_off1(7)ch1_ inv1(7)ch1_gnc2219ch1_off1(8)ch1_ inv1(8)ch1_ gnc22210
ch1_off1(9)ch1_ inv1(9)ch1_gnc311
11
ch1_off2(1)ch1_ inv2(1)ch1_ gnc31212
ch1_off2(2)ch1_inv2(2)ch1_gnc32113
ch1_off2(3)ch1_ inv2(3)ch1_ gnc322
14
ch1_off2(4)ch1_ inv2(4)ch1_gnc011
15
ch1_off2(5)ch1_ inv2(5)ch1_ gnc012
16
ch1_off2(6)ch1_ inv2(6)ch1_gnc021
17
ch1_off2(7)ch1_ inv2(7)ch1_ gnc022
18
ch1_off2(8)ch1_ inv2(8)ch1_ef (DAC)19
ch1_off2(9)ch1_inv2(9)ch1_csc(DAC)
20
7 (MSB for Left)6
5 4 3 210 (MSB for Right)
ch2_csc (DAC) (reversed bit order)
ch2_ inv2(9)ch2_off2(9)Right21
ch2_ef (DAC) (reversed bit order)
ch2_ inv2(8)ch2_off2(8)22ch2_ gnc022 (reversed bit order)
ch2_ inv2(7)ch2_off2(7)23ch2_gnc021 (reversed bit order)
ch2_ inv2(6)ch2_off2(6)24ch2_ gnc012 (reversed bit order)
ch2_ inv2(5)ch2_off2(5)25ch2_gnc011(reversedbitorder)
ch2_inv2(4)ch2_off2(4)26ch2_ gnc322 (reversed bit order)
ch2_ inv2(3)ch2_off2(3)27ch2_gnc321 (reversed bit order)
ch2_ inv2(2)ch2_off2(2)28ch2_ gnc312 (reversed bit order)
ch2_ inv2(1)ch2_off2(1)29ch2_gnc311 (reversed bit order)
ch2_ inv1(9)ch2_off1(9)30ch2_ gnc222 (reversed bit order)
ch2_ inv1(8)ch2_off1(8)31ch2_gnc221 (reversed bit order)
ch2_ inv1(7)ch2_off1(7)32ch2_ gnc212 (reversed bit order)
ch2_ inv1(6)ch2_off1(6)33ch2_gnc211 (reversed bit order)
ch2_ inv1(5)ch2_off1(5)34ch2_ gnc122 (reversed bit order)
ch2_ inv1(4)ch2_off1(4)35ch2_gnc121 (reversed bit order)
ch2_ inv1(3)ch2_off1(3)36ch2_ gnc112 (reversed bit order)
ch2_ inv1(2)ch2_off1(2)37ch2_gnc111 (reversed bit order)
ch2_inv1(1)ch2_off1(1)38ch2_gnmx0 (reversed bit order)
obcrl2 (reversed bit order)39
ch2_gnmx1 (reversed bit order)
XX40
Rev. 0.0.1

5January 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

The bytes are delivered starting from 1 to 40 and bits within a byte are delivered starting from MSB.
Bit#7 is the MSB of a byte as shown in Fig. 2. Internal registers are updated at a rising edge of 3wenin.

3wcin3wenin
SampleLatch
3wdin

X 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0 X

Byte 1

Byte NFig. 2. SPI Operation

POWER SUPPLY CONFIGURATIONThe IC requires three positive external power supplies. The first supply v2p9 is used for the data output
terminations and to power all high-speed circuitry and reference sources. The second supply v4p0 powers
the internal analog adder circuitry. The digital supply v1p2 is used for the internal CMOS circuits of theSPI.
All supplies are positive in relation to the internal common node vee=0.0V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings may cause damage to this product and/or lead toreduced reliability. Functional performance is specified over the recommended operating conditions for
power supply and temperature only. AC and DC device characteristics at or beyond the absolutemaximum ratings are not assumed or implied. All min and max voltage limits are referenced to ground.
Table 4. Absolute Maximum Ratings

Parameter
Supply Voltage (v4p0)
Supply Voltage (v2p9, v2p7)
Supply Voltage (v1p2)
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity
Rev. 0.0.1

Min-4010106Max+4.4+3.6+1.50.5+90+10098
98UnitsVVVVºCºC%%January 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

TERMINAL FUNCTIONSTERMINAL
Name No.
Type
d1p
d1n
d2p
d2n
q1p
q1n
q2pq2n53
60
282112534443wenin 26
3wcin 25
3wdin 24
3wdout 23
v2p79qreppqrepn623Nameveev2p9
v4p0v1p2
nc

Rev. 0.0.1

CML-type input

Description
High-Speed I/Os
Differential high-speed data inputs with internal SE 50Ohm
terminations to v2p9

CML-type input
CML-type output Differential high-speed data outputs with internal SE 50Ohm
terminations to v2p9; require external SE 50Ohm terminations
CML-type output to v2p9.
Low-Speed I/Os
1.2V CMOS input Enable input signal SSn for 3-wire interface
Clock input signal SCLK for 3-wire interface
Data input signal MOSI for 3-wire interface
1.2V CMOS output Data output signal MISO for 3-wire interface
Analog Control Voltages
Internal voltage Internal voltage source of v2p9-0.2V
generator output
Analog Control Nodes (for DMM measurements only!)
Analog DC output Replica differential data outputs

Supply And Termination Voltages
Description
Pin Number
External ground2, 4, 6, 11, 13, 15, 18, 20, 22, 27, 29, 31,
34, 36, 38, 43, 45, 47, 50, 52, 54, 59, 61,
63
Positive power supply
7, 10, 17, 32, 33, 48, 49, 64
Positive power supply
14, 19, 30, 35, 39, 42, 46, 51
Positive power supply
1, 16
not connected pins
8, 40, 41, 55-58

7January 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETER

MIN

v2p9
v4p0
vddvee
Iv2p9
Iv4p0
Power consumption
Junction temperature
No. of Taps
Delay between Taps
Voltage gain
Data Rate
Swing in linear mode
S11
CM Voltage Level
BandwidthSwing
S22
CM Voltage Level
qrp-qrn
Clock frequency
Low logic levelHigh logic level-25

TYP MAX UNIT
General Parameters
2.9V
4.0
V
1.2
V0.0V
400mA
175mA
180215mA
1.2550COMMENTS
Analog supply
Analog supply
CMOS digital supply
External groundAll taps enabled, maximum peaking
3 equivalent taps in each channel
Depending on bandwidth control
settings

2.1W
125°C
FIR Parameters

2x2x9
13.5
ps
6dB
From chip input to chip output
High Speed Input Data (d1p/d1n, d2p/d2n)
DC28Gb/s
110mV
Differential or SE, p-p
TBDdBV
Must match for both inputsv2p7-0.2
Analog Output Data (q1p/q1n, q2p/q2n)
DC20
GHz220mVAt each SE output
TBDdB
2.5
VDC Control Voltages
220
mV
With optimal ch1_gnmx13-Wire Interface Ports
6MHz0V
1.2
V

PACKAGE INFORMATIONThe chip die is housed in a custom, 64-pin CQFP package shown in Fig. 3. The package’s mechanicalinformation is available on the company’s website. Even though the package provides a center heat slug
located on the back side of the package to be used for heat dissipation, ADSANTEC does NOT
recommend for this section to be soldered to the board. If the customer wishes to solder it, it should beconnected to vee plain that is ground for the positive supply.
Rev. 0.0.1

8January 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

Fig. 3. CQFP 64-Pin Package Drawing (All Dimensions in mm)

The part’s identification label is ASNT6172A-KMO. The first 9 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 digits after the underscore represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per EU 2002/95/EC for all six
substances.
Rev. 0.0.1

9January 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

REVISION HISTORY
Revision
0.0.1

Rev. 0.0.1

Date08-2019

Changes
Preliminary release

10January 2019