Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT7120A-KMA
15GS/s, 4-bit Flash Analog-to-Digital Converter
20GHz analog input bandwidth
Selectable clocking mode: external high-speed clock or internal PLL with external reference clock
Broadband operation in external clocking mode: DC-15GS/s
On-chip PLL with a central frequency of 10GHz
Optional external preset of the internal clock divider
Internal demultiplexer 4-to-16 for the output data rate reduction
Differential CML input clock buffer and linear input data buffer
Proprietary low-power LVDS output interface
Selectable output clock frequency and polarity
Selectable on-chip digital-to-analog converter for self-testingSingle +3.5V power supply
Power consumption: 3.6W
Custom 100-pin metal-ceramic package

vee 75vee 74
q11n 73
q11p 72
vcc 71q12n 70q12p 69
vcc 68q13n 67
q13p 66
vcc 65
q14n 64q14p 63vcc 62
q15n 61q15p 60
n/c 59vee 58odn 57
odp 56
vcc 55n/c 54n/c 53n/c 52vee 51



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


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

Rev. 1.5.2

ASNT7120Avee 50vrefcrl 49
vlsbcrl 48
ondac 47
res 46n/c 45
vcc 44vee 43vee 42
vcc 41
dp 40
dn 39
vcc 38vee 37vee 36
vcc 35
cep 34cen 33vcc 32vee 31vee 30vcc 29crp 28crn 27vcc 261 vee
2 vee
3 q02p
4 q02n5 vcc
6 q01p
7 q01n8 vcc
9 q00p10 q00n
11 vcc12 clop
13 clon
14 n/c15 vee16 cosel1
17 cosel2
18 cosel3
19 lol20 ftr21 vee22 ceoff
23 nc
24 nc
cpcsel
25 vcc76 vcc77 q10p
78 q10n79 vcc80 q09p
81 q09n
82 vcc83 q08p
84 q08n
85 vcc86 q07p
87 q07n
88 vcc89 q06p
90 q06n
91 vcc92 q05p
93 q05n
94 vcc95 q04p
96 q04n
97 vcc98 q03p
99 q03n
100 vcc1

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DESCRIPTION
ondac

DAC

vrefcrl
vlsbcrldp/dn

LIB 154-bit
TTB
Flash 15
Encoder
ADC

odp/odn

LOB

4:16
16
DMX
16

ftr
lol
crp/crn
cep/cenceoff
rescosel1cosel2
cosel3q00p/q00nq15p/q15n

LVDS
OBx17

CMU &
DividerClk
Proc.

clop/clon

Fig. 1. Functional Block Diagram

The ASNT7120A-KMA is a 4-bit flash analog to digital converter (ADC) featuring a high sampling rate
and wide analog front-end bandwidth. The ADC system shown in Fig. 1 includes a linear input buffer(LIB) with tree-type architecture and a CML-type input interface with internal 50Ohm single-ended
terminations to vcc. The buffer delivers 15 matching copies of the input analog data signal dp/dn to the
4-bit flash ADC. The ADC creates 15 samples of the input data in thermometer code, which are thenconverted by a thermometer-to-binary encoder (TTB Encoder) into 4-bit binary words with a data rate f.
The ADC thresholds are controlled by signals vrefcrl and vlsbcrl. The encoded data is demultiplexed into
16-bit wide words with a data rate f/4 and sent to the output through 16 low-power LVDS buffers as
signals q00p/q00n–q15p/q15n. An optional digital-to-analog converter (DAC) with an output signal
odp/odn can be used to control the ADC’s operation. It is enabled by using control signal ondac.
All operations are synchronized by the internal clock multiplication unit (CMU) based on a PLL (phaselocked loop) with an integrated divider and an external loop filter connected to pin ftr. The block can
operate in two different modes which are controlled by signal ceoff: clock multiplication (PLL is on, areference clock is applied to pins crp/crn), and clock division (PLL is off, an external high-speed clock isapplied to pins cep/cen). In both modes, the divider generates internal clock signals divided by 2, 4, 8,
and 16. The generated divided clocks are sent to different internal blocks. In the CMU’s second
operational mode, the divider can be preset by external signal res to allow synchronization of parallelconnected ADCs. A PLL lock control output lol is also provided.

Rev. 1.5.2

2

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The part operates from a single +3.5V power supply. All external control signals are compatible with the
2.5V CMOS interface.

Linear Input Buffer (LIB)
The system includes a linear input buffer (LIB) with a tree-type architecture that delivers 15 matchingcopies of the wide-band input differential analog data signal dp/dn to the 4-bit flash section. Symmetry is
closely followed in both schematic and layout to ensure minimal aperture jitter.

Clock Multiplication Unit (CMU) & Divider
The PLL-based CMU with external loop filter connected to pin ftr, as shown in Fig. 2, can operate in two
different modes. In the first “clock multiplication” mode (ceoff=”1” , default), the CMU multiplies anexternal reference clock crp/crn with a speed of f/16 by means of a PLL with central frequency of f and awide tuning range of the internal VCO (voltage-controlled oscillator). The generated clock is processedby the divider in order to generate internal clock signals divided by 2, 4, 8, and 16.
100Ohm
To pin 20 (ftr)

1nF
vee

Fig. 2. Recommended External Loop Filter SchematicIn the second “clock division” mode (ceoff=”0”), the PLL is disabled and the internal clocks are
generated from the external high-speed clock input cep/cen. To align multiple ADCs in parallel, thedivider should be preset by the active-high CMOS control signal res.

HS External Clock Input Buffer
The high-speed external clock input buffer can accept high-speed clock signals at its differential CML
input port cep/cen. It can also accept a single-ended signal with AC or DC termination. In case of AC
termination, the unused pin should be also AC terminated with a 50Ohm load. In case of DC termination,a threshold voltage must be applied to the unused pin. The buffer can handle a wide range of input signal
amplitudes. The buffer utilizes on-chip single-ended termination of 50Ohm to vcc for each input line.

LS Reference Clock Input Buffer
The low-speed reference clock input buffer is a proprietary LVDS buffer with internal 100Ohm
differential termination between its inputs crp/crn. The buffer exceeds the requirements of standards
IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. It is designed to accept differential signals withamplitudes above 100mV peak-to-peak (p-p), a wide range of DC common mode voltages, and AC
common mode noise with a frequency up to 5MHz and voltage levels ranging from 0 to 2.4V.

4-bit Flash Analog to Digital Converter (ADC) with Encoder
This block samples the incoming analog data with the clock signal provided by the CMU in order togenerate a 4-bit output digital signal (Bit 0 – Bit 3) with MSB corresponding to Bit 3. The thresholdvoltages (Vth 1 - Vth 15) of the ADC can be adjusted through analog signals vrefcrl and vlsbcrl as shown in
Table 1. As can be seen, vrefcrl shifts the DC levels of all the threshold voltages simultaneously by thesame amount in relation to vcc and vlsbcrl alters the voltage range of the least significant bit (LSB) while
also shifting the DC levels.
Table 1. Simulated ADC Threshold Control States

Rev. 1.5.2

3

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vrefcrl. mV
min (vcc – 960)
min (vcc – 960)
max (vcc)
max (vcc)

vlsbcrl. mV
Vth 15, mV Vth 8, mV Vth 1, mV Vth (X+1) – Vth X, mV
min (vcc – 700) vcc-35
vcc-54
vcc-732.7
max (vcc – 260) vcc-345 vcc-751 vcc-1157
58
min (vcc – 700) vcc-355 vcc-361 vcc-366
0.8
max (vcc – 260) vcc-665 vcc-1058 vcc-1450
56

If no external voltages are applied to vrefcrl and vlsbcrl, it is recommended to have both pins ACterminated by 50Ohm resistors to vee through DC blocks! The corresponding default states are
vrefcrl=vlsbcrl=vcc-0.48V.

Demultiplexer (4:16 DMX)This block deserializes the 4-bit words from the ADC into 16-bit output words as shown in Table 2.
Table 2. Demultiplexer Bit Order

First
SecondThird
FourthSerialized input words
0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3
ADC bits (3 is MSB)
00 04 08 12 01 05 09 13 02 06 10 14 03 07 11 15
DMX output bits

Clock Processor (Clk Proc)
To increase the adaptability of the designed ADC, a clock processor that provides a low-speed output
clock signal with the options specified in Table 3, is included.
Table 3. Output Clock Options

External control signals Output clock signal
cosel1 cosel2 cosel3 Speed Inversion
1
1
1
c4
Yes
1
1
0
c4
No
0
1
1
c8
Yes
0
1
0
c8
No
x
0
1
c16
Yes
x
0
0
c16
No

Digital to Analog Converter (DAC)A DAC block is included to perform a quick test of the ADC’s functionality. When activated by theexternal control signal (ondac=”1”), it converts the digital data into a step-wise copy of the input signalthat is sent to the output odp/odn through a linear differential output buffer LOB. The circuit is notconsuming any power when disabled (ondac=”0”, default).

LVDS Output Buffers
The 16-bit differential digital data words q00p/q00n to q15p/q15n are delivered to the output through anarray of proprietary low power LVDS buffers. The low speed differential clock clop/clon also utilizes asimilar LVDS output buffer. The buffers satisfy all the requirements of the IEEE Std. 1596.3-1996 andANSI/TIA/EIA-644-1995.

Rev. 1.5.2

4

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TERMINAL FUNCTIONSPin Pin
Pin
Pin# nametypefunction1
vee supply voltage
negative power supply
2
vee supply voltage
negative power supply
3
q02p
Output data Bit 02, direct
LVDS output
4
q02n
Output data Bit 02, inverted
5
vcc supply voltage
positive power supply
6
q01p
Output data Bit 01, direct
LVDS output
7q01n
Output data Bit 01, inverted
8
vcc supply voltage
positive power supply
9q00p
Output data Bit 00, direct
LVDS output
10 q00n
Output data Bit 00, inverted
11
vcc supply voltage
positive power supply
12clop
LS output clock, direct
LVDS output
13clon
LS output clock, inverted
14n/c
not used15
vee supply voltage
negative power supply
16 cosel1 CMOS input
LS output clock phase control
17 cosel2 CMOS input
LS output clock phase control
18 cosel3 CMOS input
LS output clock phase control
19
lol
CMOS output
PLL no-lock indicator
20
ftr
External filter connection
21
vee supply voltage
negative power supply
22 ceoff
CMOS input Clock multiplication/division mode
23
n/c
not used24
n/c
not used25
vcc supply voltage
positive power supply
26
vcc supply voltage
positive power supply
27
crn
LVDS
LS reference input clock, direct
input
28
crp
LS reference input clock, inverted
29
vcc supply voltage
positive power supply
30
vee supply voltage
negative power supply
31
vee supply voltage
negative power supply
32
vcc supply voltage
positive power supply
33
cen
CML input
HS input clock, direct34
cep
CML input
HS input clock, inverted
35
vcc supply voltage
positive power supply
36
vee supply voltage
negative power supply
37
vee supply voltage
negative power supply
38
vcc supply voltage
positive power supply

Rev. 1.5.2

5

Terminationor connection
GND
GND
Needs external 100Ohm
between pins
Needs external 100Ohm
between pins
Needs external 100Ohm
between pins
Needs external 100Ohm
between pins
GND
1MOhm to vee
1MOhm to vee
1MOhm to vee

GND
1MOhm to 2.5V

100Ohmbetween pins
GND
GND
50Ohm to vcc
50Ohm to vcc
GND
GND

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Pin
Pin
Pin
# nametype39
dn
Analog input
40
dp
Analog input
41
vcc
supply voltage
42veesupply voltage
43veesupply voltage
44
vcc
supply voltage
45
n/c
46
res
CMOS input
47 ondac
CMOS input
48 vlsbcrl Analog voltage
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
Rev. 1.5.2

vrefcrl Analog voltage
veesupply voltage
veesupply voltage
n/c
n/c
n/c
vcc
supply voltage
odp
Analog output
odn
Analog output
vee
supply voltage
n/c
q15p
LVDS output
q15n
vcc
supply voltage
q14p
LVDS output
q14n
vcc
supply voltage
q13p
LVDS output
q13n
vcc
supply voltage
q12p
LVDS output
q12n
vcc
supply voltage
q11p
LVDS output
q11n
vee
supply voltage
veesupply voltage
vcc
supply voltage
q10p
LVDS output
q10n
vcc
supply voltage

Pinfunction
HS input data, direct
HS input data, inverted
positive power supply
negative power supply
negative power supply
positive power supply
not used
Divider reset (active-high)
DAC enable/disable
ADC thresholdvoltages controls
negative power supply
negative power supply
not used
not used
not usedpositive power supply
DAC output signal, direct
DAC output signal, inverted
negative power supply
not used
Output data Bit 15, direct
Output data Bit 15, inverted
positive power supply
Output data Bit 14, direct
Output data Bit 14, inverted
positive power supply
Output data Bit 13, direct
Output data Bit 13, inverted
positive power supply
Output data Bit 12, direct
Output data Bit 12, inverted
positive power supply
Output data Bit 11, direct
Output data Bit 11, inverted
negative power supply
negative power supply
positive power supply
Output data Bit 10, direct
Output data Bit 10, inverted
positive power supply
6

Terminationor connection
50Ohm to vcc
50Ohm to vcc
GND
GND
640KOhm to vee
1MOhm to vee
12KOhm to vcc
12KOhm to vcc
GND
GND

50Ohm to vcc
50Ohm to vcc
GND
Needs external 100Ohm
between pins
Needs external 100Ohm
between pins
Needs external 100Ohm
between pins
Needs external 100Ohm
between pins
Needs external 100Ohm
between pins
GND
GND
Needs external 100Ohm
between pins

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Pin PinPin# nametype
80 q09p
LVDS output
81 q09n82
vcc supply voltage
83 q08p
LVDS output
84 q08n85
vcc supply voltage
86 q07p
LVDS output
87 q07n88
vcc supply voltage
89 q06p
LVDS output
90 q06n91
vcc supply voltage
92 q05p
LVDS output
93 q05n94
vcc supply voltage
95 q04p
LVDS output
96 q04n97
vcc supply voltage
98 q03p
LVDS output
99 q03n
100 vcc supply voltage

Pinfunction
Output data Bit 09, direct
Output data Bit 09, inverted
positive power supply
Output data Bit 08, direct
Output data Bit 08, inverted
positive power supply
Output data Bit 07, direct
Output data Bit 07, inverted
positive power supply
Output data Bit 06, direct
Output data Bit 06, inverted
positive power supply
Output data Bit 05, direct
Output data Bit 05, inverted
positive power supply
Output data Bit 04, direct
Output data Bit 04, inverted
positive power supply
Output data Bit 03, direct
Output data Bit 03, inverted
positive power supply

Terminationor connection
Needs external 100Ohm
between pins
Needs external 100Ohm
between pins
Needs external 100Ohm
between pins
Needs external 100Ohm
between pins
Needs external 100Ohm
between pins
Needs external 100Ohm
between pins
Needs external 100Ohm
between pins

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings presented in Table 4 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced to
ground (vee).
Table 4. Absolute Maximum Ratings

Parameter
Supply Voltage (vcc)
Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Rev. 1.5.2

Min

-40
10
10

7

Max
4.0
4.0
1.4
+100
+100
98
98

Units
V
W
V
ºC
ºC
%
%

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ELECTRICAL CHARACTERISTICSPARAMETERTYP MAXUNIT
COMMENTS
General Parameters
3. 4
3.5
3.6
V
±3%
vcc
0.0
V
External ground
vee
Ivcc
1020
mA
Power consumption
3.57
W
Junction temperature
-25
50
125
°C
Analog Input Data (dp/dn)
Bandwidth
0.0
20
GHz
CM Level
vcc-0.8
vcc
VMust match for both inputs
Linearity range±110mV
Differential or SE, p-p
HS Input Clock (cep/cen)Frequency
DC
15
GHz
Swing
0.2
0.8
V
Differential or SE, p-p
CM Voltage Level
vcc-0.8
vcc
VMust match for both inputs
Duty Cycle
40
50
60
%
LS Reference Input Clock (crp/crn)
Frequency
560
688
MHz
1/16 of VCO frequency
CM Level
0.2
vcc
V
Voltage Swing
100
800
mV
Differential
Duty Cycle
40
50
60
%
Output Data (q00p/q00n to q15p/q15n)
Data Rate
DC
3.75
Gbps
CM Level
1.2
V
Nominal for LVDS interface
Amplitude range
250
350
mV
Rise/Fall Times
TBD
ps
20%-80%LS Output Clock (clop/clon)
Frequency
f/4
f/8
f/16
GHz
Selectable. Here f is the PLLor HS input clock frequency
CM Level
1.2
V
Nominal for LVDS interface
Amplitude range
250
350
V
JitterTBD
psDuty Cycle
50%
DAC Output (odp/odn)
Voltage Swing
250
350
mV
Single-ended. p-p
CM Levelvcc-(voltage swing)/2
V
Analog Control Signals (vrefcrl, vlsbcrl)
Voltage rangeV
See Table 1
CMOS Control Signals (cosel1, cosel2, cosel3, ceoff, res, ondac)
Logic “1” levelvee+2.3
vee+2.5
V
Logic “0” level
vee+0.2
V
Frequency
3.5
GHz
Rev. 1.5.2

MIN

8

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ELECTRICAL SPECIFICATIONSParameter
ENOB (5GS/s)
ENOB (10GS/s)
SFDR (5GS/s)
SFDR (10GS/s)
SINAD (5GS/s)
SINAD (10GS/s)
DNL
INL

Rev. 1.5.2

Conditions
fin = 3.9GHz
fin = 7.8GHz
fin = 3.9GHz
fin = 7.8GHz
fin = 3.9GHz
fin = 7.8GHz

Min

-0.2
-0.2

9

Typical
3.39
3.23
30.13
28.78
-22.15-21.19

Max

0.2
0.2

Units
bits
bits
dBFS
dBFS
dB
dB
lsbs
lsbs

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PACKAGE INFORMATIONThe chip die is housed in a custom 100-pin CQFP package shown in Fig. 3.

Fig. 3. CQFP 100-Pin Package Drawing (All Dimensions in mm)

Rev. 1.5.2

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The package provides a center heat slug located on its back side to be used for heat dissipation.
ADSANTEC recommends for this section to be soldered to the vcc plain, which is power for a positive
supply.
The part’s identification label is ASNT7120A-KMA. The first 9 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin out
count.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

REVISION HISTORY
Revision
1.5.2
1.4.2
1.4.1
1.3.1
1.2.1

1.1.1

1.0.1

1.0.0

Rev. 1.5.2

Date
Changes
02-2020 Updated Package Information
07-2019 Updated Letterhead
09-2015 Removed cpcsel function (Pinout diagram, block diagram, description, Terminal
Functions table, Electrical Characteristics table)
08-2015 Added Electrical Specifications table
07-2015 Updated title
Updated Absolute Maximum Ratings section
Revised Electrical Characteristics table
Updated Package Information section
04-2015 Corrected pin out diagram (cpcsel pin name)
Corrected description
Corrected description of ADC threshold controls
Modified Terminal Functions table03-2015 Updated block diagram
Corrected description
Corrected power consumption value
Corrected absolute maximum power
08-2014 First release11

February 2020