Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT5115-KMM
High Sensitivity DC-to-32Gbps Dual D-Type Flip-Flop

Exhibits low jitter and limited temperature variation over industrial temperature range



4ps set-up/hold time capability

88% clock phase margin for retiming of data input eyeFully differential CML input interfaces

Fully differential CML output interface with 400mV single-ended swingSingle +3.3V or -3.3V power supplyPower consumption: 1.02W

Fabricated in SiGe for high performance, yield, and reliability

Custom CQFP 44-pin package
vcc

vcc
vee

Input data single-ended common mode controls

vcc
1ndcin1pvcc

Sensitive input data buffer with increased CM range that is ideal for sampling applications

dcin1nc1pAdditional input buffer / level shifter for improved protection

vcc

vcc

High speed broadband 2-channel D-Type Flip-Flop for data retiming with full rate clockc1n

vcc
veevcc

vcc

d1p

q1p

vcc

vcc

d1nq1nASNT5115

vcc

vcc

d2p

q2p

vcc

vcc

d2n

q2n

vcc

vcc
veevccdcin2n

vcc

vcc

1

dcin2pc2n

vcc

c2p

vcc

vcc

Rev. 1.2.2

veevccJuly 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
vcc

vcc

dcin1p

50

83

125

DFF
core

d1p
d1n
125
dcin1n

q1p
q1n
5083
vcc

50vcc

vcc

50

83

125

DFF
core

d2p
d2n
125
dcin2nvcc

c1p
c1nvccdcin2pvcc50

q2pq2n5083vcc50

vcc50

vcc
c2pc2nvcc

Fig. 1. Functional Block Diagram

The temperature stable ASNT5115-KMM SiGe IC provides broadband data retiming functionality and isintended for use in high-speed measurement / test equipment. The dual-channel IC shown in Fig. 1 cansample up to 32Gbps data signals d1p/d1n and d2p/d2n with up to 32GHz clock sources c1p/c1n andc2p/c2n to create 32Gbps retimed NRZ data outputs q1p/q1n and q2p/q2n. The data input buffers aredesigned to have increased input signal sensitivity and are able to operate over a wider range of input
common mode (CM) voltages. The actual common mode voltage levels on data inputs d1p/d1n andd2p/d2n can be adjusted by applying voltages between vee and vcc to the corresponding control inputs
dcin1p/dcin1n and dcin2p/dcin2n.
The part’s I/O’s support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.
It should be noted that control inputs dcin1p/dcin1n and dcin2p/dcin2n should be always connected tovoltage sources to ensure correct 50Ohm terminations for the data inputs.
Rev. 1.2.2

2July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

POWER SUPPLY CONFIGURATION
The part can operate with either a negative supply (vcc = 0.0V = ground and vee = −3.3V), or a positivesupply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os need AC termination
when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be neededfor each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vcc).
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
Input Data Voltage Swing (SE)Input Clk Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Rev. 1.2.2

Min-4010103

Max-3.6
1.2
1.7
1.7+90+100
98
98

Units
VW
VVºC
ºC%%

July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

TERMINAL FUNCTIONSTERMINAL
NameNo.
Typed1p
d1nd2pd2nc1pc1nc2pc2nq1pq1nq2pq2ndcin1pdcin1ndcin2pdcin2nNamevcc
veeRev. 1.2.2

3739
4143303246211917152628
810DESCRIPTION

CML
Input

High-Speed I/Os
Differential data inputs with internal SE 50Ohm termination tovcc

CML
Input

Differential clock inputs with internal SE 50Ohm termination
to vccCML
Differential data outputs with internal SE 50Ohm termination
Output to vcc. Require external SE 50Ohm termination to vcc

Input

DC Controls
Input data DC common mode voltage level controls. Should bealways connected to voltage sources!

Supply and Termination Voltages
Description
Pin Number
Positive power supply
1, 3, 5, 7, 9, 11, 12, 14, 16, 18, 20, 22, 23, 25,(+3.3V or 0V)27, 29, 31, 33, 34, 36, 38, 40, 42, 44
Negative power supply
2, 13, 24, 35(0V or -3.3V)

4July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERMIN

TYP MAXUNIT
COMMENTS
General Parameters
0.0V
External groundvcc-3.47-3.3-3.14
V±5%vee
Ivcc
310340mA
Power consumption
1.02
1.12
W
Junction temperature-25
50125°C
HS Input Data (d1p/d1n, d2p/d2n)
Data rate
0.0
3240
Gbps
Swing
0.01
1.3
V
Differential or SE, p-p
CM Voltage Level
vcc-0.7+sw/2 vcc+0.6-sw/2
VMust match for both inputs
HS Input Clock (c1p/c1n, c2p/c2n)Frequency
0.0
3240
GHz
Swing
0.05
1.3
V
Differential or SE, p-p
CM Voltage Level
vcc-0.7+sw/2 vcc+0.6-sw/2VMust match for both inputs
Duty Cycle
405060%
Clock phase margin
868890%
For reliable data latching
HS Output Data (q1p/q1n, q2p/q2n)
Data rate
0.0
3240Gbps
Logic “1” levelvcc-0.05 vcc-0.03 vcc-0.01
V
Logic “0” levelvcc-0.46 vcc-0.44 vcc-0.42
V
With external 50Ohm DC termination
Jitter0.15
ps
Peak-to-peak at 32Gbps
DC Input Controls (dcin1p/dcin1n, dcin2p/dcin2n)
Max level
vcc + 1.0VMin levelvcc - 1.0
V

PACKAGE INFORMATIONThe chip die is housed in a custom 44-pin CQFP package shown in Fig. 2. Even though the package
provides a center heat slug located on the back side of the package to be used for heat dissipation,ADSANTEC does NOT recommend for this section to be soldered to the board. If the customer wishes
to solder it, it should be connected to the vcc plain that is ground for the negative supply or power for thepositive supply.
The part’s identification label is ASNT5115-KMM. The first 8 characters of the name before theunderscore identify the bare die including general circuit family, fabrication technology, specific circuit
type, and part version while the 3 characters after the underscore represent the package’s manufacturer,type, and pin out count.
This device complies with the Restriction of Hazardous Substances (RoHS) per EU 2002/95/EC for all six
substances.
Rev. 1.2.2

5July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Fig. 2. CQFP 44-Pin Package Drawing (All Dimensions in mm)

Rev. 1.2.2

6

July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.2.2
1.2.1

Date07-2019
05-2013

1.1.1
1.0.1

05-201303-2013

Rev. 1.2.2

Changes
Updated Letterhead
Removed data duty cycle specification
Corrected terminal functions
Corrected pin out diagram
First release

7July 2019