Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT8142-KMC
Generator of DC-to-23Gbps PRBS with Selectable Polynomials

DC to 23Gbps output data rateAdditional output delayed by half of the sequence period

Asynchronous reset signal for elimination of the “all zeros” initial state

Fully differential CML input interface

Fully differential CML output interface with 400mV single-ended swingSingle +3.3V or -3.3V power supplyPower consumption: 740mW

Custom CQFP 24-pin package

qpvee

vcc

Selectable power of the Polynomial

qn

vcc

Full-length (215-1) or (27-1) pseudo-random binary sequence (PRBS) generator

vcc

vee

vcc

vcc

clk_p

rstn_p

ASNT8142

vcc

vcc

clk_n

rstn_nvcc

vcc

Rev. 1.1.2

1vcc

qxorp

vcc

qxorn

vcc

vee

off15

July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION

DDDDD

D

qp/n

clkp/noff15

to all DFFs

rstnp/n
DDDDD

qxorp/nFig. 1. Functional Block Diagram

The ASNT8142-KMC SiGe IC shown in Fig. 1 provides a selectable full 32767-bit or 127-bit long
pseudo-random binary sequence (PRBS) signal according to either a (x15 + x14 + 1), or a (x7 + x6 + 1)
polynomial respectively, where xD represents a delay of D clock cycles. This is implemented as a linear
feedback shift register (LSFR) in which the outputs of either the fifteenth and fourteenth, or seventh andsixth flip-flops are combined together by an XOR function, and provided as an input to the first flip-flopof the register. The polynomial is selected through the external control signal off15.
The LSFR-based PRBS generator produces binary states, excluding the “all zeros” state that is illegal for
the XOR-based configuration. To eliminate this state that locks the LSFR and prevents PRBS generation,
an asynchronous external active-low preset signal rstnp/rstnn is implemented in the circuit. When thepreset is asserted, LSFR is set to the All-“1” state that is enough for activation of the PRBS generation.
When the preset is released, the chip delivers one consecutive bit of the PRBS signal to output pins qp/qn
per each rising edge of clock clkp/clkn, starting from the above mentioned state.
An additional copy of the same PRBS signal delayed by half of the sequence period is delivered to pins
qxorp/qxorn, and can be used to double the frequency of the output signal using an external multiplexer(e.g. ASNT5150 part) as shown in Fig. 2.

Rev. 1.1.2

2July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT8142qp
qnclkpclkn
Clkqxorp
qxorn

Main
PRBS

ASNT5150

20Gb/sMUX 2:1

PRBS
40Gb/sDelayed
PRBS

Fig. 2. PRBS Frequency Doubling

The simulated eyes for both signals are shown in Fig. 3.

Fig. 3. 20Gbps PRBS Output Eye Diagram (Simulation, Slow Corner, 125oC)

All I/O stages are back terminated to vcc with on-chip 50Ohm resistors and may be used in either DC orAC coupling modes (see also POWER SUPPLY CONFIGURATION). In the first mode, the input
signal’s common mode voltage should comply with the specifications shown in ELECTRICAL
CHARACTERISTICS. In the second mode, the input termination provides the required common mode
voltage automatically. The differential DC signaling mode is recommended for optimal performance.

POWER SUPPLY CONFIGURATION
The part can operate with either a negative supply (vcc = 0.0V = ground and vee = −3.3V), or a positivesupply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os need AC terminationRev. 1.1.23July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be neededfor each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings may cause damage to this product and/or lead toreduced reliability. Functional performance is specified over the recommended operating conditions for
power supply and temperature only. AC and DC device characteristics at or beyond the absolutemaximum ratings are not assumed or implied. All min and max voltage limits are referenced to ground(assumed vcc).
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max-3.60.86
1.0+90+1009898

UnitsVWVºCºC%%TERMINAL FUNCTIONSTERMINAL
NameNo.
Type
rstn_prstn_nclk_p
clk_n
qpqnqxorp
qxorn
off15

Namevccvee
Rev. 1.1.2

DESCRIPTION

High-Speed I/Os11
CML Differential high-speed asynchronous reset (active low) inputs
input with internal SE 50Ohm termination to vcc
921
CML Differential clock input signals with internal 50Ohm
input termination to vcc
2317
CML Differential data outputs. Require external SE 50Ohm
output termination to vcc
155
CML Differential delayed sequence data outputs. Require external SEoutput
50Ohm termination to vcc
3Control Signal
7
CMOS 3.3V CMOS input with internal 1MOhm termination to vcc
input
Supply and Termination Voltages
Description
Pin Number
Positive power supply
2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24(+3.3V or 0)
Negative power supply
1, 13, 19(0V or -3.3V)
July 20194

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERMIN

TYP MAX UNIT
COMMENTS
General Parameters-3.1-3.3-3.5
V±6%
vee0.0V
External ground
vcc
Ivee
210
240mA
Power consumption
740mW
Junction temperature -40
25125°C
HS Input Clock (clkp/clkn)
Frequency
DC23
GHz
Swing
0.05
0.8
V
Differential or SE, p-p
CM Voltage Level
vcc-0.8
vcc
VMust match for both inputs
HS Output Data (qp/qn, qxorp/qxorn)
Swing (SE)
280
440mV
CM Voltage Level
vcc-0.8vcc
VOutput Jitter
2.5ps
Peak-to-peak
Reset Signal (rstnp/rstnn)
FrequencyDC15
GHzRise time
20%of the clock period
Recovery time
36
psSwing
0.05
0.8
VDifferential p-p
CM Voltage Level
vcc-0.8vcc
V
PRBS Select Signal (off15)
Input low levelveevee+0.4
VDo not apply voltages below vee!

PACKAGE INFORMATIONThe chip die is housed in a custom 24-pin CQFP package shown in Fig. 4. The package provides a center
heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for thissection to be soldered to the vcc plain, which is ground for a negative supply, or power for a positivesupply.
The part’s identification label is ASNT8142-KMC. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
The IC complies with the Restriction of Hazardous Substances (RoHS) per EU 2002/95/EC for all 6
substances.

Rev. 1.1.2

5July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Fig. 4. CQFP 24-Pin Package Drawing (All Dimensions in mm)

Rev. 1.1.2

6July 2019

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.1.2
1.1.1

1.0.1
1.0.0

Rev. 1.1.2

Date
Changes
07-2019 Updated Letterhead
10-2017 Corrected power and current consumption values
Corrected absolute maximum power
Added specification for the PRBS select input off15
11-2015 Initial Release09-2014 Preliminary Release

7

July 2019