JAERI-Conf 95-021

PB23Development of Dynamic Pattern I/0 Modules
for Advanced Accelerator Operation
E.Takada, N.Araki, A.ltano*, M.Kanazawa, M.Kumada, K.Noda, S.Sato,
E.Hishitani **, S.Arai** and H.Nakagawa**
Accelerator Physics & Engineering Division, National Institute of Radiological Sciences, Chiba 263, Japan* Public Health & Environment Department, Hyogo Prefectural Government, Kobe 650, Japan** Electronic & Control Systems Department, Hitachi Zosen Corporation, Osaka 554, Japan
Abstract
Dynamic control of beam parameters (energy,C.O.D. etc.) is essential for advanced utilization ofsynchrotron beam. DPI/DPO modules are now underdevelopment to switch among
various excitation
patterns of main magnets and rf system while thesynchrotron is operating.
DPI/DPO are VMEbus modules which provide
maximum 20-bit parallel input/output port withindependent 16-bit control signal port, where up toabout 125kHz external clock is applicable.
Dynamic
switching of output pattern and other intelligent
functions are performed by two RISC microprocessors,
one for control and the other for calculation.
1.

INTRODUCTION

Operationofsynchrotron
magnetsarecharacterized by repetitive pattern which consists ofinjection, acceleration, extraction, deceleration andreset of beam.
In order to accelerate the beam
without losses, each field of lattice magnets, BM andQF/QD, should be excited in a matched strength. Thisis called as "tracking".
Power supplies of latticemagnets, accordingly, should be precisely controlled insynchronization with the 1,200Hz trigger timing pulseof24 phase thyrister converter for forcing power source.
HIMAC has already made use of FDI/FDO
modules which were developed for this purpose [1].
Present control system of magnet power supplies works
well, including event triggers that are generated fromanother FDO module for injection etc.
However, anadvancement in heavy ion therapy requires more
flexible and dynamic control of synchrotron operation,
as the beam delivery with pulse-to-pulse energy shift isenvisaged for cancer treatment irradiation of threedimensional scanning for HIMAC and Particle Therapy
Project in Hyogo prefecture [2].
An rf system should also be operated incoordination with main magnet excitation pattern, but
the clock system differs from that of main magnet
power supply.
T clock of about 50kHz and B clock ofmax. 120kHz are used for rf control.
Further, B clock

is of bi-directional operation to stand with fluctuation ofmagnetic field for both acceleration and deceleration ofbeam.
Although the dual memory mechanism isutilized and the digital control system operates
successfully [3], dynamic pattern switching is not fully
realized.
Dynamic switching of these patterns (bothmagnets and rf) is demanded in various aspects ofbeam operations.
For example, it is required toswitch an arbitrary combination of magnets simultaneously during beam tuning or to use a set of excitation patterns as mentioned above.
Usage is also
expected to measure beam parameters, chromaticity
e.g., to initialize magnets, and to achieve digital feedback control (Iterative control or Self-study control).
Thus a dynamic pattern switch/selection isinevitable in advanced synchrotron control, which is
now possible with the help of recent high-performance
processors.
In order to select va rious excitation
patterns of main magnets and rf system dynamically,
DPI/DPO modules are now under development.
This
paper describes DPI/DPO modules, with emphasis on
the hardware aspect of DPO, which is developed priorto DPI.
2.

FEATURES OF THE DPO

A lot of high performan'ce RISC microprocessors
for embedded system has flourished in a wide range ofelectronic appliances.
After our investigation ofabilities to handle many external interrupts and tocontrol timer/counter substantially, we have made achoice of Hitachi Super-H (SH) series CPU which uses
a 32-bit RISC core optimized for high speed and low
power consumption.
Another advantage of SH-1
CPU is several on-chip peripherals to eliminate many
additional devices.
For a dynamic selection of a required excitation
pattern from several tens to hundreds of patterns, it isnecessary to discriminate many commands and toprepare enough amount of memory to store all relevantdata.
For this purpose 12-bit external control signal
and 16MB memory are employed.
VSBbus is the subsystem standard of VMEbus.

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JAERI-Conf 95-021

Pause & Rerun
Command to break temporarily or rerun
pattern output for measurement of beam lifeetc.
Selection of pattern
Command to select any excitation pattern.
Decoding method is effective to expand therange of selection, although a surplus strobe
signal is necessary. It is capable to select not
only any single excitation pattern but also a
set of patterns and to operate partly anygrouped magnets by means of masking bit, ofwhich feature is applied to Start or Stop event
when the initialization of a part of magnets isrequired.
Change signal from T clock to B clock
Change signal from B clock toT clock

It is provided to form a digital feed-back loop byinterconnection between DPO and DPI, which isexpected to correct C.O.D., for example, in real-time.
Iterative control of magnet power supplies [4] will bealso benefited by the DPI-DPO direct connection.
Table 1 shows the outline specification of DPO.

And the block diagram is shown in Fig.l.
CPU and Memory
Multiple CPU system is provided for this module.
SH-1 CPU serves to control communications with
SH-1
VMEbus, VSBbus and all input & output ports.
forprovided
isalso manages SH-2 CPU whichofcontentions
To avoid bus
dedicated calculation.
multiple CPU system, separate local bus is provided foreach CPUs.
16MB DRAM will be used in 3 byte-word format
pattern memory to cover system requirement of rf andBM operation. User supplied programs can be loaded
into the DRAM of SH-1 or the dedicated SRAM of SH-2
and executed from local CPU, respectively.
andEach CPU responds to commands
dual
32kB
environment parameters placed in eachported SRAM which serves the accesses from theVMEbus or the local bus through the arbitration logic
which intervenes synchronously with one for anotherwhen simultaneous accesses occur.
SH-2 is provided on the mezzanine board to bechangeable to SH-3 CPU in future.
Input/output ports are also provided on the othermezzanine board in order to change RS485 to TTL orother interfaces.

2-1.

External clock
4 bits are provided for external clocks.
• Pattern start signal (Master Clock or Rf Capture)
cycle ofIt corresponds to repetitivesynchrotron operation, typically -1Hz.
Base clock (1,200Hz or 50kHz)
1,200Hz is fundamental clock distributed from
PLL.
Incremental B clock for rf (B+ clock)
Decremental B clock for rf (B- clock)
Maximum speed of B clock is presumed to be
120kHz in order to cover the BM excitation
rate of 2. 4T/sec at 0.2G/pulse clock.

2-2.

External control signals
12-bit signal is decoded and recognized as
These events are executed
following various events.
after next Master Clock except for Change signals thatare executed immediately.
Start & Stop
Command to start or stop pattern output/input
to devices altogether.

2-3.

Looked-Up Table
LUT is a memory to convert any data placed onThisthe address line to another data immediately.
feature is useful to convert an accounted value of B
clock to the rf frequency which is not always linear.
80k steps of table is required when BM is excited up toThen dual 80k x 20-bit
1.6T at B clock of 0.2G.
memory is provided, of which one serves to make data
output and the other receives next data simultaneously.
2-4.

2-5. Software functions of DPO
1) SH-1 CPU for control
Communication with Host CPU of IOC on
VMEbusCommunication with SH-2 CPU for calculation
Execution of event signal
VMEbus and VSBbus control
Initialization and placing data on LUT
Smoothing control of pattern
Data output synchronized with external clock2) SH-2 CPU for calculation
Communication with SH-1 CPU for control
Calculation of feed-back control or data filtering
Smoothing calculation of pattern
3.

CURRENT STATUS AND DISCUSSION

DPO with basic firmware will be prepared for
performance test by the end of this year. DPO will also
provide a function of timing pattern generator which
produces .dynamically various event control timings.
System considerations, such as pattern data-baseconstruction and management, division of tasks among
host computer and DPIIDPO, are necessary to specify
further details and to establish the best way of usage.
High-speed digital feed-back control with high-313-JAERI-Conf 95-021

accuracy is attractive to challenge many technicalmatters of instabilities in various synchrotron
operation.
We expect that the combination ofDPI/DPO will be useful to reduce beam ripple or tostabilize beam position by means of high-speed dataacquisition and processing.
ACKNOWLEDGEMENTS
We would like to appreciate those who developed
the present control system of HIMAC and enlightened
us with profound understandings and discussions;
Especially, Mr.· N.Tsuzuki of Fuchu Works, Toshiba
Corp. (rf control), Mr. S.Sakamoto of MIT Instr. Inc.
(FDI/FDO system), Mr. T.Nakayama of Hitachi lnf. &Cont. Systems Inc. (magnet p/s system) and · Prof.
K.Sato of Osaka University are acknowledged withsincere gratitude.
We would like to thank Dr. K.Kawachi, Dr.
S.Yamada and members of Accelerator Physics &Engineering Division of NIRS for discussions.

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REFERENCES..

N[1] E.Takada et al., Proc. 9th Symp. Ace. Sci. Tech.,
KEK, Japan, November 1993, pp. 73-75.
[2] A.ltano et al., in these proceedings.
[3] E.Takada et al., Proc. HEACC'92, Hamburg, Germany, July 1992, pp.763-765.
[4] E.Takada, T.Nakayama, E.Hishitani, HITACHIZOSEN TECHNICAL REVIEW 53 (text in Japanese),
December 1992 pp.317-323.

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Fig.l

Block Diagram of DPO

Outline Specification of DPO
Mezzanine Hoard
Mezzanine Hoard
for calculation
for J/U adaptation
SH7034(SH-1)
SH7604(SH-2)
CPU• 4kH cache memory
Two 16bit bi-directional• 4kH On-chip RAM• Hardware multipliercontrol signal port with strobe• 64kH On-chip RUM• Hardware multiplier• Hardware divider(Upto-isolated RS485 interface)• 15ch. Ext. interrupt handler• 9ch. Ext. interrupt handler• 2ch. DMA controller• 4ch. DMA controller• 5ch. Timer/Counter• 16bit Counter
20bit+Strobe output port
• 16bit Timing pattern gen;
• Watch-dog timer(Upto-isolated RS4H5 interface)• lch. Serial comm. port
• Watch-dog timer• 2ch. Serial comm. port
• Universal J/U ports
20MHz (16MIPS)
2K7MHz (25MIPS)
Clock
12gkH with zero walt state
SRAM
256kH with zero wait state
DRAM
16MH with zero walt state
Dual-ported SHAM 32kH with one clock wait state 64kH with one clock wait state
LUTSRAM3g4kH with 20bit U/D counter.Front panel
lobit Status Uill
functions
Reset switch
VMEbus J.Ecg;,n compatible slave interface (A24,D16)
Hus spec.
VSHbus J.Ecgzl compatible master/slave interface
OperatingPower source: ~ V ± 5% , typ. 3A
condition
5V± 10%, typ.l.5A (J/U isolation p/s supplied from front connector)
Temperature : O"C-50"C
Humidity : 30%-90% (Non-condensing)
TABlE 1Main Hoard-314-"

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