=-- =-----====-;=- - - - Maintenance Library-~-

2740 Communication Terminal Model 1
2740 Communication Terominal Model 22741 Communication Terminal
Theory of Operation

SY27-0013-4

PREFACE
This manual describes the theory of operation of the
IBM 2740 Modell (2740-1), 2740 Model 2 (2740-2),
and 2741 Communication Terminal and special features. To use this manual, the reader must be thoroughly familiar with these publications:

1. SLT Packaging and Documentation, SR23-2916
2. Introduction to Teleprocessing, Z25-2522
3. Common-Carrier Facilities for Teleprocessing,
Z25-2529
4. 2740/2741 Communication Terminal, Operator's Guide, GA27-3001
5. IBM Line Adapters (Modems), 8226-3003

In addition, the reader must completely understandthe operation of the Selectric
I/O.
The 2740/41 Communication Terminal Modell,
2740 Communication Terminal Model 2. FE Diagram
Manual, SY27-0014, is required to follow the
explanations in the "Functional Units, fI "Principles
of Operation, " and "Features" sections of thismanual.
All figures in this manual are positive logic--that
is, a positive level is required to condition ANDs,
ORs, etc. Triggers and latches also require a positive level to be turned on or off.

Sixth Edition (January 1973)
This is a reprint of SY27-0013-3 incorporating changes issued in Technical Newsletter
SY27-1056, dated June 10, 1970.
Changes are periodically made to the information herein; before using this publicationin connection with the operation and/ or repair of the system or equipment, refer to thelatest Technical Newsletter that is applicable and current.

This manual has been prepared by the IBM Systems Development Division, Publications
Center, Department EOl, P.O. Box 12195, Research Triangle Park, North Carolina
27709. A form for reader's comments is provided at the back of this manual. If theform has been removed, comments may be sent to the above address. Comments become the property of IBM.

© COpyright International Business Machines Corporation 1966, 1968, 1969, 1973®

2740/2741 SRL/FE Publications Availability Guide

TP SRL
Bibliography

GA24-3089

TP System Summary

DOS BTAM..-._ _ _Pr_og_r_a_m_m_in_g_l_n_fo_rm_a_t_io_n_ _ _-1 DOS Q TAM (MCP)OS BTAMOS QTAM (MCP)

GA24-3090

Component
Physical Planning/OEMI

Description

FE Information

2740 GA24-3403
2741 GA24-3415

Physical
Planning

Operator1s
Guide2740 GA24-3423
2741 GA24-3424

2740 }GA27-3001
2741

FETOM

2740 }
2741
SY27-0013

FEMM

Terminal
Physical Planning
Template
GX27-2900

2740 } SY27-0035
2741

OEMI

FEMDM

2740 } GA27-3002
2741

2740 } SY27-0014
2741

I
J
IPC
2740 Mod 1 }2741
2740 Mod 2
Comm Term PrinterS229-9505
S131-0001
S123-1008

GC30-5001
GC30-5004
GC30-2004
GC30-2005

CONTENTS

CHAPTER 1. INTRODUCTION
2740 COMMUNICATION TERMINAL, MODEL 1
Modes of Operation
Local
Communicate
Special Features (2740-1)
Record Checking
Automatic EOB
Dial-Up
Transmit Control
Station Control
2760 Attachment
2741 Communication Terminal
Special Features (2741)
Dial-Up
Receive Interrupt
Transmit Interrupt •Typamatic
Print Inhibit CPU Controi

1-1
1-1
1-3
1-3
1-3
1-3
1-3
1-3
1-4
1-4
1-4
1-4

2740 COMMUNICATION TERMINAL, MODEL 2
Modes of Operation
Local
Communicate
Special Features (2740-2)
Buffer Expansion
Buffered Receive
Telegraph Line Adapter
Speed Base--600 bps
Header Control
Edit
Document Insertion
Split Platen
Record Checking
Data Representation
Character Format
Data Flow (2740-1/2741)
Data Flow (2740-2)
Enter
Transmit
Receive
Buffer Print
Buffer Storage
Storage Operation
Character Storage Concepts
Buffered Receive Feature
Transmit Status/Answerback (2740-2)

1-6
1-7
1-7
1-7

CHAPTER 2. FUNCTIONAL UNITS
S-Register
Serializa tion (Sending,)
Deserializa tion (Receiving)
Serdes ClockControl Clock
1B-Register (2740-1/2741)
1B-Register (2740-2)
Generated Data
2B-Register (2740-1/2741)
2B -Register (2 740-2)
Generated Data

1-4A

1-5
1-5
1-5
1-5
1-5
1-5

1-8
1-8
1-8
1-8
1-8
1-9
1-9
1-9
1-10
1-10
1-10
1-11
1-12

1-13
1-13
1-14
1-14
1-14
1-14
1-16
1-16

1-19
1-19

2-1
2-1
2-1
2-2

2-3
2-3
2-4
2-4
2-4
2-5
2-5

Print and Function Decode
Print Decode
Function Decode
Strobe and I/O Cycle
Communicate/Local and Status
Communicate/Local
Statu<;
Operate Trigger
Buffer Storage
Magnetic Core Theory
Odd-Even Core Scheme
Character Cycle
Buffer Storage Address Counter
Bit Counter
Buffer Address Register
Address Register Control
Buffer Storage Array and Addressing
Memory Clock
Buffer Data Control
Summary of Buffer Storage Operation
Temperature Compensation

CHAPTER 3. PRINCIPLES OF OPERATION
2740 COMMUNICA TION TERMINAL, MODEL 1
Basic Terminal Mode Control
Transmit (Point-to-Point)
Load Control Characters into 1B-Register
Load Text Characters into 1B-Register
Transfer Characters from 1B-Register to S-Register
S -Register to 'Serial Data Out' LineEnd-of-Transmission
Receive (Point-to-Point)
Receive Bid Characters D
Receive Text Characters
Receive End-of-Transmission Character C
2B Overflow Reset
Power On Reset (2740-1/2741)
I/O Motor Control (2740-1/2741)
Keyboard Lock (2740-1/2741)
Initial Lowercase (2740-1/2741)
Incorrect Case (2740-1/2741)
2741 COMMUNICATION TERMINAL
2740 COMMUNICATION TERMINAL, MODEL 2
Terminal Mode Operation
Control Unit
Enter
Start Enter
Enter Characters
Store Character into Buffer from 2B
End Enter
Transmit (2740-2)
Generate and Transmit
Transmit Text Characters
Transmit © or ®
Receive
Buffer Print
Start Buffer Print

©

2-5
2-5
2-6
2-6
2-6
2-6
2-7
2-7
2-7
2-7
2-10
2-11
2-11
2-12
2-12
2-12
2-15
2-15
2-16
2-17
2-17

3-1
3-1
3-1
3-1
3-2
3-2
3-2
3-3
3-3
3-4
3-4
3-5
3-5
3-5
3-6
3-6
3-6
3-7
3-7

3-8
3-10
3-10
3-10
3-10
3-10
3-11
3-11

3-12
3-13
3-13
3-13
3-13

3-13
3-13
3-14

iii

I/O Error Latch
Receive Parity Error Latch
Transmit Parity Error Latch
Transmi t-S ta tus / Answerback
Status and Operational Error Conditions
Terminal to Line Adapter Interface-{All Models)
Signal Ground-AB
Transmitted Data (Serial Data Out)-BA
Received Data (Serial Data In)-BB
Data Set Ready-CC
Request to Send-CA
Clear to Send-CB
Carrier-CF
Originate (used only for 103 F data set)
Data Terminal Ready (used only for 103A data set)-CD

3-14
3-15
3-15
3-16
3-16
3-16
3-17
3-17
3-17
3-17
3-18
3-18
3-18
3-19
3-19
3-19
3-19
3-19
3-19
3-19
3-19
3-20
3-20
3-20

CHAPTER 4. FEATURESSECTION 1. RECORD CHECKING (2740-1/2740-2)
Introduction
Vertical Redundancy Check (VRC)
Longitudinal Redundancy Check (LRC)
End-of-Block (EOB) Check (2740-1)End-of-Block(EOB) Check (2740-2)
Functional Units
Parity Error (VRC)
Error Trigger
LRC Register
Mode Control
Principles of Operation
Transmit EOB Character (2740-1)
Transmit EOB Character (2740-2)
Transmit LRC Character
Receive Check Answerback
Restart
Receive Check Answerb~ck
Receive EOB Character
Receive LRC Character
Transmit Check Answerback
SECTION 2. AUTOMATIC EOB (2740-1)
SECTION 3. DIAL UP (2740-1/2741)
Dial Disconnect
SECTION 4. TRANSMIT CONTROL (2740-1)
SECTION 5. STATION CONTROL (2740-2)
Introduction
Addressing Mode Sequence
Polling Mode Sequence
Functional Units

4-1
4-1
4-1
4-1
4-1
4-2
4-2
4-2
4-3
4-3
4-4
4-5
4-5
4-5
4-6
4-6
4-6
4-7
4-8
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-14
4-15
4-16
4-16

GarbleTime-Out 15
Principles of Operation
Addressing
Transmit Status Answerback

4-16
4-18
4-18
4-18
4-19

Buffer Print Operation
End Buffer Print
Initial Lowercase (2740-2)
Incorrect Case
Keyboard Lock (2740-2)
I/O Motor Control (2740-2)
Line Parity Error (2740-2)
Storage Latches for Error Responses
Electronic Error Latch

iv

Polling
Transmit Poll Answerback
SECTION 6. RECEIVE INTERRUPT (2741)
SECTION 7. TYPAMATIC (2741)
SECTION 8. BUFFER EXPANSION (2740-2)
SECTION 9. BUFFERED RECEIVE (2740-2)
Store Received Characters
Receive Text Buffer to Buffer Print
SECTION 10. HEADER CONTROL (2740-2)
SECTION lL DOCUMENT INSERTION (2740-2)
SECTION 12. SPLIT PLATEN ~2740-2)
SECTION 13. TELEGRAPH (2740-2)
SECTION 14. SPEED BASE--600 BPS (2740-2)
SECTION 15. EDIT (2740-2)
Line Type
Detect Carrier Return
Detect Stop CodeLine Return
Operation
Back Up Control
SECTION 16. 2760 ATTACHMENT FEA TURE
Introduction
IBM 2740-1 Communication Terminal,
Serial 15000 or Higher, with Record Checking
Special Features •IBM 2760 Optical Image Unit •Interlocking
Response Point Coordinates
Filmstrip Motion Control
Image Index Counter •Message Format
Receive Format
Transmit Format
Operation
Receive Text from CPU to 2760
Transmit Message to CPU from 2760
SECTION 17. TRANSMIT INTERRUPT (2741) •SECTION 18. PRINT INHIBIT CPU CONTROL (2741)
CHAPTER 5.

POWER SUPPLIES AND CONTROL

4-21
4-21
4-22
4-23
4-24
4-25
4-25
4-25
4-26
4-27
4-27
4-28
4-28
4-29
4-29
4-30
4-30
4-30
4-30
4-31
4-33
4-33
4-33
4-33
4-33
4-34
4-35
4-35
4-36
4-36
4-37
4-37
4-39
4-40
4-40
4-42
4-43
5-1

CHAPTER 6. CONSOLE AND MAINTENANCE FEATURES
CE Aid Box
Single Cycle
Operation
Space Generator
Check Loop (2740-1/2741)

6-1
6-1
6-1
6-2
6-3
6-3

APPENDIX A. MACHINE CHARACTERISTICS

A-l

APPENDIX B. 2740-2 SPECIAL CIRCUITS

B-1

APPENDIX C. WORLD TRADE IBM 2740 MACHINE LOGICC-l

APPENDIX D. DOCUMENT INSERTION 2740-2 MECHANISM D-1
APPENDIX E.

1971 COMPATIBIUTY FEATURE

E-.1

APPENDIX F. ERROR-RECOVERY TABLES

F -1

INDEX

X-l

ILLUSTRATIONS

FigurePage

FigurePage

1-1 Communication Terminal (2740-1).
1-2 Keyboard (2740-1)
1-3 2740 Terminal Configurations •1-4 2741 Terminal Configurations •1-5 Keyboard (2741).
1-6 Communication Terminal (2740-2)
1-7 Keyboard (2740-2)
1-8 Operator Controls (2740-2)
1-9 Document Insertion Feature
1-10 2740-1/2740-2 Printer Code Conversion
1-11 2741 Printer Code Conversion (Correspondence)
1-12 2740-1/2741 Data Flow
1-13 Enter Data Flow •1-14 Transmit Data Flow (2740-2)
1-15 Receive Data Flow (2740-2)
1-16 Buffer Print Data Flow (2740-2)
1-17 Overall Flow of Outgoing Message (2740-2) •1-18 Comparison of Typed and Stored Message
1-19 Buffer Storage
1-20 Overall Flow of Buffered Receive Incoming Message
1-21 Transmit Status/ Answerback Character •

1-1
1-2
1-3
1-5
1-6
1-7
1-8
1-10
1-11
1-12
1-13
1-15
1-15
1-15
1-15
1-16
1-17
1-18
1-18
1-20

4-6 Station Control, Terminal Configuration •4-7 Addressing and Polling Character Sequence
4-8 Addressing Mode Sequence.
4-9 Polling Mode Se quence
4-10 Normal Mode Flow
4-11 1st Status Character Set in 1B-Register4-12 Typamatic Data Flow
4-13 Line Return Buffer Operation
4-14 IBM 2760 Optical Image Unit Attached to an
IBM 2740-1 Communication Terminal
4-15 Probe, Screen, and Operator's Panel
4-16 Vertical (V) and Horizontal (H) Response Points
4-17 Decimal Values of Characters Transmitted forFilm Control •4-18 Function (F) Control Character

4-14
4-14
4-15
4-16
4-17
4-20
4-23

5-1 2740/2741 Power Supply

5-1

2-1
2-2
2-3
2-4
2-5
2-6
2-7

2-8
2-9
2-11
2-11
2-13
2-14
2-18

6-1
6-2
6-3
6-4
6-5
6-6

6-1
6-2
6-4
6-4
6-4
6-5

Overall Flow of Outgoing Message
Core Theory
Addressing by Current Coincidence and Cancellation.
Buffer Storage Character Cycle
Buffer Storage Address Counter.
Array Wiring and Addressing
Buffer Data and Addressing

1-~

3-1 Generate Control Characters
3-2 Transmit Text Character.
3-3 Incorrect Case

3-3
3-4
3-8

LRC Register Operation
LRC Register Control.
Sequence of Mode Operation
Restart Circuit
Dial-up Interface (103A)

4-3
4-4

4-1
4-2
4-3
4-4
4-5

4-5
4-7
4-11

4-31
4-34
4-35
4-36
4-37
4-38

CE Aid Box
Single Cycle •Space Generator Flowchart •Space Generator
Check Loop Data Flow.
Check Loop.

B-1 Current and Data Controls
B-2 Core Array Circuits

B-2
B-4

C-1 Disconnect Logic.
C-2 Error Print Logic

C-2
C-3

D-1
D-2
D-3
D-4
D-5
D-6
D-7
D-8

D-1
D-2
D-3
D-4
D-5
D-6
D-7
D-8

Schematic of Document Guide Mechanism
Document Insertion Guide Closed
Document Insertion Guide Open.
Cross-Section of Split Platen
Schematic Feedroll Lowering Mechanism.
Feedroll Cam and Clutch
Feedroll Cam Magnet and Feedroll Latch •Feedroll Latch Magnet.

TABLES
Table
F-1 Receive Operation--Without Record Checking
Feature •F-2 Receive Operation--With Record Checking Feature
F-3 Transmit Operation--Buffer to Communications LineF-4 Enter Status--Local or Communicate Mode
F-5 Buffer Printout--Local Mode

Table

F-1
F-2
F-3
F-3
F-3

F-6 Status/ Answerback when Terminal with Receive Status
is Addressed by CPU
F-7 Status/ Answerback when Terminal without Receive Status
is Addressed by CPU
F-8 Terminal Addressed by CPU.

Page

F-4
F-4
F-5

v

ABBREVIATIONS

A dr.
Ans.
Attn.
Auto
BAT
BCD
Bfr.
Bksp.'CACAS
CASS
Central
Ck.
COMM
CR
CR
CS
CSS
Ctr. , Cntr.
Ctrl.
Cur.
EOB
EOS
EOT
Err.
Fwd
H
HD
HICG
HISG
H-reg.
I
IE
IIC
Interm.
I/O
IPM
11
12
LC
LF
LOC
LRC

Address
AnswerAttention
Automatic
Buffer Address Time
Binary Coded Decimal
BufferBackspace
Control Address ModeControl Address Selected ModeControl Address Selected Slave ModeCentral Computer or Remote Multiplexer
Check
Communicate
Carrier- RetumControl Receive ModeControl Selected ModeControl Selected Slave Mode
Counter
Control
Current
End-of-Block
End-of-StateEnd of Transmission
Error
Forward
Horizontal
Half Duplex
Horizontal Current Control Gate
Horizontal Current Source Gate
Horizontal Register'Integrator
Inhibit Interrupt
Image Index Counter
Intermediate
Input/ Output
Intermediate Polling Mode
IIC Position One
IIC Position Two
LowercaseLine Feed
Local
Longitudinal Redundancy Check

Modem
MPLX
MS
Neg
0
o 'flowPar. , Pty.
PPI
Pro
PRE
RCAB
RCS
Rec.
Reg.
Res.
Rev.
RT
RTS
SC
SD
SDI
SDO
SLT
SP
S-Register
ST
Tab
TC
TOM
TNS
TPAB
Trans.
TSAB
TT
UC
V
VICG
VISG
VRC
V-reg.
IB-Register
1 CH
2B- Register

Modulator- Demodulator
Multiplexer
Millisecond
Negative
OperateOverflow
ParityProbe Position Indicator
Print
Prefix
Receive Check Answerback Mode
Receive Check Slave Mode
Receive
Register
Reset
ReverseReceive Text Mode
Receive Text Slave Mode
Station Control
SerdesSerial Data In
Serial Data Out
Solid Logic Technology
Stop Bit
Shift Register
Start Bit
Tabulator
Transmit Control
Typamatic
Text Non-Selected Mode
Transmit Poll Answerback Mode
Transmit
Transmit
Transmit Text
UppercaseVerticalVertical Current Control Gate
Vertical Current Source Gate
Vertical Redundancy Check
Vertical Register
First Buffer Register
One Cycle Halt
Second Buffer Register

CHAJ?TER 1. INTRODUCTION

2740 COMMUNICATION TERMINAL, MODEL 1• Communicates with other terminals or acomputer.
• Retains all Selectric® typewriter functions.
• Can be used off-line as a Selectric typewriter.
• Can be connected point-to~point or multipoint.
• Requires a line adapter (common-carrier data
set or mM modem).

The IBM 2740 Communication Terminal, Model 1(Figure 1-1) is a device that enables data to beexchanged almost instantly between points far
removed from each other. An operator can send
(transmit) or receive information in typewritten
form as it is needed. The exchange of information
can be with another terminal or via a multiplexer,
with a computer. When connected to a computer,the terminal can enter information into the computer,request information from the computer (remoteinquiry), or have problems that occur in one areasolved by a computer that is located in anotherarea.

Figure 1-1 Communication Terminal (2740-1)

2740/41 FETOM(4/68)

1-1

The 2740 is designed for simplicity of operation.
All controls are located on the Selectric keyboard(Figure 1-2). Standard Selectric keys perform thesame operations for the terminal as for a standard
Selectric typewriter (except repetitive functions).
In addition to the standard Selectric keys, the2740-1 terminal has a group of keys to the left ofthe keyboard and a group of keys and lights to theright of the keyboard. (Note that not all of the keys
to the left of the terminal keyboard are presently
used.) The added keys allow the 2740 to performthe additional operations required for communications. The lights show the status of the 2740 whenin comm unicate mode. When the terminal is notneeded for c@mmunications, a Local/Communicate
switch allows the Selectric typewriter to be used
off-line . Complete operating instructions for theterminal are in the Operators Guide, Form
A27-3001, and are not covered in this manual.
Terminals can be connected to a communication
system in one of two configurations: point-to-point
or multipoint. Point-to-point configuration is theconnection of a terminal to another terminal or toa multiplexer by a single communication line
(Figure 1-3). Multipoint configuration is theconnection of more than two terminals on a single
communication line (Figure 1-3). If multipoint configuration is used without the station-control special
feature, 'alJ terminals on the line receive the message from any terminal in use. Only one terminal
can send at a time.
The 2740 terminal uses solid logic technology(SLT), permitting the terminal logic to be containedin one compact enclosure.
Information can be exchanged over short distances (room-to-room, building-to-building) or overlong distances (state-to- state, coast-to-coast).
Terminals cannot be directly connected to eachother. To connect a terminal to another terminalor multiplexer, a line adapter is needed. The line
adapter can be either a common-carrier data set oran IBM modem (modulator-demodulator). The 2740
can communicate over privately owned or commoncarrier lines. When privately owned lines are used,
an IBM modem connects the terminal to the line.
When common-carrier lines are used, either an
IBM modem or a common-carrier data set can beused. The Western Electric 103A and 103F data
sets serve as examples.

II~
Figure 1-2 Keyboard(2740-1)
1-2(4/6 8)

2740

2740
Point- To-Point

2740

2740

©

©

2740

2740

completed, the operator presses the EOT key at thesending terminal. This causes acharacter tobe generated and sent, and returns the sending terminal to control-receive mode. The
characteris received at the receiving terminal and returns
the terminal to control-receive mode. Either term inal can now "bid" for the line and start sending
information.

2740

SPECIAL FEATURES (2740-1)

~

--(

{

T1

TT

Many special features are available for the 2740.
These allow the 2740 to be used with a dial-telephonesystem, or allow more than one 2740 to be used on asingle communication line. With the recordchecking feature, the 2740 can check and verify all
incoming data.

Multiplexer

Record -Checking

1• VRC checks each character.
To Compu ter• LRC checks blocks of data.

Multipoint
Figure 1-3 2740 Terminal Configurations• Data is checked in the receiving terminals.

MODES OF OP ERATIONLocal
In local mode the I/O printer can be used as a
Selectric typewriter.
Communicate
When a terminal is turned on (power up), the terminal goes into control-receive mode. Controlrecei ve mode enables the terminal to accept andact on control characters. The control charactersfor basic-machine operation (no special features)are the bid character @ and end-of-transmission(EOT) character @. The @ character places thesending terminal into transmit mode and the receiving terminal into receive mode. The
characterreturns both terminals to control-receive mode.
When an operator sends a message, he presses
the Bid key on the terminal keyboard. This causes
the terminal logic to go into transmit mode and to
generate and send the @ character. The @ character is received at the other terminal, which thengoes into receive mode. The operator at the sending
terminal keys in the message exactly as he would ona standard typewriter. When the message is©

With this feature, the 2740 checks all data it
receives for validity. (This feature is not available
for the 2741.) Data is checked in two ways: vertical
redundancy check (VRC) and longitudinal redundancy
check (LRC). VRC checks each character for oddbit parity; LRC checks the entire message to insurethat all characters are sent and received. In LRC
checking, a special check character is generated byboth the sending and receiving 2740's.
During the sending operation, the operator periodically presses the EOB key on the sending 2740.
This causes the generated LRC check characterto be sent over the line to the receiving 2740. The
receiving 2740 then compares the check character
it receives with the one it has generated. If anerror is detected, the Restart light turns on, indicating to the operator than an error has occurred.
When a VRC-error occurs, a dash is printed inplace of the error character and the message continues. When an LRC-error is detected, a dash isprinted, the Restart light comes on, and the terminal keyboard locks until the Restart key ispressed.
Automatic EOB• Checks data each time the Carrier-Return key ispressed.

2740/41 FETOM(4/68)

1-3

The automatic EOB feature causes data to be checked
every time the Carrier-Return key is pressed on thesending 2740. Thus, each print line is checked and,in the event of an error, can be resent as soon as
the error is detected.
Dial-Up• Connects a 2740 to another 2740 or to a computerby using a dial-telephone data set.
The dial-up feature allows the 2740 to communicate,
via the common-carrier dial detwork, with another2740 or with a computer. The entire telephonecommon-carrier system is available for use by theterminals. This feature reduces common-carrier
communication costs to a minimum; a charge ismade for the line only during the time the terminalis actually connected to the line. This feature isused with the Western Electric 103A dial data set or
equivalent. The operator dials a telephone number
to connect the terminal to another terminal equippedwith the same feature.
Transmit Control• Allows the computer to control the sending or
receiving status of the terminal.
The dial-up feature is a prerequisite for this feature.
the transmit-control feature allows the computer tocontrol the sending or receiving status of a remoteterminal. Thus, the 2740 with this feature is undercomplete control of the computer. (This feature is
not needed for the 2741. )Station Control• Allows more than one 2740 to be on the samecommunication line without contention.
• A single 2740, a group of 2740's or all 2740's on
the line can be addressed to receive data.

1-4(9/69)• Each 2740 on the line is separately polled tosend data.
--The station-control feature allows more than one
2740 to be connected to a single communication line
without contention (more than one terminal attempting
to transmit at the same time). (This feature is notavailable for the 2741.) The communication line canbe either a private in-house line or a leased commoncarrier line. A special system of addressing andpolling allows a computer to control the send or
receive status of each terminal on the communication line.
Addressing is an operation by which the computer
calls a terminal to send data to it. Each 2740, a
pre-determined group of 2740' s, or every 2740 on
the line can be addressed to receive the message
through the use of special addressing codes.
Polling is an operation by which a particular
2740 is notified that it alone can send data. If thepolled 2740 is not ready to send data after a given
length of time, another 2740 on the same line ispolled.
Both the polling and addressing operations use
a special sequence of control characters to allow
operation to begin. These control characters are
explained in Chapter 4.

2760 Attachment• Allows the attachment of one IBM 2760 Optical
Image Unit to a 2740, Modell
The record-checking feature is a prerequisite fv
this feature. Neither the station control nor thetransmit control feature can be installed on the2740-1, and the 2740-1 must have serial number
15000 or higher. The attachment feature allows
one IBM 2760 Optical Image Unit to be attached to
the 2740-1. The 2760 utilizes the control circuitryof the 2740-1 to transmit data to, and receive datafrom, a muiiiplexer. When the 2760 is attached,
the 2740-1 is always in terminal-to-multiplexer
mode of operation.

IBM 2741 COMMUNICATION TERMINAL• The 2741 communicates only with a computer.
• The 2741 operations are controlled by computer
programming.
The 2741 can communicate only point-to-point witha computer (Figure 1-4). The sending or receiving
status of the 2741 is controlled by computer programming. The primary use of the 2741 is in the
IBM Administrative Terminal System (ATS).
The 2741 uses rr ost of the same sending andrecei ving circuits as the 2740 and communicates bymeans of a data set or modem. The main physicaldifference between the 2741 and the 2740 is the
Selectric keyboard. On the 2741, no keys or lights
are added to the standard Selectric keyboard, but
the Index key is replaced with the Attention key(Figure 1-5). Another difference is that all special
features available for the 2740 are not available forthe 2741. The standard 2741 uses a different typing
element from the 2740, require the use of a different character code for the print characters, calleda correspondence code.

2740/41 FETOM(9/69)

1-4A

Receive Interrupt
The Receive Interrupt feature allows the 2741 operator to interrupt the reception of a message fromthe computer so that he can send instructions.
Transmit Interrupt
The Transmit Interrupt feature allows the computer
to interrupt the transmission of text from the 2741.
Multiplexer

Typamatic
The Typamatic feature permits the operator to automatically repeat the space, backspace, and underscore/hyphen operations by pressing this key.

To ComputerFig ure 1-4

Term inal Config uratio ns (2741)

SPECIAL FEATURES (2741)

Print Inhibit CPU Control

Dial Up

The Print Inhibit CPU Control feature enables the
CPU to inhibit the 2741 from printing transmitted
or received data.

The Dial- Up feature for the 2741 performs the samefunctions as for the 2740.

~

~

2741

Com~Unication&

Terminal~.....Ja........JFig ure 1-5 Keyboard (274 1)
2740 / 41 FETOM(6 / 70)1-5

IBM 2740 COMMUNICATIONS TERMINAL MODEL 2• Faster transmission speed.
• Visual verification before transmission.

Model 2 can accommodate up to 120 characters (248
and 440 positions are available as special features),and is capable of reading out without destroying its
contents.

• Clean copy output.
• Ease in correction of keying errors.
• Automatic retransmission, if Record Checking
feature is installed• Flexibility in selection of communications facilities.
The IBM 2740 Communications T erminal Model 2 isa buffered version of the 2740 ModelL Model 2 .
(Figure 1-6) enables key input from the typewriter
keyboard (Figure 1-7) to be printed, stored in abuffer, visually verified, and subsequently transmitted to a central system. The basic buffer in the

Figure 1-6 Communication Terminal (2740-2)
1-6(4/68)The 2740 terminal (without special features) transmits over leased common-carrier or privately owned
communications facilities at the rate of 14.8 charac:';'ters per second (134.5 bits per second). Station
control is a standard function in the basic 2740 terminal. The line-control characters used bytne
Modell remain unchanged for the Model 2.
Model 2 is designed to be used in a wide variety
of applications, such as: payment entry, journal
entry, inquiries, administrative messages, file
updating, and renewals. The terminal can also be
used off-line for normal typewriter applications.

---------------- .,.,-- .
, _

---

-----------

I------.-~-

Figure 1-7 Keyboard (2740-2)

The operation of the Model 2 is basically the sameas the Model 1, with the following changes (see Figure

MODES OF OPERATION

1-8) :The IBM 2740 Model 2 can operate in either local orcommunicate mode.

• Addition of Enter key (in location formerly occupied by Dial Disc key).
• Addition of Attention light• Addition of Enter light (in location formerly occupied by Dial Connect light)

In local mode, the terminal will be in one of threestatus conditions:Enter. Keyboard-entered data will be loaded into thebuffer.

• Elimination of EOB key• Elimination of EOT key• Elimination of Dial Disc key and Dial Connect
light in the Model 2

Buffer Print. The contents of the buffer will printout with each operation of the Bid key.
Typewriter. The terminal may be used for normal
office typing without entering or affecting the buffer(Enter key not operated prior to typing).

• RST (Restart) key renamed Reset key
Communicate• RST (Restart) light renamed Reset light• Additional functions of Bid key

When operating in communicate mode, the terminal
will be in one of five status conditions:
2740/41 FETOM(4/68)

1-7

Figure 1-8

Operator Controls

Standby; Terminal may be conditioned to enter, sendor receive data; however, the keyboard is locked until
an operation is initiated.
Enter. Terminal loads operator-initiated informationfrom the keyboard into the buffer.
Bid. Operator has pressed the Bid key and terminal
is waiting to be polled in order to transmit thedata residing in the buffer.
Transmit. Terminal transmits the data from thebuffer to the communications line, after being successfully polled.
Receive. After being successfully addressed, theterminal receives data from the communications
line and prints the received data.

SPECIAL FEATURES (2740-2)
Buffer Expansion
The buffer capacity can be increased from 120 to
248 or 440 characters.
Buffered Receive
This feature permits the 2740-2 terminal to receive
data into the buffer from the communications line.
A printout of the buffer takes place after the message
is received and stored, thereby reducing the time
1-8

(4/6 8)that the transmission line is in use. The Receive
light is on and the keyboard is locked during thebuffered-receive and printout operation. The ter minal switches from a receive status to a standby
status after the buffer printout has been completed.
Idle characters are not required after function codes(CR, Tab, and Index), as the Buffered Receivefeature will stop for the function to be completed
before continuing the printout. This reduces thenumber of characters to be transmitted . The lengthof transmission cannot exceed the capacity of thebuffer (120, 248, or 440 positions). If a buffer
overflow occurs, the Reset light turns on. The
buffer receive feature must be installed with any
high speed line adapter or data set.
Telegraph Line Adapter
This feature provides an adapter that enables the2740-2 to be used with a 75-bps leased private-line
telegraph service. With this feature, the terminal
can operate over leased common-carrier or equivalent privately owned 75-bps telegraph channels .
When using this feature, the transmission rate is
8.33 characters per second (cps).
Speed Base--600 bps
This feature provides for operating over leased
common-carrier private-line telephone serive or
equivalent privately owned facilities at 600 bps(66.7 cps). The Buffered Receive feature is a prerequisite.

Header Control
This feature allocates up to 28 positions of the buffer
for storing repetitive header information. Startingwith position 1, increments of four positions (up to
28 maximum) arfl asshmed during installation. A
Header switch controls operation. With the Header
switch in the OFF position, data typed at the keyboard can be entered into the header area of thebuffer (Enter key operated). This data is available
every time the buffer reads out to the line. Changes
in data in the header area of the buffer must be madeby retyping the entire area. Once header data has
been entered, turning the Header switch to the ON
position allows subsequent data entered to automatically start at the end of the header area of thebuffer. Transmission will be from the beginning of
the header area to the end of information stored in
the buffer. All positions of the header area must be
filled with characters and/or spaces. If the terminal
power is turned off, the buffer information will be
lost. Data keyed into the buffer (including the headerarea) can be printed out for verification by entering
the data while in local-enter mode (with Header
switch in OFF position) and pressing the Bid key
after all data has been entered. If the Buffered
Receive feature is installed, the positions used forheader control are not available to receive data fromthe line when the Header switch is set to the ON
position.
Edit
The Edit feature, which simplifies the correction oftyping errors entered into the buffer, is controlled
by the following keys:
Enter Key. Pressing this key while in the entermode causes the buffer address to be reset to thefirst position and the terminal to remain in enter
mode.
Line Type Key. The Line Type key is operative
only in enter-local or enter-communicate mode.
Operating this key immediately after the buffer isrestored to position 1 by the Enter key causes thebuffer to print out to and perform the next carrier
return stored in the buffer. The Line Type key
becomes inoperative after typing a character orreaching the character where the Enter key was
operated.
Line Return Key. This key is operati ve only when
the terminal is in the enter-local or enter-communicate mode. Pressing the Line Return key immediately following the use of the Line Type key or a

keyboard operation causes the buffer to back up anderase all characters up to and including, the firstcharacter of the present line.
Edit Operation
If an error occurs in the present line of typing, thecorrection procedure is as follows:
1. Press CR/LF key (moves print element to left

margin and next line).
2. Press Line Return key to back up the buffer tothe beginning of the line.
3. Rekey the entire line.
If the error is not in the present line of typing,
the correction procedure is as follows:

1. Press CR/LF key (moves print element to left
margin and next line).
2. Press Enter key (restores buffer to position 1).
This is the second operation of the Enter key
since this key was operated to put the terminal
into enter mode before typing was started.
3. Press Line Type key. Advance the buffer line
by line until the end of the line to be corrected
is reached.
4. Press Line Return key.
5. Retype the line in error and all succeeding linesof the message.
The stored information can be verified by switching to local mode and pressing the Bid key or byrepeating the Line Type operation. This causes thecontents of the buffer to be printed. If the message
is correct, switch to communicate mode and press
the Bid key. Transmission occurs when the terminal is polled.
Document Insertion
The Document Insertion feature provides a meansof inserting ledger cards in front of the typewriter
platen without using the platen knobs.
Operation
To insert ledger card, push down on the Releasebutton (Figure 1-9, Part A) and simultaneously
pull the post toward the front of the terminal(Part B). When the card guide is tilted forward,
the feed rolls are opened and the card can beinserted (Part C).
After the card is inserted, the guide can be movea
toward the rear of the machine. The card can still
be moved at this time, and can now be positioned for
2740/41 FETOM(4/68)

1-9

printing using the Line-Position indicator located on
the plastic guide (Part D). The guide is locked inposition by again pushing down on the Release button.
The feed roll mechanism closes the feed rolls andthe card is held securely in place, ready to receive
the printed data. An interlock locks the keyboard
when the guide is not in home position.
Split Platen
A Split Platen is available to further enhance theforms-handling capability of the IBM 2740-2 terminal (provided the Document Insertion feature is
installed). The two sections of the platen may be
manually disengaged by pulling the left platen knob.
The sections will remain disengaged until the left
platen knob is manually pushed in. When the platenis split (disengaged), only the right-hand portion
will be indexed by the Index key , the CPU, or theplaten knobs. When the platen is not split (engaged),both sections are indexed in the normal manner.
The platen is split so that 5 1/ 2 inches of the printing line is available on the left-hand portion. The
print position that would print directly on the split
in the platen should not be used since it may not belegible.
The Platen Split indicator light, located to the leftof the keyboard, is on whenever the platen is in a
split condition. The keyboard locks while the platenis split, and unlocks when the platen is restored tonormal (engaged).
Record Checking
The Record Checking feature for the 2740-2 is thesame as for the 2740-1.

DATA REPRESENTATION• Data is represented in the 2740-1 and 2740-2 by
by BCD code .
• Data is represented in the 2741 by correspondence code.
Figure 1-9 Document Insertion Feature• The check bit maintains odd parity for checking.
The 2740-1 and 2 use Binary Coded Decimal (BCD)
system (Figure 1-10). Which consists of six information bits and a check bit arranged as follows:B

1-10(4/68)

A

8

4

2

1

C

Uppercase

Lowercase

.

Till

T1

T2

T3

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Magnets Picked-----..
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Orderof Rotation
3 4 5 6
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842 1
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INDEX
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@

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c~

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IND~ cy~

TAB

LC
BKS~ SHIFT
IDLE

TAB

®

LC
UC
SHIFT EOB·..... BKS~ SHIFT@)EOT:IIIIIII

IDLE.... Parity Bit
Figure 1-10 2740-1/2740-2 Printer Code Conversion

The six information bits (B, A, 8, 4, 2, 1)
identify all alpha-numeric characters for the
Selectric I/O as well as all control codes needed tomaintain semi-automatic operation during communication. The check bit maintains odd parity. A
valid character contains an odd number of bits; any
character code that is not odd is given a check bit.
A 2740 character, generated by the transmit contacts in the I/O device, is translated into BCD before
leaving the I/O device. This is accomplished in a
diode matrix in the I/O device. The BCD code, as
received from the line, is used throughout the 2740
and is decoded into the proper tilt and rotate, orfunction code, necessary to operate the I/O device.
Upon special request, the 2740 (Models 1 and 2)
can be equipped for correspondence code (Figure1-11).
The 2741 uses correspondence code. The 2741
sends and receives characters in the same bit orderas the 2740. However, the bit configurations for thesame characters are different. For example, theletter "A" in the 2740 is a BAl; in the 2741 the bit
configuration for the letter "A" is a B421. Upon
special request, the 2741 can be equipped for BCD
code.
Mechanical changes to the I/o device are required
to change from BCD code to correspondence code,'lnd vice versa. No circuit changes are required.
Character Format• The start of a 2740/2741 character is identified
with a start (ST) bit and the end with a stop (SP)bit.
• The start hit is always a O-bit (no-bit).
• The stop bit is always a I-bit (bit).
A BCD character consists of seven data bits. In
order to use this character as the input or
output of the terminal, it is necessary to
add two bit positions to the character2740/41 FETOM(4/68)

1-11

Uppercase

Lowercase
T2

TI

Head CodeMagnets Picked ------. T2 Tl T2 Tl T2 Tl T2 Tl
Line Code Bit
1 1
1 0
0 1 0 0Order~
- 1 2 1 2 1 2 1 2

t==:::'

Incrementsof Rotation

345
842

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Magnets
Picked '-.

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--

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May be received only.

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Figure 1-11 2741 Printer Code Conversion (Correspondence)the start bit (ST) and stop bit (SP). The start bit
will always be a space (no .... bit) and the stop bit will
always be a mark (bit).
The start bit is added to the character so thatthe terminal can recognize the start of a new
character. The stop bit separates characters.

ST

B

A

8

4

2 11

I C SP

DATA FLOW (2740-1/2741)• Transmit data flow is from the I/O device to the
1B-register, to the S-register, and then to theline.
• Receive data flow is from the line to the S-register, to the 1B-register, to the 2B-register, andthen to the I/o device.
1-12(4/68)• The 2B-register is not used for sending operations.
• Control characters are identified at the 1Bregister.
Data flow through the 2740-1/2741 is shown in
Figure 1-12. With the terminal in transmit mode,a data character is generated from the keyboard of
the I/o device and loaded into the 1B-register.
From the 1B-register, the character transfers to
the S-register where, under control of the serdes
clock, the parallel character is serialized (changed
from parallel to serial form) out to the communication line. The serialized character goes throughthe data-set adapter within the terminal, to either acommon-carrier data set or a built-in IBM modem
and then to the line.
With the terminal in receive mode, a characteris received in serial form from the line by the data

Line

Data
Set orModem

Serial Data Out

~

I
Data
Set
Aclpt

S-Reg

I

SerialData
Inr
SerdesClock

1
2B-Reg

1 B-Regt

I/O
Decode8. Mag.. Drivers

I/O
Device1
T
Control
Clock

Figure 1-12 2740-1/2741 Data Flow

set or modem. The character passes through thedata-set adapter and is serially loaded into the Sregister under control of the serdes clock. Whenthe character has been completely deserialized(changed from serial to parallel form) by the Sregister, the control clock gates the character into
the 1B-register and then into the 2B-register.
'While in the 1B-register, the character is examined
to see whether it is a control character. If it is,the character does not transfer to the 2B-register,
but performs the necessary control operation.
Once the character reaches the 2B-register, it
is examined to determine whether it is a print orfunction character. If it is a print character, thecharacter is gated to the print-decode circuit andthen to the I/o device to be printed. If the character is a function character, the character is gatedinto the function-decode circuit and from there into
the I/o device to perform the function. The 2Bregister is llsed only for receiving operations.
In summary, the received serial character isdeserialized by the S-register, under control of theserdes clock. Then, under control of the control
clock, the character transfers from the S-registerto the 1B-register and then from the 1B-register tothe 2B-register, and on to the I/o device. Withthe terminal in transmit mode, the parallel character is loaded directly into the 1B-register, transferred to the S-register, serialized, and sent out
on the line.
DATA FLOW (2740-2)
The 2740-2 Communication terminal is basically a2740 with buffer storage.
All functional units contained in the 2740-1 areused in the 2740-2 terminal, but because of theaddition of buffer storage, the data flow is different.
The following explanation describes the basic data
flow for each operation.
Enter (Figure 1-13)
Pressing the Enter key places the terminal in theenter mode and allows the operator to key in an input message. The buffer is restored to the firstcharacter position, the typewriter motor turns on,
and the keyboard unlocks and shifts to lower case.
2740/41 FETOM(4/68)

1-13

As the operator enters the message, the I/O prints
each character. The individual characters aretransferred to the 2B-register and then bit-by-bit
to the control unit buffer~ Figure 1-13 shows theenter data flow.
Each time the operator presses a key on the I/oprinter, the contacts transfer the bit configuration of
the character representing the key pressed. Thisbit configuration (character) is transferred to the
2B-register. From the 2B-register, the characteris "scanned" bit-by-bit into buffer storage. Buffer
storage then advances to accept the next character.
This process continues until the entire message isentered into buffer storage. Typewriter functions(tab, carrier return, upper or lower case shift,index) are entered into buffer storage as characters.
The backspace function is not entered into storageas a character, but instead, causes buffer to backup one position. This allows correction of a typing
error immediately after it occurs.
As each character is entered into buffer storage,
a parity check is made to ensure that an odd numberof bits is present for the character. An out-ofparity character causes a data check condition (thekeyboard locks and the reset light turns on).
Enter Timeout
The 15-second time-out circuit is active during enter
operation if the terminal is in communicate mode andthe circuit is enabled. The circuit is enabled by the
first transmit answerback after the terminal is turned
on. The purpose of the enter time-out is to assurethat the terminal will be available to receive messages if the operator inadvertently leaves the terminal in enter mode or if there is too great a time lapse(15 seconds) between two consecutive operator actions
during communicate-enter operations.
When the time-out occurs, a reset line is brought
up to reset the buffer, reset the rekey latch (if set),turn off the Reset light (if on), and return the terminal to not enter status. The same time delay andtime-out circuitry is also used for power-on garble
or terminal "hang up" conditions.

character. and the terminal "bids" for the line. Whenthe terminal is polled, it switches to transmit mode,
sends a @ as a reply to the poll, returns the buffer
to the first position, and begins transmitting the contents of the buffer (Figure 1-14).
Each chara~r from buffer storage is "scanned"
into the IB-register. From the IB-register, thecharacter is transferred to the S register and shifted
serially by bit to the communication line exactly asin the 2740-1 terminal.
Receive (Figure 1-15)
The 2740-2 Communication Terminal, without the
Buffered Receive special feature, receives andprints an incoming message from the central processor like the 2740-1 terminal. The data, received
serially by bit from the communications line, isshifted into the S-register (shift register). From
the S-register the character transfers to the IB
register, then to the 2B-register and finally is
decoded and sent to the I/o printer.
Buffer Print (Figure 1-16)
When the Local/Communication switch is at Local
the terminal can print out the contents of buffer
storage. If the data was entered while in communicate mode and the terminal is then switched toLocal, pressing the Bid key causes the message toprint out. Data can also be entered while the terminal is in Local. The procedure is the same as
when in communicate: the Enter ke~y is pressed, themessage is typed, and the Bid key is pressed.
Instead of being transmitted, however, the message
is printed out. When the complete message has been
printed out, the terminal returns to enter mode andmore data can be typed. The terminal is taken outof enter when the Reset key is pressed.
The characters are taken, one at a time, from
buffer storage and loaded into the 2B-register.
Once in the 2B-register, the characters are decodedand printed the same as for a receive operation.
BUFFER STORAGE

Transmit (Figure 1-14)
When the input message is complete, the operator
presses the Bid key to request that the stored information be transmitted to the central processor. If
the terminal is in upper case when the Bid key ispressed, the character code for lower case isentered into the next position of buffer and the keyboard shifts to lower case.
The terminal enters awith Record Checking) into the buffer position after the last message

© (®

1-14

(1/69)The 2740-2 does not immediately transmit information entered from the I/O keyboard but stores the
input, character-by-character, in buffer storage.
The term "buffer" describes the ability to store
characters at high or low speed and later read out
these characters at a uniform rate. The character
rate from the I/o printer is not uniform, and is not
the same as the character rate of the communication
line. Storing data characters in the buffer allows
the buffer to read out and transmit these characters

:I_~_:_gi_s_te_r---l......- - -....·-tIL..-_~_~o_f~_e_~e_-I

11/ 0 printer I"""- - -.......

Figure 1-13 Enter Data Flow

Transmission
Lines

Figure 1-14 Transmit Data Flow (2740-2)

Transmission
Lines

Line
Adapter

5
Register

18
Register

28
Register

Print andFunction
DecodeI/O printerFigure 1-15 Receive Data Flow (2740-2)

BufferStorage

28
Register

Print andFunction
DecodeI/O printerFigure 1-16 Buffer Print Data Flow (2740-2)

2740/41 FETOM(4/68)

1-15

(c) One backspace operation effectively erases a
stored function code (shift, tab, CR, or
index). Instead of backspacing when an
entry error involves a function, start over.
Press the Reset key and then the Enter key
to start over.

at a constant rate--the speed of the communication
line. Thus, input can be at the operator's speed(which varies), and not interfere with efficient useof the communication line.
Storage Operation

3. Press the Bid key. If the I/O is in upper
case, it automatically downshifts and the LC
shift code stores. The stop code(@with Record Check) stores automatically.

Buffer storage receives input from the 2B-registerand delivers output to the IB-register or the 2B-register (Figure 1-16). There are three operator controls over buffer storage (Figure 1-8): Enter (whichcauses storing), Reset (which cancels Enter andeffectively clears buffer storage), and Bid (whichcauses readout to the communication line or to theI/o printer). The sequence for sending a message is:©

(a) When in communicate the 2740-2 waits fora poll and sends the message (Figure 1-17).
(b) When in local, the I/O prints out the stored
information and stops where the stop codecharacter is (or
stored (Figure1-17). The Enter light comes on again.
The operator has three choices:©

1. Press the Enter key until the Enter light comeson. If the I/o printer is in upper case, it automatically downshifts.
2. Type message information on the I/O printerkeyboard. Each character is entered into
buffer storage as it is typed (Figure 1-17).

(1) Continue entering from the I/O keyboard.
(A downshift will be the last stored
character if the last printed character
was in upper case. )(2) Clear buffer storage and start over.
(3) Send the message by going to communicate and pressing the Bid key.

(a) In case of a typing error, backspace andretype the incorrect character. The backspace code is not stored.
(b) If an I/O printer function is erroneously
keyed, backspacing effectively erases thefunction character in buffer storage but does
not place the carrier or paper in the correct
position to continue typing (Figure 1-18).

2B
I/O Printer®)Character Storage Concepts
The optional capacities of buffer storage are 128,
256, or 448 characters; however, because the I/o

2B
1- ~

Register

Registerf-

I/O PrinterI

I

L ____ -,Enter (Local or Comm)----Send (Comm)

I

I

1

I

Buffer Pri nt (Loco I)

BufferStorage

1B

S

Register

RegisterFigure 1-17 Overall Flow of Outgoing Message (2740-2)
1-16(1/69)

Communications
Adapter

Communications
In terfaceLinekeyboard locks 8 characters from the end of memory
during an enter operation, the usable capacity is120, 248, or 440 characters. Consider buffer storage as an assembly of locations where information
can be placed. Each of the locations has a specificdesignation called its address (Figure 1-18).
Storing and retrieving is done sequentially.
It can be seen that buffer storage requires thefollowing to do its job:

3. A way to put a character in or take it from alocation (store or read-out).
4. A method of clocking so that information is always stored on time when entering, or madea vailable on time when sending (memory clock).
In the 2740-2, magnetic core storage provides
all these capabilities (Figure 1-19).
Each 2740-2 buffer character is made up of
7 -bits. Each bit requires one magnetic core, so
there are 128x7=896, 256x7=1792, or 448x7=3136

1. Locations for storing characters (cores).
2. Identification of character locations (address).

,,

MarginTab Stop

III I III IIIIII1 III I1IIII I IIIII I I II IIEnter and carrier _ _ R.
return, then typeU.

Jon e s984 03 OY __ Printout or send

Note: Press Bid Key after "Y" is Keyed.

Chara cter a ddress,.......:l--r-!:...-r-..:::....~.:....,.....::...-r-..:::......,...:~.....::...-r-....:.......--.:..::..-.,..:~r=.......:..:::.......:...:...,-:.::.,......:..::.,-....:..;...-y-.:...::....,.:-.:,.....:::..:~-=....:...,-:=-r~r-,___-,Stored in buffer
storage

Note: Backspace backs the carrier one space and backs buffer storage one character location.

Figure 1-18 Comparison of Typed and Stored Message

2740/41 FETOM(4/68)

1-17

Horizontal
Addressing
Circuits

MemoryClockMemory Go

...

II)

Backspace

E

';

Step

Reve~e~Magnetic
Core Array

D

1

O'l

c:

.~

~

"'0

~

r---L---~------~

"0

Clear

u

Buffer Storage
Address Counter

Enter

00-

Q;

>

(448 - character \\!naximum capaci~

f:l~-------------'~~i------~

From 2B Register---------------------------1

Data Circuits

A

Not EnterTo 18 Register (Send)

I

To 28 Register (Print)

Figure 1-19 Buffer Storage

Buffered Receive (Comm)

-

Line

Communication
InterfaceCommun i cati on
Adapter""-

S
Register-

18
Register-

28
Register

Buffer Print(Comm)

28- .I r· Re gister.I LII ____
,
I I
,,
I
I

I

I

I

8ufferStorage

Figure 1-20 Overall Flow of Buffered Receive Incoming Message

1-18(4/68)

I~ .J

cores in the core array. The methods of enteringcharacters into the cores or retrieving charactersfrom the cores are described in the "Buffer Storage"
section of "Chapter 2, Functional Units. "Buffered Receive Feature
During receive the received characters are enteredinto buffer storage from the 2B register and printing
is inhibited (Figure 1-20). As soon as the message

is complete, the contents of b~ffer storage are readout and the I/O prints the message. Buffer storage
can operate much faster than the electro-mechanicalI/o printer, so a faster line rate can be used withbuffer storage on-line than with the printer on-line.
With a Buffered Receive terminal, (Figures 1-17
and 1-20). there are four basic data flow routes atthree character rates, as shown in the following
table:

Operation

Data Flow

Rate

Enter

I/0~2B~Buffer storage

Typing--variablE; and slow

Transmit

Buffer storage--.1B--.S--...line

Receive

Line~S~ 1B--...2B--..Buffer storage

Buffer Print

Buffer storage~2B--....I/0

TRANSMIT STATUS/ANSWERBACK (2740-2)• Two character answerback to addressing sequence
sent by 2740-2 (sense character andor QJ).

®

• Four error conditions stored by the terminal forthe qualified
answerback (Figure 1-21).

®

• Program has the option to have messages retransmitted when errors exist.
• Three status and three operational error conditions transmitted as a qualified(Figure 1-21).

®

When addressed by the CPU, the 2740-2 respondswith a two-character answerback. The first character is a "sense character" for a specific definitionof the terminal status or error condition. The second character is a
if there is receive status or aif there is not receive status.
Four types of failures are detected and stored by
the 2740-2. Once the terminal (with receive status)
is readressed, it responds with the two-character(qualified QJ) answerback. The answerback is forthe highest priority error type detected, followed bythe (f). The sense character response to the CPU
does not cause automatic retransmission, but it isintended for error condition statistics. For example,

®

®

1

Communication line--relatively fast

I/O printer--maximum printing speed

if a message received by the 2740-2 (without Record
Checking) has an error, the CPU is not informed
until the terminal is addressed again. Then, at theoption of the program, the message can be retransmitted to correct the previous error condition. The
CPU program has the same option when the text received by the CPU contains an error.
Four latches are used to store the four types oferror conditions, each assigned a priority. In priority order, with highest first, the four conditionsare:
1. Electronic hardware (buffer) error in the last

message received;
2. I/O printer error in the last message received;
3. Line VRC error during the last message received;
4. A terminal-induced VRC error during the last
message transmitted.
If an error condition latch has been set, it generatesGO)

the sense character when a positive (qualified
answerback is transmitted. When multiple errors
occur, the character transmitted defines only thecondition which has the highest assigned priority.
For a "no error" condition, a space is transmitted
as the sense character.
The error condition latches are reset when thesense character of a two-character positive answerback has been transmitted. The latches are not2740/41 FETOM(1/69)

1-19

affected by a negative answerback. When a terminal
without receive status is addressed, it transmits thequalified
without sensing or resetting the error
condition latches. Error information, existing when
the negative answerback is sent, is retained until theterminal with'receive status is readdressed.
A qualified
response to addressing is transmitted by a terminal without receive status. In thiscase, the sense character defines the condition whichcauses the
response to the addressing sequence.
Three of these are considered as status conditions.
They are:®

®

®

1. Bid latch on.
2. In enter mode.
3. Buffer print in communicate mode.

For the first two conditions, it is assumed that a message is being prepared. Thus, the program should
continue with other processing and poll the terminal
for the message before readdressing it. For bufferprint-communicate mode, the program should continue with processing and readdress the terminal
later.
Three other conditions are considered to be operational error (rather than status) conditions because
they require operator intervention before the terminal
is ready for operation. They are:
1. Terminal in local mode.
2. Ready except out of paper.
3. Ready except document device down.

When the addressed terminal responds with thequalified
the Attention light comes on and the alarmsounds to alert the operator. Regaining status causes
the A ttention light to turn off again.
If the terminal is polled or addressed when theterm ina I or data set has power turned off, there is no
response to the CPU. However, the CPU times out
and it should post this as an error condition to the
user.

®

1-20

(1/69)

2740-2 With Receive Status Addressed by CPU
Error Condition

Answer Back

No Error Stored

Space (2)Electronic Hardware/(2)

I/O Error Received

S(2)

Parity Error Received

U(2)

Parity Error Trans.

Y(2)

2740-2 Without Receive Status Addressedby CPU
Terminal Status

Answer Back

Enter Communicate

1@

Bid Latch On

2@

Bfr. Print Comm.

4@

Local Mode8@

Out of Paper

9@

Document Devi ce Down@@

Power OffNone

Figure 1-21. Transmit Status Answerback Characters

CHAPTER 2. FUNCTIONAL UNITS

S-REGISTER• Converts parallel bits to serial (serialization).
• Converts serial bits to parallel (deserialization).
• Has a trigger for each of the BCD bits and thestart and stop bits.
• Receives data from: (1) the 1B-register when
the terminal is sending, (2) from the 'serial
data in' line when the terminal is receiving.
All data entering or leaving the 2740/2741 is inserial-by-character, serial-by-bit form. To be
usable in the terminal, the data must be in parallelby-bit form. Therefore, data must be converted
from serial to parallel form for a receiving operation and vice versa for a sending operation. The .
conversion processes, which are called serializationand deserialization, are performed by the S-register(shift register).
The S-register consists of nine triggers--oneeach for the start, B, A, 8, 4, 2, 1, C, and stop
bits--and the appropriate gating circuits (Diagram
4-1). The S-register is loaded with data fromeither the 1B-register (sending) or from the' serial
data in' line (receiving).
Serialization (Sending)
During sending operations, data from the I/O
device (or buffer, Mod 2) transfers to the IBregister. From the IB-register, the data isloaded into the S-register and serialized to the'serial data out' line. The data transfers fromthe S-register in parallel-by-bit form.
Before receiving the character from the 1Bregister, the S-register is restored by turning all
triggers on. To load the character then, those
triggers that represent a no-bit in the charactermust turn off.
Seven ANDs form the transmit-mode input to theS-register. One input to each of these ANDs is
conditioned by the absence of a bit in the associatedposition of the 1B-register. The common gating
line, 'SO reset, ' completes conditioning the ANDs,causing the character in the 1B-register to transfer
to the S-register. Bringing up "SO reset" also turns
off 'SO' and enters the start bit for the character
into the S-register. 'S8' is turned on by'S register
restore.' When 'SO reset' comes up (loading thecharacter into the S-register) no input is applied to'S8, ' so the stop bit is present for the character.
The entire character is now in the S-r,egister andmust be serialized to the' serial data out' line.
Diagram 4-1 shows that each S-register trigger
provides gating to turn the next trigger on or off.
For example, -if 'S8' is on, a gate is applied to turn'S7' on. If 'S8' is off, a gate is applied to turn 'S7'
off. If 'S7' is on, a gate is applied to turn 'S6' on.
lf 'S7' is off, a gate is applied to turn 'S6' off, etc.
This arrangement allows a bit or no-bit conditionin an upper trigger to be shifted down to the next
trigger.
The bits are shifted down through the S-register
under control of the 'SDAC' output of the serdes
clock. The 'SDAC' pulse is applied to each of theac-set and ac-reset inputs of the S-register triggers.
Each time a 'SDAC' pulse arrives, the condition of
the upper trigger transfers to the next lower trigger.
As the character shifts down through the S-register,
the 'SO' trigger turns on or off. The output of the'SO' trigger is applied directly to an AND. The otherline to condition this AND is 'send'. The output of
the AND is the 'serial data out' line. The character,now serialized, is sent over the communicationline, a bit at a time, to a terminal or multiplexer.
While the character is being shifted down throughthe S-register, 'S8' remains off because the gate toturn off 'S8' is held up.
When the complete character has been shifted
through the S-register, all triggers are off. The
absence of bits in the S-register is detected,
informing the terminal logic that shifting is completed.
Deserialization (Receiving)
Data arrives at the 2740/2741 on the 'serial data in'line in serial form. The S-register is restored to
all triggers on before data arrives. The start bit(no-bit) arrives first and this deconditions 'AND I'(see Diagram 4-1). By deconditioning 'AND 1, ' thegate to turn on 'S8' is deconditioned, while the gate
to turn off 'S8' is conditioned. The start bit also
starts the serdes clock and the first 'SDAC' pulse
from the serdes clock turns 'S8' off.
For this explanation, the character "A" is used.
"A" consists of B-, A-, and I-bits; therefore, after
the start bit, the next bit received is a B-bit. The
condition of the 'serial data in' line now reverses,
conditioning 'S8' to turn on. The next 'SDAC' pulse
transfers the start bit in 'S8' to 'S7, ' and the B-bit
2740/41 FETOM(4/68)

2-1

•is loaded into 'S8.' The next received bit is the
A-bit. The 'serial data in' line remains up. The
start bit transfers to 'S6', the B-bit transfers to'S7', and the A-bit is loaded into 'S8.' The next
received bit should be an 8-bit; since the letter "A"is being received, however, an 8-bit is not present(no-bit). The 'serial data in' line goes into a no-bit
condition, conditioning 'S8' to turn off. The previously received bits are again stepped down one
trigger position. This process repeats until theentire character has been serially loaded into andshifted down through the S-register.
When the start bit reached the 'SO' trigger, the'SO' trigger turns off. 'SO' off and 'S8' on (presenceof a stop bit) notifies the terminal circuits that the
S-register is now completely loaded with the character, and the character can transfer to the 1B-register for further use.
SEROES CLOCK• Provides clock pulses to shift data through theS register.
• Runs continuously for a sending operation.
• Runs only during character time for a receiving
operation.
For the 2740-2, one of three oscillator output
frequencies available (300 Hz, 539 Hz, 9.6 KHz).
For data to be shifted through the S-register, aclocking pulse must be developed. The clocking
pulse is the SOAC pulse generated by the serdes
clock. With the terminal in transmit mode, theserdes clock runs continuously. In receive mode,the serdes clock runs only during the time that acharacter is being received. The arrival of a valid
Start bit starts the serdes clock; the generation of an'S-register restore' pulse stops the clock.
The serdes clock consists of four triggers: 'SOl,''S02, ' 'S03, ' and 'S04' (Oiagram 4-2). 'SOl' provides gating to 'S02, , 'S02' provides gating to both'SOl' and 'S03,' and 'S03' provides gating to 'SD4. 'This gating,plus the output from the oscillator,
allows the serdes clock to be cycled. Serdes clock
operation depends upon whether the oscillator is.gated-or-.degateck __ILt.h.e_Qs_QJ1latQ1.'._i.sg~te(l~ theserdes clock runs; if the oscillator is qegated, theserdes clock does not run. The outputs of theoscillator are the 'SOCAC1' and 'SOCAC2' pulses.
These pulses, are applied to triggers 'SOl " '802,'
and'S03'.
The oscillator can be gated in two ways (Oiagram
4-2). (1) When the terminal is in transmit mode,
2-2(4/68)'send' holds the oscillator gated until the modechanges. (2) When in a receiving operation, thearrival of a start bit brings up 'not line.' If 'notline' is up for at least half-a-bit time, 'S04' turns
on, holding the oscillator gated until turned off by Sregister restore. 'Not mode change' prevents theoscillator from being gated during a mode change.
Although different methods are used to gate theserdes clock for sending and receiving operations,once gated, the clock cycles in the same mannerfor both operations. The difference is that the clock
is stopped between characters during receiving
operations. The following paragraphs describe thecycling sequence for a receiving operation (seeOiagram 4-2).
Whenever the oscillator is not gated on, 'notclock run' holds the 'SOl' and 'S02' triggers off andthe 'S03' trigger on. 'S04' would have been previously turned off by 'S-register restore.' When theStart bit is received, the oscillator is gated on,
developing the 'SOCAC' pulses and dropping 'notclock run'. The first 'SOCAC2' pulse turns on'SOl'. 'SOl' and 'SOCAC1' turns on 'S02 ..' 'S02,''S03' (already on), and' SDCAC1' turn off 'SD3. ''SD3' turning off turns on 'SD4'. 'SD4' wraps
aroung to the input of the oscillator and takes over
the oscillator gating.
It takes half-a-bit time from the drop of the'serial data in' line until '804' turns on. If the dropis caused by line noise, 'serial data in' generally
comes up before '804' turns on and degates theoscillator. Thus, line noise is prevented fromcycling the serdes clock and being recognized as acharacter. The serdes clock continues to cycle
until the character is completely received and'S
register restore' comes up. 'S-register restore'turns off 'S04, , degating the oscillator and stopping
the serdes clock. The inverted output of 'SD3' becomes the '80AC' pulse that drives the S-register.
The timing chart (Diagram 4-2) shows that theserdes clock acts as a frequency divider of the serdes oscillator. Because of clock timing, the 'SOAC'
pulse comes up midway through a bit time so thatslight variations in bit-time lengths do not causecharacter recognition errors.
The 2740-2 can be used with 75, 150, or 600
Baud lines (when a 150 Baud line is used, the terminal actually operates at 134.5 Baud). To comply
with these operating speeds, the c9rrect serdes
osciiiator rrlll.sfbeused ~ -Tlie oscIl1a:fortisea isdetermined by the line speed. For the 75 Baud rate
(75 Baud line) a 300 Hz oscillator is used as input
to the serdes clock triggers, for the 134..5 Baud rate
(150 Baud line), a 539 Hz oscillator is used. For
the 600 Baud rate, however, a oscillator frequencyof 9.6 KHz is used. This frequency is too fastfor the 600 Baud line-rate so a frequency divider(insert of Diagram 4-2) reduces the frequency byfour to 2.4 Hz before inputing to the serdes triggers.
This serdes oscillator also acts as the control
clock oscillator. Thus, by changing the oscillator
frequencies, the 2740-2 can operate with the 75
Baud telegraph line adapter, the 150 Baud data setsor IBM modems, or with the 600 Baud data sets or
IBM modems.

(using the 18 KHz osc); the pulse time is caused by
the sequence of operation of the control-clock
triggers. The control-clock 'Cl' and 'C2' output
sequence is:

CONTROL CLOCK

It is this sequence that allows the registers to be set• Provides timing for register-to-register transfers.

and reset in the proper order and accomplishes theorderly transfer of characters from register toregister.

Once in the S-register, the character transfers to
the lB-register and then to the 2 B-register. The
time allowed to transfer the character is less than
the time to load the S-register since a charactermust transfer through the registers during thetime between characters. Therefore, a control
clock that runs at a faster rate than the serdes
clock is provided.
The control clock consists of a continually running 18 KHz or 9.6 KHz oscillator, two triggers, andassociated gating circuits (Diagram 4-3). The
18KHz oscillator is used with the 75 and 150 Baudlines; the 9.6 KHz oscillator is used with the 600
Baud lines. The outputs of the oscillator, 'CCl'and 'CC2' provide the ac-set and ac-reset pulses
for the two control-clock triggers. 'CCl' and'C C2' also provide ac pulses for other triggers
throughout the terminal.
When terminal power first comes up, the 'Cl'
trigger is turned off by 'power on reset.' 'Cl' off
causes 'C2' to turn off. 'Cl' provides gating to'C2;' 'C2' wraps around and provides the turn-off
gate for' Cl.' To start the control clock, a gate isprovided to turn on 'Cl.' The AND/OR circuits at
the left side of Diagram 4-3 show the gating used
for 'Cl.' When the gate is present, 'CCI' turns
on the 'Cl' trigger. 'Cl' and the next 'CC2' pulse
turn on 'C2.' Both 'Cl' and 'C2' are now on. 'C2'
and the next' CCl' pulse turn off' Cl.' 'Cl' (off)and the next' CCl' pulse turn off 'C2.' The controlclock cycle is completed.
Each time 'Cl' turns on, the clock cycles (" Cchain"). The cycle ends and both' Cl' and' C2'
are off. The' Cl' and r C2' outputs provide thetiming necessary to transfer the characters fromthe S-register to the lB-register (then to the 2Bregister for 2740-1/2741) during receive operations; and resets the lB-register during send ing
operations. As shown in Diagram 4-3, the 'Cl'pulse has a duration of 50 microseconds andthe 'C2' pulse has a duration of 75 microseconds

1. 'not Cl' and 'not C2'
2. 'Cl' and' not C2, '3. 'C I' and 'C 2, '4. 'not Cl' and 'C2. 'lB-REGISTER (2740-1/2741)• Loaded from the S-register during receiving
operations.
• Loaded directly from the I/O device duringsending operations.
• Control characters loaded into lB by the 'lB
generate' line.
The lB-register is the intermediate storage registerfor the receiving operation and the main storage
register for the sending operation. The lB-register
is loaded with a character from the S-register during
recei ve operations. During transmit operations, thelB-register can be loaded in three ways: (1) directlyfrom the I/O device transmit contacts (print orfunction characters), (2) by bringing up the 'lB
generate line' (control characters), and (3) by -0(delta) inputs for some special features (Diagram
4-4). Only the basic-terminal inputs are explainedin this section.
With the terminal in transmit mode when a key ispressed on the I/o keyboard, the I/o device takes acycle. During the cycle, the transmit contacts forthe desired character transfer, and alB-registergating pulse develops. This gating pulse is called'strobe.' 'Strobe' tells the terminal that the I/O
device is far enough along in its cycle to correctlytransfer the character from the transmit contacts tothe lB-register. Diagram 4-4 shows this input.
The input from the I/O transmit contacts ('integrated
printer' 1 -7) partially conditions the seven lB-register
input ANDs. When the 'strobe' line comes up, conditioning of the ANDs is completed, and the desired
character is loaded into the lB-register. The character then transfers, under control of the control
clock, to the S-register for serialization.

2740/41 FETOM(4/68)

2-3

Another group of ANDs loads the control characters. When the operator presses either the EOT or
the bid key, the 'IB generate' line comes up. 'IB
generate' conditions the ANDs to the'IB3, ' '1B4''IB5, ' 'IB6,' and 'IB7' latches. If the operator
presses the Bid key, the 'not bid' line (active forevery operation but bid) deconditions the ANDs to the'IB4' and 'IB7' latches, and a @ character (821) is
loaded into the IB-register. If the operator presses
the EOT key, the © character (8421C) is loaded
into the IB-register. Once in the IB-register, thecontrol character transfers to the S-register and isserialized.
With the terminal in receive mode the IB-register
is reset before receiving a character and again after
the character is transferred to the 2B-register.
The input to the IB-register is from the S-register.
A group of ANDs, one for each latch, is conditioned.
by 'not send, ' 'IB set, ' and the output from theassociated S-register trigger. The main gating
factor is the 'IB-set' line. After transferring to the
IB-register, the character then transfers to the
2B-register for printing or the desired function. The
dotted line in Diagram 4-4 are for special features
and are discussed in Chapter 4.
IB-REGISTER(2740-2)• Loaded from the S-register during receive operations.
• Loaded from buffer storage during transmit
operations.

©

® with R. C. )• Control characters except(orloaded by bringing up lIB Generate~

The IB-register receives characters from the Sregister during receive operations, and from buffer
storage during transmit operations. Control characters except(orwith Record Checking) are
loaded directly into IB during transmit operations
and do not come from buffer storage.
Control characters are analyzed while in the IBregister to determine further terminal operations
during both receive and transmit operations.
The IB-register (Diagram 4-5) consists of sevenlatches, one for each of the data bits and checkbit. The latches are turned on to load the register--witli-1>lts-from-thr-ee-sou.-rce-s:--(ntiie-ouipui-of the
S-register, (2) the output of buffer storage, and (3)by special circuits for control characters.
During receive operations, when a completecharacter is in the S-register, the control clock isstarted. The control clock outputs bring up IB set,©

2-4

(1/69)®

which, with 'not send' and the S-register output,
transfers the character to the IB-register.
During transmit operations, the IB-register isloaded a character at a time from buffer storage.
'Memory buffer' and the outputs from the buffer
address clock, "scan" the character into the register serially by bit.
Generated Data®

The control characters except © (orwithRecord Check) are loaded into the IB-register without passing through another register or buffer storage. The control characters are used to control theterminal mode. ~he© (with R. C.) character
is loaded into buffer from the 2B-register and ends
the terminal transmit operation.
The control characters that are loaded into the
IB-register (except for theand sense characters)
are primarily the result of bringing up the 'IB generate' line. The
character does not require' IB
generate.' 'Transmit answerback' and t lB set not
EOT' bring up 'initiate IBI-B bit.' The
is delayed until the 'not 1st status character answerback'allows the IBI-B bit to be set as the second character of the two character answerback. The sensecharacters are loaded into the IB-register primarily
as a result of bringing up the t load 1st characteranswerback' line.
'IB generate' is brought up in various ways and isdiscussed in the "Principles of Operation" section ofthis manual. However, it should be noted that 'IB
generate' is delayed for one character time to allow@ to be set as the second charact er of the qualified(two character) answerback. The controlling
logic shown in Diagrams 4-5 and 5-22 is not explained
here, but it is shown for servicing assistance andconvenience for the reader.

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CD

2B-REGISTER (2740-1/2741)• Stores a character until the I/o device is readyto accept it.
• Is used ohly for a receiving operation.
The 2B-register is the input to the print-and-function
decode circuits. The received character is store~i!!.. j;h.€l_~~:.r~l§.t~.r_!l.nlli _ t]l~_lllLde.Yic e _is_rea_dy..t.Q
accept the character. The 2B-register is not used
for a sending operation (transmitted characters go
directly to the IB-register).
The 2B-register consists of seven latches(Diagram 4-6). During a receiving operation,
characters transfer from the IB-register to the 2B-

register. Before a character is loaded into the 2Bregister, the '2B reset' line is made active to resetthe entire register. The condition needed to load
the 2B-register is '2B set' and 'not 2B inhibit' ANDed
with the outputs of the 1B-register latches.
The '2B inhibit' line is present only on those2740's equipped with t~ record-checking feature.
If an error occurs, the '2B inhibit' line becomesacti ve, blocking the transfer of a new character
into the 2B-register. A special input to the '2B1'
latch, '~2B1,' turns on the latch. The presence ofa bit in the '2B1' latch causes the I/O device toprint a dash in place of the error character.
The output of the 2B-register is gated to the I/odevice through the print- or function-decode circuits.

Gene ra ted Data
When the enter operation ends (Bid key pressed), a
stop code is loaded as the last character in memory.
This characteroris generated by logic,
and does not come from the I/O printer transmit
contacts. 'Store stop code' and 'read' turn on theproper latches. The stop code then transfers tobuffer storage.

(©

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PRINT AND FUNCTION DECODE, (ALL MODELS)
Print Decode• Translates print characters to I/O code andstarts a print cycle.

2B-REGISTER (2740-2)• For receive operations, the 2B-register is loaded
from the 1B-register.
• To end the enter (and later the transmit) operations, a stop code (oris generated atand loaded into 2B and then stored in buffer storage as the last character.

©

®)• For enter operations, 2B is loaded from the output of the I/o printer transmit contacts.
• For buffer print operations (local mode or buffered recei ve feature) the output of buffer storageis transferred to 2B for printing on the I/oprinter.
The 2B-register(Diagram 4-7)receives characters(1) from the 1B-register during receive operations,(2) from the I/o printer transmit contacts during
enter operations, and (3) fro m buffer storage during
buffer print operations. The stop code (oris generated at 2B for storage at the end of enter
operations.
During receive operations, a character received
from the transmission line at the S-register istransferred from the S-register, through the 1Bregister, to the 2B-register. Once the character isin 2B, the S-register is available to receive anothercharacter. Meanwhile, the character in 2B isdecoded and printed. The character is loaded into
2B when '2B set' is brought up.
During enter operations, characters come fromthe I/o printer transmit contacts. This is accomplished during the I/o cycle when strobe comes up.
When the contents of buffer storage are to beprinted, 'buffer print, , 'memory buffer, , and thememory clock outputs "scan" the character into 2B,
a bit at a time. The character is then decoded andprinted.

©

®)• Identifies print characters by a non 8-4 combination in their bit structure.
The purpose of the print-decode circuit (Diagram
4-8) is (1) to decode the received print charactersto the proper tilt and rotate I/O code, (2) to activate
the proper magnet drivers, and (3) to cause thecharacters to be printed. The print-decode circuit
consists of various AND/OR circuits that input to themagnet drivers. These AND/OR circuits are conditioned by the output of the 2B-register to activate
the magnets needed to print the characters.
Two gating lines are used to gate the 2B-registercharacter to the print-decode circuit: 'print out'
and 'print.' The 'print' line indicates that thecharacter to be decoded is a print character. Thisline comes up when an 8-4 combination is notpresent in the character. The combination of an
8 and 4 in the character designates a function character, causing the function-decode circuit to begated. The 'print out' line comes up when '2Bregister full' (indicating that the 2B-register iscompletely loaded with a character) and 'not I/O
cycle' come up. 'Not I/o cycle' indicates that theI/o device is not presently printing a character or
performing a function and is therefore ready toreceive the incoming character. If the I/o device
is operating, the 'not I/O cycle' line is down, blocking 'print out' line. When the character has completed printing, the 'not I/o cycle' line becomes
active, allowing the character in the 2B-registerto be decoded and to start another print cycle. For
example, character "A" consists of the BCD code
B, A, and 1. The I/o code requires that rotate
magnets 2A, 2, 1, and -5 be picked. Diagram 4-8
shows that the indicated magnets are picked by the
BCD code of character "A". When the magnets are
picked, the I/O prints the character.

2740/41 FETOM(1/69)

2-5

Function Decode• Translates function characters to I/O code andstarts the function cycle.
• Identifies function characters by an 8-4 combination in their bit structure.
The function-decode circuit operates similarly to theprint-decode circuit, yet the presence of an 8-4 combination activates the function-decode circuit. If
the character contains an 8 and 4, the 'non-print\function' line comes up. The character code isagain decoded into the necessary I/O code to activate
the proper function magnet. The same 'print out'line used by the print-decode circuit gates thefunction-decode circuit.
Each of the six I/O functions requires a different
combination of bits in BCD code to be activated. For
example, for a backspace, the BCD code is B, 8, 4,
and 2. Diagram 4-8 shows that these conditions
activate the backspace-magnet driver. This in turncauses the I/o device to perform a backspace operation. When the backspace operation starts, the'print out' line drops. Dropping the 'print out' line
prevents the printing of a print character or the
performing of another function operation until thepresent operation has been completed.
STROBE AND I/O CYC LE (ALL MODELS)• I/O printer timing for terminal logic.
• Si~'als originate through I/o printer contacts.
• Two signals from printer: IOC (I/O cycle) andstrobe.
• Terminal logic generates four signals:
1. 'I/o Cycle' (latch)--same timing as laC contacts.
2. 'Strobe 0' (trigger)--same as electrical signal,'strobe, ' clipped by CCI and conditioned by'enter. '3. 'Strobe' (trigger)--same as 'strobe 0, ' offset
25 usec later (CC2).
4. 'I/O check strobe' latch--same as electricalsignal, 'strobe,' enabled by 'I/o check enable. 'Two I/O timing signals, laC (I/o cycle) and strobe,
originate by transfer of contacts. Basically, laCmeans that a cycle has started, and strobe meansthat transmitting contacts can be sampled.
Two chains of transfer contacts complete thecircuit for the I/O timing signals (Diagram 4-9).
One contact in each chairi transfers for anyone
2-6(1/69)

operation. The C5/6 contact is common to bothchains.
Depending upon the function, printer ('C')
contact(s) transfer with each mechanical cycle. The
laC and strobe N/O signal are generated as soon as
the N/O contact(s) transfer.
Note that the timing charts (Diagram 4-9) indicatethat the laC N/O contacts mechanically make withor before the strobe N/O contacts and open with orafter the strobe N/O opens. This is done to insurethat the transmit contacts have had time to settle
before they are sampled.
The strobe, strobe a and laC contacts provide
the proper timing conditions for the transfer ofdata from the I/O printer contacts to the 2B-register.
'I/O cycle' and 'I/o check strobe' allow checkingof the I/O printer during 'buffer print and communicate, ' or 'receive text and not receive text buffer. 'Either of these modes brings up 'I/O check enable. 'I/O cycle provides the proper timing conditions
to transfer the character to be printed from the 2Bregister into the I/O check enable and I/O checkregisters.
'I/o check strobe' provides the proper timing
conditions to allow data from the I/o printer contacts to control the set and/or reset of the I/o checkregister as printing is done.
COMMUNICATE/LOCAL AND STATUS• 2740 status allows mode changes necessary forcommunicate operations.
• Local operation drops status.
• Paper present can be mechanically by-passed on
the 2740-1.
Communicate/Local• Communicate operation for transmit, receive(or 2740-2 enter).
• Local operation for use of I/O printer as a typewriter.
• Local operation for 2740-2 enter or buffer print.
The_following communicate_ conditionsdrop_status:_out of paper, line adapter not operative, or waiting
to transmit. On the 2740-2 enter, buffer print, or
document insertion guide in insert position will
also drop status.
The Communicate/Local switch controls the'comm-Iocal' trigger. Changing the switch position
to Local is ineffective unless the 2740 is not printing

from buffer storage and is in the text non-selectedmode or control receive mode (Diagram 4-11).
The comm-Iocal trigger turns on (local) at CC2 whenthese conditions are met. However, the trigger willturn off (communicate) at the next CC2 after changing
the switch to Comm.
Local drops status and causes the I/o printermotor to run.
Status• Status can change at any CC2 except during transmit answerback.

performed, the 'operate' trigger is turned on byeither 'I/o cycle' or 'not strobe 0 reset gate.' Assoon as these conditions are removed, the 'operate'
trigger turns off.
When the terminal is in transmit mode, and acharacter is in or being shifted through the Sregister, the 'operate' trigger is turned on by 'not S
register empty.' As soon as the character has completely shifted out of the S-register, 'not S register
empty' drops and the 'operate' trigger is turned off
by 'not SD1, ' 'SD2, ' 'SD3' and 'send. 'BUFFER STORAGE (2740-2)• Status conditions are those necessary forreceiving.
The status conditions gate the 'status' trigger on or
off at every CC2 (Diagram 4-11). A change in statusis prevented only during transmit answerback (whenprevailing status is sent-- <X) for status,fornot-status). The operator is responsible for thecondition of the terminal since the time that a message will be received is unknown. Status circuits
drop status if any lack of capability for receiving isd.etected.
If the terminal does not have status during anormal address sequence, the 2740 will respond withand ring the alarm bell. The 2740-2 will turnon the message light also.

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OPERATE TRIGGER (ALL MODELS)• Prevents the terminal from leaving transmit orreceive mode until the operation is complete.
The function of the 'operate' trigger is to indicate
to the terminal that a character is (1) being printed,(2) being acted upon by the terminal (receive mode),or (3) in the process of being shifted through the
S-register to the' serial data out' line (transmitmode). The 'operate' trigger prevents the terminalfrom leaving transmit or receive mode until theoperation is complete. The status of the mode
triggers cannot change until the' operate' trigger
turns off.
The 'operate' trigger (Diagram 4-10) is turnedon by any of the following conditions: 'I/O cycle''communicate, ' and 'not send, ' 'not strobe 0 resetgate' and 'not send, ' '2B set set gate, ' '2B set, ''not 2B empty, ' or 'not S register empty. 'With the terminal in receive mode, when a character (1) is about to be loaded into the 2B-register(2B set set gate'), (2) is presently being loaded into
the 2B-register ('2B set'), or (3) is in the 2Bregister ('not 2B empty'), the 'operate' trigger turns
on. If a character is being printed or a function being• Magnetic Core storage device has a maximum of
3, 136 cores (448 characters).
• Processes a bit (one core) at a time using a one
position 'memory buffer' trigger.
• Bit counter, address register, and 'read-write'
trigger are used for timing and addressing
system.
• Store (write) characters during enter or buffer
receive character cycles.
• Readout (read and regenerate) characters during
send or buffer print character cycles.
The 2740-2 buffer storage is a magnetic core storage device with optional 128-, 256-, or 448character capacity. Buffer storage is an intermediate point in the flow of data characters from theI/O keyboard to the communication line (Figure 2-1).
ENTER stores input characters sequentially in
buffer storage, and SEND retrieves characterssequentially from buffer storage to transmit them.
BUFFER PRINT retrieves characters to print them.
The description of buffer storage begins with abrief explanation of coincident-current, magneticcore-storage theory; then functional units of buffer
storage are explained. The functional units are:
1. Bit counter (character cycle)
2. Buffer address register (chooses character
location in buffer storage)
3. Buffer storage circuits (control data input andoutput from buffer storage)

Magnetic Core Theory• A magnetic core is a small ferrite (powderediron) ring.

2740/41 FETOM(1/69)

2-7

• A core can be magnetized in either of two directions; one represents binary zero (no bit), theother binary one (bit).
• Each core represents one bit of data.
• A core is magnetized by passing electric current
through its center.
• Two wires, each carrying 1/2 magnetizing
current, pass through each core (coincident
current system).
• One wire is horizontal, the other vertical.
• A third wire for sensing core flip goes throughall cores.
• A read pulse and a write pulse are generated foreach bit time.

I/O Printer(Contacts)• At read time, the selected core is reset to zero.
• At write time, the selected core can be flipped
to binary one.
A magnetic core is a small ring of ferromagnetic
material, a few hundredths of an inch in diameter.
It is a mixture of ferric oxide powder and othermaterials, pressed and baked to form a ferrite ring.
Important advantages of the core are its size,
speed, power requirements, and its ability to retain
a magnetized state after current flow through thewire(s) stops. Hundreds of characters may be
stored in cores mounted on one plane on a small
pluggable card. The magnetic state of a core canbe changed by a short pulse of current passing
through the ring. The duration of the magnetizing
current pulse is only a few millionths of a second,
but the core retains its magnetism indefinitely.

2B

2B
1-'"

Register

Registert--

I/o PrinterI

I

L ____ .,Enter (Locol or Comm)----Send (Comm)

I

I

1

I

Buffer Print (Locol)

BufferStoragelB
RegisterFigure 2-1. Overall Flow of Outgoing Message

2-8,(lj69)

S
RegisterCommun i cati ons
Adapter

Communications
Interface

l---_
Line

A number of ferrite cores placed like beads on asingle wire are magnetized when a sufficient amountof current is passed through the wire (Figure 2-2A).
The direction of the current flow determines thepolarity or magnetic state of the core. It retains
the magnetic state after the current stops andreverses its magnetic state when the current isapplied in the opposite direction (Figure 2-2B).
Consequently, these two states can be used to represent 0 or 1, plus or minus, yes or no, on or off,
bit or no bit conditions.

Current is AppliedCore is Magnetized

A. Polarity of Magnetic Cores

B. Reversing a Core (Flip)

C. Selecting a Core (Addressing)

D. Core Flip and Sense

Current is reversed;
the core reverses
its magnetic state

Figure 2 -2. Core Theory

2740/41 FETOM(4/68)

2-9

A system of addressing must be devised to access• Each wire carries current individually.
each core. To accomplish this, the one wire passing• Each wire can carry current in either direction.
through each core is replaced by two wires(Figure 2-2C). If half the required current passes
through each of two wires the effect is the same as• Vertical current direction selects odd or evencore.
one wire carrying the required current. A large
number of cores can be strung on a screen of wires
and anyone core in the screen can be selected.
The two current carrying wires used in buffer storThis is done by applying one-half current to only
age are the vertical wire and horizontal wire. A
two wires. The core affected is the one at thecore is selected for read or write by coincident
intersection of these two current carrying wires.
current flow in these vertical and horizontal wires
No other core, even on the "half current" carrying
passing through the addressed core. Figure 2-3A
wires, is affected. Using this principle, theillustrates how the magnetic cores in a terminal
number of cores in an array can vary from a few
buffer are strung on wires that cross at each core.
hundred to more than a million.
This method of arraying the cores provides the
When the current in a pair of wires through a coreselection system. The third (sense) wire is not
is coincident, the core assumes a definite magnetic
shown in the figure.
polarity. If the coincident current is reversed, theAssume that the heavy lines in the figure repremagnetic state is suddenly reversed and the core issent the acti ve current lines, each carrying onesaid to flip (flux reversed). One magnetic state has
half current required to flip a core. All the cores
been predetermined to represent a bit (one) and thestrung on the active vertical and horizontal wires areother a no bit (zero). Storing a bit of information
subjected to the effect of this one-half current.
is referred to as writing; retrieving, as reading.
One-half current is not sufficient to affect the magEach time the core is addressed the cycle consists
netic state of a core, but two of the cores are subof read time first and then write time. During read
jected to both the horizontal and the vertical current
time the circuits attempt to flip the selected core
carrying wires. At this point the current direction
from a "one" state to a "zero" state. If the coreis important and determines which of the two cores
was in the "one" state prior to read time, the data
will flip.
is detected (read) by resetting the one to zero.
A schematic representation of current flow
Therefore, the core is reset, and readout is des(Figure 2-3B) is used to show the current flow
tructive. At write time the same core may be flipped
relationships. Assume that right-to-left horifrom a "zero" to a "one" state.
zontal current is read current, and left-to-rightA third wire is threaded through the core for thehorizontal current is write current. Since the verpurpose of sensing a pulse at read time (Figure
tical wire through the odd and even core columns
2-2D). When the magnetic state of the core isis the same wire, the terminology "read even orreversed, the abrupt corE' flip (flux reversal) is ofwrite odd" and "read odd or write even" is used to
sufficient magnitude to induce a voltage and generate
define the direction of vertical current flow.
At read time, the vertical read odd current flow
a pulse. Only one sense wire is needed for an entire
core plane, because only one core is selected anddown through the odd core coincides with the horiread at a time. Even though a pulse is induced inzontal read current at the odd core. The samethe sense wire each time a core flips at read time
vertical current loops back up through even core andand write time, the output circuits monitor thecancels the effect of the horizontal circuits. Thus,
sense wire at read time only.
the odd core is selected to read, while the evenTo retain the information in buffer after it iscore is not affected.
read-out, it must be rewritten. Each bit sensed
At write time, both the horizontal and verticalin storage may be restored immediately after it
currents reverse. Again the odd core is selected
is read by allowing it to be rewritten into buffer
to be flipped while the even core is not affected.
at the following write time. This process, referred
During read and write time the horizontal current-------te-as regene r~-ie--in-the-bttffered--------- -----flow-ts-controtte&withmrrre-Wcfrd-~oo_aaor even coreterminal. The bits are not regenerated at any time
selection. Selecting the even core to read and writethat new data is to be placed in buffer.
is a matter of starting the vertical current read-write
sequence with read-even and completing it with writeOdd-Even Core Scheme
even. The horizontal and vertical current coincide at
the even core and cancel at the odd core to read and• Cores are strung on wires that cross at rightthen write (regenerate) the even core only.
angles.
2-10(4/68)

I

Even
Core

Vertical

---+

Write

I Read even or

Horizontalt write odd

or write evenA.

B.

Figure 2-3. Addressing by Current Coincidence and Cancellation

Selection of either of the two cores where thewires cross has been made possible by controlling
the phase relationship of vertical current to thehorizontal current. This odd-even core scheme
reduces the number of current carrying circuits
required to address core in the buffer storage array.
One of the Buffer Address positions ('BA5') is used tocontrol the vertical current direction. When' BA5' is
off the vertical current wire selects read odd and write
odd; when 'BA5' is on, read even and write even.
Character Cycle• Basic buffer storage cycle.
• Processes one character.
• Eight bit times (0 through 7).
• Starts from 2B full when storing, 2B empty on
printout, or IB empty when sending .

The entire character cycle is 1. 56 milliseconds
long and begins with a demand to store a character(enter or buffered receive) or to retrieve a character
buffer print or send).
NOTE: With the Speed Base-600 bps feature, a 9.6 KHz
os ci lla tor is used to time buffer storage. A charact er cycleis then 2.92 milliseconds long.

Buffer Storage Address Counter• Counts in binary• Consists of two parts: buffer address register andbit counter.
The buffer storage address counter controls theselection of a specific magnetic core. This involves
selecting a vertical array line, a vertical current
read-write sequence (odd or even), and a horizontal• Runs for a minimum 1.56 ms with 18 KHz oscillator; 2.92 MS with 9.6 KHz oscillator (600 Baud).

Seven cores represent a 2740-2 character in buffer.
One character cycle spans all timings needed tostore or retrieve one character.
Each character cycle has eight bit times(Figure 2-4). Bit times 0-6 correspond to character
bits 1 through 7. The eighth bit time is used for endof-character or idle timings.
Each bit time has a read time and a write time
(Figure 2-4). Read-time horizontal and verticalcurrents allow flipping the selected core from binary
one to binary zero. Write time horizontal and verticalcurrents allow flipping the selected core from binary
zero to binary one.

~

274o-2 Chomcte,

Buffe'
Address,71

Ch~r:;;e-;-BiA

Time,

.1

.1

Cha,acte' Cycle

1 1 2 1 3 1 4 1 5 1 6 17I112
I 3I 4
I 5
I 6I 7II I
0.2! -c~~~ ~Figure 2-4. Buffer Storage Character Cycle

2740/41 FETOM(4/68)

2-11

array line (Figures 2-3 and 2-6). This counter also
provides sequential selection of every core in thearray.
Buffer Address (BA) 1, 2, and 3 make up the bitcounter. Positions 4-12 of the buffer storage address
counter make up the buffer address register. This
register can count from zero to 511, but automaticallyskips certain counts when it advanced beyond 256(See Diagram 4-15). The decimal values of the buffer
address register positions, as shown in Figure 2- 5,
add up to the character address in the buffer. In theexample, the binary ones have decimal values (rightto-left) of 4+8+32+64+128=236. The 236th characteris addressed during that cycle.
Bit Counter (Diagram 4-14)• Initially reset on (BA1, 2, and 3).
• Steps at end of each write time.
• Counts from 0 through 6 each character cycle(bits 1 through 7).
• Character cycle ends when count is 7 (BAl, 2,
and 3 on).

12 (448-character) of the buffer storage address
counter. Counting is in the normal binary manner
when BA 12 is not present.
Buffer address register triggers 4 through 10,
11, or 12 comprise a binary counter. Each trigger
has gates for turn-off that enable the counter tocount either forward (normal) or backward (reverse).
Diagram 4-15 illustrates each set of gating conditions that causes a buffer address register trigger
to turn on or off. Read down the chart for normal
counting, and up the chart for reverse counting.
'Buffer address 11' is used only with the 256- and448-character core arrays, and is not present withthe 128-character core array. Also" 'buffer address
12' is used only with the 448-character array.
Buffer address positions 4 and 6 select one of 4
vertical drivers. BA7, 8, and 11 select one of 8
vertical switches. BA9, 10, and 12 select one of 7
horizontal drivers (Figures 2-5 and 2-6).
Buffer address position 5 is used to define verticalcurrent direction (phase) and select the odd or evencore in the odd-even core selection scheme. With
BA5 off,the odd core is selected; and with BA5 on,
the even core is selected.
Address Register Control (Diagram 4-15)

At the beginning of each character cycle the bitcounter steps from 7 to 0 (first bit position). At
the end of each subsequent read-write cycle, thebit counter advances sequentially through address bit
positions two through seven (bit times 1 through 6).
Bit time seven ends the character cycle. The outputof the bit counter controls selection of one of sevenhorizontal switches (Figure 2-6).
Buffer Address Register (Diagram 4-15)• Initially reset off (zero).

• 'Buffer counter ac input' steps address register.
• Address steps normal (forward) or reverse(backward).
• Address register resets to zero automatically:
1. When Enter key is pressed.
2. At start of buffer print.
3. At end of transmit text.
4. At start of transmit text.
5. When Reset key is pressed.

• Steps binarily at the start of each character cycle.
• Buffered Receive feature adds three more resets:• May contain seven, eight, or nine triggers.
• When maximum nine triggers (BA 4-12) arepresent, 64 counts are skipped.

1. At the end of on-line buffer print.
2. At the start of receive text.
3. At the start of retransmission from central.

• Can step backward (reverse).

Address Register Advance• Count of zero identifies 'buffer address empty. 'The character address steps normal or reverse,
one address at a time. The step results from gating
shown in Diagram 4-15 and takes place when the'buffer counter ac input' line comes up (Diagram
4-16). This line may rise from two sources:• All triggers on identifies 'buffer overflow. 'Character addresses originate from BA 4 through10 (128-character), BA 11 (256-character), or BA

2-12(4/68)

1. The 'buffer address 3' trigger turns off and is

a forward (normal) advance from the memory
clock. Because a character cycle ends with'buffer address 1, 2, and 3' on, and 'readwrite' off (write), the next character cycle
begins when 'read-write' turns on (read) and'buffer address 1, 2, and 3' turn off. Therefore,
the buffer address register steps normal at thevery biginning of a character cycle.
2. The 'reverse counter sequence control' trigger
turns on at 'CC1'. This is a reverse step,
usually caused by a backspace operation whenentering from the I/o printer keyboard. A
reverse-count requires 'reverse counting
sequence' and 'not buffer address empty'. The'reverse counting sequence' trigger is on for
50 usec starting at the end of 'strobe' time.
There is no character cycle at the time because'reverse counting sequence' inhibits the turnon of the 'read/write' trigger (Diagram 4-18).

'Buffer address time 7' allows the 'buffer 2B
reset' trigger to operate. The backspace codeis reset from 2B at 'CC2', and 'memory go'
drops without starting a character cycle.
A second reverse count condition occurs
when changing from buffer print to enter, at theend of an off-line (local) printout. The operator
may choose to continue entering, so the stored
stop code must be replaced by the next character entered. The' edit control 3' trigger
turns on when the stored stop code appears in
2B. The same stop code resets the 'buffer
print' trigger, and the 'reverse counting sequence' trigger turns on. The' enter' trigger
turns on, too, but the same series of events
described in the preceding paragraph preventsa character cycle. The stop code resets out
of 2B, leaving the character address ready tostep to the stop code address when the next
character is entered.

Buffer Storage Address Counter
Buffer Address Register (Character Address)

Bit CounterII

Address Example
o 0- - - - -... 0ooFigure 2-6oBuffer Addressr - -......---..--,----,----,r--.,----,.--,---,-----,r---r----,
Triggers~.....;.--u-_ _ _ I Read Time
Decimal Value _ _ _ _.h~_t""TIiRr-ll-r,.nl_;:_t-T_t----::;r_t-?-rl__t~,t-T_t__;_t

7 Horizontal Switches
4 Vertial Drivers
Control Vertical Current Direction(5 off for read odd, write odd.
5 on for read even, write even.)
4 (without 11) or 8 (with 11) Vertical Switches
4 (without 12) or 7 (with 12) Horizontal Drivers
Note: 128-character array uses address trigger J- J O.
Trigger J J is added for 256 characters and trigger 12 for448 characters.

Figure 2-5. Buffer Storage Address Counter2740/41 FETOM(4/68)

2-13

Vertical
Switches

BA 3, 2, 1
1~------------~-------.-------.~----~.-------.-------~------~

E ~ 2 lOOf)LJ~. . ~---.·------~+-------~-------e~------~~----~~------~~------,.
6~ 3 ~-----.--------~~------~r+------~+;------~~+-----~~4-----~~~----~.~ ~ 4011----------~~~----~~+_--~~~r_--__~~----~~~----~~4_--~~~ 5l00--------~~;_t+--~~~~--~~~rr--~~~~--_.~~~--_.~~~--_,
6
7

ooo~

101------~T+~Hr_.~~r+~~r+~~~+4~~~~~+_~~~4_~(X)

110----~~T+~Hr~~~r+~Hrr+~~r++4~~+4~~~~~~~

(
JC

\.

rx:
\.:

256- or 448character
arrays, only

(

r

lC

r

lC

r

J(

(
lC

\.

r

lC

\.

r.vt-+t-I~-t-H-t-+-I~-HI-t-+H-+-~I-+-t-+-+-++-1I-+-t-H-++-1I-t-t-H~H-+--HI-+-t-H--+--+--t--+.....
K.

Verti cal

{
)(

(

(

x.

\~r+~~~r+r+~~Hrr+++;1~Hr~++~~~+++4~~~r+~~~-+-+-.
r.~
)(

\.

BA 12, 9, 10

Ec:
0

1
2

6

11
010
001
000
100
110

7

111

~3

.~ ~ 4

~ ~5

..
~

4

""__-----448- character1
array, only
Note: This drawing illustrates the whole array, but is a schematic and does not show actual wiring.
The circled address examples also appear in Figure 2-5.

Figure 2-6. Array Wiring and Addressing
2-14(4/68)oo::: 0

Horizontal

:::

..

8 :::o~CS.:'-l

~

3

2

1

~ Vertical Drivers

Address Register Reset

Buffer Storage Array and Addressing (Figure 2-6)

The 'reset buffer address' trigger (Diagram 4-16)
turns on to reset the buffer address register and the
bit counter. The address register resets to zeroand the bit counter to seven. The turn-on gate for'reset buffer address' offers several ways to reset
the address, with additional provisions when the2740-2 has the Buffered Receive feature. All ways
are listed here (unique Buffered Receive resets
identified by asterisks):• 16 or 32 vertical lines, 4 drivers and 4 or 8
switches.

1. The Enter key is pressed and the 'enter' trigger
turns on. This resets the buffer address at thevery beginning of an enter operation.
2. When the Reset key is pressed with the 'enter'trigger on. (The only other action of the Reset
key is to reset the 'enter' trigger. )3. The 'buffer print' trigger turns on. This action
occurs off-line (local) when the Bid key ispressed with the 'enter' trigger on. The resulting stop cod e (Diagram 4-18) turns on the'buffer print' trigger and the 'reset bufffer
address' trigger (Diagram 4-16).
*On a Buffered Receive machine, 'buffer
print' turns on afteris received. This is
the signal for the 2740-2 to read out the message
stored and print it on the I/O. The buffer
address register and bit counter reset just as
they do at the start of off-line buffer print.
4. Transmit text starts. The mode change totransmit text resets the address so that thefirst character sent is the first character inbuffer storage.
5. Transmit text ends with an affirmative acknowledgment. This reset prevents manual retransmission of the stored message. If an affirmative
answerback ( <X) ) is not received, the address
does not reset.
When the mess3.ge acknowledgment is @ ,directing the 2740-2 to receive a message,
buffer address resets.
*6. On-line (communicate) buffer print ends. This
reset prevents unintentional transmission of thereceived and printed message by accidental
depression of the Send key.
*7. Receive text buffer starts. The mode change
to receive text resets the address so that thefirst character received stores at the firstcharacter address in buffer storage.
*8. Receive text buffer begins without the~revious
message having been printed out (no <.QJ). Thiscase comes up when the 2740-2 sends a negative
acknowledgment to a received message andcentral retransmits the message. The retrans . . .
mission must be stored starting at the firstcharacter address in buffer storage.

©

• 28 or 49 horizontal lines, 4 or 7 drivers and 7
switches.
• Card-mounted array, diodes on array card.
• Diodes at switch end of lines, only.
• Current source is positive, current sink is
negative.
• Each driver or switch has a source and a sink.
• Vertical and horizontal lines coincide at twocores, even and odd.
• 'Buffer address 5' trigger controls odd or evencore selection (vertical current direction).

A set of vertical and a set of horizontal lines form
the matrix that is the buffer storage core array.
The address in the buffer address register, plus
the decoded bit count, selects one driver and one
switch for each set of lines.
Line selection is complete when a positive source
and a negative sink are selected; only then can current flow. To provide for this polarity selection,
each driver and each switch contains a positivE'
source and a negative sink. The positive source isconditioned by one gate and the negative sink is conditioned by the other gate.
Positive or negative polarity gating affects all
drivers or all switches, either horizontal or vertical.
The horizontal and vertical gates have two purposes:(1) to provide timing, (2) to select the correct
driver and switch polarities. Thus, the gates control the timing and direction of array currents. In
addition, the 'horizontal driver write gate' controls
whether a bin (binary one) will be written into theselected core.

Memory Clock (Diagram 4-18)• Is timed by 'CC1' and 'CC2' pulses.
• Provides 7 read-write sequences each character
cycle.
• Times array currents and advances bit counter.

2740/41 FETOM(4/68)

2-15

• Consists of three triggers: 'read-write,' 'VICG'(vertical current control gate), and 'HICG' (horizontal current control gate).
The memory clock controls array currents and advances the bit counter, which in turn advances theaddress register. The clock starts when the 'memory
go' signal is up and 'read set gate' is not inhibited.
It runs in a read-write loop until 'buffer address 7
time ends the character cycle. Controlling conditions for 'memory go' assure a full character cycleand no more.
The vertical and horizontal array currents flow
only when the two controlling clock triggers are on.
The 'VICG' (vertical current control gate) trigger
times vertical current, and the 'HICG' (horizontal
current control gate) trigger times horizontal current. The terminal clock 'CCI' and 'CC2' pulses
operate these two triggers and the 'read-write' trigger which controls current time in the read-write
sequence (Diagram 4-18).
The 'memory go' line rises when a character cycle
is needed. When inhibiting conditions are not present, the 'read set gate' line rises. The 'read-write'
trigger turns on to 'read' at 'CCI' for the first readwrite sequence, the bit counter steps from 7 to 0
and the buffer address register (character address)
advances to the new character address. 'VICG' turns
on to gate vertical read current at 'CC2' and "HICG'
turns on at the following 'CC1' to gate horizontal readcurrent. 'VICG' and 'HICG' turn off at 'CC2' and'read-write' turns off to Write at the next 'CCI. ''VICG' turns on again at 'CC2' to gate vertical write
current, and 'HICG' turns on at 'CCl' to gate horizontal write current. 'VICG' and 'HICG' turn off at, C C2.' The' read set gate' line rises again and thenext 'CC1' starts another read-write sequence. The
read-write sequence is 222 usec--11l usec for readand 111 usec for write.

NOTE: With the Speed Base--600 bps feature, the read-write
sequence is 417 usec.

Buffer Data Control~LSlngl~QSition data register.

called 'memory

buffer. '• One sense amplifier.
• Storage operation degates the sense amplifier.
• Bit is stored by gating horizontal current.

2-16(4/68)• Addressed bit regenerates during readout .
• 'Memory buffer' provides input to lB-registerduring transmit, 2B-register during buffer print.
• Data bit comes from 2B-register on enter.
• Character is checked for odd parity during buffer
print or enter.
'Memory Buffer' Trigger (Diagram 4-18). This isa one-position storage data register which allows
bit-by-bit storage input or output. The bit timer disassembles characters from 2B-register into bits for'memory buffer' when storing and assembles bitsfrom 'memory buffer' into characters when readingout to the IE-or 2B-register.
The main condition for storing new data is Enter(or 'receive text buffer with Buffered Receive).
During write time any bit sensed is ignored or lostby blocking the output of the sense amplifier.
'Receive text buffer' or 'enter' and 'buffer
address time' (0-6) condition the 'memory buffer'trigger to accept a data bit from 2B at 'CC2.' The
memory buffer output controls the 'horizontal
driver write gate' line, so the core is either left in
the reset (zero) state when 'memory buffer' is off,or set to a binary one when 'memory buffer' is on.
Without the enter condition, sense amplifier output is gated to 'memory buffer' and the bit is available as lB or 2B input. The same 'buffer address
time' (0-6) (DD021, DD023) that addressed the core,gates its binary value to the appropriate 1B- or 2Bregister position. The bit also controls the 'horizontal driver write gate' line as it did during enter.
Thus, the bit value is regenerated in the addressed
core.
Sense Line Output. The sense signal, a relatively
weak signal,is induced by a core flipping to either
polarity. Signals from other than a resetting core
may also appear on the sense line--for example,
the signal induced by the beginning or end of vertical current (vertical lines run parallel to thesense line), or the signal induced by a core setting
to binary one during write time. An accurate readout requires detection, amplification, and discriminati~

The first sense amplifier stage is basically adetector. The detected signal undergoes voltage
and current amplification by the second stage toincrease it to the strength required by ordinary SLT
logic circuits.
Discrimination between the core-read output
signal and the extraneous sense line signals is amatter of timing. The read condition eliminates
sensing of a core-write sense line signal. The'current control 2' line (Diagram 4-18) comes up
with horizontal current gating and is delayed tomake the active level coincide in time with theswitching of a core. Thus, the output of the sense
amplifier can be accepted only if a core resets from
one to zero at the normal time during enter read.
This output enters Memory Buffer where it represents the binary value that was stored in theaddressed core.
Summary of Buffer Storage Operation• Buffer storage is an intermediate point in overall
2740-2 transmit data flow (Figure 2-1).
• Buffer data control provides input.
• Enter-data flow ends at buffer storage.
• Send-data flow and buffer print data flow begin at
buffer storage.
• The buffer storage addressing and timing circuits
operate the same on enter, receive text buffer,send, and buffer print.
Store
Assume that a new character is to be stored in buffer
storage. At this moment, the cores where the character is to be stored may already contain binary ones,
the buffer address register has not yet advanced, andthe bit counter is at 7. The presence of the new input character in 2B starts the memory clock. The
bit counter steps to 0 and the character addressadvances. Seven read-write sequences ensue, andthe bit counter advances from 0 to 7.
Follow the logic and timing of the enter operationfor one character (Diagram 4-18). The appearanceof a character in 2B-register raises the 'memory go'
signal. The 'read set gate' line comes up and drops
with each bit time, allowing the 'read-write, ' 'VICG, 'and 'HICG' triggers to flip on and off.
Assume that 'buffer address 5' is off. This is aread odd/write odd condition. The' read odd-write
even' line is active in read time and the 'read evenwrite odd' line is active in write time. (When 5 is on,these two lines switch times for the read even/write
even condition.) With the turn-on of 'VICG' (verticalcurrent control gate) for read, vertical current flows
from the selected vertical driver (negative) to theselected vertical switch (positive). 'HICG' (horizontal current control gate) turns on 25 usec later, andhorizontal current flows from the selected horizontal
switch (negative) to the selected horizontal driver(positive). The selected core resets to zero and its
contents are destroyed by not being admitted to'memory buffer'. Instead, a bit value from 2B isgated to 'memory buffer.' Horizontal and verticalread currents end at 'CC2' when the controlling
triggers turn off.
Write time reverses current flow in the selectedvertical line. The selected vertical driver becomes
positive and the vertical switch becomes negative.
Vertical current flows when 'VICG' (vertical current
control gate) turns on for write. Again, 'HICG' turns
on 25 usec later, if 'memory buffer' contains a bit.
Then, the selected horizontal switch is positive, theselected horizontal driver becomes negative, andhorizontal current flows. The coincident current
sets the selected core to binary one. If horizontal
current does not flow (no bit in the 2B position or in'memory buffer'), there is no effectoon the core andit remains at zero. Both currents cease at 'CC2'
when the controlling triggers turn off.
The following 'CC1' flips 'read-write' to 'read'again and the bit counter advances. The read-write
sequence repeats, this time using a different horizontal switch, a different horizontal line, a different core, and a different bit from 2B.
The 'VICG' and 'HICG' triggers do not operate
during buffer address time 7. The bit counter stops
at seven, 'read-write' turns off to 'write', 'memory
go' drops, and the character cycle ends. The input
character is stored.
Readout
A send or buffer print character cycle is similar to
the end character cycle. In this case, however,the cycle starts with the demand to retrieve a character for transmission or for printing. With a notenter condition, the sense amplifier output can gatea binary one from the 'sense' line and set the Ol~einto 'memory buffer.' Input from 2B is inhibited.
'Memory buffer' again controls horizontal current,
and any bit read out is regenerated in the coreduring write.
During a readout operation, buffer storage reads
out the seven-bit character and this character isassembled bit-by-bit in the 1B-register for transmit
or in the 2B-register for a print operation. The
advancing bit counter selects each core sequentially,
and gates the matching register position (Figure2-7). Again, the eighth count ends the character
cycle.
Temperature Compensation (Figure 2-7)
• Temperature compensation regulates arraycurrents.
2740/41 FETOM(4/68)

2-17

The core array enclosure contains a temperaturesensitive resistor called a thermistor that allows
higher array currents when the array is cold; lower
currents when the array is warm. Thermistor output controls the 'TEMP. COMPo V' circuit DDOll
directly, and the I CONTROL circuits indirectly.

Magnetic cores require higher current for switchingwhen they are cold, so low array temperature is offset by. increased array currents. As the switchingactivity and high currents warm the array, the current is reduced. The cores switch more easily as
they warm, thus temperature compensation maintains uniform core switching time. This contributes
to the accuracy and efficiency of buffer storage operation.

Temperature Compensation,..
Buffer Print12B Empty)
Enter 2B Full)
Transmit Text (1B Empty)

1 OR
IMemory Go
rMemor)'Clock

Timing Pulses(Allow clock to run)

7 Horizontal
Drivers

7 Read-Write
Sequences(Fig. 2-4),.

rCurrent
Control
Gates

~

r-1

I--

. r

8 Vertical
I-Switches
49 X 64
I---

I

Core
Sense
Array
(See Fig 2-3)
4 Vertical
t-Drivers

5
Buffer Address
Registert,: Bit
I
I

I

-.,11

Counter

7 Horizontal
SwitchesReadI

12 11 109 8

7 6

II1

1

1 ---

II -

4 1 3 2

t

1

1
- ~W
BA 1, 2, 3
BA4 6

BA 7, 8, 11
BA 9, 10, 12

Heavy lines represent
data routes-..- 2B Register

Buffer Print

*A

.....

~
"'--1+-_ 1B Register

'irA

-

....

MemoryBufferSend

8-

2B Register

lj *A

Enter
-

-

N

*Note: Multiple ANDs; One for each 2740-2 character bit.
Figure 2-7. Buffer Data and Addressing
2-18(4/68)Eh

Sense
Amplifier ~Not Enter

CHAPTER 3.

PRINCIPLES OF OPERATION

2740 COMMUNICATION TERMINAL, MODEL 1
BASIC-TERMINAL MODE CONTROL• All terminal operations are determined by theterminal mode.
• The basic-2740 mode is determined by the condition of mode triggers 'A' and 'B. '• In the basic 2740 there are three modes: (1) 'A'
and 'B' on (control receive mode), (2) 'A' on and'B' off (transmit text mode), and (3) 'A' off and'B' on (receive text mode).
The mode in the basic 2740 is determined by thecondition of two triggers: the 'A' trigger and the 'B'
trigger. When both the 'A' and 'B' triggers are aI].,the 2740 is in control receive mode. While incontrol receive mode, the 2740 can receive any of
the control characters, such as the bid character@' When only the 'A' trigger is on, the 2740 is intransmit text mode. When only the 'B' trigger is on,
the 2740 is in receive text mode. If the 2740 isequipped with some of the special features, many
more modes are possible with the addition of othermode triggers. For this explanation, however, justthe basic 2740 is discussed.
When machine power first comes up in the 2740,
the 'power on reset' line turns both the 'A' and 'B'
mode triggers on, putting the 2740 into control
receive mode (Diagram 5-1).
To send data, the 2740 is placed into transmit
text mode. This is accomplished by turning off the'B' mode trigger. The operator presses the Bid key
to turn on the 'bid' trigger. 'A,' 'B,' and 'bid' bringup the 'B reset gate' line, which turns off the 'B'
mode trigger. An AND connected to the mode-trigger
outputs determines whether the 2740 is in transmit
or in receive mode. If the AND is conditioned by'A' on and 'B' off, the 'send' line comes up. If any
other condition exists, the 'not send' line is active.
'B reset gate' also conditions an OR that turns on
the 'mode change' trigger. Every time a change
in modes occurs, the 'mode change' trigger turns on
to provide a reset to some of the 2740 circuits. The'mode change' trigger then gates itself off with thenext 'CC l' pulse.
When the bid character @ is received at thereceiving terminal, the 'A' trigger turns off, putting
the 2740 in receive text mode. The 'A' trigger isturned off by the conditions: 'status," @ , ' 'B, 'and 'A.' These conditions bring up the 'A reset gate'line.
To stop sending, the sending terminal operator
presses the EOT key. A
is sent and the terminal
goes into control receive mode. The mode changeis accomplished by turning on the 'B' mode trigger.
'Send " '"not operate , ' 'not EOT , ' and 'endof-state' bring up the 'B set gate, ' returning theterminal to control receive mode.
When the 2740 is iIi receive text mode and theend-of-transmission characteris received, the'A' trigger turns on to return the 2740 to control
receive mode. An AND feeding an OR brings up the'A set gate' line, which turns the 'A' trigger on.
This line is brought up by the conditions: 'not send, ''not operate, ' and'If a loss of status occurs
while the terminal is in receive text mode, 'not A'
and 'not status' bring up 'A set gate.' Thus, the2740 returns to control receive mode.
The status of the 2740 is determined by the condition of the 'status' trigger (see Diagram 5-1). As
long as the 'status' trigger is on, the 2740 is capableof receiving or sending data. The 'status' trigger
turns on when (1) paper is in the terminal, (2) the
terminal is in communicate mode, and (3) the data
set has status (power on, able to communicate).
Failure to have any of these conditions turns the'status' trigger off. If, while 'status' is off, a @character is received, an AND--conditioned by'not status, ' 'not Cl, ' 'A, ' 'B, ' and' D '--rings
the alarm bell. 'Status' is also needed to illuminate
the Standby light.

©

,©.

©

© .'

TRANSMIT (POINT-TO-POINT)
The 2740 is capable of sending control and text characters. The control characters are sent when theoperator presses the Bid or EOT keys and text
characters, when any of the print or function keys on
the I/o keyboard are pressed.
A character is loaded into the IB-register in oneof two ways: if the character is a control character,the 'IB generate' line provides input to the IBregister; if the character is a text character, theI/O transmit contacts provide the input. The flowchart (Diagram 5-2) shows the sending sequence.

2740/41 FETOM(4/68)

3-1

• Control characters are developed by bringing up'lB generate. 'the IE-register. 'lB generate' also starts thecontrol clock to provide the 'lB set' pulse. 'lB set'
completes conditioning the ANDs, loading thecharacter (8421C) into the IE-register.

• @ is developed by gating the 'lB3,' 'lB5,' andLoad Text Characters Into 1B-Register

Load Control Characters Into 1B-Register©

, 1B6' triggers.

• © is developed by gating the 'lB3' through 'lB7'• Text characters originate at the I/O transmit contacts.

triggers.
• Control characters are loaded by bringing up'113 set. 'The control character inputs to the 1B-register are
shown in Figure 3-1. To start sending, the operator
presses the Bid key. If (1) the 2740 is in control
receive mode, (2) the Local/Communicate switch isin the COMM position, and (3) the serdes clock is
not running, the 'bid' trigger turns on. The 'bid'
trigger on and the 'send' line up bring up 'lB generate.' 'lB generate' conditions one leg of the ANDs
to the 'lB3, ' 'lB4,' 'lB5, ' 'lB6,' and 'lB7' triggersof the 1B-register. 'lB generate' also gates on thecontrol clock. 'lB set' comes up when both the 'C 1 'and 'C2' outputs of the control clock are active, the'send' line is up, and the 'enter serdes' trigger isoff. 'lB set' completes conditioning the ANDs to the'lB3,' 'lB5,' and 'lB6' triggers. The 'bid' trigger
prevents turning on the 'lB4' and 'lB7' triggers.
Thus, the @ character (821) is loaded into the 1Bregister.
To stop sending, the operator presses the EOT
key to return the sending and receiving terminals
to control receive mode. This is accomplished bygenerating and sending the EOT character ©. Whenthe EOT key is pressed, one leg of an AND to turn on
the EOT trigger is conditioned (see Figure 3-1). The
other conditions are 'send,' 'lB empty, ' 'not 1B
generate,' 'not strobe 0, ' and 'not operate.' These
conditions ensure that:
1. The 2740 is in transmit mode.
2. The IE-register is empty.
3. The Bid key has not been pressed. (The' 1B
generate' input acts as an interlock, preventing
both bid and EOT characters from attempting toload the IE-register at the same time. )4. The I/O device is not presenU)Lgfrin~ihrnllg1L~
cycle.
5. The 2740 is not presently transferring a character through logic.

The 'EOT' trigger coming on causes 'lB generate'
to come up (similar to 2740 sending a bid character).
The '113 generate' conditions one leg of five ANDs to
3-2(4/68)• Text characters are loaded into the 1B-registerby the 'strobe' line.
When the operator presses a key on the I/o keyboard,transmit contacts in the I/O device transfer into the
bit configuration of the desired character. When
gated, these contacts condition the ANDs that load
the desired character into the 1B-register (Figure3-2). As the I/o device goes through its cycle,'C7' (in the I/O device) makes, bringing up the 'strobe
N/O l' line. 'Strobe N/O 1 '--ANDed with 'send, ''not 113 generate, ' and 'lB empty' --turns on the'strobe 0' trigger. 'Strobe 0' gates on the 'strobe'
trigger, which loads the text character into the 1Bregister. The strobe circuit insures that the I/O
device has had enough time to properly transfer thetransmit contacts before gating through them to the
IE-register. The control clock is not started at
this time; the character is loaded into the 113register without need of the control clock outputs.
Transfer Characters from 1B-Register to S-Register• S-register restored by'S register empty. '• 'Enter serdes' transfers the character in the 1Bregister to the S-register.
• 1B reset by the control clock.
Once in the 1B-register, all characters (control
or text) transfer to the S-register in the samemanner. When a character is in the 1B-register,'113 full' comes up. If the'S register empty' trigger
is on and the I/o device is not presently going througha cycle (noted by 'not strobe 0'), the 'enter serdes
gate' turns on (Diagram 5-3). The 'enter serdes
gate' trigger allows the'S register restore' pulse
to occur before a new char acter is loade~register restore' is accomplished by delaying theturning on of the 'enter serdes' trigger. When theprevious character is shifted out of the S-register,the'S register empty' trigger turns on. 'S register
empty' turns on the 'enter serdes gate' trigger and,
ANDed with 'SD1' and 'send', applies the restore
pulse to the S-register. 'Enter serdes gate' and theBid KeyA
B(Not) Clock Run
Communicate

1

Bid
A

~

CC2

-

serd~ ~

Enter

AA301

FF

Send

r-

I
AA131

Power On ResetI(Not) Communicate~~------------~(Not) Transmit Answer Back-------------

B-

I A

_Not8;d

~
AA291

1 B1
(B)

I
I
JI

- 1 B2

(A)

OR

1 B3
(8)

; - AA131

EOT KeySend
1 B Empty
Not Strobe 0(Not) Operate(Not) 1B Generate(Not)Transmit Answer Back

FF--------'---AA111

--,
~A

AA101

OperateS~R~eg~Em~p~ty~______~~
Power On ResetA

I~(Not)@)(Not) B
(Not) (0

LA

AA231

I
----l

ControlClockr--r---To S-Reg

1B4
(4)

EOT
A

r---

Send
(Not) Enter Serdes
C1
C2

r---

1B6
(1 )

r---

1 B7
(C)

r---

AA181
AA191

r----

A

1 B5
(2 )

1 B Set

'----

I ~I

821
8421C

I

AA141

AA071

Figure 3-1. Generate Control Charactersnext 'SDAC' pulse turn the 'enter serdes' trigger onand the'S register empty' trigger off.
'Enter serdes' -- along with 'IB full, ' 'not C2, 'and 'send' -- conditions an AND the output of which,'SO reset, ' is the gating pulse that transfers thecharacter from the IB-register to the S-register.
'SO reset' also goes directly to the 'SO' trigger,
turning it off, which loads the start bit for the character. 'S register empty' ANDed with 'send' hasalready loaded the stop bit. When 'SO' turns off,the control clock starts. The control clock outputs,'CI' and 'C2, ' turn off the 'enter serdes' trigger
and reset the IB-register.
The complete character is now in the S-registerand must be serialized to the 'serial data out' line.
S-Register to 'Serial Data Out' Line (Diagram 5-3)
During sending operations, the serdes clock is continuously running, providing 'SDAC' pulses to theS-register. When the character is received in the
S-register, it immediately begins to shift down

through the S-register, bit-by-bit, to an AND. The
AND is conditioned by 'send.' The output of the AND
is the 'serial data out' line. When the character has
completely shifted down through and out of the Sregister, the'S register empty' trigger turns on,
and the S-register is restored.

End-of-Transmission
When an EOT character is generated and sent, it
causes the sending and receiving terminals to go
into control receive mode. In the sending terminal,
the EOT character is detected when it is in the IBregister. The EOT character brings up the line
The'
line turns on the end-of-state'latch and, after theis transmitted, the 'B' mode
trigger. The 'end-of-state' latch prevents the IBregister from resetting, since the terminal modecannot change until the complete EOT character issent. When the 'B' mode trigger turns on, a modechange occurs. This resets the IB-register.

, © .'©'©

2740/41 FETOM(4/68)3-3

11Strobe rv'0 1
Send(Not) 18 Generate
18 Em to(Integrated
Printer 1)

18-Reg
181
(8)

12
182
(A)

A

13

Vo

Transmit
Contacts

183
(8)
14
15

*Strobe

FF

CC2

q

FF

Power On Reset

Mode Change

To S-Re

185
(2 )
186
(1 )

N
AA10l

16

184
(4)

17
AA201

187
eC)
AA181
AA191

Figure 3-2. Transmit Text Characters

RECEIVE (POINT-TO- POINT)• The 2740 receives either control or text characters.
• Control characters change mode operation.
• Text characters either print or cause a function
to occur.
The 2740 is initially in control receive mode and isable to receive any character into the IB-register.
If the character is anything but a @ character,nothing occurs. If, however, the character is a @ ,the 2740 goes into receive mode. The following
paragraphs explain the receiving operation, startingwith receipt of the @ character, then the text characters, and finally the end-of-transmission character©. The flowchart (Diagram 5- 5) shows the receiving sequence.
Recei ve Bid Character @• Receipt of @ causes 2740 to go into receive mode.
• @is detected in IB-register.

3-4(4/68)

When the 2740 is to receive a message, the sending
terminal sends the bid character @. The @character is received and detected, putting the receiving terminal into receive mode. If any character
other than a @ is received, the terminal remains
in control receive mode.
The first bit to arrive on the communication lineis the start bit. The serdes clock does not run
continuously during receiving operations; therefore,
the start bit starts the serdes clock. The start bit
arrives (on the 'serial data in' line) at an AND conditioned by 'not send' (Diagram 5-6). 'Not send' isup for receive and control receive modes. The start
bit turns off the 'S8' trigger and starts the serdes
clock. (The S-register was previously restored
to all-triggers-on when power was brought up orwhen the mode changed.) The start bit, along with'not send' and 'SO, ' also conditions an AND to turnon the 'enter serdes gate' trigger. The' enter serdes
gate' trigger gates on the 'enter serdes' trigger.
Mter the character received by the S-register istransferred to the IB-register, the 'enter serdes'and 'enter serdes gate' triggers cause the S-registerto be restored.
Meanwhile, the bits arriving on the 'serial data
in' line are gated into 'S8' and from there are shifteddown through the S-register until the start bit reaches
the 'SO' trigger. The 'SO' trigger off (ANDed with'enter serdes' and 'not Cl') starts the control clock.
The sequence of the control clock pulses is 'not Cl'
and 'not C2,' 'Cl' and 'not C2, ' 'Cl' and 'C2, ' and'not Cl' and 'C2.' 'Cl' and 'not C2' reset the lBregister before the character transfers; 'C l' and'C2' provide the 'IB set' pulse to transfer the character from the S-register to the lB-register.
'IB set' is brought up by an AND (Diagram 5-6)-the main conditions of which are 'Cl,' 'C2,' 'S8, 'and 'not SO.' ('S8' and 'not SO' indicate that acomplete character is in the S-register.) 'C2,''not send, ' and 'not 2B set' turn off the 'enter serdes
gate' trigger, bringing up one condition of an AND
to the'S register restore.' The other conditions
are 'not send' and the 'enter serdes' trigger on.
When the 'enter serdes gate' trigger goes off, itconditions an AND to gate off the 'enter serdes' trigger. The time between the turning off of the 'enter
serdes gate' trigger and the turning off of the 'enter
serdes' trigger is'S register restore' time. The
character is now in the lB-register; the S-registerhas been restored and is ready to accept the next
character.
Because this is the first character sent, a @ isin the lB-register. The @ character is detected(Diagram 5-6) and the 2740 goes into receive mode.
The mode change resets the @ from the lB-register.

second time (the first time before the character was
set into the lB-register).
The output of the 2B-register inputs to both theprint-decode and function-decode circuits. At thispoint, the character is checked to see if it is a print
or function character. The appropriate circuit isthen gated by either 'print' or 'non print function. 'To transfer the character to the gated circuit, the'print out' line must come up. When the charactertransferred to the 2B-register, the '2B full' line
came up. '2B full' and 'not I/O cycle' bring up the'print out' line, decoding the character and transferring it to the gated print or function circuit.
Once the character has started the operation of the
I/O device, the 2B-register is reset in preparation
for receipt of the next character. The condition of theI/o device is indicated by the 'I/O cycle' latch. The'lac N/O l' line from the I/O device turns on the 'I/O
cycle' latch. '2B full, ' 'not 2B set, ' 'not 2B resetgate, ' and the 'I/O cycle' latch turn on the '2B reset'
trigger. The '2B reset' trigger output conditions
one leg of an AND to the '2B reset' line (Diagram
5-6) and, with 'I/O cycle, ' provides a gate to turnon the '2B reset gate' trigger. The output completes conditioning the AND, causing 2B to reset.
The '2B reset' trigger turns itself off at the next
'CC2' pulse, but '2B reset gate' stays on until 'I/ocycle' goes down. This prevents unwanted '2B
resets. 'Receive Text Characters

Receive End-of-Transmission Character ©

• Text characters are received up to the lBregister the same as control characters.

• Receipt ofcharacter causes 2740 to go into
control-receive mode.

• Text characters transfer to the 2B-register.

• © character is detected in the lB-register.
At the end of the message, the EaT character © is

• Characters are checked to determine whether
they are function or print characters, and are
gated to the appropriate circuit.
The 2740 is now in receive mode. The @ characterhas been reset from the lB-register and the terminal is ready to receive the first text character. The
first text character arrives on the 'serial data in'line, shifts down through the S-register, and transfers to the lB-register like the @ character. Whenthe character is in the lB-register, the 'IB full line'
comes up. If (1) 2B is empty, (2) the character inlB is a valid character, and (3) 2B is not resetting(main conditions), the '2B set' trigger turns on (Diagram 5-6). '2B set' transfers the character from thelB-register to the 2B-register. '2B set' also starts
the control clock. '2B set' and the 'Cl' and 'C2'
outputs of the control clock reset the lB-register a©

©

received. The
character causes the receiving
2740 to go into control receive mode.
The
character is received exactly like the@ character. When thecharacter is in the lBregister, it is detected (Diagram 5-6), and the terminal goes into control receive mode. The modechange does not occur until the operation of the previously received character is completed (when 'EOS
and not 0' comes up). The mode change brings up'mode change, ' which resets the © character fromthe terminal registers. The terminal is now free tosend or receive data.

©

©

2B Overflow Reset• Detects characters being supplied to printer atexcessive rate.

2740/41 FETOM(4/68)

3-5

• Resets the 2B-register.
• The character in 2B is lost.
Characters can arrive at the 2740 at a faster rate
than the printer can print them. In this error condition, the 2B-register is reset and the character islost. The excessive line rate activates the overflowreset circuit.
'Overflow reset' comes up when characters arein the IB- and 2B-registers (' IB full, ' '2B full ') anda character has shifted,down through the S-registerto the point that the 'SI' trigger is turned off by thestart bit. 'SDl,' 'SD2,' 'SD3, ' and 'not 2B set' and'not 2B reset gate' complete conditioning an AND(Diagram 5-6) to develop the 2B overflow reset.
'2B overflow reset' resets the 2B-register by bringing
up both the '2B reset' and '2B reset gate' triggers,developing '2B reset. 'POWER-ON RESET (2740-1/2741)• The terminal is reset when power comes up.
• Power supply relay (Kl) provides the power-on
reset.
• The terminal is also reset if 'data set ready'drops.
When power comes up, the 2740 goes into control
receive mode. Most triggers and all registers
should be reset. The reset state can be either off
or on, depending upon circuit requirements. The
triggers and registers are reset either directly by
the 'power on reset' line or, following the modechange, by the 'mode change' line.
When the Off-On switch is turned on, ac power isapplied to the dc power supply (Diagram 4-10). At
the same time, ac power is supplied to relay Kl.
The dc power is present some milliseconds before
the pick of Kl is completed. Power-on reset occurs
during this time.
The KI-3 operating point is connected to ground.
The N/C point goes to a converter. As soon as dc
power comes up, the output of the converter brings
up the 'power on reset -X' line ~ conditioning the OR-r<JtIre-tpuwer on reset' Ime. When the pICk of KI IS
completed, the 'power on reset -X' line drops, completing power-on reset.
'Power on reset' also turns on the 'mode change'
trigger, bringing up 'mode change.' Between 'poweron reset' and 'mode change, ' the terminal triggers
and registers reset; the terminal goes into control

3-6(4/68)

receive mode, ready to start sending or receiving.
As shown in Figure 3-3, lack of 'data set ready'causes a power-on reset. If the terminal has thedial-up feature, loss of carrier causes a power-on
reset.

I/O MOTOR CONTROL (2740-1/2741)• In communicate mode, the I/o motor runs only
when the terminal can send or receive text characters.
• The I/O motor runs continuously in local mode.
In control-receive mode, the terminal must be readyto receive information without operator assistance.
In this mode, the I/O device can be inactive forseveral hours at a time. The I/o motor should not
run during these standby periods because of the unnecessary heat and wear. The circuit shown in
Diagram 4-10 controls the motor contactor and provides for the several conditions under which the I/O
motor mUl3t turn on. If any of the input conditions to
the OR are met, the I/O motor turns on. The conditions to run the I/o motor (for the basic terminal)are:
1. 'Not comm'--runs motor when the terminal is

in local mode.
2. 'Not A' or 'not B'-- runs motor when the terminal is in any mode but control-receive.
3. 'Initial lowercase' and 'I/o cycle'--allow theI/O device to be shifted if, when first turned on,
it is in uppercase. ('I/O cycle' acts as an overlap to keep the motor running until the shift iscomplete. )KEYBOARD LOCK (2740-1/2741)• Locks keyboard to prevent unintentional pressingof keys.
• Locks keyboard during carrier-return, tab, receive mode, control-character generation, andfor one second at beginning of transmit mode.
The keyboard-lock circuit prevents operation of the
I/O keyboard during the times when an error results
if a key is unintentionally pressed. These times are:
1. When a long function (carrier-return or tab
operation) occurs.
2. When the terminal first goes into transmit
mode. A I-second delay prevents operation

of the keyboard until the motor comes up to
speed.
3. When the terminal is in receive mode.
4. When a control character is generated.
5. When the line adapter cannot accept data.
The logic needed to generate keyboard lock during
these conditions is shown in Diagram 4-10. The keyboard is locked for a carrier return or tab by the'long function' line. This line inputs to 'OR 1. ''OR l' can also be conditioned by the output of anAND. One condition to the AND is the 'not local'
line. 'Not local' holds the AND deconditioned when
the terminal is in local mode, thus holding the keyboard unlocked. The other leg of the AND is from'OR 2.' 'OR 2' can be conditioned by the output fromthe 'time-out l' latch, 'lB generate, ' , © " or'not send.' The 'time-out l' latch inserts a I-second
delay before unlocking the keyboard when the terminal goes into transmit mode. When the 'B' trigger goes off, an AND is conditioned to the input ofa I-second delay. The output of the delay goes toan AND that turns on the 'time-out l' latch. One
second after the 'B mode' trigger turns off, the'time-out l' latch turns on. During this one second,
the keyboard remains locked.
Whenever a control character is to be sent, the'lB generate' line comes up. During this time, thekeyboard remains locked. If the control characteris athe keyboard must be locked until the terminal returns to control receive mode. 'lB generate'and ' © ' immediately lock the keyboard and keep
it locked until the mode change is completed.
When the terminal is in receive mode, the keyboard is held locked by the 'not send' line.
If the line adapter (data set or modem) cannot
accept data, the 'not clear to send' line keeps the
keyboard locked.

©,

INITIAL LOWERCASE (2740-1/2741)• Causes the I/o device to shift to lowercase, whenin control-receive mode.
This circuit insures that the I/o device begins each
operation in lowercase. The I/O shift mechanism
is designed for both manual and electrical operation.
Either the keyboard shift-lock or the latching of theshift magnets can lock the I/o device in uppercase.
The initial lowercase circuit will shift the I/O device
to lowercase for either condition.

The keyboard shift-trip mechanism in the I/O
device is operated by the logic shown in Diagram
4-10. When an uppercase condition exists duringcontrol receive mode and communicate, the 'initiallowercase' flip latch turns on and conditions theshift-trip magnet driver. The shift-trip magnet
moves the keyboard shift-lock pawl from its keeper.
During the shift-down operation, the flip latch holds
the pulse on the magnet until the I/O device returns
to lowercase. When it does, the 'UC1' signal deconditions the flip latch and the pulse is removed
from the magnet.
If the I/O device is latched in uppercase by theshift-magnet armature latch, the above operation
does not restore the I/o device to lowercase. The
I/o device must be shifted to lowercase by pulsing
the shift magnet. 'Initial lowercase' inputs to an OR
to the shift-magnet driver. With 'initial lowercase'conditioned, the shift-magnet driver is conditioned
and the lowercase magnet is picked.

INCORRECT CASE (2740-1/2741)• If the I/o device is in the same shift as the re-ceived shift character, 'incorrect case' comes up.
• 'Incorrect case' causes a hyphen to be printed.
When the sending terminal sends an uppercase or
lowercase shift character, the receiving terminal
shifts into the desired case. However, the terminal
may already be in the desired case. If this occurs,
the previously sent characters might have been printed
in the wrong case. The operator must be notified ofan error. Figure 3-3 shows the circuit used toindicate this error.
When the shift character is in the 2B-register,
the condition of the case contacts, located in the I/O
device, is sampled. If the I/O device is in uppercase
and receives an uppercase character, the 'incorrectcase' line comes up. The same thing occurs if the
I/O device is in lowercase and receives a lowercase
character. 'Incorrect case' causes the T1 and R5
magnet drivers to be activated, printing a hyphen,which indicates to the operator that an error has
occurred. The 'incorrect case' line also degates
the ANDs to the shift magnet driver to prevent a
shift attempt.
If the terminal is equipped with the recordchecking feature, 'incorrect case' also turns on the'error' trigger. When the receiving terminal performs an EOB-check, the condition of the 'error'
trigger informs the sending terminal of the error.

2740/41 FETOM(4/68)3-7

(N ot ) 28)(Not) 282
283
284
285
(Not) 286-1 8it(Not) I/O Cycle
Upper Case)

r---

A

-

281
282
283
284
285
(Not) 286-) 8it(Not) I/O Cycle
Lower Case 1-

To R5 MD
(AA241)~ Incorrect Case

~~

r----

(AA241)

~~

r-

AA091

To T1 MD

~S

Upper
Case
Shift

Checking Feature~A(Turn On Error Trigger)(8802)

Receive Text

AA091

8802)
A

----

I--

Lower
Case
Shift

AA091

Figure 3-3. Incorrect Case

2741 COMMUNICATION TERMINAL• Basic 2741 sending and receiving circuits are thesame as in the 2740-1.
• Control-· receive mode with the Local/Communicate
switch at COMM causes the terminal to go intotransmit· text mode and to send a @ .
• Pressing either the Carrier-Return or Attention
key causes the terminal to send a © and to go
into receive· control mode.

©

• In receive control mode, receipt of aputs theterminal into control- receive mode; receipt of a
@ puts the terminal into receive· text mode.
The 2741 Communication Terminal is designed to be
used only with a computer. The terminal operates
point-to-point with the computer multiplexer.
The 2741 keyboard does not use the same control
keys as the 2740. The only difference between the2741 keyboard and a standard SELECTRIC@keyboard
is the Attention key, which replaces the Index key.
The standard character code used by the 2741 iscorrespondence code, although BCD code is available.
The basic 2741 sending and receiving circuits are
identical to those of the 2740 except for the @ andcontrol characters. As in the 2740, operations
are controlled by the terminal modes: controlreceive, transmit-text, receive-text, and receivecontrol.

©

3-8(4/68)

Operation starts when the terminal is turned on.
(Diagram 5- 8). As in the 2740, a power-on reset
places the 2741 into control receive mode. When theterminal is in control receive mode with 'communicate, ' not 'initial lower case, ' and not 'operate, 'the 'bid' trigger turns on, loading a @ into 1B andplacing the terminal into transmit text mode. The© is sent to the multiplexer and informs the multiplexer that the terminal is on-line and in transmit
text mode. The 2741 operator can send data until hepresses the Attention key or the Carrier-Return key.
is then sent to the multiplexer, and the terAminal goes into receive control mode.
In receive control mode, the terminal can receive
ei ther a @ or a ©. If a @ is received, the terminal goes into receive text mode, and the multiplexer
sends its message. If a © is received, the terminal
first goes into control receive mode, loading a @into 1B; and then to transmit-text mode, sending the@. The operator can now send a message. Mter
sending a © ' the terminal goes into receive
control mode.
The primary objective of the following operation
is to recognize the control character and then tochange the terminal mode.
When (1) the terminal is in control receive mode,(2) the terminal is shifted to lowercase, (3) nooperation is taking place, and (4) the Local/
Communicate switch is at COMM, the 'bid' trigger©

turns on (Diagram 5- 9) . The 'bid' trigger operates
exactly as in the 2740 terminal, bringing up 'IB
generate, ' which loads a @ character into the lBregister. The 'B reset gate' comes up to place theterminal into transmit text mode and to send the @A message can now be sent in exactly the same manner as with the 2740.
When the operator presses the Carrier-Return or
the Attention key, the 'EOT' trigger turns on. If theoperator presses the Attention key, 'Attn I' (Attention key N/O contacts) and the other conditions to'AND I' turn on the 'EOT' trigger. If the operator
presses the Carrier-Return key, the carrier-return
character is loaded into the lB-register in the normalmanner. The carr:ier-return code is recognized by'AND 2' and (with 'send, ' 'enter serdes, ' and 'Cl')
turns on the 'auto EOT' trigger. 'Auto EOT' and'not operate' turn on the EOT trigger when the carrier
return is completed. The 'EOT' trigger operates
exactly as in the 2740, bringing up 'lB generate, 'which loads a © into the lB-register.
Because the Shift key is not interlock€d with anyother key, the Carrier-Return key and the Shift key
can be pressed at the same time. This causes the
IB-register to be loaded with an error character.

To ensure that the carrier-return character isgenerated and sent properly, the 'CRt latch turns onwhen the carrier-return contact (C6 N/O) makes.
The 'CR' latch prevents the loading of bits into IBregister positions lB2 and lB5. When 'IB generate'
comes up to load thecharacter into IB, the 'CRt
latch turns off. The © is detected and brings up 'A
reset gate' (placing the terminal in receive-controlmode), and turns off the 'auto EOT' trigger.
In receive control mode, the terminal can receive
either a @ or a © character. If a © is received,
the A and B set gates are brought up by 'not send, ''not operate, ' and ' © , ' putting the terminal into
control receive mode. A @ is loaded into lB, andthe mode changes to transmit text. The @ is thensent.
If a @ is received, the terminal goes into receive
text mode. The 'B set gate' is brought up by 'notsend, ' 'not B, ' and 'The multiplexer thensends its message and, when the message is completed, send~ a ©. If the Communicate/Local
switch is turned to LOCAL during any mode, theterminal returns to control receive mode by bringing up the \A and B set' gates.

©

© .,

2740/41 FETOM(4/68)

3-9

2740 COMMUNICATION TERMINAL, MODEL 2
TERMINAL MODE OPERATIONENTER (2740-2)• All terminal operations are controlled by the terminal mode.

• The terminal does not have status (status inhibit)
during enter.

• Station control is standard on 2740-2.

• Enter may be initiated in either local or communicate.

• The terminal mode is determined by the conditionsof the 'A, ' 'B, ' 'E, I and 'F' triggers.

• Enter is established when the Enter key is pressedor (in Local) when buffer print ends.

• The terminal modes are the same as those for2740-1 with Station Control.

• Enter unlocks the keyboard in communicate.

Many of the circuits in the 2740-2 are the same as
those used in the 2740-1 and its features. Therefore
2740-2 circuit explanations will be given only for
those circuits that are:
1. Used differently from the 2740-1.
2. In addition to those of 2740-1.
3. Require special emphasis or review.
For the explanation of station control (standard on
2740-2), refer to "Station Control", Section 5 ofChapter 4.
Control Unit
• Contains the logic circuits, power supply, and theelectronic buffer.

®

• Transmits aanswerback character to thecentral processor when a station is polled andhas nothing to send.
• Transmits @ followed by text if a bid has been
made for the line and the station is polled by theprocessor.

• Enter ends when the Bid key or the Reset key ispressed.
• While in enter, the backspace key will backbuffer address one character position.
The purpose of the enter operation is to store amessage that will be sent to the central computer
location. Enter uses the I/O printer, the 2B register, buffer storage, and controlling circuits. Threedefinite phases of enter occur:
1. The initiation of enter starts with the pressingof the Enter key or the end of off-line buffer
print and ends with the Enter indicator comes on.
2. Message is stored character-by-character.
3. The end of enter starts when the Bid key or the
Reset key is pressed and ends when the Enter
indicator goes off.
The following text describes the enter operation
by sequence: start enter, enter characters, andend enter.
Start Enter• Press Enter key.

• When addressed by the processor, the control
unit responds with anindication if the station
is prepared to receive the processor message.

®

• If the station is not ready when addressed by theprocessor, the control unit responds with asets the attention indicator, and sounds the
audible alarm.

®'• When the terminal has finished receiving themessage, it will transmit either aorindication to the processor if record checking isinstalled.

®

3-10

(4/68)®

• Reset buffer storage address.
• Shift printer to lower case if in upper case.
• Turn on 'enter' trigger and Enter light.
• Turn off standby indicator and drop 'status. '• Start printer motor and unlock printer keyboards(communicate) .
The two ways to start enter are: (1) press the Enter
key to begin storing a message; (2) automatically atthe end of off-line (local) buffer print allow the operator to continue entering. To begin, press theEnter key if the Reset indicator is not on (if it ison, press the Reset key). This action brings up
the'Enter l'line (Diagram 5-30). 'Enter l'resets thebuffer storage address and downshifts the I/O printerif it is in upper case. The 'ILC' (initial lower case)latch starts the motor, downshifts the printer, andturns off when the printer is in lower case. 'Lowercase' and 'buffer address empty' are the main conditions needed for 'enter l' to turn on the' enter' trigger.
The 'enter' trigger will condition all the controlling circuits that transfer character codes fromthe I/o printer transmitting contacts to the 2Bregister and into buffer storage. The 'enter' trigger
inhibits status (Diagram 5-30), which allows theprinter motor to continue running, and unlocks the
keyboard. The Enter light comes on, the Standby
light goes off.
Enter Characters• Keyed action on I/o printer transfers the printertransmit contacts.
• Character code is set into the 2B-register throughtransferred printer transmit contacts.

• Backspace operation backs the character address
one position and inhibits memory timing.
Circuit operation for storing a character is identicalfor every character that is stored. The printercycles whenever a print character or a function is
keyed. This cycle not only operates the transmit
contacts, which provide circuits for each bit of thecharacter code (Diagram 5-30), but also operates
cycle timing contacts, which provide circuits for'strobe' and 'I/O cycle' timing. The circuits forcharacter bits enter terminal logic as I lines. Printertimings enter terminal logic as 'I/o cycle N/C, ''I/O cycle N/O,' 'strobe N/C, ' and 'strobe N/O. 'Load 2B from I/O:
1. Print or function is keyed.

/

2. Terminal 'strobe' sets the character bits into
the 2B-register.
3. '2B full' and 'I/O cycle' turn on the '2B reset' trigger, which turns on the '2B reset gate' trigger.
2B latches not held on by input from the I lines
are reset by '2B reset.' The '2BR' trigger turns
off when 'I/O cycle' ends. 2B now contains thebits that represent the keyed character.
4. The 'memory go' line comes up, but memory
timing cannot start until the 'strobe' line drops.
Store Character into Buffer from 2B (Diagram 5-30)• '2B reset' clears 2B latches that are not forced on.
• 'Strobe' and 'I/o cycle' timings control the set
and reset of 2B, and delay the start of memory
timing until the character is in 2B.
• '2B full' starts memory timing in enter.
• Memory timing runs for eight bit times 'buffer
address time 0-7. '• The character stores from 2B during the firstseven bit times.
• Character parity is checked after storing.
• The 'buffer 2B reset' trigger operates at theeighth bit time.
• 'Buffer 2B reset' resets the 2B-register and drops'2B full. '• Bell rings and enter light blinks 16- 8 characters
before end of buffer.
• Keyboard locks 8 characters before end of buffer.
• Check parity of all characters entering buffer.

1. 'strobe' drops 'memory go' comes up, andmemory timing begins.
2. The bit counter steps from 7 to 0 and the character address advances one.
3. 'Buffer address time 0' sets the B-bit (2B1) into
the 'memory buffer' trigger. The 'buffer odd parity' trigger flips if the B-bit is a binary "one. "4. The B-bit stores at the new character address
and the 'memory buffer' trigger resets.
5. The bit counter steps, and steps 3 and 4 repeat
as follows:
Buffer Address Time 1
Buffer Address Time 2
Buffer Address Time 3
Buffer Address Time 4
Buffer Address Time 5
Buffer Address Time 6

A-bit (2B2)8-bit (2B3)
4-bit (2B4)
2-bit (2B5)
1-bit (2B6)
C-bit (2B7)

6. When the C-bit has been stored, the 'buffer odd
parity' trigger should be on. An error isindicated if it is not on, the bell rings, and the
keyboard locks.
7. In case of an error, press the Reset key toput out the light and unlock the keyboard. Backspace and retype the bad-parity character.
2740/41 FETOM(4/68)

3-11

(Memory timing does not start on a backspace
operation, and nothing is stored.) Even if theerror occurred on a function, such as shift,
backspace is necessary to back up the character
address in buffer storage. Backspace effectively
erases the bad-parity character code because
the next character entered stores in place ofthe bad one at the same address.
8. The 'buffer 2B reset' trigger operates at 'buffer
address time, ' resetting the 'buffer odd parity'
trigger and the 2B-register, and dropping the'memory go' line.
9. Every keyed print operation or printer function
stores its representative character code in thesame manner.
End Enter• Three ways out of enter: (1) automatic 15-second
time-out, (2) press Reset key, (3) press Bid key.
• Reset key resets the buffer storage character
address, the 'enter' trigger, the 'rekey' latch,and reset light.
• Reset key and communicate sets terminal to text
non-selected mode.
• Pressing Bid downshifts the printer and stores
the LC shift character if the printer is in upper
case, stores the stop code (orandresets the 'enter' trigger.

©

® ),

• Stop code stores just like a character code,
except that © or ® is automatically generated
in 2B and the printer does not cycle.
• Bid in local mode does not set the 'bid' trigger.
The 'buffer print' trigger turns on instead.
• 'Bid' and 'buffer address empty' will reset enter,no stop code is stored.
The 'enable enter time-out' latch allows the terminal to return to not enter status after 15 seconds ofinactivity while in enter-communicate mode. 'Poweron reset' resets the 'enable enter time-out' latch andthe timer is inactive until the terminal transmits anaddress answerback or negative answerback to polling.
'Transmit answerback' sets the 'enable enter time out'
latch to activate the time-out circuits for current and/or subsequent enter operations (Diagram 4-13). If
the Enter key is pressed and released in communicate
mode the 15-second time delay is started by 'enable
enter time-out,' 'enter, ' 'communicate, ' '2B empty, ''not enter 1,' 'not line return N/Cl,' and 'not line type
N/C1.' Each time a character is entered through the
3-12(1/69)

2B-register, '2B empty' drops to inhibit the time-out
and to restart the time delay for another possible 15
seconds. The time-out is also inhibited by 'enter 1, ''line return N/Cl, ' or 'line type N/Cl' each time theEnter, Line Return, or Line Type key is pressed.
(The Line Type and Line Return keys are not present
on machines without the Edit feature. )When the 15-second time-out occurs, '15 sec'
'not 1 cycle halt' and the condition which started thetime delay are ANDed to set the 'time-out 15' latch.
'Time-out 15' and 'enable enter time--out' bring up a
special 'reset N/O' line to reset the buffer, 'enter'trigger, and 'rekey' latch (if set). The Reset light(if on) is turned off when the terminal returns to
not enter status.
Pressing the Reset key resets the buffer address(unless a character is still being entered) and thenturns off the 'enter' trigger.
When the Bid key is pressed, conditions must be
set up either to print out the stored message (local
buffer print) or to send the stored message (communicate). The preparations for printout and for transmit
are nearly identical (Diagrams 5-33 and 5-36).
The Bid key brings up the 'bid I' line. 'Bid I'
downshifts the printer (if it is in upper case). If
the printer shifts, the LC shift code stores in thesame manner as any other character code (see"Enter Characters"). As soon as the printer is inlower case, the 'store stop code' trigger operates togenerate the stop code ( © or ® ) in the 2B-register.
'Memory go' rises immediately and is held up by'2B full' and 'enter.' The stop code enters buffer
storage as the bit counter steps through 'buffer address time 0' through 6. At 'buffer address time 7, 'the stop code in 2B turns off the 'enter' trigger andoperates the 'buffer 2B reset' trigger to reset the
2B-register and the 'buffer odd parity' trigger. With'2B empty' and 'enter' off, 'memory go' drops, theEnter indicator goes out, and the enter operation iscomplete.
The following sequence summarizes the eventsat the end of enter:
1. Press Bid key.
2. Printer downshifts and LC shift code stores if
printer is in upper case.
3. Stop code ( © oris generated in 2B andstored in buffer storage.
4. The 'enter' trigger resets and the Enter inditor goes out.

®)

NOTE: If no message is stored (buffer address empty) andthe bid key is pressed with the Enter indicator on, no stop
code is stored, and 'enter' ends with no further action.
The 'enter' trigger resets and the Enter indicator goes out.

End Enter to Transmit

Transmit Text Characters

The 'bid' trigger sets to provide for the transition
from enter to transmit (Diagram 5-30). Gated by
the decoded stop code, 'buffer addres s time 7,' 'read'and 'enter, ' the 'CC2' pulse turns on the 'bid' trigger
and turns off the 'enter' trigger. 'Status' comes up(is no longer inhibited), the keyboard locks, and the
motor stops. The 'bid' trigger stays on until thefirst transmission character enters the S-register,and indicates that the terminal has a message to send.

Once in the IB-register, all characters, whether
generated or from buffer storage, are transmitted
in the same manner as the 2740-1. The buffer circuits are activated for read out by 'transmit text'
and'IB empty (Diagram 4-18).

End Enter to Buffer Print

Transmit © or®

Each character is transmitted until the stop codecharacter,oris detected in the IB-register.
This character turns on the 'end of state' trigger.
'End of state' prevents a 'IB reset' until a modechange occurs. The transmission of thewill
return the terminal to the control receive mode.
The ® will place the terminal in the transmit LRC
mode (record checking).

©

®'

©

Buffer print occurs in Local mode when the Bid key
is pressed. 'Local' holds the 'bid' trigger off, butallows the 'buffer print' trigger to turn on at 'buffer
address time 6' of the stop code. 'Status' is still
inhibited and the motor continues to run, but the keyboard locks for buffer print. The buffer print operation begins immediately (see "Buffer Print").

RECEIVE (2740-2)

TRANSMIT (2740- 2)• The 2740-2 receives either control or text characters.

• A @ is generated and transmitted as the firstmessage character.
• The contents of buffer storage are transferred, acharacter at a time, to the IB-register.
• Each character is parity checked as it is read outof buffer.
• The character in IB is transferred to the Sregister and serialized to the transmission line.
• The final character from memory is a

© or ® .

• With Record Check installed, ® is followed byan LRC character which is generated by the LRC
register.
This section explains the operation of the terminal
after it has been successfully polled. The procedure
for polling the terminal and placing it in transmit
text mode is explained under "Station Control"
Chapter 4, Section 5.
Generate and Transmit @The first character that the terminal sends to thecentral processor ( @ ) does not come from buffer
storage, but is generated and loaded directly into
the IB-register (the same as 2740-1). Operation of
buffer storage is prevented until after transmissionof this character.

• Control characters change mode operation .
• Text characters either print or cause a function
to occur.
• Receive in the 2740-2 is identical to the 2740-1
receive with Station Control (Diagram 5-6).

BUFFER PRINT (2740-2)• The terminal does not have status (status inhibit)
during buffer print.
• Buffer print is initiated manually by pressing theBid key while in Local-Enter mode.
• Buffer print ends when the stop code at the endof the stored message is reached.
• The end of buffer print, local, automatically sets
the terminal back to enter.
• Buffer print communicate takes place only onterminals with the Buffered Receive feature, but
is explained here because it is similar to Local
buffer print.
The purpose of the buffer print operation is to printout the contents of buffer storage.

2740/41 FETOM(1/69)

3-13

The buffer print operation has three phases:

Buffer Print Operation

1. The transition into buffer print--from local
enter or from receive text buffer on terminals
with the Buffered Receive feature.
2. The buffer print operation, during which the I/O
printer prints the characters and performs thefunctions.
3. The transition out of buffer print--to enter, if
in Local mode or to the Standby condition (TNSor CR) from buffer print, communicate, on terminals with the Buffered Receive feature.

• Reads out character codes from buffer.

Start Buffer Print• Pressing the Bid key (local) places the printer inlower case and stores the shift character (ifnecessary) and then generates the © or @stop
code in 2B.
• Stop code turns on 'buffer print' and turns off'enter. '• Buffer Address resets as 'buffer print' sets.
• Buffer print (Communicate) takes place on terminals with the Buffered Receive feature andbegins when © is received.
Buffer print, local or communicate mode, begins
when a stop code is decoded in the 2B-register. The
generated © orstop code starts local buffer
print; the received
stop code starts communicate
buffer print.

®
©

Transition to Buffer Print from Receive Text Buffer(Buffered Receive)®

A receive text buffer message may end with aand LRC if Record Check is installed. This control
character does not store nor does it cause the stored
message to print out. Printout begins only when the© is received and stored. The © control character turns on the 'set buffer print' latch and decodes
as a stop code in the 2B-register. The memory
timings used to store the © allow the 'set buffer
print' latch to turn on the 'buffer print' trigger andreset the buffer address. The 2B...;register resets
and the 'memory go' line comes up. The 'buffer
prmt' or 'enter' lIne comes up and the standby
indicator goe s out. The keyboard remains locked,
but 'status inhibit' comes up and the I/o printermotor starts (Diagram 5-36).

3-14(4/68)• Memory timing times readout of the seven bitsthat make up each character code.

• I/o cycle times 'memory go' and '2B reset. '• Character code parity is checked on readout.
The transition to buffer print ends with the 'buffer
print' trigger on and the 'memory go' line up. Buffer
storage timing starts as soon as the buffer address
is reset. The sense amplifier sets a binary one froma core into the 'memory buffer' trigger, andcharacter-bits begin to set into the 2B-register.
As each binary one sets into the 'memory buffer'trigger during buffer print, the 'buffer odd parity'
trigger flips (Diagram 4-18). Each character code
contains an odd count so the 'buffer odd parity'
trigger should be on when the character code has
been completely read out at the end of 'buffer address
time 6.' If not, the 'rekey' latch turns on, the bellrings, and the Reset indicator comes on. There is
no assurance of what will print for the error character. The 'buffer odd parity' trigger resets to its
initial off condition when the 2B-register resets.
An "incorrect case" in the stored message inhibits
the shift function and prints a hyphen (-) in its place(Diagram 5-36).
At 'buffer address time 7', the '2B full' line comesup and the character code in 2B is decoded for tiltand-rotate or function input to the I/O printer.
'Memory go' drops and the printer starts a cycle.
The 'I/o cycle' timing signifies that the printer has
begun its cycle and no longer needs the decoded output of the 2B-register. The '2B reset' trigger turns
on, followed by the '2B res~t gate' trigger and 2B
resets. The '2B reset' trigger turns off, but '2B
reset gate' stays on until the 'I/o cycle' line drops.
This prevents repetitive reset of the 2B-register,and allows it to be used again immediately.
The 'memory go' line comes up again after 2B
resets, and memory timing starts again. The next
character code reads out to the 2B-register. The'2B full' line comes up again and 'memory go' drops,
with a new character code in 2B (even though theprinter has just begun to print or perform the functIOn dema:rute--a--byttrepr-evwas---cna-r-a:cter code ).
NOTE: It takes only about 2 0 of the printer cycle to read acharacter code out of buffer storage.

The 2B reset circuits cannot operate again until
the 'I/O cycle' line drops and comes up again so theunprinted character waits in 2B. When the 'I/O
cycle' line drops, the new character is decoded fortilt-and-rotate or function and the printer continues
from one cycle directly into the next. The 'I/O
cycle' line rises; 2B resets; 'memory go' comes up;
the readout-and-print repeats for the next character.
Printout continues, character-by-character,until a stop code appears (or © in 2B, or
end-of-memory in the address register). The stop
code initiates the transition out of buffer print.

®

End Buffer Print• Turn off 'buffer print' trigger.
• In local buffer print, return to enter and reverse
buffer address one character (the stop code iseffectively erased).
• In communicate buffer print, reset buffer
address and turn on the Standby indicator.
The decode of a stop code in the 2B-register at theend of 'buffer address time 6, ' turns off the 'buffer
print' trigger and the 'buffer print' line drops.
Transition from Buffer Print to Enter (Local,
Diagram 5-36)
This transition returns terminal logic to enter. The
stored stop code is automatically erased by backing
up the buffer storage character address. When thestop code'is complete in 2B, the next' CC1' (startof write, 'buffer address time 6') turns on the 'edit
control 3' trigger (Diagram 4-16). The 'buffer
print' trigger turns off at the end of 'buffer address
time 6' and the 'rev ctg seq' (reverse counting
sequence) trigger turns on at the next' CC2' (thesame 'CC2' that turns on 'buffer 2B reset' to reset
the stop code in 2B). 'Rev ctg seq' turns on'reverse counter sequence control' at 'CC1' time tofurnish the 'bfr. cntr. ac input' and back up theaddress. 'Rev ctg seq' turns itself off and thebuffer storage address backs up one character
location. Thus, the next character stored obliterates the stored stop code.
After the 'buffer print' trigger is turned off andthe printer is in lower case, the next' CC2' willturn on the 'enter' trigger. The 'edit control 3'
trigger is on momentarily, and turns off at 'CC1'
after 'enter' is turned on.
The keyboard unlocks, the I/O printer motor continues to run, and the Enter indicator comes on.
The terminal is back in enter, with the only carry-over from buffer print being the possibility that an
LC shift code was automatically stored and theprinter downshifted immediately before the stop
code. Upper case entry can be continued by simply
shifting the printer from the keyboard.
Transition from Buffer Print to standby (Buffered
Receive Feature)
This transition returns the terminal logic to standby
status and resets the buffer storage address. The
resetting of the 'buffer print' trigger drops the'status inhibit' line, the motor stops, and theStandby indicator comes on (if TNS or CR mode).
The keyboard remains locked. The terminal logic
can be manually switched to Local only after buffer
print has ended (Diagram 5-9).
INITIAL LOWERCASE (2740-2)• Causes the I/o printer to shift to lower caseprior to entering, sending, or receiving.
This circuit insures that the I/o printer begins
entering, sending, or receiving in lower case, sothat the central processor can know what case theI/o printer is in at the beginning of a sending or
receiving operation. The I/O printer is placed inlower case at the beginning of enter for operator
convenience.
The I/O shift mechanism is designed for bothmanual and electrical operation. Either the keyboard shift-lock or the latching of the shift magnets
can lock the I/o printer in upper case. The initiallower case circuit will shift the I/o printer to lower
case for either condition
The keyboard shift-trip mechanism in the I/oprinter is operated (Diagram 4-10) when an upper
case condition exists:
1. At the beginning of enter;
2. At the end of enter (before transmission begins);
3. While the terminal is in control receive or text
non-selected mode; or
4. When the terminal is addressed, but before
receive text mode (control address selectedmode),
the 'initial lower case' flip latch turns on and conditions the shift-trip magnet driver. The shift-trip
magnet moves the keyboard shift-lock pawl from its
keeper. During the shiftdown operation, the flip
latch holds the pulse on the magnet until the I/oprinter returns to lower case. When it does, the'UC1' signal deconditions the flip latch and thepulse is removed from the magnet.

2740/41 FETOM(4/68)

3-15

If the I/O printer is latched in upper case by theshift-magnet armature latch, the above operation
does not restore the I/o printer to lower case. The
I/O printer must be shifted to lower case by pulsing
the shift magnet. 'Initial lower case' inputs to an
OR to the shift-magnet driver. With 'initial lower
case' conditioned, the shift-magnet driver is conditioned and the lower case magnet is picked.

INCORRECT CASE (2740-2)• If the terminal is in the same shift as the received

shift-character, 'incorrect case' comes up.
• Incorrect case causes a hyphen to be printed.
When the terminal receives a shift character, it
shifts to the desired case. If already in thatcase, the previously received characters might
have been printed in the wrong case and the operator
must be notified. Diagram 2-2 shows the circuitthat indicates this error.
When the shift character is in the 2B-register,
the condition of the case contacts, located in the
I/O printer, is sampled. If the I/O printer is inupper case and receives an upper case character,the 'incorrect case' line comes up. The same thing
occurs if the I/o printer is in lower case andreceives a lower case character. 'Incorrect case'causes the Tl and R5 magnet drivers to be activated,
printing a hyphen, which indicates to the operator
that an error has occurred. The 'incorrect case'line also degates the ANDs to the shift magnet
driver to prevent a shift attempt, and turns on the'error' trigger. During transmit check answerback,the 'error' trigger is sampled, causing ato betransmitted to the central processor.

®

KEYBOARD LOCK (2740-2)• Locks keyboard to prevent unintentional pressingof keys.
The keyboard-lock circuit prevents operation of the
I/O keyboard during the times when an error results
if a key is unintentionally pressed or when it isundesirable to print a character. These times are:

1. When a long function (carrier-return or tab)occurs.
2. During buffer print operations.
3. Eight characters before end-of-memory (entermode).
4. When an error occurs.

3-16(1/69)

5. During ledger card insertion.
6. When the platen is split.
7. During any non-enter condition in communicate.
The logic needed to generate keyboard lock isshown in Diagram 4-10. The keyboard is locked fora carrier return or tab by the 'long function' line.
'Buffer print' locks the keyboard during buffer print
operations. 'Enter' and the buffer address value
shown in Diagram 4-10 lock the keyboard eight char. acters before the end of memory. 'Rekey' locks the
keyboard when an error occurs; the keyboard cannot
be unlocked until the Reset key is pressed. During
ledger card insertion, the keyboard is locked when
the card chute is not closed. This is accomplishedby bringing up the 'insert card, ! 'drive down, ' and'drive up lines.' Any time the platen is split, thekeyboard is locked by 'platen shift.' In communicate,
the only time the I/o keyboard is unlocked is when
the terminal is in enter. 'Not enter' and 'communicate' lock the keyboard at all other times.

I/O MOTOR CONTROL (2740-2)• In communciate mode, the I/O motor runs only
when the terminal can send or receive text characters.
• The I/o motor runs continually in local mode.
In text non-selected and control receive modes, theterminal must be ready to receive information without operator assistance. In this mode, the I/oprinter can be inactive for several hours at a time.
The I/o motor should not run during these standby
periods because of the unnecessary heat and wear.
The circuit shown in Diagram 4-10 controls the
motor contactor and provides for the conditions
under which the I/o motor must turn on. If any of
the input conditions to the ORs are met, the I/O
motor turns on. The I/o motor runs for the following conditions:
1. For initial lower case operations.
2. When the terminal is in local mode (off-line).
3. When the terminal is in receive text mode.
4. For enter and buffer print operations (status
inhibit).
5. During a long function (carrier return, tab).
6. To complete an I/o cycle.
7. Control selected, transmit status answerback,and control selected modes--to get motor up to
speed before going to receive text mode.

• When error or buffer busy conditions exist, theCPU is notified by a qualified Q? sent by a terminal with receive status and a qualified
sent
by a terminal without receive status.

8. Transmit check answerback mode--to carry
motor over to receive text mode.
9. During ledger card insertion.
10. Receive check answerback mode.
11. Transmit text mode.

®

• A "no error" condition is indicated by a space,
QJ answerback.
LINE PARITY ERROR (2740-2)• Light indicates transmit or receive parity error0• All error latches are reset when the qualified
G.? response is sent by the terminal.

• A Line parity error does not alter terminal
operation.

• Error latches are not reset when a qualified
is sent.

• Parity-Reset latch (light) must be reset byparity-reset switch.

Electronic Error Latch

The purpose of the Parity light is to indicate that theterminal has detected a receive or transmit parity
error. The light and associated switch are operativewith or without the Record Checking feature.
In transmit mode 'SD3', 'not S-register empty'
and 'serial data out' bring up 'Xmit parity AC set'
and fli p the 'Xmit odd parity' trigger(Diagram 2-2).
If this trigger is not on at the end of a trans mitted
character, the' parity error' latch will turn on.
During a receive text operation, several conditions may set the 'parity error or not S8' latch(Diagram 2-2). The latch output, 'not L' and'receive text' sets the' parity error' latch.
The' parity error' latch and the Parity light will
stay on until reset by operating the Parity-Resetswitch. The latch being on does not alter theterminal operation.

®

The parity of characters going into and out of buffer
are checked by the 'buffer odd parity' latch. If thelatch is not on at 'buffer address time 6,' 'verticalcurrent control gate,' and 'write' bring up the'buffer VRC' line. 'Buffer VRC' and 'receive text'
set the 'error' latch (Diagram 2-2). 'Buffer VRC'
is also ANDed with 'receive text' or 'buffer print
and communicate' to set the 'electronic error'
latch. When the error latches are used to set up
the sense character answerback, the electronicerror has highest priority. Electronic errors do
not set the 'electronic error' latch if the Buffered
Recei ve feature is not installed.
I/O Error Latch

The I/O error latch is set when printer errors aredetected, if the terminal is in buffer print andcommunicate mode for terminals with Buffered
Receive feature, or in receive text and not receive
STORAGE LATCHES FOR ERROR RESPONSES
text buffer mode for terminals without Buffered(2740-2)
Receive. Feedback information comes from thetransmit contacts in the I/o printer to control the
I/ocheck register which has a latch for each of• Electronic error latch is set for buffer VRC errors
the
seven
bits. This register and an I/O check enwhen the terminal with Buffered Receive featureable
registerare set by bits in the 2B-register at
is in (1) buffer print and com municate, or (2) reprint
time.
The
two registers make it possible toceive text buffer mode.
check for extra or missing feedback bits during theactual print operation.
• I/O error latch is set when a printer error is deFor Simplicity of explanation let us assume that atected by integrated printer feedback.
numeric "1" is to be printed and the 'I/O check 6
enable' and 'I/o check 6' latches will be used.
• Electronic errors on terminals w"ithout Buffered
These two latches are used to detect a missing bit,
Receive feature cause the I/o error latch to be
but
the other six I/O check latches are needed inset.
order to check for extra bits.
The print cycle is initiated by the character' l'• Receive parity error latch is set when the terminalin the 2B-register and the 'I/O cycle' line comes up.
receives a character (1) with VRC error or (2)The '2B reset' latch is turned on by 'I/O Cycle'
without a stop bit in receive text mode.
at 'CC2' time, and '2B reset' and 'I/o cycle'
bring
up 'set I/o latches' before the 2B-register is• Transmit parity error latch is set when the terminal transmi ts a character with a VRC error.
2740/41 FETOM(1/69)

3-17

reset. 'Set I/o latches' and '2B6' set· 'I/o check
6 enable' and 'I/O check 6. ''Receive text and not receive text buffer' or 'buffer
print and communicate' bring up 'I/o check enable'
to allow the actual checking to be done. 'I/o checkenable' and 'strobe N/O l' set the 'I/O check strobe'
latch which ANDs with 'integrated printer 6-1 bit'and 'I/O check 6 enable' to reset the 'I/o check 6'
latch when printi ng is proper. If the 'integrated
printer 6-1 bit' is missing, the 'I/o check 6' latch
is left on during 'I/o error sample' time to indicate an error. Any extra bit, sensed by an integrated contact output, will set the respective I/ocheck latch. This is done by the integrated printercontact output, 'I/o check strobe' and not 'I/o checkenable' latch (not set by 2B- register). Thus, an
extra bit also leaves an I/o check register latch
set during 'I/O error sample' time.
Reset of the I/o Check and the I/O Check Enableregisters, the 'I/o error sample' and the set ofthe 'I/o error' latch are under the control of the 'I/O
check control l' and I/o check control 2' sequence
started by 'I/o check strobe.' 'I/o check strobe'
allows 'CC1' to set 'I/o check control l' trigger
which stays on until the 'CC1' pulse after 'I/o check
control 2' comes on. After 'I/O check strobe' isreset by 'strobe N/C l' 'I/O check control 2' is set
at 'CC2' time by 'I/o check control l' and 'not I/ocheck strobe.' At this time the strobe operation iscomplete, the I/O check register is set (for errors
only) and 'I/o error sample' is brought up by 'I/ocheck control l' and 'I/o check control 2.' For any
missing or extra bit H/O check register full' and'I/o error sample' set 'I/O error' latch. 'I/o checkenable' and 'not I/o check inhibit' are also necessary
to allow 'I/o error' set.
'Rekey I/o error' is set or inhibited under thesame condition that control the 'I/o error set' as
described above.
If either an'incorrect case' error or a '2B overflow reset' condition has occurred, the error latch
is set. Either of these conditions along with 'I/ocheck enable' will set the 'I/o check inhibit' latch
and inhibit an I/o error condition.
At the end of the I/o check operation, the I/ocheck and I/o check enable registers are reset by'reset I/o latches' brought up by 'I/o check control
2 and not control 1. 'acter is printed. Therefore, the 'I/o error' latch
is set instead of the 'electronic error' latch and theI/o error becomes the highest priority error condition with added significance. When the terminal
with receive status is ~ddressed after an electronic
failure, the positive answerback sense character
indicates that an I/o error has occurred. The importance of and the additional possible cause of such anerror indication should not be overlooked.
If the Buffered Recei ve feature is installed; theI/o error has a priority second to electronic error
when a qualified ® answerback is sent by anaddressed terminal with receive status.
When the 'rekey' latch is set because of an I/oerror, it can be reset only by pressing the Reset key.

Receive Parity Error Latch
The receive parity error latch is set when the terminal receives a character with a VRC error or if
the S8-stop bit is missing. Either of these two conditions sets the 'parity error or not S8' latch (Diagram 2-2). 'Receive text,' 'not L mode latch, 'and'parity error or not S8' set the 'receive parity error'
latch. The same conditions set the 'parity error'
latch which turns on the Parity Error light.
Receive parity error has third priority when aqualified Q? answerback is sent by the terminal.

Transmit Parity Error Latch
The transmit parity error latch is set when acharacter with a VRC error is trans mitted by theterminal. The 'serial data out' is checked by'transmit odd parity' trigger which should be on toindicate proper transmission. If it is not on, 'nottransmit odd parity' and 'not S-register full' set
the 'transmit parity error' latch. This error condition has lowest priority when the 1B-register is
set by 'load 1st character answerback. 'TRANSMIT-STATUS/ANSWERBACK
A terminal with receive status sends a qualified <X> ,two-character answerback, when it is addressed.

~~~~~~INf~t~h~e~B~uffffienI~e~d~R~e~c~e±iv~e~f~efta~~~I~e~is~fl~o~t~i~n~s~~~lUIBBddr,~~~~H~a~n~y~e~rrors~vebeensensedmds~reddur~gthe 'I/O error' latch is set indirectly by an electronicerror as well as an I/o print error. For example,
an electronics failure may cause a printable evenparity character to be set into the 2B-register and,in turn. into the I/O check and I/O check enableregister. A parity difference is sensed, due to the
odd parity of the feedback contacts, when the char3-18(1/69)

the previous communication operation the 'load 1st
character answerback' loads the 1B-register withthe character which represents highest priority error
sensed. 'lB generate' is delayed while this characteris sent, so the <X> will be the second charactertransmitted.

If the terminal has status, all error latches arereset after '1st status character answerback' drops.

Status and Operational Error Conditions
If an addressed terminal is not ready to receive data,a qualified
will be transmitted as the answerback.
Any error conditions stored because of previous
operations will not be affected.
If the addressed terminal is in 'enter and communicate, ' or 'bid' mode, the computer program shouldpoll the terminal before readdressing it. Otherwise
the terminal would continue to send the qualified
as a response and it would not return to receive
status.
When the terminal has bid status, 'bid latch' and'load 1st character answerback' set a 2 bit in the IBregister and the 2,
are sent as the answerback.
When the terminal has enter status in communicate
mode, 'communicate, ' 'enter, ' and 'load 1st character answerback' set a 1 bit in the IB-register and1,
are sent.
If the terminal is addressed while in 'buffer print
and communicate' a 4 bit is set in IB-register to besent as a response to the CPU. The 4 bit is set
into the IB-register by 'buffer print, ' 'communicate, 'and 'load 1 st character answerback. 'If the terminal is out of paper, in local mode, or
has the document insertion device down, the terminal is considered to have an operational error
condition and a qualified
is transmitted to notify
the CPU program. The Attention light comes on
and the alarm sounds. When the terminal regains
status the Attention light goes off. A9,
is sent
for an out-of-paper condition; 8,
for local mode;
and @,
for insertion device down.
When the terminal is out of paper, 'not status
inhibit, ' 'not bid latch, ' 'not paper, ' and 'load 1st
character answerback' set the 1 bit, 8 bit, and C
bit in the IB-register for the sense characteranswerback.
When the terminal is in local mode, the 8 bit isset in IB-register by 'not communicate, ' and 'load
1st character answerback. 'If paper is in the feed and the insert device isdown, an @ is set in IB-register by 'paper,' 'not
bid latch,' 'not status inhibit,' 'insert card,' and'load 1st character answerback. '

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TERMINAL TO LINE-ADAPTER INTERFACE(ALL MODELS)• Line adapters connect terminals to com munication lines.

• The connections between the line adapter andthe terminal form the interface.
Because dc voltage is used by the 2740/2741 terminal,
data cannot be sent directly to another terminal.
The bits making up a character musr be changed toanother form for transmission, by connecting theterminal output to a line adapter. The line adapter
can be either a common-carrier data set or an IBM
modem (modulator-demodulator). The connecting
circuits and lines between the line adapter and theterminal are the interface.
The following paragraphs explain the function of
the interface lines in the 2740/2741 terminals. For
some of the line adapters the descriptions mightvary in use due to the use of half duplex, full duplex,
special features and operation with multiplexers.
Diagram 5-47 shows the interface for all line adapters used with the terminals.
Signal Ground-AB
This line serves as the signal voltage reference
between the line adapter and the terminal.
Transmitted Data (Serial Data Out)-BA
This is the data-out line from the terminal to theline adapter. Data generated in the terminal is sentout on this line.
Received Data (Serial Data In)-BB
This is the data-in line from the line adapter to theterminal. Data received by the terminal arriveson this line.
Data Set Ready- CC
This line from the line adapter indicates to the terminal that the line adapter has power and can communicate.
Request to Send- CA
This line from the terminal tells the line adapterthat the terminal is prepared to send data. In theadapter, this line usually generates the carrier
frequency.
Clear To Send-CB
When the line adapter is in a condition to send data,'clear to send' comes up to allow the terminal to
begin sending.

2740/41 FETOM(1/69)

3-19

Carrier-CF
This line comes up when 'carrier' from the sending
line adapter is received and detected by the receiving line adapter. 'Carrier' coming up allows theterminal to receive data.

'originate' line, normally held up, drops. For fullduplex operation, the 'originate' line is held down,
keeping one set of communication lines in answer
mode and the other in originate mode.
Data Terminal Ready (Used Only for 103A Data
Set)-CD

Originate (Used Only for 103 F Data Set)-CY
This line puts the 103 F data set into answer mode.
For half-duplex operation, data sets on both ends ofthe line are in originate mode. In order to send data,
one of the data sets must be put into answer mode.
The 'originate' line serves this purpose. When'request to send' is brought up in the terminal, the

3-20(lj69)

This line from the terminal to the line adapter controls the operation of the 103A data set. If the line
is up (indicating that the terminal has status and the
Dial-Disconnect key has not been pressed), the dialconnection is maintained; if the line drops, a dial
disconnect begins.

CHAPTER 4.

FEATURESSECTION 1. RECORD-CHECKING (2740-1/2740-2)
INTRODUCTION

however, and no LRC-error can be recognized until
an end-of-block check is made.

• Data is checked vertically and longitudinally.
End-of-Block (EOB) Check (2740-1)• Parity errors (VRC) are indicated by a hyphen
printed at the receiving terminal.
• Sending terminal starts the EOB-check.
• Response to EOB-check indicates accuracy ofreception.
Record-checking is a method whereby the great
majority of sending and receiving errors are detected. Each character received is checked vertically for odd parity (vertical redundancy check); theentire message is checked longitudinally by maintaining an odd-even count of each bit position as thecharacters are sent and received (longitudinal redundancy check). This latter count (LRC) is maintained at each terminal. The receiving terminal's
response to periodic sending-terminal inquiries
indicates the accuracy of data received.
Vertical Redundancy Check (VRC)
VRC uses the odd-bit count of each character received to test the accuracy of received data. If the
bit count of a character is even, the gain or loss ofa bit is indicated; a hyphen is printed at the receiving
terminal to alert the operator of an error. Also,an error trigger within the terminal turns on tolater advise the sending terminal (or central processor) of an error.
Longitudinal Redundancy Check (LRC)
LRC uses an odd-even count of bits in each bit position to develop a 7 -bit LRC-character. This character is developed in the sending terminal duringtransmission. The receiving terminal (or central
processor) also develops an LRC -character at thesame time.
The presence of a bit within the LRC-character
indicates that an odd number of bits has been sentin that position; the absence of a bit indicates aneven number of bits has been sent. Because thesame data generates the LRC-character at bothterminals, the characters should be identical. No
comparison between the LRC-characters is made,During the sending operation, the sending terminal
receives no indication of errors. Periodically, thesending terminal operator checks the receiving terminal (or central processor) for accuracy of reception by pressing the EOB key on the I/o keyboard.
This automatically compares the LRC-charactersdeveloped at each location and checks the 'error'
trigger at the receiving location. Any terminal
error is then indicated at the sending terminal byprinting a hyphen, ringing the alarm bell, and locking
the terminal.
Operation: When a block of information is to bechecked, the sending terminal initiates the EOBcheck. A
character, followed by the LRCcharacter, is sent to the receiving location. The
LRC-characters are then compared to determine
whether a longitudinal error has occurred.
Sending thecharacter places the terminal intotransmit-LRC mode. In transmit-LRC mode, theterminal sends the LRC-character, after which theterminal goes into receive-check/answerback mode.
In this mode, the Receive light, Restart light, andmotor are on; and the terminal waits for an answer
from the receiving location.
If aanswerback is received (message received correctly), the terminal returns to transmittext mode and transmission continues. If a codeother than a Q? is received, the terminal prints ahyphen, rings the alarm bell, and shifts to transmittext/lock mode. In this mode, the keyboard islocked and the Transmit light, Restart light, andmotor are on. The lock condition exists until either
the EOT or Restart key is pressed. The restart
operation returns the terminal to transmit-text
mode. The EO T operation sends aand places
the terminal into control-receive mode. If the terminal is receiving the message, the EOB check is
initiated at the other location.
The terminal, upon reception of thecharacter,goes into receive-LRC mode. This mode conditions
the terminal circuits to recognize the next characteras an LRC-character. The motor and the Receive
light are on, and the parity-error circuit is inhibited. The circuit is inhibited because the LRC-

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2740/41 FETOM(4/68)

4-1

character can correctly have either an odd or evenbit count. Reception of the LRC-character places
the receiving terminal into transmit-check/answerback mode. In this mode, the received
LRC-character is compared to the LRC-character
developed within the receiving terminal. If the characters do not compare, the 'error' trigger turns on,
and a hyphen is printed.
The condition of the terror' trigger also determines the response that is returned to the sending
location. With the 'error' trigger on, anegative
response is sent; with the 'error' trigger off, a Q?
positive response is sent. In either case, the receiving terminal returns to receive text mode.

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FUNC TIONAL UNITSPari ty Error (VRC)• The 'parity error' trigger ('receive odd parity'
trigger in 2740-2) is first turned on at start bittime.
• Each data bit changes the state of the 'parity
error' trigger.
• stop bits are not checked.
• The 'parity error' trigger on at the end of a character indicates a parity error.

End-of-Block (EOB) Check (2740-2)
For the 2740-2, the end-of-block check is performed
with every transmission. If an error is detected at
the central processor, the terminal is notified andthe message is retransmitted until either the message is received correctly or the central processor
tells the terminal to quit sending. If the latteroccurs, the Reset light turns on and the alarm bellrings.
Operation: The last Character of each buffer message is thewhich is generated when the Bid key
is pressed. Following the transmission of the @ ,the developed LRC character is sent. The modes
used to accomplish this are the same as for the
2740-1. The 2740- 2 then goes to receive checkanswerback mode.
If the 2740-2 receives a @ answerback, aisgenerated and transmitted and the. terminal goes tocontrol receive mode. If any character other thana Q? oris received, the terminal returns totransmit text mode and resends the message. Retransmission continues until either the message is
recei ved correctly ( Q? answerback) or aisreceived. Reception of awhile in receive checkanswerback mode causes:

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1. The Reset light to turn on
2. The keyboard to lock3. The alarm bell to ring
4. The terminal to go to control receive mode
If the 2740-2 is receiving a message, the EOBcheck is initiated by the central processor like the2740-1.
NOTE: The hyphen is not printed on terminals equipped withBuffered Receive.

4-2(4/68)• A parity error turns on the 'parity error or not
S8' latch.
The parity-error circuit is used only in receive
mode. The 'parity error' trigger ('receive odd
parity' trigger in 2740-2) first turns on when thestart bit arrives. Each succeeding data bit turns the'pari ty error' trigger on or off. When a complete
in-parity character is received, the 'parity error'
trigger is off. When a character containing a parity
error is received, the 'parity error' trigger is on.
The input to the parity-error circuit is the outputof the IS-register' trigger, 'S8.' 'AND I' (Diagram2-1) is conditioned by 'S8, ' 'not send, ' the 'parity
error' trigger off, and 'not L' ('not L' disables theparity-error circuit when the LRC-character isreceived). 'AND 2' is conditioned by 'S8,' 'notsend, ' and the 'parity error' trigger on. If the'parity error' trigger is off, it is turned on by thenext bit; if the 'parity error' trigger is on, it isturned off by the next bit.
The parity check starts when the start bit is received by the S-register. Because the 'parity error'
trigger is first turned off and 'S8' trigger turned on
by IS-register restore, ' the SDAC that gates thestart bit to 'S8' turns the 'parity error' trigger on.
The 'parity error' trigger turns on and off as thebits are received. If the received character is inparity, the 'parity error' trigger will be off at stopbit time. The condition of the 'parity error' trigger
is tested when the start bit reaches 'SO.' 'Not SO'
signals the terminal that the complete character hasb€l€ln r€lc€liJl€ld. B€lcaus€l of this timing, the stop bit
is not included in the parity check.
If the stop bit is absent from the character (usuallycaused by line trouble), the 'S8' trigger is off. Because the stop bit should turn the 'S8' trigger on, theabsence of a bit in 'S8' indicates loss of the stop bit.

Either the 'parity error' trigger on or the absenceof a stop bit turns on the 'parity error or not 88'
latch. 'Parity error or npt 88, ' ANDed with 'not L'
and 'receive text, ' turns on the 'error' trigger. The'error' trigger is tested during the EOB-operation.

Transmission Characters
lRC
latch
11
l2

NOTE: The 2740-2, with or without Record Checking, always
parity checks received characters. Without Record Checking
an out of parity character turns on the Parity light; thecentral processor is not notified of the error. With Record
Checking, the 2740-2 operates as previously explained andthe Parity light turns on.

Error Trigger
The 'error' trigger (Diagram 2-1, 2-2) informs theterminal when one of the following errors has
occurred:
1. An LRC-error
2. The absence of a stop bit
3. A parity error
4. A 2B overflow reset
5. Incorrect case
6. Buffer VRC error (2740-2 only)

The condition of the 'error' trigger, when sampled,
indicates an error to the terminal.
LRC-Register• The LRC-character is developed in the LRCregister.
• Characters enter the LRC-register from the lBregister.
• All text characters and thethe LRC-character.

® character form

• Comparing is accomplished when the transmitted
LRC-character is entered into the LRC-register.
• If any LRC-register triggers are on after thecomparison, an error is indicated.
The LRC-register (Diagram 4-12), consists ofseven triggers, one for each data-bit position. The
input to the LRC-register is from the lB-register.
Each LR C-register trigger is turned on or off by the
input data bit. If the trigger is on, it turns off;
if the trigger is off, it turns on. Thus, an accountof each data-bit position is kept. Fi'gure 4-1 shows
the theory of LRC-register operation. Note that if
an odd number of any given data bit is gated to an
LRC-register trigger, the trigger is on for the check

l3

I

8

t

B

+
8 +

A

8

A

,

M

4
2

l6

1

l7

C

4

7

Generated@

I RC"'-l"hnr

+B t

l4
l5

2

+

B

t

t 2 •
t
4

2

+

1

4

A

t

8

•

t 4 +
2

+

C +
+
+ Tum On lRC-Register latch+ Tum Off lRC-Register latch

A

C

*
t

C

Figure 4-1. LRC Register Operation

character; if the number of bits is even, the trigger
is off.
If the terminal is sending, the LRC character isdeveloped and sent when the EOB operation is ini~
tiated. If the terminal is receiving, the LRC character is developed and compared when the LRC isreceived from the sending location. To compare
characters, the transmitted LRC-character is received and entered into the LRC-register. All
triggers that are on should turn off and none should
turn on. If any triggers are left on, 'LRC error'
comes up (see Diagram 4-12).
Control of the LRC-register is shown in Figure
4-2. All characters sent or received while the terminal is in a "text" mode are entered into the LRCregister. In transmit-text mode, when 'enter
serdes, ' 'Cl, ' and 'time-out I' are up, the 'set LRC'
trigger turns on. 'Set LRC' gates the characterfrom the lB-register to the LRC-register. The 'set
LRC' trigger then gates itself off. Another AND,conditioned by 'transmit text,' 'enter .serdes,' 'Cl,'and 'not @ " also turns on the 'set LRC' trigger.
'Not @ , prevents the @ character from enteringthe LRC-register. For the model 2 the 'not @ ,line is replaced by 'transmit @ .' The 'transmit@ , trigger does not turn on until after the firstcharacter (is transmitted.
In receive-text mode, 'receive text,' 'Cl,' and'not 2B set, ' turn on the 'set LRC' trigger. 'Set
LRC' occurs at the same time as 'IB set. 'The LRC-register is reset by the 'reset LRC'
trigger. The trigger turns on when the 'L' mode
trigger is off and the mode changes. The 'reset LRC'
trigger then turns itself off. The IL' trigger input
allows thecharacter to be set into the LRCregister.

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2740/41 FETOM(4/68)

4-3

, ..----- Not Mod2Enter serdes
ClTime Out-l
Transmit Text

A
0-- ~

Receive Text
Not 2B Set

Transmit Text
Transmit @
(Not)

A OR

---- -""'---Set
LRC-Reg

I~

CC2
CCl

~A

--

Power On ResetA

Set LRC Register

FF(Mod 2)

BB181@ (Mod 1)

Reset
LRC-Reg

Mode Change(Not) LI----------------------------~A

Reset LRC RegisterFF~CC~2~------------~IL JA
CCl
I r-

fA

Power On Reset
BB181

Transmit Text
ClEnter Serdes

Transmit

I A

J

@

.

CCl

IL

FL

JA

Transmit(2740-2)©

B
BB421·
Figure 4-2. LRC Register Control

Mode Control• Additional mode triggers are required forRecord Checking.
The terminal mode determines the action the terminal
performs. To enable the terminal to change to theadditional modes needed for the Record Checking
feature, more mode triggers are required. Diagram
5-12 shows all the mode trigger inputs for the 2740-1.
Diagram 5-28 shows all the mode trigger inputs forthe 2740-2.
The terminal mode is determined by various
combinations of mode triggers on. Figure 4-3 defines the mode trigger(s) that turn on for each mode.
Control receive, transmit text, and receive text
modes are the same as for the 'basic terminals.

4-4(4/68)

The additional modes used for Record Checking
perform the following functions:
Transmit LRC--causes the terminal to send thecontents of the LRC register (LRC character).
Receive LRC--allows the terminal to accept the
LRC character and compare it with the one it hasdeveloped.
Transmit check answerback--causes the terminal
to sample the 'error' latch and to return the result (orReceive check answerback--allows the terminal toaccept the answerback character ( <X> '
or

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Transmit text lock (2740-1 Only)--Causes the terminal to lock up if a negative answerback (is received.

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TRANSMITTING TERMINALRECEIVING TERMINAL

Control-Receive

,
1

1

0 0

0

Receive-Text

0

1

0

0

,

1

Receive-LRC

0

1

0

0

1

+
0

Transmit-Check/Answerback

0

1

A

B D F

L

Control-Receive

1

1

0 0

0

Transmit-Text

1+
0 0 0 0

1

0

+

+

Transmit-LRC

1 0

Receive-Check/Answerback
See Note 1

1

0

1 0

Transmit-Text/Lock

1

0

1

Transmit-Text

1

0

Control-Recei ve

1

MODES

See Note 2 and 3

+
1

+

MODES

A

B D F L0

Receive-Text

0

0 0

0

Control-Receive

1

0 0

0

1

++

Note 1:

Depending on response, the transmitting
terminal may go to either transmit-text/
lock or transmit·text mode.

Note 2:

From transmit-text;1ock mode the transmitting
terminal may go to either transmit-text mode
(Restart key depressed) or to control-receive
mode (EOT key depressed.)

Note 3:2740-2 does not use Transmit-Text/Lock mode.

+

+
1

+
1

0

1 0

0

0

+
0

0 0
0

0

Figure 4-3. Sequence of Mode Operation, Record Checking

Figure 4-3 shows the sequence of operation of themode triggers for both transmitting and receiving
operations.

register. Similarly, because the'strobe' signal is notproduced, 'IB set' must be developed. 'IB generate'
starts the control clock, producing the 'IB set'
pulse. 'IB generate' and 'IB set' place theinto
the IB-register. From the IB-register, thetransfers to the S-register and is sent the same as
any other character. 'IB full' conditions 'enter
serdes gate' to turn on; 'enter serdes gate' turns on'enter serdes, ' which starts the transferring sequence. 'Enter serdes' turns off the 'EOB' trigger,
dropping 'IB generate. ' 'EOB gate' turns off when
the operator releases the EOB key. The
is alsoloaded into the LRC register.
While theis in the IB-register, it is detected
and, with 'enter serdes, ' turns on the 'end-of-state'latch (Diagram 5-14). The 'end-of-state' latch prevents the reset of the IB-register. When the operation is completed, the 'operate' trigger turns off.
End of state and not operate ('EOS and not 0') andturn on the 'D' and 'L' mode triggers. 'A,'
'D, ' and 'L' mode triggers put the terminal intotransmit-LRC mode. 'Mode change' resets thefrom the terminal registers.

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PRINCIPLES OF OPERATION
Transmit EOB-Character (2740-1)• Pressing the EOB key at the sending terminal
starts the operation.

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• The
character (A842C) is placed in the IBregister by 'IB generate' and 'IB set. '• From the IB-register the character is sent normally.
• Sending the
LRC mode.

® changes the terminal to transmit®)

Sending the EOB-character (is much the sameas sending the @ andcharacters. Pressing
the EOB key while the terminal is in the transmittext mode turns on the 'EOB' trigger(Diagram 5-14).
The 'EOB gate' trigger interlocks the 'EOB' trigger
to ensure that a single EOB-operation is performed
regardless of the length of time the EOB key is held.
'EOB' coming on produces 'IB generate.' Because the I/O device is inactive during this operation,'IB generate' is required to place the @ in the IB-

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Transmit EOB Character (2740-2)®

For the 2740-2, theis generated and loaded into
buffer storage when the Bid key is pressed. The
EOB operation does not begin until theis detected in the IB-register during transmission.
Following recognition of thethe EOB operation
for the 2740-2 is exactly the same as for the 2740-1.

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2740/41 FETOM(4/68)

4-5

Transmit LRC-Character• 'Transmit LRC' brings up the 'transmit answerback' line.
• 'Transmit answerback' and 'lB emptyi' start thecontrol clock.
• 'lB set' transfers the LRC-character to the 1Bregister.
• 'lB full' is forced up by 'parity error or not S8. '• The LRC-character is placed into the S-registerand sent normally.
• Sending the LRC-character changes the mode torecei ve-check/ answerback.
The change to transmit-LRC mode brings the 'transmit LRC' and 'transmit answerback' lines up (Diagram 5-14). 'Transmit answerback' and 'lB empty'
start the control clock to produce the 'lB set' pulse.
'Transmit LRC' and 'lB set' transfer the LRCcharacter from the LRC-register to the 1B-:register.
Mter theLRC-character transfers to the 1Bregister, the 'lB full' signal must be produced totransfer the character to the S-register. The LRCcharacter can contain any bit configuration, including
the combination in. which all 1B-register triggers areoff. To ensure that' 1B full' is brought up under
this condition, the 'parity error or not S8' latch isturned on by the 'lB set' pulse, forcing up 'lB full. 'The character is transferred to the S-registerand transmitted normally.
The 'end-of-state' latch is turned on by 'transmit
answerback' ('transmit LRC '), 'enter serdes, ' and'Cl.' When character time is completed, 'EOS and
not 0' change the mode from transmit-LRC toreceive-check/answerback by turning off the 'L'
mode trigger. Mode change resets the LRC character from the 1B-register.
The sending terminal has now sent the EOB- andLRC-characters and is in receive-check/answerback
mode, awaiting an answerback from the receiving
location. The keyboard is locked.
Receive-Check/Answerback (2740-1)• The EOB-check response is received in the normal manner.
• A positive response ( @ ) changes the mode totransmit-text.

4-6(4/68)®)• A negative response (prints a hyphen andchanges the mode to transmit-text/lock.
• No response causes the terminal to lock inreceive-check/ answerback mode.
While in receive-check/answerback mode, the sending terminal receives the response to the EOBcheck from the receiving location. Reception of the
response character occurs normally. When the
response character is in the 1B-register, the character is analyzed to determine subsequent action.
The @ character (BA821) is recognized as apositive response and brings the' @ , line up (Diagram 5-15). The (X) character turns off the 'D' mode
trigger, which places the terminal into transmit-text
mode. The mode change resets the (X) from theterminal registers. The @ is not printed because
the mode change occurs before the character transfers to the 2B-register.
Any other response character is recognized as anot (X) , or negative response. This results in thedevelopment of a '2B set' pulse. 'Not @ , and'receive answerback' bring up '2B inhibit, ' whichblocks all normal inputs to the 2B-register. '2B1,'
however, is turned on by '2B set' and 'receive
answerback' (Diagram 5-15). A hyphen (B-bit) isentered into the 2B-register and the hyphen is printed.
When the operation is complete, the 'operate' trigger
turns off. (The 'end-of-state' latch turned on when
'2B set' came up.) 'EOS and not 0, ' 'receive answerback,' and 'D' mode trigger on turn on the 'F' mode
trigger.
The 'A, ' 'D, ' and 'F' mode triggers (on) developtransmit-text/lock mode. The mode change resets
the negative response character from the terminal
registers. The terminal keyboard is locked. The
operable control keys are the EOT and RST (Restart)
keys. If the operator presses the EOT key, theterminal goes into control-receive mode. If theoperator presses the Restart key, the terminal goes
into transmit-text mode, and data transmission cancontinue.
It is possible that neither a positive nor a negative
response is received as a result of the receiving
location being off at the time the EOB-check is performed., In this case, the terminal remains inreceive-check/answerback mode, with the keyboard
locked until the Restart key or EOT key is pressed.
Restart• Returns the sending terminal to transmit-text
mode following an error response from the receiving location.

• Pressing the Restart key turns on the 'restart'
trigger.
• The 'restart' trigger gates off the 'D' and 'F'
mode triggers.
When an error response is received from the receiving location, the terminal goes into transmit-text/
lock mode. To return the terminal to transmit-text
mode, the operator must press the Restart key toturn on the 'restart' trigger. Figure 4-4 shows
conditions, If the 'D' and 'F' mode triggers are on(transmit-text/lock mode) the 'restart' trigger provides a gate to turn the triggers off. The resulting
mode change then turns off the 'restart' trigger.
Reverse Transmission: Terminals connected to a
multiplexer are equipped with reverse transmission
which causes the terminal to go into receive-text
mode if a @ is received in place of the response
character. The circuit is shown in the dotted area
on Diagram 5-15.
When the terminal is in recei ve-check/ answerback
mode and a @ is received from the multiplexer, the'B' mode trigger turns on, and the 'A' and 'D' mode
triggers turn off.
Receive Check Answerback (2740-2)

GJ• A
answerback returns the terminal to transmit
text mode to transmit a

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• A
answerback returns the terminal to transmit text to retransmit the message.

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• A
answerback on any transmission causes anerror indication and a return to control receive
mode .
• A @ answerback places the terminal into receive
text mode.
After transmission of the message, the terminal
goes to receive check answerback mode. In thismode, a character is received from the central processor to indicate if the message was received correctly. If the terminal receives afor an answerback, it returns to transmit text mode, transmits athen goes to control receive mode.
If the message was not received correctly at thecentral processor, it returns acharacter. This
character causes the terminal to return to transmit
text and to retransmit the message. The number ofretransmissions is controlled by the central processor program.
The central processor could return aas theanswerback following any transmission; the terminal
would go to control receive mode after indicating anerror (the bell rings and the Reset light turns on).
If, after receiving the transmission, the central
processor wishes to place the terminal into receive
text mode without going through the addressing procedure (reverse transmission), a @ is returned as
the answerback character. This character places
the terminal in receive text mode.
Refer to Diagram 5-16. The answerback character is received in the S-register and transferredto the 1B-register. If the transmission was received correctly at the central processor, a
char-

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®

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GJ

1 B Em tAD(Not) lB Generate(Not) EOT Gate
(Not) Operate
Res tart 1 (Restart Ke )(Not) Carrier HD
Res tart Se t- B

(Th is line depends on data
set or modem used.)

A

Restart Set GateD
D Reset Gate

BBOll

BB041
Restart
CC2

FF

Mode Changeo Restart Reset(This line not presently
used. )

Power On Reset

BB321
F

F Reset Gate

D

BB011
Figure 4-4. Restart Circuit

2740/41 FETOM(4/68)

4.-7

acter is now in the 1B-register. 'Q?,' 'Receive
answerback, ' and 'not C2' bring up 'D reset gate, 'causing the terminal to return to transmit text mode.
The terminal returns acharacter to the central
processor and then goes to control receive mode.
If the message was not received correctly by thecentral processor, the terminal receives a negative
answerback. 'Not ~ , ' 'not'receive answerback, ' and 'lB full' bring up 'receive negative answerback'--whichwith 'not C1'--brings up 'D reset gate, 'placing the terminal into transmit text mode. The
terminal again transmits the message (except the@ ) and returns to receive check answerback mode.
If the message is received correctly by the central
processor, a ~ is returned; the terminal returns
to transmit text mode, transmits aand then goesto control receive mode. If the message is not recei ved correctly, the central processor may again
return a @ character. Retransmission continues
until the central processor returns a ~ or aforthe answerback. If a
is received, 'receive answerback, ' ,and 'not C1' turn on the 'rekey'
latch. The 'rekey' latch turns on the Reset light,
rings the alarm bell, locks the keyboard, disables
the Bid and Enter keys, and blocks the status set
gate (see Diagram 4-11). At the same time, 'set
control receive' is brought up by 'not send, ' 'notoperate, ' ,'not C 2, ' and 'not C 1, ' placing theterminal into control receive mode. The terminal
remains locked until the Reset key is pressed. The
operator can press the Bid key and, once polled,
send the contents of buffer again or start over andre-enter the message.

©

© ,'

©

©'

©

©

©"

Receive EOB-Character

®

• The
character is received normally andputs the terminal into receive-LRC mode.
• '2B inhibit' prevents the transfer of thethe 2B register.

® to

The EOB-character is received normally by thereceiving terminal and is placed into the 1B-register.
While in the 1B-register, theis detected andconditions an AND to turn on the 'V mode trigger(Diagram 5-17). 'L' on puts the terminal into
receive-LRC mode, conditioning the terminal to recognize the next character as the LRC-character.
The
is added to the LRC-register to complete thereceiving-terminal LRC-character. The @ also
brings up '2B inhibit, ' which prevents the transferof theto the 2B-register and the I/O device.

®

®

®

4-8

(4/68)

Receive LRC-Character• The parity circuit is disabled for the LRCcharacter.
• The LRC-character is added to the LRC-registerfor comparison.
• Failure to compare turns on the 'error' trigger.
• The 'error' trigger is sampled; if the trigger isoff, the mode changes directly to transmit-check/answerback; if the trigger is on, the hyphen prints
and the mode changes to transmit-check/answerback.
Receive- LRC mode (1) disables the parity-check
circuit for the LRC-character, (2) disables the' 1B
OK'circuit so that the LRC-character is not recognized as a control character (the LRC-character canbe any bit configuration), and (3) forces up 'invalidcharacter' to prevent a normal '2B set. 'The LRC-character is received and loads into the
1B-register. When 'set LRC' comes up, the LRCcharacter is added to the LRC-register. If the transmit and receive LRC-characters are the same, all
LRC-register triggers turn off. This results indropping the 'LRC error' line (Diagram 5-17). If an
LRC-error has occurred, the LRC-characters do
not compare, and one or more of the LRC-register
triggers remain on. The' LRC error' line remains
up, indicating an LRC-error.
At this point '2B set' is brought up by forcing the'parity error' or 'not 88' latch up. 'L,' 'not A, ''not 2B set, ' and 'C1' turn on the 'parity error or
not 88' latch. 'Parity error or not 88' and otherconditions shown on Diagram 5-17 bring up '2B
set set gate, ' turning on the '2B set' trigger. If
the 'LRC error' line is up, '2B set' turns on the'error' trigger. The 'error' trigger might alreadybe on because of a previous error (parity error,
no stop bit, etc.). '2B set' also turns the 'end-ofstate' latch on.
If the LRC-characters compare, the 'error'
trigger does not turn on; the terminal goes intotransmit-check/answerback mode. If the 'error'
trigger is on, a hyphen is printed, and the terminal
goes into transmit-check/answerback mode. The
circuit for printing the hyphen is as follows: '2B
inhibit'prevents normal entry to all 2B-register
triggers, except' 2Bl.' In the event of an error,
the '2Bl' trigger is turned on by '2B set, ' the 'L'
trigger on, 'receive text, ' and 'C1' (Diagram 5-17).
The B-bit is entered into the 2B-register and ahyphen is printed.

At the end of the printing operation, the 'operate'
trigger turns off and 'EOS and not A' comes up. The'D' mode trigger turns on, the 'L' mode trigger
turns off, and the terminal goes into transmit-check/answerback mode. Depending upon the state of the'error' trigger, the receiving terminal now returns
either aor
to the sending terminal.

®

®

Transmit-Check/Answerback• Puts receiving terminal into a sending condition.
• Positive response ( Q? ) sent if 'error' trigger
is off.
• Negative response (is on.

®) sent if 'error' trigger• After sending either response, the terminal returns to receive-text mode.
Transmit-check/answerback mode places the receiving terminal into a sending condition. Depending
upon the condition of the 'error' trigger, a positiveor negative response returns to the sending terminal.
The 'send' line is brought up by the 'D' and 'B'
mode triggers. The 'send' line starts the serdes
clock (Diagram 5-18), allowing the response character to be serialized to the 'serial data out' line.

The terminal now enters the correct response character into the lB-register.
If the 'error' trigger is off, 'IB generate' isbrought up by 'D, ' 'transmit answerback,' 'not L, 'and 'not error.' 'IB generate' provides gating to the'lB2,' 'lB3,' 'lB4, ' 'lB5, ' 'lB6,' and 'lB7' latches.
The control clock is started and brings up 'IB set. 'The @ (B, A, 8, 2, 1) is entered into the lBregister. Note that the 'lB4' and 'lB7' latches aredegated by 'not transmit answerback'; therefore, fora positive response, 'IB set' turns on the 'lBl, ''lB2, ' 'lB3, ' 'lB5, ' and 'lB6' latches. 'lBl' isbrought up by 'IB set, ' 'transmit answerback, ' and'not transmit LRC, ' regardless of which response is
sent.
If the 'error' trigger is on, 'IB generate' does
not come up. The control clock is started insteadby 'not C2,' 'transmit answerback,' 'D,' and 'IB
empty,' which condition the '~Cl gate' line. The
control clock pulses again bring up 'IB set.' But
because 'IB generate' is down, only the 'lBl' latchturns on, and thenegative response is sent.
When either response has been sent, the 'operate'
trigger turns off. The 'end-of-state' latch was
turned on by 'transmit answerback, ' 'Cl, ' and 'enter
serdes.' 'EOS and not 0, ' along with 'transmit
answerback' and 'not transmit LRC, ' turn the 'D'
mode trigger off (Diagram 5-18). The receiving terminal now returns to receive-text mode, ready torecei ve data.

®

2740/41 FETOM(4/68)

4-9

SECTION 2. AUTOMATIC EOB (2740-1)• Record-checking feature is a prerequisite.
• Carrier-Return key generates carrier-returnand starts EOB-sequence.
• Check switch selects auto-EOB off, terminalto-terminal, or terminal-to-multiplexer.
• A second carrier-return is forced by a negative
response to EOB-check.
• If the Auto-Check switch is in TERM, the second
carrier-return character is sent; if the Auto-

Check switch is at MP LX, the second carrierreturn character is not sent.
The automatic- EOB feature starts the EOB checking
sequence whenever the operator presses the CarrierReturn key. A switch permits the terminal operator
to select anyone of three auto-checking modes:
OFF, TERM, or MPLX. The Check switch mustbe at either TERM or MPLX for the automatic-EOB
feature to be used.
Diagram 5-13 illustrates the auto- EOB function.
When the terminal is in transmit-text mode and the
Check switch is at TERM or MPLX, a carrierreturn started by the terminal operator causes a
carrier-return character and the EOB- and LRCcharacters to be sent. The LRC-character is sent
and the terminal goes into receive check answerback
mode. If a
answerback is received, the terminal goes into transmit text mode. If a
answerback is received, a hyphen is printed toindicate the error response, and the terminal goes
into transmit text lock mode.
If a restart is initiated by the operator, the terminal goes into transmit text mode; and a second
carrier-return is performed. The second carrierreturn, which occurs only when there is an error
response to the EOB-check, synchronizes the communicating terminals to print subsequent data fromthe left margin. The second carrier-return character is sent if the terminal is connected to anotherterminal (TERM); the carrier-return is not sent if
the terminal is connected to a multiplexer (MPLX).

®

4-10

(4/68)®

When the operator presses the Carrier-Return key
the I/o transmit contacts are strobed, transferring
the carrier-return character to the 1B-register.
The carrier-return code is detected and brings up
the 'carrier return code' line (Diagram 5-19). The
carrier-return character is sent normally as thecarrier-return function is performed.
The 'auto EOB' trigger must turn on in order togenerate the EOB-character. 'CR code' ANDed with
'auto check, ' (transmit text), 'not auto EOB,' 'enter
serdes,'and 'C2' turns on the 'auto EOB' trigger. Autocheck is active when the check switch is at TERM or
MPLX. 'Auto EOB' brings up 'EOB gate, ' whichturns on the 'EOB' trigger and starts the normal
EOB/LRC transmit sequence.
After sending the LRC-character, the terminal
goes into receive check answerback mode, awaitinga response from the receiving terminal. If a
response is received, the terminal goes into transmit text mode. The mode change resets the 'auto
EOB' trigger.
If the response is not a (X) , the terminal prints
a hyphen and goes into transmit text lock mode.
When the operator presses the RST key, the terminal goes into transmit text mode; and a second
carrier-return is performed. The second carrierreturn is caused by the 'force CRt latch. 'Receive
answerback' and '2B set, ' the same conditions thatcause the hyphen to print, turn on the 'force CRY
latch. 'Force CR, ' 'ANDed with·transmit text'(comes up when the RST key is pressed) and 'not
I/O cycle, ' pick the carrier-return magnet, performing the carrier-return.
'Strobe' transfers the carrier-return characterto the 1B-register; if the Auto-Check Switch is at
TERM, the character is sent. If the Check switch is
at MPLX, 'C1 gate' comes up starting the control
clock. The control clock outputs cause the carrier
return character to be reset from 1B (Diagram 5-19).
The 'auto EOB' trigger is reset by 'auto EOB, ' 'CR
code, ' and 'C2.' The 'auto EOB' trigger off and 'CR
code' reset the 'force CRY latch.
If the operator presses the EOT key instead of the
RST key, the terminal goes into control receive mode.
The 'auto EOB' trigger is then turned off by 'B'.

®

SECTION 3. DIAL-UP (2740-1/2741)• Allows Vilestern Electric 103A (or equivalent)toconnect terminal to common-carrier communication system .

The following "handshaking" procedure establishes
a connection to another terminal or multiplexer dataset.

• Terminal is disconnected from system when
Dial-Disconnect key is pressed.

Originating Data Set

Answering Data Set

Lift receiver and dial. *------.~Answer. *The Dial-Up feature permits the 2740-1/2741 terminal to use the Western Electric 103A data set (orequivalent) to communicate over the common-carrier
network (normal dial-telephone service). The terminal operator simply dials the telephone number of
the terminal or multiplexer with which communication is desired; once the connection is established,messages can be sent or received. When carrier isrecei ved from the data set while the terminal is incontrol receive mode, the Dial-Connect light indicatesthat a connection has been established.
Figure 4-5 shows the interface from the terminal
to the 103A data set. Note that most interface lines
are similar to those used by other line adapters.
One difference is that the 'clear to send' line isbrought up (with a 45 ms delay for 2740-1, and 330
ms for 2741) when 'send' ('request to send') comesup. For an explanation of these common lines. Ree"Terminal to Line Adapter Interface. "Auto answer or press
data button. * (103A
goes into and remains
in data mode if 'data
terminal ready' is up
and remains up. )Wait 1. 5 ieconds fortoll billing.

~!.

Receive F2M . . . .t---------Turn on F2M (answer
carrier tone).
Pus h data button. *Wait 150 lilliseconds;
monitor F2M.

~

Unclamp 'receive data'
ADAPTERTERMINAL

103A OR EQUIVALENT

Serial Data Out

BA Transm itted Data

Serio I Data In

BB Received Data

Data Set Read

CC Data Set Read

Carrier

Clear to Send

Send
Clear To Send

Delay Time:J) 45ms for 2740- J2) 330ms for 274 J

Data Terminal Ready

CD Data Terminal Read

line.

1

Wait 1. 5 seconds (remove
echo suppressors).

~

Turn on F1M.--------l.~Receive F1M.

Waitmonitor F1M.

Bring up {data carrier detect'and 'clear to send. 'Unc lamp
data' line.

B1K4
3562

~'rece iverJ

Wait 200 milliseconds(turn around time).

ADAPTER CARDS
Position
Card No.

150~milliseconds,

Wait 200 Lilliseconds(turn around time).

B1L4
3561

Bring uptdata carrier
detect' and 'clear tosend.'!

Figure 4-5. Dial-up Interface (103A)

Once the connection is established, the terminal
operates point-to-point.
*Operator action

2740/41 FE TOM(4/68)

4-11

Dial-Disconnect
Because a charge is made for the common-carrierline only while in use, the terminal should be disconnected from the communication line when datacannot be sent or received. Therefore, the statusof the terminal controls the data set. A loss of terminal status disconnects the terminal from the communication line. The disconnection is caused by theterminal dropping 'data terminal ready, ' which
signals the data set to disconnect. The terminal isalso disconnected if the operator presses the DialDisconnect key on the I/o keyboard.
A special feature is available from the common
carrier that permits both ends of the communicationline to be disconnected when 'data terminal ready'drops. This feature requires no changes to theterminal.
The condition of 'data terminal ready' is determined by both the condition of the 'status' trigger

4-12(4/68)and the 'dial disconnect' latch (see Diagram 5-47,
Sheet 2). If the 'status' trigger is off (lack of paper,
local mode, or loss of data-set status) 'data terminal
ready' drops. Turning on the 'dial disconnect'
latch (operator pressing the Dial-Disconnect key)also drops 'data terminal ready. 'Dial Up (2741)
The Dial-Up feature for the 2741 operates like the2740, except when 'send' ('request to send') comes
up, 'clear to send' is delayed 330 ms. The delay isneeded for turn-around time. In the 2740, turnaround (from receive to transmit) is accomplishedwhen the operator presses the Bid key. Operator
action takes enough time to allow for the turn-around.
In the 2741, the computer causes turn-around; additional time must be allowed before data can be sent.

SECTION 4. TRANSMIT CONTROL (2740-1)• Allows a computer to control the sending or
receiving status of the terminal.
• The terminal goes into receive mode when a@ is received.
• The terminal goes into transmit mode when a
2-character sequence (slash-space) is received.
• If, during a period of 15 seconds, no key ispressed, the 'time-out 15' latch turns on,
causing the terminal to go into controlreceive mode.
The transmit-control feature allows a computer tocontrol the sending or receiving status of a terminal.
The dial-up feature is a prerequisite. The terminal
goes into receive mode when the multiplexer sends
a @ character. This operation is identical tobasic terminal operation.
The terminal goes into trans mit mode when themultiplexer sends a special 2-character sequence(Diagram 5-25), which consists of a slash (/)
followed by a space. Receipt of this 2-character
sequence places the terminal into transmit mode andautomatically causes a @ character to be returnedto the multiplexer. Once the terminal is in eithertransmit or receive mode, it operates like a basic
terminal.
The terminal goes into trans mit text mode
(Diagram 5-26) when the slash is received by theterminal. It is detected, and turns on the 'F' mode
trigger. Turning the 'F' mode trigger on (with the'A' and 'B' mode triggers already on) puts the terminal into intermediate control-receive mode,
which conditions the terminal to receive the spacecharacter. The space is detected by an AND, theoutput of which, 'space,' goes to several AND'sshown on Diagram 5-26. Space and 'intermediate
control receive' turn off the' F' and 'B' mode
triggers and turn on the 'bid' trigger. This places

the terminal into transmit mode and causes a @character to be sent. When the @ is sent, (1) the
alarm bell rings, (2) the motor turns on, and (3) the
keyboard unlocks. If the second character is not a
space, the 'F' trigger turns off and the terminal
returns to control-receive mode.
When the terminal is in transmit mode and theoperator does not press any key for 15 seconds, theterminal returns to control receive mode. Diagram5-26 shows the circuit. 'Not 1B generate, ' 'send, ''not test, ' 'not strobe 0, ' 'not operate, ' and' 1B
empty' condition an AND. This AND indicates thatno operation is taking place. The output of the AND
enters a 15-second time delay. If no operation occurs
for 15 seconds, the time delay times out, and its output turns on the 'time-out 15' latch. The output of
the latch turns on the 'B' i:node trigger and blocks
an AND to the input of the 'strobe 0' trigger (to prevent further operations). The control clock must run
in order to generate pulses to change the mode. The
clock is gated on by the 'C1 gate.' The conditions tobring up this line are 'multiplexer transmit control, ''not garble,' 'not C1, ' and 'time-out 15' latch on.
Transmission with the Transmit Control feature isended normally by sending acharacter.
A 2-position switch is mounted on the side of theterminal. This switch can be in either the MTC(multiplexer transmit control) or the OFF position.
While at OFF, the terminal operates normally,
except the time-out 15 feature is retained.
Any telephone in the country can call a terminal
and be connected. Therefore, the terminal must not
become tied up if a non data-type telephone makes aconnection. Only a data set or modem is capable ofgenerating carrier; a standard telephone is not. Noteon Diagram 5- 26 that an AND inputs to the 'time-out
15' latch, the conditions of which are 'data set ready'and 'not carrier.' If' data set ready' is up and no
carrier is received for 15 seconds, the 'time-out
15' latch turns on. 'Time-out 15' and 'not-carrier'cause a dial-disconnect to disconnect the data set
from the common-carrier lines.

©

2740/41 FE TOM(4/68)

4-13

SECTION 5. STATION CONTROL (2740-1/2740-2)
INTRODUCTION• Allows more than one terminal to be connected to
a computer (via a multiplexer) by a single communication line (Figure 4-6).
• A terminal is addressed to receive data.
• A single terminal, a group of terminals, or all
terminals on the communication line .can beaddressed.
• A terminal is polled to send data.
• Only one terminal is polled at a time.
• Feature is standard on 2740-2.
A single communication line greatly reduces the costof communication. facilities to the customer. In orderfor terminals to communicate with the computer
without contention (more than one terminal attempting
to use the communication line at the same time), a
special addressing and polling scheme is used.
Addressing prepares a terminal or group of terminals to receive data.
Polling informs an individual terminal that it
alone can send data. Each terminal is polled in apredetermined order that is controlled by computer
programming. To send data, the operator presses
the Bid key before the next poll. When polled, theterminal goes into transmit text mode; the operator
can then send a message.

AddreSSing and polling are accomplished by sending a special sequence of characters to the terminal(Figure 4-7). Note that the @ ,andcharacters are the same as used in other terminaloperations. The(comma, A821C) identifies
the addressing operation.
Each terminal is assigned three addresses: anindividual terminal address, a group address, andan all-call address (Figure 4-6). The terminal
address consists of an alphabetic character and aspace. The terminal address is used for both polling
and addressing, and identifies each terminal. A
group address, which also consists of an alphabetic
character and a space, is assigned to two or moreterminals. Both terminal and group addresses are
wired into the terminal (using jumpers) by the
Customer Engineer. The group address, used only
for addressing~ allows all terminals in the addressedgroup to receive the computer message. The allcall address (not wired) is a slash (/)-space, andenables all terminals on the communication line toreceive the computer message.
When either a group or all-call address is used,
one terminal in the group is assigned the role ofmaster (all other being slaves). For the all-calladdress, only one terminal on the communicationline is designated master. For the group address,
one terminal in each group is designated master.
A master is designated by Customer-Engineer wiring(using jumpers). The all-call or group master
responds to the addressing sequence by informing
the multiplexer of the status of the terminal. Only
the status of the master terminal is sent to the multiplexer; if a slave terminal does not have status, theterminal does not receive the message.

©, ®,

®

®

To Computer

Addressing
Add

MULTIPLEXERMPLX to TERM©® Char Space@ Receive Text ©

@) or (2)2740-1 to MPLX~~~; (2) or @) *2740-2 to MPLX

Polling
Add
Terminal AddressGroup Address
All-Call Address

A Space
G Space/ Space

B Space
G Space/ Space

C Space
H Space/ Space* Group Master** All-Call MasterFigure 4-6.

4-14

Station Control, Terminal Configuration(1/69)

D Space
H Space/ Space

MPLX To TERMTERM To MPLX
Note

©

Space
Char

@) or @

Transmit Text

* (2) for terminal with receive status; @) , without.

Figure 4-7. Addressing and Polling, Character Sequence©

Addressing Mode Sequence
Terminal operation with station control is dependent
upon the terminal mode (Figure 4-8). The terminal
is first placed in text non selected mode when power
comes up. In text non selected mode, only receiptof a
can cause a mode change. The
placesthe terminal in control receive mode, where theterminal can recognize a @ , ®, or any alphabetic address-character. Because an addressing
sequence is being received, the next character
received is theThe
indicates that the terminal is being addressed (not polled) and places theterminal in control address mode. In control
address mode, the terminal can recognize a@ , terminal address, group address, or an all-:;call address. This explanation assumes that a terminal address is being received.

©

©

®.

®

©,

Terminal Address

Transmit Status Answerback (2740-1)
The address character is followed by a space in theaddressing sequence. The space character causes
the terminal to go into transmit status answerback
mode. In this mode the status of the terminal is
A

B

E

F

Text Non-selected

1

1

1

0

Control-Receive

1

1

0

0

Control-Address

0

1

0

0

Contro I-Address/Se lected

0

1

0

1

1

0

1

~
~
~
~
Transm it-Status/Answerback

1

Control-Selected

0

1

1

1

Receive- Text

0

1

1

0

1

0

~

~

~

~
Control-Receive®

®

Transmit Status Answerback (2740-2)
The address character is followed by a space in theaddressing sequence. The space character causes
the terminal to go into transmit status answerback
mode. In this mode the status of the terminal ischecked and a two-character response returns to
the multiplexer in the form of a qualified
or aqualified(Figure 4-7). Thus, the 2740-2 has a
two-character positive or negative answerback
when addressed.
Theoris qualified by a sense character
which is generated by an error condition stored inerror latches, status condition of the terminal, orby no error condition (Figure 1-21).

1

~
0

®

®

®

The terminal address is recognized and places theterminal in control address selected mode. Only
the terminal that is wired for the received addresscharacter changes mode; unselected terminals
remain in control address mode until either a ©
or @ is received.

MODES

checked and a response returns to the multiplexer
in the form of a @ or Q? character.
The
indicates to the multiplexer that the terminal does not have status and that the computer message should not be sent. The alarm bell rings to notify the operator that the terminal was addressed. If
ais sent by the terminal, status is indicated andthe multiplexer can send its message.

®

Receive Text. If the qualified @ is sent by theterminal, status is indicated, and the multiplexer
can send its message. The terminal is placed incontrol selected mode when the positive answerback is sent. In this mode the terminal waits forthe first character of the message (@). (However, the multiplexer can send ain whichcase the terminal returns to control receive mode. )Receipt of the @ places the selected terminal into
receive text mode and the unselected terminals
into text non-selected mode. Should the terminal
lose status during the message, the terminal isreturned to text non-selected mode.
When the message is completed the multiplexer
sends awhich informs the terminal that themessage is completed and causes the terminal to
go into control receive mode.

©'

©,

®

Negative Response. If theor qualified @issent to the multiplexer, it indicates that the terminal does not ha ve status and that the computer
message should not be sent. The alarm bell rings
and the Attention light comes on to notify the operator that the terminal was addressed. The 2740-2
encodes and sends a sense character to inform theCPU program of the status or operator error condition which caused the terminal to 1;>e without
receive status. The program should go to otherbusiness before readdressing the terminal, and if

Figure 4-8. Addressing, Mode Sequence
2740/41 FETOM(1/69)

4-15

bid or enter in communicate mode were indicated,
the program should poll the terminal before readdressing it.
After thehas been transmitted, 'not 1st or
2nd status character answerback' allows the resetof the A and F triggers (Diagram 5-22,3), and theterminal goes into control-address mode.
Operator action is required if the terminal is in
local mode, out of paper, or the document insertion
device is down. Gaining status turns off the Attention light and conditions the terminal to make apositive response to the next address.

A

B

E

F

Text Non-selected

1

1

1

0

Control-Receive

1

1

0

Intermediate Polling

1

1Transmit-Poll/Answerback

1

0

Transmit-Text

1

0

Control-Receive

1

MODES

J

®

J 'J
See note.

©

As in addressing, the terminal is first placed in text
non selected mode when power comes up (Figure 4-9).
Receipt of thein the polling sequence places theterminal into control receive mode. As in addressing,a@,or station address character can bereceived in control receive mode. Because this is apolling operation, the character received is the station
address character. The address character places theterminal into intermediate polling mode.
When the terminal is in intermediate polling mode,the space is received, and the Bid key has beenpressed, the terminal goes into transmit text mode.
A @ is returned to the multiplexer. The operator
can then send the message. If the Bid key has notbeen pressed, the terminal goes into transmit pollanswerback mode. A
is sent to notify the multiplexer that the terminal has no message. The terminal then returns to control receive mode.
When the operator finishes the message, hepresses the EOT key to send aand return the

©
®

®

©

4-16

(1/69)

1

1

1

1

0

t

J

l

t

1

0

0

Note:
At this point the terminal can
go to either transm it-poll/answerback(Bid key not pressed) or to transm ittext (Bid key pressed) .
Figure 4-9. Polling, Mode Sequenceterminal to control receive mode. The terminal is
now available to be polled or addressed. Figure
4-10 shows the normal mode change sequences.
FUNCTIONAL UNITS®

Polling-Mode Sequence

©,

1

+

Group or All-Call Address
When a group or all-call address is received, thesequence up to control address mode is the same
as for the terminal address. In control address
mode, however, the group or all-call address isrecognized by more than one terminal. Only themaster terminal can send an answerback; all otherterminals fBla ves) must not send an answerback.
the master of the group performs like an individual
terminal address is received. All other terminals
become slaves and perform differently.
While in control address mode, the status of theslave terminal is checked. If the terminal has status,
the terminal goes into control address selectedslave mode; if the terminal does not have status, theterminal remains in control address mode and isinactive until eitheroris received, at whichtime the terminal goes into either text non selected
or control receive mode.

0

When the terminal is first turned on, it can receive
data in mid-character (garble). If this occurs, theterminal might interpret the incomplete character(s)as a valid control character. Furthemore, theterminal might achieve a status that would interferewith proper operation of the line. In order to prevent the unpredictable effects of garble, the terminalis prevented from responding to line data for 15
seconds after power is turned on. Within 15 seconds,
the 'SO' and 'S8' relationship to the start and stop
bits of the received character is correct.
When power first comes up, the 'power on reset'line turns on the two garble triggers (Diagram 4-13).
The garble circuit (1) blocks the 'lB set' line, and(2) prevents recognition of a character as a parity
error or not S8 error (no stop bit). The output of thegarble circuit, ANDed with 'not repeat' and 'not poweron reset, , starts a 15-second time delay. Fifteen
seconds after the time delay is conditioned, the'time-out 15' latch turns on. The output of the 'timeout 15' latch, ANDed with 'not C1' and 'not C2, ,turns off the 'garble 2' trigger (see Diagram 4-13).
The 'garble 2' trigger turns off the 'garble l' trigger
and the 'time-out 15' latch, allowing the terminal toreceive data.

POWER ON RESET,SET: A,B,E; RESET: D,F

POLLING SEQUENCE--

©

ADDR
SPACE
CHAR

RECEIVERESET E

INTERMEDIATEPOLLING MODE~
E
F

ADDRESSING SEQUENCE --@®

©,

ADDR
SPACE
CHAR

RECEIVERESET ARECEIVE 1ST
ADDR. CHAR.,SET E AND F

CD,

SLAVE

,.....---""--~I""""""I RECEIVESPACE, RE~---T--""'I...o."" SET BAND F

I

RECEIVE 1ST
ADDR. CHAR.

?
~______~____~~SETF

r--------.1..-----,....-, RECEIVE 1ST
ADDR. CHAR.

~-------r-----L.-...J ~~~E;

B,~------~--~~~RECEIVE SPACE,SET A

RECEIVESPACE,~______r -____~~SETENORECEIVE@ ,RESET F
ENCODE AND
TRANSMITQUALIFIED (2)ANSWER BACKENCODE AND
TRANSMITQUALIFIED @ANSWER BACKGO INTOCONTROLADDRESS
MODE

©,

.-------'-------, RECEIVE
SET A AND B,
L-._ _ _ _ _ _~------...J RESET E
SEND (i) FOR
STATUS,RESET A,RESET ARESET F~------~----~~SETERECEIVE@,RESET F©,RECEIVE
SET A, RESET~______~------~E

NOTE:
HEAVY BLOCKS REPRESENT THE
MODES DURING WHICH A MESSAGE IS SENT OR RECEIVED.
ALL OTHERS ARE USED FORANSWERBACK OR LINE CONTROL.

2740

A SPACEG SPACE/ SPACETERMINAL ADDRESSGROUP ADDRESS
ALL-CALL ADDRESS

2740

2740

2740

B SPACEG SPACE/ SPACEC SPACEH SPACE/ SPACED SPACEH SPACE/ SPACE* GROUP MASTER** ALL-CALL MASTER

Figure 4-10. Normal Mode Flow
2740/41 FETOM(1/69)

4-17

Time-Out 15

The terminal is first placed into text non selectedmode when power comes up (Diagram 5-20). The
The time-out 15 circuit (see Diagram 4-13) operates
terminal waits in text non selected mode until thethe same as in transmit control. It returns the teraddressing sequence begins. When theisminal to control receive mode if more than 15 seconds received and detected in the IB-register, the terelapse between depressions of the I/O-device keys
minal goes into control receive mode. '©', 'notwhile in transmit text mode. For example, if 2740-2
send, ' and 'not operate' condition' set control receive'
memory "hangs up" 'send, ' 'not IB generate' 'notwhich brings up the 'E reset gate' and 'set TNS or
CR' lines (Diagram 5-21). 'Set TNS or CR' turns on
strobe 0, ' 'not operate, ' 'not test (modem), ' andthe' A' and 'B' mode triggers and turns off the 'D' and'IB empty' condition the 15 second time delay circuit.
'F' mode triggers. The terminal is now in control
If all of the preceding conditions exist for 15 seconds(indicating the failure to transmit a character) thereceive mode, awaiting reception of thecharacter.
The
is received and detected in the IB-register,'time-out 15' latch turns on. 'Transmit text' andbringing up 'A reset gate' (Diagram 5-21), which'time-out 15' turn on the' EOT' trigger, causing aplaces the terminal into control address mode. The
to be generated and transmitted and the terminal
reception of thecharacter indicates that the operto switch to control receive mode (freeing the comation is to be addressing and not polling. While themunciation line).
If it has been enabled, time-out 15 is active forterminal is in control address mode, a @,enter operations performed in communicate mode.
terminal address, group address, or all-call address
Pressing the Enter key ('enter 1') inhibits time-out
can be received.
until the key is released. When the Enter key is
If the all-call address (I) is received, the operareleased the first operation must be within 15 seconds
tion is as follows: The' F set gate' line comes up,
and the time lapse between subsequent operations
and the terminal goes into control address selectedmust be less than 15 seconds. 'Time-out 15' resets
mode. The conditions bringing up 'F set gate' are
the terminal to not enter status if no character isslash character detection, 'IB OK, ' and control
keyed or function performed (tab carrier return, etc.); address mode. When the terminal is in control ador if the Line Return, Line Type, or Enter key is not
dress mode, it must be determined whether it is apressed for 15 seconds.
master or a slave. If the terminal is a master,
When power is first turned on, the timer is inactive
only' F set gate' comes up; if it is a slave with
until the terminal transmits an address answerback
status, 'B reset gate' and 'F reset gate' both come up.
or a negative answerback to polling. When enter
Whether the terminal is a master or a slave depends
time-out does occur, the 'reset Nlo' line is brought
upon whether the all-call master jumper is wired.
up to reset the buffer, reset the rekey latch (if set)
If the jumper is wired, the terminal goes intoand return the terminal to not enter status. The
control address selected mode. If the jumper isreset light is turned off when the 'rekey' latch is
not wired, the terminal goes into control address
reset by enter time-out.
selected slave mode. (The difference between allcall master and slave modes is that for the master,
PRINCIPLES OF OPERATION
the 'B' mode trigger is on; for the slave, it is off. )If the group address is received, the preceding
Addressing
operation repeats. Again, determine whether theterminal is a slave or a master. Although different
places the terminal into control receive mode.
circuits are used, the master is determined the same.
If the terminal address is received, no slave orplaces the terminal into control address mode.
master determination is necessary; the terminal
always reacts as a master. As with the group or• Station address character places the selected
all-call masters. 'F set gate' comes up.
terminal into control address selected mode;
While the terminal is in control address selected
unselected terminals remain in control-address
mode, the space character is received in the IBmode.
register. 'Space,' 'B, ' and control address selectedmode bring up 'A set gate, ' putting the terminal into
• Spfl,ce character places the selected terminal intotransmit status answerback mode. In control
transmit status answerback mode.
address selected mode, the terminal can receive
a @ orinstead of space. If a @ is received,• @ places the selected terminal into receive
the terminal returns to text non selected mode.
text mode; unselected terminals to text non·If a
is received, the terminal returns to control
selected mode.
receive mode. If a character other than a space, @or(for example, parity error) is received, the

©

®

®

©

®

©,

• ©
•®

©

©

©

4-18

(1/69)

'F reset gate' and 'B set gate' lines come up to
return the terminal to control address selected
mode.
Transmit-Status/ Answerback (2740-1)• Terminal with status sends a®.

• Terminal without status sends a®.

With the terminal in transmit status answerback
mode, the individual terminal (terminal address) or
the master (all-call, group address) checks its status
and returns an answer to the mUltiplexer. If theterminal has status, a eX) is loaded into the 1Bregister and sent to the multiplexer. If the terminal
does not have status, ais loaded into 1B and sent.
Transmit status answerback mode actually changes
the terminal from a receiving to a sending condition.
The 'send' line comes up and causes the serdes clock
to run continuously as in any transmit mode. Also,
if the terminal does not have status, the alarm bellrings to notify the operator that the terminal has
been addressed.
If the terminal has status, the '1B generate' line
is brought up by 'transmit answerback, ' 'status, ''B, ' and 'not D'. The control clock is started by
the conditions shown on Diagram 5-22. The control
clock outputs, 'CI' and 'C2, ' bring up 'IB set. ''IB set, ' 'IB generate, 'and the other conditions
shown on Diagram 5-22 load thecharacter into
the IB-register. The character then transfers to
the S-register. When 'enter serdes' and 'CI' comeup, the 'end-of-state' trigger turns on. As in basic
machine operation, the 'end-of-state' latch prevents
the IB-register from resetting until the (X) has
caused a mode change.
While @ is in the IB-register, it is detected and'B, ' 'not D, ' 'EOS and not 0, ' and 'transmit answerback' bring up the' E set gate'. 'Transmit answerback, ' 'EOS and not 0, ' and 'B' also bring up the'A reset gate' lines, putting the terminal into control
selected mode. Reception of aindicates to themultiplexer that the terminal has status; the multiplexer returns a @. The @ is detected and, with'control selected, ' brings up 'F reset gate' to place
the terminal in receive text mode (Diagram 5-21).
The terminal is now conditioned to receive thecomputer message.
If a terminal does not have status, a hyphen (Bbit) is loaded into the IB-register. Whether theterminal has status or not, a B-bit is always loaded
into IB (Diagram 5-22). Because the terminal does
not have status, 'IB generate' does not come up,thus preventing any other IB- latch from turning
on. The control clock is started and the 'CI' and

®

GD

®

, C2' outputs bring up 'IB set, , loading the B-bit
into the IB-register. The fact that aand not a
is in the IB-register is detected. 'Not @ "'B, ' 'not D, ' 'EOS andrtot 0, ' and 'transmit answerback' bring up 'F reset gate'; 'B, ' 'EOS and not 0, 'and 'transmit answerback' bring up 'A reset gate;
the terminal goes into control address mode.
The terminal remains in control address mode
until either a @ oris received. The terminal
then goes to either text non selected or control
receive mode.

®

®

©

Transmit-Status/Answerback (2740-2)• Terminal with status sends a qualified QJ• Terminal without status sends a qualified®

With the terminal in transmit status answerback
mode, the individual terminal (terminal address)or the master (all-call, group address) checks its
status and returns an answer to the multiplexer.
If the terminal has status, a qualified
is loaded
into the IB-register and sent to the multiplexer. If
the terminal does not have status, a qualified
isloaded into IB and sent.
In the addressing sequence theis received
first, the E mode trigger is reset, and the terminal
goes into control receive mode. The
is received
next, A mode latch is reset, and the terminal goes
into control address mode. The first address
character received by the terminal sets the F mode
latch for control address selected, and the space
places the terminal in transmit status answerback
mode.
This mode actually changes the terminal from a
receiving to a sending condition. The 'send' line
comes up and causes the serdes clock to run continously as it does in any other transmit mode.
Also, if the terminal does not have status, the alarmbell rings to notify the operator that the terminal
has been addressed.
The 2740-2 transmits two status-answerback
characters. 'Space,' 'B,' and' control address selected' set the '1st status character answerback'latch. ('Not B' prevents this latch from being set
for slave terminals.) 'Transmit answerback,' 'notC2,' 'IB empty,' 'B,' and 'not D' bring up the C1/C2
chain necessary for 'IB set.' 'IB set not EOT, ''transmit answerback, ' and '1st status characteranswerback' bring up the 'load 1st character answerback' line. The conditions determined by the error
storage latc hes or the terminal status (Diagrams
4-5 and 5-22) are ANDed with 'load 1st charactera!lswerback' to bring up the lines required to set thefirst character into the IB-register (Figure 4-11).

GJ

®

©

®

2740/41 FETOM(1/69)

4-19

1st Status Character Set In 1 B-Register

Latches and Bits

1 B2 (A)Diagram 4-5 AND Bloch

1

1 B3 (8)2

12Status Inhibit

not

not

Bid Latch

not

not

No Paper

not

X

~,~

Insert Device Down

X.....::I :0C

Local

'"::I

E

VI

3

1 B4 (4)1

2

1B6 (1)

1 B5 (2)
1

2

1

X

2

3

1B7 (C)
1

Char.

Bit
Configuration

2

not

not

-

not

not

2

X

X

9

1

@

A

8

8

4

4

2
8

C

Q)

>

'Qj0::: .....

X

o 0

",£U

~~
::I

OCC
C ...
,- Q)

Buffer Pr int

X

Communicate

X

X

-

X

1

1

Ett:
.. ::I
Q)cc

Enter

I- '-"

Status

X

X

X

X

X

X

-

Space

Electronic Error

not

not

not

X

*

/

A

1

C

not

not

X

*

S

A

2

C

not

X

*

U

A

4

C

Trans, Parity Error

®
®
®
®

*

Y

A

8

C

Load 1st Character Ans, back

X

X

-

...c
..... '"
::I

~E
VI
o

C

I/O Error

Q)>

Receive Parity Error'E 'Qj'- u
Q)Q)

I- 0:::

Note:

X
X

X

X

X

X

X

X

X

X

X

X

® Any error condition through on OR block with receive status.
*

Figure 4-11.

The C Bit is set because the terminal has receive status.
1st Status Character Set in lB-Register

The control clock is started and 'send' brings up
serdes clock (Diagram 5-22) to transmit the' 1st
status character answerback. 'With the first character in the 1B-register, 'lB
full' caused the response character to be set into
S-register and serialized out to the communications
line. 'Transmit answerback,' 'enter serdes,' and'C1,' set the 'EOS' latch. 'Transmit answerback, ''EOS and not 0,' 'not enter serdes,' and '1st statuscharacter answerback' bring up 'lB reset' to clear
the status sense character from the 1B-register.
'lB reset,' 'end of state, ' and '1st status characteranswerback' set the '2nd status character answerback' latch.
If the terminal has receive status, the no error
or error condition of the previous message is definedby the 1st status character answerback which precedes the <X>. If the terminal is without receive
status, the "non-status" condition is defined by thesense character followed by a'Transmit answerback,' 'B,' 'not D,' 'not C2,' and'lB empty' start a second C1/C2 chain for the 2nd
status character. 'C1,' and '2nd status character

®.

4-20

X

(1/69)

answerback reset the '1st status character answerback' latch and the second character response is
set into 1B-register by 'not 1st status characteranswerback' and either 'initiate 1B1-B bit' (or 'initiate IB generate·' (The '2nd statuscharacter answerback' latch is reset when theor <X> is set into the S-register.
Mode changes are allowed only by the signal, 'not
1st or 2nd status character answerback', whichcomes up after the 2nd character response. If the
1st response character precedes a,'1st or 2nd
status character answerback' inhibits' A reset gate'
and 'F reset gate' until the terminal sends the(Diagram 5-22). After theis transmitted theterminal goes to control-address mode.
After the <X> is sent by a terminal with status,
it goes to control-selected mode. 'Not 1st or 2nd
status character answerback,' and 'EOS and not 0'
bring up 'end of status answerback.' 'EOS answerback,' , <X> " 'B,' 'transmit answerback', and 'notD' bring up 'E set gate.' 'A reset gate' is broughtup the same as after a
response.
Thus the error conditions stored, and the status

®)

® ).

®

®

®

®

®

and mode of the terminal are used to set up thequalifiedoranswerback for the CPU program.
The program decodes the status sense character todetermine what processing should follow. For example, the program may retransmit the previous
message or poll the terminal for a message before
readdressing it.

®

®

Polling• © places the terminal into control receivemode.
• The station address character places the selected
terminal into intermediate polling mode.

ation, a station address character is received andis recognized to place the selected terminal into
intermediate polling mode.
The next polling-sequence character, space,arrives. If any character other than a space oris received, the terminal returns to text nonselected mode. A
causes it to go to controlreceive mode. If the operator has pressed the Bidkey (indicating a desire to transmit), the space
places the terminal into transmit text mode bybringing up 'F reset gate' and 'B reset gate'.
Because the 'bid' trigger is on, a @ returns to
the multiplexer. The @ is sent exactly as it isin the basic terminal.
If the operator has not pressed the Bid key, thespace places the terminal into transmit pollanswerback mode by bringing up 'B reset gate' •©

©

• If the Bid key has been pressed, the space char-acter places the terminal into transmit text
mode and a @ is sent.
• If the Bid key has not been pressed, the spacecharacter places the terminal into transmit
poll answerback mode.
• In transmit poll answerback mode, a ®
returns to the multiplexer.
As in addressing, the terminal is first placed intext non selected mode when power comes up (seeDiagram 5-20). The first polling-sequence character, ©, places the terminal in control receive
mode (Diagram 5-23). In control receive mode theterminal can receive a@'or station
address character. Because this is a polling oper-©,®,

Transmit Poll Answerback
Transmit poll answerback mode indicates to theterminal that the o~rator has not pressed the Bid
key; therefore, a ® (B-bit) returns to the multiplexer. The
is loaded into lB when 'lB set'is brought up by the control clock (Diagram 5-24).
The control clock is started by 'transmit answerback,''not B,' 'lB empty,' and 'not C2'. When 'enter
serdes' comes up, the 'end-of-state' latch turns on
to prevent the reset of lB until the character has been
sent. When the ® has been sent, 'not B, ''transmit answerback, , 'not D, ' and 'EOS and not
0' causes the terminal to return to control receive
mode.

®

2740/41 FE TOM(1/69)

4-21

SECTION 6. RECEIVE INTERRUPT (2741)• While in receive mode, the terminal sends a 200
ms "space" to the multiplexer to allow the terminal to go into transmit mode before completionof the multiplexer message.
• The terminal must be connected to the multiplexer
on full-duplex lines.
This feature is used only when the terminal is in thereceive-text mode. If the operator wishes to stop
the mUltiplexer from sending, he presses the
Attention key to place a 200 ms "space" on the' serial
data out' line. The multiplexer senses the long spaceand sends acharacter back to the terminal. This
places the terminal into transmit text mode and theterminal sends a @. The operator can now send
new instructions to the multiplexer.
Diagram 5-10 shows the interrupt logic. If theoperator presses the Attention key while the terminal
is in receive text mode, the 'interrupt' trigger turns
on. 'Interrupt' and 'not power on reset' start a 200

©

4-22

(6/70)

ms single shot. The output of the single shot, ANDed
with 'not A' and 'B, ' transmits the 200 ms "space"to the multiplexer. When the Attention key is released, the N/ C contact makes, turning off the'interrupt' trigger and the 'IB' latch. The 'IB'(inhibit interrupt) latch acts as an interlock toprevent the terminal from sending a "space" whenthe Attention key is pressed (to send awhile theterminal is in transmit text mode.
The 'halt I' line is also an interlock. 'Halt I'
prevents the terminal from going from transmit
text mode to receive control mode. The 'EOT'
trigger is not allowed to turn on until the 'interrupt'
trigger is reset by releasing the Attention key.
otherwise the terminal would hang up in receive
control mode.
In order to use this feature, the terminalmust be connected to the multiplexer on full-duplex
lines. This is necessary so that the terminal
can send the "space" at the same time that it isreceiving data.

©)

SECTION 7. TYPAMATIC (2741)• Permits automatic repeating of space, underscore/dash, or backspace.
• Repeating is accomplished by circuitry.
• The transmission character is loaded into 2B.
• I/O device is synchronized with the S-register.
The typamatic feature causes the 2741 to automaticallyrepeat I/o cycles if any of the typamatic keys areheld depressed. For example, if the operator
presses and holds the Space key, the I/O device continues to space until the Space key is released. If
any typamatic key is pressed, but not held, a single
I/O cycle occurs. In the standard SELECTRIC ®
repeating is made possible by mechanical changes
to the SELECTRIC. For the I/o SELECTRIC, however, repeating is accomplished by circuitry.
Circuits must be used because the unrestricted
speed of the I/o device can overrun the terminal
logic. Therefore, the I/o device must by synchronized with the operation of the S-register.
During a sending operation, the character that is
set up in the I/o transmit contacts is loaded into the
IB-register. From the 1B-register the character isloaded into the S-register and sent. With the Typamatic feature installed, the character is also loaded
into the 2B-register (Figure 4-12). The characterin 2B, however, does not print until the 'print-out'line comes up. During a sending operation, the'print-out' line can come up only when the operator
presses and holds a typamatic key.

Figure 4-12. Typematic Data Flow

The character in 1B is loaded into 2B at the sametime as the character is loaded into the S-register.
'2B set' is brought up by the conditions shown on
Diagram 5-11. The principle condition is 'enter
serdes, ' which is also the principle condition toload the S-register.
In addition to the normal set of contacts, thetypamatic keys have another set of contacts fortypamatic operation (the Underscore/Dash andBackspace keys share the same set of tYpamatic
contacts). For the typamatic operation to begin,
the key must be held at least 100 ms. The 100 ms
delay, in addition to ensuring that the key has been
held and not just pressed, ensures that any characterin 2B has had time to reset.
When a typamatic key is pressed and held, the
100 ms delay times out and, with 'not I/o cycle' and'2B full, , turns on the 'type' trigger (Diagram 5-11).
The 'type' trigger does three things: (I) frees theprintout circuit, (2) disables the 2B-overflow reset
circuit, and (3) brings up 'incorrect case' to prevent any shift during the typamatic operation.
The character is printed normally the first time.
As soon as the operation is completed (indicated by'not I/o cycle'), the 'type' trigger turns on and the'print-out' line comes up, transferring the characterin 2B to the I/O magnets, just as in a receiving
operation. The cycle repeats as long as the 'type'
trigger is on. When the typamatic key is released
and the last character is transferred out of 2B, the'type' trigger turns off.
The Typamatic feature also causes one otherchange in basic 2741 logic. In addition to the normal
2B-reset conditions, the 'TOM (typamatic) 2B reset'
trigger is added (Diagram 5-11). The 'TOM 2B
reset' trigger causes the 2B-register to reset during
the following times:
1. When the Attention key is pressed during a sending operation (transmit EOT).
2. When the terminal is in control receive mode.
3. When the terminal is placed into local (off-line)
while sending.
4. When the Carrier-Return key is pressed (causing
an automatic EOT) during a sending operation.

2740/41 FETOM(1/69)

4-23

SECTION 8.

BUFFER EXPANSION (2740-2)• Increases buffer capacity from 128 to 256 or
448 characters.

4-24(4/68)• See "Buffer Address Register" in Functional
Units chapter.

SECTION 9. BUFFERED RECEIVE (2740-2)
Buffered receive differs from receive text after thereceived character enters the 2B-register. The '2B• Characters received from the communication line
full' line, which normally causes an I/O cycle byare stored in buffer storage.
gating the decoded contents of 2B to the printer magnets, raises the 'memory go' line instead (Diagram• There is no printing while receiving from the line.
5-38). 'Inhibit print out' prevents the I/o cycle. The
buffer storage address resets during the mode change
to receive text so the first character cycle stores• 'Parity error or not S8' rings the bell and turns on'error' while red~iving. A "-" stores in place ofthe first received character at the first buffer storage character address.
the error character.
The 'memory go' line starts buffer storage timing• No incorrect case error detection while receiving.
by stepping the bit counter to zero and advancing thecharacter address to 1. Buffer address time 0' gates
the B-bit from '2B1' to the 'memory buffer' trigger.
• The message is not printed if an error is received.
The read time of 'buffer address time 0' clears the
The Buffered Receive feature adds circuits to inhibit
first core at character address 1; a binary one inprinting and enable storing during receive text and'memory buffer' sets a 1 in the core during write
provides for three additional buffer address resets:time (Diagram 4-18). The 'memory buffer' trigger
resets at 'CC2-' when write current stops. The other(1) at the beginning of receive text, (2) when © does
six character bits follow.
not follow a received message, and (3) at the end of
The 'buffer 2B reset' trigger turns on at 'buffer
on-line buffer print starts only whenis received.
address time 7' and 2Bresets; the '2B full' line drops
Buffered receive from the 2B-register into buffer
storage is described in this section (Refer to "Receive" and 'memory go' goes down (Diagram 5-38). The
buffer storage character cycle ends in 'buffer address
in Chapter 3 for the receive operation from the comtime 7' and memory circuits wait for receive circuits
munication line to the 2B-register.) Section 3,"Buffer Print," describes the transition from buffered
to set another character into 2B.
There is little chance that the 2B overflow reset
recei ve to buffer print.
will ever function with the Buffered R ecei ve feature
installed.
Store Received Characters (Diagram 5-38)• 600 bps Speed Base feature is required.

©

• Buffered receive is similar to enter.

Receive Text Buffer to Buffer Print• 'Receive text buffer' is the main control line.

• Buffered Receive stores only characters received
in receive text mode.

• Functions of 'receive text buffer':a. Inhibit printout from 2B
b. Gate 'memory go' linec. Gate 2B to 'memory buffer' trigger
d. Inhibit incorrect case error.
e. Gate 'buffer 2B reset' trigger• Characters received in receive text mode
exceptare stored.

®

• Parity checked in store circuits and by VR C
circuits.

• ® is not stored; © is stored.
• © Starts buffer print (refer to "Buffer Print"
in Chapter 3. )When the 2740-2 acknowledges the received message with ® during transmit check answerback, thecentral processor does not respond with
Instead,the central processor immediately begins to retransmit the message. The 2740-2 changes modes toreceive text and, because the 'reset buffer address'
trigger is on, resets the buffer address. 'Receive
text buffer' again causes the storing of received characters in buffer storage, starting at character
address 1.

©.

2740/41 FETOM(4/68)

4-25

SECTION 10. HEADER CONTROL (2740-2)• Allows repetitive header information to be transmitted at the beginning of each message.
• Predetermined number of positions (28 maximum)
wired to customer!3 requirements.
• Buffer address register reset to zero in transmit
text mode.
• Buffer address register reset to wired value inall other operations.
• Normal operation with Header switch off.
The terminal operator may wish to transmit the same
information at the beginning of each message. When
the Header Control feature is used, it is necessary to
key in desired data only once. Information changes inthis area must be made by rekeying the entire header.
Once the header has been keyed, switch control allows
the buffer to automatically start at the end of theheader area for subsequent keying. Transmissions
include the data in the header area. All positions of
the header must be filled with characters and/or
spaces. If the terminal power is turned off, thebuffer information is destroyed.
The customer determines the fixed number of
positions to be reserved at the beginning of buffer
for header information. The machine is wired
accordingly, with a maximum of 28 (groups of 4).
This is done by using 6 jumper positions, three of
which control the set of'buffer address' triggers 6,
7, and 8 (binary values of 4, 8, and 16 respectively).

4-26(4/68)The three other positions a;re used to wire the'not buffer address' lines and redefine 'buffer
address empty' (Diagram 5-45). The 'buffer
address empty' must be satisfied for information
to be entered. During a header control operation
the buffer address is not zero when the first character is entered., Therefore, the proper 'notbuffer address' jumper positions are wired for
the 'buffer address empty' to be satisfied withthe desired header address set in the address
register.
The 'header storage buffer address set'
trigger is turned on by 'reset buffer address' if
the Header switch is on and the terminal is not, in transmit text mode. During any enter operation,other than transmit, this trigger causes the addressof the first non-header character to be set in thebuffer address register. With the switch off 'notheader N/O l' holds the trigger off for normal
terminal operation and keyed data may be enteredinto the header area of the buffer and read backfor verification. Turning the switch on prevents
entering characters into the header area. 'Transmit text' resets the 'header storage buffer address
set' trigger and allows the address to reset tozero for transmission of all data.

SECTION 11. DOCUMENT INSERTION (2740-2)• Provides automatic mechanical actions.
• Status is down from beginning to end of document
insertion.
The four mechanical functions involved in the I/O
printer document insertion are as follows:
1. Document guide is opened manually to guide theinsertion of a ledger card from the front of theplaten.
2. Feedrolls that are lowered automatically.
3. Document guide is manually closed to process
document.
4. Feedrolls that are raised automatically.
In the I/O printer, a mechanical feedroll latch identifies the feedroll positions. A feedroll cam drives
the feedrolls up or down. The positions of the document guide and feedroll latch control 'insert card'and 'latch in' lines to generate associated document
insertion functions (Diagram 5-46).

When the document guide is opened, 'insert card'comes up. This turns on 'drive down' because thefeedrolls are still up and 'latch in' is up. 'Drive
down' starts the I/o motor, drops status, locks
the keyboard, and energizes the cycle magnet.
'Insert card' and 'not drive up' energize the feedroll latch magnet. The feedroll cam rotates andthe mechanical latch comes out--the feedrolls
are lowered. With the mechanical latch out 'drive
down' turns off. Mter the card is inserted andaligned, the guide is closed. 'Drive up' is turned
on with not 'insert card' and not 'latch in'. The
cycle magnet is energized again to raise the feedrolls. 'Latch in' comes up when the feedrolls
are up and turns off 'drive up'.
'Drive up, ' 'drive down, ' and 'insert card'overlap so that at least one of them at all times is
up during document insertion. These lines are
ORed to hold status down, keep the keyboard
locked, and cause the I/O motor to run during
the entire operation.

SECTION 12. SPLIT PLATEN (2740-2)• Provides a two-section platen on the I/o printer.
The Split Platen is a two-section platen that facilitates
dual-document printing. It allows independent linespacing of the right-hand document, controlled by
the central processor. The left lmob is pulled out tosplit the platen, and pushed in to re-join it. The rightknob operates the conventional platen vernier.

The mechanical operation of the Split Platenfeature is explained in Appendix D. The 'split
platen' latch (Diagram 5-46) turns on when the left
hand platen knob is pulled out. The latch turns on
the Split Platen light and locks the keyboard. The
terminal returns to normal when the platen isrejoined by pushing in the left hand platen knob.

2740/41 FETOM(4/68)

4-27

SECTION 13. TELEGRAPH (2740-2)• Enables thp 2740-2 to bp uspd OVf'r telegraphsystems.
The Telegraph feature requires two changes tonormal 2740-2 circuits: (1) the serdes oscillator
frequency is reduced to 300 Hz to match the 75 bps
line, and (2) a special telegraph line adapter isused (Diagram 5-47, Sheet 5).
The telegraph line adapter consists of two relays:
receive and transmit. The receive relay coil isconnected in series with the transmit relay N/C contacts, across the telegraph line. The telegraph line
adapter operates on a current loop line. Current
flowing indicates a mark level (or bit); no current
flowing indicates a space level .(or no bit).
The receive relay monitors the line, and ispicked when current is flowing. This causes thereceive relay N/ C contacts to open and a bit isindicated to the terminal logic. The normal condition of the telegraph line (no data being sent or
received) is current flowing.
When the terminal is sending data, the transmit
relay coil follows the inverted condition of the'Serial Data Out' line, that is, a bit does not pickthe relay but a no-bit does. Picking the relaycauses the N/C contacts to transfer, putting a no-bit
on the line; not picking the relay allows current toflow and a bit is put on the line.
NOTE: The removal of the relay will open the current loop to
all terminals on that line. A manual shunt switch, installedon the adapter, will provide an alternate current path, when
operated. This switch must be operated to 'shunt' anytime
the relay is to be removed.

SECTION 14. SPEED BASE--600 BPS (2740-2)• Allows transmission and reception of data at
600 bps.
• One oscillator is used for both the serdes andcontrol clocks.
• Frequency to the serdes clock is reduced by ahigh speed frequency divider circuit.
The Speed Base feature increases the transmission
and receiving speed of the 2740-2 terminal. This
enables increased throughput for the system andreduces the time that each terminal ties up thecommunication line. This feature requires threechanges: (1) the frequency of the serdes and control
clocks is changed,(2) a higher speed line adapter isused, and (3) buffer receive must be installed.

4-28(4/68)A single oscillator, running at 9.6 KHz, is used forboth the serdes and control clocks. The output of thisoscillator is fed directly to the control clock, and while
it is slower than normal oscillator frequency, it isstill fast enough to operate the terminal logic. The
output of the oscillator is not fed directly to the serdes
clock. A frequency reduction network is inserted
between the oscillator output and the serdes driving
pulse ('SDMV' )--dotted area on Diagram 4-2. This
network reduces the oscillator frequency by four to
2.4 KHz, allowing 600 bps operation.
IBM Limited Distance Type 2, an IBM Leased Line,or a Western Electric 202D (or equivalent) data set
is used for attachment to the communication line. Theinterface is shown in Diagram 5-47, Sheet 5.

SECTION 15.

EDIT (2740-2)• Pressing Line Type key causes the buffer to readout and print until a carrier return character isreached.

• Line Type key causes a single print line to typeout.

• '2B upper case' keeps track of the shift of printed
characters.

• Line Return key causes the memory address togo back to the beginning of a print line to beerased from memory.

The line type operation is performed as follows: theoperator initially presses the Enter key and types amessage. Press Enter key again. This stores thestop code, resets the buffer to the starting positionand sets up the line type circuits.
Pressing the Line Type key causes circuits toprint a line of characters and to search for a carrier...
return or a stop code. When either is reached, theoperation ends. Another depression of the Line
Type key causes another search (assuming a carrier
return and not a stop code ended the previous operation). When the stop code is reached, the enter
trigger is turned on and further depressions of theLine Type key have no effect. The Bid key can bepressed following any line type operation, and themessage, as printed, up to that point is transmitted.
Refer to Diagrams 5-39 and 5-40 for the following. With the terminal in enter mode, pressing theEnter key causes the 'reset buffer' trigger to turnon. 'Reset buffer' initiates a check of the I/O
printer shift. If the I/O printer is in upper case, it
shifts to lowercase. The 'strobe' signal is inhibited,
however, so the lowercase character is not stored.
'Reset buffer' also turns off the '2B upper case'latch to ensure that the I/O printer and the terminal
are synchronized. The 'store stop code' trigger
turns on causing a stop code to load in the next position of memory. 'Reset buffer' and '2B full' (thestop code in 2:B~) turn off the 'line type inhibit' latch
to allow the line type operation to be performed.
Upon completion of the shift (if one was required),'reset buffer address' turns on causing the buffer tore set to the starting position. The term inal is now
prepared to do a line type operation.
Pressing the Line Type key turns on the 'line type'
trigger. 'Line type' causes the 'buffer print' trigger
to turn on and then the 'enter' trigger to turn off.
'Buffer print' and '2B empty' bring up 'memory go',causing a character to read out of memory and load
'into the 2B-register. While in the 2B-register, thecharacter is examined to see if it is an uppercase
shift, lowercase shift, carrier return, or a stop
code character. If none of these, the characteris printed. If the character is an uppercase character, the '2B upper case' latch turns on and theI/O shifts to uppercase.. If the character is a lowercase character, the '2B upper case' latch turns off
and the I/O shifts to lowercase. '2B upper case'keeps track of the shift of the characters as they are• Enable enter time out is effective only after anaddress answerback or a negative answerback
to polling.
The Edit feature allows the terminal operator toverify and correct message data before it is transmitted. By pressing the Line Type key, the operator can initiate a line-by-line printout of the message entered. If an error is discovered following
an enter or line type operation, memory can bebacked up to the previous carrier return by pressing
the Line Return key. The error can then be corrected by retyping the error line. If line return isused during the line type operation all subsequentlines of the message must also be retyped. Afterthe operator is sure the message is correct, theBid key is pressed and the message is transmitted
when the terminal is polled. The Edit feab....... 1b
operable in the local or communicate mode.
Once enabled, a 15-second timeout is effective
for enter operations in communicate mode. Therefore, if the Edit feature is to be used, the timeout
must be considered and the operator must perform
an operation within 15 seconds. A character must
be typed, function performed, or the Line Type orLine Return key pressed to prevent a terminal reset
to not enter status. Holding the Line Type key orLine Return key depressed inhibits the timer fromtiming out. If the operator wishes to inhibit theenter time-out (while talking, etc.) she should holdthe Line Type key pressed if the Edit feature is
installed. PreSSing the Enter key inhibits the timeout, but it also resets the buffer.
When the terminal is initially powered on, thetimer is inactive until the terminal transmits anaddress answerback or negative answerback topolling. The buffer address is reset, 'rekey' latch
reset (if set), and 'enter' trigger reset by a timeout condition. The reset light is turned off whenthe 'rekey' latch is reset by the timer.

LINE TYPE• Stores stop code and resets buffer starting position by pressing Enter key while in enter mode.

2740/41 FETOM(1/69)

4-29

printed. After the character is reset from the 2Bregister the next character is read out of memory.
Detect Carrier Return
The preceding operation is repeated until a carrier'return or stop code character is detected in the 2Bregister. If the CR character is reached the 'edit
control 3' trigger turns on. The carrier returnoccurs. 'Edit control 3' then turns off the 'buffer
print' trigger. If the I/O is in uppercase, it shifts
to lower case. When the I/O is in LC, the 'enter'trigger turns on. 'Enter' and 'edit control 3' thenturn off the 'line type' trigger, following which,'edit control 3' turns off. The circuits are still set
up for line type, and pressing the Line Type key
will cause printing until another carrier return isdetected.
Detect Stop Code
When the stop code character is reached, the' edit
control 3' trigger turns on. 'Edit control 3' and'stop code' then turns on the 'line type inhibit' latch.
Because a stop code was detected, back up thebuffer one position for the next entered character tostore in place of the stop code. The stop code,
however, remains in storage until another characteris entered. 'Stop code', 'line type' and 'bfr. adr.
time 7' turn on the 'reverse count sequence' trigger
which causes the memory to backup one position.
Following the backup of memory, (1) the 'buffer
print' trigger turns off, (2) the I/O shifts to lower
case (if in upper case), and (3) the 'enter' trigger
turns on. The 'line type' trigger then turns off and
one "CC" pulse later, 'edit control 3' turns off.
At the end of any line type operation, the Bid key
can be pressed. If the terminal is in communicate
mode, the information printed out up to that point istransmitted. If the terminal is in local mode, theinformation is printed. To meet the conventions ofterminal operation, insert a lowercase shift character
prior to the stop code if the preceding information isin uppercase. If the last printed character was inuppercase, the '2B upper case' latch will be on.
Depression of the Bid key causes the' store stop
code' trigger to turn on. 'Store stop code' and '2Bupper case turn on the 'store lowercase code' latch,which brings up 'edit 3'.
'Edit 3' causes the following:
1. The lowercase character loads directly into the'memory buffer' trigger.
2. The 'memory buffer gate' is blocked so that thestop code sitting in 2B can not yet be stored.
3. The buffer parity circuit is blocked.
4-30(1/69)

When storing of the lowercase character is completed, the stop code, held in the 2B-register isstored. The' 2B uppercase' latch is reset followed
by 'store lowercase code'. The buffer resets to thestarting position and normal buffer print or transmit
operation can begin.
LINE RETURN• Buffer initially backs up one address position andgoes forward one position to read out the character.
• Following the initial back up, buffer backs up two
address positions and forward one position toreadout.
• Back up ends when a carrier return is detected or
beginning of memory is reached.
Following an enter or line type operation, memory
can be backed up to the previous carrier return bypressing the Line Return key. Subsequent depressionsof the Line Return key cause memory to back up one
line at a time, until the beginning of memory isreached. The buffer address is initially stepped backone position and then read forward so the charactercan be examined to determine if it is an uppercase
or lowercase shift character. The first character
read out (last character of print line could be a
carrier return; if so, detection is prevented by the'reverse count once' latch.) The character is readout to be examined. The buffer is then backed up
two positions and a character read out. Again thecharacter is examined. This process continues,
back up two and read out one, until a carrier returnis detected. Information can then be entered tocorrect any errors. Figure 4-13 shows the sequenceof buffer operation for line return.
Operation
If the 'line return enable' latch is set, pressing
the Line Return key turns on the 'line return' trigger
which then turns on the 'line type or line return'latch (Diagram 5-43). If the I/O is in uppercase, it
shifts to lowercase. The strobe pulse from the I/o
is inhibited, however, so the shift character is notstored.
Before the 'line return' trigger turned on, both
'edit control l' and 'edit control 2' were held off.
When the 'line return' trigger turns on, 'edit control
I' turns on at the next 'CCl' pulse. 'Edit control l'causes the 'reverse count sequence' trigger to turnon and, with the 'reverse count once' latch off, turns
on the 'edit control 2' .latch. The 'reverse countCharacter Position
Character In Memory

12

13

14

15

16

17

18

CR

UC

E

LC

d

i

t
Back Up 1

19

I
I

"-

[Read Out
Beg;n Une Re turn offe':t'::' __ -l'2B Uppe<ea.
Back Up 2[~,~d Out
Back Up 2- - - - -ll~ ReadOutlid-----lII

Bock Up 2

L~ad 1Out':!o~.:.:l
Back Up 2I

m on '2B Uppe<ea .. 'Back Up 2

Read Out"E"-- --lRead Out"UC" - - Turn off '2B Upp ercase'

Back Up 2
Read Out
"CR"
----~

L E n d of Line Return '2B Uppercase' off.
Figure 4-13. Line Return Buffer Operation

once' latch off, allows buffer to back up only one
address for the first character to be read out. 'Line
type or line return,' 'lower case 1, ' and 'not edit
control l' (with other conditions) turns on the'buffer print' trigger. 'Buffer print' (main condition)then turns off the 'enter'trigger. 'Buffer print' and'2B empty' bring up 'memory go' and a character isread out of memory and loaded into the 2B-register.
The character is examined and if the character is:

Following read out of the first character, allow
buffer to back up two address positions so the character just read will be skipped and the next character
addressed to be read. The 'reverse count once'
latch is turned on and further operations of 'edit
control 2' and 'edit control l' result in a back up of
two positions.

1. An uppercase shift, the '2B upper case' latch

The back up operation is as follows: When the character from storage is in the 2B-register, the 'buffer
2B reset' trigger turns on. This causes the character to reset from 2B and the 'edit control 2' trigger
to turn off. The first 'CCl' pulse following the turnoff of 'edit control 2' turns on 'edit control 1'. The
next 'CC2' pulse turns on 'reverse count sequence'.

turns off;
2. A lower case shift, the '2B upper case' latchturns on;
3. A carrier return, the operation is not ended-recognition of the character is prevented(explained later).

Back Up Control

2740/41 FETOM( 1/69)4-31

'Reverse count sequence', 'not buffer address
empty', and the next' CC1' pulse turn on 'reverse
count sequence control', which supplies the buffer
back up pulse (Diagram 4-16). As long as 'edit
control l' is on, pulses to back up the buffer are
generated. For the initial back up 'reverse countonce' and 'edit control l' on turn on 'edit control
2', allowing only one back up pulse. For all backups after this, another circuit turns on 'edit
control 2'. The sequence for backing up two positions differs in one way: the turn on of 'edit control
2' is delayed enough to allow another back up pulse
to occur. During the back up operations, 'edit

4-32(4/68)

control l' on 'not edit control 2' block 'memory
go' preventing the read out of a character. The
details of this operation are shown on the timing
chart (Diagram 5-;4:4).
Detect Carrier Return
When a carrier return is read out of memory andloaded into 2B, it is detected and turns on the 'edit
control 3' trigger. H this is the first character readout of memory, 'edit control 3' is prevented fromturning on by '2B6 or rev ct once'.

SECTION 16.

2760 ATTACHMENT FEATURE

INTRODU CTION• The 2760 attachment feature provides the necessary interface and control signals between the2740-1 and the 2760.
• The feature allows the attached 2760 to use thecontrol circuitry of the 2740-1.
• The 2760 is an I/o device attached to an IBM
2740-1, serial number 15000 or higher.
• Certain features cannot be installed on an IBM
2740-1 if the 2760 attachment feature is used.
The 2760 attachment feature allows one IBM 2760
Optical Image Unit to be attached to an IBM 2740-1.
The 2760 utilizes the control circuitry of the 2740-1
to transmit data to, and receive data from, a central processing unit, via a multiplexer. When the2760 is attached, the 2740-1 is always in terminalto-multiplexer mode of operation. The 2760 can beplaced on a customer-provided desk or table locatedat a distance of up to 8 feet from the 2740-1. All
signals between the 2740-1 and the 2760 are at dc
levels. The ac power required by the 2760 is provided by a cable from the 2740-1.

Record Checking (prerequisite)
Auto EOB
Auto Disconnect (World Trade only)
Dial-Up Adapter
IBM Line Adapters
IBM Modems
The station control and transmit control special
features cannot be installed on the 2740 terminal
if the 2760 attachment is used.

IBM 2760 OPTICAL IMAGE UNIT
• An operator-oriented component used to communicate with a remote central processing unit via
the IBM 2740-1.
• Interlocking allows alternate operation of the2760 and the I/O Selectric without interference.
• Screen and probe used for on-line data selection
and transmission in conversational mode.
• Data is represented on an overlay and an image
projected on the screen.
• Response points are defined by coordinates andrepresent specific data in each program.

IBM 2740-1 Communication Terminal,
Serial 15000 or Higher, with Record Checking
The IBM 2760 Optical Image Unit is an I/o device
used with an IBM 2740-1 Communication Terminal.
Basically, it is a data entry device that operates
on-line, in conversational mode, with a programmed
computer system. Only one 2760 can be attachedto each 2740-1, and in order for this to be done, the2740-1 must have serial number 15000 or higher andmust already have the record-checking feature installed.

Special Features
The IBM 2760 Optical Image Unit attachment will
operate with any of the following special featuresinstalled on the 2740 terminal:• Projected information is stored on a 16mm
filmstrip contained in a cartridge.
• Film movement is under computer program control.
• Manual Frame Advance allows film movement by
the ope rator also.
• An Image Index Counter permits the central processing unit to check film movement accuracy.
The IBM 2760 Optical Image Unit (Figure 4-14) is an
input/output, operator-oriented component used withan IBM 2740 Communication Terminal, ModelL
Only one IBM 2760 is attachable to each IBM 2740-1.
The operator need not have any keyboard skill or any
knowledge of program mingo Card punching and2740/41 FETOM(9/69)

4-33

Figure 4-14.

liM 2760 Optical Image Unit Attached to liM 2740- 1 Communication Terminal

processing are also eliminated. The user has thecapability of communicating directly with a remotely
located computer by using illustrations or any combination of numbers, letters, words, phrases, andsentences in his own language. The lack of computeror program knowledge has no effect upon the proficiency of an Opti cal Image Unit operator as he selects items or operations properly displayed inwords, numbers , and/ or pictures .
Interlocking
The 2760 input occurs when the operator presses
the spring-loaded tip of the RF probe on one of the
243 response points. Three of these are utility

4_34(9/69)

response points (labeled, as shown in Figure 4-15),
and the other 240 points are for data entry. The
2740-1 keyboard is also used for data entry, but any
given input message must come from only one of thetwo sources. These two I/o units share the 2740-1
terminal control unit and they cannot operate simultaneously.
The sequence of the alternate operations isplanned by the system designer and placed undercontrol of the CPU program. While either unit isoperating, the other unit is interlocked to assurecompletion of the operation in process. The control
unit must be released before subsequent operations
can be initiated.

Figure 4-15.

Probe, Screen, and Operator's Consol e

Response Point Coordinates
The vertical (V) and horizontal (H) coordinates are
given character assignments for transmission andapplication program definition purposes. These
coordinates are stored in V (vertical) and H (horizontal) registers until transmitted.
Figure 4-16 shows the V and H coordinatesassigned to each of the 240 possible data response
points on the entire screen (the projection screen
plus the auxiliary screen). The V coordinate istransmitted first over the com munications line.
Filmstrip Motion Control
Images are stored on 16-millimeter filmstrips, inindividual plastic cartridges which are manuallyloaded by the operator as required by the application.

The Optical Image Unit handles only one cartridge
at a time, selecting and displaying images underprocessor control.
The application program for a given filmstrip iscalled into computer storage when the filmstrip is
identified by the operator's (title) frame of the filmstrip. Subsequent images are selected and displayed
in a sequence specified by the application programfor given operator responses. Each filmstrip may
contain up to 12 8 images.
Film movement is under computer program control, and the 2760 is equipped with an electronic
Image Index Counter that perm its the stored program to check the accuracy of film movement.
The CPU program has the capability of allowing
the operator to manually move film, one frame ata time. The Image Index Counter still maintains
image count information for the CPU program.

2740/41 FETo.M(9 / 69)4-35

- - - - - - - - - - - - - - - - - H o r i z o n t a l Positions

L.o'

I
L

------------------.,;,.-----.1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

15

Id

1m

lu

14

Ic

II

It

13

Ib

Ik

Is

12

la

Ij

1/

II

1&

I..,

I@

21

I

t5

td

tm

tu

t4

tc

tl

tt

t3

tb

2

tk

ts

t2

to

tj

tl

tl

t&

t-

t@

3

35

3d

3m

3u

34-

3c

31

3t

33

3b

3

3k

3s

32

3a

3j

31

31

3&

3-

3@

8

b5

bd

bm

bu

b4

bc

bl

bt

b3

bb

bk

bs

b2

ba

bj

bl

bl

b&

b-

b@

K

k5

kd

km

ku

k4

kc

kl

kt

k3

kb

5

kk

ks

k2

ka

kj

kl

kl

k&

k-

k@ k space

S

s5

sd

sm

su

54

sc

51

st

s3

sb

6

sk

55

52

sa

sj

51

51

5&

s-

s@

2

25

2d

2m

2u

24

2c

21

2t

23

2b

7

2k

2s

22

2a

2j

2/

21

2&

2-

~

A

a5

ad

am

au

a4

ac

al

at

a3

ab

8

ak

as

a2

aa

aj

al

al

a&

a-

a@ a space

J

j5

jd

jm

ju

j4

jc

jl

jt

j3

jb

9

jk

js .

j2

ja

ii

jl

jl

j&

j-

j@

I

15 Id

1m

lu 14

Ic

II

It

13

/b

10

/k

Is

12 la

Ij

II

II

1& 1- I@

15

ld

1m

lu

14

Ic

11

It

13

Ib

II

Ik

1s

12

la

Ij

1/

11

1&

1-

1@

&5

&d

&m

&u

&4-

&c

&1

&t

&3

&b

12

&k

&5

&2

&a

&j

&/

&1

&&

&-

&@

D

M

U

4

C

L

T

3

B

1K

S

2

A

j

/

Auxiliary Screen

Vertical Positions

I
I

T(V) Vertical
Coordinates·

I

I
I

I

&

@-

I

UNLOADLOAD

s space
I

I

END
ENTRY

(H) HorizontaI
Coordinates*

Image Screen• Shown in upper case for ease of reading. The 2760 operates in lower case shift automatically. No case shift characters are required or permitted in messages to or from the unit.
Figure 4-16.

Vertical (V) and Horizontal (H) Response Points

Image Index Counter
The Image Index Counter is standard on the IBM
2760. It is a two-position electronic counter used,
together with the CPU program routine, to ensure
the accuracy of film movement. This counter,located inside the 2760 and controlled by feedback
impulses from the film drive motor, increments ordecrements in step with the movement of the filmstrip. Therefore, the Image Index Counter contains
a continuous record of the image being viewed by theoperator. The counter is provided with read-out
circuitry to trans mit its contents to the CPU. This
read-out occurs at the beginning of every message
from the 2760 to the CPU.
The Image Index Counter read-out characters aredesignated 11 and 12 and are always the first two
characters following a PRE (prefix), 0 (alphabetic0) sequence in the message transmitted from the2760 to the CPU. Figure 4-17 shows the various
characters used to represent the numerical contentsof the counter.
If the 2760 receives instructions from the CPU tomove the filmstrip beyond its last frame, an "interlock" is activated to stop film movement. This, in
4-36(9/69)

turn, prevents any further operation of the counter,
thereby providing a method of indicating improper
operation to the CPU. (A subsequent move reverse
will deactivate the "interlock" and activate the Image
Index Counte r. )MESSAGE FORMAT• Messages received from the CPU containfilmstrip motion instructions for the 2760.
• The Function Control (F) character in thereceived message sets manual or automatic
EOM mode in the 2760.
• The F (Function Control) character enables ordisables the Manual Frame Advance switch.
• Transmission of a message is initiated by aprobe ope ration.
• The probe point data is defined for the CPUby the V and H coordinate cbaracters transmitted
in the message.

A-1 inV Reg.

A-2 in
H Reg.

Film
Control
CharacterTransmitted

Frames of Fi 1m Movement

Receive
FormatI
I mage Position CountIn I mage I ndex Counter

1-1

1-2

0

0

(Space)

0

0

32

1

@

32

1

64

2

-

64

2

96

3

&

96

3

128

4

1

128

4

160

5

/

160

5

192

6

J

192

6

224

7

A

224

7

256

8

2

256

8

288

9

S

288

9
10

320

10

K

320

352

11

B

352

11

384

12

3

384

12

416

13

T

416

13

448

14

L

448

14

480

15

C

480

15

-

16

4

-

16

-

17

U

-

17
19

22

-

-

26
27

-

18

M

19

D

20

5

21

V

I-Bit
Not I-Bit2-Bit
Not 2-Bit4-Bit
Not 4-Bit

18

22

N

-

23

E

-

23

24

6
W
0

-

24

25

F

-

27

28

Z

-

28

20

25
26

29

X

-

29

P

-

30

31

G

-

31

Transmit Format• Automatic EOM Mode is used for transmissionof one entry per message.
• Manual EOM mode is used for transmission ofmultiple entries within a given message.

Bit Configuration and Value In Counter and Registers

16

A2,12
Al/11
BCD

• Figure 4-17.

8

4

8

4

2

1

256

128

64

32

2

1

B

A

Decimal Values of Character Transmitted
for Film Control

Move Forward
Move Reverse
Set Manual EOM Mode
Set Auto EOM Mode
Enable Local Move switch
Disable Local Move switch

The Al and A2 characters are stored in thevertical and horizontal registers in complement form.
They specify the amount of filmstrip movement
necessary to display the next I/O image in the application routine (Figure 4-17). The filmstrip movement is initiated after the message is properly
received.

21

30

The message forrpat for the CPU to the 2760 is:@ , PRE, 0, F AI' A.l' @ , LRC, and theformat to the 2740-1 is QJ) , (text), @ , LRC;
PRE, 0, F, AI' A2 form the text part of the 2760
message.
The PRE, 0 sequence indicates to the terminal
control unit: (1) that the message is intended for the
2760, and (2) that the three characters following willdefine the function and the number of filmstrip
frames to be moved by the filmstrip transport unit.
The F character determines: (1) mode of operation, (2) direction of film rnOVemei.lt, and (3) whether
the Manual Frame Advance switch is enabled or
disabled (Figure 4-18.) The F character bit code
cannot have an 8-bit, but the presence or absence of
the A- or B-bit has no effect on the function. A
summary of the bit relation to the functions is asfollows:• The Local Move switch is enabled, for operator
control of filmstrip movement.
• The Local Move switch is disabled, for filtrts-trip
motion under control of the CPU program only.

2740/41 FETOM(9/69)

4-37

Move

Bit
Config.

l-Bit

1

1

Fwd

2

2

3

1, 2

4

4

5

1, 4

6

2, 4

7

1, 2, 4Char.

(Not) 1

Rev
Fwd

2-Bit

Mode Set To(Not) 2

Local Move Switch
4-Bit(Not) 4Auto

Disabled

ManualDisabled

ManualDisabled

Rev
Fwd
Rev
Fwd

Enabled

Auto

EnabledManualEnabledManualEnabled

Rev

Space

Auto

Auto

Disabled

NOTE: Thirty two combinations are possible with 1, 2, 4, A, and B Bits. The presence or absence of the A or B bits has noeffect, but 'an 8-Bit must not be present.
Figure 4-18.

Function (F) Control Character

The basic 2760-to-CPU message format is: @ ,PRE, 0, 11 , 1 2 , V, H, @ , LRC. In the variationsof this format, the 1 1 , 12 characters keep the same
significance. These characters are transmitted to
the CPU to assure proper indentification of the image
The bit configurations of these characters and theirrespective decimal values are the same as the A 1 ,A2 characters in the CPU-to-2760 message format(Figure 4-17).
The filmstrip motion control varies from format
to format. The direction of automatic motion andthe use of the Local Move switch are defined in the
F character of the message previously received fromthe CPU. A VH coordinate point is transmitted to
the CPU in each message, in the form of two characters. These characters, representing the data
part of the message, are transmitted from the vertical register and the horizontal register. The character combinations define 243 possible probe response
points on the 2760 screen (Figure 4-16). At least
one entry (VH coordinate) is transmitted in eachmessage, but in the Manual EOM mode, there may
be more than one entry.
Auto EOM Mode
Auto EOM mode is set by the F character (not 2-bit)in the message previously received from the CPU.
Only one entry is made in the text of each message
transmitted, and the end of message routine ( @ ,LRC) is automatically initiated. Completion of theentry is signaled to the operator when the positive
4-38(9/69)

answerback ( (iT) ) is received. (The audible tonesounds and the On- Line light goes off.) Automatic
retransm ission occurs if a negative ( ® ) answerback is received.
The Auto EOM mode format (2760-to-processor;@ , PRE, 0, 11' 12 , V, H, ®, LRC) is briefly
explained as follows:@ --Standard 2740-1 bid character.
PRE,o--Prefix, alphabetic 0, special character
sequence. It(1) defines the message as coming fromthe 2760(2) indicates that the next two characterswill be I , 12
11' I 2--Read-out of tfie Image Index Counter; defines
image defines for the CPU program.
V, H--Response point coordinates; represents data
presented on the image defined by 1 , 1 .
1 2@ ,LRC--Standard end-of-message routine; therecord-checking character is generated.
An audible tone is produced to notify the operator
that the message was properly received and that
additional messages may be transmitted.

Manual EOM Mode
Manual EOM mode is set by the F character (2-bit)in the message previously received from the CPU.
If the F character does not contain a 4-bit, theManual Frame Advance switch is disabled and thefilmstrip motion is under CPU program control.
Several entries may be made from a single image,after which the end-of-message is signaled by autility response point probed by the operator(usually End Entry).
Description of a sample Manual EOM Mode format( @ , PRE, 0, II' 12' V, H, V, H, V, H, V, H,@ , LRC) is as follows:@--Standard 2740-1 bid character.
PRE,o--Prefix, alphabetic 0, sequence is automatically inserted when the first response pointis probed. It(1) defines the message as coming from the 2760
(2) indicates that the next two characters will
be II' 12
II' I2 --Read-out of the Image Index Counter; allows
the CPU program to identify the image probed.
V, H --First data entry; an audible tone indicates onlythat the coordinate characters were transmitted.
V, H --Second data entry; an audible tone indicatesproper transmission (Several data entry points
may be probed. )V, H --Last data entry; an audible tone indicatesproper transmission.
V, H --Utility response point probed (usually End
Entry); coordinates transmitted and EOM routine initiated.
®, LRC--End-of-message routine initiated by thepreviously probed point; @ and check character are generated and transmitted; an audible tone indicates that the entire message
was properly received by the CPU.

2. The operator views three images and probes
six response points for data entry.
3. The operator probes End Entry utility response
point to initiate an EOM.
Under these conditions, a sample message format ( @ , PRE, 0, II' 12 , V, H, V, H; PRE, 0,
II' 12 , V, H, V, H, V, H, V, H, @ , LRC) is
discussed as follows:@ , PRE, 0, II' 12 , V, H--This part of the mes-sage is generated and transmitted when the first
response point is probed on the first image.
V, H--Second data entry from the first image.
(Semicolon)--Operator manually moves the filmstrip
by using the Local Move switch (enabled). Index
Count is updated, but no transmission takes place.
The operator may move several frames (one at atime) before an entry is made.
PRE, 0, II' 12 , V, H--This part of the message istransmitted when the first and only point isprobed on the second image.
(Semicolon)--No transmission, the Local Move switch
is operated for selection of another image; Index
Count is updated.
PRE, 0, II' 1 , V, H--First entry response point is
2probed on the third image.
V, H--Second data entry from the third image.
V, H--Third data entry from the third image.
V, H--End Entry utility response point initiates
the EOM routine.
@ , LRC--Standard termination of message.
Positive answerback causes the audible tone tosound, for indication that a proper message wasreceived by the CPU.

Manual Frame Advance
Manual Frame Advance is enabled by a 4-bit in the
F character of the previous message received fromthe CPU. This gives the operator the option to movethe filmstrip, one frame at a time, in either direction. The operator is allowed to select the image
or images from which entries are to be made. The
Image Index Counter is updated by each imagechange, to assure transmission of a proper countnumber (II' 12). The count is transmitted thefirst time any image is probed, after the filmstrip
has moved.
Manual Frame Advance enabled allows operational
flexibility, and for proper explanation, certain
operational assumptions must be made. Thus, let
us assume:
1. Manual EOM mode is set and Manual Frame
Advance is enabled by the command (F character) from the CPU.

OPERATION• A film cartridge is inserted and a program isinitialized by the 2760 operator.
• Mode and instruction information are received
from the central processing unit.
• Data is transmitted by the 2760.
• Appropriate responses are received fromthe CPU.
To start a program, the operator inserts a film
cartridge into the 2760 and probes the Load utility
response point. The contents of the Image Index
Counter and the VH coordinates for Load are transmitted to the CPU. The T (Transmit) light on the

2740/41 FETOM(9/69)

4-39

typewriter and the On-Line light on the 2760 turnon while the message is being transmitted.
The message received by the Optical Image Unit
contains instructions for film movement and also
sets the mode of operation of the terminal. The
start of the execution of the instruction is at the endof the message, at which time the 2760 is interlocked. During the execution of the instruction, an
incoming message for the 2760 will set the 2740
'error' trigger and a negative reply will be sent at
EOB time. Messages to and from the I/O printerare allowed, however.
The first (title) image displayed for the operator
contains an appropriate probe response point to
identify the filmstrip in use and the program to be
used. When the operator probes this point, theinformation is transmitted to the CPU, and theapplication program is called into CPU storage.
Detail data may now be transmitted to the CPU andappropriate responses received from the CPU until
the operation is terminated by the CPU program or
the operator.

4. The message is ended by EOB character received, and the LRC routine is initiated tocheck the message validity.
An error in the 2760 brings up 'error set gate
OIU' to set the 'error' trigger in the 2740 which
generates a negative answerback. The 'error'
trigger is also set when errors are detected by the2740-1.
If either the PRE or the "0" are missing from themessage, the 2740-1 is enabled and the message isdirected to the I/O printer.
Transmit Message to CPU from 2760
• Message format is © , PRE,
EOB, LRC.

0,

11' 12 , V, H,• A probe operation initiates message from the2760 to the CPU via the 2740-1.
• 'Bid N/O OIU' comes from the 2760, which
waits for 'clear to send'.

Receive Text from CPU to 2760
• The 2760 receives @ , PRE,
EOB, LRC.
• The PRE,
• PRE,00,0,F, AI' A2 ,F, AI' A2 sequence is the text.

Receiving a @ from the CPU activates the terminaland prepares it to receive the message. The firsttext character of the message intended for the 2760
is a PRE, which is received by the serdes register(S-register) and transferred to the 1B-register,where it is decoded for the 2760. The 'lB Reg bits',
ANDed with 'invalid character', bring up the 'prefix'
line to the 2760.
The 0 (alphabetic 0, BCD B42), following the PRE,
goes to the 2760 via the 2B-register bit lines in the2740-1. These bit lines are decoded in the 2760,
which prepares to receive the message as follows:
1. The 2760 sends 'inhibit print OIU' to the 2740-1,
to turn off the I/O motor and inhibit printout.
2. The 2B-register is reset by '2B reset OIU' andis prepared to receive the F character which
follows.
3. The F, AI' A 2 , instruction message is received
via S-register, 1B-register, 2B-register, and2B-register bit lines to the 2760.

(9/69)• The position counter in the 2760 controls generation and gate-out of characters to 1B-register
bit lines to the 2740.

directs the message to the 2760.

• F, AI' A2 furnish instructions for the 2760.

4-40• PRE, 0 is generated to identify the message as
being from the 2760.

• A basic 2740-1 sequence transfers the characters from the 1B-register to the S-registerfor serialized transmission.
• 'EOB N/O OIU' initiates the ending and recordchecking sequences.
• An error message retransmission is initiatedby an automatic 'restart OIU' from the 2760
in Auto EOM mode.
• An operator probe operation is required for'restart OIU' if the 2760 is in Manual EOM mode.
The operator probes a response point on the 2760
screen to initiate a message transmission from the2760. During the transmission, 'keyboard lock OIU'
from the 2760 locks the I/O printer keyboard to prevent 2740-1 operations.
A proper probe operation starts the oscillator,
sets the 'send' latch, and brings up 'bid N/O' in the2760, which watts for 'clear to send.' The 2740-1
accepts the 'bid N/O OIU' from the 2760 to initiate
the bid, and send the @ . When 'clear to send'goes back to the 2760 vi.a the 2740-1, 'on-line' isbrought up in the 2760 to allow 'gate out', 'gate out
bus', and position counter advance.
The 2760 (in Auto EOM mode) requires only one
probe operation to send the PRE, 0, II' 12 , V, H,
EOB, LRC message. As the position counter advances, the PRE and "0" characters are generated
to identify the sender for the CPU.
These characters are followed by II' 12 (index
counter) and V and H (register) characters gated tothe output bus. The output bus is gated to '(bit)transmit out' lines by 'gate output bus.' During
each character time (except LRC), the 'transmit out'
bits become input to message parity transmit logic,
and 'C transmit out' is brought up, if needed for odd
parity.
The transmit-out bit lines from the 2760 are
gated into the lB-register in the 2740. During
each character time, defined by the 2760 position
counter, 'gate out' comes up to bring up 'gate out
strobe OIU' which sets the' strobe 0' latch in the2740. 'Strobe 0' sets' strobe', and' strobe' gatesthe character into the lB-register.
A basic 2740-1 transmission sequence transfers
the characters from the lB-register to the S-register, where they are serialized to the transmissionline.

At the proper position count, 'EOB N/O OIU'
from the 2760 brings up 'EOB-l', and the messageend and LRC-check sequence follows. If an error
is detected, the' F-mode' latch is set in the 2740
and' F mode latch OIU' is sent to the 2760. In the2760, 'F-mode,' 'clear to send, ' and 'not restore
keyboard' bring up , ® '. 'Auto EOT' and' ® 'bring up 'restart to 2740', and the message is
automatically retransmitted.
While the 2740 is in transmit LRC mode, 'online, ' 'A mode, ' 'D mode, ' and 'L mode' set the'rec ansbk' latch in the 2760. 'Rec ansbk' and theappropriate 2740 mode latch lines decode as © ,@ , or G:J to terminate the transmission. For
example, 'rec ansbk, ' 'not B mode, ' 'not D mode, 'and 'not F mode' bring up , G.? " which first becomes·'EOT N/O OIU' and then 'EOT-l' in the 2740.
'EOT-l' brings up 'l-B generate' to send EOT, andthe message is complete.
If the 2760 is in Manual EOM mode, the operator
must manually reset the error condition and probe
again to retransmit the message. Manual EOM
mode allows more than one probe operation withina message, but the registers retain only the characters for the last probe point; t.,h.erefore, the operator must reconstruct the entire message after anerror is detected in Manual EOM mode.

2740/41 FE TOM(9/69)

4-41

SECTION 17. TRANSMIT INTERRUPr (2741)• A 2741 in transmit text mode receives a 200 ms"space" from the multiplexer and is forced to
the receive control mode.
• The terminal must be connected to the multiplexer
on full-duplex lines.
This feature is used only when the terminal is intransmit text mode. If the 2741 is transmitting text
and a "space" condition occurs for 200 ms on thereceive data line, the 2741 is forced to the receive
control mode. In receive control mode the keyboard is locked and the terminal monitors the line
until a @ takes the terminal to receive text or atakes the terminal to transmit text.
The multiplexer must transmit a minimum of one
character time of "mark" signal following the 200

©

4-42

(6/70)

ms of "space" to allow the 2741 to properly recognize the next character received•
The printed data at the 2741 is not necessarily
identical to the transmitted data for the print line
during which the interrupt occurs. Thus, the interrupt is considered as a terminating condition which
voids the entire print line.
The logic for the transmit interrupt feature ison AA671. A 200 ms "space" signal on the 'serial
data in' line ANDed with the B mode latch off(transmit mode) fires a 100 ms time delay thatbeings up 'A reset gate'. Reset forces the terminal
to control receive mode to receive the next control
character from the multiplexer.
The terminal must be connected to the multiplexer on full-duplex lines to use the transmit interrupt feature. This enables the terminal to receivethe "space" at the same time that it is transmitting
data.

SECTION 18

0

PRINT INHIBIT CPU CONTROL (2741)• Enables the CPU to inhibit the 2741 from printing
transmitted or received datao• Codes used are 'bypass' (A 8 4) and 'restore'(B 8 4)0

When the 2741 receives a "bypass" code, all further
printing is inhibited until a "restore" code is received, or the 2741 is powered off and ono All
printed characters received or keyed from the keyboard while the terminal is in print suppression modecause the print element to function, but not printo

All function codes are recognized as they are received•'Power on reset' sets the 'bypass restore' latch
and resets the 'print inhibit' latch (AA691)o Whenthe terminal is in receive text mode and a "bypass"code is received, the 'bypass restore' latch is reseto
The reset of the 'bypass restore' latch and' (not)10 cycle' sets the 'print inhibit' latch which picks
and holds the non print magnet until a "restore"
code and receive text mode set the 'bypass restore'
latch o The 'bypass restore' latch and' (not) 10
cycle' resets the 'print inhibit' latch and drops thenon print magneto

2740/41 FETOM(6/70)

4-43

CHAPTER 5. POWER SUPPLIES AND CONTROL

Figure 5-1 is a block diagram of the 2740/2741
power supply and input voltages for domestic andWorld Trade use. The different voltages and cycles
are accommodated by using a different transformer,
different taps on the transformer, or both. Internally, the power supply functions the same for all
inputs. The outputs of the power supply are: +48
volts dc, +12 volts dc, and -12 volts dc. The +48
volts is used in the I/O device. The +12 and -12
volts are used by the SLT logic. The power supply
also supplies the power-on reset, described in
Chapter 3.

ac Input

Old Style(All Models)

New Style(2740-2 )Domestic
60 Cycle

115
208/230

100/115200/208/230

112.5
123.5
195

100
110
123.5
200

220
235

220
235

World
Trade
50 Cycle

Although similar to the 2740 power supply inevery other respect, the 2741 power supply does
not contain an alarm bell.
CAUTION
Terminals wired for 115VAC, 60 cycle do not
use the same transformer as terminals wired
for 208/230 VAC. If the power supply is wired
for 208/230 VAC (Transformer taps 11 or 12),it must not be changed to the 115 VAC wiring(tap 10), or vice versa, or the supply will bedamaged.
The proper transformer should be used forthe available line voltage.

ac input

2740-12740-22741
PowerSupply

+48v
+12v
-12v
Gnd
Power On Reset

ALD 2000

Figure 5-1. 2740/2741 Power Supply

2740/41 FETOM(1/69)

5-1

CHAPTER 6.

CONSOLE AND MAINTENANCE FEATURESCE AID BOX

Single Cycle• Used for dynamic troubleshooting.

• Character is held in the register(s) until C E
presses Cycle (pushbutton).

• Shows condition of 1B-register, mode triggers,and 'parity error or not S8' trigger.
• 2B-register can also be displayed on 2740-2.

By setting the 1 CH (single-cycle halt) switch on the
CE can single-cycle the terminal. With the switch
in the off position, the terminal operates normally.

• Allows terminal to be single-cycled.

2740-1/2740-2/2741• Contains a Space character generator.

During transmit operations, the character is held in
the 1B-register. Pressing the cycle pushbutton
causes the character to be transferred to theS-register for transmission. The next characteris then loaded into lB.
For receive operations each character is received
in the S-register and transferred to the 1B-register.
The character is held in 1B until the cycle button ispressed. It then transfers to 2B and prints.

The CE Aid Box helps the Customer Engineer diagnose terminal failures under dynamic conditions.
The CE can observe the contents of the 1B-register(also 2B-register on 2740-2),the condition of themode triggers, and the condition of the 'parity error
or not S8' latch (P). A single-cycle circuit thatallows the terminal to be cycled through its operations
is incorporated into the C E Aid Box. In addition, thereception of a Space character can be simulatedusing the space generator circuit. The space generator causes the terminal to receive Spaces continuously so that the CE can check the terminal.
The CE Aid Box is an external device that isplugged into a receptacle on the terminal gate. All
power for the CE Aid Box is provided by the terminal
power supply. Figure 6-1 shows the location of the
CE Aid Box lights and switches.

r-'] B or *2B re ister
9

'-1

2

3

Mon~tor 1 B--plug connector ~nto B1 C1Monitor 2B--plug connector Into B101

4

5

6

7

0000000
0000000
A

CYCLE

B

0

o

E

F

~::

L

g

OFF

*2B register can be displayed on the 2740-2 only.

P

SPACE

2740-2
NOTE: EC306818 must be installed on the CE Aid Box to enable
1CH functions to operate with the Model 2.

The 2B-register may be displayed on the 2740-2 bymoving the paddle card on the B board from location
Cl to Dl. The 2740-2 has the following additional
single-cycle capabilities:
1. Enter
2. Buffer print
3. Buffered receive
During Enter, a character is loaded into the 2Bregister. The operation of the cycle pushbutton
increments buffer address and stores the characterin buffer. A second depression of the cycle button
is required to reset 2B and allow another characterto be entered.
Buffer print gates the character to 2B-register.
The cycle button allows the character print and 2B
reset.
Receive with Buffered Receive feature is initiallythe same as any receive operation. The first rlepres'::sion of the cycle button transfers the character from
1B-register to 2B-register and from 2B-register
into buffer. The second operation of the cycle button

Figure 6-1. CE Aid Box
2740/41 FETOM(4/68)

6-1

'stop clock' trigger. The 'stop clock' trigger off
and the 'cycle N/O' line still up turn on the 'cycle
interlock' latch. The 'cycle interlock' latch degates'stop clock reset gate.' The Cycle pushbutton must
be released and again pressed to cycle the terminal.
When the CE releases the Cycle pushbutton,'cycle N/C' comes up and turns off the 'cycle'
trigger; the' cycle inter lock' latch remains on
until the 'stop clock' trigger is again turned on.
During receiving operation, when 'C1' 'not 2B
reset, ' and IS-register empty' come up (indicatingthat a character is in 1B), the 'stop clock' trigger
turns on. The procedure to cycle the terminal is
the same as for the transmit operation, except thedata transfer is to 2B and printer instead of theline.
The operation with the 2740-2 is identical to theabove description with the following exception: thecontrol clock is stopped at the end of each buffer
character cycle (Top AND to turn on 'stop clock'
trigger, Figure 6-2). This circuit is required

resets 2B-register and allows a new character tobe accepted from the line.
Operation
Figure 6-2 shows the single-cycle circuit. With the
1 CH switch at Ol\l the 'lcycle halt' line activatesthe single-cycle circuit. For an enter operation,
when 'strobe' and 'not strobe 0' come up, an AND is
conditioned to turn on the 'stop clock' trigger.
'stop clock' degates the control oscillator inputs tothe control-clock triggers. The character is now in
2B. The control clock must run to enter the character into buffer storage.
For the control clock to run, the CE must press
the Cycle pushbutton. This causes 'cycle N/O I' tocome up to turn on the 'cycle' trigger. The 'cycle'
trigger on and the 'cycle interlock' latch off (turned
off when 'stop c lock' came up) condition an AND tobring up 'stop clock reset gate', turning off theEnter, Transmit, Buffer Print, Buffer Receive 2740-2

Vertical Current
Control Gate

Receive 2740-1/2740-2/2741
Buffer Receive 2740-2~

1 Cycle Halt

1 CH Switch
Down except
when Switch
isON

Strobe~(N~o-t)~St-ro~b-e~O~--~ A

Stop
Clock

BB182

AA361
AA362
. AA364

FF

CC2
CMV (Control Multivibrator), , Stop Clock Ac Reset,,Stop Clock Res Gate

CEOll

CE031
Down whencontacts not
made

CCl Gate
Power On Reset+-------t A OR~--c>-+.:...--,--...:...--....

Cycle
Pushbutton

Cycle
Interlock
CC2

FL

Cycle N/C 1
CMV (Control
Mu Itiv ibrator)

Clock Run
Cycle

FF

CE031

AA131

* Logically, but nottechnically correct

Figure 6-2. Single Cycle
6-2(4/68)

during buffer print and transmit since the data
source is the buffer. However, the circuit effects
operation during enter and buffer receive.
During both enter and puffer receive, the character is transferred to buffer with the first depression of the cycle button. As the character is loaded
into buffer, 'vertical current control gate', 'write'and 'BAT 6' turn on the 'stop clock' trigger. A
second depression of the cycle button is required toreset 2B-register and allow the next character tobe set into 2B-register.

CHECK LOOP (2740-1/2741 only)

Space Generator

The check-loop circuit allows the CE to check the
I/O device off-line. To check the I/o device, theCE causes the device to repeatedly print any I/Ocharacter or perform any I/o function except shift.
When the CE presses the Bid key on the 2740-1 or
the Attention key on the 2741 while the terminal is
in local mode, the check-loop circuit is activated.
Pressing any other key on the I/o keyboard causes
the character to be printed or the function to be
performed continuous ly until the Bid key is released.
Data flow is shown on Figure 6-5.
When 'not send, ' not clock run, , 'lB empty, ' and'local' are up, pressing the Bid key turns on the'repeat' trigger (Figure 6-6). Before the 'repeat'
trigger comes on, the 1B-register is reset by 'modechange, ' which is forced up by 'not repeat, ' 'notsend, ' 'local, ' and 'bid 1.' Pressing an I/o key
starts the I/O cycle, during which the transmit
contacts are set up in the configuration of the character.
When the 'strobe N/O' contacts make, the'strobe 0' trigger turns on to start the normal
sequence that gates the contents of the trans mit contacts to the 1B-register and' 1B full' comes up. As
soon as 'strobe' drops, the '2B set' trigger turns on
to transfer the character to the 2B-register. Just
as in a receiving operation, the character in 2B isgated to the I/o magnets, causing the I/o to recycle.
To stop the operation, the CE releases the Bid key.
When the present cycle ends, the 'repeat' trigger
turns off.
During check-loop operation the following occurs:• Continuously loads Space characters into the Sregister.
• Simulates carrier.
• Blocks power-on reset.
The space generator continuously simulates Space
characters (C-bit only) on the' serial data in' line.
Thus the CE can check the operation of the terminal
and I/o device while in receive mode without using
another terminal. Figure 6-3 shows the space generator sequence. Figure 6-4 shows the logic thatgenerates the Space character.
Normally, the 'received data' line from the line
adapter is in a "marking" or up condition when data
is not being received. An AND, conditioned by'received data' and 'not space N/O' is the source of
the 'serial data in' line. When the CE turns on theSpace switch, the AND is deconditioned and 'serial
data in' drops. This simulates a start bit and starts
the serdes clock.
The S-register loads with no-bits until the start
bit reaches 'S2;' 'not S2' brings up the 'serial data
in' line. With the start bit in 'S2, ' the timing issuch that when the 'serial data in' line comes up, aC-bit is loaded into the S-register. The next bit
shifted into 'S2' is a no-bit; therefore, 'serial data
in' remains up and loads the stop bit.
Once the complete character is in the S-register,
the character transfers to the 1B-register and 'lB7'
comes up. 'lB7' continues to hold the' serial data
in' line up mark condition. When the character in
1B transfers to the 2B-register, 'lB7' drops andthe loading of another space character begins. The'lB7' input prevents the terminal from generating
spaces faster than the I/o printer can use them.
Also, when the CE turns on the Space switch, 'space
N/O' coming up simulates 'carrier, ' which allows
the terminal to operate in receive mode withoutline-adapter carrier. 'Srace N/O' also blocks thepower-on reset circuit.

• Permits the I/o device to be checked dynamically
off-line.
• The strobe circuit is forced up to gate the transmit contacts to lB.
• '2B set' is forced up to transfer 1B to 2B.
• The character in 2B then restarts the I/O device.

1. The 1B OK circuit is disabled to prevent
recognition of any control characters.
2. The power-on reset circuit is disabled.
3. The 'local/communicate' trigger is held in local.
4. The' serial data in' line is held at mark levelto prevent the reception of data.
If the station-control feature is installed in theterminal, 'repeat' holds the terminal in text nonselected mode, holds the 'garble' trigger on, andblocks the turn-on of the 'time-out 15' latch.
When the terminal is in communicate mode, the'repeat' trigger is held off.
2740/41 FETOM(4/68)

6-3

Space Switcho--L.ySpace N/O (See note)<> Carrier(CE041 or CE042)
Power On Reset-X(To AA231)(Not) Data Set Ready
Power
On
Reset
Drop Serial Data In line

SerialData

In(Not) S2-A Bit
1B or 2B7-C Bit
From
line
AdapterNo

Yes

Received
DatC1

Note:
Space N/O is down
until key is pressed.
Figure 6-4. Space Generator

Yes

No

,..- - - - --,I~~n: __ ,

I

S-Reg

1

:____ _
I

L __ : } ___ J

No

Yes
1

1
1

I

r - - '---..,I
Control 1: Clock :L ______ J

Figure 6 -5. Check Loop Data Flow

6-4

(4/68)_____ JIr- - -1- - - ,: Serdes :I Clock
I
L ______ J

End Operation

Figure 6-3. Space Generator Flowchart

1-'I'
1L ____ ,o Strobe 0 Set Gate

Strobe0 1(Not) Repeat Reset Gate
AA371
(Not) Strobe
18 Full028 Set Set Gate
AA371

(Not) Send(Not) Clock Run
18 Em t
8id 1
Local

A

18 OK

Re eat Set Gate

AA371
t------------t N t-----..------,o ,Mode Change-A (Reset 1B)(Not) Send
Local
8id 1

A
AA371

RepeatCC2
CCl

FF

Power On Reset
AA141
Serial Data In

Repeat
Reset
Gate

A

Line

{Not} Dial Disconnect
AA131

AA371
_C_l________________~~~s~S~et~Te~x-t~N~o~n~-~s~e~le~c~te~d~--(Not) Local {Comm}

____

B8111
Local/Comm

Local

FF
Communicate
AA201

Note: SC - Station Control

Garble

FF

BBI0l
SC
L..------------INt-------t

Garble(Not) Power On ResetAo Time Out 15-A

88101

Figure 6 -6. Check Loop

2740/41 FETOM(4/68)

6-5

APPENDIX A.
COMMUNICATIONS TERMINALS 2740-1/2741
Dimensions: Width 28 3/4"
Depth 25 1/4"
Height (Overall) 36 1/2"
Height (Desk-Top) 29"

MACHINE CHARACTERISTICS• Western Union Class D (180-baud) channel with
Western Union Data Loop Transceiver 1183-A(or equivalent).
• Western Union ClaSs E channel with IBM Leased
Line Adapter, or IBM Shared Line Adapter (orequivalents) .

Maximum Weight: 196 lbs
Service Clearances: Front 30"
Rear 42"
Left 18"
Right 18"
Electrical Requirements:
Voltage
115 or 208/230 .::': 10%
15 amps
ServiceFrequency
60.::': 1/2
1
Phases
0.15
KVA• Privately owned communications facilities withother modulator/demodulator equipment similar
to IBM Line Adapters or common carrier data
sets incorporating the proper interface.
• Local or in-plant customer installed or commOllcarrier wiring with IBM Limited-Distance Line
Adapter Type 1 (for distances up to 4.75 miles) or
IBM Limited Distance Line Adapter Type 2 (fordistances up to 8.25 miles).

COMMUNICATIONS TERMINAL MODEL 2
Temperature Range:+50F. to +100 F.
Humidity Range:
10% RH to 80% RH
Maximum Wet Bulb Temperature:
85 F
The 2740/2741 can communicate with other terminals
or System/360 over these facilities:

Dimensions
Width: 36 in. ; Depth: 29 1/2 in. ;Height (Overall): 36 1/2 in. ;Height (Desk-Top): 28 7/8 in.
Maximum Weight
200 lbs (90.7 kg)Service Clearances• Common-c:lrrier switched telephone network with
Western Electric Data Set 103A (or equivalent).
• Common-carrier switched 150-baud teletypewriter exchange (TWX) network with WesternElectric Data Set 103A (or equivalent).
• Common-carrier leased private-line telephoneservice with Western Electric Data Set 103F
(or equivalent), IBM Leased Line Adapter, or
IBM Shared Line Adapter (or equivalents).

NOTE: Common-carrier data sets and IBM Line Adapters cannot
be mixed in the same network.

• Common-carrier leased private-line telegraphservice (telephone company 150-baud, schedule
3A channel) with appropriate channel termination.

Front: 30 in. ; Rear: 42 in. ;Left: 18 in. ; Right: 18 in.
Electrical Requirements
Voltage: 115 or 208/230 + 10%
Frequency: 60.::': 1/2 Hz Phases: 1
kva: 0.15
Service Amperes: 15
Plug Types:
Hubbell or Pass & Seymour 5267 (115v, non lock)Hubbell or Pass & Seymour 4720 (115v, locking)Hubbell 5666 (208/230v, non lock)Hubbell or Pass & Seymour 4770 (208/230v, locking)
Receptacles: Customer provides matching receptacles-- Hubbell or Pass and Seymour 5262 for 5267
2740/41 FETOM(4/68)

A-1

plug; 4700 for 4720 plug; 5662 for 5666 plug; and4750 for 4770 plug.
Circuit: Circuit should be separate three-wire,
single-phase branch circuit from power distribution panel, with green wire connected to ground,not current neutral.

equivalent privately owned communications facilities, using an IBM Leased- Line or Shared- Line
Adapter.
• Telephone Company leased private-line telephoneservice with Western Electric Data Set 103F2 or
202D1 or equivalents.

Environmental Specifications
BTU/hr: 400 (101 kcal/hr)
Temperature: 50-110°F (10-43° C), Operating andNonoperating;Relative humidity: 8-80%, Operating and Nonoperating
Wet Bulb Temperature: 85°F (29° C) max, Operating and Nonoperating.
Shipping Temperature: For shipping, temperature
limits are _40° to +150°F (-40° to +66°C)
Conversion Table
Inches (in.) Centimeters (cm) Feet (ft) Meters (m)18287/8
29 1/230
36
36 1/2
42

45,7
73,9
74,9
76,2
91,4
92,7
106,7

6
8

1,83
2,44

• Western Union Class D (180-baud) channel using aWestern Union Data Loop Transceiver 1183-A or
equivalent.
• Telephone Company Type 1006 (150-baud) privateline telegraph service with appropriate channel
termination.
• Telephone Company Type 1005 (75-baud) or
Western Union Class C (75-baud) channel.
• Local or in-plant customer-installed or commoncarrier facilities with IBM Limited-Distance Line
Adapter Type 1 (for distance up to 4.75 miles) or
IBM Limited-Distance Line Adapter Type 2 (fordistance up to 8.25 miles).
• Equivalent privately owned communications facilities with IBM Line Adapters or other modulator /demodulator equipment similar to IBM Line Adapters or common-carrier data sets incorporating
the proper interface.

Communications Facilities
The IBM 2740 Model 2 can communicate with a System/360 over the following facilities:• Telephone Company leased private-line telephoneservice, Western Union Class E or G channels, or

A-2(4/68)

NOTE: Common-carrier data sets and IBM Line Adapters cannot
be mixed on the same channel. For additional information on
IBM Line Adapters, see the publication, Planning and Installation of a Data Communications System Using IBM Line Adapters, Form A24-3435-2 or later edition.

Signal-Cable Chart

Signal Cable

LengthDiameterConnector
Supplied by IBM

Matching Connector
Supplied by Customer

From 2740 to
Data Set

8ft

3/8 in.
(0,95 cm)

EIA RS-232Aor equivalent

Supplied with Data Set by Common Carrier.

From IBM Line
Adapter (Special
Feature) to Communications Line8ft

3/8 in.
(0,95 cm)

Western Electric 283B plug
or equivalentWestern Electric 404B (or equivalent for
Surface Mounting, or Western Electric 493A(or equivalent) for Flush Mounting.

From TelegraphLine Adapter(IBM Special Feature) to Communications Line

8 ft

5/16 in.
(0,79 cm)

#8 Ring Lugs

Attaches to Common-Carrier Terminal
Board.

2740/41 FETOM(4/68)A-3

APPENDIX B.
SPECIAL CIRCUITS ON CARD AT LOCATION AIM4
(Figure B-1)
Voltage Reference (Block 2H)• Fixed voltage for sense-amplifier-sensitivity
reference.

2740-2 SPECIAL CIRCUITS

differential amplifier to operate only when certain
conditions are satisfied. These conditions are: 'notenter, ' 'read, ' 'horizontal current, ' and '200N delay.
The delay begins at the start of horizontal current
and times out at the time when a resetting core has
started to change magnetic states. Thus, the sample
for a changing core is on the steep part of the Sense
line signal (Figure B-1).

• Fixed voltage for temperature-compensationreference.
Temperature-Compensation Voltage (Block 3H)• Thermistor resistance to ground varies inverselywith temperature change.

SPECIAL CIRCUITS ON CARDS AT LOCATIONSAIG4 AND A1G5 (Figure B-1).
Current Control (I Control, Blocks 3C)• Provide gating to drivers and switches.

• Thermistor input to compensation circuit modifies reference voltage.
• Compensated reference voltage at A1M4D09 regulates forward bias of current-control circuits.
The fixed-reference voltage and the thermistor output comprise the inputs necessary to provide a precise current-control reference voltage that varies
with array temperature. The voltage level at
A1M4D06 becomes more positive as array temperature drops and less positive as array temperaturerises. It is pre-adjusted at a given temperature andlocked at the factory. This level clamps the inputs
to the I Control blocks (3C) to limit forward bias.
Differential Amplifier, Strobe AND, and Strobe
Delay (Blocks 3D, 2E, and 4D respectively)• Operates on a difference in voltage on the twoends of the Sense line.
• Output at A1M4D04 is positive, regardless ofsense input, until the strobe delay elapses.
• Strobe AND satisfied when horizontal current
starts.
• Strobe delay allows time before sampling for thecore to start resetting in response to coincident
array currents.
The sense amplifier has two parts. The first is adifferential amplifier, which senses and amplifies avoltage difference between the ends of the array sense
winding. The second, a clamp circuit, allows the• Regulate current-carrying capability of sinks(negative) .
As explained under "Temperature-Compensation
Voltage," the I Control input at pin BOS limits forward bias at a level that varies with array temperature. The other I Control inputs are logical, having
to do with array line-current direction and timing.
Transistors in the current-control circuits arecascade-connected to transistors in the current sinks(I Control transistor collector to current-sink transistor emitter). Thus, limited forward bias in thecurrent-control circuit limits the amount of current
that can be conducted by the sink.
When an array line carries current, a source isconditioned at the positive end and a sink at the negative end. The source can conduct no more current
than the sink will provide, so array line current islimited. By this means, temperature-compensation
circuits allow for higher array currents when thearray is cold, lower currents when it is warm.
The ANDed inputs and corresponding outputs
from the current-control blocks are as follows:
AND Input Pins

AND Output Pins

BOS, D12, B13
BOS, D12, D02

DI0
D06

Whenever either AND is satisfied, the current line
at D07 rises from ground to its positive value. Thislevel rises because of its electrical function as anegative enlitter source in the current-control circuit
and a negative collector return for the current sinks.
The positive level at D07 serves the logical function
2740/41 FETOM(4/68)

B-1

'Tj

Ij;j
I

N

Qq'
~
(1)

-:;

Ij;j
I

~

()

---..
0'1

~

a

-MEMORY BUFFER RESET GATE-POWER ON RESET-MEMORY BUFFER SET GATE

(1)

I

0.-

(FROM FIG. B-2) -<f"t

B-AIM4
2H-SA

III

g

TEMP COMP V
807X~

bfr---V REFERENCE.--SPEC
V25AC
B07

III

::l

0

f"t

'1

V25AB

J09 N B-A I M4
5C-SG

DIFF. AMPL.
G08~

J06 V07AZ
JI2 TD 200NS
007 *SPEC
J05 V45DF- J04
B-AIM4rGro 2E-SJ-RECEIVE TEXT BUFFER

I

6B-SD

V20AD
B-AIM4
7B-SE
~

6C-SF

I G05

B-AIM4
3D-SH

B-AIM4

J04 HORIZONTAL CURRENT~

G05 S6IAF

~

ro04

~

'---

D04 SENSE AMP BIT~B13 STROBE DELAY
~

'---

KBI3

I

~

~

-MEMORY BUFFER

JIO......

~ B-AIM4~+ MEMORY BUFFER

*Fl

'---

V20AB

Ii;'

+VERTlCAl CURRENT SOURCE GATE
- ENTERI~~Lff-.-.-b'";QR
*A
V20AC

009

r==-

,SENSE LINE 2

0~

MEM.BFR.
...... ~JI3*~ B-AIM4

G07 N B-AIM4~ B-AIM4SENSE LINE I ~

::l

V20AC

V20AB
rTHERMISTOR~

III

GI3"'~Lf ~'*OR- CC2

J06/G08 DIFFERENTIAL+HORIZONTAL CURRENT+VERTICAL CURRENTVERTICAL SWITCH READ GATEVERTICAL DRIVER WRITE GATE+READ ODD-WRITE EVEN
+VERTICAL CURRENT CONTROL GATE

D12~

I CONTROL

07

V25AD

010

V32AC

006

B04 B-AIG5

~~D

V03CM

B-AIG5r--~

BI3 B-AIG5

~

B13~

807

VERTICAL SWITCH WRITE GATE

oo2r--;;:-

V03CM

V32AC

I-- t--f

VERTICAL DRIVER READ GATE~~

D12r;:--+ READ EVEN-WRITE ODD

D09

D02 B-AIG5

B04 B-AIG5~~2G-AD

L.....--+ READ+MEMORY GO- HORIZONTAL SWITCH READ GATE- HORIZONTAL DRIVER WRITE GATE
+ WRITE+HORIZONTAl CURRENT CONTROL GATE

I CONTROl
DI2 r--;;:V03CM

V25AD

BI3 B-AIG4

B-AIG4
3C-AF-

L-.......;:..;.~

D12~+MEMORY BUFFER

805 V03CM
D02 B-AIG4NOTE.
SEE DIAGRAM 4-18 FOR lOGIC OF
DIFF. AMPl., MEM. BFR., AND
I CONTROl. V REFERENCE IS A
CONSTANT VOLTAGE SOURCE,
AND TEMP. COMP. V CONTROLSARRAY CURRENTS. ARRAY CURRENT
DECREASES AS TEMPERATURE RISES.

~

DIO

B13.---A
V32AC t-.... 009

D06

B04 B-AIG4~r-;spfC~- HORIZONTAL DRIVER READ GATE

~~

'--~

~~
V32AC

I---

807

- HORIZONTAL SWITCH WRITE GATE

B04 B-AIG4.....::::..:...~ALD PAGES:
DDOI!
DDO!2
DDOl3

Sink

of timing sense-amplifier strobe in reference tohorizontal current (block 2E).
ANDed Inputs
SPECIAL CIRCUITS ON CARDS AT LOCATIONS
A1H6, A1H7, A1J3, A1J4, A1J5, A1J6, A1J7
(Figure B-2)
Current Sources and Current Sinks (Blocks 4B, 3C,
4L and 3M)

Output+ on Address lines- on Gate line

- (Driver,or Switch In)

SPECIAL CIRCUITS ON CARD AT LOCATION A1L4
(Figure B- 2)• These circuits conduct array line current
Core-Array Current Lines (Blocks 4B and 4E)• Driver and switch circuits are identical; eachcontains a positive source and a negative sink.

• Connections to vertical and horizontal lines.

• Source and sink outputs are common in drivercircuit.

• Switch In and Switch Out line-isolation diodes areon array card A1L4.

• Source and sink outputs are diode-isolated inswitch circuit; diodes are on array card.

• Branching of driver and switch lines to form thearray matrix is land-pattern wiring on the array
card.

The electron flow of array current is from a negative sink to a positive source. The negative origin
is the current line at A1D6D07 (horizontal) or
A1D5D07 (vertical). The positive termination is a
resistor to +12 volts A1D5D04, horizontal; A1D6D04,
vertical.
Array-current timing, direction (selection ofsource or sink), and amount are determined bycurrent-control inputs to the driver and switch circuits. Addressing takes effect at the driver or switch,so that only one element of each group conducts--i. e. ,one horizontal driver, one horizontal switch, one
vertical driver, and one vertical switch. Selectionof a source or sink conduct current is equivalent toa logical AND, as follows:

Array Sense Winding (Block 4H)• Passes through each and every core.
• Crossovers tend to cancel unwanted signals.
• Change in magnetic state of a core induces potential difference (approximately 30 millivolts) between ends of sense winding.
• Ends of sense winding connect to differential amplifier.
Thermistor (Block 4K)• Mounted on array card inside array cover.

SourceANDed Inputs+ on Address lines- on Gate line

Output+ (Driver,or Switch Out)

• Temperature-sensitive resistor; increases resistance with temperature drop, decreases with temperature rise.
• One end grounded, other end connects totemperature-compensation circuit.

2740/41 FETOM(4/68)

B-3

t1J
I
,j>.

-;
........

0\

~

'Tj

a'Q'
~

--;:--

t1J

V03CJ

CD

CUR~URCE~I!"

BOSB-A1J7·n
2B-AA

*SPEC
V32AD ~8,.!!3. 8-A U7

C~SINK, - - - - - *SPEC
V32AE

~

DOS

802 B-AU7
F~

.---

U12

~HORIZONTAL SWITCH lOUT BEX

504

S07

~HORIZONTAL SWITCH 2 OUT BEX~ HORfZONTAL SWITCH 3 OUT BEX

S12HORIZONTAL SWITCH 1 IN
HORIZONTAL SWITCH 2 IN
HORIZONTAL SWITCH 3 IN
HORIZONTAL SWITCH 4 IN

U13

S13

(;1

S09

S08

~HORIZONTAL SWITCH 4 OUT BEX~PlHORIZONTAL SWITCH 5 IN
HORIZONTAL SWITCH 6 IN

B03

B05

~ HORIZONTAL SWITCH 5 OUT BEX

Q

r--

~

'---

HORIZONTAL SWITCH lOUT

-<

D.
..,
0

s.
~

HORIZONTAL DRIVER 1
HORIZONTAL DRIVER 2

B09 *ARRAY B08
B-AIL4
B02 4E-SB
002
GQ4
G03

HORIZONTAL DRIVER 3

G02

HORIZONTAL SWITCH 7 IN,

HORIZONTAL SWITCH WRITE GATE,HORIZONTAL SWITCH READ GATEI+ HORIZONTAL CURRENT,+ BUFFER ADDRESS TIME 0

HORIZONTAL DRIVER 4

B13

HORIZONTAL DRIVER 5

B12
M05

HORIZONTAL DRIVER 6HORIZONTAL DRIVER 7t-~HORIZONTAL SWITCH 6 OUT BEX~ HORIZONTAL SWITCH 7 OUT BEX

Gl0
L---

+12 VOLTS

r-

004

V03CJ

- ~

I--

- BUFFER ADDRESS 12

1!clL- HORIZONTAL DRIVER READ GATE

B07

~ VERTICAL SWITCH 3 0 UT BEX

VERTICAL SWITCH 4 IN

009

BIO

~VERTICAL SWITCH 4 OUT BEX

VERTICAL SWITCH 5 IN
VERTICAL SWITCH 6 IN
VERTICAL SWITCH 7 IN

UII *ARRAY UIO
U06 B-AIL4 S05
4B-SA
010
007

VERTICAL SWITCH 7 OUT

B04

VERTICAL SWITCH 8 OUT

B08

VERTICAL SWITCH 8 IN

006

VERTICAL DRIVER 1,

VERTICAL DRIVER 2

P05
M03

VERTICAL DRIVER 3
VERTICAL DRIVER 4

GI2

B-AU4

CURRENT SINK+ HORIZONTAL CURRENT

B02

L
.....

'---

A3
ARRAY
TERMINAL

~ ~
~, ~

I--~

B-AIJ4~4

ARRAY
TERMINAL
073

3M-SG

~

AI L4J04,(';'

HORIZONTAL SWITCH lOUT AIL4UI2VERTICAL SWITCH 6 OUT

M02

r;sPeCAI L4S12VERTICAL SWITCH 5 OUT

002", V32AE

HORIZONTAL DRIVER WRITE GATEHORIZONTAL SWITCH 1 IN

~ VERTICAL SWITCH 2 OUT BEX

004

S02
M13

=:....-~

B09

013 B-AU4

*SPEC
V32AD

~ VERTlCAL_~ITCH lOUT BEX

MI2

B-AIG4VERTICAL SWITCH 2 IN
VERTICAL SWITCH 3 IN

CUR~OURCE

B04~

S03

VERTICAL SWITCH 1 IN~
+ BUFFER ADDRESS 9 AND 10

-

561KW

C3
ARRAY
TERMINAL(

AIL4G04
HORIZONTALDRIVER I

071

AIL4J05.---- J05

ARRAY
J04
B-AIL4
4H-SC~

SENSE LINE ISENSE LINE 2

'---

>
(
(

~

TO FIG.
B-1

.---R
S61KX
B-AI L4
4K-SD(PARALLEL TO VERTICAL)

S10

THERMISTOR-'rAIL400~AIL4SI0

7
NOTE: 'GATE' LINES ARE EMITTER SOURCES SWITCHED BY 'I CONTROL' (FIG. 8-1)\
TEMPERATURE UP/RESISTANCE DOWNTEMPERATURE DOWN/RESISTANCE UP

APPENDIX C--WORLD TRADE IBM 2740 MACHINE LOGICThe World Trade version of the IBM 2740 is functionally the same as the domestic machine. There
are some logic changes, particularly Auto-Disconnect with the IBM 3976-2 Modem and the circuits forgenerating and printing the slash ( / ) instead of thedash ( -). These two changes are described andillustrated here.
Auto- Disconnect With IBM 3976-2 Modem••

Causes for disconnect:(a) No bid within 15 seconds after connection.
(b) No character sent within 15- to 30-second
period.
(c) No character received within 15-second
period.
(d) No bid within 15 seconds after EOT.
(e) Out of paper.
(f) Data set (modem) not operational.
(g) Manual disconnect by either operator.
Indications of disconnect:
NOTE: (a) and (b) do not happen when thedata set (modem) becomes not operational.
(a) Transmit and Receive lights on, Dial Connect light off.
(b) Bell sounds once.
(c) Modem "Data" light off.

A dialed connection establishes communication
between two terminals, as though on a leased line,
until disconnected. Disconnection occurs when the
Dial Disconnect key is pressed, by loss of terminal
status, by not following EaT with a bid, or by failureof the sending terminal to maintain carrier and a
stream of transmitted characters. All disconnects
except Dial Disconnect key depression or loss ofstatus occur only after a 15-second waiting period
has timed out. The delay is controlled by a 15second timer and a latch.
Once a connection is completed, the 15-second
timer and 'time-out 15' latch will respond to anyoneof several potential reasons for disconnection(Figure C-l), if it continues uninterrupted for 15
seconds. These are:
1. Data set capable of data operation (ready) but
no carrier present (AA431 and BB291).
2. No character being sent (mainly 'send' and'IB
empty', AA311).
3. No character being received (AA431--'data set
ready', 'not send', and 'not inhibit time-out'.

The 'inhibit time-out' trigger turns on only forgood- parity characters with S,tl. )NOTE: Since the 15-second time delay is aleading edge delay, only, there is no carryover from
one timing period to another. If carrier has been off
and momentarily comes on again, or if a characteris sent or received, the 'TOI5' latch and the 15second timer are reset. A new 15- second timeout
period begins.
When a connection is made and neither terminal
bids for the line, timeout for auto-disconnect occurs
because no character has been sent or recei ved. The
garble timeout (BBI0l) is not present in dial-up
machines.
When a reason for disconnecting prevails for 15
seconds and the 'TOI5' latch turns on, the 'dial disconnect' latch turns on. Timeout, with 'not-send(receive)' or 'not-carrier', sets the 'dial disconnect'
latch. Operator-initiated disconnect (dial disconnectkey) also turns on the' dial disconnect' latch andworks like auto-disconnect throughout the remainderof disconnect circuit operation. The' dial disconnect' latch resets when disconnection is accomplished and the data set becomes not-ready.
Dial disconnect not only signals the 3976-2 tolisconnect (by dropping the 'data terminal ready'.dne, Figure C-l), but also turns on the 'autodisconnect indicate' latch. The disconnect operation
turns off carrier (if it is not already off), the transmit and receive lights turn on, and the bell sounds
once. The intended method of resetting these indications of auto-disconnect is to press the EaT key.
Machine operation is normal if this is done. If the'dial disconnect indicate' latch remains on because
EaT has not been pressed, a new connection canstill be dialed. Carrier comes on and turns out thelights, but a momentary loss of carrier during the
new connection will flash the lights and sound thebell without actually disconnecting.
Notice that loss of status also causes disconnection. This occurs without the 15- second timeout, andis caused by running out of paper or loss of data set
readiness (Figure C-l). Disconnection caused bydata set not ready does not turn on the lights orsound the bell.
To summarize, a disconnect may occur becauseof loss of carrier, failure to send characters often
enough or soon enough, operator preSSing the dial
disconnect key, a terminal running out of paper, ora modem becoming non-operational. In each case,
except the last, the transmit and receive lights come
2740/2741

FETOM(9/67)

C-1

on and the bell sounds once. The proper method ofturning off the lights is to press the EOT key. Thena new connection can be dialed and normal operation
resumed. The 'TOI5' and 'dial disconnect' latches
reset automatically, and the 'auto disconnect indicate' latch is reset manually.

Generate and Print the Slash ( ! )•Incorrect case error prints II / " . World
Trade circuits pick T2, RI, R2, R2A, andR5 for II / " .

•LR C error prints II /•2B overflow prints II /•Recei ving error prints II /

".

".

".

•

Domestic 2740 circuits set 2BI for II - " .
Added World Trade circuits reset 2BI and
set 2B2, 2B6, and 2B7 for II / " .

The " / II that prints in place of the II - II is generated
as described earlier in this manual. The modification necessary for World Trade is to clear from 2B
the domestic code for II - II (2BI) and insert in its
place the World Trade code for II / II (2B2, 2B6, and
2B7). Since all errors except incorrect case aredetected before print time, this can be done as shownin Figure C-2.
The incorrect case error, which can be detected
only after the previous printout operation is complete,does not allow time to insert the " / II in 2B before
printing. Instead, tilt and rotate for the II / II are
generated directly in the print decoding circuits andshifting is inhibited (Figure C-2). World Trademachines use print decoding circuits that provide
the correct tilt and rotate; that is, T2, RI, R2,
R2A, and R5.

Line
Bit Count Even
Bit Count Odd

N

Data Set Rdy
Not Carrier

AA431
Bit Count Even
Bit Count Odd
lB SetSD4
NotC2
Not SO

Inhibit TO
FF
A
A

OR

POR-X
AA431

AA431

•

OR

(Not Send Char)Not in dial-up machine

CCI
A

Inhibit Time-out

GarbleNot Repeat
Not. POR~------~N~~~~~~----;--'--'
Data Set Ready
Not Send
OR
Inhibit Time-out ResetA(Reset Inhibit Time-out) _N_ot....;Ca;.;;;.....rri....;er~r_-L_..I----J
AA431
100M

AA311

Time Out 15-A

L . - - - - - - - - I N t---=-N..:.;:ot~SD4:;,..;...-+-_ _ _ _ _-IoDial 3976-2 Data Terminal Readyr-t-------------+-----4N~---~~--------~-.

(to modem)

Data Set Ready

Dial Disconnect

Auto Disc
Indicate Latch

Data Terminal Not Ready A~No~t~S~~~tu~s_ _ ___I OR

Fl

Rec-C
(Rec lite)

EOT-l (key)AA348Trans Lite-A

OR

POR-X

AA431
AA431

DO KeyNot CLRISSTime Out 15

FLFl
Not lCH

Not Send
Not Data Set Ready

AA311

POR
BB291

Figure C-1.
C-2

(9/67)

Disconnect Logic

T2 MD
Incorrect Case

R2 MD

R1 MD

R2AMD

R5 MD
AA252

A
Shift

OR

A

AA252
Parity Error or Not 58
Not L

Receive Text
Error

Circle B
Not C2

4J

A
L
C1

r

..----

r--A

~~

OR

A
~

2B SetRecei ve Answer-Back

Error Print

Reset
2B1 LatclY
FL

- --I

J

C2
A
Print Out Gate J

BB341

2B Reset
BB341

t---

Not 0 2B 1 (reset 2B 1)~

Clear error bit set by domestic
2740 circuits.

A
BB341

o2B2 )
02B6
02B7

Figure C-2.

) Insert World Trade error bits)

Error Print Logic

2740/2741

FETOM(9/67)C-3

APPENDIX D. DOCUMENT INSERTION 2740-2 MECHANISM

DOCUMENT INSERTION MECHANISM

shaft operates the document insertion switch (Figures D-2 and D-3). Press down on the plunger andswing the guide forward and down for document insertion (Figure D-l).
Lowering the document guide automatically lowers
the feedrolls and positions the guide so that an inserted document passes between the feedrolls andthe platen from the front. The document insertion
switch transfers as the guide opens, which activates
the terminal circuits that cause the feedroll lowering mechanism to operate (Diagram 5-46).
Closing the document guide retains the card inposition for printing and automatically raises thefeedrolls. Again, it is the document insertion
switch that begins the operation of raising the feedrolls against the card and platen.

Document Insertion Guide Assembly

Split Platen Assembly• Swings forward and down when released.

• Designed for dual-document use.

• Attached to hollow paper bail shaft.

• Allows independent spacing of right-hand document.

• Document guide lower link operates document
insertion switch via paper bail center shaft.

• Keyboard locks when platen is split and ledger
card inserted.

The document insertion guide (Figure D-l) is attachedto the paper bail shaft. The shaft is in two concentric parts; the hollow shaft carries the paper bailrolls and the insertion guide mounts, the center

The Split Platen is a two-section platen that facilitates dual-document printing. The main purpose is
to allow independent line-spacing of the right-handdocument, controlled by the central processor. The
left knob is pulled out to split the platen, and pushed
in to re-join it. The right knob operates the conventional platen vernier.
The left (platen split) pushrod (Figure D-4)
detents in two positions. As it moves from one position to the other, it moves the shift collar and left
section driver laterally. The pins that connect theseparts move through slots in the hollow platen shaft.
The ball bearing causes the locking clutch to m01e
laterally, and also allows independent rotation of
the locking clutch and the shift collar.
With the pushrod detented to the left (as shown
Figure D-4), the locking clutch (which is engaged
with the left platen section) meshes with the stationary left platen bearing. This holds the left platen
section stationary, but allows the platen shaft torotate. The right platen section and the index ratchet
are disengaged only by the platen vernier, so an indexing operation line-spaces the right-hand document.

Added mechanisms in the I/O printer provide forfront-insertion and independent spacing of the ledger
card. A manually-operated guide chute lowers to
direct the ledger card under and around the platenfrom the front. This releases the feedrolls automatically. When returned to the raised position,
the guide holds the card against the platen in theprinting area and automatically raises the feedrolls.
The platen can be split manually by pulling to theleft on the left-hand platen knob. When the platenis split, the left platen section does not rotate, but
the right section can be rotated in the usual ways.
The platen vernier is released by the right-handplaten knob on the Split Platen.

~--- Release Plunger

Document Guide(Closed)~

Front

Figure D-1.

Schematic of Document Guide Mechanism
2740/41 FETOM(4/68)

D-1

With the pushrod detented to the right, the locking clutch unmeshes from the left platen bearing andthe left section driver meshes with the left platen
section. Now, an indexing operation rotates theplaten shaft and line-spaces both platen sections.
FEEDROLL LOWERING MECHANISM• Feedrolls drop to allow document insertion.

Figure D-2.

D-2

(4 / 68 )Document Insertion Guide Closed• Feedrolls raise to hold inserted document for
printing.
• Document brake holds journal paper during
document insertion.
.. Clutch-controlled cam operates feedroll mechanism .
• Magnet-controlled latch acts as an interposer tohold feedrolls in raised position.

Cam Cycle Assembly• Operates to lower or raise the feedrolls.
• The cam cycles when the document insertion
guide is opened or closed.
• The feedroll cam follower operates the feedroll
tension spring bail.

Figure 0-3.

Figure D-5 shows the feedrolls in the normal,
raised position. In this position, the feedroll tension springs, through linkage, press the feedrolls
against the platen. Manual feedroll release rotates
the feedroll arm shaft, stretching the tension springs
and lowering the feedrolls. Automatic feedroll
lowering relaxes the tension springs by rotating thespring bail, thus allowing the feedrolls to drop.

Document Insertion Guide Open2740/ 41 FETOM(4 / 68)

D-3

In Figure D-5, assume that the feedroll cam
takes a 360 cycle. (The feedroll cam clutch, Figure D-6 , is a conventional assembly and is similar
to the other operational cams.) As the cam rotates,
it operates the follower slightly. This stretches thetension springs a little as the pushrod moves upward.
The latch, now free of pressure, can be withdrawn
while the cam follower supports the pushrod. As0the cam continues to rotate, the cam follower rides
the surface of the cam until the pushrod comes torest against the power frame base. As the pushrod
moves down, the spring bail rotates, the springs
relax, and the feedrolls drop away from the platen.
As the feed rolls drop, a rubber-tipped stop rises
to press the journal paper (left-hand document)

Left-Hand Platen Bearing(Held stationary by serrated left
platen latch) - - - - ,Left-Hand(Split Platen)
Knob

Right-Hand
Retaining Collar

Left
PlatenRetaining
Clip

Always rotates with platen shaft:
PI aten knobs and pushrods
Shift collar
Left section driver
Detent spring
Right platen section
Vernier clutch
Right-hand retaining collar

Note:
Vernier affects only right platen
section when platen is split. Thisdrawing shows the platen split.

Figure D-4.

D-4

(4/68)

Cross Section of Split Platen

Right
PlatenSection --~Right-Hand
Platen Bearing

Right-Hand(Platen Vernier)
Knob

Stationary with platen split:
Left-hand platen bearing
Locking clutch
Left platen section

against the platen and hold it in proper printing position. The cam completes its cycle with the latch
out and the feed rolls lowered.
To raise the feedrolls, the cam takes another360 cycle. The cam follower raises the pushrod,
rotates the spring bail, places tension on the springs,
raises the feedrolls against the platen, and lowers
the journal stop. The latch slides into place under
the pushrod and the cam follower lowers the pushrod onto the latch. The cam follower comes toreset, and the cam completes its cycle to the position illustrated in Figure D-5.
Refer to Figures D-6 (near right end of opera'7
tional shaft) and D-7 (right rear corner) for photographs of feedroll lowering mechanism components
in the I/o printer. Notice the cam release magnet
position and the link to the release arm. Also notethe latch, pushrod, and spring bail.
0• Latch in: feedrolls up; latch not in: feedrolls
down.
The feedroll latch acts as an interposer under thepushrod, to hold the feedrolls up against the platen.
When the feedroll cam follower raises the pushrod
off the latch, the energized feedroll latch magnet canmove the latch out from under the pushrod. The
armature attracts, the bellcrank rotates, and thelong link (Figure D-5) moves the latch aside. The
bellcrank also operates the latch switch (Figure D-8)
which signals terminal logic when the latch is in(under the pushrod). Refer to Figure D-7 for a
photograph of the latch under the pushrod. As seenin this photograph, the latch rotates clockwise to
move out from under the pushrod. ObViously, then,the schematic (Figure D-5) does not show the actual
movement. The effect is the same, however.

Latch Assembly• Controlled by magnet on right side of keyboard.

Feedroll
Tension

/~dn9

Front

SpringBail~

Feedroll

\ '

-

Cam
Follower

FeedmllShaft

Pu,h,od

A,m\ ! /

latch

/

~~\
Power frame
base

Latch Magnet Armature

Bellcrank• Stationary pivoto Moving pivot_ Direction of Motion to lower

Figure D-S.

Schematic Feedroll Lowering Mechanism

2740/41 FETOM(4/68)

D-S

Figure D-6.

0-6

(4/68 )

Feedroll Cam and Clutch

Figure D-7.

Feedroll Cam Magnet and Feedroll Latch

2740/ 41 FETOM(4/ 68)

D-7

Figure 0-8.

0-8

Feedroll Latch Magnet(4/ 68)APPENDIX E.

VERTICAL REDUNDANCY CHECK ONLY
(RPQ 858083)• Checks parity (VRC) of each transmitted andreceived character.
• No LRC checking.

1971 COMPATIBILITY FEATURE (2740-2)

NEGATIVE ANSWERBACK OVERRIDE (RPQ 858084)• Allows status answerback without paper in theterminal I/o printer.

©, ®, ter-• Special addressing sequence used (minal identification, and idle character).

• Prints a hyphen (-) to indicate an error.
The 2740-2 Record-Checking feature (descrirbed in
Chapter 4, Section 1) provides for both vertical andlongitudinal redundancy checks (VRC and LRC) withan answerback after each EOB-LRC transmitted. If
desired, RPQ 858083 provides for VRC only (parity
check without LRC). With this RPQ installed, theterminal operates similar to a 1971 terminal. The
answerback (after EOB) indicates whether a parity
error existed in the transmitted message and ahyphen (-) is printed to indicate any VRC error.
Removal of the 2740-2 Record Checking feature
is prerequisite.
V R COnly (WTC)• Checks for parity error only.
• Prints slash (/) to indicate an error.
The RPQ described above provides for "VRC only"
for WTC terminals also. The only difference is the
WTC terminal prints a slash (/) instead of a hyphen(-) to indicate a parity error.
950 BAUD (RPQ 858092)

Installation of the "negative answerback override
RPQ" allows the use of a special addressing sequenceterminal identification, and idle orinvalid character) to bring up status without paper in
the I/o printer.
When the special addressing sequence is used fora master terminal, the idle (invalid) character isused with 'control address selected' mode to satisfy
conditions to turn on the 'paper switch cheater' latch(AW BB301). The output of this latch brings up the'paper-X' line and turns on the 'space' latch. statusis brought up and the output of the 'space' latch istreated as a space in the addressing sequence. Thus,a master terminal goes to transmit status answerback
mode and transmits a 2 character answerback (qualified (y) ) to allow the system to proceed.
Slave terminals in 'control address' mode with'not message' bring up 'paper' to allow the terminal
to go to control address selected slave mode. 'Control address selected' with 'space' and 'not B' bringup 'E set gate' to place the terminal in control selected slave mode.
The special addressing sequence is used at theoption of the programmer, possibly after the firstnormal addressing sequence received a negative
response.
There are no prerequisites for this RPQ.

( © , ®,• Receive and Transmit at 950 bps (105.5 cps)
The 950 baud RPQ equips the terminal with a faster
oscillator to increase the line speed to 105. 5 characters per second.
The terminals having this RPQ installed will
operate only with a WE202D data set.
The Buffered Receive feature is a prerequisite.

RETRANSMIT ONCE RECEIVE CHECK ANSWERBACK(RPQ 858095)• Turn on 'retransmit' latch with first transmission.
• A eX) answerback returns the terminal to transmit text mode.

2740/41 FETOM(1/69)

E-1

®

• A
answerback (after first transmission)
returns the terminal to transmit text to retransmit message.

®

• A second
answerback causes the Reset lightto turn on, the alarm to ring, and the terminal
to be placed in control receive mode.

©

• A
answerback for either transmission causes
the Reset light to turn on, the alarm to ring andthe terminal to return to control receive mode.
The 'retransmit' latch is turned on with the transmission of the first message. After transmissionof the message, the terminal goes to receive checkanswerback mode. In this mode, a character isreceived from the central processor to indicate if
the message was received correctly, If so, theterminal receives afor an answerback, returns
to transmit text mode, transmits aand goesto control receive mode.

GJ

E-2

(4/68)©'

answerback, returns to transmit text mode, transmits aand goes to control receive mode.
If the message was not received correctly at thecentral processor, it returns acharacter.
This causes the terminal to return to transmit text,
retransmit the message, and turn off the retransmit
latch. If the message is again received in error,
the central processor again returns awhichwith 'not retransmit' causes the terminal to return
to transmit text mode, transmit a
indicate anerror (ring alarm, turn on Reset light) and then go
into control receive mode. The central processor
can be programmed to return aas the answerback following either transmission to place the terminal in control receive mode after indicating anerror by turning on Reset light and ringing the alarm.
The prerequisite for the Retransmit Once RPQ is
the Record Checking Feature (regular or VRC only).
For a more detailed description of "Receive
Check Answerback" refer to Chapter 4, Section 1.

©,

®

®,
©,

©

APPENDIX F. ERROR-RECOVERY TABLES (2740-2)

ERROR-RECOVERY PROCEDURES
The charts in Tables 1 through 7 illustrate various
error conditions. They indicate the line response(if any), the indicator(s) turned on, and the procedure
for recovery.
1. Receive Operation--without Record Checking

Table F-1.

2. Receive Operation--with Record Checking
3. Transmit Operation--Buffer to Communications
Line
4. Enter Status-- Local or Communicate Mode
5. Buffer Printout-- Local Mode
6. Terminal Addressed by CPU
7. Terminal Polled by CPU

Receive Operation--without Record Checking Feature

Type of Error

Buffered
Receive

Buffer print parity
error.

Yes

Incorrect case.
Detected during
buffer print.

Yes

Buffer overflow.

Yes

Lose forms while
receiving from line.*

With orWithout

Yes

Incorrect case.

No

Receive parity
error.

Reset light ON, charactermayor may not be printed,
and alarm sounds.

/

No

With orWithout

Recovery@Printed hyphen.
None

Lose forms while
printing out from
buffer. ""Overflow printer.

Terminal Responseto next Add. Seq.

Indicator

message. (At 600
or 950 BAUD the operator
may not see the Reset light.)

Send message to request
retransmission.

Ga~bles

Receive light turns OFF andStandby light fails to turn ON.

None

9

Insert forms and send message to request retransmission.

Standby light fails to turn ON
after message is printed out.

9

Print hyphen. Reset light ON
until
is received.

None

Characters omitted. Resetlight ON until
is received.

None

Parity light on. Reset light
ON untilis received.

U

©

©

* Forms must be missing when the terminal is addressed for 9©

@@
Send message to request
ret ransmission

G)

Press parity reset switch.
Send message to request
retransmission.

® response.

2740/41 FETOM(1/69)

F-1

Table F-2.

Receive Operation--with Record Checking Feature

Type of Error

Buffered
Receive

Pari t y error.
No stop bit.

Yes

LRC error.
Yes'Terminal Response
To EOB-LRC To next
Add. Seq.

Indicator
Reset light ON until response
is sent.
!Une Parity light ON.
Insert hyphen in buffer.
Message will not buffer
print.
Reset light ON until response
is sent.
Message will not buffer print.

@)

RecoveryU

G)

CPU retransmits message.

U

G)CPU retransmits message.

Insert forms.
Post conditions to user.

@

No stop bit.

No

Line Parity light ON.
Reset light ON until response
is sent. Print hyphen.

LRC error.

No

Reset light ON until
response is sent.

@

Lose forms while
receiving datafrom line.

With orWithout

Receive light turns OFF andStandby light fails to turn ON.

None (CPUtimes out)

9@

Lose forms while
printing out from
buffer.

Yes

Standby light fails to turn ON
after message has printed out.

None

9

@

Buffer overflow.

Yes

©

None

Post error message touser.

Reset light ON. Charactersomitted and hyphen printed
at LRC check.

©

None

Post error message touser.

Reset light ON. Alarm
sounds. Character mayor may
not be printed.

None

/

None

None

Send error message toCPU.

Print hyphen. Reset light
ON (turned off by
answerback).

©

None

Post error message touser.

Reset light ON until reset by
response. Message will
not buffer print.

®

®

/

G)

Pari ty error.

®

*

*

Message will not buffer print.
Reset light ON until turned offbyanswerback. (The operator may not see the light. )©

Overflow printer.

No

Buffer parity error
while printing out
message.

Yes

Incorrect case(detect during
print -out).

Yes

Incorrect case.

No

G)

Print hyphen.

©

Insert forms and send mes
sage to request retransmission.

Press Reset key. Send
error message to CPU.

CPU retransmits message.

Buffer error
while receiving.

Yes

Receive parity
error.

With orWithout

Parity light ON. Reset light
ON until response is sent.

@ **

U

G)

1/ 0 Error while printing.

Without

Reset light ON.

®

S@ CPU retransmits message.

* Forms must be missing when the terminal addressed for 9 @response.
** The same conditions that set the'receive parity error'latch also set the'error/trigger.

F-2(] /69)Press parity reset switch
to turn off parity light.

Table F-3.

Transmit Operation--Buffer to Communications Line

Type of Error

RecordChecking

Buffer VRC error.

Yes

Reset light ON.
sounds.

Alarm

® or©

Buffer VRC error.

No

Reset light ON.
sounds.

Alarm

None

Responsefrom CPU

Indicator

Alarm sounds.
light ON.

Reset

Press local switch.
Press Reset key.
Rekey message.

Y@*

Press local switch.
Press Reset key. Rekey
message. Post systemerror to user.

or garbles
answerback

Space

@

Automatic retransmissionof message.

©

Space

GJ

Press Reset key, press Bid
key, and wait to be polled.

Space

G)

Press local switch, thenReset key, and switch
back to communicate mode.

Y@

Press parity reset switch
to turn off the parity
light.

Y

G)

Press parity reset.
Message retransmission
is automatic.

No response

None

No

Parity light ON.

Transmit parity error.

Yes

Parity light ON*Note: Buffer VRC error should also cause a transmit parity error which will force a

Table F-4.

@*

Reset light ON and
Receive light ON.

Transmit parity
error.

Recovery

Y

®

None
No error detected
in 2740.
Yes

Term. Responseto next Add.

®
Y @ response.

Enter Status--local or Communicate Mode

Type of Error

Indicator

Recovery

Buffer parity error.

Reset light ON.
Keyboard locked.
Alarm sounds

Press Reset key, press Enter key, and rekey
message.

Buffer overflow.

Alarm sounds eight characters before end of buffer,and keyboard locks at endof buffer.

Message can be sent as is, or press Reset andEnter keys to reload message.

lose forms while entering data.

None.

load forms if hard copy is desired.

No forms.

Enter light fails to turn
ON when Enter key ispressed.

load forms.

Indicator

Recoverylocked.

Reset light ON and keyboard
Alarm sounds.

Press Reset key, press Ent er key, and rekey
message.

Print hyphen.

Use backspace or edit keys, or rekey message.

Table F-S.

Buffer Printout--local Mode

Type of Error
Buffer parity error.

Incorrect case.

2740/41 FETOM(1/69)

F-3

Table F-6.

Status/Answerback when Terminal with Receive Status is Addressed by CPU

Terminal Condition

Buffered
Receive

Terminal
Response*

No Error Stored

With orWithout

SpaceElectronic hardware error on
last message

With

/

G>

I/O Error on last message
received

With orWithout**

S

G)

Line VRC error during
last message received

With orWithout

U

G)

Terminal induced VRC error
during a transmitted message

With orWithoutyG>

G>

Recovery Procedure

None required

Note:
When messages are received in error
by terminals without Record Checking,
the CPU is not informed. However, atthe option of the program, the previous
message may be retransmitted uponreceipt of the addressing response.

Message retransmitted at
the programs option.

Note: *The qual ified (2) response to the CPU is intended for condition statistics. All of the firstcharacters except space should be stored or printed for error analysis.
**Without Buffered Receive Feature a parity error in the 1B or 2B register will cause theI/O error latch to be set.

Table F-7.

Status/ Answerlnck when Terminal without Receive Status is Addressed by CPU

Terminal Status

See
Note

Bid Latch is on*

In Enter while in Communicate mode*

Buffer print in Commun icate mode*

In Local mode**

Ready except out ofpaper
Ready except document device is down
No power on terminalor data set

Indication at Terminal

Attention Iight on

Terminal
Response

Recovery Procedure2(8)Wait to be polled or go to
local mode and press Reset key.

1(8)Complete entering, press Bid
key and wait to be polled orpress Reset key

**

4(8)
8(8)
9(8)

Load paper

**

@(8)

Raise document device

None (CPUtimes out)

Turn power on. CPU should
post error condition to user.

Gaining status willturn off attention light

None

Switch to Communicate mode.

Note: *Should be considered status or buffer busy conditions. Program should go to other business and also poll theterminal before re-addressing for bid, or enter in communicate mode.
** Should be considered as operator errors. Program should retry twice and then post an error condition to user.

F -4(1/69)

Table F-8.

Terminal Polled by CPU

Terminal Status

Terminal Response
to Poll:Recovery

Enter or buffer print.

®

For Enter Mode, Press Communicate switch,press Bid key, and wait to be polled. Normal condition.
System should continue polling.

Not in communicate mode.

@)

Press Ent er key and key message. Press Communicate
switch. Press Bid key and wait to be poned. Normal
condition. System should continue polling.

Bid key not operated.

®)

Press Communicate switch. Press Bid key if message
has been entered. Normal condition. System should
continue polling.

No power on terminal or data set

None

Turn power on. System should repoll twice. Aftersecond retry, post condition to user (what the condition is and when it occurred).

2740/41 FETOM( 1/69)F-5

INDEXA Trigger 3-1
Addressing 4-16
Addressing Identifier 4-18
Addressing Mode Sequence 4-15
Alarm Bell 3-11, 4-18
All Call Address 4-15
Answering Data Set 4-11
Attachment for 2760 4-33
Attention Key 3-8, 4-10
Auto Check Switch 4-10
Auto EOB 1-3, 4-10
Auto EOB Trigger 4-10
Auto EOM
4-38

Auto EOT Trigger

3-9

B Trigger 3-1, 3-10
Back Space 2-13
Back Up Control 4-31
BCD-to-I/O Conversion 1-10
Bell 3-11, 4-18
Bid 1-8
Bid Trigger 3-10
Bit Time 2-11
Buffer Address (BA) Triggers 2-12
Buffer Expansion 1-8, 4-22
Buffer Print 1-7, 3-13
Buffered Receive 1-8, 4-25
Buffer Storage
Address Counter 2-11
Address Register 2-12
Address Register Control 2-12
Array and Addressing 2-15
Bit Counter 2-12
Buffer Data Control 2-16
Buffer Sense Line Output 2-16
Character Cycle 2-11
Character Storage Concepts 1-19
Magnetic Core Theory 2-7
Memory Clock 2-15
Odd Even Core Scheme 2-10
Read Out Operation 2-17
Store Operation 1-16, 2-17
Temperature Compensation 2-17
CA-X Latch 3-19
Carrier-CF 3 -20
Carrier Return Key
3-8, 4-23
Cartridge
4-35, 4-39
CR/LF Key 1-9
CCl 2-3
CC2 2-3
CE Aid Box 6-1
Characteristics A-l
Character Format 1-11
Check Loop 6-3
Check Switch 4-10
Clear to Send-CB 3-19

ClocksControl 2-3
Serdes 2-2
Comm/Local 1-3, 2-6
Contention 4-14
Control Address Mode 4-18
Control Address/Selected Mode 4-18
Control Address/Selected Slave Mode 4-18
Control Characters
Basic Terminal 3-4
Record Checking 4-1
Station Control 4-15
Transmit Control 4-14
Control Clock 2-3
Control Clock Sequence 2-3
Control Receive Mode 3-1, 4-18
Control Selected Mode 4-17
Control Selected Slave Mode 4-17
Control Unit
3-10
Coordinates, V and H
4-35
Correspondence-to-I/O Conversion 1-10
CR Latch 3-9
CR Character Detection 4-29, 4-32
Cycle Inlk Latch 6-2
Cycle Pushbutton 6-1
Cycle Trigger 6-2
C 1 Trigger 2-3
C2 Trigger 2-3
D Trigger 4-7, 4-18
Data Button 4-11
Data Flow 1-12, 1-19
Data Representation 1-10
Data Set Ready-CC 3-19
Data Terminal Ready-CD 3-20
Deserializa tion 2-1
Detect CR Character 4-29, 4-32
Dial-Connect Light 4-11
Dial Disconnect Key 4-12
Dial Disc Latch 4-12
Dial-Up 1-4, 4-11
Document Insertion 1-9, D-l
E Trigger 3-10
Edit 1-9, 4-29
Edit Control 1 Trigger 4-30
Edit Control 2 Latch 4-30
Edit Control 3 Trigger 2-13, 4-29
End of Block 4-5, 4-10
End of State Latch 4-6, 4-21
End of Transmission 3-3Enter 1-7, 1-13, 3-10
Enter Key 1-9
Enter Serdes Gate Trigger 3-2
Enter Serdes Trigger 3-3
Enter Time-out 1-14, 4-18
EOB Character 4-1, 4-5

X-1

EOB Check 4-1
EOB Gate Trigger 4-5
EOB Key 4-1, 4-5
EOB Trigger
4-5, 4-10
EOM Mode
4-38
EOT Character 3-3
EOT Key 3-2, 4-10
EOT Trigger 3-2, 3-9
Error Conditions F -1
Error Storage (2740-2)
Electronic Error 3-17
I/O Error 3-17
Receive Parity 3-18
Transmit Parity 3-18
Error Trigger
4-3, 4-8
F Character 4-36
F Trigger 4-6, 4-18
Filmstrip Motion Control
Force CR Latch 4-10
Function Control 4-36
Function Decode2-5

EOT 3-2, 4-10
Line Return 1-9, 4-29
Line Type 1-9, 4-29
Loc/Comm 1-2, 3-9
Reset 3-10, 3-12
Restart 4-1, 4-7
RST 1-7,.4-10
Shift 3-9
K1 Relay 3-6
LRC 4-1
L Trigger 4-3, 4-6
Latches
CR 3-9Cycle Inlk 6-2
Dial Disc 4-12
Edit Control 2 4-30
Electronic Error 3-17
End of State 4-6
EOB Gate 4-5
Force CR 4-10
Initial Lower Case 3-7, 3-15
I/O Cycle 2-6, 3-5
I/O Error 3-17
Line Return Enable 4-30
Line Type Inhibit 4-30
Parity Error or Not S8 4-2, 6-1
Receive Parity Error 3-18
Rekey 3-12, 3-14~ 4-8
Rekey Reset 4-8
Reverse Count Once 4-28, 4-31
Set Buffer Print 3-14, 4-29
Split Platen 4-25
Store LC Code 4-30
Time Out 1 3-7Time Out 15 4-16, 6-3
Transmit Parity Error 3-18
1B-Register 2-3
2B-Register 2-4
2B Upper Case 4-29

4-35

Garble 4-16
Garble Triggers 4-16
Generated Data 2-4
Group Address 4-16
Handshaking Procedure 4-11
Header Control 1-9, 4-26
Horizontal Current 2-11
Horizontal Current Control Gate
Horizontal Drivers 2-12
Horizontal Switches 2-6
I/O Cycle Latch
I/O Error 3-17

2-16

3-5

I/O Motor Control
3-6, 3-16
Image Index Counter
4-36
Incorrect Case 3-7, 3-16
Indicators (See Ligh1x)
Initial Lower Case Latch 3-7, 3-15
Initial Lowercase 3-7, 3-15
Inter~ace, Terminal to Line Adapter
Interlocking 2740/2760 4_34
Intermediate-Control/Receive Mode
Intermediate-Polling Mode 4-21
Interrupt, Receive
1-5, 4-22
Interrupt, Transmit
1-5, 4-42
Interrupt Trigger 4-22
Jumpers

4-18

Keyboard Lock 3-6,3-16
Keyboard Shift-Trip 3-15
Keys
Attn 3-8
Backspace 4-21
Bid 1-8, 3-2, 3-12
Carrier Return 3-8, 4-23
CR/LF 1-9
Dial Disc 4-12Enter 1-9, 3-10
EOB 4-1,4-5
X-2

3-19
4-13

LightsBid 1-8
Dial Conn 4-11
Enter 1-7, 3-10
Receive F-1
Reset 3-10, 4-2, F-1
Restart 1-7
Standby 1-8, 3-10
Transmit F-1
Line Return Key 1-9, 4-29
Line Type Key 1-9, 4-29
Loc/Comm Key 1-2, 3-9Long Function 3-6
LRC Character 4-1, 4-9
LRC Check 4-1
LRC-Register 4-3
LRC-Register Control

Manual EOM Mode
4-38
Manual Frame Advance
4-39
Master 4-18
Message Format, 2760 4-37

Mode Change Trigger
3-1,4-4
Modes
Auto EOM 2760
4-38
Control-Address 4-18
Control-Address/Selected 4-18
Control-Address/Selected-Slave 4-18
Control-Receive 4-2, 4-15
Control-Selected 4-17
Control-Selected-Slave 4-17
Intermediate-Control/Receive 4-13
Intermediate-Polling
4-21
Manual EOM 2760 4-38
Receive-Check/Answerback 4-6
Receive-Control 3-8
Receive-LRC 4-1, 4-8
Receive-Text 3-1, 4-3
Receive-Text-Slave 4-17
Text-Non-Selected 4-15
Transmit-Check/Answerback 4-9
Transmit-LRC 3-13, 4-6
Transmit-Poll/Answerback 4:-21
Transmit-Status/Answerback 4-18
Transmit-Text 3-1, 4-6
Transmit-Text/Lock 4-4, 4-7
Multipoint 1-2, 1-3
Negative Response

4-15

Odd-Even Core Scheme 2-10
Operate Trigger
2-7
Optical Image Unit
1-4, 4-33
Originate-CY 3-17
Originating Data Set 4-11
Overflow (2B) 3-5
Parity Check 3-13
Pari ty Error 4-2
Parity Error Latch 3-20
Pari ty Error Light F -1
Parity Error or Not S8 4-2, 6-1
Parity Error Trigger 4-2
PE or Not S8 Latch 4-2, 4-6
Point-to-Point 1-2, 3-1
Polling 4-19
Power on Reset 3-6, 5-1
Power Supply
5-1
Prefix Character
4-38
Print Decode2-5Print Inhibit CPU control (2741)
1-5, 4-43
Probe
4-35
Pushbuttons (See Keys)
Read Time 2-4, 2-11
Read/Write Trigger 2-16
Receive 3-4, 3-13
Receive-Check/Answerback Mode 4-6
Receive Control Mode 3-8
Received Data-BB 3-19
Receive EOB Character 4-8
Receive Interrupt (2741)
1-5, 4-22
Receive LRC-Character 4-8
Receive-LRC Mode 4-8
Receive Parity Error 3-18
Receive Text 4-15
Receive Text Buffer 4-25

Receive-Text Mode 3-1
Receive-Text Slave Mode 4-17
Record Checking 1-3, 4-1
Registers
1B 2-3, 3-2
2B 2-4, 2-5
LRC 3-13, 4-3
S 2-1
Relay Kl 3-6
Repeat Trigger 6-5
Request to Send-CA 3-19
Reset Key 3-10
Reset LRC Reg Trigger 4-4
Reset LRC Register
4-4
Response Point Coordina tes
4-35, 4-38
Restart 4-6
Restart Key 4-7
Restart Light F-1
Restart Trigger 4-7
Reverse Transmission 4-7
RST Key 1-7, 4-10
S Reg Empty Trigger 3-3
S-Register 2-1, 2-2
Screen and Probe
4-35
SDAC
2-2
2-2
SDAC1
SDAC2 2-2
SD1 Trigger 2-2
SD2 Trigger 2-2
SD3 Trigger 2-2
SD4 Trigger 2-2
Sense Line 2-16
Sense Wire 2-10
Serdes Clock 2-2
Serialization 2-1, 2-13
Set LRC Reg Trigger 4-4
Single Cycle 6-1
Signal Ground-AB 3-19
Slave 4-18
Space Generator 6-3
Space Switch 6-3
Special Circuits B-1
Special Features
2740-1 1-3
2740-2 1-82741 1-5
Speed Base 600 bps 1-8, 4-28
Split Platen 1-10, 4-25
Standby 1-8, 3-10
Start Bit 1-2
Station Control 3-10, 4-14
Status 2-6
Status Inhibit 3-10
Status Trigger 3-1, 4-16
Stop Bit 1-12, 4-3
Stop Clock Trigger 6-2
Stop Code 3-12Store Received Character 4-25
Strobe and I/O Cycle 2-6
Strobe 0 Trigger 2-6, 3-2
Strobe Trigger 2-6
Switches
Auto Check 4-10
Transmit Control 4-13
X-3

Telegraph 4-28
Telegraph Line Adapter 1-8
Terminal Address 1-8
Terminal Mode Operation 3-10
Text-Non-Selected Mode 4-15
Thermistor 2-18
Time Out 1 Latch 3-7Time Out 15 Latch 4-16
TOM 2B Reset Trigger 4-23
Transformer 5-1
Transmit 3-1, 3-13
Transmit Control 1-4, 4-13
Transmit Check/Answerback Mode 4-9
Transmit Control Character Sequence 4-13
Transmit EOB Character 4-5
Transmit-LRC Character 4-6
Transmit-LRC Mode 4-6
Transmit-Poll/Answerback Mode 4-19
Transmit Parity Error 3-18
Transmit-Status/Answerback (2740-1) 4-15, 4-19
Transmit-Status Answerback (2740-2) 1-19, 3-18, 4-15
Transmit-Text Mode 4-6
Transmit-Text/Lock Mode 4-4, 4-7
Transmit Data-BA 3-17
Transmit Interrupt
1-5, 4-42
Triggers
A 3-1, 3-10
Auto EOB 4-10
Auto EOT 3-9
B 3-1, 3-10
Bid 3-1
Buffer Address (BA) 2-12
Buffer Print 2 -13, 4-29
Buffer 2B Reset 2-13, 4-31
Comm/Local 6-5
Cycle 6-2
Cl 2-3
C2 2-3
D 4-7
Drive Down 4-27
Drive Up 4-27
E 3-10
Edit Control 1 4-30
Edit Control 3 2-13, 4-29
Enter 2-13, 3-10
Enter Serdes 3-3Enter Serdes Gate 3-2
EOB 4-5,4-10
EOT 3-2,3-9
Error 3-7, 4-3
F 3-10, 4-7
Frequency Division 1 4-28
Frequency Division 2 4-28
Garble 1 4-16
Garble 2 4-16
Header Storage Buffer Address Set 4-26
HICG 2-16
Interrupt 4-22
L 4-3,4-8
Line Return 4-30

X-4

LRC-Register 4-3
Memory Buffer 2-16, 3-11
Mode Change 3-1, 3-6
Odd Parity 3-11
Operate 2-7
Pari ty Error 4-2
Read/Write 2-16
Repeat 6-5
Reset Buffer 4-27
Reset Buffer Address 2-15
Reset LRC Reg 4-4
Restart 4-7
Reverse Count Sequence 2-13, 4-30
Reverse Count Sequence Control
SDI 2-2
SD2 2-2
SD3 2-2
SD4 2-2
SO
3-5
Set LRC Reg 4-4
S-Reg Empty 3-2
S-Register 2-1
Status 2-7, 3-1
Stop Clock 6-2
Store Stop Code 4-30
Strobe 0 3-2, 6-3
TOM 2B Reset 4-21
Type 4-21
VICG 2-16
Xmit Odd Parity 3-17
2BR 3-6
2B Reset 3-6
2B Reset Gate 3-5
2B Set 3-5
Typamatic 1-5, 4-21
Type Trigger 4-21
Typewriter 1-7
Vertical Current 2-11
Vertical Driver 2-12
Vertical Switch 2-12
VICG 2-16
Voltages 5-1
VRC Check 4-1, 4-2
IB Generate 3-2
1B Register 2-3
ICh Switch 6-1
IS-Second Time Delay 4-16, 6-3
2B Overflow Reset 3-5
2B Reset Gate Trigger 3-5
2B Set Trigger 3-5
2B Register 2-4
2B Reset Trigger 3-6
2BR Trigger 3-6
1971 Compatibility E-l
2760 Attachment
1-4, 4-33
2760 Receive Format
4-37
2760 Transmit Format
4-37

2740 Communication Terminal Modell
2740 Communication Terminal Model 22741 Communication Terminal
Theory of Operation

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