TDA21570

1

Description• High frequency, low profile DC-DC converters;• Voltage Regulators for CPUs, GPUs and DDR memory arrays;• Telecom controlled and uncontrolled

The TDA21570 integrated power-stage contains a low quiescent current synchronous buck gate-driver IC which isco-packed with control and synchronous MOSFETs along with an active diode structure that achieves low Vsd
similar to a schottky with very little reverse recovery charge. The package is optimized for PCB layout, heattransfer, driver/MOSFET control timing, and minimal switch node ringing when layout guidelines are followed.
The paired gate driver and MOSFET combination enables higher efficiency at lower output voltages required by
cutting edge CPU, GPU and DDR memory designs.
The internal MOSFET sensing achieves superior current sense accuracy vs. best-in-class controller-based Inductor
DCR sense methods.
Protection includes IC temperature reporting and over temperature protection feature (OTP with thermal
shutdown), cycle-by-cycle over current protection (OCP), control MOSFET short detection (HSS - High side short
detection), VDRV and bootstrap under-voltage protection. The TDA21570 also features "refreshing" of bootstrap
capacitor to prevent the bootstrap capacitor from over-discharging.
Operation of up to 1.5 MHz switching frequency enables high performance transient response, allowing
miniaturization of output inductors, as well as input and output capacitors while maintaining industry leading
efficiency.

Features• Integrated driver, active diode, control MOSFET Q1 and synchronous MOSFET Q2• On-chip MOSFET Current sensing and reporting at 5 µA/A.
• Input voltage (VIN) range of 4.25 V to 16 V
• VCC and VDRV supply of 4.25 V to 5.5 V• Output voltage range from 0.225 V up to 5.5 V at VIN = 12 V
• Output current capability of 70 A
• Operation up to 1.5 MHz• Enhanced Fault reporting and identification• VDRV under voltage lockout (UVLO)• Bootstrap under-voltage protection• 8mV / °C temperature analog output• Over temperature protection and thermal shutdown• Cycle-by-cycle over current Protection (OCP) and flag
• Control MOSFET short (HSS) detection and flag
• Auto-replenishment on bootstrap capacitor• Compatible with 3.3 V tri-state PWM Input• Body-Braking™ load transient support• DEEP SLEEP mode for power saving via EN= low (32 µA typ)• Small 5 mm x 6 mm x 0.9 mm PQFN package• Lead free RoHS compliant package
Please read the Important Notice and Warnings at the end of this document

www.infineon.com

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OptiMOSTM Powerstage
TDA21570
Description
Table 1

Product Identification

Part Number

Temp Range

Package

Marking

TDA21570-40 to 125C

PQFN 5 mm x 6 mm

TDA21570

Figure 1

Picture of the Product2

Description

2.1

Pinout`Figure 2

Pinout, Numbering and Name of Pins (transparent top view)
Note: Pin 7 omitted for compatibility with TDA2147x2

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OptiMOSTM Powerstage
TDA21570
Description
Table 2I/O Signals

Pin No. Name

Pin Type Buffer Type Function

6, 41

GL

I/O

AnalogLow-side MOSFET driver pin that can be connected to atest point in order to observe the waveform.

10-19

SW

O

AnalogSwitching node of synchronous buck converter.

32

PHASE

I

AnalogSwitching node. For Bootstrap capacitor connection only.

33

BOOT

I

AnalogBootstrap capacitor connection. Connect an X7R ceramic
capacitor with value between 0.22 µF to 0.56 µF from
BOOT to PHASE pin. Recommended value is 0.47µF. The
bootstrap capacitor provides the charge to turn on thecontrol MOSFET. For VIN > 13.2 V, a 2-Ω bootstrap resistor
in series with the capacitor is required to help reduce SW
ringing and EMI.

34

PWM

I/O

+3.3 V logic

3.3 V logic level PWM input. PWM input: “High” turns
control MOSFET on; “Tri-state” turns both MOSFETs off;
“Low” turns the synchronous MOSFET on.

35

EN

I

+3.3 V logic

Pulling EN high enables the driver; pulling EN low disables
the driver and enters ultra-low quiescent current mode.
Floating this pin is not recommended, however a pulldown is embedded to keep the driver off if the pin is
floating. Pin is VCC tolerant.

36

TMON /FAULT

O

Analog

The voltage at this pin is defined by the equation
8mV * (Celsius Temperature) + 0.6 V. This pin will bepulled up to 3.3 V under severe over-temperature, overcurrent, HSS or bootstrap under-voltage condition.

38

IMON

O

AnalogSensed current output signal referenced to the IMONREF
pin through external resistor. V (IMON – IMONREF) voltage
across that resistor represents current information.

39

IMONREF

I/O

AnalogThis pin provides a system reference for the IMON
information. This pin can be tied to a fixed voltage
between 1.1 V and 1.9 V such as bias rails of a PWM
controller.

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OptiMOSTM Powerstage
TDA21570
Description
Table 3

Power Supply

Pin No.

Name

Pin Type

Buffer Type Function

4

VDRV

POWER

–

The supply of gate driver. Connect a 1 µFcap between
VDRV and PGND. VDRV should be connected to +5 V power
supply.

3

VCC

POWER

–

Bias voltage for control logic. Connect a 1 µFcap between
VCC and AGND. VCC should be connected to +5 V power
supply.

25-30

VIN

POWER

–

4.25 V to 16 V high current input voltage connection.

Table 4
Pin No.

Not ConnectedName

1, 31, 43, 42 NC
Table 5

Pin Type

Buffer Type Function––

Leave the pin unconnected.

Ground Pins

Pin No.

Name

Pin Type

Buffer Type Function

2

AGND

GND

–

Signal ground. All interface signals are referenced to thispin.

5, 8, 9, 2024, 37

PGND

GND

–

Power ground. It is also the power ground of thesynchronous MOSFET.

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OptiMOSTM Powerstage
TDA21570
Simplified Block Diagram3

Simplified Block Diagram

Figure 3 Simplified Block Diagram5

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OptiMOSTM Powerstage
TDA21570
Electrical Specification

4

Electrical Specification

4.1

Absolute Maximum Ratings

Note: TA = 25 °C

Stresses above those listed in Table 6 “Absolute Maximum Ratings” may cause permanent damage to the device.
These are absolute stress ratings only and operation of the device is not implied or recommended at these or any
other conditions in excess of those given in the operational sections of this specification. Exposure over values of
the recommended ratings for extended periods may adversely affect the operation and reliability of the device.

Table 6

Absolute Maximum Ratings

Parameter

SymbolValuesUnit Note

Min.

Typ. Max.

0.1

–

1.5

MHz

Maximum average load current IOUT

–

–

70

A

Input Voltage

VIN

-0.30

–

25

V

Pin VIN

Logic supply voltage

VCC

-0.3

–

6.5

V

Pin VCC

High and low-side drivervoltage

VDRV

-0.3

–

6.5

V

Pin VDRV

Switch node voltage

VSW (DC)

-1

–

25

V

Pin SW

VSW (AC)

Below -5V for 5ns–

34 for 1ns

VPHASE (DC)

-1

–

25

V

Pin PHASE

VPHASE (AC)Below -5V for 5ns–

34 for 1ns

VVIN-PHASE(DC)

-1

–

25

VVIN-PHASE(AC)Below -5V for 5ns–

34 for 1ns

VBOOT (DC)

-0.3

–

29

V

VBOOT (AC)Below -0.3V for 5ns

–

–

V

VBOOT-PHASE

-0.3

–

6.5V (DC),
7.5V for 3ns

GL voltage

VGL

-0.3

–

6.5

V

Pin GL

EN voltage

VEN

-0.3

–

6.5

V

Pin ENPWM voltage

VPWM

-0.3

–

3.6

V

Pin PWM

TMON voltage

VTMON

-0.3

–

3.6

V

Pin TMON /FAULTIMON voltage

VIMON

-0.3

–

3.6

V

Pin IMONIMONREF voltage

VIMONREF

-0.3

–

3.6

V

Pin IMONREF

NC Pin (Pin 43) voltage

V43

-0.3

–

0.3

V

Pin NC

Junction temperature

TJmax

-40

–

150

C

–

Storage temperature

TSTG

-55

–

150

C

–

Frequency of the PWM input

PHASE voltage
VIN-PHASE Voltage
BOOT voltage

fSWV
Pin BOOT–

Note: All rated voltages are relative to voltages on the AGND and PGND pins unless otherwise specified.
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OptiMOSTM Powerstage
TDA21570
Electrical Specification

4.2

Thermal Characteristics

Table 7

Thermal Characteristics

Parameter

SymbolValues
Min.

Typ.

Max.

–

1.5

–

Thermal resistance-Junction to θJC_PCB
PCB (pin 24)

Unit

Note / Test Condition

K/W–

Thermal resistance-Junction to θJC_Top
–
16.7
–
–
top of package–––
Thermal resistance to ambient θJANote
20.5
Note: Thermal Resistance (θJA) is measured with the component mounted on a high effective thermal
conductivity test board in free air.

4.3

Recommended Operating Conditions

Table 8

Recommended Operating Conditions

Parameter

SymbolValues
Min.

Typ.

Max.

Unit

Note / Test Condition

V–

Input voltage

VIN

4.25

–

16

MOSFET driver voltage

VDRV

4.25

–

5.5

–

Logic supply voltage

VCC

4.25

–

5.5

–

Frequency of the PWM

fSW

100

–

1500

kHz

-

EN voltage

VEN

–

–

5.5

V

Pin ENPWM voltage

VPWM

–

–

3.6

V

Pin PWM

Current Sense reference voltage

VIMON_CM

1.1

–

1.9

V

Pins IMON, IMONREF

Junction temperature

TjOP

-40

–

+125

°C

–

4.4

Electrical Characteristics

Note: VDRV = VCC = 5 V, TJ = 25 °C, VIMONREF = 1.2V
Table 9Voltage Supply, Biasing Current

Parameter

SymbolValuesMin.

Unit

Note / Test Condition

Typ. Max.

UVLO VDRV rising

VUVLO_R

–

4.05

–

UVLO VDRV falling

VUVLO_FVUVBOOT_R

–

–

–

3.85
3.82

VUVBOOT_F

–

3.61

–

IVDRV

–

29

–

mA

EN = H, fSW = 600 kHz, D=15%

–

2.5

–

µA

EN = L

–

8

–

mA

EN = H, fSW = 600 kHz, D=15%

–

30

–

µA

EN = L

–

–

5

µA

No switching, EN=L

Bootstrap Under voltage
rising threshold
Bootstrap Under voltage
falling threshold

Driver current
Supply Current
VIN Current

IVcc
IVIN

V

–

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OptiMOSTM Powerstage
TDA21570
Electrical Specification
Table 10

Current Sense

Parameter

SymbolValues

Unit

Note / Test Condition

Min.

Typ.

Max.

IMON IMON Voltage range VIMON

0.8

–

2.35

V

DC + AC componentsNote 1

IMON/IMONREF
reference voltage
range

VIMON_CM

1.1

–

1.9

V

Reference Voltage connected
externally for the current sense
signalCurrent sense gain

Acs

–

5

–

µA/A

IMON Gain resistor
range

Table 11

RIMON

1

-

SymbolTMON Temperature/
Sense Slope
FAULT Temperature
Sense Offset
Voltage

Values

Note / Test Condition

Min.

Typ.

Max.

-

8.0

-

mV/°C

25°C ≤ TJ ≤ 125°C, Note 1

-

800

-

mV

TJ = 25°C, 0.6 V + 8 mV/°C * TJ

ATMPGAIN
VTMPOFFSE
T

SymbolValuesMin. Typ.

PWM

Unit

Other Logic Functions, Inputs/Outputs And Thresholds

ParameterENkΩ

Temperature Sense and Fault Communication

Parameter

Table 12-

Resistor to be connected
between IMON and IMONREF. For
5mV/A, recommended 1kΩ RIMON

Enable Power-on
Delay

Unit

Note / Test ConditionMax.

tEN_ondelay

-

17

-

μs

PWM=0. Measured from EN risingedge to VGL> 1 V. Note 1

Enable Power-off
tEN_offdelay
Delay

0.1

-

1

us

PWM=0. Measured from EN fallingedge to VGL < 4 V. Note 1

Internal Pull
down Resistance

RPULLDN_EN

-

280

-

kΩ

When EN is floating

Input High
Voltage

VEN_H

2.0

–

–

V

Input Low
Voltage

VEN_L

–

–

0.95

V

PWM Input High
Threshold

VIH

2.4

–

–

V

PWM Input Low
Threshold

VIL

–

–

0.8

V

40

-

mV

PWM Hysteresis

IPWM_HYS-

8PWM Low or Tri-state to HighPWM High or Tri-state to Low
Active to Tri-state or Tri-state to
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OptiMOSTM Powerstage
TDA21570
Electrical Specification
Table 13

Protection

Parameter
OTP

HSS
FAULT

Symbol

Unit

Min.

Typ.

Max.

Note / Test Condition

Over Temp RisingThreshold

TRISE

–

140

–

°C

TMON/FAULT pulled up high Note 1

Over Temp FallingThreshold

TFALL

–

128

–

°C

TMON/FAULT released Note 1

-

560

-

mV

–

150

–

ns

IOCP_TH

-

100

-

A

Over-Current Delay TOCP_DEL

10

–

–

Cycle

High-side MOSFET
Short Threshold

VHSS_TH

TMON/FAULT Delay THSS_DEL
OCP

ValuesOver-Current
Threshold

VSW – VPGND
After VHSS_TH is detected and
TMON/FAULT is pulled highPWM High-Low Cycles to
TMON/FAULT is pulled highNotes
1. Guaranteed by design but not tested in production

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OptiMOSTM Powerstage
TDA21570
Typical operating conditions

5

Typical operating conditions

Single Phase Circuit of Figure 18, VIN = 12 V, VOUT = 1.8 V, ƒSW = 1MHz, L = 100 nH, VCC = VDRV = 5 V, TAMBIENT = 25 °C,
no heat sink, no air flow, 8-layer PCB board of 3.7”(L) x 2.6”(W), no PWM controller loss, no inductor loss, unlessspecified otherwise.

Figure 3

Powerstage Efficiency

Figure 5

VCC / VDRV current v/s Frequency

Figure 4 Power stage Loss

Figure 6 Thermal derating, Tcase <= 125℃

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OptiMOSTM Powerstage
TDA21570
Theory of Operation

6

Theory of Operation

6.1

Description

The TDA21570 contains an improved high speed MOSFET driver optimized to drive a pair of co-packaged high-side
and low-side OptiMOS MOSFETs at frequency up to 1.5 MHz. Dc-dc controllers using traditional current sense
methods like DCR sensing and Rdson sensing typically have limitations. DCR current sensing is sensitive totemperature changes of the inductor and needs temperature compensation either implemented externally using
a thermo-couple or inside the power stage. Rdson current sensing, on the other hand, is not dependent on the
inductor but there is a temperature co-efficient associated with the MOSFET rdson. Besides, it is difficult toimplement rdson current sensing for high-side MOSFET which is therefore replaced by emulated current while thelow-side current is sensed across the MOSFET. With the advanced current-mirror sensing in TDA21570, all theselimitations are eliminated while achieving superior accuracy. Current on both high-side as well as low-side
MOSFET is mirrored on a sense MOSFET which is a part of the main MOSFET device, and hence comes with an
inherent temperature compensation without the need for an additional circuitry. Real current-sensing on both
MOSFET ensures that the system is always monitoring the real output current and can immediately react to any
critical events like load step or over-current fault.
The TDA21570 reports accurate temperature with the gain of 8 mV / °C, which helps the system to actively monitor
the temperature in real time. Temperature outputs from multiple power stages can be connected together toreport the highest temperature to Infineon’s digital PWM controller.
The TDA21570 PWM input is compatible with industry standard 3.3V PWM input with tri-state.
The TDA21570 can enable Body-Braking mode by responding to PWM tri-state signals sent from the controller,
quickly disabling both MOSFETs in the power stage in order to enhance transient performance or provide a highimpedance output.
The TDA21570 supports diode emulation mode through the PWM tri-state signal. Controlled by Infineon’s digital
PWM controller, the PWM tri-state signal will force the low-side FET to be off when the inductor current is about togo negative. The light-load efficiency then can be increased by preventing conduction loss caused by negative
inductor current.
The TDA21570 also supports deep-sleep power saving mode. When in deep-sleep mode, the driver will disable
most of the function circuitry to greatly reduce power consumption.
The TDA21570 features a full-range of protection, including VCC/VDRV Under-Voltage-Lockout (UVLO), thermal
shutdown against an internal over-temperature condition, phase fault detection of a shorted high-side MOSFET,

11

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OptiMOSTM Powerstage
TDA21570
Theory of Operationand programmable cycle-by-cycle over-current protection due to an overload condition or saturated output
inductor.
The TDA21570 also features internal protection circuitry to automatically replenish the voltage across thebootstrap capacitor. It avoids the gradual depletion of capacitor energy when the power stage sits in tri-state fora long period of time.

6.2

Sleep Modes

When EN is pulled low, the power stage enters deep-sleep mode. The gate driver circuitry will be turned off
immediately and most of the logic circuitry will be shut down to reduce the bias current to less than 32 µA. The
IMON output will be shorted to IMONREF in deep sleep mode.
When EN toggles from low to high, the power stage will be active and able to accept PWM signals after a delay of
17 µs.

6.3

Current Sensing and Reporting

The TDA21570 features a very accurate current mirror architecture on both high-side as well as low-side MOSFET,
thus reporting the real time current information. The current information is reported using the IMON and IMONREF
pins. A differential connection between IMON and IMONREF pins is connected to the PWM controller to report thepowerstage current information to the controller. The reported current is in the form of current output with thegain of 5µA /A. In order to convert this into voltage, a 1KΩ, 0.1% resistor is recommended between the IMON and
IMONREF pins, close to the controller. The converted voltage signal at the controller side has an effective gain of
5mV/A i.e. for every 1 A load, the controller will read 5mV from the power stage. The current-output differential
signal from the power stage provides excellent noise immunity to the reported current information.

6.4

Advanced Fault Reporting

TDA21570 uses TMON / FAULT pin for reporting all types of faults detected. Since typical multiphase applications
connect the TMON / FAULT signal from all the phases in a particular loop into a wired OR connection, the systemcannot distinguish the faulty phase and the type of fault occurred. This is resolved by using advanced fault
reporting in TDA21570 which uses a combination of TMON / FAULT and IMON signals to identify the fault. Since
the IMON is separately connected from each phase to the controller, it provides phase-specific information in theevent of a fault. Appropriate IMON response to each fault is explained in the corresponding fault sub-sections
further. A summary of fault reporting is given in the Table 15 at the end of Section 4.

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OptiMOSTM Powerstage
TDA21570
Theory of Operation

6.5

VDRV Undervoltage Lock-out (UVLO)

TDA21570 features a VDRV under voltage lock-out fault circuitry that monitors the VDRV voltage actively. As shownin Table 15, this is a non-catastrophic fault and the TMON/FAULT pin is pulled low with a weak pull down as longas the VDRV voltage is below the UVLO threshold. If the power stage has not started up, the power stage PWM pin
is also pulled down to 0V with a weak pull down. This can be monitored by the PWM controller as a signal fromthe power stage indicating that it is not ready yet for power up. As soon as VDRV voltage is above the UVLO
threshold, the PWM pin is at tri state instead of 0V, this indicating the controller that it is OK to send the PWM
signals. At the same time, TDA21570 shorts IMON and IMONREF thus identifying itself to the controller that it is in
UVLO condition.
Once the powerstage is in normal operation, if then it encounters a VDRV UVLO condition, the power stage stops
switching, and both TMON and IMON pins are pulled down to 0V. If there are multiple phases connected in thesame loop, the TMON pin voltage, being connected to other power stage TMON pins, will continue reporting thehighest power stage temperature. But the controller can still detect IMON pin voltage to be 0V (IMON –IMONREF =-IMONREF, as seen by the controller), and thus identify this faulty phase. Since TMON pin is not pulled high, but
continues reporting the temperature, this can be distinguished from a BOOT UVLO condition as shown in Table
15.

6.6

Temperature Reporting and Over-temperature protection

An internal temperature-sense circuit monitors the temperature of the TDA21570. The sensed temperature isreported at the TMON/FAULT pin with a linear voltage slope of 8mV/°C and a 0.6V offset at 0°C, as shown inequation (1).

VTMON / FAULT (V ) = 0.6V + 0.008V / C x T j (C ) ………………………………………….……… (1)The TMON/FAULT pin also serves as a FAULT pin that is pulled to 3.3V in case of any catastrophic faults and ispulled down to 0V in case of any non-catastrophic faults. When there is no fault, it continues reporting temperature
as long as the VCC supply is connected to a voltage in the recommended operating range.
Once the temperature rises above the OTP rising threshold (140 °C), the TMON/FAULT output will be pulled highimmediately but the driver will continue responding to the PWM signal input from the controller. The controller
decides whether to stop the regulation of the VR or continue switching. The TMON/FAULT will remain high until
temperature falls below the falling threshold (128 °C). As soon as TMON is pulled high during OTP, the IMON isinternally shorted to IMONREF, thus identifying the faulty phase and occurrence of OTP to the system. The system
can then respond accordingly.

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OptiMOSTM Powerstage
TDA21570
Theory of Operation

6.7

Over Current Protection and Flag

This feature protects the power stage from self-destruction from repetitive high current events such as saturated
inductors due to poor component selection or by incorrectly optimized control loops. These high current events
could eventually lead to a shorted high-side MOSFET failure.
With cycle-by-cycle self-preservation, the current is monitored every cycle. If the over-current threshold (default
100 A) has been exceeded, the PWM high pulse will be truncated so that the inductor current is allowed to relax.
When TDA21570 detects 10 consecutive PWM cycle over-current events, the TMON/FAULT pin is flagged high toindicate the controller of the fault. The TMON/FAULT flagged “high” along with IMON information crossing theover-current threshold helps the controller identify the faulty phase that caused OC.

6.8

Bootstrap Capacitor Under-Voltage

TDA21570 features a bootstrap capacitor under voltage circuitry that detects a missing bootstrap capacitor before
powering up or a damaged bootstrap capacitor during normal operation. Once bootstrap capacitor under voltage
is determined, the TMON/FAULT pin will pulled high to report a catastrophic fault to the PWM controller. At thesame time, IMON pin is pulled to 0V or GND voltage, thus effectively indicating a negative IMONREF voltage
differential between IMON and IMONREF pins at the controller.

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OptiMOSTM Powerstage
TDA21570
Theory of Operation
Table 15 Advanced Fault Reporting and Identification

Non-Catastrophic

Fault
Severity
Level

Type of Fault

Power stage PWM
Response

Power
Powerstage TMON Recommended
stage IMON
Response
Controller
Response
Identification
Criteria

VDRV UVLO

Weak pull down to 0V= IMONREF(power-up)(PWM pin voltage can be
driven by controller, noswitching on
powerstage)VDRV UVLO

Weak pull down to 0V

Power stage stops
switching until OTP
clearsTMON < 2V,
PWM < 0.8V

(or VTMON from otherpower stages insame loop)= 0V(normal operation) (PWM pin voltage can be
driven by controller, noswitching on
powerstage)
OTP

Weak pull down to
0V

Weak pull down to
0V

TMON < 2V,
IMON < 0.4V

(or VTMON from otherpower stages insame loop)= 0V= 3.3V

TMON > 2.6V,
IMON=IMONREF,
1V < IMON < 2V

Power stage continues
responding to PWM(10 events without 3
signal from controller.
consecutive good
Truncates high side
cycles)pulse until powerstage
is in OCP.

Catastrophic

OCP

HSS (1st event)

BOOT UVLO (10events without 3
consecutive goodcycles)Power stage continues
responding to PWM
signal from controller.
Power stage continues
responding to PWM
signal from controller.

15

Continues
reportingcurrent= 3.3V

TMON > 2.6V,
IMON-IMONREF> CTRL_OCP,
IMON < 2.6V

= 3.3V= 3.3V(latched)= 0V(latched)

TMON > 2.6V,
IMON > 2.6V

= 3.3V

TMON > 2.6V,
IMON < 0.4V

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OptiMOSTM Powerstage
TDA21570
Application

7

Application

7.1

Typical Application

12V
CVIN1

VIN
TMON/FLT

PWM1
ISEN1

L1

1K

IMONREFGL

Infineon
PWM
Controller
VRDY1

PGND

VCC
VDRV

EN

VCC

1uF

L
O
A
D

TDA21570
IMON

VRTN2
3.3V

V_CPU_L1

SW

PWM

AGND

VSEN1

BOOT

Cboot1
PHASE

CVCC1

CVDRV1

+5V

12V

VRDY2

CVIN2

VINSEN1

TMON/FLT

13K

PWM2
ISEN2

IMONREF
EN

GL
V
V

1K

CVCC2

.
.
.
.
.
.

PHASE
L6
SW

TDA21570
IMON
IMONREF

EN
GL

V
V

VR_EN2

CVIN6
Cboot6PWM

1K

VR_EN1

12V

TMON/FLT

TSEN1
PWM6
ISEN6

CVDRV2+5V

VIN

SV_ALERT#SV_DAT
SV_CLKVRHOT_ICRIT#

From
System

PGND

PGND

AGND

CPU SerialBus

SM_CLK
SM_ALERT#

V V

VCCIO

SM_DAT

L2

SW

TDA21570
IMON

1K

I2C Bus

PHASE

PWM

VCC
VDRV

10nF

BOOT

1K

VCC
VDRV

RVIN1_2

AGND

VIN_1

BOOT

VIN

Cboot2

RVIN1_1

CVCC6

CVDRV6+5V

PWR_IN_ALERT#
12V
CVIN1_L2

TSEN2
PWM1_L2

PROG

TMON/FLT

BOOT

VIN

Cboot1_L2
PHASE
L_L2
SW

PWM

TDA21570
IMON

ISEN1_L2

CFILT

VSEN2

PGND

V_CPU_L2

VCC
VDRV

GL

EN

AGND

IMONREF
1K

L
O
A
D

CVCC1_L2

CVDRV1_L2

1uF

VRTN2

+5V

GND

Figure 6

6+1 - Phase Voltage Regulator - Typical Application (simplified schematic)

16

Rev 2.02021-06-01

OptiMOSTM Powerstage
TDA21570
Mechanical Drawing PQFN

8Mechanical Drawing PQFN

Figure 7

Mechanical Dimensions of Package (Top View and Side View) in mm

17

Rev 2.02021-06-01

OptiMOSTM Powerstage
TDA21570
Mechanical Drawing PQFN

Figure 8

Mechanical Dimensions of Package (Bottom View) in mm

18

Rev 2.02021-06-01

OptiMOSTM Powerstage
TDA21570
Mechanical Drawing PQFN

Figure 9

Solder Resist [Compatible with TDA2147x]19

Rev 2.02021-06-01

OptiMOSTM Powerstage
TDA21570
Mechanical Drawing PQFN

Figure 10

Recommended Solder Paste Mask [Compatible with TDA2147x]20

Rev 2.02021-06-01

OptiMOSTM Powerstage
TDA21570
Mechanical Drawing PQFN

Figure 11

Metal and Component Placement [Compatible with TDA2147x]

21

Rev 2.02021-06-01

Trademarks of Infineon Technologies AGµHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™,DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™,HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™,
OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™,
SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™
Trademarks updated November 2015
Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.

Edition <2018-04-05><yyyy-mm-dd>
Published byInfineon Technologies AG
81726 München, Germany
owners.
© 2021 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about thisdocument?
Email: erratum@infineon.com
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