OL2311
Highly integrated single-chip sub 1 GHz RF receiverRev. 1 — 8 December 2011

Product data sheet

1. General description
A highly integrated single-chip receiver solution, the OL2311 is ideally suited to telemetry
applications operating in the ISM/SRD bands. The small form factor, low power
consumption and wide supply voltage range make this device suitable for use in battery
powered, handheld devices and their counter parts.
The device utilizes a fully integrated, programmable fractional-N PLL (including loop filter)to control the Local Oscillator (LO), thus supporting multi-channel operation andfrequency hopping schemes. This feature also allows programmable frequency steps forcrystal (XTAL) drift compensation.
The device is based on a low IF direct conversion receiver architecture, with on-chip IF
filtering and programmable channel bandwidth. After filtering and amplification thequadrature signals are digitized, demodulated and processed in the digital domain.
Baseband processing of the received signal comprises a demodulator, a data-slicer andclock recovery followed by a Manchester decoder. Automated signal signature recognition
units are available to allow simple, fast and reliable data reception.
The device is controlled via a three-wire serial interface (SPI) with data input and output,
data clock and interface enable. The interface can be configured to a full SPI interface
with separate data and clock pins. Additional pins are available to access internal signals
in real-time.

2. Features and benefits













Highly integrated solution for the 315/434/868/915 MHz band
Very few external components required
Complies with ETSI EN300-220/FCC part 15 standards
Near zero-IF RX architecture
On-chip channel filtering with automatic calibration supported to provide stable cut-off
frequencies and filter roll-off
Multi-channel operation by fully integrated fractional-N PLL with on-chip loop filter
Automatic VCO sub-band selection and calibration to reduce PLL loop bandwidthvariation
Digital RSSI with a configurable threshold
Onboard Signal Signature Recognition Unit with Preamble Pattern Recognition
Configurable polling timer with 2% absolute accuracy
Level Sensitive Data slicer with self-adjusting threshold
Low power Consumption (RX 16mA), with ultra Low 0.5µA standby current andconfigurable polling timer

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver Single Lithium cell operation (2.1V). Operation up to 3.6V fully supported
 32-Pin HVQFN32 Pb-free package

3. Applications







Smart metering (wireless M-bus)
Home and building security and automation (KNX-RF)
Remote control devices
After-market Remote Keyless Entry (RKE)
Wireless medical applications
Wireless sensor network

4. Ordering information
Table 1.

Ordering information

Type number
OL2311AHN

OL2311

Product data sheet

Package
Name

Description

Version

HVQFN32

plastic thermal enhanced very thin quad flat package; no leads; 32
terminals; body 5  5  0.85 mm

SOT617-3

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© NXP B.V. 2011. All rights reserved.

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CHANNEL FILTERAUTO CALIBRATIONRECEIVE
STATE MACINERSSI LEVELCLASSIFICATION

TIMING
CLASSIFICATIONMODULATIONAMPLITUDE
CLASSIFICATIONPREAMBLE
DETECTION
UNIT

P14/IND
TEN

limiter

CHANNELFILTER

LNA

RF_IN

limiter

FM
DEMOD

RSSI

FSK

DATA
FILTERLEVELSLICERCLOCK
RECOVERYNXP Semiconductors

P11/INTPOLLING
TIMER

5. Block diagram

OL2311

Product data sheet

SIGNAL SIGNATURE RECOGNITION UNIT
BAUD-RATEGENERATOR

P12/CLOCK
P13/SDO

ASK

MANCHESTERDECODER

P10/DATABASEBAND PROCESSING
SEN
SDIO
SPI

CONTROL LOGIC, GAIN

SCLK
PTDIS
RESET
GENERATOR

NUM/FRACTIONAL-N PLL

VCO
AUTO
CALIBRATION

PFD

optionallyto P12

MAIN DIVIDERCHARGEPUMP

GND_REG_PLL

GND_REG_VCO

GND_XOGND_RING

GND_VCOGND_RF

GND_LNA

GND_PLL

GND_IF

GND_DIG

VCC_REGVCC_RF

VCC_IF

VCC_DIG

REG
VCO

VREG_VCO(VCO supply)

exposeddie pad001aan713

OL23113 of 133© NXP B.V. 2011. All rights reserved.

VCC_XO

VREG_PLL(PLL supply)

XTAL2(1) All internal domain grounds including external GND pins 1, 8, 9, 16 and 32 are connected to the exposed die pad.

Block diagram

REG
PLL

XTAL
OSCILLATOR

XTAL1

Fig 1.

VREG_DIG(digital supply)

TEST1

VCO

TEST2

0°

bufferloop filter

÷2
OR
÷4

TEST3

90 °

REG
DIG

Highly integrated single-chip sub 1 GHz RF receiverRev. 1 — 8 December 2011

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EDGE
SLICER

RSSI

50 kHz to
300 kHzOL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

6. Pinning information

25 XTAL1

26 VCC_XO

27 RSTDIS

28 TEN

29 TEST330 VREG_PLL

terminal 1
index area

31 VCC_REG

32 GND

6.1 Pinning

GND

1

24 XTAL2

VREG_VCO2

23 P13/SDO

VCC_IF3

22 P12/CLOCK

TEST1

4

TEST2

5

VCC_RF6

19 SCLK

RF_IN

718 SDIO

GND

8

17 SEN

21 P11/INT

GND 16

P14/PIND 15

20 P10/DATAVCC_DIG 14

VREG_DIG 13

n.c. 12n.c. 119GND

n.c. 10

OL2311001aan712

Transparent top viewFig 2.

Pin configuration

6.2 Pin description

OL2311

Product data sheet

Table 2.

Pin description

SymbolPin Type

Reset
state

Description

GND

1

-

-

ground; use exposed heatsink as ground reference

VREG_VCO

2

AZ

VCO regulator output voltage to decoupling capacitor

VCC_IF

3

A

A

IF section power supply

TEST1

4

A

Z

RX test I output

TEST2

5

A

Z

RX test Q output

VCC_RF

6

A

A

LNA power supply

RF_IN

7

A

A

RX RF signal input

GND

8

-

-

ground; use exposed heatsink as ground reference

GND

9

-

-

ground; use exposed heatsink as ground reference

n.c.

10

A

Z

not connected

n.c.

11

A

Z

not connected

n.c.

12

A

A

not connected

VREG_DIG

13

A

A

digital regulator output voltage to decoupling capacitor

VCC_DIG

14

A

A

digital module supply voltage

P14/PIND

15

DO

Z

digital output port with increased drive capability for PIN
diode control

GND

16

-

-

ground; use exposed heatsink as ground reference

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Highly integrated single-chip sub 1 GHz RF receiver

Table 2.

Pin description …continued

SymbolPin Type

Reset
state

Description

SEN

17

DI

DI

serial interface enable

SDIO

18

DIO

DI

serial interface input/output

SCLK

19

DIO

DI

serial interface clockP10/DATA

20

DIeO

Z

digital output port, RX data output, data output of debug
interface

P11/INT

21

DO

POR,
interrupt
outputdigital output port, interrupt output, several statusindicators, reference clock output, frame indicator of
debug interface

P12/CLOCK

22

DO

1 MHz
referenceclock

digital output port, RX data clock, clock of debug interface

P13/SDO

23

DO

Z

digital output port, status indicators, serial interface data
output

XTAL2

24

A

A

crystal reference clock frequency input

XTAL1

25

A

A

crystal connection

VCC_XO

26

A

A

crystal oscillator supply voltage

RSTDIS

27

DI

DI

reset disable signal

TEN

28

DI

DI

test enable input

TEST3

29

A

Z

PLL test output

VREG_PLL30

AZ

PLL regulator output voltage to decoupling capacitor

VCC_REG31

A

A

PLL, VCO regulators power supply

GND

32

-

-

ground; use exposed heatsink as ground reference

exposed die
pad

-

A

GND

ground connection[1]

A = analog.
DI = digital input.
DO = digital output with enable signal.
DIO = digital input without enable signal and output with enable signal.
DIeO = digital input and output both with enable signal.

7. Functional description
7.1 General architecture description
The OL2311 receiver is designed for use in both complex base-stations, when paired withpowerful microcontrollers, and low component-count remote units with low pin-countmicrocontrollers. The IC features unique configuration possibilities via external pin-level
configuration or SFR bit manipulation. Several automatic sequences are implemented toease device operation, all of which can be manually influenced or overridden bycontrol-bits.

OL2311

Product data sheet

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Highly integrated single-chip sub 1 GHz RF receiver

7.1.1 Power management
The device contains a configurable power-on reset block. The device control registers arereset as the external voltage rises to ensure that the device state is in Standby mode. Thisis implemented by ensuring that all blocks are off except the SPI and the digital regulator.
Note that the digital regulator is operating in clamp mode at this time.

7.1.2 XTAL oscillator
The main time-reference is derived from an amplitude-controlled XTAL oscillator. This
16 MHz reference is used as a reference clock for the PLL and as a timing reference forvarious analog calibration purposes.

7.1.3 Polling timer
Several base-station applications require a low-power polling timer for periodic device
wakeup. This feature is essential to enable listening in pre-programmed time-windows
when the OL2311 is used in RX mode applications. Internal configuration and trimming
registers allow the setting of a wide range of different timer intervals while achieving an
average timing accuracy of 2 %.

7.1.4 VCO calibration
On-chip calibration is available to reduce the VCO input voltage range and thus reduce
the PLL loop bandwidth variation. The variation in system parameters such as locking
time and LO phase noise can therefore be maintained within a tight window.
Calibration is performed by selecting the proper VCO sub-band according to the desiredchannel frequency. VCO sub-band selection and the PLL start-up sequence can betriggered by command and are supported by an automatic flow sequence. This flow canbe overridden if required. Note that if the incorrect sub-band is chosen the VCO calibrationis unable to tune to the desired frequency.

7.1.5 RX block
The OL2311’s RX path consists of a broadband resistive-feedback LNA, a mixer (mixing
down the input signal to an IF of 300 kHz), a channel-filter, a limiter, an RSSI stage (AMdemodulation) and a base-band signal processing block used for FM and AM data andclock recovery. The LNA, limiter and channel-filter gain settings can be configured via
control bits. The channel filter bandwidth can also be adapted.

OL2311

Product data sheet

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OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

ANALOG PARTDIGITAL PARTLNA gain switch (2 bits)
high IP3 (1 bit)bandwidth choice (3 bits)
filter gain switch (2 bits)

RSSI

I

TX/RX
SWITCH

RF
LNA
LO_Q

IF
LO

Q

channelfilterRSSII

I AND QCALIBRATIONQ

LO_I
RF VCO

limiter/ADC
RC AUTOCALIBRATION
filter calibration
I and Q phase and amplitude
calibration
001aan588

Fig 3.

RX block diagram

7.1.6 Channel filter auto-calibration
Channel bandwidth accuracy requirements vary between applications. The modulation
bandwidth changes with different bit rates. Bit rates can be 0.5 kbit/s to 112 kchip/s andthe IF channel filter bandwidth must be set accordingly in the range 50 kHz to 300 kHz.
Channel bandwidth auto-calibration is implemented to maintain constant performance.
This ensures stable cut-off frequencies and filter roll-off over process and temperature
variations. This calibration is included in the RX command.

7.1.7 I/Q calibration
I/Q calibration can be implemented to improve the channel image rejection for certain
applications. This calibration improves amplitude mismatch and phase quadrature
between I and Q signals.
Both parameters can be trimmed by injecting an external RF signal operating in the image
channel. The RSSI can then be used to determine the optimum settings to have theminimal remaining signal. This calibration is required for each frequency band.
The I/Q calibration settings are made available to -, and must be stored by, an external
microcontroller.

7.1.8 Receive command
The predefined set of RX parameters (center frequency, modulation, etc.) enables
Receive mode (receiver and LO buffers switched on) to be entered quickly after receiving
the RX command. Several methods of signal signature recognition are implemented.
These modes of semi-automatic signal processing can be pre-selected by the RXcommand.
OL2311

Product data sheet

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Highly integrated single-chip sub 1 GHz RF receiver

7.1.9 Signal signature recognition unit
Several signal recognition units are implemented to provide fast and accurate signal
detection. Signal signatures such as signal level (RSSI), modulation depth or baud-rate
and coding can be automatically detected as wakeup criteria during the wakeup searchphase.

7.1.10 Preamble detection
A configurable 1 to 32-bit pattern recognition unit can be implemented to aid power saving
and avoid unintended wakeup due to ambient noise.

7.2 General operation
The OL2311 is a state machine-based receiver to be used in conjunction with amicrocontroller. Study this datasheet carefully to help choose the appropriate OL2311
configuration for a specific application. The interface to the microcontroller must be
defined first, see Section 7.3. Next, the correct basic settings must be identified. The
operational frequency band must be chosen, all relevant registers must be programmed(exact setting of desired frequency, IF bandwidth, baseband filtering, etc). It is strongly
recommended to study every aspect of this datasheet in detail and to verify correct device
operation by measuring available debug-signals. The optimum operation and the highest
device performance is achieved by fine-tuning and verification of all device settings. Use
the automatic operating sequences after determining the optimum device configuration.
Generally, the first operation is to bring the device from standby to power-up state, whichis the precondition for any operation. This can be done manually, triggered by the external
microcontroller, or automatically by the built-in polling timer. In this device mode, the XTAL
oscillator is operational. SFR register bits (configuration data) can be changed. This modecan be left by issuing an RX command. To save power and operating time the command
can be prepared by the ‘prepare RX’ command.

7.3 Interface description
7.3.1 Port connections
The minimum connection between a host controller and the OL2311 comprises three SPI
lines: SDIO, SCLK and SEN. SPI communication and data transfer can be achieved bymultiplexing the SPI data and clock lines. The host controller’s SPI must be set in slave
mode after the RX command is sent, the SCKL then shifts the out/in data via the hostcontroller’s SPI.

MOSI

SDIO

MISO

P13/SDO

SCLK

SCLK

HOST
Port1
CONTROLLER
Port2

P10/DATA

Port3

P12/CLOCK

Port4

P11/INTSEN

OL2311001aan714

Fig 4.

OL2311

Product data sheet

Minimum port connections for RX mode

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OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

The device also supports full four-line SPI mode, the line SDIO serving as data input andP13/SDO as data output.
Alternatively, the device can be configured for separate data inputs and outputs. The lines
SDIO, SCLK and, if selected, P13/SDO can be reserved for SPI command handling. In
this case, RX data is handled by the port pin P10/DATA, the clock is carried by port
P12/CLOCK. The OL2311’s remaining ports can be used for additional status information.

MOSI

SDIO

MISO

P13/SDO

SCLK

SCLK

HOST
Port1
CONTROLLER
Port2

P10/DATA

Port3

P12/CLOCK

Port4

P11/INTSEN

OL2311001aan715

Fig 5.

Full port connections between host controller and the OL2311

7.4 Special ports
7.4.1 TEN
The test enable input (pin TEN) must always be connected to GND. This pin is only
required for a factory test and has no user-operable functionality.

7.4.2 TEST1, TEST2 and TEST3
Test pins for internal analog test-signals. In the application, these pins must be left open.

7.4.3 RSTDISThe status of pin RSTDIS defines the polling timer state enable bit after power on. Whenthe pin is LOW, the device is initialized with the polling timer enable bit set to 1.

7.5 General purpose ports
The device features five general purpose ports: P10 to P14, with selectable dedicateduser functions; see Section 7.8.3 “Reset and power mode register” on page 15. The portfunction is controlled by bits P1xCx. The width of these control bits for every port depends
on the number of selectable signals.
All general purpose ports, except P11/INT and P12/CLOCK, are in 3-state after power-on
reset. Port P11/INT is initialized as an output driving the active-LOW POR interrupt. Notethat this interrupt is non-maskable.
Port P12/CLOCK is initialized to provide a 1 MHz reference clock as the default output.

7.5.1 P10/DATA
Priority of functions:• Output signal of receiver debug interface• RX data output, if bit SEP_RX_OUT is logic 1 and the receiver is activatedOL2311

Product data sheet

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Highly integrated single-chip sub 1 GHz RF receiver

If register PORTCON2 bit SEP_RX_OUT is set and if P12C[2:0] = 010b, the port delivers
the RX clock associated with the data provided at P10/DATA. This clock is activated after
the RX DATA command’s ninth SCLK pulse. If the RX command is a PRDA, this clock is
activated after successful preamble detection. In both cases the clock continues as longas the receiver state machine is in its DATA state. This clock is recovered from the RX
signal timing and informs the controller when it can sample the data delivered at theP10/DATA line.
Note that in contrast to P10/DATA, where setting bit SEP_RX_OUT overrules the normal
port function, this is not the case for P12/CLOCK. The clock is only output if selected
when P12C[2:0] = 010b.
Bit P10INV inverts output data, including RX data.

7.5.2 P11 and P12
P11 and P12 together with P10, form the serial interface when the receiver debug mode isactivated; see Section 7.32 “RX debug interface” on page 72.

7.5.3 P14
P14 can be used to control an external circuit, such as a RX switch or an LNA.

7.6 Serial configuration interface description
7.6.1 General SPI information
The chip is configured via a three- or four-wire serial interface consisting of an 8-bit shift
register and 80  8-bit registers holding the configuration data.
Data can be exchanged with multiple 8-bit frames (auto-incrementing) or in portions of
8 bits (1 byte), which provides an advantage when using a hardware SPI-interface. Datain the shift register is loaded into the addressed register on the last edge of SCLK within
the last bit of the transferred byte.

7.6.2 SEN
A logic LOW applied to pin SEN disables the SPI interface. The internal state machine
halts and every activity on pins SDIO and SCLK is ignored.
If the device is in Power-down mode, a positive edge on pin SEN activates the device.
The crystal oscillator is always on, unless the device is in Power-down mode. The
watchdog is cleared with a HIGH level on pin SEN; see Section 7.11 “Watchdog” on page23.

7.6.3 SCLKSCLK is the clock pin for the serial interface. Every edge of SCLK shifts data into or getsdata from the SPI register-set. The second clock edge (SCLK) is used for data capturing.
SDIO direction switching between input and output is accomplished with the first clockedge of the ninth bit. An additional clock edge is necessary at the start of a RX command.
The clock polarity for an SPI command can be selected; see Section 7.6.5.
If desired, pin SCLK can carry the recovered RX clock during a RX command.

OL2311

Product data sheet

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OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

7.6.4 SDIO
SDIO is the serial interface’s bidirectional data input/output pin. Data in or data out
operation is adapted automatically during SPI communication sequences.
If desired, pin SDIO can be used to input RX data if a RX command is active.

7.6.5 General SFR access information
If SCLK is HIGH at the rising edge of SEN, the data is transferred with the rising edge of
SCLK; see Figure 6 and Figure 7. If SCLK is LOW at the rising edge of SEN, the data istransferred at the falling edge of SCLK.
For continuity, all figures and examples in this data sheet assume SEN is LOW at therising edge of SCLK, unless otherwise stated. The first edge of SCLK is referred to as therising edge and the second as the falling edge.

7.7 Write and read access to SFR
7.7.1 Write access to SFR

SEN

SCLK
SDIO
external
driver

0

0

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

0

0

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SDIO
internal
driverSDIO

polarity of SCLK
evaluated herecommand and address
evaluated here

data D7 to D0 moved toaddress A5 to A0 here
001aan591

Fig 6.

OL2311

Product data sheet

Write serial interface timing diagram

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OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

7.7.2 Read access to SFR

SEN

SCLK
SDIO
external
driver

0

1

A5

A4

A3

A2

A1

A0

SDIO
internal
driver

SDIO

0

1

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

data D7 to D0 at address
A5 to A0 is read here

Fig 7.

001aan592

Read serial interface timing diagram

7.7.3 Separation of SDI and SDO line
A four-wire SPI interface can be implemented using pin SDIO for MOSI and pin P13/SDO
for MISO. Timing and output control of pin SDO is the same as for the internal SDIO
driver.

7.7.4 Read access to SFR with separate SDO line

SEN

SCLK
SDIO
external
driver

0

1

A5

A4

A3

A2

A1

A0

0

1

A5

A4

A3

A2

A1

A0

SDIO
internal
driver

SDIO
P13/
SDIO

D7

D6

D5

data D7 to D0 at address
A5 to A0 is read here

Fig 8.

OL2311

Product data sheet

D4

D3

D2

D1

D0

001aan593

Read serial interface timing diagram (SEP_SDO = 1)

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Highly integrated single-chip sub 1 GHz RF receiver

7.7.5 Read and write access to SFR with auto-increment function
If the SPI clock (SCLK) is still applied after the first 8 data bits are transferred, theauto-increment function automatically increments the address by one for the following 8
data bits. This enables data to be written to a continuous range of bytes without having to
set the address for every single data-byte. The auto-increment function is terminated on
the falling edge of SEN.
If the address reaches the end of the address range (3Fh) an additional increment causes
the address to start at 00h again. This wrap around is accomplished in the current
address bank. The auto-increment function has no influence on the bank selection.

OL2311

Product data sheet

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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

NXP Semiconductors

OL2311

Product data sheet

7.7.6 Write access to SFR with auto-increment function

SEN

SCLK
SDIO
external
driver

0

0

A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

00

A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDIOinternal
driverSDIO

data D7 to D0
moved to address
A5 to A0 +1 here

data D7 to D0
moved to address
A5 to A0 +2 here

data D7 to D0
moved to address
A5 to A0 +3 here

data D7 to D0
moved to address
A5 to A0 +4 here
001aan594

Fig 9.

Write serial interface auto-increment timing diagram

SEN must be forced LOW after registers are written to indicate end of write. Figure 9 is an example showing 5 successive
bytes stored.

7.7.7 Read access to SFR with auto-increment function

SEN

SCLK
SDIO
external
driver

0

1

A5 A4 A3 A2 A1 A0

SDIOinternal
driverSDIO

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

0

1

A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
data D7 to D0 ataddress A5 to A0 +1
is read here

data D7 to D0 ataddress A5 to A0 +2
is read here

data D7 to D0 ataddress A5 to A0 +3
is read here

data D7 to D0 ataddress A5 to A0 +4
is read here

data D7 to D0 ataddress A5 to A0 +5
is read here(not used)
001aan595

Fig 10. Read serial interface auto-increment timing diagram (SEP_SDO = 0)

OL231114 of 133

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data D7 to D0 ataddress A5 to A0
is read here

Highly integrated single-chip sub 1 GHz RF receiverRev. 1 — 8 December 2011

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data D7 to D0
moved to address
A5 to A0 here

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiverSEN must be forced LOW after registers are read to indicate end of read. Figure 10 is an
example showing 5 successive bytes read.

7.8 Device mode description
7.8.1 Automatic start-up procedures
The device features the following automatic start-up procedures for easy device handlingand configuration:• Power-on and crystal oscillator start-up• PLL and VCO start-up including calibration• Preparation for RX mode
• VCO auto-calibration at every centre frequency change
7.8.2 General description
The automatic start-up procedures are implemented to aid the quick and easy transition
between operational states. Most procedures are controlled by changing bits in the
PWRMODE register. Certain configurations can be directly entered by the RX command.

7.8.3 Reset and power mode register
The PWRMODE register acts as the device’s ‘main power on/off/standby switch’. Setting
the RESET bit of this register brings the device into the reset condition equal to thepower-on reset state. This power-down state is also reached automatically at firstpower-on (battery insertion). If this bit is set with a write command, the effect on all
registers with a reset condition is a ‘hard-reset’. If, with the same SPI write command,
other bits are simultaneously written to the PWRMODE register, they are changed
automatically to the power-on reset state; see Section 8.2.1.10 “General power mode
register PWRMODE” on page 87.
7.8.3.1

First power-on reset
The non-maskable interrupt flag IF_POR is set when the initial power-on reset takes place(battery insertion).

7.8.3.2

Power-down
Setting bit PD brings the device into low current consumption standby mode. All analog
receiver and transmitter circuitry including the crystal oscillator are turned off and all
dynamic digital activity is stopped. Only the SPI and the polling timer, if enabled, areactive. Bit PD is also under automatic device control and is set under the following
conditions:• power-on reset or setting bit RESET (setting bit RESET overrides all others)• the watchdog timer times out
7.8.3.3

Device mode states
Three important static device internal enable signals are decoded from DEV_MODE:
PLLEN and RXEN.

• PLLEN is set whenever the DEV_MODE is not logic 00• RXEN is set only if DEV_MODE is logic 10
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power-down
conditions
RECEIVE STATE
RX command

power-onreset

polling
timer
event

preparereceiver = 1

RX command
SPI command

preparereceiver = 0

SEN = 1POWER-DOWN
STATEIDLE STATESPI command

power-down
conditions
001aan716

Fig 11. Simplified state diagram

DEV_MODE bits can be either set directly by writing the PWRMODE register or by
sending a RX command, where a RX command sets DEV_MODE to logic 10.
Setting bit RESET or setting bit PD (power-down) resets DEV_MODE to logic 00, where
only the crystal oscillator is (potentially) enabled.

7.8.4 Flow description
The following actions are performed if the device leaves power-down state and enters
active state. The internal control signals of these states are explained in more detail inlater sections.
Power-down state indicator is cleared.
7.8.4.1

Digital regulator start-up
The digital voltage regulator is turned on whenever the device leaves the power-down
state.

7.8.4.2

XTAL oscillator start-up
The crystal oscillator or the buffer for the external clock is turned on depending on thestates of CLOCKCON register bits XODIS and EXT_CLK_BUF_EN.
Bit XO_RDY is logic 1 once the crystal oscillator has settled. The device waits for several
clock periods until the clock output’s frequency and duty cycle have fully settled to within
the required specification. The end of this waiting period is indicated by bit REFCLK_RDY
changing to logic 1. This enables the master clock gate at the root of the clock distribution
tree and if applicable, the reference clock for the digital section is enabled. A polling timer
recalibration is also initiated at this point.

7.8.4.3

PLL start-up
This sequence is controlled by the internal control signal PLLEN. The voltage regulators
for the PLL and VCO (REG_VCO_ON, REG_PLL_ON) are turned on.
Wait until the voltage regulators have settled. This sequence ends, if LO_PWR_RDY = 1.

7.8.4.4

Turn on VCO
The phase frequency detector (PFD_ON), prescaler (PRESC_ON), clock for the PLL(CLK_PLL_ON) and PLL lock detection are turned on with the next clock cycle.

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Highly integrated single-chip sub 1 GHz RF receiver

7.8.4.5

Perform VCO calibration
This sequence is complete once the PLL is locked (LO_RDY is set). A manual VCO
calibration immediately stops any RX command.

7.8.4.6

Preparation for RX modeThis mechanism is invoked by issuing device mode logic 10 (prepare for RX) or by
sending a RX command.
The bandgap reference circuit for the receiver section (bit RX_GAP_ON), VCO clock
divider for the receiver section (bit PLL_LOCK), reference clock for the RX path (bit
CLK_RXA_ON), and the analog section of receiver (bit RXA_ON) are enabled.

7.8.4.7

Perform channel filter calibration
The channel filter calibration is performed every time the device enters RX mode. Thissequence ends if the channel filter calibration ends.

7.8.5 Changing device modes
Intermediate device modes may be required in an operation sequence e.g. start digital
regulator and XTAL to initialize/change SFR contents or to re-trim the polling timer. Thiscan be carried out by changing the corresponding registers. However, the directcommands may be more useful if the only operation required is the entering of RX mode.
The corresponding sequences start automatically and operation enabled after all internal
settling times are met.

7.8.6 Interrupts
TheOL2311 can generate various interrupts which can be enabled by the IEN register andread from the IFLAG register; see Section 8.2.1.11 “Interrupt enable register IEN” on page
88. The IFLAG register is always cleared after it is read. Certain pins can also be
configured to present these interrupts; see Section 7.3 “Interface description” on page 8.

7.9 Power supply and reset
Each main functional block is equipped with its own dedicated supply voltage pin.
Therefore, several supply pins are available on the package and all must be connected.
Note that all ground connections of these functional blocks are bonded to the exposed die
pad of the package (metal plate underneath the die). Some blocks are supplied via
dedicated integrated low-dropout voltage-regulators. Note that for all regulators the output
voltage is available both internally and externally on a pin for connection of a decoupling
capacitor. The following blocks have regulated supplies.
Table 3.

Blocks with regulated supplies

Block

Regulator supply pin

Pin to decouple

PLL

VCC_REG

VREG_PLLVCO

VCC_REG

VREG_VCO

digitalVCC_DIG

VREG_DIG

7.9.1 Voltage regulators operation
All regulators are operated automatically by selecting the corresponding device modes.
The device modes are set by DEV_MODE[1:0] in register PWRMODE; for details see
Section 7.8.3 “Reset and power mode register” on page 15.
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The regulators can also be independently controlled by the control bits located inside the
TEST registers. Individual operation of the voltage regulators can be necessary for debug
or measurement purposes. The following paragraphs describe each individual regulator
and its purpose.

7.9.2 Digital regulator
Before the device can be operated, the digital regulator must be switched on. In standby
state (power-down state) the digital regulator is bypassed and supplies the digital section
with a low supply voltage to guarantee data retention in the configuration registers. If thedigital regulator is switched on, the voltage reaches its stabilized value of approximately
1.8 V. The digital regulator can be activated or deactivated by bit REG_DIG_DIS in TEST1
register. Clearing the bit enables the regulator, depending on the selected device mode.
Setting the bit always disables the regulator.

7.9.3 PLL regulator
To start any PLL operation the PLL regulator must be switched on. This happens
automatically with operation of bit REG_PLL_ON in the TEST2 register.
Remark: this bit only starts the PLL regulator, all PLL functional blocks are enabledindividually by separate control-bits.

7.9.4 VCO regulator
For stability and immunity reasons the VCO is supplied via an independent voltage
regulator. This regulator can be manually controlled via bit REG_VCO_ON in the TEST2
register.
Remark: this bit only starts the VCO regulator. VCO operation is enabled individually by aseparate control-bit.

7.9.5 Device reset
A device reset occurs whenever the supply voltage is applied on the VCC pins (battery
insertion). The device utilizes two power-on detection mechanisms, one digital and one
analog. These reset circuits constantly monitor the supply voltage. Setting bit RESET in
the PWRMODE register performs the same operation by software. This is equivalent to a
power-on reset. If bit RESET is set via a command, it is cleared automatically when SPI
signal SEN goes LOW after the next write register command.

7.10 Main control and timing blocks
7.10.1 Crystal oscillator
7.10.1.1

Circuit description
The crystal oscillator is the source of the reference clock for the PLL, the digital section
and the mixed signal blocks in the receiver chain. The crystal oscillator circuit diagram isshown in Figure 12.

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Highly integrated single-chip sub 1 GHz RF receiver

xo_en

ext_clk_buf_en

signals to analog blocks

OSCILLATOR CORE
VCC_XOAMPLITUDE
CONTROL

Ibias

XO_RDY

xoready

OSCILLATORBUFFERING

driverOSCILLATORCONTROL LOGIC

DC-coupled
buffer

KICKquartz

Xtal1

Xtal2
Cx1

Xtal2

refclkrawrefclk

valid clock signal

Cx2

signals from digital control

test signals

power down

XODIS

EXT_CLK_BUF_EN

FORCE_XO_RDY

XOSTARTUPDELAY[1:0]

EXT_CLK_BUF_EN

XO_EN

EXT_CLK_BUF_EN

XO_KICK_DIS

test5 registerAC-coupled
buffer001aan597

Fig 12. Crystal oscillator circuit

The crystal oscillator consists of three main blocks: the oscillator core, the oscillator buffer
and the oscillator control logic.
The oscillator core is a low power quartz based Pierce oscillator. The oscillation frequency
is defined by the quartz and the tuning capacitors CX1 and CX2. The driver’s low
capacitance has negligible impact on the frequency value. The oscillator core is suppliedby pin VCC_XO.
When the oscillation starts and the amplitude successfully detected, the amplitude control
releases the signal XO_RDY to the oscillator control logic for validation. This signal
indicates that the amplitude control loop has entered regulation mode and not that theoscillator has settled. An extra delay is still needed to ensure the frequency accuracy; see
Table 98 “XOSTARTUPDELAY bit functions” on page 108.
After start-up, the amplitude control avoids clipping and excessive driving power in the
crystal unit.
The oscillator control logic validates the oscillator signal and provide configuration
facilities. The oscillator control logic is supplied by the digital regulator to the level
VREG_DIG.

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The oscillator buffer consists of two amplifiers connected in parallel: one low-noise
AC-coupled amplifier for crystal operation and one high-input voltage DC-coupled
amplifier for testing purposes only. The buffer plays the role of level-shifter for the signals
in PLL and digital supply domains. The buffer circuitry is supplied by the PLL and digital
regulators accordingly.
Alternatively, an external clock signal can be applied at pin XTAL2; see the external clock
buffer description in Section 7.10.2 “Oscillator control and control bits” on page 21. The
applied signal must comply with the logic levels in the digital core (0 V for LOW and 1.8 V
for HIGH). With the OL2311 properly configured, the DC-coupled amplifier replaces the
low-noise AC-coupled amplifier. This provides the possibility to skip the internal
oscillator’s start-up sequence and also allows the customer to stop the clock sequence fortest purposes.
Remark: The use of an external clock signal requires special care in the hardware
configuration. The oscillator core circuitry connected to pin XTAL2 cannot withstand levels
higher than 2.8 V. Therefore, the use of this test mode with supply voltages higher than
2.8 V requires a hardware modification for pin VCC_XO. The recommended solution is toconnect pin VCC_XO to pin VREG_DIG. In that configuration the circuit’s integrity isensured but the digital noise needs to be considered.
The crystal oscillator is always active either in oscillator mode or in external clock buffer
mode when the device is not in Power-down state.

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20 of 133xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
raw
xo_enable

TRANSITION xo_enable
CONTROLen

OSCILLATOR
CORE ANDBUFFERINGrdy

XO_RDY(1)osc out

xtal1

xtal2

pin XTAL1

pin XTAL2

CLOCK GATE
raw ext_clk_
buf_enEXT_CLK_BUF_EN

NXP Semiconductors

OL2311

Product data sheet

power-down
XODIS

ref_clken
TRANSITION ext_clk_buf_en
CONTROL
raw_ref_clk
EXT_CLK_BUF_EN
FORCE_XO_RDY
DELAY
COUNTERreset

expiredD

Q

REFCLK_RDY(1)CP
R

delay ctrl
EXT_CLK_BUF_EN

clock_present

xo_enable

power-down
XO_RDY(1)FORCE_XO_RDY

XOSTARTUPDELAY

XO_RDY(1)FORCE_XO_RDY

001aan598(1) Denote internal and official status signals.

Fig 13. Diagram for crystal oscillator with clock selection circuitry

7.10.2 Oscillator control and control bits
The oscillator control logic is described in Figure 13. Upper case signal names denote control bits in the OL2311’s registerset. Upper case signal names labelled ‘(1)’ denote (internal and ‘official’) status signals. Lower case signal names denote
internal signals.

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The enable logic is visible at the top left corner for both modes: the crystal oscillator mode and the external clock buffer
mode. The crystal oscillator is turned on when both, power-down and XODIS, are false. The transition control ensures thatno glitches can be generated when turning the oscillator on and off. The external clock buffer is turned on when the device is
not in power-down mode and both control bits, XODIS and EXT_CLK_BUF_EN are set; see Section 8.2.1.15 “Clockconnection register CLOCKCON” on page 90. As a consequence, putting the device in power-down mode disables all clock
activity, and turning the crystal oscillator on has priority over turning the external clock buffer on.

Highly integrated single-chip sub 1 GHz RF receiverRev. 1 — 8 December 2011

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CPOL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

If the crystal oscillator is turned on (XO_ENABLE becomes true) and a crystal isconnected to the oscillator, the raw clock becomes available after the oscillation reaches asignificant amplitude, which is then signalled with the internal XO_RDY status signal. This
internal status signal can be routed to pin P12/CLOCK for observation. While the crystal
oscillator is disabled, it is ensured that the clock from this clock source is held at the zerolevel.
If the external clock buffer is activated (bit EXT_CLK_BUF_EN is true) the signal
connected to pin XTAL2 is taken as the clock source. While the external clock buffer isdisabled, it is ensured that the clock from this clock source is held at the zero level.
Since only one clock source can deliver a clock at a given time they can be easily merged.
The clock is only fed into the circuit when the clock gate is enabled. The following
paragraphs explain the conditions for enabling this clock gate separately for each clock
source.
When using the crystal oscillator, the delay counter, in Figure 13, is held in reset state
during Power-down mode or if both, the internal status signal XO_RDY and the expert
control bit FORCE_XO_RDY, are false. If the oscillator signals XO_RDY after start-up (orif the FORCE_XO_RDY is set), the delay counter is released from reset, which lets it
count the raw clock pulses from the oscillator. Note that counting will not occur if theoscillation amplitude is too low or if the clock pulses are too ‘thin’ (duty cycle near 0 % ornear 100 %). Therefore it is ensured that the delay counting will not start before the raw
clock has a usable shape. After a programmable count (Table 98 on page 108) is reached,
the counter stops and signals the end of the delay.
The digital oscillator start-up delay can be controlled by bits XOSTARTUPDELAY[1:0] inregister EXPERT1.
After the delay counter’s end status reaches the REFCLK_RDY flip-flop, (shown at thelower right corner of Figure 13), it is sampled by the raw clock, now stabilized, and thisdeclares the reference clock ready. This also enables the clock gate which passes theclock on to the circuit starting with the following clock pulse. The REFCLK_RDY status
flip-flop is immediately reset when the raw clock is no longer present, which happens
when the crystal oscillator is turned off or bit XO_RDY is false due to any reason which
may have stopped the oscillation.
Note that special care is needed when non-recommended crystals are used. The use of
non-recommended crystals and resonators may have a negative impact on the start-up
behavior, on the frequency stability and on the PLL noise performance.
The oscillation amplitude is always large enough for recommended crystals so theamplitude control can properly detect that the start-up and noise generated by the
AC-coupled buffering is appropriate for PLL operation.
If the crystal is replaced by a resonator with a low Q factor, the resulting amplitude may
not be large enough for the XO_RDY status to be properly detected, although thegenerated clock may still be usable. To use the OL2311 under such conditions, the
XO_RDY status must be overridden by using the expert control bit FORCE_XO_RDY.
Note that the delay counting mechanism will not start counting before the raw clock
reaches a certain quality.

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If the external clock buffer is used, it is assumed that the clock source, which is connected
to pin XTAL2, provides a stable clock with a duty cycle close to 50 % at the time when bit
EXT_CLK_BUF_EN is set. Therefore the delay counter is not needed in this case. But
even without the delay counter, the circuit provides a well-controlled startup sequence,
which is enforced by the REFCLK_RDY flip-flop and the clock gate, so that no glitches are
generated when the clock buffer is turned on or off. Note that not using the delay counterin this normal case requires the FORCE_XO_RDY expert control bit to be in the cleared
state.
However, if bit FORCE_XO_RDY is set when using the external clock buffer, the delay
mechanism is activated. This is how the delay counter is tested in the production test but it
may also help to overcome start-up problems in the external clock source. The XO_RDY,
REFCLK_RDY signals can be observed for oscillator testing via the test buffer. The
resulting clock can be probed at pin CLOCK.

7.11 Watchdog
The device features a watchdog timer to recover from situations when activation is notdesired. The watchdog timer runs with the reference clock and it is activated, if the device
is not in Power-down mode.
The watchdog is cleared and temporarily stopped under the following circumstances:• Pin SEN is HIGH
• A terminating wakeup search is executed, i.e. either a pessimistic wakeup search isactivated (bit WUPSMODE = 0) or the timer for the wakeup search is activated during
an optimistic wakeup search (bit WUPSMODE = 1 and bits WUPSTIMEOUT not
equal to 0).

• A terminating preamble detection is executed, i.e. the timeout for the preamble mustbe activated (bit EN_PREADET_TIMEOUT = 1 and bits WUPSTIMEOUT not equal to0).
Bit EN_PREADET_TIMEOUT can be found in register SIGMON1; see Section 8.2.2.2“Signal monitoring control register SIGMON1” on page 99. Bit WUPSMODE can be foundin register SIGMON0; see Section 8.2.2.1 “Signal monitoring register SIGMON0” on page
98. Bits WUPSTIMEOUT can be found in register WUPSTO; see Section 8.2.2.4“Register WUPSTO” on page 100.
The watchdog timeout can be adjusted according to Equation 1.
215 + WUPSTIMEOUT
watchdogtimeout = -----------------------------------------------------------CLK REF(1)

where:
CLKREF = 16 MHz
watchdogtimeout = desired watchdog timeout
It is not possible to turn off the watchdog completely. The watchdog can be disabled for an
arbitrary period only if pin SEN is set HIGH.

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7.12 Polling and wakeup timer
The device features a low power oscillator, which can be used to generate wakeup
events. A polling timer overflow always generates an interrupt request. Moreover, if
selected, the device can be automatically released from the Power-down state and it canenter the RX state.
The low power oscillator has a nominal period of 40 s and a tolerance of  50 % over theentire temperature and supply voltage range and over process-dependent device spread.

CLKPT
POLLINGTIMER
OSCILLATOR

CLKPTCAL

DIGITAL CALIBRATOR

CLKWUPTICK

:16

0
:16

1

CLKWUPPOLLINGTIMER WAKEUP
TIMER
CLR

POLLTIM_EN
PTCALREG

EXTPOLLTIMRNG
POLLWUPTIME

CLKREF

REFERENCE
COUNTER AND
CALIBRATIONCONTROLxr

x≥r

wakeupinterrupt
request001aan599

Fig 14. Polling timer block diagram

The polling timer employs a digital calibration with a modulo counter. The crystal oscillator
clock CLKREF is used as a reference clock for the calibration. The calibration procedure
measures one period of the polling timer clock CLKPT and determines the appropriate
calibration value for the modulo counter. The output clock CLKPTCAL has a nominal periodof 62.5 s.
The polling timer can be turned on and off with bit POLLTIM_EN in the PWRMODE
register. The state of this bit after a master reset is determined by the level on pin
RSTDIS.
Note that due to the absence of the reference clock it is not possible to trim the polling
timer directly after a master reset. The calibration register PTCALREG is set to its nominal
value after a master reset.
After exiting Power-down mode, the polling timer calibration is triggered automatically if
the crystal oscillator starts properly. It is also possible to trigger a manual calibration by
setting bit MANUALPTCAL. Setting this bit generates a short pulse, which starts thecalibration routine. Reading bit MANUALPTCAL always yields zero. The manual
calibration is only executed if the polling timer and the crystal oscillator are running
otherwise the request is ignored. Setting bit MANUALPTCAL at the same time as
POLLTIM_EN is not supported. The calibration is only performed after the polling timer
oscillator settles.
The value in the calibration register is consistent under all circumstances. This must also
be the case if a running calibration is interrupted. Direct read or write access to register
PTCALREG is not supported.

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The polling timer wakeup time can be set with the 8-bit control register POLLWUPTIME.
The wakeup time calculates to:
T WUP =  POLLWUPTIME + 1   T WUPTICK(2)

The achievable resolution and wakeup times can be selected in two different ranges, anormal and an extended polling timer range according to the setting of bit
EXTPOLLTIMRNG in the CLOCKCON register.
It is possible to change the register POLLWUPTIME while the polling timer is running. If
the new value is greater than the polling timer counter’s current content, the running
period is not interrupted and the newly set wakeup time is seamlessly adjusted. Thismechanism allows the setting of a new wakeup time with respect to the last wakeup
event. If the newly set value in register POLLWUPTIME is smaller than the polling timer
counter’s current content, the counter is reset immediately.
The digital calibration is implemented so that the accuracy of wakeup times greater than
10 ms is better than 1 %. This allows an overall timing error of less than 2 % for the given
range.

7.12.1 Actions at polling timer wakeup
Register POLLACTION defines which action the device carries out after a polling timer
event; see Section 8.2.1.14 “Polling action register POLLACTION” on page 89.
POLL_MODE[1:0] defines the device’s operating mode after a polling timer event.
RX_GAIN[1:0] means the same as the RX flags RE and RF (gain step/switch selectionbits). The RX_CMD bit means the same as RX flag RC. It allows a choice between a
WUPS (0) and a PRDA command (1). RX_FREQ[1:0] means the same as RX flags RA
and RB (frequency selection).
The last bit in the POLLACTION register, SET_RX_FLAGS, defines whether the RX flagregister’s current content is used for the automatically initiated RX command (if 0) or
whether the RX flags RA, RB, RC, RE and RF flags are overwritten with the contents of
the RX_FREQ, RX_CMD and RX_GAIN bit settings of this register, respectively, before
the command is actually launched (if 1). If the flags are overwritten, RX flag RD is set tologic 1 to make the sub-command either a WUPS or a PRDA command; see Section
7.23.2 “Receive command” on page 42 for more information.

7.13 Baud-rate generator
The baud-rate generator generates the nominal, unsynchronized chip clock according toEquation 3.
111
16 MHz 2 + MAINSC-  -------------------------------------  --------b aud rate = ----------------PRESC
12
128
2
2

(3)

where PRESC is an exponent in the range from 0 to 7, and 211 + MAINSC is the mantissain the range 2048 to 4095. The resulting baud-rate clock can jitter by one prescaler clock
cycle CLKPSC.
The mainscaler MAINSCL lower bits can be found in register TIMING0.
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The MAINSCH and the PRESC bits can be found in register TIMING1; see Section
8.2.1.5 “Timing register TIMING1” on page 82.
The divide-by-128 divider is used as a ‘clock’ for several other blocks to measure thesub-timing within one chip interval.
This baud-rate generator is used as a time reference for the clock-recovery in RX mode.

PRESC

CLKREFPRESCALER
÷2 ÷4 ÷8

÷2presc

CLKPSCCLKMSC

MAIN SCALER
x 0.5 ... x 0.999

÷32

÷2

÷2

÷2

÷16

MAINSCto test function
selector of port
pin P12/CLOCK

111
110
101
100
011
010
001
000

to function
selector of
port pins
P11/INT and
P12/CLOCKCLKSOURCESEL

001aan717

Fig 15. Baud-rate generator

Bits CLKSOURCESEL are in register CLOCKCON; see Section 8.2.1.15 “Clockconnection register CLOCKCON” on page 90.

7.13.1 Clock recovery for RX mode
The clock-recovery for RX mode is dependent on the baud rate accuracy. If the absolutecorrect baud rate cannot be selected, choose the next available integer value. The clock
recovery is able to cope with a 1 % tolerance to be able to operate correctly with standard
XTAL cutting and temperature inaccuracies. The clock recovery is implemented as adigital phase control loop with a fixed operating frequency determined by the baud-rate
generator setting. The baud-rate generator’s mainscaler clock acts as the reference clock
for the clock-recovery PLL (128 times the actual chip clock). The clock recovery PLL is
programmable with regards to its settling speed. The settling of the clock-recovery speed
can be set to reach its final state within 3, 7, 15 or 31 chips. If the clock-recovery is locked
to the bit-stream the actual possible phase-error is proportional to the selected settling
speed setting. Highest settling speed (settling within 3 chips) produces the smallest actual
phase error due to fast regulation; slowest speed (settling within 31 chips), allows for thelargest phase error due to the slowest regulation time constant; see Table 85“CLOCK_RECOV_TC bit functions” on page 102.
Note that the decoding of NRZ signals with long constant bit-periods is directly influenced
by the accuracy of the selected baud rate. Proper coding can significantly improvesensitivity and the BER of NRZ decoding.

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7.14 Phase-locked loop
A complete on-chip PLL is available to provide an RF carrier in RX mode. The PLL is a
4th-order fractional-N PLL. The PLL analog section is described in Section 7.14.1 and the
PLL digital section is described in Section 7.14.7.

charge
pump
UP

PFD

16 MHzreference
signalloop filter

DOWN

MAIN DIVIDER

1.2 GHz to
1.856 GHz
VCO

001aan601

Fig 16. PLL block diagram

7.14.1 PLL building blocks
All PLL building blocks except bit VCO_BAND in register LOCON and the charge pumpreference current (PLL_ICP[4:0]) settings are automatically configured and operated by
selecting the corresponding device modes. The following paragraphs describe thefunction of the internal control signals. These control signals can be influenced, if desired,by operating control bits located in the EXPERTn and TESTn registers.

7.14.2 PLL and VCO regulators
To operate the whole PLL, both regulators must be switched on; see Section 7.9.3 “PLL
regulator” on page 18.

7.14.3 General PLL operation
The following blocks are enabled after switching on the regulators so that the entire PLL is
operational: VCO (VCO_ON), phase-detector (PFD_ON), prescaler (PRESC_ON) andreference clock buffer (CLK_PLL_ON).

7.14.4 Charge pumpThis block delivers the charge to the loop filter. The polarity and amount of charge areproportional to the phase error reported by the phase detector.
The peak current of this charge pump is automatically adjusted. It can be overridden by
PLL_ICP[4:0] in register EXPERT0; see Section 8.2.4.1 “Register EXPERT0” on page108. The charge pump peak current is a function of the icp control bits: icp[0] * 15 A +icp[1] * 30 A + icp[2] * 60 A + icp[3] * 120 A + icp[4] * 240 A.
This means that a value from 15 A up to 465 A can be selected. The purpose of thisprogrammability is to compensate for gain variation in other blocks, especially RF VCO,
and to keep a constant PLL loop bandwidth. The recommend value is to set PLL_ICP to 2.

7.14.5 RF VCO
The very low phase-noise on-chip RF oscillator is based on an LC oscillator.
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A capacitor bank is integrated to centre the resonant frequency of the LC tank on thedesired RF frequency. The VCO auto-calibration routine automatically trims the VCO tothe correct sub-band. Whenever a different frequency setting is used, the VCO
auto-calibration is carried out automatically. Automatic trimming can be blocked by setting
bit SKIP_VCO_CAL in the LOCON register except during the PLL start-up; see Section
8.2.1.3 “Local oscillator control register LOCON” on page 82. The trimming (sub-band
selection) can be manually modified by control bits VCO_SUBBAND[5:0] in register
VCOCON; see Section 8.2.1.2 “VCO control register VCOCON” on page 81. Frequency
sub-band setting 0 corresponds to the maximum frequency, and 3Fh to the minimum
frequency.
Note that this RF VCO is running at twice (868 MHz and 928 MHz bands) or four times(313 MHz and 434 MHz bands) the chosen frequency bands.
Setting bit VCO_BAND selects the VCO’s appropriate operating mode. This bit must be
set to logic 1 at RF frequency bands below 400 MHz, or set to logic 0 for all other bands.

7.14.6 PLL loop bandwidth setting
It is recommended that the PLL loop bandwidth is set to just above 150 kHz (3 dB closed
loop bandwidth) as this gives the best trade off between noise behavior and locking time.
The loop bandwidth can be set by PLL_ICP[4:0] to the recommended value ICP = 2.

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7.14.7 Delta-sigma modulator for fractional-N synthesis
The operating frequency is set by the content of frequency control registers FC0 to FC3, which each have a width of 20 bits.
The ‘active’ frequency control register is selected directly by the RX command; see Section 8.2.1.1 “Frequency control
registers” on page 80.

DISFRAC

LSB
=1
15

16

last A, B
flags

K(t)

MASH 1 to 1
ΣΔ
MODULATOR

S(t)
0

S2

-1 to 2
0

1
FC0
20

FC1

S1

LSBs

20
C

F(t)

1
×2

MSBs

D(t)

1228
DIVIDER

RX

U11
O

5

P(t)

5

S12

FC3

-2 to 4N(t)TX and FSK enable

S11
M(t)

S4
2

DOUBLE_SD_RESULT

modulation
signal10

FDEV_MANTFDEV_EXP

NEG

53

MANT × 2exp

DIVIDER

D

0

S11

1

RF_LO_DIV
S11

0

S5

-D

SLEW-RATECONTROL
FRMP_EXP
FRMP_MANT

3

S11

S6

1

≠0

4
001aan602

Fig 17. Computing the frequency divider control word

7.14.7.1

PLL operating frequency f0

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In Figure 17, the integer (Nt) is forwarded directly to the adder which produces the relevant control word (Pt) for the PLL.
The remaining fractional values cannot be handled by the frequency divider directly and are therefore converted into a
pseudo-random sequence of integers. This conversion is implemented by the sigma delta modulator. It produces numbers in
the range from 1 to +2, whose average over time equals the given fractional part.

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FC2

S3

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

The spectral purity of the resulting RF signal is highly dependent on the randomness ofthe sequence generated by the fractional part. If this contained short repetitive patterns
unwanted spurious signals may occur in the RF spectrum. To guarantee the produced
sequences are always of maximal length, we append a constant 1-bit to the given
fractional part, which resolves the issue. The weight of this 16th bit is 1 / 216 = 1 / 65536,
which is very low. It creates a tiny frequency offset which can be taken into account whencalculating the centre frequency control value FCx for a given centre frequency.
When the fractional part approaches 0 or 1 the low frequency noise components in thepseudo-random sequence become more dominant and can no longer be sufficiently
suppressed by the PLL’s transfer function. The visible effect is an increase of the phasenoise in the RF output near the carrier. To counteract this effect, the OL2311 uses bit
DOUBLE_SD_RESULT (Double Sigma Delta Result). If this bit is set, the fractional
contribution to the PLL control word is doubled. So when the frequency control value F(t)is increased linearly, each RF output frequency is produced twice; once with a fractional
value that is closer to zero or one (between 0 and 1 / 4 or between 3 / 4 and 1) and asecond time with a fractional value which is closer to the mid-value 1 / 2 (between 1 / 4
and 3 / 4). The latter value produces a good pseudo-random sequence.
The frequency control value’s fractional part is processed differently depending on bit
DOUBLE_SD_RESULT, and the center frequency changes accordingly. Therefore theformulae, which convert between a given Frequency Control (FC) value and the RF center
frequency, change with the state of bit DOUBLE_SD_RESULT.
In normal mode the expression is straightforward as shown in Equation 4.
2  FCx + 1
1
f RF = f ref   64 + 2  -----------------------------  -------------------------------------------------
65536  2 + 2  RF_LO_DIV(4)• The expression’s left side shows the reference frequency. The output frequency
varies proportionally with the reference.

• The parenthesized expression (64 + 2 …) is the characteristics of the PLL frequency
divider.

• The right term in the parenthesized expression accounts for the number interpretationof C and F(t) and the constant 1 LSB, which is added to guarantee maximum length
sequences from the sigma-delta modulator• The fraction at the right is the output division ratio, which is either 1 / 2 or 1 / 4,
depending on the setting of bit RF_LO_DIV.
After simplifying the expression further we get the results shown in Equation 5.
2  FCx + 1
1
f RF = f ref   32 + -----------------------------  ----------------------------------------
65536  1 + RF_LO_DIV(5)

For the inverse we solve the above expression for FCx and then we round the result to thenearest integer number as shown in Equation 6.
  f RF
FCx = round   -------   1 + RF_LO_DIV  – 32   32768 – 0.5 f  ref(6)

Using the floor function this becomes as shown in Equation 7.
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Highly integrated single-chip sub 1 GHz RF receiverFCx = f RF-   1 + RF_LO_DIV  – 32   32768
 -----f
 ref


(7)

Remark: Equation 7 is an important equation.
If bit DOUBLE_SD_RESULT is set, the integer part and the fractional part of the centre
frequency setting must be considered separately. In this case the expression for the
output frequency is shown in Equation 8.

2  FCx  14:0  + 1 
1
f RF = f ref   64 + 2   FCx  19:15  + 2  ---------------------------------------------   -------------------------------------------------65536
2+2

RF_LO_DIV(8)In the inner parenthesized expression the integer part is taken as is, where the term whichcontains the fractional part has an additional factor of 2. After cancelling certain factors of
2 we get result shown in Equation 9.

2  FCx  14:0  + 1 
1
f RF = f ref   32 + FCx  19:15  + ---------------------------------------------   ----------------------------------------32768
 1 + RF_LO_DIV(9)The inverse of this function is problematic, because the function for the output frequency
is not monotonous. But we know that each output frequency is produced exactly twice andwe know also that we want the solution where the average of the sigma-delta output S(t)is closest to 1 / 2. Let us convert Equation 9 such that the integer part of the frequency
control value has no factor and the term containing the fractional part of the frequency
control value becomes isolated on one side of the equation as shown in Equation 10.
f RF
2  FCx  14:0  + 1-------   1 + RF_LO_DIV  – 32 – FCx  19:15  = --------------------------------------------- = 2  fract
f ref
32768

(10)

Now we ask for the integer part for which the fractional part becomes a value in the range
from 0.25 to 0.75, which is equivalent to twice the fractional part, and lies between 0.5 and
1.5 as shown in Equation 11 and Equation 12.
f RF-------   1 + RF_LO_DIV  – 32 – FCx  19:15   0.5
f ref

(11)

f RF
-------   1 + RF_LO_DIV  – 32 – FCx  19:15   1.5
f ref

(12)

Now we can isolate the integer part from both inequalities so that the right sides are thesame as shown in Equation 13 and Equation 14.
f RF
FCx  19:15   -------   1 + RF_LO_DIV  – 32 – 0.5
f ref

(13)

f RF
FCx  19:15 +1  -------   1 + RF_LO_DIV  – 32 – 0.5
f ref

(14)

These inequalities can be combined into a single expression to calculate the integer
control value for the PLL as shown in Equation 15.
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Highly integrated single-chip sub 1 GHz RF receiverFCx  19:15  =f RF-------   1 + RF_LO_DIV  – 32.5
f ref

(15)

Remark: Equation 15 is an important equation.
The integer part which we have just found can be entered in Equation 9 and then we cansolve for the fractional part. We get the result for the settings after rounding it to thenearest integer number shown in Equation 16.
  f RF
FCx  14:0  = round   -------   1 + RF_LO_DIV  – 32 – FCx  19:15    16384 – 0.5 f  ref(16)

When using the floor function this becomes as shown in Equation 17.
FCx  14:0  = f RF-   1 + RF_LO_DIV  – 32 – FCx  19:15    16384
 ----- f ref(17)Remark: Equation 17 is an important equation.
From Equation 4 and Equation 9 we can also see which frequency resolution can beachieved in which mode. If bit DOUBLE_SD_RESULT is set to logic 0, we have
Equation 18.
f ref
1
2
1
f RF res  0  = f ref  2  ---------------  -------------------------------------------------- = ---------------  ----------------------------------------65536 2 + 2  RF_LO_DIV 32768 1 + RF_LO_DIV(18)

If bit DOUBLE_SD_RESULT is set to logic 1, the resolution becomes as shown inEquation 19.
f ref
1
2
1
f RF res  1  = f ref  2  ---------------  -------------------------------------------------- = ---------------  ----------------------------------------65536 2 + 2  RF_LO_DIV 16384 1 + RF_LO_DIV(19)

Taking bit DOUBLE_SD_RESULT into the formula, Equation 18 and Equation 19 can be
combined intof ref
1 + DOUBLE_SD_RESULT
f RF res = ---------------  ---------------------------------------------------------------------32768
1 + RF_LO_DIV(20)

Remark: Equation 20 is an important equation.

7.14.8 RX frequency offset
Because the OL2311 receiver implements a superheterodyne architecture with anintermediate frequency of 300 kHz, the local oscillator is automatically tuned to
300 kHz above the wanted RX centre frequency in RX mode.
This is accomplished by adding an offset value O to the centre frequency setting C; see
Figure 17 “Computing the frequency divider control word” on page 29. This offset value is
automatically adjusted so that it matches the LO frequency resolution, which changes withthe settings of bits RF_LO_DIV and DOUBLE_SD_RESULT.

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Table 54 “RX frequency offset” on page 92 shows that the resulting RX frequency offset isindependent of the RF_LO_DIV and DOUBLE_SD_RESULT settings. It is always 195 Hz
below the nominal IF of 300 kHz, which is accurate enough in all cases.

7.14.9 PLL lock detection
A lock detection circuit is implemented to support the shortest PLL power-on time. The
lock-detection circuit monitors the phase and frequency differences of the PLL and thereference clock. If the phase-difference of the two clock signals is settled within a defined
window, an internal LOCK_DETECT signal is triggered. After a specified time, set by bit
LOCK_DET_TIME[1:0] in register EXPERT1, status bit LO_RDY is set in register
DEVSTATUS. Since the lock detect circuit consumes additional power, it is only enabledduring the PLL’s start-up phase and whenever a different sub-band setting is applied. The
lock detect circuit can be manually controlled by bit LOCK_DET_ON in register LOCON;
see Section 8.2.1.3 “Local oscillator control register LOCON” on page 82.

7.14.10 VCO auto-calibration
VCO calibration is performed every time the VCO’s centre frequency is changed. The
following internal sequences are started:
1. Start VCO calibration and turn on PLL lock detection. The output of the lock detection
must be gated LOW when the calibration is running.
2. With the next clock cycle: turn on phase frequency detector (bit PFD_ON), prescaler(bit PRESC_ON), clock for PLL (bit CLK_PLL_ON) and PLL lock detection.
3. Perform VCO calibration (select best possible sub-band for desired frequency
setting).
4. Check PLL lock detection plus lock detect time.

7.15 RX operation
limiter

3

A
LNA

1
1

CHANNELFILTER

limiter

f

A
2

5

3

A
5

2
7

6

A

4

8

t

A

6

f

8

RSSI

4

t

7

t
001aan608

Fig 18. RX signal diagram

Figure 18 visualizes internal signal shapes inside the RX block. Signal 1 represents thesignal input spectrum, sketched in the frequency domain. The frequency spectrum iscentred to the desired RX frequency. Signal 2 represents the amplified spectrum of the
input signal (signal 1). Signal 2 is mixed with the LO frequency (must be set to 300 kHz
above the RX frequency) down from the RX input frequency with the I and the Q mixer tothe IF (300 kHz). Signal 3 and signal 6 represent the IF signals of the I and the Q channel
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Highly integrated single-chip sub 1 GHz RF receiver(90  phase difference) in the time domain. Signals 4 and 7 represent the I and Q signals
after the channel filter. Signals 5 and 8 are the amplified and limited I and Q signals at theoutput of the limiter. It is possible to switch some of these internal analog signals to pins
TEST1, TEST2 via bits ANA_TEST_SEL[2:0] in register TEST1. The digital IQ signals of
the limiter output, and other digital baseband signals can be accessed via the alternative
port functions of P11C and P12C with the appropriate setting of bits DIG_TEST_SEL[2:0]in register TEST0; see Table 103 “Register TEST0 - (address 35h) bit description” onpage 110 for more details.

7.15.1 General operation
The RX block consists of a fully analog front-end including an analog channel filter. The
mixer and channel filter demodulates only one sideband to the IF. The LO frequency (RFVCO frequency) must be set 300 kHz above the expected frequency of the RX signal. The
receiver mixes down the RX signal’s lower side-band. The LNA gain settings and thechannel filter are adjustable to achieve a high dynamic operating range. Field strength
detection, automatic gain selection and AM demodulation are implemented via the RSSI
information. The RSSI is derived from a limiter. Automatic gain selection is explained in
Section 7.19.
Data demodulation is performed in the digital part of the RX chain. The circuit is capable ofdemodulating ASK and FSK signals. FSK demodulation is applied directly with the analog
IF signal from the channel filter. This signal is directly fed into the digital FM demodulator
where it is processed further. ASK demodulation employs the RSSI signal which is
decoded in the digital part and then further processed. The Data slicer and clock recovery
mechanisms regenerate the bit stream for both, ASK and FSK signals.
The OL2311 is able to cope with a 1 % data rate tolerance enabling it to operate correctlywith standard XTAL cutting and temperature inaccuracies.

7.16 LNA
The feed from the single-ended antenna is converted to a differential signal at the input of
the mixer. The intrinsic voltage gain (from input pin RX to the unloaded LNA) is adjustable
to typically 4 dB, 17 dB, 23 dB or 25.5 dB. Two gain settings can be programmed to meetthe dynamic range requirements of the receiver chain. In parallel to the LNA gain, thechannel filter gain can also be adjusted. The selection of the appropriate gain setting(Hi-gain or Lo-gain) is executed automatically by the gain control loop. The individual gain
setting is programmed by the control bits located in the RXGAIN register; see
Section 7.19.

7.17 Mixer
The mixer is effectively an active I/Q mixer. It mixes down the amplified signal from the
LNA to the 300 kHz IF frequency.

7.18 Channel filter
Channel filter gain and bandwidth can be selected independently with control bits. A
well-defined filter bandwidth is achieved using auto-calibration features. The filter
bandwidth can be configured by setting bits CF_BW[2:0] in register RXBW. The different

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Highly integrated single-chip sub 1 GHz RF receiveradjustable bandwidth settings of the IF channel filter can be found in Table 57 on page 92.
The best noise performance is achieved by setting the channel filter’s bandwidth as close
as possible to the bandwidth occupied by the modulated RX signal.

7.18.1 Channel filter auto-calibration
The channel filter auto-calibration is implemented to achieve a well-centered filter roll-off
characteristic in the filter pass-band. This feature can compensate for process andtemperature dependent parameter mismatches. Filter auto-calibration is performed
automatically before every RX operation.
The calibration can be blocked by setting bit SKIP_CF_RC_CAL, and can be forced at
any time by setting bit FORCE_CF_RC_CAL both in register TEST4.
Channel filter calibration status information can be accessed by reading the CFRCCAL
register. All CFRCCAL register bits are read-only.
After starting channel filter calibration, bit CF_RC_CAL_RUNNING in register CFRCCAL
can be probed. This bit is set to logic 1 when the RC calibration algorithm is running.
Status bit CF_RC_CAL_OK is set to logic 1 when a channel-filter calibration has beencorrectly performed. This indicates that the data of CF_RC_CAL_RES[3:0] are valid.
CF_RC_CAL_RES[3:0] indicate the channel RC calibration result. These bits are applied
directly to the internal RC components of the channel filter.
Channel filter auto-calibration can be manually overridden by special register TEST4.
Control bits CF_RC_ADJUSTCAL[1:0] allow the accuracy of the channel filter
auto-calibration routine to be cross-checked.
Setting bit SKIP_CF_RC_CAL by-passes the on-chip RC-calibration. Setting bit
FORCE_CF_RC_CAL triggers an RC auto-calibration. The corresponding RC calibration
values set in CF_RC_CAL_RES[3:0] in register CFRCCAL after auto-calibration, have to
be entered in MAN_CF_RC_CALVAL[3:0] in register TEST4.
The CF_RC_ADJUSTCAL[1:0] control bits can be used to evaluate the on-chip channel
filter RC calibration block accuracy. The R part of the RC reference is trimmed bychanging the value of these two bits. By knowing the adjusted R variation we can verify
that the output of the CF_RC_CAL_RES[3:0] control bits is changing accordingly. This
enables the complete RC measurement mechanism to be validated.

7.18.2 Channel I/Q calibration
An I/Q calibration is implemented to achieve a high image frequency rejection. Thiscalibration is intended to be used once during production of the final application PCB aspart of an end-of-line test. It requires an external signal at the image frequency of thedesired RX frequency to be applied to pin RX. The I/Q calibration routine automaticallycalculates the best I/Q trimming configuration for the optimum image rejection of >50 dBc.
This result must be read and stored by the external microcontroller. The calibration value
is valid for the whole frequency band over all supply voltages and temperatures.
Perform the I/Q calibration as follows:
Apply a signal at the RX image frequency. The signal level must be chosen so that the
RSSI is still able to measure the damped image; for example, an input of 40 dBm gives
an image at 90 dBm, which is still a sufficient RSSI operating margin.
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The I/Q calibration is enabled by setting bit START_CF_IQ_CAL in register CFIQCAL.
Status bit CF_IQ_CAL_RUNNING indicates an active calibration cycle. All possible I/Q
offset combinations are run sequentially at every combination an RSSI measurement isperformed. The combination with the minimum RSSI reading is stored in
CF_IQ_CALVAL[6:0]. This information must be stored by the external microcontroller.
Initialize this register with the stored values each time. Set CF_IQ_CALVAL[6:0] to logic 0
if no IQ calibration is required.
Figure 19 shows the effect of a simulated I/Q calibration. With this calibration an image
rejection of 50 dB is achievable.

IMAGE

CHANNEL

IMAGE

21.5 dB@ 300 kHz

20
10
(dB)

−10
−30

−10
−20

−50

−30

−70

−50

22.7 dB@ 300 kHz

10

(dB)

0

−40

CHANNEL30

30−24 dB to −29 dB(I/Q calibration)@ −300 kHz

−90
−110

case 2200 kHz CF-BW

−60
−70
−500

−100

300

700

−130
−500

−25 dB to −65 dB(I/Q calibration)@ −300 kHz−100

case 1
50 kHz CF-BW
300

700
f (kHz)f (kHz)001aan609

CF-BW = Channel filter bandwidth.

Fig 19. Simulation examples for I/Q calibration with different channel filter bandwidth
settings

7.19 LNA and channel filter gain settings
Table 4 gives the intrinsic voltage gain of the LNA circuit. LNA voltage gain is
programmable and this table indicates the incremental ICC steps impacting RX front-end
current consumption.
Table 4.

OL2311

Product data sheet

Channel filter gain settings

Channel filter gain 1

Channel filter gain 0

Voltage gain (dB)

0

0

2

0

1

17

1

0

22

1

1

27

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Highly integrated single-chip sub 1 GHz RF receiver

Table 5.

RX gain control

LNA gain 1

LNA gain 0

Gain (dB)

0

0

4[1]

0.55

0

1

17

0.55

1

0

23

1.1

1

1

25.5

1.65

[1]

LNA input stage
typical current (mA)

LNA low gain stage.

Voltage gain induced by an impedance transformation network (from antenna to input pinRX) needs to be added to the values in Table 4 (such as 6 dB extra gain in case of ideal
50  to 200  impedance transformation) to compute the overall RX front-end voltage
gain.
The RX analog chain voltage gain (before limiter) can be performed by adding thesevalues to those of the channel filter given in Table 4.
Figure 20 and Figure 21 show the field-strength as a function of gain switching.

RSSI
1.3
+30 %
switch

1

−120

−100

−70

−40

Pin (dBm)
001aan610

Fig 20. 20 dB difference between Hi-gain and Lo-gain setting

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RSSI
1.65

+65 %

switch

1

−120

−100

−70

−40

−20

Pin (dBm)
001aan611

Fig 21. 40 dB difference between Hi-gain and Lo-gain setting

7.20 Limiter
The function of the limiter is to amplify or limit the input signal so that the output voltage ofthe last stage of the limiter is always constant. This applies to both very small signals at
the sensitivity limit and very large input signals. The limiter block consists of 5 gain stages
for each channel (I and Q). The limiter output signal of the last stage can be seen as arail-to-rail square signal. Two limiter chains are implemented. One chain limits the I-signal,
the other is used to limit the Q-signal. These square wave signals are used for FM
demodulation in the baseband signal processing section. Therefore the limiter can beinterpreted as a one-bit ADC directly connected to the digital section. The analog output
signal levels of the individual limiter stages are used in conjunction with the RSSI block tomeasure the RX signal strength on a logarithmic scale.

7.21 Limiter block filter cut-off frequency
The following cut-off frequencies are selected after allowing for the IF frequency of 300
kHz, and a maximum bandwidth of 300 kHz:• high-pass cut-off frequency < 100 kHz• low-pass cut-off frequency > 500 kHz

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Highly integrated single-chip sub 1 GHz RF receivergain control

RSSI
reference-60 dBm

LNA

channelfiltermixer

bufferI
Q

DIGITALFM
DEMODULATOR

limiterconversion gain =30 dB, 35 dB, 25 dB
or 5 dBsensitivity =-116 dBm

gain = 25 dB, 0 dB, 10dB
or 35 dB

IF = 300 kHz

gain = -12 + 81 = 69 dBmin
14 dB per stage (nominal)

IF = 300 kHz
pin = -71 dBm to 5 dBm

IF = 300 kHz
signal level = -12 dBVp(diff)(= 250 mVpdiff, 10 Vt)

001aan612

Fig 22. Signal level plan

7.22 RSSIThe RSSI function is implemented by adding tail currents used in the individual limiter
stages. This does not apply to levels higher than the compression point. In thiscase the gain of the LNA and channel filter is reduced to increase the linearity and the
dynamic range of the RSSI.
Remark: As the RSSI is proportional to the input voltage level having a frequency of
300 kHz, it must be filtered to ensure a stable result as the input voltage. The RSSI
frequency is 600 kHz due to the nature of the RSSI detector principle.

7.22.1 Dynamic range and operation
The RSSI’s dynamic operation is required for ASK demodulation and carrier detection. An
overall dynamic range of 130 dB is required, 120 dBm minimum sensitivity up to+10 dBm maximum signal strength. The front-end gain can be switched. An overlap of the
dynamic ranges of 20 dB is recommended to guarantee continuous ASK demodulation.
This results in a single range of 70 dB.

7.22.2 Resolution
The resolution is set to 2 dB in all conditions. A 6-bit converter is implemented to allow
for process and temperature variations.

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start clk

limiter
IRSSI

STATE
MACHINE

lo

2lo

4lo

8lo

16lo

32lo
001aan613

Fig 23. Block diagram of RSSI

7.22.2.1

RSSI low-pass filtering
The filter integration time-constant of the analog RSSI signal can be adapted to achieve amore stable digital RSSI reading (RSSI raw value) as an input to the digital filtering andinterpolation. The RC-type analog filter is used in addition to the digital filters implemented
in the baseband digital signal processing unit. This first order low-pass filter is applied
directly to the summed output of the limiter tail-currents. The limiter gain bandwidthcharacteristics are not affected.

7.22.2.2

RSSI digital filtering
The raw RSSI value is fed to a digital filtering and interpolation circuit. The output of thedigital circuit is the digitised RSSI value. The digital RSSI filter cut-off frequency can beselected by bits RSSI_FILTER_FC[3:0] in register RXBW.
The first-order low-pass filter previously mentioned cut-off frequency can be calculated
according to the Equation 21.
f ref
f c = -----------------------------------------------------5+RSSI_FILTER_FC
2  2(21)

Where fref is the reference frequency and RSSI_FILTER_FC[3:0] is a 4 bit value inregister RXBW; see Section 8.2.1.18 “Channel filter bandwidth and RSSI filter settingsregister RXBW” on page 92.
7.22.2.3

Low-level signal detection
The RSSI is used to detect the start of a communication sequence. Carriers at asensitivity level as low as 110 dBm are detected properly.

7.22.3 RSSI gain control
The automatic front-end gain selection switching threshold is controlled by the RSSI’s
output signal. This principle decreases the gain of the front-end and, if necessary, thechannel filter when the input level is significantly greater than the reference sensitivity
level. This gain switching increases the linearity of the overall chain and the robustness forlarge signal behavior and also increases the RSSI’s dynamic range.
Register HIGAINLIM contains control word HI_GAIN_LIMIT[7:0]; see Section 8.2.1.20“Register HIGAINLIM” on page 93. At power-up the front-end gain is always set to thevalue of RX_HI_GAIN[4:0] in register RXGAIN, so that the RSSI operates in its mostsensitive mode; see Section 8.2.1.17 “Receiver gain control register RXGAIN” on pageOL2311

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92. If the gain switching is enabled during wakeup-search, the gain is reduced to the
RX_LO_GAIN[3:0] setting provided the RSSI threshold set by HI_GAIN_LIMIT[7:0] is
exceeded. The RSSI reading is performed automatically during the wakeup-searchdetection.
Remark: If the input signal level is above the switching threshold and the gain-switching is
initiated, two bits are lost due to the switching event. The length of the wakeup and thepreamble must be chosen accordingly to guarantee safe operation. The minimum lengthof preamble must be 8 bits; the bit time of two bits is necessary to start the receiver and to
perform the necessary RSSI measurement. Two bits may be lost due to RSSI switching,
and a minimum of 4 bits are required to detect the preamble correctly and to synchronize
the clock recovery. This is true only when using the edge slicer, more time may berequired when using the level-sensitive slicer.
The result of the RSSI conversion can be retrieved in status register RSSILEVEL; see
Section 8.2.2.12 “Register RSSILEVEL” on page 106.
A compensation value can be set in the GAINSTEP register to achieve a continuous RSSI
reading when the front-end gain is changed; see Section 8.2.1.19 “Register GAINSTEP”
on page 93. RSSI_GAIN_STEP_ADJ[6:0] in register GAINSTEP represents the difference
between the gain values set in RX_HI_GAIN[4:0] and RX_LO_GAIN[3:0] for thecorresponding RSSI read value. The RSSI_GAIN_STEP_ADJ[6:0] value is added to the
RSSI conversion result when RX_LO_GAIN[3:0] is activated. This yields an RSSI overall
dynamic range of more than 120 dB.

7.23 Receive mode
7.23.1 Preparation for RX mode
The device initiates RX mode upon the correct setting of DEV_MODE[1:0] in register
PWRMODE. This, in turn, sets internal enable bits PLLEN and RXEN.

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ENTER RECEIVE
MODE

RX_GAP_ON = 1

CLK_RXA_ON = 1

SKIP_CF_RC_CAL
1WAIT 1 μs

CF_RC_CAL_OK

0

10

PLL_LOCKEDFALLING EDGE OF
REF CLK TURNSCALIBRATION CLK OFF

1
RX_ON = 1
VCO CLOCK DIVIDERFOR RECEIVER PARTON

001aan614

Fig 24. Preparation for RX mode

1. Turn on the bandgap reference circuit for the receiver section (bit RX_GAP_ON) andthe clock for the channel filter RC calibration (CLK_RXA_ON) with the negative edgeof the reference clock. The latter is done only if the channel filter RC calibration is not
skipped (bit SKIP_CF_RC_CAL). Then wait 1 μs until the bandgap stabilizes.
2. If the channel filter RC calibration is enabled, start it and then wait until it ends. Thenturn off the clock for the RC calibration at the next falling edge of the reference clock.
3. Wait until the PLL control-state machine reaches the state PLL_LOCKED and thenturn the receiver on (bit RX_ON), which also turns on the VCO clock divider in thereceiver section.
This sequence ends with the channel filter RC calibration, if enabled. When this ends, thereceiver is turned on.

7.23.2 Receive command
The device features a RX command. The command includes the six command bits RA,
RB, RC, RD, RE and RF:• RA, RB: RX frequency selection bits
• RC, RD: sub-command bits
• RE, RF: gain step/switch selection bits

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Table 6.

Receive command packet

D0

D1

D2

D3

D4

D5

D6

D7

1

0

RA

RB

RC

RD

RE

RF

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Table 7.

Frequency selection (bits RA, RB)

Bit RA

Bit RB

Selected frequency band

00

FC0L, FC0M, FC0H

01

FC1L, FC1M, FC1H

1

0

FC2L, FC2M, FC2H

1

1

FC3L, FC3M, FC3H

Remark: In RX mode a frequency offset of +300 kHz is automatically added to theresulting center frequency to account for the necessary LO frequency offset. Wheneverthese flags change from one RX command to another, an LO sub-band calibration (VCO
calibration) is initiated.
Table 8.

Sub-command selection bits RC, RD

Bit RC

Bit RD

Selected RX sub-command

00

CONT (continue)

0

1

WUPS (wakeup search)

10

PRDA (preamble detection followed by data
reception)

1

1

DATA (data reception without preamble
detection)

With a CONT RX command, the microcontroller can continue with any previously initiated
WUPS, DATA or PRDA command. If the frequency selection bits RA and RB are the sameas in the previous RX command and if the flags RE and RF are both logic 0, then, with thenext rising edge of SCLK, only the RX clock and the RX data lines are switched to the SPISCLK and D(I)O pins, respectively. This provides the microcontroller with the possibility tointerlace SPI Read and Write commands with RX data, provided that the SPI
communication rate is much faster than the data reception rate. If no RX operation is inprogress, no initiation occurs, and the CONT RX command only switches the SPI lines
with the next SPI clock edge, and delivers the internal RX result. The RX result can be therecovered chip clock and the transparent slicer signal or just a constant level, dependingon the current RX output configuration and depending on the RX state.
A WUPS RX command initiates a wakeup search operation. This command’s restart
characteristics enable it to interrupt any RX operation. During this command the
RXDCON0 configuration is applied as the dynamic configuration for the slicer and signal
classification and detection; the RX clock and data result can be observed with the SPI
lines producing a constant HIGH on the clock line and a constant LOW on the data line indigitised mode. This output (not the wakeup search operation itself) can be interrupted
with Read and Write commands and can be continued with a CONT RX command. The
WUPS command ends after either a WAKEUP_FOUND or a WAKEUP_NOT_FOUND
decision. In both cases the status of the detection method is sampled. When the WUPS
command ends, the WUPS_FOLLOWUP configuration dictates how the device operates;
see Table 11 “RX operating mode transitions” on page 48.
A PRDA RX command initiates a preamble detection. This command’s restart
characteristics enable it to interrupt any other RX operation. During this command the
RXDCON1 configuration is applied as the dynamic configuration for the slicer and signal
classification and detection method; the RX clock and data result can be observed with
the SPI lines producing a constant HIGH on the clock line and a constant HIGH on thedata line during preamble detection in digitised mode. This output (not the preamble
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detection operation itself) can be interrupted with Read and Write commands and can becontinued with a CONT RX command. When the correct preamble is detected, thereceiver switches automatically into data reception mode. This switch does not influence
the signal processing section of the receiver, which means that there is a seamless
transition from the preamble detection mode to the data reception mode. What changes
with the switch is the dynamic part of the configuration and the state of the signal
detection and classification means. The dynamic configuration for the signal detection andclassification method is switched to the RXDCON2 set and the detection methods arerestarted.
If the preamble detection ends with a PREAMBLE_NOT_FOUND status (after running
into a timeout), the PREA_FOLLOWUP configuration automatically decides if and how thereceiver operates; see Table 11 “RX operating mode transitions” on page 48. Regardlessof the outcome of the preamble detection phase (found or timeout) the status of thedetection method is sampled when the preamble detection ends.
If the digitised RX output format is selected for the RX clock and data, both are held
constant while the preamble detection is in progress. When the preamble is detected, theRX clock starts and the associated RX data bits are delivered with each RX clock pulse. Intransparent mode the output signals are always available.
A DATA RX command initiates the reception of frame data and skipping the preamble
detection phase. This command always uses the RXDCON2 set as the dynamic
configuration for the slicer and the signal detection and classification methods. Afterinitializing the slicer it behaves similar to the PRDA command after successful preamble
detection.
Both the PRDA command in data reception mode and the DATA command do not end
automatically on any selectable criteria. They can be terminated with another restarting
RX command, or by turning the receiver off.
Table 9.

Gain switch selection (bits RE, RF)

Bit RE

Bit RF

Selected gain step/switch configuration

00keep RX gain as is

0

1

gain switch (WUPS sub-command only), same as logic 00 forother sub-commands

10

use low gain settings

1

1

use high gain settings

The combination logic 01 (gain switch) is only applicable with the wakeup search (WUPS)
RX command. If this is chosen, the wakeup search starts with the high gain settings. If thereceived RF signal strength is always below the limit given by the HI_GAIN_LIMIT
settings, then the low gain settings are used throughout the whole wakeup search. But if
the RF amplitude exceeds this limit, the receiver automatically switches to the low gain
settings and continues with the wakeup search. Note that the wakeup search timer is not
influenced by the gain switch.

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SEN
SCLK
external
driverSCLKinternal
driverSCLK
SDIO
external
driver

1

0

RA

RB

RC

RD

RE

RF

SDIO
internal
driver

SDIO

1

0

RA

RB

RC

command and flags
TA and TB
evaluated here

RD

RE

RF

flags TC to TF
evaluated here

RX DATARX DATARX DATARX DATARX DATARX DATA

1st bit to befetched byhost controller

2nd bit to be
3rd bit to befetched byfetched byhost controller host controller
001aan615

Fig 25. Example of a RX command (SEP_SDO = 0, SEP_RX_OUT = 0)

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SEN
SCLK
external
driverSCLKinternal
driverSCLK
SDIO
external
driver

1

0

RA

RB

RC

RD

RE

RF

1

0

RA

RB

RC

RD

RE

RF

SDIO
internal
driverSDIO
P12/CLOCKinternal
driver
P10/DATA
internal
driverRX DATA

1st bit to befetched byhost controller

RX DATARX DATA

2nd bit to be
3rd bit to befetched byfetched byhost controller host controller
001aan616

Fig 26. Example of a RX command (SEP_SDO = 0, SEP_RX_OUT = 1)

From a sequence and timing point of view the RX command behaves as follows:
The DEV_MODE is set to logic 10 (RX mode) on the falling edge of the SPI clock after
receiving the 4th bit (flag bit RB) of the command. The new frequency setting is applied
according to the flag bits RA and RB. The LO is initialized at this frequency and thereceiver remains switched on even if the RX command is aborted. A 4-bit command canbe used to turn the receiver on and to switch the LO frequency. A new calibration of the
VCO sub-band, provided it is enabled, and a new PLL lock-in occurs under the following
conditions.

• upon receipt of the first RX command• the first RX command after powering up the device• the frequency settings are changed with respect to a previous RX command
The next relevant action occurs upon receiving the 8th bit (flag bit RF) of the command on
the SPI clock’s falling edge. This latches the remaining flags (RC to RF) into the RX flagregister. Please note that the receiver state machine is still not influenced after receiving
the full command byte. This gives the microcontroller the chance to wait until the analog
section of the receiver settles fully before executing the command from a sequence pointof view.

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The command is initiated on the next rising edge of the SPI clock. In the case of a WUPS,a PRDA or a DATA RX command, this brings the receiver state machine to the respective
starting point of the sub-command. If a CONT RX command is issued, the receiver statemachine is not influenced. The SPI clock’s rising edge also switches the RX clock onto the
SCLK line after a programmable delay (CLK2SCLK_DELAY[4:0]) and the RX data output
is immediately switched onto the SD(I)O line. This delay takes effect when switching the
SPI line SCLK with a RX command into the mode, where it changes its direction to output.
In this mode it delivers the RX clock, respectively. The delay starts with the next positiveedge of the reference clock following the 9th edge of SCLK (activation edge). After thedelay the output driver of SCLK is activated.
The delay value is (CLK2SCLK_DELAY + 1) / fref, where CLK2SCLK_DELAY[4:0] can be
set to a value in the range 0 to 15. So if the 9th edge of SCLK occurs just before thepositive edge of the reference clock and if CLK2SCLK_DELAY[4:0] is set to logic 0, theminimum delay is 1 reference clock cycle (62.5 ns at 16 MHz). If the 9th edge of SCLK
occurs just after the positive edge of the reference clock and if CLK2SCLK_DELAY[4:0] is
set to 15, the maximum delay is 17 reference clock cycles (1062.5 ns at 16 MHz); see
Section 8.2.1.3 “Local oscillator control register LOCON” on page 82.
If digitised RX output mode is configured, the clock output delivers a constant HIGH state
during wakeup search and during preamble detection. The output starts toggling during
data reception according to the recovered RX clock. The data output behaves in a similar
way to digitised mode, the only difference is that it is in LOW state during wakeup search
operations.
If transparent RX output is configured (see register RXCON), the clock and data output
always delivers the recovered chip clock and the deglitched slicer output, respectively.
7.23.2.1

Dynamic receiver configuration
It is not always appropriate to have a fixed setting for all aspects of the receiverconfiguration for a given protocol. This is illustrated in the following two examples:• If the transmitter sends its frames continuously without RF interruption, then it makes
sense to initialize the slicer at the start of the wakeup search but to skip the slicer
initialization at the start of the preamble detection in order to save time.

• If Manchester encoded data is to be received then the modulation amplitude detection
must be configured to allow single signal gaps which occur at data bit transitions (01or 10). But if the wakeup pattern is a constant Manchester encoded 000… or 111…
pattern, allowing no signal gaps increases discrimination precision.
To be able to manage these scenarios whilst minimizing the loading of the external
microcontroller, a so-called dynamic device configuration can be implemented. This
dynamic device configuration is controlled with the following control bytes.
Table 10.

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RXDCON registers

Register

Nomenclature

RXDCON0

wakeup search settings

RXDCON1

preamble-detection settings

RXDCON2

data reception settings

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The relevant register is automatically selected depending on whether the receiver is in
wakeup search mode, preamble detection mode or in data reception mode. The settingsof SLICERINITSEL[1:0] and INIT_ACQ_BITS[1:0] make two individual alternative
configuration sets available because only one slicer initialization is necessary for the
combined preamble detection and data reception operation.
It is possible to chain all these device modes together, employing individual device
configuration settings automatically. This is especially useful when the first command isinitiated from a polling timer event where the receiver can work in parallel to the wakeup of
the microcontroller.
Table 11.

RX operating mode transitionsFirst operation

After wakeup search

After preamble detection

Initiated bypolling timer

Success(+)/fail()

+



+



+



+



Power-down

-

[1]

-

[1]

-

[1]

-

[1]

Stop

[1][2][1][2]

[1]

[1]

-

[1][2]

-

[1]

DATA

[1][2]-[1]-[1][2]

-

[1]

-

PRDA

[1]

-

[1]

-

-

-

-

-

WUPS_FU_TSWUPS_FU_TF

WUPS_FU_CSWUPS_FU_CF-

PREA_FU_TF-

PREA_FU_CF

Bit (field) namefollow-up
configuration
namecommandpolling timer

WUPS_FOLLOWUP[1]

A possible operating mode transition.

[2]

A non-maskable interrupt is generated.

command

PREA_FOLLOWUP

Table 11 can be used to determine the configuration of the RXFOLLOWUP register; see
Section 8.2.2.9 “Register RXFOLLOWUP” on page 103. Note that an interrupt may begenerated when a wakeup search or a preamble detection ends. All other interrupts canbe enabled with the interrupt enable register.

7.24 Signal signature recognition unit
The signal signature recognition unit provides a user-friendly and easy method to support
quick and configurable RX tools. The basic challenge in RX mode is to distinguish noiseor unwanted disturbers from the wanted RX signal. This signal quality decision must be
taken within the shortest time possible to save system power consumption. The RX
process must start after successful signal quality detection. The RX process basicallyconsists of data and clock regeneration. To make the system even more robust to ambient
noise and/or disturbers, the data and clock recovery can be gated by additional methods.
If the baud rate and the coding of the RX signal is known, a wakeup pattern matching unit
can be activated. Table 12 gives a comprehensive overview of the various available units.
All units are individually selected and configured.

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Table 12.

Overview of the signal signature recognition unit

Recognition unit

Block nameSignal process

Started by

PurposeRSSI levelclassification

RSSI levelclassification

digitised RSSI-

determine correct
signal strength; upperand lower limit can be
definedModulation amplitudeclassification

modulation amplitudeclassification

demodulated
basebandstart of wakeup search determine correct
FSK/ASK modulation
amplitude

Data classification

slicerdemodulated
basebandstart of wakeup search, enable selection for
only if initial acquisition different data slicer
is enabled
behavior (fast settling,
long averaging, hold of
previously acquired
levels)chip timing verificationand code checker

slicer output

slicer output valid after decode and search forstart of wakeup search correct Manchester
coding and special
coding sequences

baud-rate checker

slicer output

check for correct baud
FIRST_SYNC or
RESYNC of the timing rate
verification after start of
wakeup searchpreamble checker

slicer output

end of wakeup search

wakeup search timer-

start of wakeup search start/end of recognition
sequence

Wakeup search timer

configurable 1-to-32 bit
preamble patternmatching

7.24.1 RSSI level classification
The RSSI circuit is used for ASK demodulation, for determining the front-end gain switch
threshold and for signal level detection. Two different application scenarios can besupported by a level detection circuit.

• Check for a carrier signal strength within a given threshold, i.e. above a minimum
level or below a maximum level or between minimum and maximum• Check for a carrier signal strength outside a given threshold, i.e. below a minimum
level or above a maximum level
The first scenario can be used to determine the presence of a carrier as a precondition forother demodulation or classification measures. The second scenario is useful to quickly
check for occupied channels in a multi-channel system.
The RSSI classification unit is a window comparator with programmable threshold values.

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7.24.1.1

Functional block diagram

UPPERRSSITH

r

8

x

below orequal upper thresholdx<rx
cooked RSSI value

8ywithin rangex<yx
LOWERRSSITHr

8

above orequal lower thresholdx>r001aan617

Fig 27. RSSI wakeup recognition

Input signals:• 8-bit digitised RSSI value• 8-bit upper limit of the desired RSSI range• 8-bit lower limit of the desired RSSI range
Output signals:
Two individual signals, which indicate whether the input signal is above or below therespective threshold; these two indicators are provided as (latched) status information.
The logic combination of the two output signals indicates that the RSSI signal is within therange defined by the two thresholds. The definition of what is intended by the phrase‘within the range’ depends on whether the value of the upper limit is greater or less thanthe lower limit. This is illustrated in Figure 28.

UPPERRSSITH

outsideLOWERRSSITH

withinLOWERRSSITH

outsidewithinoutsideUPPERRSSITH

within001aan618

Fig 28. RSSI threshold

If a single minimum threshold is desired, the UPPERRSSITH[7:0] value must be set to
255 (0xFF). To achieve a single maximum threshold, the LOWERRSSITH[7:0] registermust be set to logic 0.

7.24.2 Modulation amplitude classification
This block consists of two sub-blocks, the first of which is the amplitude measurement,
which is followed by a threshold comparison and the decision logic.
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7.24.2.1

Method to determine the modulation amplitude
The modulation amplitude classification block measures the magnitude of the signaltransitions within one chip interval. The baseband signal is delayed by one chip interval
using an oversampling ratio of 4 samples per chip interval. A raw amplitude measurement
is computed for each sample by subtracting the delayed sample and taking the absolutevalue of the difference. Then for each chip interval the maximum of the four adjacent raw
values is determined.

UPPER_MODAMP_THR
basebandsignal

ABS

MAX

>

LATCH

FAIL

−
reset

Z−1 Z−1 Z−1 Z−1

Z−1>

SEQUENCER(4 TIMES OVERSAMPLINGPER CHIP INTERVAL)

LOWER_MODAMP_THR

001aan619

Fig 29. Block diagram of the modulation amplitude classification

If there is a transition in the chip interval, the output of this measurement is valid. If there isno transition in the interval the output from the measurement can be much lower than thenominal amplitude. This appears as a gap in the sequence of measurements. If weconsider a Manchester coded signal having at least one transition within each two-chip
interval, we have to accept (and ignore) at most one gap between valid measurements.
The modulation amplitude is compared against the threshold defined with register
LMODAMPTH and if it is lower than the threshold for a duration greater than
NUM_MODAMP_GAPS_x[1:0]  (chip duration), then a ‘modulation amplitude too low’error is reported in bit 0 of register SIGMONERROR.

001aan620

5500
modulation
(Hz)
4500

3500

2500

1500

500
0.03

0.032

0.034

0.036

0.038

0.04
t (s)

4  oversampling.

Fig 30. Modulation amplitude measurement of a Manchester coded signal

Figure 30 shows an example of the amplitude measurement when measuring a noise-free
Manchester encoded baseband signal. The top waveform is the baseband signal. Notethat this signal can have an arbitrary offset. The lower waveform shows the output of theamplitude measurement. The red dots show the actual values (oversampling rate of 4
versus the chip-clock) used for computation.
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Due to the ripple in the output signal (lower trace) and the discrete sampling time, thesampled signal can be lower than the theoretical maximum value. Worst case input
signals for this algorithm produce a maximum amplitude error of 8 % of the maximum
theoretical value.

001aan621

2500
modulation
(Hz)
2400

2300

2200

2100

2000
0.03430.03470.03510.0355t (s)4  oversampling.

Fig 31. Modulation amplitude measurement (zoomed)

In this example the upper horizontal dashed line corresponds to the actual amplitude Aact.
The lower horizontal dashed line corresponds to Aact 8 % = 0.92 Aact. Consider thiswhen calculating the lower and upper limit for the modulation amplitude detection. The
higher limit can be set close to the expected value, the lower limit must be at least 8 %lower than the expected value.
The amplitude measurement for each chip interval is compared with two programmablethresholds. If the measured amplitude is above the upper threshold, the result is
immediately classed as a FAIL. If the measured amplitude is below the lower threshold,this can be either a low amplitude condition or a gap. The outcome is a FAIL if two
successive amplitude measurements deliver a value which is below the lower threshold;there must be no more than one gap between valid measurements.
The lower and upper thresholds can be independently selected with the 8 bit registers
LOWER_MODAMP_TH and UPPER_MODAMP_TH, respectively. The actual thresholdvalue is defined by the associated register settings according to Equation 22.
xxxThresholdValue = min  2

xxx_MODAMP_TH[7:4] xxx_MODAMP_TH[3:0] 7FFFh (22)

Where xxx stands for LOWER_ or UPPER_.
Example: FSK signal Manchester coded, 2 kbit/s respectively 4 kchip/s, modulation
deviation: 1.5 kHz.
The FSK signal must be mapped to the output range of the FSK demodulator. The output
signal range is 0 to 32256. This range equates to a frequency deviation of 200 kHz
respectively 600 kHz, depending on bit LARGE_FM_DEM_RANGE in register EXPERT2.
The expected peak-to-peak modulation amplitude is 1.5 / 200  32256 = 242.
The UPPER_MODAMP_TH is set to at least the expected value: 16  24 = 256.

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UPPER_MODAMP_TH_MANT[3:0] = 15d = 1111b
UPPER_MODAMP_TH_EXP[7:4] = 4d = 0100b.
The LOWER_MODAMP_TH should be set to 92 % of the maximum expected value:242  0.92 = 222.
The closest programmable value not exceeding this is 13  24 = 208. Therefore, the
LOWER_MODAMP_TH should be programmed as follows:
LOWER _MODAMP_TH_MANT[3:0] = 13d = 1101b
LOWER _MODAMP_TH_EXP[7:4] = 4d = 0100b
The lower and the upper thresholds can be disabled. The lower threshold is disabled by
setting LOWER_MODAMP_TH to 0d and the higher threshold is disabled by any value:
UPPER_MODAMP_TH  215.

7.25 Data classification
The data slicer is used for the timing, code and baud rate classification modules.

7.25.1 Data slicer
The device features a versatile collection of different data slicers with different initialisation
and adaptation mechanisms, including:• an edge-sensitive slicer with minimum latency: used in applications where fast dataslicer settling times are crucial• a level-sensitive slicer: more robust to noise, appropriate when a longer settling timeis acceptable
7.25.1.1

Number of corrupted bits in RX mode
The number of corrupted bits during the start of RX mode depends on the selected slicer
method and the associated settings. The edge slicer provides the fastest possible settling
time, only 1 chip period (1 / 2 bit) is lost. The loss of level-sensitive slicer bits depends on
its initialization setting. If the initialization sequence is selected, 4 chips (2 bits) or 16 chips(8 bits) can be lost. It is possible to recover all bits, provided the level sensitive slicer is
pre-initialized to the correct threshold.

7.25.1.2

Slicer description
The level-sensitive slicer is configured by the RXDCONx registers; see Section 8.2.1.26“Register RXDCON0” on page 96. The level slicer threshold can also be initialized with adesired value by programming registers SLICERINITL and SLICERINITH. This could be
used to improve level slicer settling time. The actual level slicer threshold currently used
can be read from these registers at any time.

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LEVEL SLICER

READ/WRITEACCESS FROMSPISLICERINITTHRSLICERTHR

INITIALACQUISITION

LOW-PASSFILTERr
x x³r

basebandsignalsliceroutputEDGE SENSITIVESLICER

001aan622

Fig 32. Slicer block diagram

The edge-sensitive slicer will not make use of these two registers. The
EDGE_MODAMP_TH contains the expected peak modulation amplitude with which theedge slicer is initialized. The expected peak modulation value is provided by the
EDGE_MODAMP_TH[7:0] register; see Section 8.2.1.25 “Register EMODAMPTH” onpage 95. The EDGE_MODAMP_TH is calculated by:ThresholdValue = 2

EDGE_MODAMP_TH[7:4]

 EDGE_MODAMP_TH[3:0](23)

7.25.2 Edge slicer
The edge slicer operates as a differentiating slicer in combination with a fixed-level slicer.
The time-constant is automatically adjusted in accordance with the selected chip rate of
the baud-rate generator unit. This slicer is also capable of demodulating NRZ code withlong constant bit sequences provided the expected peak modulation amplitude initializes
correctly. The basic principle of the edge slicer is explained in Figure 33.

max

max

max

a

a

a

thresholdthresholdbelow
thresholdat thresholdabove
thresholdthreshold

a

a

a

min

min

min
001aan623

Fig 33. Working principle of the edge slicer

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The slicer operating mode slicer is selected by the slicer selection bits
SLICERSEL_W[1:0]; see Table 66 “SLICERSEL_W bit functions” on page 96.
The edge slicer takes five adjacent samples at intervals equivalent to ¼ of the chip width.
The four outermost samples (red and blue dots in Figure 33) are used to make up a
dynamic threshold and the middle sample (green dot) is compared against this. The
threshold value is the average of the maximum and minimum of the four outermost points.
The exact description of the algorithm for the edge slicer is:
1. Consider 5 consecutive samples taken at a distance a ¼ of the chip period width.
2. Compute the minimum and the maximum of all samples except the middle one.
3. Take the average of the maximum and the minimum as the slicer threshold.
4. Compute the maximum and the minimum of the two neighbors of the middle sample.
5. Take the difference of the maximum and the minimum as the amplitude measurement.
6. Compare the measured amplitude against the peak value of the signal which isprovided by register EMODAMPTH; see Section 8.2.1.25 “Register EMODAMPTH”
on page 95.
7. If the amplitude is above the threshold, set the slicer output according to thecomparison of the signal (middle sample) with respect to the slicer threshold.
8. If the amplitude is below the threshold, keep the current state of the slicer output.
The following list summarizes the properties of the edge slicer algorithm:• Because the input signal needs to be fed through a delay line and because of thenecessary linear interpolation the slicer has a delay of about one chip interval.

• Since the slicer acts only on valid signal edges and since it ignores what is between
these edges, it can handle arbitrary coded signals, including NRZ.

• The slicer output is valid after the first signal edge and the slicer delay.
• Due to its differentiating function, the edge slicer is more susceptible to noise thanslicer threshold generation methods which average over the signal (level-sensitive
slicer).
The slicer needs to know the expected amplitude of the baseband signal for amplitudeclassification, this can be easily provided for FSK signals.
The following configuration settings must be initialized when the edge slicer is used.
Expected peak modulation value: must be provided by the EDGE_MODAMP_TH[7:0]
register; see Section 8.2.1.25 “Register EMODAMPTH” on page 95. The
EDGE_MODAMP_TH[7:0] value must be calculated using the following procedure:
ThresholdValue = 2

EDGE_MODAMP_TH[7:4]

 EDGE_MODAMP_TH[3:0](24)

Example: FSK signal Manchester coded, 2 kbit/s respectively, 4 kchip/s, modulation
deviation: 1.5 kHz.

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The FSK signal must be mapped to the output range of the FSK demodulator. The output
signal range is from 0 to 32256. This range equates to a frequency deviation of 200 kHz to
600 kHz depending on bit LARGE_FM_DEM_RANGE in register EXPERT2. The
expected peak modulation amplitude is 1.5 / 200  32256 = 242. The
EDGE_MODAMP_TH is set as close as possible to the expected value: 15  24 = 240.
EDGE_MODAMP_TH_MANT[3:0] = 15d = 1111b
EDGE_MODAMP_TH[7:4] = 4d = 0100b
7.25.2.1

Edge slicer signal monitor setting
The lower and upper thresholds for the peak-to-peak amplitude of the baseband signal(FSK modulation) are simply the TX peak-to-peak frequency deviation plus and minus a
guard band tolerance (factor of 3 / 4 or 5 / 4) mapped to the output range of the FSK
demodulator. They can be calculated with the following equations:Register LMODAMPTH = 3000  (32256 / 200000)  (3 / 4) = 362.
Register UMODAMPTH = 3000  (32256 / 200000)  (5 / 4) = 605.
Register UMODAMPTH must be set to a value higher than 605 (10  26 = 640).
UMODAMPTH[3:0] = 10d = 1010b
UMODAMPTH[7:4] = 6d = 0110b
Register LMODAMPTH must be set to a value lower than 362 (11  25 = 352).
LMODAMPTH[3:0] = 11d = 1011b
LMODAMPTH[7:4] = 5d = 0101b
Remark: the amplitude threshold must be set to the expected peak amplitude value.

7.25.3 Level-sensitive slicer
The level-sensitive slicer offers various features which can be configured to improve noise
immunity or to reduce latency; see Section 8.2.1.26 “Register RXDCON0” on page 96.
These include:• User-definable initialisation value• Initial acquisition of the threshold by averaging the baseband signal over 2, 4, and 8
bits• Continuously variable threshold configured according to output from 1st-order
low-pass filter
The slicer operating mode is selected with slicer selection bits SLICERSEL_x[1:0]according to Table 66 “SLICERSEL_W bit functions” on page 96.
The time-constant for the low-pass filter is derived from the baud-rate generator settings.
It is assumed that a Manchester encoded single bit comprises two chips.

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The various level slicer initialisation mechanisms are controlled by bits
SLICERINITSEL_x[1:0]. If the slicer is initialized, its output becomes invalid for at least
one cycle, which restarts the deglitcher and the edge detector. The output remains valid
even when the slicer threshold is updated after the initial acquisition refines its thresholdvalue (after 4 and 8 bits).
7.25.3.1

Level-sensitive slicer initial acquisition
The initial acquisition generates a first estimate of the threshold by averaging the RX
baseband signal over a fixed time interval of two bits. If a constant 0 or 1 sequence or analternating 01 sequence is received, the expected value of the error is exactly zero. If aManchester encoded signal is being received, the maximum error can be ¼ of the wholeswing, which is sufficient for an initial estimation. After having calculated this average, theslicer output changes from UNKNOWN to VALID.
The following samples from the baseband signal are used to improve the initially foundthreshold. After processing an additional 2-bit interval (4 bits in total), a new average iscomputed having less uncertainty as the initial value (by a factor 2). This is used as the
new slicer threshold. Once an additional 4-bit interval is accumulated, having processed 8
bits in total, the final, more accurate estimate for the threshold can be calculated. This
threshold value can be read via register SLICERINITH. Register SLICERINITL is
automatically updated every time a new initial slicer threshold is available.
It is possible that the 2-bit interval period used for the initial estimate lies in a time period
where there is either no RF, RF with only CW (no modulation) or the frame start containing
Manchester code violations. In this case the slicer output may have no edges for a longtime interval, which may indicate an incorrectly chosen threshold value. If the timing
verification block detects a timeout (time interval between edges > 3.5 chip width) it makes
sense to reset the threshold estimation in order to get a better initial threshold value. The
slicer’s output is again UNKNOWN after the reset for the next 2-bit interval. The slicer’s
output becomes VALID again and the classification of its output edges may provide
successful data reception. If the RX signal is not usable the slicer may be reset several
times until the selected RX operation is aborted.
If the initial acquisition is not used during the wakeup search, it might be useful to disable
the auto-reset feature mentioned above. This can be accomplished by a dedicated setting
in register SLICERINITSEL.
The initial acquisition operation always inhibits the use of the slicer output (status
UNKNOWN) during the calculation of the first two bits, regardless of whether the initialacquisition was triggered for the first time (by an RX event) or if it was re-triggered from a
bit timeout.
The initial acquisition updates the slicer initialisation register and the slicer register after
the calculation of 2, 4, and 8 bits (selected by INIT_ACQ_BITS) provided the RX event
was not interrupted by the higher-level state machine. In these circumstances the initialacquisition is stopped to avoid unwanted data corrupting the calculation of the threshold.
Access register SLICERINITH only via the SPI if the initial acquisition is not active. Failure
to comply with this may result in the reading of unstable values and the content of register
SLICERINITH may become undefined.

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7.25.4 Deglitcher and edge detector
The purpose of the deglitcher is to suppress multiple signal transitions when a noisy
baseband signal crosses the slicer threshold. The deglitcher operates as follows: if asignal transition is detected, the deglitcher passes the transition to its output and then it
locks this output for a certain time period, which can be selected by
DEGLITCHER_WINDOW_LEN[1:0] according to Table 61“DEGLITCHER_WINDOW_LEN bit functions” on page 94.
The lock timer is held in its reset state while the slicer output is invalid. This means thatthe deglitcher can only enter its locking state when the edge detector produces an output
event.
The edge detector locates the edges in the deglitched slicer output and supplies theblocks which measure and classify time intervals between edges. The edge detector
produces edges only after the slicer output is valid. If the slicer produces a transition at thesame time as its output becomes valid, it is suppressed by the edge detector. The
deglitcher lock window is also suppressed by the edge detector and only becomes active
when the edge detector produces an output event.

7.26 Timing classification block
The purpose of this module is to classify the time intervals between the transitions fromthe slicer and to determine whether the RX signal is a Manchester coded signal. Certain
additional conditions can be selected.
The property of a Manchester coded signal, used as the main classification criteria in thisblock, is that there are only two different time intervals, namely one chip width or two chip
widths between two transitions.

7.26.1 Chip timing verification
In the proposed implementation, the signal is oversampled with an OSR of 128, giving atime measurement resolution that is better than 1 %. The time interval between each pairof transitions is measured. If the measured time interval is < 1.5  chip width, then it isassumed that the associated nominal width is 1  chip width and so 1  chip width issubtracted from the measurement to calculate the timing error. If the measured timeinterval is > 1.5  chip width then it is assumed that the associated nominal width is2  chip width and so 2  chip width is subtracted from the measurement to calculate thetiming error. This measurement includes a timeout such that widths greater than
3.5  chip width are always rejected. The absolute value of the timing error is calculated
and compared to a limit which can be chosen from the 16, 24, 32, or 48 counts of theoversampling clock according to the setting of bits SGLBITTMGERRTH[1:0]; see Section
8.2.2.7 “Register TIMINGCHK” on page 101. The time interval is accepted if its absolutevalue is below the limit. This corresponds to timing errors which are less than 12.5 %,18.75 %, 25 % and 37.5 % of a nominal chip width, respectively. The single-chip timing
verification block is a powerful means to classify signals with a given baud rate. The
edges of these signals are assumed to emerge at a virtual chip grid. Therefore, the same
absolute error limit is applied for short and long intervals to allow a specified range of edge
jitter.
The chip timeout value can be changed with an expert bit. The standard value is
3.5  TCHIP. This value can be reduced to 2.5  TCHIP if bit REDUCED_CHIP_TIMEOUT isset; see Section 8.2.4.3 “Register EXPERT2” on page 109.
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TIME OFPREVIOUS
EDGE

chip rate counterchip width = 128 counts

REDUCED_
CHIP_TIMEOUT−≥ = 3201≥ = 448

0interval toolarge, chiptimeout

LATCH≥ = 192−

longinterval
0

128

1

256
single interval
timing error value(will be averaged
in the baud-rate
checker)

ABS()

0
1

≥=

2
3

single chip timing
error detected

8
16
24
32

SGLBITTMGERRTH
001aan624

Fig 34. Block schematic of chip timing verification block

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reset
IDLE

off

edge

FIRST_SYNC

off

not valid
unknown

offtimeout

timeout

timeout

timeout

TIMEOUTedge

offtimeoutedge

timeout

valid
error

RESYNC

off
off
edge
edge

CHECK

valid
ok/error

001aan625

Fig 35. State diagram of chip timing verification block

After the first synchronisation (reception of two edges) the chip timing verification block
becomes VALID and the chip timing CHECK begins. The last chip timing step is directly
used as the ERROR criteria when in this state.
If a timeout occurs, the state machine signals an ERROR. Upon reception of twoconsecutive edges, the timing verification block can be re-synchronised, the statemachine then again entering the CHECK state.
Remark: a single chip timing error will not change the state of the state machine unless it
is a timeout.

7.26.2 Code checker
Typical wakeup patterns consist either of a constant 0 sequence, a constant 1 sequence,or an alternating 01 sequence. In these cases the pattern only contains a single timeinterval length. It is therefore possible to apply further restrictions on the accepted timeintervals.
Correct chip timing is a pre-requisite for the code checker. A single bit timing error always
causes a code checker error. Changing the setting of CODINGRESTR_W[1:0], while thecode checker is running is not recommended; see Section 8.2.1.28 “Register RXDCON2”
on page 97. This can cause a false error indication. A false error indication may arise at alater stage if Manchester code checking is newly selected. The Manchester
MANCHESTER START state is not necessarily executed immediately.

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reset

IDLE

off

off

off

on

egde

START

FIRST_SYNC

timeout

not valid
unknown

off

off
timeout

timeout

off
CodeOK or
ManchesterLong

CodeViolation
TIMEOUT
ManchesterShortedge

timeout
timeout

CodeOK or
ManchesterLong

off

ManchesterShort

CodeViolation
ManchesterShort

MANCHESTERSTARTCodeOK or
ManchesterLong

off

CodeViolation

RESYNC
off
off

valid
error

CodeViolation orManchesterLong
timeout

ManchesterLong

valid
ok

ManchesterShort
offtimeout
RUN

CodeOK or
ManchesterLong

MANCHESTERSHORTCodeViolation

ManchesterShorttimeout

offtimeout

001aan626

CodeViolation = Edge  [SingleBitTimingError or (CODINGRESTR = 1)  LongInterval or(CODINGRESTR = 2)  ShortInterval].
CodeOK = Edge  [(CODINGRESTR = 0) or (CODINGRESTR = 1)  ShortInterval or (CODINGRESTR = 2)  LongInterval].
ManchesterLong = Edge  (CODINGRESTR = 3)  LongInterval.
ManchesterShort = Edge  (CODINGRESTR = 3)  ShortInterval.

Fig 36. Code checker state diagram

The timeout is derived from the chip timing verification block, i.e. a timeout is generated if
a bit exceeds a length of 3.5  chip width.

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The OK/ERROR information is directly derived from the state machine. The RESYNC
state is initiated after a code violation is recognized by any of the other states, unlike thechip timing verification block which only enters the RESYNC state after the occurrence ofa timeout.
If CODINGRESTR_W[1:0] is set, it is only possible to differentiate between a run of zeros
or a run of ones (short time intervals) if the first long time interval is received, thus
determining if the data represents a 01 or a 10 transition. Once the long time interval isreceived, the remaining sequence can be checked against Manchester coding rules. Aftera long interval is detected, short intervals must always be in pairs; the following sequenceis illegal: SSSSSLLSSLSSSSLSSSL.

7.26.3 Baud-rate checker
An averaging facility is implemented to increase the accuracy of the single time interval
check and baud-rate detection by a factor of 4. This averaging is performed on blocks of 8bits, where the first block starts whenever the chip timing block reaches either
FIRST_SYNC state or RESYNC state. Correct timing of a single bit is a prerequisite forthe baud-rate checker, therefore averaging is restarted even if a single bit timing error
occurs.
The baud-rate checker has no information about the coding of the signal. Thus it ispossible that a sequence of 8 bits comprises 17 instead of 16 chips, e.g. if 15 shortintervals followed by one long interval are to be examined. If a sequence of several 8-bit
blocks is assessed, the accumulated timing uncertainty is never more than 1 chip.
Averaging over 16 chips requires dividing the sum of the individual timing errors by 16,
thus causing an unnecessary loss of precision. Therefore the division is omitted and only
the timing errors are summed during an 8-bit block. The product of the 8 bits is comparedagainst a limit which can be selected by SUMBITTMGERRTH[2:0] according to Table 82“SUMBITTMGERRTH bit functions” on page 101.
This block can be easily extended to allow the number of observed bits to be adjusted toeither 8, 16, 24 or 32 bits according to the baud rate observation length setting
BROBSLENGTH[1:0]; see Table 81 “BROBSLENGTH bit functions” on page 101.
The output of the baud-rate checker is only VALID after the absolute value of the sum of
the received 8 bits is checked against the limit. The output immediately signals an
ERROR if the limit is violated. If the sum value is within the limit, the measurement
proceeds until either a limit violation is detected or the requested number of bits areobserved. In the latter case the output becomes VALID and signals OK.
The baud-rate checker continues checking on an 8-bit basis after the requested numberof bits was checked successfully. The ERROR signal is updated at the end of every 8-bit
sequence. It stays VALID and OK if the baud rate is within the limit. If the baud rate is
outside the limit, an ERROR is signalled and the baud-rate checker restarts. The ERROR
signal is retained as long as no 8-bit sequence is within the limit. If the selected
observation length is greater than 8 bits, the baud-rate checker enters the NOT VALID
state as soon as the first correct 8-bit sequence is received and finally signals VALID and
OK after successful reception of the selected observation length. This mechanism
assures that the baud-rate checker can only signal VALID and OK once the selected
number of consecutive bits are received with the correct baud rate.

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Highly integrated single-chip sub 1 GHz RF receiverOn the occurrence of a timeout or a single bit timing error, the baud-rate checker resets
immediately, NOT VALID is signalled instantaneously and the baud-rate checker restarts.

7.26.4 Timeout timer for the wakeup search
The control logic includes a timeout timer for the wakeup search operation. When used,
this timer generates a negative wakeup detection output provided a positive wakeup
detection is not generated prior to the timer expiration. When this timer is disabled, theoutput of the wakeup search operation is instantly negative upon a failure signal from anyof the detection operations.

CLKBitPRESCALER:2:4:16 :64
WUPSTIMEOUTWUPSTIMEOUTPRESC

00

01

10

11
WAKEUP SEARCHTIMEOUT TIMER
CLKWUPSTO

wakeup searchtimeout
001aan627

Fig 37. Wakeup search timeout timer schematic

The wakeup search timer consists of a prescaler and a timer register. The clock is derived
from the mainscaler clock and is therefore associated with the selected baud rate.
The timeout can be selected by WUPSTIMEOUT[5:0] and is calculated as
WUPSTIMEOUT5:0]  TWUPSTO for WUPSTIMEOUT[5:0] = 1 to 63d.
The value WUPSTIMEOUT[5:0] = 0 disables the timeout timer and selects an infinite
timeout.
The generated timeout has an uncertainty of 2 to 0 TBIT regardless of the setting of
WUPSTIMEOUTPRESC[1:0] and WUPSTIMEOUT[5:0].
Timeout timer resolution and range:• The fastest bit rate of 50 kbit/s requires the timeout to be adjusted in a range of 40 s
up to 80 ms with a resolution of 40 s, 80 s, 320 s, and 1.28 ms respectively.

• A bit rate of 1 kbit/s requires the timeout to be adjusted in a range of 2 ms up to 4 swith a resolution of 2 ms, 4 ms, 16 ms, and 64 ms respectively; see Section 8.2.2.4“Register WUPSTO” on page 100.

7.27 Wakeup search logic
A summary of the signal monitoring conditions which can be used as wakeup criteria areshown in Table 13.

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Table 13.

Overview of signal monitoring methods

Block name

Processes the signal

Started by

Output is valid after

Can be started by

RSSI levelclassification

digitised RSSI-

input is valid-

Modulation amplitudeclassification

demodulated
basebandstart of wakeup search 2 chips-

Slicerstart of wakeup search 2 bits if initialonly if initial acquisition acquisition, otherwise
is enabled
immediately

timeout from chiptiming verification, only
if enabled and inmode 2Chip timing verification slicer output
and code checker

slicer output valid after 0 < t <5 chips (2 chip
start of wakeup search time-outs)

in mode 2 by the slicer,
only if initial acquisitionis enabled

Baud-rate checker

8 bits  t  configured
FIRST_SYNC or
RESYNC of the timing observation length (8,verification after start of 16, 24 or 32 bits)
wakeup searchin mode 2 by the chiptiming verification withanother FIRST_SYNC
or RESYNC

start of wakeup search FAIL after configured
timeout-

Wakeup search timer-

At the start of a wakeup search the following blocks are reset:• wakeup search timer• modulation amplitude classification• chip timing verification and code checker• baud-rate checker• the slicer (conditionally)
The slicer is only reset if configured to acquire the value from the slicer initialisation
register (SLICERINITSEL_x[1:0] not equal to 00b). If slicer initial acquisition is selected,
the chip timing verification, code checker block and baud-rate checker are held in thereset state for the duration of the slicer initial acquisition mode.
Register SIGMON_EN_W[5:0] provides enable bits which determine signal monitors thatare considered for the overall wakeup detection decision; see Section 8.2.2.1 “Signal
monitoring register SIGMON0” on page 98. All signal monitors operate regardless ofthese enable bits and, after the wakeup search ends, their results are available in thecorresponding status bits. Section 7.27.1 and Section 7.27.2 describe how the individual
results from several signal monitors can be combined to achieve an overall wakeup
decision.
Each of the signal monitors can have an invalid period caused by an initialisation or
resynchronisation during which the output result is not considered. The logic depicted in
Figure 38 shows how this information is translated into the PASS/FAIL condition used by
the wakeup search logic. If a signal monitor is in its invalid state, neither a PASS or FAIL
condition is generated. If a signal monitor is not selected for the wakeup search, the FAIL
is always zero and the PASS always one. The PASS and FAIL signals are exclusively
used for the wakeup search logic and they must not be confused with the actual state of
the corresponding signal monitor (signals VALID and ERROR) which can be observed inregisters SIGMONSTATUS and SIGMONERROR; see Section 8.2.2.10 “Register
SIGMONSTATUS” on page 105.
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valid
fail

error

pass

WUPS_EN[i]001aan628

Fig 38. Creation of PASS/FAIL information from one signal monitor

Two different mechanisms are provided for the wakeup search:• ‘pessimistic wakeup search’ or mode 1• ‘optimistic wakeup search’ or mode 2
In the pessimistic wakeup search (mode 1) the wakeup search timer has no meaning andtherefore will not influence the result. In the optimistic wakeup search (mode 2) the
wakeup search timer is always active.

WUPSMODEWAKEUP SEARCH
TIMER

timeout

interrupt request:
wakeup searchfinished

fail
RSSI LEVELCLASSIFICATION

pass

fail
MODULATION AMP.
CLASSIFICATION pass
fail
CHIP TIMING
CLASSIFICATION

pass
fail

CODE
CHECKER

pass
fail

BAUD-RATECHECKER

pass

wakeupdetected

WUPSFAIL
001aan629

Fig 39. Block diagram of wakeup search

At the end of the wakeup search an interrupt request is generated and the result is storedin bit WUPSFAIL. If this bit is set, it signals that the wakeup criteria was not met.
Otherwise it is cleared. The content of this bit is undefined prior to first use of the wakeup
search.
The polarity of bit WUPSFAIL is chosen so that register SIGMONSTATUS can be used asa mask for register SIGMONERROR when the host controller is interested in retrieving
the cause of an unsuccessful wakeup detection. If the wakeup search was successful (bitWUPSFAIL is cleared) the content of register SIGMONERROR is not required to beconsidered as all relevant bits are cleared.
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SIGMONSTATUS

SIGMONERRORWUPS_ENWUPSFAILWUP TIMEOUTWUPSMODECHIP TIMEOUT
CHIP TIMING
CODING

valid
indicators

BAUD RATERSSI LEVELMODULATION AMPLITUDE TOO HIGH
MODULATION AMPLITUDE TOO LOW

RFU

status register
address k + 1

control registerstatus register ataddress k

001aan630

Fig 40. Wakeup search registers

7.27.1 Sampling the signal monitoring status
Since the information from the OL2311’s signal monitoring method is made up of morethan 8 bits, it is desirable to provide a mechanism which ensures that the controller canalways retrieve a consistent set of status information. Therefore the OL2311 provides
three status registers: SIGMONSTATUS, SIGMONERROR and RSSILEVEL into which
the status is simultaneously transferred, whenever it is either actively requested by thecontroller or automatically saved by the wakeup search logic; see Section 8.2.2.12“Register RSSILEVEL” on page 106.
There are two cases in which the status is sampled:• after a read command, regardless of the address that follows, but only if bit
STATAUTOSAMPLE is set; see Section 8.2.2.8 “Register RXCON” on page 102• always at the end of a wakeup search
Bit STATAUTOSAMPLE either allows software to control the sampling of the status
information with each read command (logic 1) or allows the status to be unaffected by any
read command (logic 0). This allows consistent read and write command status
information to be read as shown by the examples given in Table 14 and Table 15.
Table 14.

OL2311

Product data sheet

Example 1: Using single byte reads

Command

Description

Write (STATAUTOSAMPLE, 1)

enable status sampling with the next read

Read (SIGMONSTATUS)

this samples the consistent status

Write (STATAUTOSAMPLE, 0)

disable status sampling with the next reads

Read (SIGMONERROR)

consistent with line 2

Read (RSSILEVEL)

consistent with line 2

Read (SIGMONSTATUS)

reads the same as line 2

Read (RSSILEVEL)

reads the same as line 5

Read (SIGMONERROR)

reads the same as line 4

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The status of SIGMONSTATUS, SIGMONERROR and RSSILEVEL is only sampled inline 2. Single byte read commands (lines 4 and 5) only transfer the previously sampled
status once bit STATAUTOSAMPLE is set back to logic 0. Lines 4 to 8 do not change thecontents of the registers because status sampling is already disabled.
Table 15.

Example 2: Using read command auto-increment address

Command

Description

Write (STATAUTOSAMPLE, 1)

enable status sampling with the next read

Read (SIGMONSTATUS, SIGMONERROR,RSSILEVEL)

using the address auto-increment feature, thestatus is sampled at the start of the readcommand and then, since the status registers
occupy adjacent addresses, the continuous
reading of these bytes transfers the consistentstatus to the controller

Bit STATAUTOSAMPLE is automatically set to logic 0 at the end of a wakeup search. Thisguarantees that the important wakeup search results are retained until they aretransferred to the controller. It can also be automatically set to logic 1 whenever the status
register RSSILEVEL is transferred to the controller, provided bit AUTOSAMPLEMANUAL
is cleared; see Section 8.2.2.8 “Register RXCON” on page 102. This allows the scenario
following a wakeup search: the status information is automatically sampled and stored in
the status registers until the last status register (RSSILEVEL) is read. The controller now
continues polling the signal monitors without switching the status into ‘live’ mode, because
reading register RSSILEVEL automatically sets bit STATAUTOSAMPLE. Note that further
consistent status polling requires the address auto-increment feature to continue beingused.
If automatic entry to ‘live’ mode is undesired, bit AUTOSAMPLEMANUAL can be set tokeep bit STATAUTOSAMPLE under software control. Note that bit STATAUTOSAMPLE isalways cleared after completing a wakeup search. This is necessary to guarantee that the
wakeup search results are unconditionally sampled and saved until the controller acquiresthem.

7.27.2 Evaluating the wakeup search result
The bits in register SIGMONSTATUS provide the VALID information for the signal
monitors. If a VALID flag is zero, the corresponding bit in register SIGMONERROR is also
zero. Bit SIGMONERROR is set if an error occurs. The failing signal monitor can be
identified by reading register SIGMONERROR. Calculating the expression
SIGMONSTATUS & ~SIGMONERROR indicates which signal monitors provided a pass
result; see Table 89 “Signal monitor states set by registers SIGMONSTATUS andSIGMONERROR” on page 105.

7.28 Data reception
7.28.1 Preamble detection
A preamble detection can be issued upon completion of a wakeup search or at any time
when expecting a frame. The preamble pattern can be configured with a length between 1
and 32 chips. The preamble length is set with the PREA_LEN[4:0] control bits. If
PREA_LEN4:0] is set to logic 0 a length of 32 chips is used. The bit error rate of thepreamble can be configured with register PREA_TOL; see Section 8.2.2.13 “Register
PREACON” on page 106.
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7.29 RX data decoding
After a wakeup search, if configured, a preamble detection and data reception follows
seamlessly. After successful completion of the wakeup search and the preamble
detection, the RX data is switched to the corresponding port pins, dependent on thedevice configuration. The data pin is kept LOW during wakeup search and HIGH during
preamble detection. Data reception can be interleaved with SPI commands. Details are
given in Section 7.23.2 “Receive command” on page 42. The device has a Manchester
code recovery feature which enables inversion of the RX data. The precondition of thiscode recovery unit is the full reception of a Manchester data stream with at least one
polarity change within the code. The accumulated sum of data changes within a chip canbe found in the MANCHESTER_COUNT[3:0] field in register EXTRXSTATUS; see
Section 8.2.3.1 “Register EXTRXSTATUS” on page 107. This is a 4-bit signed number
which is applicable only when receiving data through the Manchester decoder. It is notneeded if the frame start is properly synchronised with a preamble detection. If data
reception is initiated with the DATA sub-command (without preamble detection), theManchester decoding starts at the first chip it gets, without knowing whether this is the leftor the right bit half. The RX data line can deliver the data correctly or inverted. If the signal
contains any bit transitions, this counter counts up if the transition occurs at the assumed
bit boundary (i.e. when it is correct) and it counts down if the transition occurs in the
middle of the assumed bit grid (i.e. when it is incorrect). The result is that bit 3 of thiscounter is logic 0 if the data is decoded properly and it is logic 1 if the data is delivered
inverted. The whole counter stays at zero if the RX signal contains no bit transitions, inwhich case it is not possible to tell whether the RX data is a long run of only zeros or a runof ones. If the sum is negative, the RX code must be treated as inverted, if the sum ispositive, the data reception was correct. It is possible to invert the RX data stream by
setting bit INV_RX_DATA; see Section 7.13.1 “Clock recovery for RX mode” on page 26.
If the receiver is configured transparently (see register RXCON), the data pin is directly
switched to the selected data slicer and mapped to the corresponding port pin after the RXcommand is issued.

7.30 RX clock generation
After a wakeup search, if configured, a preamble detection and clock recovery operate inparallel. Allow sufficient settling time from the start of data reception to the successful
recovery of a stable clock. The run-in time (wakeup time and length of preamble) must be
longer than the programmed settling time without code timing violations in-between the
different phases to ensure correct operation. After successful completion of the wakeup
search and the preamble detection, the bit or chip clock is switched to the corresponding
port pin, depending on the device configuration. During wakeup search and preamble
detection, the clock pin is kept at a constant HIGH. Data reception can be interleaved by
SPI commands. Details are given in Section 7.23.2 “Receive command” on page 42.
If bit RX_MANCHESTER is set, the clock rate is set to the bit rate so that every second
chip is sampled at the correct time; see Section 8.2.2.8 “Register RXCON” on page 102.
This enables the microcontroller to directly decode the Manchester bit stream by sampling
the RX data with the negative clock edges.
If the receiver is configured in a transparent mode, the clock pin is directly switched toclock recovery and mapped to the corresponding port pin after the RX command isissued.

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7.31 RX digital signal processing
7.31.1 AM demodulator
AM demodulation requires bit DEMOD_ASK in register RXBW to be set; see Section
8.2.1.18 “Channel filter bandwidth and RSSI filter settings register RXBW” on page 92. In
this case, the data from ASK demodulator output will be connected to the digital baseband
filter input.

7.31.2 FM demodulator
The FM demodulator consists of a discrete delay line and an XOR gate. This principle isused because it features perfect linearity over the full input frequency range. The FM
demodulator takes the limited IF I signal and optionally also the Q signal as its input andproduces a square-wave type output signal whose time varying average – the low
frequency component – is directly proportional to the input frequency. Figure 41 shows adetailed block diagram of the FM demodulator.

limited IF
I channel
0limited IF
Q channel

1

N-TAP DISCRETE
DELAY LINE

demodulator
output16 MHz

FM_DEM_IANDQLARGE_FM_DEM_RANGE

001aan631

Fig 41. XOR FM demodulator

If bit FM_DEM_IANDQ is set to logic 0, only the limited I channel IF input is used for
demodulation. In this case the demodulator is set to a centre frequency of 300 kHz. If bit
FM_DEM_IANDQ is set to logic 1, the I and the Q signals, which have a phase differenceof 90 , are combined with an XOR gate. In these circumstances the demodulator is set toa centre frequency of 600 kHz as the I and Q combination effectively doubles thefrequency.
If the input frequency is within the specified range, the average value of the second XOR’s
output is a perfectly linear function of the input frequency.
If bit LARGE_FM_DEM_RANGE is cleared, the input frequency range of the FM
demodulator is 200 kHz to 400 kHz. This is the appropriate setting for frequency
deviations up to  100 kHz. If this bit is set to logic 1, the input frequency range is
extended to between 0 Hz and 600 kHz, allowing for process frequency deviations, which
are only limited by the analog channel filter. The demodulator output noise increases by
the same factor (3) as the frequency range in these circumstances.
Switching to the large input frequency range is achieved by cutting the length of the delayline into one third of its original value. However, this also changes the slope of the output
characteristics from positive to negative thereby inverting the demodulator output. The
third XOR compensates for this inversion.

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Table 16. FM demodulator configurations
See register EXPERT2 bit descriptions in Table 99 on page 109.
D7

D6

Center frequency(kHz)

Input frequency range Maximum frequency(kHz)
deviation (kHz)

Number of delay
elements

0

0

300

200 to 400

100

40

0

1

300

0 to 600

300

13

1

0

600

200 to 400

100

20

1

1

600

0 to 600

300

77.31.3 Baseband filter
The baseband filter serves the following purposes:• suppresses the high frequency (square-wave) components from the FM demodulator,
leaving only the time-varying average, or baseband component of the demodulated
signal• suppresses spectral portions of the quantization noise from the demodulator and thedemodulated noise coming from the RF input which do not fall into the baseband
signal’s bandwidth• helps achieve a suitable sampling rate for further processing of the baseband signal
The baseband filter is a 3rd-order IIR filter topology that is optimized such that it features a
step response with almost no ringing as shown in Figure 43.
7.31.3.1

RX baseband configuration
The filter is split into a 1st-order and a 2nd-order section to minimize the internal
quantization noise. Figure 42 shows the baseband filter distributed over two filter blocks.

BASEBAND_FILTER_FC
output from FM
demodulator
result fromRSSI ADC

01

DOWNSAMPLE
1st-order
section

DEMOD_ASK
1st-order
section2nd-order
sectionto baseband
processing

001aan632

Fig 42. Baseband filter signal flow

The 1st and 2nd-order sections combine to make the 3rd-order baseband filter for ASK or
FSK. The filter cut-off frequency is controlled by register BASEBAND_FILTER_FC control
bits; see Section 8.2.1.22 “Register RXBBCON” on page 93. The 1st-order section filters
the RSSI information which is sampled with the ADC in the limiter/RSSI analog circuitry.
Its cut-off frequency can be controlled separately by register RSSI_FILTER_FC; see
Section 8.2.1.18 “Channel filter bandwidth and RSSI filter settings register RXBW” onpage 92.
Note that the baseband filter and the RSSI filter are two separate filters.

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Figure 43 and Figure 44 show the step response and the frequency response of thebaseband filter, respectively. Figure 43 shows that the step response has an undershoot(negative overshoot) of approximately 3 % and an almost unnoticeable overshoot. This
demonstrates a characteristic close to that of an analog Bessel filter. Figure 44 contains
one frequency response curve for each of the ten implemented cut-off frequency control
values (0 to 9).

001aan633

1.2
amplitude

0.8

0.4

0
0

40

80

120

160
200
samplesFig 43. Step response of the baseband filter

001aan6340amplitude responses
(dB)
−20
−40
−60
−80
−100

1

10

102

103

104

105

107
106
f (Hz)

Fig 44. Frequency response of the baseband filter

The accurate output sampling frequency of the data filter can be calculated. The
frequency is divided by a factor of 2 when the cut-off frequency control setting isincremented by 1. The relevant formula is:
114 kHzf c = ----------------------FskFilterFc
2(25)

It can be seen that each increment in the cut-off frequency control setting divides thecorner frequency of the filter by approximately a factor of 2.

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Table 17.

BASEBAND_FILTER_FC definition

D3

D2

D1

D0

Cut-off frequency (fc)Down-sampling factor

Output sampling rate

0

0

0

0

115.45 kHz

2

8 MHz

0

0

0

1

57.174 kHz

4

4 MHz

0

0

1

0

28.405 kHz

8

2 MHz

0

0

1

1

14.204 kHz

16

1 MHz

0

1

0

0

7.0795 kHz

32

500 kHz

0

1

0

1

3.5400 kHz

64

250 kHz

0

1

1

0

1.7701 kHz

128

125 kHz

0

1

1

1

885.12 Hz

256

62.5 kHz

1

0

0

0

442.59 Hz

512

31.25 kHz

1

0

0

1

221.31 Hz

1024

15625 Hz

-

-

-

-

undefined

undefined

undefined

7.32 RX debug interface
If the digital scan test and the channel filter multi-tone test are both not active(CF_MULTITONE_EN = 0), setting RXD_DBG_SEL[3:0] to a non-zero value switches
ports P10/DATA/TEST4, P11/INT/TEST5 and P12/CLOCK into RX digital debug mode;see Section 8.2.5.1 “Register TEST0” on page 110. In this mode the normal function ofthese pins is overwritten with the function of a fast 3-wire synchronous serial transmission,
where:• P12/CLOCK outputs the 16 MHz serial clock• P10/DATA/TEST4 outputs the serial data. This data changes with the 16 MHz clock
rising edge and it is stable at the clock falling edge. Each data word consists of
16 bits. Words are transmitted starting with the MSB and ending with the LSB.

• P11/INT/TEST5 outputs a synchronization pulse for each serial 16-bit data word. Thisline goes HIGH during transmission of bit 0, which is the last bit of each word. Afterthe pulse, transmission continues with the MSB of the next 16-bit word.

P12/CLOCKP10/DATA/TEST4

bit 2

bit 1

bit 0

bit 15

bit 14

bit 2

bit 1

bit 0

bit 15

bit 14

P11/INT/TEST5
001aan635

Fig 45. Data transmission on the RX digital debug interface

RXD_DBG_SEL[3:0] determines which 16-bit signal vector is sampled in parallel at
1 Msamples/s and output as a serial data stream as shown in Figure 45. The available
debug signal vectors are given in Table 18.

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Table 18.

Available RX debug signal vectors

RXD_DBG_SEL Bit range Signal nameSignal description

1[15:8]

w8RssiLevelOut

digitised RSSI result as it can be retrieved through the status
register RSSI_LEVEL

1[7]

wIFSettledIn

indicates when the 300 kHz IF signal is declared stable

1[6]

wRssiSettled

indicates when the RSSI result is declared stable

1

[5:0]

r6RawRssiAdcValOut

raw RSSI ADC readings

2[15:4]

w12FiltdRssi

RSSI signal after the 1st order low-pass filter

2[3]

rFrontEndGainLoOut

indicates which of the front-end gain settings are applied. 0:
RX_HI_GAIN, 1: RX_LO_GAIN

2[2]

wRssiGtUpperTh

indicates when the RSSI result is greater than the threshold
set with UPPERRSSITH

2[1]

wRssiLtLowerTh

indicates when the RSSI result is less than the threshold set
with LOWERRSSITH

2[0]

wRssiOutsideLimitsOut

indicates when the RSSI is outside the limits defined withboth LOWERRSSITH and UPPERRSSITH.

3[15:4]

w12DataFilter1Res

baseband signal after the 1st-order section of the baseband
filter

3[3]

wLimIfIIn

digital IF input from the I channel limiter

3[2]

wLimIfQIn

digital IF input from the Q channel limiter

3[1]

wRawXorFmDemodraw, unfiltered output from the XOR FM demodulator

3[0]

wIFSettled

indicates when the 300 kHz IF signal is declared stable

4[15:1]

w15BasebandSig

filtered and interpolated baseband signal

4[0]

wBasebandValid

indicates when the baseband signal is declared valid

5[15:1]

w15SlicerInitThrRegOutcontents of the initial slicer threshold register. This is thesame as it is available through registers SLICERINITL and
SLICERINITH.

5[0]wLoadInitSlicerThr

indicates when the initial threshold register is re-loaded. At
chip rates > 7812 chip/s this pulse is shorter than thesampling interval and so pulses may be missed

6[15:1]

w15SlicerThr

threshold of the level slicer.

6[0]

wLoadSlicerThr

indicates when the threshold is re-loaded. At chip rates >7812 chip/s this pulse is shorter than the sampling intervaland so pulses may be missed.

7[15:8]

ws8ClkRcvPllPhaseError

signed clock recovery phase error measurement value in
offset binary format.

7

[7:0]

-

always zero (Reserved)

8

[15]

wRxFrame

indicates when data is being received

8

[14]

wRxData

RX data sampled with wRxClock and optionally Manchester
decoded8[13]

wRxClock

Recovered bit clock

8

[12]

wPatternMatchraw pattern match indicator from the preamble detection
block

8

[11]

wChipClockraw chip clock from clock recovery PLL

8

[10]

wEdgeDetectededge detector output from deglitcher, pulses are shorter than
the sampling interval for chip rates > 7812 chip/s so somepulses may be missed

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Table 18.

Available RX debug signal vectors …continued

RXD_DBG_SEL Bit range Signal nameSignal description

8[9]

wDeglitchedLevel

output from deglitcher block8[8]

wDeglitchedLevelValid

indicates when deglitcher output and edge detector output
are valid

8[7]

wSlicerResult

selected slicer result

8[6]

wSlicerReady

indicates when selected slicer is ready to deliver a valid
signal8[5]

wSlicerValid

indicates when selected slicer actually delivers a valid signal

8[4]

wBasebandValid

indicates when baseband signal is declared valid

8[3]

wRxRdyOut

indicates when RX hardware is ready and baseband signal isstable, same as bit RX_RDY in register DEVICE_STATUS

8[2]

wIfSigSettledTo2ndOrderFilt

indicates when IF signal is declared stable, signal principally
the same as the next but is longer for processing with slower
clock

8

[1]

wIfSigSettled

indicates when IF signal is declared stable

8[0]

wRxAnaRdy

indicates when analog RX hardware is ready (powered up
and calibrated)

9

[15]

wCmdTimeout

indicates when a timeout occurs during a wakeup search or
preamble detection

9

[14]

wSigMonFail

logic 1 if enabled signal monitors indicate a fail condition

9

[13]

wSigMonPass

logic 1 if signal monitors indicate a pass condition

9

[12]

wCmdTimeoutEn

indicates when command timeout counter is active

9

[11]

wCTVTimeout

indicates a chip timing verification timeout (no edges for morethan (3.5  REDUCED_CHIP_TIMEOUT) times the chipduration)

9[10]

wSingleBitTmgError

single chip timing error ( interval between two edges exceeds
limits defined by SGLBITTMGERRTH[1:0])

9[9]wCodeCheckerError

indicates code checker detected an error

9[8]

wCTVValid

valid signal for chip timing verification block, indicates validityof chip timeout, single chip timing error and code checker

9[7]

wBaudrateCheckerError

indicates baud-rate checker error

9[6]

wBaudrateCheckerValidbaud-rate checker result is valid signal

9[5]

wRssiOutsideLimits

indicates current RSSI result is outside limits defined byregisters UPPERRSSITH and LOWERRSSITH

9[4]

wRssiSettledOut

indicates when RSSI result is declared stable

9[3]

wSigAmpTooHighindicates baseband amplitude (modulation amplitude) isgreater than limit defined by register UPPER_MODAMP_TH

9[2]

wSigAmpTooHighValid

valid indicator for signal wSigAmpTooHigh

9[1]

wSigAmpTooLow

indicates baseband amplitude (modulation amplitude)
smaller than limit defined by register LOWER_MODAMP_TH

9[0]wSigAmpTooLowValid

valid indicator for signal wSigAmpTooLowValid

9

-

-

always zero (reserved)

OL2311

Product data sheet

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74 of 133

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

8. Special function registers
8.1 Overview
A map of the Special Function Registers (SFR) is shown in Table 19.
The SFRs are arranged into two banks: bank 0 and bank 1. Bank 0 or bank 1 can beselected by setting bit BANK_SEL in register BANKSEL, visible in both banks,
accordingly.
Bytes 0 to 2Dh and 3Fh can always be accessed, independent of the setting of bit
BANK_SEL in register BANKSEL (3Fh). Clearing bit BANK_SEL enables bytes 2Eh to
3Eh in bank 0; the contents of bank 1 remain unchanged. Setting register BANKSEL
activates bytes 2Eh to 3Eh in bank 1.
Reading from a status register returns the current status of the device. Writing to a status
register is ignored by the device. Status bits are identified by [4] in Table 19.
All control registers can be accessed via the SPI interface. If a control register contains
less than 8 bits, writing to a non-existent bit has no effect and reading from a non-existent
bit always returns a zero. All registers are control registers (Write only) unless otherwise
indicated.
Some register bits provide information about the implemented state-machines. These
additional status bits can change independently of SPI transmission. These bits are also
identified by [4] in Table 19, other bits such as VCO_SUBBAND[5:0] can also change.
The control registers remain stable during power-down. When a Power-on reset occurs,
evaluated by reading bit IF_POR in register IFLAG), register bits identified by [1] inTable 19 are preset to their default values.
Bits denoted by RFU are reserved. These bits are Read/Write but do not effect the device.

OL2311

Product data sheet

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Rev. 1 — 8 December 2011

© NXP B.V. 2011. All rights reserved.

75 of 133xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Register map table

Register

Addr BankBit
7 (MSB)

6

5

4

FC0L[1]32

10 (LSB)

Default
value [7]

0

0

0

0

0000 0000

FC0L

00h

01

FC0M

01h

01

FC0M[1]0000 0000

FC0H

02h

01

FC0H[1]1011 0001

FC1L[2]

FC1L

03h

01

FC1M

04h

01

FC1M[2]0

XXXX XXXX

FC1H

05h

01

FC1H[2]XXXX XXXX

FC2L[2]

0

0

0

06h

01

FC2M

07h

01

FC2M[2]XXXX XXXX

FC2H

08h

01

FC2H[2]XXXX XXXX

09h

01

FC3M

0Ah

01

FC3M[2]

FC3H

0Bh

01

FC3H[2]

VCOCON

0Ch

01

LOCON

0Dh

01

TIMING0

0Eh

0

0

0

0

0

CLK2SCLK_DELAY[1]XXXX XXXXSKIP_VCOCAL[1]0SXX XXXXLOCK_DET
ON[1]

VCO_
BAND[1]

RF_LO_DIV 0000 0001
[1]

MAINSCL[1]01
WATCHDOG_TIME[1]0000 0000

PRESC[1]MAINSCH[1]

0Fh

01

PORTCON010h

01

PORTCON1

11h

01

PORTCON2

12h

01

SEP_SDO[1]SEP_RX_
OUT[1]

RFU[1]

RFU[1]PWRMODE

13h

01

0

0

0

POLLTIM_
EN[1]

IEN

14h

01

IE_RX_
RDY[1]

IE_EOF[1]IE_PREA[1]IE_WUPS[1]IE_
IE_WATCHD IE_BROWNPOLLTIM[1]OG[1]OUT[1]

IFLAG

15h

01

IF_RX_
RDY[1]

IF_EOF[1]IF_PREA[1]IF_WUPS[1]IF_
POLLTIM[1]POLLWUPTIME

16h

01

P11INV[1]P13C[1]

P10C[1]P13INV[1]P12C[1]
RFU[1]

P14C[1]

DEV_MODE[5]PD[3]IF_WATCHD IF_BROWN
OG[1]
OUT[1]

0110 0000
P10INV[1]0010 1000

P12INV[1]0000 1110

P14INV[1]0000 0000

RESET[3]000S 0000

00000 0000

IF_POR[1]0000 0001

POLLWUPTIME[1]POLLACTION

17h

01

POLL_MODE[1]CLOCKCON

18h

01

MANUALPTPTCAL
CAL[3]RUNNING[4]RX_FREQ[2]EXTPOLLTIMRNG[1]RX_CMD[2]CLKSOURCESEL[1]1111 1111
RX_GAIN[2]EXT_CLK_BUF_EN[1]SET_RX_FLAGS[2]00XX XXXXXODIS[1]0S00 0100

OL231176 of 133

© NXP B.V. 2011. All rights reserved.

TIMING1

P11C[1]XXXX XXXXXXXX XXXXVCO_SUBBAND[2]VCO_CAL_FORCE_
VCO_CAL[3] RUNNING[4]XXXX XXXX

Highly integrated single-chip sub 1 GHz RF receiverRev. 1 — 8 December 2011

All information provided in this document is subject to legal disclaimers.

FC3L

0

XXXX XXXX

FC2L

FC3L[2]00

NXP Semiconductors

OL2311

Product data sheet

Table 19.

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Register map table …continued

Register

Addr BankDEVSTATUS

19h

01

RXGAIN

21h

01

Bit
7 (MSB)

6

5

4

3

2

1

0 (LSB)0

PA_ON[4]PA_PWR_RDY[4]

LO-PWR_RDY[4]

RX_RDY[4]RFU

LO_RDY[4]REFCLK_
RDY[4]

RX_HI_GAIN[1]CF_BW[1]Default
value [7]0SSS SSSS

RX_LOW_GAIN[1]1111 0000

RSSI_FILTER_FC[2]X000 XXXX

RXBW

22h

01

DEMOD_
ASK[2]GAINSTEP

23h

01

0

HIGAINLIM

24h01

HI_GAIN_LIMIT[2]XXXX XXXXXXXX XXXXRSSI_GAIN_STEP_ADJ[2]

25h

01

LOWERRSSITH

26h

01

LOWERRSSITH[2]RXBBCON

27h

01

UMODAMPTH

28h

01

0XXX XXXXXXXX XXXXBASEBAND_FILTER_FC[2]XXXX XXXXUPPER_MODAMP_TH_EXP[2]UPPER_MODAMP_TH_MANT[2]XXXX XXXXLOWER_MODAMP_TH_MANT[2]XXXX XXXXEDGE_MODAMP_TH_MANT[2]XXXX XXXXDEGLITCHER_
WINDOW_LEN[2]BASEBAND_SETTL_TIME[2]

LMODAMPTH

29h01

LOWER_MODAMP_TH_EXP[2]EMODAMPTH

2Ah

01

EDGE_MODAMP_TH_EXP[2]RXDCON02Bh

01

NUM_MODAMP_GAPS_W[2]SLICERSEL_W[2]RXDCON1

2Ch

01

NUM_MODAMP_GAPS_P[2]SLICERSEL_P[2]

SLICER_INITSEL_PD[2]RXDCON2

2Dh

01

NUM_MODAMP_GAPS_D[2]SLICERSEL_D[2]CODINGRESTR_W[2]SIGMON0

2Eh

0

WUPS
MODE[2]

SIGMON_EN_W[2]SIGMON1

2Fh

0

EN_
PREADET_TIMEOUT[2]SIGMON_EN_P[2]

ACCU_SIG 0XXX XXXXFAILS_P[2]

SIGMON230h

00

SIGMON_EN_D[2]ACCU_SIG XXXX XXXXFAILS_D[2]

WUPSTO

31h

0

WUPSTIMEOUTPRESC[2]SLICER_INITSEL_W[2]

INIT_ACQ_BITS_W[2]XXXX XXXXINIT_ACQ_BITS_PD[2]XXXX XXXXCODING
CODING XXXX XXXXRESTR_P[2] RESTR_D[2]0

WUPSTIMEOUT[2]XXXX XXXXSLICERINITTHR_LO[2]32h0SLICERINITH

33h

0

0

TIMINGCHK

34h

0

RFU[2]

RXCON

35h

0

STATAUTOSAMPLE[2]XXXX XXXXSLICERINITTHR_HI[2]BROBSLENGTH[2]AUTO
SAMPLEMANUAL[2]INV_RX_DATA[2]SUBMITTMGERRTH[2]CLOCK_RECOV_TC[2]0XXX XXXXSGLBITTMGERRTH[2]RX_MAN
RX_CLOCKCHESTER[2] TRANSP[2]XXXX XXXX

RX_DATA_ XXXX XXXX
TRANSP[2]OL231177 of 133

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SLICERINITLXXXX XXX0

Highly integrated single-chip sub 1 GHz RF receiverRev. 1 — 8 December 2011

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UPPERRSSITH

UPPERRSSITH[2]NXP Semiconductors

OL2311

Product data sheet

Table 19.

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Register map table …continued

Register

Addr BankRXFOLLOWUP

36h

0

SIGMONSTATUS 37h

0

SIGMONSTATUS[4]SSSS SSSSSIGMONERROR 38h

0

SIGMONERROR[4]SSSS SSSSRSSILEVEL0

RSSI_LEVEL[4]

39h

Bit
7 (MSB)

6

PREA_FU_
TF[1]

PREA_FU_
CF[1]

RFU[2]

5

4

3

WUPS_FU_TS[1]2

PREA_TOL[2]1

WUPS_FU_CS[1]WUPS_FU_TF[1]0 (LSB)

Default
value [7]WUPS_FU_ 1000 1000
CF[1]SSSS SSSSPREA_LEN[2]PREACON

3Ah

0

PREA0

3Bh

0

PREA0[2]XXXX XXXXXXXX XXXXXXXX XXXX

3Ch

0

PREA2

3Dh

0

PREA2[2]XXXX XXXXPREA3[2]XXXX XXXX

3Eh

0

EXTRXSTATUS

2Eh

1

RX_HI_GAIN[4]LIVE_STATUS[4]CFRCCAL

2Fh

1

CF_IQ_CAL_RUNNING

CF_RC_CAL_RUNNING[4][4]CFIQCAL

30h

1

START_CF_
IQ_CAL[3]EXPERT0

31h

1

RED_VCO_SWING[1]EXPERT1

32h

EXPERT2

33h

EXPERT3

34h

RXCMD[4]0

CF_RC_CAL_RES[4]SS00 SSSS

CF_IQ_CALVAL[1]1

XOSTARTUPDELAY[1]ASKRSTBB
MID[1]

1

FM_DEM_
IANDQ[1]WIDE_REDUCED_ TWORSSIM
AMPL_
CHIP_
SBITS
WINDOW[1]
TIME[1]
SLOW[1]LARGE_FM_DEM_
RANGE[1]000000 0000

PLL_ICP[1]FASTCFFILTSETTL[1]0

SSSS SSSS0LARGE_
PLL_RST_
DELAY[1]1

MANCHESTER_COUNT[4]RFU[1]

0

RFU[1]

RFU[1]

0000 0100

DISFRAC[1]LOCK_DET_TIME[1]0100 1001

FASTRSSI
FILTSETTL

CAP_RSSI[1]0000 0010[1]

ALLOWREGLTDIQ
SWITCH[6] PHASECAL
[1]

35h

1

CF_MULTITONE_EN[6]DIG_TEST_SEL[6]

TEST1

36h

1

IQ_TEST_
LV[6]

ANA_TEST_SEL[6]RXD_DBG_SEL[6]REG_DIG_DIS[6]

PLL_CTRL[6]0000 0000

0110 0000
VCO_TEST 0000 0000
ON[6]OL231178 of 133

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TEST0

DONOT
DISTURB
PTCAP[1]Highly integrated single-chip sub 1 GHz RF receiverRev. 1 — 8 December 2011

All information provided in this document is subject to legal disclaimers.

PREA1

PREA1[2]PREA3

NXP Semiconductors

OL2311

Product data sheet

Table 19.

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Register map table …continued

Register

Addr Bank

TEST2

37h

Bit
7 (MSB)

6

5

4

3

2

1

0 (LSB)1

REG_VCO_ON[6]

REG_PLL_
ON[6]

REG_PA_
ON[6]FORCE_
REG_VCO_RDY[5]FORCE_
REG_PLL_
RDY[5]FORCE_
REG_PA_
RDY[5]FORCE_LOCK_
DETECTEDFORCE_XO_RDY[1]PRESC_ON[6]

PFD_ON[6]SKIP_CF_
RC_CAL[6]CF_RC_ADJUSTCAL[6]XO_IOFFS[2]XO_IOFF
SSINK_ENNXP Semiconductors

OL2311

Product data sheet

Table 19.

Default
value [7]0000 0000

[5]

TEST3

38h

1

VCO_ON[6]

TEST4

39h

1

FORCE_CF_RC_CAL[3]

TEST5

3Ah

1

CLK_PLL_O
N[6]

RFU

XO_IOFF
SEN[6]

RX_ON[6]PA_STEP_T 0000 0000
EST[6]

MAN_CF_RC_CALVAL[2]0000 XXXXRX_GAP_ON[6]XO_KICK_DIS[6]

XO_DET_
DIS[6]XO_BIAS_
DIS[6]XXXX 0000

[2]

3Bh

1

-[1]
-[3]

TCBEN0

3Ch

1

TCBR

3Dh

1

TCBEN13Eh

1

BANKSEL

3Fh

010000 0000
0000 0000
IDDQ1[1]-IDDQ0[1]ASYNC
SCAN[1]SCANEN[1] 0000 0000

-[3]
0

0

0

0

0000 0000
000

BANK_SEL 0000 0000
[5]

[1]

Bits/field preset at power-on.

[2]

Bits cannot be preset.

[3]

Command bits.

[4]

Status bit (Read only) and indicated by ‘S’in the Default value column. Their values are undefined because they depend on the device status after a reset.

[5]Bits/field reset in power-down mode.

[6]

Test bits.

[7]‘X’ denotes the bit is undefined after a device reset; the value is completely random and independent of the device status.

OL231179 of 133

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RFU

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

8.2 Register descriptions
The SFRs are arranged into two banks: bank 0 and bank 1. Bank 0 or bank 1 can beselected by setting bit BANK_SEL in register BANKSEL, visible in both banks,
accordingly.

8.2.1 Registers visible in both bank 0 and bank 1
8.2.1.1

Frequency control registers
The frequency control registers contain the PLL frequency control information. Fourvalues can be stored to provide four independent frequency settings available for RX
purposes. The frequency values have 20 bits. These 20 bits are divided into 4 leastsignificant bits (L) a medium significant byte (M) and a high significant byte (H).
Table 20. Frequency control register FC0L - (address 00h) bit description
Reset value = 00h.
Bit

SymbolValue

Description

7

FC0L

0

lower 4 bits of 15-bit fractional part of operating
frequency value FCx

6

0

5

0

4

0

3

-

0

2

0

1

0

0

0

-

Table 21. Frequency control register FC0M - (address 01h) bit description
Reset value = 00h.
Bit

SymbolValue

Description

7

FC0M

0

middle 8 bits of 15-bit fractional part ofoperating frequency value FCx

6

0

5

0

4

0

3

0

2

0

1

0

0

0

Table 22. Frequency control register FC0H - (address 02h) bit description
Reset value = B1h.

OL2311

Product data sheet

Bit

SymbolValue

Description

7

FC0H

0

5 integer bits of operating frequency value FCx

6

0

5

0

4

0

3

0

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Highly integrated single-chip sub 1 GHz RF receiver

Table 22. Frequency control register FC0H - (address 02h) bit description …continued
Reset value = B1h.
Bit

SymbolValue

Description

2

FCxH

1

high 3 bits of 15-bit fractional part of operating
frequency value FCx

1

1

0

0

Frequency control register FC1L (address 03h); same bit description as FC0L, but reset
value = XXh.
Frequency control register FC1M (address 04h); same bit description as FC0M, but reset
value = XXh.
Frequency control register FC1H (address 05h); same bit description as FC0H, but reset
value = XXh.
Frequency control register FC2L (address 06h); same bit description as FC0L, but reset
value = XXh.
Frequency control register FC2M (address 07h); same bit description as FC0M, but reset
value = XXh.
Frequency control register FC2H (address 08h); same bit description as FC0H, but reset
value = XXh.
Frequency control register FC3L (address 09h); same bit description as FC0L, but reset
value = XXh.
Frequency control register FC3M (address 0Ah); same bit description as FC0M, but reset
value = XXh.
Frequency control register FC3H (address 0Bh); same bit description as FC0H, but reset
value = XXh.
8.2.1.2

VCO control register VCOCON
Table 23.
Bit

SymbolValue

Description

7

FORCE_VCO_CAL

0starts a VCO calibration unconditionally whenrequested by microcontroller. 1 = calibration starts.

6

VCO_CAL_RUNNING

S

status bit indicates the VCO calibration is requested
or is in progress. 0 = sub-band value, which can beread from this register, is valid and stable.

5

VCO_
SUBBAND

X

resulting sub-band settings from the automatic VCO
calibration, value can be overwritten at any time by
the microcontroller. If the value is written during an
ongoing calibration, the result is undefined.
0 = maximum frequency, and 63h to the minimum
frequency.

4

OL2311

Product data sheet

VCO control register VCOCON - (address OCh) bit description

X

3

X

2

X

1

X

0

X

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OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

8.2.1.3

Local oscillator control register LOCON
Table 24.

Local oscillator control register LOCON - (address ODh) bit description

Bit

SymbolValue

Description

7

CLK2SCLK_DELAY

0

delay from the 9th SCLK edge in a RX command until thedevice starts driving the SCLK line. Only applicable if bit
SEP_RX_OUT is logic 0 when sending an RX command.

6

0

5

0

4

0

3

SKIP_VCO_CAL

0

automatic VCO calibration performed under the following
circumstances:• if the active FCxH, VCO_BAND, RF_LO_DIV,DOUBLE_SD_RESULT, DISFRAC changes• if the device mode switches from/to RX mode
• if frequency selection flags A, B change• if the PLL is started from idle mode
calibration under the first three conditions can besuppressed by setting this bit. Calibration is always
executed on the last condition: PLL start up.

8.2.1.4

2

LOCK_DET_ON0

1 = lock detector continuously monitors the PLL during
operation. When logic 0, the lock detector only monitors
the PLL for a short time after VCO calibration.

1

VCO_BAND0must be set to 1 for RF frequency bands below 400 MHz.
Must be set to logic 0 for all other bands.

0

RF_LO_DIV

1

0 = VCO frequency is divided by 2 to achieve an RX
frequency above 500 MHz. 1 = VCO frequency is divided
by 4 to achieve an RX frequency below 500 MHz.

Timing register TIMING0Register TIMING0 (address OEh), MAINSCL[6:0]: main scaler lower byte of baud-rate
generator; see Table 25 for description.

8.2.1.5

OL2311

Product data sheet

Timing register TIMING1
Table 25.

Timing register TIMING1 - (address 0Fh) bit description

Bit

Symbol7

WATCHDOG_ 0
TIME1

programmable watchdog timeout:

6

5

PRESC

1

baud-rate prescaler setting

40

generator. Baud rate is calculated:

30

CLK ref 2 11 + MAINSC
1-  -------------------------------------  --------- where
baud rate = ----------------PRESC
12
128
2
2
CLKREF = 16 MHz, PRESC is an exponent in therange 0 to 7 and 211 + MAINSC is the mantissa in therange 2048 to 4095. The resulting baud-rate clock canjitter by one prescaler clock cycle CLKPSC.

Value

Description
15+WATCHDOG_TIME

2
watchdog timeout = --------------------------------------------------CLK ref

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82 of 133

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

Table 25.

8.2.1.6

Timing register TIMING1 - (address 0Fh) bit description …continued

Bit

SymbolValue

Description

2

MAINSCH0

3 highest bits of baud-rate generator’s main scaler

1

0

0

0

Port control registers PORTCON0 to PORTCON2
Registers PORTCON0 to PORTCON2 define the function of Port pins P10, P11, P12, P13
and P14. Test functions can be enabled in combination with register TEST0. Register
PORTCON2 defines the general SPI mode.

8.2.1.7

Port control register PORTCON0
Table 26.

Port control register PORTCON0 - (address 10h) bit description

Bit

SymbolValue

Description

7

P11C

0

configures P11/INT; see Table 28

6

0

5

1

4

0

3

P11INV1

inverts the pin polarity

2

P10C

0

configures P10/DATA; see Table 27

1

OL2311

Product data sheet

00P10INV0logic 1 inverts the pin polarity

Table 27.

P10C port control data functions

D2

D1

Function003-state0

1

constant LOW

10

PRNG output

1

1

reserved

Table 28.

P11C port control data functions

D7

D6

D5

D4

Function

0

0

0

0

3-state

0

0

0

1

always zero

0

0

1

0

interrupt request

0

0

1

1

clock output from clock generation according to
CLKSOURCESEL[2:0] settings

0

1

0

0

CF_IQ_CAL_RUNNING

0

1

0

1

LO_RDY flag

0

1

1

0

RX_RDY flag

0

1

1

1

reserved

1

0

0

0

reserved

1

0

0

1

reserved

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83 of 133

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

Table 28.

P11C port control data functions …continued

D7

D6

D5

D4

Function

1

0

1

0

reserved signal; always 0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

test signals controlled by DIG_TEST_SEL[2:0]; see
Table 29 and Table 30

The test signals shown in Table 29 are available if register PORTCON0 bits D7 = 1, D6 =1, D5 = 1, D4 = 0 and if DIG_TEST_SEL[2:0] in register TEST0 (address 35h), are set
according to this table.
Table 29.

Test signal I

D6

D5

D4

Function000digital regulator enable

0

0

1

VCO regulator enable

0

1

0

PLL regulator enable

0

1

1

reserved

1

0

0

XO enable

1

0

1

1

1

0

1

1

1

XO startup signal kick A

The test signals shown in Table 30 are available if register PORTCON0 bits D7 = 1, D6 =1, D5 = 1, D4 = 1 and if DIG_TEST_SET[2:0] in register TEST0 (address 35h), are set
according to this table.

8.2.1.8

Table 30.

Test signal II

D6

D5

D4

Function000

I signal from limiter

0

0

1

channel filter RC calibration enable

0

1

0

polling timer enable

0

1

1

RSSI DAC value LSB

1

0

0

PLL lock detector enable

1

0

1

1

1

0

1

1

1

Port control register PORTCON1
Table 31.

Product data sheet

Port control register PORTCON1 - (address 11h) bit description

Bit

SymbolValue

Description

7

P13C

0

configures P13/SDO

6

0

5

0

4
OL2311reserved

P13INV0

1= inverts the pin polarity

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Highly integrated single-chip sub 1 GHz RF receiver

Table 31.

Port control register PORTCON1 - (address 11h) bit description …continued

Bit

SymbolValue

Description

3

P12C

0

configures P12/CLOCK; see Table 32

2

1

1

1

0

P12INV

Table 32.

0

1 = inverts the pin polarity

P12C port control data functions

D3

D2

D1

Function0003-state001

always zero

0

1

0

RX clock output; if bit SEP_RX_OUT = 1 and RX is
activated.

0

1

1

clock generated output according to
CLKSOURCESEL[2:0]

1

0

0

PLL feedback clock

1

0

1

uncalibrated polling timer clock

1

1

0

1

1

1

test signals controlled by DIG_TEST_SEL[2:0]; see
Table 33 and Table 34

The test signals shown in Table 33 are available if register PORTCON1 bits D3 = 1, D2 =1, D1 = 0 and if DIG_TEST_SET[2:0] in register TEST0 (address 35h), are set according
to this table.
Table 33.

Test signal III

D6

D5

D4

Function000digital regulator brown-out detection

0

0

1

VCO regulator brown-out detection

0

1

0

PLL regulator brown-out detection

0

1

1

reserved

1

0

0

XO_RDY

1

0

1

XO startup signal kick A

1

1

0

XO startup signal kick C

1

1

1

The test signals shown in Table 34 are available if register PORTCON1 bits D3 = 1, D2 =1, D1 = 1 and if DIG_TEST_SET[2:0] in register TEST0 (address 35h), are set according
to this table.

OL2311

Product data sheet

Table 34.

Test signal IIII

D6

D5

D4

Function000

Q signal from limiter

0

0

1

CF_RC_CAL_RUNNING flag

0

1

0

uncalibrated polling timer clock

0

1

1

RSSI ADC comparator output

1

0

0

PLL lock detector signal (raw)All information provided in this document is subject to legal disclaimers.

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Highly integrated single-chip sub 1 GHz RF receiver

Table 34.

8.2.1.9

Test signal IIII …continued

D6

D5

D4

Function

10

1

PLL lock detector signal (digitally filtered)

1

1

0

continuous 1 MHz clock

1

1

1

constant LOW (reserved)

Table 35.

P13C port control data functions

D3

D2

D1

Function0003-state001

always zero

0

1

0

reserved

01

1

RX_RDY

1

0

0

REFCLK_RDY

1

0

1

LO_RDY1

1

0

RX_RDY1

1

1

reserved

Port control register PORTCON2
Table 36.

Port control register PORTCON2 - (address 12h) bit description

Bit

SymbolValue

Description

7

SEP_SDO0

1 = P13 is 3-state or SPI data output and has priority over thenormal function of P13 [1]6

SEP_RX_OUT

0

if set to 1 and a RX command is active, P10 is always(independent of P10C settings) used as RX data and P12
conditionally used as RX clock output, depending on P12C
configuration, see Table 37 [1]

5

RFU

0

reserved

4

RFU

0

reserved

3

RFU

0

reserved

2

P14C

0

configures P14/PIND; see Table 38

1
0
[1]

0
P14INV

Product data sheet

1 = inverts the pin polarity

SEP_xxx bits override all other P13 port settings. P10C configured functions are overridden if bit
SEP_RX_OUT = 1 and RX is activated.

Table 37.

OL2311

0

SEP_RX_OUT data functions

SEP_RX_OUT

RX data output

RX clock output

0

SDIO or SDO,
depending on
SEP_SDOSCLK

1P10/DATA

P12/CLOCK (optional, only if P12C = 010b)

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Highly integrated single-chip sub 1 GHz RF receiver

Table 38.

8.2.1.10

P14C port control data functions

D2

D1

Function003-state0

1

constant LOW

1

0

0 = RX_MODE or 3-state1

1

0 = RX_MODE or 3-state

General power mode register PWRMODETable 39.

General power mode register PWRMODE - (address 13h) bit description

Bit

Symbol

7

0

Value

Description

0

-

6

0

5

0

4

POLLTIM_EN

S

polling timer enable bit. Initialization occurs on every(power-on) reset. Bit POLLTIM_EN is set to theinverse of pin RSTDIS. Therefore this pin controls
polling timer initial condition. 1 = polling initiallydisabled; see Table 40 and Table 41

3

DEV_MODE0device mode control bits; see Table 42

2

0

1

PD

1

power-down bit: logic 1 puts device into standby

mode where it consumes much less power. All
analog RX circuitry and the XTAL oscillator are
turned off. All dynamic digital activity is stopped
except SPI and polling timer, if enabled.[1]
0

RESET

0

reset bit: logic 1puts the device into power-on

state, the same state reached after powering up
the device. If set logic 1 with a Write command,
all other bits, simultaneously written to register
PWRMODE, are ignored as the register isforced to the power-on state.
[1]

Bit PD can also be set automatically at Power-on reset or setting bit RESET, watchdog timer timeout, or
receive state machine request. A logic 1 cannot be read because the SPI Read command causes theOL2311 to exit Power-down mode.

Table 40.
D4Function0polling timer off and no current is drawn

1polling timer on

Table 41.

OL2311

Product data sheet

POLLTIM_EN data functions

Polling timer status after master reset

Pin RSTDIS

Status after master reset

LOW

POLLTIM_EN = 1: polling timer is activated with the settings of register
POLLWUPTIME = 255 and EXTPOLLTIMRNG = 0.

HIGH

POLLTIM_EN = 0: polling timer off

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Table 42.

DEV_MODE[1:0] device mode control functions

D3

D2

Function00crystal oscillator or external clock buffer is enabled and after
crystal oscillator stabilization (if selected) the device is
supplied with the reference clock01

PLL controlled local oscillator (LO) enabled. LO power-up
procedure includes VCO sub-band calibration(unconditionally) and PLL lock-in detection

10

prepare and enable RX operation. LO enabled and after PLL
acquires lock, RX is switched on and enabled11reserved

8.2.1.11 Interrupt enable register IEN
Table 43.
Bit

SymbolValue

Description

7

IE_RX_RDY0

triggered if RX mode is successfully reached after
automatic start-up sequences issued [1]6

IE_EOF0

EOF is generated in data reception mode if an enabledsignal monitor detects an unsatisfactory RX signal
condition. This is the case when data reception mode isreached either automatically after a successful preamble
detection or upon receipt of a DATA RX command.

5

IE_PREA

0

triggered on every completion of a preamble detection
regardless of whether it was successful or not

4

IE_WUPS0

triggered on every completion of a wakeup search
regardless of whether it was successful or not

3

IE_POLTIM

0

triggered when a polling timer event takes place

2

IE_WATCHDOG 0

triggered when a watchdog overflow takes place1

IE_BROWNOUT 0

triggered on brown-out detection of the voltage regulators(undervoltage detection)

0

0

0

[1]

8.2.1.12

Interrupt enable register IEN - (address 14h) bit description

0

Issuing another RX command will not trigger this interrupt when the device is already in RX mode,
respectively. An interrupt is only generated when the ready state is reached.

Interrupt flag register IFLAG
The IFLAG bits indicate if an interrupt source is triggered since this register was last read.
The register bits are always set to logic 0 after being read.
Table 44.

OL2311

Product data sheet

Interrupt flag register IFLAG - (address 15h) bit description

Bit

SymbolValue

Description

7

IF_RX_RDY0

set after completion of automatic start-up sequences

6

IF_EOF

05

IF_PREA

0successful preamble detection (non-maskable)

4

IF_WUPS0

successful wakeup search (non-maskable)

3

IF_POLLTIM

0polling timer event (non-maskable)

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Highly integrated single-chip sub 1 GHz RF receiver

Table 44.

8.2.1.13

Bit

SymbolValue

Description

2

IF_WATCHDOG

0watchdog overflow

1

IF_BROWNOUT

0undervoltage detection

0

IF_POR1

first battery power-on reset (battery insertion detection).
Setting bit RESET also sets the IF_POR flag.

Polling timer control register POLLWUPTIME
Table 45.

8.2.1.14

Interrupt flag register IFLAG - (address 15h) bit description …continued

Polling timer control register POLLWUPTIME - (address 16h) bit description

Bit

SymbolValue

Description

7

POLLWUPTIME

1

sets polling timer wakeup time. Wakeup time iscalculated by:
T WUP =  POLLWUPTIME + 1 T WUPTICK

6

1

5

1

4

1

3

1

2

1

1

1

0

1

Polling action register POLLACTION
Table 46.

Polling action register POLLACTION - (address 17h) bit description

Bit

SymbolValue

Description

7

POLL_MODE

0defines the operating mode the device enters after apolling timer event, see Table 47

RX_FREQ

X

6
5

0

4

OL2311

Product data sheet

where TWUPTICK is either 1 ms or 16 ms depending on bit
EXTPOLLTIMRNG (extended polling timer range).

X

RX_FREQ[1:0] means the same as RX flags RA and RB(frequency selection)

3

RX_CMDX

bit RX_CMD means the same as RX flag RC. It allows achoice between a WUPS (logic 0) and a PRDA (logic 1)
command.

2

RX_GAINX

RX_GAIN[1:0] means the same as RX flags RE and RF(gain step/switch selection bits)

1

X

0

SET_RX_FLAGS X

defines whether the current contents of RX flag register
is used for the automatically initiated RX command (iflogic 0) or whether RX flags RA, RB, RC, RE and RF are
overwritten with the contents of RX_FREQ[1:0],
RX_CMD and RX_GAIN[1:0] settings of this register,
respectively, before the command is actually launched (iflogic 1). If the flags are overwritten, the RX flag RD is set
to logic 1 to make the sub-command either a WUPS or a
PRDA command.

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Highly integrated single-chip sub 1 GHz RF receiver

Table 47.

8.2.1.15

POLL_MODE[1:0] device mode control functions

D7

D6

Function

00after signalling the polling timer interrupt, which isunmaskable, the device remains in Power-down mode

01

after signalling the polling timer interrupt, which isunmaskable, the device leaves Power-down mode, whichturns the crystal oscillator or the external clock buffer on

10

device is fully powered up to RX mode. If the polling timer
interrupt is enabled, an interrupt occurs, either with thepolling timer event or when the receiver is ready1

1

device is fully powered up to RX mode. After RX settles, an
RX command is automatically initiated as configured by theremaining bits of this register. It is guaranteed that at least
one interrupt will occur in the command sequence.

Clock connection register CLOCKCON
Table 48.

Clock connection register CLOCKCON - (address 18h) bit description

Bit

SymbolValue

Description

7

MANUALPTCAL

0

manual start of polling timer calibration. Reading bit
MANUALPTCAL always yields zero. Manual calibration is
only executed if polling timer and crystal oscillator are
running. Otherwise the request is ignored.

6

PTCALRUNNINGS

status bit set when polling timer calibration is running

5

EXTPOLLTIMRNG

0extended polling timer range calculated
by: T WUPTICK = 1 + 15  EXTPOLLTIMRNG ms; see
Table 49

4

CLKSOURCESEL

0

3

0

2

1

1

EXT_CLK_BUF_EN 0

0

XODIS

Table 49.

EXTPOLLTIMRNG bit functions
Wakeup counter resolution
TWUPTICK

Selectable wakeup times
TWUP

0

1 ms

1 ms to 256 ms

1

16 ms

16 ms to 4096 ms

Table 50.

Product data sheet

external clock buffer enable bit is used to turn on clock
buffer for external clock. The effect of this bit also depends
on bit XODIS; see Table 51

0

EXTPOLLTIMRNG

OL2311clock selection for selected port pin; see Table 50

CLKSOURCESEL bit functions

D4

D3

D2

Port pin000reference clock (16 MHz)

0

0

1

reference clock / 2 (8 MHz)

0

1

0

reference clock / 4 (4 MHz)

0

1

1

reference clock / 8 (2 MHz)

1

0

0

4  chip clock

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Highly integrated single-chip sub 1 GHz RF receiver

Table 50.

CLKSOURCESEL bit functions …continued

D4

D3

D2

Port pin

10

1

2  chip clock

1

1

0

chip clock

1

1

1

bit clock

Table 51.

8.2.1.16

EXT_CLK_BUF_EN / XODIS bit functions

D1

D0

Function00crystal oscillator enabled. Digital reference clock disabledduring oscillator start-up.

0

1

crystal oscillator and external clock buffer disabled

10crystal oscillator enabled. Digital reference clock permanently
enabled and during oscillator start-up.

1

1

crystal oscillator disabled and external clock buffer enabled.
Digital reference clock permanently enabled.

Device status register DEVSTATUS
Table 52.
Bit

Symbol

Product data sheet

Value

Description

7

0

0

-

6

RFU

0

reserved

5

RFU

0

reserved

4

LO_PWR_RDY

0logic 1 indicates VCO and PLL regulators are delivering
power to these LO sections

3

RX_RDY

S

status bit: automated RX mode preparation sequence
ready, device ready for RX

2

RFU

S

reserved1

LO_RDY

S

status bit: VCO running, PLL settled and locked

0

REFCLK_RDY

S

status bit: XTAL oscillator stable or external clock available.
External clock stability is not checked by the device.

Table 53.

OL2311

Device status register DEVSTATUS - (address 19h) bit description

Register RFU - (address 20h) bit description

Bit

SymbolValue

Description

7

DOUBLE_SD_
RESULT0

configures the Sigma delta fractional-N modulation; see
Section 7.14.7 “Delta-sigma modulator for fractional-N
synthesis” on page 29 for details

6

RFU

0

reserved

5

RFU

0

reserved

4

RFU

0

reserved

3

RFU

0

reserved

2

RFU

0

reserved

1

RFU

0

reserved

0

RFU

0

reserved

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Highly integrated single-chip sub 1 GHz RF receiver

Table 54.

8.2.1.17

RX frequency offset

RF_LO_DIVDOUBLE_SD_
RESULT

Offset value

Frequency
resolution (Hz)RX frequency
offset

0

0

614

488.3

299.805 kHz

0

1

307

976.6

1

0

1228

244.1

1

1

614

488.3

Receiver gain control register RXGAIN
Gain configuration of the receiver for Hi gain and LO gain mode. If automatic gain
switching is activated, the receiver configuration will be automatically changed from HI to
LO gain when a certain signal level is exceeded.
Table 55.

Receiver gain control register RXGAIN - (address 21h) bit description

Bit

SymbolValue

Description

7

RX_HI_GAIN

1

sets the desired gain for high gain mode including both
RF front-end gain and channel filter gain settings

6

1

5

1

4

1

3

8.2.1.18

Product data sheet

0

2

0

1

0

0

0

sets the desired gain for low gain mode including both
RF front-end gain and channel filter gain settings

Channel filter bandwidth and RSSI filter settings register RXBW
Table 56.

Channel filter bandwidth and RSSI filter settings register RXBW - (address 22h)
bit description

Bit

Symbol7

DEMOD_ASK X

switches the digital baseband filter input andbaseband signal processing chain to the ASK
demodulator output

6

CF_BW

channel filter bandwidth selection bits, see Table 57

Value

Description

0

5

0

4

0

3
2

RSSI_FILTER X
_FC
X

1

X

0

X

Table 57.

OL2311

RX_LO_GAIN

RSSI corner frequency selection bits

CF_BW bit functions

D6

D5

D4

Bandwidth (kHz)

0

0

0

300

0

0

1

200

0

1

0

150

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Highly integrated single-chip sub 1 GHz RF receiver

Table 57.

8.2.1.19

D6

D5

D4

Bandwidth (kHz)

0

1

1

100

1

0

0

75

1

0

1

50

Register GAINSTEPTable 58.
Bit

SymbolValue

Description

0

0

-

6

RSSI_GAIN_STEP_ADJX

the receiver automatically adds this value to thefiltered and properly scaled RSSI reading whenever it
is in low gain mode to compensate for the difference(high gain minus low gain). This seamlessly extends
the RSSI’s dynamic range by switching the RX chain
gain.

X

4

X

3

X

2

X

1

X

0

X

Register HIGAINLIM
Table 59.

Register HIGAINLIM - (address 24h) bit description

Bit

SymbolValue

Description

7

HI_GAIN_LIMIT

0

8-bit gain switching threshold value [1]

6

0

5

0

4

0

3

X

2

X

1

X

0

X

[1]

8.2.1.21

Register GAINSTEP - (address 23h) bit description

75

8.2.1.20

CF_BW bit functions …continued

If the RSSI reading exceeds this value during a wakeup search, the RX gain can be switched from
RX_HI_GAIN to RX_LO_GAIN automatically provided it is programmed to do so (flags E, F = 01b).

Registers UPPERRSSITH and LOWERRSSITH
Registers UPPERRSSITH (address 25h) and LOWERRSSITH (address 26h) contain the
8-bit upper and lower RSSI threshold level respectively. This value is compared against
the digitised RSSI value in the RSSI level classification unit.

8.2.1.22

Register RXBBCON
Table 60.
Bit

SymbolValue

Description

7

DEGLITCHER_
WINDOW_LEN

X
X

control the deglitcher’s hold-off time to suppress multiple
signal transitions when a noisy baseband signal crosses
the slicer threshold, see Table 626OL2311

Product data sheet

Register RXBBCON - (address 27h) bit description

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Table 60.
Bit

SymbolValue

Description

5

BASEBAND_SETTL_TIME

X

adjusts the baseband settling delay. Delay is the time
between the declared valid IF signal and the declared valid
baseband signal. The delay is
2  (1 + BASEBAND_SETTL_TIME)  chip duration.
Correct adjustment of this delay is essential if operating a
wakeup search in pessimistic mode, because signal
measurement and classification must not be started until
the whole RX chain (including the channel and baseband
filters) are settled. The dominant settling time is usually the
baseband filter and must be taken into accountBASEBAND_FILTER_FC

X

4

3
2

X

baseband digital filter cut-off frequency

X

1

X

0

X

Table 61.

8.2.1.23

Register RXBBCON - (address 27h) bit description …continued

DEGLITCHER_WINDOW_LEN bit functions

D7

D6

Deglitcher lock duration

0

0

0

0

1

2 / 16 of chip width1

0

3 / 16 of chip width

1

1

4 / 16 of chip width

Register UMODAMPTH

Table 62.

Register UMODAMPTH - (address 28h) bit description

Bit

SymbolValue

Description

7

UPPER_MODAMP_
TH_EXP

X
X

UMODAMPTH 
UPPER_MODAMP_TH_EXP = max  0, log 2  ---------------------------------------- 


7.75



6
5

X

4

X

3
2

UPPER_MODAMP_
TH_MANT

X
X

1

X

0

X

UMODAMPTH
UPPER_MODAMP_TH_MANT = 0.5 + -----------------------------------------------------------UPPER_MODAMP_TH_EXP
2

Register UMODAMPTH contains the upper modulation amplitude measurement thresholdlevel (modulation amplitude classification unit). In FSK mode one increment corresponds
to approximately 6.2 Hz when bit LARGE_FM_DEM_RANGE is logic 0 and approximately
18.6 Hz when bit LARGE_FM_DEM_RANGE is logic 1. In ASK mode one increment
corresponds to approximately 1.5 dB/512 = 0.00293 dB.
T
1 + --------100
In FSK mode: UMODAMPTH = F DEV  --------------------------------------------------------------------------------------------------------------------------  32256
200 kHz   1 + 2  LARGE_FM_DEM_RANGE 

where FDEV = nominal peak-to-peak frequency deviation (Hz), T = tolerance (%).

OL2311

Product data sheet

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OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiverT
1 + --------100
In ASK mode: UMODAMPTH = ASK MOD  ------------------  512 where ASKMOD = ASK
1.5
modulation amplitude ratio (dB), T = tolerance (%).
Remark: The specified amplitude is peak-to-peak.
8.2.1.24

Register LMODAMPTH
Register LMODAMPTH (address 29h) contains the lower modulation amplitude
measurement threshold level (modulation amplitude classification unit). It configures thethreshold level similar to register UMODAMPTH.
T
1 + --------100
In FSK mode: LMODAMPTH = FDEV  --------------------------------------------------------------------------------------------------------------------------  32256
200 kHz   1 + 2  LARGE_FM_DEM_RANGE 

where FDEV = nominal peak-to-peak frequency deviation (Hz), T = tolerance (%).
T
1 + --------100
In ASK mode: LMODAMPTH = ASK MOD  ------------------  512 where ASKMOD = ASK
1.5
modulation amplitude ratio (dB), T = tolerance (%).
Remark: The specified amplitude is peak-to-peak.
8.2.1.25

Register EMODAMPTH
Table 63.

Register EMODAMPTH - (address 2Ah) bit description

Bit

SymbolValue

Description

7

EDGE_MODAMP_TH

0expected peak modulation value; calculation of
EDGE_MODAMP_TH; see register
UMODAMPTH

6

0

5

0

4

0

3

0

2

0

1

0

0

0

The EMODAMPTH register contains the expected peak modulation value used as theamplitude reference value for the edge slicer. It configures the threshold level similar toregister UMODAMPTH.
F
200 kHz   1 + 2  LARGE_FM_DEM_RANGE DEV-  32256
In FSK mode: EMODAMPTH = F DEV  -------------------------------------------------------------------------------------------------------------------------

where FDEV = nominal peak-to-peak frequency deviation (Hz).
ASK MOD
In ASK mode: EMODAMPTH = ----------------------  512 where ASKMOD = ASK modulation3
amplitude ratio (dB).
Remark: The specified amplitude is peak.

OL2311

Product data sheet

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Highly integrated single-chip sub 1 GHz RF receiver

8.2.1.26

Register RXDCON0
Table 64.

Register RXDCON0- (address 2Bh)

RegisterTable 65.

Nomenclature

RXDCON0

wakeup search settings

RXDCON1

preamble detection settings

RXDCON2

data reception settings

Register RXDCON0 - (address 2Bh) bit description

Bit

SymbolValue

Description

7

NUM_MODAMP_GAPS_W

X

the maximum expected duration, expressed as a number of chip widths,
between any two transitions minus 1, for example, if data stream ‘0000’
were Manchester encoded, the data stream at chip level appears as‘01010101’, a transition occurring every single chip width, therefore thevalue is logic 0.

6

5

X

SLICERSEL_W

X

4
3

X
SLICERINIT_SEL_W

2
1

data slicer selection for wakeup search phase, see Table 66

Xinitial initialization mode selection for selected slicer type for wakeup
search phase

X
INIT_ACQ_BITS_W

0

SLICERSEL_W bit functions

D5

D4

Function00edge slicer selected01level-sensitive slicer selected. The low-pass filter is not
activated, which means that the current slicer threshold isheld constant. Slicer threshold initialisation is accomplishedaccording to the setting of SLICERINITSEL_W[1:0]10level-sensitive slicer is selected and low-pass filter with atime-constant of 2 bits (4 chips) is activated continuously.
Slicer threshold initialisation is accomplished according to
the setting of SLICERINITSEL_W[1:0].

1

1level-sensitive slicer is selected and low-pass filter with atime-constant of 8 bits (16 chips) is activated continuously.
Slicer threshold initialisation is accomplished according to
the setting of SLICERINITSEL_W[1:0].

Table 67.

Product data sheet

2, 4 or 8-bit averaging on initial acquisition during wakeup search. The
initial acquisition updates slicer initialisation register and slicer thresholdafter every calculation of 2, 4, and 8 bits; see Table 68

X

Table 66.

OL2311X

SLICERINITSEL_W bit functions

D3

D2

Function

00slicer threshold is never initialized

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Table 67.
D3

D2

Function

01

slicer threshold is initialized with the content of register
SLICERINITH at the start of a RX event.

10

initial acquisition is achieved at the start of a RX event.
Slicer threshold is updated each time a new result isavailable from the initial acquisition.

1

1

same as setting 10 but the initial acquisition is
automatically restarted when a chip duration timeout
occursTable 68.

8.2.1.27

SLICERINITSEL_W bit functions …continued

INIT_ACQ_BITS_x bit functions

D1

D0

Number of bits used to calculate slicer
threshold

0

0

0

0

1

2

1

0

4

1

1

8

Register RXDCON1
Table 69.

Dynamic RX mode control register RXDCON1 - (address 2Ch) bit description

Bit

SymbolValue

Description[1]

7

X

6

NUM_MODAMP_GAPS_PX

number of expected modulation gaps during preamble
detection

5

SLICERSEL_P

X

data slicer selection for preamble detection phase432SLICERINIT_
SEL_PD1

INIT_ACQ_BITS_PD X

0

X

[1]

8.2.1.28

X2, 4 or 8-bit averaging on initial acquisition during
preamble detection and data reception. Initial acquisition
updates the slicer initialisation register and slicer
threshold after every calculation of 2, 4, and 8 bits.

Register RXDCON2
Dynamic RX mode control register RXDCON2 - (address 2Dh) bit description

Bit

SymbolValue

Description

7

X

6

NUM_MODAMP_GAPS_DX

number of expected modulation gaps during data
reception

5

SLICERSEL_D

X

data slicer selection for data reception phase4

Product data sheetX

initial initialization mode selection for selected slicer typefor preamble detection and data reception

See Table 64 for detailed explanation of control bits.

Table 70.

OL2311

X

X

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Table 70.

Dynamic RX mode control register RXDCON2 - (address 2Dh) bit description

Bit

SymbolValue

Description

3

CODINGRESTR_W

X

wakeup search, coding verification unit. Selection of thepermitted signal encoding, see Table 71

2

X

1

CODINGRESTR_P

X

coding restriction for preamble detection. If logic 0, no
restriction, both time intervals (1  chip and 2  chip
width) are accepted in an arbitrary order. If logic 1, bothtime intervals are accepted and the sequence ischecked for Manchester coding.

0

CODINGRESTR_D

X

coding restriction selection for data reception. If logic 0,
no restriction, both time intervals (1  chip and 2  chip
width) are accepted in an arbitrary order. If logic 1, bothtime intervals are accepted and the sequence ischecked for Manchester coding.

[1]

See Table 64 for detailed explanation of control bits.

Table 71.

CODINGRESTR_W bit function

D3

D2

Function00

no restriction, both time intervals (1  chip and 2  chip width)
are accepted in an arbitrary order

01

only short time interval (1  chip width) is accepted

10

only long time interval (2  chip width) is accepted11both time intervals are accepted and the sequence is checkedfor Manchester coding

8.2.2 Registers only visible in bank 0
8.2.2.1

Signal monitoring register SIGMON0
Table 72.

Signal monitoring registers SIGMON0, SIGMON1 and SIGMON2

Register
SIGMON0

wakeup search settings

SIGMON1

preamble detection settings

SIGMON2

data reception settings

Table 73.

Product data sheet

Signal monitoring control register SIGMON0 - (address 2Eh) bit description

Bit

SymbolValue

Description

7

WUPSMODE

X

wakeup search mode selection bit, see Table 74

6

SIGMON_EN_W

X

selection of signal monitor (signal signature recognitionunit) to be activated during wakeup search, see Table 75

5

X

4

X

3

X

2

X

1

X

0

OL2311

Nomenclature

0

0

-

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8.2.2.2

Table 74.

WUPSMODE bit functions

D7

Function0‘pessimistic’ wakeup search (also called mode 1): wakeup search ends when either oneof the enabled signal monitors signals a FAIL or all enabled signal monitors signal
PASS. In the first case the result of the wakeup search is FAIL; in the latter case it isPASS

1‘optimistic’ wakeup search (also called mode 2): wakeup search ends when either all
enabled signal monitors signal a PASS or the wakeup search timer expires. In the firstcase the result of the wakeup search is PASS; in the latter case it is FAIL.

Table 75.

SIGMON_EN_W bit functions

Bit

SymbolValue

Description (if set)

6

SIGMON_EN_W

X

enable chip timeout

5

X

enable chip timing

4

X

enable coding check3

Xenable baud-rate check2

Xenable RSSI level check1

X

enable modulation amplitude detection

Signal monitoring control register SIGMON1
Table 76.
Bit

SymbolValue

Description

7

EN_PREADET_TIMEOUTX

if logic 1, wakeup search timeout (WUPSTO) is also applied
to the preamble detection

6

SIGMON_EN_P

X

selection of signal monitor (signal signature recognition unit)
to be active during preamble detection, see Table 75

5

X

4

X

3

X

2

X

1

X

0

OL2311

Product data sheet

Signal monitoring control register SIGMON1 - (address 2Fh) bit description

ACCU_SIG_
FAILS_PX

logic 1 causes error indicators to be accumulated over theduration of preamble detection. Accumulator is reset at thestart of preamble detection and when the microcontroller
samples the status.

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8.2.2.3

Signal monitoring control register SIGMON2
Table 77.
Bit

Symbol

7

0

0

-

6

SIGMON_EN_D

X

selection of signal monitor (signal signature recognition unit)
to be active during data reception, see Table 75. If an
enabled signal monitor detects an abnormal condition, it isindicated by the IF_EOF (End-of-Frame flag).

Value

5

X

4

X

3

X

2

X

1

X

0

8.2.2.4

Signal monitoring control register SIGMON2 - (address 30h) bit description

ACCU_SIG_
FAILS_DX

logic 1 causes the error indicators to be accumulated overthe duration of data reception. The accumulator is reset atthe start of data reception and when the microcontroller
samples the status.

Register WUPSTO
Table 78.

Wakeup search timeout control register WUPSTO - (address 31h) bit description

Bit

Symbol7

WUPSTIMEOUTPRESC

6
5

Value

Description

Xprescaler for wakeup search timeout counter, see
Table 79X
WUPSTIMEOUT

X

4

X

3

X

2

X

1

X

0

X

Table 79.

8.2.2.5

Description

sets timeout to WUPSTIMEOUT[4:0]  TWUPSTO for
WUPSTIMEOUT[4:0] = 1 to 63. ValueWUPSTIMEOUT[4:0] = 0 disables the timeout timer
and sets timeout to infinity

WUPSTIMEOUTPRESC bit functions

D7

D6

Clock selection for wakeup search timeout timer TWUPSTO00

TBIT  2

0

1

TBIT  4

1

0

TBIT  16

1

1

TBIT  64

Register SLICERINITL
Register SLICERINITL (address 32h) bits are the slicer’s LSBs data threshold acquired
during intialisation. This register can be read to measure, for example, the RX frequency
offset or to save a correct threshold value for later use. The register can be written, forexample to restore a previously saved threshold value. Note that the register SLICERINIT
value is different from the actual threshold value.

8.2.2.6

Register SLICERINITH
Register SLICERINITH (address 33h) bits are the slicer’s MSBs data threshold acquired
during initialisation.

OL2311

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8.2.2.7

Register TIMINGCHK
Register TIMINGCHK (address 34h) configures the timing-check units.
Table 80.

Register TIMINGCHK - (address 34h) bit description

Bit

SymbolValue

Description

7

RFU

X

reserved

6

BROBSLENGTH

X

baud rate observation length setting: number of observed
bits configurable to 8, 16, 24 or 32 bits, see Table 81

5
4

X
SUMBITTMGERRTH

3X
SGLBITTMGERRTH

0

Table 81.

OL2311

Product data sheet

baud-rate checker threshold value for the sum of 8-bits
timing, see Table 82

X

2
1

X

X

single chip timing check threshold value. The timeinterval is accepted if its absolute value is below the limit.
Corresponds to timing errors which are less than 12.5 %,18.75 %, 25 % or 37.5% of a nominal chip width
respectively; see Table 83

X

BROBSLENGTH bit functions

D6

D5

Number of nominal bits to be considered for baud-rate
checker

0

0

8

0

1

16

1

0

24

1

1

32

Table 82.

SUMBITTMGERRTH bit functions

D4

D3

D2

Total timing error threshold Relative limit with respect
in TCHIP / 128 per 8 bits
to 8 nominal bits (%)

0

0

0

16

0.78

0

0

1

24

1.17

0

1

0

32

1.56

0

1

1

48

2.34

1

0

0

64

3.13

1

0

1

96

4.69

1

1

0

128

6.25

1

1

1

192

9.38

Table 83.

SGLBITTMGERRTH bit functions

D1

D0

Single chip timing error threshold in TCHIP / 128 per interval

0

0

16

0

1

24

1

0

32

1

1

48

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8.2.2.8

Register RXCON
Table 84.

Receive mode control register RXCON - (address 35h) bit description

Bit

SymbolValue

Description

7

STATAUTOSAMPLE

X

allows the software to control whether the status issampled when certain Read commands are issued.
Automatically set to logic 0 after a wakeup search andpreamble detection to save the result of this command

6

AUTOSAMPLEMANUAL

X

logic 1 prevents bit STATAUTOSAMPLE being set oncompletion of an RSSILEVEL read5

INV_RX_DATA

X

inverts the slicer output. If logic 0, in FSK mode thelower frequency is received as logic 1 and the higher
frequency is received as logic 0, whereas in ASK mode
the lower RF amplitude is received as logic 0 and thehigher RF amplitude is received as logic 1. Ifsynchronizing the Manchester decoder with a preamble
it samples the slicer output in the middle of the first halfof a bit.

4

CLOCK_RECOV_TC

X

set time-constant of clock recovery settling time, see
Table 85

3

X

2

RX_MANCHESTERX

if logic 1, data is Manchester decoded. Manchester
decoding is done by skipping every other chip clock
pulse. Which two possible pulse trains is omitted is set
after recognizing the programmed preamble during a
preamble detection. If data reception is initiated without
prior preamble detection, there is an equal chance thateither the right or the wrong clock pulse train issuppressed. In the first case, RX data is decoded
properly; in the latter case, RX data is inverted. The
MANCHESTER_COUNT in register EXTRXSTATUS
helps determines if data was received correctly orinverted.

1

RX_CLOCK_TRANSP

X

if logic 1, the clock output is always the chip clock
produced by the clock recovery PLL. If logic 0, the clock
output is always the bit clock which is equal to the chipclock in NRZ mode during data reception. During
wakeup search and preamble detection the clock isheld HIGH. The microcontroller must sample the RX
data line with the bit clock 1-to-0 transition.

0

RX_DATA_TRANSPX

If logic 1, the data output is taken from the deglitchedslicer result. If logic 0, the deglitched slicer result is
re-sampled with the bit clock’s rising edge. Therefore
the microcontroller must take the data with the bit clock
1-to-0 transition. During the wakeup search, the dataline is kept LOW, whereas during preamble detection itis held HIGH.

Table 85.

OL2311

Product data sheet

CLOCK_RECOV_TC bit functions

D4

D3

Maximum settling time
(chips)Maximum bit edge phase error(deg)Tolerance
(%)

0

0

3 (not recommended88

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Table 85.

8.2.2.9

CLOCK_RECOV_TC bit functions …continued

D4

D3

Maximum settling time
(chips)Maximum bit edge phase error(deg)Tolerance
(%)

0

1

7

15

4

1

0

15

30

2

1

1

31

60

1

Register RXFOLLOWUP
Table 86.

Receive mode follow-up control register RXFOLLOWUP - (address 36h) bit
description

Bit

SymbolValue

Description

7

PREA_FU_TF

1this bit is only effective:
when preamble detection (PRDA),
was initiated by the polling timer event,and preamble detection failed.
if this bit is logic 1:
device enters power-down.
if this bit is logic 0:
device stops, but stays on,a non-maskable interrupt occurs.

6

PREA_FU_CF

0

this bit is only effective:
when preamble detection (PRDA),
was initiated by command,and preamble detection failed.
if this bit is logic 1:
device enters power-down.
if this bit is logic 0:
device stops, but stays on.

5
4

WUPS_FU_TS

00these bits are only effective:
when wakeup search (WUPS),
was initiated by the polling timer event,and a WUPS signal was detected.
if these bits are logic 0X:
device stops, but stays on,a non-maskable interrupt occurs.
if these bits are logic 11:
device enters data receive mode.
a non-maskable interrupt occurs.
if these bits are logic 10:
device enters PRDA mode.

OL2311

Product data sheet

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Table 86.

Receive mode follow-up control register RXFOLLOWUP - (address 36h) bit
description …continued

Bit

SymbolValue

Description

3

WUPS_FU_TF

1this bit is only effective:
when wakeup search (WUPS),
was initiated by the polling timer event,and WUPS detection failed.
if this bit is logic 1:
device enters power-down.
if this bit is logic 0:
device stops, but stays on,a non-maskable interrupt occurs.

2

WUPS_FU_CS

100these bits are only effective:
when wakeup search (WUPS),
was initiated by command,and a WUPS signal was detected.
if these bits are logic 0X:
device stops, but stays on.
a non-maskable interrupt occurs.
if these bits are logic 11:
device enters data receive mode.
if these bits are logic 10:
device enters PRDA mode.

0

WUPS_FU_CF

0

this bit is only effective:
when wakeup search (WUPS),
was initiated by command,and WUPS detection failed.
if this bit is logic 1:
device enters power-down.
if this bit is logic 0:
device stops, but stays on.

OL2311

Product data sheet

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8.2.2.10

Register SIGMONSTATUS
Table 87. Status register SIGMONSTATUS - (address 37h) bit description
See Section 7.27 “Wakeup search logic” on page 63 for further details.
Bit

SymbolValue

Description

7

SIGMONSTATUS

S

if logic 1, the previous wakeup search or preamble detection
has failed. If logic 0, the command completed successfully.
Other status registers can be read to ascertain more
information if required.

6

Schip timeout

5

S

chip timing

4

S

coding3

Sbaud rate

2

S

RSSI level

1

S

modulation amplitude too high0Smodulation amplitude too low

8.2.2.11 Register SIGMONERROR
Table 88.
Bit

SymbolValue

Description

7

SIGMONERRORS

WUP timeout

6

S

chip timeout

5

S

chip timing

4

S

coding3

Sbaud rate

2

S

RSSI level

1

S

modulation amplitude too high0Smodulation amplitude too low

Table 89.

OL2311

Product data sheet

Status register SIGMONERROR - (address 38h) bit description

Signal monitor states set by registers SIGMONSTATUS and SIGMONERRORSIGMONSTATUS

SIGMONERROR

Signal monitor status

00decision not yet available

01

not possible

1

0

no error detected11

error detected

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8.2.2.12

Register RSSILEVEL
Table 90.

Register RSSI - (address 39h) bit description

Bit

Symbol7

RSSI_LEVEL

Value

Description0

result of RSSI conversion

6

0

5

0

4

0

3

X

2

X

1

X

0

X

Register RSSI contains the measured RSSI level at the completion of a wakeup search or
preamble detection, or at the moment the microcontroller recently triggered sampling theRX signal status.
8.2.2.13

Register PREACON
Table 91.

Preamble detection control register PREACON - (address 3Ah) bit description

Bit

SymbolValue

Description

7

RFU

0

reserved

6

PREA_TOLX

definition of allowed chip errors during preamble
detection, see Table 92

5
4

PREA_LEN

X

3

X

2

X

1

X

0

X

Table 92.

8.2.2.14

X

definition of pattern length of preamble to be detected.
Defined in chips, 1 to 31 is the length in chips; 0 = 32
chips.

PREA_TOL bit functions

D6

D5

Value

0

0

0

0

1

1

1

0

2

1

1

3

Register PREA0
Register PREA0 (address 3Bh) contains the 8 least-significant chips[7:0] of the preamble
pattern assuming the preamble MSB is sent first.

8.2.2.15

Register PREA1
Register PREA1 (address 3Ch) contains bits [15:8] of the preamble pattern.

8.2.2.16

Register PREA2
Register PREA2 (address 3Dh) contains bits [23:16] of the preamble pattern.

OL2311

Product data sheet

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8.2.2.17

Register PREA3
Register PREA3 (address 3Eh) contains bits [31:24] of the preamble pattern.

8.2.3 Registers only visible in bank 1
8.2.3.1

Register EXTRXSTATUS
Table 93.

Register EXTRXSTATUS - (address 2Eh) bit description

Bit

SymbolValue

Description

7

RX_HIGH_GAIN

S

logic 1 when high gain is selected, logic 0 when low gain is
selected (either automatically or by command)

6

LIVE_STATUS

S

logic 0 if the consistent set of status information is
automatically sampled on completion of wakeup search or
preamble detection. Logic 1 if the status was sampled by aRead operation from one of the 4 receiver status registers.

5

RX_CMDS

RX sub-command code during which, or on completion, thestatus is sampled. 00 = IDLE, 01 = WUPS, 10 = PREA and
11 = DATA.

432

8.2.3.2

S
MANCHESTER_
COUNT

S

0

S

Register CFRCCAL

Product data sheet

Register CFRCCAL - (address 2Fh) bit description

Bit

SymbolValue

Description

7

CF_IQ_CAL_RUNNINGS

status bit indicates running IQ calibration

6

CF_CAL_RUNNINGS

status bit indicates running RC calibration

5

0

0

-

4

0

0

-

3

CF_RC_CAL_RES

S

result of RC auto-calibration

2

S

1

S

0

S

Register CFIQCAL
Table 95.

OL2311

accumulated sum of RX data changes within a single chip
period, see Section 7.29 “RX data decoding” on page 68

S

1

Table 94.

8.2.3.3

S

IQ calibration register CFIQCAL - (address 30h) bit description

Bit

SymbolValue

Description

7

START_CF_IQ_CAL

0setting this bits starts the I/Q calibration sequence

6

CF_IQ_CALVAL

S

configuration for the best I/Q calibration. The result of a
triggered calibration sequence used in production test.
Configuration value must be initialized and stored by theexternal microcontroller for every individual device toachieve best image rejection performance.

5

0

4

0

3

0

2

0

1

0

0

0
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8.2.4 Expert registers
The expert registers enable the use of built-in functions for special application cases. It is
recommended that these settings are not changed.
8.2.4.1

Register EXPERT0
Table 96.

8.2.4.2

Register EXPERT0 - (address 31h) bit description

Bit

SymbolValue

Description

7

RED_VCO_SWING

0automatically set at lower band, if logic 1, VCO output
swing and LO power consumption are reduced. If logic 0,
VCO is running at highest drive level.

6

LARGE_PLL_RST_
DELAY

0

if logic 1, the PLL phase detector reset pulse width isincreased from 2.1 ns to 3.1 ns

5

FASTCFFILTSETTL

0

if logic 0, sufficient delay is provided until the channel filter
is declared settled after an input transient. Especially
important if a WUPS is performed in pessimistic mode.
Logic 1 reduces the delay allowing faster operation. A small
reduction of settling accuracy is acceptable for all other RX
commands.

4

PLL_ICP0

manual programming of PLL charge pump current. The
final charge pump current can be computed as a function of
the register setting using formula:

3

0

2

1

1

0

0

0

Register EXPERT1
Table 97.

Register EXPERT1 - (address 32h) bit description

Bit

Symbol7

XOSTARTUPDELAY

65

ASKRSTBBMID

4

RFU

Description

0

sets/influences delay after XO_READY detection.
Required for influencing automated startup sequences, see
Table 98

0

applies only when receiving ASK. If left at logic 0,
baseband filter resets to logic 0 (corresponding to minus
infinite dBm plus noise level) after an input transient. If
logic 1, baseband filter resets to the mid-point
corresponding to RSSI mid-range in dBm.

0reserved

1

2

DISFRAC0disables PLL fractional-N mode

1

LOCK_DET_TIME

0sets additional delay after ‘physical’ PLL lock detection.
Available delays are: 00 = 16 s, 01 = 32 s, 10 = 48 s, 11= 64 s, required for influencing automated startup
sequences.

0

Table 98.

Product data sheet

Value
1

3

OL2311

Icp = PLL_ICP 15 A
see Section 7.14.4 “Charge pump” on page 27.

1

XOSTARTUPDELAY bit functions

D7

D6

Delay time00

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Highly integrated single-chip sub 1 GHz RF receiver

Table 98.

8.2.4.3

XOSTARTUPDELAY bit functions …continued

D7

D6

Delay time01

512 s (default Power-on reset value)1

0768 s1

11024 sRegister EXPERT2
Table 99.

Register EXPERT2 - (address 33h) bit description

Bit

SymbolValue

Description

7

FM_DEM_IANDQ

0

if logic 1, I and Q limiter outputs are used for FSK
demodulation

6

LARGE_FM_DEM_
RANGE

0

logic 0 selects 200 kHz range (200 kHz to 400 kHz),
logic 1 selects 600 kHz range (0 Hz to 600 kHz). 0 Hz isa theoretical value limited to the channel filter AC
coupling lower corner frequency.

5

WIDE_AMPL_WINDOW

0

selects the number of samples window to be used foredge detection amplitude. Logic 0 selects 2 samples at
1 and +1 either side of center. Logic 1 selects 4
samples at 2, 1, +1 and +2 either side of center.

4

REDUCED_CHIP_TIMEOUT

0

selects timeout value for the chip timing verification
block. Logic 0 selects 3.5 chips, logic 1 selects 2.5
chips.

3

TWORSSIMSBITSSLOW 0

determines time taken to acquire the 2 MSBs in the
RSSI ADC. Logic 0 selects 3 clocks for bit 5 and 1 clock
for bit 4. Logic 1 selects 2 clocks for bit 5 and 2 clocks
for bit 4.

2

FASTRSSIFILTSETTL

0controls the RSSI filter settling time. Logic 0 selects 4
time-constants settling to within 2 % of the last step.
Logic 1 selects 2 time-constants settling to within 14 %of the last step.

1

CAPRSI1

allows the RSSI analog data low-pass filter to betrimmed changing the filter capacitor values which affectthe low-pass cut-off frequency, see Table 10100Table 100. FM demodulator configurations
D7

D6

Center frequency(kHz)

Input frequency
range (kHz)Maximum frequency Number ofdeviation (kHz)delay elements

0

0

300

200 to 400

100

40

0

1

300

0 to 600

300

13

1

0

600

200 to 400

100

20

1

1

600

0 to 600

300

7Table 101. CAPRSSI bit functions

OL2311

Product data sheet

D1

D0

Typical capacitor value (pF)

Time-constant (R = 300 k
typical)0000 (parasitics only)

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Highly integrated single-chip sub 1 GHz RF receiver

Table 101. CAPRSSI bit functions …continued

8.2.4.4

D1

D0

Typical capacitor value (pF)

Time-constant (R = 300 k
typical)012

0.6 s105

1.5 s1

1

12

4.8 sRegister EXPERT3
Table 102. Register EXPERT3 - (address 34h) bit description
Bit

SymbolValue

Description

7

0

0

-

6

0

0

-

5

0

0

-

4

0

0

-

3

TESTBUFFERCAL

0logic 1 turns the calibration path on. Required during
test buffer calibration

2

ALLOWREGSWITCH

0

controls the behavior of the REG_xxx_ON test bits. If
logic 0, the REG_xxx_ON bits are OR’d to the normal
control lines allowing unconditional turn-on of
selected regulators. If logic 1, the REG_xxx_ON bits
replace the normal control lines allowing full control(on and off) of the regulators.

1

LTDIQPHASECAL

0

if logic 0, all possible matching combinations in the
RX chain are attempted in order to achieve the best
image rejection. If logic 1, certain phase trimming
values are forbidden to eventually achieve a betteroverall performance over temperature.

0

DONOTDISTURBPTCAL

0

if logic 0, a polling timer calibration can run in parallelwith the PLL startup. If logic 1, the PLL startup, whenrequested, is delayed until the polling timer
calibration ends.

8.2.5 Test registers
The test register bits are initialized to logic 0 after power-up. Test registers must never beused in standard applications.
8.2.5.1

Register TEST0
Table 103. Register TEST0 - (address 35h) bit description
Bit

SymbolValue

Description

7

CF_MULTITONE_EN

0channel filter multi-tone testing

6

DIG_TEST_SEL

0selects digital test signals to be used in conjunction with
the P11C[3:0] and P12C[3:0] settings, see Section 8.2.1.7
on page 83 and Section 8.2.1.8 on page 84

5

0

4

0

3

OL2311

Product data sheet

RXD_DBG_SEL

0

2

0

1

0

0

0

selects digital test signals

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8.2.5.2

Register TEST1
Table 104. Register TEST1 - (address 36h) bit description
Bit

SymbolValue

Description

7

IQ_TEST_LV

0must be set if IF output signals test buffer is used at supply
voltages below 2.0 V

6

ANA_TEST_SEL

0selects analog test signal

5

0

4

0

3

REG_DIG_DIS

0

disables voltage regulator digital section

2

PLL_CTRL

0test and configures PLL

1
0

8.2.5.3

0
VCO_TEST_ON0enables VCO test

Register TEST2
Table 105. Register TEST2 - (address 37h) bit description
Bit

SymbolValue

Description

7

REG_VCO_ON0enables VCO voltage regulator

6

REG_PLL_ON

0enables PLL voltage regulator

5

REG_PA_ON0enables PA voltage regulator

4

FORCE_REG_VCO_RDY

0overrides VCO ready signal [1]3

FORCE_REG_PLL_RDY

0

overrides PLL ready signal [1]2

FORCE_REG_PA_RDY

0overrides PA ready signal [1]1

FORCE_LOCK_DETECT

0overrides PLL lock detect signal [1]0FORCE_XO_RDY

0overrides XO ready signal [1][1]

8.2.5.4

These bits override internal status information and enable automatic sequences to run even if thecorresponding status information indicates a failing block.

Register TEST3
Table 106. Register TEST3 - (address 38h) bit description

OL2311

Product data sheet

Bit

SymbolValue

Description

7

VCO_ON0enable VCO

6

PRESC_ON0enable prescaler

5

PFD_ON0enable PLL phase detector

4

CLK_PLL_ON

0enable PLL clock

3

RFU

0

reserved

2

RX_GAP_ON0enable bandgap reference, required for RX mode

1

RX_ON

0

enable receiver

0

RFU

0

reserved

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8.2.5.5

Register TEST4
Table 107. Register TEST4 - (address 39h) bit description
Bit

SymbolValue

Description

7

FORCE_CF_RC_CAL

0issues an RC auto-calibration on request

6

SKIP_CF_RC_CAL

0

prevents RC auto-calibration

5

CF_RC_ADJUSTCAL

0

enables verification of the channel filter RC
auto-calibration accuracy: time-constant reference
value is adjusted by this value; see Table 108

430
MAN_CF_RC_CALVAL

X

2

X

1

X

0

X

for manual entry of the RC auto-calibration value in
CF_RC_CAL_RES[3:0]Table 108. Time-constant reference settings for RC auto-calibration
CF_RC_ADJUST CAL

R variation (%)

D5

8.2.5.6

D4

0

0

0

0

1

+12.5

1

0

6.2

1

1

4.1

Register TEST5
Table 109. Register TEST5 - (address 3Ah) bit description

OL2311

Product data sheet

Bit

SymbolValue

Description

7

XO_IOFFS

0

sets programmable offset current for oscillator
control loop

6

0

5

0

4

XO_IOFFSET_SINK_EN

0

only active if XO_IOFFSET_EN is logic 1. If logic 1,
the bias source must sink the offset current
otherwise it is sourced

3

XO_IOFFSET_EN0enables crystal oscillator offset current: controls atest signal to control the bias current. Must be
logic 0 during normal crystal oscillator operation.

2

XO_KICK_DIS

0

disables crystal oscillator start-up kick: controls atest signal to disable the start-up kick after
power-on. Must be logic 0 during normal crystal
oscillator operation.

1

XO_DET_DIS

0

disables crystal oscillator detector: controls a test
signal to disable the detector. Must be logic 0
during normal crystal oscillator operation.

0

XO_BIAS_DIS

0

disables crystal oscillator bias circuit

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9. Limiting values
Table 110. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter

Conditions

Tstg

storage temperature

Tjjunction temperature

VIO

input/output voltage

+125

C

+95

C

+3.6

V

all other pins to GND

0.3

+2.8

V

-

4

mA

-

12.9

dBm

100

-

mA

2

-

kV

200

-

V

-

120

mW

Pi(max)maximum input powerRX[1][2]

latch-up current[3]

human body model
peak

[3]

machine model
peaktotal power dissipation

Ptot

55
0.3

maximum DC current for
I/O pins

electrostatic discharge
voltageUnit-

input/output current

VESD

Max

any VCC or I/O pin to GND

IIO

Ilu

Min

[1]

Only applies to pins which are connected to active devices in the application. According to the standard,
only relevant for VCC pins and digital I/Os.

[2]

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at these or any conditions otherthan those described in the Operating conditions and Electrical characteristics section of this specification
is not implied.

[3]This product includes circuitry specifically designed for the protection of its internal devices from thedamaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions betaken to avoid applying greater than the rated maximum.

10. Static characteristics
Table 111. Static characteristics
Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and
GND_PLL, VREG_VCO and GND_VCO. Capacitor of 47 nF // 270 pF connected between VREG_DIG and GND_DIG quartz
crystal NDK NX5032SA with CL = 12 pF, unless otherwise specified. The Edge Slicer was used for all relevantmeasurements.
SymbolParameter

Conditions

Min

Typ

Max

Unit

2.1

2.7

3.6

V

25

+25

+85

C

+25 C

-

0.5

1.6

A

+85 C

-

5

-

A

crystal oscillator on, digital module
active; PLL and PA off

-

900

1200

A

local oscillator supply current 315 MHz/434 MHz/868 MHz band;
LO and PLL on; PA off

-

5

7

mA

Current consumption
VCC

supply voltage

Tambambient temperature

ICC

supply current

ICC(LO)

OL2311

Product data sheet

power-down mode

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Table 111. Static characteristics …continued
Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and
GND_PLL, VREG_VCO and GND_VCO. Capacitor of 47 nF // 270 pF connected between VREG_DIG and GND_DIG quartz
crystal NDK NX5032SA with CL = 12 pF, unless otherwise specified. The Edge Slicer was used for all relevantmeasurements.
SymbolParameter

Conditions

ICC(RX)

receiver supply current

315 MHz/434 MHz/868 MHz band

Min

Typ

Max

Unit

+25 C

15.5

16.5

18

mA

25 C to +85 C

13.5

16.5

21.5

mA

Digital I/Os
VIH

HIGH-level input voltage

VCC = 2.1 V to 3.6 V

0.8VCC

-

VCC

V

VIL

LOW-level input voltage

VCC = 2.1 V to 3.6 V



-

0.4

V

IIH

HIGH-level input current

1

-

+1

A

IIL

LOW-level input current

VOH

HIGH-level output voltage

LOW-level output voltage

VOL

IOH

HIGH level output current

IOL

LOW level output current

fio

input/output frequency

[1]

1

-

+1

A

SPI pins (SCLK, SDIO and SDO);
VCC = 2.1 V to 3.6 V

0.7VCC-

VCC

V

VCC = 2.1 V to 3.6 V

0.8VCC-VCC

V

SPI pins (SCLK, SDIO and SDO);
VCC = 2.1 V to 3.6 V

0-

0.3VCCV

VCC = 2.1 V to 3.6 V

0-

0.2VCC

V

1

-

-

mA

1

-

-

mA

-

-

4

MHz

10 pF output load

Different biasing configurations are available in the receiver to trim performances (mainly sensitivity and linearity) versus power
consumption.

11. Dynamic characteristics
Table 112. Dynamic characteristics
Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and
GND_PLL, VREG_VCO and GND_VCO; capacitor of 47 nF // 270 pF connected between VREG_DIG and GND_DIG; quartz
crystal NDK NX5032SA with CL = 12 pF; unless otherwise specified. The Edge Slicer was used for all relevantmeasurements.
SymbolParameter

Conditions

Min

Typ

Max

Unit

fRF

RF frequency

315 MHz

300

315

320

MHz

434 MHz

415

434

450

MHz

868 MHz

865

868

870

MHz

915 MHz

902

915

928

MHz

315 MHz

-

150

-

Hz

434 MHz

-

200

-

Hz

868 MHz

-

400

-

Hz

915 MHz

-

415

-

Hz

Manchester (orNRZ) encoding

0.4

-

112

kchip/s-

0.1-

kchip/sfRF(step)

RF frequency step

Demodulation
fchip

chip ratefchip(step)

chip rate step

OL2311

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Table 112. Dynamic characteristics …continued
Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and
GND_PLL, VREG_VCO and GND_VCO; capacitor of 47 nF // 270 pF connected between VREG_DIG and GND_DIG; quartz
crystal NDK NX5032SA with CL = 12 pF; unless otherwise specified. The Edge Slicer was used for all relevantmeasurements.
SymbolParameter

Conditions

Min

Typ

Max

Unit

15.95

16

16.05

MHz

-

-

1

ms

Reference crystal oscillator
fxtal

crystal frequency[1]

tstartup(xtal)

crystal start-up time

Cdrv(xtal)

crystal driver capacitancedriver

-

1

-

pF

Rs(xtal)crystal series resistance10 C to +65 C;
2.1 V minimum;
quartz crystal NDK
NX5032SA;
CL = 12 pF

-

-

700



Vi(clk)clock input voltage

external clock
applied topin XTAL2
clock HIGH

-

1.8

-

V

clock LOW

-

0

-

V

[2]

PLL
BPLL(loop)

PLL loop bandwidth

3 dB closed loop at
868 MHz

[3]

-

150

-

kHz

tcal(VCO)

VCO calibration time

auto-calibration

[4]

-

110

-

s

[4]

-

120

200

s

at 868 MHz[5]-66 to j94-



at 434 MHz[5]-

125 to j139 -

at 315 MHz[5]-157 to j138 -



50

-

300

kHz

-

250

350

s

-

7

-

dB

tlock(PLL)

PLL lock time

Receiver section
Zi

input impedanceBbandwidthchannel filter[6]

tstartup(PLL)RX

receiver PLL start-up timefrom PLL start-up to
RX ready[4]

NF

noise figure

cascaded; maximum
front-end gain

OL2311

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Table 112. Dynamic characteristics …continued
Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and
GND_PLL, VREG_VCO and GND_VCO; capacitor of 47 nF // 270 pF connected between VREG_DIG and GND_DIG; quartz
crystal NDK NX5032SA with CL = 12 pF; unless otherwise specified. The Edge Slicer was used for all relevantmeasurements.
SymbolParameter

Conditions

SRX

receiver sensitivity

BER  103; Eb/N0
of 9.8 dB maximum
front-end gain

OL2311

Product data sheet

Min

Typ

Max

Unit

Manchester
encoded data rate
= 2.4 kbit/s;
deviation =2.4 kHz; channel
filter B = 50 kHz

109

112

-

dBm

Manchester
encoded data rate
= 4.8kbit/s;
deviation =4.8 kHz; channel
filter B = 50 kHz

108

110

-

dBm

Manchester
encoded data rate
= 9.6 kbit/s;
deviation =15 kHz; channel
filter B = 75 kHz

106

109

-

dBm

Manchester
encoded data rate
= 20 kbit/s;
deviation =20 kHz; channel
filter B = 100 kHz

103

105

-

dBm

Manchester
encoded data rate
= 2.4 kbit/s;channel filter B =50 kHz; ASK
modulation with
50 % duty cycle
square wave;
on/off keying;mean output
power

-

118

-

dBm

Manchester
encoded data rate
= 4.8 kbit/s;channel filter B =50 kHz; ASK
modulation with
50 % duty-cycle
square wave;
on/off keying;mean output
power

-

117

-

dBm

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Table 112. Dynamic characteristics …continued
Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and
GND_PLL, VREG_VCO and GND_VCO; capacitor of 47 nF // 270 pF connected between VREG_DIG and GND_DIG; quartz
crystal NDK NX5032SA with CL = 12 pF; unless otherwise specified. The Edge Slicer was used for all relevantmeasurements.
SymbolParameter

Conditions

Min

Typ

Max

Unit

ch

channel rejection

co-channel; using
Edge Slicer

-

11

-

dB

channel spacing =channelbandwidth

10

-

-

dB

 2 channels
separation

30

-

-

dB

wanted 3 dB above
the sensitivity level,
CW jammer, BER 
102OL2311

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Table 112. Dynamic characteristics …continued
Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and
GND_PLL, VREG_VCO and GND_VCO; capacitor of 47 nF // 270 pF connected between VREG_DIG and GND_DIG; quartz
crystal NDK NX5032SA with CL = 12 pF; unless otherwise specified. The Edge Slicer was used for all relevantmeasurements.
SymbolParametersup(f)image

image frequency suppression

Conditions
with calibration,
315 MHz and
434 MHz band withtrimming at RT andnominal voltage;
FSK modulation;
Manchester encode
data rate = 2.4 kbit/schannel filter B =50 kHz[7]

with calibration,
315 MHz and
434 MHz band withtrimming at RT andnominal voltage;
FSK modulation;
Manchester encode
data rate = 20 kbit/schannel filter B =300 kHzwith calibration,
868 MHz band withtrimming at RT andnominal voltage;
FSK modulation;
Manchester encode
data rate = 2.4 kbit/schannel filter B =50 kHz[7]

with calibration,
868 MHz band withtrimming at RT andnominal voltage;
FSK modulation;
Manchester encode
data rate = 20 kbit/schannel filter B =300 kHz

OL2311

Product data sheet

Min

Typ

Max

Unit

-

30

-

dB

50

-

-

dB

45

-

-

dB

45

-

-

dB

40

-

-

dB

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Table 112. Dynamic characteristics …continued
Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and
GND_PLL, VREG_VCO and GND_VCO; capacitor of 47 nF // 270 pF connected between VREG_DIG and GND_DIG; quartz
crystal NDK NX5032SA with CL = 12 pF; unless otherwise specified. The Edge Slicer was used for all relevantmeasurements.
SymbolParameter

Conditions

Min

Typ

Max

Unit

ch(image)

image channel rejection

wanted 3 dB above
the sensitivity level;
CW jammer at
image frequency;
BER  102;calibration withexternal RF signal,
FSK modulation

[7]

-

22

-

dB

315 MHz and
434 MHz;Manchester
encoded data rate
= 2.4 kbit/s;channel filter B =50 kHz

[7]

40

-

-

dB

315 MHz and
434 MHz;Manchester
encoded data rate
= 20 kbit/s;channel filter B =300 kHz

[7]

30

-

-

dB

868 MHz;Manchester
encoded data rate
= 2.4 kbit/s;channel filter B =50 kHz

[7]

30

-

-

dB

868 MHz;Manchester
encoded data rate
= 20 kbit/s;channel filter B =300 kHz

[7]

25

-

-

dB

 1 MHz fromedge band

40

-

-

dB

 2 MHz fromedge band

50

-

-

dB

 5 MHz fromedge band

60

-

-

dB

 10 MHz fromedge band

60

-

-

dB

to mixer output;
front-end maximum
gain

-

36

-

dBm

oob

ICP1dB

out-of-band rejection

blocking signal

1 dB input compression point

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Table 112. Dynamic characteristics …continued
Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and
GND_PLL, VREG_VCO and GND_VCO; capacitor of 47 nF // 270 pF connected between VREG_DIG and GND_DIG; quartz
crystal NDK NX5032SA with CL = 12 pF; unless otherwise specified. The Edge Slicer was used for all relevantmeasurements.
SymbolParameter

Conditions

Min

Typ

Max

Unit

IP3

third-order intercept point+5 MHz and
10 MHz; to mixer
output; front-end
maximum gain

-

23

-

dBm

PL(lo)

local oscillator leakage power

at RX input; LO >
1 GHz

-

-

47

dBm

Psp(RX)

receiver spurious power

emission in RX
mode
9 kHz to 1 GHz

-

-

57

dBm

1 GHz to 4 GHz

-

-

47

dBm

-

80

-

dB

RSSI
RSSIrange(dyn) received signal strength indicator
dynamic range
RSSIacc(abs)absolute accuracy of received
signal strength indicator

input power
variation (in range of90 dBm) to achieve
nominal digital codeof 89 LSB for any
device under any
condition

[7]

-

12

-

dB

RSSI

received signal strength indicator input power
variation
variation (in range of90 dBm) for one
device over supply
and temperature

[7]

-

3

-

dB

GRSSI

RSSI gain

0.4

-

0.9

dB/LSB

RSSIminminimum received signal
strength indicator

-

110

100

dBm

linked to reference
sensitivity[1]Start-up time includes XOSTARUPDELAY = 256 s.

[2]Only for test purposes, and not to be used in the application.

[3]

On-chip loop filter: ICP value = 2.

[4]

Guaranteed by design.

[5]

Input resistance in series with reactance in high gain mode. These values are indicative, determine input impedance on an applicationbasis, and refer to the application note.

[6]

There are six bandwidth settings for 50 kHz, 75 kHz, 100 kHz, 150 kHz, 200 kHz and 300 kHz.

[7]

Values derived from characterization result.

OL2311

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 8 December 2011

© NXP B.V. 2011. All rights reserved.

120 of 133

xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x

100 nF

100 nF

100 nF

VCC_REGVCC_DIG

VCC_XOVCC_RF

VCC_IF

1 μF

GND

TEN

XTAL2

TEST1

RSTDIS

47 nF

TEST2
TEST3

22 nF

VREG_DIGSEN

OL2311

VREG_VCO

SDIO

VREG_PLL

antenna

22 nF

SCLK
P10/DATA
P11/INT
P12/CLOCK

100 kΩ

100 kΩOPTIONAL

Fig 46. Application diagram

001aan718

OL2311121 of 133© NXP B.V. 2011. All rights reserved.

The values for the matching circuit components must be finalized after test board layout.
All connections to GND must be separated.

ADDITIONAL FILTERIF REQUIRED

GND32

GND16

exposed die pad

100 kΩGND9

SPI/DATA

GND8

GND1

RF_IN

Highly integrated single-chip sub 1 GHz RF receiverRev. 1 — 8 December 2011

All information provided in this document is subject to legal disclaimers.

XTAL1

NXP Semiconductors

100 nF

12. Application information

OL2311

Product data sheet

100 nF

VDD

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

13. Package outline
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm

D

B

SOT617-3

A

terminal 1
index area

A
A1

E

detail X

C
e1
e
9

y1 C

C A B
C

v
w

1/2 e b

y

16

L
17

8

e

e2

Eh
1/2 e

24

1
terminal 1
index area

32

25
X

Dh
0

2.5
scale

Dimensions
Unit(1)
mm

5 mm

A(1)

A1

b

max
0.05 0.30
nom 0.85
min
0.00 0.18

c

D(1)

Dh

E(1)

Eh

5.1

3.75

5.1

3.75

4.9

3.45

4.9

3.45

0.2

e

e1

e2

L

v

w

y

0.1

0.05 0.05

y1

0.5
0.5

3.5

3.5

0.1

0.3

Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outlineversion
SOT617-3

References
IEC

JEDEC

JEITA

sot617-3_po

Europeanprojection

Issue date
11-06-14
11-06-21

MO-220

Fig 47. Package outline SOT617-3 (HVQFN32)
OL2311

Product data sheet

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Rev. 1 — 8 December 2011

© NXP B.V. 2011. All rights reserved.

122 of 133

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

14. Abbreviations
Table 113. Abbreviations

OL2311

Product data sheet

AcronymDescription

AM

Amplitude Modulation

ASK

Amplitude-Shift Keying

ADC

Analog-to-Digital Converter

BER

Bit Error Rate

CW

Continuous Wave

DAC

Digital-to-Analog Converter

EOF

End Of FileFM

Frequency Modulation

FRMP

FSK RaMPFSK

Frequency Shift Keying

GFSK

Gaussian Frequency Shift Keying

ICP

Input Compression Point

IF

Intermediate Frequency

ISM

Industrial, Scientific and Medical

LC

inductor Capacitor

LNA

Low-Noise Amplifier

LO

Local Oscillator

LSB

Least Significant Bit

MISO

Master In Slave Out

MOSI

Master Out Slave In

MSB

Most Significant Bit

NRZ

Not Return to ZeroOSROverSampling Ratio

PA

Power Amplifier

PAM

Power Amplifier Mode

PFD

Phase Frequency Detector

PLL

Phase-Locked Loop

POR

Power-On Reset

PRDA

PReamble detection followed by DAta reception

PREA

PREAmble

PRNG

Pseudo-Random Number Generator

RC

Resistor Capacitor

RF

Radio Frequency

RFU

Reserved for Future Use

RSSI

Residual Signal Strength Indicator

RT

Room TemperatureRX

Receiver

SAW

Surface Acoustic Wave

SFR

Special Function Register
All information provided in this document is subject to legal disclaimers.

Rev. 1 — 8 December 2011

© NXP B.V. 2011. All rights reserved.

123 of 133

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

Table 113. Abbreviations …continued

OL2311

Product data sheet

AcronymDescription

SPI

Serial Peripheral Interface

SRD

Short-Range Device

TX

Transmitter

VCO

Voltage-Controlled Oscillator

WUP

Wake UP

WUPS

Wake UP Search

XO

Crystal Oscillator

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 8 December 2011

© NXP B.V. 2011. All rights reserved.

124 of 133

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

15. Revision history
Table 114. Revision history
Document ID

Release date

Data sheet status

Change notice

Supersedes

OL2311 v.1

20111208

Product data sheet--

OL2311

Product data sheet

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Rev. 1 — 8 December 2011

© NXP B.V. 2011. All rights reserved.

125 of 133

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

16. Legal information
16.1 Data sheet status
Document status[1][2]Product status[3]Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product development.

Preliminary [short] data sheet

Qualification

This document contains data from the preliminary specification.

Product [short] data sheet

Production

This document contains the product specification.

[1]

Please consult the most recently issued document before initiating or completing a design.

[2]

The term ‘short data sheet’ is explained in section “Definitions”.

[3]

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions
Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences ofuse of such information.
Short data sheet — A short data sheet is an extract from a full data sheetwith the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed andfull information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, thefull data sheet shall prevail.
Product specification — The information and data provided in a Productdata sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors andcustomer have explicitly agreed otherwise in writing. In no event however,shall an agreement be valid in which the NXP Semiconductors product isdeemed to offer functions and qualities beyond those described in the
Product data sheet.

16.3 Disclaimers
Limited warranty and liability — Information in this document is believed tobe accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy orcompleteness of such information and shall have no liability for theconsequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordancewith the Terms and conditions of commercial sale of NXP Semiconductors.

malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications andtherefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer productdesign. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications andproducts planned, as well as for the planned application and use ofcustomer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with theirapplications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in thecustomer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications andthe products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or theCharacteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects toapplying the customer’s general terms and conditions with regard to thepurchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to makechanges to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted orconstrued as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents orother industrial or intellectual property rights.

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical orsafety-critical systems or equipment, nor in applications where failure or

Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.

OL2311

Product data sheet

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Rev. 1 — 8 December 2011

© NXP B.V. 2011. All rights reserved.

126 of 133

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of thisdocument, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use inautomotive applications to automotive specifications and standards, customer(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design anduse of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.

16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.

17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

OL2311

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 8 December 2011

© NXP B.V. 2011. All rights reserved.

127 of 133

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

18. Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 3. Blocks with regulated supplies . . . . . . . . . . . . .17
Table 4. Channel filter gain settings . . . . . . . . . . . . . . .36
Table 5. RX gain control . . . . . . . . . . . . . . . . . . . . . . . .37
Table 6. Receive command packet . . . . . . . . . . . . . . . .42
Table 7. Frequency selection (bits RA, RB) . . . . . . . . . .43
Table 8. Sub-command selection bits RC, RD . . . . . . .43
Table 9. Gain switch selection (bits RE, RF) . . . . . . . . .44
Table 10. RXDCON registers . . . . . . . . . . . . . . . . . . . . .47
Table 11. RX operating mode transitions . . . . . . . . . . . .48
Table 12. Overview of the signal signature recognition
unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 13. Overview of signal monitoring methods . . . . . .64
Table 14. Example 1: Using single byte reads . . . . . . . .66
Table 15. Example 2: Using read command
auto-increment address . . . . . . . . . . . . . . . . . .67
Table 16. FM demodulator configurations . . . . . . . . . . . .70
Table 17. BASEBAND_FILTER_FC definition . . . . . . . . .72
Table 18. Available RX debug signal vectors . . . . . . . . .73
Table 19. Register map table . . . . . . . . . . . . . . . . . . . . . .76
Table 20. Frequency control register FC0L (address 00h) bit description . . . . . . . . . . . . . .80
Table 21. Frequency control register FC0M (address 01h) bit description . . . . . . . . . . . . . .80
Table 22. Frequency control register FC0H (address 02h) bit description . . . . . . . . . . . . . .80
Table 23. VCO control register VCOCON (address OCh) bit description . . . . . . . . . . . . .81
Table 24. Local oscillator control register LOCON (address ODh) bit description . . . . . . . . . . . . .82
Table 25. Timing register TIMING1 - (address 0Fh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 26. Port control register PORTCON0 (address 10h) bit description . . . . . . . . . . . . . .83
Table 27. P10C port control data functions . . . . . . . . . . .83
Table 28. P11C port control data functions . . . . . . . . . . .83
Table 29. Test signal I . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Table 30. Test signal II . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Table 31. Port control register PORTCON1 (address 11h) bit description . . . . . . . . . . . . . .84
Table 32. P12C port control data functions . . . . . . . . . . .85
Table 33. Test signal III . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 34. Test signal IIII . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 35. P13C port control data functions . . . . . . . . . . .86
Table 36. Port control register PORTCON2 (address 12h) bit description . . . . . . . . . . . . . .86
Table 37. SEP_RX_OUT data functions . . . . . . . . . . . . .86

Table 38. P14C port control data functions . . . . . . . . . . . 87
Table 39. General power mode register PWRMODE (address 13h) bit description . . . . . . . . . . . . . . 87
Table 40. POLLTIM_EN data functions . . . . . . . . . . . . . . 87
Table 41. Polling timer status after master reset . . . . . . . 87
Table 42. DEV_MODE[1:0] device mode control
functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 43. Interrupt enable register IEN (address 14h) bit description . . . . . . . . . . . . . . 88
Table 44. Interrupt flag register IFLAG (address 15h) bit description . . . . . . . . . . . . . . 88
Table 45. Polling timer control register POLLWUPTIME (address 16h) bit description . . . . . . . . . . . . . . 89
Table 46. Polling action register POLLACTION (address 17h) bit description . . . . . . . . . . . . . . 89
Table 47. POLL_MODE[1:0] device mode control
functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 48. Clock connection register CLOCKCON (address 18h) bit description . . . . . . . . . . . . . . 90
Table 49. EXTPOLLTIMRNG bit functions . . . . . . . . . . . 90
Table 50. CLKSOURCESEL bit functions . . . . . . . . . . . . 90
Table 51. EXT_CLK_BUF_EN / XODIS bit functions . . . 91
Table 52. Device status register DEVSTATUS (address 19h) bit description . . . . . . . . . . . . . . 91
Table 53. Register RFU - (address 20h) bit description . 91
Table 54. RX frequency offset . . . . . . . . . . . . . . . . . . . . 92
Table 55. Receiver gain control register RXGAIN (address 21h) bit description . . . . . . . . . . . . . . 92
Table 56. Channel filter bandwidth and RSSI filter settingsregister RXBW - (address 22h) bit description 92
Table 57. CF_BW bit functions . . . . . . . . . . . . . . . . . . . . 92
Table 58. Register GAINSTEP - (address 23h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 59. Register HIGAINLIM - (address 24h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 60. Register RXBBCON - (address 27h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 61. DEGLITCHER_WINDOW_LEN bit functions . 94
Table 62. Register UMODAMPTH - (address 28h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 63. Register EMODAMPTH - (address 2Ah)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 64. Register RXDCON0- (address 2Bh) . . . . . . . . 96
Table 65. Register RXDCON0 - (address 2Bh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 66. SLICERSEL_W bit functions . . . . . . . . . . . . . . 96
Table 67. SLICERINITSEL_W bit functions . . . . . . . . . . 96
Table 68. INIT_ACQ_BITS_x bit functions . . . . . . . . . . . 97

continued >>OL2311

Product data sheet

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Rev. 1 — 8 December 2011

© NXP B.V. 2011. All rights reserved.

128 of 133

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

Table 69. Dynamic RX mode control register RXDCON1 (address 2Ch) bit description . . . . . . . . . . . . . .97
Table 70. Dynamic RX mode control register RXDCON2 (address 2Dh) bit description . . . . . . . . . . . . . .97
Table 71. CODINGRESTR_W bit function . . . . . . . . . . .98
Table 72. Signal monitoring registers SIGMON0, SIGMON1and SIGMON2 . . . . . . . . . . . . . . . . . . . . . . . . .98
Table 73. Signal monitoring control register SIGMON0 (address 2Eh) bit description . . . . . . . . . . . . . .98
Table 74. WUPSMODE bit functions . . . . . . . . . . . . . . . .99
Table 75. SIGMON_EN_W bit functions . . . . . . . . . . . . .99
Table 76. Signal monitoring control register SIGMON1 (address 2Fh) bit description . . . . . . . . . . . . . .99
Table 77. Signal monitoring control register SIGMON2 (address 30h) bit description . . . . . . . . . . . . .100
Table 78. Wakeup search timeout control register WUPSTO- (address 31h) bit description . . . . . . . . . . . .100
Table 79. WUPSTIMEOUTPRESC bit functions . . . . . .100
Table 80. Register TIMINGCHK - (address 34h)
bit description . . . . . . . . . . . . . . . . . . . . . . . .101
Table 81. BROBSLENGTH bit functions . . . . . . . . . . . .101
Table 82. SUMBITTMGERRTH bit functions . . . . . . . . .101
Table 83. SGLBITTMGERRTH bit functions . . . . . . . . .101
Table 84. Receive mode control register RXCON (address 35h) bit description . . . . . . . . . . . . .102
Table 85. CLOCK_RECOV_TC bit functions . . . . . . . . .102
Table 86. Receive mode follow-up control register
RXFOLLOWUP - (address 36h)
bit description . . . . . . . . . . . . . . . . . . . . . . . .103
Table 87. Status register SIGMONSTATUS (address 37h) bit description . . . . . . . . . . . . .105
Table 88. Status register SIGMONERROR (address 38h) bit description . . . . . . . . . . . . .105
Table 89. Signal monitor states set by registers
SIGMONSTATUS and SIGMONERROR . . . .105
Table 90. Register RSSI - (address 39h) bit description 106
Table 91. Preamble detection control register
PREACON - (address 3Ah) bit description . .106
Table 92. PREA_TOL bit functions . . . . . . . . . . . . . . . .106
Table 93. Register EXTRXSTATUS - (address 2Eh)
bit description . . . . . . . . . . . . . . . . . . . . . . . .107
Table 94. Register CFRCCAL - (address 2Fh)
bit description . . . . . . . . . . . . . . . . . . . . . . . .107
Table 95. IQ calibration register CFIQCAL (address 30h) bit description . . . . . . . . . . . . .107
Table 96. Register EXPERT0 - (address 31h)
bit description . . . . . . . . . . . . . . . . . . . . . . . .108
Table 97. Register EXPERT1 - (address 32h)
bit description . . . . . . . . . . . . . . . . . . . . . . . .108
Table 98. XOSTARTUPDELAY bit functions . . . . . . . . .108
Table 99. Register EXPERT2 - (address 33h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 100. FM demodulator configurations . . . . . . . . . . 109
Table 101. CAPRSSI bit functions . . . . . . . . . . . . . . . . . 109
Table 102. Register EXPERT3 - (address 34h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 103. Register TEST0 - (address 35h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 104. Register TEST1 - (address 36h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 105. Register TEST2 - (address 37h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 106. Register TEST3 - (address 38h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 107. Register TEST4 - (address 39h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 108. Time-constant reference settings for RC
auto-calibration . . . . . . . . . . . . . . . . . . . . . . . 112
Table 109. Register TEST5 - (address 3Ah)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 110. Limiting values . . . . . . . . . . . . . . . . . . . . . . . 113
Table 111. Static characteristics . . . . . . . . . . . . . . . . . . . 113
Table 112. Dynamic characteristics . . . . . . . . . . . . . . . . 114
Table 113. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 114. Revision history . . . . . . . . . . . . . . . . . . . . . . 125

continued >>OL2311

Product data sheet

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Rev. 1 — 8 December 2011

© NXP B.V. 2011. All rights reserved.

129 of 133

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

19. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Fig 28.
Fig 29.
Fig 30.
Fig 31.
Fig 32.
Fig 33.
Fig 34.
Fig 35.
Fig 36.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .4
RX block diagram . . . . . . . . . . . . . . . . . . . . . . . . .7
Minimum port connections for RX mode . . . . . . . .8
Full port connections between host controller andthe OL2311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Write serial interface timing diagram . . . . . . . . . . 11
Read serial interface timing diagram . . . . . . . . . .12
Read serial interface timing diagram(SEP_SDO = 1) . . . . . . . . . . . . . . . . . . . . . . . . . .12
Write serial interface auto-increment timing
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Read serial interface auto-increment timing
diagram (SEP_SDO = 0) . . . . . . . . . . . . . . . . . . .14
Simplified state diagram. . . . . . . . . . . . . . . . . . . .16
Crystal oscillator circuit . . . . . . . . . . . . . . . . . . . .19
Diagram for crystal oscillator with clock
selection circuitry . . . . . . . . . . . . . . . . . . . . . . . . .21
Polling timer block diagram . . . . . . . . . . . . . . . . .24
Baud-rate generator. . . . . . . . . . . . . . . . . . . . . . .26
PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . .27
Computing the frequency divider control word. . .29
RX signal diagram . . . . . . . . . . . . . . . . . . . . . . . .33
Simulation examples for I/Q calibration withdifferent channel filter bandwidth settings . . . . . .36
20 dB difference between Hi-gain andLo-gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . .37
40 dB difference between Hi-gain andLo-gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Signal level plan. . . . . . . . . . . . . . . . . . . . . . . . . .39
Block diagram of RSSI. . . . . . . . . . . . . . . . . . . . .40
Preparation for RX mode . . . . . . . . . . . . . . . . . . .42
Example of a RX command (SEP_SDO = 0,
SEP_RX_OUT = 0) . . . . . . . . . . . . . . . . . . . . . . .45
Example of a RX command (SEP_SDO = 0,
SEP_RX_OUT = 1) . . . . . . . . . . . . . . . . . . . . . . .46
RSSI wakeup recognition . . . . . . . . . . . . . . . . . .50
RSSI threshold. . . . . . . . . . . . . . . . . . . . . . . . . . .50
Block diagram of the modulation amplitudeclassification . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Modulation amplitude measurement of a
Manchester coded signal . . . . . . . . . . . . . . . . . . .51
Modulation amplitude measurement (zoomed) . .52
Slicer block diagram . . . . . . . . . . . . . . . . . . . . . .54
Working principle of the edge slicer . . . . . . . . . . .54
Block schematic of chip timing verification block .59
State diagram of chip timing verification block . . .60
Code checker state diagram . . . . . . . . . . . . . . . .61

Fig 37. Wakeup search timeout timer schematic . . . . . . 63
Fig 38. Creation of PASS/FAIL information from one
signal monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Fig 39. Block diagram of wakeup search . . . . . . . . . . . . 65
Fig 40. Wakeup search registers. . . . . . . . . . . . . . . . . . . 66
Fig 41. XOR FM demodulator . . . . . . . . . . . . . . . . . . . . . 69
Fig 42. Baseband filter signal flow . . . . . . . . . . . . . . . . . 70
Fig 43. Step response of the baseband filter. . . . . . . . . . 71
Fig 44. Frequency response of the baseband filter. . . . . 71
Fig 45. Data transmission on the RX digital debug
interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Fig 46. Application diagram. . . . . . . . . . . . . . . . . . . . . . 121
Fig 47. Package outline SOT617-3 (HVQFN32) . . . . . . 122

continued >>OL2311

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 8 December 2011

© NXP B.V. 2011. All rights reserved.

130 of 133

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

20. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4Ordering information . . . . . . . . . . . . . . . . . . . . . 2
5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
6.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 5
7.1
General architecture description. . . . . . . . . . . . 5
7.1.1
Power management . . . . . . . . . . . . . . . . . . . . . 6
7.1.2
XTAL oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 6
7.1.3
Polling timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
7.1.4
VCO calibration . . . . . . . . . . . . . . . . . . . . . . . . 6
7.1.5
RX block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
7.1.6
Channel filter auto-calibration . . . . . . . . . . . . . . 7
7.1.7
I/Q calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7.1.8
Receive command . . . . . . . . . . . . . . . . . . . . . . 7
7.1.9
Signal signature recognition unit . . . . . . . . . . . 8
7.1.10Preamble detection. . . . . . . . . . . . . . . . . . . . . . 8
7.2
General operation . . . . . . . . . . . . . . . . . . . . . . . 8
7.3Interface description . . . . . . . . . . . . . . . . . . . . . 8
7.3.1
Port connections . . . . . . . . . . . . . . . . . . . . . . . . 8
7.4
Special ports . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.4.1
TEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.4.2
TEST1, TEST2 and TEST3 . . . . . . . . . . . . . . . 9
7.4.3
RSTDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.5
General purpose ports . . . . . . . . . . . . . . . . . . . 9
7.5.1
P10/DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.5.2
P11 and P12 . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.5.3
P14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.6
Serial configuration interface description . . . . 10
7.6.1
General SPI information . . . . . . . . . . . . . . . . . 10
7.6.2
SEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.6.3
SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.6.4
SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.6.5
General SFR access information . . . . . . . . . . 11
7.7
Write and read access to SFR . . . . . . . . . . . . 11
7.7.1
Write access to SFR . . . . . . . . . . . . . . . . . . . . 11
7.7.2
Read access to SFR. . . . . . . . . . . . . . . . . . . . 12
7.7.3
Separation of SDI and SDO line . . . . . . . . . . . 12
7.7.4
Read access to SFR with separate SDO line . 12
7.7.5
Read and write access to SFR with
auto-increment function . . . . . . . . . . . . . . . . . 13
7.7.6
Write access to SFR with auto-increment
function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.7.7
7.8
7.8.1
7.8.2
7.8.3
7.8.3.1
7.8.3.2
7.8.3.3
7.8.4
7.8.4.1
7.8.4.2
7.8.4.3
7.8.4.4
7.8.4.5
7.8.4.6
7.8.4.7
7.8.5
7.8.6
7.9
7.9.1
7.9.2
7.9.3
7.9.4
7.9.5
7.10
7.10.1
7.10.1.1
7.10.2
7.11
7.12
7.12.17.13
7.13.17.14
7.14.17.14.27.14.37.14.47.14.57.14.67.14.77.14.7.1
7.14.87.14.97.14.10
7.15

Read access to SFR with auto-increment
function . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device mode description . . . . . . . . . . . . . . . .
Automatic start-up procedures . . . . . . . . . . . .
General description . . . . . . . . . . . . . . . . . . . .
Reset and power mode register. . . . . . . . . . .
First power-on reset . . . . . . . . . . . . . . . . . . . .
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . .
Device mode states . . . . . . . . . . . . . . . . . . . .
Flow description . . . . . . . . . . . . . . . . . . . . . . .
Digital regulator start-up. . . . . . . . . . . . . . . . .
XTAL oscillator start-up . . . . . . . . . . . . . . . . .
PLL start-up . . . . . . . . . . . . . . . . . . . . . . . . . .
Turn on VCO . . . . . . . . . . . . . . . . . . . . . . . . .
Perform VCO calibration . . . . . . . . . . . . . . . .
Preparation for RX mode . . . . . . . . . . . . . . . .
Perform channel filter calibration . . . . . . . . . .
Changing device modes . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power supply and reset . . . . . . . . . . . . . . . . .
Voltage regulators operation . . . . . . . . . . . . .
Digital regulator . . . . . . . . . . . . . . . . . . . . . . .
PLL regulator . . . . . . . . . . . . . . . . . . . . . . . . .
VCO regulator . . . . . . . . . . . . . . . . . . . . . . . .
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . .
Main control and timing blocks. . . . . . . . . . . .
Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . .
Circuit description . . . . . . . . . . . . . . . . . . . . .
Oscillator control and control bits . . . . . . . . . .
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polling and wakeup timer. . . . . . . . . . . . . . . .
Actions at polling timer wakeup . . . . . . . . . . .
Baud-rate generator. . . . . . . . . . . . . . . . . . . .
Clock recovery for RX mode . . . . . . . . . . . . .
Phase-locked loop . . . . . . . . . . . . . . . . . . . . .
PLL building blocks . . . . . . . . . . . . . . . . . . . .
PLL and VCO regulators . . . . . . . . . . . . . . . .
General PLL operation. . . . . . . . . . . . . . . . . .
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . .
RF VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL loop bandwidth setting . . . . . . . . . . . . . .
Delta-sigma modulator for fractional-N
synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL operating frequency f0 . . . . . . . . . . . . . .
RX frequency offset . . . . . . . . . . . . . . . . . . . .
PLL lock detection . . . . . . . . . . . . . . . . . . . . .
VCO auto-calibration . . . . . . . . . . . . . . . . . . .
RX operation . . . . . . . . . . . . . . . . . . . . . . . . .

14
15
15
15
15
15
15
15
16
16
16
16
16
17
17
17
17
17
17
17
18
18
18
18
18
18
18
21
23
24
25
25
26
27
27
27
27
27
27
28
29
29
32
33
33
33

continued >>OL2311

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 8 December 2011

© NXP B.V. 2011. All rights reserved.

131 of 133

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

7.15.1
7.16
7.17
7.18
7.18.1
7.18.2
7.19
7.20
7.21
7.22
7.22.1
7.22.2
7.22.2.1
7.22.2.2
7.22.2.3
7.22.37.23
7.23.1
7.23.2
7.23.2.1
7.24
7.24.1
7.24.1.1
7.24.2
7.24.2.1
7.25
7.25.1
7.25.1.1
7.25.1.2
7.25.2
7.25.2.1
7.25.37.25.3.1
7.25.47.26
7.26.1
7.26.2
7.26.37.26.47.27
7.27.1
7.27.27.28
7.28.1
7.29
7.30
7.31
7.31.1
7.31.2
7.31.3General operation . . . . . . . . . . . . . . . . . . . . . . 34
LNA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Channel filter . . . . . . . . . . . . . . . . . . . . . . . . . 34
Channel filter auto-calibration . . . . . . . . . . . . . 35
Channel I/Q calibration . . . . . . . . . . . . . . . . . . 35
LNA and channel filter gain settings . . . . . . . . 36
Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Limiter block filter cut-off frequency . . . . . . . . 38
RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Dynamic range and operation . . . . . . . . . . . . 39
Resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
RSSI low-pass filtering . . . . . . . . . . . . . . . . . . 40
RSSI digital filtering . . . . . . . . . . . . . . . . . . . . 40
Low-level signal detection . . . . . . . . . . . . . . . 40
RSSI gain control . . . . . . . . . . . . . . . . . . . . . . 40
Receive mode. . . . . . . . . . . . . . . . . . . . . . . . . 41
Preparation for RX mode . . . . . . . . . . . . . . . . 41
Receive command . . . . . . . . . . . . . . . . . . . . . 42
Dynamic receiver configuration . . . . . . . . . . . 47
Signal signature recognition unit . . . . . . . . . . 48
RSSI level classification . . . . . . . . . . . . . . . . . 49
Functional block diagram . . . . . . . . . . . . . . . . 50
Modulation amplitude classification . . . . . . . . 50
Method to determine the modulation
amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Data classification. . . . . . . . . . . . . . . . . . . . . . 53
Data slicer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Number of corrupted bits in RX mode . . . . . . 53
Slicer description . . . . . . . . . . . . . . . . . . . . . . 53
Edge slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Edge slicer signal monitor setting . . . . . . . . . . 56
Level-sensitive slicer . . . . . . . . . . . . . . . . . . . 56
Level-sensitive slicer initial acquisition . . . . . . 57
Deglitcher and edge detector . . . . . . . . . . . . . 58
Timing classification block . . . . . . . . . . . . . . . 58
Chip timing verification . . . . . . . . . . . . . . . . . . 58
Code checker . . . . . . . . . . . . . . . . . . . . . . . . . 60
Baud-rate checker . . . . . . . . . . . . . . . . . . . . . 62
Timeout timer for the wakeup search . . . . . . . 63
Wakeup search logic . . . . . . . . . . . . . . . . . . . 63
Sampling the signal monitoring status . . . . . . 66
Evaluating the wakeup search result . . . . . . . 67
Data reception . . . . . . . . . . . . . . . . . . . . . . . . 67
Preamble detection. . . . . . . . . . . . . . . . . . . . . 67
RX data decoding . . . . . . . . . . . . . . . . . . . . . . 68
RX clock generation . . . . . . . . . . . . . . . . . . . . 68
RX digital signal processing . . . . . . . . . . . . . . 69
AM demodulator . . . . . . . . . . . . . . . . . . . . . . . 69
FM demodulator . . . . . . . . . . . . . . . . . . . . . . . 69
Baseband filter . . . . . . . . . . . . . . . . . . . . . . . . 70

7.31.3.1 RX baseband configuration . . . . . . . . . . . . . . 70
7.32
RX debug interface . . . . . . . . . . . . . . . . . . . . 72
8Special function registers . . . . . . . . . . . . . . . 75
8.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.2
Register descriptions . . . . . . . . . . . . . . . . . . . 80
8.2.1
Registers visible in both bank 0 and bank 1 . 80
8.2.1.1
Frequency control registers . . . . . . . . . . . . . . 80
8.2.1.2
VCO control register VCOCON . . . . . . . . . . . 81
8.2.1.3
Local oscillator control register LOCON. . . . . 82
8.2.1.4
Timing register TIMING0 . . . . . . . . . . . . . . . . 82
8.2.1.5
Timing register TIMING1 . . . . . . . . . . . . . . . . 82
8.2.1.6
Port control registers PORTCON0 to
PORTCON2 . . . . . . . . . . . . . . . . . . . . . . . . . . 83
8.2.1.7
Port control register PORTCON0. . . . . . . . . . 83
8.2.1.8
Port control register PORTCON1. . . . . . . . . . 84
8.2.1.9
Port control register PORTCON2. . . . . . . . . . 86
8.2.1.10 General power mode register PWRMODE . . 87
8.2.1.11 Interrupt enable register IEN . . . . . . . . . . . . . 88
8.2.1.12 Interrupt flag register IFLAG . . . . . . . . . . . . . 88
8.2.1.13 Polling timer control register POLLWUPTIME 89
8.2.1.14 Polling action register POLLACTION. . . . . . . 89
8.2.1.15 Clock connection register CLOCKCON . . . . . 90
8.2.1.16 Device status register DEVSTATUS . . . . . . . 91
8.2.1.17 Receiver gain control register RXGAIN . . . . . 92
8.2.1.18 Channel filter bandwidth and RSSI filter
settings register RXBW . . . . . . . . . . . . . . . . . 92
8.2.1.19 Register GAINSTEP . . . . . . . . . . . . . . . . . . . 93
8.2.1.20 Register HIGAINLIM . . . . . . . . . . . . . . . . . . . 93
8.2.1.21 Registers UPPERRSSITH and
LOWERRSSITH. . . . . . . . . . . . . . . . . . . . . . . 93
8.2.1.22 Register RXBBCON. . . . . . . . . . . . . . . . . . . . 93
8.2.1.23 Register UMODAMPTH . . . . . . . . . . . . . . . . . 94
8.2.1.24 Register LMODAMPTH . . . . . . . . . . . . . . . . . 95
8.2.1.25 Register EMODAMPTH . . . . . . . . . . . . . . . . . 95
8.2.1.26 Register RXDCON0 . . . . . . . . . . . . . . . . . . . . 96
8.2.1.27 Register RXDCON1 . . . . . . . . . . . . . . . . . . . . 97
8.2.1.28 Register RXDCON2 . . . . . . . . . . . . . . . . . . . . 97
8.2.2
Registers only visible in bank 0 . . . . . . . . . . . 98
8.2.2.1
Signal monitoring register SIGMON0. . . . . . . 98
8.2.2.2
Signal monitoring control register SIGMON1. 99
8.2.2.3
Signal monitoring control register SIGMON2 100
8.2.2.4
Register WUPSTO . . . . . . . . . . . . . . . . . . . . 100
8.2.2.5
Register SLICERINITL. . . . . . . . . . . . . . . . . 100
8.2.2.6
Register SLICERINITH . . . . . . . . . . . . . . . . 100
8.2.2.7
Register TIMINGCHK . . . . . . . . . . . . . . . . . 101
8.2.2.8
Register RXCON . . . . . . . . . . . . . . . . . . . . . 102
8.2.2.9
Register RXFOLLOWUP . . . . . . . . . . . . . . . 103
8.2.2.10 Register SIGMONSTATUS . . . . . . . . . . . . . 105
8.2.2.11 Register SIGMONERROR . . . . . . . . . . . . . . 105
8.2.2.12 Register RSSILEVEL . . . . . . . . . . . . . . . . . . 106

continued >>OL2311

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 8 December 2011

© NXP B.V. 2011. All rights reserved.

132 of 133

OL2311NXP Semiconductors

Highly integrated single-chip sub 1 GHz RF receiver

8.2.2.13 Register PREACON . . . . . . . . . . . . . . . . . . . 106
8.2.2.14 Register PREA0 . . . . . . . . . . . . . . . . . . . . . . 106
8.2.2.15 Register PREA1 . . . . . . . . . . . . . . . . . . . . . . 106
8.2.2.16 Register PREA2 . . . . . . . . . . . . . . . . . . . . . . 106
8.2.2.17 Register PREA3 . . . . . . . . . . . . . . . . . . . . . . 107
8.2.3
Registers only visible in bank 1 . . . . . . . . . . 107
8.2.3.1
Register EXTRXSTATUS . . . . . . . . . . . . . . . 107
8.2.3.2
Register CFRCCAL . . . . . . . . . . . . . . . . . . . 107
8.2.3.3
Register CFIQCAL . . . . . . . . . . . . . . . . . . . . 107
8.2.4
Expert registers . . . . . . . . . . . . . . . . . . . . . . 108
8.2.4.1
Register EXPERT0 . . . . . . . . . . . . . . . . . . . . 108
8.2.4.2
Register EXPERT1 . . . . . . . . . . . . . . . . . . . . 108
8.2.4.3
Register EXPERT2 . . . . . . . . . . . . . . . . . . . . 109
8.2.4.4
Register EXPERT3 . . . . . . . . . . . . . . . . . . . . 110
8.2.5
Test registers . . . . . . . . . . . . . . . . . . . . . . . . 110
8.2.5.1
Register TEST0 . . . . . . . . . . . . . . . . . . . . . . 110
8.2.5.2
Register TEST1 . . . . . . . . . . . . . . . . . . . . . . 111
8.2.5.3
Register TEST2 . . . . . . . . . . . . . . . . . . . . . . 111
8.2.5.4
Register TEST3 . . . . . . . . . . . . . . . . . . . . . . 111
8.2.5.5
Register TEST4 . . . . . . . . . . . . . . . . . . . . . . 112
8.2.5.6
Register TEST5 . . . . . . . . . . . . . . . . . . . . . . 112
9Limiting values. . . . . . . . . . . . . . . . . . . . . . . . 113
10
Static characteristics. . . . . . . . . . . . . . . . . . . 113
11
Dynamic characteristics . . . . . . . . . . . . . . . . 114
12
Application information. . . . . . . . . . . . . . . . . 121
13
Package outline . . . . . . . . . . . . . . . . . . . . . . . 122
14
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 123
15
Revision history . . . . . . . . . . . . . . . . . . . . . . . 125
16
Legal information. . . . . . . . . . . . . . . . . . . . . . 126
16.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . 126
16.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
16.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 126
16.4
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 127
17
Contact information. . . . . . . . . . . . . . . . . . . . 127
18
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
19
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.

© NXP B.V. 2011.

All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 December 2011
Document identifier: OL2311