SE050

Plug & Trust Secure Element
Rev. 3.8 — 18 October 2023
504938

Product data sheet

1 Introduction
The SE050 is a ready-to-use IoT secure element solution. It provides a root of trust at the IC level and it gives
an IoT system state-of-the-art, edge-to-cloud security capability right out of the box.
SE050 allows for securely storing and provisioning credentials and performing cryptographic operations forsecurity critical communication and control functions. SE050 is versatile in IoT security use cases such as
secure connection to public/private clouds, device-to-device authentication or protection of sensor data.
SE050 has an independent Common Criteria EAL 6+ security certification up to OS level and supports both
RSA & ECC asymmetric cryptographic algorithms with high key length and future proof ECC curves. The latest
security measures protect the IC even against sophisticated non-invasive and invasive attack scenarios.
The SE050 is a turnkey solution that comes with Java Card operating system and an applet optimized for
IoT security use cases pre-installed. This is complemented by a comprehensive product support package,enabling fast time to market & easy design-in with Plug & Trust middleware for host applications, easy to use
development kits, reference designs, and extensive documentation for product evaluation.
The SE050 is a product platform that comes in several pin-to-pin compatible product variants, see [4].
Additional information on the integration can be found in several application notes on the NXP website. See [3].
For additional information on guidelines for the usability of SE050 and the security recommendations for using
the module, see [5]To implement inclusive language, the terms "master/slave" has been replaced by "controller/target", following
the recommendation of MIPI.

1.1 SE050 use cases• Secure connection to public/private clouds, edge computing platforms, infrastructure• Device-to-device authentication• Secure data protection• Secure commissioning support• Secure CL/MIFARE/Wi-Fi interactions• Device ID for blockchain• Secure key storage• Secure provisioning of credentials• Ecosystem protection• Qi 1.3 wireless charging authentication• Matter ReadySE050NXP Semiconductors

Plug & Trust Secure Element

1.2 SE050 target applications• Smart Industry• Smart Home• Smart Cities• Smart Supply Chains
HOST MCU/MPU

SE050
SENSORACTUATOR

IoT APPLETPLUG AND TRUSTMWI2C

JCOPOS
I2C

14443

7816

SDA SCLSCL SDA LALBCLK IO2: SCL
RST IO:SDA

I2C target
SW I2C controller

NFC DEVICEREADER

14443
aaa-032990

Figure 1. SE050 solution block diagram

Note: SE050 is designed to be used as a part of an IoT system. It works as an auxiliary security device
attached to a host controller. The host controller communicates with SE050 through an I²C interface (with thehost controller being the I²C controller and the SE050 being the I²C target). Besides the mandatory connection
to the host controller, the SE050 device can optionally be connected to a sensor node or similar element
through a separate I²C interface. In this case, the SE050 device is the I²C controller and the sensor node theI²C target. Lastly, SE050 has a connection for a native contactless antenna, providing a wireless interface to an
external device like a smartphone.

1.3 SE050 naming convention
The following table explains the naming conventions of the commercial product name of the SE050 platform.
Every SE050 product gets assigned a commercial name, which includes application specific data.
The SE050 commercial names have the following format.
SE05yagddd/Zrrff
All letters are explained in Table 1 .
Table 1. SE050 commercial name format
Variable

Meaning

Valuesy

JCOP version

0aApplet Config

A
B
C
D
E
F

SE050

Product data sheet

Description
Configuration options with different key provisioning
options, see [4]All information provided in this document is subject to legal disclaimers.

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Table 1. SE050 commercial name format...continued
Variable

Meaning

ValuesDescriptiongTemperature range

1
2Operational ambient temperature
1 = -25 °C - 85 °C ,2 = -40 °C - 105 °C

ddd

Delivery TypeHQ1

HX2QFN20

Letters andnumbers

NXP internal code to identify individual configurations

Zrrff

2 Features and benefits
2.1 Key benefits• Plug & Trust for fast and easy design with complete product support package• Easy integration with different MCU & MPU platforms and OS´ (Linux, RTOS, Windows, Android, etc.)• Turnkey solution ideal for system-level security without the need to write security code
• Secure credential injection for root of trust at IC level• Secure, zero-touch connectivity to public & private clouds• Real end-to-end security, from sensor to cloud• Ready-to-use example code for each of the key use cases

2.2 Key features
The SE050 is based on NXP's Integral Security Architecture 3.0™ providing a secure and efficient protection
against various security threats. The efficiency of the security measures is proven by a Common Criteria EAL6+
certification.
The SE050 operates fully autonomously based on an integrated Javacard operating system and applet. Direct
memory access is possible by the fixed functionalities of the applet only. With that, the content from the memory
is fully isolated from the host system.
• Built on NXP Integral Security Architecture 3.0 ™
• CC EAL 6+ certified HW and OS as environment to run NXP IoT applications, supporting fully encrypted
communications and secured lifecycle management• FIPS 140-2 certified platform with Security Level 3 for OS and Applet, and Security Level 4 related to Physical
Security of the HW– Disclaimer: FIPS certification require a specific product type. For more information, refer to [4].
• Effective protection against advanced attacks, including Power Analysis and Fault Attacks of various kinds• Multiple logical and physical protection layers, including metal shielding, end-to-end encryption, memory
encryption, tamper detection• Support for RSA and ECC asymmetric cryptography algorithms, future proof curves and high key length, e.g.
Brainpool, Edwards and Montgomery curves• Support for AES and DES symmetric cryptographic algorithms for encryption and decryption• Support for AES Modes: CBC, EBC, CTR• HMAC, CMAC, SHA-1, SHA-224/256/384/512 operations• Various options for key derivation functions, including HKDF, MIFARE KDF, PRF (TLS-PSK)• Extended temperature range for industrial applications (-40 °C to 105 °C)• Small footprint HX2QFN20 package (3x3 mm)

SE050

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Plug & Trust Secure Element22• Standard physical interface I C target (High-speed mode, 3.4 Mbit/s), I C controller (Fast mode, 400 kbit/s).
Both can be active at the same time
• Dedicated CL wireless interface for IoT use cases simplifying configuration set-up, maintenance in the field
and late stage configuration• Secured user flash memory up to 50 kB for secure data or key storage• Support for SCP03 protocol (bus encryption and encrypted credential injection) to securely bind the host withthe secure element• TRNG compliant to NIST SP800-90B• DRBG compliant to NIST SP800-90A• Support for applet level secure messaging channels to allow end-to-end encrypted communication in multitenant ecosystems• In 2022 NXP launched a new generation of product variants, the SE050E platform. The SE050E platform
supports the following new features.
– AES Modes: CCM and GCM– GMAC– EC Curves for ECDH: Curve448• Matter Ready: SE050 provides the necessary cryptographic functions to support the upcoming Matterstandard for connecting smart home devices.
Note: The available features in each product vary according to the chosen variant. More details are available
on [4].

2.3 Features in detail
Table 2. Feature Overview
Categories

Subcategory

ValueStandards

Security certification

CC EAL6+ (HW+JCOP), FIPS 140-2 L3

JavaCard version

3.0.5

GlobalPlatform specification version

GP 2.3.1

ECC

ECDSA, ECDH, ECDHE, EdDSA

MAC

HMAC, secure HMAC, CMAC, GMAC

Hash

SHA-1, SHA-224, SHA-256, SHA-384,
SHA-512Key derivation

HKDF, PBKDF2, PRF (TLS-PSK),MIFARE-AES-KDF

AES

AES (128, 192, 256)

AES Modes

CBC, EBC, CTR, CCM

3DES

2K, 3K

RSA

RSA cipher for de-/encryption (up to4096 bit)ECC

ECC NIST (192 to 521 bit)

Cryptography

Crypto curves

[1]

[1]

, GCM

[1]

Brainpool (160 to 512 bit)
Twisted Edwards Ed25519 /Montgomery Curve25519
Koblitz (192 bit to 256 bit)[1]

Montgomery (Curve448) [Goldilocks]
SE050

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Plug & Trust Secure Element
Table 2. Feature Overview...continued
Categories

Subcategory

Value

User memory

50 kB

TRNG

NIST SP800-90B, AIS31DRBGNIST SP800-90A, AIS20
up to 100 Mio write cycles / 25 years

Memory reliability
Interfaces

Power saving modes
Temperature

Packaging[1]

2

I C Target

High-speed mode (3.4 Mbit/s)2

I C Controller

Fast Mode (400 kbit/s)

Contactless

ISO14443-A PICC

Power-Down (with state retention)< 500 µA

Deep Power-Down (no state retention)<5 µA

Standard-25 °C - 85 °C, see Naming
Conventions

Extended-40 - 105 °C, see Naming Conventions

Plastic QFN

3 x 3 mm (HX2QFN20)

New feature of the new generation of SE050 product family.

SE050

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Plug & Trust Secure Element

3 Functional description
3.1 Functional diagram
EdgeLock™ SE050 ENABLEMENTPLUG AND TRUST MIDDLEWARE
Dev Environments: Linux, Windows ®, macOS ®

Android, Linux, FreeRTOS, Zephyr
PREINTEGRATIONTO MAINOS AND
MCU, MPU

USE CASE BASED EXAMPLE CODES, pyCLI TOOLEDGELOCK
2GO AGENT

Arm
mbed
TLS

OpenSSLPKCS11Arm
PSA
CryptoAPI

Matter

Qi 1.3Auth.

Android
KeyMaster

TPM-TSSOPC-UAAPIEDGELOCK SE050
loT APPLETJAVA CARD OPERATING SYSTEM
HARDWARE
aaa-034211

Figure 2. SE050 functional diagram
2

The SE050 uses I C as communication interface. Section 4 gives more details. The SE050 commands are2
wrapped using the Smartcard T=1 over I C (T=1o I2C) protocol. The detailed documentation of the SE050
commands (see [3]) and T=1 over I2C protocol encapsulation is available on [1].
2

In order to simplify the product usage a host library which abstracts for SE050 commands and T=1 over I C
protocol encapsulation is provided. The host library supporting various platforms is available for download
including complete source code on the SE050 website.
SE050 IoT applet features a generic file system capable of securely storing secure objects and associatedprivilege management. All objects can either be stored in persistent memory or in RAM with the capability tosecurely export and import them to be stored in an externally provided storage. All secure objects feature basic
file operations such as write, read, delete and update.

3.1.1 Random number generator
The SE050 IoT Applet provides random numbers using an AIS20 compliant pseudo random number generator(PRNG) with class DRG.4 generator initialized by a TRNG compliant to AIS31 class PTG.2. The PRNG is
implemented according to NIST SP800-90Arev1.
DRG.3 functionality is a subset of DRG.4, therefore the TOE is also compliant to DRG.3.

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3.1.2 Supported secure object types
A secure object is an entry in the file system of SE050. Each secure object has certain features and capabilities.
The following secure object types are available (for more details on the objects refer to [3]):• Symmetric Key (AES, 3DES)• ECC Key• RSA Key• HMAC Key• Binary File
• User ID• Counter• Hash-Extend register

3.1.3 Access control
Each secure object can be linked to object specific access control policies. An access control policy associatesa user identified by an authentication with a set of privileges such as read, write, …
To scale the functionality into a broad range of ecosystems, a set of different authentication options is provided:• User-ID based authentication• Symmetric key based authentication with secure messaging• Asymmetric key based authentication with secure messaging
At creation of a secure object, an optional set of policies is associated with that secure object. Each policy
assigns a set of allowed operations on that object to an authentication object.

3.1.4 Sessions and multi-threading
The SE050 IoT applet is prepared for ecosystems where multi-threading and multi-tenant use cases areneeded on APDU level. To enable that, the applet supports 2 simultaneous sessions that can span full secure
messaging sessions, self-authenticated APDUs for tenants not requiring long-lasting sessions and on top one
default session for single tenant use cases .

3.1.5 Attestation and trust provisioning
SE050 applet comes with a set of trust provisioned root credentials allowing the owner of the device to securely
attest all generated secure keys. Next to that, a customer has the possibility to define own attestation keys.
Attestation certificates signed by an attestation CA are included in certain SE050 configurations as documented
in [4].

3.1.6 Application support
For specific ecosystems, SE050 IoT applet has built-in crypto features to simplify the deployment of specific use
cases such as• MIFARE SAM functionality• Wi-Fi password protection• ECC-Key and RSA-Key based cloud connectivity
2• Secure Sensor readout using I C controller• Remote attestation and trust provisioning• Platform Configuration Registers
SE050

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3.2 Credential Storage & Memory
Within SE050, all credentials and secure objects are stored inside a dynamic file structure. At creation, a user
has to associate a file identifier with the object created. This identifier is then used in subsequent operations toaccess the object. The number of objects that can be allocated is only limited by the available memory in thesystem. After usage, objects can be deleted and the associated memory is freed up again.
There is also the possibility to create transient objects. Transient objects have an object descriptor stored in
non-volatile memory, but the object content is stored in RAM. Together with the import/export functionality ofSE050, transient objects can be used securely store secret keys in a remote memory system.

3.3 Preprovisioned "Ease of Use" configurations
Some generic SE050 variants are offered pre-configured for ease of use and can be used during development
phase and in the field. With this customers have all keys pre-injected in SE050 that are required for the mainuse cases as e.g. cloud onboarding. For more information, see: [4]3.4 Startup behavior
If a supply voltage is applied to pins Vin, VCC within the specified supply voltage operating range or an RF fieldaccording to ISO/IEC 14443 is applied to antenna pins LA, LB the IC boots up.
During boot the IC checks for active interface according list below (in the order of the list):• ISO7816: If interface available for this product type, check CLK to be toggling, then wait for RST to be high• ISO14443: If interface available for this product type, check of RF field on LA, LB antenna pins
22
2
• I C: If interface available for this product type, check if both I C_SDA, I C_SCL pins are at high level (internal
weak pull-up active)• The chosen interface is the only interface the SE050 will receive commands for processing. To select a
different interface the IC needs to be reset.

4 Communication interfaces2

4.1 I C Interfaces
2

The I C interface vary according the specific SE050 variant see Section 4.1.1.
2

2

The SE050 has one I C interface supporting target and one I C interface supporting controller mode.
2

The I C target interface is the main communication interface of the device and is used by the host controller tosend arbitrary APDUs to the device. It supports clock frequencies up to 3.4 MHz when operated in High-Speed22Mode (HS). The I C interface is using the Smartcard T=1 over I C protocol.
The default target address of the SE050 is configured to 0x48.
target address
1

0

0

1

0

0

0

R/W

aaa-037450

Figure 3. target address
2

The I C controller interface is supposed to be used with target devices that need to be securely written andread. This interface features a maximum SCL clock rate of 400 kHz.
2

2

I C controller can only be used when the I C target interface is active.
SE050

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4.1.1 Supported I C frequencies
2

2

The SE050 I C target interface supports the I C high-speed mode with a maximum SCL clock of up to 3.4
MHz when clock stretching is enabled. In case clock stretching is disabled the maximum supported SCL clock
frequency is 1 MHz. This is the default setting for the SE050 new generation products, SE050E.
In the following SE050 configurations, A,B,C,D,F, the Clock stretching is enabled by default. Clock stretching2
will occur for frequencies higher than 600 kHz. In case clock stretching is not supported by the I C controller adedicated configuration with disabled clock stretching has to be used to ensure the above mentioned maximum
clock frequency.
2

The SE050 I C controller interface supports maximum 400 kHz SCL clock frequency.
For more details on the features of each configuration, refer to [4].

4.2 ISO7816 and ISO14443 Interface
2

1

The SE050 supports in addition to the I C interface ISO7816 and ISO14443-A Smartcard interfaces. For
the ISO7816 interface SmartCard protocols T=0 and T=1 are supported. For the ISO14443 interface protocol
T=CL is used. The supported resonance input capacitance is 56 pF. In addition one additional GPIO pad IO2 is
supported.
2

The RST_N pin can only be used as external reset source if the ISO7816 interface is enabled. If only the I C
interface is enabled, the RST_N pad has no effect. If the SE050 is kept in reset state the current consumption isas defined for idle, see Table 12.

5Power-saving modes

The device provides two power-saving operation modes. The Power-down mode (with state retention) and the
Deep Power-down mode (no state retention). These modes are activated via pad ENA (Deep Power-downmode) or by the SW (Power-down mode).

5.1 Power-down mode
The Power-down mode has the following properties:• All internal clocks are frozen• CPU enters power-saving mode with program execution being stopped• CPU registers keep their contents• RAM keeps its contents
2

The SE050 enters into Power-down mode by receiving "End of APDU session request" via the T=1 over I C
protocol. In Power-down mode, all internal clocks are frozen. The IOs hold the logical states they had at thetime Power-down mode was activated.
2

2

To exit from the Power-down mode an external interrupt edge must be triggered by a falling edge on I C_SDA .

5.2 Deep Power-down mode
The SE050 provides a special power-saving mode offering maximum power saving. This mode is activated bypulling enable PIN (ENA) to a logic zero level.
1 ISO7816 is not enabled in generic SE050 configurations (see [4], AN12436) but available on customer request.
2 In case ISO7816 is enabled a reset signal on RST_N exits the Power-down mode. After wake-up from Power-down mode via RST_N

the device is in idle mode (see Table 12)

SE050

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2

While in Deep Power-down mode the internal power and VOUT is switched off completely and only the I C pads
stay supplied.
To leave the Deep Power-down mode pad ENA has to be pulled up to to a logic „1" level.
For usage of Deep Power-down mode the SE050 must be supplied via pin Vin and pin VCC needs to be suppliedby pin Vout.

6 Ordering information
6.1 Ordering options
Table 3. SE050 Ordering information
12NC

Type number

SE050 Variant

Orderable part number

9354 343 82472

SE050E2HQ1/Z01Z3

SE050E2

SE050E2HQ1/Z01Z3Z

9354 284 44472

SE050F2HQ1/Z018H

SE050F2

SE050F2HQ1/Z018HZ

9353 867 22472

SE050A1HQ1/Z01SG

SE050A1

SE050A1HQ1/Z01SGZ

9353 869 84472

SE050A2HQ1/Z01SH

SE050A2

SE050A2HQ1/Z01SHZ

9354 015 87472

SE050D2HQ1/Z01PA

SE050D2

SE050D2HQ1/Z01PAZ

9353 869 85472

SE050B1HQ1/Z01SE

SE050B1

SE050B1HQ1/Z01SEZ

9353 869 86472

SE050B2HQ1/Z01SF

SE050B2

SE050B2HQ1/Z01SFZ

9353 869 87472

SE050C1HQ1/Z01SC

SE050C1

SE050C1HQ1/Z01SCZ

9353 869 88472

SE050C2HQ1/Z01SD

SE050C2

SE050C2HQ1/Z01SDZ

Table 4. SE050 Ordering information for development kit
12NC

Type number

Description

9354 332 66598

OM-SE050ARD-E

SE050 Arduino-compatible development kit,
SE050E configuration

9354 357 63598

OM-SE050ARD-F

SE050 Arduino compatible development kit,
SE050F configuration

9353 832 82598

OM-SE050ARD

SE050 Arduino-compatible development kit,
SE050C configuration

6.2 Ordering SE050 samples
Samples can be ordered from NXP Semiconductors via nxp.com using the "Buy Direct" button on the productinformation page for SE050. Note that NXP Semiconductors can provide up to five pieces free of charge. Larger
quantities have to be ordered commercially.

6.3 Configuration
Detailed information about the configurations and enabled features for each available variant of the SE050 are
available in a separate NXP Application Note, see [4]SE050

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7 Pinning information
7.1 Pinning

16 ISO 7816 IO217 ISO 14443 LA

19 VSS

20 n.c.

terminal 1
index area

18 VCC

7.1.1 Pinning HX2QFN20

ISO 14443 LB

1

15 VOUT

n.c.

2

14 ISO 7816 RST_N

ISO 7816 IO1

3

n.c.

4

12 VINn.c.

5

11 ENAl2C_SCL 10913 ISO 7816 CLK

l2C_SDA

8
n.c.

7
n.c.

n.c.

6

SE050

aaa-031924

Transparent top view

Figure 4. Pin configuration for HX2QFN20 (SOT1969-1)

Note: Terminal 1 index area is marked on the bottom with a notch on the center pad and on the top with aprinted dot.
Table 5. Pin description HX2QFN20
SymbolPin

Description

ISO 14443 LB

1

ISO14443 Antenna Connection, if not used connect to VSS

n.c.

2

not connected

ISO 7816 IO1

3

ISO 7816 IO or I C controller SDA, if not used n.c (recommended) or connect
to VCCn.c.

4

not connected

n.c.

5

not connected

n.c.

6

not connected

n.c.

7

not connected

n.c.

8

not connected2

I C_SDA9

I C target data, if not used n.c.

I C_SCL

2

10

I C target clock, if not used n.c.

ENA

11

Deep Power-down mode enable, if not used then connect to VCC

VIN

12

power supply voltage input for I C pads and ISO 7816/14443 interface andlogic supply in case Deep Power-down mode is used

ISO 7816 CLK

13

ISO 7816 clock input, if not used then n.c (recommended) or connect to VCC

SE050

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2

2
2

2

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Table 5. Pin description HX2QFN20...continued
SymbolPin

Description

ISO 7816 RST_N

14

ISO 7816 reset input low active, if not used then connect to VCC or VSS

Vout

15

supply voltage output to be connected with pad VCC on PCB level, if DeepPower-down mode is used. n.c. if not used.

ISO 7816 IO2

16

ISO7816 IO2 pad or I C controller SCL. I if not used n.c (recommended) orconnect to Vout.

ISO 14443 LA

17

ISO14443 antenna connection, if not used then connect to VSS

VCC

18

logic and ISO7816/ISO14443 interface power supply voltage input, to beconnected with pad Vout on PCB level, if Deep Power-down mode to be used

VSS

19

groundn.c.

20

not connected

2

The center pad of the IC is not connected, although it is recommended to connect it to ground for thermal
reasons.
2

Reference voltage for ISO 7816 IO1, CLK, RST is VCC; for I C, SDL, and SCL reference voltage is Vin and for
IO2 it is Vout.

8 Package
SE050 is offered in HX2QFN20 package. The dimensions are 3 mm x 3 mm x 0,32 mm with a 0,4 mm pitch.
Please refer to the package data sheet [2], SOT1969-1.

9 MarkingTable 6. Marking codes
Type number

Marking code

Sx050...

Line A: S50
Line B: **** (**** = 4-digit Batch code)
Line C: nDyww
D: RHF-2006 indicatorn: Assembly Center
Y: Year
WW: Week

10 Packing information
10.1 Reel packing
The SE050 product is available in tape on reel.
Table 7. Reel packing options
SymbolParameter

Numbers of units per reel

HX2QFN20

7" tape on reel

3000

SE050

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11 Electrical and timing characteristics
The electrical interface characteristics of static (DC) and dynamic (AC) parameters for pads and functions used2
2
for I C are in accordance with the NXP I C specification (see [1]).

12 Limiting values
Table 8. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS (ground = 0 V).
Symbol Parameter

Conditions

Vin, VCC supply voltage
Vininput voltage

II

input current

any signal pad

V

-

10

mA

2

2

-

10

mA

pad I C_SDA, I C_SCL

latch-up current

VI < 0 V or VI > Vin, VCC

-

100

mA

2

2

[2]

-

±2

kV

2

2

[3]

-

± 500 V

[4]

-

600

mW

-55

125

°C

Vesd_hbm electrostatic discharge
voltage (Human Body
Model)

pads VCC, VSS, RST_N, I C_SDA, I C_SCL, IO1, IO2, CLK

Vesd_cdm electrostatic discharge
voltage (Charge Device
Model)

pads VCC, VSS, RST_N, I C_SDA, I C_SCL, IO1, IO2, CLK

[1]
[2]
[3]
[4]

V

6

Ilu

Storage temperature

6

Unit

-0.3

pad I C_SDA, I C_SCL

Tstg

-0.3

[1]

2

output current

Total power dissipation

Max

2

Io

Ptot

Min

Maximum supported supply voltage is 6 V. The SE050 is characterized for the specified operating supply voltage range of 1.62 V to 3.6 V. In case of
supply voltages above 3.6 V, Deep Power-down mode current <5 µA is not guaranteed.
MIL Standard 883-D method 3015; human body model; C = 100 pF, R = 1.5 kΩ; Tamb = -40 °C to 105 °C.
JESD22-C101, JEDEC Standard Field induced charge device model test method.
Depending on appropriate thermal resistance of the package.

13

Recommended operating conditions

The SE050 is characterized by its specified operating supply voltage range of 1.62 V to 3.6 V.
Table 9. Recommended operating conditions
Symbol Parameter

Conditions

Min

Typ

Max

Vin, VCC Supply voltage

Nominal supply voltage

1.62 1.8

3.6

[1]

V

-0.3

[2]
VCC/Vin

V

Vin

DC input voltage on digital
inputs and digital I/O pads-

H

Field strength

Contactless interface operation

Tamb

Operating ambient[3]
temperature

[1]
[2]
[3]

-

Unit

+ 0.3
1.5

-

7.5

A/m

-40

-

105

°C

Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-down mode current <5 µA is not guaranteed.
IO1, CLK, RST has VCC as reference, SDA, SCL, IO2 and ENA has VIN as reference
All product properties and values specified within this data sheet are only valid within the operating ambient temperature range.

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1.62 V

3.6 V

aaa-015200_

Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-down mode current <5 µA
is not guaranteed.
Figure 5. Characteristic supply voltage operating range

14 Characteristics
14.1 DC characteristics
Measurement conventions
Testing measurements are performed at the contact pads of the device under test. All voltages are defined withrespect to the ground contact pad VSS. All currents flowing into the device are considered positive.

14.1.1 General and General Purpose I/O interface
Table 10. Electrical DC characteristics of Input/Output: IO1/IO2. Conditions: VCC = 1.62 V to 3.6 V (see ; VSS = 0 V;
Tamb = -40 °C to 105 °C, unless otherwise specified
In Table 10 VCC means for IO1 voltage on VCC pin, for IO2 voltage on VIN pin
Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-down mode current <5 µA is
not guaranteed.
Symbol Parameter

Conditions

Min

Typ

Max

Unit
V

VIH

HIGH level input voltage

0.7 × VCC -VCC + 0.3

VIL

LOW level input voltage

-0.3

-

0.25 × VCC V

IIH

HIGH level input current in"weak pull-up" input mode

0.7 VCC ≤ Vin ≤ VCC Test conditions for the
maximum absolute value: IIH(max):
Vin = 0.7 × VCC, VCC = VCC(max)

-

-

-20

μA

IIL

LOW level input current

0 V ≤ Vin ≤ 0.3 VCC;
Test conditions for the maximum
absolute value: IIL(max):
Vin = 0 V, VCC = VCC(max)

-

-

-50

μA

ITL

HIGH-to-LOW transition
input current (only "quasibidirectional" mode)

0.3 VCC < Vin ≤ VCC; Test conditions forthe maximum absolute value: Vin = 0.5
VCC, VCC = VCC(max)

-

-

-250

μA

II

Input current in "weak pull-up" 0 V ≤ VI ≤ VCC; Test conditions for the
input mode
maximum absolute value: II(max):
Vin = 0 V, VCC = VCC(max)

0

-

-50

μA

IILIH

Leakage input current at input VCC < Vin ≤ VCC + 0.3 V;
voltage beyond VCC in "weak -40 °C ≤ Tamb ≤ 105 °C;
pull-up" input mode
Test conditions: Vin = VCC + 0.3 V;
VCC = VCC(max), Tamb = 105 °C

-

-

20

μA

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Table 10. Electrical DC characteristics of Input/Output: IO1/IO2. Conditions: VCC = 1.62 V to 3.6 V (see ; VSS = 0 V;
Tamb = -40 °C to 105 °C, unless otherwise specified...continued
In Table 10 VCC means for IO1 voltage on VCC pin, for IO2 voltage on VIN pin
Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-down mode current <5 µA is
not guaranteed.
Symbol Parameter

Conditions

Min

Typ

Max

Unit

-

-

-50

μA

-0.3 V ≤ Vin < 0 V;
30 °C ≤ Tamb ≤ 105 °C
Test conditions: Vin = -0.3 V;
VCC= VCC(max), Tamb = 105 °C

-

-

-1000

μA

VCC < Vin ≤ VCC + 0.3 V;-40 °C ≤ Tamb≤ 105 °C
Test conditions: Vin = VCC +0.3 V;
VCC = VCC(max); Tamb = 105 °C

-

-

100

μA

-

-

-120

μA

-

-

-1000

μA

0.7 × VCC --V
V

Leakage input current at input -0.3 V ≤ Vin < 0 V;
voltage below VSS in "weak-40 °C ≤ Tamb ≤ 30 °C
pull-up" input mode
Test conditions: V = -0.3 V;

IILIL

in

VCC= VCC(max), Tamb = 30 °C

IILIHQ

Leakage input current at
input voltage beyond VCC(only in "quasi-bidirectional"
mode)

IILILQ

Leakage input current at input -0.3 V ≤ Vin < 0 V; -40 °C ≤ Tamb ≤ 30 °C
voltage below VSS (only in
Test conditions: Vin = -0.3 V;"quasi-bidirectional"
VCC = VCC(max)Tamb= 30 °C
mode)-0.3 V ≤ Vin < 0 V; 30 °C ≤ Tamb ≤ 105 °C;
Test conditions: Vin = -0.3 V; VCC =VCC(max), Tamb= 105 °C
[2]

VOH

HIGH level output voltage

IOH = -20 μA

VOL

LOW level output voltage

IOL = 1 mA

-

-

0.3

IOL = 0.5 mA--

0.15 × VCC V

[1]
[2]

IO1/IO2 source a transition current when being externally driven from HIGH to LOW. This transition current (ITL) reaches its maximum value when the
input voltage VI is approximately 0.5 VCC. Current IIL is tested at input voltage VI= 0.3 V.
External pull-up resistor 20 kΩ to VCC assumed. The worst case test condition for parameter VOH is present at minimum VCC.

VI

II
IIL1maxu-0.3 V

IIH1maxu
VCC

00
VIL1max

VIH1minIILI1maxI

IIHI1maxI

aaa-029327

Figure 6. Input characteristic of RST_N

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Vl

ll

lImin

-0.3 V 0 V

lILIHmaxlIHmin

VILmax

VIHminVCC

0
VCC +0.3 V

lILmaxlImax

lIHmaxlILILmax

aaa-007192

Figure 7. Input characteristic of IO1/IO2

II

VI
IIL1max

II1maxIILIH1max

IIH1max-0.3 V
00V

VIL1max

VIH1min

VCC +0.3 V
VCC

IIL1min

IlLlL1max

II1minaaa-007191

Figure 8. Input characteristic of CLK when the IC is not in reset

II

VI
II2min

VIL2max-0.3 V 0 V

IlLIH2max

IIH2min

VIH2min

VCC

0
VCC +0.3 V

IILIL2max

IIL2max

II2max

IIH2max
aaa-007190

Figure 9. Input characteristic of CLK during IC reset

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14.1.2 I C Interface
2

Table 11. Electrical DC characteristics of I C pads SDA, SCL. Conditions: VCC, VIN = 1.62 V to 3.6 V; VSS = 0 V; Tamb
= -40 °C to 105 °C, unless otherwise specified*
Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-down mode current <5 µA is
not guaranteed.
SCL, SDA pads are in open-drain mode.
Symbol Parameter

Conditions

Min

Typ

Max

Unit

VIH

HIGH level input voltage

0.7 × Vin -Vin + 0.3

V

VIL

LOW level input voltage

-0.3

-

0.25 × Vin

V

VHYS

Input hysteresis voltage

0.081 V--V

VOL(OD)

Low level output voltage (open-drain
mode)

IOL = 3 mA

0

-

0.4

V

IOL(OD)

Low level output current (open-drain
mode)

VOL = 0.6 V

0.6

-

-

mA

IWPU

weak pull-up current

VIO = 0 V

-265-180 -70

µA

IILIH

Leakage input current high level

VSDA = 3.6 V, VSCL = 3.6 V-

0.27 15µA

14.1.3 Power consumption
Table 12. Electrical characteristics of IC supply voltage VCC; VSS = 0 V; Tamb = -40 °C to 105 °C
SymbolParameter

Conditions

Min

Typ

Max Unit

VCC

supply voltage range

VCC = 1.62 V - 3.6 V

1.62 1.8

3.6

V

[1]
IDD

operating mode: typical CPU,no coprocessor active

fCPU = 48 MHz, fMST = 96 MHz

-

4.4

7

mA

AES coprocessor active(AES 48 MHz)CPU in idle mode

-

6.5

7.5

mA

Public Key cryptography
Coprocessor active(96 MHz)CPU in idle mode-

14.4 16.1 mA

DES coprocessor active(DES 48 MHz)CPU in idle mode

-

6.5

7.6

mA

supply current Power-down mode
(ISO7816 clock-stop)

VCC(min) ≤ VCC ≤ VCC(max); Clock to input CLK
stopped, Tamb= 25 °C

-

430

480

µA

IDDD (DPD)

supply current Deep Power-down
mode

VCC(min) ≤ VIN ≤ VCC(max); Tamb= 25 °C

-

3

5

µA

IDD (PD-I2C)

supply current I C Power-down
2mode (I C wake-up source)

450

500

µA

SupplyIDD (PDISO7816)[1]

2

VCC(min) ≤ VCC ≤ VCC(max); Clock to input SCL
stopped, Tamb = 25 °C SDA, SCL pads in pull-up
Typical value with VCC = 1.8 V

Maximum current consumption with concurrent AES and Public Key Cryptography 19 mA.

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14.2 AC characteristics
Table 13. Non-volatile memory timing characteristics
Conditions: VCC = 1.62 V to 3.6 V; VSS = 0 V; Tamb = -40 °C to 105 °C, unless otherwise specified.
Symbol Parameter

Conditions
[2]

[1]

Min

Typ

Max Unit

-

2.3

-

ms

tEEP

FLASH erase + program timetEEE

FLASH erase time

-

1.4

-

ms

tEEW

FLASH program time

-

0.9

-

ms

tEER

FLASH data retention time

-

years

-

cycles

NEEC

[1]
[2]

Tamb = 55 °C

FLASH endurance (maximum number of programming
cycles applied to the whole memory block, performed
by NXP static and dynamic wear leveling algorithm)

25
20 × 106

6

100 × 10

Typical values are only referenced for information. They are subject to change without notice.
Given value specifies physical access times of FLASH memory only.

2

2

[1]

Table 14. Electrical AC characteristics of I C_SDA, I C_SCL, and RST_N ; VCC = 1.8 V ± 10 % or 3 V ± 10 % V;
VSS = 0 V; Tamb = -40 °C to 105 °C
SCL, SDA pads in open-drain mode.
Symbol Parameter2

Conditions

Min

Typ

Max Unit

2

Input/Output: I C_SDA, I C_SCL in open-drain mode
tr(i)
tf(i)
tf(o)

input rise time
input fall time
output fall time

Input/reception mode

[2]

-

-

1

μs

Input/reception mode

[3]

-

-

1

μs

Output/transmission mode; CL = 30 pF

[2]

-

-

0.3

μs

-

-

3.4

MHz

2

tCLKW, Tamb and VCC in their specified limits

2

fCLK

External clock frequency in I C
applications

tPD

Power down duration time (I C
wake-up)

CPU clock = 48 MHz

[4]

-

67

-

μs

tWKPD

Wake-up from power down
2
duration time (I C wake-up)

CPU clock = 48 MHz

[5]

-

97

-

μs

CPIN

Pin capacitances RST_N,
2
2
I C_SDA, /I C_SCL

Test frequency = 1 MHz; Tamb = 25 °C--

10.5 pF

tENalt

ENA low time and Vout, VCC low
time for entering deep power
down mode

-

2

-

μs

Ron

Resistance of power switch

Tamb = 105 °C, Iload = 25 mA, Vin = 1.62 V

-

-

1.1

Ω

Iout

maximum current driving
capability of pin Vout

Tamb = 105 °C

-

-

25

mA

[6]

Inputs: RST_N (active only if ISO7816 UART interface is enabled)tRW

Reset pulse width (RST_N low)
without entering Power-down
mode

40

-

400

μs

tRDSLP

Reset pulse width (RST_N low)
to enter Power-down mode

500

-

-

μs

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2

2

[1]

Table 14. Electrical AC characteristics of I C_SDA, I C_SCL, and RST_N ; VCC = 1.8 V ± 10 % or 3 V ± 10 % V;
VSS = 0 V; Tamb = -40 °C to 105 °C...continued
SCL, SDA pads in open-drain mode.
Symbol Parameter

Conditions

Min

Typ

Max UnittWKP

Wake-up time from Power-down
mode

fCLKmin < fCLK < fCLKmax

-

8

10

μs

tWKPIO

Pad LOW time for wake-up fromPower-down modelevel triggered ext.int.

-

8

10

μs

edge triggered ext.int.

-

8

10

μs

40

-

-

μs

-

-

10.5 pF

tWKPRST RST_N LOW time for wake-up
from Power-down mode
CPIN
[1]
[2]
[3]
[4]
[5]
[6]

Pin capacitances RST_N,
2
2
I C_SDA, /I C_SCL

Test frequency = 1 MHz; Tamb = 25 °C

All appropriately marked values are typical values and only referenced for information. They are subject to change without notice.
tr is defined as rise time between 30 % and 70 % of the signal amplitude.tf is defined as fall time between 70 % and 30 % of the signal amplitude.
tr is defined as rise time between 30 % and 70 % of the signal amplitude.tf is defined as fall time between 70 % and 30 % of the signal amplitude.
2
Wakeup from power down: if clock stretching disabled and I C_SCL=400 kHz; the wakeup time will not be sufficient under the rare condition where hostsends the first command during the time where SE is just entering power down; in this case the SE will send an R block to request retransmission from thehost
2Wakeup from power down: if clock stretching disabled and I C_SCL=1 MHz; the wakeup time will not be sufficient to receive the first host command; theSE will send an R block to request retransmission from the hostLow glitches below 0.4 V on pin ENA and Vin, Vout, VCC larger than 30 ns cause Power-On-Reset, respectively entering deep power-down mode.
Vhigh
CLK (et al)
Vlow

70 % level

0.5 VDD

30 % level

tCLKW

tfCLK
tfRST
tfIO

1/fCLK

trCLK
trRST
trIO
aaa-037451

1)

2

2

During AC testing the inputs RST_N, I C_SDA, I C_SCL are driven at 0 V to 0.3 V for a LOW input level and at VCC -0.3
V to VCC for a HIGH input level. Clock period and signal pulse (duty cycle) timing is measured at 50 % of VCC.
2)

tr is defined as rise time between 30 % and 70 % of the signal amplitude. tf is defined as fall time between 70 % and 30% of the signal amplitude.
2

2

Figure 10. External clock drive and AC test timing reference points of I C_SDA, I C_SCL, and RST_N (seein open-drain mode

1)

2)

and )

Table 15. Electrical AC characteristics of IO1, IO2, CLK and RST_N (ISO7816 interface)
Conditions: VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS = 0 V; Tamb = -40 °C to 105 °C, unless otherwise specified. Typicalvalues are only referenced for information. They are subject to change without notice.
SymbolParameter

Conditions

Min

Typ

Max

Unit

Input/Output: IO1/IO2
tr(i)

tf(i)

tr(o)
tf(o)

input rise time

input fall time

output rise time
output fall time

SE050

Product data sheet

Input/reception mode

[1] [2]

-

-

1

μs

Input/reception mode[3] [2]--0.25 xtIOWx_minμs

Input/reception mode

[1] [2]

-

-

1

μs

Input/reception mode[3] [2]--0.25 xtIOWx_minμs

Output/transmission mode; CL = 30 pF

[2]

-

-

0.1

μs

Output/transmission mode; CL = 30 pF

[2]

-

-

0.1

μs

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Table 15. Electrical AC characteristics of IO1, IO2, CLK and RST_N (ISO7816 interface)...continued
Conditions: VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS = 0 V; Tamb = -40 °C to 105 °C, unless otherwise specified. Typicalvalues are only referenced for information. They are subject to change without notice.
SymbolParameter

Conditions

Min

Typ

Max

Unit

0.85 -

11.5

MHz

40

-

60

%

Inputs: CLK and RST_N
External clock frequency
in ISO/IEC 7816 UART
applications

tCLKW

Clock pulse width i.r.t. clock
period (positive pulse duty
cycle of CLK)

tr(i)(CLK)

CLK input rise time

[5]

-

-

[6]

CLK input fall time[2] [6]--[6]tr(i)(RST_N) RST_N input rise time

[2]

-

-

400

μs

tf(i)(RST_N) RST_N input fall time[2] [7]

-

-

400

μs

tf(i)(CLK)

[1]
[2]
[3]

[4]
[5]
[6]
[7]

tCLKW, tamb and VCC in their
specified limits

[4]

fCLK

At minimum IO1 input signal HIGH or LOW level voltage pulse width of 3.2 μs. This timing specification applies to ISO7816 configurations down to aminimum etu duration of 16 CLK cycles at a maximum CLK frequency of 5 MHz (TA1=0x96, (Fi/Di)=(512/32)), for example.
tr is defined as rise time between 10 % and 90 % of the signal amplitude.
At minimum IO1 input signal HIGH or LOW level voltage pulse width of less than 3.2 μs. This timing specification applies to ISO7816 configurations
beyond the conditions listed in note [2], down to a minimum etu duration of 8 CLK cycles at a maximum CLK frequency of 5 MHz (TA1=0x97, (Fi/Di)=(512/64)), for example. An 8 CLKs/etu at fclk = 5 MHz configuration results in tIOWx_min = 1.6 μs, and in a time of 400 ns for trIO_max and tfIO_max,
matching the (Fi/Di)=(512/64) speed enhancement requirements of ETSI TS 102 221.
ISO/IEC 7816 I/O applications have to supply a clock signal to input CLK in the frequency range of 1 MHz to 10 MHz nominal. A ± 15 % tolerance range
yields the allowed limits of 0.85 MHz and 11.5 MHz.
During AC testing the inputs CLK, RST_N, and IO1 are driven at 0 V to +0.3 V for a LOW input level and at VCC − 0.3 V to VCC for a HIGH input level.
Clock period and signal pulse (duty cycle) timing is measured at 50 % of VCC, see Figure 18.
The maximum CLK rise and fall time is 10 % of the CLK period 1/fCLK - with the following exception: In the CLK frequency range of 1 MHz to 5 MHz the
maximum allowed CLK rise and fall time is 50 ns, if 10 % of the CLK period is shorter than 50 ns.
The ETSI TS102 221/GSM 11.1x specifications specify a maximum reset signal (RST_N) rise time and fall time of 400,000 μs, respectively.

Note: tf is defined as fall time between 90 % and 10 % of the signal amplitude.
Table 16. Electrical AC characteristics of LA, LB; Conditions: Tamb = -40 °C to 105 °C, unless otherwise
specifiedSymbol Parameter

Conditions

Typ

[1]

Max Unit

Input/Output: LA, LB
[2]

CLALB

Pin capacitance LA, LB, bare die (SO28 empty package ground-off)Configured for antenna input with 56 pF capacitance,
Test frequency = 13.56 MHz; Tamb= 25 °C

VLA,LB = 2.1 Vrms

[3] [4]

54.3

-

pF

VLA,LB = 0.3 Vrms

[4]

50.1

-

pF

[3] [4] [5]0.913 -kΩ13.56 -

MHz

[2]
RLALB

Configured for antenna input with 56 pF capacitance,
test frequency = 13.56 MHz; Tamb= 25 °C

VLA,LB = 2.1 Vrms

fLALB

Operating frequency LA, LB

level triggered ext.int.

[1]
[2]
[3]
[4]
[5]

Typical values (± 10 %) are only referenced for information. They are subject to change without notice.
The CLALB and RLALB values stated here assume a parallel RC equivalent circuit for the chip.
The value stated here was measured at estimated start of chip operation and is comparable to the values stated in other family member data sheets.
Measured with sine wave at LA, LB.
Parameter is valid in contactless ISO14443 compliant operation valid only.

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14.3 I C Bus Timings
2

Parameters defined in this chapter replace the parameter definitions of I C bus, for specification see [4].
SDA
50 %

50 %

SCL
50 %

50 %

tHDf;DAT50

tHDr;DAT50

aaa-036486

2

Figure 11. I C Bus Timings
2

Table 17. I C Bus Timing Specification
SymbolParameter

Condition Min

Max Unit[1]tHDf;DAT50

data hold time 50 % SCL - 50 % SDA level

Fast mode 8

-

ns

[2]
tHDr;DAT50

data hold time 50 % SCL - 50 % SDA level

Fast mode 24

-

ns

[1]
tHDf;DAT50

data hold time 50 % SCL - 50 % SDA levelHs mode

8

-

ns

[2]
tHDr;DAT50

data hold time 50 % SCL - 50 % SDA levelHs mode

9

-

ns

[1]
[2]

tHDf;DAT50, as defined in Figure 11, replaces parameter tHD;DAT defined in [4]tHDr;DAT50, as defined in Figure 11, replaces parameter tHD;DAT defined in [4]14.4 EMC/EMI
EMC and EMI resistance according to IEC 61967-4.

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15 Abbreviations
Table 18. Abbreviations
AcronymDescription

AES

Advanced Encryption Standard

APDU

Application Protocol Data Unit

CL

Contactless

CLK

External clock signal input contact pad

CC

Common Criteria

CMAC

Cipher-based MAC

CRC

Cyclic Redundancy Check

CRI

Cryptography Research Incorporated

DES

Digital Encryption Standard

DPA

Differential Power Analysis

DSS

Digital Signature Standard

EAL

Evaluation Assurance Level

ECC

Elliptic Curve Cryptography

EMC

Electromagnetic compatibility

EMI

Electro Magnetic Immunity

FM

Fast-ModeFM+

Fast-Mode+GP

Global Platform

GPIO

General-purpose input/output

HS

High-Speed-Mode

HKDF

HMAC-based Extract-and-Expand Key Derivation Function

HMAC

Keyed-Hash Message Authentication Code

HW

HardwareIC

Integrated Circuit

2

I C

Inter-Integrated Circuit

I/O

Input/Output

IoTInternet of Things

JCOP

Java Card Open Platform

LA

ISO 14443 Antenna Pad

LB

ISO 14443 Antenna Pad

NFCNear Field Communication

MAC

Message Authentication Code

MCU

Microcontroller unit

MPU

Microprocessor

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Table 18. Abbreviations...continued
AcronymDescription

MW

Middleware

OS

Operating System

NIST

National Institute for Standards and Technology

PCB

printed circuiy board

PKI

Public Key Infrastructure

PRF

Pseudo Random Function

RAM

Random Access Memory

RSA

Rivest-Shamir-Adleman

RST

Reset

SAM

Secure Access Module

SCL

Serial clock

SDA

Serial data

SPA

Simple Power Analysis

SFI

Single Fault Injection

SHA

Secure Hash Algorithm

SW

Software

TLS

Transport Layer Security

VCC

Supply Voltage Input

Vin

Input voltage

Voutoutput voltage

VSS

GroundSE050

Product data sheet

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Rev. 3.8 — 18 October 2023
504938© 2023 NXP B.V. All rights reserved.

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16 References
[1]
[2]
[3]
[4]
[5]

2

NXP SE05x T=1 Over I C Specification User manual, document number UM11225. Available on NXP
websiteSOT1969-1; HX2QFN20; Reel packing and package information. Available on NXP website
SE050 IoT Applet APDU Specification, document number AN 12413. Available on NXP website
SE050 configurations Application Note, document number AN12436. Available on NXP website
SE050 Use and Security Guidelines Application Note, document number AN12514. Availavle on NXP
website.

SE050

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3.8 — 18 October 2023
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17 Revision history
Table 19. Revision history
Document ID

Release date

Data sheet status

Change notice

Supersedes

SE050 v.3.820231018

Product data sheet-

504937

Modifications• Corrected a typo in the second paragraph after Table 5 ISO1816 must be ISO7816• Adjusted the timing value in Table 1 the value of the erase time and program time where
switched around• Corrected the layout of some tables• Corrected the notation of some symbols, and added a space where mandatory• updated the legal information

5049372022-10-27

Modifications• Update Section 3.1.1

5049362022-08-24

Modifications• Update Section 3.1.1

5049352022-08-22

Modifications• Update Section 2.3

5049342022-03-28

Modifications• Update Section 1.3• Update Section 2.2• Update Section 2.3• Update Section 4.1• Update Section 4.1.1• Update Section 6.1• Update Table 3• Update Figure 25049332021-07-01

Modifications• Insert SE050F2 variant to Table 35049322021-05-05

Modifications• updated Section 2.2• updated Table 2• Moved technical information on secure objects in Section 3.1.2 to the APDU specification [3]• Replace "master/slave" with "controller/target"• updated Figure 1• Updated references

504931

2020-12-15

Modifications• updated Figure 2• updated legal information• corrected Section 1.3

SE050

Product data sheet

Product data sheet
Product data sheet

504936504935

Product data sheet

504934

Product data sheet

504933

Product data sheet
Product data sheet

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3.8 — 18 October 2023
504938504932504931504930© 2023 NXP B.V. All rights reserved.

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SE050NXP Semiconductors

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Table 19. Revision history...continued
Document ID

Release date

Data sheet status

5049302020-05-12

Product data sheet

Modifications• updated: Section 7.1.1• updated: Table 6• updated: Section 2.3• added Section 3.4• added Figure 3• added Section 14.3
• updated Section 12• updated Section 14.1.3• updated Section 14.2
• updated Section 14.1.2• updated Section 13

504913

20190607

Objective data sheet

504912504912

20190510

Objective data sheet

504911504911

20181122

Objective data sheet

SE050

Product data sheet

Change notice

All information provided in this document is subject to legal disclaimers.

Rev. 3.8 — 18 October 2023
504938Supersedes
504913© 2023 NXP B.V. All rights reserved.

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SE050NXP Semiconductors

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18 Legal information
18.1 Data sheet status
Document status[1][2]

Product status[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for productdevelopment.

Preliminary [short] data sheet

Qualification

This document contains data from the preliminary specification.

Product [short] data sheet

Production

This document contains the product specification.

[1]
[2]
[3]

Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

18.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may resultin modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have noliability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheetwith the same product type number(s) and title. A short data sheet isintended for quick reference only and should not be relied upon to containdetailed and full information. For detailed and full information see therelevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with theshort data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Productdata sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors andcustomer have explicitly agreed otherwise in writing. In no event however,shall an agreement be valid in which the NXP Semiconductors productis deemed to offer functions and qualities beyond those described in the
Product data sheet.

18.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for theconsequences of use of such information. NXP Semiconductors takes noresponsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removalor replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability
towards customer for the products described herein shall be limited inaccordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right tomake changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
SE050

Product data sheet

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical orsafety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability forinclusion and/or use of NXP Semiconductors products in such equipment orapplications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of theirapplications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for thecustomer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use bycustomer’s third party customer(s). Customer is responsible for doing allnecessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above thosegiven in the Recommended operating conditions section (if present) or theCharacteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects toapplying the customer’s general terms and conditions with regard to thepurchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.

All information provided in this document is subject to legal disclaimers.

Rev. 3.8 — 18 October 2023
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SE050NXP Semiconductors

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Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of thisdocument, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Suitability for use in non-automotive qualified products — Unless
this document expressly states that this specific NXP Semiconductors
product is automotive qualified, the product is not suitable for automotive
use. It is neither qualified nor tested in accordance with automotive testingor application requirements. NXP Semiconductors accepts no liability forinclusion and/or use of non-automotive qualified products in automotive
equipment or applications.
In the event that customer uses the product for design-in and use inautomotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warrantyof the product for such automotive applications, use and specifications, and(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design anduse of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document, including
the legal information in that document, is for reference only. The English
version shall prevail in case of any discrepancy between the translated andEnglish versions.

Security — Customer understands that all NXP products may be subject tounidentified vulnerabilities or may support established security standards or
specifications with known limitations. Customer is responsible for the designand operation of its applications and products throughout their lifecycles
to reduce the effect of these vulnerabilities on customer’s applications
and products. Customer’s responsibility also extends to other open and/or
proprietary technologies supported by NXP products for use in customer’s
applications. NXP accepts no liability for any vulnerability. Customer should
regularly check security updates from NXP and follow up appropriately.
Customer shall select products with security features that best meet rules,
regulations, and standards of the intended application and make theultimate design decisions regarding its products and is solely responsible
for compliance with all legal, regulatory, and security related requirements
concerning its products, regardless of any information or support that may beprovided by NXP.
NXP has a Product Security Incident Response Team (PSIRT) (reachable
at PSIRT@nxp.com) that manages the investigation, reporting, and solution
release to security vulnerabilities of NXP products.
NXP B.V. — NXP B.V. is not an operating company and it does not distributeor sell products.

18.4 Trademarks
Notice: All referenced brands, product names, service names, andtrademarks are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.
EdgeLock — is a trademark of NXP B.V.
I2C-bus — logo is a trademark of NXP B.V.
JCOP — is a trademark of NXP B.V.
MIFARE — is a trademark of NXP B.V.

SE050

Product data sheet

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Rev. 3.8 — 18 October 2023
504938© 2023 NXP B.V. All rights reserved.

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TablesTab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10.

Tab. 11.

SE050 commercial name format ....................... 2
Feature Overview .............................................. 4
SE050 Ordering information ............................10
SE050 Ordering information fordevelopment kit ............................................... 10
Pin description HX2QFN20 ............................. 11
Marking codes .................................................12
Reel packing options .......................................12
Limiting values ................................................ 13
Recommended operating conditions ............... 13
Electrical DC characteristics of Input/
Output: IO1/IO2. Conditions: VCC = 1.62 V
to 3.6 V (see ; VSS = 0 V; Tamb = -40 °C to105 °C, unless otherwise specified ................. 14
Electrical DC characteristics of I2C pads
SDA, SCL. Conditions: VCC, VIN = 1.62 V
to 3.6 V; VSS = 0 V; Tamb = -40 °C to 105°C, unless otherwise specified* .......................17

Tab. 12.
Tab. 13.
Tab. 14.

Tab. 15.
Tab. 16.
Tab. 17.
Tab. 18.
Tab. 19.

Electrical characteristics of IC supply
voltage VCC; VSS = 0 V; Tamb = -40 °C to105 °C ............................................................. 17
Non-volatile memory timing characteristics ..... 18
Electrical AC characteristics of I2C_SDA,
I2C_SCL, and RST_N; VCC = 1.8 V ± 10
% or 3 V ± 10 % V; VSS = 0 V; Tamb = -40°C to 105 °C ................................................... 18
Electrical AC characteristics of IO1, IO2,
CLK and RST_N (ISO7816 interface) ............. 19
Electrical AC characteristics of LA, LB;
Conditions: Tamb = -40 °C to 105 °C,
unless otherwise specified .............................. 20
I2C Bus Timing Specification .......................... 21
Abbreviations ...................................................22
Revision history ...............................................25

FiguresFig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.

SE050 solution block diagram ...........................2
SE050 functional diagram ................................. 6
target address ................................................... 8
Pin configuration for HX2QFN20(SOT1969-1) ....................................................11
Characteristic supply voltage operating
range ............................................................... 14
Input characteristic of RST_N ......................... 15
Input characteristic of IO1/IO2 ........................ 16

SE050

Product data sheet

Fig. 8.
Fig. 9.
Fig. 10.

Fig. 11.

Input characteristic of CLK when the IC is
not in reset ...................................................... 16
Input characteristic of CLK during IC reset ...... 16External clock drive and AC test timingreference points of I2C_SDA, I2C_SCL,
and RST_N (see 1) and 2)) in open-drainmode ............................................................... 19
I2C Bus Timings ..............................................21

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Rev. 3.8 — 18 October 2023
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Contents
1
1.1
1.2
1.3
2
2.1
2.2
2.3
3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.2
3.3

Introduction ......................................................... 1
SE050 use cases .............................................. 1
SE050 target applications ..................................2
SE050 naming convention .................................2
Features and benefits .........................................3
Key benefits .......................................................3
Key features ...................................................... 3
Features in detail ...............................................4
Functional description ........................................6
Functional diagram ............................................ 6
Random number generator ............................... 6
Supported secure object types .......................... 7
Access control ................................................... 7
Sessions and multi-threading ............................ 7
Attestation and trust provisioning .......................7
Application support ............................................ 7
Credential Storage & Memory ........................... 8
Preprovisioned "Ease of Use"configurations .....................................................8
3.4
Startup behavior ................................................ 8
4
Communication interfaces ................................. 8
4.1
I2C Interfaces .................................................... 8
4.1.1
Supported I2C frequencies ................................9
4.2
ISO7816 and ISO14443 Interface ..................... 95Power-saving modes .......................................... 9
5.1
Power-down mode .............................................9
5.2
Deep Power-down mode ................................... 96
Ordering information ........................................ 10
6.1
Ordering options .............................................. 10
6.2
Ordering SE050 samples ................................ 10
6.3
Configuration ....................................................10
7
Pinning information .......................................... 11
7.1
Pinning ............................................................. 11
7.1.1
Pinning HX2QFN20 ......................................... 11
8
Package ..............................................................129
Marking ...............................................................12
10
Packing information ..........................................12
10.1
Reel packing ....................................................12
11
Electrical and timing characteristics ...............13
12
Limiting values .................................................. 13
13
Recommended operating conditions .............. 13
14
Characteristics .................................................. 14
14.1
DC characteristics ............................................1414.1.1
General and General Purpose I/O interface .....1414.1.2I2C Interface .................................................... 17
14.1.3
Power consumption ......................................... 17
14.2
AC characteristics ............................................18
14.3
I2C Bus Timings .............................................. 21
14.4
EMC/EMI ..........................................................21
15
Abbreviations .................................................... 22
16
References ......................................................... 24
17
Revision history ................................................ 25
18
Legal information .............................................. 27
Please be aware that important notices concerning this document and the product(s)described herein, have been included in section 'Legal information'.

© 2023 NXP B.V.

All rights reserved.

For more information, please visit: http://www.nxp.com
Date of release: 18 October 2023
Document number: 504938