Development ofNew LLRF System~ KEKB LLRF Team ~T. Kobayashi, K. Akai, K. Ebihara,
A. Kabe, K. Nakanishi, M. Nishiwaki, J. Odagiri,~ Mitsubishi Electric TOKKI System Corp. ~H. Deguchi, K. Harumatsu, K. Hayashi, J. Nishio,
J. Mizuno, M. Ryoshi,

1 /17

Talk Outline
1. Overview the Digital LLRF System
2. Performance Evaluation of the prototypea) FB Controlb) Temperature Dependencyc) Auto Tuner Control
3. RF Reference Distribution
4. Summary

2 /17

Features of New LLRF System
Preset analog systems will be replaced by new digital ones step-by-step.

• It consists of µTCA-based FPGA boards & PLC (EPICS-Sequencer).
• EPICS-IOC on Linux-OS is embedded in each of them. They can be
operated remotely via EPICS-Channel Access.

• Hardware is common for both of ARES & SC Cavity. (Also bothsoftwares are much the same.)• EPICS record names will be consistence with the present systems.

• Klystrons (LLRF) : Cavity unit = 1 : 1 (SuperKEKB)EPICS control on FPGA core and PLCuTCA-platform
FPGA Boardswith CPU (PPC) runningLinux-OS for EPICS-IOC.
3 /17

Prototype of New LLRF System
A prototype of new digital LLRF system(α-version) was produced in last year.
And the performance was evaluated.

for the SuperKEKB
New LLRF System for one klystron(EIA-19” rack)

PLC：EPICS Sequencer (F3RP61)
Linux-OS PC’s with EPICS

RF-Output Unit (IQ-Modulator & RF-SW）µTCA-based Digital FB unit
Down Converter Unit (IF out)

Operate via CAµTCA
GUI is composed by using EDM.

Arc Sensor

RF Interlock Unit
Distribution Unit
(LO & CLK generation and distribution)

4 /17

1.

&LLRF%#!

uTCACPU(+HDD)%#!
uTCA-platform Digital Control Unit

'Linux Server (tftp, nfs, DHCP, ntp)
common with the STF.
'FPGAConfigurationboot loader (3$(")

Board - (A)$(")
    $("Board - (B)*  

PM (Power Module)

Board - (C)$("+ 
FPGA Board

16-bit ADC x 4ch,16-bit DAC x 2ch

Board - (A)Digital FB Control

Each board has a CPU (PPC), and the
EPICS-IOC on Linux-OS is embedded.
3

2010/11/25

KEKB_UG_LLRF-069B



Board - (B)Tuner Control  

Board - (C)I/L Control& VSWR Monitor
5 /17

Block Diagram of FB&Tuner Cont. (ARES)-1 Mode FB
508.8MHzI/Q Mod.

RF : 508.9 MHz

TunerCont. PTG
(S)

1/6

CLK
84.8 MHz

LO & CLK
Distributor

1/2

CLK
1/4 42.4 MHz

PTG
(A)

DAC

P-gainP-gainΔΦ
(s-g)

ΔΦ Detune
offset
(a-c)

+

Ref-I

S-Cav
KLY
C-DmprDriver
Amp

FB
Cont.

ARES Cavity

A-Cav

RF
SW

FF- Q

+

Tuner

DCCT

uTCA-based
Ref-Q FPGA boards--Selector

ADC

Rot.

Rot.

I,Q

I,Q

ADC

ADC

IF
10.6 MHz

LO

LO : 519.5 MHzInter Lock

PI - Cont.

Rot. Rot. Rot. Rot.
I,QI,Q I,Q I,Q
ADC ADC

DAC

TunerRotation

FF- I

ADC

Q

I

CLKLO

Tuner Driver

Combiner

10V
1kHz

RF Reference
508.9 MHz

cw/ccw

PTG : Pulse Train Generator

cw/ccw

LLRF System

LO

Monitor Signals
508.9 MHzADC CLK
4 x IF

IF-Q

I
Q

-I

Phases can be easily calibrated by
calculation of I/Q-rotation.
KLYout FWD
A-Cav PickUp (a)C-Cav PickUp (c)S-Cav PickUp (s)Cav-Input (g)6 /17

Block Diagram of FB&Tuner Cont. (SC)
Piezo Cont. Voltage

LLRF Systemcw/ccw

PTG : Pulse Train Generator

508.9 MHz508.8MHzI/Q Mod.

RF : 508.9 MHz

1/6DAC

Piezo
Gain

FF- IPulseGain

84.8 MHzPI-Cont

Detuneoffset1/2ΔΦ(a-g)

CLKRot. Rot. Rot. Rot.
I,QI,Q I,Q I,Q

1/4

RFSW

FB
Cont.

DAC

SCC
KLY
DriverAmp

Rotation

CLK
LO & CLK
Distributor

PTG

DAC

Tuner

Inter Lock

Q

I

Tuner
Cont.

Tuner

-1 Mode FB
Combiner

RF Reference

Tuner Driver

Piezo

42.4 MHz ADC ADC ADC

LO+-Ref-Q-uTCA-based
FPGA boards

Monitor Signals
508.9 MHz

Selector

ADC

CLKIF
10.6 MHz

LO : 519.5MHz+PI - Cont.

Ref-I

DCCT

FF- Q

Rot.

Rot.

I,Q

I,Q

ADC

ADC

LO
LO

KLYout FWD

Cav PickUp (a)Cav-Input (g)7 /17

Evaluation of FB Control
FB control performance was evaluatedby using a simulant cavity
Tuner

Pgain=2, Igain=2.6x104

LO

RFFPGAIFADC

FB Cont

DAC
DAC

IQ-Mod.

Simulant Cav.
-1 dBmSimulant
Cavity( Coaxial Resonator )QL~3000

QL~3000+26dBmThis evaluation condition is more adverse than thereal operation for the stability.
ARES Cavity: QL~20000 (β~5)
8 /17FB Control Result( Monitored Data by FPGA acting FB cont. )1.05MS/s, 4096 points (~ 4-ms duration)

Amplitude

10 acquisitions are superimposed.

< 0.03% (rms)Phase< 0.02 deg. (rms)Very good stability was obtained.
The amplitude and phase stabilities are 0.03% and 0.02 deg., respectively.
The FB control performance satisfy the requirements very well in short termstability.

9 /17

Long Term Stability orTemperature Dependency
for acc. gradient+/- 1% in Amplitude+/- 1 deg. in Phase

Required Stability
Our target value of the stability

for LLRF System+/- 0.3% in Amplitude+/- 0.3 deg. in Phase(pk-pk)Ambient Temperature Change : about +/- 2 deg.C

Acceptable
Temp. Coefficient

0.1%/deg.C in Amplitude
0.1 deg./deg.C in Phase
LLRF system total

Measured Result

Amplitude: 0.5 % / deg.C
Phase: 0.25 deg. / deg.C
Requirements are not satisfied.

10 /17

Countermeasure for Temperature Dependency
From the evaluation of each RF element device,
It was found that the BPF property is main factor for the temperature dependency.
However, BPF is essential in the LO generation and pick-up RF monitoring.

508.9 MHz

Ref

LLRF System

508.9 MHz

LO & CLK Distributor

LORef

BPF

1/8

CLKFPGA

42.4 MHz519.5 MHzAppropriate BPF, of which
temperature coefficient islower, will be selected asmuch as possible.

RF1/12IF
TVA

ADC

IQ

IQ-Mod.

ch1

IF 10.6 MHz
TVA

ADC
ch4

508.9 MHz-PICont.

φcav

DAC
OutCavity“Thermal Variable Attenuators (TVA)” will beinserted here to compensate amplitude change.

Amplitude

IQ−φref

DAC

For the phase stability, Directly reference signal
is monitored together on FPGA, and the FBcontrol will be calibrated with the reference.

Phase

0.09 % / deg.C

Expected Value

0.04 deg. / deg.C

Improvement will be verified in next test model.

11 /17

ARES 100W Drive Test for FB & Tuner Control
10V
1kHz

-1 Mode FB

I/Q Mod.

RF:508.9MHz

Tuner
Cont. PTG
(S)

1/6

CLK

1/2

CLK
1/4 42.4MHzPTG(A)

P-gainP-gainΔΦ(s-g)

ΔΦ
(a-c)

DAC

ADC ADC

Detuneoffset+100W
Driver Amp

C-DmprTuner

FF- Q+-Ref-Q-Monitor Signals
508.9MHz

Selector

ADC

Rot.

Rot.

I,Q

I,Q

ADC

ADC

IF
10.6MHzLO

LO:519.5MHz

S-Cav

RFSW

FB
Cont.

A-Cav

PI - Cont.

Ref-I

CLK

LO

DAC

Tuner

Inter Lock

RotationRot. Rot. Rot. Rot.
I,QI,Q I,Q I,Q
ADC

Q

I

FF- I

84.8MHzLO & CLK
Distributor

ARES Cavity

508.8MHz

Combiner

RF Reference
508.9 MHz

cw/ccw

Tuner Drivercw/ccw

LLRF SystemLO

KLYout FWD
A-Cav PickUp (a)C-Cav PickUp (c)S-Cav PickUp (s)Cav-Input (g)12 /17

Running Test of ARES Auto Tuningby 100W Driving (not High Power)
Trend graph for 2 days
Cavity Temperature

Tuning Phase( Cavity Transmission Phase)

S-cav Tuner Pos.
S-cav Tuner Pos.

Cavity Temperature+/- 0.5 deg.

Tuning Phase
S-Cav & A-Cav

A-cav Tuner Pos.
A-cav Tuner Pos.

Cavity temperature change is small. (It is maybe due to ambient temperature.)
Also tuner moved slightly to keep tuning. This tuner position change
corresponds to about 15 degrees of the storage cavity.
Auto tuner controller of FPGA board worked successfully.

13 /17

#"%

RF Reference Distribution

78>.0#"$!
The details are under consideration now.
(4)19=:;$D1!

$D2

5

Design Concept• Optical Distribution（Master OSC. -> E/O -> O/E）

5

• Phase Stabilized Optical Fiber (PSOF) will be
D4

D11Central
6=9<>;
Control Bldg.

D10

D8

D7#
Opt.
Receiver System

Opt.
Transmitter System#Damping Ring2.
Damping Ring

D5used.

• The PSOF cables will be transferred in the acc.
tunnel. (Temperature stability : +/- 1 deg.C)#by means of “Star” configuration.
• Distributed• Phase# FB control will be implemented tocompensate temperature drift of the cable ifnecessary.

Damping Ring

B700m
Present reference system is maintained for the backup.
14 /17

Optical Reference Transmitter & Receiver
Opt. Signal

Central Control Bldg.

OpticalAmplifier
E/O

Optical Divider

OpticalDelay Line

Temp. Chamber
508.9MHz
Master OSC.

ODL

RF Station(LLRF Cont. Room)
WDM

WDM

O/E

-ΔΦ

O/E

2ΔΦ
P/D

LLRF

O/E
λ2

O/E
P/D

λ1

ODL

O/E

DividerElec. (RF) Signal

PSOF

P/D

Temp. ChamberWDM : Wavelength Division Multiplexing
PSOF : Phase Stabilized Optical Fiber
ODL: Optical Delay Line (like a trombone)
E/O : Optical Transmitter
O/E : Optical Receiver
P/D : Phase Detector

As the phase detector, digital direct sampling method is proposed.
Temperature of the transceiver system should be stabilized.
Validity of these method and components will be studied andthe specification will be fixed next fiscal year.

15 /17

Schedule of Production and Installation
FY2012123456FY2013
789 10 11 12123456FY2014
78

9 10 11 12123456789 10 11 12Acc. Operation
Total Operation Test
Beam Commissioning

LLRF System
β-version Production
β-version Test @ D4Quantity Production
Installation & Op.Test @ D5 ( 6 Systems)
The other stations depend on the budget.

Damping Ring LLRF
DesignBasically same as MR one,
3-Cavity Vector Sum Cont.

Production
Installation & Op. Test

Reference Distribution
R&D of Transmitter & Receiver System
Opt. Cable Installation
Production
Installation & Op. Test

• β-version (final test model) is under production now and will be evaluated at D4 from April this year.
• 6 new systems (actual operation model) will be produced and installed in D5 station in FY2013.
Additional production & installation for the other station will rely on the budget.

• DR-LLRF system also will be designed next fiscal year and will be produced in FY2013.
• For the reference distribution, the design detail will be studied and fixed next fiscal year, and theinstallation will be in FY2013. Optical cables will be installed next year.
16 /17

Summary• Prototype of the digital LLRF system for the SuperKEKB wasdeveloped, and Its performance was evaluated.

• Very good stability of is obtained in FB control. (0.03% in amp. & 0.02
deg. in phase)• But, temperature dependency is not negligible. Some countermeasures
should be studied.

• Auto Tuner Control given by the FPGA works successfully. ( Piezo tuner
control is not yet tested.)• Optical RF reference distribution system is under consideration. The
detail specification will be fixed next fiscal year.
Next model for the quantity production (β version)is in the process of fabrication now.
17 /17

Thank you for your attention !

18 /17

Followed by Backup Slides

19 /17

Low-level RF for KEKB Superconducting cavity

KEKB-LLRF System (Present)interlocks

from RFreference line

Phase Lock Loop
combiner for klystron

klystron circulator

Tuning Control Loop

SWoutout

FBC

FBC

FBC

FB

ref.

φ det.

FBref.

FB

φ det.

FBC

Present LLRF
System of the KEKB
( for one klystron )TunerController

FBklystron out

tuner

out

FBC
Vc set

KLYcont.
Gain
Controlfor klystron
Lop

outK. Akai et al. / Nuclear Instruments and Methods in Physics Research A 499 (2003) 45–65

ref.
offsetφ det.

DLbeamFBcavity

Direct RF
RF Feedback
DirectFeedackSWpick up (Vc)

Amplitude
Amplitudecont.
Control Loopfor Vc

Fig. 2. RF station for the SCC cavities.

Phase Lock Loop for Vc

Phase Lock Loop

RF input

S-cav

A-cav

coupling
accelerating
cavitycavitystorage cavity

ARES Tuner Control
Configuration

c-dampers-tuner

BPF(RF ON)

beam signal

BPF

ref.

outa-tuner
BPF

BPF

BPF

φsg
φsb(RF OFF)φacfor ALC and PLL

Fig. 3. Tuning control.

20 /17

The -1 mode feedback• Beam current was limited due to the -1 mode
instability at 1 A in LER and 1.2 A in HER, muchlower current than expected.
• The -1 mode digital feedback selectively reduces
impedance at the driving frequency.
• After the -1 mode feedback was installed, thebeam current could be successfully increased.

1600
1400
1200
1000

Stored beam current

800
600
400
200
0

Feedback off
3:30 PM
03.6.30

Feedback on

3:45 PM

4:00 PMDate

FB OFFƒrf - ƒrev-40

ƒrf - ƒrev + ƒs

(a)

-0.97

-0.95

-60
-80
-100
-120-1

-0.99

-0.98

-0.96

Frequency Δƒ/ƒrev

-1 mode sideband

FB ON
ƒrf - ƒrev-40(b)-60ƒrf - ƒrev + ƒs-80-100-1-0.99

-0.98

-0.97

-0.96

Frequency Δƒ/ƒrev-0.95

21 /17KEB RF Reference System
Tsukuba

LLRF

LLRF

Nikko

Control Room
LLRF

MR OSC.

Oho
LLRF

LLRF

Linac
LLRF

Master OSC.

Fuji
Transmitter
ReceiverPhase Detector

22 /17

DFT of the waveform
1.05MS/s, 4096 points (~ 4-ms duration)
10 acquisitions are superimposed.

Amplitude< 0.03% (rms)Phase< 0.02 deg. (rms)20

FFT270kHz
Due to the latency of the FPGA
and DAC, which makes 650nsloop delay.
No problem for the ARES
Cavity (QL~20000).

1510-100 dBc
50Δf ~ 256
Hz5000524kHz
1000

1500

200023 /17

Bode Plot for the Simulant Cavity(QL~3000)
Amplitude @dBD
10Pgain=2, Igain=2.6x104
10k

100k

1M

Delay:700ns

0-10Gain

Delay:400ns-40
Phase@deg.D
180
90
Phase
0

Closed Loop
10k

100k

Loop Delay = 700ns
Latency in the FPGA :55 clock-20-30Frequency @HzD
10M

QL=3000 Δω = 0

1M

Frequency @HzD
10M

Loop Delay :~650nsGain Mergin :~13dB-90

Pmax ~2.2-180

24 /17

Bode Plot for the ARES
(QL~20000)
Amplitude @dBD
10Pgain=2, Igain=2x105
10k

100k

1M

Frequency @HzD
10M

Closed Loop

0QL=20000 Δω = 0(Q0=120000, Coupling=5)-10Gain

Loop Delay = 3us-20-30

Open Loop-40

Phase@deg.D
18090
Phase

10k

100k

1M

Frequency @HzD
10M

Gain Mergin :~18dB
Pmax ~40-90

25 /17

RF & ARC Inter Lockα version

Analogue comparator is used for I/LDET
RF I/L+-x 8ch
ARC I/L Optical Fiberto PLC AD module
Alarm to RFSW-OFF
Threshold form PLC-DAC

PD+-x 8chAlarm to RFSW-OFF
Thresholdβ version

Detector output is sampled by
ADC at 42-MHz Clock on FPGA.

DETRF I/LFPGA (for RF-I/L)
ADC comp.

x 8ch
ARC I/L Optical Fiberx 8ch

Sampled waveform can be read as
EPICS record.

Alarm to RFSW-OFF

x 8ch ADCPDFPGA (for ARC-I/L)
ADC comp.

Alarm to RFSW-OFF

x 8ch ADC
26 /17