Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT1123-KMM
DC-64Gbps Broadband Digital DDR 4:1 Multiplexer

Ideal for high speed proof-of-concept prototyping

Differential CML I/O data and clock buffersHalf-rate clock input (DDR mode)Quarter-rate clock output

Single +3.3V or -3.3V power supplyPower consumption: 1.15W

Fabricated in SiGe for high performance, yield, and reliability

Custom CQFP 44-pin packagevccveevcc
d1p
vcc
d1n
vcc

vcc
n/c
vcc
qp

ASNT1123-KMM
ASNT1123

d2p
vcc
d2n
vcc

vcc
qn
vcc

1cepvcc
cenvcc

vcc
d3n
vcc

n/c
vcc
veevccvcc
veevccd3p

Rev. 1.7.2

vee
vcc

Exhibits low jitter and limited temperature variation over industrial temperature range

vcc
c4op
vcc

d0n
vcc
d0p
vcc
c4on

High speed broadband 4:1 Multiplexer (MUX)

vcc

January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
vcc
d0pd0nd1pd1nvcc
qpqn

d2pd2nd3pd3nvcc
cepcenDIV

c4op
c4onFig. 1. Functional Block Diagram

The ASNT1123-KMM SiGe IC is a low power and high-speed digital 4 to 1 serializer-multiplexer(MUX) that functions seamlessly over data rates (fbit) ranging from DC to its maximum frequency.
The main function of the part shown in Fig. 1 is to multiplex 4 parallel differential CML data signals
d0p/d0n, d1p/d1n, d2p/d2n, d3p/d3n running at a bit rate of fbit/4 into a high speed serial bit stream
qp/qn running at a bit rate of fbit. Differential or single-ended half-rate clock cep/cen (DDR mode) must
be provided by an external source for the part to function properly.
The serialized data words qp/qn and the clock divided-by-4 signal c4op/c4on are transmitted through
CML output interfaces. The clock and data outputs are phase-matched to each other resulting in very little
relative skew over the operating temperature range of the device.
The input data streams should be phase-aligned to the output c4 clock as shown in Fig. 2 and Table 1.
tholdthold

c4op

tsetuptsetupd0p,d1p,d2p,d3p
Fig. 2. Input Data Alignment to Output c4 Clock

Rev. 1.7.2

2January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Table 1. Input Data to Output c4 Clock Phase Requirements

Maximum required tsetup, ps25

Maximum required thold, ps-16

The output data is then delayed in relation to the input half-rate clock as shown in Fig. 3 and Table 2.

tD

cep

qptD
Fig. 3. Output Data to Input Clock DelayTable 2. Output Data to Input Clock Delay Values (DDR Mode)

Minimum tD, ps Maximum tD, ps60
118
The part’s I/O’s support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should complywith the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.

POWER SUPPLY CONFIGURATION
The part can operate with either negative supply (vcc = 0.0V = ground and vee = −3.3V), or positivesupply (vcc = +3.3V and vee = 0.0V = ground). In case of the positive supply, all I/Os need ACtermination when connected to any devices with 50Ohm termination to ground. Different PCB layouts
will be needed for each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.
Rev. 1.7.2

3January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 3 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground.
Table 3. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010

Max-3.6
1.3
1.4+90+1009898

Units
VW
VºCºC%%TERMINAL FUNCTIONSTERMINAL
NameNo.
Typed0pd0nd1pd1nd2pd2nd3pd3nc4op
c4on
cep
cen
qp
qnNamevcc
veen/cRev. 1.7.2

DESCRIPTION

Low-Speed I/Os
Differential quarter-rate data inputs with internal SE 50Ohm
termination to vcc
Differential quarter-rate data inputs with internal SE 50Ohm
termination to vcc
Differential quarter-rate data inputs with internal SE 50Ohm
termination to vcc
Differential quarter-rate data inputs with internal SE 50Ohm
termination to vcc
Differential quater-rate clock outputs with internal SE 50Ohm
termination to vcc. Require external SE 50Ohm termination to vcc
High-Speed I/Os
8
CML Differential half-rate clock input signals with internal 50Ohm
input termination to vcc
1019
CML Differential full-rate data outputs with internal SE 50Ohm
output termination to vcc. Require external SE 50Ohm termination to vcc
17
Supply and Termination Voltages
Description
Pin Number
Positive power supply
1, 3, 5, 7, 9, 11, 12, 14, 16, 18, 20, 22, 23, 25, 27, 29,(+3.3V or 0)
31, 33, 34, 36, 38, 40, 42, 44
Negative power supply
2, 13, 24, 35(0V or -3.3V)
Not connected pins
15, 21303237394143462628

CML
input
CML
input
CML
input
CML
input
CMLoutput

4January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERMIN

TYP MAX UNIT
COMMENTS
General Parameters-3.1-3.3-3.5
V
±6%
vee
0.0
V
Externalground
vcc
Ivee
347mA
Power consumption
1.15
W
Junction temperature -40
25125°C
LS Input Data (d0p/d0n, d1p/d1n, d2p/d2n, d3p/d3n)
Data Rate
DC1016Gb/s
Swing
0.20.8V
Differential or SE, p-p
CM Voltage Level
vcc-0.8
vcc
VMust match for both inputs
HS Input Clock (cep/cen)Frequency
DC2032GHz
Swing
0.20.8V
Differential or SE, p-p
CM Voltage Level
vcc-0.8
vcc
VMust match for both inputs
Duty Cycle
405060%HS Output Data (qp/qn)
Data Rate
DC4064
Gb/s
Logic “1” level
Vvcc
Logic “0” levelvcc-0.4
V
With external 50Ohm DC termination
Output Jitter2psPeak-to-peak at 40Gb/s
LS Output Clock (c4op/c4on)
Frequency
DC1016GHz
Logic “1” level
Vvcc
Logic “0” levelvcc-0.4
VWith external 50Ohm DC termination
Duty Cycle
50%
Output Jitter1ps
Peak-to-peak at 10GHz

PACKAGE INFORMATIONThe chip die is housed in a custom 44-pin CQFP package shown in Fig. 4. The package provides a center
heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for thissection to be soldered to the vcc plain, which is ground for a negative supply, or power for a positive
supply.
The part’s identification label is ASNT1123-KMM. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.
Rev. 1.7.2

5January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Fig. 4. CQFP 44-Pin Package Drawing (All Dimensions in mm)

Rev. 1.7.2

6January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.7.2
1.6.2
1.6.1
1.5.1
1.4.1

Date
01-2020
07-2019
05-2019
05-2015
01-2014

1.3.1

02-2013

1.2.1
1.1.1
1.0.1

01-201301-201301-2013

Rev. 1.7.2

Changes
Updated Package Information
Updated Letterhead
Added timing diagrams
Updated Package Information
Title correction
Corrected Electrical Characteristics
Title correction
Corrected description
Corrected Terminal Functions table
Corrected Electrical Characteristics
Updated Package Information
Updated Maximum speed
Updated power and current consumption
First release

7January 2020