Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT2110D-KMF
Programmable CDR DMUX 1-to-2
1:2 demultiplexer (DMUX) with integrated full-rate CDRInput data range from DC to 32.5Gb/s



Digital operational mode with DC to 32.5GHz external clock

CDR locking range from 25.2Gb/s to 32.0Gb/s



RZ and NRZ input data formats

Adjustable time of data sampling point for optimum BER performance

CML compliant differential input and output high-speed data and clock interfaces

LVDS compliant input reference clock interface

Full rate clock and retimed data output for 1:1 CDR operation

Half rate data outputs with toggle synchronization functionality

Signal inversion and muting capabilities in all output buffers

Single +3.3V or -3.3V power supply

Low power consumption of 1.6W at the maximum operational speedIndustrial temperature rangeCustom CQFP 64-pin package
vee
vcc
dop
vcc
don
vcc
ondo
pol
tog
onco
vcc
c2p
vcc
c2n
vcc
vee



ASNT2110
ASNT2110D

vee
vcc
q0p
vcc
q0n
vcc
ond2o
lolp
icph
icpl
vcc
q1p
vcc
q1n
vcc
vee

vee
vcc
cep
vcc
cen
vcc
vcos1
ftr
is
vcos0
vcc
c32p
vcc
c32n
vcc
vee

vee
vee
pkdtp
pkdtn
dcinp
vcc
vcc
dp
vcc
dn
vcc
vcc
dcinn
phshftvee
veeRev. 1.0.2

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DESCRIPTION
ondo
ce
ond2o
d
dcinp
dcinn
pkdt
c32

HS
CIB

DOB

D

Data
IB

DMX
1:2

CDR
CLK
IB

do

D2OB
x2

q1

C2

lolp
fltp
phshft
icph
icpl
vcos0
vcos1
tog
pol
onco

q0

COB

c2

Fig. 1. Functional Block Diagram

ASNT2110D-KMF is a 1:2 demultiplexer (DMUX) with full-rate integrated clock and data recovery(CDR). The IC shown in Fig. 1 can function in either CDR mode covering a wide range of input data
rates (fbit) by utilizing its three on-chip VCOs (voltage-controlled oscillators), or in a broadband digitalmode. Selection of the desired working data rate and mode is accomplished through pins vcos0 andvcos1 (see Table 1). An external low speed system clock c32p/c32n running at 1/32 the frequency of theactive VCO must be applied to the low-speed LVDS clock input buffer (CLK IB) in CDR mode. An
external full-rate clock cep/cen must be applied to the high speed CML clock input buffer (HS CIB) for
digital operation.
The main function of the chip is to convert a RZ or NRZ input data signal dp/dn with a bit rate of fbit
accepted by CML buffer (Data IB) into 2 parallel NRZ data signals q0p/q0n and q1p/q1n running at bit
rates of fbit/2 and delivered to the outputs by CML data output buffers (D2OBx2). The clock and data arerecovered from the input data stream by the CDR. The phase of the clock recovered by the CDR can be
adjusted externally through pin phshft to locate the optimum data sampling point and achieve the lowest
system bit error rate (BER).
A full rate retimed NRZ data output signal dop/don is also available through the CML data output buffer(DOB) allowing the part to be used as a 1:1 CDR. Half rate clock c2p/c2n delivered through the CML
clock output buffer (COB) has a tight phase alignment to the demultiplexed data output signals q0p/q0n
and q1p/q1n.
Rev. 1.0.2

2

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Data IB can operate with either differential or single-ended input signals. It includes tuning pins
dcinp/dcinn for DC offset of the input signals in case of AC termination. When the buffer is operatingwith a DC-terminated single ended input signal, a correct threshold voltage should be applied to theunused input pin. A peak detector is also included to provide means of demodulating AM components
carried by the input data with frequency ranges of up to a few hundred KHz. The peak detector’s output
signal is delivered to the differential port pkdtp/pkdtn.
All CML I/Os provide on chip 50Ohm termination to vcc and may be used differentially, AC/DC
coupled, single-ended, or in any combination (see also POWER SUPPLY CONFIGURATION). Output
buffers DOB, COB, and D2OBx2 can be individually disabled through pins ondo, onco, and ond2o tosave power.
Utilizing pin pol, the deserializer can invert the polarity of the three output data signals. Pin tog flips theorder of q0p/q0n and q1p/q1n signals thus simplifying the interface between the DMUX and a following
ASIC. It also allows for synchronization of the bit order of two or more DMUXes working in parallel.
A loss of lock CMOS alarm signal lolp is generated by the CDR to indicate its locking state. An off chippassive filter is required by the CDR, and should be connected to pin ftr (see CDR).
The deserializer is characterized for operation from 0°C to 125°C of junction temperature. The package
temperature resistance is 15°C /W.

Data IBThe Data Input Buffer (Data IB) can process an input CML data signal dp/dn in either RZ or NRZ format
due to its high analog bandwidth. It provides on-chip single-ended termination of 50Ohm to vcc for each
input line. The buffer can also accept a single-ended signal to one of its input ports dp or dn with athreshold voltage applied to the unused pin in case of DC termination. In case of AC termination, tuning
pins dcinp/dcinn allow for data common mode adjustment. The tuning pins have 1KOhm terminations to
vcc and allow the user to change the slicing level before the data is sampled by the recovered clock.
Tuning voltages from vcc to vee deliver 150mV of DC voltage shift.
Also included in Data IB is an input signal peak detector that delivers its response through the output
differential signal pkdtp/pkdetn. The detector can demodulate AM component(s) carried by the input
data with frequency ranges of up to a few hundred KHz. The detector’s output impedance is 4KOhm
single ended to vcc.

HS CIBThe High-Speed Clock Input Buffer (HS CIB) can process either differential or single-ended external
CML clock signals cep/cen. In single-ended mode, the clock is applied to one of the pins together with athreshold voltage applied to the unused pin. The buffer utilizes on-chip single-ended termination of
50Ohm to vcc for each input line.

CLK IBThe Clock Input Buffer (CLK IB) consists of a proprietary universal input buffer (UIB) that exceeds
LVDS standards IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. UIB is designed to accept
differential signals with a speed up to 1Gb/s, DC common mode voltage variation between vcc and vee,Rev. 1.0.2
3
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AC common mode noise with a frequency up to 5MHz, and voltage levels ranging from 0 to 2.4V. It canalso receive a DC-terminated single-ended signal with a threshold voltage between vcc and vee applied
to the unused pin. The input termination impedance is set to 100Ohm differential.

CDR
The Clock and Data Recovery Block (CDR) contains both a phase and frequency acquisition loop. The
frequency loop works in concert with low-speed clock c32p/c32n while the phase loop utilizes data
signal dp/dn. The CDR requires a single off-chip filter shown in Fig. 2 to be connected to pin ftr.

66Ohm
ftr
390pF

22nF

Fig. 2. External Loop Filter

The main function of the CDR is to frequency-lock the selected on-chip VCO to the input data signal(clock recovery) while phase-aligning it to latch in the incoming data with minimal error (data recovery).
By default, the CDR aligns the recovered clock’s working edge in the middle of the incoming data bits. A
DC voltage from vee to vcc applied to pin phshft can be utilized to shift this position from one edge ofthe data bit to the other in order to locate the optimum sampling point which provides the lowest system
BER. The recovered clock is divided down in frequency by two (C2) and utilized by DMX 1:2 fordemultiplexation of the recovered data.
By utilizing the 2.5V CMOS control pins vcos0 and vcos1, the desired working frequency of the CDR
can be selected in accordance with Table 1 below.
Table 1. CDR Mode Selection (Case Temperature from 0 to 90°C)

vcos0
vcos1
VCO Operation Frequency (GHz)“0” (0V)“0” (0V)
fmin≤25.2, fmax≥28.0“0” (0V) ”1” (2.5V)
fmin≤27.5, fmax≥29.5”1” (2.5V) “0” (0V)fmin≤29.0, fmax≥32.0”1” (2.5V) ”1” (2.5V)
Digital Mode, default state
The loop gain can be adjusted by two 2.5V CMOS control pins icph and icpl that control the charge pumpcurrent as shown in Table 2.
Table 2. Charge Pump Current Control

icph
icpl
Charge Pump current, mA“0” (0V)“0” (0V)Imax“0” (0V) ”1” (2.5V)
Imax-0.04”1” (2.5V) “0” (0V)
Imax-0.27”1” (2.5V) ”1” (2.5V)
Imax-0.31

Rev. 1.0.2

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The lock detect circuitry signals an alarm through the 2.5V CMOS signal lolp when a frequency
difference exists between an applied system reference clock c32p/c32n and a recovered full rate clock
divided-by-32 that is greater than ±1000ppm.
Another feature included in the CDR is the ability to simultaneously invert the polarity of all three data
outputs through the 2.5V CMOS input pin pol (pol = “1” (default): direct; pol = “0”: inverted). The orderof the half-rate output data streams can be inverted by using the 2.5V CMOS input pin tog, which
provides means to synchronize two adjacent DMUXes operating in parallel. The synchronization process
may be accomplished by the “blind” toggling in one of the chips and leaving the task of recognizing the“right” position to downstream components (e.g. FEC chip).

DMX1:2
The 1 to 2 Demultiplexer (DMX1:2) latches in the retimed data stream D from the CDR on both edges of
the half rate clock signal C2. The high speed data signal is subsequently demultiplexed into two half rate
NRZ data signals and delivered to D2OBx2 in parallel fashion as a 2-bit wide word with the order definedby the tog signal.

DOB
The Data Output Buffer (DOB) receives a full rate retimed serial data stream D from the CDR andconverts it into a CML output signal dop/don. This CML buffer requires 50Ohm external termination
resistors connected between vcc and each output. The buffer can be enabled or disabled by the external
2.5V CMOS control signal ondo (ondo = “1” (default): enabled; ondo = “0”: disabled).

D2OBx2
The Half Rate Data Output Buffer (D2OBx2) receives two half rate data signals from DMX1:2 andconverts them into CML output signals q0p/q0n and q1p/q1n. The buffer requires 50Ohm externaltermination resistors connected between vcc and each output. The buffer can be enabled or disabled by
the external 2.5V CMOS control signal ond2o (ond2o = “1” (default): enabled; ond2o = “0”: disabled).

COB
The Clock Output Buffer (COB) receives a half rate clock signal from DMX1:2 and converts it into CML
output signal c2p/c2n. The buffer requires 50Ohm external termination resistors connected between vcc
and each output. The buffer can be enabled or disabled by the external 2.5V CMOS control signal onco
(onco = “1” (default): enabled; onco = “0”: disabled). The negative edge of the c2 signal is aligned to thehalf rate output data crossing points.

POWER SUPPLY CONFIGURATIONThe ASNT2110D-KMF can operate with either a negative supply (vcc = 0.0V = ground and vee = -3.3V),or a positive supply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os needAC termination when connected to any devices with 50Ohm termination to ground. Different PCB layouts
will be needed for each different power supply combination.

All the characteristics detailed below assume vcc = 3.3V and vee = 0V (external
ground)Rev. 1.0.2

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ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 3 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only that are specified in ELECTRICAL
CHARACTERISTICS. AC and DC device characteristics at or beyond the absolute maximum ratings are
not assumed or implied. All min and max voltage limits are referenced to ground (assumed vee).
Table 3. Absolute Maximum Ratings

Parameter
Min
Max
Units
Supply Voltage (vcc)+3.8
VPower Consumption
1.6
W
Input Voltage Swing (SE)
1.0
V
Case Temperature*)+90ºC
Storage Temperature
-40
+100
ºC
Operational Humidity
1098%
Storage Humidity
1098%*) - Operating the part at temperatures over this value could/will damage the part. Operating at thistemperatureor

any temperatures

above

the recommended maximum value specified in
ELECTRICAL CHARACTERISTICS does not guarantee correct functionality as is statedabove.

TERMINAL FUNCTIONS
Name
vcc
vee

Name

Supply and Termination Voltages
Description
Pin Number
Positive power supply (+3.3V)
2, 4, 6, 11, 13, 15, 18, 20, 22, 27, 29, 31, 34, 36,
38, 43, 45, 47, 54, 55, 57, 59, 60
Negative power supply (GND or 0V)
1, 16, 17, 32, 33, 48, 49, 50, 63, 64

TERMINAL
No.
Type

cep
cen
q1p
q1n
q0p
q0n
c2p
c2n
dop
don
dp
dn
Rev. 1.0.2

3
5
21
19
30
28
37
35
46
44
56
58

Input
OutputOutputOutputInput

DESCRIPTION
High-Speed I/Os
CML differential full rate clock inputs with internal SE 50Ohm
termination to vcc
CML differential half rate data outputs. Require external SE 50Ohm
termination to vcc

CML differential half rate clock outputs. Require external SE 50Ohm
termination to vcc
CML differential full rate data outputs. Require external SE 50Ohm
termination to vcc
CML differential data inputs with internal SE 50Ohm termination tovcc
6

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c32p
c32n
pkdtp
pkdtn

12
14
51
52

Input

Low-Speed I/Os
LVDS clock input with internal differential 100Ohm termination

OutputPeak detector outputs
Controls
CDR operational mode selection, see Table 1

vcos1
vcos0
is
icpl
icph
ond2o

7
LS In.,
10 2.5V CMOS
9
VCO current control (high, default: higher current; low: lower current)
23
Charge pump current control, see Table 224
26
D2OBx2 control (high, default: buffer is on; low: buffer is disabled)

onco

39

COB control (high, default: buffer is on; low: buffer is disabled)

tog
pol
ondo
lolp

40
41
42
25

Order inversion of output data signals (default: high)Data output signal polarity (high, default: inverted data outputs)
DOB control (high, default: buffer is on; low: buffer is disabled)
CDR lock indicator (high: no lock; low: locked)

LS out,2.5V CMOS53
LS IN
Input data common mode voltage adjustment
61
62
LS IN
CDR sampling point adjustment
8
I/O
External CDR filter connection

dcinp
dcinn
phshftftr

ELECTRICAL CHARACTERISTICSPARAMETER
vcc
vee
Ivcc
Power Consumption
Junction Temperature
Case temperature
Data Rate
Swing p-p (Diff or SE)
CM Voltage Level
Rev. 1.0.2

MIN

TYP MAX
UNIT
General Parameters
+3.0
+3.3
+3.6
V
0.0
V
490
mA
1.6
W
-25
50
125
°C
75
°C
HS Input Data (dp/dn)
DC
32.5
Gbps
25.2
32.0
Gbps
0.05
0.6
V
vcc-0.8
vcc
V
7

COMMENTS±9%
All functions active

Recommended value
Digital mode
CDR mode
at 32.5Gbps
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LS Input Reference Clock (c32p/c32n)
787.5
1015.625
MHz
0.06
0.8
V
V
vee
vcc
40
50
60
%
HS Output Full Rate Data (dop/don)
DC
32.5
Gbps
Digital mode
Data Rate
25.2
32.0
Gbps
CDR mode
Logic “1” levelV
vcc
Logic “0” levelvcc -0.4 vcc -0.3
V
Jitter
7
8
ps
HS Output Half Rate Data (q0p/q0n, q1p/q1n)
DC
16.25
Gbps
NRZ, Digital mode
Data Rate
12.6
16.0
Gbps
NRZ, CDR mode
Logic “1” levelV
vcc
Logic “0” levelvcc -0.4
V
Jitter7
ps
HS Output Half Rate Clock (c2p/c2n)
DC
16.25
GHz
Digital mode
Clock Rate
12.6
16.0
GHz
CDR mode
Logic “1” levelV
vcc
Logic “0” levelvcc -0.4
vcc -0.15
V
Jitter5
8
ps
Input Data Common Mode Control (dcinp/dcinn)
Input DC Voltage
V
vee
vcc
Input Data Voltage Shift
0
-150
mV
Referenced to vcc
Output of Peak Detector (pkdtp/pkdtn)
Swing p-p (Diff)-1
1
VOver full input range
CM Voltage Level
vcc -1.0
V
Data Sampling Point Adjustment (phshft)
Input DC Voltage
vcc -1.0
NC
vcc
V
NC=Not Connected
Phase Shift
-15
0
+15
ps
Shift Stability-22
ps
From 0°C to 125°C
Bandwidth
0.0
100
MHz
CMOS Control Inputs/Outputs
Logic “1” level
2.1
2.5
V
Logic “0” levelvee +0.4
V
Timing Parametersc2p/c2n to q0p/q0n &Over the full2
ps
q1p/q1n delay variation
temperature range
Frequency
Swing p-p (Diff or SE)
CM Voltage Level
Duty Cycle

Rev. 1.0.2

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PACKAGE INFORMATIONThe chip die is housed in a custom 64-pin CQFP package. The dimensioned drawings are shown in Fig. 3.

Fig. 3. CQFP 64-Pin Package Drawing (All Dimensions in mm)

Rev. 1.0.2

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The package’s leads will be trimmed to a length of 1.0mm. After trimming, the package’s leads will befurther processed as follows:
1. The lead’s gold plating will be removed per the following sections of J-STD-001D:
3.9.1 Solderability
3.2.2 Solder Purity Maintenance3.9.2 Solderability Maintenance3.9.3 Gold Removal
2. The leads will be tinned with Sn63Pb37 solder
The package provides a center heat slug located on its back side to be used for heat dissipation.
ADSANTEC recommends for this section to be soldered to the vcc plain, which is ground for a negative
supply, or power for a positive supply.
The part’s identification label is ASNT2110D-KMF. The first 9 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin out
count.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

REVISION HISTORY
Revision
1.0.2

Date
10-2020

0.1.2
0.0.2

04-2020
04-2020

Rev. 1.0.2

Changes
Corrected frequency range
Corrected short description (bullets)
Corrected filter schematic
Corrected Electrical Characteristics table
Corrected data rate and clock frequency
Preliminary release10

October 2020