A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

ASNT3010_QQB
2Gbps LVDS/CMOS/LVDS Converter and Signal Splitter•

2-channel LVDS-to-CMOS converter (Receiver).

•2-channel CMOS-to-LVDS converter (Transmitter).

•

Triple-action programmable LVDS/CML/ECL inputs.

•Optional DS (Data/Strobe) encoding/decoding for compatibility with Space Wire Standard.

•Optional signal splitter function with selectable inversion.

•Flexible selection of channels enabling and operational modes.

•High-impedance states of disabled CMOS outputs.

•Single +3.3V power supply.

•

Industrial temperature range.

•Power consumption: 115mW with all 4 channels enabled.

•

Package: 40-pin MLF with 6x6mm2 body size and 0.5mm lead pitch.

ASNT3010 BONDING DIAGRAM

Rev.: 05,September 2009.

ASNT3010_QQB

A D S A N T E C

A d v a n c e dS c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

Mux
2:1

CML toCMOS

qm1

RCB

crlr1
crlr2

CML toCMOS

qm2

CMOS
to CML

dm1

TCB

crlt1
crlt2

CMOS
to CML

dm2

DESCRIPTION
d1p
d1n

UIB

oncml
onecl
d2p
d2n

UIB

q1pq1n

LVDS

q2p
q2n

LVDS

Mux
2:1

Mux
2:1

Mux
2:1

ASNT3010 is a bi-directional 4-channel digital interface converter. It includes two independent“Receiver” channels with programmable LVDS/CML/ECL differential inputs (“d1p/n”, “d2p/n”)
and CMOS outputs (“qm1’, “qm2”), as well as two reverse “Transmitter” channels with CMOS
inputs (”dm1”, “dm2”) and LVDS differential outputs (“q1p/n”, “q2p/n”).
All channels can be independently enabled or disabled by control signals (“crlr1”, “crlr2”,“crlt1”, “crlt2”). When disabled, the CMOS output drivers are set to a high impedance (high-Z)
state. Both receiver and transmitter channel pairs can be combined into a Space Wire
receiver/transmitter with optional data/strobe (DS) encoding or decoding. The assignment of dataand strobe or data and clock signals to the individual channels is user-selectable.
Dual transmitter and/or receiver channels can be used for splitting one of the input signals into
two exact copies at two corresponding outputs. The signal at the second output can be inverted
using the second input as a selector (a differential DC signal must be applied). Detailed
instructions for using this operational mode are available on request.
The converter operates at data rates up to 2Gbps with a nominal power consumption of 115mW
from a single +3.3V power supply in a fully activated mode. The device is characterized for
operation from −25°C to 125°C of junction temperature.
The converter has an improved TID tolerance due to the HBT-based implementation.
Rev.: 05,

September 2009.

ASNT3010_QQB

A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

Universal IB
The proprietary Universal Input Buffer (UIB) is designed to accept differential signals withamplitudes higher than 60mV, DC common mode voltage variation between the negative andpositive supply voltages, and AC common mode noise with a frequency up to 5MHz and voltage
levels ranging from 0 to 2.4V. It can also receive single-ended signals with amplitudes of morethan 60mV and threshold voltages between the negative and positive supply rails. The buffer
outputs standard internal CML signals with amplitude of 220mV.
The buffer features a reconfigurable input block with internal LVDS, CML, or ECL terminationthat is controlled by two external CMOS signals “oncml” and “onecl” in accordance with thefollowing table.
“oncml”“onecl”
Termination
valuevalue
Type
Resistance Voltage
VCC
VEE (default) Single-ended (SE)
50Ohm VCC
VEE (default)
VCC
Single-ended (SE)
50Ohm VECLVEE (default) VEE (default)
Differential
100OhmThe ECL termination mode requires an external termination voltage of VECL=VCC-2V applied tothe pins labeled “vecl”. The buffer is set to work with incoming LVDS data by default.
CML-to-CMOS Converter
The CML-to-CMOS converter represents the output buffer of the Receiver. It includes a signal
converter based on the current mirror architecture and an output CMOS driver. The block
designed in a BiCMOS configuration operates at a data rate up to 2Gbps.
CMOS-to-CML Converter
The input CMOS-to-CML converter represents the input buffer of the Transmitter. It is designed
as a standard CML buffer with additional resistive dividers required for the handling of rail-torail CMOS signals.
LVDS Output Buffer
The proprietary LVDS output buffer utilizes NPN HBTs that are available in standard BiCMOStechnologies. It accepts the internal CML signals and converts them into output LVDS signals.
The buffert utilizes a special architecture that ensures operation at data rates up to 2Gbps with alow power consumption level of 19mW. The buffer satisfies all the requirements of the IEEE Std.
1596.3-1996 and ANSI/TIA/EIA-644-1995.
Internal Data Processing Circuitry
The internal parts of all 4 channels include an XOR and multiplexer 2:1 CML cells. Whenactivated, the XOR performs the DS encoding or decoding required by the Space Wire protocol,
while the multiplexer operates as a selector between the channel’s input signal or XORprocessed signals. The corresponding control signals are generated by the receiver or transmittercontrol blocks (RCB or TCB) from 3-state external activation control signals.
Each channel can function as an independent converter, as well as a data/strobe or clock/strobe
Space Wire encoder/decoder in accordance with the following table. In the second mode, thedevice can also perform the 1-to-2 data splitting operation (described in Application notes).
Rev.: 05,

September 2009.

ASNT3010_QQB

A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

“crlt1”/”crlr1” “crlt2”/”crlr2” Channel 1 (T or R) Channel 2 (T or R)
off
off
VEE
VEE
N/C (Default)
offon
VEE
offon
VEEVCCN/C (Default)
onoffVEE
N/C (Default) N/C (Default)onon
N/C (Default)
Data
Strobe/Clock
VCC
on
off
VCC
VEE
N/C (Default)
Strobe/Clock
Data
VCC
on
on
VCC
VCC

TERMINAL FUNCTIONS
Name

NumberType

DESCRIPTION

vcc
vee
veed
vecl
n/c
rfbL
rfb2_2rfb2_1
rfb1_1
rfp
crlt2
crlt1
crlr1
oncml
onecl
crlr2
vcm
dm2
dm1
qm2
qm1
d1p
d1n
d2p
d2n
q1p
q1n
q2p
q2n

3,8,16,22
2,6,10,17,25,29
21
28
1,11,30,40
4
523
24
71215
20
2627359131418193132333436373839

PSPSPSPS
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
DC voltage
Input
Input
OutputOutput
Input
Input
Input
Input
OutputOutputOutputOutputPositive power supply
Negative power supply (analog ground)
Digital ground
ECL input termination voltage
Floating package pin
Internal reference voltages. Used only in test
operational modes. For normal operation must beleft not connected.

Rev.: 05,

September 2009.

Transmitter channel 2 activation control signal
Transmitter channel 1 activation control signal
Receiver channel 1 activation control signal
Activation of the input CML termination mode
Activation of the input ECL termination mode
Receiver channel 2 activation control signal
CMOS input threshold voltage, default: (VCC+VEE)/2Transmitter channel 2 SE CMOS input
Transmitter channel 1 SE CMOS input
Receiver channel 2 SE CMOS output
Receiver channel 1 SE CMOS output
Receiver channel 1 LVDS direct input
Receiver channel 1 LVDS inverted input
Receiver channel 2 LVDS direct input
Receiver channel 2 LVDS inverted input
Transmitter channel 1 LVDS direct output
Transmitter channel 1 LVDS inverted output
Transmitter channel 2 LVDS direct output
Transmitter channel 2 LVDS inverted output

ASNT3010_QQB

A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

ELECTRICAL CHARACTERISTICSPARAMETER

MIN

VCC
VEE
VEED
VECL
Power consumption

3.14

Junction temperature

-25

TYP

MAX

UNIT

COMMENTS

General Parameters
3.3
0.0
0.0
VCC-2.07.0
20.0
115.0
50

3.47

125VVVVmW
mW
mW
°C

±5%
LVDS grownd
CMOS ground
1 Receiver channel, DC
1 Transmitter channel
Total

LVDS Inputs
Data Rate
DC common mode voltage
AC common mode voltage
Sensitivity

0.0
VEE
VEE

2.0
VCC
2.4
60

Gbps
VV
mV

DC voltage
AC signal <5MHz

CMOS Inputs
Frequency
Logic “1” level
Logic “0” level

0.0
VCC-0.4

1.0
0.4

Gbps
VV

LVDS Outputs
Voltage Swing
CM voltage
Impedance
Total current
Output current

320
1.277455.2
174.5

Rise/Fall Times1.25
122
115
5.727
7.0
TBD

mVV
Ohm
Ohm
mA
mA
mA
pS

Each SE output
DC testAC test (0-2Gbps)
From “vcc”
Shorted to VEE
Shorted together
20%-80%CMOS Outputs
Logic “1” level
Logic “0” level
Rise/Fall Times
Duty Cycle

VCC-0.2

Logic “1” level
Logic “0” level

VCC-0.4

0.2
45%

TBD
50%

VV
20%-to-80%

55%

CMOS Control Inputs
0.4

VV

PACKAGE INFORMATIONThe chip is packaged into the standard 40-pin QFN package. The package mechanicalinformation is available on the company’s website.
Rev.: 05,

September 2009.

ASNT3010_QQB