Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT2011-PQA
DC-17Gbps Digital Demultiplexer 1:16 / Deserializer
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Broadband digital deserializer 1-to-16
Low-power LVDS output data buffers with a proprietary architecture
Clock-divided-by-16 LVDS output buffer with 90°-step phase selection
Single +3.3V power supply
Industrial temperature range
Low power consumption of 730mW at the maximum speed
Standard 100-pin QFN package (12mm x 12mm)ncncncncnc

Rev. 2.4.2

1May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
bitordn
q00
dData
IB

DMX
1:16

16

LVDS
DOB
x16
q15

LVDS
COB
ce

HS
CIB

cls

CLK
Proc

/16

phs1
phs2
Fig. 1. Functional Block Diagram

ASNT2011-PQA is a low power and high-speed digital 1 to 16 demultiplexer / deserializer IC. The IC shown inFig. 1 can function seamlessly over input data rates (fbit) ranging from DC to 17Gbps.
The main function of ASNT2011-KMA is to demultiplex a serial input data channel d running at a bit rate of fbit
into 16 parallel data channels q00-q15 running at a bit rate of fbit/16. The high sensitivity data input buffer(Data IB) ensures accurate operation at low input data signal amplitudes. It provides on-chip 50Ohm
termination to vcc and is designed to be driven by devices with 50Ohm source impedance.
During normal operation, the received serial input data is latched into a tree-type demultiplexer DMX1:16 andsubsequently deserialized and delivered to the demultiplexer’s output as 16-bit wide low-speed parallel words.
The output MSB corresponds to q00 when bitordn=0 (default), or to q15 when bitordn=1.
A full rate clock must be provided by an external source ce to the high-speed clock input buffer HS CIB where
it is routed to the internal divider-by-16 (/16). The divider provides signaling for DMX1:16 and produces a fullrate clock divided-by-16 C16 for the low speed LVDS compliant clock output buffer LVDS COB. The phaseof cls can be modified by 90° increments by utilizing pins phs1 and phs2 and the clock processing block CLKProc.
Sixteen proprietary low-power LVDS output data buffers LVDS DOBx16 are used to deliver the 16 data output
signals q00-q15 while a similar LVDS clock output buffer LVDS COB outputs the low-speed clock signal cls.
The deserializer uses a single +3.3V power supply and is characterized for operation from −25°C to 125°C ofjunction temperature.
Rev. 2.4.2

2May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Data IBThe Data Input Buffer (Data IB) can process an input CML data signal d with bit rates from DC to fbit. It canalso accept a single-ended signal to one of its pins with a threshold voltage applied to the unused pin. Data IB
can handle a wide range of input signal amplitudes. The buffer utilizes on-chip single-ended termination of
50Ohm to vcc for each input line.

HS CIBThe High-Speed Clock Input Buffer (HS CIB) can process an external CML clock signal ce with frequencies
from DC to fbit. It can also accept a single-ended signal to one of its pins with a threshold voltage applied to theunused pin. HS CIB can handle a wide range of input signal amplitudes. The buffer utilizes on-chip singleended termination of 50Ohm to vcc for each input line.

/16
The Divider-by-16 (/16) includes 4 divide-by-2 circuits connected in series. The high-speed clock delivered by
HS CIB is fed into the first divide-by-2 where its output is routed internally to the next divide-by-two circuitand outside of the block to DMX1:16. Other divided down clock signals are formed and routed to DMX1:16 insimilar fashion. A full rate clock divided-by-16 C16 is passed on to CLK Proc for additional phase adjustment.

DMX1:16
The 1 to 16 Demultiplexer (DMX1:16) utilizes a tree type architecture that latches in the data stream from Data
IB on both edges of a half-rate clock signal supplied by the divider (/16). The high speed data signal issubsequently demultiplexed down and delivered to LVDS DOBx16 in parallel fashion as 16-bit wide words
running at a data rate up to fbit/16.

CLK Proc
By utilizing the CMOS control pins phs1 and phs2, the phase of cls can be altered as shown in Table 1.
Table 1. Output Clock Phase Selection

C16S phase
phs1
phs2
vee (default) vee (default)
270°
180°
veevcc
90°
vcc
vee
0°
vcc
vcc

LVDS DOBx16
The LVDS Data Output Buffer (LVDS DOBx16) accepts 16-bit wide words from DMX1:16 and converts theminto LVDS output signals. Each proprietary low-power LVDS output buffer utilizes a special architecture thatensures operation at bit rates up to 2Gb/s with a nominal output current of 3.5mA. The buffer satisfies all therequirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995 standards. The output MSB
corresponds to q00 when bitordn=0 (default), or to q15 when bitordn=1.

LVDS COB
The LVDS Clock Output Buffer (LVDS COB) receives C16 from CLK Proc and converts it into the LVDS
output signal cls. The proprietary low-power LVDS output buffer utilizes a special architecture that ensures
Rev. 2.4.2

3May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

operation at frequencies up to 2.0GHz with a nominal output current of 3.5mA. The buffer satisfies all therequirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995 standards.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 2 may cause damage to this product and/or
lead to reduced reliability. Functional performance is specified over the recommended operating conditions forpower supply and temperature only. AC and DC device characteristics at or beyond the absolute maximum
ratings are not assumed or implied. All min and max voltage limits are referenced to ground (assumed vee).
Table 2. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-40
1010

Max
+3.6
0.8
1.2
+90
+1009898UnitsVWVºCºC%%TERMINAL FUNCTIONSNamevccveenc

Supply And Termination Voltages
Description
Pin Number
Positive power supply
1, 7, 10, 13, 16, 29, 32, 35, 38, 41, 45, 49, 52, 55,(+3.3V)60, 63, 66, 69, 72, 78, 81, 84, 87, 92, 95, 98
Negative power supply
3, 17, 25, 50, 51, 58(GND or 0V)
Not connected pins
2, 4, 19, 20, 21, 22, 23, 24, 26, 27, 28, 30, 31, 33,34, 39, 40, 44, 46, 47, 48, 53, 54, 59, 73, 74, 75

TERMINAL
Name
No.
Type

Rev. 2.4.2

dpdncep
cen43
42
37
36

phs1
phs2
bitordr

57
56
18

DESCRIPTIONHigh-Speed I/Os
CML differential data inputs with internal SE 50Ohm
termination to vcc
Input CML differential clock inputs with internal SE 50Ohm
termination to vcc
Controls
LS In., Low-speed output clock phase selection (default: both low)
CMOS
LS In., Output bit order selection (active: high, q15 is MSB; default:
CMOS low, q00 is MSB)
Input

4May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

TERMINAL
NameNo.
TypeDESCRIPTIONLow-Speed I/Os

q00n
q00p
q01n
q01p
q02n
q02p
q03n
q03p
q04n
q04p
q05n
q05p
q06n
q06p
q07n
q07p
q08n
q08p
q09n
q09p
q10n
q10p
q11n
q11p
q12n
q12p
q13n
q13p
q14n
q14p
q15n
q15p
clsp
clsn

Rev. 2.4.2

121198
6
5
100
99
97
96
94
93
91
90
89
88
86
85
83
82
80
79
77
76
71
70
68
67
65
64
62
61
1415Output

LVDS data outputs

Output LVDS clock output, can transmit four different clock phases
as defined by phs1 and phs2

5May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERMIN
TYP MAXUNIT
COMMENTS
General Parameters+3.14+3.3+3.47
V
±5%
vcc
0.0
V
External ground
vee
Ivcc
220mA
Power consumption
730mW
Junction temperature-2550125°C
HS Input Data (dp/dn)
Data Rate
01718Gbps
Swing p-p (Diff or SE)
0.04
1.2
V
Peak-to-peak
CM Voltage Level
vcc -0.8vcc
V
HS Input Clock (cep/cen)Frequency
0.01718GHz
Swing p-p (Diff or SE)
0.2
1.2
V
Peak-to-peak
CM Voltage Level
vcc -0.8vcc
VDuty Cycle
405060%LS Output Data (q00p/q00n-q15p/q15n)
Data Rate
0.0
1063
1125
Mbps
Interface
LVDS
Meets the IEEE Std.
1596.3-1996
LS Output Clock (clsp/clsn)
Frequency
0.0
1063
1125
MHz
Interface
LVDS
Meets the IEEE Std.
1596.3-1996
CMOS Control Inputs/Outputs
Logic “1” levelvcc -0.4
V
Logic “0” level
vee+0.4
V
Timing Parameters
cls to q0-q15 delay±2.5%
Over the fullvariation
temperature range

Rev. 2.4.26May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATIONASNT2011
Fig. 2. Package Drawing

Even though the package provides a center heat slug located on the back side of the package to be used for heatdissipation, ADSANTEC does NOT recommend for this section to be soldered to the board. If the customer
wishes to solder it, it should be connected to the vee plain that is ground for the positive supply.
The part’s identification label is ASNT2011-PQA. The first 8 characters of the name before the dash identify
the bare die including general circuit family, fabrication technology, specific circuit type, and part version whilethe 3 characters after the dash represent the package’s manufacturer, type, and pin out count.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

Rev. 2.4.2

7May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
2.4.2
2.3.2
2.3.1

Date
05-2020
07-2019
10-2013

2.2.1

05-2013

2.1.1

09-20122.004-2012

1.001-2009

Rev. 2.4.2

Changes
Updated Package Information
Updated Letterhead
Corrected pin out drawing
Corrected terminal functions (vcc and nc pins)
Corrected input voltage characteristics
Corrected maximum ratings
Corrected input voltage range
Corrected format
Added package pin out drawing
Added absolute maximum ratings
Revised package information section
First release

8May 2020