Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT6101-KMM
53Gb/s - 26.5Gbaud/s PAM4 Signal Generator / Encoder

vcc

vcc
vee

vcc
1n
xadjn

xadjp

vcc

d1n

vcc

d1p

High-speed two input binary data signals to one PAM4 output signal
Adjustable data output amplitude for all 3 levels and eye quality control
Single-ended output data eye cross point adjustment
Opposite and parallel timing adjustment of the main clock vs. both data inputs
Fully differential CML input and output data, and clock interfaces
Single power supply of 3.6V
Average power consumption: 1.25W
Custom CQFP 44-pin packagevcc







vcc
vee
vcc

vcc

dlyadjvddshD

vcc

vcc

ci0p

qp

ASNT6101

vcc

vcc

ci0n

qn

vcc

vcc

skwadjvthvccvcc
vee

Rev.1.2.2

1

vcc

tune2

vcc

tune1

vcc

d2p

vcc

d2n

vcc

vee

vcc

vcc

February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION

ci0p/ci0n

Dly

Dly

Dly

Dly

skwadjdlyadjtune1
d1p/d1n

DFF

tune2

DOB

vddshDDD
qp/qn
xadjp/xadjn

d2p/d2n

DFF

vthFig. 1. Functional Block Diagram

The ASNT6101-KMM SiGe IC shown in Fig. 1 is a single lane PAM4 encoder. It takes twobinary input data signals d1p/d1n, and d2p/d2n, retimes them with the input clock ci0p/ci0n,
and then combines them into a 4 level output signal (PAM4) qp/qn. The input data rates in Gbps
should be equal to the input clock frequency in GHz. The output data symbol rate will be equal
to the input data symbol rate, but deliver twice the amount of data due to the multiple levels (i.e.
twice the input data bit rate). For example, if the input data and clock are at 20Gb/s, and 20GHz
respectively, then the output signal will be running at 40Gb/s-20Gbaud/s.
The input clock ci0p/ci0n is initially split into two identical paths comprising of several delay
adjustable stages. Using skwadj, the delays of the two clock paths can be changed with respect
to each other where one path’s delay is increased while the other path’s delay is decreased (oropposite). Both of the clock lanes can be delayed by more or less equal amounts using thecontrol pin dlyadj. These two adjustment pins allow for proper alignment of the clock to the two
input data signals at the two re-timing internal D-type flip flops DFF.
After the DFFs, the two signals are combined into a PAM4 signal where d1p/d1n is the MSB,
and d2p/d2n is the LSB. External pins tune1, and tune2 can be used to separately adjust theamplitudes of the 3 upper signal levels in the PAM4 signal (i.e. independently adjust the weightsof the MLB and the LSB). Pin tune1 adjusts the weight of d1p/d1n’s contribution to the PAM4
signal while pin tune2 adjusts the weight of d2p/d2n’s contribution. Pin vth can be used toadjust all 3 upper signals simultaneously, and can be considered the part’s output amplitudecontrol.
Further signal shaping can take place in the data output buffer DOB using control signals
vddshD, and xadjp/xadjn. Pin vddshD can improve the quality of the output eye by
Rev.1.2.2

2February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

increasing/decreasing under/overshoot. Differential analog control voltage xadjp/xadjn can beutilized to adjust the crossing points of single-ended output eyes. At the default state of xadjp =xadjn = 0V, the crossing points in both direct and inverted eyes should be centered. The crossing
points are moving up in the direct eye and down in the inverted eye if xadjp = -xadjn > 0, or in
the opposite directions if xadjp = -xadjn < 0.
The part’s I/Os support CML logic interface with on-chip 50Ohm termination to ground.
External 50Ohm termination is also required, and is usually provided by the adjacent IC or when
testing measurement instrumentation is used. DC-coupling for the data output ports is stronglyrecommended. The input ports can use DC or AC coupling. Differential input clock, and data arestrongly recommended.

TERMINAL FUNCTIONSTERMINAL
Name No. Typed1pd1nd2pd2nci0p
ci0nqpqn

3230643941
1917CMLInputs

Description
High-Speed I/Os
Differential high-speed data inputs
Differential high-speed data inputs
Differential high-speed clock inputs

CML Differential high-speed data outputs (PAM4)
Outputs
Analog Control Voltage Inputs
xadjp 28 Analog Output data eye cross point adjustment, differentialInputs
xadjn 26
withtune1 8Analog control amplitude adjustment MSB, SE
tune2 10 100kohm Analog control amplitude adjustment LSB, SE
vth15 termination Threshold voltage for the analog control maximum value adjustment
to vcc Adjustment of Delay 2 blocks, SE
dlyadj 37
skwadj 43
Adjustment of Delay 1 blocks, SE

Supply And Termination Voltages
Name
Description
Pin Numbervcc
Positive power supply
1, 3, 5, 7, 9, 11, 12, 14, 16, 18, 20, 22, 23,25, 27, 29, 31, 33, 34, 36, 38, 40, 42, 44
vee
Negative power supply
2, 13, 24, 35
vddshD Output data peaking adjustment
21Rev.1.2.2

3February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

POWER SUPPLY CONFIGURATION
The part can operate with either a negative supply (vcc = 0.0V=ground and vee = -3.6V), or apositive supply (vcc = +3.6V and vee = 0.0V=ground). In case of a positive supply, all I/Os needAC termination when connected to any devices with 50Ohm termination to ground. Different
PCB layouts will be needed for each different power supply combination.

All the characteristics detailed below assume vcc = +3.6V and vee = 0V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to thisproduct and/or lead to reduced reliability. Functional performance is specified over therecommended operating conditions for power supply and temperature only. AC and DC device
characteristics at or beyond the absolute maximum ratings are not assumed or implied. All minand max voltage limits are referenced to ground (assumed vee).
Table 1. Absolute Maximum Ratings

Parameter
Power Supply Voltage (vcc)
Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Rev.1.2.2

Min-4010104Max
4.0
1.36
1.2
+90+1009898Units
VW
VºCºC%%February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERTYP MAX UNIT
COMMENTS
General Parameters
3.4
3.6
3.8
Vvcc
0.0V
External groundveePower1.25WJunction temperature
050
100°C
Data inputs (dp/dn)
Rate
1.026.5 Gb/s
SE Swing
50200500mV
Peak-to-peak
CM Levelvcc-(SE swing)/2Clock input (ci0p/ci0n)Frequency
1.026.5 GHz
Any skwadj and dlyadj
SE Swing
50200500mV
Peak-to-peak
CM Levelvcc-(SE swing)/2
Data output (qp/qn)
Rate2.053Gbps
SE Swing
0.01250mV
Peak-to-peak
CM Level
vcc-0.1
vcc-0.75
V
Depends on the amplitude
Rise/Fall Times
121314
ps20%-80%
SE tuning ports (tune1, tune2, skwadj, dlyadj)
Linear control voltage
vcc-2
vcc
V
Switch-off threshold
vcc-2
VCross point control (xadjp/xadjn)
Differential voltage range vcc-8.0
vcc+8.0
V±4V at each input
CM Levelvcc
Current in/out of the pin+4 / -4mA at +4V / -4V
Threshold control (vth)
Voltage range
vcc-2
vcc
V
Externally Controlled Operational Ranges
Clock-to-Clock skew
-30+30ps
skwadj control
Clock and Data delay
0+45
ps
dlyadj control
Output eye cross point-25+25%of the eye amplitude
Variable supply voltages (vddshD)
Voltage range
2.8
3.6
V

Rev.1.2.2

MIN

5February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATIONThe chip die is housed in a custom 44-pin CQFP package. The dimensioned drawings are shownin Fig. 2. The package provides a center heat slug located on its back side to be used for heatdissipation. ADSANTEC recommends for this section to be soldered to the vcc plain, which isground for a negative supply, or power for a positive supply.
The part’s identification label is ASNT6101-KMM. The first 8 characters of the name before thedash identify the bare die including general circuit family, fabrication technology, specific circuit
type, and part version while the 3 characters after the dash represent the package’s manufacturer,type, and pin out count.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for
all ten substances.

Rev.1.2.2

6February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Fig. 2. CQFP 44-Pin Package Drawing (All Dimensions in mm)

Rev.1.2.2

7February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.2.2
1.1.2
1.1.1

Date
02-2020
07-2019
10-2016

1.0.1

01-2016

Rev.1.2.2

Changes
Updated Package Information
Updated Letterhead
Updated title specifications
Updated electrical characteristics
First release

8February 2020