Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT2124-KMM
DC-64Gbps Broadband Digital DDR 1:4 Demultiplexer

Differential CML I/O data and clock buffersHalf-rate clock input (DDR mode)External control of internal clock’s duty cycle

Quarter-rate clock output

Single +3.3V or -3.3V power supplyPower consumption: 1.25W

Fabricated in SiGe for high performance, yield, and reliability

Custom CQFP 44-pin packagevccveevccq1p
vcc
q1n
vcc

vcc
nc
vcc
dp

ASNT2124-KMM

q2p
vcc
q2n
vcc

vcc
dn
vcc

1

cep
vcc
cenvcc

vcc
q3n
vcc

dccp
vcc
dccn
vcc

vcc
veevccq3p
Rev. 1.2.2

vee
vcc

Exhibits low jitter and limited temperature variation over industrial temperature range

vcc
c4op
vcc

q0n
vcc
q0p
vcc
c4on

High speed broadband 1:4 Demultiplexer (DMUX)

vcc

May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
50 Ohm vcc
q0p
q0n
50 Ohm

vcc

q1p
q1n

dp
dn

q2pq2n50 Ohmq3p
q3n
vcc 50 Ohm
cepcen

c4op
c4on

DIV
50 Ohmdccp
dccn

50 Ohm1000 Ohm

Fig. 1. Functional Block Diagram

ASNT2124-KMM is a low power and high-speed digital 1-to-4 deserializer-demultiplexer (DMUX) thatfunctions seamlessly over data rates (fbit) ranging from DC to its maximum speed.
The main function of the part shown in Fig. 1 is to demultiplex an incoming high speed serial differential
CML data bit stream dp/dn running at a bit rate of fbit into 4 parallel data channels q0p/q0n, q1p/q1n,q2p/q2n, q3p/q3n running at a bit rate of fbit/4. Differential or single-ended half-rate clock cep/cen must
be provided by an external source for the part to function properly. The internal clock’s duty cycle can be
adjusted through analog ports dccp/dccn.
The parallel words and clock divided-by-4 c4op/c4on are transmitted through CML output interfaces.
The clock and data outputs are phase-matched to each other resulting in a very little relative skew over theoperating temperature range of the device.
The part’s I/O’s support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.

Rev. 1.2.2

2May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

HS CIBThe high-speed clock input buffer can accept high-speed clock signals at its differential CML input port
cep/cen. It can also accept a single-ended signal with a threshold voltage applied to the unused pin. HS
CIB can handle a wide range of input signal amplitudes. The buffer utilizes on-chip single-ended 50Ohm
termination to vcc for each input line.
The buffer includes two external DC analog ports dccp and dccn for adjustment of its output signal duty
cycle. By lowering the voltage of one of the ports below vcc while keeping the other one at vcc or notconnected, the common mode voltage of the corresponding clock input can be lowered below vcc. If bothcontrol inputs are left not connected the common mode voltages of both clock inputs are at vcc. The
dependence of either input clock common mode voltage on the control voltage is shown in Fig. 2.

Fig. 2. Dependence of cep (or cen) Common Mode Voltage on dccp (or dccn) Voltage

DMX4:1
The 1-to-4 internal demultiplexer utilizes a tree-type architecture which latches in the serial data stream
on both edges of the half-rate clock signal that is supplied by the on-chip divider (DIV). The 4-bit wide
data word is then delivered to the data output buffers.

Data OBs
The data output buffers receive high-speed data from DMX4:1 and convert them into differential CMLoutput signals q0p/q0n, q1p/q1n, q2p/q2n, and q3p/q3n. The buffers utilize internal 50Ohm loads tovcc and require matching 50Ohm external termination resistors to be connected from vcc to each output.

HS COBThe quarter-rate clock output buffer utilizes the same termination scheme as Data OB and can operate atits maximum frequency while producing a full single-ended CML output swing.

Rev. 1.2.2

3May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

POWER SUPPLY CONFIGURATION
The part can operate with either a negative supply (vcc = 0.0V = ground and vee = −3.3V), or a positivesupply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os need AC termination
when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be neededfor each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground.
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage TemperatureOperational Humidity
Storage Humidity

Rev. 1.2.2

Min-4010104Max-3.6
1.3
1.0+100+1009898UnitsVWVºCºC%%May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

TERMINAL FUNCTIONSTERMINAL
Name
No.
Typeq0pq0nq1pq1nq2pq2n
q3p
q3n
c4op
c4on
cepcendp
dn
dccp
dccn
Name
vcc
veenc

Rev. 1.2.2

DESCRIPTION

Low-Speed I/Os30
CML Differential quarter-rate data outputs. Require external SE
output50Ohm termination to vcc
3237
CMLoutput
3941
CMLoutput
43
4CMLoutput
626
CML Differential quarter-rate clock outputs. Require external SE
output 50Ohm termination to vcc
28
High-Speed I/Os
8
CML Differential half-rate clock input signals with internal 50Ohm
input termination to vcc
1019
CML Differential full-rate data input signals with internal 50Ohm
input termination to vcc
17Control Ports
15
Analog Differential or SE tuning ports with internal SE connections toinput dp/dn through 1000Ohm resistors
13Supply and Termination Voltages
Description
Pin Number
Positive power supply
1, 3, 5, 7, 9, 11, 12, 14, 16, 18, 20, 22, 23, 25, 27,(+3.3V or 0)
29, 31, 33, 34, 36, 38, 40, 42, 44
Negative power supply
2, 24, 35(0V or -3.3V)
Not connected pins
21

5May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERveevcc
Ivee
Power consumption
Junction temperature
Data Rate
Swing
CM Voltage Level
Frequency
Differential swing
CM Voltage Level
Duty Cycle
Data Rate
Logic “1” level
Logic “0” level
Output Jitter
Frequency
Logic “1” level
Logic “0” level
Duty Cycle
Output Jitter
Voltage range
Termination

MIN

TYP MAXUNIT
COMMENTS
General Parameters
-3.1
-3.3
-3.5
V
±6%
0.0
V
External ground
380mA
1255mW-4025125°C
HS Input Data (dp/dn)
DC4064Gb/s
0.20.8V
Differential or SE, p-p
vcc-0.8vcc
VMust match for both inputs
Half-Rate Input Clock (cep/cen)
DC
2032
GHz
0.20.8V
Differential or SE, p-p
vcc-0.8
vcc
VMust match for both inputs
405060%LS Output Data (q0p/q0n, q1p/q1n, q2p/q2n, q3p/q3n)DC
10
16Gb/sVvcc
vcc-0.44
V
With external 50Ohm DC
termination
2ps
Peak-to-peak at 10Gb/s
LS Output Clock (c4op/c4on)
DC
1016GHzV
vcc
vcc-0.4
V
With external 50Ohm DC
termination
50%1psPeak-to-peak at 10GHz
Analog Control Inputs (dccp/dccn)
Vveevcc1.0KOhmto corresponding clock
input

PACKAGE INFORMATIONThe chip die is housed in a custom, 44-pin CQFP package shown in Fig. 3. The package provides acenter heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends forthis section to be soldered to the vcc plain, which is ground for a negative supply, or power for a positivesupply.
Rev. 1.2.2

6May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

The part’s identification label is ASNT2124-KMM. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

Fig. 3. CQFP 44-Pin Package Drawing (All Dimensions in mm)

Rev. 1.2.2

7May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.2.2
1.1.2
1.1.1

Date05-2020
07-2019
05-20161.0.1
1.0.005-2015
09-2014

Rev. 1.2.2

Changes
Updated package information
Updated Letterhead
Corrected pin out diagram
Corrected block diagram
Corrected the Description section
Corrected the HS CIB section
Corrected Terminal Functions
Corrected Electrical Characteristics
Corrected Power Consumption
First release
Preliminary release

8May 2020