Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT2032-MBL
Digital DMUX 12-to-24 with LVDS Interfaces





Digital demultiplexer (DMUX) 12-to-24 with LVDS output interface
Programmable LVDS/CML/ECL input interface
Supports data rates from 1.0Mbps to 3.6Gbps
Preset function for synchronization of multiple parallel devices
Two pairs of clock divided-by-2 and synchronous clock enable outputs for supporting a tree-type
demultiplexation structure
Selectable clock divided-by-4 or divided-by-2 output
Power supply of +3.3V
Industrial temperature range
Low power consumption of 924mW at 3.6Gbps
Available in custom 256-pin BGA package (13mm x 13mm x 2.5mm)

Fig. 1. BGA Ball Placement, view from the Top of Package

Rev. 1.9.2

1May 2020

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DESCRIPTION

Fig. 2. Functional Block Diagram

ASNT2032-MBL is a broadband multichannel digital deserializer/demultiplexer (DMUX) 12-to-24 withan external initial preset function, selectable LVDS, CML or ECL input interface, and LVDS output
interface. The part shown in Fig. 2 also features selectable clock divided-by-2 or clock divided-by-4
outputs with multiple phases. The latter is intended for DDR interface support.
The operational speed of the DMUX is defined by an external clock signal (cip/cin) that is converted into
the required timing signals by its internal divider. The divider can be preset to a certain initial state by an
external active-low reset signal (rnp/rnn), which allows synchronization of multiple DMUX devices
operating in parallel. The reset signal is retimed inside the chip by the external clock and its positive edge
must satisfy the timing shown in Fig. 3. The position of the reset signal’s negative edge is not important.
Input clocktrhtrs

ResetFig. 3. Reset Timing Diagram.

The optimal alignment of input data (dXXp/dXXn) and clock (cip/cin) is illustrated in Fig. 4.
Input ClocktdstdhInput Data

Input DataFig. 4. Input Timing Diagram

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The actual values of setup (trs and tds) and hold (trh and tdh) times are presented in ELECTRICAL
CHARACTERISTICS.
This part also supports cascaded tree-type structures as shown in Fig. 5, by supplying two synchronouscopies of clock divided-by-2 (co1p/co1n and co2p/co2n) and clock enable (rno1p/rno1n andrno2p/rno2n) signals.

rnp/rnndXX incip/cin

rno 1co 1
data out
rno 2
co 2

ASNT2032
LVDS
DeMUX

rno 1
co 1
data outrno 2
co 2

ASNT2032
LVDS
DeMUX

ASNT2032
LVDS
DeMUX
ASNT2032
LVDS
DeMUX
ASNT2032
LVDS
DeMUX
ASNT2032
LVDS
DeMUX

Fig. 5. Cascaded Tree-Type Structure

A clock divided-by-4 output signal can also be provided for higher flexibility instead of a clock dividedby-2. The type of output clock co1p/co1n and co2p/co2n can be controlled by the cosel1 and cosel2
signal values shown in Table 1.
Table 1. Clock divided-by-2 and clock divided-by-4 selection

cosel1 or cosel2 value Clock output co1 or co2, respectively“0” (default)
Clk/2
“1”
Clk/4
All chip outputs are phase aligned with each other, with the capability to select the output clock phaserelative to the output data. They are also stabilized over PVT variations. The selection is performed byapplying the c4o_ph and clk_o_ph signals. The default values of those signals are defined by on-chip
terminations to vee and are equal to “0”. Possible phase relations of the outputs are shown in Table 2.
The DMUX IC uses one positive power supply vcc = +3.3V and is characterized for operation from−25°C to 125°C of junction temperature.

Rev. 1.9.2

3May 2020

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Table 2. Output clock phase selection

clk_o_ph c4o_ph
Clk/2 rising edges and Clk/4 edges are syncronous with datatransition.
Data

0Clk/2

Clk/40Only Clk/4 edges are shifted from data transition (half data period).
Data

1Clk/2Clk/4

Clk/2 rising edges and Clk/4 edges are shifted from data transition(half data period).
Data

0
Clk/2

Clk/4

1

Only Clk/2 edges are shifted from data transition (half data period).
Data

1

Clk/2

Clk/4

Rev. 1.9.2

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LVDS/ECL/CML Input Buffers
The data input buffer may operate with LVDS, ECL or CML interfaces. The clock and divider reset inputbuffers may only be used as CML or LVDS. To select the desired interface, refer to Table 3.
Table 3. Input interface selection

on_ecl (for data input only)Interfaceon_cml“0” (default)“0” (default)
LVDS
“1”
“0”
ECL
“0”
“1”
CML
“1”
“1”
Not Allowed
When the ECL mode is selected, the vecl voltage must be set to 2V below vcc and should support both
sourcing and sinking of the current.
Possible application schemes for different interfaces are detailed in Table 4, where Vcm is the commonmode voltage of the applied signal.
Table 4. Input Application Schemes

Interface Input
direct (p) signal
typetype Swing, mV Connection
Vcm, V*)
LVDS
Diff.
DC
1.2±1.0
ΔV*)
SEAC
ΔVThresholdDC
1.2±1.0
CML orDiff.
DCvcc-Swing/2
ΔV*)
ECLAC*)SEAC
ΔV

inverted (n) signal
Swing, mV Connection
Vcm, V*)DC
1.2±1.0
ΔVThresholdDC
1.2±1.0ACΔV*)*)DC
vcc-Swing/2
ΔVAC
Not
connectedACThreshold
DCΔV*)vcc
N/C
ACΔV*)*)
Threshold
DCAC
ΔVvcc*) – ΔV is defined in ELECTRICAL CHARACTERISTICS as Swing (SE).

DeMUX 12:24
The block consists of 12 independent 1-to-2 demultiplexers with a standard M-S/M-S-S architecture. It
latches in the data signals on both edges of half-rate clock c/2 that is supplied by the internal divider anddelivers the deserialized outputs aligned to the corresponding clock edges. The output data signals aremarked with “1” and “2” and are both aligned to the positive edge of the output clock divided-by-2.

Divider-by-4
The divider-by-4 converts the input clock signal (cip/cin) into clock divided-by-2 (c/2) and clock
divided-by-4 (c/4) signals internally aligned to the positive edge of the input clock. The divider can bepreset to the 0 initial state by the external active-low reset signal rnp/rnn that is internally retimed by thepositive edge of the input clock. The timing diagram is presented in Fig. 3 above.
Rev. 1.9.2

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LVDS Output Buffers
The LVDS output buffers are designed in full compliance with the LVDS standard and operate from a
3.3V supply at frequencies up to 3GHz. The buffer requires external 100Ohm differential DC termination.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 5 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vee).
Table 5. Absolute Maximum Ratings

Parameter
Supply Voltage (vcc)
Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Rev. 1.9.2

Min-4010106Max+3.6
1.1
1.0+90+10098
98UnitsVW
VºCºC%%May 2020

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TERMINAL FUNCTIONS
The ball assignment for the BGA package is shown in Table 6 and Table 7.
Table 6. Package Signal Balls

Name CodeRev. 1.9.2

dp00
dn00
dp01
dn01
dp02
dn02
dp03
dn03
dp04
dn04
dp05
dn05
dp06
dn06
dp07
dn07
dp08
dn08
dp09
dn09
dp10
dn10
dp11
dn11
rnp
rnncipcin

A8
A7
A6
A5
A4
A3
A2
A1
B1
C1
D1
E1
M1
N1
P1
R1
T1
T2
T3
T4
T5
T6
T7
T8
J1
K1
G1
H1

rno1p
rno1n
rno2p
rno2n
co1p
co1n
co2p
co2n

A9
B9
T9
R9
H15
H16
J15
J16

Type
Description
High-Speed Inputs
LVDS, CML, or ECL Differential data inputs

LVDS or CML

Differential divider reset input

LVDS or CML

Differential clock input

LVDS

High-Speed Outputs
Differential divider reset outputs

LVDS

Differential clock outputs

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Name Code Type
Description
q0p<00> B10 LVDS Differential data outputs
q0n<00> A10
q1p<00> B11
q1n<00> A11
q0p<01> B12
q0n<01> A12
q1p<01> B13
q1n<01> B14
q0p<02> A13q0n<02> A15q1p<02> A14q1n<02> A16q0p<03> B15q0n<03> B16q1p<03> C15q1n<03> C16q0p<04> D15q0n<04> D16q1p<04> E15q1n<04> E16q0p<05> F15q0n<05> F16q1p<05> G15q1n<05> G16q0p<06> K15q0n<06> K16q1p<06> L15q1n<06> L16q0p<07> M15q0n<07> M16q1p<07> N15q1n<07> N16q0p<08> R16q0n<08> P16q1p<08> T16
q1n<08> P15q0p<09> T14q0n<09> R15q1p<09> T13q1n<09> T15q0p<10> R13
q0n<10> R14

Rev. 1.9.2

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Name
q1p<10>
q1n<10>q0p<11>
q0n<11>
q1p<11>
q1n<11>

Code
R12
T12
R11
T11
R10
T10

Type
LVDS

Description
Differential data outputs

Low-Speed Control Signals
cosel1
M8
3.3V CMOS DC Binary control signals with a default value of “0”cosel2N8
clk_o_phP8c4o_phP7
oncml_c D6, N6
onecl_dD9oncml_d
D8Table 7. Package Power Supply Balls

Nameveevccvecl
n/cX

Rev. 1.9.2

Code
B2-B8, C2-C14, D2-D4, D10-D14,
E2-E14, F2-F4, F12-F14, G2-G4,
G12-G14, H2-H4, H12-H14,
J2-J4, J12-J14, K2-K4, K12-K14,
L2-L4, L12-L14, M2-M7,
M10-M14, N2-N5, N9-N14,
P2-P6, P9-P14, R2-R8
F7-F11, G6, G7, G9-G11, H10,J10, K6, K7, K9-K11, L7, L9-L11, M9
F6, G8, H5, H6, H7,J5, J6, J7, K8, L6, L8
F1, L1
D5, D7, F5, G5, H8, H9, H11,J8, J9, J11, K5, L5, N7

9

TypeGround

Positive
supply voltage
ECL input
termination voltage
Not connected
Removed balls

Value, V0

3.3
vcc-2VMay 2020

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ELECTRICAL CHARACTERISTICSPARAMETERMIN

TYP MAXUNIT
COMMENTS
General Parameters+3.14+3.3+3.47
V±5%vcc0.0
VExternal groundvee
Ivcc
280mAPower consumption
924mW
Junction temperature-25
50125°C
Input Data (dXXp/dXXn)
Data Rate
13600
Mbps
Swing (SE)50600mV
Peak-to-peak
CM Voltage Level
13.3
V
In LVDS mode
Interface
LVDS, ECL, CML
Complies with IEEE Std
Input Clock (cip/cin)
Frequency
13600
MHz
Swing (SE)50600
mV
Peak-to-peak
CM Voltage Level
13.3
V
In LVDS mode
Interface
LVDS, CML
Complies with IEEE Std
Output Data (q0XX, q1XX)
Data Rate
0.5
1800
Mbps
Swing (SE)250325400mV
Peak-to-peak
CM Voltage Level
1.1251.21.275
VInterface
LVDS
Complies with IEEE Std
Divided Output Clock (co1p/co1n, co2p/co2n)Frequency
0.5/0.25
1800/900
MHzSwing (SE)
250
325
400mV
Peak-to-peak
CM Voltage Level
1.125
1.2
1.275
V
Interface
LVDS
Complies with IEEE Std
CMOS Control Inputs
Internal termination
KOhm
Terminated to vee
600
Logic “1” levelvcc-0.3
V
Logic “0” level
vee+0.3
V
Timing Parameters
Data skew
0ps
Clock skew

0ps

tds
tdhtrstrh-902002525pspspsps

Rev. 1.9.2

10

By simulations

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PACKAGE INFORMATIONThe chip is packaged in a custom 256-pin BGA package shown in Fig. 6.

ASNT2032

ASNT 2032

Fig. 6. BGA Package Drawing (All Dimensions in mm)

The part’s identification label is ASNT2032-MBL. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

Rev. 1.9.2

11May 2020

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REVISION HISTORY
Revision
1.9.2
1.8.2
1.8.1
1.7.1
1.6.1
1.5.1

Date
05-2020
07-2019
01-2015
01-2015
07-201404-2014

1.4.1
1.3.1

08-201301-20131.2
1.1
1.001-2012
08-201106-2011

Rev. 1.9.2

Changes
Updated Package Information
Updated Letterhead
Added Table 4 (Input Application Schemes)
Corrected ball numbers for co1p and co1n signals
Corrected maximum frequency
Added specifications for CMOS control signals
Added description of default control states
Added reset timing in Description and in Electrical Characteristics
Corrected format
Corrected block diagram
Added Absolute Maximums Rating table
Corrected Package Information section
Revised Electrical Characteristics
Revised Electrical Characteristics
First release

12May 2020