Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT8052-PQB
11-13.3GHz and 13-14.4GHz Programmable PLL with integrated VCOs

nc

vee

vee

phs2

phs1

nc

vcc

clop

vcc

clon

vcc

vcc

vcc

chop

vcc

chon

ASNT8052

vcc

vcc

1

vee

off12goffpll

ftr1n

vee

ftr1p

vcc

loln

vcc

offcho

cen

vee

vcc

offecl

cep

cr16n

vcc

cr16p

Rev. 1.4.2

vcc

vcc

vecl

Programmable clock multiplier (CMU) with two selectable frequency ranges of internal PLL
Optional operational mode as a clock divider with PLL disabled
Closed-Loop SSB phase noise at 10MHz offset better than 98dB/Hz
On-chip Loss-of-Lock control circuit
External RC loop filter
LVDS, CML, or PECL input reference clock interface
Full-rate CML clock input interface
Full-rate or half-rate CML clock output interface
LVDS divided clock output with optional 90°-step phase adjustment
Single +3.3V power supply
Low power consumption of 585mW
Fabricated in SiGe for high performance, yield, and reliability
Standard 40-pin QFN packagevee
February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
ce
offplloff12gloln
ftr1p
ftr1nvecl
cr16
offecloffcho

HS
CIB

PLL

/16
LS
CIB

CPR

phs1
phs2

LSCOBclo

HS
COB

cho

C2
ref

CFig. 1. Functional Block Diagram.

ASNT8052-PQB is a clock multiplication unit (CMU) with a dual-range phase-locked loop (PLL)
incorporating high-speed voltage-controlled oscillators (VCOs). The part features several control
functions shown in Table 1. All functions are further described in the specified sections.
Table 1. PLL Control Functions.

Control
Logic State
Describedsignalin.
“0”
Not connected (default)“1”
off12gLower VCO range
Same as 0 state
Higher VCO range
PLL
offchoFull-rate HS output clock Half-rate HS output clock HS COB disabled
HS COB
phs1/phs2
See Table 4
CPRoffpll
PLL enabledSame as 0 state
PLL disabled
PLLoffecl CML/PECL input interface
Same as 1 state
LVDS input interface LS COB
One of the two frequency ranges can be selected by the control signal off12g. In the main operationalmode, the IC shown in Fig. 1 accepts a low-speed reference clock cr16p/cr16n with the frequency f/16
and converts it into a high-speed output clock cho with the selectable frequency f or f/2 and a low-speed
output clock clo with the frequency f/16. The frequency of the high-speed clock is selected through theexternal 3-state control signal offcho that can also disable the clock output buffer.
One of four 90° shifted phases of the low-speed output clock with the frequency f/16 can be selected bycontrol signals phs1 and phs2.
When operating in the closed-loop mode, the PLL requires an external loop filter connected to pins ftr1pand ftr1n. The output signal loln indicates the locked or unlocked state of the PLL. The PLL also supports
an open-loop mode of operation with its selected VCO controlled externally by voltages applied to thefilter pins ftr1p and ftr1n. The chip can operate as a divider by 16 of the input high-speed clock cep/cen
if the PLL is disabled by the control signal offpll.
The IC uses a single +3.3V power supply and is characterized for operation from −25°C to 125°C ofjunction temperature.
Rev. 1.4.2

2February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
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HS CIBThe High-Speed Clock Input Buffer (HS CIB) can process an external clock signal cep/cen withfrequencies from DC to the specified maximum value. The clock inputs support the CML logic interface
with on chip 50Ohm termination to vcc and may be used differentially, AC/DC coupled, single-ended, orin any combination. In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.

LS CIB
The Low-Speed Clock Input Buffer (LS CIB) is a proprietary universal input buffer (UIB) that can run ata high frequency. The UIB’s input termination impedance is controlled by the CMOS signal offecl and is
set to 100Ohm differential if offecl=”1” (true LVDS mode, default state) or 50Ohm single-ended to vecl
if offecl=”0” (CML mode). The value of vecl should be equal to vcc in CML mode. It can be also set tovcc-2V in order to support the PECL interface. In this case, the corresponding termination voltage source
should be able to both sink and source up to 20mA of current. Possible input clock application schemes
are detailed in Table 2, where Vcm is a common-mode voltage of the clock signal.
Table 2. LS Input Clock Application Schemes.

Interface Clockcr16p signal
cr16n signal
typetype Swing, mV Connection
Vcm, VSwing, mV Connection
Vcm, VLVDS Diff. 70-to-500
DC1.2±1.070-to-500
DC1.2±1.0(offeclSE 140-to-900
ACThreshold
DCvcc -to- vcc= 1)
ThresholdDCvcc -to- vcc 140-to-900
ACCML or Diff. 70-to-500
DCvcc -Swing/2 70-to-500
DCvcc-Swing/2PECLACAC(offeclSE 140-to-900
ACNot connected= 0)140-to-900
ACThreshold
DCvcc
Not connected
140-to-900
ACThresholdDC
140-to-900
ACvcc
As can be seen, the UIB is designed to accept differential signals with DC common mode voltages
between the negative (vee) and the positive (vcc) supply rails, as well as AC common mode noise with afrequency up to 5MHz and voltage levels from vee to vee+2.4V. It can also receive single-ended signals
with a threshold voltage between vee and vcc applied to the unused pin of the differential input interface.

PLLThe PLL contains a phase frequency detector, a charge pump, an on-chip integrator with an additional offchip filter connected between pins ftr1p and ftr1n, and two selectable LC-tank VCOs with different
central frequencies. The recommended parameters of the external filter schematic components shown inFig. 2 are for reference only and can be modified based on specific requirements.

Rev. 1.4.2

3February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
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flr1p10nFflr1nFig. 2. External Filter Schematic.

The PLL is activated by the external control signal offpll=”0” (default state). In case of offpll=”1”, thePLL is disabled and the chip operates as a divider by 16.
The main function of the PLL is to synthesize the full-rate clock C by aligning the phase and frequency ofthe divided clock from the internal divider to the externally applied reference clock cr16. Selection of therequired VCO is defined by the CMOS control signal off12g (lower-speed VCO if off12g=”1”; higherspeed VCO if off12g=”0”, default state). The state of the PLL is indicated by the output CMOS loss-oflock alarm signal loln (loln=”0” if PLL is not locked, loln=”1” if phases and frequencies of internal andreference clocks are matching).
If required, the selected VCO can be externally controlled by voltages applied to pins ftr1p and ftr1n as
shown in Table 3. In this case, the PLL is operating in the open-loop mode. The unused VCO iscompletely disabled in order to save power.
Table 3. VCO External Control Modes.

ftr1p signal, V
Vccm+0.8=3.1
Vccm-0.8=1.5
Vccm=2.3
Vccm=2.3

ftr1n signal, V VCO frequency
Vccm=2.3
min
Vccm=2.3
max
Vccm+0.8=3.1
max
Vccm-0.8=1.5
min

Divider-by-16
The Divider-by-16 (/16) includes 4 divide-by-2 circuits connected in series. The clocks divided by 8 and
16 are supplied to the PLL’s phase detector and to the clock processor CPR.

CPR
The clock processor (CPR) receives divided by 16 clocks from the divider and supplies the processedsignal to the low-speed clock output buffer LS COB. The phase of the delivered divided-by-16 clock C16
can be altered utilizing the CMOS control pins phs1 and phs2 as shown in Table 4.
Table 4. Output Clock Phase Selection.

phs1
phs2
C16 phasevee (default) vee (default)
0°
90°
vee
vcc
180°
vcc
vee
270°
vcc
vcc

Rev. 1.4.2

4February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

HS COBThe High Speed Clock Output Buffer (HS COB) receives the full-rate (C) and half-rate (C2) clocks fromthe PLL and converts the selected one into CML output signal cho. The state of the buffer is controlled
by the external CMOS control signal offcho (disabled if offcho=”1”; C2 output if offcho is notconnected, default state; C output if offcho=”0”).

LS COB
The LVDS Low-Speed Clock Output Buffer (LS COB) converts the signal from the CPR into the LVDS
output signal clo. The proprietary low-power LVDS output buffer utilizes a special architecture thatensures operation at frequencies up to 2.0GHz with a low power consumption level of 30mW. The buffer
satisfies all requirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. For the correct
operation, it requires external differential 100Ohm DC termination at the receiver side. These pins should
NEVER be CONNECTED to devices with 50Ohm termination to ground WITHOUT DC BLOCKS!

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 5 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vee).
Table 5. Absolute Maximum Ratings.

Parameter
Supply Voltage (vcc)
Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Rev. 1.4.2

MinMax3.6
0.65
1.0+90+10098
98-40
10105UnitsVWVºCºC%%February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
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TERMINAL FUNCTIONSTERMINAL
NameNo. Type
cepcenchop
chon

1413
1716

cr16p
cr16n
clop
clon

1
2
20
19

offecloffchooff12goffpll
phs2
phs1
ftr1p
ftr1n
loln
Name
vcc
veenc

Rev. 1.4.2

3591124
25786

DESCRIPTION

High-Speed I/Os
Input CML differential external clock inputs with internal SE 50Ohm
termination to vcc
Output CML differential clock outputs with internal SE 50Ohm
termination to vcc. Require external SE 50Ohm termination tovcc
Low-Speed I/Os
Input LVDS/CML clock inputs. See LS CIB for allowed application
schemes
Output LVDS clock outputs. See LS COB for a detailed description

Input

Controls
3.3V CMOS control signals

Input

Pins for connecting the external loop filter. Can be also used for
VCO external control in the open-loop mode
Output 3.3V CMOS control output
Supply and Termination Voltages
Description
Pin Number
Positive power supply. (+3.3V )12, 15, 18, 27, 28, 29, 31, 32, 33,34, 35, 36, 37, 38, 39
External ground. (0V )4, 10, 22, 23, 30, 40
Not connected pins
21, 26

6February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
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ELECTRICAL CHARACTERISTICSPARAMETERTYP MAXUNIT
COMMENTS
General Parameters
0.0
V
External ground
vee
3.1
3.3
3.5
V
±6%vcc
Ivcc
168
185mA
Power consumption
583mW
Junction temperature-4025125°C
HS Input Clock (cep/cen)Frequency
DC17GHz
Swing
230
800mV
Differential or SE, p-p, at 17GHz
50800mV
Differential or SE, p-p, at 4GHz
CM Voltage Level
vcc-0.8
vcc
VMust match for both inputs
Duty Cycle
40%
50%60%LS Input Clock (cr16p/cr16n)Frequency
DC810
MHzSwing
140
900mV
Differential or SE, p-p
CM Voltage Level
vee
1.6
vcc
V
Must match for both inputs
HS Output Clock (chop/chon)Frequency
DC17GHz
Logic “1” level
Vvcc
Logic “0” levelvcc-0.58
VJitter6ps
Peak-to-peak at 12.5GHz
Duty Cycle
50%
LS Output Clock (clop/clon)
Frequency
DC1060MHzInterfaceLVDS
Meets the IEEE Std.
CMOS control inputs and outputs (offecl, offcho, off12g, offpll, phs1, phs2, loln)
Logic “1” levelvcc-0.3
V
Logic “0” level
vee+0.3
VVCOs
Low frequency of VCO 1
11.0
GHzHigher-speed VCO.
Active if off12g =”0”High frequency of VCO 1
13.3
GHz
Low frequency of VCO 2
13.0
GHz
Lower-speed VCO.
Active if off12g =”1”
High frequency of VCO 2
14.4
GHz
External control common
2.3
V
In the open-loop modemode vccm
External control voltage vccm-0.8
vccm+0.8
VIn the open-loop mode
range

Rev. 1.4.2

MIN

7February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATIONThe chip is packaged in a standard 40-pin QFN package shown Fig. 3. It is recommended that the center
heat slug located on the back side of the package is soldered to the vee plain that is ground for thepositive supply.
The part’s identification label is ASNT8052-PQB. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

ASNT8052
Fig. 3. Package Drawing

Rev. 1.4.2

8February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.4.2
1.3.2
1.3.1
1.2.1

Date
02-2020
07-2019
05-201303-20131.1
1.005-2012
04-2012

Rev. 1.4.2

Changes
Updated Package Information
Updated Letterhead
Corrected clock names in Table 2
Revised title
Corrected description
Corrected electrical characteristics
Updated format
Corrected supply information
First release

9February 2020