Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT8050-PQB
7.4-8.8GHz and 10.8-12.7GHz Programmable PLL with integrated VCOs

oncml

vee

vee

phs2

phs1

vee

vcc

clop

vcc

clon

vcc

vcc

vcc

chop

vcc

chon

ASNT8050

vcc

vcc

lol

1

vee

offplloff12g

vee

ftr2

vcc

ftr1

vcc

offchocen

off16b

vcc

vee

cep

cr16n

vcc

cr16p

Rev. 1.7.2

vcc

vcc

vcc

Programmable clock multiplier (CMU) with two selectable frequency ranges of internal PLL
Optional operational mode as a clock divider with PLL disabled
Closed-Loop SSB phase noise at 10MHz offset better than 98dB/Hz
Selectable internal divider ratio of 8 or 16
On-chip Loss-of-Lock control circuit
External RC loop filter
LVDS or CML input reference clock interface
Full-rate CML clock input and output interfaces
LVDS divided clock output with optional 90°-step phase adjustment
Exhibits low jitter and limited temperature variation over industrial temperature range
Single +3.3V power supply
Power consumption: 630mW
Fabricated in SiGe for high performance, yield, and reliability
Standard MLF/QFN 40-pin packagevee
February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
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DESCRIPTION
ce

HS
CIB

offplloff12g
lol
ftr1
ftr2
cr16
oncml

off16b

PLL/16LS
CIB

C

refoffcho

CPR

phs1
phs2

LS
COBcloHS
COBchoFig. 1. Functional Block Diagram

ASNT8050-PQB is a clock multiplication unit (CMU) with a dual-range phase-locked loop (PLL)
incorporating high-speed voltage-controlled oscillators (VCOs). The part features several control
functions shown in Table 1. All functions are further described in the specified sections.
Table 1. PLL Control Functions

Control
Logic State
Described
signalin“0”Not connected (default)“1”
Higher VCO range
Same as “0” state
Lower VCO range
PLL
off12gHS COB enabledSame as “0” state
HS COB disabled
HS COB
offchoSee
Table4CPR
phs1/phs2
Clock division ratio of 16
Same as “0” state
Clock division ratio of 8 PLL, CPR
off16b
PLL enabledSame as “0” state
PLL disabled
PLLoffpll
LVDS input interface
Same as “0” state
CML input interface
LS CIBoncml
One of the two frequency ranges can be selected by the control signal off12g. In the main operationalmode, the IC shown in Fig. 1 accepts a low-speed reference clock cr16p/cr16n with the frequency f/8 or
f/16 and converts it into a high-speed output clock cho with the frequency f and the low-speed output
clock clo with the corresponding frequency f/8 or f/16. The frequency of the reference and output clocks
is defined by the settings of the control signal off16b.
The high-speed clock output buffer can be enabled/disabled by the control signal offcho. One of four 90°
shifted phases of the low-speed output clock with the frequency f/16 can be selected by control signals
phs1 and phs2. This phase selection is not available for the output clock with the frequency f/8.
When operating in the closed-loop mode, the PLL requires an external loop filter connected to pins ftr1and ftr2. The output signal lol indicates the locked or unlocked state of the PLL. The PLL also supports anopen-loop mode of operation with its selected VCO controlled externally by voltages applied to the filter
pins ftr1 and ftr2.
Rev. 1.7.2

2February 2020

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The chip can operate as a divider of the input high-speed clock cep/cen if the PLL is disabled by thecontrol signal offpll. The division ratio of 8 or 16 can be selected by the control signal off16b.
The IC uses a single +3.3V power supply and is characterized for operation from −25°C to 125°C ofjunction temperature.

HS CIBThe High-Speed Clock Input Buffer (HS CIB) can process an external clock signal cep/cen withfrequencies from DC to the specified maximum value. The clock inputs support the CML logic interface
with on chip 50Ohm termination to vcc and may be used differentially, AC/DC coupled, single-ended, orin any combination. In the DC-coupling mode, the input signal’s common mode voltage should complywith the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.

LS CIB
The Low-Speed Clock Input Buffer (LS CIB) is a proprietary universal input buffer (UIB) that can run ata high frequency. The UIB’s input termination impedance is controlled by the CMOS signal oncml and is
set to 100Ohm differential if oncml=”0” (true LVDS mode, default state) or 50Ohm single-ended to vcc
if oncml=”1” (CML mode). Possible input clock application schemes are detailed in Table 2, where Vcm
is the common-mode voltage of the input clock signal.
Table 2. LS Input Clock Application Schemes

Interface Clockcr16p signal
cr16n signal
typetype Swing, mV Connection
Vcm, VSwing, mV Connection
Vcm, VLVDS Diff. 70-to-500
DC1.2±1.0
70-to-500DC1.2±1.0(oncml
SE 140-to-900
ACThreshold
DCvee-to-vcc=”0”)ThresholdDC
vee-to-vcc 140-to-900
ACCMLDiff. 70-to-500
DCvcc -Swing/2 70-to-500
DCvcc-Swing/2(oncmlACAC=”1”)
SE 140-to-900
AC
Not connected
140-to-900
ACThreshold
DCvcc
Not connected
140-to-900
ACThresholdDC
140-to-900
ACvcc
As can be seen, the UIB is designed to accept differential signals with DC common mode voltages
between the negative (vee) and the positive (vcc) supply rails, as well as AC common mode noise with afrequency up to 5MHz and voltage levels from vee to vee+2.4V. It can also receive single-ended signals
with a threshold voltage between vee and vcc applied to the unused pin of the differential input interface.

PLLThe PLL contains a phase frequency detector, a charge pump, an on-chip integrator with an additional offchip filter connected between pins ftr1 and ftr2, and two selectable LC-tank VCOs with different central
frequencies. The recommended parameters of the external filter schematic components shown in Fig. 2 arefor reference only and can be modified based on specific requirements.
Rev. 1.7.2

3February 2020

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2790 Skypark Drive Suite 112, Torrance, CA 90505

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Fig. 2. Recommended External Filter Schematic

The PLL is activated by the external control signal offpll=”0”. In case of offpll=”1” (default state), thePLL is disabled and the chip operates as a divider by 8 or 16. The division ratio is defined by the CMOS
control signal off16b (division by 8 if off16b=”1”; division by 16 if off16b=”0”, default state).
The main function of the PLL is to synthesize the full-rate clock C by aligning the phase and frequency ofthe divided clock from the internal divider to the externally applied reference clock cr16. Selection of therequired VCO is defined by the CMOS control signal off12g (lower-speed VCO if off12g=”1”; higherspeed VCO if off12g=”0”, default state). The frequency of the required reference clock is defined by theCMOS control signal off16b (divided-by-8 if off16b=”1”; divided-by-16 if off16b=”0”, default state).
The state of the PLL is indicated by the output CMOS loss-of-lock alarm signal lol (lol=”1” if PLL is notlocked, lol=”0” if phases and frequencies of internal and reference clocks are matching).
If required, the selected VCO can be externally controlled by voltages applied to the pins ftr1 and ftr2 as
shown in Table 3. In this case, the PLL is operating in the open-loop mode. The unused VCO iscompletely disabled to save power.
Table 3. VCO External Control Modes

ftr1 signal, V
Vccm+0.8=3.1
Vccm-0.8=1.5
Vccm=2.3
Vccm=2.3

ftr2 signal, V VCO frequency
Vccm=2.3
min
Vccm=2.3
max
Vccm+0.8=3.1
max
Vccm-0.8=1.5
min

Divider-by-16
The Divider-by-16 (/16) includes 4 divide-by-2 circuits connected in series. The clocks divided by 8 and
16 are supplied to the PLL’s phase detector and to the clock processor CPR.

CPRThe clock processor (CPR) receives divided clocks from the divider and supplies the selected clock to thelow-speed clock output buffer. The type of the clock is defined by the CMOS control signal off16b(divided-by-8 if off16b=”1”; divided-by-16 if off16b=”0”, default state). The phase of the divided-by-16
clock C16 can be altered utilizing the CMOS control pins phs1 and phs2 as shown in Table 4.
Table 4. Output Clock Phase Selection

phs1
phs2
C16 phasevee (default) vee (default)
0°
90°
vee
vcc
180°
vcc
vee
270°
vcc
vcc
Rev. 1.7.2

4February 2020

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2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
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HS COBThe High Speed Clock Output Buffer (HS COB) receives the high-speed clock from the PLL andconverts it into the CML output signal cho. The buffer can be enabled or disabled by the external CMOS
control signal offcho (disabled if offcho=”1”; enabled if offcho=”0”, default state).

LS COB
The LVDS Low-Speed Clock Output Buffer (LS COB) converts the signal from the CPR into the LVDS
output signal clo. The proprietary low-power LVDS output buffer utilizes a special architecture thatensures operation at frequencies up to 2.0GHz with a low power consumption level of 30mW. The buffer
satisfies all requirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. For the correct
operation, it requires external differential 100Ohm DC termination at the receiver side. These pins should
NEVER be CONNECTED to devices with 50Ohm termination to ground WITHOUT DC BLOCKS!

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 5 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vee).
Table 5. Absolute Maximum Ratings

Parameter
Supply Voltage (vcc)
Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Rev. 1.7.2

Min-4010105Max
3.6
0.7
1.0
+90+1009898Units
VW
VºCºC%%February 2020

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TERMINAL FUNCTIONSTERMINAL
NameNo.
Typecepcenchopchon

14
13
1716

CML
input
CMLoutput

cr16p
cr16nclopclon

1
2
20
19

Input

off16boffcho
off12goffpll
oncml
phs2
phs1
ftr1
ftr2
lol
Namevccvee

Rev. 1.7.2

459112124
25786

DESCRIPTION
High-Speed I/Os
CML differential external clock inputs with internal SE 50Ohm
termination to vcc
CML differential clock outputs with internal SE 50Ohm termination tovcc. Require external SE 50Ohm termination to vcc
Low-Speed I/OsLVDS/CML clock inputs. See LS CIB for allowed application schemes

Output LVDS clock outputs. See LS COB for a detailed description

Input

Controls
3.3V CMOS control signals

Input

Pins for connecting the external loop filter. Can be also used for VCO
external control in the open-loop mode
Output 3.3V CMOS control output
Supply and Termination Voltages
Description
Pin Number
Positive power supply (+3.3V) 12, 15, 18, 27, 28, 29, 31, 32, 33, 34, 35, 36, 37, 38, 39
Negative power supply (0V)
3, 10, 22, 23, 26, 30, 40

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Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
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ELECTRICAL CHARACTERISTICSPARAMETER

MAX UNITCOMMENTS
General Parameters
0.0
V
External groundvee
3.1
3.3
3.5
V
±6%
vcc
Ivcc
185195mA
Power consumption
630mW
Junction temperature -40
25125°C
HS Input Clock (cep/cen)Frequency
DC14GHz
Swing
220
800
mV
Differential or SE, p-p, at 14GHz
50800mV
Differential or SE, p-p, at 4GHz
CM Voltage Level
vcc-0.8
vcc
VMust match for both inputs
Duty Cycle
40%
50%60%LS Input Clock (cr16p/cr16n)Frequency
DC1600
MHzSwing
140
900mV
Differential or SE, p-p
CM Voltage Level
vee
1.6
vcc
V
Must match for both inputs
HS Output Clock (chop/chon)Frequency
DC
14
GHz
Logic “1” level
Vvcc
Logic “0” levelvcc-0.85
VJitter6
ps
Peak-to-peak at 12.5GHz
Duty Cycle
50%
LS Output Clock (clop/clon)
Frequency
DC1750MHzInterface
LVDS
Meets the IEEE Std.
CMOS control inputs and outputs (off16b, offcho, off12g, offpll, oncml, phs1, phs2, lol)
Logic “1” levelvcc-0.3
V
Logic “0” level
vee+0.3
VVCOs
Low frequency of
10.8
GHzHigher-speed VCO.
VCO 1
Active if off12g =”0”High frequency of
12.7
GHz
VCO 1
Low frequency of
7.4
GHz
Lower-speed VCO.
VCO 2
Active if off12g =”1”
High frequency of
8.8
GHz
VCO 2
External control
2.3
V
In the open-loop mode
common mode vccm
External control
vccm-0.8
vccm+0.8
V
In the open-loop mode
voltage range
Rev. 1.7.2

MINTYP

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Advanced Science And Novel Technology Company, Inc.
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Offices: 310-530-9400 / Fax: 310-530-9402
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PACKAGE INFORMATIONThe chip die is housed in a standard 40-pin QFN package shown in Fig. 3. It is recommended that thecenter heat slug located on the back side of the package is soldered to the vee plain that is ground for thepositive supply.
The part’s identification label is ASNT8050-PQB. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all tensubstances.

ASNT8050
Fig. 3. QFN 40-Pin Package Drawing (All Dimensions in mm)

Rev. 1.7.2

8February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
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REVISION HISTORY
Revision
1.7.2
1.6.2
1.6.1
1.5.1

Date
02-2020
07-2019
08-2015
08-2014

1.4.1
1.3.105-2013
03-20131.2.103-2013

1.1
1.005-2012
04-2012

Rev. 1.7.2

Changes
Updated Package Information
Updated Letterhead
Correct Fig. 2 External Filter Schematic
Corrected format
Corrected default state of the offpll input
Corrected clock names in Table 2
Corrected name of the supply in the Absolute Maximum Ratings table
Removed broken link
Revised title
Revised description
Revised absolute maximum ratings
Revised terminal functions
Revised electrical characteristics
Revised package information
Updated format
Corrected supply information
First release

9February 2020