A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

A D S A N T E C

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

ASNT1012 (ASNT1032)
16:1 MUX-CMU
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•
•
•
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16 to 1 multiplexer (MUX) with integrated CMU (clock multiplication unit).
Supports multiple data rates in the 9.8-12.5Gb/s range.
LVDS compliant input data buffers.
Clock-divided-by-16 LVDS output buffer.
Single +3.3V power supply.
Industrial temperature range.
Low power consumption of 660mW at 12.5Gbps.
Available in standard 100-pin QFN package (12mm x 12mm).

DESCRIPTION
bitorderd00

d15

LSDIB
x16

off12g
lol1n
ftr1p
ftr1n
cr16

MUX
16:1

16

C16

PLL
LS
CIB

/16

ref

CC2

Data
OB

qcml

LVDS
COBcloHS
COB

chooffcho
Fig. 1. Functional Block Diagram.

ASNT1012 is a low power and high-speed 16 to 1 multiplexer (MUX) with an internal clock
multiplier unit (CMU). The MUX can function at data rates (fbit) between 9.8Gbps to 12.5Gbps
by utilizing its multiple on-chip full-rate VCOs.
The main function of ASNT1012 is to multiplex 16 parallel data channels running at a bit rate offbit/16 into a high speed serial bit stream running at fbit. It provides a high-speed output datachannel for point-to-point data transmission over a controlled impedance media of 50Ohm. The
transmission media can be a printed circuit board or copper coaxial cables. The functional
distance of the data transfer is dependent upon the attenuation characteristics of thetransportation media and the degree of noise coupling to the signaling environment.
Rev.: 1,Sept 2008.

1ASNT1012-PQA

A D S A N T E CA d v a n c e dS c ie n c ea n d
N o v e lT e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

During normal operation, the serializer’s low-speed input buffer (LS DIBx16) accepts external
16-bit wide parallel data words “d00”-“d15” through 16 differential LVDS inputs and delivers
them to the multiplexer’s core (MUX16:1) for serialization. By utilizing pin “bitorder”, theserializer can designate either “d00” or “d15” as the MSB thus simplifying the interface between
ASNT1012 and a proceeding ASIC.
MUX16:1 serializes the data words with multiple divided down clock signals that are generated
from the full rate clock “C” by the internal divider (/16). The divider also produces half rate
clock “C2” for the high speed clock output buffer (HS COB), and engenders a full rate clock
divided-by-16 signal “C16” for use by the PLL (PLL). “C” is synthesized by PLL, which locks“C16” to the external system level clock “cr16” that is provided by the low speed clock input
buffer (LS CIB). “cr16” must be 1/16 the frequency of the active full rate VCO in PLL. PLL
contains 2 full rate VCOs to cover the 9.8-12.5GHz range, which are selected utilizing the“off12g” control pin.
The serialized words are transmitted as 2-level signals “qcml” by a differential CML output
buffer (Data OB). A full-rate or half-rate clock “cho” is transmitted by a similar CML buffer (HSCOB) in parallel with the high-speed data. The clock and data outputs are well phase matched toeach other resulting in very little relative skew over the operating temperature range of thedevice. HS COB may be disabled or its operational mode changed by means of the 3-state (vee,vcc, not connected (n/c)) CMOS “offcho” signal. Both output stages are back terminated withon-chip 50Ohm resistors.
ASNT1012 also provides a differential low speed output clock “clo” though a LVDS clockoutput buffer (LVDS COB). PLL generates a loss of lock signal alarm “lol1n”. An off chipcapacitor is required for PLL and is connected through pins “ftr1p/n”.
The serializer uses a single +3.3V power supply and is characterized for operation from −25°C to125°C of junction temperature.

LS DIBx16
The Low-Speed Data Input Buffer (LS DIBx16) consists of 16 proprietary universal input
buffers (UIBs) that exceed the LVDS standards IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-6441995. UIB is designed to accept differential signals with amplitudes above 60mV peak-to-peak(p-p), DC common mode voltage variation between the negative (vee) and positive (vcc) supply
rails, and AC common mode noise with a frequency up to 5MHz and voltage levels ranging from0 to 2.4V. It can also receive single-ended signals with amplitudes above 60mV p-p and thresholdvoltages between vee and vcc. The input termination impedance is set to 100Ohm differential.

LS CIB
The Low-Speed Clock Input Buffer (LS CIB) is a UIB that can run at a frequency up to 800MHz.
This block is used to deliver the low speed system clock “cr16” as a reference signal to PLL.

PLL
The Phase Locked Loop (PLL) contains a phase frequency detector, charge pump, an on-chip
integrator with an additional off-chip filter connected between the pins “ftr1p” and “ftr1n” (Fig.
2), and two selectable LC-tank VCOs centered at 11.8GHz and 11.0GHz. The main function ofRev.: 1,Sept 2008.

2

ASNT1012-PQA

A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e lT e c h n o lo g y27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

PLL is to synthesize full rate clock “C” by aligning the phase and frequency of “C16” of theactivated VCO to the externally applied system clock “cr16”. A logic “0” output CMOS loss-oflock “lol1n” alarm signal is generated by PLL if its two input clock signals are not matching inphase and/or frequency.
ftr1
ftr2

430
4301nFig. 2. External Filter Schematic.

Selection of the different VCOs of PLL is achieved by utilizing the CMOS control pin “off12g”.
A logic “1” chooses the 11.0GHz VCO while a logic “0” selects the 11.8GHz VCO (defaultstate). The unused VCO is turned completely off in order to save power.

/16
The Divider-by-16 (/16) includes 4 divide-by-2 circuits connected in series. High-speed clock“C” is fed into the first divide-by-2 circuit that generates “C2”. “C2” is routed internally to thenext divide-by-two circuit and outside of the block to MUX16:1 and HS COB. Other divided
down clock signals are formed and routed to MUX16:1 in similar fashion. “C16” is passed on toPLL and LVDS COB to become the output low speed clock signal “clo”.

MUX16:1
The 16 to 1 Multiplexer (MUX16:1) utilizes a tree type architecture that latches the incoming
data on the negative edge of the “C16” clock signal that is supplied by /16. The 16-bit wide data
word is subsequently multiplexed and delivered to Data OB as a serial data stream running at adata rate up to 12.5Gbps. The latency of this circuit block is equal to roughly one period of thelow-speed input clock. When “bitorder”=0 (default), “d00”is the MSB and when “bitorder”=1,“d15” is designated the MSB.

Data OBThe Data Output Buffer (Data OB) receives high-speed serial data from MUX16:1 and converts
it into the CML output signal “qcml” with a single ended swing of 600mV. The buffer requires
50Ohm external termination resistors connected between “vcc” and each output to match its
internal 50Ohm resistors and can operate at a data rate up to 12.5Gbps.

HS COBThe High Speed Clock Output Buffer (HS COB) utilizes the same termination scheme as Data
OB and can operate at a frequency up to 12.5GHz while producing a single-ended CML output
swing of 600mV. The buffer can be enabled or disabled by the external 3-state (vcc, vee, notconnected (n/c)) control signal “offcho”. The n/c default state corresponds to a “C2” output
signal. The logic “0” state provides a full-rate clock output signal while the logic “1” state
disables the buffer completely to save power.

LVDS COB
The LVDS Clock Output Buffer (LVDS COB) receives “C16” from /16 and converts it into aLVDS output signal “clo”. The proprietary low-power LVDS output buffer utilizes a special
architecture that ensures operation at frequencies up to 2GHz with a low power consumption
level of 30mW. The buffer satisfies all the requirements of the IEEE Std. 1596.3-1996 andANSI/TIA/EIA-644-1995.
Rev.: 1,Sept 2008.

3

ASNT1012-PQA

A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e lT e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

Output Timing
Phase relation between the output data “qcml” and full rate output clock “cho” is specified inTable 1 and illustrated by Fig. 3.
Table 1. Output Data-to-Clock Phase Difference

Junction temperature,
τ, psºC
Min. Max.
-25
7780
5082861258791clk edge

τOutput
DataTclk
Fig. 3. Output Timing Diagram

TERMINAL FUNCTIONS
The description of the package pins is presented in the table below.
TERMINAL
NameNo.
TypeDESCRIPTION

High-Speed I/Os
37 Output CML differential clock outputs. Require external SE 50Ohm
termination to “vcc”. Can be disabled by “offcho”.
36
43 Output CML differential data outputs. Require external SE 50Ohm
termination to “vcc”.
42chopchon
qcmlp
qcmln

Controls
lol1n
ftr1p
ftr1n
offchooff12gbitorderRev.: 1,21 LS Out, PLL lock indicator (high: locked; low: no lock).
CMOS
22 I/O PLL external filter connection (1nF capacitor differential).
2320 LS In., HS COB control (active: high, buffer is disabled; active: low,3-state full-rate clock; default: not connected, half-rate clock).
24 LS In., VCO frequency selection (active: high, 11.0GHz; default: low,CMOS 11.8GHz).
60 LS In., Input bit order selection (active: high, d15 is serialized first;
CMOS default: low, d00 is serialized first).

Sept 2008.

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ASNT1012-PQA

A D S A N T E C

A d v a n c e dS c ie n c ea n d
N o v e lT e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

Low-Speed I/Os
cr16p
cr16n
clopclon
d00p
d00n
d01p
d01n
d02p
d02n
d03p
d03n
d04p
d04n
d05p
d05n
d06p
d06n
d07p
d07n
d08p
d08n
d09p
d09n
d10p
d10n
d11p
d11n
d12p
d12n
d13p
d13n
d14p
d14n
d15p
d15n

Rev.: 1,14 Input LVDS clock inputs.
1548 Output LVDS clock outputs.
47
61 Input
62
64
65
67
68
70
71
76
77
79
80
82
83
85
86
LVDS data inputs.
88
89
90
91
93
94
96
97
99
100
56
8
91112

Sept 2008.

5ASNT1012-PQA

A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

Supply and Termination Voltages
Name
vcc
veenc

Description
Positive power supply.
(+3.3V)
Negative power supply.
(GND or 0V)
Unconnected pin.

Pin Number
1, 7, 10, 13, 16, 29, 32-35, 38-41, 44, 45, 49, 55, 63,66, 69, 72, 78, 81, 84, 87, 92, 95, 98.
3, 17, 25, 26, 50, 51, 58.
2, 18, 19, 27, 28, 30, 31, 46, 53-54, 56, 57, 59, 73-75.

ELECTRICAL CHARACTERISTICSPARAMETER
VCC
VEEPower consumption
Junction temperature
Data Rate
Differential Swing
CM Voltage Level
Frequency
Differential Swing
CM Voltage Level
Data Rate
Logic “1” level
Logic “0” level
JitterFrequency
Logic “1” level
Logic “0” level
JitterDuty Cycle
Frequency
Interface
Logic “1” level
Logic “0” level

MIN

TYP MAXUNIT
COMMENTS
General Parameters+3.14+3.3+3.47
±5%
V0.0V
660
mW-2550125°C
LS Input Data (d00-d15)
612.5
780
Mbps
0.06
0.8
Peak-to-peak
VVEE
VCC
V
LS Input Reference Clock (cr16)
612.5
780
MHz
0.06
0.8
Peak-to-peak
V
VEE
VCC
V
HS Output Data (qcml)
9.8
12.5
Gbps
VCC
V
VCC-0.6
V
12
Peak-to-peak @12.5Gb/s
ps
HS Output Clock (cho)
4.9
12.5
GHz
VCC
V
VCC-0.6
V
6
Peak-to-peak @12.5GHz
ps50%
LS Output Clock (clo)
612.5
780
MHz
LVDS
Meets the IEEE Std.
CMOS Control Inputs/Outputs
VCC-0.4
VVEE+0.4
V

PACKAGE INFORMATIONThe chip is packaged in a standard 100-pin QFN package. The package’s mechanicalinformation is available on the company’s website.
Rev.: 1,Sept 2008.

6

ASNT1012-PQA