Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT2111-KMF
Programmable CDR DMUX 1-to-2
1:2 demultiplexer (DMUX) with integrated full-rate CDR

Input data range from 18Gb/s to 36Gb/s

NRZ input data format

CML compliant differential input and output high-speed data and clock interfaces
1.3V CMOS 3-wire interface for digital controls

LVDS or CML compliant input reference clock interface

Full-rate clock and retimed data output for 1:1 CDR operationHalf-rate data outputs with toggle synchronization functionality

Signal inversion and muting capabilities in all output buffers

Single +3.3V or -3.3V power supply

Low power consumption of 1.8W at the maximum operational speedIndustrial temperature rangeCustom CQFP 64-pin package
vee
vcc
dop
vcc
don
vcc
3wdo
3wdin
3wcin
3wenin
vcc
c2p
vcc
c2n
vcc
vee



ASNT2111

vee
vcc
q0p
vcc
q0n
vcc
nc
lolp
nc
nc
vcc
q1p
vcc
nq1n
vcc
veeveevcc
nc
vcc
nc
vcc
nc
ftr
vcc_vco
ncvcc
c32p
vcc
c32n
vcc
vee

vee
vee
pkdtp
pkdtn
dcinp
vcc
vcc
dp
vcc
dnvcc
vcc
dcinn
nc
vee
vee

Rev. 1.0.2

1October 2020

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DESCRIPTION
DOBd
dcinp
dcinn
pkdtp
pkdtn

DataIB

c32

CLKIBDCDR

DMX
1:2

c2

onco

ondo

ond2o

DAC
rangecrl<7:0>

vcosel<2:0>togpol
upicppupicpfCOB
offcml

q0

q1

C2

lolp
fltp

3wdin
3wcin
3wenin3wdo

D2OBx2

do3-Wire Interface

Fig. 1. Functional Block Diagram

ASNT2111-KMF is a 1:2 demultiplexer (DMUX) with full-rate integrated clock and data recovery(CDR). The IC shown in Fig. 1 functions in CDR mode covering a wide range of input data rates (fbit) byutilizing its six on-chip VCOs (voltage-controlled oscillators). To reduce the physical number of control
inputs to the chip, a shift register with a 3-wire input interface (SPI) has been included on chip. The SPI
block provides all the digital controls for the chip. It also provides digital controls for digital-to-analog
converters (DACs) that handle internal analog DC voltage adjustments.
Selection of the desired working data rate of the CDR is accomplished through the digital control vcosel(see Table 1). An external low speed system clock c32p/c32n running at 1/32 the frequency of the active
VCO must be applied to the low-speed clock input buffer (CLK IB).
The main function of the chip is to convert a RZ or NRZ input data signal dp/dn with a bit rate of fbit
accepted by CML buffer (Data IB) into 2 parallel NRZ data signals q0p/q0n and q1p/q1n running at bit
rates of fbit/2 and delivered to the outputs by CML data output buffers (D2OBx2). The clock and data arerecovered from the input data stream by the CDR.
A full rate retimed NRZ data output signal dop/don is also available through the CML data output buffer(DOB) allowing the part to be used as a 1:1 CDR. Half rate clock c2p/c2n delivered through the CMLclock output buffer (COB) has a tight phase alignment to the demultiplexed data output signals q0p/q0n
and q1p/q1n.
Rev. 1.0.2

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Data IB can operate with either differential or single-ended input signals. It includes tuning pins
dcinp/dcinn for DC offset of the input signals in case of AC termination. When the buffer is operatingwith a DC-terminated single ended input signal, a correct threshold voltage should be applied to theunused input pin. A peak detector is also included to provide means of demodulating AM components
carried by the input data with frequency ranges of up to a few hundred kHz. The peak detector’s output
signal is delivered to the differential port pkdtp/pkdtn.
All CML I/Os provide on chip 50Ohm termination to vcc and may be used differentially, AC/DC
coupled, single-ended, or in any combination (see also POWER SUPPLY CONFIGURATION). Output
buffers DOB, COB, and D2OBx2 can be individually disabled through control bits ondo, onco, andond2o to save power.
Utilizing control bit pol, the deserializer can invert the polarity of the three output data signals. Control bit
tog flips the order of q0p/q0n and q1p/q1n signals thus simplifying the interface between the DMUX
and a following ASIC. It also allows for synchronization of the bit order of two or more DMUXes
working in parallel.
A loss of lock CMOS alarm signal lolp is generated by the CDR to indicate its locking state. An off chippassive filter is required by the CDR, and should be connected to pin ftr (see CDR).
The deserializer is characterized for operation from 0°C to 125°C of junction temperature. The package
temperature resistance is 15°C /W.

Data IBThe Data Input Buffer (Data IB) can process an input CML data signal dp/dn in either RZ or NRZ format
due to its high analog bandwidth. It provides on-chip single-ended termination of 50Ohm to vcc for each
input line. The buffer can also accept a single-ended signal to one of its input ports dp or dn with athreshold voltage applied to the unused pin in case of DC termination. In case of AC termination, tuning
pins dcinp/dcinn allow for data common mode adjustment. The tuning pins have 1kOhm terminations tovcc and allow the user to change the slicing level before the data is sampled by the recovered clock.
Tuning voltages from vcc to vee deliver 150mV of DC voltage shift.
Also included in Data IB is an input signal peak detector that delivers its response through the output
differential signal pkdtp/pkdtn. The detector can demodulate AM component(s) carried by the input datawith frequency ranges of up to a few hundred kHz. The detector’s output impedance is 4kOhm single
ended to vcc.

CLK IBThe Clock Input Buffer (CLK IB) consists of a proprietary universal input buffer (UIB) that can operatein either CML or LVDS mode depending on the state of digital control bit offcml. This control should be
set to “low” for CML mode and to “high” for LVDS mode. Depending on the mode of operation, theinput impedance switches between 50 Ohms to vcc single-ended in CML mode, and 100 Ohms
differential in LVDS mode. The input buffer exceeds LVDS standards IEEE Std. 1596.3-1996 andANSI/TIA/EIA-644-1995. UIB is designed to accept differential signals with a speed up to 1Gb/s, DC
common mode voltage variation between vcc and vee, AC common mode noise with a frequency up toRev. 1.0.2

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5MHz, and voltage levels ranging from 0 to 2.4V. It can also receive a DC-terminated single-ended signal
with a threshold voltage between vcc and vee applied to the unused pin.

CDRThe Clock and Data Recovery Block (CDR) contains a phase acquisition loop, and a frequency
acquisition loop. The frequency loop works in concert with low-speed clock c32p/c32n while the phaseloop utilizes input data signal dp/dn. The CDR requires a single off-chip filter shown in Fig. 2 to beconnected to the pin ftr.

66Ohmftr390pF

22nFFig. 2. External Loop Filter

The main function of the CDR is to frequency-lock the selected on-chip VCO to the input data signal(clock recovery) while phase-aligning it to latch in the incoming data with minimal error (data recovery).
By default, the CDR aligns the recovered clock’s working edge in the middle of the incoming data bits.
The recovered clock is divided down in frequency by two (C2), and utilized by DMX 1:2 fordemultiplexation of the recovered data.
By utilizing the 3-bit digital control vcosel, the desired working frequency of the CDR can be selected inaccordance with Table 1 below.
Table 1. CDR Mode Selectionvcosel
01234567vcosel<2> vcosel<1> vcosel<0> VCO Operation Frequency (GHz)000off001fmin≤16.7, fmax≥24.5
0
10fmin≤19.4, fmax≥28.2
011fmin≤22.2, fmax≥31.6
100fmin≤25.1, fmax≥34.7
101fmin≤27.8, fmax≥37.2
110fmin≤31.0, fmax≥39.9
1
11off

The loop gain can be adjusted by two control bits upicpp and upicpf that control the charge pump current
as shown in Table 2.
Table 2. Charge Pump Current Control

upicpp upicpf Charge Pump current, mA
00Imax-0.31
01Imax-0.27
10Imax-0.04
11ImaxRev. 1.0.2

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By utilizing the control byte rngcrl the DC current of the control emitter follower of the active VCO canbe adjusted linearly. Higher values of the control result in higher emitter follower currents. Higher emitterfollower currents result in a more linear VCO frequency dependence on the control voltage at the expenseof the frequency range.
The lock detect circuitry signals an alarm through the 2.5V CMOS signal lolp when a frequency
difference exists between an applied system reference clock c32p/c32n and a recovered full rate clock
divided-by-32 that is greater than ±1000ppm.
Another feature included in the CDR is the ability to simultaneously invert the polarity of all three data
outputs through the 2.5V CMOS input pin pol (pol = “1” (default): direct; pol = “0”: inverted). The orderof the half-rate output data streams can be inverted by using the 2.5V CMOS input pin tog, which
provides means to synchronize two adjacent DMUXes operating in parallel. The synchronization process
may be accomplished by the “blind” toggling in one of the chips and leaving the task of recognizing the“right” position to downstream components (e.g. FEC chip).

DMX1:2
The 1 to 2 Demultiplexer (DMX1:2) latches in the retimed data stream D from the CDR on both edges ofthe half rate clock signal C2. The high speed data signal is subsequently demultiplexed into two half rate
NRZ data signals, and delivered to D2OBx2 in parallel fashion as a 2-bit wide word with the orderdefined by the tog signal.

DOBThe Data Output Buffer (DOB) receives a full rate retimed serial data stream D from the CDR andconverts it into a CML output signal dop/don. This CML buffer requires 50Ohm external termination
resistors connected between vcc and each output. The buffer can be enabled or disabled by the control bitondo (ondo = “1”: enabled; ondo = “0”: disabled).

D2OBx2
The Half Rate Data Output Buffer (D2OBx2) receives two half rate data signals from DMX1:2 andconverts them into CML output signals q0p/q0n and q1p/q1n. The buffer requires 50Ohm externaltermination resistors connected between vcc and each output. The buffer can be enabled or disabled by
the control bit ond2o (ond2o = “1”: enabled; ond2o = “0”: disabled).

COB
The Clock Output Buffer (COB) receives a half rate clock signal from DMX1:2 and converts it into CMLoutput signal c2p/c2n. The buffer requires 50Ohm external termination resistors connected between vcc
and each output. The buffer can be enabled, or disabled by the control bit onco (onco = “1”: enabled;onco = “0”: disabled). The negative edge of the c2 signal is aligned to the half rate output data crossing
points.

3-Wire Interface Control BlockTo reduce the physical number of control inputs to the chip, a 3-byte shift register with a 3-wire input
interface has been included on chip. The SPI block is powered by an internally generated supply voltageof +1.2V from vee. The digital control bits applied through 3wdin input are latched in and shifted down
Rev. 1.0.2
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the register with the clock 3wcin. Write enable signal 3wenin must be set to logic “0” during the dataread-in phase. The SPI data can be monitored through the output 3wdo. Table 3 presents the byte order ofthe 3-wire interface block.
Table 3. Control Bytes

Byte
Number123765Bit Number
43

upicpfX

upicppX

tog
X

rngcrl(7:0)
onco ond2oXX

210

ondo pol offcml
vcosel(2:0)

SPI load order is illustrated in Fig. 3.
3wcin
3weninSampleLatch
3wdin

X 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0 X

Byte 1

Byte NFig. 3. SPI Load Order

Rev. 1.0.2

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POWER SUPPLY CONFIGURATIONThe ASNT2111-KMF can operate with either a negative supply (vcc = 0.0V = ground and vee = -3.3V),or a positive supply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os needAC termination when connected to any devices with 50Ohm termination to ground. Different PCB layouts
will be needed for each different power supply combination.

All the characteristics detailed below assume vcc = 3.3V and vee = 0V (externalground)

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 3 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only that are specified in ELECTRICAL
CHARACTERISTICS. AC and DC device characteristics at or beyond the absolute maximum ratings are
not assumed or implied. All min and max voltage limits are referenced to ground (assumed vee).
Table 4. Absolute Maximum Ratings

ParameterMinMax
Units
Supply Voltage (vcc)+3.8VPower Consumption
1.8W
Input Voltage Swing (SE)1.0VCase Temperature*)+90ºC
Storage Temperature-40+100ºC
Operational Humidity
1098%
Storage Humidity
1098%*) - Operating the part at temperatures over this value could/will damage the part. Operating at thistemperature or any temperatures above the recommended maximum value specified in ELECTRICAL
CHARACTERISTICS does not guarantee correct functionality as is stated above.

Rev. 1.0.2

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TERMINAL FUNCTIONS
Namevccvcc_vcoveenc

Name

Supply and Termination Voltages
Description
Pin Number
Positive power supply (+3.3V)
2, 4, 6, 11, 13, 15, 18, 20, 22, 27, 29, 31, 34, 36,38, 43, 45, 47, 54, 55, 57, 59, 60
Positive power supply for VCO
9(+3.3V)
Negative power supply (GND or 0V)
1, 16, 17, 32, 33, 48, 49, 50, 63, 64
Not connected pins
3, 5, 7, 10, 23, 24, 26, 62

TERMINAL
No.
Typedpdnq1pq1nq0pq0nc2pc2n
dop
don56
58
211930283735
4644

c32p
c32n
pkdtp
pkdtn
3wenin
3wcin
3wdin
3wdo

12Input
1451
Output52
39 1.2V CMOS
input
40
41
42 1.2V CMOS
output

lolp

25

dcinp
dcinn
ftr

Rev. 1.0.2

Input
OutputOutputOutputDESCRIPTION
High-Speed I/Os
CML differential data inputs with internal SE 50Ohm termination tovcc
CML differential half rate data outputs. Require external SE 50Ohm
termination to vcc

CML differential half rate clock outputs. Require external SE 50Ohmtermination to vcc
CML differential full rate data outputs. Require external SE 50Ohmtermination to vcc
Low-Speed I/Os
CML or LVDS clock input with internal SE 50Ohm SE or differential
100Ohm termination
Peak detector outputs
Enable input signal for 3-wire interface
Clock input signal for 3-wire interface
Data input signal for 3-wire interface
Data output signal of 3-wire interface

Controls
LS out,
CDR lock indicator (high: no lock; low: locked)
2.5V CMOS
53
LS INInput data common mode voltage adjustment
618I/O
External CDR filter connection8October 2020

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ELECTRICAL CHARACTERISTICSPARAMETERTYP MAXUNIT
COMMENTS
General Parameters
+3.0
+3.3
+3.6
V
±9%
vcc
0.0
Vvee
Ivcc
535mA
All functions active
Power Consumption
1.8
W
Junction Temperature
-25
50
125°C
Case temperature
75°C
Recommended value
HS Input Data (dp/dn)
Data Rate
1836Gbps
NRZ
Swing p-p (Diff or SE)
0.05
0.6
V
CM Voltage Level
vcc-0.8vccVLS Input Reference Clock (c32p/c32n)Frequency
562.5
1.125
MHzSwing p-p (Diff or SE)
0.060.8
VCM Voltage Level
Vveevcc
Duty Cycle
405060%HS Output Full Rate Data (dop/don)Data Rate
1836Gbps
NRZ
Logic “1” level
Vvcc
Logic “0” levelvcc -0.4 vcc -0.3
VJitter78
psp-p
HS Output Half Rate Data (q0p/q0n, q1p/q1n)
Data Rate
918Gbps
Logic “1” level
Vvcc
Logic “0” levelvcc -0.4
VJitter
7psp-pHS Output Half Rate Clock (c2p/c2n)
Clock Rate
918
GHz
24 to 36Gbps input
Logic “1” level
Vvcc
Logic “0” levelvcc -0.4
vcc -0.15
VJitter
58psp-pInput Data Common Mode Control (dcinp/dcinn)
Input DC Voltage
Vveevcc
Input Data Voltage Shift
0-150mV
Referenced to vcc
Output of Peak Detector (pkdtp/pkdtn)
Swing p-p (Diff)-1
1
VOver full input range
CM Voltage Level
vcc -1.0
V
3-Wire Inputs (3wdin, 3wcin, 3wenin)
High voltage levelvee+1.1
vee+1.35
VLow voltage levelvee
vee+0.35VClock speed
350
400
MHz
Rev. 1.0.2

MIN

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PACKAGE INFORMATIONThe chip die is housed in a custom 64-pin CQFP package. The dimensioned drawings are shown in Fig. 4.
The package’s leads will be trimmed to a length of 1.0mm. After trimming, the package’s leads will befurther processed as follows:

Fig. 4. CQFP 64-Pin Package Drawing (All Dimensions in mm)

Rev. 1.0.210October 2020

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1. The lead’s gold plating will be removed per the following sections of J-STD-001D:
3.9.1 Solderability
3.2.2 Solder Purity Maintenance3.9.2 Solderability Maintenance3.9.3 Gold Removal
2. The leads will be tinned with Sn63Pb37 solder
The package provides a center heat slug located on its back side to be used for heat dissipation.
ADSANTEC recommends for this section to be soldered to the vcc plain, which is ground for a negativesupply, or power for a positive supply.
The part’s identification label is ASNT2111-KMF. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin out
count.
This device complies with the Restriction of Hazardous Substances (RoHS) per EU 2011/65/EU for all
ten substances.

REVISION HISTORY
Revision
1.0.2

Date10-20200.0.103-2020

Rev. 1.0.2

Changes
Official release
Corrected frequency range
Corrected filter schematic
Preliminary release

11October 2020