ASNT6111-KMF
30Gbps Advanced Driver/Amplifier
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High-speed limiting amplifier with selectable built-in pre-emphasis.
Four pre-emphasis taps with externally controlled weight and inversion.
Adjustable data output amplitude from 0 to 1.3Vpp single-ended.
Single-ended output data eye cross point adjustment.
Optional main clock frequency multiplier by 2.
Duty cycle indicators for the main clock before and after the multiplier.
Opposite and parallel adjustment of the main clock and data delays.
Additional clock input.
Fully differential CML input and output data and clock interfaces.
Selectable main or additional clock output with adjustable amplitude from 0 to 800mVpp.
CMOS 3-wire interface for digital controls.
On-chip linear temperature sensor.
Two power supplies: negative -4.3V and floating positive +3.5V.
Power consumption: <4W.
Custom CQFP 64-pin package.

Rev.: 3-3,May 2012

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ASNT6111-KMF

DESCRIPTION
tune 1/2/3
T1
T2

Delay

Delay

Delay

Delay

Igg
DOB

SB

d p/nI

T3
T4

Ig

Ig

vddshDdcq p/nq p/n
dampadj
xadj p/ncb_adjskwadjdlyadjvddshCco p/ncampadj

DCycl

dcyc1

Temp

temp

DCycl
dlypol

phadj

offch

ci1 p/n
3wdin
3wcin
3wenin

COB

cosel

dcyc0

Clk x2

inv 0/1/2/3

ci0 p/n3-Wire Interface
Fig. 1. Functional Block Diagram

The ASNT6111-1111-KMC SiGe IC shown in Fig. 1 is an advanced programmable driver
amplifier (ADA) with built-in pre-emphasis. ADA generates a combination of four delayedcopies of its input differential data signal “d p/n” with certain user-controlled weights andpolarities. The copies are created in a 4-bit shift register activated by internal high-speed clock
signal (see Sampling Block and Taps). This clock signal is a copy of the main input clock “ci0p/n” with either matching or doubled frequency. In the multiply-by-2 clock mode, the duty
cycles of the input and internal clock signals are monitored and the output duty cycle can be
adjusted through external control port “phadj” (see Clock Multiplier).
Input clock and data signals can be delayed in the same or opposite directions to ensure theircorrect phase relations at the inputs of the shift register and at the chip outputs (see Input DelaySection). ADA can accept one additional clock signal “ci1 p/n” and deliver it to output “co p/n”
instead of the main clock “ci0p/n”, thus operating as a clock buffer (see Additional Input Clockand Clock Output Buffer).
The part’s I/Os support CML logic interface with on-chip 50Ohm termination to ground.
Amplitude and peaking in the clock and data output signals can be externally adjusted. Bothsingle-ended data output signals also have controlled DC common-mode levels and eye crossing
points (see Data Output Buffer).
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2ASNT6111-KMF

The operational modes of the chip are controlled through a 3-wire serial interface (see 3-WireInterface Control Block).
The chip operates from one negative power supply (positive pin connected to external Ground,negative pin “vee”=-4.3V) and one floating positive power supply (negative pin connected to“vee” and positive pin “v3p5”=3.5V). It is recommended to keep the relative deviation of “v3p5”
from Ground within less than ±0.1V.

Input Delay Section
As shown in Fig. 1, ADA accepts differential input data “d p/n” and clock “ci0 p/n” signals andinserts them both into identical variable delay blocks “Delay” that can be oppositely adjusted byexternal analog control voltage “skwadj” in order to eliminate skew between the two channels.
The blocks can compensate the skew up to ±15ps. Subsequently, both input signals are further
processed by two additional “Delay” blocks that can be adjusted in parallel or opposite modes
depending on the polarity of internal digital signal “dlypol” (“0”=parallel, “1”=opposite)
provided by the 3-Wire Interface block. This second pair of “Delay” blocks allows for external
adjustment of the data vs. clock signals when operating in opposite mode or varying the delay ofthe output data and clock signals when in parallel mode. The delay adjustment range is ±75ps in
the opposite mode or 0-75ps in the parallel mode.

Clock Multiplier
The clock doubler “Clk x2” uses a “delay and XOR” mechanism to create output clock pulses
from each edge of the input clock “ci0 p/n”. The multiplier is intended for operation with input
clock signals within the frequency range from 6GHz to 15GHz. Analog control voltage “phadj”
performs a dual function. Voltages within the range from 0V to -2.0V activate the multiplication
function and are used for tuning the block’s internal delay in order to achieve 50% duty cycle ofthe multiplied clock. Voltages between -2.0V and “vee” disable the multiplication function andallow for direct passing of the input clock to the multiplier’s output. This mode should be usedfor operation with clock signal frequencies below 12GHz.
Two duty cycle control blocks “DCycl” are used for monitoring the clock pulse shapes before
and after the multiplier. The first block is positioned before the multiplier and delivers singleended analog voltage “dcyc0” that indicates the input clock’s duty cycle deviation from 50%.
The second block is positioned after the multiplier and delivers similar signal “dcyc1” for theoutput clock. Both output voltages can be used in combination with “phadj” input within external
control loops for getting an optimal shape of the multiplied clock.

Additional Input Clock and Clock Output Buffer
ADA can also accept an additional input clock signal “ci1 p/n” and deliver it to the clock output.
This allows the IC to operate solely as a clock amplifier where the output clock signal’s
amplitude supplied by output buffer “COB” can be adjusted using analog signal “campadj”. The
amplitude range is from 0Vpp (campadj≤-2.0V) to 800mVpp (campadj=0V) single ended. “COB”
can also be completely disabled by applying “campadj” voltage between -2.0V and “vee”. Either“ci0” or “ci1” clock signal can be processed by output buffer “COB”. Selection of the input
clock is accomplished through digital control signal “clock select” (“0” - ci0, “1” - ci1) deliveredby the 3-wire interface block.
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ASNT6111-KMF

Quality of the output signal shape can be optimized using control voltages “cb_adj” and“vddshC”. The first voltage controls the default position of the output eye crossing point andpeaking on the rising edge of the output signal (weak influence). The allowed voltage range isfrom 0V to “vee”. The second (positive) voltage controls peaking on the falling edge of theoutput signal (strong influence). The allowed voltage range is from 1.8V to 4.3V with thenegative pin of the supply connected to “vee”. In both cases, more positive voltages correspondto more peaking.

Sampling Block and Taps
Sampling block “SB” is essentially a 4-bit shift register that generates 4 delayed bits “T1-T4”
needed for ADA’s 4-tap pre-emphasis capability. As stated above, analog control voltage“dlyadj” is used to adjust the phase relationship between clock and data to ensure optimum
sampling in SB. All four samples delivered by “SB” can be independently inverted by circuit
blocks “I”, where the polarity of the signals is set by four control signals “inv 0/1/2/3”(“0”=direct, “1”=inverted) provided by the 3-wire interface.
The weights of taps are set by the gain adjustment blocks “g” that are controlled by a special
current distributing circuitry using three external analog voltages “Tune 1/2/3”. The circuitry
operates in such a way that the first control voltage “Tune 1” either defines the fraction of themain current that is used in the first tap (0V corresponds to full current and -2.0V corresponds tono current), or disables the first tap completely (voltages below -2.0V). The remaining current is
distributed between the second and the third taps in the same way in accordance with the valueof the second control voltage “Tune 2”, and then between the third and the fourth taps inaccordance with the value of the third control voltage “Tune 3”. Thus, the total current (andweight) is independent from the number of activated taps and their individual settings. Highvalue (~0V) of a certain “Tune X” signals can be used for disabling all subsequent taps based oninternal thresholds. This function can be activated/deactivated through digital control signal“offch” (“0” – thresholds activated, “1” – thresholds deactivated) delivered by the 3-wireinterface block. The combined current from the taps is delivered to data output buffer “DOB” forthe final signal conditioning.

Data Output Buffer
Data output buffer “DOB” includes several features to tune the output data signal generated byADA. Similar to “COB”, adjustment of the output data’s amplitude is possible by means ofexternal analog control voltage “dampadj”. The amplitude range is from 0.0Vpp (dampadj≤2.0V) to 1.3Vpp (campadj=0V) single-ended.
Differential analog control voltage “xadj p/n” can be utilized to adjust the crossing points in the
single-ended output eyes. At the default state of “xadjp”= “xadjn”=0V, the crossing points inboth direct and inverted eyes should be centered. The crossing points are moving up in the direct
eye and down in the inverted eye if “xadjp”=-“xadjn”>0, or in the opposite directions if“xadjp”=-“xadjn”<0. The allowed voltage range of ±4.0V corresponds to shifts of the crossing
points up to ±25% of the eye amplitude.
Quality of the output signal shape can be optimized using control voltages “cb_adj” and“vddshD” as described in Clock Output Buffer section above.
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Finally, 1.0KOhm resistors are attached to both data outputs “qp” and “qn” to provide DC
shifting of the output signals. Access to the resistors is through the control pins “dcq p/n”. Theallowable DC voltage that can be applied to those pins is from 0 to “vee”.

3-Wire Interface Control BlockTo reduce the physical number of digital control inputs to ADA, an 8-bit shift register with a 3wire input interface has been included on chip. The digital control bits applied through “3wdin”
input are latched in and shifted down the register by negative edges of low-speed clock “3wcin”.
Write enable signal “3wenin” must be set to logic 1 during the data read-in phase and then set tologic 0 to retain the shifted in values after 8 clock periods of “3wcin”. All input signals shouldhave voltage levels of V”1”=0V and V”0”=-3.3V. The maximum frequency of “3wcin” clock is
100KHz. Table 1 below maps the input 8-bit word to the internal digital control signals.
Table 1. 3-Wire Interface Bit Map.

Input Digital Data Byte “3wdin”Internal Digital Control Signal

8th Bit (last serial bit)

tap1 inversion (“0”=direct, “1”=inverted)

7th Bit

tap2 inversion (“0“=direct, “1“=inverted)

6th Bit

tap3 inversion (“0“=direct, “1“=inverted)

5th Bit

tap4 inversion (“0“=direct, “1“=inverted)

4th Bitdlyadj polarity (“0“=parallel, “1“=opposite)

rd

3 Bit

output clock select (“0“=ci0, “1“=ci1)

nd

2 Bit

tap thresholds (“0“=enabled, “1“=disabled)

1 Bit (first serial bit)

Not usedstTemperature Sensor
A linear temperature sensor is included on chip. Its behavior is illustrated in Fig. 2 below.

Fig. 2. Temperature Sensor’s Characteristic.

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5ASNT6111-KMF

TERMINAL FUNCTIONSTERMINAL
Name No.
Type
dp
dn
ci0p
ci0n
ci1p
ci1n
cop
con
qp
qn

19 CML21 Inputs
28
30
35
37
46 CML
44 Outputs
56
58

3wenin 39 3.3V
3wcin 40 CMOS
3wdin 41 Inputs

Description
High-Speed I/Os
Differential high-speed data inputs
Differential high-speed main clock inputs
Differential high-speed additional clock inputs
Differential high-speed clock outputsDifferential high-speed data outputs
Low-Speed I/Os
Enable input signal for 3-wire interface
Clock input signal for 3-wire interface
Data input signal for 3-wire interface
Analog Control Voltage Inputs
Output data eye cross point adjustment, Differential

xadjp
5 Analog
xadjn
3 Inputs
tune3
7 withTap 3 weight adjustment, SE
100KOhm
tune2
8Tap 2 weight adjustment, SE
tune1
9 termination Tap 1 weight adjustment, SE
dampadj 10 to “vdd”. Data output amplitude adjustment, SE
cb_adj 12
Cascode bias current adjustment, SEdlyadj 24
Data/clock skew/output phase adjustment, SEskwadj 25
Data/clock skew adjustment, SEphadj
26
Clock multiplier delay (output duty cycle) adjustment, SEcampadj 51
Clock output amplitude adjustment, SE
dcqp
61 Analog
Direct data output common-mode DC shift, SEdcqn
62 Inputs
Inverted data output common-mode DC shift, SE
Analog Control Indicators
temp
14 Analog
Linear temperature-dependent voltage
dcyc1
50 Outputs
Linear voltage indicating output clock duty cycle
dcyc052
Linear voltage indicating main input clock duty cycle

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Supply And Termination Voltages
NameDescription
Pin Number
vddExternal ground
2,4,6,11,13,15,18,20,22,27,29,31,34,36,38,43,45,47,54,55,57,59,60
vee“-4.3V” negative power supply
17,32,33,48,64v3p5 “+3.5V” positive power supply.
1,16,23,49,63
Negative pin to “vee”
vddshC Output clock and data peaking adjustment.
42
Positivepowersupply.
Negativepinto“vee”
vddshD
53

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 2 may cause damage to thisproduct and/or lead to reduced reliability. Functional performance is specified over therecommended operating conditions for power supply and temperature only. AC and DC device
characteristics at or beyond the absolute maximum ratings are not assumed or implied. All min
and max voltage limits are referenced to ground (assumed “vcc”).
Table 2. Absolute Maximum Ratings.

Parameter
Negative Supply Voltage (“vee”)
Positive Supply Voltage (“v3p5”)
Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Rev.: 3-3,May 2012

Min-40
10107

Max
-4.8
3.8
4.4
1.0+90+100
98
98

Units
VVW
VºCºC%%

ASNT6111-KMF

ELECTRICAL CHARACTERISTICSPARAMETER
veevcc
v3p5
Ivcc
Iv3p5
Power
Allowed junction temperature
Rate
SE Swing
CM Level

MIN TYP MAX
General Parameters-4.1-4.3-4.5
0.0
3.4
3.5
3.6
110
950
3.8
050
100
Data input (“dp/dn”)
DC30
50
200500“vcc”-(SE swing)/2Clock input (“ci0p/ci0n”, “ci1p /ci1n”)
Frequency
0.1
15
SE Swing50200
500
CM Level“vcc”-(SE swing)/2
Data output (“qp/qn”)
Rate
DC
28.6
SE Swing
0.0
1300
CM Level
Vcc
Vcc-0.65
Rise/Fall Times
101214

UNIT
V
V
V
mA
mA
W°C

COMMENTS

External ground“-“ pin to “vee”

Gb/s
mV

Peak-to-peak

GHzmV

Peak-to-peak

Gbps
mV
V
ps

Peak-to-peak
20%-80%

Clock output (“cop/con”)
Frequency
DC30
GHz
SE Swing
0.0
800mV
Peak-to-peak
CM Level
Vcc
Vcc-0.4
V
Rise/Fall Times
101214ps
20%-80%SE tuning ports (“tune 1/2/3” “skwadj” “dlyadj” “phadj” “dampadj” “campadj”)
Linear control voltage-20
V
Switch-off threshold-2V
Cross point control (“xadjp/xadjn”)
Differential voltage range-8.0
8.0
V±4V at each input
CM Level“vcc”
Current into the pin
4mA
at +4V
Current out of the pin-4mA
at -4V
Bias control (“cb_adj”)
Voltage range
veevccV
DC common mode voltage control (“dcqp/dcqn”)
Voltage range
veevccVRev.: 3-3,May 2012

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PARAMETERMIN TYP MAXUNIT
Variable supply voltages (“vddshC”, “vddshD”)
Voltage range
1.8
4.3
V
IvddshD
18mA
IvddshC
1.1mA
Duty Cycle Indicator (“dcyc0/1”)
Voltage range
-3.3
-0.8
V
Temperature Sensor (“temp”)
Voltage range
-3.3
-2.3
V
3-Wire Inputs (“3wdin” “3wcin” “3wenin”)
High voltage level
-0.2
0.0
V
Low voltage level
-3.3
-3.1
V
Clock speed
100KHzCOMMENTS“-“ pin to “vee”
All 4 taps active.

PACKAGE INFORMATIONThe chip die is housed in a custom 64-pin CQFP package. The dimensioned drawings are shownin Fig. 3. The package’s mechanical information is also available on the company’s website.
The package’s leads will be trimmed to a length of 1.0mm. After trimming, the package’s leads
will be further processed as follows:
1. The lead’s gold plating will be removed per the following sections of J-STD-001D:
3.9.1 Solderability
3.2.2 Solder Purity Maintenance3.9.2 Solderability Maintenance3.9.3 Gold Removal
2. The leads will be tinned with Sn63Pb37 solder.
Even though the package provides a center heat slug located on the back side of the package tobe used for heat dissipation, ADSANTEC does NOT recommend for this section to be soldered
to the board. If the customer wishes to solder it, it should be connected to “vcc” plain that isground for the negative supply or power for the positive supply.
The part’s identification label is ASNT6111-KMC. The first 8 characters of the name before thedash identify the bare die including general circuit family, fabrication technology, specific circuit
type, and part version while the 3 characters after the dash represent the package’s manufacturer,type, and pin out count.
This device complies with the Restriction of Hazardous Substances (RoHS) per EU 2002/95/EC
for all six substances.

Rev.: 3-3,May 2012

9ASNT6111-KMF

Fig. 3. Package Drawing.

REVISION HISTORY
Revision
3-3

Date
05-2012

3-2

04-20123-1

12-2011

Rev.: 3-3,

Changes
Corrected description
Corrected Electrical Parameters (based on measurements)
Added Pin Diagram
Added Absolute Maximums Rating table
Revised Package Information section
Added Revision History table
First release
May 2012

10ASNT6111-KMF