Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT8120-KMC
DC-28.6Gbps Linear Phase Detector

Output clock duty cycle indicatorData edge density indicator

Fully differential CML input data and clock interfaces

Fully differential CML-type output phase error interface with 300mV single-ended swingSingle +3.3V or -3.3V power supplyPower consumption: 760mWFabricated in SiGe for high performance, yield, and reliability

Custom CQFP 24-pin packageveeSelectable input clock multiplier by 2 with externally adjustable duty cycle

vcc



pern

Adjustable data input equalizer with a by-pass possibility

vcc



perp

Broadband linear phase detector with differential output

vcc

ed

vcc

vcc

dp

cp

ASNT8120
ASNT5111

vcc

vcc

dncn

vcc

vcc

Rev. 2.1.2

1

vcc

dcyc

vcc

eqadj

vcc

vee

phadj

February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION

dpdnEQ

eqadj

cpcnphadj

SELPhaseDet.

perp
pernedDuty
Cycle
Cntrl.

dcyc

CMP

Cx2

SEL

CMPFig. 1. Functional Block Diagram

The ASNT8120-KMC SiGe IC shown in Fig. 1 provides a differential phase error signal perp/pern thatindicates the phase difference between the data dp/dn bit transitions and the edges of the input clock
cp/cn. The input data spectrum can be corrected by the equalizer EQ with a frequency response
adjustable by the variation of the control input signal eqadj within the voltage range from vcc to vcc-2V.
The lower values of eqadj disable the equalizer and send the input data signal directly to the phasedetector block PhaseDet. The input clock can be delivered to the phase detector block either directly or
through the multiplier by 2 Cx2 with its output duty cycle adjustable by means of the phadj control
voltage. The phadj control operates similar to eqadj with a tunable range from vcc to vcc-2V and amultiplication enabling threshold value of vcc-2V.
The phase detector also provides two single-ended signals ed and dcyc. The ed output delivers an analog
voltage indicating the number of transitions in the data bit stream. The duty cycle control block
DutyCycleCntrl generates the analog signal dcyc that indicates the clock duty cycle deviation from 50%.
The part’s differential input clock and data ports support the CML logic interface with on chip 50Ohm
termination to vcc and may be used differentially, AC/DC coupled, single-ended, or in any combination(see also POWER SUPPLY CONFIGURATION). In the DC-coupling mode, the input signal’s commonmode voltage should comply with the specifications shown in ELECTRICAL CHARACTERISTICS. In
the AC-coupling mode, the input termination provides the required common mode voltage automatically.
The output phase error port supports a CML-type interface with on chip 100Ohm termination to vcc andmay be used differentially, AC/DC coupled, single-ended, or in any combination (see also POWER
SUPPLY CONFIGURATION). The differential DC signaling mode is recommended for optimalperformance.
Rev. 2.1.2

2February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Equalizer
The simulated equalizer frequency response at different values of the eqadj signal is shown in Fig. 2 andits simulated control characteristic is shown in Fig. 3.

Fig. 2. Equalizer Frequency Response at Full, Half, and No Gain

Equalizer Gain at 15GHz vs. Tunning Voltage
25Gain (dB)

2015

10

50-2

-1.8

-1.6

-1.4

-1.2

-1-0.8-0.6-0.4-0.20Tunning Voltage (V)Fig. 3. Equalizer Control Characteristic

Rev. 2.1.2

3February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Clock Multiplier
The multiplier operation is illustrated in Fig. 4 which shows the dcyc output voltage vs. the phadj input
duty cycle control value for the case of multiplication by 2 of a 14.3GHz input clock.

Fig. 4. Measured Duty Cycle Voltage vs. phadj Input Control Voltage at Different Clock Frequencies

Phase Detector
Transfer characteristics of the phase detector at 10Gb/s (measured) and 28.6Gb/s (simulated) data rates
are shown in Fig. 5 and Fig. 6 respectively.

Rev. 2.1.24February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com
ASNT8120 ErrDet Out
400300Phase Error, mV

200

1000-100-200-300
385

395

405

415

425

435

445

455

465

475

485

Delay, psFig. 5. Measured Phase Detector Characteristic at 10Gb/s Data Rate

400300200mV1000-100-200-300-40005101520253035ps

Fig. 6. Simulated Phase Detector Characteristic at 28.6Gb/s Data Rate

Rev. 2.1.2

5February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

The edge density detector operation is illustrated in Fig. 7 for 10Gb/s data rate.

Edge Density-1

ED Output Voltage-1.1-1.2-1.3-1.4-1.5024

6810121416

Number of Logic "1"s16-bit PatternFig. 7. Measured Edge Density Characteristic at 10Gb/s Data Rate

POWER SUPPLY CONFIGURATION
The part can operate with either negative supply (vcc = 0.0V = ground and vee = −3.3V), or positivesupply (vcc = +3.3V and vee = 0.0V = ground). In case of the positive supply, all I/Os need ACtermination when connected to any devices with 50Ohm termination to ground. Different PCB layouts
will be needed for each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vcc).
Rev. 2.1.2

6February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max-3.6
0.84
1.0+90+1009898

Units
VW
VºC
ºC%%

TERMINAL FUNCTIONSTERMINAL
Name
No.
Type

DESCRIPTION

Namevcc

High-Speed I/Os
21
CML Differential high-speed data input signals with internal SE
input 50Ohm termination to vcc
2311
CML Differential high-speed clock input signals with internal SEinput 50Ohm termination to vcc
917
Analog Differential phase error output with internal SE 100Ohm
output terminations to vcc.
15
3
Analog Equalization level adjust / equalizer enableinput
7
Analog Duty cycle adjust / clock multiplier enableinput
5
Analog Duty cycle indicator signal
output19
Analog Edge density indicator signal
outputSupply and Termination Voltages
Description
Pin Number
Positive power supply (+3.3V or 0)2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24

vee

Negative power supply (0V or -3.3V)

dpdncpcnperpperneqadj
phadj
dcyc
edRev. 2.1.2

71, 13February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETER
veevccIvee
Power consumption
Junction temperature
Data Rate
Swing
CM Voltage Level
Frequency
Swing
CM Voltage Level
Linear range
CM Voltage Level
Linear control range
Switching threshold
Voltage range

MIN

TYP

MAX UNITCOMMENTS
General Parameters-3.1-3.3-3.5
V±6%0.0V
External ground230mA760mW-4025125°C
HS Input Data (dp/dn)
DC28.6Gbps
10300
mV
Differential or SE, p-p
vcc-0.3vcc
VMust match for both inputs
HS Input Clock (cp/cn)
DC14.3GHz
10300
mV
Differential or SE, p-p
vcc-0.3vcc
VMust match for both inputs
Phase Error Output (perp/pern)
300mV
Single-ended
vcc-0.275
V
Tuning ports (eqadj, phadj)
-20V
-2
V
Output indicators (ed, dcyc)-3.30.0V

PACKAGE INFORMATIONThe chip die is housed in a custom 24-pin CQFP package shown in Fig. 8. The package provides a center
heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for thissection to be soldered to the vcc plain, which is ground for a negative supply, or power for a positivesupply.
The part’s identification label is ASNT8120-KMC. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin out
count.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all tensubstances.

Rev. 2.1.2

8February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Fig. 8. CQFP 24-Pin Package Drawing (All Dimensions in mm)

Rev. 2.1.2

9February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
2.1.2
2.0.2
2.0.1

Date02-2020
07-2019
03-2013

1.2.1
1.1.1

08-201208-2012

1.007-2009

Rev. 2.1.2

Changes
Updated Package Information
Updated Letterhead
Revised title
Revised description
Revised absolute maximum ratings
Revised terminal functions
Revised electrical characteristics
Revised package information
Added mechanical drawing
Revised format
Updated formatting
Added pin out drawing
Added power supply configuration text
Added absolute maximum ratings table
Revised electrical characteristics section
Revised package information section
Added revision historyModified format
First release10

February 2020