Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT5141-KMC
4-30GHz Frequency DoublerFully differential CML input interfaces

Fully differential CML output interface with 400mV single-ended swingSingle +3.3V or -3.3V power supplyPower consumption: 545mWFabricated in SiGe for high performance, yield, and reliability

Custom CQFP 24-pin packagevee

Ideal for high speed proof-of-concept prototypingvcc

vcc

Exhibits low jitter and limited temperature variation over industrial temperature range

vcc

vcc

High speed frequency doubler

vcc

vee

vcc

vcc

ip

outp

ASNT5141

vcc

vcc

inoutnvcc

vcc

Rev. 5.4.2

1vcc

icntn

vcc

icntp

vcc

vee

vee

June 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION

5050

ip

outp

MULT
coreinoutn

5050100
icntp

100
icntn

Fig. 1. Functional Block Diagram

This temperature stable SiGe IC provides broadband frequency multiplication, and is intended for use inhigh-speed measurement / test equipment. The IC shown in Fig. 1 can receive a high-speed clock input
signal ip/in, which is delivered to its input buffer chain, distributing it to two delay paths inside theMULT core, which in turn provide a high-speed double frequency clock output signal outp/outn while
controlling its duty cycle via tuning port icntp/icntn.
The minimum frequency of operation of this device is set by the internal delay paths. There are two delay
paths as mentioned before, and as shown in Fig. 2.

Fig. 2. Operational block diagram

One of them is a static delay path with a maximum delay of approximately 38ps. The other is a dynamic
delay path with a range from 90ps to 168ps. The minimum frequency of operation is achieved bysubtracting the static delay of 38ps from the maximum shift possible on the dynamic delay of 168ps. This
Rev. 5.4.2
2June 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

result in a net relative delay of 130ps, which provides the maximum shift of the clock signal, to ensurethat proper multiplication occurs. Since only a ¼ of the period relative shift is required to achieve aproper 50% duty cycle multiplication on the output, the maximum allowed clock period is 130x4=520ps.
This period is equivalent to approximately 1.9GHz. Therefore, it is safe to say that the minimum input
frequency that can be multiplied reliably is approximately 2GHz. This is shown in Fig. 3.
The maximum frequency of operation is limited by the switching speed of the XOR gate, and the delay
cells themselves. This frequency has been found to be about 15GHz. The corresponding simulation
results are shown in Fig. 4.

Fig. 3. Minimum frequency of operation at 2GHz input

Fig. 4. Maximum frequency of operation at 15GHz input

Rev. 5.4.2

3June 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

The part works best if the input clock signal’s duty cycle is as close to 50% as possible; therefore if asingle ended signal is applied to ip, input in can be used to adjust the DC common mode voltage using aseparate voltage source. This adjustment allows setting the voltage threshold to the correct input commonmode point to create an almost ideal 50% duty cycle input clock signal.
The part’s I/O’s support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (also see POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.

POWER SUPPLY CONFIGURATION
The part can operate with either a negative supply (vcc = 0.0V = ground and vee = −3.3V), or a positivesupply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os need AC termination
when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be neededfor each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vcc).
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Rev. 5.4.2

Min-4010104

Max-3.6
0.60
1.0+90+100
98
98UnitsVW
VºCºC%%

June 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

TERMINAL FUNCTIONSTERMINAL
NameNo.
Typeipinoutp
outn
icntp
icntn
Namevccvee

DESCRIPTION

High-Speed I/Os
Differential clock inputs with internal SE 50Ohm termination
to vccDifferential clock outputs with internal SE 50Ohm termination
to vcc. Require external SE 50Ohm termination to vcc
Differential tuning ports with internal 100Ohm termination tovcc
Supply and Termination Voltages
Description
Pin Number
Positive power supply (+3.3V or 0)2, 4, 6, 8, 10, 12, 14, 15, 16, 17, 18,20, 22, 24
Negative power supply (0V or -3.3V)
1, 7, 13, 192123
11935

CML
input
CMLoutput
CMLinput

ELECTRICAL CHARACTERISTICSPARAMETERveevcc
Ivee
Power consumption
Junction temperature
Frequency
Swing
CM Voltage Level
Frequency
Logic “1” level
Logic “0” level
Rise/Fall times
Output Jitter
Duty cycle
Bandwidth
Swing
CM Voltage Level
Rev. 5.4.2

MIN

TYP

MAX UNITCOMMENTS
General Parameters
-3.1
-3.3
-3.5
V
±6%
0.0
V
External ground
165mA545mW-4025125°C
HS Input Clock (ip/in)
215GHz0.05
1.0VDifferential or SE, p-p
vcc-0.8
vcc
VMust match for both inputs
HS Output Clock (outp/outn)
430
GHzVvccvcc-0.4
VWith external 50Ohm DC termination
6810ps20%-80%1ps
Peak-to-peak
455055%For clock signal
Tuning port (icntp/icntn)
DC100
MHz
vcc-0.4
VDifferential
vcc-0.4vcc
VMust match for both inputs
5June 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Figure 5. CQFP 24-Pin Package Drawing (All Dimensions in mm)

Rev. 5.4.2

6June 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATIONThe chip die is housed in a custom 24-pin CQFP package shown in Figure 5. The package provides acenter heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends forthis section to be soldered to the vcc plain, which is ground for a negative supply, or power for a positivesupply.
The part’s identification label is ASNT5141-KMC. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin out
count.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

REVISION HISTORY
Revision
5.4.2
5.3.2
5.2.2
5.2.1

Date
06-2020
02-2020
07-2019
12-2015

5.1.1

08-2015

5.0.103-2013

4.010-2008

3.0
2.0
1.006-2007
04-2007
01-2007

Rev. 5.4.2

Changes
Updated format of the description and captions
Updated Package Information
Updated Letterhead
Updated description section
Added Figure 2, 3, and 4
Corrected title
Corrected frequency of operation range
Revised power supply configuration section
Revised absolute maximum ratings section
Revised electrical characteristics
Revised package information
Corrected title
Added package pin out drawing
Revised functional block diagram
Revised description
Added power supply configuration
Added absolute maximum ratings
Revised terminal functions
Revised electrical characteristics
Added package information and mechanical drawing
Format correction
Revised electrical characteristics section
Revised packaging information section
Revised electrical characteristics section
Revised terminal functions section
First release

7

June 2020