Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT1011A-KMA
DC-to-17Gbps Digital Multiplexer 16:1 / Serializer


Broadband digital serializer 16 to 1 operating seamlessly from DC to 17Gbps

LVDS compliant input data buffers



Full-rate clock output



Clock divided-by-16 LVDS output buffer with 90°-step phase selectionSingle +3.3V power supplyIndustrial temperature range

Low power consumption of 660mW at 17Gbps

Custom 100-pin CQFP package (12mm x 12mm)

Rev. 2.3.2

1January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION

Fig. 1. Functional Block Diagram

ASNT1011A-KMA is a low power and high-speed digital 16-to-1 multiplexer (MUX) / serializer IC. The IC
shown in Fig. 1 functions seamlessly over data rates (fbit) ranging from DC to 17Gbps.
The main function of the IC is to multiplex 16 parallel data channels running at a bit rate of fbit/16 into a highspeed serial bit stream running at fbit. It provides a high-speed output data channel for point-to-point datatransmission over a controlled impedance media of 50Ohm. The transmission media can be a printed circuitboard or copper coaxial cables. The functional distance of the data transfer is dependent upon the attenuation
characteristics of the transportation media and the degree of noise coupling to the signaling environment.
During normal operation, the serializer’s low-speed input buffer (LS DIBx16) accepts external 16-bit wide
parallel data words d00p/d00n-d15p/d15n through 16 differential LVDS inputs and delivers them to themultiplexer’s core (MUX16:1) for serialization. A full rate clock must be provided by an external source
cep/cen to the high-speed clock input buffer (HS CIB) where it is routed to the high speed clock output buffer(HS COB) and the internal divider-by-16 (/16). The divider provides signaling for MUX16:1 and produces afull rate clock divided-by-16 “C16” for the low speed LVDS compliant clock output buffer (LVDS COB).The
phase of clop/clon can be modified by 90° increments by utilizing pins phs1 and phs2 and the clock
processing block (CLK Proc).
Rev. 2.3.2

2January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

By utilizing pin bitorder, the serializer can designate either d00p/d00n or d15p/d15n as the MSB thus
simplifying the interface between ASNT1011A-KMA and a proceeding ASIC.
The serialized words are transmitted as 2-level signals qcmlp/qcmln by a differential CML output buffer (DataOB). A full-rate clock is transmitted by HS COB in parallel with the high-speed data. The clock and dataoutputs are well phase matched to each other resulting in very little relative skew over the operating temperature
range of the device. Both output stages are back terminated with on-chip 50Ohm resistors.
The serializer uses a single +3.3V power supply and is characterized for operation from −25°C to 125°C ofjunction temperature.

LS DIBx16
The Low-Speed Data Input Buffer (LS DIBx16) consists of 16 proprietary universal input buffers (UIBs) thatexceed the LVDS IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995 standards. UIB is designed to accept
differential signals with amplitudes above 60mV peak-to-peak (p-p), DC common mode voltage variation
between the negative vee and positive vcc supply rails, and AC common mode noise with a frequency up to
5MHz and voltage levels ranging from 0 to 2.4V. It can also receive single-ended signals with amplitudes above
60mVp-p and threshold voltages between vee and vcc. The input termination impedance is set to 100Ohm
differential.

HS CIBThe High-Speed Clock Input Buffer (HS CIB) can process an external CML clock signal cep/cen withfrequencies from DC to 17GHz. It can also accept a single-ended signal to cep/cen with a threshold voltage
applied to the unused cen/cep pin. HS CIB can handle input signal amplitudes between 200mV and 1.2V p-p
differential or single-ended. The buffer utilizes on-chip single-ended termination of 50Ohm to vcc for each
input line.

/16The Divider-by-16 (/16) includes 4 divide-by-2 circuits connected in series. The high-speed clock “C” is fed
into the first divide-by-2 circuit that generates half rate clock “C2”. “C2” is routed internally to the next divideby-two circuit and outside of the block to MUX16:1. Other divided down clock signals are formed and routed toMUX16:1 in similar fashion. “C16” is passed on to LVDS COB to become the output low speed clock signal
clop/clon.

MUX16:1
The 16 to 1 Multiplexer (MUX16:1) utilizes a tree type architecture that latches the incoming data on thenegative edge of the “C16” clock signal that is supplied by /16. The 16-bit wide data word is subsequently
multiplexed and delivered to Data OB as a single serial data stream running at a data rate up to 17Gbps. Thelatency of this circuit block is equal to roughly one period of “C16”. The input MSB corresponds to d00p/d00n
when bitorder = 0 (default), or to d15p/d15n when bitorder = 1.

Data OBThe Data Output Buffer (Data OB) receives high-speed serial data from MUX16:1 and converts it into the CML
output signal qcmlp/qcmln with a single ended swing of 600mV. The buffer requires 50Ohm externaltermination resistors connected between vcc and each output to match its internal 50Ohm resistors and canoperate at a data rate up to 17Gbps.
Rev. 2.3.2
3January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

HS COBThe High Speed Clock Output Buffer (HS COB) utilizes the same termination scheme as Data OB and canoperate at a frequency up to 17GHz while producing a single-ended CML output swing of 600mV. The buffer
can be enabled or disabled by the external 2-state control signal offcho. The logic “0” state provides a full-rate
clock output signal while the logic “1” state disables the buffer completely to save power.

CLK Proc
By utilizing the CMOS control pins phs1 and phs2, the phase of clop/clon can be altered in accordance with
Table 1.
Table 1. Output Clock Phase Selection

phs1
phs2
C16 phasevee (default) vee (default)
270°
180°
veevcc
90°
vcc
vee0°
vcc
vcc

LVDS COB
The LVDS Clock Output Buffer (LVDS COB) receives “C16” and converts it into an LVDS output signal
clop/clon. The proprietary low-power LVDS output buffer utilizes a special architecture that ensures operation
at frequencies up to 2.0GHz with a low power consumption level of 30mW. The buffer satisfies all therequirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995 standards.

Output Timing
The phase relation between the output data qcmlp/qcmln and the full rate output clock chop/chon is specified
in Table 2 and illustrated by Fig. 2.
Table 2. Output Data-to-Clock Phase Difference

Junction temperature,
τ,psºC
Min. Max.
-2577805082861258791
clk edge
OutputDataτ

Tclk
Fig. 2. Output Timing Diagram

Rev. 2.3.2

4January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 3 may cause damage to this product and/or
lead to reduced reliability. Functional performance is specified over the recommended operating conditions forpower supply and temperature only. AC and DC device characteristics at or beyond the absolute maximum
ratings are not assumed or implied. All min and max voltage limits are referenced to ground (assumed vee).
Table 3. Absolute Maximum Ratings

Parameter
Supply Voltage (vcc)
Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

MinMax
+3.6
0.72
1.0
+90
+100
98
98-40
1010Units
VW
VºCºC%%TERMINAL FUNCTIONSTERMINAL
NameNo.
Typecepcenchopchon
qcmlp
qcmln

Rev. 2.3.2

28
2734
33
40
39

phs1
phs2
offcho57
56
18

bitorder59

DESCRIPTION

High-Speed I/Os
Input
CML differential external clock inputs with internal SE50Ohm termination to vcc
Output CML differential clock outputs. Require external SE 50Ohm
termination to vcc
Output CML differential data outputs. Require external SE 50Ohm
termination to vcc
Controls
LS In., Low-speed output clock phase selection (default: both low)
CMOS
LS In., HS COB control (active: high, buffer is disabled; default: low,
CMOS full-rate output clock)
LS IN., Input bit order selection (active: high, d15p/d15n is serialized
CMOS first; default: low, d00p/d00n is serialized first)

5January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

TERMINAL
Name
No.
Typeclop
clon
d00p
d00n
d01p
d01n
d02p
d02n
d03p
d03n
d04p
d04n
d05p
d05n
d06p
d06n
d07p
d07n
d08p
d08n
d09p
d09n
d10p
d10n
d11p
d11n
d12p
d12n
d13p
d13n
d14p
d14n
d15p
d15n

Rev. 2.3.2

46456061636466
676970727377
78808183848687
8990929395
96
98
993467910DESCRIPTION

Low-Speed I/Os
Output LVDS clock outputs. Can transmit four different clock phases
as defined by phs1 and phs2

Input

LVDS data inputs

6January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

NamevccveeNC

Supply and Termination VoltagesDescription
Pin Number
Positive power supply
5, 8, 11, 14, 24, 25, 26, 29, 32, 35, 38, 41, 44, 47, 52,(+3.3V)55, 62, 65, 68, 71, 76, 79, 82, 85, 88, 91, 94, 97, 100
Negative power supply
1, 15, 16, 17, 23, 30, 36, 37, 50, 51, 58, 75(GND or 0V)
Unconnected pin
2, 12, 13, 19, 20, 21, 22, 31, 42, 43, 48, 49, 53, 54, 74

ELECTRICAL CHARACTERISTICSPARAMETER
vcc
vee
Power consumption
Junction temperature
Data Rate
Differential Swing
CM Voltage Level
Frequency
Swing (Diff or SE)
CM Voltage Level
Duty Cycle
Data Rate
Logic “1” level
Logic “0” level
JitterFrequency
Logic “1” level
Logic “0” level
JitterDuty Cycle
Frequency
Interface
Logic “1” level
Logic “0” level

Rev. 2.3.2

MIN

TYP MAXUNIT
COMMENTS
General Parameters+3.14+3.3+3.47
V
±5%
0.0
V
660
mW
-2550
125°C
LS Input Data (d00p/d00n-d15p/d15n)
0.0
1063
Mbps
0.06
0.8
V
Peak-to-peak
Vveevcc
HS Input Clock (cep/cen)
0.0
17GHz
0.2
1.2
V
Peak-to-peakvcc -0.8vcc
V
40%
50%
60%HS Output Data (qcmlp/qcmln)
0.0
17
Gbps
Vvcc
vcc -0.6
V
12ps
Peak-to-peak @12.5Gb/s
HS Output Clock (chop/chon)
0.0
17
GHzV
vcc
vcc -0.6
V6
ps
Peak-to-peak @12.5GHz
50%
LS Output Clock (clop/clon)
0.01063
MHz
LVDS
Meets the IEEE Std.
CMOS Control Inputs
vcc -0.4
Vvee +0.4
V

7January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATION

Fig. 3. Package Drawing

Rev. 2.3.2

8January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

The chip die is housed in a custom 100-pin CQFP package. The dimensioned drawings are shown in Fig. 3.
The package’s leads will be trimmed to a length of 1.0mm. After trimming, the package’s leads will be further
processed as follows:
1. The lead’s gold plating will be removed per the following sections of J-STD-001D:
3.9.1 Solderability
3.2.2 Solder Purity Maintenance3.9.2 Solderability Maintenance3.9.3 Gold Removal
2. The leads will be tinned with Sn63Pb37 solder
The package provides a center heat slug located on its back side to be used for heat dissipation. ADSANTEC
recommends for this section to be soldered to the vcc plain, which is power for a positive supply.
The part’s identification label is ASNT1011A-KMA. The first 9 digits of the name before the underscore
identify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 digits after the underscore represent the package’s manufacturer, type, and pin out count.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all tensubstances.

REVISION HISTORY
Revision
2.3.2
2.2.2
2.2.1

Date
01-2020
07-2019
05-2015

2.102-2012

2.001-2012

1.001-2011

Rev. 2.3.2

Changes
Updated Package Information
Letterhead Updated
Corrected Absolute Maximum Ratings section
Revised Package Information section
Updated format
Revised Description section
Revised Package Information section
Revised Electrical Characteristics section
Revised Package Information sectionAdded Absolute Maximums Rating table
Added Pin Diagram
First release

9January 2020