A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

A D S A N T E C

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

ASNT2012 (2032)
1:16 CDR-DMUX
•
•
•
•
•
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1:16 demultiplexer (DMUX) with integrated full rate CDR (clock and data recovery).
Supports multiple data rates in the 11.3-12.5Gbps range.
Supports NRZ input data format.
LVDS output data buffers that feature a low-power proprietary architecture.
Clock-divided-by-16 LVDS output buffer with 90°-step phase selection.
Single +3.3V power supply.
Industrial temperature range.
Low power consumption of 730mW at 12.5Gbps.
Available in standard 100-pin QFN package (12mm x 12mm).

DESCRIPTION
bitordn
cmr

CLK
IB
DMX
1:16

dlol

q00
16

LVDS
DOB
x16q15

CDR

ftr1
ftr2

LVDS
COB/16cls

CLK
Proc

phs1
phs2

Fig. 1. Functional Block Diagram.

Rev.: 1,October 2008.

1ASNT2012-PQA

A D S A N T E CA d v a n c e dS c ie n c ea n dN o v e lT e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

ASNT2012 is a 12.5Gbps 1:16 deserializer (DMUX) with full rate integrated clock and data
recovery (CDR). The DMUX can cover input data rates (fbit) from 11.3Gbps to 12.5Gbps byutilizing its on-chip full-rate VCO.
The main function of ASNT2012 is to demultiplex a serial input data channel “d” running at a bit
rate of fbit into 16 parallel data channels “q00-q15” running at a bit rate of fbit/16. The highsensitivity CDR block ensures accurate clock and data recovery for input data signal amplitudes
greater than 40mV peak to peak (p-p) differential or single-ended. This is accomplished with theCDR circuitry incorporating both a phase and frequency acquisition loop to recover a full rate
clock “C” from the input data stream. This recovered clock is used to sample the input data bits
before they are demultiplexed and provides a signal for the internal divider (/16). The applicationof an external low speed system clock “cmr” running at 1/16 the frequency of the VCO clock isrequired for CDR to operate correctly.
The high-speed CML data input buffer in CDR provides on-chip 50Ohm termination and isdesigned to be driven by devices with 50Ohm source impedance. The low speed clock input
buffer (CLK IB) accepts the system reference clock “cmr” through a LVDS interface anddelivers it to the CDR block.
The reconstructed serial input data is latched into the tree-type demultiplexer (DMX1:16) andsubsequently deserialized and delivered to the demultiplexer’s output as 16-bit wide low-speed
parallel words. Utilizing pin “bitordn”, the deserializer can designate either “q00” or “q15” as theMSB thus simplifying the interface between ASNT2012 and a following ASIC.
Sixteen proprietary low-power LVDS output data buffers (LVDS DOBx16) are used to deliverthe 16 data output signals “q00-q15” while a similar LVDS clock output buffer (LVDS COB)
outputs the low-speed clock signal “cls”. The buffers satisfy all the requirements of the IEEE
Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995 while only consuming 30mW each. The phase of“cls” can be modified by 90° increments by utilizing pins “phs1” and “phs2” and the low speed
clock processing block (CLK Proc).
A loss of lock system signal alarm “lol” is generated by CDR. Off chip passive filter components
are required by CDR and are connected through pins “ftr1/2”.
The deserializer uses a single +3.3V power supply and is characterized for operation from −25°C
to 125°C of junction temperature.

CDRThe Clock and Data Recovery Block (CDR) contains both a phase and frequency acquisition
loop that require an additional off-chip filter connected between the pins “ftr1p” and “ftr1n” (Fig.
2). The frequency loop works in concert with “cmr” while the phase loop utilizes “d”.
ftr1
ftr2

430
430

1nFig. 2. External Filter Schematic.

Rev.: 1,October 2008.

2ASNT2012-PQA

A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

The main function of CDR is to frequency lock the on-chip VCO to the input data signal (clockrecovery) while phase aligning it to latch in the incoming data with minimal error (datarecovery). The recovered clock is also utilized by /16 and DMX 1:16 to demultiplex the data.
The lock detect circuitry signals an alarm through the CMOS signal “lol” when a frequency
difference exists between the applied system reference clock “cmr” and recovered full rate clock
divided-by-16 that is greater than ±1000ppm.

CLK IBThe Clock Input Buffer (CLK IB) consists of a proprietary universal input buffer (UIB) thatexceeds the LVDS standards IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. UIB is
designed to accept differential signals with amplitudes higher than 60mV p-p, DC common mode
voltage variation between the negative (vee) and positive (vcc) supply rails, and AC common
mode noise with a frequency up to 5MHz and voltage levels ranging from 0 to 2.4V. It can also
receive single-ended signals with amplitudes of more than 60mV p-p and threshold voltages
between vee and vcc. The input termination impedance is set to 100Ohm differential.

/16
The Divider-by-16 (/16) includes 4 divide-by-2 circuits connected in series. The high-speed
clock “C” delivered by CDR is fed into the first divide-by-2 where its output is routed internallyto the next divide-by-two circuit and outside of the block to DMX1:16. Other divided down
clock signals are formed and routed to DMX1:16 in similar fashion. Full rate clock divided-by16 “C16” is passed on to CLK Proc for additional phase adjustment.

DMX1:16
The 1 to 16 Demultiplexer (DMX1:16) utilizes a tree type architecture that latches in the data
stream from CDR on both edges of a half rate clock signal that is supplied by /16. The highspeed data signal is subsequently demultiplexed down and delivered to LVDS DOBx16 inparallel fashion as16-bit wide words running at a data rate up to 780Mbps.

CLK Proc
By utilizing the CMOS control pins “phs1” and “phs2”, the phase of “cls” can be altered inaccordance with the table below.
“phs1”“phs2”C16S phase
VEE (default) VEE (default)
270°
VEE
VCC
180°
VCC
VEE
90°
VCC
VCC
0°

LVDS DOBx16
The LVDS Data Output Buffer (LVDS DOBx16) accepts 16-bit wide words from DMX1:16 andconverts them into LVDS output signals. Each proprietary low-power LVDS output buffer
utilizes a special architecture that ensures operation at bit rates up to 2Gb/s with a low power
Rev.: 1,October 2008.

3

ASNT2012-PQA

A D S A N T E CA d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

consumption level of 30mW. The buffer satisfies all the requirements of the IEEE Std. 1596.31996 and ANSI/TIA/EIA-644-1995. When “bitorder”=0 (default), “q00”is the MSB and when“bitorder”=1, “q15” is designated the MSB.

LVDS COB
The LVDS Clock Output Buffer (LVDS COB) receives “C16” from CLK Proc and converts it
into the LVDS output signal “cls”. The proprietary low-power LVDS output buffer utilizes a
special architecture that ensures operation at frequencies up to 2GHz with a low power
consumption level of 30mW. The buffer satisfies all the requirements of the IEEE Std. 1596.31996 and ANSI/TIA/EIA-644-1995.

Terminal Functions
The description of the package pins is presented in the table below.
TERMINAL
NameNo.
TypeDESCRIPTION

Low-Speed I/Os
cmrp
cmrn
q00n
q00p
q01n
q01p
q02n
q02p
q03n
q03p
q04n
q04p
q05n
q05p
q06n
q06p
q07n
q07p
q08n
q08p
q09n
q09p
q10n
Rev.: 1,31 Input LVDS reference clock inputs for CDR.
30
12 Output
119865100
99
97
96
94
93
91
90
89
LVDS data outputs.
88868583
82
80
October 2008.

4ASNT2012-PQA

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S c ie n c ea n d
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A D S A N T E C

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

q10p
q11n
q11p
q12n
q12p
q13n
q13p
q14n
q14p
q15n
q15p
clsp
clsn

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

7977767170686765646261
14 Output LVDS clock outputs. Can transmit four different clock phases
as defined by “phs1” and “phs2”.
15High-Speed I/Os
dpdn4342Input

CML differential data inputs with internal SE 50Ohm
termination to “vcc”.

Controls
phs1
phs2
lol
ftr1
ftr2
bitordn57 LS In., Low-speed output clock phase selection (default: both low).
56 CMOS21 LS Out, CDR lock indicator (high: locked; low: no lock).
CMOS
22 I/O External CDR filter connections.
2318 LS In., Output bit order selection (active: high, q15 is MSB; default:
CMOS low, q00 is MSB).

Supply and Termination Voltages
Namevcc

Description
Positive power supply.
(+3.3V)

Pin Number
1, 7, 10, 13, 16, 19, 29, 32-35, 38-41, 44, 45, 52, 55, 60,63, 66, 69, 72, 78, 81, 84, 87, 92, 95, 98.

vee

Negative power supply.
(GND or 0V)
Unconnected pin.

3, 17, 25, 49-51, 58.

nc

Rev.: 1,October 2008.

2, 4, 20, 24, 26-28, 36, 37, 46-48, 53, 54, 59, 73-75.

5

ASNT2012-PQA

A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

ELECTRICAL CHARCTERISTICSPARAMETER
VCC
VEEPower consumption
Junction temperature
Data Rate
Swing (Diff or SE)
CM Voltage Level
Frequency
Swing (Diff or SE)
CM Voltage Level
Duty Cycle
Data Rate
Interface

Frequency
Interface

Logic “1” level
Logic “0” level“cls” to “q0-q15” delay
variation

MIN

TYP MAX
UNIT
General Parameters+3.14+3.3+3.47V
0.0V
730mW
-2550
125°C
HS Input Data (d)
11.3
12.5
Gbps
0.04
1.2
V
VCC-0.8
VCC
V
LS Input Reference Clock (cmr)
700
780
MHz
0.06
0.8
V
VEE
VCC
V
40%
50%
60%
LS Output Data (q00-q15)
700
780
Mbps
LVDS
LS Output Clock (cls)700780LVDS

COMMENTS±5%

Peak-to-peakPeak-to-peakMeets the IEEE Std.
1596.3-1996

MHz

CMOS Control Inputs/Outputs
VCC-0.4
V
VEE+0.4
V
Timing Parameters±2.5%

Meets the IEEE Std.
1596.3-1996

Over the fulltemperature range

PACKAGE INFORMATIONThe chip is packaged in a standard 100-pin QFN package. The package’s mechanicalinformation is available on the company’s website.

Rev.: 1,October 2008.

6

ASNT2012-PQA