Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT2011-KMA
DC-to-17Gbps Digital Demultiplexer 1:16 / Deserializer



Broadband digital deserializer 1-to-16
Low-power LVDS output data buffers with a proprietary architecture
Clock-divided-by-16 LVDS output buffer with 90°-step phase selection
Single +3.3V power supply
Industrial temperature range
Low power consumption of 730mW at 17Gbps
Custom 100-pin CQFP package (13mm x 13mm)

Rev. 3.5.21May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
bitordn
q00
dData
IB

DMX
1:16

16

LVDS
DOB
x16
q15

LVDS
COBce

HS
CIB

cls

CLK
Proc

/16

phs1
phs2
Fig. 1. Functional Block Diagram

ASNT2011-KMA is a low power and high-speed digital 1 to 16 demultiplexer / deserializer IC. The IC shownin Fig. 1 can function seamlessly over input data rates (fbit) ranging from DC to 17Gbps.
The main function of ASNT2011-KMA is to demultiplex a serial input data channel dp/dn running at a bit rateof fbit into 16 parallel data channels q00p/q00n-q15p/q15n running at a bit rate of fbit/16. The high sensitivity
data input buffer (Data IB) ensures accurate operation at low input data signal amplitudes. It provides on-chip
50Ohm termination to vcc and is designed to be driven by devices with 50Ohm source impedance.
During normal operation, the received serial input data is latched into the tree-type demultiplexer DMX1:16 andsubsequently deserialized and delivered to the demultiplexer’s output as 16-bit wide low-speed parallel words.
The output MSB corresponds to q00p/q00n when bitordn = 0 (default), or to q15p/q15n when bitordn = 1.
A full rate clock must be provided by an external source cep/cen to the high-speed clock input buffer HS CIB
where it is routed to the internal divider-by-16 (/16). The divider provides signaling for DMX1:16 and produces
a full rate clock divided-by-16 C16 for the low speed LVDS compliant clock output buffer LVDS COB. Thephase of clsp/clsn can be modified by 90° increments by utilizing pins phs1 and phs2 and the clock
processing block CLK Proc.
Sixteen proprietary low-power LVDS output data buffers LVDS DOBx16 are used to deliver the 16 data output
signals q00p/q00n-q15p/q15n while a similar LVDS clock output buffer LVDS COB outputs the low-speed
clock signal clsp/clsn.
The deserializer uses a single +3.3V power supply and is characterized for operation from −25°C to 125°C ofjunction temperature.
Rev. 3.5.2

2May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Data IBThe Data Input Buffer (Data IB) can process an input CML data signal dp/dn with bit rates from DC to fbit. It
can also accept a single-ended signal to one of its pins with a threshold voltage applied to the unused pin. Data
IB can handle a wide range of input signal amplitudes. The buffer utilizes on-chip single-ended termination of50Ohm to vcc for each input line.

HS CIBThe High-Speed Clock Input Buffer (HS CIB) can process an external CML clock signal cep/cen withfrequencies from DC to fbit. It can also accept a single-ended signal to one of its pins with a threshold voltage
applied to the unused pin. HS CIB can handle a wide range of input signal amplitudes. The buffer utilizes onchip single-ended termination of 50Ohm to vcc for each input line.

/16
The Divider-by-16 (/16) includes 4 divide-by-2 circuits connected in series. The high-speed clock delivered by
HS CIB is fed into the first divide-by-2 where its output is routed internally to the next divide-by-two circuitand outside of the block to DMX1:16. Other divided down clock signals are formed and routed to DMX1:16 insimilar fashion. A full rate clock divided-by-16 C16 is passed on to CLK Proc for additional phase adjustment.

DMX1:16
The 1 to 16 Demultiplexer (DMX1:16) utilizes a tree type architecture that latches in the data stream from Data
IB on both edges of a half-rate clock signal supplied by the divider (/16). The high speed data signal issubsequently demultiplexed down and delivered to LVDS DOBx16 in parallel fashion as 16-bit wide words
running at a data rate up to fbit/16.

CLK Proc
By utilizing the CMOS control pins phs1 and phs2, the phase of clsp/clsn can be altered as shown in Table 1.
Table 1. Output Clock Phase Selection

phs1
phs2
C16S phasevee (default) vee (default)
270°
180°
vee
vcc
90°
vcc
vee
0°
vcc
vcc

LVDS DOBx16
The LVDS Data Output Buffer (LVDS DOBx16) accepts 16-bit wide words from DMX1:16 and converts theminto LVDS output signals. Each proprietary low-power LVDS output buffer utilizes a special architecture thatensures operation at bit rates up to 2Gb/s with a nominal output current of 3.5mA. The buffer satisfies all therequirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995 standards. The output MSB
corresponds to q00p/q00n when bitordn = 0 (default), or to q15p/q15n when bitordn = 1.

LVDS COB
The LVDS Clock Output Buffer (LVDS COB) receives C16 from CLK Proc and converts it into the LVDSoutput signal clsp/clsn. The proprietary low-power LVDS output buffer utilizes a special architecture that
Rev. 3.5.23May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ensures operation at frequencies up to 2.0GHz with a nominal output current of 3.5mA. The buffer satisfies all
the requirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995 standards.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 2 may cause damage to this product and/or
lead to reduced reliability. Functional performance is specified over the recommended operating conditions forpower supply and temperature only. AC and DC device characteristics at or beyond the absolute maximum
ratings are not assumed or implied. All min and max voltage limits are referenced to ground (assumed vee).
Table 2. Absolute Maximum Ratings

Parameter
Supply Voltage (vcc)
Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max+3.6
0.8
1.2+90+1009898UnitsVW
VºCºC%%TERMINAL FUNCTIONS
Namevccveenc

Supply And Termination Voltages
Description
Pin Number
Positive power supply 5, 8, 11, 14, 25, 26, 29, 32, 35, 38, 41, 44, 47, 52, 55,(+3.3V)59, 62, 65, 68, 71, 76, 79, 82, 85, 88, 91, 94, 97, 100
Negative power
1, 15, 17, 18, 23, 30, 36, 37, 50, 51, 58, 75
supply (GND or 0V)
Not connected pins
2, 19, 20, 21, 22, 24, 27, 28, 31, 42, 43, 45, 46, 48,49, 53, 54, 74

TERMINAL
NameNo.
Type

Rev. 3.5.2

dpdncepcen

40393433

phs1
phs2
bitordr

57
56
16

DESCRIPTION

High-Speed I/Os
CML differential data inputs with internal SE 50Ohm
termination to vcc
Input CML differential clock inputs with internal SE 50Ohm
termination to vcc
Controls
LS In., Low-speed output clock phase selection (default: both low)
CMOS
LS In., Output bit order selection (active: high, q15p/q15n is MSB;CMOS default: low, q00p/q00n is MSB)
Input

4May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

TERMINAL
NameNo.
TypeDESCRIPTION
Low-Speed I/Os

q00n
q00p
q01n
q01p
q02n
q02p
q03n
q03p
q04n
q04p
q05n
q05p
q06n
q06p
q07n
q07p
q08n
q08p
q09n
q09p
q10n
q10p
q11n
q11p
q12n
q12p
q13n
q13p
q14n
q14p
q15n
q15p
clsp
clsn

Rev. 3.5.2

109
7
6
4
3
99
98
96
95
93
92
90
89
87
86
84
83
81
80
78
77
73
72
70
69
67
66
64
6361601213Output LVDS data outputs

Output LVDS clock outputs. Can transmit four different clock phases
as defined by phs1 and phs2

5May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERMIN
TYP MAXUNIT
COMMENTS
General Parameters+3.14+3.3+3.47
V
±5%
vcc
0.0
V
External ground
vee
Ivcc
221mA
Power consumption
730mW
Junction temperature
-2550
125°C
HS Input Data (dp/dn)
Data Rate
01718Gbps
Swing p-p (Diff or SE)
0.040.8V
Peak-to-peak
CM Voltage Level
vcc -0.8
vcc
V
HS Input Clock (cep/cen)Frequency
0.0
1718
GHz
Swing p-p (Diff or SE)
0.2
0.8
V
Peak-to-peak
CM Voltage Level
vcc -0.8
vcc
V
Duty Cycle
4050
60%
LS Output Data (q00p/q00n-q15p/q15n)
Data Rate
0.0
1063
1125
Mbps
Interface
LVDS
Meets the IEEE Std.
1596.3-1996
LS Output Clock (clsp/clsn)
Frequency
0.0
1063
1125
MHz
Interface
LVDS
Meets the IEEE Std.
1596.3-1996
CMOS Control Inputs/Outputs
Logic “1” levelvcc -0.4
VLogic “0” levelvee+0.4
VTiming Parameters
clsp/clsn to±2.5%Over the fulltemperature range
q00p/q00n-q15p/q15n
delay variationRev. 3.5.2

6May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATION

Fig. 2. Package Drawing

Rev. 3.5.2

7May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

The chip die is housed in a custom 100-pin CQFP package shown in Fig. 2. The package’s leads will betrimmed to a length of 1.0mm. After trimming, the package’s leads will be further processed as follows:
1. The lead’s gold plating will be removed per the following sections of J-STD-001D:
3.9.1 Solderability
3.2.2 Solder Purity Maintenance3.9.2 Solderability Maintenance3.9.3 Gold Removal
2. The leads will be tinned with Sn63Pb37 solder
The package provides a center heat slug located on its back side to be used for heat dissipation. ADSANTEC
recommends for this section to be soldered to the vcc plain, which is power for a positive supply.
The part’s identification label is ASNT2011-KMA. The first 8 characters of the name before the dash identify
the bare die including general circuit family, fabrication technology, specific circuit type, and part version whilethe 3 characters after the dash represent the package’s manufacturer, type, and pin out count.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

REVISION HISTORY
Revision
3.5.2
3.4.2
3.4.1

Date05-202007-2019
05-2015

3.3.109-2012

3.2
3.106-2012
02-20123.001-2012

2.002-2009

1.001-2009

Rev. 3.5.2

Changes
Updated Package Information
Updated Letterhead
Corrected Absolute Maximum Ratings section
Revised Package Information section
Updated format
Corrected input voltage range
Corrected format
Corrected package dimensions
Revised Description section
Revised Package Information section
Added Absolute Maximums Rating table
Revised Electrical Characteristics section
Revised Package Information section
Revised Electrical Characteristics section
Revised Package Information section
First release

8May 2020