Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT2123-PQP
DC-32Gbps Broadband Digital DDR 1:4 Demultiplexer
High speed broadband 1:4 Demultiplexer (DMUX)Exhibits low jitter and limited temperature variation over industrial temperature range

Differential CML I/O data and clock buffersHalf-rate clock input (DDR mode)Quarter-rate clock output

Single +3.3V or -3.3V power supplyPower consumption: 1.16W

Fabricated in SiGe for high performance, yield, and reliability

Standard QFN 36-pin package

vcc
q0nvccq0pvccc4onvcc
c4opvee

27 26 25 24 23 22 21 20 19282930
31
32
33
34
35
36

ASNT2123
1 2 34 5

6 7 818171615
1413
12
11
109vcc
nc
vcc
dp
vcc
dn
vcc
nc
vee

vee
q3p
vcc
q3n
vcc
cep
vcc
cen
vcc

vee
q1p
vcc
q1n
vcc
q2p
vcc
q2n
vcc

Rev. 1.1.2

1January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
vcc
q0p
q0n
q1p
q1nvccdp
dnq2pq2nq3pq3nvcc
cepcenDIV

c4op
c4onFig. 1. Functional Block Diagram

ASNT2123-PQP is a low power and high-speed digital 1-to-4 deserializer-demultiplexer (DMUX) thatfunctions seamlessly over data rates (fbit) ranging from DC to its maximum speed.
The main function of the part shown in Fig. 1 is to demultiplex an incoming high speed serial differential
CML data bit stream dp/dn running at a bit rate of fbit into 4 parallel data channels q0p/q0n, q1p/q1n,q2p/q2n, q3p/q3n running at a bit rate of fbit/4. Differential or single-ended half-rate clock cep/cen must
be provided by an external source for the part to function properly.
The parallel words and clock divided-by-4 c4op/c4on are transmitted through CML output interfaces.
The clock and data outputs are phase-matched to each other resulting in a very little relative skew over theoperating temperature range of the device.
The part’s I/O’s support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.

POWER SUPPLY CONFIGURATION
The part can operate with either negative supply (vcc = 0.0V = ground and vee = −3.3V), or positivesupply (vcc = +3.3V and vee = 0.0V = ground). In case of the positive supply, all I/Os need ACtermination when connected to any devices with 50Ohm termination to ground. Different PCB layouts
will be needed for each different power supply combination.

Rev. 1.1.2

2January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vcc).
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Rev. 1.1.2

Min-4010103Max-3.6
1.3
1.0+100+1009898

UnitsVWVºCºC%%January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

TERMINAL FUNCTIONSTERMINAL
Name
No.
Type
q0p
q0n
q1p
q1n
q2pq2nq3pq3nc4op
c4on
cepcendpdn
Name
vcc
veenc

Rev. 1.1.2242629313335242022CML
outputCML
outputCML
outputCML
outputCML
outputDESCRIPTION
Low-Speed I/Os
Differential quarter-rate data outputs. Require external SE50Ohm termination to vcc

Differential quarter-rate clock outputs. Require external SE
50Ohm termination to vcc
High-Speed I/Os
6
CML Differential half-rate clock input signals with internal 50Ohm
input termination to vcc
815
CML Differential full-rate data input signals with internal 50Ohm
input termination to vcc
13Supply and Termination Voltages
Description
Pin NumberPositive power supply
3, 5, 7, 9, 12, 14, 16, 18, 21, 23, 25, 27,(+3.3V or 0)30, 32, 34, 36
Negative power supply
1, 10, 19, 28(0V or -3.3V)
Not connected pins
11, 174

January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERTYP MAX UNIT
COMMENTS
General Parameters
-3.1
-3.3
-3.5
V
±6%
vee
0.0
V
External ground
vcc
Ivee
350mA
Power consumption
1160mW
Junction temperature -40
25125°C
HS Input Data (dp/dn)
Data Rate
DC2032Gb/s
Swing
0.20.8V
Differential or SE, p-p
CM Voltage Level
vcc-0.8
vcc
VMust match for both inputs
Half-Rate Input Clock (cep/cen)Frequency
DC
1016GHz
Differential swing
0.20.8V
Differential or SE, p-p
CM Voltage Level
vcc-0.8
vcc
VMust match for both inputs
Duty Cycle
405060%LS Output Data (q0p/q0n, q1p/q1n, q2p/q2n, q3p/q3n)
Data Rate
DC58Gb/s
Logic “1” levelVvcc
Logic “0” levelvcc-0.44
V
With external 50Ohm DC termination
Output Jitter2
ps
Peak-to-peak at 10Gb/s
LS Output Clock (c4op/c4on)
Frequency
DC58
GHz
Logic “1” level
Vvcc
Logic “0” levelvcc-0.4
V
With external 50Ohm DC termination
Duty Cycle
50%
Output Jitter1
ps
Peak-to-peak at 10GHz

Rev. 1.1.2

MIN

5January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATIONThe chip die is housed in standard 36-pin QFN package with a footprint shown in Fig. 2. It is
recommended that the center heat slug located on the back side of the package is soldered to the vee plainthat is ground for the positive supply or power for the negative supply.
The part’s identification label is ASNT2123-PQP The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all tensubstances.

Fig. 2. QFN 36-Pin Package Drawing (All Dimensions in mm)

Rev. 1.1.2

6January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.1.2
1.0.2
1.0.1
0.0.1

Rev. 1.1.2

Date01-2020
07-2019
11-2017
10-2017

Changes
Updated Package Information
Updated Letterhead
Initial release
Preliminary release

7January 2020