A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

A D S A N T E C

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

ASNT5112-PQC
14Gbps D-Type Flip-Flop with Increased Input Signal Sensitivity•

14GHz analog input bandwidth for both clock and data.

•8ps set-up/hold time capability.

•88% clock phase margin for retiming of data input eye.

•Fully differential input and output buffers with on-chip 50Ω termination.

•CML output interface with 400mV single-ended swing.

•Single ±3.3V power supply.

•Power consumption: 345mW.

•Fabricated in SiGe for high performance, yield, and reliability.

•Standard MLF/QFN 24-pin package.

Functional Block Diagram

OUTP

229VCCVCC

238OUTNVEE

247VCC56ASNT5112

VEEClockinp Clockinn

10DN

VCC

50VCC

450

VCC

21CN50

11350

VEE

20VCC

DATAout n

12DP2DATAinn

DATAout p19CPDFF
core

18 17 16 15 14 13
VCC

1DATAinp

50

VCC

50

Boosted Gain &CM Range

VCC

Exhibits low jitter and limited temperature variation over industrial temperature range.

VCC

•VCC

Sensitive input data buffer with increased CM range that is ideal for sampling applications.

VCC

•

VCC

High speed broadband D-Type Flip-Flop for data retiming with full rate clock.

VEE•

Package Pins

DESCRIPTION
The temperature stable ASNT5112-PQC SiGe IC provides broadband data retiming functionality
and is intended for use in high-speed measurement / test equipment. ASNT5112-PQC cansample an up to 14Gbps data signal with an up to 14GHz clock source to create a 14Gbps
retimed NRZ data output. The data input buffer is designed to have increased input signal
sensitivity and is able to operate over a wider range of input common mode (CM) voltages. The
part’s I/Os support the CML logic interface with on chip 50Ω termination and may be useddifferentially, AC/DC coupled, single-ended, or in any combination. It operates from a single±3.3V power supply.
Rev.: 4,February 2008.

ASNT5112-PQC

A d v a n c e d
S c ie n c ea n dN o v e l
T e c h n o lo g y

A D S A N T E C

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

TERMINAL FUNCTIONSTERMINAL
NAMEvcc
vee
dpdn
cp
cn
outp
outn

TYPE

(NO.)
1,3,5,7,9,11
13-17,19,21,23
6,12,18,24
20
22
2
4108

DESCRIPTION

PS

Power Supply: 0V (GND)

PS
Input

Power Supply: -3.3V
Differential CML high-speed data signal inputs

Input

Differential CML high-speed clock signal inputs

OutputDifferential CML high-speed data signal outputs

ELECTRICAL CHARACTERISTICSPARAMETER
VEE
VCC
IEE
Power
Junction Temp.
Input Data (d)Frequency
CM Level
SE Swing
Input Clock (c)Frequency
CM Level
SE Swing
Duty Cycle
Output Data (out)Frequency
CM Level
SE Swing
Rise/Fall Times
Additive Jitter
Clock Phase Margin

MIN TYP MAX-3.1
0.0 / -3.3-3.5
3.1
3.3 / 0.0
3.5
105
345-25
50
125

UNIT
VV
mA
mW°C

COMMENTS±6%±6%

0.014
Vcc-1.5 Vcc-0.3 Vcc+0.3
25300
800

GbpsV
mV

Peak-to-peak

0.0
14
Vcc-0.8 Vcc-0.3 Vcc+0.3
50 300800
40%50%60%

GHzV
mV

Peak-to-peak

0.0
14
Vcc-0.3 Vcc-0.2 Vcc-0.1
380 400
420<18<580% 85% 90%Gbps
V
mV
ps
ps

Peak-to-peak
20%-80%Peak-to-peak

PACKAGE INFORMATIONThe chip is packaged in a standard 24-pin QFN package. The package’s mechanical information
is available on the company’s website.

Rev.: 4,February 2008.

ASNT5112-PQC