Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT2116-KMF
25.0-to-31.5GHz Programmable CDR 1-to-1
1-to-1 CDR (clock and data recovery unit)

CDR range from 25.0GHz to 31.5GHz covered by 3 selectable VCOs



Digital operational mode with DC to 32GHz external clock

RZ and NRZ input data formats

Adjustable time of the data sampling point for optimal BER performance

Selectable full-rate, half-rate, or disabled clock output

Optional signal inversion in all output buffers



Fully differential CML input and output interfaces for high-speed clock and data

LVDS-compliant input reference clock interfaceSingle +3.3V power supplyPower consumption: 2.25W at the maximum operational speedCustom CQFP 64-pin package
vee
vcc
vgc
vcc
dtemp
vcc
off_c2
poloff_i
onco
vcc
cqp
vcc
cqn
vcc
vee



ASNT2116

vee
vcc
nc
vcc
qp
vcc
nc
lolp
icph
icpl
vcc
qn
vcc
nc
vcc
vee

vee
vcc
cep
vcc
cenvccvcos1
fltr
isvcos 0
vcc
c32p
vcc
c32n
vcc
vee

vee
vee
pkdtp
pkdtn
dcinp
vcc
vcc
dp
vcc
dnvcc
vcc
dcinn
phshftvee
veeRev. 1.4.2

1January 2020

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DESCRIPTION
pol
cep/cen

HSCIB

vgc
dp/dn
dcinp
dcinn
pkdtp/pkdtn

HSDIB

c32p/c32n

LSCIB

dtemp

DHS
DOB

qp/qn
icph

CDR

icpl

lolp
fltr
phshftvcos0
vcos1
off_ioff_c2
oncoHSCOB

cqp/cqn

Fig. 1. Functional Block Diagram

ASNT2116-KMF is a 1:1 full-rate clock and data recovery unit (CDR). The main function of the IC
shown in Fig. 1 is to recover a full-rate clock signal C and a retimed data signal D from an RZ or NRZ
input data signal dp/dn with a bit rate of fbit accepted by a CML input data buffer HS DIB. The IC canfunction either in CDR mode covering a wide range of input data rates by utilizing its three on-chip VCOs
(voltage-controlled oscillators), or in broadband digital mode. Selection of the desired operational modeand the CDR input data rate is accomplished through pins vcos0 and vcos1 (see Table 1). An external
low speed reference clock c32p/c32n running at 1/32 of the frequency of the active VCO must be applied
to a low-speed LVDS clock input buffer LS CIB in CDR mode. An external full-rate clock cep/cen must
be applied to a high speed CML clock input buffer HS CIB in digital mode.
The CDR includes two control loops for latching the correct frequency and phase states and requires asingle external loop filter connected to pin fltr. The loops’ gain can be tuned independently using control
signals icph and icpl. The phase of the clock recovered by the CDR can be adjusted using an external
control voltage phshft. This helps achieve the lowest system bit error rate (BER) by selecting the optimal
input data sampling time. An internal control circuit generates an alarm signal lolp that indicates thefrequency locking state of the CDR.
The data input buffer HS DIB can operate with either differential or single-ended input signals dp/dn. It
includes tuning pins dcinp/dcinn for DC offset of the input signals in case of AC termination. When thebuffer is operating with a DC-terminated single-ended input signal, a correct threshold voltage should beapplied to the unused input pin. A peak detector is also included to provide means of demodulating AM
components carried by the input data with a frequency up to a few hundred kHz. The peak detector’s
output signal is delivered to differential port pkdtp/pkdtn.
Rev. 1.4.2

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Depending on the state of control signal off_c2, either a full-rate or a half-rate recovered clock isdelivered to outputs cqp/cqn by CML output buffer HS COB. The clock polarity can be inverted using
another control signal off_i. The buffer HS COB can be enabled or disabled using control signal onco.
The retimed data is delivered to outputs qp/qn by CML output buffer HS DOB. It has a tight phasealignment to output clock cqp/cqn.
All CML I/Os provide on chip 50Ohm termination to vcc and may be used differentially, AC/DC
coupled, single-ended, or in any combination (see HS DIB). The LVDS input buffer should be used inaccordance with the standard (see LS CIB).
The internal temperature can be monitored by a diode’s current running into pin dtemp.

HS DIBThe High-Speed Data Input Buffer (HS DIB) can process input data signals dp/dn in either RZ or NRZ
format due to its high analog bandwidth. It supports the CML logic interface with on chip 50Ohmtermination to vcc and may be used differentially, AC/DC coupled, single-ended, or in any combination(see also POWER SUPPLY CONFIGURATION). In the DC-coupling mode, the input signal’s commonmode voltage should comply with the specifications shown in ELECTRICAL CHARACTERISTICS. In
the AC-coupling mode, the input termination provides the required common mode voltage automatically.
The differential DC signaling mode is recommended for optimal performance. In case of AC termination,
the tuning pins dcinn or dcinp allow for internal data common mode adjustment. This adjustment may be
used for changing the slicing level before the data is sampled by the recovered clock. The tuning ports
have internal 1kOhm single-ended terminations to vcc.
The small-signal gain of the buffer can be adjusted from 32dB to 38dB using control voltage vgc. Thecontrol port has an internal 2kOhm termination to vcc. The allowed range is from vee to vcc.
Also included in the buffer is an input signal peak detector that delivers its response through the output
differential port pkdtp/pkdetn. The detector can demodulate AM component(s) carried by the input datain the frequency range of up to a few hundred kHz. The detector’s output ports have internal 2.8kOhm
single-ended terminations to vcc.

HS CIBThe High-Speed Clock Input Buffer (HS CIB) can process external clock signals cep/cen in the digital
operational mode. It supports the CML logic interface with on chip 50Ohm termination to vcc and may be
used in the same modes as the HS DIB.

Rev. 1.4.2

3

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LS CIB
The Low-Speed Clock Input Buffer (LS CIB) can process an external reference clock signal c32p/c32nwith a frequency equal to 1/32 of the selected VCO frequency. The clock input supports the LVDS logic
interface with on chip 100Ohm terminations between the direct and inverted lines. The proprietary LVDS
buffer exceeds the requirements of standards IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. It isdesigned to accept differential signals with amplitudes above 70mV peak-to-peak (p-p), DC common
mode voltage variation between the negative vee and positive vee+2.4V supply rails, and AC common
mode noise with a frequency up to 5MHz within the same voltage range. It can also receive single-ended
signals with amplitudes above 60mVp-p and threshold voltages between vee and vee+2.4V.

CDR
The Clock and Data Recovery block (CDR) contains two loops for adjusting both the phase and thefrequency of the internal clock generated by the selected VCO. The frequency loop works in conjunction
with the low-speed clock c32p/c32n, while the phase loop utilizes the input data signal dp/dn. The CDR
requires an off-chip loop filter with the proposed schematic shown in Fig. 2. The filter should beconnected to pin ftr.

200Ohm
ftr
100pF

1nF

Fig. 2. Proposed External Loop Filter

The main function of the CDR is to frequency-lock the selected on-chip VCO to the input data signal(clock recovery) while aligning the phases in such a way that the incoming data is latched-in with theminimal error (data recovery). By default, the CDR positions the recovered clock’s working edge in themiddle of the incoming data bits. Using external control voltage phshft with the range from vee to vcc,
this edge can be shifted back or forth in order to locate the optimum data sampling point that provides thelowest system BER. The recovered clock is also divided down in frequency by two (C2) and either thefull-rate or the half-rate clock is delivered to HS COB depending on the state of the 2.5V CMOS control
signal off_c2 (off_c2 = “1” (default): full-rate; off_c2 = “0”: half-rate).
By utilizing the 2.5V CMOS control pins vcos0 and vcos1, the desired working mode and the frequencyof the CDR can be selected in accordance with Table 1 below.
The phase and frequency loops’ gains can be adjusted by two 2.5V CMOS control pins icph and icpl that
control the currents in the corresponding sections of the charge pump as shown in Table 2.

Rev. 1.4.2

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Table 1. CDR Mode Selection

vcos0 vcos1
Selected VCO“0”“0”
VCO1 (lower frequency)“0””1”
VCO2 (medium frequency)”1”“0”
VCO3 (higher frequency)”1””1”Digital mode, all VCOs disabled (default state)
The lock detect circuitry generates an active-high 2.5V CMOS signal lolp that indicates that the frequency
difference between the recovered full-rate clock divided by 32 and the applied system reference clock
c32p/c32n exceeds ±1000ppm.
Table 2. Charge Pump Current Controlicph icpl
“0”
“0”
”1”
”1”

“0””1”“0””1”

Charge Pump current, mA
Phase loop section Frequency loop section
550
69
550
35275
69275
35

The CDR allows for polarity inversion of the sampled data signal by means of a 2.5V CMOS control
signal pol (pol = “1” (default): inverted; pol = “0”: direct), and of the recovered high-speed clock signal
by means of a 2.5V CMOS control signal off_i (off_i = “1” (default): direct; off_i = “0”: inverted).

HS DOBThe High-Speed Data Output Buffer (HS DOB) receives full-rate retimed serial data stream D from theCDR and converts it into CML output signal qp/qn. This buffer provides internal single-ended 50Ohm
terminations to vcc for each output line and also requires 50Ohm external termination resistors to beconnected between vcc and each output.

HS COBThe High-Speed Clock Output Buffer (HS COB) receives a full-rate or a half-rate clock signal from theCDR and converts it into CML output signal cqp/cqn. The buffer provides internal single-ended 50Ohm
terminations to vcc for each output line and also requires 50Ohm external termination resistors to beconnected between vcc and each output. The buffer can be enabled or disabled by external 2.5V CMOS
control signal onco (onco = “1” (default): enabled; onco = “0”: disabled). The negative edges of thecqp/cqn signal are aligned to transitions of the output data signal.

Rev. 1.4.2

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POWER SUPPLY CONFIGURATION
The part operates with a single positive supply (vcc = +3.3V and vee = 0.0V = ground). All CML I/Os
need AC termination when connected to any devices with 50Ohm termination to ground.

All the characteristics detailed below assume vcc = 3.3V and vee = 0V (externalground)

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 3 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vee).
Table 3. Absolute Maximum Ratings

Parameter
Supply Voltage (vcc)
Power Consumption
Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Rev. 1.4.2

Min-4010106Max
3.6
2.5
1.0+90+10098
98UnitsVW
VºCºC%%

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TERMINAL FUNCTIONSNameTERMINAL
No.
Typecepcenqp
qncqp
cqn
dp
dnc32p
c32n
pkdtp
pkdtn
vcos1
vcos0
isicpl
icph
onco
off_i
pol
off_c2
lolp
fltr
vgc
dcinp
dcinn
phshft
dtemp
Name
vcc
veenc
Rev. 1.4.2

3
528
21
37
35
5658

DESCRIPTION

High-Speed I/Os
CML Input Differential full-rate clock inputs with internal SE 50Ohm termination
to vccCML Output Differential full-rate data outputs with internal SE 50Ohm termination
to vcc. Require external SE 50Ohm termination to vcc
CML Output Differential high-speed clock outputs with internal SE 50Ohmtermination to vcc. Require external SE 50Ohm termination to vcc
CML Input Differential data inputs with internal SE 50Ohm termination to vcc

Low-Speed I/Os
12 LVDS Input Differential low-speed clock input with internal differential 100Ohmtermination
1451Output
Peak detector outputs with internal SE 2.8KOhm termination to vcc
52Digital Controls
7 2.5V CMOS CDR operational mode and VCO frequency selection, see Table 1
Input
109
VCO current control (high, default: higher current; low: lower current)
For test purposes only! Keep not connected for normal operation!
23
Charge pump current control, see Table 2
24
39
COB control (high, default: buffer is enabled; low: buffer is disabled)40
Output clock polarity (high, default: direct; low: inverted)
41
Output data polarity (high, default: inverted; low: direct)
42
Output clock select (high, default: buffer is on; low: buffer is disabled)
25 2.5V CMOS CDR lock indicator output (high: no lock; low: locked)
Control Voltages
8InputExternal loop filter connection
46
Input
Input gain control voltage. Allowed values from vee to vcc
53
DC Input Input data common mode voltage adjustment. Allowed values fromvee to vcc
61
62
DC Input CDR sampling point adjustment. Allowed values from vee to vcc
44
OutputOn-chip temperature control diode’s anode
Supply and Termination Voltages
Description
Pin Number
Positive power supply (+3.3V)
2, 4, 6, 11, 13, 15, 18, 20, 22, 27, 29, 31, 34, 36,38, 43, 45, 47, 54, 55, 57, 59, 60
Negative power supply (0V)
1, 16, 17, 32, 33, 48, 49, 50, 63, 64
Not connected pins
19, 26, 30
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ELECTRICAL CHARACTERISTICSPARAMETER
veevcc
Ivcc
Power consumption
Junction temperature
Package t° resistance
Data Rate
Swing
External CM voltage
Internal CM voltage
HS DIB gain

MIN

TYP MAXUNITGeneral Parameters
0.0V
3.13.3
3.5V680mA
2.25
W-2550125°C
15°C/W
HS Input Data (dp/dn)
25.0
31.5
Gbps
DC32Gbps
0.05
0.6
V
vcc-0.8vccV
vcc-0.15
vcc
VExternal ground±6%

RZ or NRZ, CDR mode
RZ or NRZ, digital mode
Differential or SE, p-p
Must match for both inputs
Set by dcinp/dcinn on thecorresponding inputs
Controlled by vgc

38
dBHS Input Clock (cep/cen)Frequency
DC32
GHzSwing
0.05
0.6
V
Differential or SE, p-p
CM voltage levelvcc-0.8
vcc
VMust match for both inputs
Duty Cycle
455055%LS Input Reference Clock (c32p/c32n)Frequency
781.25984.38MHz
1/32 of the VCO frequency
Swing140900mV
Differential, p-p
CM voltage levelvee
vee+2.4
V
Duty cycle
405060%HS Output Data (qp/qn)
Data rate
DC32Gbps
NRZ
Logic “1” level
Vvcc
Logic “0” levelvcc -0.4
V
Jitter8
ps
p-p at 25.6Gbps
HS Output Clock (cqp/cqn)
Frequency
DC32
GHz
Logic “1” level
Vvcc
Logic “0” levelvcc -0.4
VJitter5
psp-p at 12.8GHzInput Data Common Mode Control (dcinp/dcinn)
Internal termination
1kOhm
SE to vcc
DC voltage range
Vvee creates max downshift
veevccPeak Detector Output (pkdtp/pkdtn)
Internal termination
2.8kOhm
SE to vcc
Swing p-p (Diff)-1
1
VOver full input range
CM Voltage Level
vcc -1.0
V
Rev. 1.4.2

32

COMMENTS

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PARAMETERMIN
TYP MAXUNIT
COMMENTS
Data Sampling Point Adjustment (phshft)
Internal termination
1.8
kOhm
SE to vcc
Input DC Voltage
vcc -1.0vcc
VPhase Shift-150+15
ps0 at phshft=n/c
Shift Stability-22ps
From 0°C to 125°C
Bandwidth
0.0
100
MHz
Input Gain Control (vgc)Internal termination
2.0
kOhm
SE to vcc
Input DC Voltage
Vvee delivers min gainvee
vcc
CMOS Control I/Os (icph, icpl, vcos0, vcos1, off_i, off_c2, pol, onco, is, lolp)
Logic “1” level
2.1
2.5VLogic “0” levelvee +0.4
VTiming Parameterscqp/cqn to qp/qn delay
2psOver the full temperature
variation
range
VCOs
Low frequency of VCO1
25.0
GHz
Lower-frequency VCO
High frequency of VCO1
27.4
GHz
Low frequency of VCO2
26.3
GHz
Medium-frequency VCO
High frequency of VCO2
29.2
GHz
Low frequency of VCO3
28.0
GHz
Higher-frequency VCO
High frequency of VCO3
31.5
GHz
External control voltage
vcc-2.5vcc
V
In the open-loop mode
range (applied to fltr)
Temperature Monitoring Diode (dtemp)
Input current
2.33mAAt -25°C
2.48mAAt 125°C

PACKAGE INFORMATIONThe chip die is housed in a custom 64-pin CQFP package shown in Fig. 3. The package provides a center
heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for thissection to be soldered to the vcc plain, which is power for a positive supply.
The part’s identification label is ASNT2116-KMF. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

Rev. 1.4.2

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Fig. 3. CQFP 64-Pin Package Drawing (All Dimensions in mm)

Rev. 1.4.2

10January 2020

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REVISION HISTORY
Revision
1.4.2
1.3.2
1.3.1
1.2.1

Date
01-2020
07-2019
05-2015
03-2014

1.1.1
1.0.1

07-201305-2013

Rev. 1.4.2

Changes
Updated Package Information
Updated Letterhead
Revised package information section
Corrected CDR Frequency operating range
Corrected Electrical Characteristics
Corrected CDR Frequency operating range
Initial release

11January 2020