Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

ASNT6104-PQB
32Gbps-16Gbaud PAM4 Decoder

vee

vcc

msbn

vcc

msbp

vcc

vee

vcc

vcc

3wdo

co2n

vcc

vcc

3wdin

co2p

nc

ASNT6104

vcc

3wcin

vcc
1

vcc

vcc_vco

ci

vcc

vcc

vcc

n/useddnn/used3wenin

vcc

vcc

v1p2

vcc

vcc

dp

vee
Rev.1.0.2

lsbn

vcc

lsbp

One high-speed input PAM4 signal to two binary output signals
Half-rate clock output synchronized with two output data signals
Adjustable threshold levels for input signal
Fully differential CML input and output data
Differential CML input clock interface
1.2V CMOS 3-wire interface for digital controls
Single -3.3V or +3.3V power supply
Power consumption: 2.4W
Standard QFN 40-pin packagevcc

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January 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

DESCRIPTION
dp/dn

DIB

ci

vth3crl

vth1crl

CIB

CMPDelay

PAM4DecoderCore

msbp/msbn

OB

lsbp/lsbn

OBco2p/co2ncdelcrl

VthGEN

OB

DACs
3wdin
3wcin
3wenin
3wdo

SPIFig. 1. Functional Block Diagram

The ASNT6104-PQB SiGe IC shown in Fig. 1 is a PAM4 decoder. The differential PAM4 input datasignal dp/dn is processed by the linear input buffer (DIB) and is sent to the Comparator block (CMP).
Three limiting buffers inside CMP process the 3-level PAM4 signal. One of the buffers processes theinput signal differentially. The other two buffers compare single-ended data to their own threshold levels
that are produced by the Voltage Threshold Generator block (Vth GEN). The three resulting differential
binary data streams are sent to the PAM4 Decoder Core where they are retimed by D-type flip flops(DFFs) with a full-rate external clock, and delayed by the adjustable delay line block (Delay). The threedifferential signals are decoded into two differential data streams. The two signals are retimed again, andare sent to the output through Output Buffers (OB).
To reduce the physical number of control inputs to the chip, a shift register with a 3-wire input interface(SPI) has been included on chip. The SPI block provides all the digital controls for the chip. It also
provides digital controls for digital-to-analog converters (DACs) that handle internal analog DC voltage
adjustments.

DIB
The Data Input Buffer (DIB) can process an input analog CML data signal dp/dn in PAM4 format. It
provides on-chip single-ended termination of 50Ohms to vcc for each input line. The buffer can also
Rev.1.0.2
2January 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

accept a single-ended signal to one of its input ports dp, or dn with a threshold voltage applied to theunused pin in case of DC termination.

CMP
CMP accepts a differential analog 4-level PAM4 signal from DIB. The purpose of CMP is to transformthe signal to three binary digital data signals by utilizing two threshold levels that are generated by theVoltage Threshold Generator block. The first signal is generated after the positive single-ended version of
the analog input PAM4 signal, and the DC voltage threshold signal vth1 go through a limiting buffer. The
level of vth1 should be between the top level of the single-ended PAM4 signal after the input buffer, andthe next lower level. The second digital output signal of CMP is formed by letting the differential input
through a limiting buffer. The third signal is generated after the positive single-ended version of theanalog input PAM4 signal, and the DC voltage threshold signal vth3 go through a limiting buffer. Thelevel of vth3 should be between the bottom level of the single-ended PAM4 signal after the input buffer
and the next higher level.

Vth GEN
The purpose of the Voltage Threshold Generator block (Vth GEN) is to form two threshold voltage levels
for CMP. The levels are independently adjusted through two digital bytes of the SPI. The byte vth1crl
controls the top level. The byte vth3crl controls the bottom level. Fig. 2 presents the dependence of thetwo levels on their own digital codes of the SPI.

Fig. 2. Voltage Threshold Adjustment (vee=0V)

Rev.1.0.2

3January 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

PAM4 Decoder Core
The three digital binary differential signals from CMP are retimed in the Core by the full-rate clock. Thenthe signals go through decoder logic to form two differential digital binary data signals. The signals areretimed by the shifted full-rate clock, and sent to the output buffers. The full-rate clock goes through theclock dvider-by-2, and is sent to an identical output buffer. The edges of the data, and clock signals arealigned.

External clock Input Buffer (CIB)
An external full-rate clock signal is required for the part operation. The clock buffer CIB has CML
interface with internal 50Ohm terminations to vcc for both direct and inverted inputs. It accepts either
differential or single-ended signal. DC common mode voltage for the input signal should match the values
specified in ELECTRICAL CHARACTERISTICS. Otherwise, DC blocks are required.
Proper alignment of the external clock with the incoming data is critical for the correct data decoding.
This can be achieved by means of the internal delay block described below.

Delay
The purpose of the delay block is to deliver the delayed version of the full-rate external clock to thedecoder core. By utilizing the digital control byte delcrl, the phase of the clock can be shifted with respect
to data to achieve optimal latching by the DFFs.

3-Wire Interface Control BlockTo reduce the physical number of control inputs to the chip, a 5-byte shift register with a 3-wire input
interface has been included on chip. The SPI block is powered by an internally generated supply voltageof +1.2V from vee. The supply voltage of the SPI can be monitored through pin v1p2. The digital control
bits applied through 3wdin input are latched in, and shifted down the register with the clock 3wcin. Write
enable signal 3wenin must be set to logic “0” during the data read-in phase. The SPI data can bemonitored through the output 3wdo. Table 1 presents the byte order of the 3-wire interface block.
Table 1. Control Bytes

Byte
Bit Number
Number 7 6 5 4 3 2 1 0
vth3crl(7:0)
1vth1crl(7:0)
2delcrl(7:0)
3400000000
5X X X X 0 0 0 0

SPI load order is illustrated in Fig. 3.
Rev.1.0.2

4January 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
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3wcin
3weninSampleLatch
3wdin

X 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0 X

Byte 1

Byte N

Fig. 3. SPI Load OrderPOWER SUPPLY CONFIGURATIONThe ASNT6104-PQB can operate with either a negative supply (vcc = 0.0V = ground and vee = -3.3V),or a positive supply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os needAC termination when connected to any devices with 50Ohms termination to ground. Different PCB
layouts will be needed for each different power supply combination.

All the characteristics detailed below assume vcc = 3.3V and vee = 0V (externalground)

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 2 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vee).
Table 2. Absolute Maximum Ratings

Parameter
Supply Voltage (vcc)
Power Consumption
Input Voltage Swing (SE)
Case Temperature*)
Storage TemperatureOperational Humidity
Storage Humidity

Rev.1.0.2

Min-4010105Max+3.8
2.1
1.0+90+100
98
98

UnitsVWVºCºC%%

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Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
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TERMINAL FUNCTIONSTERMINAL
NameNo.
Typedp
dnci
msbp
msbn
lsbp
lsbn
co2p
co2n

37
39
925
23
29
27
35
33

3wenin
3wcin
3wdin
3wdo

13151719v1p2

3DESCRIPTION

High-Speed I/Os
CML differential data inputs with internal SE 50Ohm termination tovcc
Input
SE full-rate clock input with internal 50Ohm termination to vcc_vco
Output
CML differential data outputs. Require external SE 50Ohm termination
to vccOutput
CML differential data outputs. Require external SE 50Ohm termination
to vccOutput
CML differential half-rate clock outputs. Require external SE 50Ohmtermination to vcc
Low-Speed I/Os
1.2V CMOS Enable input signal for 3-wire interface
input
Clock input signal for 3-wire interface
Data input signal for 3-wire interface
1.2V CMOS Data output signal of 3-wire interface
outputControls
I/OInternally generated SPI supply voltage
Input

Supply and Termination Voltages
Description
Pin Number
2, 4, 6, 8, 10, 12, 14, 18, 20, 22, 24, 26, 28, 30,vcc
Positive power supply (+3.3V)
32, 34, 36, 38, 40
vcc_vco Positive power supply for VCO (+3.3V)
11vee
Negative power supply (GND or 0V)
1, 21, 31
n/used Not used in this chip configuration
5, 7ncNot connected
16NameRev.1.0.2

6January 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERMIN

TYP MAX
UNIT
General Parameters
vcc and vcc_vco+3.0+3.3
+3.6
V
0.0
Vvee
Ivcc
670
mA
Ivcc_vco
45mA
Power Consumption
2.4
W
Junction Temperature
-25
50
125°C
HS Input Data (dp/dn)
Data Rate
1617
Gbaud
Swing p-p (Diff or SE)
0.05
0.6
V
CM Voltage Level
vcc-0.8vcc
V
HS Input Clock (ci)Frequency
1617
GHz
Swing p-p (Diff or SE)
0.05
0.8
CM Voltage Level
vcc-0.8
vcc
HS Output Data (msbp/msbn, lsbp/lsbn)
Data Rate
1617Gbps
Logic “1” level
Vvcc
Logic “0” levelvcc -0.66
vcc -0.6
VJitter35
ps
HS Output Half-Rate Clock (co2p/co2n)
Clock Rate
88.5
GHz
Logic “1” level
Vvcc
Logic “0” levelvcc -0.66
vcc -0.6
VJitter24
ps
3-Wire Inputs (3wdin, 3wcin, 3wenin)
High voltage levelvee+1.2
vee+1.4
VLow voltage levelveevee+0.35
VClock speed350400MHzCOMMENTS±9%

PAM4p-pp-p

PACKAGE INFORMATIONThe chip is packaged in a standard 40-pin QFN package shown in Fig. 4. It is recommended that thecenter heat slug located on the back side of the package is soldered to ground to help dissipate heatgenerated by the chip during operation.
The part’s identification label is ASNT6104-PQB. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all tensubstances.
Rev.1.0.2
7January 2021

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Dr., Ste #112, Torrance, CA 90505
Office: (310) 530-9400 Fax: (310) 530-9402
www.adsantec.com

ASNT6104
Fig. 4. QFN 40-Pin Package Drawing (All Dimensions in mm)

REVISION HISTORY
Revision
1.0.2

Date
01-2021

0.2.2
0.1.2
0.0.2

12-2020
09-2020
09-2020

Rev.1.0.2

Changes
Corrected pin out diagram
Corrected operational speed
Corrected functional block diagram
Removed CR description
Corrected description of ci termination
Pin out diagram corrected
Preliminary release

8January 2021