Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
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ASNT2031-MBL
Digital DMUX 24-to-48 with SSTL Interface
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
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

Digital demultiplexer (DMUX) 24-to-48 with SSTL1.5 input and output interfaces.
Supports data rates from 1.0Mbps to 2.0Gbps.
User-controllable independent internal delays for data and clock signals.
1.5V I2C control interface with a user-defined 3-bit chip address.
Preset function for synchronization of multiple parallel devices.
Full-rate output copy of external high-speed clock input signal.
Two pairs of clock divided-by-2 and synchronous clock enable outputs for supporting the treetype demultiplexation structure.
Additional synchronous clock divided-by-4 output.
Dual power supply of +3.0V and +1.5V.
Industrial temperature range.
Low power consumption of 2.1W at 2.0Gbps.
Available in custom 256-pin BGA package (13mm x 13mm x 2.5mm).

Fig. 1. BGA Ball Placement, view from the Top of Package.

Rev. 1.6.2

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DESCRIPTION

Fig. 2. Functional Block Diagram.

ASNT2031-MBL is a broad-band multi-channel digital deserializer-demultiplexer (DMUX) 24-to-48 withexternal initial preset functionality and 1.5V single-ended SSTL1.5 input and output interfaces for dataand preset signals, as well as matching differential interfaces for clock signals.
The part includes active variable delay lines (DelLine) in each input data and clock path for accurate
signal alignment at the DMUX register inputs in order to define the optimal sampling point for the input
data signals (data in). The value of each delay is externally controlled through an I2C interface with auser-selectable 3-bit chip address.
The operational speed of DMUX is defined by an external clock signal (clk in) that is converted into therequired timing signals by an internal divider and is also supplied to the output of the chip (clk out). The
divider can be preset to a certain initial state by the external clock enable signal (clken in), which allows
synchronization of multiple DMUX devices operating in parallel.
The optimal alignment of input data (data in) and clock is illustrated in Fig. 3. The actual values of setup(tSU) and hold (tH) times are presented in Table 6.
This part also supports cascaded tree-type structures as shown in Fig. 4, by supplying two synchronouscopies of clock divided-by-2 (c/2 F, c/2 R) and clock enable (clken F, clken R) signals.
Clock divided-by-4 (c/4 out) output signal is also provided for higher flexibility.
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Clock Edge

τcdi1

Input
Data

Clock Edge

τcdi2

Valid Clock
Fig. 3. Input Timing Diagram.

clken indata inclken out F

ASNT2031 c/2 out F
SSTL
data outclken
out R
Register
c/2 out R

clken out F

clk inASNT2031 c/2 out F
data out
SSTL
out R
Register clken
c/2 out R

ASNT2031
SSTL
Register
ASNT2031
SSTLRegister
ASNT2031
SSTL
Register
ASNT2031
SSTLRegisterFig. 4. Cascaded Tree-Type Structure.

All clock and clock enable outputs are phase-aligned as shown in Fig. 5. The defined phase relations arestabilized over PVT variations.

Fig. 5. Clock Signals.

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The output data alignment to the output clock divided-by-2 is illustrated in Fig. 6. It is also stabilized overPVT variations. The actual values of setup (tSU) and hold (tH) times are presented in Table 6.
c/2 output

τc2ddataoutput

τc2c4
c/4 output

Fig. 6. Output Data Alignment.

The DMUX IC uses two power supplies: vdd= +1.5V for CMOS I/Os and vcc= +3.0V for the internalcircuitry. It consumes about 2.1W of power and is characterized for operation from −25°C to 125°C ofjunction temperature.

SSTL Input Buffers
The SSTL input buffer is designed as a differential current switch with high tolerance to input commonmode voltage level variation. In a differential mode used for clock inputs, it accepts two complementarysignals and provides a selectable internal termination for both of them depending on the state of aninternal switch. The switch is controlled by external 3.0V CMOS signal term_on as shown in Table 1. A
special external voltage vtt=vdd/2 should be provided for the correct operation of the termination circuit.
Table 1. Input Termination States.

term_on signal state Switch state Termination typeHigh
Closed50Ohm to vttLowOpen
High impedance
The buffer can also operate in a single-ended mode used for data and clock enable inputs. In this mode, itaccepts one input signal and external reference voltage vref=vdd/2. Deviations of the reference voltage
may result in the duty cycle distortion of input signals.

Delay Lines
Digitally-controlled on-chip active delay lines are used for the alignment of input clock and data signals inorder to achieve the optimal sampling conditions at the inputs of the demultiplexer’s internal register.
Each delay line has 15 states with an absolute delay from 400ps to 1400ps. The accuracy of the minimum
delay value is within ±20% for the full PVT range. This relatively high variation is insignificant for thechip operation due to the matching delays in all input paths. The additional controllable delay of 1ns ishighly stabilized and falls within ±5% accuracy range.
The states of the delay lines are controlled within the 1-2-4-8 algorithm by signals provided from theinternal I2C interface.

DeMUX 24:48
The block consists of 24 independent demultiplexers 1-to-2 with the standard M-S/M-S-S architecture. It
latches in the data signals on both edges of half-rate clock c/2 that is supplied by the internal divider-by-4
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and delivers the deserialized outputs aligned to the corresponding clock edges. The output data signals aremarked A and B and are aligned to the rising edge of c/2.

Divider-by-4
The Divider-by-4 converts the input clock signal (clk in) into clock divided-by-2 (c/2) and clock dividedby-4 (c/4) signals aligned to a positive edge of the input clock. The divider can be preset to the 0 initialstate by the external clken_in signal that is preliminarily retimed by the input clock.

SSTL Output Buffers
The SSTL output buffers are designed in full compliance with the SSTL1.5 standard and operate from anominal 1.5V supply. Their CMOS driver can source or sink the required current through a 25Ohm series
resistor. The output of the buffer may be 50Ohm terminated to an external voltage equal to a half of thebuffer’s supply voltage, or left non-terminated.

Clock Enable and Divider Reset
The clock enable signal must be at least 2 high-speed input clock periods long. The clock enable signal
must be aligned with the falling edge of the high-speed input clock.

I2C Interface
This 2-wire 3.0V serial-to-parallel interface with initial preset (with the all “0” address word for reset) isused for setting the values of internal delays in the data and clock paths. The chip incorporates a Slave I2C
device that supports write operations as described below.
The I2C system uses a serial data line (SDA) and a serial clock line (SCL) for data transfers. Data istransferred between Master and Slave synchronously on a byte-by-byte basis. There is one SCL clock
pulse for each data bit with the MSB being transmitted first. An acknowledgement bit set by Slavefollows each transferred byte. Each bit is sampled during the high period of SCL.
The first byte of data transferred by Master immediately after START signal is the requested slaveaddress. It consists of Vendor/Device code (currently 0xD) followed by Chip Address Addr[2:0] and an
RW bit. The address of DMUX chip is defined by hard-wiring of 3 corresponding pins to either vee orvcc. The RW bit defines the type of operation: writing information from Master to Slave, or reading
information by Master from Slave.
When RW=0 (write operation) and the requested address matches the preset slave address, the chip’s I2C
block responds by pulling the following bit (9-th acknowledgement bit) low. It then saves 4 LSBs of thenext byte in the Input Address Register and returns another acknowledgement bit at the end of the secondbyte. After that, the block saves the next byte in the Input Data Register and returns acknowledgement bit
one more time. During the same time, the interface transfers the previously stored byte of data from theInput Data Register to the internal register in accordance with the 4-bit address previously saved in theInput Address Register. The address assignment is detailed in Table 2.

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Table 2. Internal Address Assignments.

Address
1’b0000
1’b0001
1’b0010
1’b0011
1’b0100
1’b0101
1’b0110
1’b0111
1’b1000
1’b1001
1’b1010
1’b1011
1’b1100
1’b1101
1’b1110
1’b1111

DestinationNot Used
Delay for Data Channel 13 and 1
Delay for Data Channel 14 and 2
Delay for Data Channel 15 and 3
Delay for Data Channel 16 and 4
Delay for Data Channel 17 and 5
Delay for Data Channel 18 and 6
Delay for Data Channel 19 and 7
Delay for Data Channel 20 and 8
Delay for Data Channel 21 and 9
Delay for Data Channel 22 and 10
Delay for Data Channel 23 and 11
Delay for Data Channel 24 and 12
Delay for Clock Enable and Clock
Not Used
Delay for Data Channels 13-to-24 and 1-to-12

Data
Data[7:4] and Data[3:0]Data[7:4] and Data[3:0]Data[7:4] and Data[3:0]Data[7:4] and Data[3:0]Data[7:4] and Data[3:0]Data[7:4] and Data[3:0]Data[7:4] and Data[3:0]Data[7:4] and Data[3:0]Data[7:4] and Data[3:0]Data[7:4] and Data[3:0]Data[7:4] and Data[3:0]Data[7:4] and Data[3:0]Data[7:4] and Data[3:0]Data[7:4] and Data[3:0]

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 3 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground.
Table 3. Absolute Maximum Ratings.

ParameterFirst Supply Voltage (vcc)
Second Supply Voltage (vdd)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Rev. 1.6.2

Min-4010106Max+3.6+1.8
2.3
1.8+90+1009898

UnitsVVWVºCºC%%May 2020

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TERMINAL FUNCTIONS
The ball assignment for the BGA package is shown in Table 4 and Table 5.
Table 4. Package Signal Balls.

Rev. 1.6.2

Name

Codedata in 00
data in 01
data in 02
data in 03
data in 04
data in 05
data in 06
data in 07
data in 08
data in 09
data in 10
data in 11
data in 12
data in 13
data in 14
data in 15
data in 16
data in 17
data in 18
data in 19
data in 20data in 21
data in 22
data in 23
clk in p
clk in nclken inA8A7A6A5A4A3A2A1
B1C1D1E1M1
N1P1
R1
T1
T2T3
T4T5
T6T7
T8G1
H1
F1

clk out p
clk out n
c/2 out A p
c/2 out A n
c/2 out B p
c/2 out B n
c/4 out p
c/4 out nclken out Aclken out B

J1
K1
T9R9A9B9H16
H15J16J15Type
Description
High-Speed Inputs
1.5V CMOS input Single-ended data inputs

Differential clock inputs
Single-ended clock enable input
High-Speed Outputs
SSTL 1.5V output Differential clock outputs
Differential clock outputs
Differential clock outputs
Differential clock outputs
Single-ended clock enable output
Single-ended clock enable output
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Name
CodeTypeDescription
data out A 00 B10 SSTL 1.5V output Single-ended data outputs
data out B 00 A10
data out A 01 B11data out B 01 A11
data out A 02 B12data out B 02 A12
data out A 03 B13
data out B 03 B14
data out A 04 A13
data out B 04 A15
data out A 05 A14
data out B 05 A16
data out A 06 B15
data out B 06 B16
data out A 07 C15
data out B 07 C16
data out A 08 D15
data out B 08 D16
data out A 09 E15
data out B 09 E16
data out A 10 F15
data out B 10 F16
data out A 11 G15data out B 11 G16
data out A 12 K15
data out B 12 K16
data out A 13 L15
data out B 13 L16
data out A 14 M15
data out B 14 M16
data out A 15 N15
data out B 15 N16
data out A 16 R16
data out B 16 P16
data out A 17 T16
data out B 17 P15
data out A 18 T14
data out B 18 R15
data out A 19 T13
data out B 19 T15
data out A 20 R13
data out B 20 R14

Rev. 1.6.2

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Namedata out A 21
data out B 21
data out A 22
data out B 22
data out A 23
data out B 23

CodeR12T12R11T11R10T10Type
SSTL 1.5V output

Description
Single-ended data outputs

sdasclkadd1
add2
add3

M9M8N8P8P7

1.5V CMOS input

I2C bi-directional data signal
I2C clock signal
Chip address setup pins

dtoncton

D9
D83V DC CMOS
inputs

1.5V DC CMOS
inputsActivation of internal termination
for data and clock inputs: “high”termination “ON”, “low”termination “OFF”

Table 5. Package Power Supply Balls.

NameCodeTypeValue, Vvee
B2-B8, C2-C14, D2-D4, D10-D14, Ground
0E2-E14, F2-F4, F12-F14, G2-G4,
G12-G14, H2-H4, H12-H14,J2-J4, J12-J14, K2-K4, K12-K14,
L2-L4, L12-L14, M2-M7,
M10-M14, N2-N5, N9-N14,
P2-P6, P9-P14, R2-R8
vcc
F8, F9, F10, G9, K9, L9, L10
Analog positive
2.9 – 3.3
supply voltage
vdd
F7, F11, G6, G7, G10, G11, H10, Digital positive
1.4 – 1.6
J10, K6, K7, K10, K11, L7, L11 supply voltage
vtt
F6, G8, H5, H6, H7,SSTL input
vdd/2
J5, J6, J7, K8, L6, L8
termination voltage
vref
D6, N6
Reference voltage
vdd/2
for SSTL input buffersn/c
L1
Not connectedX
D5, D7, F5, G5, H8, H9, H11,
Removed balls
J8, J9, J11, K5, L5, N7

Rev. 1.6.2

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ELECTRICAL CHARACTERISTICS
Table 6. Electrical Characteristics.

PARAMETERVCC
VDDVEEPower consumption
Junction temperatureData Rate
Swing (SE)CM Voltage Level
Allowed VIH range
Allowed VIL range
Frequency
Swing (SE)CM Voltage Level
Data Rate
Swing (SE)CM Voltage Level
Interface
Frequency
Swing (SE)CM Voltage Level
Interfaceclk_in to clk_out

MIN
TYP MAX
UNIT
General Parameters+3.14+3.3+3.47
V
+1.43
+1.5
+1.57
0.0
V
2.1
W
-2550
125°C
Input Data (data in)
12000
Mbps
1.5
V
750mV
1.1
1.8
V
0450mV
Input Clock (clk in)
12000
MHz
1.5
V
750mV
Output Data (data out)
0.51000
Mbps
1.5V
750mV
SSTL1.5HS Output Clock (clk out)
12000
MHz
1.5
V750
mV
SSTL1.5
Timing Parameters420510560
ps

clk_in to c2_out

640

780880ps

clk_in to c4_out

640760890

ps

Data skew

0ps

Clock skew

0ps

τcdi1
τcdi2
τc2d
τc2c4
Rev. 1.6.2

200
230
90

245
275
201300330
24-1

10COMMENTS±5%

Peak-to-peakPeak-to-peakPeak-to-peakPeak-to-peak

Propagation delay

By simulation

ps
ps
ps
ps

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PACKAGE INFORMATIONThe chip is packaged in a custom 256-pin BGA package. The drawing of the package is shown in Fig. 7.

ASNT2031

ASNT 2031

Fig. 7. BGA Package.

The part’s identification label is ASNT2031-MBL. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all tensubstances.

Rev. 1.6.2

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REVISION HISTORY
Revision
1.6.2
1.5.2
1.5.1

Date
05-2020
07-2019
01-2013

1.4
1.3
1.2
1.1
1.0

08-201108-201107-201107-201106-2011

Rev. 1.6.2

Changes
Updated Package Information
Updated Letterhead
Corrected format.
Added pin out drawing.
Corrected block diagram.
Added Absolute Maximums Rating table.
Corrected Package Information section.
Added Revision History table.
Revised Electrical Characteristics.
Revised Electrical Characteristics.
Revised Electrical Characteristics.
Revised Electrical Characteristics.
First release.

12May 2020