Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT7120-KMA
6GS/s, 4-bit Flash Analog-to-Digital Converter
18GHz analog input bandwidth
Selectable clocking mode: external high-speed clock or internal PLL with external reference clock
Broadband operation in external clocking mode: DC-6GS/s
On-chip PLL with a central frequency of 10GHz
Optional external preset of the internal clock divider
Internal demultiplexer 4-to-16 for the output data rate reduction
Differential CML input data and clock buffers
Proprietary low-power LVDS output interface
Selectable output clock frequency and polarity
Selectable on-chip digital-to-analog converter for self-testingSingle +3.5V power supply
Power consumption: 2.4W
Custom 100-pin metal-ceramic package
vee
vee
q11n
q11p
vcc
q12n
q12p
vcc
q13n
q13p
vcc
q14n
q14p
vcc
q15n
q15p
n/c
vee
odn
odp
vcc
n/c
n/c
n/cvee














ASNT7120vee
vrefcrl
vlsbcrl
ondac
resn/cvcc
vee
vee
vcc
dpdnvcc
vee
vee
vcc
cep
cen
vcc
vee
vee
vcc
crp
crn
vcc

vee
vee
q02p
q02n
vcc
q01p
q01n
vcc
q00p
q00n
vcc
clop
clon
n/c
vee
cosel1cosel2
cosel3
lol
ftr
vee
ceoff
vee
cpsel
vcc

vcc
q10p
q10n
vcc
q09p
q09n
vcc
q08p
q08n
vcc
q07p
q07n
vcc
q06p
q06n
vcc
q05p
q05n
vcc
q04p
q04n
vcc
q03p
q03n
vcc

Rev. 2.7.2

1

February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
ondac

DAC

vrefcrl
vlsbcrld

LIB 154-bitTTB
Flash 15
EncoderADC

odLOB

4:16
16
DMX
16

ftr
lolcr
ceceoff

LVDS
OBx17

CMU &Divider

rescosel1cosel2
cosel3q00-q15

ClkProc.

cloFig. 1. Functional Block Diagram

The ASNT7120-KMA is a 4-bit flash analog to digital converter (ADC) featuring high sampling rate andwide analog front-end bandwidth. The ADC system shown in Fig. 1 includes a linear input buffer (LIB)
with a tree architecture and a CML-type input interface with internal 50Ohm single-ended terminations tovcc. The buffer delivers 15 matching copies of the input analog data signal d to the 4-bit flash ADC. The
ADC creates 15 samples of the input data in thermometer code, which are then converted into 4-bit binary
words with a data rate f. The encoded data is demultiplexed into 16-bit wide words with a data rate f/4 andsent to the output through 16 low-power LVDS buffers. An optional digital-to-analog converter (DAC)
can be used for the control of the ADC’s operation.
All operations are synchronized by the internal clock multiplication unit (CMU) based on a PLL (phaselocked loop) with an integrated divider. The block can operate in two different modes: clock
multiplication (PLL is on) and clock division (PLL is off). In both modes, the divider generates internal
clock signals divided by 2, 4, 8, and 16. The generated clocks divided by 4, 8, and 16 are sent to theLVDS output clo through a clock processor that selects the desired speed (cosel1, cosel2 controlsignals) and polarity (cosel3 control signal) of the output clock. In the second operational mode of CMU,
the divider can be preset by the external signal res to ensure the correct phase relation between the output
data and clock.
The part operates from a single +3.5V power supply. All external control signals are compatible with the2.5V CMOS interface.

Rev. 2.7.2

2February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Linear Input Buffer (LIB)
The system includes a linear input buffer (LIB) with a tree-type architecture that delivers 15 matchingcopies of the wide-band input differential analog data signal dp/dn to the 4-bit flash section. Symmetry is
closely followed in both schematic and layout to ensure minimal aperture jitter.

Clock Multiplication Unit (CMU) & Divider
The PLL-based CMU with external loop filter connected to the pin ftr as shown in Fig. 2 can operate in
two different modes. In the first “clock multiplication” mode (ceoff=”1”), the CMU multiplies theexternal reference clock crp/crn with the speed of f/16 by means of a PLL with a central frequency of f
and a wide tuning range of the internal VCO (voltage-controlled oscillator). The generated clock isprocessed by the divider in order to generate internal clock signals divided by 2, 4, 8, and 16.
100Ohm
To pin 20 (ftr)

1nFveeFig. 2. Recommended External Loop Filter SchematicIn the second “clock division” mode (ceoff=”0”), the PLL is disabled and the internal clocks aregenerated from the external high-speed clock cep/cen. To ensure the correct bit order, the divider should
be preset by the active-high CMOS control signal res. A special control signal cpcsel can be used tofine-tune the PLL loop gain. It is recommended to keep this pin not-connected (at default state).

HS External Clock Input Buffer
The high-speed external clock input buffer can accept high-speed clock signals at its differential CML
input port cep/cen. It can also accept a single-ended signal with a threshold voltage applied to the unused
pin. HS CIB can handle a wide range of input signal amplitudes. The buffer utilizes on-chip single-endedtermination of 50Ohm to vcc for each input line.

LS Reference Clock Input Buffer
The low-speed reference clock input buffer is a proprietary LVDS buffer with internal 100Ohm
differential termination between its inputs crp/crn. The buffer exceeds the requirements of standards
IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. It is designed to accept differential signals withamplitudes above 100mV peak-to-peak (p-p), a wide range of DC common mode voltages, and AC
common mode noise with a frequency up to 5MHz and voltage levels ranging from 0 to 2.4V.

4-bit Flash Analog to Digital Converter (ADC) with Encoder
This block samples the incoming analog data with the clock signal provided by the CMU in order togenerate a 4-bit output digital signal (Bit 0 – Bit 3) with MSB corresponding to Bit 3. The thresholdvoltages (Vth) of the ADS can be adjusted through analog signals vrefcrl and vlsbcrl as shown in Table 1.
Table 1. Threshold Adjustment Options

Control signal
Adjusted value
Name
Range
NameRange
vrefcrl
vcc-1.0V -> vcc
Vth 15vcc -0.5V -> vcc -0.15Vvlsbcrl vcc -0.6V -> vcc -0.2V Vth (X+1) – Vth X
550uV -> 55mV
Rev. 2.7.2

3February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

As can be seen, vrefcrl shifts the DC levels of all the threshold voltages simultaneously by the sameamount while vlsbcrl alters the voltage range of the least significant bit (LSB).
If no external voltages are applied to vrefcrl and vlsbcrl, it is recommended that both pins are ACterminated by 50Ohm to vee through a DC block!

Demultiplexer (4:16 DMX)This block deserializes the 4-bit words from the ADC into 16-bit output words as shown in Table 2.
Table 2. Demultiplexer Bit OrderFirstSecondThirdFourth
Serialized input words
0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3
ADC bits (3 is MSB)
00 04 08 12 01 05 09 13 02 06 10 14 03 07 11 15
DMX output bits

Clock Processor (Clk Proc)
To increase the adaptability of the designed ADC, a clock processor that provides a low-speed output
clock signal with the options specified in Table 3, is included.
Table 3. Output Clock Options

External control signals Output clock signal
cosel1 cosel2 cosel3 Speed Inversion
111c4
Yes
110c4
No011c8
Yes0
10c8
Nox01c16
Yes
x00c16
No

Digital to Analog Converter (DAC)A DAC block is included to perform a quick test of the ADC’s functionality. When activated by theexternal control signal (ondac=”1”), it converts the digital data into a step-wise copy of the input signalthat is sent to the output odp/odn through a linear differential output buffer. The circuit is not consuming
any power when disabled (ondac=”0”).

LVDS Output Buffers
The 16-bit differential digital data words q00p/q00n to q15p/q15n are delivered to the output through anarray of proprietary low power LVDS buffers. The low speed differential clock clop/clon also utilizes asimilar LVDS output buffer. The buffers satisfy all the requirements of the IEEE Std. 1596.3-1996 andANSI/TIA/EIA-644-1995.

Rev. 2.7.2

4February 2020Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

TERMINAL FUNCTIONS
Pin # Pin namePin type
Pin # Pin name Pin type Pin # Pin name Pin type
GND
3.5V
LVDS
1
vee
35
vcc
69
q12p
outputs
GND
GND
2
vee
36
vee
70
q12n
LVDS
GND
3.5V
3q02p
37
vee
71
vcc
outputs
3.5V
LVDS
4q02n
38
vcc
72
q11p
outputs
3.5V
HS CML5vcc
39
dn
73
q11n
inputs
LVDS
GND
6q01p
40
dp74veeoutputs
3.5V
GND
7q01n
41vcc
75
vee
3.5V
GND
3.5V
8vcc
42
vee
76vcc
LVDS
GND
LVDS
9q00p
43
vee
77
q10p
outputs
outputs
3.5V
10q00n
44vcc
78
q10n
3.5V
3.5V
11vcc
45
n/c
79
vcc
LVDS
CMOS input
LVDS
12clop
46
res
80
q09p
outputs
outputs
CMOS input
13
clon
47
ondac
81
q09n
Control
3.5V
14n/c
48
vlsbcrl82
vcc
voltages
GND
LVDS
15
vee49
vrefcrl83
q08p
outputs
CMOS
input
GND
16
cosel150
vee
84
q08n
CMOS input
GND
3.5V
17
cosel251vee85vcc
CMOS input
LVDS
18cosel352n/c86
q07p
outputs
Control output
19lol
53n/c87q07n
Filter
3.5V
20
ftr
54n/c88vcc
GND
3.5V
LVDS
21
vee
55
vcc
89
q06p
outputs
CMOS input
LS CML
22
ceoff
56
odp
90
q06n
outputs
GND
3.5V
23
vee
57
odn
91
vcc
CMOS input
GND
LVDS
24
cpcsel
58
vee
92
q05p
outputs
3.5V
25
vcc
59
n/c93
q05n
3.5V
LVDS
3.5V
26vcc
60
q15p94vcc
outputs
LVDS
LVDS27crn
61
q15n
95
q04p
inputsoutputs
3.5V
28
crp62
vcc
96
q04n
3.5V
LVDS
3.5V
29
vcc
63
q14p
97
vcc
outputs
GND
LVDS
30
vee
64
q14n
98
q03p
outputs
GND
3.5V
31
vee
65
vcc
99
q03n
3.5V
LVDS
3.5V
32
vcc
66
q13p
100
vcc
outputs
HS CML
33
cen67
q13n
inputs
3.5V
34
cep
68
vcc

Rev. 2.7.2

5February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.comELECTRICAL CHARACTERISTICSPARAMETERTYP MAXUNIT
COMMENTS
General Parameters
3. 4
3.5
3.6
V
±3%vcc0.0
VExternal groundveeIvcc
680mA
Power consumption
2.4W
Junction temperature
-2550
125°C
Analog Input Data (dp/dn)
Bandwidth
0.018
GHz
CM Level
vcc-0.8vcc
VMust match for both inputs
Linearity range±110mV
Around CM level
Non-linearity±3%of the linearity range
HS Input Clock (cep/cen)Frequency
DC6GHzSwing
0.20.8V
Differential or SE, p-p
CM Voltage Level
vcc-0.8
vccVMust match for both inputs
Duty Cycle
405060%LS Reference Input Clock (crp/crn)
Frequency
560688MHz
1/16 of VCO frequency
CM Level
0.2vccVVoltage Swing
100800mV
Differential
Duty Cycle
405060%
Output Data (q00p/q00n to q15p/q15n)
Data RateDC
1.5Gbps
CM Level
1.2
V
Nominal for LVDS interface
Amplitude range
250350mV
Rise/Fall Times
TBD
ps
20%-80%LS Output Clock (clop/clon)
Frequency
f/4
f/8
f/16
GHz
Selectable. Here f is the PLLor HS input clock frequency
CM Level
1.2V
Nominal for LVDS interface
Amplitude range
250350
VJitter
TBD
psDuty Cycle
50%
DAC Output (odp/odn)
Voltage Swing
250350mV
Single-ended. p-p
CM Levelvcc-(voltage swing)/2V
Analog Control Signals (vrfcrl, vlsbcrl)
Voltage rangeV
see Table 1
CMOS Control Signals (cosel1, cosel2, cosel3, ceoff, cpcsel, res, ondac)
Logic “1” levelvee+2.3
vee+2.5
V
Logic “0” level
vee+0.2
V
Rev. 2.7.2

MIN6February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings presented in Table 4 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (vee).
Table 4. Absolute Maximum Ratings

Parameter
Supply Voltage (vcc)
Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max
4.0
2.75
1.4+100+10098
98UnitsVW
VºCºC%%

PACKAGE INFORMATIONThe chip die is housed in a custom 100-pin CQFP package shown in Fig. 3. The package provides acenter heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends forthis section to be soldered to the vcc plain, which is power for a positive supply.
The part’s identification label is ASNT7120-KMA. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all tensubstances.

Rev. 2.7.2

7February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.comFig. 3. Package Drawing

Rev. 2.7.2

8February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
2.7.2
2.6.2
2.6.1

2.5.1
2.4.1
2.3.1
2.2.1

2.1
2.0
1.1

1.0

Rev. 2.7.2

Date
Changes
02-2020 Updated Package Information
07-2019 Updated Letterhead
07-2015 Updated title
Revised Electrical Characteristics table
Revised Absolute Maximum Ratings section
Revised Package Information section
09-2013 Corrected Table 309-2013 Corrected Table 203-2013 Corrected description
Revised package information
03-2013 Corrected description
Added Bit Order table
Corrected absolute maximum ratings
Corrected electrical characteristics
Revised package information
Corrected format
03-2012 Corrected range of control voltages
03-2012 Added pin out drawing
Added external loop filter schematic
06-2011 Added Absolute Maximums Rating table
Added packaging information
Added RoHS compliancy
Added revision history table
01-2011 First release

9February 2020