A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

A D S A N T E C

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

ASNT5121/5120-PQC
17Gbps Data, 14GHz Clock Distributor

One input signal port and three amplified output signal ports.

On-chip matched phase delays for all outputs.

Fully differential input and output buffers with on-chip 50Ω termination.

CML output interface with 400mV single-ended swing.

Single ±3.3V power supply.

Power consumption: 580mW.

Fabricated in SiGe for high performance, yield, and reliability.

Standard MLF/QFN 24-pin package.

VCC

14GHz analog input bandwidth.

CO1N



VCC

Exhibits low jitter and limited temperature variation over industrial temperature range.

CO1P



VCC

High-speed broadband Data/Clock Amplifier and Splitter for signal distribution.

VEE

18 17 16 15 14 13Rev.: 5,VCC

1912VEECIP

2011VCC

VCC

2110CO2PCIN

229VCC

VCC

238CO2NVEE247VCCFebruary 2010.

123456VCC

CO3P

VCC

CO3NVCCVEE

ASNT5121

ASNT5121-PQC (Old # 5120)

A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

A D S A N T E C

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

DESCRIPTION
The temperature stable ASNT5121-PQC SiGe IC provides active broadband data/clock signal
splitting and is intended for use in high-speed measurement / test equipment. ASNT5121-PQC
can receive an up to 17Gbps data or 14GHz clock signal and effectively distribute it to three
separate phase matched outputs. The part’s I/Os support the CML logic interface with on chip50Ω termination and may be used differentially, AC/DC coupled, single-ended, or in any
combination. It operates from a single ±3.3V power supply.

CLK1outn

CLK1outp

FUNCTIONAL BLOCK DIAGRAM

50505050

C L K in p

C L K 2 ou t p

C L K in n

C L K 2 ou t n
5050

CLK3outn50
CLK3outp50

TERMINAL FUNCTIONSTERMINAL
NAME(NO.)vcc
1,3,5,7,9,11
13,15,17,19,21,23vee
6,12,18,24
cip
20
cin
22
co1p
16
co1n
14
co2p
10
co2n8
co3p2
co3n4

Rev.: 5,TYPE

DESCRIPTION

PS

Power Supply: 3.3V / 0V

PS
Input

Power Supply: 0V / -3.3V
Differential CML high-speed signal inputs

OutputDifferential CML high-speed signal outputs

OutputDifferential CML high-speed signal outputs

OutputDifferential CML high-speed signal outputs

February 2010.

ASNT5121-PQC (Old # 5120)

A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

ELECTRICAL CHARACTERISTICSPARAMETERMIN TYP MAX
UNIT
-3.1
0.0 / -3.3-3.5
V
VEE
3.1
3.3 / 0.0
3.5
V
VCC
175mA
IEE
580mW
Power-2550
125°C
Junction Temp.
Input Data-Clock (clki)
Data rate/Clock frequency
0.017/14
Gbps/GHzCM Level
Vcc-0.8 Vcc-0.2 Vcc
VSwing (Diff or SE)
50400
1000mV
Duty Cycle
40% 50% 60%
Out Data-Clock (clko)
Data rate/clock frequency
0.0
17/14
Gbps/GHzCM Level
Vcc-0.25 Vcc-0.2 Vcc-0.15
VSE Swing
380 400
420mV
Rise/Fall Times
15
1719
ps
Additive Jitter
5ps
Duty Cycle
45%
50%
55%

COMMENTS±6%±6%

Peak-to-peak
For clock signal

Peak-to-peak
20%-80%Peak-to-peak
For clock signal

PACKAGE INFORMATIONThe chip is packaged in a standard 24-pin QFN package. The package’s mechanical information
is available on the company’s website.

Rev.: 5,February 2010.

ASNT5121-PQC (Old # 5120)