Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT8140-KMC
DC-23Gbps PRBS Generator with the (x7 + x + 1) Polynomial

Additional output delayed by half of the sequence period

Asynchronous reset signal for elimination of the “all zeros” initial state

Fully differential CML input interface

Fully differential CML output interface with 400mV single-ended swingSingle +3.3V or -3.3V power supplyPower consumption: 530mW

Custom CQFP 24-pin package

qpveevcc

DC to 23Gbps output data rateqnvccFull-length (27-1) pseudo-random binary sequence (PRBS) generator

vcc

vee

vcc

vcc

clk_p

rstn_p

ASNT8140

vcc

vcc

clk_n

rstn_nvcc

vcc

Rev. 1.7.2

1vcc

qxorp

vcc

qxorn

vcc

vee

vee

February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION

Fig. 1. Functional Block Diagram

The ASNT8140-KMC SiGe IC shown in Fig. 1 provides a full 127-bit long pseudo-random binary
sequence (PRBS) signal according to the polynomial (x7 + x + 1), where xD represents a delay of D clock
cycles. This is implemented as a linear feedback shift register (LFSR) in which the outputs of the seventhand first flip-flops are combined together by an XOR function and provided as an input to the first flipflop of the register.
The LFSR-based PRBS generator produces 127 binary states, excluding the “all zeros” state that is illegal
for the XOR-based configuration. To eliminate this state that locks the LFSR and prevents PRBSgeneration, an asynchronous external active-low preset signal rstn_p/rstn_n is implemented in thecircuit. When the preset is asserted, LFSR is set to the “1000000” state containing one logic “1” value thatis enough for the activation of the PRBS generation. When the preset is released, the chip delivers one
consecutive bit of the PRBS signal to output pins qp/qn per each rising edge of clock clk_p/clk_n,
starting from the above mentioned state.
An additional copy of the same PRBS signal delayed by 63 bits (half of the sequence period) is delivered
to pins qxorp/qxorn and can be used to double the frequency of the output signal using an external
multiplexer (e.g. ASNT5150 part) as shown in Fig. 2.

ASNT8140
qp
qn
clk_p
clk_n
Clk

qxorp
qxorn

Main
PRBS

ASNT5150

20Gb/sMUX 2:1

PRBS
40Gb/sDelayed
PRBS

Fig. 2. PRBS Frequency Doubling

Rev. 1.7.2

2February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

The simulated eyes for both signals are shown in Fig. 3.

Fig. 3. 20Gbps PRBS Output Eye Diagram (Simulation, Slow Corner, 125oC)

All I/O stages are back terminated to vcc with on-chip 50Ohm resistors and may be used in either DC or
AC coupling modes (see also POWER SUPPLY CONFIGURATION). In the first mode, the input
signal’s common mode voltage should comply with the specifications shown in ELECTRICAL
CHARACTERISTICS. In the second mode, the input termination provides the required common mode
voltage automatically. The differential DC signaling mode is recommended for optimal performance.

POWER SUPPLY CONFIGURATION
The part can operate with either a negative supply (vcc = 0.0V = ground and vee = −3.3V), or a positivesupply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os need AC termination
when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be neededfor each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.

Rev. 1.7.2

3February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vcc).
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max
-3.6
0.58
1.0
+90
+100
98
98UnitsVW
VºCºC%%

TERMINAL FUNCTIONSTERMINAL
Name
No.
Type
rstn_prstn_n
clk_p
clk_n
qp
qn
qxorp
qxorn
Namevccvee

Rev. 1.7.2

DESCRIPTION

High-Speed I/Os
Differential high-speed asynchronous reset (active low) inputs
with internal SE 50Ohm termination to vcc
Differential high-speed clock input signals with internal 50Ohm
termination to vcc
Differential high-speed data outputs. Require external SE
50Ohm termination to vcc
Differential delayed sequence high-speed data outputs. Require
external SE 50Ohm termination to vcc
Supply and Termination Voltages
Description
Pin Number
Positive power supply
2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24(+3.3V or 0)
Negative power supply
1, 7, 13, 19(0V or -3.3V)
1192123171553CML
input
CML
input
CMLoutput
CMLoutput

4February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERMIN

TYP MAX UNIT
COMMENTS
General Parameters-3.1-3.3-3.5
V
±6%
vee
0.0
V
External ground
vcc
Ivee
160mA
Power consumption
530mW
Junction temperature -40
25125°C
HS Input Clock (clk_p/clk_n)
Frequency
DC23GHz
Swing0.05
0.30.8V
Differential or SE, p-p
CM Voltage Level
vcc-0.8
vcc
VMust match for both inputs
HS Output Data (qp/qn, qxorp/qxorn)
Swing (SE)
280
440mV
CM Voltage Level
vcc-0.8vcc
VOutput Jitter
2.5
ps
Peak-to-peak
Reset Signal (rstn_p/rstn_n)
Frequency
DC
15
GHz
Rise time
20%of the clock period
Recovery time36
ps
Swing0.05
0.3
0.8
VDifferential p-p
CM Voltage Level
vcc-0.8
vcc
V

PACKAGE INFORMATIONThe chip die is housed in a custom 24-pin CQFP package shown in Fig. 4. The package provides a centerheat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for thissection to be soldered to the vcc plain, which is ground for a negative supply, or power for a positive
supply.
The part’s identification label is ASNT8140-KMC. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all tensubstances.

Rev. 1.7.2

5February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Fig. 4. CQFP 24-Pin Package Drawing (All Dimensions in mm)

Rev. 1.7.2

6February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.7.2
1.6.2
1.6.1

1.5.1
1.4.1

1.3.1
1.2.1

1.1
1.0

Rev. 1.7.2

DateChanges
02-2020 Updated Package Information
07-2019 Updated Letterhead
11-2015 Updated description
Updated power supply configuration
Updated absolute maximum ratings section
Corrected electrical characteristics table
Updated package information section
08-2013 Corrected description
02-2013 Corrected title
Corrected description
Corrected terminal functions table
Corrected package information section
01-2013 Updated power and current consumption
01-2013 Added package pin out drawing
Corrected absolute maximum ratings
Added package mechanical drawing
Format correction
01-2012 Updated description
Updated electrical characteristics section
08-2011 Initial release7

February 2020