A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

A D S A N T E C

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

ASNT1016
16:1 MUX-CMU
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16 to 1 multiplexer (MUX) with integrated CMU (clock multiplication unit).
PLL-based architecture featuring both counter and forward clocking modes.
Supports multiple data rates in the 9.8-12.5Gb/s range.
Optional CML high-speed clock input for a broad-band digital mode of operation.
LVDS compatible parallel input data and low-speed clock buffers.
High speed full rate clock output.
Dual clock-divided-by-16 LVDS output buffers.
Single +3.3V power supply.
Industrial temperature range.
Low power consumption of 660mW at 12.5Gbps.
Available in custom 12x12-pin BGA package (10mm x 10mm).

DESCRIPTION
bitorder
d00

d15
vecl
offecloffchooffc64
off12g
lol1n
ftr1p
ftr1n
cr16

LS
DIB
x16

MUX
16:1

16HS
COBcho

LVDS
COBx2

clo

PLL1LSCIBref

C16/16Cclcc

cdqcml/4ceoffpll1
oncc
offpll2
lol2n
ftr2p
ftr2n

DataOBcco

PLL2
LSCIB

ref

Fig. 1. Functional Block Diagram.

Rev.: 1,April 2008.

1ASNT1016-BGA

A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

ASNT1016 is a low power and high-speed 16-to-1 multiplexer (MUX) with an internal clock
multiplication unit (CMU). The MUX can function in CMU mode at data rates (f bit ) between
9.8Gb/s and 12.5Gb/s by utilizing its multiple on-chip full-rate VCOs, or as a broad-band digital
MUX with data rates from DC to 14Gb/s.
The main function of ASNT1016 is to multiplex 16 parallel data channels running at a bit rate off bit /16 into a high speed serial bit stream running at a rate of f bit . It provides a high-speed output
data channel for point-to-point data transmission over a 50Ohm controlled-impedance media.
The transmission media can be a printed circuit board or copper coaxial cables. The functional
distance of the data transfer is dependent upon the attenuation characteristics of thetransportation media and the degree of noise coupling to the signaling environment.
During normal operation, the serializer’s low-speed input buffer (LS DIBx16) accepts external
16-bit wide parallel data words “d00”-“d15” through 16 differential inputs with LVDS interfaces
tolerable to common-mode voltage deviation from “vee” to “vcc”, and delivers them to themultiplexers core (MUX16:1) for serialization. By utilizing pin “bitorder”, the serializer candesignate either “d00” or “d15” as the MSB thus simplifying the interface between ASNT1016
and a proceeding ASIC.
MUX16:1 serializes the data words with multiple divided down clock signals that are generated
from the full rate clock “C” by the internal divider (/16). The divider also produces a clock
divided-by-16 signal “C16” for use by both phase locked loops. “C” is synthesized by the main
phase-locked loop (PLL1) that references either an external system level clock “cr16” deliveredby one of the low speed clock input buffers (LS CIB) or the internal clock “cc” that is generated
by the secondary phase locked loop (PLL2) in concert with a different external low speed clock“cd”. Both “cr16” and “cd” must be 1/16 the frequency of the active full rate VCO in PLL1.
PLL1 contains 2 full rate VCOs to cover the 9.8-12.5GHz range, which are selected utilizing the“off12g” control pin. PLL1 can be also disabled through “offpll1” control pin, in which caseclock “C” must be provided externally through input “ce”. This input can be either DC coupled
utilizing a differential CML signal, or AC-coupled utilizing a single-ended (SE) signal applied to
one of the differential pins.
ASNT1016 offers 3 different kinds of clocking modes. In the default state, PLL2 is turned off
through pin “offpll2” and PLL1 is locked to the “clean” system clock “cr16”.
In the forward clocking mode (“offpll2”=0 & “oncc”=0), an active PLL2 is locked to the “dirty”
external clock “cd” provided by the preceding ASIC in parallel with the input data and generates
a “clean” reference clock “cc” for PLL1. The “clean” system clock “cr16” is not needed since
PLL2 provides “clock cleaning” functionality.
In the counter clocking mode (“offpll2”=0 & “oncc”=1), PLL2 is used to ensure a robustinterface between the driving ASIC and ASNT1016. PLL1 is locked to the “clean” system clock“cr16”, while PLL2 is locked to “C16”, which is generated by PLL1 and /16. The low speed
output clock from PLL2 “cco” controls the output stage of the preceding ASIC and initiates thetransmission of its parallel data and respective clock “cd” across the parallel bus to the inputs ofASNT1016.
Rev.: 1,April 2008.

2

ASNT1016-BGA

A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

The serialized words are transmitted as 2-level signals “qcml” by a differential CML outputbuffer (Data OB). A full-rate clock “cho” is transmitted by a similar CML buffer (HS COB) inparallel with the high-speed data. The clock and data outputs are well phase matched to eachother resulting in very little relative skew over the operating temperature range of the device. HS
COB may be disabled to save power by means of the 2-state CMOS “offcho” signal. Both output
stages are back terminated with on-chip 50Ohm resistors.
ASNT1016 also provides a differential low speed output clock derived from PLL1 though aLVDS clock output buffer (LVDS COB). This LVDS output signal “clo” may be configured foreither “C16” or full rate clock divided-by-64 “C64” operation through pin “offc64”.
Both PLL1 and PLL2 generate loss of lock signal alarms “lol1n” and “lol2n”. Off chip capacitors
are required for both PLLs and are connected through pins “ftr1p/n” and “ftr2p/n”.
The serializer uses a single +3.3V power supply and is characterized for operation from −25°C to125°C of junction temperature.

LS DIBx16
The Low-Speed Data Input Buffer (LS DIBx16) consists of 16 proprietary universal input
buffers (UIBs). UIB is designed to accept differential signals with amplitudes higher than 60mV
peak-to-peak (p-p), DC common mode voltage variation between the negative (vee) and positive(vcc) supply voltages, and AC common mode noise with a frequency up to 5MHz and voltage
levels ranging from 0 to 2.4V. It can also receive single-ended signals with amplitudes of morethan 60mV p-p and threshold voltages between vee and vcc. By default, the input termination
impedance is set to 100Ohm differential to support the LVDS standard. Correct impedance for
the CML and ECL standards (50Ohm single ended to vcc) is set by applying logic “0” to“offecl”. Vcc should be applied to “vecl” for CML operation while +2V is needed for ECL input
signaling.

LS CIB
The Low-Speed Clock Input Buffer (LS CIB) is a UIB that can run at a frequency up to 800MHz.
This block is used for both low speed clock inputs “cd” and “cr16” inputs and is also affected by
the “offecl” and “vecl” control signals.

PLL1
The Main Phase Locked Loop (PLL1) contains a phase frequency detector, charge pump, an onchip integrator with an additional off-chip filtering capacitor of 1nF connected between the pins
“ftr1p” and “ftr1n”, two selectable LC-tank VCOs centered at 11.8GHz and 11.0GHz, and aselectable HS clock input buffer with a SE 50Ohm input termination.
The main function of PLL1 is to synthesize full rate clock “C” by aligning the phase andfrequency of “C16” of the activated VCO to the low-speed reference clock signal that is either
applied externally “cr16” or generated internally by PLL2 “cc”.

Rev.: 1,April 2008.

3

ASNT1016-BGA

A D S A N T E CA d v a n c e dS c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

A logic “0” output CMOS loss-of-lock “lol1n” alarm signal is generated by PLL1 if its two input
clock signals are not matching in phase and/or frequency.
Selection of the different VCOs of PLL1 is achieved by utilizing the CMOS control pin“off12g”. A logic “1” chooses the 11.0GHz VCO while a logic “0” selects the 11.8GHz VCO(default state). The unused VCO is turned completely off in order to save power.
The clock multiplication function of PLL1 can be disabled by a CMOS logic “1” level at thecontrol pin “offpll1”. In this case an external HS clock must be applied to “ce” inputs and thechip operates in the digital mode.

PLL2
The Secondary Phase Locked Loop (PLL2) is used for input reference clock “cleaning” in theforward-clocking mode or for output reference clock generation in the counter-clocking mode. Itcontains a phase frequency detector, charge pump, an on-chip integrator with an additional offchip filtering capacitor of 47nF connected between the pins “ftr2p” and “ftr2n”, and a ring VCO.
The operational modes of PLL2 are controlled by the external CMOS signals “oncc” and“offpll2”. The default state for both signals is logic “1”, which enables the counter-clocking
mode for PLL1, but disables PLL2.
A logic “0” output CMOS loss-of-lock “lol2n” alarm signal is generated by PLL2 if its two input
clock signals are not matching in phase and/or frequency.

/16
The Divider-by-16 (/16) includes 4 divide-by-2 circuits connected in series. High-speed clock“C” is fed into the first divide-by-2 circuit that generates “C2”. “C2” is routed internally to thenext divide-by-two circuit and outside of the block to MUX16:1. Other divided down clock
signals are formed and routed to MUX16:1 in similar fashion. “C16” (“offc64”=1, default) or“C64” (“offc64”=0) is passed on to a LVDS COB and becomes the output low speed clock
signal “clo”.

MUX16:1
The 16 to 1 Multiplexer (MUX16:1) utilizes a tree type architecture that latches the incoming
data on the negative edge of the “C16” clock signal that is supplied by /16. The 16-bit wide data
word is subsequently multiplexed and delivered to Data OB as a serial data stream running at adata rate up to 12.5Gbps. The latency of this circuit block is equal to roughly one period of thelow-speed input clock. When “bitorder”=0 (default), “d00”is the MSB and when “bitorder”=1,“d15” is designated the MSB.

Data OBThe Data Output Buffer (Data OB) receives high-speed serial data from MUX16:1 and converts
it into the CML output signal “qcml” with a single ended swing of 600mV. The buffer requires
50Ohm external termination resistors connected between “vcc” and each output to match its
internal 50Ohm resistors and can operate at a data rate up to 12.5Gbps.
Rev.: 1,April 2008.

4ASNT1016-BGA

A D S A N T E CA d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

HS COBThe High Speed Clock Output Buffer (HS COB) utilizes the same termination scheme as Data
OB and can operate at a frequency up to 12.5GHz while producing a single-ended CML output
swing of 600mV. The buffer can be enabled or disabled by the external 2-state control signal“offcho”. The logic “0” state provides a full-rate clock output signal while the logic “1” state
disables the buffer completely to save power.

LVDS COB x2
The dual LVDS Clock Output Buffer (LVDS COB x2) receives “cl” and “cc” signals andconverts them into the LVDS output signals “clo” and “cco”. Each proprietary low-power LVDS
output buffer utilizes a special architecture that ensures operation at frequencies up to 2GHz witha low power consumption level of 30mW. The buffer satisfies all the requirements of the IEEE
Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995.

Output Timing
Phase relation between the output data “qcml” and full rate output clock “cho” is specified inTable 1 and illustrated by Fig. 2.
Table 1. Output Data-to-Clock Phase Difference

Junction temperature,
τ, psºC
Min. Max.
-25
77
80
50
82
86
12587
91

clk edge
OutputDataτ

Tclk
Fig. 2. Output Timing Diagram

Rev.: 1,April 2008.

5

ASNT1016-BGA

A D S A N T E CA d v a n c e dS c ie n c ea n dN o v e lT e c h n o lo g y27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

TERMINAL FUNCTIONS
The description of the package balls is presented in the table below.
TERMINAL BALL
Name Code TypeDESCRIPTION

High-Speed I/Os
chopchon
qcmlp
qcmln
cepcen

M11 Output CML differential clock outputs. Require external SE 50Ohm
termination to “vcc”. Can be disabled by “offcho”.
L12
H12 Output CML differential data outputs. Require external SE 50Ohm
termination to “vcc”.
E12L6 InputCML differential clock inputs with on-chip SE 50Ohm
termination to “vcc”. Used in digital mode of operation as anM6
alternative for the internal clock generated by PLL1.

Controls
lol1n
lol2n
ftr1p
ftr1n
ftr2p
ftr2n
offpll1
offc64
offpll2
offchooff12goncc
bitorderE3 LS Out, PLL1 lock indicator (high: locked; low: no lock).
D3 CMOS PLL2 lock indicator (high: locked; low: no lock).
K8 I/O PLL1 external filter connection (1nF capacitor differential).
K9F3 I/O PLL2 external filter connection (47nF capacitor differential).
G3
J10 LS In., PLL1 activation (default: low, PLL1 is enabled; active: high,
CMOS PLL1 is disabled, digital mode of operation).
K5 LS In., Division ratio clock selection (active: low, division by 64;
CMOS default: high, division by 16).
J4 LS In., PLL2 activation (active: low, PLL2 is enabled; default: high,CMOS PLL2 is disabled).
K3 LS In., HS COB control (active: high, buffer is disabled; default: low,
CMOS full-rate output clock).
K10 LS In., VCO frequency selection (active: high, 11.0GHz; default: low,CMOS 11.8GHz).
K6 LS In., Counter clocking control (active: low, forward clocking mode;
CMOS default: high, counter-clocking mode).
C4 LS In., Input bit order selection (active: high, d15 is serialized first;
CMOS default: low, d00 is serialized first).

Low-Speed I/Os
cr16p
cr16n
cdp
cdn
clop
clon
ccop
Rev.: 1,A11 Input Differential reference clock inputs with internal termination
selectable through “offecl” and “vecl”.
B12
A6 Input Differential inputs for clock aligned with data. Internaltermination is selectable through “offecl” and “vecl”.
B6
M8 Output LVDS clock outputs. Can transmit “C16” or “C64” divided
clocks from PLL1 as defined by “offc64”.
M9A9 Output LVDS clock outputs from PLL2.
April 2008.

6

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27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

ccon
d00p
d00n
d01p
d01n
d02p
d02n
d03p
d03n
d04p
d04n
d05p
d05nd06p
d06n
d07p
d07n
d08p
d08n
d09p
d09n
d10p
d10n
d11p
d11n
d12p
d12n
d13p
d13n
d14p
d14n
d15p
d15n

A8A5
B5A4B4A3
B3A2
B2
C2C1
D2
D1E2
E1
F2
F1
G1
G2
H1
H2
J1
J2
K1
K2
L2
M2
L3
M3
L4
M4
L5M5

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

Input

Differential data inputs with internal termination selectablethrough “offecl” and “vecl”. Default is set to LVDS.

Supply and Termination Voltages
Namevcc
veenc
Rev.: 1,Description
Positive power supply.
(+3.3V)
Negative power supply.
(GND or 0V)
Unconnected pin.
April 2008.

Ball CodeB1, C5, C6, C7, C9, E10, H10, K4, L1
A1, A7, A10, A12, B7-B11, C8, C10-C12, D5-D9,D11, D12, E4-E9, E11, F4-F12, G4-G9, G11, G12,
H4-H9, H11, J3, J5-J9, J11, J12, K7, K11, K12, L7L11, M1, M7, M10, M12
C3 (removed ball), D4, D10, G10, H37

ASNT1016-BGA

A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

ELECTRICAL CHARACTERISTICSPARAMETER
V CC
V EE
V ECL
Power consumption
Junction temperature
Data Rate
Swing (Diff or SE)
CM Voltage Level
Frequency
Swing (Diff or SE)
CM Voltage Level
Duty Cycle
Data Rate
Logic “1” level
Logic “0” level
JitterFrequency
Logic “1” level
Logic “0” level
JitterDuty Cycle
Frequency
Interface
Logic “1” level
Logic “0” level

MIN

TYP MAX
UNIT
General Parameters+3.14+3.3+3.47
V
0.0
V+2.0
V660
mW-2550125°C
LS Input Data (d00-d15)
612.5
780
Mbps
0.06
0.8
V
V EE
V CCV
LS Input Reference Clock (cr16, cd)
612.5
780
MHz
0.06
0.8
V
V EE
V CC
V
40%
50%60%HS Output Data (qcml)
9.8
12.5
Gbps
V CC
V
V CC -0.6
V12ps
HS Output Clock (cho)
9.8
12.5
V CC
V CC -0.6
6GHzVVps50%
LS Output Clock (clo, cco)
612.5
780
MHz
LVDSCMOS Control Inputs/Outputs
V CC -0.4
VV EE +0.4
VCOMMENTS±5%

Peak-to-peakPeak-to-peakPeak-to-peakat 12.5Gb/s

Peak-to-peakat 12.5Gb/s

Meets the IEEE Std.

PACKAGE INFORMATIONThe chip is packaged in ADSANTEC’s custom 144-pin BGA package. The package’s
mechanical information is available on the company’s website.

Rev.: 1,April 2008.

8ASNT1016-BGA