Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT1017-PQA
DC-to-17Gbps Programmable Multiplexer 16:1 / Serializer
Programmable serializer 16-to-1 with CMU or digital operational modes
Supports data rates from 12.0Gb/s to 14.3Gb/s in CMU mode and DC to 17Gb/s in digital mode
LVDS compliant input data buffers
Selectable full-speed or divided-by-2 clock output
LVDS output clock-divided-by-16 with a selectable phase
Single +3.3V power supply
Industrial temperature range
Low power consumption of 500mW at maximum speed
Standard 100-pin QFN package (12mm x 12mm)

vee
vecl
d04n
d04p
vcc
d03n
d03p
vcc
d02n
d02p
vcc
d01n
d01p
vcc
d00n
d00p
bitorder
nc
phs1
phs2
vcc
nc
nc
nc
vee











ASNT1017

vee
nc
nc
nc
clop
clon
vcc
nc
nc
vcc
qp
qn
vcc
nc
vee
vcc
chop
chon
vcc
nc
vee
vcc
cep
cen
vcc

vee
vecl
d13p
d13n
vcc
d14p
d14n
vcc
d15p
d15n
vcc
cr16p
cr16noffecl
vee
offc64nc
offcho
lol1n
ftr1p
ftr1n
off12gvee
offpll
vcc

vcc
d05p
d05n
vcc
d06p
d06n
vcc
d07p
d07n
vcc
d08p
d08n
vcc
d09p
d09n
vcc
q10p
d10n
vcc
d11p
d11n
vcc
d12p
d12n
vcc

Rev. 2.34.232
2019May 2020

1July

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
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Rev. 2.34.232
2019May 2020

2July

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
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DESCRIPTION
bitorderd00

d15

LS
DIB
x16

offc64
off12g
lol1n
ftr1p
ftr1n

PLL

cr16

LSCIBce

HSCIB

MUX
16:1

16

C16/16refC

DataOB

qcml

LVDS
COBclo

CPR

phs1
phs2

HS
COB

choC2

offplloffchoFig. 1. Functional Block Diagram

ASNT1017-PQA is a low power and high-speed 16-to-1 programmable multiplexer (MUX) with an internal
clock multiplier unit (CMU) that can also operate in digital mode using an external high-speed clock. The mainfunction of the chip shown in Fig. 1 is to multiplex 16 parallel data channels running at a bit rate of fbit/16 into ahigh-speed serial bit stream running at fbit. It provides a high-speed output data channel for point-to-point datatransmission over a 50Ohm controlled impedance media. The transmission media can be a printed circuit board
or copper coaxial cables. The functional distance of the data transfer is dependent upon the attenuation
characteristics of the transportation media and the degree of noise coupling to the signaling environment.
During normal operation, the serializer’s low-speed input buffer LS DIBx16 accepts external 16-bit wide
parallel data words d00-d15 through 16 differential LVDS inputs and delivers them to the multiplexer’s core
MUX16:1 for serialization. By utilizing the pin bitorder, the serializer can designate either d00 or d15 as theMSB (first output serial bit), thus simplifying the interface between the multiplexer and a digital data processor.
MUX16:1 utilizes multiple divided down clock signals that are generated from the full rate clock C by theinternal divider /16. The divider also produces the half rate clock C2 for the high speed clock output buffer HS
COB and the divided-by-16 clock signal C16 for use by the phase-locked loop PLL.
In PLL mode, the clock signal C is synthesized by the PLL which locks the internal signal C16 to the external
system-level clock cr16 delivered through the low speed clock input buffer LS CIB. The cr16 frequency may
be selected as either 1/16 or 1/64 of the frequency of the activated VCO (voltage-controlled oscillator) in theRev. 2.34.232
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2019May 2020

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PLL. The PLL contains 2 full rate VCOs to cover the required frequency range. One of the VCOs can beselected utilizing the off12g control pin. The PLL also generates a loss-of-lock alarm signal lol1n. In digitalmode, the PLL is disabled and the external signal ce delivered through the high-speed clock input buffer HS
CIB is used as clock signal C.
The serialized words generated by MUX16:1 are transmitted as binary signals qcml by the differential CML
output buffer Data OB. The selectable full-rate or half-rate clock cho is transmitted by a similar CML buffer(HS COB) in parallel with the high-speed data. The clock and data outputs are well phase-matched to each otherresulting in a very little relative skew over the operating temperature range of the device. HS COB may bedisabled or its operational mode changed by means of the 3-state (vee, vcc, not connected) CMOS signaloffcho. Both output stages are back terminated with on-chip 50Ohm resistors.
The chip also provides a differential low speed output clock clo though an LVDS clock output buffer (LVDSCOB). The 0º, 90º, 180º, or 270º phase of the clock signal can be selected using control pins phs1 and phs2 asshown in Table 2.
The serializer uses a single +3.3V power supply and is characterized for operation from −25°C to 125°C ofjunction temperature.

LS DIBx16
The Low-Speed Data Input Buffer (LS DIB) is a proprietary universal input buffer (UIB) that can run at afrequency up to 1.0GHz. The input termination impedance is controlled by 3.3V CMOS signal offecl and is set
to 100Ohm differential if offecl=”1” (true LVDS mode, default state) or 50Ohm single-ended to vecl ifoffecl=”0” (CML mode). The value of vecl should be equal to vcc in CML mode or vcc-2V in PECL mode. In
this case, the corresponding termination voltage source should be able to both sink and source up to 20mA ofcurrent. Possible input clock application schemes are detailed in Table 1, where Vcm is the common-mode
voltage of the clock signal.
Table 1. LS Input Clock Application Schemes

Interface Clockcep signal
cen signal
typetype Swing, mV Connection
Vcm, VSwing, mV Connection
Vcm, VLVDS
Diff. 70-to-500
DC1.2±1.070-to-500
DC1.2±1.0(offecl
SE140-to-900
ACThresholdDC
vee-to-vcc=”1”)
ThresholdDC
vee-to-vcc 140-to-900
ACCML orDiff. 70-to-500
DCvcc-Swing/2 70-to-500
DC
vcc-Swing/2
PECL
ACAC
(offecl
SE140-to-900
AC
Not connected=”0”)140-to-900
ACThreshold
DCvcc
Not connected
140-to-900
ACThresholdDC
140-to-900ACvcc
As can be seen, UIB is designed to accept differential signals with amplitudes above 60mV peak-to-peak (p-p),
DC common mode voltage variation between negative (vee) and positive (vcc) supply rails, and AC common
mode noise with a frequency up to 5MHz and voltage levels ranging from 0 to 2.4V. It can also receive singleRev. 2.34.232
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ended signals with amplitudes above 60mVp-p and threshold voltages between vee and vcc. UIB fully complies
with LVDS standards IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995.

LS CIB
The Low-Speed Clock Input Buffer (LS CIB) is the same UIB described above. This block is used to deliver thelow speed system clock cr16 as a reference signal to the PLL.

PLL
The Phase Locked Loop (PLL) contains a phase frequency detector, charge pump, an on-chip integrator with anadditional off-chip filter connected between the pins ftr1p and ftr1n (Fig. 2), and two selectable LC-tank VCOs
centered at 14GHz and 12.5GHz. The main function of the PLL is to synthesize the full rate clock C by aligning
the phase and frequency of the C16 signal to the externally applied system clock cr16. The required frequencyof cr16 is defined by the 3.3V CMOS control signal offc64 and should be either 1/16 (offc64=”1”) or 1/64(offc64=”0”) of the activated VCO’s frequency. The active-low 3.3V CMOS loss-of-lock lol1n alarm signal isgenerated by the PLL if its two input clock signals are not matching in phase and/or frequency.

ftr14301n
ftr2430Fig. 2. External Filter Schematic

Selection of different VCOs of the PLL is achieved by utilizing the 3.3V CMOS control pin off12g. The logic“1” chooses the high-speed VCO, while the logic “0” (default state) selects the low-speed VCO. At any state,
the unused VCO is turned completely off in order to save power.

HS CIBThe High-Speed Clock Input Buffer (HS CIB) can accept high-speed clock signals at its differential CML inputport cep/cen. It can also accept a single-ended signal with a threshold voltage applied to the unused pin. HSCIB can handle a wide range of input signal amplitudes. The buffer utilizes on-chip single-ended 50Ohm
termination to vcc for each input line.

/16
The Divider-by-16 (/16) includes four divide-by-2 circuits connected in series. The high-speed clock C is fed
into the first divide-by-2 circuit that generates the half-rate clock C2. C2 is then routed internally to the next
divide-by-2 circuit and outside of the block to MUX16:1. Other divided down clock signals are formed androuted to MUX16:1 in a similar fashion. C16 is passed on to LVDS COB to become the output low speed clocksignal clo.

MUX16:1
The 16-to-1 Multiplexer (MUX16:1) utilizes a tree-type architecture which latches the incoming data on thenegative edge of the C16 clock signal supplied by /16. The 16-bit wide data word is subsequently multiplexedand delivered to Data OB as a single serial data stream. The latency of this circuit block is equal to roughly one
Rev. 2.34.232
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period of C16. The output bit order is controlled by the 3.3V CMOS signal bitorder. The first output serial bit(MSB) corresponds to d00 when bitorder=”0” (default), or to d15 when bitorder=”1”.

Data OBThe Data Output Buffer (Data OB) receives high-speed serial data from MUX16:1 and converts it into
differential CML output signal qcmlp/qcmln. The buffer utilizes internal 50Ohm loads to vcc and requires thematching of 50Ohm external termination resistors connected between vcc and each output.

HS COBThe High Speed Clock Output Buffer (HS COB) utilizes the same termination scheme as Data OB and canoperate at maximum frequency while producing a full single-ended CML output swing. The buffer can beenabled or disabled by the external 3-state (”1"=vcc, “0”=vee, “n/c”=not connected) 3.3V CMOS control signal
offcho. The “n/c” default state corresponds to the C2 output signal, the logic “0” state provides a full-rate
clock output signal, while the logic “1” state disables the buffer completely.

CLK Proc
By utilizing the 3.3V CMOS control pins phs1 and phs2, the phase of clo can be altered in accordance with
Table 2.
Table 2. Output Clock Phase Selection

phs1
phs2
C16 phasevee (default) vee (default)
270°
180°
vee
vcc
90°
vcc
vee
0°
vcc
vcc

LVDS COB
The LVDS Clock Output Buffer (LVDS COB) receives the divided clock C16 and converts it into LVDSoutput signal clo. The proprietary low-power LVDS output buffer utilizes a special architecture that ensures
operation at frequencies up to 2.0GHz with a nominal output current of 3.5mA. The buffer satisfies all therequirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995 standards.

Output Timing
The phase relation between the output data qp/qn and the full rate output clock cho is specified in Table 3 andillustrated by Fig. 3.
Table 3. Output Data-to-Clock Phase Delay

Junction temperature,
τ,ps°C
Min. Max.
-25778050828612587
91

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clk edge
OutputDataτ

TclkFig. 3. Output Timing Diagram

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 4 may cause damage to this product and/or
lead to reduced reliability. Functional performance is specified over the recommended operating conditions forpower supply and temperature only. AC and DC device characteristics at or beyond the absolute maximum
ratings are not assumed or implied. All min and max voltage limits are referenced to ground (assumed vee).
Table 4. Absolute Maximum Ratings

Parameter
Supply Voltage (vcc)
Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Rev. 2.34.232
2019May 2020

Min-4010107

Max+3.60.72
1.0+90+10098
98Units
VW
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TERMINAL FUNCTIONS
Namevccveevecl
ncSupply and Termination Voltages
Description
Pin Number
Positive power supply (+3.3V) 5, 8, 11, 25, 26, 29, 32, 35, 38, 41, 44, 55, 62,65, 68, 71, 76, 79, 82, 85, 88, 91, 94, 97, 100
Negative power supply (GND
1, 15, 23, 30, 36, 50, 51, 75
or 0V)
Input termination voltage (vcc2, 74
for CML, vcc-2V for ECL)
17, 31, 37, 42, 43, 47, 48, 49, 52, 53, 54, 58
Keep not connected!

TERMINAL
NameNo.
Typecepcenchopchon
qpqn28
27
34
33
40
39

lol1n19ftr1p
ftr1n
offecl20
21
14offc64

16offcho

18off12g

22offpll

24

phs1
phs2
bitorder57
56
59

Rev. 2.34.232
2019May 2020

DESCRIPTION

High-Speed I/Os
CML differential external clock inputs with internal SE50Ohm termination to vcc
Output CML differential clock outputs. Require external SE 50Ohm
termination to vcc. Can be disabled by offcho
Output CML differential data outputs. Require external SE 50Ohm
termination to vcc
Controls
LS Out, PLL lock indicator (high: locked; low: no lock)
CMOS
I/O PLL external filter connections (see Fig. 2)
Input

LS In., LS input termination selector (active: low, CML or PECLCMOS depending on vecl connection; default: high, LVDS)LS In., Input reference clock rate selection (active: low, divided-by-64;
CMOS default: high, divided-by-16)
LS In., 3-state HS COB control (high: buffer is disabled; n/c: half-rate
CMOS output clock; low: full-rate output clock)
LS In., VCO frequency selection (active: high, high-speed VCO;
3-state default: low, low-speed VCO)
LS In., PLL activation signal (active: high, PLL is off; default: low,CMOS PLL is on)
LS In., Low-speed output clock phase selection (see Table 2)
CMOS
LS In., Input bit order selection (active: high, d15 is serialized first;
CMOS default: low, d00 is serialized first)
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TERMINAL
NameNo.
Typecr16p
cr16n
clopclon
d00p
d00n
d01p
d01n
d02p
d02n
d03p
d03n
d04p
d04nd05p
d05n
d06p
d06n
d07p
d07n
d08p
d08n
d09p
d09n
d10p
d10n
d11p
d11n
d12p
d12n
d13p
d13n
d14p
d14n
d15p
d15n
Rev. 2.34.232
2019May 2020

121346
45
60
61
63
64
66
67
69
70
72
73
77
78
80
81
83
84
86
87
89
90
92
93
95
96
98
99
3
4
6
7
910Input

DESCRIPTION
Low-Speed I/Os
LVDS clock inputs

Output LVDS clock outputs
Input

LVDS data inputs

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ELECTRICAL CHARACTERISTICSPARAMETER

TYP
MAX
UNIT
COMMENTS
General Parameters+3.14+3.3+3.47
V±5%
vcc
0.0
V
External ground
vee
Ivcc
150mA
Power consumption
500mW
Junction temperature
-2550
125°C
LS Input Data (d00p/d00n-d15p/d15n)
Data Rate
0.0
937.5
1063
Mbps
Differential Swing
0.06
0.8
V
Peak-to-peak
CM Voltage Level
Vveevcc
LS Input Reference Clock (cr16p/cr16n)Frequency
747
831
MHz
12.5GHz VCO is active
807893
MHz
14GHz VCO is active
Differential Swing
0.06
0.8
V
Peak-to-peak
CM Voltage Level
Vveevcc
VCO Frequency Range
Frequency
12.013.3
GHz
12.5GHz VCO is active
Frequency
12.9
14.3
GHz
14GHz VCO is active
HS Input Clock (cep/cen)Frequency
0.0
1517GHz
Swing (Diff or SE)
0.2
1.2
V
Peak-to-peak
CM Voltage Level
vcc-0.8
vcc
VDuty Cycle
405060%HS Output Data (qcmlp/qcmln)
Data Rate
0.0
1517Gbps
Logic “1” level
Vvcc
Logic “0” levelvcc-0.6
VJitter
12ps
Peak-to-peak @12.5Gb/s
HS Output Clock (chop/chon)Frequency0.01517GHz
Logic “1” level
Vvcc
Logic “0” levelvcc-0.6
VJitter5ps
Peak-to-peak @12.5GHz
Duty Cycle
50%
LS Output Clock (clop/clon)
Frequency
0.0937.5
1063
MHz
Rev. 2.34.232
2019May 2020

MIN

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Interface

LVDS
Meets the IEEE Std.
CMOS Control Inputs (3-state input has an additional N/C state)
Logic “1” levelvcc-0.4
VLogic “0” level
vee+0.4
VPACKAGE INFORMATIONASNT1017
Fig. 4. Package Drawing

The chip die is housed in a custom 100-pin QFN package shown in Fig. 4. Even though the package provides acenter heat slug located on the back side of the package to be used for heat dissipation, ADSANTEC does NOT
recommend for this section to be soldered to the board. If the customer wishes to solder it, it should beconnected to the vcc plain that is power for the positive supply.

Rev. 2.34.232
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The part’s identification label is ASNT1017-PQA. The first 8 characters of the name before the dash identify
the bare die including general circuit family, fabrication technology, specific circuit type, and part version whilethe 3 characters after the dash represent the package’s manufacturer, type, and pin out count.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.
This device complies with the Restriction of Hazardous Substances (RoHS) per EU 2002/95/EC for all six
substances.

REVISION HISTORY
Revision
2.34.32
2.3.2
2.3.1

Date
05-2020
07-2019
08-2013

2.2.1

07-2013

2.1.1
2.0.1

06-201206-20121.001-2011

Rev. 2.34.232
2019May 2020

Changes
Updated Package Information
Updated Letterhead
Corrected locking range for the 14GHz VCO (changed frequencies of the HS andreference clocks in Description and Electrical Characteristics)
Corrected Format
Corrected Description
Corrected Electrical Characteristics
Corrected Terminal Functions (offpll pin assigned as a control)
Corrected Description
Revised Electrical Characteristics section
Corrected Terminal Functions
Revised Package Information section
New template
First release

12JulyFormatted: Left