A D S A N T E C

A d v a n c e dS c ie n c ea n dN o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

ASNT2011A (ASNT2015)
1:16 Digital DMUX
•••
•
•••
•
•••

1:16 demultiplexer (DMUX) with integrated full rate CDR (clock and data recovery).
Supports multiple data rates in the 11.3-12.5Gbps range in the CDR mode.
Can operate in broadband digital mode up to 12.5Gbps with application of full rate clock.
Supports both RZ and NRZ input data formats.
LVDS output data buffers that feature a low-power proprietary architecture.
Stable clock-divided-by-16 LVDS output with 90°-step phase selection.
Supports clock-divided-by-16/64 input reference clock.
Single +3.3V power supply.
Industrial temperature range.
Low power consumption of 730mW at 12.5Gbps.
Available in standard 100-pin QFN package (12mm x 12mm).

DESCRIPTION
bitordn/4
oncml
cr
oncr16vtt
off0d

CLKIBDataIBsldDMX
1:16

CDRFWD16LVDS
DOB
x16
q15

C16offrz
losnloln
ftr1
ftr2
ceq00

C16C/16HS
CIB

LVDS
COBx2

clmclo

CLKProcoffcdr
phs1
phs2
Fig. 1. Functional Block Diagram.

Rev.: 1,October 2008.

1ASNT2011A-PQA

A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

ASNT2016 is a 12.5Gbps 1:16 deserializer (DMUX) with full rate integrated clock and data
recovery (CDR FWD). The DMUX can cover input data rates (fbit) in the CDR mode from
11.3Gbps to 12.5Gbps by utilizing its on-chip full-rate VCO or function in the broadband digitalmode. An external full clock “ce” must be applied to the high speed CML clock input buffer (HSCIB) for digital operation. Selection of the operational mode is made through pin “offcdr”.
The main function of ASNT2016 is to demultiplex a serial input data channel “d” running at a bit
rate of fbit into 16 parallel data channels “q00-q15” running at a bit rate of fbit/16. The highsensitivity CDR FWD block ensures accurate clock and data recovery for input data signal
amplitudes greater than 20mV peak to peak (p-p) differential or single-ended. This isaccomplished with the CDR FWD circuitry incorporating both a phase and frequency acquisition
loop to recover a full rate clock “C” from the input data stream. This recovered clock samples theinput data bits before they are demultiplexed and is also sent to the internal divider (/16).
The application of an external low speed system clock “cr” running at 1/16 or 1/64 the frequencyof the VCO clock through the low speed clock input buffer (CLK IB) is required for CDR FWD
to operate correctly. CLK IB by default provides a LVDS input interface, but can properly
process input CML signaling through utilization of the “oncml” control signal. Pin “oncr16”
selects between direct “cr” and “cr” post the divider-by-4 (/4) block.
The high-speed CML data input buffer (Data IB) and HS CIB provide on-chip 50Ohm
termination and are designed to be driven by devices with 50Ohm source impedance. Data IBsets its termination voltage internally, but “vtt” can be used to externally adjust it if desired. Pins
“off0” control the offset voltage between Data IB’s “dp” and “dn” inputs allowing the user tochange the slicing or threshold level at the serial data input. A peak detector is incorporated inData IB to monitor the amplitude of the incoming data stream with its output made available
through the differential pins “sld”. Data IB can handle both RZ and NRZ input data formats.
The reconstructed serial input data is latched into the demultiplexer (DMX1:16) and is
subsequently deserialized and delivered to the demultiplexer’s output as 16-bit wide low-speed
parallel words. Utilizing pin “bitordn”, the deserializer can designate either “q00” or “q15” as theMSB thus simplifying the interface between ASNT2016 and a following ASIC.
Sixteen proprietary low-power LVDS output data buffers (LVDS DOBx16) are used to deliverthe 16 data output signals “q00-q15” while a similar dual LVDS clock output buffer (LVDSCOBx2) outputs the two low-speed clock signals “clm” and “clo”. The buffers satisfy all therequirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995 while only consuming
30mW each. The phase of “clo” can be modified by 90° increments by utilizing pins “phs1” and“phs2”, which program the clock processing block (CLK Proc).
ASNT2016 includes alarm indicators loss of signal “losn” and loss of lock “loln”. “offrz” mustbe activated when NRZ data is present for proper “losn” alarm generation. Off chip passive filter
components are required by CDR FWD and are connected through pins “ftr1/2”.
The deserializer uses a single +3.3V power supply and is characterized for operation from −25°C
to 125°C of junction temperature.
Rev.: 1,October 2008.

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ASNT2011A-PQA

A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

Data IBThe Data Input Buffer (Data IB) can process an input CML data signal “d” with bit rates up to12.5Gbps in either the RZ or NRZ format. Data IB can also accept a single-ended signal to oneof its input ports “dp” or “dn” with a threshold voltage applied to the opposite tuning pin “off0n”
or “off0p”. The tuning pins have input impedances of 250Ohm and allow the user to change theslicing level before the data is sampled by the recovered clock. Data IB can handle input signal
amplitudes between 20mV and 600mV p-p differential or single-ended. The buffer utilizes onchip single-ended termination of 50Ohm to “vtt”=2.5V (default) for each input line where “vtt”
can be adjusted externally.
Also included in Data IB is an input signal peak detector that delivers its response through theoutput differential signal “sld”. The detector can demodulate AM component(s) carried by theinput data stream that are in the frequency range of up to a few hundred kHz. The peak detector’s
output impedance is 3.2KOhm single ended to Vcc.

CLK IBThe Clock Input Buffer (CLK IB) consists of a single proprietary universal input buffer (UIB).
UIB is designed to accept differential signals with amplitudes higher than 60mV p-p, DC
common mode voltage variation between the negative (vee) and positive (vcc) supply voltages,
and AC common mode noise with a frequency up to 5MHz and voltage levels ranging from 0 to
2.4V. It can also receive single-ended signals with amplitudes of more than 60mV p-p andthreshold voltages between vee and vcc. By default, the input termination impedance is set to
100Ohm differential to support the LVDS standard. Correct impedance for the CML standard(50Ohm single ended to vcc) is set by applying logic “1” to “oncml”.

/4
The divide-by-4 block (/4) is controlled by “oncr16” and is activated when “cr” is equal to thefrequency of “C16”. “oncr16” should be set to logic “0” (default) when “cr” is 1/4 the frequencyof “C16”. In both cases, a reference clock signal is delivered to CDR FWD with a frequency of
1/64 the rate of “C”.

HS CIBThe High-Speed Clock Input Buffer (HS CIB) can process an external CML clock signal “ce”
with frequencies from 10.0MHz to 12.5GHz. It can also accept a single-ended signal to “cep/cen”
with a threshold voltage applied to the unused “cen/cep” pin. HS CIB can handle input signal
amplitudes between 200mV and 1.2V p-p differential or single-ended. The buffer utilizes on-chipsingle-ended termination of 50Ohm to vcc for each input line.

CDR FWD
The Clock and Data Recovery Block (CDR FWD) contains both a phase and frequencyacquisition loop that require a single off-chip filter featuring a 200Ohm resistor in series with a1nF capacitor across the pins “ftr1” and “ftr2”. The frequency loop works in concert with “cr”
while the phase loop utilizes “d”.
Rev.: 1,October 2008.

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ASNT2011A-PQA

A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

The main function of CDR FWD is to frequency lock the on-chip VCO to the input data signal(clock recovery) while phase aligning it to latch in the incoming data with minimal error (datarecovery). The recovered clock is also utilized by /16 and DMX 1:16 to demultiplex the data.
CDR FWD raises the loss of signal “losn” flag when the input data’s quality in RZ format is not
sufficient enough for an acceptable bit error rate or the transition density of the data in either
format is not enough or too much. By default, CDR FWD is set for RZ input data (“offrz”=0)
where “offrz” must set to logic “1” when there is input NRZ signaling. A loss of lock “loln” isgenerated by CDR FWD when the frequency difference between a processed “cr” and “C”
divided-by-64 is greater than ±1000ppm.

/16
The Divider-by-16 (/16) includes 4 divide-by-2 circuits connected in series. The high-speed
clock “C” delivered by CDR FWD is fed into the first divide-by-2 where its output is routed
internally to the next divide-by-two circuit and outside of the block to DMX1:16. Other divided
down clock signals are formed and routed to DMX1:16 in similar fashion. Full rate clock
divided-by-16 “C16” is passed on to CLK Proc for additional phase adjustment as well as
directly to a LVDS OB.

DMX1:16
The 1 to 16 Demultiplexer (DMX1:16) utilizes a tree type architecture that latches in the data
stream from CDR FWD on both edges of a half rate clock signal that is supplied by /16. The highspeed data signal is subsequently demultiplexed down and delivered to LVDS DOBx16 inparallel fashion as16-bit wide words running at a data rate up to 780Mbps.

CLK Proc
By utilizing the CMOS control pins “phs1” and “phs2”, the phase of “clo” can be altered inaccordance with the table below.
“phs1”“phs2”“clo” phase
VEE (default) VEE (default)
270°
VEE
VCC
180°
VCC
VEE
90°
VCC
VCC
0°

LVDS DOBx16
The LVDS Data Output Buffer (LVDS DOBx16) accepts 16-bit wide words from DMX1:16 andconverts them into LVDS output signals. Each proprietary low-power LVDS output buffer
utilizes a special architecture that ensures operation at bit rates up to 2Gb/s with a low power
consumption level of 30mW. The buffer satisfies all the requirements of the IEEE Std. 1596.31996 and ANSI/TIA/EIA-644-1995. When “bitordn”=0 (default), “q15”is the MSB and when“bitordn”=1, “q00” is designated the MSB.

Rev.: 1,October 2008.

4ASNT2011A-PQA

A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

LVDS COB x2
The dual LVDS Clock Output Buffer (LVDS COB x2) receives two clock signals and converts
them into the LVDS output signals “clm” and “clo”. Each proprietary low-power LVDS output
buffer utilizes a special architecture that ensures operation at frequencies up to 2GHz with a lowpower consumption level of 30mW. The buffer satisfies all the requirements of the IEEE Std.
1596.3-1996 and ANSI/TIA/EIA-644-1995.

Terminal Functions
The description of the package pins is presented in the table below.
TERMINAL
NameNo.
TypeDESCRIPTION

Low-Speed I/Oscrp
crn
q00n
q00p
q01n
q01p
q02n
q02p
q03n
q03p
q04n
q04p
q05n
q05p
q06n
q06p
q07n
q07p
q08n
q08p
q09n
q09p
q10n
q10p
q11n
q11p
q12n
Rev.: 1,27 Input LVDS or CML reference clock inputs for CDR FWD. Can beeither C/16 or C/64.
28
10 Output
9764399
98
96
95
93
92
90
89
87
LVDS data outputs.
8684838180
7877737270
October 2008.

5ASNT2011A-PQA

A d v a n c e dS c ie n c ea n dN o v e lT e c h n o lo g y

A D S A N T E C

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

q12p
q13n
q13p
q14n
q14p
q15n
q15p
clop
clon
clmp
clmn
sldp
sldn

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

69676664636160
12 Output LVDS clock outputs. Can transmit four different clock phases
as defined by “phs1” and “phs2”.
1317 Output LVDS clock outputs.
1845 Output Peak detector outputs.
46

High-Speed I/Osdpdncepcen

3940
3334Input
Input

CML differential data inputs with internal SE 50Ohm
termination to “vtt”.
CML differential clock inputs with internal SE 50Ohm
termination to “vcc”.

Controls
bitordn
loln
ftr1
ftr2
oncml
vtt
offrz
offcdr
off0p
off0n
losn
oncr16
phs1
phs2
Rev.: 1,16 LS In., Output bit order selection (default: high, q15 is MSB; active:CMOS low, q00 is MSB).
19 LS Out, CDR FWD lock indicator (high: locked; low: no lock).
CMOS
20 I/O External CDR FWD filter connections.
21
24 LS In., Low-speed input clock termination selection: (default: low,CMOS LVDS; active: high, CML).
31 DC In. Termination voltage for Data IB (default: 2.5V). Can be
adjusted externally to desired value.
37 LS In., Input data format selection (default: low, RZ data; active:CMOS high, NRZ data).
47 LS In., Selects CDR or Digital mode of operation (default: low,CMOS CDR; active: high, Digital).
48 DC In., DATA IB thresholding.
49
53 LS Out, Input data signal quality indicator (high: good; low: not
CMOS good).
54 LS In., Activation of /4 block (default: low, cr = C/64, active: high, cr
CMOS = C/16).
57 LS In., Low-speed output clock “clo” phase selection (default: both
56 CMOS low).

October 2008.

6ASNT2011A-PQA

A D S A N T E CA d v a n c e d
S c ie n c ea n d
N o v e lT e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

Supply and Termination Voltages
Namevcc

Description
Positive power supply.
(+3.3V)

Pin Number
5, 8, 11, 14, 25, 26, 29, 32, 35, 38, 41, 44, 52, 55, 59,62, 65, 68, 71, 76, 79, 82, 85, 88, 91, 94, 97, 100.

vee

Negative power supply.
(GND or 0V)
Unconnected pin.

1, 15, 23, 30, 36, 50, 51, 58, 75.

ncRev.: 1,October 2008.

2, 22, 42, 43.

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ASNT2011A-PQA

A D S A N T E C

A d v a n c e d
S c ie n c ea n d
N o v e l
T e c h n o lo g y

27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.

Ph. # 1-310-377-6029.

Fax # 1-310-377-9940.

ELECTRICAL CHARCTERISTICSPARAMETER

Data Rate
Interface

TYP MAX
UNIT
General Parameters+3.14+3.3+3.47
V
0.0
V
730
mW
-2550
125°C
HS Input Data (d)
11.3
12.5
Gbps
0.02
1.2
V
VCC-0.8
VCC
V
HS Input Clock (ce)
0.0
12.5
GHz
0.2
1.2
V
VCC-0.8
VCC
V
40%
50%60%LS Input Reference Clock (cr)
350
780
MHz
0.06
0.8
V
VEE
VCC
V
40%50%60%
LS Output Data (q00-q15)
700
780
Mbps
LVDS

Frequency
Interface

LS Output Clocks (clm, clo)
700780MHzLVDS

Swing (Diff)
Cm Voltage Level

Output of Peak Detector (sld)00.6
V
Vcc-2.5
VVCC
VEE
Power consumption
Junction temperature
Data Rate
Swing (Diff or SE)
CM Voltage Level
Frequency
Swing (Diff or SE)
CM Voltage Level
Duty Cycle
Frequency
Swing (Diff or SE)
CM Voltage Level
Duty Cycle

Logic “1” level
Logic “0” level“clm” and “clo” to “q0q15” delay variation

MIN

CMOS Control Inputs/Outputs
VCC-0.4
V
VEE+0.4
V
Timing Parameters±2.5%

COMMENTS±5%

Peak-to-peakPeak-to-peak

C/64 or C/16
Peak-to-peakMeets the IEEE Std.
1596.3-1996

Meets the IEEE Std.
1596.3-1996
Pk-pk over full range

Over the fulltemperature range

PACKAGE INFORMATIONThe chip is packaged in a standard 100-pin QFN package. The package’s mechanicalinformation is available on the company’s website.
Rev.: 1,October 2008.

8ASNT2011A-PQA