Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT2017-PQA
Programmable CDR/Digital DMUX 1:16
1-to-16 demultiplexer (DMUX) with integrated full rate CDR
Supports data rates from 12.5Gb/s to 13.6Gb/s in CDR mode
Supports data rates from DC to 17Gb/s in the optional digital mode
Proprietary low-power LVDS output buffers for data and clock-divided-by-16
Supports divided by 16 or by 64 input reference clocks in CDR mode
Single +3.3V power supply
Industrial temperature range
Low power consumption of 890mW at maximum speed
Standard 100-pin QFN package (12mm x 12mm)

vee
nc
q04n
q04p
vcc
q03n
q03p
vcc
q02n
q02p
vcc
q01n
q01p
vcc
q00n
q00p
swf20u
vee
phs1
phs2
vcc
oncr16
losn
vcc
vee











ASNT2017

vee
off0n
off0p
offcdr
sldn
sldp
vcc
nc
nc
vcc
dn
dp
vcc
swfm13
vee
vcc
cen
cep
vcc
vtt
vee
vcc
crn
crp
vcc

vee
swam35
q13p
q13n
vcc
q14p
q14n
vcc
q15p
q15n
vcc
clop
clon
swf50uvee
bitordn
clmp
clmn
loln
ftr1
ftr2
swfm32
vee
oncml
vcc

vcc
q05p
q05n
vcc
q06p
q06n
vcc
q07p
q07n
vcc
q08p
q08n
vcc
q09p
q09n
vcc
q10p
q10n
vcc
q11p
q11n
vcc
q12p
q12n
vcc

Rev. 2.0.2

1

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Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
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DESCRIPTION
bitordn/4cr
oncr16
vtt
off0
d

LCI
q00

DIP

DMX
1:16

CDR
FWD

sld

16

LVDS
DOB
x16
q15

setlotsetlod
losn
loln
ftr1
ftr2

c/16

c/16

/16
ce
offcdr
phs1
phs2

LVDS
COB
x2

clm
clo

CLK
Proc

HCI

Fig. 1. Functional Block Diagram

ASNT2017-PQA is a user-programmable 1:16 deserializer (DMUX) with a full-rate integrated clock and data
recovery unit (CDR) that incorporates a frequency window detector (FWD). The main function of the chipshown in Fig. 1 is to demultiplex a serial input data signal d running at a bit rate of fbit into 16-bit wide parallel
data words q00-q15 running at a bit rate of fbit/16. The DMUX can operate in one of two main modes: CDR
mode that utilizes on-chip full-rate VCO with a central frequency of fbit, or broadband digital mode that requires
application of an external full-rate clock ce with the same frequency to the inputs of a high speed CML clock
input buffer (HS CIB). Selection of the operational mode is made through control pin offcdr.
The high sensitivity CDR FWD block incorporates phase and frequency acquisition loops to ensure accurate
recovery of clock and data for an NRZ input data stream. For the correct operation of the block, off-chip passive
filter components should be connected to pins ftr1 and ftr2. CDR FWD also requires an external reference
clock running at 1/16 or 1/64 the VCO’s frequency to be applied to the input cr. The acceptable frequency of
the reference clock is defined by the oncr16 control signal. If the 1/16 mode is selected, the input clock with
Rev. 2.0.2

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Advanced Science And Novel Technology Company, Inc.
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Offices: 310-530-9400 / Fax: 310-530-9402
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frequency of fbit/16 is applied to CDR FWD after an additional divider by 4 (/4). The reference clock input
buffer supports LVDS or CML interfaces as defined by the oncml control signal. The recovered clock is used
for sampling the input data bits before they are demultiplexed and is also sent to the internal divider (/16). CDR
FWD also provides active-low alarm indicators for loss of input signal (losn) and loss of lock (loln).
The high-speed CML data and clock input buffers provide on-chip 50Ohm termination and are designed to be
driven by devices with 50Ohm source impedance. The data input buffer sets its termination voltage internally,
but the vtt pin can be used to externally adjust it if desired. Pin off0 control the offset voltage between data
inputs dp and dn allowing the user to change the slicing or threshold level at the serial data input. A peakdetector is incorporated in Data IB to monitor the amplitude of the incoming data stream with its output madeavailable through differential pins sld.
The reconstructed serial input data is latched into the demultiplexer (DMX1:16) and is subsequently
deserialized and delivered to the demultiplexer’s output as 16-bit wide low-speed parallel words. Sixteen
proprietary low-power LVDS output data buffers (LVDS DOBx16) are used to deliver the 16 data output
signals q00-q15, while a similar dual LVDS clock output buffer (LVDS COBx2) outputs the two copies clm
and clo of the low-speed clock signal. The buffers satisfy all the requirements of the IEEE Std. 1596.3-1996 andANSI/TIA/EIA-644-1995 standards. The phase of the clo clock signal can be selected with a 90° increment by
utilizing control pins phs1 and phs2.
Utilizing control pin bitordn, the deserializer can designate either q00 or q15 as the MSB (first input serial bit),thus simplifying the interface between the demultiplexer chip and a following ASIC.
The chip uses a single +3.3V power supply and is characterized for operation from −25°C to 125°C of junction
temperature.

DIP
The Data Input Processor (DIP) can process differential or single-ended CML signals with bit rates from DC tofbit. The data inputs utilize on-chip single-ended 50Ohm termination to vtt=2.5V (default) for each input line
where vtt can be also adjusted externally. A single-ended data signal can be applied to one of the differential
input pins either directly (DC coupling) or through a capacitor (AC coupling). In case of DC coupling, athreshold voltage must be set on the other pin. In case of AC coupling, the unused input pin must be terminatedto vtt. In any case, the duty cycle of the received signal can be adjusted using control inputs off0n or off0p with
input impedances of 250Ohm.
Additionally, DIP includes an input signal peak detector that generates two DC signals sldp and sldn shown in
Fig. 2a. The value of sldn represents the input data common mode voltage as shown in Fig. 2b. The difference
between sldp and sldn represents the input SE peak-to-peak swing as shown in Fig. 2c. Each single-ended
output of the peak detector has a 3.1KOhm impedance value in relation to vcc.

Rev. 2.0.2

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a.

b.

c.

Fig. 2. Simulated Peak Detector Output Signals: (a) – sldp and sldn vs. SE input swing (p-p) at vcc=3.3V, (b) – sldn vs.
input common mode voltage at vcc=3.3V, (c) – sldp-sldn vs. SE input swing (p-p) at vcc=3.3V

LCI
The Low-Speed Clock Input Buffer (LCI) is a proprietary universal input buffer (UIB) that can run at afrequency up to 1.0GHz. The input termination impedance is controlled by the CMOS signal offecl and is set to
100Ohm differential if offecl=”1” (true LVDS mode, default state) or 50Ohm single-ended to vecl if offecl=”0”(CML mode). The value of vecl should be equal to vcc in CML mode or to vcc-2V in PECL mode. In PECL
mode, the corresponding termination voltage source should be able to both sink and source up to 20mA ofcurrent. Possible input clock application schemes are detailed in Table 1, where Vcm is the common-mode
voltage of the clock signal. As can be seen, UIB is designed to accept differential signals with common mode
DC voltages between negative (vee) and positive (vcc) supply rails, as well as AC common mode noise with afrequency up to 5MHz and voltage levels from vee to vee+2.4V. It can also receive single-ended signals with athreshold voltage between vee and vcc applied to the unused pin of the differential input port.
Table 1. LS Input Clock Application Schemes

Interface Clockcep signal
cen signal
type
type Swing, mV Connection
Vcm, V
Swing, mV Connection
Vcm, V
LVDS
Diff.
70-to-500DC1.2±1.070-to-500DC1.2±1.0(offeclSE
140-to-900
AC
ThresholdDC
vee-to-vcc=”1”)
ThresholdDC
vee-to-vcc 140-to-900
AC
CML orDiff.
70-to-500
DC
vcc-Swing/2 70-to-500
DC
vcc-Swing/2
PECL
AC
AC
(offeclSE
140-to-900
AC
Not connected=”0”)
140-to-900
AC
ThresholdDC
vcc
Not connected
140-to-900
AC
ThresholdDC
140-to-900
ACvcc
Rev. 2.0.2

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The divider by 4 (/4) is used to adjust the external reference clock cr if its frequency is selected to be equal to
1/16 of the active VCO’s frequency. The divider is activated by the oncr16 control signal (oncr16=vcc) anddelivers a standard divided-by-64 reference clock to CDR FWD. In case of oncr16=vee, the reference clock isdelivered to CDR FWD, bypassing /4.

HCI
The high-speed clock input buffer (HCI) can accept external CML clock signals and provides on-chip singleended termination of 50Ohm to vcc for each input line cep or cen. A single-ended clock can be applied to oneof the differential input pins either directly (DC coupling) or through a capacitor (AC coupling). In case of DC
coupling, a threshold voltage must be set on the other pin. In case of AC coupling, the unused input pin must be
terminated to vcc.

CDR FWDThe clock and data recovery block with frequency window detector (CDR FWD) contains both phase andfrequency acquisition loops. It requires an off-chip filter shown in Fig. 3. The main function of CDR FWD is tolock the frequency of the on-chip VCO to that of the input data signal (clock recovery) while adjusting the
VCO’s clock phase to latch in the incoming data with minimal error (data recovery). The recovered clock isalso utilized by the internal divider (/16) to generate all internal timing signals.
flr1
1nF
flr2

Fig. 3. External Filter Schematic

CDR FWD assigns the 3.3V CMOS loss-of-signal flag losn=”0” when the input data’s transition density is notenough or too much. The similar loss-of-lock flag loln=”0” is generated by CDR FWD when the frequency
difference between the reference clock and the internal clock divided-by-64 exceeds ±1000ppm.

/16
The divider-by-16 (/16) includes four divide-by-2 circuits connected in series. The high-speed clock deliveredby CDR FWD is fed into the first divide-by-2 where its output is routed internally to the next divide-by-2
circuit and outside of the block to DMX1:16 through a buffering circuit. Other divided down clock signals arealso buffered and routed to DMX1:16 in a similar fashion. The clock divided-by-16 c/16 is passed on to one
LVDS OB and to CLK Proc for additional phase adjustment.

DMX1:16
The 1-to-16 demultiplexer (DMX1:16) utilizes a tree-type architecture which latches in the data stream fromCDR FWD on both edges of the half-rate clock signal that is supplied by the divider /16. The high speed data
signal is subsequently demultiplexed down and delivered to LVDS data output buffers (LVDS DOBx16) as16bit wide parallel words.

CLK Proc
By utilizing the 3.3V CMOS control pins phs1 and phs2, the phase of the main low-speed clock output signal
clo can be selected in accordance with the table below.
Rev. 2.0.2

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Table 2. Clock Phase Selection

phs1
phs2
C16 phasevee (default) vee (default)
270°
180°
vee
vcc
90°
vcc
vee
0°
vcc
vcc

LVDS DOBx16
LVDS data output buffers (LVDS DOBx16) accept 16-bit wide words from DMX1:16 and convert them into
sixteen LVDS output signals. Each proprietary low-power LVDS output buffer utilizes a special architecturethat ensures operation at bit rates up to 2Gb/s with a low power consumption level of 30mW. The buffer
satisfies all the requirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. The block also
provides a bit order selection under control of the external 3.3V CMOS signal bitordn. The first input serial bit(MSB) is assigned to q15 at bitordn=”0” (default) or to q00 at bitordn=”1”.

LVDS COB x2
The dual LVDS clock output buffer (LVDS COBx2) utilizes the same proprietary output buffers as in
DOBx16. It receives two clock signals and converts them into LVDS output signals clo and clm. The phase ofclo can be adjusted as described above.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 3 may cause damage to this product and/or
lead to reduced reliability. Functional performance is specified over the recommended operating conditions for
power supply and temperature only. AC and DC device characteristics at or beyond the absolute maximum
ratings are not assumed or implied. All min and max voltage limits are referenced to ground (assumed vee).
Table 3. Absolute Maximum Ratings

Parameter
Supply Voltage (vcc)
Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Rev. 2.0.2

Min

-40
10
10

6

Max
+3.6
1.0
1.2
+90
+100
98
98

Units
V
W
V
ºC
ºC
%
%

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TERMINAL FUNCTIONS
Name
vcc
vee
nc

Supply and Termination Voltages
Description
Pin Number
Positive power supply
5, 8, 11, 25, 26, 29, 32, 35, 38, 41, 44, 52, 55, 62,(+3.3V)65, 68, 71, 76, 79, 82, 85, 88, 91, 94, 97, 100
Negative power supply
1, 15, 23, 30, 36, 50, 51, 58, 75(GND or 0V)
Unconnected pin
42, 43, 74

TERMINAL
Name No.
Type
dp
dn
cep
cen
bitordn
loln
ftr1
ftr2
oncml
vtt
swam35swf50uswfm32
swfm13
swf20uoffcdr
off0p
off0n
losn
oncr16
phs1
phs2

Rev. 2.0.2

DESCRIPTION

High-Speed I/Os
CML differential data inputs with internal SE 50Ohm
termination to vtt
Input
CML differential clock inputs with internal SE 50Ohm
termination to vcc
Controls
16 LS In., CMOS Output bit order selection (default: low, the first serial bit(MSB) is q15; active: high, MSB is q00)
19 LS Out, CMOS CDR FWD lock indicator (high: locked; low: no lock)20
I/O
External CDR FWD filter connections
21
24 LS In., CMOS Low-speed input clock termination selection: (default: low,
LVDS; active: high, CML)
31
DC In.
Adjustable termination voltage for DIP (default: 2.5V)
2 LS In., CMOS Charge pump current selection (apd current, off by default)
14 LS In., CMOS Charge pump current selection (fwd current, off by default)
22
3759
47 LS In., CMOS Selects CDR or Digital mode of operation (default: low,
CDR; active: high, Digital)
48
DC In.,DATA IB thresholding49
53 LS Out, CMOS Input data signal quality indicator (high: good; low: notgood)
54 LS In., CMOS cr16 frequency selection (default: low, cr=C/64, active:
high, cr=C/16)
57 LS In., CMOS Low-speed output clock clo phase selection (default: both
low)
56
39
40
33
34

Input

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TERMINAL
Name No.
Type
crp
crn
q15n
q15p
q14n
q14p
q13n
q13p
q12n
q12p
q11n
q11p
q10n
q10p
q09n
q09p
q08n
q08p
q07n
q07p
q06n
q06p
q05n
q05p
q04n
q04p
q03n
q03p
q02n
q02p
q01n
q01p
q00n
q00p
clop
clon
clmp
clmn
sldp
sldn

Rev. 2.0.2

27
28
10
9
7
6
4
3
99
98
96
95
93
92
90
89
87
86
84
83
81
80
78
77
73
72
70
69
67
66
64
63
61
60
12
13
17
18
45
46

Input
OutputOutputDESCRIPTION
Low-Speed I/Os
LVDS or CML reference clock inputs for CDR FWD. Can
correspond to either C/16 or C/64
LVDS data outputs

Output

LVDS clock outputs. Can transmit four different clockphases as defined in Table 2
LVDS clock outputs

OutputPeak detector outputs

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ELECTRICAL CHARACTERISTICSPARAMETERMIN
TYP MAX
UNIT
General Parameters
+3.14
+3.3
+3.47
V
vcc
0.0
V
vee
Ivcc
270
mA
Power consumption
890
mW
Junction temperature
-25
50
125
°C
HS Input Data (dp/dn)
Data Rate
12.5
13.6
Gbps
0.0
17
Gbps
Swing (Diff or SE)
0.02
1.2
V
CM Voltage Level
vcc-0.8
vcc
V
HS Input Clock (cep/cen)Frequency
0.0
17
GHz
Swing (Diff or SE)
0.2
1.2
V
CM Voltage Level
vcc -0.8
vcc
V
Duty Cycle
40
50
60
%
LS Input Reference Clock (crp/crn)
Frequency
781
850
MHz
195
213
MHz
Swing (Diff or SE)
0.06
0.8
V
CM Voltage Level
V
vee
vcc
Duty Cycle
40
50
60
%
LS Output Data (q00p/q00n-q15p/q15n)
Data Rate
DC
1063
Mbps
Interface
LVDS

Frequency
Interface

LS Output Clocks (clmp/clmn, clop/clon)
DC
1063
MHz
LVDS

Swing (Diff)

Output of Peak Detector (sldp/sldn)
00.6
VCM Voltage Level

vcc -2.5

9±5%
External ground

In CDR mode
In digital mode
Peak-to-peakPeak-to-peak

C/16 reference
C/64 reference
Peak-to-peakMeets IEEE Std.
1596.3-1996

Meets IEEE Std.
1596.3-1996
Peak-to-peak overfull input range

V

CMOS Control Inputs/Outputs
Logic “1” levelvcc -0.4
V
Logic “0” levelvee +0.4
V
Timing Parameters
clm and clo to q0-q15±2.5%
delay variationRev. 2.0.2

COMMENTSOver the fulltemperature range
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PACKAGE INFORMATIONASNT2017
Fig. 4. Package Drawing

The chip die is housed in a custom 100-pin CQFP package shown in Fig. 4. Even though the package provides acenter heat slug located on the back side of the package to be used for heat dissipation, ADSANTEC does NOT
recommend for this section to be soldered to the board. If the customer wishes to solder it, it should beconnected to the vee plain that is ground for the positive supply.
The part’s identification label is ASNT2017-PQA. The first 8 characters of the name before the dash identify
the bare die including general circuit family, fabrication technology, specific circuit type, and part version whilethe 3 characters after the dash represent the package’s manufacturer, type, and pin out count.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

Rev. 2.0.2

10

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Offices: 310-530-9400 / Fax: 310-530-9402
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REVISION HISTORY
Revision
2.0.2
1.9.2
1.9.1

Date
05-2020
07-2019
06-20141.8.1

01-2014

1.7.1
1.6.1
1.5.1
1.4.1
1.3.1
1.2.1

07-201301-2013
12-201210-201207-201206-2012

1.1

06-20121.0

03-2011

Rev. 2.0.2

Changes
Updated Package Information
Updated Letterhead
Corrected frequency of operation in CDR mode
Corrected electrical characteristics
Corrected description
Corrected electrical characteristics
Revised package information
Corrected format
Corrected LS output data rate and output clock frequency
Corrected Electrical Specifications
Corrected Data/Clock Input frequency
Added Peak Detector description
Corrected LCI description
Added loop filter schematic
Corrected formatting
Added package pin out drawing
Corrected pin out information
Added Absolute Maximum Ratings
Revised Package Information section
First release11

May 2020