ASNT8010-PQB
17GHz Programmable Integer Divider
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Wide frequency range from DC to 17GHz.
Contiguous division ratios from 1 to 256.
50% duty cycle of the divided clock signal.
Differential or single-ended CML input interface with on-chip 50ohm termination to thepositive supply rail (“vcc”).
Differential or single-ended CML output interface with on-chip 50ohm termination to thepositive supply rail (“vcc”).
Easy 8-bit parallel programming interface compatible with LVTTL or 3.3V CMOS
standards.
Optional external reset function.
Optional dynamic mode of the division ratio adjustment with a short set-up time (about20ns after the pulse edge on any control input).
Single 2.5...3.5V power supply.
Industrial temperature range.
Current consumption of 950mA at full operational speed.
Standard 40-pin QFN package with a thermal pad.

PACKAGE DIAGRAM
Rev.: 01.

September 2008.

ASNT8010-PQB

DESCRIPTIONASNT8010-PQB is a high-speed programmable integer clock divider with static or dynamicadjustment of the division ratio through the standard 8-bit parallel LVTTL/CMOS interface andoptional external reset (active-high 3.3V CMOS/LVTTL signal). The device automatically resets
itself after the initial power-up and any change of the division control signals. When optional
external reset signal (“reset”) is set to “high”, ASNT8010-PQB switches to idle (static “0”output) after a 0.7ns delay as shown in the timing diagram below. When “reset” returns to “low”,
the divider switches back to normal operation after (64...128) periods of the high-speed system
clock plus additional 1.6ns delay. The minimum allowed “reset” pulse must not be shorter than64 periods of the high-speed system clock.
TInput ClockReset Signal
> 64T
0.7ns

(64...128)T+1.6ns

Divided Clock

The divider accepts the input clock signal (“chip/chin”) with a speed from DC to 17GHz andprovides a clean 50% duty cycle output signal (“cop/con”) in any operational mode. The utilized
input and output buffers are fully compatible with the CML interface. They feature internal
50Ohm termination to the positive supply rail (“vcc”) and support both differential (DC or AC)
and single-ended (AC) termination modes. The external transmission media can be a printed
circuit board or copper coaxial cables with a 50Ohm impedance.
The divider allows for both static and dynamic adjustment of the division ratio from 1 to256 with a step of 1. In the static mode, the binary code on the control inputs “C0”-“C7” defines
the value of the ratio from 1 to 255, where “C7” is the most significant bit. All “0”s (“low” state)define the division by 256. Following any change of a control signal in the dynamic mode, thedivider switches to idle after (64...128) periods of the high-speed system clock plus additional
1.6ns delay, and returns back to normal operation with the new division ratio after additional
delay equal to 192 periods of the high-speed system clock.
The chip uses a positive 3.3V power supply with “vee” as a ground node and ischaracterized for operation at −25°C to 125°C of junction temperatures. It can also operate froma negative 3.3V supply voltage with “vcc” as a ground node and the appropriate correction of thecontrol signals.
The device is packaged into a standard 40-pin QFN plastic package with a bottom
thermal pad.

APPLICATIONASNT8010-PQB can be used as a general-purpose reprogrammable divider in a variety of highfrequency synthesizer applications. It is particularly suitable for the advanced measurement
equipment.
Rev.: 01.

September 2008.

ASNT8010-PQB

PIN-OUT
Pin # Name
Function
Pin # Name
Function
1vee
Negative supply node21
vee
Negative supply node2
vee
Negative supply node
22
C7
Division control (MSB)
3vee
Negative supply node
23
C6
Division control
4vcc
Positive supply node
24
C5
Division control
5clkipDirect clock input
25
C4
Division control
6vcc
Positive supply node
26vcc
Positive supply node
7clkinInverted clock input
27
C3
Division control
8vcc
Positive supply node28
C2
Division control
9dec 47nF external capacitor to vee 29
C1
Division control
10vee
Negative supply node30
C0
Division control (LSB)
11vee
Negative supply node31
vee
Negative supply node
12vee
Negative supply node32
resExternal reset input
13vcc
Positive supply node33
n/c
Keep open!
14vcc
Positive supply node34
vcc
Positive supply node
15
clkon Inverted divided clock output
35
n/c
Keep open!
16
vcc
Positive supply node36
vcc
Positive supply node17
clkop
Direct divided clock output
37
n/c
Keep open!
18
vcc
Positive supply node38
vcc
Positive supply node19
n/c
Keep open!
39
n/c
Keep open!
20
vee
Negative supply node40
vee
Negative supply node

PCB DESIGN RECOMMIDATIONS
1.
2.
3.
4.

The divider requires a 50Ohm impedance environment for clock input and output signals.
Pins No. 19, 33, 35, 37, and 39 must be kept OPEN (not connected)!
One external capacitor of 47nF must be inserted between pin No. 9 and the ground plane.
Additional heat sink is recommended for the reliable operation.

PACKAGE INFORMATIONThe chip is packaged in a standard 40-pin QFN package. The package’s mechanical information
is available on the company’s website.

Rev.: 01.

September 2008.

ASNT8010-PQB