Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT1121-KMM
DC-50Gbps Broadband Digital 4:1 Multiplexer

Differential CML I/O data and clock buffersQuarter-rate clock output

Single +3.3V or -3.3V power supplyPower consumption: 960mWFabricated in SiGe for high performance, yield, and reliability

Custom CQFP 44-pin package

vcc
veevccd1p
vcc
d1nvccvcc
n/cvccqp

ASNT1123-KMM
ASNT1121

d2pvccd2n
vcc

vcc
qn
vcc

1

cepvcccenvcc

vcc
d3n
vcc

n/c
vcc
vee
vcc

vcc
veevccd3p

Rev. 1.8.2

vee
vcc

Exhibits low jitter and limited temperature variation over industrial temperature range

vcc
c4op
vcc

d0n
vcc
d0p
vcc
c4on

High speed broadband 4:1 Multiplexer (MUX)

vcc



January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
vcc
d0p
d0n
d1p
d1nvccqp
qn

d2p
d2n
d3pd3nvcc
cepcenDIV

c4op
c4onFig. 1. Functional Block Diagram

The ASNT1121-KMM SiGe IC is a low power and high-speed digital 4-to-1 serializer-multiplexer(MUX) that functions seamlessly over data rates (fbit) ranging from DC to its maximum frequency.
The main function of the part shown in Fig. 1 is to multiplex 4 parallel differential CML data signals
d0p/d0n, d1p/d1n, d2p/d2n, d3p/d3n running at a bit rate of fbit/4 into a high speed serial bit streamqp/qn running at a bit rate of fbit. Differential or single-ended full-rate clock cep/cen must be provided by
an external source for the part to function properly.
The serialized data words qp/qn and the clock divided-by-4 signal c4op/c4on are transmitted through
CML output interfaces. The clock and data outputs are phase-matched to each other resulting in a very
little relative skew over the operating temperature range of the device.
The part’s I/O’s support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.

POWER SUPPLY CONFIGURATION
The part can operate with either negative supply (vcc = 0.0V = ground and vee = −3.3V), or positive
supply (vcc = +3.3V and vee = 0.0V = ground). In case of the positive supply, all I/Os need AC
termination when connected to any devices with 50Ohm termination to ground. Different PCB layouts
will be needed for each different power supply combination.
Rev. 1.8.2

2January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.

ABSOLUTE MAXIMUM RATINGSCaution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground.
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Rev. 1.8.2

Min-4010103Max-3.6
1.1
1.4+100+1009898UnitsVWVºCºC%%January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

TERMINAL FUNCTIONSTERMINAL
Name
No.
Typed0p
d0n
d1p
d1n
d2p
d2n
d3p
d3n
c4op
c4on
cepcen
qp
qn
Name
vcc
veen/cRev. 1.8.2

DESCRIPTION

Low-Speed I/Os
Differential quarter-rate data inputs with internal SE 50Ohm
termination to vccDifferential quarter-rate data inputs with internal SE 50Ohm
termination to vcc
Differential quarter-rate data inputs with internal SE 50Ohm
termination to vcc
Differential quarter-rate data inputs with internal SE 50Ohm
termination to vcc
Differential quater-rate clock outputs with internal SE 50Ohm
termination to vcc. Require external SE 50Ohm termination to vcc
High-Speed I/Os
8
CML Differential full-rate clock input signals with internal 50Ohm
input termination to vcc
1019
CML Differential full-rate data outputs with internal SE 50Ohm
output termination to vcc. Require external SE 50Ohm termination to vcc
17
Supply and Termination Voltages
Description
Pin Number
Positive power supply
1, 3, 5, 7, 9, 11, 12, 14, 16, 18, 20, 22, 23, 25, 27, 29,(+3.3V or 0)
31, 33, 34, 36, 38, 40, 42, 44
Negative power supply
2, 13, 24, 35(0V or -3.3V)
Not connected pins
15, 21
30
32
37
39
41
43
4
626
28

CML
input
CML
input
CML
input
CML
input
CML
output4January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERMINTYP MAX UNIT
COMMENTS
General Parameters-3.1-3.3-3.5
V±6%vee0.0
VExternal ground
vcc
Ivee
290mA
Power consumption
960
mW
Junction temperature -40
25125°C
LS Input Data (d0p/d0n, d1p/d1n, d2p/d2n, d3p/d3n)
Data Rate
DC10
12.5
Gbps
Swing
0.20.8V
Differential or SE, p-p
CM Voltage Level
vcc-0.8
vcc
VMust match for both inputs
HS Input Clock (cep/cen)Frequency
DC4050GHzSwing
0.20.8V
Differential or SE, p-p
CM Voltage Level
vcc-0.8vcc
VMust match for both inputs
Duty Cycle
405060%HS Output Data (qp/qn)
Data Rate
DC
4050Gb/s
Logic “1” level
Vvcc
Logic “0” levelvcc-0.6
V
With external 50Ohm DC termination
Output Jitter3
ps
Peak-to-peak at 40Gb/s
LS Output Clock (c4op/c4on)
Frequency
DC1012.5
GHz
Logic “1” level
Vvcc
Logic “0” levelvcc-0.6
V
With external 50Ohm DC termination
Duty Cycle
50%
Output Jitter2ps
Peak-to-peak at 10GHz

PACKAGE INFORMATIONThe chip die is housed in a custom 44-pin CQFP package shown in Fig. 2. The package provides a center
heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for thissection to be soldered to the vcc plain, which is ground for a negative supply, or power for a positive
supply.
The part’s identification label is ASNT1121-KMM. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.

Rev. 1.8.2

5January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

Fig. 2. CQFP 44-Pin Package Drawing (All Dimensions in mm)

Rev. 1.8.2

6January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.8.2
1.7.2
1.7.1
1.6.1
1.5.1

Date01-2020
07-2019
05-2019
05-2015
02-2013

1.4.1

01-2013

1.3.1
1.3
1.2

12-2011
11-201105-20111.101-2011

1.0

12-2010

Rev. 1.8.2

Changes
Updated Package Information
Updated Letterhead
Corrected cep/cen description in Terminal Function table
Updated Package Information section
Title correction
Corrected description
Corrected Terminal Functions table
Corrected Electrical Characteristics
Updated Package Information
Corrected block diagram
Updated Package Information
Updated Description
Format Correction
Corrected Terminal Functions table
Added Absolute Maximums Rating table
Added packaging information
Added RoHS compliancy
Added revision history table
First release

7

January 2020