Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT1011-PQA
DC-to-16Gbps Digital Multiplexer 16:1 / Serializer
Broadband digital serializer 16-to-1
LVDS compliant input data buffers
Full-rate clock output
Clock-divided-by-16 LVDS output buffer with 90°-step phase selection
Single +3.3V power supply
Industrial temperature range
Low power consumption of 660mW at the maximum speed
Custom 100-pin QFN package (12mm x 12mm)
vccncveevcc
d03nd03p
vcc
d02n
d02p
vcc
d01n
d01p
vcc
d00n
d00p
vcc
nc
vee
phs1
phs2
vcc
nc
nc
vcc
vee









ASNT1011

vee
vcc
clop
clon
nc
vcc
vcc
qcmlp
qcmln
vcc
vcc
vcc
vcc
chop
chon
vcc
vcc
vcc
vcc
cep
cen
vcc
vee
vee
vcc

vcc
nc
vee
nc
d13p
d13n
vcc
d14p
d14n
vcc
d15p
d15n
vcc
nc
nc
vcc
vee
vee
vee
offcho
nc
nc
nc
vee
vee

d04p
d04n
vcc
d05p
d05n
vcc
d06p
d06n
vcc
d07pd07n
vcc
d08p
d08n
d09p
d09n
vcc
q10p
d10n
vcc
d11p
d11n
vcc
d12p
d12n

Rev. 2.2.21May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION

d00

LS
DIB
x16

16

MUX
16:1

Data
OBqcml

LVDS
COB

clo

HS
COB

cho

d15

CLK
Proc

C16/16

ce

HS
CIB

C

phs1
phs2
Fig. 1. Functional Block Diagram

ASNT1011-KMA is a low power and high-speed digital 16-to-1 multiplexer (MUX) / serializer. The IC shownin Fig. 1 functions seamlessly over data rates (fbit) ranging from DC to the specified maximum value.
The main function of the IC is to multiplex 16 parallel data channels running at a bit rate of fbit/16 into a highspeed serial bit stream running at fbit. It provides a high-speed output data channel for point-to-point datatransmission over a controlled impedance media of 50Ohm. The transmission media can be a printed circuitboard or copper coaxial cables. The functional distance of the data transfer is dependent upon the attenuationcharacteristics of the transportation media and the degree of noise coupling to the signaling environment.
During normal operation, the serializer’s low-speed input buffer (LS DIBx16) accepts external 16-bit wide
parallel data words d00-d15 through 16 differential LVDS inputs and delivers them to the multiplexer’s core
(MUX16:1) for serialization. A full rate clock must be provided by an external source (ce) to the high-speed
clock input buffer (HS CIB) where it is routed to the high speed clock output buffer (HS COB) and the internal
divider-by-16 (/16). The divider provides signaling for MUX16:1 and produces a full rate clock divided-by-16
C16 for the low speed LVDS compliant clock output buffer (LVDS COB).The phase of clo can be modified by90° increments by utilizing pins phs1 and phs2 and the clock processing block (CLK Proc).
Rev. 2.2.2

2May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

The serialized words are transmitted as 2-level signals qcml by a differential CML output buffer (Data OB). A
full-rate clock is transmitted by HS COB in parallel with the high-speed data. The clock and data outputs arewell phase matched to each other resulting in very little relative skew over the operating temperature range ofthe device. Both output stages are back terminated with on-chip 50Ohm resistors.
The serializer uses a single +3.3V power supply and is characterized for operation from −25°C to 125°C ofjunction temperature.

LS DIBx16
The Low-Speed Data Input Buffer (LS DIBx16) consists of 16 proprietary universal input buffers (UIBs) thatexceed the LVDS standards IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. UIB is designed to accept
differential signals with amplitudes above 60mV peak-to-peak (p-p), DC common mode voltage variation
between the negative (vee) and positive (vcc) supply rails, and AC common mode noise with a frequency up to5MHz and voltage levels ranging from 0 to 2.4V. It can also receive single-ended signals with amplitudes above
60mVp-p and threshold voltages between vee and vcc. The input termination impedance is set to 100Ohmdifferential.

HS CIBThe High-Speed Clock Input Buffer (HS CIB) can accept high-speed clock signals at its differential CML input
port cep/cen. It can also accept a single-ended signal with a threshold voltage applied to the unused pin. HSCIB can handle a wide range of input signal amplitudes. The buffer utilizes on-chip single-ended termination of
50Ohm to vcc for each input line.

/16
The Divider-by-16 (/16) includes 4 divide-by-2 circuits connected in series. The high-speed clock C is fed into
the first divide-by-2 circuit that generates half rate clock C2. C2 is routed internally to the next divide-by-two
circuit and outside of the block to MUX16:1. Other divided down clock signals are formed and routed toMUX16:1 in similar fashion. C16 is passed on to LVDS COB to become the output low speed clock signal clo.

MUX16:1
The 16 to 1 Multiplexer (MUX16:1) utilizes a tree type architecture that latches the incoming data on thenegative edge of the C16 clock signal that is supplied by the divider. The 16-bit wide data word is subsequently
multiplexed and delivered to Data OB as a single serial data stream running at a data rate up to 17Gbps. The
latency of this circuit block is equal to roughly one period of C16. The input MSB corresponds to d00.

Data OBThe Data Output Buffer (Data OB) receives high-speed serial data from MUX16:1 and converts it into
differential CML output signal qcmlp/qcmln. The buffer requires 50Ohm external termination resistors
connected between vcc and each output to match its internal 50Ohm resistors.

HS COBThe High Speed Clock Output Buffer (HS COB) utilizes the same termination scheme as Data OB. The buffer
can be enabled or disabled by the external 2-state control signal offcho. The logic “0” state provides a full-rate
clock output signal while the logic “1” state disables the buffer completely to save power.
Rev. 2.2.2

3May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

CLK Proc
By utilizing the CMOS control pins phs1 and phs2, the phase of clo can be altered in accordance with Table 1.
Table 1. Output Clock Phase Selection

phs1
phs2
C16 phasevee (default) vee (default)
270°
vee
vcc
180°
vcc
vee
90°
vcc
vcc
0°

LVDS COB
The LVDS Clock Output Buffer (LVDS COB) receives C16 and converts it into an LVDS output signal clo.
The proprietary low-power LVDS output buffer utilizes a special architecture that ensures operation at
frequencies up to 2.0GHz with a nominal output current of 3.5mA. The buffer satisfies all the requirements of
the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995.

Output Timing
The phase relation between the output data qcml and the full rate output clock cho is specified in Table 2 andillustrated by Fig. 2.
Table 2. Output Data-to-Clock Phase Difference

Junction temperature,
τ,psºC
Min. Max.
-25
77
80
50
82
86
125
87
91

clk edge
Output
Data

τ

Tclk
Fig. 2. Output Timing Diagram

Rev. 2.2.2

4May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 3 may cause damage to this product and/or
lead to reduced reliability. Functional performance is specified over the recommended operating conditions for
power supply and temperature only. AC and DC device characteristics at or beyond the absolute maximum
ratings are not assumed or implied. All min and max voltage limits are referenced to ground (assumed vee).
Table 3. Absolute Maximum Ratings

Parameter
Supply Voltage (vcc)
Power Consumption
RF Input Voltage Swing (SE)
Case TemperatureStorage Temperature
Operational Humidity
Storage Humidity

Min-401010Max+3.60.72
1.0+90+1009898

UnitsVWVºCºC%%TERMINAL FUNCTIONS
Namevccveenc

Supply And Termination Voltages
Description
Pin Number
Positive power
1, 4, 7, 10, 13, 16, 26, 29, 32-35, 38-41, 44, 45, 49, 52,
supply. (+3.3V)
55, 60, 63, 66, 69, 72, 75, 78, 81, 84, 87, 92, 95, 98.
Negative power
3, 17-19, 24, 25, 27, 28, 50, 51, 58, 73.
supply. (GND or 0V)
Not connected pins.
2, 14, 15, 21-23, 46, 53, 54, 59, 74.

TERMINAL
NameNo.
Typecepcenchopchon
qcmlp
qcmln
phs1
phs2
offchoRev. 2.2.2

DESCRIPTION

High-Speed I/Os
31 Input
CML differential external clock inputs with internal SE
50Ohm termination to vcc.
30
37 Output CML differential clock outputs. Require external SE 50Ohm
termination to vcc.
36
43 Output CML differential data outputs. Require external SE 50Ohm
termination to vcc.
42Controls
57 LS In., Low-speed output clock phase selection (default: both low).
56 CMOS20 LS In., HS COB control (active: high, buffer is disabled; default: low,
CMOS full-rate output clock).

5May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

TERMINAL
Name
No.
Typeclop
clon
d00p
d00n
d01p
d01n
d02p
d02n
d03p
d03n
d04p
d04n
d05p
d05n
d06p
d06n
d07p
d07n
d08p
d08n
d09p
d09n
d10p
d10n
d11p
d11n
d12p
d12n
d13p
d13n
d14p
d14n
d15p
d15n

Rev. 2.2.2

DESCRIPTION

Low-Speed I/Os48 Output LVDS clock outputs. Can transmit four different clock phases
as defined by phs1 and phs2.
4761 Input LVDS data inputs.
62646567
68707176
77
7980
82
83
85
86
88
899091
93
9496
97
99
100
568911126May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERvcc
veeIvcc
Power consumption
Junction temperature
Data Rate
Differential Swing
CM Voltage LevelFrequencySwing (Diff or SE)
CM Voltage Level
Duty Cycle
Data Rate
Logic “1” level
Logic “0” level
JitterFrequency
Logic “1” level
Logic “0” level
JitterDuty Cycle
Frequency
Interface
Logic “1” level
Logic “0” level

Rev. 2.2.2

MIN

TYP
MAX
UNIT
COMMENTS
General Parameters+3.14+3.3+3.47
V
±5%
0.0
V
External ground
200mA
660mW
-2550125°C
LS Input Data (dXXp, dXXn)
0.0
1000
Mbps
0.06
0.8
V
Peak-to-peak
Vveevcc
HS Input Clock (cep, cen)0.016GHz
0.2
1.2
V
Peak-to-peakvcc-0.8
vcc
V
40
5060%
HS Output Data (qcmlp, qcmln)
0.0
16
Gbps
Vvcc
vcc-0.6
V12
ps
Peak-to-peak @12.5Gb/s
HS Output Clock (chop, chon)
0.0
16
GHzV
vcc
vcc-0.6
V6
ps
Peak-to-peak @12.5GHz
50%
LS Output Clock (clop, clon)
0.0
1000
MHzLVDS
Meets the IEEE Std.
CMOS Control Inputs
vcc-0.4
V
vee+0.4
V

7May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATIONThe chip die is housed in a custom 100-pin QFN package shown in Fig. 3. Additional package’s mechanicalinformation is available on the company’s website.

ASNT1011
Fig. 3. Package Drawing

Even though the package provides a center heat slug located on the back side of the package to be used for heatdissipation, ADSANTEC does NOT recommend for this section to be soldered to the board. If the customer
wishes to solder it, it should be connected to vcc plain that is power for the positive supply.
The part’s identification label is ASNT1011-PQA. The first 8 characters of the name before the dash identify
the bare die including general circuit family, fabrication technology, specific circuit type, and part version whilethe 3 characters after the dash represent the package’s manufacturer, type, and pin out count.
This device complies with the Restriction of Hazardous Substances (RoHS) per EU 2002/95/EC for all six
substances.
Rev. 2.2.2

8May 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
2.2.2

Date05-2020

2.1.1
2.007-2019
06-20121.009-2008

Rev. 2.2.2

Changes
Updated Package information
Corrected format
Updated Letterhead
Revised Electrical Characteristics section.
Corrected Terminal Functions.
Revised Package Information section.
Added Absolute Maximums Rating table.
Added Pin Diagram.
First release.

9May 2020