S-82K5B Series
BATTERY MONITORING IC
FOR 3-SERIAL TO 5-SERIAL CELL PACK(SECONDARY PROTECTION)

www.ablic.com© ABLIC Inc., 2024

Rev.1.1_00

This IC is used for secondary protection of lithium-ion rechargeable batteries, incorporating high-accuracy voltage detection
circuits and delay circuits in a small 8-pin package.
Short-circuiting between cells makes it possible for serial connection of 3-cell to 5-cell.
By cascade connection of these ICs, it is possible to protect 6-serial or more cells lithium-ion rechargeable battery packs.

 Features● High-accuracy voltage detection circuit for each cell
Overcharge detection voltage n
3.500 V to 4.700 V (5 mV steps)

Accuracy ±20 mV (Ta = +25°C)
Accuracy ±25 mV (Ta = −10°C to +60°C)
Overcharge release voltage n*1
3.100 V to 4.700 V
Accuracy ±50 mV● Delay times for overcharge detection are generated only by an internal circuit (external capacitors are unnecessary)
Overcharge detection delay time:
0.5 s, 1 s, 2 s, 4 s, 6 s, 8 s● CO pin output voltage is limited to 7.5 V max.
• Overcharge timer reset function:
Available, unavailable● High withstand voltage:
Absolute maximum rating 28 V
● Wide operating voltage range:
3.6 V to 24 V
● Wide operating temperature range:
Ta = −40°C to +85°C● Low current consumption
During operation (3.4 V for each cell): 5.0 μA max.
● Lead-free (Sn 100%), halogen-free*1. Overcharge release voltage = Overcharge detection voltage - Overcharge hysteresis voltage(Overcharge hysteresis voltage can be selected from a range of 0 mV to 400 mV in 50 mV step.)
Remarkn = 1, 2, 3, 4, 5

 Applications● Lithium-ion rechargeable battery pack

 Packages● TMSOP-8● SNT-8A

1

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-82K5B Series
Rev.1.1_00
 Block Diagram

VDD

Overcharge
detection comparator 1

CO pin output voltage
limit circuit

VC1

VC2

Overcharge
detection comparator 2COOvercharge
detection comparator 3
Control logic
Delay circuit
Oscillator

VC3

VC4

Overcharge
detection comparator 4

Overcharge
detection comparator 5

VSS

RemarkDiodes in the figure are parasitic diodes.
Figure 1

2

CTLC

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.1_00
S-82K5B Series
 Product Name Structure
1.

Product name
S-82K5B xx - xxxx U

Environmental codeU:
Lead-free (Sn 100%), halogen-free

Package abbreviation and IC packing specifications*1
K8T2: TMSOP-8, Tape
I8T1: SNT-8A, Tape

Serial code*2
Sequentially set from AA to ZZ*1. Refer to the tape drawing.
*2. Refer to "3. Product name list".

2.

Packages
Table 1 Package Drawing Codes

Package NameTMSOP-8
SNT-8A

3.

Dimension
FM008-A-P-SD
PH008-A-P-SD

Tape
FM008-A-C-SD
PH008-A-C-SD

Reel
FM008-A-R-SD
PH008-A-R-SD

Land−
PH008-A-L-SD

Product name list
3. 1

TMSOP-8
Table 2

Product Name
S-82K5BAA-K8T2U

Overcharge Detection
Voltage[VCU]
4.275 V

*1. Overcharge detection delay time:*2. Overcharge timer reset function:
Remark
3. 2

Overcharge Release
Voltage[VCL]
4.225 V

Overcharge Detection
Delay Time*1
[tCU]
2.0 s

Overcharge Timer
Reset function*2
Available

0.5 s, 1 s, 2 s, 4 s, 6 s, 8 s
Available, unavailable

Please contact our sales representatives for products other than the above.
SNT-8A
Table 3

Product Name
S-82K5BAA-I8T1UOvercharge Detection
Voltage[VCU]
4.275 V

*1. Overcharge detection delay time:*2. Overcharge timer reset function:
RemarkOvercharge Release
Voltage[VCL]
4.225 V

Overcharge Detection
Delay Time*1
[tCU]
2.0 s

Overcharge Timer
Reset function*2
Available

0.5 s, 1 s, 2 s, 4 s, 6 s, 8 s
Available, unavailable

Please contact our sales representatives for products other than the above.
3

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-82K5B Series
Rev.1.1_00
 Pin Configuration
1.

TMSOP-8
Table 4Top view

Pin No.

1
2
3
4

8
7
6
5
Figure 2

2.

Symbol

1

VDD

2

VC1

3

VC2

4

VC3

5

VC4

6

VSS

7
8

CTLC
CO

Description
Positive power supply input pin,
Positive voltage connection pin of battery 1
Negative voltage connection pin of battery 1,
Positive voltage connection pin of battery 2
Negative voltage connection pin of battery 2,
Positive voltage connection pin of battery 3
Negative voltage connection pin of battery 3,
Positive voltage connection pin of battery 4
Negative voltage connection pin of battery 4,
Positive voltage connection pin of battery 5
Negative power supply input pin,
Negative voltage connection pin of battery 5
CO control pin
Overcharge detection output pin

SNT-8A
Table 5Top view
1
2
3
4

8
7
6
5
Figure 3

4

Pin No.

Symbol

1

VDD

2

VC1

3

VC2

4

VC3

5

VC4

6

VSS

7
8

CTLC
CO

Description
Positive power supply input pin,
Positive voltage connection pin of battery 1
Negative voltage connection pin of battery 1,
Positive voltage connection pin of battery 2
Negative voltage connection pin of battery 2,
Positive voltage connection pin of battery 3
Negative voltage connection pin of battery 3,
Positive voltage connection pin of battery 4
Negative voltage connection pin of battery 4,
Positive voltage connection pin of battery 5
Negative power supply input pin,
Negative voltage connection pin of battery 5
CO control pin
Overcharge detection output pin

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.1_00
S-82K5B Series
 Absolute Maximum Ratings
Table 6
(Ta = +25°C unless otherwise specified)
Item
Input voltage between VDD pin and VSS pin

Input pin voltage

Output pin voltage
Operation ambient temperature
Storage temperature
CautionSymbolVDS

Applied Pin
VDD

VIN1

VC1

VIN2

VC2

VIN3

VC3

VIN4

VC4

VIN5
VOUT
Topr
Tstg

CTLC
CO
−
−

Absolute Maximum Rating
VSS − 0.3 to VSS + 28
VDD − 6.0 to VDD + 0.3,
VIN2 − 0.3 to VIN2 + 6.0
VIN3 − 0.3 to VIN3 + 6.0,
VIN3 − 0.3 to VDD + 0.3
VIN4 − 0.3 to VIN4 + 6.0,
VIN4 − 0.3 to VDD + 0.3
VSS − 0.3 to VSS + 6.0,
VSS − 0.3 to VDD + 0.3
VSS − 0.3 to VSS + 28
VSS − 0.3 to VDD + 0.3−40 to +85−40 to +125

Unit
V
V
V
V
V
V
V
°C
°C

The absolute maximum ratings are rated values exceeding which the product could suffer physicaldamage. These values must therefore not be exceeded under any conditions.

 Thermal Resistance
Table 7
Items

SymbolCondition

TMSOP-8Junction-to-ambient thermal resistance*1 θJA
SNT-8A

Board A
Board B
Board C
Board D
Board E
Board A
Board B
Board C
Board D
Board E

Min.
−
−
−
−
−
−
−
−
−
−

Typ.
160
133
−
−
−
211
173
−
−
−

Max.
−
−
−
−
−
−
−
−
−
−

Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W

*1. Test environment: compliance with JEDEC STANDARD JESD51-2A
RemarkRefer to " Power Dissipation" and "Test Board" for details.

5

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-82K5B Series
Rev.1.1_00
 Electrical Characteristics
Table 8(Ta = +25°C unless otherwise specified)
Item

SymbolCondition

Min.

Typ.

Max.

Unit

Test
Circuit

V

1

V

1

V

2

Detection Voltage
Overcharge detection voltage n(n = 1, 2, 3, 4, 5)

V1 = V2 = V3 = V4 = V5 = VCU − 0.1 V
VCUn

Ta = −10°C to +60°C*1,
V1 = V2 = V3 = V4 = V5 = VCU − 0.1 V

Overcharge release voltage n
VCLn(n = 1, 2, 3, 4, 5)
Input voltage
Operation voltage between VDD
VDSOP
pin and VSS pin
Output Voltage
CO pin voltage "H"
VCOH
Input Current

−

VCU −
0.020
VCU −
0.025
VCL −
0.050

VCU
VCU
VCL

VCU +
0.020
VCU +
0.025
VCL +
0.050

−

3.6

−

24

V

−

−

5.0

6.0

7.5

V

2

−

2.0

5.0

μA

2

−1.0

0

1.0

μA

2

V1 = V2 = V3 = V4 = V5 = 3.4 V,
SW1 ON, SW2 OFF, SW3 OFF,SW4 OFF, SW5 OFF
V1 = V2 = V3 = V4 = V5 = 3.4 V,
SW1 ON, SW2 OFF, SW3 OFF,SW4 OFF, SW5 OFF

Current consumption during
operation

IOPE

VCn pin current(n = 1, 2, 3, 4)

IVCn

Output current
CO pin sink current
CO pin source current
Delay Time

ICOL
ICOH

−
−

20
−

−
−

−
−20

μA
μA

2
2

Overcharge detection delay time tCU

−

tCU ×
0.7

tCU

tCU ×
1.3

−

2

Overcharge timer reset delay
−
tTR
6
12
20
ms
2
time
Control Pin−
CTLC pin reverse voltage
VCTLC
0.2
0.7
2.0
V
2
VDS +
VDS +
5.1 MΩ resistor connected to the VDS +CTLC pin reverse voltage during
VCTLC_C
V2
communication
0.2
1.2
2.5
CTLC pin−−μA
CTLC pin curent "H"
ICTLCH
0.1
0.3
2
−
−0.1
μA
CTLC pin curent "L"
ICTLCL
0.0
0.1
2*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteedby design, not tested in production.

6

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.1_00
S-82K5B Series
 Test Circuits
In the initial status of the test circuit, SW2, SW3, SW4, and SW5 should be OFF.

1.

Overcharge detection voltage n (VCUn)(Test circuit 1)
After setting V1 = V2 = V3 = V4 = V5 = VCU − 0.1 V, V1 is gradually increased. When the CO pin output inverts, thevoltage V1 is defined as the overcharge detection voltage 1 (VCU1). Other overcharge detection voltage n (VCUn) can be
determined in the same way as when n = 1.

2.

Overcharge release voltage n (VCLn)(Test circuit 2)
Set SW1 to ON, V1 = VCU + 0.1 V, and V2 = V3 = V4 = V5 = VCL − 0.1 V to invert the CO pin output. After that, V1 isgradually decreased. When the CO pin output inverts again, the voltage V1 is defined as the overcharge release voltage(VCL1). Other overcharge release voltage n (VCLn) can be determined in the same way as when n = 1.

Remark3.

n = 1, 2, 3, 4, 5

CO pin output voltage "H" (VCOH)(Test circuit 2)
The CO pin output voltage "H" (VCOH) is the voltage between the CO pin and the VSS pin when setting SW1 to ON, V1= 4.8 V, V2 = V3 = V4 = V5 = 3.05 V, I1 = 0.1 μA, and SW5 to ON.

4.

CO pin source current (ICOH), CO pin sink current (ICOL)(Test circuit 2)
Set SW4 to ON after setting SW1 to ON, V1 = 4.8 V, V2 = V3 = V4 = V5 = 3.05 V, and V7 = VCOH − 0.5 V. The CO pin
current is the CO pin source current (ICOH) at that time.
Set SW4 to ON after setting SW1 to ON, V1 = V2 = V3 = V4 = V5 = 3.4 V, and V7 = 0.5 V. The CO pin current is the CO
pin sink current (ICOL) at that time.

5.

Overcharge detection delay time (tCU)(Test circuit 2)
After setting SW1 to ON, V5 = VCU − 0.2 V, and V1 = V2 = V3 = V4 = 3.4 V, V5 is increased to VCU + 0.2 V. The overcharge
detection delay time (tCU) is the time period until the CO pin output inverts.

6.

CTLC pin reverse voltage (VCTLC)(Test circuit 2)
Set SW2 to ON after setting SW1 to OFF, V1 = V2 = V3 = V4 = V5 = 3.4 V, and V6 = 17 V. When the voltage V6 isgradually decreased and the CO pin output inverts, V6 is defined as the CTLC pin reverse voltage (VCTLC).

7.

CTLC pin reverse voltage during communication (VCTLC_C)(Test circuit 2)
Set SW3 to ON after setting SW1 to OFF, V1 = V2 = V3 = V4 = V5 = 3.4 V, and V6 = 17 V. When the voltage V6 isgradually increased and the CO pin output inverts, V6 is defined as the CTLC pin reverse voltage during communication(VCTLC_C).

8.

Current consumption during operation (IOPE)(Test circuit 2)
Set SW1 to ON and V1 = V2 = V3 = V4 = V5 = 3.4 V. The current consumption during operation (IOPE) is IVDD at that time.

7

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-82K5B Series
Rev.1.1_00
9.

Overcharge timer reset delay time (tTR)(Test circuit 2)
Increase V1 up to 5.0 V (first rise) after setting SW1 to ON and V1 = V2 = V3 = V4 = V5 = 3.4 V, and decrease V1 down
to 3.4 V within tCU. After that, increase V1 up to 5.0 V again (second rise), and detect the time period till the CO pin output
changes.
When the period from when V1 has fallen to the second rise is short, CO pin output changes after tCU has elapsed since
the first rise. If the period is gradually made longer, CO pin output changes after tCU has elapsed since the second rise.
The overcharge timer reset delay time (tTR) is the period from V1 fall till the second rise at that time.

10. CTLC pin current "H" (ICTLCH), CTLC pin current "L" (ICTLCL)(Test circuit 2)
Set SW1 to OFF, SW2 to ON, V1 = V2 = V3 = V4 = V5 = 3.4 V, and V6 = 17 V. The CTCL pin current is the CTLC pin
current "H" (ICTLCH) at that time.
Set SW1 to OFF, SW2 to ON, V1 = V2 = V3 = V4 = V5 = 3.4 V, and V6 = 0 V. The CTLC pin current is the CTLC pin
current "L" (ICTLCL) at that time.

8

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.1_00
S-82K5B Series

V1
V2
V3

100 Ω

1 μF

1 kΩ
1 μF
1 kΩ

1 μF

1 kΩ
V4

V5

1 VDD

CO 8

2 VC1

CTLC 7

3 VC2

VSS 6

4 VC3

VC4 5
V

1 μF
1 kΩ
1 μF

Figure 4 Test Circuit 1

SW1

A

1 VDD

CO 8

A

A

2 VC1

CTLC 7

A

A

3 VC2

VSS 6

4 VC3

VC4 5

V1
V2
SW2

V3
A

V4

A

SW5
SW3

SW4

5.1 MΩ
V

V7

V

V6

I1

V5

Figure 5 Test Circuit 2

9BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-82K5B Series
Rev.1.1_00
 Operation
1.

Normal status
When the voltage of all batteries is less than or equal to the overcharge detection voltage n (VCUn), the CO pin outputs"L". This status is called the normal status.

2.

Overcharge status
When the voltage of any of the batteries exceeds the overcharge detection voltage n (VCUn) during charging and thiscondition continues for the overcharge detection delay time (tCU) or longer, the CO pin output inverts. This status is called
the overcharge status.
When the voltage of all batteries falls below the overcharge release voltage n (VCLn), the overcharge status is released,
and this IC returns to its normal status.

3.

Overcharge timer reset function
During tCU, which is from when the voltage of any of the batteries being charged exceeds VCUn until charging stops, thisIC has the following operations.
Even if an overcharge release noise, which temporarily forces the battery voltage below VCUn, is input, tCU is continuously
counted as long as the overcharge release noise time is shorter than the overcharge timer reset delay time (tTR). Under
the same conditions, if the overcharge release noise time is tTR or longer, counting of tCU is reset once. After that, when
VCUn has been exceeded, counting of tCU resumes.
Remark4.

n = 1, 2, 3, 4, 5

CTLC pin
The CTLC pin controls the CO pin. These controls precede the battery protection circuit.
Table 9 Status Set by CTLC Pin
CTLC Pin
CO pin
VSS level ≤ CTLC pin voltage < VCTLC
VCTLC ≤ CTLC pin voltage < VDD level
VDD level ≤ CTLC pin voltage < VCTLC_C
VCTLC_C ≤ CTLC pin voltage

"H"
"L"
"L"
"H"

Remark The CTLC pin is at the VDD level or higher in cascade connection. Connect a resistor of 5.1 MΩ to the CTLC
pin in this case.
VCTLC:
CTLC pin reverse voltage
VCTLC_C:
CTLC pin reverse voltage during communication

5.

VCn pin
The VCn pin is connected to a constant current circuit. When the connection between the battery and the IC is
disconnected, pulling up/down the VCn pin using this constant current circuit enables disconnection detection.
However, this disconnection detection may not work properly due to other external components.
If detection operation is required, please conduct thorough evaluations with the actual applications. If this constantcurrent circuit is not required, select the S-82K5A Series.
Remark10

n = 1, 2, 3, 4

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.1_00
S-82K5B Series Timing Charts
1.

Overcharge detection operation (With overcharge timer reset function)
VCUn
VCLn
Battery voltagetTR or longertCU or shorter
VCOH
CO pintCU
Figure 62.

Overcharge timer reset operation (With overcharge timer reset function)tTR or shortertTR or shortertTR or longer

VCUn
VCLn
Battery voltage

VCOH

tCU orshortertTR

CO pinTimer resettCU
Figure 7

Remarkn = 1, 2, 3, 4, 5

11

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-82K5B Series
Rev.1.1_00
 Connection Examples of Battery Monitoring IC
1.

5-serial cell
SCP

EB+
RCTLC

VDD
BAT1

RVDD

CVDD
VC1

R1
BAT2

CTLC

C1
VC2

R2
BAT3

C2
VC3

R3
BAT4

FET*1

DP

CO

C3
VC4

R4
BAT5

C4
VSS

EB−

*1. This IC limits its CO pin output voltage to 7.5 V max., so a FET with the gate withstand voltage of 8 V can be used.
Figure 8

Table 10 Constants for External Components

Caution 1.
2.

3.

12

No.
Part
Typ.
Unit
kΩ
1
R1 to R4
1
μF
2
C1 to C4, CVDD
1
Ω
3
RVDD
100
kΩ
4
RCTLC
1
The constants may be changed without notice.
It has not been confirmed whether the operation is normal or not in circuits other than theconnection example. In addition, the connection example and the constants do not guarantee
proper operation. Perform thorough evaluation using an actual application to set the constants.
Since the CO pin may become the detection status transiently when the battery is being connected,
connect the positive terminal of BAT1 last in order to prevent the protection fuse from cutoff.

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.1_00
S-82K5B Series
2.

10-serial cell
SCP

EB+
RCTLC

VDD
BAT1

RVDD1

CVDD1
VC1

R11
BAT2

CTLC

C11
VC2

R21
BAT3

C21
VC3

R31
BAT4

CO

C31
VC4

R41
BAT5

C41
VSS

RCTLC_C
CCTLC_C
VDD
BAT6

RVDD2

CVDD2
VC1

R12
BAT7

CTLC

C12
VC2

R22
BAT8

C22
VC3

R32
BAT9

FET*1

DP

CO

C32
VC4

R42
BAT10

C42
VSS

EB−

*1. This IC limits its CO pin output voltage to 7.5 V max., so a FET with the gate withstand voltage of 8 V can be used.
Figure 9
RemarkRegarding the recommended values for external components, refer to "Table 11 Constants for External
Components".
13

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-82K5B Series
Rev.1.1_00
3.

9-serial cell
SCP

EB+
RCTLC

VDD
BAT1

RVDD1

CVDD1
VC1

R11
BAT2

CTLC

C11
VC2

R21
BAT3

C21
VC3

R31
BAT4

CO

C31
VC4

R41
BAT5

C41
VSS

RCTLC_C
CCTLC_C
VDD
BAT6

RVDD2

CVDD2
VC1

R12
BAT7

CTLC

C12
VC2

R22
BAT8

C22
VC3

R32
BAT9

FET*1

CO

DP

C32
VC4

VSS

EB−

*1. This IC limits its CO pin output voltage to 7.5 V max., so a FET with the gate withstand voltage of 8 V can be used.
Figure 10
Remark14

Regarding the recommended values for external components, refer to "Table 11 Constants for External
Components".

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.1_00
S-82K5B Series
4.

7-serial cell
SCP

EB+
RCTLC

VDD
BAT1

RVDD1

CVDD1
VC1

R11
BAT2

CTLC

C11
VC2

R21
BAT3

C21
VC3

R31
BAT4

CO

C31
VC4

VSS

RCTLC_C
CCTLC_C
VDD
BAT5

RVDD2

CVDD2
VC1

R12
BAT6

CTLC

C12
VC2

R22
BAT7

FET*1

C22
VC3

CO

DP

VC4

VSS

EB−

*1. This IC limits its CO pin output voltage to 7.5 V max., so a FET with the gate withstand voltage of 8 V can be used.
Figure 11.
RemarkRegarding the recommended values for external components, refer to "Table 11 Constants for External
Components".
15

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-82K5B Series
Rev.1.1_00
Table 11 Constants for External Components

No.

Caution 1.
2.

3.

Part
Typ.
Unit
R11 to R41,kΩ
1
1
R12 to R42
C11 to C41,μF
2
C12 to C42,1
CVDD1, CVDD2
Ω3
RVDD1, RVDD2
100
kΩ
4
RCTLC
1
MΩ
5
RCTLC_C
5.1
μF
6CCTLC_C
0.01
The constants may be changed without notice.
It has not been confirmed whether the operation is normal or not in circuits other than theconnection example. In addition, the connection example and the constants do not guarantee
proper operation. Perform thorough evaluation using an actual application to set the constants.
Since the CO pin may become the detection status transiently when the battery is being connected,
connect the positive terminal of BAT1 last in order to prevent the protection fuse from cutoff.

[For SCP, contact]
Dexerials Corporation
Tokyo Office
Address: Mitsui Sumitomo Kaijo Tepco Building 9F, 1-6-1
Kyobashi, Chuo-ku, Tokyo 104-0031, Japan
Tel: +81-3-3538-1230 (main)
https://www.dexerials.jp/en/



16



BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.1_00
S-82K5B Series
 Precautions● Do not connect batteries charged with VCL or higher.
● If the connected batteries include a battery charged with VCL or higher, this IC may become the overcharge status after
all pins are connected.
● In some application circuits, even if an overcharged battery is not included, the order of connecting batteries may be
restricted to prevent transient output of the CO pin detection pulses when the batteries are connected. Perform thoroughevaluation with the actual application circuit.
● The application conditions for the input voltage, the output voltage, and the load current should not exceed the power
dissipation.
● Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
● ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.

17

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-82K5B Series
Rev.1.1_00
 Characteristics (Typical Data)
Current consumption
1. 1 IOPE vs. VDD

1. 2 IOPE vs. Ta

3.0

5

2.5

4

2.0

IOPE [µA]

IOPE [µA]

1.

1.5
1.0

3
2

0.5

1

0.0

0
VDD [V]2.

Ta [°C]

Detection voltage, release voltage
2. 1 VCU vs. Ta

2. 2 VCL vs. Ta

4.305

4.275

4.285

VCL [V]VCU [V]

4.295
4.275
4.265

4.225

4.255
4.245

4.175

Ta [°C]

3.

Delay time
3. 1 tCU vs. Ta

2.0

tCU [s]

1.5
1.0
0.5
0.0
Ta [°C]18

Ta [°C]

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.1_00
S-82K5B Series
Output pin
4. 2 ICOL vs. VDD

0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50

600
500
ICOL [µA]

ICOH [µA]

4. 1 ICOH vs. VDD

400
300
200
100
0

VDD [V]VDD [V]

4. 3 VCOH vs. VDD

VCOH [V]4.

VCU = 4.275 V

10
9
8
7
6
5
4
3
2
1
0
VDD [V]

19

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-82K5B Series
Rev.1.1_00
 Marking Specifications
1.

TMSOP-88

Top view
7
6
5

(1):
(2) to (4):(5):(6) to (8):Blank
Product code (refer to Product name vs. Product code)Blank
Lot number(1) (2) (3) (4)(5) (6) (7) (8)

1

2

3

4

Product name vs. Product code

Product Code
(2)
(3)
(4)
b
F
A

Product Name
S-82K5BAA-K8T2U

2.

SNT-8A8

Top view
7
6
5

(1):
(2) to (4):(5), (6):(7) to (11):(1) (2) (3) (4)(5) (6) (7) (8)(9) (10) (11)

1

2

3

4

Product name vs. Product code

Product Name
S-82K5BAA-I8T1U

20

Product Code
(2)
(3)
(4)
b
F
A

Blank
Product code (refer to Product name vs. Product code)Blank
Lot number

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.1.1_00
S-82K5B Series Power Dissipation
TMSOP-8

SNT-8A
Tj = +125°C max.

B

0.8

A
0.6
0.4
0.2
0.0

0

25

50

75

100

125

150

175

Tj = +125°C max.

1.0

Power dissipation (PD) [W]Power dissipation (PD) [W]

1.0

0.8
B

0.6

A
0.4
0.2
0.0

0

25

Ambient temperature (Ta) [°C]
Board
A
B
C
D
E

Power Dissipation (PD)
0.63 W
0.75 W
−
−
−

50

75

100

125

150

175

Ambient temperature (Ta) [°C]
Board
A
B
C
D
E

Power Dissipation (PD)0.47 W
0.58 W−−−

21

TMSOP-8 Test Board(1) Board A

IC Mount Area
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]

1
2
3
4

Thermal via

Specification
114.3 x 76.2 x t1.6
FR-4
2Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.070-(2) Board B
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]Thermal via

1
2
3
4

Specification
114.3 x 76.2 x t1.6
FR-4
4Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070-

No. TMSOP8-A-Board-SD-1.0

ABLIC Inc.

SNT-8A Test Board
IC Mount Area

(1) Board A
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]

1
2
3
4

Thermal via

Specification
114.3 x 76.2 x t1.6
FR-4
2Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.070-(2) Board B
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]Thermal via

1
2
3
4

Specification
114.3 x 76.2 x t1.6
FR-4
4Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070-

No. SNT8A-A-Board-SD-1.0

ABLIC Inc.

0.45±0.25142.8±0.284.0±0.2

2.90±0.2

0.2±0.1
0.65±0.1

0.8max.

0.08±0.05

0.6±0.1

0.13±0.1

No. FM008-A-P-SD-1.2

TITLE

TMSOP8-A-PKG Dimensions

No.

FM008-A-P-SD-1.2

ANGLE
UNIT

mm

ABLIC Inc.

1.75±0.1

4.00±0.1(10 pitches:40.0±0.2)

4.00±0.1

4.25±0.05+0.2

5.50±0.05
ø1.05±0.05

1.00±0.1

12.0 -0.1

2.00±0.05+0.1
ø1.5 -00.30±0.05

3.25±0.05

4

1

5

8

Feed direction

No. FM008-A-C-SD-3.0

TITLE

TMSOP8-A-Carrier TapeNo.

FM008-A-C-SD-3.0

ANGLE
UNIT

mm

ABLIC Inc.

+0

ø180 - 3

ø60 +1-0+1.0

13.0 - 0.0
15.4±1.0

Enlarged drawing in the central part±0.8

ø13±0.2
2±
0.5

1
ø2

(60°)

(60°)

No. FM008-A-R-SD-2.0

TITLE

TMSOP8-A-ReelNo.

FM008-A-R-SD-2.0
QTY.

ANGLE
UNIT

mm

ABLIC Inc.

4,000

1.97±0.03
8

7

6

5

3

4

+0.05

1

0.5

2

0.08 -0.02

0.48±0.02

0.2±0.05

No. PH008-A-P-SD-2.1

TITLE

SNT-8A-A-PKG Dimensions

No.

PH008-A-P-SD-2.1

ANGLE
UNIT

mm

ABLIC Inc.

+0.1

ø1.5 -02.25±0.05

4.0±0.1

2.0±0.05

ø0.5±0.1

0.25±0.05

0.65±0.05

4.0±0.1

4321

5 6 78Feed direction

No. PH008-A-C-SD-2.0

TITLE

SNT-8A-A-Carrier TapeNo.

PH008-A-C-SD-2.0

ANGLE
UNIT

mm

ABLIC Inc.

+1.0

9.0 - 0.0
11.4±1.0

Enlarged drawing in the central part

ø13±0.2

(60°)

(60°)

No. PH008-A-R-SD-2.0

TITLE

SNT-8A-A-ReelNo.

PH008-A-R-SD-2.0
QTY.

ANGLE
UNIT

mm

ABLIC Inc.

5,000

0.52

2.01

2

0.52

0.2 0.3
1.
2.

1(0.25 mm min. / 0.30 mm typ.)(1.96 mm ~ 2.06 mm)
1.
2.
3.
4.

0.03 mm

SNT

1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm).
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1.
2.

(0.25 mm min. / 0.30 mm typ.)(1.96 mm ~ 2.06 mm)

No. PH008-A-L-SD-4.1

TITLE

SNT-8A-A-Land Recommendation

No.

PH008-A-L-SD-4.1

ANGLE
UNIT

mm

ABLIC Inc.

Disclaimers (Handling Precautions)1.

All the information described herein (product data, specifications, figures, tables, programs, algorithms andapplication circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.

2.

The circuit examples and the usages described herein are for reference only, and do not guarantee the success ofany specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any otherright due to the use of the information described herein.

3.

ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information describedherein.

4.

Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due tothe use of the products outside their specified ranges.

5.

Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.

6.

When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-relatedlaws, and follow the required procedures.

7.

The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,biological or chemical weapons or missiles, or use any other military purposes.

8.

The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.

9.

In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products areallowed to apply for the system on customer's own responsibility.

10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of thisdocument described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07

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