On-Wafer Small-Signal and Large-Signal
Measurements up to Sub-THz Frequencies
Invited Paper
Viktor Krozer, Ralf Doerner, Franz-Josef Schmückle,
Nils Weimann, Wolfgang HeinrichFerdinand-Braun-Institut (FBH),
Leibniz-Institut für Höchstfrequenztechnik
Berlin, Germany
viktor.krozer@fbh-berlin.deAndrej Rumiantsev*,$*

MPI Corporation,
Chu-Pei City, Hsinchu County, Taiwan$
Brandenburg University of Technology (BTU),
Cottbus-Senftenberg, Cottbus, Germany
a.rumiantsev@ieee.org

Marco Lisker, Bernd Tillack
IHP GmbH
Innovations for High Performance Microelectronics
Leibniz-Institut für innovative MikroelektronikFrankfurt (Oder), Germany
Abstract — Recent advances in MMIC technology haveopened the possibilities for circuit operation in the THz range.
There are numerous examples of BiCMOS and III-V compounddevice technologies with demonstrated performance beyond
600 GHz. Characterization of such MMIC are predominantly
performed on-wafer in a planar environment. However, on-wafer
characterization facilities do not fully keep pace with MMIC
development in terms of frequency and power. The paper
discusses issues involved in on-wafer calibration at mm-wave
frequencies, which is the basis for accurate measurements andcharacterization of active and passive device. Subsequently, thepaper discusses mm-wave interconnect characterization. Lowloss interconnects are important for mm-wave MMIC, especiallyin case of heterogeneous integration. Finally, a novel
heterogeneous integration approach of bipolar technologies,
using both BiCMOS and InP DHBT processes is presented. Thisapproach heavily relies on low-loss interconnects and accurate
device modelling. It will be shown that accurate large-signal
models can be efficiently extracted from well-calibrated on-wafer
multi-bias small-signal measurements, but verification is difficult
due to calibration difficulties at mm-wave frequencies.
Keywords — on-wafer calibration techniques, on-wafer
characterization, mm-wave and sub-mm-wave circuits, calibration
methodologies, sub-mm-wave transmission lines, interconnects

I. INTRODUCTION
Recent advances in MMIC technology have opened thepossibilities for integrated circuit operation in the THz range.
There are numerous examples of BiCMOS and III-V
compound device technologies, with demonstrated
performance beyond 600 GHz. The design of such MMIC isgenerally based on a detailed knowledge of EM effects of thepassives and interconnects, and on good large-signal andsmall-signal device modelling. Characterization of such
MMIC is predominantly performed on-wafer in a planar
environment and requires accurate calibration techniques.

But on-wafer characterization facilities do not fully keep
pace with MMIC development in terms of frequency ofoperation and power. Especially critical is the accuratecharacterization and modelling of devices operational up to
THz frequencies. This owes to the fact that accurate on-wafer
calibration is difficult at higher frequencies, due to excitationof higher order modes, signal coupling and a multi-mode
operation as well as coupling effects corrupting the calibration
data. The situation becomes even more difficult with the
newly implemented processes utilizing transfer substrates andheterogeneous integration, which exhibit many transitions to a
multitude of transmission line technologies. Characterizationof passives like interconnects requires calibration up to THz
frequencies, while device model extraction necessitates
measurements at somewhat lower frequencies. An example,
the attenuation of a coplanar waveguide (CPW) line ispresented in Fig. 1 as a function of frequency. It shows that
corrupted or inaccurate data obtained during calibration leads
to inaccuracies in the device under test (DUT) measurement
results. The paper will show below that the origin of theseissues have to be determined and overcome in order toaccurately determine the DUT performance at THz
frequencies.
Of particular importance is the choice of the transmission
line technologies (e.g. CPW, standard, thin-film and inverted
microstrip) and the according interconnects. In particular, thepaper discusses transmission line and interconnect
performances, using simulations verified with experiments at
millimeter-wave frequencies. It is shown that thin-film
microstrip or stripline lines are especially suitable for line
calibration standards and interconnects at THz frequencies.
Further, the paper shows that although active device modelling
generally utilize data up to 60 GHz, device model verification
requires measurements up to THz frequencies due to the highcut-off and maximum oscillation frequencies of modern
bipolar devices. One important aspect for useful© 2014 IEEE. Reprinted, with permission, Bipolar/BiCMOS Circuits and Technology Meeting (BCTM); DOI: 10.1109/BCTM.2014.6981306

measurements is the control of output power, which has to be
sufficiently low for transistor characterization and hence limits
considerably the dynamic range of today's measurement
equipment. Another aspect is the positioning accuracy of theprobes at high frequencies.

The impact of the on-wafer probe can be understood byconsidering that the outer structure dimensions are large
compared to the on-wafer calibration standard dimensions.
This enables the excitation of additional propagating modes
on-wafer, which are not related to the desired CPW mode.
Firstly, the coupling between probe ground and on-wafer
ground creates a parasitic propagating signal. Secondly, in thevicinity of the pad structure a mode is excited similar to theparallel-plate mode between the CPW ground contacts andbackside contact. Finally, there is a mode which is guided
between the ground of the coaxial probe and the wafer
backside metallization. Fig. 2 shows these effects obtained
from 3D EM simulations of calibration standards employing
microstrip lines. The interaction of the probe with thesurrounding structures is clearly visible.

Fig. 1: CPW attenuation versus frequency for a CPW line extracted frommeasurements using multi-line TRL. The theoretical CPW attenuation is also
indicated [3].

Thin-film transmission lines and interconnects are built on
top of a substantial dielectric stack on top of the active device
layers. In this paper we go a step further and demonstrate thatsuch stacks can be efficiently combined using BiCMOS and
III-V technologies at mm-wave frequencies. The paper will
demonstrate interconnect and device characterization in thiswafer-level heterogeneous integration processes. It is based ona newly established InP-on-BiCMOS process, available now
through the SciFab IHP foundry. The transitions from the
BiCMOS circuits to the InP circuits and vice versa as well asactive device performance will be discussed in detail using
simulated and measured results.
II. PITFALLS IN ON-WAFER CALIBRATION AT MM-WAVE
FREQUENCIESIt becomes indispensable to perform accurate on-wafer
device characterization at mm-wave frequencies, due to theincreasing transit and maximum oscillation frequencies of thedevices employed in such circuits. Generally, results rely todate on extrapolations from low-frequency measurements. The
difficulties in on-wafer measurements have many sources,
such as for example: crosstalk between probes, crosstalk withother structures on-wafer, parasitic mode excitation withprobes, on-wafer calibration errors, probe misalignment,
multi-mode propagation on the calibration standards, signal
losses, limited dynamic range of equipment due to low signal
levels, radiation into the substrate, parallel plate mode
excitation in CPW structures etc. Another difficulty appearing
at frequencies above 110 GHz is the necessity for recalibration of the system at each band with the according reoccurrence of all the above difficulties.
The key components for understanding the above effects
are the on-wafer probes, the transmission line properties andthe calibration procedures employed. Calibration procedures
will be treated in the following section, while the other two
will be discussed below.

Fig. 2: Left: Electrical field Ey in the longitudinal cross-section (y is thevertical axis, blue color means negative, red color positive and green color
zero field values, respectively); Right: Electrical field Ey in the top view crosssection directly under the ground metallization of the microstrip lines (y is thenormal direction). Inset: The exciting probe positioned over a shortneighboring microstrip line [3].

The impact of this coupling and excitation of parasitic
modes on the calibration procedure can be evaluated, whensimulating different calibration standards in microstrip
technology [4] and CPW environment [1], [2], [5], [6],respectively. As an example, Fig. 3, shows simulated resultsfor S21 of three different transmission line lengths, which are
typically used during calibration. It can be concluded from thefigure that coupling to a neighboring line gives rise totransmission dips at frequencies related to the length of thisline. Coupling to several lines on both ends of the DUT will
give rise to several dips in the frequency characteristic. These
dips are then responsible for measurement inaccuracies in the
final measurements after calibration, independent of thecalibration methodology used.

L

Fig. 3: Signal transmission for neighboring short microstrip lines of threedifferent lengths (L = 600 μm, 1000 μm and 1400 μm) corresponding topronounced resonance points (75, 48 and 37 GHz) [4].

© 2014 IEEE. Reprinted, with permission, Bipolar/BiCMOS Circuits and Technology Meeting (BCTM); DOI: 10.1109/BCTM.2014.6981306

It is common practice to employ CPW waveguides ascalibration standards on-wafer in addition to the calibration
substrates. These calibration standards are prone to parallelplate mode propagation and consequently to substrate mode
excitation. Fig. 4 illustrates the coupling effect for a substrateplaced on top of a ceramic mimicking an infinite substrate andthe same situation with a metallized back-plane. One canclearly see the strong coupling into a parallel-plate mode incase of backside metallization.

Fig. 4: Field plots from CST Microwave Studio simulations with the CPW
substrate placed on: ceramic (top) and metal (bottom). Open boundary
condition is applied at the bottom for ceramic CPW substrate, while anelectric wall boundary is applied for metal CPW substrate [22].

III. ADVANCED CALIBRATION PROCEDURES
A. On-Wafer Calibration
Scattering (S)-parametermeasurementsofdevicesfabricated on semiconductor wafers are usually calibratedusing a two-step procedure: first the measurement reference
plane is set close to the RF probe tips using suitablecalibration substrates and then parallel and serial parasitic
impedances are characterized by measurements of the device
de-embedding elements. As it was demonstrated in [13]–[15],the on-wafer S-parameter calibration with in-situ standards isthe preferable strategy for accurate device characterization at
sub-mm-wave frequencies, in particular on silicon. The
measurement reference plane is shifted close to the device
terminals (Fig. 5). Application of commercial planarcalibration standards assures consistent level of calibration
accuracy for the wafer-level S-parameter measurement
system [11]. This procedure remains accurate only if theabove coupling effects on the calibration substrate can beignored. In addition, de-embedding of the device back end ofline (BEOL) parasitics becomes a challenge at mm-wave andsub-mm-wave frequencies due to the increased complexity of
the BEOL equivalent circuit and de-embedding algorithms,
involving more than five measurement steps (e.g. [12]).
While a great variety of S-parameter calibration methods
are available nowadays, the multiline thru-reflect-line(mTRL) [16] and the transfer thru-match-reflect (TMR, or
LRM) [17] are relevant for implementation. The convincing
advantage of mTRL is its capability to directly measure theS-parameters of in-situ transmission lines at a well-defined
single-mode reference plane setting the calibration reference
impedance ZREF to the characteristic impedance of the line

standard [20], [21]. Thin-film lines provide line standards withcharacteristic impedance close to 50 Ω and reduced dispersion
region using modern semiconductor technologies. Therefore,
the transformation of the calibration reference impedance tothe system of 50 Ω reference impedance (i.e. to “pseudo
S-parameters”, [18]) may not be required for the majority ofmeasurement tasks. The remaining practical limitation of themTRL, however, is the relatively big size of the test chip taken
by calibration standards and the need to re-position wafer
probes during calibration procedure. It is important to note,that the minimal size of the TRL chip is reverse proportional
to measurement frequencies and is less relevant at sub-mmwave frequencies, omitting low frequencies.

Fig. 5: Three different locations of the reference plane: probe tip, top metal
and DUT terminals

The transfer TMR approach has a remarkable advantage: itrequires only three standards with the same geometry taking
the minimum space of a test chip. The TMR can be easily
automated and runs without the need of operator interaction ona conventional wafer probe system. However, the accurate
determination of the calibration reference impedance of TMR
at sub-mm-wave range is difficult (same holds for any otherlumped-standard based calibration method). While [19]suggested several methods applicable for W-band range, thesolution for higher frequencies is still underway.
B. Calibration Reference Plane
Designing in-situ broadband thin-film transmission lines
close to the DUT terminals necessitates the utilization of the
top metal level, for instance M6 for the ST Microelectronics’
BiCMOS9MMW process (Fig. 6), or the LB metal for IBM’s
SOI12S0 process (Fig. 7). Therefore, the optimal position of
the in-situ calibration reference plane is at the top metal level
and can be shifted from the top metal to the intrinsic device
terminals by a conventional de-embedding approach. Because
the parasitic impedance of the contact pads and interconnectlines are already included into the systematic calibration error
model, the equivalent impedance of the de-embedding
elements should be mostly of pure lumped nature [20], [21].

Fig. 6: Cross-section (left) and a photograph (right) of the thru standard
implemented in the ST Microelectronics’ Si/SiGe:C BiCMOS9MMW
process(taken from [20]).

© 2014 IEEE. Reprinted, with permission, Bipolar/BiCMOS Circuits and Technology Meeting (BCTM); DOI: 10.1109/BCTM.2014.6981306

The work in [15] demonstrated an implementation of thein-situ mTRL calibration up to 750 GHz frequencies withsmooth and consistent propagation constant suitable fortransistor device characterization. The calibration lines wererealized in a thin-film microstrip design on a thinbisbenzocyclobutene-based (BCB) monomers film. Later, asimilar experiment was performed on calibration lines realized
by IBM’s SOI12SO process (Fig. 8). These results confirm
that suitable sub-mm-wave transmission lines for calibration
purposes can be realized using thin-film transmission lines andmTRL is applicable.

Fig. 7: Cross-section of the transmission-line (top) and test structure (bottom)
implemented in IBM 45-nm complementary metal-oxide-semiconductor(CMOS) silicon-on-insulator SOI12S0 integrated-circuit process [21].

interior crosstalk models was reported recently in [22]. It wasdemonstrated that correction for the parasitic coupling andcrosstalk errors become relevant already at upper W-band
frequencies (Fig. 9). Several useful recommendations on
optimization of on-wafer standards were given there, such as
minimizing of the signal-conductor width and the gap to theground conductors for CPW standard design and keeping theaccess lines short.

Fig. 9: Two-tier interior crosstalk model (top) and the maximum stable gainof a transistor corrected with standard TRL and with TRL augmented withcoupling corrections (bottom) [22].

IV. MM-WAVE DEVICE ON-WAFER CHARACTERIZATION
A. Interconnects and Transmission Lines
Mm-wave and sub-mm-wave MMIC require low-loss
interconnects and low-loss transmission lines. As indicated in
the previous section, thin-film and inverted microstrip lines
have demonstrated suitability for MMIC applications up to
THzfrequencies,
due
to
their
advantageous
characteristics [21].

Fig. 8: Comparison of measured effective dielectric constant of the line
standard implemented in Teledyne BCB and IBM’s SOI process [21]).

C. Correction for Crosstalk and CouplingWith increase of measurement frequency to the sub-THz
range, the impact of parasitic effects described above cansignificantly contribute to the calibration residual errors. Then,the conventional approach of modeling the systematic
measurement errors of a wafer probe measurement system by
twelve error terms becomes insufficient. A comprehensive
study of two different approaches, the 16-term and the two-tierThin-film microstrip lines require, however, an appropriate
dielectric stack with the according interconnects. Fig. 10shows a comparison of simulated and measured transmission
coefficient up to 220 GHz for a thin-film microstrip line in
BiCMOS, with interconnect transitions to a BCB thin-film
microstrip line and pads in InP technology. These results
confirm the broadband capabilities of low-loss interconnecttransitions employed in thin-film transmission line technology.
In fact, the losses of each transition from the BCB to the
BiCMOS stack are lower than 0.5 dB at 220 GHz. Such lowloss transition structures can be employed in heterogeneous
integration, as described below or for chip-to-chip transitions.
Measurement results for similar lines are presented in Fig. 11
for different line lengths. These results demonstrate the© 2014 IEEE. Reprinted, with permission, Bipolar/BiCMOS Circuits and Technology Meeting (BCTM); DOI: 10.1109/BCTM.2014.6981306

usefulness of such lines and interconnects for calibration andcircuit purposes.

capabilities increased exponentially, new probe technologies
came to place and the list of probe manufactures
expanded [23]. Recently, micromachined probes designed tofacilitate the development of TMICs in the 750 GHz to
1.1 THz frequency range have been introduced. This probedemonstrated an insertion loss of less than 7 dB and a returnloss of greater than 15 dB, as can be observed in Fig. 13 [24].

Fig. 10: Comparison of simulated and measured transmission losses of a
microstrip line on BiCMOS probed through a microstrip line on InP
heterogeneously integrated on top of the BiCMOS wafer. The results include
line losses and losses due to two transitions between the two technologies [8].
Fig. 13: Measured S-parameters of the 1.1 THz wafer probe [24].

Fig. 11: Comparison of simulated and measured transmission losses of a
microstrip line on BiCMOS probed through a microstrip line on InP
heterogeneously integrated on top of the BiCMOS wafer. The results include
line losses and losses due to two transitions between the two technologies.

While small-signal measurement capabilities of modern
systems have already achieved the THz frequency range, themore sophisticated wafer-level large-signal and noise
measurements still remain a great challenge. Load-pull and RF
noise measurement systems for the W-band are seldom
available. The traditional load-pull techniques that require
integration of the electro-mechanical impedance tuners on thewafer probe system suffer from high losses (e.g. larger than
2 dB at W-band) and other limitations at millimeter-wave
frequencies and beyond. As a result, the maximum reachable
reflection coefficient of such systems is lower than 0.6.

Thin-film transmission lines exhibit also a relatively small
phase constant as can be seen in Fig. 12 with a respective
attenuation constant of around 1 dB/mm at 200 GHz.

Fig. 12: Measured attenuation constant (left) and relative phase constant(right) frequency characteristics of a thin-film microstrip line in BCB.

B. Transistor Devices and MMIC
Wafer-level device characterization technology made asubstantial progress in the last decade: RF probe frequency

Fig. 14: The schematic diagram (top) and the photograph (bottom) of the Wband double-stub MEMS switch impedance tuner [26].

A novel concept of an active real-time load-pull W-band
system with frequency up/down conversion technique wasreported in [25]. The authors claimed to reach load reflection
coefficients as high as 0.95 at 94 GHz. Nearly full coverage of© 2014 IEEE. Reprinted, with permission, Bipolar/BiCMOS Circuits and Technology Meeting (BCTM); DOI: 10.1109/BCTM.2014.6981306

the Smith chart enables verification of the large-signal device
models and accurate characterization of microwave integrated
circuits the sub-THz frequency range. An alternative approachto minimize the setup losses is to integrate a reconfigurable
impedance tuner into the wafer probe [26]. The schematic
circuit and a micrograph are shown in Fig. 14. Realizing
double and triple switching topologies and using MEMS
switches, maximum load reflection coefficient lower than 0.92
and 0.82 were achieved for 75 GHz and 100 GHz frequencies,
respectively.

based HBTs are presented here based on [29]. Aftertransferring the elements found from small-signal extraction to
the large-signal model, the parameters affecting the DC andthermal characteristics of the device are determined. The
large-signal model can accurately predict large-signal
performance including device scaling, as illustrated in Fig. 16.

A further step toward reducing the setup losses is theintegration of the tuner on-wafer, e.g. the in-situ impedancetuning. In [27] the design of an in-situ impedance tuner andmeasurement results of the device noise parameters obtainedat D-band have been presented. As it was originally discussed
in [28], the tuner is based on 50 Ω transmission lines anddigital tunable capacitances (DTC) connected in parallel. It
can provide 32 different impedance points, optimized forcharacterization of a particular device, as illustrated in Fig. 15.
As it is claimed in [27] the developed in-situ impedancetuning technique is an efficient solution for extracting thedevice noise parameters in the entire D-band range.

Fig. 16: Measured (solid line w. symbols) and simulated (solid line) largesignal performance at 77 GHz for single-finger device biased at Vce = 1.4 V
with a quiescent current of Icq = 22.7 mA (top) and two-finger device biased atVce = 1.4 V with a quiescent current of Icq = 29.6 mA (bottom) [29].

These results demonstrate a successful sequence of steps
comprised of on-wafer system calibration, low-loss
interconnect transitions and single mode transmission lines,
reference plane shift, small-signal model parameter extraction
and finally large-signal parameter extraction. This procedure
is subsequently applied to the characterization of devices in
the heterogeneous integration technology described below.
V. HETEROGENEOUS MMIC DEVICE TESTING

Fig. 15: The schematc of the DTC (top) and a photograph of the D-bandsource-pull in-situ impedance tunners (bottom). Pictures from [27], [28].

C. Large-Signal Device Characterization
The small-signal equivalent circuit parameters fortransistor devices in two-terminal and three-terminal
configurations are determined by employing a direct
parameter extraction methodology. The accuracy of thisextraction relies entirely on the accuracy of the on-wafer
calibration and on the accuracy of the reference plane shift
towards the intrinsic device terminals. Assuming that thecalibration issues described above have been avoided and asuitable calibration procedure has been applied allows for
direct parameter extraction using multi-bias S-parametertransistor measurements. As an example, results for InP III-V

Wafer-level integration of heterogeneous technologies has
recently attracted a lot of attention, due to technologicaldevelopments in several large-scale projects, such as e.g.
COSMOS [5], [6], or SciFab [7]–[10]. The major driving
force is to provide high-speed III-V semiconductor devices on
Si platforms, providing not only speed improvement without
trade-off in signal amplitude, but also functional complexity tohigh-speed circuits.
Such technology developments put high demands on
device characterization. Fig. 17 illustrates schematically thecross-section of the InP-on-BiCMOS process. One challenge
is the device characterization of devices after heterogeneous
wafer-level integration. The characterization of the impact ofsuch a technology on device performance is facilitated byintroducing pad and interconnect structures, whichinterconnect the buried BiCMOS devices with top-level pads
on InP.
The impact of the additional layers on transistor
performance in BiCMOS and InP technologies, respectively,© 2014 IEEE. Reprinted, with permission, Bipolar/BiCMOS Circuits and Technology Meeting (BCTM); DOI: 10.1109/BCTM.2014.6981306

are shown in Fig. 18 and Fig. 19. Fig. 18 shows theextrapolated transit and maximum oscillation frequencies,
respectively, from measurements of BiCMOS transistor
devices on completely processed InP-on-BiCMOS wafers. The
various curves represent values for devices across a 3-inch
wafer area. The horizontal lines in Fig. 18 indicate themaximum values for the transit and maximum oscillation
frequencies for devices before heterogeneous integration.
These results employ low-loss interconnect via technology. It
can be concluded from the figure that the impact of theheterogeneous integration can be estimated to cause a decreasein both values of only around 5 GHz and is not limited by theinterconnects.

that the filler structures, as well as the thermal via structuresare small and non-interconnected, which has been confirmed
by 3D EM simulations.

Fig. 17: Cross-section of the InP-on-BiCMOS substrate transfer process. Theinterconnects between TM2 with G2 and Gd with M1, respectively, form athin-film microstrip interconnection. Top-level pads are on metal level G2 [9].

Fig. 19: Small-signal input and output S-parameters of single-finger InPDHBT in a transferred-substrate (TS) process and the same device with fillers
in the InP-on-BiCMOS process (top) and implementing a heat-sinkunderneath the transistor in SiGe (bottom). Measurements are in the range
1 GHz–110 GHz. Cyan and blue lines are results for the standard TS process,red and magenta are results for InP HBT transistors in InP-on-BiCMOS
process. Insets show the transistor layout for the two cases, respectively [10].

Fig. 18: Interpolated transit frequency fT and maximum oscillator frequency
fmax as a function of collector current Ic measured at 30 GHz and an emittercollector voltage Vce = 1.5 V for eight NPN HBTs in parallel. Horizontal lines
indicate the respective values before heterogeneous integration [9].

It has been shown in [10] that device small-signal andlarge-signal performance of the BiCMOS and InP HBT
devices, respectively, remains essentially unaffected by thehetero-integration InP-on-BiCMOS process. Small-signal
measurements provided in Fig. 19 indicate that there is only aminor impact by fillers and thermal vias in SiGe BiCMOS on
InP DHBT performance. This is most probably due to the fact

These results are important for circuit integration in bothtechnologies, which requires dissipation of thermal energy
from the top-level InP DHBT devices operating under largesignal conditions.
VI. SUMMARY
It is shown that mm-wave and sub-mm-wave on-wafer
characterization presents a challenge from calibration, onwafer measurement, measurement system and circuit design
point of view. The methodologies to overcome thesechallenges include modified calibration standards avoiding
probe coupling and coupling between structures in on-wafer
calibration substrates.

© 2014 IEEE. Reprinted, with permission, Bipolar/BiCMOS Circuits and Technology Meeting (BCTM); DOI: 10.1109/BCTM.2014.6981306

These also include the suppression of multi-mode
propagation using thin-film transmission lines, as well as
appropriate transitions between the levels. The suggestions
discussed in the paper lead to improved calibration standards
suitable for TRL and LRM calibration methodologies.
It is further shown, that successful attempts exist for smallsignal characterization of devices and MMICs up to sub-mmwave frequencies using thin-film transmission lines. The
impact of standard calibration procedures on device
characterization is discussed. It is shown that accurate device
characterization is important for the verification of theextracted models. Finally, characterization results forheterogeneously integrated devices and MMIC are presented.
ACKNOWLEDGMENT
Viktor Krozer thanks Oerlikon AG for partial financial
support.
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© 2014 IEEE. Reprinted, with permission, Bipolar/BiCMOS Circuits and Technology Meeting (BCTM); DOI: 10.1109/BCTM.2014.6981306