S-19117/19119xxxA Series
www.ablic.com

AUTOMOTIVE, 125°C OPERATION, 36 V,
SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR
WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00© ABLIC Inc., 2021-2022

This IC, developed using CMOS technology, is a high-accuracy voltage detector with the supply voltage divided output. The
detection voltage and release voltage are fixed internally with an accuracy of ±1.5%.
Apart from the power supply pin, the detection voltage input pin (SENSE pin) is also prepared, so the output is stable even if
the SENSE pin voltage (VSENSE) falls to 0 V. The SENSE pin also has a built-in reverse connection protection circuit that
reduces current in the SENSE pin during a reverse connection.
The release signal can be delayed by setting a capacitor externally, and the release delay time accuracy is ±15% (CD =3.3 nF). The output form is Nch open-drain output.
The supply voltage divided output is prepared in this IC. The supply voltage divided output is a function that divides the
VSENSE into VSENSE/6, VSENSE/8, VSENSE/12 or VSENSE/14 and outputs the voltage. For example, this function makes it possiblethat the IC connects to a low voltage microcontroller A/D converter directly and the microcontroller monitors a battery
voltage.
ABLIC Inc. offers FIT rate calculated based on actual customer usage conditions in order to support customer functionalsafety design.
For more information regarding our FIT rate calculation, contact our sales representatives.
CautionThis product can be used in vehicle equipment and in-vehicle equipment. Before using the product forthese purposes, it is imperative to contact our sales representatives.

 Features
Detector block• Detection voltage:
4.0 V to 10.0 V (0.05 V step)• Detection voltage accuracy:±1.5%• Hysteresis width selectable from "Available" / "Unavailable":"Available": 5.0%, 10.0%"Unavailable": 0%• Release delay time accuracy:±15% (CD = 3.3 nF)• Output form:
Nch open-drain output
Supply voltage divider block• Output voltage:• Output capacitor (CPM):• Built-in enable circuit:
Overall• Current consumption:• Built-in reverse connection protection circuit:• Operation voltage range:• Operation temperature range:• Lead-free (Sn 100%), halogen-free• Withstand 45 V load dump
• AEC-Q100 qualified*1*1.

VPMOUT = VSENSE/6 (S-19117 Series L / M / N type)VPMOUT = VSENSE/8 (S-19117 Series P / Q / R type)VPMOUT = VSENSE/12 (S-19119 Series L / M / N type)VPMOUT = VSENSE/14 (S-19119 Series P / Q / R type)
A ceramic capacitor can be used (0.1 μF to 0.22 μF).
Ensures long battery life.
During supply voltage divided output operates 1.15 μA typ.
During supply voltage divided output stops
0.75 μA typ.
Reduces current in the SENSE pin during a reverse connection.
3.0 V to 36.0 V
Ta = −40°C to +125°C

Contact our sales representatives for details.

 Applications• Automotive battery voltage detection• For automotive use (engine, transmission, suspension, ABS, related-devices for EV / HEV / PHEV, etc.)

 Packages• HTMSOP-8• HSNT-8(2030)

1

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00
 Block Diagrams
1.

S-19117/19119 Series L / P type
VDD

PMEN
Enable circuit
+

SENSE

PMOUT

−

SW

RO

−

*1

+

Delay
circuit

VREF
*1

*1

*1

*1

VSS

CD

*1.

Parasitic diodeFigure 1

1. 1

S-19117 Series
Table 1

Product TypeL typeP type1. 2

Output Voltage of Supply
Voltage Divider Block (VPMOUT)VSENSE/6
VSENSE/8

Hysteresis Width

PMEN Pin
Input Logic

0%0%

Active "H"
Active "H"

RO PinOutput FormNch open-drain output
Nch open-drain output

RO Pin Output
Logic
Active "L"
Active "L"

S-19119 Series
Table 2

Product TypeL typeP type2

Output Voltage of Supply
Voltage Divider Block (VPMOUT)VSENSE/12
VSENSE/14

Hysteresis Width

PMEN Pin
Input Logic

0%0%

Active "H"
Active "H"

RO PinOutput FormNch open-drain output
Nch open-drain output

RO Pin Output
Logic
Active "L"
Active "L"AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series
2.

S-19117/19119 Series M / N / Q / R type
VDD

PMEN
Enable circuit
+

SENSE

PMOUT

−

SW

RO
Delay
circuit

−
+

*1

VREF
*1

*1

*1

*1

VSS

CD

*1.

Parasitic diodeFigure 2

2. 1

S-19117 Series
Table 3

Product TypeM typeN typeQ typeR type2. 2

Output Voltage of Supply
Voltage Divider Block (VPMOUT)VSENSE/6
VSENSE/6
VSENSE/8
VSENSE/8

Hysteresis Width

PMEN Pin
Input Logic

5.0%
10.0%
5.0%
10.0%

Active "H"
Active "H"
Active "H"
Active "H"

RO PinOutput FormNch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output

RO Pin Output
Logic
Active "L"
Active "L"
Active "L"
Active "L"

S-19119 Series
Table 4

Product TypeM typeN typeQ typeR typeOutput Voltage of Supply
Voltage Divider Block (VPMOUT)VSENSE/12
VSENSE/12
VSENSE/14
VSENSE/14

Hysteresis Width

PMEN Pin
Input Logic

5.0%
10.0%
5.0%
10.0%

Active "H"
Active "H"
Active "H"
Active "H"

RO PinOutput FormNch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output

RO Pin Output
Logic
Active "L"
Active "L"
Active "L"
Active "L"3

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00
 AEC-Q100 Qualified
This IC supports AEC-Q100 for operation temperature grade 1.
Contact our sales representatives for details of AEC-Q100 reliability specification.

 Product Name Structure
1.

Product name
S-1911 x x

xx A - xxxx U

7Environmental codeU:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
S8T1: HTMSOP-8, Tape
A8T1: HSNT-8(2030), Tape
Operation temperatureA:
Ta = −40°C to +125°C
Detection voltage
40 to A0(e.g., when the detection voltage is 4.0 V,
it is expressed as 40.
when the detection voltage is 10.0 V,
it is expressed as A0.)
Product type*2
Output voltage of supply voltage divider block*2
7:
VPMOUT = VSENSE/6
VPMOUT = VSENSE/8
9:VPMOUT = VSENSE/12
VPMOUT = VSENSE/14
*1.
*2.

4

Refer to the tape drawing.
Refer to "2. Function list of product types".

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series
2.

Function list of product types
2. 1

S-19117 Series
Table 5

Product Type

Output Voltage of Supply
Voltage Divider Block (VPMOUT)

L typeM typeN typeP typeQ typeR typeVSENSE/6
VSENSE/6
VSENSE/6
VSENSE/8
VSENSE/8
VSENSE/8

2. 2

Hysteresis Width

PMEN Pin
Input Logic

0%
5.0%
10.0%
0%
5.0%
10.0%

Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"

RO PinOutput FormNch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output

RO Pin Output
Logic
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"

S-19119 Series
Table 6

Product Type

Output Voltage of Supply
Voltage Divider Block (VPMOUT)

L typeM typeN typeP typeQ typeR type3.

VSENSE/12
VSENSE/12
VSENSE/12
VSENSE/14
VSENSE/14
VSENSE/14

Hysteresis Width

PMEN Pin
Input Logic

0%
5.0%
10.0%
0%
5.0%
10.0%

Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"

RO PinOutput FormNch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output

RO Pin Output
Logic
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"

Packages
Table 7 Package Drawing Codes
Package NameHTMSOP-8
HSNT-8(2030)

Dimension
FP008-A-P-SD
PP008-A-P-SD

Tape
FP008-A-C-SD
PP008-A-C-SD

Reel
FP008-A-R-SD
PP008-A-R-SD

Land
FP008-A-L-SD
PP008-A-L-SD

5

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00
 Pin Configurations
1.

HTMSOP-8
Top view

Table 8

1
2
3
4

8
7
6
5
Bottom view
1
2
3
4

8
7
6
5

Pin No.

SymbolDescription

1
2
3
4
5
6
7
8

PMEN
VDD
PMOUT
SENSE
CD*2
VSS
RO
NC*3

Supply voltage divided output enable pin
Voltage input pin
Supply voltage divided output pin
Detection voltage input pin
Connection pin for release delay time adjustment capacitor
GND pin
Voltage detection output pin
No connection*1

Figure 3
*1.
*2.

*3.

2.

Connect the heat sink of backside at shadowed area to the board, and set electric potential GND.
However, do not use it as the function of electrode.
Connect a capacitor between the CD pin and the VSS pin. The release delay time can be adjusted according to
the capacitance.
Moreover, the CD pin is available even when it is open.
The NC pin is electrically open.
The NC pin can be connected to the VDD pin or the VSS pin.

HSNT-8(2030)
Top view
1

Table 98

4

5

Bottom view
8

1

5

4
*1

Pin No.

SymbolDescription

1
2
3
4
5
6
7
8

PMEN
VDD
PMOUT
SENSE
CD*2
VSS
RO
NC*3

Supply voltage divided output enable pin
Voltage input pin
Supply voltage divided output pin
Detection voltage input pin
Connection pin for release delay time adjustment capacitor
GND pin
Voltage detection output pin
No connection

Figure 4
*1.
*2.

*3.

6

Connect the heat sink of backside at shadowed area to the board, and set electric potential GND.
However, do not use it as the function of electrode.
Connect a capacitor between the CD pin and the VSS pin. The release delay time can be adjusted according to
the capacitance.
Moreover, the CD pin is available even when it is open.
The NC pin is electrically open.
The NC pin can be connected to the VDD pin or the VSS pin.

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series
 Absolute Maximum Ratings
Table 10
(Ta = −40°C to +125°C unless otherwise specified)
Item

SymbolVDD

Unit
V
S-19117 Series L / M / N typeV
S-19117 Series P / Q / R typeV
SENSE pin voltage
VSENSE
S-19119 Series L / M / N typeV
S-19119 Series P / Q / R typeV
CD pin input voltage
VCD
V
PMEN pin input voltage
VPMEN
V
Detector block
VRO
V
Output voltage
Supply voltage divider block
VPMOUT
V
IOUT
mA
Output current
IPMOUTmA
Junction temperature
Tj°C
Operation ambient temperature
Topr°C
Storage temperature
Tstg°C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physicaldamage. These values must therefore not be exceeded under any conditions.
Power supply voltage

Absolute Maximum Rating
VSS − 0.3 to VSS + 45.0
VSS − 30.0 to VSS + 42.0
VSS − 30.0 to VSS + 45.0
VSS − 30.0 to VSS + 45.0
VSS − 30.0 to VSS + 45.0
VSS − 0.3 to VDD + 0.3 ≤ VSS + 7.0
VSS − 0.3 to VSS + 45.0
VSS − 0.3 to VSS + 45.0
VSS − 0.3 to VDD + 0.3 ≤ VSS + 7.0
25
2−40 to +150
−40 to +125
−40 to +150

 Thermal Resistance Value
Table 11
Item

SymbolCondition

Board A
Board B
Board CHTMSOP-8
Board D
Board E
Junction-to-ambient thermal resistance*1 θJA
Board A
Board B
HSNT-8(2030) Board C
Board D
Board E
*1. Test environment: compliance with JEDEC STANDARD JESD51-2A
Remark

Min.
−
−
−
−
−
−
−
−
−
−

Typ.
159
113
39
40
30
181
135
40
42
32

Max.
−
−
−
−
−
−
−
−
−
−

Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W

Refer to " Power Dissipation" and "Test Board" for details.

7

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00
 Electrical Characteristics
1.

Detector block
Table 12
(Ta = −40°C to +125°C unless otherwise specified)
Item

SymbolCondition

Min.

Typ.

Max.

Unit

Test
CircuitVDD = 13.5 V,
VDET(S)
VDET(S)
VDET(S)V
1
4.0 V ≤ VDET(S) ≤ 10.0 V
× 0.985
× 1.015
L / P type
VDET
−
−
V
1
× 0.00(VHYS = 0%)
M / Q type
VDET
VDET
VDET
Hysteresis width*2
VHYS
V1
× 0.04
× 0.05× 0.06(VHYS = 5.0%)
N / R type
VDET
VDET
VDET
V
1
× 0.09× 0.10× 0.11(VHYS = 10.0%)−−
Operation voltage
VDD
3.0
36.0
V
1
RO pin Nch driver,
−
−
0.60
mA
2
Output current
IOUT
VDD = 3.0 V, VDS*3 = 0.1 V,
VSENSE = VDET(S) − 1 V
RO pin Nch driver,−−μA
Leakage current
ILEAK
VDD = 36 V, VRO = 36 V,
2.0
2
VSENSE = 13.5 V−−
μs
Detection response time*4
tRESET
80
200
3
Release delay time*5
tDELAYCD = 3.3 nF
8.5
10.0
11.5
ms
3
−
MΩ
SENSE pin resistance
RSENSE VPMEN = 0 V
6.8
200
7
−
kΩ
−
CD pin discharge ON resistance RCDD
VDD = 3.0 V, VCD = 0.7 V
0.15
0.90
*1. VDET: Actual Voltage detection voltage value, VDET(S): Set voltage detection voltage value*2. The release voltage (VREL) is as follows.
L / P type (hysteresis width "Unavailable"):VREL = VDET
M / N / Q / R type (hysteresis width "Available"): VREL = VDET + VHYS
*3. VDS: Drain-to-source voltage of the output transistor*4. The time period from when the pulse voltage of VDET(S) + 1.0 V → VDET(S) − 1.0 V is applied to the SENSE pin after
VSENSE reaches the release voltage once, until VRO reaches 50% of VDD.
*5. VREL(S): Set release voltage value
The time period from when the pulse voltage of VREL(S) − 1.0 V → VREL(S) + 1.0 V is applied to the SENSE pin to when
VRO reaches 50% of VDD.
Detection voltage*1

8

VDET

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series
2.

Supply voltage divider block
Table 13
(Ta = −40°C to +125°C unless otherwise specified)
Item

SymbolInput voltage
SENSE pin voltage

VDD
VSENSE−VSENSE/6
output product
VSENSE/8
output product
VSENSE/12
output product

Typ.

Max.

Unit

3.0
5.0

−
−

36.0
36.0

V
V

Test
Circuit
−
−

V

4

V

4

V

4

VPMOUT(S)× 1.020VPMOUT(S)VSENSE/8
× 1.025
VPMOUT(S)VSENSE/12
× 1.030VPMOUT(S)× 0.966

VSENSE/14

VPMOUT(S)× 1.034

V

4

−10

−

10

μA

4

−3

−

3

μA

4

−

−

1000

Ω

4

−

15

30

ms

5

1.3

−

−

V

6

−

−

0.3

V

6

0.00
−0.1

−
−

0.50
0.1

μA
μA

6
6

RPMSENSE VPMEN = VDD

5.8

−

140

MΩ

7

RPLOW

−

2.8

−

kΩ

8

IPMOUT

Output impedance

RPS

Set-up time*2

tPU

PMEN pin input voltage "H"

VPSHPMEN pin input voltage "L"

VPSLPMEN pin input current "H"
PMEN pin input current "L"SENSE pin resistanceduring operation of
supply voltage divider block
Discharge shunt resistanceduring power-off

IPSH
IPSL

*1.

VDD ≥ VSENSE − 2.0 V

Min.

VPMOUT(S)× 0.980
VPMOUT(S)× 0.975
VPMOUT(S)× 0.970

Output voltage of
VPMOUT
supply voltage divider block*1

Load current

Condition

3.0 V ≤ VDD ≤ 18.0 V,
5.0 V ≤ VSENSE ≤ 18.0 V,−10 μA ≤ IPMOUT ≤ 10 μA

3.0 V ≤ VDD ≤ 18.0 V,
VSENSE/14
5.0 V ≤ VSENSE ≤ 18.0 V,
output product−3 μA ≤ IPMOUT ≤ 3 μA
VSENSE/6 output product,
VSENSE/8 output product,
VSENSE/12 output product
VSENSE/14 output product
3.0 V ≤ VDD ≤ 18.0 V,
5.0 V ≤ VSENSE ≤ 18.0 V
VDD = 18.0 V, VSENSE = 18.0 V,
CPM = 0.22 μF, no load, tr = 1.0 μs
VDD = 18.0 V,
determined by VPMOUT output level
VDD = 18.0 V,
determined by VPMOUT output level
VDD = 18.0 V, VPMEN = VDD
VDD = 18.0 V, VPMEN = 0 V

VDD = 13.5 V, VPMEN = 0 V, VPMOUT = 0.1 V

VSENSE/6

VPMOUT: Actual output voltage value of supply voltage divider block,
VPMOUT(S): Set output voltage value of supply voltage divider block
Set-up time shows the time period from when the input voltage reaches 50% until the output voltage of supply voltage
divider block rises to 99%, when the PMEN pin is set to ON (tr = 1.0 μs).

*2.

3.

Overall
Table 14
(Ta = −40°C to +125°C unless otherwise specified)
Item

SymbolISS1Current consumption
ISSP1

Condition
During supply voltage divided output stops,
VDD = 13.5 V, VSENSE = 13.5 V,
VPMEN = 0 V
During supply voltage divided output operates,
VDD = 13.5 V, VSENSE = 13.5 V,
VPMEN = VDD, no load

Min.

Typ.

Max.

Unit

Test
Circuit

−

0.75

3.0

μA

7

−

1.15

5.4

μΑ

7

9

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00
 Test Circuits
R
100 kΩ

VDD
PMEN
*1

SENSE

PMOUT
RO

VSS

CD

+
V

*1.

VDD
PMEN
*1

+
V

Set to ON

*1.

*1

*1.

PMEN
*1

Oscilloscope

CD

VSS

Set to ON

*1.

VSS

SENSE

PMOUT
RO

VSS

CD

+

A

+
V

↓

Figure 8 Test Circuit 4

VDD

VDD

+

A

PMOUT

SENSE

+
V

Set to ON

Figure 7 Test Circuit 3

PMEN

CD

VDD

PMOUT
RO

SENSE

VSS

+

A

Figure 6 Test Circuit 2R
100 kΩ

PMEN

PMOUT
RO

Set to ON

Figure 5 Test Circuit 1

VDD

SENSE

RO

Oscilloscope

PMEN

PMOUT

SENSE

*1

CD

+ VSS

RO

+

CD

V

V

*1.

Set to ON or OFF

Figure 9 Test Circuit 5

Figure 10 Test Circuit 6
VDD

VDD
+

A
+
*1

PMEN
A

SENSE
+
V

*1.

PMOUT

VSS

RO

PMEN

Set to ON or OFF

*1

VSS

*1.

PMOUT

SENSE

CD

Figure 11 Test Circuit 7

10

+

A

+

A

RO
CD

Set to OFF
Figure 12 Test Circuit 8+VAUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series
 Standard Circuit
VDD
PMEN

R1*3

SENSE

PMOUT
RO

VSS

CD
CD*1

*1.

CPM*2

CD is a release delay time adjustment capacitor. The CD should be connected directly to the CD pin and the VSS
pin.
CPM is a capacitor for stabilizing the output. The CPM should be connected directly to the PMOUT pin and the
VSS pin.
R1 are the external pull-up resistors for the reset output pin.

*2.
*3.

Figure 13
Caution

The above connection diagram and constants will not guarantee successful operation. Perform thoroughevaluation including the temperature characteristics with an actual application to set the constants.

 Condition of Application
Release delay time adjustment capacitor (CD): A ceramic capacitor with capacitance of 1.0 nF or more is recommended.
Supply voltage divider block output capacitor (CPM): A ceramic capacitor with capacitance of 0.1 μF to 0.22 μF is
recommended.
Caution 1.
2.

The CD pin is available even when it is open.
Refer to "1. Power on sequence" in " Usage Precautions" when using it open.
Generally, in a supply voltage divider, an oscillation may occur depending on the selection of theexternal parts. Perform thorough evaluation including the temperature characteristics with anactual application using the above capacitors to confirm no oscillation occurs.

 Selection of Release Delay Time Adjustment Capacitor (CD)In this IC, the release delay time adjustment capacitor (CD) is necessary between the CD pin and the VSS pin to adjust
the release delay time (tDELAY) of the detector. Refer to "1. 4 Delay circuit" in " Operation" for details.
Caution

Perform thorough evaluation including the temperature characteristics with an actual application to
select CD.

 Selection of Supply Voltage Divider Block Output Capacitor (CPM)
This IC requires CPM between the PMOUT pin and the VSS pin for phase compensation.
The operation is stabilized by a ceramic capacitor with capacitance of 0.1 μF to 0.22 μF. When using an OS capacitor, atantalum capacitor or an aluminum electrolytic capacitor, the capacitance also must be 0.1 μF to 0.22 μF. However, an
oscillation may occur depending on the equivalent series resistance (ESR).
Caution

Perform thorough evaluation including the temperature characteristics with an actual application to
select CPM.

11

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00
 Explanation of Terms
1.

Detector block
1. 1

Detection voltage (VDET)The detection voltage is a SENSE pin voltage at which the output voltage in Figure 16 turns to "L". The detection
voltage varies slightly among products of the same specification. The variation of detection voltage between thespecified minimum and the maximum is called the detection voltage range (Refer to "Figure 14 Detection
Voltage").
Example: In VDET = 4.0 V product, the detection voltage is at any point in the range of 3.940 V ≤ VDET ≤ 4.060 V.
This means that some VDET = 4.0 V product has VDET = 3.940 V and some has VDET = 4.060 V.
1. 2

Release voltage (VREL)

The release voltage is a SENSE pin voltage at which the output voltage in Figure 16 turns to "H". The releasevoltage varies slightly among products of the same specification. The variation of release voltage between thespecified minimum and the maximum is called the release voltage range (Refer to "Figure 15 Release Voltage").
The release voltage becomes the value differs from the detection voltage within the range shown below.
• M / Q type: 4% to 6% (5% typ.)• N / R type: 9% to 11% (10% typ.)Example: For N / R type, VDET = 4.0 V product, the release voltage is at any point in the range of 4.294 V ≤ VREL ≤4.507 V despite VREL = 4.400 V typ.
This means that some N / R type, VDET = 4.0 V product has VREL = 4.294 V and some has VREL = 4.507 V.

12

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series

Release voltage

Detection voltage

VSENSEVDET max.

VREL max.

Detection voltage
range

VDET min.

Release voltage
range

VREL min.
VSENSEtRESET
VRO

tDELAY

VRO

Figure 14 Detection Voltage

Figure 15 Release Voltage

VDD

VDD PMEN
PMOUT
SENSE
RO

+
V
VSENSE

VSS

CD

R1
100 kΩ+V
CPM

Figure 16 Test Circuit of Detection Voltage and Release Voltage
1. 3

Hysteresis width (VHYS)

The hysteresis width is the voltage difference between the detection voltage (VDET) and the release voltage (VREL).
Voltage difference between VREL and VDET is the hysteresis width (VHYS*1) of the RO pin. Setting the hysteresis width
between VDET and VREL, prevents malfunction caused by noise on the input voltage.
*1.
1. 4

Refer to "1. 2

S-19117/19119 Series M / N / Q / R type" in "■ Operation" for details.

Feed-through current

The feed-through current is a current that flows instantaneously to the VDD pin at the time of detection and releaseof a voltage detector.

13

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00
2.

Supply voltage divider block
2. 1

Supply voltage divided output

The supply voltage divided output is a function that divides the SENSE pin voltage (VSENSE) into VSENSE/6, VSENSE/8,
VSENSE/12 or VSENSE/14 and outputs the voltage.
For example, a microcontroller can monitor a battery voltage by inputting the output voltage of supply voltage divider
block (VPMOUT) to the microcontroller A/D converter.
2. 2

Output voltage of supply voltage divider block (VPMOUT)

This is the voltage of the divided VSENSE. The following voltages are the outputs.
• S-19117 Series L / M / N type: VSENSE/6• S-19117 Series P / Q / R type: VSENSE/8• S-19119 Series L / M / N type: VSENSE/12• S-19119 Series P / Q / R type: VSENSE/14
This voltage is the output in accuracy range of between ±2.0% and ±3.4%*1 when the power supply voltage, VSENSE,
temperature and load current satisfy a certain condition*1.
*1. Differs depending on the product type.
Example: For S-19117 Series L / M / N type, VSENSE = 15.0 V, the output voltage of supply voltage divider block is
at any point in the range of 2.450 V ≤ VPMOUT ≤ 2.550 V.
This means that some S-19117 Series L / M / N type has VPMOUT = 2.450 V and some has VPMOUT = 2.550 V.
Caution

2. 3

If the certain condition is not satisfied, the output voltage may exceed the accuracy range.
Refer to Table 13 of " Electrical Characteristics" for details.

Output impedance (RPS)This is the supply voltage divider block impedance. It shows how much output offset voltage changes when the load
current changes.
For example, the output impedance can be used in sampling rate calculation as signal source impedance when
VPMOUT from the PMOUT pin is input to the A/D converter as a microcontroller input signal.
2. 4

Set-up time (tPU)

This is the time from when the supply voltage divided output is operated until VPMOUT stabilizes.
2. 5

Discharge shunt resistance during power-off (RPLOW)

This is the ON resistance of the N-channel transistor built into the supply voltage divider block.
When the supply voltage divided output is stopped, VPMOUT is set to the VSS level by the built-in N-channel transistor.

14

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series
 Operation1.

Detector block
Figure 17 and Figure 19 show that the RO pin being pulled up by resistors (R1) is an example of basic detector block
operation.
1. 1

S-19117/19119 Series L / P type(1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage(VSENSE) is the release voltage (VREL) or higher, the Nch transistor is turned off to output VDD ("H") when the output
is pulled up.
(RB + RC ) • VSENSEAt this time, the input voltage to the comparator is.
RA + RB + RC
(2) When VSENSE decreases to the detection voltage (VDET) or lower (point A in Figure 18), the Nch transistor isturned on. And then VSS ("L") is output from the RO pin after the elapse of the detection response time (tRESET).
(3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the RO pin isstable when VDD is minimum operation voltage or higher.
(4) Even if VSENSE increases, VSS is output when VSENSE is lower than VREL.
(5) When VSENSE increases to VREL or higher (point B in Figure 18), the Nch transistor is turned off. And then VDD is
output from the RO pin after the elapse of the release delay time (tDELAY) when the output is pulled up.

R1
VDD

100 kΩ

PMEN
Enable circuit

SENSE

PMOUT

+
−

SW

RA

−
VDD VPMEN VSENSE

+

RO

VRO
CPM

Delay
circuit

*1

RB
VREF
VSS

*1

RC

*1

*1

*1

+
V

+
V

CD
CD

*1. Parasitic diodeFigure 17 Operation of S-19117/19119 Series L / P type15

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00(1)Detection voltage (VDET)(2)
A(3) (4)(5)

B

Release voltage (VREL)VSENSE
Minimum operation voltage
VSS
VDD
Output from RO pin

VSStRESETtDELAY

Remark The release voltage is set to the same value as the detection voltage, since there is no hysteresis width.
Figure 18 Timing Chart of S-19117/19119 Series L / P Type

16

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series
1. 2

S-19117/19119 Series M / N / Q / R type(1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage(VSENSE) is the release voltage (VREL) or higher, the Nch transistor is turned off to output VDD ("H") when the output
is pulled up.
(RB + RC ) • VSENSE
Since the Nch transistor (N1) is turned off, the input voltage to the comparator is.
RA + RB + RC
(2) Even if VSENSE decreases to VREL or lower, VDD is output when VSENSE is higher than the detection voltage (VDET).
When VSENSE decreases to VDET or lower (point A in Figure 20), the Nch transistor is turned on. And then VSS ("L")
is output from the RO pin after the elapse of the detection response time (tRESET).
RB • VSENSEAt this time, N1 is turned on, and the input voltage to the comparator is.
RA + RB(3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the RO pin isstable when VDD is minimum operation voltage or higher.
(4) Even if VSENSE exceeds VDET, VSS is output when VSENSE is lower than VREL.
(5) When VSENSE increases to VREL or higher (point B in Figure 20), the Nch transistor is turned off. And then VDD is
output from the RO pin after the elapse of the release delay time (tDELAY) when the output is pulled up.

R1
VDD

100 kΩ

PMEN
Enable circuit

SENSE

PMOUT

+
−

SW

RO

RA
−

VDD VPMEN VSENSE

CPM

Delay
circuit

+

VRO

*1

RB
N1

VREF
VSS

*1

RC

*1

*1

*1

+
V

+
V

CD
CD

*1. Parasitic diodeFigure 19 Operation of S-19117/19119 Series M / N / Q / R type17

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00

(1)

(2)

(3)

(4)

(5)

B

Hysteresis width
A(VHYS)

Release voltage (VREL)
Detection voltage (VDET)VSENSE

Minimum operation voltage
VSS
VDD
Output from RO pin

VSStRESETtDELAY

Figure 20 Timing Chart of S-19117/19119 Series M / N / Q / R Type18

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series
1. 3

SENSE pin

The SENSE pin is the input pin for the detection voltage. The power supply VDD pin and SENSE pin, for voltage
detection, are divided. Therefore, as long as a voltage is supplied to the VDD pin, the reset signal will be held even
if the input voltage to the SENSE pin drops below the minimum operation voltage. Also, the SENSE pin of this IC
has a built-in reverse connection protection circuit. Even when the SENSE pin voltage is less than the VSS pin
voltage, the voltage flowing from the VSS pin to the SENSE pin is reduced to 0.05 mA typ.
1. 3. 1

Error when detection voltage is set externally

The detection voltage can be set externally by connecting a node that was resistance-divided by the resistor (RA)and the resistor (RB) to the SENSE pin as shown in Figure 21.
For conventional products without the SENSE pin, external resistor cannot be too large since theresistance-divided node must be connected to the VDD pin. This is because a feed-through current will flow
through the VDD pin when it goes from detection to release, and if external resistor is large, problems such as
oscillation or larger error in the hysteresis width may occur.
In this IC, RA and RB in Figure 21 are easily made larger since the resistance-divided node can be connected to
the SENSE pin through which no feed-through current flows. However, be careful of error in the current flowing
through the internal resistance (RSENSE) that will occur.
Although RSENSE*1 in this IC is large to make the error small, RA and RB should be selected such that the error iswithin the allowable limits.
Please note that the supply voltage divided output is a function to divide and output the SENSE pin voltage sowhen the detection voltage is set externally, care is required as the supply voltage divider block output voltage
will change.
*1. During supply voltage divided output stops: 6.8 MΩ min.
During supply voltage divided output operates: 5.8 MΩ min.

19

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00
1. 3. 2

Selection of RA and RB

In Figure 21, the relation between the external setting detection voltage (VDX) and the actual detection voltage(VDET) is ideally calculated by the equation below.
RA
VDX = VDET × (1 + R ) ·········································(1)B

However, in reality there is an error in the current flowing through RSENSE.
When considering this error, the relation between VDX and VDET is calculated as follows.
RA
VDX = VDET × (1 + R || R
)
B
SENSE
RA

= VDET × 1 +
 RB × RSENSE  RB + RSENSE RARA× VDET ················(2)= VDET × (1 + R ) + R
B
SENSE
By using equations (1) and (2), the error is calculated as VDET × R

RA

SENSE

.

The error rate is calculated as follows by dividing the error by the right-hand side of equation (1).
RA || RB
RA × RB
× 100 [%] = R
× 100 [%] ····(3)SENSE
RSENSE × (RA + RB)
As seen in equation (3), the smaller the resistance values of RA and RB compared to RSENSE, the smaller the error
rate becomes.
Also, the relation between the external setting hysteresis width (VHX) and the hysteresis width (VHYS) is calculated
by equation below. Error due to RSENSE also occurs to the relation in a similar way to the detection voltage.
RA
VHX = VHYS × (1 + R ) ··········································(4)
B

A

VDX

RA
VDET

VDD
SENSE

RO

RSENSERB

VSS

Figure 21 Detection Voltage External Setting Circuit
Caution20

If RA and RB are large, the SENSE pin input impedance becomes higher and may cause a
malfunction due to noise. In this case, connect a capacitor between the SENSE pin and the
VSS pin.

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series
1. 4

Delay circuit

The delay circuit has a function that adjusts the release delay time (tDELAY) from when the SENSE pin voltage(VSENSE) reaches the release voltage (VREL = VDET + VHYS) or higher to when the output from RO pin inverts.
tDELAY is determined by the delay coefficient, the release delay time adjustment capacitor (CD) and the release delay
time when the CD pin is open (tDELAY0). They are calculated by the equations below.
tDELAY [ms] = Delay coefficient × CD [nF] + tDELAY0 [ms]Table 15
Operation
Temperature
Ta = +125°C
Ta = +105°C
Ta = +25°C
Ta = −40°C

Min.

Delay Coefficient
Typ.

Max.

2.65
2.71
2.92
2.65

3.03
3.05
3.06
3.09

3.41
3.35
3.14
3.41

Table 16
Operation
Temperature
Ta = +125°C
Ta = +105°C
Ta = +25°C
Ta = −40°C
Caution 1.

2.

3.

Release Delay Time when CD Pin is Open (tDELAY0)
Min.
Typ.
Max.
0.05
0.05
0.06
0.06

0.09
0.10
0.11
0.13

0.17
0.17
0.19
0.25

Mounted board layout should be made in such a way that no current flows into or flows fromthe CD pin since the impedance of the CD pin is high, otherwise correct delay time cannot beprovided.
There is no limit for the capacitance of CD as long as the leakage current of the capacitor canbe ignored against the built-in constant current value (approximately 160 nA). The leakage
current may cause error in delay time. When the leakage current is larger than the built-in
constant current, no detect or release takes place.
The above equations will not guarantee successful operation. Determine the capacitance of CD
through thorough evaluation including temperature characteristics in the actual usage
conditions.

21

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00
2.

Supply voltage divider block
2. 1

Basic operation

Figure 22 shows the block diagram of the supply voltage divider block to describe basic operation.
Reference voltage (Vrefpm) is generated by dividing the SENSE pin voltage (VSENSE) using the dividing resistance(Rpm1 and Rpm2). Since the buffer amplifier constitutes a voltage follower, it can perform the feedback control so thatthe output voltage of supply voltage divider block (VPMOUT) and Vrefpm are the same. Low output impedance isrealized by the buffer amplifier, while outputting VPMOUT according to VSENSE.
When "L" is input to the PMEN pin, the current which flows to Rpm1 and Rpm2 and the current which flows to thebuffer amplifier can be stopped. The buffer amplifier output is pulled down to VSS by the built-in N-channel transistor,and VPMOUT is set to the VSS level.

SENSE

VDD

SW
Rpm1
Vrefpm

+
−

Rpm2
PMEN

Enable circuit

VSS
Figure 22

22

PMOUT

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series
2. 2

PMEN pin

Input to the PMEN pin controls the internal circuit in the supply voltage divided output, and it starts or stops the
supply voltage divided output.
When the PMEN pin is set to "L" level, the internal circuit stops operating, reducing current consumption significantly.
In addition, the PMEN pin has absolutely no effect on the operation of the detector block.
Note that the current consumption increases when a voltage of 0.8 V to VDD min. − 0.3 V is applied to the PMEN pin.
The PMEN pin is configured as shown in Figure 23.
Since the PMEN pin is internally pulled down to the VSS pin in the floating status, the PMOUT pin is set to the VSS
level. When the PMEN pin is set to "H" level, PMEN pin input current "H" (IPSH) in Table 13 of " Electrical
Characteristics" flows through the PMEN pin and care is required.
Table 17
Product Type
L/M/N/P/Q/R
L/M/N/P/Q/R*1.
*2.

PMEN Pin"H": ON"L": OFFInternal Circuit
OperateStop

PMOUT Pin Output
Constant value*1
Pulled down to VSS*2

Current Consumption
ISSP1
ISS1

The constant value is output due to the operation based on the set output voltage value of supply voltage
divider block.
The buffer amplifier output is pulled down to VSS by the built-in N-channel transistor, and PMOUT pin output is
set to the VSS level due to resistance (RLOW = 2.8 kΩ typ.) of the discharge shunt circuit and a load.
VDD

PMEN

VSS

Figure 23

23

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00
2. 3

PMEN pin voltage and output voltage of supply voltage divider block (VPMOUT)

Figure 24 shows the timing chart of the supply voltage divided output.
When "H" is input to the PMEN pin, the supply voltage divided output operates. When the set-up time (tPU) = 50 ms
max.*1 elapses, VPMOUT stabilizes, the SENSE pin voltage (VSENSE) is divided at the set ratio, and the voltage is
output to the PMOUT pin.
When "L" is input to the PMEN pin, the supply voltage divided output is stopped. VPMOUT is set to the VSS level by thebuilt-in N-channel transistor.
By repeatedly inputting "H" and "L" to the PMEN pin, it is possible to lower current consumption when the supply
voltage divided output is not needed.
*1.

When 5 V ≤ VSENSE ≤ 18 V, CPM = 0.22 μF, no load

VPMENVSENSEt PU

t PU
VPMOUTVPMOUT

Figure 24
Remark VPMEN = VDD ↔ VSS

24

VPMOUT

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series
 Usage Precautions
1.

Power on sequence
Turn on the power in one of the following two procedures.
(1) Order of VDD pin and SENSE pin (Refer to Figure 25)(2) VDD pin and SENSE pin at the same time
When VSENSE ≥ VREL applies, output voltage (VRO) becomes "H", and the detector enters release status.

VDD

VDD min.
VREL

VSENSEtDELAY

VRO

Figure 25
CautionWhen the SENSE pin is turned on before the VDD pin, a release may mistakenly occur even if
VSENSE is less than VREL.

25

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00
2.

SENSE pin voltage glitch (Typical data)
2. 1

Detection operation

Figure 26 shows the relation between pulse width and pulse voltage difference (VOD) where the release status canbe maintained when a pulse equal to or lower than the detection voltage (VDET) is input to the SENSE pin during
release status.
Tj = −40°C to +150°C

Pulse width [µs]1000

Pulse width

100

VIH*1

10
VRO = “H”
1

VSENSE VDET

0.1

VIL*2

VOD
10

100
VOD [mV]

1000

tf = 1 µs*1.
*2.

Figure 26
Caution

2. 2

tr = 1 µs

VIH = 13.5 V
VIL = VDET − VOD

Figure 27 SENSE Pin Input Voltage Waveform

Figure 26 shows the pulse condition which can maintain the release status. If the pulse whose
pulse width and VOD are larger than this condition is input to the SENSE pin, the RO pin may
change to a detection status.

Release operation

Figure 28 shows the relation between pulse width and pulse voltage difference (VOD) where the detection status
can be maintained when a pulse equal to or higher than the release voltage (VREL) is input to the SENSE pin during
detection status.
Tj = −40°C to +150°C

Pulse width [µs]1000

Pulse width

100
VIH*1

10

VOD

VRO = “L”

VSENSE VREL

1
0.1
10

100
VOD [mV]

VIL*2

1000

tr = 1 µs*1.
*2.

Figure 28
Caution26

tf = 1 µs

VIH = VREL + VOD
VIL = VDET − 1.0 V

Figure 29 SENSE Pin Input Voltage Waveform

Figure 28 shows the pulse condition which can maintain the detection status. If the pulse whose
pulse width and VOD are larger than this condition is input to the SENSE pin, the RO pin may
change to a release status.

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series
 Precautions• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• Because the SENSE pin has a high impedance, malfunctions may occur due to noise.
Be careful of wiring adjoining SENSE pin wiring in actual applications.
• In the supply voltage divided output, the values of an overshoot and an undershoot in the output voltage varydepending on the variation factors of input voltage start-up, input voltage fluctuation and load fluctuation etc., or thecapacitance of CPM and the value of the equivalent series resistance (ESR), which may cause a problem to the stable
operation. Perform thorough evaluation including the temperature characteristics with an actual application to selectCPM.
• When designing for mass production using an application circuit described herein, the product deviation andtemperature characteristics should be taken into consideration. ABLIC Inc. shall not bear any responsibility for patent
infringements related to products using the circuits described herein.
• ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.

27

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00
 Characteristics (Typical Data)
Detector block
Detection voltage (VDET), Release voltage (VREL) vs. Temperature (Ta)VDET(S) = 4.0 V, VREL(S) = 4.4 V, VDD = 13.5 V
4.8
VREL
4.6

4.4
4.2
4.0
3.8

VDET

3.6
-40 -25

VDET, VREL [V]

1. 2

1. 3

VDET, VREL [V]

VDET, VREL [V]

1. 1

0

25
50
Ta [°C]

75

100

125

4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8

VDET(S) = 4.0 V, VREL(S) = 4.4 V

VREL
Ta = +25°C
Ta = +125°C
Ta = -40°C
Ta = +25°C Ta = +125°C
VDET0Ta = -40°C
6

12

18
24
VDD [V]

30

36

10.5
10.0
9.5

VDET
0

11
10

100

125

11.2
11.0
10.8
10.6
10.4
10.2
10.0
9.8

VDET(S) = 10.0 V, VREL(S) = 11.0 V

VREL
Ta = -40°C
Ta = +25°C
Ta = +125°C
Ta = +25°C Ta = +125°C
Ta = -40°C
VDET

0

6

12

18
24
VDD [V]

30

36

11
10
9

8
-40 -2502550Ta [°C]75

100

8-40 -25

125

0

25
50
Ta [°C]

75

100

125

Hysteresis width (VHYS) vs. Power supply voltage (VDD)
VDET(S) = 4.0 V, VREL(S) = 4.4 V

VDET(S) = 10.0 V, VREL(S) = 11.0 V

1212Ta = -40°C

11

Ta = +25°C

VHYS [%]

VHYS [%]

75

VDET(S) = 10.0 V, VREL(S) = 11.0 V, VDD = 13.5 V
12

9

10
Ta = +125°C

9
8

28

25
50
Ta [°C]

Hysteresis width (VHYS) vs. Temperature (Ta)VHYS [%]

VHYS [%]

11.0

Detection voltage (VDET), Release voltage (VREL) vs. Power supply voltage (VDD)

VDET(S) = 4.0 V, VREL(S) = 4.4 V, VDD = 13.5 V
12

1. 4

VDET(S) = 10.0 V, VREL(S) = 11.0 V, VDD = 13.5 V
12.0
VREL
11.5

9.0
-40 -25

VDET, VREL [V]

1.

0

6

12

18
24
VDD [V]11

Ta = -40°C

10
9

30

36

Ta = +25°C

8

Ta = +125°C
0

6

12

18
24
VDD [V]

30

36

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series
1. 5

Nch transistor output current (IOUT) vs. VDS
VDET(S) = 4.0 V, VSENSE = 3.0 V, Ta = −40°C
10

VDD = 36.0 V

68
IOUT [mA]

8
IOUT [mA]

VDET(S) = 4.0 V, VSENSE = 3.0 V, Ta = +25°C
10

VDD = 13.5 V

42

VDD = 36.0 V

6VDD = 13.5 V

42

VDD = 3.0 V

0

VDD = 3.0 V

0
0.0

0.1

0.2

0.3
0.4
VDS [V]

0.5

0.6

0.0

0.1

0.2

0.3
0.4
VDS [V]

0.5

0.6

VDET(S) = 4.0 V, VSENSE = 3.0 V, Ta = +125°C
10

IOUT [mA]8

VDD = 36.0 V

6VDD = 13.5 V

4

VDD = 3.0 V

2
0
0.0

0.1

0.2

0.3
0.4
VDS [V]

0.5

0.6

Remark VDS: Drain-to-source voltage of the output transistor
1. 6

Nch transistor output current (IOUT) vs. Power supply voltage (VDD)

IOUT [mA]

VDET(S) = 4.0 V, VDS = 0.1 V, VSENSE = 3.0 V
1.5

1.0

Ta = -40°C

Ta = +25°C

0.5
Ta = +125°C
0.0
0

6

12

18
24
VDD [V]

30

36

Remark VDS: Drain-to-source voltage of the output transistor
Output voltage (VRO) vs. SENSE pin voltage (VSENSE)
VDET(S) = 4.0 V, VREL(S) = 4.4 V, VDD = 3.0 V,
pull-up to VDD, pull-up resistance: 100 kΩ
4

VDET(S) = 4.0 V, VREL(S) = 4.4 V, VDD = 3.0 V,
pull-up to 16.0 V, pull-up resistance: 100 kΩ
20

3

15

Ta = -40°C

VRO [V]

VRO [V]

1. 7

Ta = +25°C

2

Ta = +125°C
10

Ta = -40°C
Ta = +25°C

10

Ta = +125°C
5

0

1

2

3
VSENSE [V]

4

5

6

0

0

1

2

3
4
VSENSE [V]

5

6

29

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00
Dynamic response vs. Output pin capacitance (COUT) (CD pin; open)

Response time [ms]10

VDET(S) = 4.0 V, VREL(S) = 4.4 V,
VDD = 13.5 V, Ta = −40°C

Response time [ms]Response time [ms]

1. 8

tPLH

1
0.1
0.01
0.001
0.00001

10tPHL
0.00010.001
COUT [µF]

0.01

0.1

VDET(S) = 4.0 V, VREL(S) = 4.4 V,
VDD = 13.5 V, Ta = +25°C

10

tPLH

1
0.1
0.01

tPHL

0.001
0.00001

0.00010.001
COUT [µF]

0.01

0.1

VDET(S) = 4.0 V, VREL(S) = 4.4 V,
VDD = 13.5 V, Ta = +125°C

tPLH

1
0.1
0.01
0.001
0.00001

tPHL
0.00010.001
COUT [µF]

0.01

0.1

1 µs

1 µs

VIH*1
VSENSE
VIL*2

tPLH

tPHL

VDD1
VRO

*1.
*2.

VDD1 × 50%

VDD1 × 50%

VIH = VDET(S) + 1.0 V
VIL = VDET(S) − 1.0 V
Figure 30 Test Condition of Response TimeR
100 kΩVDD

VSENSE

RO

SENSE

VDD
V

+

VSS

CD
V

+

VDD1

Figure 31 Test Circuit of Response Time
Caution30

The above connection diagram and constants will not guarantee successful operation. Perform thoroughevaluation including the temperature characteristics with an actual application to set the constants.

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series
Supply voltage divider block2. 1

Output voltage of supply voltage divider block (VPMOUT) vs. Load current (IPMOUT)

2. 1. 1VPMOUT = VSENSE/6

2. 1. 2VSENSE = 5.0 V, VDD = 3.0 V, VPMEN = 3.0 V

1.2

VPMOUT [V]Ta = +125°C

0.4

0.8
0.4
0.2

0.0
-10

0.0

-5

0
IPMOUT [µA]510Ta = +25°C

Ta = -40°C

0.6

0.2

Ta = +125°C
-3

-2

-1

0
1
IPMOUT [µA]23

Output voltage of supply voltage divider block (VPMOUT) vs. Temperature (Ta)2. 2. 1VPMOUT = VSENSE/6

2. 2. 2VPMOUT = VSENSE/14

VSENSE = 5.0 V, VDD = 3.0 V, VPMEN = 3.0 V
0.88

VSENSE = 5.0 V, VDD = 3.0 V, VPMEN = 3.0 V
0.40

0.86

0.38

IPMOUT = 10 µA

0.84

IPMOUT = 0 µA

VPMOUT [V]VPMOUT [V]
2. 2

1.0

0.8
0.6

VPMOUT = VSENSE/14

VSENSE = 5.0 V, VDD = 3.0 V, VPMEN = 3.0 V
1.2

Ta = +25°C

Ta = -40°C

1.0

VPMOUT [V]

2.

0.82
0.80
0.78
-40 -252550
Ta [°C]

75

100

125

IPMOUT = 0 µA

0.36
0.34
IPMOUT = -3 µA

0.32

IPMOUT = -10 µA
0

IPMOUT = 3 µA

0.30
-40 -2502550Ta [°C]

75

100

125

31

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00
Output voltage of supply voltage divider block (VPMOUT) vs. SENSE pin voltage (VSENSE)
VPMOUT = VSENSE/6

VPMOUT [V]82

VPMOUT [V]

5

10

15

20

25
VSENSE [V]30

IPMOUT = 0 µA

6

IPMOUT = 10 µA

4
2
0

36

VDD = 36.0 V, VPMEN = 3.0 V, Ta = +25°C

IPMOUT = -10 µA
5

10

15

20
25
VSENSE [V]3036

VDD = 36.0 V, VPMEN = 3.0 V, Ta = +125°C

IPMOUT = 0 µA
IPMOUT = 10 µA

42

2. 3. 2IPMOUT = -10 µA
5

10

15

20
25
VSENSE [V]30

36

VPMOUT = VSENSE/14

4

VPMOUT [V]

IPMOUT = -10 µA

60

VDD = 36.0 V, VPMEN = 3.0 V, Ta = −40°C

IPMOUT = 0 µA

3

IPMOUT = 3 µA

2
1
0

4

VPMOUT [V]

IPMOUT = 10 µA

4

8

8

IPMOUT = 0 µA

6

0IPMOUT = -3 µA
5

10

15

20

25
VSENSE [V]3036

VDD = 36.0 V, VPMEN = 3.0 V, Ta = +125°C

IPMOUT = 0 µA

3

IPMOUT = 3 µA

2
1
0

32

VDD = 36.0 V, VPMEN = 3.0 V, Ta = −40°C

VPMOUT [V]

2. 3. 1IPMOUT = -3 µA
5

10

15

20
25
VSENSE [V]30

4VPMOUT [V]

2. 3

36

VDD = 36.0 V, VPMEN = 3.0 V, Ta = +25°C

IPMOUT = 0 µA

3

IPMOUT = 3 µA

2
1
0

IPMOUT = -3 µA
5

10

15

20
25
VSENSE [V]30

36

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series
Overall
3. 1

Current consumption (ISS1) vs. Temperature (Ta)VDET(S) = 4.0 V, VDD = 13.5 V, VSENSE = 13.5 V,
VPMEN = 0 V (during release)
1.5

VDET(S) = 10.0 V, VDD = 13.5 V, VSENSE = 13.5 V,
VPMEN = 0 V (during release)
1.5

1.2

ISS1 [µA]

ISS1 [µA]

1.2
0.9
0.6
0.3
25
50
Ta [°C]

75

100

0

25
50
Ta [°C]

75

100

125

VDET(S) = 4.0 V, VDD = 13.5 V, VSENSE = 3.0 V,
VPMEN = 0 V (during detection)
1.5

VDET(S) = 10.0 V, VDD = 13.5 V, VSENSE = 9.0 V,
VPMEN = 0 V (during detection)
1.5

1.2

1.2

0.9
0.6

0.9
0.6
0.3

0.0
-40 -2502550Ta [°C]

75

100

0.0
-40 -25

125

0

25
50
Ta [°C]

75

100

125

Current consumption (ISS1) vs. Power supply voltage (VDD) (No load)

VDET(S) = 4.0 V, VDD = 0 V → 36.0 V,
VSENSE = 13.5 V, VPMEN = 0 V (during release)
1.5
Ta = +125°C

VDET(S) = 10.0 V, VDD = 0 V → 36.0 V,
VSENSE = 13.5 V, VPMEN = 0 V (during release)
1.5
Ta = +125°C

1.0

1.0

Ta = +25°C

ISS1 [µA]

ISS1 [µA]0.60.0-40 -25125

ISS1 [µA]

ISS1 [µA]

0

0.3

3. 2

0.9

0.3

0.0
-40 -250.5
0.0

Ta = -40°C
0

6

12

18
24
VDD [V]

30

0.5
0.0

ISS1 [µA]

Ta = +25°C
Ta = -40°C
0

6

12

18
24
VDD [V]30

36

Ta = -40°C
0

6

12

18
24
VDD [V]

30

36

VDET(S) = 10.0 V, VDD = 0 V → 36.0 V,
VSENSE = 9.0 V, VPMEN = 0 V (during detection)
1.5
Ta = +125°C

Ta = +125°C
1.0

Ta = +25°C

0.5
0.0

36

VDET(S) = 4.0 V, VDD = 0 V → 36.0 V,
VSENSE = 3.0 V, VPMEN = 0 V (during detection)
1.5

ISS1 [µA]3.

1.0Ta = +25°C

0.5
0.0

Ta = -40°C
0

6

12

18
24
VDD [V]

30

36

33

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00
3. 3

Current consumption (ISSP1) vs. Temperature (Ta)(No load, during supply voltage divided output operates)

VDET(S) = 4.0 V, VDD = 13.5 V,
VSENSE = 13.5 V, VPMEN = 13.5 V

1.5

2.0

ISSP1 [µA]

ISSP1 [µA]

2.0

1.0
0.5

1.5
1.0
0.5

0.0
-40 -25

3. 4

VDET(S) = 10.0 V, VDD = 13.5 V,
VSENSE = 13.5 V, VPMEN = 13.5 V

0

25
50
Ta [°C]

75

100

0.0
-40 -25

125

4.0

30

3.0

Ta = +125°C

20

0

ISSP1 [µA]

ISSP1 [µA]

75

100

125

VDET(S) = 4.0 V, VDD = 0 V → 36.0 V,
VSENSE = 13.5 V, VPMEN = 13.5 V

40

Ta = -40°C

10
0

6

12

Ta = +25°C
1824
VDD [V]30

Ta = +125°C
Ta = -40°C

2.0

0.0

36

0

30

3.0

Ta = -40°C

10
0

ISSP1 [µA]4.0Ta = +125°C

0

6

12

Ta = +25°C

1824
VDD [V]

30

6

12

18
24
VDD [V]

30

36

VDET(S) = 10.0 V, VDD = 0 V → 36.0 V,
VSENSE = 13.5 V, VPMEN = 13.5 V

40

20

Ta = +25°C

1.0

VDET(S) = 10.0 V, VDD = 0 V → 36.0 V,
VSENSE = 13.5 V, VPMEN = 13.5 V

ISSP1 [µA]2550Ta [°C]

Current consumption (ISSP1) vs. Power supply voltage (VDD)(No load, during supply voltage divided output operates)

VDET(S) = 4.0 V, VDD = 0 V → 36.0 V,
VSENSE = 13.5 V, VPMEN = 13.5 V

340

Ta = +125°C
Ta = -40°C

2.0

Ta = +25°C

1.0
36

0.0

0

6

12

18
24
VDD [V]

30

36

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series Reference Data1.

Detection response time (tRESET) vs.
Temperature (Ta)2.

Detection response time (tRESET) vs.
Power supply voltage (VDD)
VDET(S) = 4.0 V, VREL(S) = 4.4 V,
CD = 3.3 nF

200

200

150

150

tRESET [µs]tRESET [µs]VDET(S) = 4.0 V, VREL(S) = 4.4 V,
VDD = 13.5 V, CD = 3.3 nF

100
50
0
-40 -2502550Ta [°C]

75

100

Ta = +25°C

100
50
0

125

Ta = -40°C

Ta = +125°C
0

6

12

18
24
VDD [V]

30

36

1 µs
VIH*1
VSENSE
VIL*2

R
100 kΩVDD

tRESET
VDD

VDD
VRO

VDD × 50%

V

+

SENSE
VSS

RO
CD
V

VSENSE

+

CD

VSS
*1.
*2.

VIH = VDET(S) + 1.0 V
VIL = VDET(S) − 1.0 V

Figure 32 Test Condition of Detection Response Time
CautionFigure 33 Test Circuit of Detection Response TimeThe above connection diagram and constants will not guarantee successful operation. Perform thoroughevaluation including the temperature characteristics with an actual application to set the constants.

35

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00
3.

Release delay time (tDELAY) vs. Temperature (Ta)12

4. Release delay time (tDELAY) vs. Power supply voltage (VDD)

VDET(S) = 4.0 V, VREL(S) = 4.4 V,
VDD = 13.5 V, CD = 3.3 nF

VDET(S) = 4.0 V, VREL(S) = 4.4 V,
CD = 3.3 nF

12
Ta = -40°C

1098-40 -25

5.

tDELAY [ms]tDELAY [ms]

11

0

25
50
Ta [°C]

75

100

10
9
8

125

Ta = +25°C

11

Ta = +125°C
0

6

12

18
24
VDD [V]30

36

Release delay time (tDELAY) vs. CD pin capacitance (CD) (Without output pin capacitance)
1000

VDET(S) = 4.0 V, VREL(S) = 4.4 V

Ta = +25°C

tDELAY [ms]10010Ta = -40°C

1
0.1
0.01
0.01

Ta = +125°C
0.1

1
CD [nF]

10

100

1 µs
VIH*1
VSENSE
VIL*2

R
100 kΩVDD

tDELAY
VDD

VDD
VRO

VDD × 50%

V

+

SENSE
VSS

RO
CD
V

VSENSE

+

CD

VSS
*1.
*2.

VIH = VREL(S) + 1.0 V
VIL = VREL(S) − 1.0 V

Figure 34 Test Condition of Release Delay Time
Caution36

Figure 35 Test Circuit of Release Delay TimeThe above connection diagram and constants will not guarantee successful operation. Perform thoroughevaluation including the temperature characteristics with an actual application to set the constants.

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series
Transient response characteristics of PMEN pin (Ta = +25°C)

VPMOUT
-5

20

25

16

6

8

4
2
0
-2

30

24

8

0

VPMEN

-8
-16

VPMOUT
-5

0

-24
5

10 15
t [ms]

20

25

30

VPMOUT = VSENSE/14

VDD = VSENSE = 5.0 V, CPM = 0.22 μF,
VPMEN = 0 V ↔ 5.0 V (tr = tf = 1.0 μs)

VPMEN

VPMOUT
0

-5

5

10 15
t [ms]

20

25

8
6
4
2
0
-2
-4
-6
-8

VDD = VSENSE = 18.0 V, CPM = 0.22 μF,
VPMEN = 0 V ↔ 18.0 V (tr = tf = 1.0 μs)

5

20

3

10

2
1
0
-1

30

30

4

0

VPMEN

-10
-20

VPMOUT
-5

0

-30
5

10 15
t [ms]

20

25

30

Example of equivalent series resistance vs. Load current characteristics (Ta = −40°C to +125°C)
7. 1

VPMOUT = VSENSE/6, VSENSE/8, VSENSE/12

7. 2

VPMOUT = VSENSE/14

CPM = 0.1 μF

CPM = 0.1 μF

100

100
RESR [Ω ]

7.

10 15
t [ms]

10

VPMEN [V]

1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2

5

RESR [Ω ]VPMOUT [V]

6. 2

0

VDD = VSENSE = 18.0 V, CPM = 0.22 μF,
VPMEN = 0 V ↔ 18.0 V (tr = tf = 1.0 μs)

VPMEN [V]

VPMEN

8
6
4
2
0
-2
-4
-6
-8

VPMEN [V]VDD = VSENSE = 5.0 V, CPM = 0.22 μF,
VPMEN = 0 V ↔ 5.0 V (tr = tf = 1.0 μs)

VPMOUT [V]

2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
-0.4

VPMOUT = VSENSE/6

VPMEN [V]VPMOUT [V]6. 1

VPMOUT [V]6.

Stable

0

0

10

−10

Stable3−3

IPMOUT [μA]

IPMOUT [μA]

Figure 36

Figure 37

PMEN

VDD

PMOUT
CPM*1

SENSE VSS
RESR

*1.

CPM: TDK Corporation CGA4J2X8R1H104K
Figure 38

37

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
S-19117/19119xxxA Series
Rev.1.2_00
Load dump characteristics (Ta = +25°C)
8. 1

VDET(S) = 4.0 V

VDD = VSENSE = 13.5 V ↔ 45.0 V,
VDD1 = 5.0 V, CD = 3.3 nF

VRO [V]

6.0

50

5.8

40

5.6

30

5.4
5.2
5.0

20

VDD

10

VRO

4.8
−0.2

VDD [V]

8.

0
0.0

0.2

0.4

0.6

0.8

SENSE

VDD
V

−10

R
100 kΩ

VDD

+

VSS

VDD1
RO

CD

V

CD

+

t [s]
Figure 39
VPMOUT = VSENSE/12

VPMOUT [V]VDD = VSENSE = VPMEN = 13.5 V ↔ 45.0 V,
CPM = 0.1 μF, CD = 3.3 nF

12.0
10.0
8.0
6.0 VDD
4.0
2.0
0.0 VPMOUT
−2.0
−0.2
0.0

0.2

0.4

0.6

0.8

50
40
30
20
10
0
−10
−20

VDD [V]

8. 2

VDD

SENSE

VDD
V

+

VSS

PMOUT
CD
CD CPMt [s]Figure 40

38

PMEN

V

+

AUTOMOTIVE, 125°C OPERATION, 36 V, SUPPLY VOLTAGE DIVIDED OUTPUT, VOLTAGE DETECTOR WITH SENSE PIN REVERSE CONNECTION PROTECTION
Rev.1.2_00
S-19117/19119xxxA Series Power Dissipation
HTMSOP-8

HSNT-8(2030)
Tj = +150°C max.

5

Tj = +150°C max.

5
Power dissipation (PD) [W]Power dissipation (PD) [W]

E
4
C
3 D
2
B
1

E

4

C
3

D

2
B

1

A
0

0

A
25

50

75

100

125

150

175

0

0

25

Ambient temperature (Ta) [°C]
Board
A
B
C
D
E

Power Dissipation (PD)
0.79 W
1.11 W
3.21 W
3.13 W
4.17 W

50

75

100

125

150

175

Ambient temperature (Ta) [°C]
Board
A
B
C
D
E

Power Dissipation (PD)0.69 W
0.93 W
3.13 W
2.98 W
3.91 W

39

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Disclaimers (Handling Precautions)1.

All the information described herein (product data, specifications, figures, tables, programs, algorithms andapplication circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.

2.

The circuit examples and the usages described herein are for reference only, and do not guarantee the success ofany specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any otherright due to the use of the information described herein.

3.

ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information describedherein.

4.

Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due tothe use of the products outside their specified ranges.

5.

Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.

6.

When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-relatedlaws, and follow the required procedures.

7.

The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,biological or chemical weapons or missiles, or use any other military purposes.

8.

The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.

9.

In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products areallowed to apply for the system on customer's own responsibility.

10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of thisdocument described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07

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