S-8255A Series
www.ablic.com

BATTERY MONITORING IC
FOR 3-SERIAL TO 5-SERIAL CELL PACK© ABLIC Inc., 2018

Rev.1.4_00

The S-8255A Series is a monitoring IC for 3-serial to 5-serial cell lithium-ion rechargeable batteries, which includes
high-accuracy voltage detection circuits and delay circuits. The S-8255A Series can monitor the status of 3-serial to 5-serialcell lithium-ion rechargeable battery packs. Cascade connection using the S-8255A Series realizes monitoring 6-serial ormore cells lithium-ion rechargeable battery packs.
Connecting an NTC, it allows for the temperature detection at four different points: high temperature detection during
charging, low temperature detection during charging, high temperature detection during discharging, and low temperaturedetection during discharging.

 Features
 High-accuracy voltage detection function for each cell
Overcharge detection voltage n (n = 1 to 5):3.550 V to 4.600 V (50 mV step)
Accuracy 20 mV
Overcharge release voltage n (n = 1 to 5):3.150 V to 4.600 V*1
Accuracy 50 mV
Overdischarge detection voltage n (n = 1 to 5):
2.000 V to 3.200 V (100 mV step)
Accuracy 80 mV*2
Accuracy 100 mV
Overdischarge release voltage n (n = 1 to 5):
2.000 V to 3.400 V
 Each delay time is settable by external capacitor (Temperature detection delay time is internally fixed)
 Independent control of charge inhibition, discharge inhibition, and power-saving by each control pin
 0 V battery detection function is selectable:
Available, unavailable CO and DO pin output voltage is limited to 8 V max. respectively
 Switching control for 3-serial to 5-serial cell is possible by inputting voltage to the SEL1 pin and the SEL2 pin
 Monitoring of 6-serial or more cells is possible by cascade connection
 Temperature detection is possible at four different points by connecting an NTC
High temperature detection ratio during charging / discharging: 0.600 to 0.900 (0.005 step)
Accuracy 0.005
Low temperature detection ratio during charging / discharging: 0.030 to 0.400 (0.005 step)
Accuracy 0.005
 High-withstand voltage:
Absolute maximum rating 28 V
 Wide operation voltage range:
5 V to 24 V Wide operation temperature range:
Ta = 40C to 85C Low current consumption
During operation:
19 A max. (Ta = 25C)
During power-saving:
0.1 A max. (Ta = 25C) Lead-free, halogen-free*1. Overcharge release voltage = Overcharge detection voltage  Overcharge hysteresis voltage(Overcharge hysteresis voltage n (n = 1 to 5) is selectable in 0 V to 0.4 V in 50 mV step)*2. Overdischarge release voltage = Overdischarge detection voltage  Overdischarge hysteresis voltage(Overdischarge hysteresis voltage n (n = 1 to 5) is selectable in 0 V to 0.7 V in 100 mV step) Application
 Rechargeable lithium-ion battery pack

 Package 20-Pin TSSOP

1

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00

 Block Diagram

VDD

Temperature detection circuit

TH

VC1



Overcharge 1Overdischarge 1Overcharge 2Overdischarge 2

Voltage regulator

VREG

CTLC

VC2
CTLD

PSI
VC3



Overcharge 3Overdischarge 3

CCT

CDT

VC4



Overcharge 4Overdischarge 4

Control circuit
CO pin output voltage
limit circuit

CO

VC5





Overcharge 5
Overdischarge 5

CO pin output voltage
limit circuit

VSS
DO
SEL1

SEL2

PSO
THC/DX

RemarkDiodes in the figure are parasitic diodes.
Figure 1

2

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00

 Product Name Structure
1. Product nameS-8255A xx

-

TET1

S

Environmental codeS:
Lead-free, halogen-free
Package abbreviation and IC packing specifications*1
TET1: 20-Pin TSSOP, Tape
Serial code*2
Sequentially set from AA to ZZ*1. Refer to the tape drawing.
*2. Refer to "3. Product name list".

2. Package
Table 1 Package Drawing CodePackage Name
20-Pin TSSOP

Dimension
FT020-B-P-SD

Tape
FT020-B-C-SD

Reel
FT020-B-R-SD

3. Product name list
Table 2 (1 / 2)
Product Name
S-8255AAA-TET1S
S-8255AAB-TET1S

Overcharge
Detection Voltage[VCU]
4.100 V
4.250 V

Overcharge
Release Voltage[VCL]
4.050 V4.150 V

Overdischarge
Detection Voltage[VDL]
2.600 V
2.500 V

Overdischarge
Release Voltage[VDU]
2.700 V
3.000 V

0 V Battery
Detection
Function*1
Unavailable
Available

Table 2 (2 / 2)
Low Temperature
High Temperature
Detection Ratio
Detection Ratio
Product Nameduring Charging
during Charging[rTHCL][rTHCH]S-8255AAA-TET1S
0.670
0.270
S-8255AAB-TET1S
0.670
0.270
*1. 0 V battery detection function "available" / "unavailable" is selectable.

High Temperature
Detection Ratio
during Discharging[rTHDH]
0.795
0.795

Low Temperature
Detection Ratio
during Discharging[rTHDL]
0.190
0.190

Remark Please contact our sales office for products other than those specified above.

3

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00

 Pin Configuration
1. 20-Pin TSSOP
Table 3Top view

1
2
3
4
5
6
7
8
9
10

Pin No.

20
19
18
17
16
15
14
13
12
11
Figure 2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

4

SymbolTH

Description

Input pin for temperature detection
Input pin for positive power supply,
VDD
connection pin for positive voltage of battery 1
VC1
Connection pin for positive voltage of battery 1
Connection pin for negative voltage of battery 1,
VC2
connection pin for positive voltage of battery 2
Connection pin for negative voltage of battery 2,
VC3
connection pin for positive voltage of battery 3
Connection pin for negative voltage of battery 3,
VC4
connection pin for positive voltage of battery 4
Connection pin for negative voltage of battery 4,
VC5
connection pin for positive voltage of battery 5
Input pin for negative power supply,
VSS
connection pin for negative voltage of battery 5
Switching pins for number of cells in series
SEL1[SEL1, SEL2] = ["L", "L"] :5-serial cell
[SEL1, SEL2] = ["L", "H"] :4-serial cell
[SEL1, SEL2] = ["H", "L"] :3-serial cell
SEL2
[SEL1, SEL2] = ["H", "H"] :Setting inhibited
Capacitor connection pin for delay
CCT
for overcharge detection voltage
Capacitor connection pin for delay
CDT
for overdischarge detection voltage
PSO
Output pin for power-saving signal (CMOS output)
DO
Connection pin of discharge control FET gate (CMOS output)
CO
Connection pin of charge control FET gate (CMOS output)
THC/DX Switching pin for detection temperature
CTLC
Control pin for CO pin output
CTLD
Control pin for DO pin output
PSI
Control pin for Power-saving
VREG
Voltage output pin for temperature detection

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00

 Absolute Maximum Ratings
Table 4
(Ta = 25°C unless otherwise specified)
Item
SymbolApplied Pin
Absolute Maximum Rating Unit
Input voltage between VDD pin and VSS pin VDS
VDD
VSS  0.3 to VSS  28
V
VC1, VC2, VC3, VC4, VC5,
Input pin voltage 1
VIN1
CCT, CDT, SEL1, SEL2,
VSS  0.3 to VDD  0.3
VTH, THC/DX
Input pin voltage 2
VIN2
PSI
VDD  28 to VDD  0.3
V
Input pin voltage 3
VIN3
CTLC, CTLDVSS  0.3 to VSS  28
V
Output pin voltage
VOUT
CO, DO, PSO, VREG
VSS  0.3 to VDD  0.3
V
Operation ambient temperatureTopr40 to 85°CStorage temperatureTstg
40 to 125
°C
Caution

The absolute maximum ratings are rated values exceeding which the product could suffer physicaldamage. These values must therefore not be exceeded under any conditions.

 Thermal Resistance Value
Table 5
Item

SymbolCondition
Board A
Board B
Junction-to-ambient thermal resistance*1 JA
20-Pin TSSOP Board CBoard D
Board E
*1. Test environment: compliance with JEDEC STANDARD JESD51-2A

Min.






Typ.
68
59




Max.






Unit
C/W
C/W
C/W
C/W
C/W

Remark Refer to " Power Dissipation" and "Test Board" for details.

5

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00

 Electrical Characteristics
Table 6 (1 / 2)

Item
Detection Voltage
Overcharge detection voltage n(n = 1 to 5)
Overcharge release voltage n(n = 1 to 5)
Overdischarge detection voltage n(n = 1 to 5)
Overdischarge release voltage n(n = 1 to 5)
Delay Time Function*1
CCT pin internal resistance
CDT pin internal resistance

Symbol

VCUn(V1 = V2 = V3 = V4 = V5 = 3.5 V, Ta = 25°C unless otherwise specified)
TestCondition
Min.
Typ.
Max.
Unit
Circuit
V1 = V2 = V3 = V4 = V5 =VCUn  0.050 V

VCLn



VDLn



VDUn



RCCT
RCDT

V1 = VCU  0.025
V1 = VDL  0.085

CCT pin detection voltage

VCCT

V1 = VCU  0.025

CDT pin detection voltage

VCDT

V1 = VDL  0.085

VDSOP

Input Voltage
Operation voltage between
VDD pin and VSS pin
Input Current
Current consumption during
operation
Current consumption during
power-saving
VC1 pin current
VC2 pin current
VC3 pin current
VC4 pin current
VC5 pin current
Output Pin
CO pin voltage "H"*2
DO pin voltage "H"*3
CO pin source current
CO pin sink current
DO pin source current
DO pin sink current
PSO pin source current
PSO pin sink current
0 V Battery Detection Function
0 V battery detection voltage n(n = 1 to 5)
*1.
*2.
*3.

VCUn 
0.020
VCLn 
0.050
VDLn 
0.080
VDUn 
0.100

VCLn
VDLn
VDUn

VCUn 
0.020
VCLn 
0.050
VDLn 
0.080
VDUn 
0.100

V

1

V

1

V

1

V

1

6.15
615
VDS 
0.68
VDS 
0.68

8.31
831
VDS 
0.70
VDS 
0.70

10.20
1020
VDS 
0.72
VDS 
0.72

M
k

1
1

V

1

V

1

Fixed output voltage of DO pin
and CO pin

5



24

V



IOPE





10

19

A

1

IPSV







0.1

A

1

IVC1
IVC2
IVC3
IVC4
IVC5








0.8
0.8
0.8
0.8

0.25
0.0
0.0
0.0
0.0

0.50
0.8
0.8
0.8
0.8

A
A
A
A
A

1
1
1
1
1


V1 = V2 = V3 = V4 = V5 = 5.6 VV1 = V2 = V3 = V4 = V5 = 1.9 V

4.0
4.0
10
10
10
10
10
10

6.0
6.0







8.0
8.0







V
V
A
A
A
A
A
A

1
1
1
1
1
1
1
1

1.0

1.3

1.5

V

1

VCOH
VDOH
ICOH
ICOL
IDOH
IDOL
IPSOH
IPSOL
V0INHnVCOH  VDS
VDOH  VDS

0 V battery detection function"available"

Refer to "4. Delay time setting" in " Operation" for details of the delay time function.
When VCOH  VDS, VCOH = VDDWhen VDOH  VDS, VDOH = VDD

Remark VDS: Input voltage between VDD pin and VSS pin (V1  V2  V3  V4  V5)

6

VCUn

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00

Table 6 (2 / 2)

Item

Symbol(V1 = V2 = V3 = V4 = V5 = 3.5 V, Ta = 25°C unless otherwise specified)
TestCondition
Min.
Typ.
Max.
Unit
CircuitControl Pin
SEL1 pin voltage "H"
VSEL1H
VDS  0.95
SEL2 pin voltage "H"
VSEL2H
VDS  0.95
SEL1 pin voltage "L"
VSEL1L
SEL2 pin voltage "L"
VSEL2L
CTLC pin reverse voltage
VCTLC

0.1
CTLD pin reverse voltage
VCTLD

0.1
PSI pin reverse voltage
VPSI

0.1
CTLC pin response delay time
tCTLC

0.275
CTLD pin response delay time
tCTLD

0.275
PSI pin response delay time
tPSI

0.3
CTLC pin curent "H"
ICTLCH0.1
CTLC pin curent "L"
ICTLCL0.45
CTLD pin curent "H"
ICTLDH
0.1
CTLD pin curent "L"ICTLDL0.45
PSI pin curent "H"
IPSIH

0.0
PSI pin curent "L"
IPSIL

0.1
CTLC pin reverse voltage during
5.1 M resistance connected
VCTLC_C
VDS  0.2
communication
to the CTLC pin
CTLD pin reverse voltage during
5.1 M resistance connected
VCTLD_C
VDS  0.2
communication
to the CTLD pin
PSI pin reverse voltage during
5.1 M resistance connected
VPSI_CVSS  1.9
communication
to the PSI pin
Temperature Detection Function
Output voltage for temperature
Voltage between VDD pin
VREG
4.0
detection
and VREG pin
rTHCH High temperature detection ratio
rTHCH
rTHCH = (VREG  VTH) / VREG
during charging
0.005
rTHCL Low temperature detection ratiorTHCL
rTHCL = (VREG  VTH) / VREG
during charging
0.005
rTHDH High temperature detection ratio
rTHDH
rTHDH = (VREG  VTH) / VREG
during discharging
0.005
rTHDL Low temperature detection ratiorTHDL
rTHDL = (VREG  VTH) / VREG
during discharging
0.005
THC/DX pin voltage "H"VTHHVDS  2.0
THC/DX pin voltage "L"
VTHL

0.5
Temperature detection delay time tTH

1.0





0.7
0.7
4.0
0.500
0.500
0.9
0.0
0.20
0.0
0.20
0.2
0.0



VDS  0.05
VDS  0.05
2.0
2.0
8.0
0.725
0.725
3.0
0.1
0.05
0.1
0.05
0.4
0.1

V
V
V
V
V
V
V
ms
ms
ms
A
A
A
A
A
A





1
1
1
1
1
1
1
1
1
1
1
1

VDS  0.7

VDS  1.3

V

3

VDS  0.7

VDS  1.3

V

3

VSS  1.0

VSS  0.3

V

3

5.0

6.0

V

2



2



2



2



2

V
V
s

2
2
2

rTHCH
rTHCL
rTHDH
rTHDL
VDS  1.5
1.0
2.0

rTHCH 0.005
rTHCL 0.005
rTHDH 0.005
rTHDL 0.005
VDS  1.0
1.5
3.0

7

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00

 Test Circuits
Unless otherwise specified, for the CO pin output voltage (VCO), DO pin output voltage (VDO), and PSO pin output voltage(VPSO), "L" or "H" is judged as follows.
L : [VCO, VDO, VPSO]  VDS  0.1 V
H : [VCO, VDO, VPSO]  VDS  0.1 V
Remark

VDS: Input voltage between VDD pin and VSS pin (V1  V2  V3  V4  V5)

1. Test circuit 1
10 k
0.1 F
10 k
1 TH

V1
V2
V3
V4
V5

VREG 20

2 VDD

PSI 19

A

A

3 VC1

CTLD 18

A

A

4 VC2

CTLC 17

A

A

5 VC3

THC/DX 16

A

A

6 VC4

CO 15

A

A

7 VC5

DO 14

A

A

8 VSS

PSO 13A

9 SEL1

CDT 12A

10 SEL2

CCT 11

A

S-8255A

SW1 SW2

V6

SW3

V7

V

SW4

V8

V

SW5

V9

V

V10 V11 V12 V13 V14

Figure 3 Test Circuit 1
This section provides explanations of Test items using Test circuit 1.
Perform each test after setting as shown in Table 7.
Table 7
V1
3.5 V

V11
0V

8

V2
3.5 V

V12
0V

V3
3.5 V

Initial Setting of Test Circuit 1 (1 / 2)
V4
3.5 V

V5
3.5 V

V6


V7


V8


Table 7

Initial Setting of Test Circuit 1 (2 / 2)

V13
0V

V14
VDS

SW1
OFF

SW2
OFF

SW3
OFF

SW4
OFF

V9


SW5
OFF

V10


Rev.1.4_00

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

1. 1 Overcharge detection voltage n (VCUn), overcharge release voltage n (VCLn)
When the voltage V1 is gradually increased after setting V1 = V2 = V3 = V4 = V5 = VCUn  0.05 V and VCOchanges from "H" to "L", V1 is defined as the overcharge detection voltage 1 (VCU1). When the voltage V1 is thengradually decreased and VCO changes from "L" to "H", V1 is defined as the overcharge release voltage 1 (VCL1).
Overcharge detection voltage n (VCUn) and overcharge release voltage n (VCLn) (n = 2 to 5) can be determined in
the same way as when n = 1.
1. 2 Overdischarge detection voltage n (VDLn), overdischarge release voltage n (VDUn)
When the voltage V1 is gradually decreased and VDO changes from "H" to "L", V1 is defined as the overdischarge
detection voltage 1 (VDL1). When the voltage V1 is then gradually increased and VDO changes from "L" to "H", V1 isdefined as the overdischarge release voltage 1 (VDU1).
Overdischarge detection voltage n (VDLn) and overdischarge release voltage n (VDUn) (n = 2 to 5) can be
determined in the same way as when n = 1.
1. 3 CCT pin internal resistance (RCCT), CCT pin detection voltage (VCCT)The CCT pin internal resistance (RCCT) is defined by RCCT = VDS / ICCT under the set conditions of V1 = VCU1 
0.025 V after setting V6 = 0 V and setting SW1 to ON. When the voltage V6 is then gradually increased and VCOchanges from "H" to "L", V6 is defined as the CCT pin detection voltage (VCCT).
1. 4 CDT pin internal resistance (RCDT), CDT pin detection voltage (VCDT)The CDT pin internal resistance (RCDT) is defined by RCDT = VDS / ICDT under the set conditions of V1 = VDL1 
0.085 V after setting V7 = 0 V and setting SW2 to ON. When the voltage V7 is then gradually increased and VDOchanges from "H" to "L", V7 is defined as the CDT pin detection voltage (VCDT).
1. 5 Current consumption during operation (IOPE)
The current consumption during operation (IOPE) is IVSS under the initial setting shown in Table 7.
1. 6 Current consumption during power-saving (IPSV)
The current consumption during power-saving (IPSV) is IVSS when V14 = 0 V.
1. 7 CO pin source current (ICOH)
The CO pin source current (ICOH) is ICO when V10 = VCOH  0.5 V and SW5 is ON.
1. 8 CO pin sink current (ICOL)The CO pin sink current (ICOL) is ICO when V1 = V2 = V3 = V4 = V5 = 4.6 V, V10 = 0.5 V, and SW5 is ON.
1. 9 DO pin source current (IDOH)
The DO pin source current (IDOH) is IDO when V9 = VDOH  0.5 V and SW4 is ON.
1. 10 DO pin sink current (IDOL)The DO pin sink current (IDOL) is IDO when V1 = V2 = V3 = V4 = V5 = 1.9 V, V9 = 0.5 V, and SW4 is ON.
1. 11 PSO pin source current (IPSOH)
The PSO pin source current (IPSOH) is IPSO when V14 = 0 V, V8 = VDS  0.5 V, and SW3 is ON.
1. 12 PSO pin sink current (IPSOL)
The PSO pin sink current (IPSOL) is IPSO when V8 = 0.5 V and SW3 is ON.

9BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00

1. 13 0 V battery detection voltage n (V0INHn) (0 V battery detection function "available")
When the voltage V1 is gradually decreased and VCO changes from "H" to "L", V1 is defined as the 0 V battery
detection voltage 1 (V0INH1).
0 V battery detection voltage n (V0INHn) (n = 2 to 5) can be determined in the same way as when n = 1.
1. 14 CTLC pin reverse voltage (VCTLC)
When the voltage V12 is gradually increased and VCO changes from "H" to "L", V12 is defined as the CTLC pinreverse voltage (VCTLC).
1. 15 CTLD pin reverse voltage (VCTLD)
When the voltage V13 is gradually increased and VDO changes from "H" to "L", V13 is defined as the CTLD pinreverse voltage (VCTLD).
1. 16 PSI pin reverse voltage (VPSI)When the voltage V14 is gradually decreased and VPSO changes from "L" to "H", V14 is defined as the PSI pin
reverse voltage (VPSI).
1. 17 CTLC pin response delay time (tCTLC)
The CTLC pin response delay time (tCTLC) is the time period from when the voltage V12 changes to V12 = VDS until
when VCO changes from "H" to "L".
1. 18 CTLD pin response delay time (tCTLD)The CTLD pin response delay time (tCTLD) is the time period from when the voltage V13 changes to V13 = VDS until
when VDO changes from "H" to "L".
1. 19 PSI pin response delay time (tPSI)The PSI pin response delay time (tPSI) is the time period from when the voltage V14 changes to V14 = 0 V until
when VPSO changes from "L" to "H".
1. 20 CTLC pin current "H" (ICTLCH), CTLC pin current "L" (ICTLCL)The CTLC pin current "H" (ICTLCH) is ICTLC when V12 = VDS.
The CTLC pin current "L" (ICTLCL) is ICTLC when V12 = 0 V.
1. 21 CTLD pin current "H" (ICTLDH), CTLD pin current "L" (ICTLDL)The CTLD pin current "H" (ICTLDH) is ICTLD when V13 = VDS.
The CTLD pin current "L" (ICTLDL) is ICTLD when V13 = 0 V.
1. 22 PSI pin current "H" (IPSIH), PSI pin current "L" (IPSIL)
The PSI pin current "H" (IPSIH) is IPSI when V14 = VDS.
The PSI pin current "L" (IPSIL) is IPSI when V14 = 0 V.

10

Rev.1.4_00

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

2. Test circuit 2

V

V7

1 TH

V1
V2
V3
V4
V5

0.1 F

VREG 20

2 VDD

PSI 193 VC1CTLD 18

4 VC2CTLC 175 VC3THC/DX 16

6 VC4

20 k

CO 15

S-8255A

7 VC5

DO 14

8 VSS

PSO 13

9 SEL1

CDT 12

10 SEL2

CCT 11V

V

V6

Figure 4 Test Circuit 2This section provides explanations of Test items using Test circuit 2.
Perform each test after setting as shown in Table 8.
Table 8 Initial Setting of Test Circuit 2
V1
V2
V3
3.5 V
3.5 V
3.5 V
*1. V7 is an absolute value.

V4
3.5 V

V5
3.5 V

V6
0V

V7*1
2.5 V

2. 1 Output voltage for temperature detection (VREG)
The maximum voltage between the VDD pin and VREG pin is defined as the output voltage for temperaturedetection (VREG).
2. 2 High temperature detection ratio during charging (rTHCH)
When the voltage V7 is gradually decreased after setting V6 = VDS and VCO changes from "H" to "L", the hightemperature detection ratio during charging (rTHCH) is defined by (VREG  V7) / VREG.
2. 3 Low temperature detection ratio during charging (rTHCL)
When the voltage V7 is gradually increased after setting V6 = VDS and VCO changes from "H" to "L", the lowtemperature detection ratio during charging (rTHCL) is defined by (VREG  V7) / VREG.
2. 4 High temperature detection ratio during discharging (rTHDH)
When the voltage V7 is gradually decreased and VCO changes from "H" to "L" and VDO changes from "H" to "L", thehigh temperature detection ratio during discharging (rTHDH) is defined by (VREG  V7) / VREG.
2. 5 Low temperature detection ratio during discharging (rTHDL)
When the voltage V7 is gradually increased and VCO changes from "H" to "L" and VDO changes from "H" to "L", thelow temperature detection ratio during discharging (rTHDL) is defined by (VREG  V7) / VREG.

11

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00

2. 6 THC/DX pin voltage "H" (VTHH)
When the voltage V6 is gradually increased after setting (1  rTHDH)  VREG  V7  (1  rTHCH)  VREG and VDOchanges from "L" to "H", V6 is defined as the THC/DX pin voltage "H" (VTHH).
2. 7 THC/DX pin voltage "L" (VTHL)
When the voltage V6 is gradually decreased after setting (1  rTHDH)  VREG  V7  (1  rTHCH)  VREG and VDOchanges from "H" to "L", V6 is defined as the THC/DX pin voltage "L" (VTHL).
2. 8 Temperature detection delay time (tTH)
The temperature detection delay time (tTH) is the time period from when the voltage V7 changes to 0 V until when
VCO changes from "H" to "L" and VDO changes from "H" to "L".

3. Test circuit 3
10 k
0.1 F
10 k
1 TH

V1
V2
V3

VREG 20

2 VDD

PSI 193 VC1CTLD 18

4 VC2CTLC 175 VC3THC/DX 16

6 VC4

V4
V5

S-8255A

5.1 M
5.1 M
5.1 M

CO 15

7 VC5

DO 14

8 VSS

PSO 13

9 SEL1

CDT 12

10 SEL2

CCT 11

V

V

V6

V7

V8

Figure 5 Test Circuit 3
This section provides explanations of Test items using Test circuit 3.
Perform each test after setting as shown in Table 9.
Table 9 Initial Setting of Test Circuit 3
V1
3.5 V

V2
3.5 V

V3
3.5 V

V4
3.5 V

V5
3.5 V

V6
VDS  2.0 V

V7
VDS  2.0 V

V8
2.0 V3. 1 CTLC pin reverse voltage during communication (VCTLC_C)
When the voltage V6 is gradually decreased and VCO changes from "H" to "L", V6 is defined as the CTLC pinreverse voltage during communication (VCTLC_C).
3. 2 CTLD pin reverse voltage during communication (VCTLD_C)
When the voltage V7 is gradually decreased and VDO changes from "H" to "L", V7 is defined as the CTLD pinreverse voltage during communication (VCTLD_C).
3. 3 PSI pin reverse voltage during communication (VPSI_C)
When the voltage V8 is gradually increased and VPSO changes from "L" to "H", V8 is defined as the PSI pin reverse
voltage during communication (VPSI_C).
12

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00
 Operation

Remark Refer to " Connection Examples of Battery Protection IC".

1. Normal status
The status when CO pin output voltage (VCO) = "H", DO pin output voltage (VDO) = "H" and PSO pin output voltage(VPSO) = "L" is the normal status.
All the conditions mentioned below should be satisfied for returning to the normal status.
 The voltage of each of the batteries is in the range from overcharge detection voltage n (VCUn) to overdischarge
detection voltage n (VDLn).
 CTLC pin voltage and CTLD pin voltage are lower than CTLC pin reverse voltage (VCTLC) and CTLD pin reverse
voltage (VCTLD), respectively, and PSI pin voltage is higher than PSI pin reverse voltage (VPSI).
 Either (1) or (2) below is satisfied for TH pin voltage (VTH).
(1) When VTHC/DX  VTHH: (1  rTHCH)  VREG  VTH  (1  rTHCL)  VREG
(2) When VTHC/DX  VTHL: (1  rTHDH)  VREG  VTH  (1  rTHDL)  VREG
Caution

After the battery is connected, there may be cases when discharging cannot be performed. In thiscase, the S-8255A Series returns to the normal status when the following condition is satisfied.
 Changing the PSI pin voltage to be VDS  0 V  VDS

Remark

VTHC/DX: THC/DX pin voltage
THC/DX pin voltage "H"
VTHH:
VTHL:
THC/DX pin voltage "L"
rTHCH:High temperature detection ratio during charging
rTHCL:
Low temperature detection ratio during charging
rTHDH:High temperature detection ratio during discharging
rTHDL:
Low temperature detection ratio during discharging
VREG:
Output voltage for temperature detection
VDS:
Input voltage between VDD pin and VSS pin (V1  V2  V3  V4  V5)

2. Overcharge status
When the voltage of any of the batteries exceeds the overcharge detection voltage n (VCUn) and the status continues*1
for the overcharge detection delay time (tCU) or longer, the CO pin changes to the VSS level. This is the overcharge
status.
The overcharge status is released if the following condition is satisfied.
 Voltage of battery  VCLn
*1. Refer to "4.
Remark

VCLn:

Delay time setting" for details.
Overcharge release voltage n (n = 1 to 5)

13

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00

3. Overdischarge status
When the voltage of any of the batteries falls below the overdischarge detection voltage n (VDLn) and the status*1
continues for the overdischarge detection delay time (tDL) or longer, the DO pin changes to the VSS level. This is theoverdischarge status.
The overdischarge status is released if the following condition is satisfied.
 Voltage of battery  VDUn
*1. Refer to "4.

Delay time setting" for details.

RemarkOverdischarge release voltage n (n = 1 to 5)

VDUn:

4. Delay time setting
Users are able to set delay time for the period from when the S-8255A Series detects change in the voltage of any ofthe batteries until when it outputs to the CO pin or DO pin. Each delay time is determined by a resistor in the S-8255A
Series and an external capacitor.
In the overchage detection, when the voltage of any of the batteries exceeds overcharge detection voltage n (VCUn),
the S-8255A Series starts charging to the CCT pin's capacitor (CCCT) via the CCT pin internal resistance (RCCT). Aftera certain period, the CO pin changes to the VSS level when the voltage at the CCT pin reaches the CCT pin detection
voltage (VCCT). This period is overcharge detection delay time (tCU).
tCU is calculated using the following equation.
tCU [s] = ln (1  VCCT / VDS)  CCCT [F]  RCCT [M]= ln (1  0.7 typ.)  CCCT [F]  8.31 [M] typ.
= 10.0 [M] typ.  CCCT [F]
Overdischarge detection delay time (tDL) is calculated using the following equations as well.
tDL [ms] = ln (1  VCDT / VDS)  CCDT [F]  RCDT [k]
When CCCT = CCDT = 0.1 [F], each delay time is calculated as follows.
tCU [s] = 10.0 [M] typ.  0.1 [F] = 1.0 [s] typ.
tDL [ms] = 1000 [k] typ.  0.1 [F] = 100 [ms] typ.
RemarkVDS:

Input voltage between VDD pin and VSS pin (V1  V2  V3  V4  V5)

5. 0 V Battery detection function
For detection function of self-discharged battery (0 V battery), "available" / "unavailable" is selectable.
 0 V battery detection function "available"
The voltage VCO changes to the VSS level when the voltage of any of the batteries is V0INHn or lower.

14

CautionWhen the VDD pin voltage is lower than the minimum value of operation voltage between VDD pin
and VSS pin (VDSOP), the S-8255A Series' operation is not assured.

Remark

V0INHn:VCO:

0 V battery detection voltage n (n = 1 to 5)
CO pin voltage

Rev.1.4_00

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

6. SEL1 pin and SEL2 pin
Switching control for 3-serial to 5-serial cell is possible by inputting voltage to the SEL1 pin and the SEL2 pin.
Be sure to use the SEL1 pin and the SEL2 pin at the "H" or "L" level.
Table 10

Settings of SEL1 Pin and SEL2 Pin

SEL1 Pin
"L"
"L"
"H"
"H"
RemarkSEL2 Pin
"L"
"H"
"L"
"H"

Setting
5-serial cell monitoring
4-serial cell monitoring
3-serial cell monitoring
Setting inhibited"H" is the status when VSEL1  VSEL1H, VSEL2  VSEL2H, and "L" is the status when VSEL1 
VSEL1L, VSEL2  VSEL2L.
VSEL1H:VSEL2H:VSEL1L:VSEL2L:SEL1 pin voltage "H"
SEL2 pin voltage "H"
SEL1 pin voltage "L"
SEL2 pin voltage "L"

7. CTLC pin and CTLD pin
The CTLC pin controls the CO pin, and the CTLD pin controls the DO pin. Thus it is possible for users to control theCO pin and the DO pin respectively. These controls precede the battery monitoring circuit.
Table 11 Status Set by CTLC Pin
CTLC Pin
VSS level  CTLC pin voltage  VCTLC
VCTLC  CTLC pin voltage  VDD level
VDD level  CTLC pin voltage  VCTLC_C
VCTLC_C  CTLC pin voltage
RemarkCO Pin"H"
VSS level
VSS level"H"

CTLC pin is at the VDD level or higher in cascade connection.
Connect a resistor of 5.1 M to the CTLC pin in this case.
VCTLC:
CTLC pin reverse voltage
VCTLC_C: CTLC pin reverse voltage during communication
Table 12 Status Set by CTLD Pin

CTLD Pin
VSS level  CTLD pin voltage  VCTLD
VCTLD  CTLD pin voltage  VDD level
VDD level  CTLD pin voltage  VCTLD_C
VCTLD_C  CTLD pin voltage
Remark

DO Pin"H"
VSS level
VSS level"H"

CTLD pin is at the VDD level or higher in cascade connection.
Connect a resistor of 5.1 M to the CTLD pin in this case.
VCTLD:CTLD pin reverse voltage
VCTLD_C: CTLD pin reverse voltage during communication

15

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00

8. PSI pin
When the PSI pin is activated, the power-saving function starts to operate, and most operations halt. In this case, theCO pin and DO pin change to the VSS level, and the PSO pin changes to the VDD level.
Table 13

Status Set by PSI Pin

PSI Pin

CO PinDO PinPSO Pin

VPSI  PSI pin voltage  VDD level

"H"

"H"

VSS level

VSS level  PSI pin voltage  VPSIVSS level

VSS level

VDD level

VPSI_C  PSI pin voltage  VSS level

VSS level

VSS level

VDD level

PSI pin voltage  VPSI_C

"H"

"H"

VSS level

RemarkPSI pin is at the VSS level or lower in cascade connection.
Connect a resistor of 5.1 M to the PSI pin in this case.
VPSI:
VPSI_C:

PSI pin reverse voltage
PSI pin reverse voltage during communication

The S-8255A Series is initialized and the power-saving function is released by deactivating the PSI pin. As a result,each detection operation is carried out after returning to the normal status.

9. Temperature detection
Serially connect an NTC and a low temperature-dependent resistor (RTH) between the VDD pin and the VREG pin,and then connect their middle point to the TH pin. It allows for temperature detection at four different points: hightemperature detection during charging, low temperature detection during charging, high temperature detection during
discharging, low temperature detection during discharging.
When the temperature rises, according to the NTC temperature characteristics, the resistance (RNTC) decreases, andthe ratio between RNTC and RTH changes, and then the TH pin voltage (VTH) increases.
When the temperature falls, according to the NTC temperature characteristics, the resistance (RNTC) increases, andthe ratio between RNTC and RTH changes, and then the TH pin voltage (VTH) decreases.
The temperature detection during charging and temperature detection during discharging switch by comparing
THC/DX pin voltage (VTHC/DX) and either of THC/DX pin voltage "H" or "L" (VTHH, VTHL).
If the relation between RNTC, RTH, and VTHC/DX satisfies the itemized condition in Table 14 in each temperaturedetection, and each status continues for the temperature detection delay time (tTH) or longer, the CO pin changes tothe VSS level and the DO pin changes to the "H" or VSS level. This is the temperature protection status.
If the itemized condition in Table 14 is not satisfied in each temperature detection, and each status continues for tTH or
longer, the temperature protection status is released.
Table 14 Conditions for Each Temperature Detection
Item

TH Pin

THC/DX Pin

High temperature detection during charging
Low temperature detection during charging
High temperature detection during discharging
Low temperature detection during discharging

rTHCH  RTH / (RNTC  RTH)
rTHCL  RTH / (RNTC  RTH)
rTHDH  RTH / (RNTC  RTH)
rTHDL  RTH / (RNTC  RTH)

VTHC/DX  VTHH
VTHC/DX  VTHH
VTHC/DX  VTHL
VTHC/DX  VTHL

Remark16

rTHCH:rTHCL:
rTHDH:rTHDL:High temperature detection ratio during charging
Low temperature detection ratio during charging
High temperature detection ratio during discharging
Low temperature detection ratio during discharging

CO PinDO Pin"H"

VSS level
VSS level

Rev.1.4_00

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

The detection temperature can be set according to the NTC and RTH characteristics.
*1
For example, if RNTC and RTH (10 k) are connected to S-8255AAA, each detection temperature is as follows.
Table 15
Item
Temperature for high temperature detection
during charging
Temperature for low temperature detection
during charging
Temperature for high temperature detection
during discharging
Temperature for low temperature detection
during discharging

Temperature Detection Ratio

RNTC

Detection Temperature

rTHCH = 0.670

4.9 k45C

rTHCL = 0.270

27.0 k0C

rTHDH = 0.795

2.6 k65C

rTHDL = 0.190

42.6 k10C*1. The calculation method for RNTC is as follows.
rTHCL = RTH / (RNTC  RTH)
RNTC = RTH / rTHCL  RTH= 10 k / 0.270  10 k= 27.0 k

RNTC [k]

When low temperature during charging is detected, RNTC = 27.0 k, so detection temperature = 0C according to
the RNTC characteristics shown in Figure 6.

200
180
160
140
120
100
80
60
40
20
0

RNTC = 10 k, Ta = 25C, B constant (25 / 85C) = 3434K

40

25

0

25
Ta [C]

50

75

85

Figure 6 Example of RNTC Characteristics
RemarkTemperature detection is carried out intermittently for 512 ms typ. per cycle, of which 1 ms typ. is thedetection operation period.
The VREG pin voltage is output only during detection operation. During other periods, the VREG pin is at
the VDD level.
Regarding details of intermittent operation, refer to "2. Temperature detection (High temperaturedetection during charging)" in " Timing Charts".

17

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00

 Timing Charts
1. Overcharge detection, overdischarge detection
VCUn
VCLn
Battery voltage
VDUn
VDLn
(n = 1 to 5)
VDOH
DO pin voltage
VSS
VCOH
CO pin voltage
VEB

Overcharge detection delay time (tCU)
Status

*1

(1)

(2)

(1)

*1. (1) : Normal status(2) : Overcharge status(3) : Overdischarge status
Figure 718

Overdischarge detection delay time (tDL)
(3)

(1)

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00

2. Temperature detection (High temperature detection during charging)
VDD
VTHCH = (1  rTHCH)  VREG
TH pin voltage
VTHCL = (1  rTHCL)  VREG

VDOH
DO pin voltage

VSS
VCOH
CO pin voltage

VSS
VDD
VTHH
THC/DX pin voltage
VTHL
VSS

Status

*1

(2)

(3)

(2)

(3)

Temperature detection delay time (tTH)
(2)
(2)
(3)
(2)
(3)
(1)

(3)

(2)
(4)

*1. (1) : Normal status(2) : Temperature detection sleep time(3) : Temperature detection awake time(4) : Temperature protection status
Figure 8

19

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00

 Connection Example of Battery Monitoring IC
1. S-8255A Series (10-serial cell)
EB
NTC1
CTH1
RTH1

RVC11
RVC21

VREG 20

1 TH

RVDD1
CVDD1
CVC11
CVC21

RVC31

CVC31

RVC41

CVC41

RVC51

CVC51

RSEL11

2 VDD

PSI 193 VC1CTLD 18

4 VC2CTLC 175 VC3THC/DX 16

6 VC4

S-8255A

RCTLD
RCTLC
RTHC / DX1

CO 15

7 VC5

DO 14

8 VSS

PSO 13

9 SEL1

CDT 12

10 SEL2

CCT 11

RSEL21CCCT1CPSI_CCCDT1

RCTLD_C

RCTLC_C

RPSI_C

NTC2
CTH2
RTH2
RVDD2
RVC12
RVC22
RVC32

CVDD2
CVC12
CVC22
CVC32

RVC42

CVC42

RVC52

CVC52

RSEL12

RSEL22

1 TH

VREG 20

2 VDD

PSI 19

3 VC1

CTLD184 VC2CTLC 175 VC3THC/DX 16

6 VC4

S-8255A

CCTLD_C

CCTLC_C

RPSI

RTHC / DX2

CO 15

7 VC5

DO 14

8 VSS

PSO 13

9 SEL1

CDT 12

10 SEL2

CCT 11

CCCT2

OD
OC

CCDT2

EB

Remark20

Regarding the recommended values for external components, refer to "Table 16
Components".
Figure 9Constants for External

Rev.1.4_00

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series
Table 16 Constants for External Components

SymbolRVDD1*1, RVDD2*1
RVCn1, RVCn2 (n = 1 to 5)*1
RSEL11, RSEL12, RSEL21, RSEL22
RCTLC, RCTLD, RPSI
RTHC/DX1, RTHC/DX2
RCTLC_C, RCTLD_C, RPSI_C
NTC1, NTC2
RTH1, RTH2
CVDD1, CVDD2*1
CVCn1, CVCn2 (n = 1 to 5)*1
CCTLC_C, CCTLD_C, CPSI_C
CCCT1, CCCT2
CCDT1, CCDT2
CTH1, CTH2
*1.

Min.

Typ.

Max.

Unit

68
0.68
1
1.0
1.0
4.0


0.68
0.068
470
0.01
0.01
0.1

100
1.00
1
2.0
1.0
5.1
10
10
1.00
0.100
470
0.10
0.10
0.1

100
1.00

5.1

6.0


10.00
1.000



0.1


k
k
k
k
M
k
k
F
F
pF
F
F
F

RVDD1  CVDD1 = RVDD2  CVDD2 = 100 F   is recommended.
Set filter constants to satisfy RVC1  CVC1 = RVC2  CVC2 = RVC3  CVC3 = RVC4  CVC4 = RVC5  CVC5 = RVDD1  CVDD1.

Caution 1.
2.

3.

The above constants may be changed without notice.
Sufficient evaluation of transient power supply fluctuation and overcurrent protection function withthe actual application is needed to determine the proper constants when setting the filter constants
between the VDD pin and VSS pin. Contact our sales office if setting the constants between the
VDD pin and VSS pin to anything other than the recommended values.
It has not been confirmed whether the operation is normal or not in circuits other than theconnection example. In addition, the connection example and the constants do not guarantee
proper operation. Perform thorough evaluation using the actual application to set the constants.

21

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00

 Precautions
 The application conditions for the input voltage, output voltage, and load current should not exceed the power
dissipation.
 Batteries can be connected in any order; however, there may be cases when discharging cannot be performed after abattery is connected. In this case, the S-8255A Series returns to the normal status when the following condition issatisfied.
Changing the PSI pin voltage to be VDS  0 V  VDS

Remark VDS: Input voltage between VDD pin and VSS pin (V1  V2  V3  V4  V5)
 Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
 ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.

22

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00

 Characteristics (Typical Data)
1.

Current consumption
1. 1 IOPE vs. VDS

1. 2 IOPE vs. Ta

40

30

30
IOPE [A]

IOPE [A]

Ta = 25C

40

20
10

20
15
0

0
0

5

10

15
20
VDS [V]2530

1. 3 IPSV vs. VDS

VDS = 17.5 V

40 25025Ta [C]75 85

1. 4 IPSV vs. Ta
Ta = 25C

VDS = 17.5 V

0.5

0.5

0.4

0.4

IPSV [A]

IPSV [A]

50

0.3
0.2

0.3
0.2
0.1

0.1

0.0

0.0
0

5

10

15
20
VDS [V]2530

40 25025Ta [C]

50

75 85

23

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series
2.

Detection voltage, release voltage

S-8255AAA
4.12

S-8255AAA
4.100

4.11

4.075

VCL [V]

2. 2

VCU [V]2. 1 VCU vs. Ta

4.10
4.09
4.08

4.025
40 25

4.000

0

25
Ta [C]5075 85

40 25

S-8255AAA
2.68

S-8255AAA
2.80

2.64

2.75
VDU [V]

2. 4

VDL [V]2. 3 VDL vs. Ta

2.60

2.52

0

25
Ta [C]

50

75 85

0

25
Ta [C]50

75 85

VDU vs. Ta

2.70
2.65
2.60

40 25025Ta [C]5075 85

40 25

Delay time function
3. 1 RCCT vs. Ta

3. 2
VDS = 19 V

124
40 2512.0
025Ta [C]

50

75 85

3. 4
VDS = 15.5 V

1500

40 25025Ta [C]

50

75 85

VCDT vs. Ta
VDS = 15.5 V

12

1250

11

1000

VCDT [V]

RCDT [k]

13.0
12.5

3. 3 RCDT vs. Ta

750
500

10
9

250
0

VDS = 19 V

13.5

8

0

VCCT vs. Ta

14.0

VCCT [V]

RCCT [M]

16

24

VCL vs. Ta

4.050

2.56

3.

Rev.1.4_00

40 2580

25Ta [C]5075 85

40 25025Ta [C]

50

75 85

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00
4.

Output pin
4. 1 ICOH vs. VDS

4. 2 ICOL vs. VDS
Ta = 25C

500

300

400
ICOL [A]

ICOH [A]

Ta = 25C

400

200
100
0
0

5

10

15
20
VDS [V]

25

200
100

30

4. 3 IDOH vs. VDS

300

0

5

10

15
20
VDS [V]Ta = 25C

500

2500

400

2000

IDOL [A]

IDOH [A]30

4. 4 IDOL vs. VDS
Ta = 25C

300
200
100

1500
1000
500

0
0

5

10

15
20
VDS [V]25

030

4. 5 IPSOH vs. VDS

0

5

10

15
20
VDS [V]25

30

4. 6 IPSOL vs. VDS
Ta = 25C

120
100

250

80

200

60
40

Ta = 25C

300

IPSOL [A]

IPSOH [A]

25

150
100
50

20

0

0
0

5

10

15
20
VDS [V]

25

30

0

5

10

15
20
VDS [V]

25

30

25

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series
5.

Temperature detection function
5. 1 rTHCH vs. Ta

5. 2 rTHCL vs. Ta
VDS = 17.5 V

0.8

0.8

0.6

0.6

0.4
0.2
0.0

VDS = 17.5 V

1.0

rTHCL

rTHCH

1.0

0.4
0.2

40 250.0025Ta [C]50

75 85

5. 3 rTHDH vs. Ta40 25025Ta [C]

0.8

0.8

0.6

0.6

rTHDL

rTHDH

1.0

0.4
0.2
40 250.0025Ta [C]

50

75 85

5. 6
VDS = 17.5 V

6.0

40 25025Ta [C]50

75 85

tTH vs. Ta
VDS = 17.5 V

3.0
2.5

tTH [s]5.5

VREG [V]0.4
0.2

5. 5 VREG vs. Ta

5.0
4.5
4.0

75 85

VDS = 17.5 V

1.0

0.0

50

5. 4 rTHDL vs. Ta
VDS = 17.5 V

26

Rev.1.4_00

2.0
1.5

40 251.0025Ta [C]5075 85

40 25025Ta [C]

50

75 85

BATTERY MONITORING IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
S-8255A Series

Rev.1.4_00

 Power Dissipation
20-Pin TSSOP
Tj = 125C max.

2.0
Power dissipation (PD) [W]

B
1.5

A

1.0

0.5

0.0

0

25

50

75

100

125

150

175

Ambient temperature (Ta) [C]
Board
A
B
C
D
E

Power Dissipation (PD)
1.47 W
1.69 W






27

20-Pin TSSOP Test Board
IC Mount Area
(1) Board A
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]

1
2
3
4

Thermal via

Specification
114.3 x 76.2 x t1.6
FR-4
2Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.070-(2) Board B
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]Thermal via

1
2
3
4

Specification
114.3 x 76.2 x t1.6
FR-4
4Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070-

No. TSSOP20-A-Board-SD-1.0

ABLIC Inc.

6.5±0.3

0.65

20

11

1

10

+0.1

0.15 -0.05

0.22±0.1

No. FT020-B-P-SD-1.0

TITLE

TSSOP20-B-PKG Dimensions

No.

FT020-B-P-SD-1.0

ANGLE
UNIT

mm

ABLIC Inc.

+0.1

ø1.5 -0

4.0±0.1

2.0±0.1

0.3±0.05+0.1

8.0±0.1

ø1.5 -0

6.9±0.1

1

20

10

11

Feed direction

No. FT020-B-C-SD-1.0

TITLE

TSSOP20-B-Carrier Tape

No.

FT020-B-C-SD-1.0

ANGLE
UNIT

mm

ABLIC Inc.

60°

17.4±1.0
21.4±1.0

Enlarged drawing in the central part
ø21±0.82±0.5
ø13±0.2

No. FT020-B-R-SD-1.0

TITLE

TSSOP20-B-Reel

No.

FT020-B-R-SD-1.0

ANGLE

QTY.

UNIT

mm

ABLIC Inc.

4.000

Disclaimers (Handling Precautions)1.

All the information described herein (product data, specifications, figures, tables, programs, algorithms andapplication circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.

2.

The circuit examples and the usages described herein are for reference only, and do not guarantee the success ofany specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any otherright due to the use of the information described herein.

3.

ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information describedherein.

4.

Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due tothe use of the products outside their specified ranges.

5.

Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.

6.

When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-relatedlaws, and follow the required procedures.

7.

The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,biological or chemical weapons or missiles, or use any other military purposes.

8.

The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.

9.

In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products areallowed to apply for the system on customer's own responsibility.

10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of thisdocument described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07

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