Safety and reliability

R2 Design FlowsPR ESE RVATION OF PLACE AN D ROUTE.
FU NCTIONAL AN D PHYSICAL ISOLATION.
DYNAM IC R ECON FIG U RATION.
FU LLY ROUTE D PARTIAL B ITSTR EAM.

R2 FLOWS: ENABLING SAFE AND RELIABLE SOC
SOLUTIONS FOR CERTIFIABLE APPLICATIONSR2 Flows:  Reusable and Reliable
Design Flows• Reduce system cost and NRE• Reduce risk and certification burden• Enhance system functionality
and availability• Based on 4th generation fail-safe heritage

R2 Flows include:• Partitioning and Preservation• Isolation Design Flow

Xilinx R2 Flows are built on the foundation of design partitioning and preservation ofplacement and routing. These flows leverage Xilinx’s extensive expertise and heritage
in secure military applications.
Isolation Design Flow is a direct result of heritage work in Single Chip Cryptographic
Milcom radio designs which rely on separation of red-side and black-side processing
for assurance of data integrity within a single device. Similarly the Qualified Bitstream
Flow is based on the core capabilities that enable delivery of a fully placed and routed
partial bitstream, the Security Monitor IP Core. The fundamental enabling technology
in Xilinx FPGA silicon and design environments allow us to support these flows aswell as Dynamic Partial Reconfiguration.
R2 Flows enable advanced, safe, and reliable SoC FPGA applications. They are suitedfor certifiable applications including avionics, automotive, industrial, and medical.
R 2 F lows

• Dynamic Partial Reconfiguration• Qualified Bitstream FlowFirst Configuration

Second Configuration

Qualified Bitstream Flow

R2 Flows are:• Suitable for hi-rel applications such asavionics, automotive, industrial, medical• Enabling complex SoC FPGA designs
targeted for safe and reliable applications

Isolation Design Flow
Fenced Configuration

Partial Reconfiguration Flow

• Supporting of IP reuse with reduced
certification or verification burden• Ideally suited for Xilinx’s 7 series devices
with scalable optimized architecture
Four independent yet related design flows built on a common foundation. Mix and match the flows to meetsystem goals.

Safety and reliability

Partitioning and Preservation

R2 Design Flows

F irst and S econd C onfigurations

Locked and preserved placement and routing for specified
functional blocks. Example: Three functions implemented via ahierarchical design are placed an routed. One function, thered, uses preservation to retain its exact placement androuting. In rerouted design the other two functions can use all
unutilized resources. The verified behavior of locked, red,function remains unchanged. The precise placement, and thus
performance, is unchanged.
Based on the design rules, using existing tool flow, this flow
reduces NRE for engineering changes, and it forms thefoundation for other R2 flows.

Isolation Design Flow

I solated C onfiguration

Supporting enhanced verification and mixed-level certification in a single device.
Isolation Design Flow adds verifiable physical isolation, to partitioning andpreservation.
Approved for secure cryptographic systems that require information assurance.
• Utilizing a justifiable/certifiable design flow
• Leveraging an independent Isolation Verification Tool (IVT)• Ensuring physical and functional isolation

I D F D esign Iterations

A commercial systems reference design, XAPP584, gives atutorial; implementing a lockstep soft core MicroBlaze(tm)processor design with adherence to IDF design rules andwalking through the full flow to verification using IVT.
Achieve:• Isolation of critical and non-critical functions• Reduction of common cause failure modes• Separation of test and debug logic• Enhanced verification capability• Reduced NRE for design modifications
IDF XAPP584 design shown in Floorplaner, SVG, and FPGA Editor
post implementation.

Well suited for:• Avionics applications requiring DO-254• Industrial systems requiring IEC 61508• Other certifiable systems requiring functional safety androbust designSafety and reliability

R2 Design Flows

Dynamic Partial R econfiguration

Dynamic Partial Reconfiguration enables dynamically adaptiveapplications with on-the-fly/real-time reprogramming ofhardware during operation.
Allow multiple algorithms to run in a single hardware platform.
Adapt functionality for a given operational scenario. Leveragea time multiplexed hardware implementation.
Achieve:• Higher performance• Lower cost
• Increased power efficiency
Well suited for:• Software Defined Radio• Imaging and Video systems• Sensor Payloads• Adaptive systems• Self-healing applications• Hardware muli-tasking
Swappable algorithms can enable smaller device sizes and reduced power.

Q ualified B itstream F low

Qualified Bitstream Flow is a newly emerging advanced flowthat allows for reuse of fully placed routed partial bitstreams.
Security Monitor is the first and only IP core in world to bedelivered as a fully placed and routed IP. With significant
heritage Xilinx is now expanding the capability to other IP coreand customer uses.
The flow follows design floor planning rules to allow insertionof partial bitstreams. IP solutions may be generated andverified to the bitstream level. After integration and fullybuilding the final device bitstream, the partial bitstream can still
be verified against the golden verified source, irrespective ofdesign flow versions.
QBF is the ultimate reusable IP solution, with an unmatcheddegree of integrity and security.

Qualified bitstream can be inserted in design and later extracted forcomparison against golden source.

Safety and reliability

R2 Design FlowsR 2 D esign F low
1. Partitioning and Preservation Design Flow

Synthesize HDL

2. Isolation Design Flow
Isolation
Region A

Design Rule
Checks

FENCE

FENCE

Logic
Comparator
Region B

Isolation
Region D

Isolation
Region A1MAP
Place and RouteTiming Simulationand Static Timing
Analysis

Isolation
Region CFENCE

TranslatePost-Translate
Simulation

FENCE

Functional
Simulation

Isolation Verification
Tool (IVT)FENCE

Generate HDL

Verification Steps

Design Isolation
ChecksBitstream
Generation

4. Qualified Bitstream FlowA

3. Reference DesignPlatform
ACB

DCB

AC

Begin building advanced, efficient, cost-effective, scalable, certifiable SoC applications today.

Take the NEXT STEP
For documentation and more information about R2 Flows, and for information regarding DO-254 and SEU Mitigation, visit theavionics site, and avionics developers site, accessible at: www.xilinx.com/avionics/
For information regarding licensing of Isolation Design Flow (IDF), or Dynamic Partial Reconfiguration, consult a local Xilinx sales rep.
For interests in the Qualified Bitstream Flow (QBF), please email avionics@xilinx.com
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