Building Heterogeneous
Chiplets with AMBA
Interconnects

Jeff Defilippi, Senior Director Product Management
Feb 26, 2023
© 2023 Arm

Building Heterogeneous Chiplets with AMBA Interconnects
The scalable AMBA CHI (Coherent Hub Interface) specification has provided thefoundation for building complex SoCs across a broad range of applications including
mobile, networking, automotive and data centers. The high-speed, credited, packetized
attributes make it well suited to build multi-chip(let) networks.
This talk will highlight the scope of a new AMBA CHI Chip-to-Chip specification that iscurrently in development and illustrate how the specification will complement chiplet
standards such as UCIe.

2© 2023 Arm

Economics Driving Chiplet Investments
Increasing design cost with less benefit• Logic continues to scale, but IO & SRAM

only shrinking by 5~10%

SoC NRE limiting product derivatives• Chiplets lowers overall platform cost and barrier

to deploy a diverse product portfolio

Market demands performance and efficiency• New chiplet technology offers a 20x speed andpower improvement over traditional PCIe SERDES
Source: IBS, as cited in IEEE Heterogeneous Integration Roadmap

3© 2023 Arm

SoC Accelerator Framework for Heterogenous Compute
Moving from Monolithic to Chiplet
SINGLE DIE(AMBA)

CPUIO

4

© 2023 Arm

MULTI-DIE(UCIe)

AA

CPUA

A
MemIO

Mem

MULTI-CHIP on
PCB(PCIe, CXL)The Path to a Chiplet Ecosystem
Multi-Vendor
Chiplet Ecosystem
Semi-Custom
Chiplet Platform
CustomChiplet Platform•

PHY, Transport and Protocol
standards drive IP development
and broader adoption

5© 2023 Arm•

PHY, Transport and Protocol
standards required forinteroperability•

PHY, Protocol and Transport•

Mechanical, thermal & power•

Pre/post-silicon test & debug•

Software standards•

Silicon qualification andreliability

The Path to a Chiplet Ecosystem
Multi-Vendor
Chiplet Ecosystem

We are here

Semi-Custom
Chiplet Platform
CustomChiplet Platform•

PHY, Transport and Protocol
standards drive IP development
and broader adoption

6© 2023 Arm•

PHY, Transport and Protocol
standards required forinteroperability•

PHY, Protocol and Transport•

Mechanical, thermal & power•

Pre/post-silicon test & debug•

Software standards•

Silicon qualification andreliability

AMBA: Specifications, Interface and Protocols Diagram
Key AMBA Specifications: CHI, ACE, AXI, AHB, APB
Key AMBA specifications

AMBA

CHI

Credited coherent protocol
Layered architecture for scalability

ACE

ACE is a superset of AXI – system-wide
coherency across multicore clusters

AXI

AXI supports separate A/D phases, bursts,
multiple outstanding addresses, OoO responses

Coherent Hub Interface

AXI coherency Extensions

Adv. eXtensible Interface

AHB

Adv. High-performance Bus

APB

Advanced Peripheral Bus

AMBA 3© 2023 Arm

AMBA 5ACE

ACE5

AXI4

AXI5+LiteAPB

AXI3AHBAHB

APB2APB3+Lite, +Stream+Lite

AHB5+Lite

Selected AMBA specifications only. Other specifications include: ATB, ATP, CXS, DTI, GFB, LPI and LTI.
7AMBA 4CHI

AHB supports 64/128 bit multi-managers
AHB-Lite for single managers
System bus for low
bandwidth peripherals

AMBA 2+Lite

APB4

APB5

AMBA: Specifications, Interface and Protocols Diagram
Key AMBA Specifications: CHI, ACE, AXI, AHB, APB
Key AMBA specifications

AMBA

CHI

Credited coherent protocol
Layered architecture for scalability

ACE

ACE is a superset of AXI – system-wide
coherency across multicore clusters

AXI

AXI supports separate A/D phases, bursts,multiple outstanding addresses, OoO responses

Coherent Hub Interface

AXI coherency Extensions

Adv. eXtensible Interface

AHB

Adv. High-performance Bus

APB

Advanced Peripheral Bus

AMBA 3© 2023 Arm

AMBA 5ACE

ACE5

AXI4

AXI5+Lite

APB

AXI3
AHB

AHB

APB2

APB3+Lite, +Stream+Lite

AHB5+Lite

Selected AMBA specifications only. Other specifications include: ATB, ATP, CXS, DTI, GFB, LPI and LTI.
8AMBA 4CHI

AHB supports 64/128 bit multi-managers
AHB-Lite for single managers
System bus for lowbandwidth peripherals

AMBA 2+Lite

APB4APB5

NVIDIA Grace Hopper Superchip
Combining Grace CPU (72x Arm Neoverse V2 CPUs)
with Hopper GPU inside the package
New 900 GB/s NVIDIA-CTC interconnect
using AMBA CHI for the multichip protocol
Unified virtual memory systemwith shared paged tables
30X Higher System Memory
B/W to GPU in a Server

9© 2023 Arm

Grace Hopper Superchip

Extending AMBA Architecture to Multichip
with CHI C2C

New AMBA CHI Chip-to-Chip Specification inDevelopment

ACPUAIOMem

A unified interface for device attach• Compute, Accelerator and Memory• Coherent and IO Coherent accelerator traffic

Architectural features extended across chip(let) boundaries• Virtualization (DVM), Interrupts, Timers• Telemetry and Resource Management• Security for trust, memory protection and Confidential Compute

Composable with die re-use across different solutions
Accelerator
Memory (DDR, HBM, etc)
IO (PCIe, CXL, etc)

10

© 2023 Arm• Appropriate for Multi-Die and Multi-chip through PCB• Supports UCIe and bespoke PHY options

CHI Protocol Overview
AMBA 5 CHI protocol features:• Full cache coherency model• Supports snoop filter and directory-based systemsfor snoop scaling• Definition for simpler IO and Memory interfaces

Other features:• Credited, non-blocking, high-speed transports• Configurable bus width - 128, 256 or 512 bits

• Support for end-to-end Quality of Service (QoS)• Virtual memory management through Distributed

Virtual Memory (DVM) operations

AMBA CHI Specification:

https://developer.arm.com/search#q=amba%205%20chi%20architecture%20specification11© 2023 Arm

REQ

Request Channel

RSP

Response Channel

DAT

Data Channel

SNP

Snoop Channel

AMBA CHI Chip-to-Chip Specification
Packetization of CHI channels with cross-chip credit exchange
CHI Channels

Link aggregation for bandwidth scalability

CHI C2C
Gateway

ON-CHIP
INTERCONNECT

Portability across different PHY and packaging technology
Clean interface definition between on-chip interconnect andPHY/Link Layer for IP portability between vendors

Data Link Layer
PHY

Support for point-to-point and chiplet network topologies
Tx12© 2023 Arm

Rx

DIE-TO-DIE PHY

Packetization Layer

REQ

REQ

RSP

RSP

DAT

CHI FLITCHI FLIT

SNP

SNP

MISC

MISC

Link Layer

C2CInterface

C2C
Interface

Physicalchannel
Data-link
Retry Buffer13© 2023 ArmDATCRC Check andData-link Retry

Link LayerProtocol
Layer

Protocol
Layer

Packetization Layer

Packetization Layer

REQREQ

RSP

RSP

DAT

CHI FLITCHI FLIT

SNP

SNP

MISC

MISC

Link Layer

C2CInterface

C2C
Interface

Physicalchannel
Data-link
Retry Buffer14© 2023 ArmDATCRC Check andData-link Retry

Link Layer

ProtocolLayer

Protocol
Layer

Packetization Layer

Message classcredit exchange

Open Chiplet: Platform on a Package
Align Industry around an
open platform to enable
chiplet based solutions
Enables construction of SoCs that exceed maximum reticle size
• Package becomes new System-on-a-Chip (SoC) withsame dies (Scale Up)
Reduces time-to-solution (e.g., enables die reuse)
Lowers portfolio cost (product & project)• Enables optimal process technologies• Smaller (better yield)• Reduces IP porting costs• Lowers product SKU cost
Enables a customizable, standard-based product for specificuse cases (bespoke solutions)
Scales innovation (manufacturing and process locked IPs)

15

© 2023 Arm

Customer IP &Customized Chiplets

High-Speed Standardized
Chip-to-Chip Interface (UCIe)

Sea of Cores(heterogeneous)• 20X I/O Performance at
1/20th Power vs offpackage SerDes atLaunch• Gap more prominent
with better on-package
technologies in future
MemoryAdvanced2D/2.5D/3DPackaging

Heterogeneous Integration Fueled by an Open Chiplet Ecosystem(Mix-and-match chiplets from different processnodes / fabs / companies / assembly)

UCIe Layered Architecture
UCIe 1.0 provides a complete multichip interface specification
Leverages PCIe/CXL protocol for architectural agnostic attach• PHY definitions for 2.1D and 2.5D packaging•AMBA CHI C2C will use the UCIe Streaming Interface•

Streaming interface with additional flit formats provide link robustnessusing UCIe defined data-link CRC and retry

Arm will support both CHI and CXL/PCIe options to provide
flexibility for the wide range of potential chiplet integrations

PROTOCOL LAYER

DIE-TO-DIE ADAPTERPHYSICAL LAYERAMBACHI C2CCXL/PCIe

ARB/MUX (when applicable)
CRC/RETRY (when applicable)
LINK STATE MANAGEMENTPARAMETER NEGOTIATIONLINK TRAINING
LANE REPAIR (when applicable)
LANE REVERSAL (when applicable)
SCRAMBLING/DE-SCRAMBLING (opt-in)
SIDEBAND TRAINING & TRANSFERS
ANALOG FRONT END
CLOCK FORWARD

UCIe defines support for both 2.1D and 2.5D packaging
https://www.uciexpress.org/webinars

16© 2023 Arm16

AMBA CHI C2C Extends on-chip performance to Multi-chip(lets)
Economics are driving chiplet investments and momentum toward Semi-Custom Chiplet Platforms• Standards investments for PHY, Transport and Protocol IP accessibility and interoperability• New PHY and packaging technology offering ‘on-chip’ performance and efficiency; 20x speed and power

improvement over traditional PCIe SERDESNew AMBA CHI Chip-to-Chip specification will extend the on-chip bus to multi-chip• Provides a unified memory, security and virtualization architecture across chiplets• Built to run over standards based die-to-die interconnects such as UCIe or bespoke solutions

Stay tuned!

• AMBA CHI C2C specification is under development, more updates expected throughout the year

17

© 2023 Arm© 2023 Arm

Thank You
DankeGracias
Grazie谢谢
ありがとう
AsanteMerci감사합니다
ध"यवाद
Kiitos‫ﺷﻛًرا‬ধন#বাদ‫תודה‬The Arm trademarks featured in this presentation are registeredtrademarks or trademarks of Arm Limited (or its subsidiaries) inthe US and/or elsewhere. All rights reserved. All other marks
featured may be trademarks of their respective owners.
www.arm.com/company/policies/trademarks© 2023 Arm