Chapter 7
Conclusions
The followings are the conclusions through this thesis.

Chapter 2
The power consumption in CCD image sensor is estimated as proportional to thecubic of the number of pixels in line, which will be one of the most serious problems
in mega-pixel CCDs.
The probabilistic model of power consumption for both combinational logics andsequential circuits are described.
It is also described the power reduction methodologies for both combinational
logics and sequential circuits without modi cation of their function.
The power consumption of combinational logics, 1 bit full adder as an example,
is expected to be reduced up to 030% by optimum input assignment for logicallysymmetric input terminals.
The power consumption of sequential circuits is expected to be reduced up to010% by the binary state code assignment minimizing the mean number of transition at each clock cycle, against the conventional state code assignment minimizing
the complexity of combinational logics. In this case, the number of transistors incombinational logics increases about 10% by minizing power consumption against
minizing the complexity of combinational logics, while the total number of transis-

Chapter 7 Conclusions

125

tors increase less than 10%, since the number of ip- ops is the same.

Chapter 3
A method of using tree structure for image signals is proposed, which is e ective
especially for the image containing many 0s by skipping redundant scan steps forthe large area of 0s.
It is also derived that the optimal number of branches in the tree structure is 4,
which we call \1:4 tree structure". The expectation of code length using 1:4 tree
structure is shorter than that of the raster scan in case of less than quarter of thepixels are \1" in random white noise image, but in the practical image containing
about half of \1" pixels can be scanned by 1:4 tree scan with the shorter code lengththan that of the raster scan.
It is also indicated that the code length by the scan using 1:4 tree structure isshorter than that of run-length compression, especially in case of containing many
white pixels.
The methodology for decoding the 1:4 tree code is also described, where thepartially decoded images represent the rough images corresponding to the current
level of 1:4 tree structure.

Chapter 4Some concepts and implementations are described for the applications of 1:4 tree
sensor for various adaptivities of images as our eyesight has, and the algorithms usedin movie compression, and visual tracking system.
The spatial adaptivity for scanning images is implemented by 1:4 tree scan withstopping the scan steps to the lower level, since the sub-areas corresponding to thenodes in the lower level represent the part of image with the higher spatial resolution.
The selection whether the rough scan or the detail scan for each sub-area should
be executed, is determined according to the interests for it. One of the criteria
determining the spatial resolution for each area is the partial uniformity of image,

Chapter 7 Conclusions

126

and the detail scan is executed for the sub-area with low uniformity, while the roughscan is executed for the sub-area of high uniformity. This scan method indicates
one possibility of compressing images with maintaining the quality of image.
It is also described the intensional adaptivity for image signals using 1:4 tree
structure, since the charge time of junction capacitance by photo current is concernedwith the light intensity. The spatial distribution of the pixel whose output voltage
reaches to the threshold voltage at each charge time, gathers spatially, which is thecase that 1:4 tree scan can be executed eciently.
The applications of 1:4 tree scan for two important algorithms used in movie
compression, inter-frame di erence and motion compensation, are described.
The 1:4 tree scan is used for the scan of ag indicating the pixels has a e ective
di erence in successive two frames, which is the case that 1:4 tree structure can scaneciently, and the analog value of di erence can be read out by the other signal
path.
The motion compensation within one pixels, which is expected to be suitable
assuming high frame rate, can be implemented by adding the interconnections amongneighbor pixels and the selector of them to each pixel. It is also notable that themotion compensation using this algorithm can be executed for any size of sub-areas,since the node automata has the mean value of its lower sub-areas.
It is also described the visual tracking algorithm using 1:4 tree structure, which
can scan just for the areas containing moving objects with masking the other areas.

Chapter 5
The implementations of 1:4 tree structure in CMOS circuit are described. In thedesigned node automata, the clock signals are provided just along the scan path,
which is expected to be suitable for low power operation. The two dimensionallayout of node automata and pixels that can be extended for any number of levels
are described, by placing the magni ed cross-shaped node automata for the higher
level, which is also suitable for minizing the signal delay.
The alternative implementation of 1:4 tree structure is also described, by plaicing

Chapter 7 Conclusions127

address decoders indicating the pixels to be scanned outside the pixel plain. The
1:4 tree sensor using this architecture is expected to achieve the higher ll factor
and higher integration of pixels in image sensor.
The architecture of decoder for 1:4 tree code is also described, which is implementing the identical address decoders and controllers used in the 1:4 tree sensor
using external address decoders.
The circuits of pixels are also described, which implement taking inter-frame difference, and gray scale scan considering charge-up time by photo current.
It is also described the concept of light-powered 1:4 tree sensor for ultra low power
operation.

Chapter 6
The design and evaluation of 1:4 tree sensors using node automata are described,
for both prototype system using FPGAs and full custom chip using 1.5m CMOS
technology is discussed. The designed chip contains 32 2 32 pixels in 7.2mm27.2mm
chip, and its power consumption at each scan step is expect to be proportional to theedge size, which is smaller enough than CCD image sensors in mega-pixel sensors.
The photo current of photo diodes is also measured, and the photo current of thephoto diode with 36m 2 100m is about 1A, and it is proportional to both lightintensity and area of photo diode.
The design and evaluation of 1:4 tree sensors using external address decoders aredescribed. The designed 1:4 tree sensor using external address decoders can integrate
about 16 times of pixels against using node automata. The power consumption of
1:4 tree sensors using external address decoders is estimated using spice, which isproportional to O(n0 84 ), where n is the edge size of pixel plain, that is expected besmall enough for mega-pixel image sensors.
The designs of 1:4 tree code decoders are also described, both in prototype systems
using FPGAs and full-custom chip using 1.5m CMOS technology are described,
and the operation of the prototype systems is checked.
:Chapter 7 Conclusions

128

List of Presentations andPublications
Chapter 2

 J.Akita and K.Asada, \A Method of Reducing Power Consumption of CMOS
Logic Based on Probability Model of Signal Transition," Technical Report ofIEICE, ED93-83, Sep. 1993.

 J.Akita and K.Asada, \A Method for Reducing Power Consumption of CMOS
Logic Based on Signal Transition Probability," Proc. of EDAC-ETC(EuropianDesign Automation Conference & Europian Test Conference) Euro ASIC,Mar. 1994.

 J.Akita and K.Asada, \A Method for Power Reduction of Finite State Circuitwith Optimum State-code Assignment," Technical Report of IEICE, ICD94104, Sep. 1994.

 H.Hayashi, J.Akita, and K.Asada, \A Method of Optimal State Code Assignment for Reducing Power Consumption in Synchronous Circuits," Proc. of1994 IEICE Fall Conference, A-67, Sep. 1994.

 J.Akita, H.Hayashi, and K.Asada \An Estimation and Reduction of Power
Consumption in Clock Line of Synchronous Flip-Flops," Proc. of 1994 IEICE
Fall Conference, A-68, Sep. 1994.

 K.Asada and J.Akita, \Optimum State Assignment for CMOS Implementation
List of Presentations and Publications

129

of Low Power Finite State Machine," Proc. of IFIP Workshop on Logic andArch. Synthesis, Dec. 1994.

 J.Akita and K.Asada, \An Estimation of State Code Assignment for Low
Power Finite State Circuit," Proc. of 1995 IEICE Spring Conference, A-108,Mar. 1995.

 K.Asada and J.Akita, \A Method for Reducing Power Consumption of CMOS
Logic Based on Signal Transition Probability," IEICE Trans. on Electronics,
Vol.E78-C, No.4, pp.436{440, Apr. 1995.

Chapter 3

 J.Akita and K.Asada, \A Signal Scanning Method of Sensors With Hierarchal
Structure of Node Automata," Technical Report of IEICE, VLD95-62, Sep.
1995.

 J.Akita and K.Asada, \An Image Scanning Method with Data Compression
using Tree Structure of Automata," Proc. of 1996 IEICE Spring Conference,
A-43, Mar. 1996.

 J.Akita, R.Watabe, and K.Asada, \A Novel Tree Structure of Automata for
Selective Scanning of Image Signals," Proc. of the ITEC'96, p.33, Jul. 1996.

 K.Asada and J.Akita, \Image Sensor using Tree Structure," Symposium on
Scienti c Research on Priority Areas, \Ultimate Integration of Intelligence on
Silicon Electronic Systems", Mar. 1997.

 J.Akita and K.Asada, \Image Data Compression Eciency using Tree Scanning and Run-length Coding," Proc. of 1997 IEICE Spring Conference, A-610, Mar. 1997.

 K.Asada, J.Akita, and R.Watabe, \A Tree Structure of Automata for Selective Image Scanning and Its Implementation," Comp. & Elec. Eng. (to bepublished).

List of Presentations and Publications

130

Chapter 4

 K.Asada, J.Akita, M.Nawamin, and R.Watabe, \Intelligent Lower Power Devices and Circuits," Symposium on Scienti c Research on Priority Areas, \Ultimate Integration of Intelligence on Silicon Electronic Systems", Mar. 1996.

 K.Asada and J.Akita, \A Selective Image Scanning Method using Tree Structure of Automata and Its Implementation," Proc. of 1996 IEICE Fall Conference, ES-3-7, Sep. 1996.

 K.Asada, J.Akita, and R.Watabe, \A Tree Structure of Automata for SelectiveImage Scanning and Its Implementation," Proc. of 4th Int. Conf. on SoftComputing (IIZUKA'96), pp.113{116, Oct. 1996.

Chapter 5 and 6

 R.Watabe, J.Akita, and K.Asada. \An Implementation on CMOS Circuit ofTree Structure of Automata for Image Scanning," Proc. of the ITEC'96, p.35,
Jul. 1996.

 J.Akita and K.Asada, \An Implementation of Image Scanning Method with
Selective Activation of Tree Structure," Proc. of 1996 IEICE Fall Conference,A-54, Sep. 1996.

 J.Akita and K.Asada, \An Image Sensor using Quad Tree for Selective Scanning with Adaptive Resolution," Proc. of IEEE CCD & AIS Workshop, p.5-1,
1997.6.

 J.Akita and K.Asada, \An Image Scanning Method with Selective Activationof Tree Structure," IEICE Trans. on Electronics, Vol.E80-C, No.7, pp.956{961, 1997.7.

 J.Akita and K.Asada, \A CMOS Image Sensor with Variable Block AccessFunction," Proc. of 1997 IEICE Fall Conference, C-12-39, Sep. 1997.

List of Presentations and Publications131

Acknowledgement
It is a great pleasure to express my gratitude to the dissertation supervisor, Professor Kunihiro Asada, for his heartful advices and hints through the term of this work,and his encouragements for the comfortable circumstances of this work. His help
and encouragement in both professional and private manners greatly has in uencedme from various points of view.
I would like to give my thanks to Professor Kiyoharu Aizawa in University ofTokyo, and Dr. Takayuki Hamamoto, who is currently a research assistant of Science
University of Tokyo, for giving many helpful discussions and hints, in the projectof scienti c research on priority areas, mainly from the viewpoints of the image
processing researchers and image sensor designers.
I am also thankful to all of my past and present colleagues in Asada Laboratory
who gave me helpful advices, heartful encouragement, comfortable research circumstances and pleasant time, especially Dr. Makoto Ikeda, who is currently research
assistant of VLSI Design and Education Center, for his e orts of comfortable computer circumstances, and Dr. Rimon Ikeno, who is currently in Texas Instruments
Tsukuba Research & Development Center Ltd., for his heartful encouragements anduseful hints on researches.
I also thank Mr. Hiroyuki Hayashi for his cooperations in the research for thepower reduction methodologies of the sequential circuits.
I would like to express my thanks to Mr. Mukdathong Nawamin, Mr. Ryota
Watabe, who is currently in Matsushita Communication Industrial Co., Ltd., andMr. Kenji Hirota, who is currently in KDD Co. Ltd., and Mr. Masashi Hoshino,for their cooperations in the research for development of the prototype systems of132

1:4 tree sensor and 1:4 tree code decoder.
I also would like to thank to Mr. Tomohiro Nezuka, and Mr. Kagehiro Mukai, fortheir cooperations in the research for the intelligent pixel circuits.
I esteem Mr. Shinichi Suzuki, Ms. Noriko Yokochi, and Ms. Makiko Okazaki for
their help for my activities in the laboratory.
I would like to thank to Professor Yoshihiro Mizoguchi, who is associate professorof Kyushu Institute of Technology, for his advice on the previous studies on quadtree in image processing from the viewpoint of mathematical science. I also thankto Mr. Hideyuki Suzuki, who is in the doctor course student in Department ofMathematical Engineering and Information Physics, University of Tokyo, for hisadvice on the mathematical methodologies for the two dimensional random images
with the desired power spectrum characteristics. I would like to give my thanks
and love to all of my friends, especially in Yugen Club o ered by Professor Heisuke
Hironaka, who is currently the president of Yamaguchi University, through his eager
activities for mathematical science education. I would like to express my thanks
and love to Naoko Kamiryo in the medical course of Hiroshima University, for herheartful encouragement.
Finally, I would like to express my thanks and love to my father and my motherin my home town, Nagoya, who have been continuously supporting me throughout
my life.

133

Bibliography[1] A.Moini, \Vision Chips or Seeing Silicon,"
http://www.eleceng.adelaide.edu.au/Groups/GAAS/Bugeye/visionchips/index.html[2] M.Yasuda et al., \An Electronic Model of Visual Receptive Fields," Trans. ofIEICE(Japanese) Vol.54-C, No.6, pp.514{521, 1971.
[3] C.Mead, \Analog VLSI and Neural Systems," Addison-Wesley Reading, 1989.
[4] A.Moini et al., \An Analog Implementation of Early Vision Processing in Insects," Proc. of 1993 VLSITSA, pp.283{287, 1993.
[5] H.Kobayashi et al., \An Active Resistor Network for Gaussian Filtering of Images," IEEEE Journal of Solid-State Circuits, Vol.26, No.5, pp.738{748, 1991.
[6] H.Kobayashi et al., \An Analog CMOS Network for Gaussian Convolution withEmbedded Image Sensing," ISSCC Dig. of Tech. Papers, pp.216{217, 1990.
[7] C.Koch, \Implementing early vision algorithms in analog hardware," Proc. SPIE,
Vol.1473, pp.2{16, 1991.
[8] A.Gruss et al., \A VLSI Smart Sensor for Fast Range Finding," Proc. IEEE Int.
Conf. on Intelligent Robots and Systems, pp.349{358, 1992.
[9] S.E.Kemeny et al., \CCD Focal-Plane Image Recognization Prosessors for Lossless Image Compression," IEEE Journal of Solid-State Circuits, Vol.27, No.3,
pp.398{405, 1992.

Bibliography134

[10] T.Hamamoto et al., \Focal Plane Compression and Enhancement Sensors,"ISCAS'97, Vol.3, pp.1912{1915, 1997.
[11] T.Nishimura et al., \Three Dimensional IC For High Performance Image SignalProcessor," Proc. IEDM, pp.111-114, 1987.
[12] A.Yakovle et al., \A micro-sensor based on insect vision," Workshop on Conputer Architecture for Machine Perception, pp.137{146, 1993.
[13] M.Koyanagi et al., \Three-dimensional laminated image processing systems,"Symposium on Scienti c Research on Priority Areas, \Ultimate Integration ofIntelligence on Silicon Electronic Systems", Mar. 1997.
[14] R.H.Dennard et al., \Design for ion-implanted MOSFET's with very small
physical dimensions," IEEE Journal of Solid-State Circuits, Vol.9, No.5, pp.256{268, 1974.
[15] \Panasonic Data Book of CCD '96," Matsushita Electronics Corp., 1996.
[16] T. Quarles et al., \SPICE 3B1 User's Guide," Jan. 1989.
[17] S.Devadas et al., \MUSTANG: State Assignment for Finite State Machines
Targeting Multilevel Logic Implementation," IEEE Trans. on Computer-Aided
Design, Vol.7, No.12, 1988.
[18] H.Samet, \Region representation: quad trees
from binary arrays," Computer Graphics and Image Processing, Vol.13, pp.88{
93, 1980.
[19] J.van der Spiegel et al., \A foveated retina-like sensor using CCD technology,"in Analog VLSI implementation of neural systems, Kluwer Academic Publishers,
1989.
[20] T.Yagi et al., \The role of retinal bipolar cells in early vision: an implication
with analog networks and regularization theory," Biological Cybernetics, Vol.77,
pp.163{171, 1997.

135

[21] T.M.Bennard et al., \A programmable VLSI retina for rough vision," MachiVision and Applications, Vol.7, pp.4-11, 1993.
[22] C.Mead, \A Sensitive Electronic Photoreceptor," Chappel Hill Conference onVLSI, pp.463{471, 1985.
[23] V.Ward et al., \VLSI Implementation of Receptive Fields with Current-ModeSignal Processing for Smart Vision Sensors," Analog Integrated Circuits and Signal Processing 7, pp.167{179, 1995.
[24] V.Ward et al., \CMOS photodetector with built-in light adaptation mechanism," Microelectronics Journal, Vol.24, pp.547{553, 1993.
[25] ISO/IEC 13818-1, 13818-2, 13838-3 International Standard, 1994.
[26] I.Ishii et al., \Target tracking algorithm for 1ms visual feedback system using
massively parallel processing," Proc. IEEE Int. Conf. Robotics and Automation,
pp.2309{2314, 1996.
[27] N.H.E.Weste et al., \Principles of CMOS VLSI design: a systems perspective,"
Addison-Wesley, 1988.
[28] Y.S.Trisno et al., \Optimization of an Optically Pulsed Photocell Array as aSensor Power Source," IEEE Trans. Instrum. Meas., Vol.37, No.1, pp.142{144,Mar. 1988.
[29] \The Programmable Logic Data Book," Xilinx Inc., 1994.

136