Highlight
Developing a Global R&D Network to Stay Close to Our
Customers and Expanding into New Business Areas
Tokyo Electron is expanding its R&D
network worldwide in a variety of fields

Tokyo Electron’s R&D centers
Partner research organizations

U.S.
imec (Belgium)

Albany NanoTech (U.S.)

CEA-Leti (France)

SEMATECH (U.S.)TEL Technology Center,America, LLC

Korea

TaiwanJapan

TEL Technology Center, Korea

TEL Technology Center, Taiwan

Tokyo Electron Technology Center Tsukuba
Process Technology CenterTokyo Electron Technology Development Institute, Inc.

Ensuring timely delivery of products from a location close to customers
In order to ensure timely delivery of necessary products tocustomers, it is important to establish R&D centers at locations
adjacent to them and to maintain close cooperation to expedite thecommercialization of technology.
In addition to a technology center established in Hsinchu City,
Taiwan in 2010, we also opened a process technology center in South
Korea and a technology center in Tsukuba City, Ibaraki Prefecture in2012 to enhance our ability to meet customers’ needs promptly.
The development of the most advanced technology requires
the creation of novel concepts through the synthesis of technicalknowledge from various fields, making it necessary to leverage

Tokyo Electron Technology Center Tsukuba• Location : Tsukuba City, Ibaraki Prefecture, Japan• Floor area : 13,234 m2• Construction began/completed:
August 2011/March 2012
• Activities :	Research and development ofphotovoltaic panel production
equipment technology andsemiconductor production equipment
technology• Number of employees:
Approx. 110 (plan for the first fiscal year)
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external sources of expertise. Tokyo Electron is actively promoting
collaboration with universities and research consortiums such as
SEMATECH and imec for basic research. The establishment of theTokyo Electron Technology Center Tsukuba has also opened up theway for joint projects with research institutes clustered in Tsukuba
City, allowing us to work together in R&D on new semiconductormaterials and photovoltaic power generation as well as on thecreation of new technological seeds.
These R&D efforts are expected to bear fruit over the next
five to 10 years and yield products that will drive the company’s
continued growth.

The acquisition of NEXX Systems—Paving the way to providing exceptional opportunities
in the emerging 3D interconnect technology arena for energy-saving electronic devices
reduce inductance, allowing higher-speed signals and conducting heatbetter. The wafer level packaging processing equipment market, which
includes flip chip bumping and TSV, is expected to grow at an annual
rate of more than 30 percent in the coming five years.
Tokyo Electron’s acquisition of NEXX will expand its position inadvanced packaging to include electrochemical deposition (ECD) andphysical vapor deposition (PVD) systems that have won awards fortheir outstanding performance, low cost of ownership, development
flexibility, and their extendibility to future applications.
Integrating NEXX’s applications with Tokyo Electron’s broad productline-up and leading global support will enable the company to growits business portfolio while continuing to offer the best solutions tocustomers. NEXX Systems, a wholly-owned subsidiary of Tokyo Electron
US Holdings, Inc., changed its name to TEL NEXX, Inc. on May 1, 2012.

TEL NEXX, Inc.

TEL NEXX’s metal deposition technology enables the formation of not only electrode bumps
but also TSV electrodes for 3D packaging on the wafer, with excellent cost performance.

• Location

MANAGEMENT REPORTTEL NEXX’s advanced wafer-level packaging technology

HIGHLIGHT

Amid the explosive growth of multifunctional mobile devices, such as
smartphones and tablets, it has become critical to produce thinnerand smaller devices that consume less power. Advanced packaging
technologies address these needs. From flip chip bumping to throughsilicon vias (TSV), wafer level packaging has emerged as the fastest
growing semiconductor packaging arena.
Flip chip is a method for interconnecting semiconductor devices,such as IC chips, to external circuitry with solder bumps that have been
deposited onto the chip parts. The solder bumps are deposited on thetop side of the wafer during the final wafer processing step. This is aninnovative departure from conventional wire bonding, in which wires areused to interconnect the chip pads to external circuitry. The resulting
completed flip chip assembly is much smaller and shorter in height
than a traditional wire bonding system. The short interconnects greatly: United States• Number of employees : 153 (as of June 2012)

Wire-bonding

Flip chip

WireBumpChipThinnerChip

TSV*1 3D integrationA chip is bonded using
gold or copper wire.

The bumps formed on the chip are
directly connected to electrodes on thewiring board.
• Thinner and smaller footprint• Higher pattern density, higherperformance• Lower resistance, lower power
consumption

EHS REPORTHeight of package

Development of packaging technology

Multiple semiconductors are verticallyinterconnected.
• Shorter wiring• Far greater number of I/Oterminals*1 TSV : Through Silicon Via

SOCIAL REPORT

Joint development project with Tohoku University
Tokyo Electron will participate in STT-MRAM (magnetic memory) researchand development led by Prof. Tetsuo Endoh of Tohoku University’sGraduate School of Engineering as part of a program to be implemented at
the International Academic-Industrial Collaboration Center for Integrated
Electronics Research and Development (provisional name), which Tohoku
University plans to open in the spring of 2013. The Company will engage inthe development of manufacturing equipment technology.
Tokyo Electron has been working with Prof. Endoh on the developmentof STT-MRAM production equipment technology and integration
technology since December 2011. Under the upcoming program, we willfurther develop this partnership, provide the Center with products, and aim
to quickly establish manufacturing equipment technology and integration
technology for the production of STT-MRAM, which is attracting attention
as a next-generation memory device.

Advantages of STT-MRAM*2 (spintronics memory)• Uses magnetic materials for the semiconductor.
• Realizes lower power consumption for servers, PCs, mobile phones, andother devices.
• Maintains data without power supply (non-volatile).

TOHOKU UNIVERSITY

Device design technology

Magneticmaterial(MTJ* 3)
Process technology

Word line
Bit line

Production equipment
technology

Courtesy of Prof. Tetsuo Endoh, Tohoku University*2 STT-MRAM: Spin Transfer Torque-Magnetoresistive Random AccessMemory*3 MTJ: Magnetic Tunnel Junction

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