Chapter 6
Design and Evaluation of 1:4 Tree
Sensors
In this chapter, the designs and the evaluations for the manufactured 1:4 tree
sensors are described. The characteristics of photo diodes fabricated the used CMOS
1.5m process is discussed at rst.
The prototype systems of the 1:4 tree image sensor using FPGAs will be describedin section 6.2. It will be described the design and the evaluation of the 1:4 tree image
sensor having the tree structure of node automata in the following section 6.3.
The design and the evaluation of the 1:4 tree sensor with the architecture ofplacing address selector externally will be described in section 6.4.
The design and the evaluation of the decoder of 1:4 tree code will be described in
the section 6.5.
6.1

Design and Evaluation of Photo Diodes

We have designed the photo diode TEGs (test element groups) to estimate thephoto current. The designed TEG chip in 2.3mm22.3mm using CMOS 1.5m technology is shown in Figure 6.11 . The designed photo diodes are shown in Figure 6.2.
1 The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI

Design and Education Center(VDEC), the University of Tokyo with the collaboration by Nippon

Chapter 6 Design and Evaluation of 1:4 Tree Sensors

93

Figure 6.1: Chip photograph of the designed photo diode TEGs
N-well (cathode)P+ diffusion (anode)

36um x 100um 36um x 100um
(a)

(b)

100um x 100um(c)Figure 6.2: Designed photo diodes of tree types. (a)small diode, (b)small combshaped di usion diode, and (c)large diode.
Three types of photo diodes are designed; the small one whose size is 36m 2 100mshown in Figure 6.2(a), the one of same size with the comb-shaped p+ di usion inorder to obtain the larger edge length of di usion area shown in Figure 6.2(b), andthe large one whose size is 100m 2 100m shown in Figure 6.2(c).
The characteristics of photo diodes are shown in Figure 6.3. Here the intensity oflight is measured by exposure meter in exposure value (EV), de ned as the follows,

E = 2EV C=S:

(6.1)

where E is the illuminance in lux2 , C is the correction coecient determined exMotorola and Dai Nippon Printing Corporation.
2 1[lux] is de ned as the illuminance at the distance of 1m from the light source of 1[cd]. 1[cd]Chapter 6 Design and Evaluation of 1:4 Tree Sensors

94

0

Darkness0

Darkness
EV=16
EV=16.5

-0.5

EV=17

-1

EV=16.5-0.5

Id[uA]

Id[uA]

EV=16

EV=17.5

-1.5

EV=17
-1

EV=17.5

-1.5

EV=18

EV=18

-2

-6

0

-4

-2

0

-2

-6

-4

-2

Vd[V]

Vd[V]

(a)

(b)

0

Darkness
EV=16

Id[uA]

EV=16.5
EV=17-3

EV=17.5

EV=18

-6

-6

-4

-2

0

Vd[V]

(c)
Figure 6.3: Measured characteristics of fabricated photo diodes. (a)small diode,(b)small comb-shaped di usion diode, and (c)large diode.

Chapter 6 Design and Evaluation of 1:4 Tree Sensors

95

Photo Current [a.u.]Light Intensity [a.u.]
Figure 6.4: Relation of the normalized photo current per area and the normalized
light intensity
perimentally which is 330, and S is the lm sensitivity used in the exposure meter
which is ISO400 in this case. The distance between exposure meter and light sourceis 3cm.
Seen in Figure 6.3, the photo currents for the photo diode(a) and (b) in Figure
6.2(a) and (b), respectively, are almost the same, and the reason is that the depletion
layer between teeth in comb-shaped di usion area in photo diode (b) is overlapped,
and the distribution of depletion layer, which is the area photon generates the pairof electron and hole, is identical with that of photo diode (a).
It is also indicated that the intensity of light increases twice, the photo current isalso increase about twice, and the photo current is almost proportional to the size
is de ned as 1=60 of the light intensity of the black body whose temperature is the melting pointof platinum, 2045K.

Chapter 6 Design and Evaluation of 1:4 Tree Sensors

96

FPGA-U

FPGA-AFPGA-B FPGA-C

FPGA-D

Figure 6.5: Con gure of the 1:4 tree structure using ve FPGAs.
of the di usion area. The relation of the normalized photo current per area and thenormalized intensity is shown in Figure 6.4, and it indicates that the photo current
is proportional to both light intensity and size of di usion area.
6.2

Prototype System for 1:4 Tree Sensor using Node Automata

6.2.1

Prototype implementation 1:4 tree sensor using FPGAs

We have developed the prototype system of the 1:4 tree sensor using FPGAs(Field
Programmable Gate Array). We have employed the FPGA of XC4025[29] , which isthe production of Xilinx Inc., which has logic blocks whose logical functions can bede ned by the con gure ROMs outside. The developed prototype systems consistsof ve FPGAs, four for the lower sub-trees, and one for the top node, as shown in
Figure 6.5, where the number of pixels is 1; 024 = 210 with the 6 levels of 1:4 tree
structure. Figure 6.6 shows the photograph of the developed prototype system.
The function of the pixel is emulated by having the ip- ops as the pixel value,
which can be set serially from outside using shift registers, as shown in Figure 6.8.
The image data captured by the video camera are transferred to the PC, then the
PC transfers them to the prototype system serially.
The 1:4 tree scan for the prototype systems is executed, with the clock signal from

Chapter 6 Design and Evaluation of 1:4 Tree Sensors

97

Figure 6.6: Photograph of the developed prototype system for 1:4 tree sensor.
the another PC; this PC is prepared to receive the 1:4 tree code and decode it totwo dimensional images, too.
The con gure of this system is described in Figure 6.7(a), with the photograph in
Figure 6.7(b).
6.2.2

Evaluation of prototype system

Figure 6.9 shows the decoded images from the 1:4 tree code generated by thedeveloped prototype system, from the image captured by video camera. The proper
operations of the developed prototype system are observed, and it is also shownthat 1:4 tree code length can be smaller than that of the raster scan, 1024. The
operation of the developed prototype system with the clock frequency up to 1MHz
is observed, which is restricted by the ability of the clock generator. The operation
with the higher clock frequency is expected, since the number of inter-connection
between FPGAs is very small.

Chapter 6 Design and Evaluation of 1:4 Tree Sensors

98

videocameraprototypesystemw/FPGAs

digitizerasterize

PC

PC

(a)

(b)
Figure 6.7: Model of the developed prototype system of 1:4 tree sensor(a), and its
photograph(b).

Chapter 6 Design and Evaluation of 1:4 Tree Sensors

99

Q
D
Q

Q

1:4

St

re

Q

D

D

Q

Q

D

D

Q

Q

D

Q

D

D

to

ee
Tr

tu
ruc

D

D

Q

Q

D

Pixel Set ClockD

Q

Raster Image In
Serial Shift Clock

Figure 6.8: Architecture of serial shift registers to emulate the pixels\Par"(573bit)(a)\Peace"(529it)(b)\Fox"(433it)(c)\Good"(293bit)(d)Figure 6.9: Four sample images decoded from 1:4 tree code generated by the developed prototype system. The code lengthes are also shown below.

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

100

(a)

(b)

Figure 6.10: Layout of the pixel(a) and the node automata(b) in the designed 1:4
tree sensor.
6.3

Design and Evaluation of 1:4 Tree Sensor using Node
Automata

6.3.1

Design of 1:4 tree sensor using node automata

The 1:4 tree image sensor with the tree structure of node automata has been
designed, by using the circuits of node automata designed in Figure 5.2, with the
pixel which can take inter-frame di erence, as designed in Figure 5.15. The layoutsof the each pixel and the each node are shown in Figure 6.10, using CMOS 1.5m
technology, and the whole layout of the chip is shown in Figure 6.11. The chip
photo graph of the fabricated chip is also shown in Figure 6.123 . The chip size is
3 The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI

Design and Education Center(VDEC), the University of Tokyo with the collaboration by Nippon
Motorola and Dai Nippon Printing Corporation.

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

101

Figure 6.11: Whole layout of the designed 32 2 32 pixels 1:4 tree sensor.

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

102

Figure 6.12: Chip photograph of the designed 32 2 32 pixels 1:4 tree sensor.

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

103

L

Figure 6.13: Model of scan path to from the top node to the pixel. L is the lengthof the edge in whole chip.
7.2mm27.2mm, and the number of transistors 104,784, with the ll factor of about
20%.
6.3.2

Evaluation of 1:4 tree sensor using node automata

The power consumption of designed 1:4 tree sensor is estimated by the modeland the simulations. In the designed node circuit, the clock signal is provided justalong the scanned signal path, which is expected to be suitable to reduce power
consumption.

Assuming the number of pixels is n 2 n and the length of edge in whole chip isL, the activated signal scan path from the top node to the pixel is shown in Figure

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

1046.13. The length of this scan path, L , is derived as follows.

X L 2 20 0  L / n
L =

t

N

t

l=1

(l

2

(6.2)

1)

This scan path is activated at every step of 1:4 tree scan, and the power consumption
per step by charging and discharging this scan path is expected to be proportional
to n.
Assuming the number of branches as b, the number of transitions of each nodethrough all the scan steps until nish, is equal to (b + 1) for the nodes whose values
are \1", while no transitions occur in the nodes whose values are \0". Total numberof transition of nodes in whole tree structure, Nnode is expressed as follows,

Nnode = (b + 1)

Xb 0 p ;
N

N

(6.3)

l

l

l=1

where p is the probability that the node at the level l has the value of \1".
The expectation of power consumption per scan step, Nnode , is derived by dividing
Nnode by the mean code length L, as follows.
l

Nnode = Nnode =L

Xb 0 pb+1=
Xb
1+ b 0 p(b + 1)

N

N

l

l

(6.4)

l=1

N

N

l+1

l

l=1

In case of 1:4 tree, assuming b = 4, Nnode is derived as 5/4. In the designed circuitof node automaton shown in Figure 5.2, the expectation of the number of ip- ops
per each transition is derived as follows.
1+1+2+2+2 8
=
5
5

(6.5)

Thus the total expectation of the number of ip- ops which make transitions in thewhole 1:4 tree structure is derived as 5=4 2 8=5 = 2, which is constant through all
the scan steps.
The total power consumption per scan step, Utree is expressed the sum of theconstant part, U0 and the part proportional to n, U1 1 n, as follows.
tt

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

105

Table 6.1: Power consumption of 1:4 tree structure per scan step
Image
# of pixels Code length U [pJ/bit]

Chapter 6

424

21bit

19.5

424

21bit

19.8

424

13bit

19.1

828

41bit

24.4

828

53bit

24.6

828

29bit

24.2

16216

93bit

32.5

16216

117bit

34.7

16216

61bit

32.5

Design and Evaluation of 1:4 Tree Sensors

106Figure 6.14: Layout of the designed address select controller.

Utree = U0 + U1 n
t

(6.6)

t

Table 6.1 shows the calculated power consumption of 1:4 tree structure per scanstep, using the simulation results of spice for the circuits of 1:4 tree structure
consists of node automata and voltage sources as the value of pixels. The load
capacitance of each node is determined to be proportional to 2 , where l is the levelwith assuming the standard 1.5m CMOS process, and the total number of levels,
N is N = 2 for 4 2 4 pixels, N = 3 for 8 2 8 pixels, and N = 4 for 16 2 16 pixels,
respectively.
l

The two part of power consumption in Equation (6.6) is derived as U0 = 14:4pJ
and U1 = 1:26pJ, respectively. Seen above, it is shown that the power consumption
in 1:4 tree structure is proportional to O(n), while O(n2 ) for CCD raster scan image
sensor, which is expected to be small enough for larger n.
tt

Because of the design mistake in pad assignment suitable for LSI tester, the measurement of the fabricated chip has not been carried out yet.
6.4

Design and Evaluation of 1:4 Tree Sensor using External Address Decoders

6.4.1

Design of the 1:4 tree sensor using external address decoders

The 1:4 tree image sensors using the external address decoders have been designed,by using the circuits of the controller and the address decoders designed in Figure
5.11, which is shown in Figure 6.14.
The two types of pixels are designed; the pixels with the function of taking interframe di erence, as shown in Figure 6.15(a), and the compact pixels without taking
inter-frame di erence, which has only one latch to hold data, as shown in Figure

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

107

(a)

(b)

Figure 6.15: Layouts of the designed pixels for the 1:4 tree sensor using external
address decoders. (a)pixel with taking inter-frame di erence, (b)simple, compact
pixel without taking inter-frame di erence.

D
D

Q

D

Vref

Q

D

Q

D

Vref
CK1

CK2
(a)

CK
(b)

Figure 6.16: Circuits of pixels used for the 1:4 tree sensor using external address decoders. (a)pixel with taking inter-frame di erence, (b)simple, compact pixel without
taking inter-frame di erence.

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

108

6.15(b). The circuit of each pixel is shown in Figure 6.16.

Two chips are designed using CMOS 1.5m technology; 64 2 64 pixels chip withthe function of taking inter-frame di erence using the pixels in Figure 6.15(a), and
128 2 128 pixels chip without the function of taking inter-frame di erence using the
pixels in Figure 6.15(b). Whole layouts of the designed chip are shown in Figure
6.17 and Figure 6.18, respectively.
The chip photographs of both chips are shown in Figure 6.19 and Figure 6.20,
respectively4 .

The chip size of the 64 2 64 chip is 4.8mm24.8mm, and the number of transistors
is 120,045, with 64 2 64 = 4; 096 pixels which have the functions of taking inter-frame
di erences.

The chip size of the 128 2128 chip is 7.2mm27.2mm, and the number of transistors
is 207,661, with 128 2 128 = 16; 384 pixels which have the simple photo-electron
conversion function without taking inter-frame di erences.
6.4.2

Evaluation of the 1:4 tree sensor using external address decoders

The power consumption in the 1:4 tree architecture using external address decoders should be larger than that of the 1:4 tree sensor designed in section 6.3, since
the long pixel select lines across the pixel plain is activated at scan step, while theonly one signal scan path is activated in the 1:4 tree sensor as discussed in section
6.3.2.
The power consumption in the 1:4 tree sensor using external address decoders is
composed of the following parts.

 power consumption of charging and discharging each bit line, B .
i power consumption of charging and discharging each row select line, R .
j power consumption of charging and discharging the word line, W .
4 The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI

Design and Education Center(VDEC), the University of Tokyo with the collaboration by Nippon
Motorola and Dai Nippon Printing Corporation.

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

109

Figure 6.17: Whole layout of the designed 64 2 64 1:4 tree sensor using external
address decoders, with taking inter-frame di erence.

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

110Figure 6.18: Whole layout of the designed 128 2 128 1:4 tree sensor using external
address decoders.

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

111

Figure 6.19: Chip photograph of the designed 64 2 64 1:4 tree sensor using external
address decoders, with taking inter-frame di erence.

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

112

Figure 6.20: Chip photograph of the designed 128 2 128 1:4 tree sensor using external
address decoders, without taking inter-frame di erence.

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

113

1

Pd

0.2
64x64
16x16 32x32
analytical

0.1
simulated(MC)

0.001

0.01

p0

0.1

1

Figure 6.21: Relation of the selection probability of the bit lines or the row selectlines, P , and the probability of the pixels being \1", p0s power consumption if the scan sequence controller, U

FSM.

The probability of each bit line B or row select line R being selected, P is derived
as dividing the frequency of selection through all the scan steps by the number ofscan steps as follows,ijs

X2 0 p
P =
;
0
X
0
1+
4
p
N

N +1

l

l

(6.7)

l=1

s

N

1

N +1

l

l

l=1

where p is the probability of the node at the level l being \1" derived in Equation(3.2) as p = 1 0 (1 0 p0 )4 , where p0 is the probability of the pixel being \1". The
relation of P and p0 is shown in Figure 6.21, with the results of the Monte-Carloswitch level simulation, for the various size of pixel plain, 16 2 16, 32 2 32, and64 2 64. The relative frequency of the bit lines or row select lines being selected islower for the larger p0 , since the number of scan steps increases rapidly.
It is also derived the probability of the bit in 1:4 tree code being \1", P as dividing
the total number of the nodes whose value is \1" by the number of scan steps asfollows.
l

l

l

s

d

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

114

1

Pd

0.2
64x64
16x16 32x32
analytical

0.1
simulated(MC)

0.001

0.01

p0

0.1

1

Figure 6.22: Relation of the probability of the bit in 1:4 tree code being \1" and theprobability of the pixels being \1", p0

Xb 0 pP =X0 b 0 p
1+
N

N

l

l

(6.8)

l=0

d

N

1

N +1

l

l

l=1

The relation of P and p0 is shown in Figure 6.22, with the results of the MonteCarlo switch level simulation, for the various size of pixel plain, 16 2 16, 32 2 32,
and 64 2 64. The probability of the bit in 1:4 tree code being \1" is smaller for thesmaller p0 .
Using these probabilities, the probabilities of charging or discharging signal lines
are derived as follows.
d The bit line B is discharged when it is selected and at least one pixel at the
selected rows is \1", and the probability is expressed as P f1 0 (1 0 p ) g,
i

s

0

nPs

since nP is the expectation of selected rows.
s The bit line B is charged when it is discharged at the previous scan step, andi

it is also selected at the current scan step, and the probability is expresses as
P 1 P f1 0 (1 0 p0 ) g.
s

s

nPs

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

115

500

U[pJ/bit]

400
300

7.6n0.84+11.6

200
100
0

10

100

n[pixel]Figure 6.23: Relation of power consumption per scan step and the number of pixels
at one edge, for various images

 The row select line R is charged and discharged by the probability of selection,j

P at the every scan step.
s The word line W is discharged when the bit of 1:4 tree code is \1", and theprobability is expressed as P .
d The word line W is charged at the pre-charge cycle if it is discharged at theprevious scan step, and the probability is expressed as P .
dThe load capacitance of the bit lines and the row select lines and the word line areproportional to their lengthes, and they are proportional to the number of pixels at
one edge, n. Thus the expectation of power consumption at each scan step, P isexpressed as the sum of each power consumption as follows.

P (1 + P )f1 0 (1 0 p0 )nP g
nC 0 V 22+nP 2 nC 0 V 2 + P 2 nC 0 V 2 + UFSM

P =n2

s

s

s

B

s

R

dd

d

W

dd

dd

(6.9)

The power consumption for some sample images is calculated by spice simulation,
since the active probability of pixels have spatial correlation in these cases, which
can not be derived by the Equation (6.9), that is derived by assuming no correlation
among pixels. The load capacitance of bit lines, row select lines, and word line isassumed to be proportional to the number of pixels at one edge using the standard

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

116

Table 6.2: Power consumption of 1:4 tree structure using external address decoders
per scan step# of Code
Image
pixels length U [pJ/bit]

Chapter 6

424

21bit

38.5

424

21bit

40.5

424

13bit

43.0

828

41bit

55.1

828

53bit

57.5

828

29bit

62.6

16216

93bit

89.5

16216 117bit

95.5

16216

61bit

101.1

32232 317bit

150.3

Design and Evaluation of 1:4 Tree Sensors

117

Figure 6.24: Photograph of the developed prototype system for 1:4 tree code decoder.
1.5m CMOS process. The simulation results are shown in Table 6.2. The relationof power consumption per scan step and the number of pixels at one edge is shownin Figure 6.23, with the curve- tting results using least mean square (LMS) method.
It is expected to be proportional to O(n0 84 ), which is expected to be small enoughthan that of CCD image sensors for the larger n.
Because of the design mistake in pad assignment suitable for LSI tester, the measurement of the fabricated chip has not been carried out yet.
:

6.5

Design and Evaluation of Tree-Code Decoder

6.5.1

Prototype implementation of tree-code decoder

We have developed the prototype system of the 1:4 tree code decoder using FPGAs(Field Programmable Gate Array). We have employed the FPGA of XC4025,
which is used in section 6.2.1, and one for memory cell arrays, and the other for
address decoders and controllers. The number of memory cells is 32 2 32 = 1; 024,
and the decoded image is serially read out.

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

118

(a)

(b)

(d)

(e)

(c)

Figure 6.25: Original image(a) and the images under decode(b), (c), (d), and thecompletely decoded image(e).
The photograph of the prototype 1:4 tree code decoder is shown in Figure 6.24.
The 1:4 tree code to be decoded is given by PC, with the system clocks, and it
is decoded to binary image by the developed prototype system. The binary image
is again transferred to PC serially. The image under decode procedure can be also
read out serially, since each memory cell is set its value according to the decoding
step, which is more detail at the decode step for lower levels. Figure 6.25 shows theoriginal image and the images under decode, and the completely decoded image.
The operation frequency of the developed prototype system is up to 1MHz, whichis restricted by the speed of PC.
6.5.2

Design of full-custom tree-code decoder

The decoder of 1:4 tree code has been designed, by using the circuits of thecontroller and the address decoders, which are identical to those used in the 1:4

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

119

/V

V

CKL
r

Di

r

/S

S

D

Q

Do

CKS

Figure 6.26: Circuit of memory cell for the 1:4 tree code decoder
tree sensor using external address decoder, used in section 6.4. The circuit of thememory cell is shown in Figure 6.26. The memory cell has coupled inverters tostore the value of raster image, and one D- ip- op for the shift register in orderto shift out outside the decoded image. The decoded image is given by V and its
complementary as /V, and they are stored to the coupled inverters using clock CKL,
if the row of this pixel is selected by r. The selection of columns is done by thesignal generation circuit placed at each column, as shown in Figure 5.14. The stored
image is transferred to D- ip- op at the positive edge of CKS by keeping S as low
and /S as high. The transferred image is shifted out outside by the clock of CKS
with keeping S as high and /S as low. Data input Di is connected to the data outputof the previous stage in shift register, and data output Do is connected to the data
input of the next stage in shift register, respectively. Data output Do of the nal
state in shift register is the serial output of the decoded image.
The layout of the memory cell used in this decoder is shown in Figure 6.27, which
is implemented by the circuit described in section 5.3.

The whole layout of the designed 64 2 64 decoder of 1:4 tree code is shown in
Figure 6.28, which has the functions of read out the rasterized image serially, andcan be cascaded for the decoding of the larger raster images, as shown in Figure

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

120

Figure 6.27: Layout of the memory cell for the decoder of 1:4 tree code.
6.29. In this case, one decoder chip is used as master, and the address select signals
are send to the other slave chips. The other tree decoder chips are used as slave,
where only the address decoders are used to select memory cells. One level of thecontroller in one of the slave decode chips is also used to generate the address selectsignals for the extended number of levels. The serial inputs and serial outputs ofthe decoded images in each chip is connected in order, so as to form a large shift
register.
The chip photograph of the designed decoder of 1:4 tree code is shown in Figure
6.305 . The number of transistors is 110,024.
There was a fatal design mistake in the fabricated chip, one connection in serial
shift registers is lost, and the measure and evaluation of this chip has not been done
yet.
6.6

Summary and Conclusion

In this chapter, the designed chips of the 1:4 tree sensors and the decoder of 1:4
tree code and their prototype systems using FPGAs, are described. It is shown
5 The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI

Design and Education Center(VDEC), the University of Tokyo with the collaboration by Nippon
Motorola and Dai Nippon Printing Corporation.

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

121Figure 6.28: Whole layout of the designed 64 2 64 decoder of 1:4 tree code.

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

122

"Slave" decoder chip

M

M

em

o
Pl r y Cai en llController

Row/Column
Address Decodersem

Row/Column
Address Decoders

Controller

Row/Column
Address DecodersoPl r y Cai en llController

Row/Column
Address Decoders

Controller"Master" decoder chip

Row/Column Address Select Signals"Slave" decoder chipo
Pl r y C
ai e
n ll

em
M

o
Pl r y C
ai e
n ll

em
M

"Slave" decoder chip

Serial Decode Images
Serial Output
of Decoded Image

Figure 6.29: Extend connection of designed decoder chips for the larger image

Figure 6.30: Chip photograph of the designed 64 2 64 decoder of 1:4 tree code.

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

123that the 1:4 tree sensor using the external address decoder can integrate about 16
times pixels in the same size of chip, compared with that using tree structure ofautomata. It is also shown that the decoder of 1:4 tree code can be implemented
by using the external address decoder designed for the 1:4 tree sensor with external
address decoders.
The evaluations of them, mainly in terms of the power estimation are also described.

Chapter 6

Design and Evaluation of 1:4 Tree Sensors

124