Chapter 2Power Reduction Methodologies
for Image Sensors and CMOS
Circuits
In this chapter, the problems of power consumption in image sensors and CMOS
circuits will be discussed. In section 2.1, the models of power consumption in conventional image sensors will be described. In the following section 2.2 and section
2.3, the probabilistic models of power consumption in CMOS combinational logics
and sequential circuits will be described. It will be also discussed the power reduction methodologies for CMOS combinational logics and sequential circuits withmaintaining the performance in these sections.
2.1

Power Consumption Modeling of Image Sensors

Figure 2.1 describes the typical architecture of CCD transfer image sensors. Image
signals are converted to charge in each photo detector, shown as squares in Figure
2.1, and the charge is carried to the vertical transfer CCDs and horizontal transfer
CCDs outside to the image sensor.
The clock signals provided to each CCD are usually multi-phase clock signals,
and their swings are often very large compared with the CMOS logic circuits. For

Chapter 2 Power Reduction Methodologies for Image Sensors and CMOS Circuits

11

Figure 2.1: The simpli ed model of CCD transfer image sensors. (The square
presents the photo detector, and the circle presents the transfer CCD.)(®
(¯

4um x 4um
200nm

(a)

(b)

Figure 2.2: Model structure of CCD transfer gate. (a)a part of transfer line,(b)example size of unit CCD transfer gate.

Chapter 2 Power Reduction Methodologies for Image Sensors and CMOS Circuits

12Figure 2.3: Example of multi-phase clocks for CCD devices (From [15])example, the voltage swing of 07V to 0V is provided for vertical transfer CCDs,
and 0V to +5V for horizontal transfer CCDs. Such a high clock voltage is needed
because of the large size of devices, which is not easy to be scaled down to keep the
charge transfer eciency. (On the other hand, the size of MOSFETs in conventional
CMOS logics can be reduced by the advanced fabrication technology, and it resultsin both power and delay reduction[14].)
The multi-voltage and multi-phase clock signals, for example as shown in Figure
2.3, should make the control circuits more complex.
It is notable that the clock signals are always provided to all transfer CCDs, andthe number of transfer CCDs is quite large, it is almost same to the number ofpixels, for example about 350,000 for VGA resolution image sensors.
Figure 2.4 shows the model structure of CCD transfer gates in image sensors.
Assuming that the vertical and the horizontal number of pixels are both equal ton, the number of vertical and horizontal transfer CCD, n and n , respectively, areequal to n = n2 and n = n, respectively. In case of scanning pixels, the transfer
clocks for vertical CCDs are provided n times, while the transfer clocks for horizontal
CCD are provided n2 times. The total number of clocks provided for vertical andhorizontal CCDs are equal to 2n3 , and the power consumption in transfer CCDs
is expected to be proportional to O(n3 ), which will be one of the most important
problems in mega-pixel CCD image sensors.
v

v

h

h

Chapter 2 Power Reduction Methodologies for Image Sensors and CMOS Circuits

13

n

(ó
Horizontal CCDs

(ånVertical CCDs

Figure 2.4: Model of CCD image sensor
Discussed in above, the reasons of increasing power consumption of CCD image
sensors are follows.

 Clock signals are always provided to the all transfer CCDs. The number oftransfer CCDs is almost same to the number of pixels.

 Voltage of clock signals can not be reduced because of the large size of devices.
It is dicult to reduce the size of devices to keep the transfer eciency.
The another type image sensor is based on memory-like architecture as shown in
Figure 2.5. The non-CCD image sensor of this architecture has the advantages asfollows.

 Just the address lines to the pixels being scanned are activated, and the mostof address lines are not activated.

 The row and column decoders are combinational logics, and it can be \scaled
down" in order to reduce power consumption. The driving voltage for eachpixel can be kept to be equal to the supply voltage of decoder logics, which islower than that of CCD image sensors.

Chapter 2 Power Reduction Methodologies for Image Sensors and CMOS Circuits

14

Row Decoder

Column Decoder

Figure 2.5: Model of non-CCD image sensor. (The squares represents the photodetectors, and the horizontal and vertical lines acrossing the photo detectors are
address lines.)
In spite of the switching noise problem, the non-CCD image sensors (they are often
called as \CMOS sensors") are expect to be a low power image sensor comparedwith CCD image sensors.
2.2

Models of Power Consumption in CMOS Combinational Logics and Its Reduction

In non-CCD type image sensors seen in previous section, the conventional logic
elements, such as combinational logic gates and sequential circuits including ip- ops
are used in non-CCD image sensors for signal scanning circuits. In this section, thepower consumption modeling of CMOS combinational logics are described. It is also
discussed the power reduction methodologies for combinational logics with keeping
circuit function and circuit performance at the design step after logic synthesis.
2.2.1

Probabilistic power model of CMOS combinational logics

Here we assume that the input signals for combinational logic have the following
characteristics.

Chapter 2 Power Reduction Methodologies for Image Sensors and CMOS Circuits

15

α

1−α

1

1−β

0

β

Figure 2.6: De nition of probabilistic parameters, ( ; ).

 Input signals change synchronously with the system clock.
 Input signals change probabilistically concerning with the value in the previous
cycle. (Markov chain) Input signals change independently.
Letting and to be conditional probabilities of \0" to \1" and \1" to \0", respectively as shown in Figure 2.6, the probabilities from \0" to \0" and \1" to \1"
are equal to (1 0 ) and (1 0 ), respectively. Here we call the pair of ( ; ) as theprobabilistic parameters of input signal. Assuming the stable state of input signals,
the probability of input signal being \0", P0 is derived from the following equation.

P0 = P0(1 0 ) + (1 0 P0)(2.1)

From the Equation (2.1), the P0 and the probability of input being \1", P1 arederived as follows.

P0 =
P1 =

(2.2)

+

(2.3)

+

The load capacitances of logic circuits are charged or discharged along to the
input signals, which are the most part of the power consumption of CMOS logics.
For example, 2 input NAND gate can be simpli ed as shown in Figure 2.7. It has
two load capacitances, the load capacitance C and the internal node capacitanceC . Assuming that the probabilistic parameters of input x and y are ( ; ) and( ; ), respectively, the stable probabilities for all combinations of input signals
L

i

x

y

x

y

Chapter 2 Power Reduction Methodologies for Image Sensors and CMOS Circuits

16

x
z

y

(a)

x
x
y

y

z

x

Ci CL

y

(b)

Ci CL

(c)

Figure 2.7: Models of 2 input NAND gate. (a)gate model, (b)transistor model,(c)switch model.

00

10

01

11

Figure 2.8: Transition diagram of two inputs.
are derived as follows.

P00 =

x

x

P10 =

+

x

x

x

P01 =

+

x

x

x

P11 =

+

x

x

x

+

x

1
1
1
1

(2.4)

y

y

+

y

(2.5)

y

y

+

y

(2.6)

y

y

+

y

(2.7)

y

y

+

y

Here P means the probability of x = X and y = Y .
Using these probabilities, the all transition probabilities between two combinationsof inputs, as shown in Figure 2.8 can be derived. For example, the probability oftransition from (x; y ) = (0; 1) to (x; y) = (1; 1) is equal to the product of P01 and
XY

Chapter 2 Power Reduction Methodologies for Image Sensors and CMOS Circuits

17the conditional probability of x = 0 to x = 1,
follows.

P01!11 = P01 (1 0 ) =
x

x

y

x

+

y

x

y

+

and y = 1 to y = 1, 1 0

x

x
y

(1 0

y

y

, as

)

It also can be derived the probabilistic parameters of output z , ( ; ) along to
the transition diagram of output node z , as follows.
z= 1 0 (1 0zx

= fP00 (1 0

z

)(1 0

x

y

y

z

)

(2.8)

) + P10 (1 0

y

+

x

y

) + P01 (1 0

x

+

x

y

)g

= (P00 + P01 + P10 )(2.9)

In the switch level model shown in Figure 2.7, both load capacitances have twostates; charged state (\1") and discharged state (\0"). The states of load capacitances C and C change between \1" and \0", and it is easy to be describe theprobabilistic parameters of charging/discharging each load capacitance, ( L ; L )and ( i ; i ) as follows.
L

i

C

C

C

C

C

C

L =
L =

C

C

i =

z

(2.10)

z(2.11)

P (

i =1

(0)
00

0

x

0

) + P01+ P11 (
(0)
P00 + P01 + P11

x

y

x

y

y

y

0

x

y

)

(2.12)(2.13)

Here P00(0) is the probability of inputs are both \0", with the discharged state of C ,which is oating in this case, as follows.
P (1 0 ) + P11
P00(0) = 01
(2.14)+ 0
The probabilistic parameters of load capacitances give the probabilities of charging
load capacitances, N L and N i , respectively, as the product of the probability ofstate \0" and the transition from \0" to \1", as follows.
i

x

x

y

C

N L=

C

C

N i=

C

L+
C

C

C

L
i

i+

C

C

y

L

i
C

x

y

y

C

L
C

x

i

(2.15)(2.16)

Chapter 2 Power Reduction Methodologies for Image Sensors and CMOS Circuits

18

120

Pmodel [µW]

100

3.5

Pmodel[µW]

3.0
2.5

80

60

2.0
40

1.5
1.0
20

0.5
0.0
0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

20

40

60

80

100

120

Psim [µW]

Psim [µW]

(a)

(b)

Figure 2.9: Calculated power by probabilistic model, P model and spice simulation,
Psim . (a)2-input NAND gate and (b)1-bit full adder
Using these probabilities, the expectation of power consumption per one system
clock cycle, P is described as follows.

P = f fN L C V 2 + N i C V (V
C

L

dd

C

i

dd

dd

0 V )g(2.17)T

Here f is the system clock frequency, V is the supply voltage, and V is thethreshold voltage of n-channel MOSFETs.
This probabilistic model of power consumption can be extended for a large logic
circuits containing many logic gates by assuming that the probabilistic parametersof a input signal are equal to those of the output signals connected to it.
The accuracy of this probabilistic model is checked by spice simulation, as shownin Figure 2.9. Psim and Pmodel represent the power consumption calculated fromspice simulation results[16], and from the probabilistic model by Equation (2.17),
respectively. Simulations for both 2-input NAND gate and 1-bit full adder, containing 9 NAND gates shown in Figure 2.10, are shown in Figure 2.9(a) and 2.9(b),respectively. Figure 2.9(b) indicate a small di erence between the power calculated
by spice simulation and that of the probabilistic model in case of 1-bit full adder.
The reason is that signals of each gate in the circuits are not always independent
each other.
dd

T

Chapter 2 Power Reduction Methodologies for Image Sensors and CMOS Circuits

19

x0
s1

y0

c0

c1

Figure 2.10: Circuit of 1-bit full adder
2.2.2

Power reduction methodologies for CMOS combinational logics

Figure 2.7 gives the hints of reducing power consumption without changing logic
function of 2-input NAND gate. The inputs x and y are symmetric logically, though
they are asymmetric topologically. The charge and discharge for load capacitance
C will happen depending on the state of output signal, but charge and discharge
for internal capacitance will depend on the state of C , since C will be opened whenx = y = 0 and keeps the previous state. This situation will depend on whether
input signals S and S are connected to the input terminals x and y, respectively,or connected to the input terminals y and x, respectively, though these two cases
give the identical logic function of 2-input NAND gate.
We can choice the optimal input assignment by comparing the expectation of
power calculated from the probabilistic model.
For example, we carried out the simulation for the 1-bit full adder shown in Figure
2.10, which has 9 2-input NAND gates and tree inputs; x0 , y0 and c0 . There are
29 = 512 possible input signal assignments for all NAND gates, and the maximum
power consumption, Umax and the minimum power consumption, Umin in all possible
assignments are shown in Figure 2.11. Here we assume that C =40fF, C =20fF,
0 =0 = 0:1,0 =0 = p 0 and
0 =0 = p 0 . The result shows that
there are the ratio of Umax =Umin of 1.74 in maximum and 1.10 in minimum, and this
implies that the power consumption of 1-bit full adder can be reduced about 40%
in maximum by the optimum input assignment, without the modi cation of logic
function.
L

i

x

i

y

L

x

x

y

y

y

c

c

i

c

Chapter 2 Power Reduction Methodologies for Image Sensors and CMOS Circuits

20

Umax

U[pJ]

4.0

3.5

Umin

3.0

2.5

2.0
0.8
0.7
0.6
0.2

0.5
0.3

0.4

pyo

0.4
0.5

0.3
0.6

0.7

pco

0.2
0.8

Figure 2.11: Maximum and minimum of power consumption of 1-bit full adder forvarious probabilistic parameters of input y0 and c0 .

Chapter 2 Power Reduction Methodologies for Image Sensors and CMOS Circuits

21

Primary
inputsCurrent
State Code

Combinational
Logic

Flip-Flops

Outputs

Next
State Code
System Clock

Figure 2.12: Architecture of nite state machine (FSM).
2.3

Models of Power Consumption in CMOS Sequential
Circuits and Its Reduction

In this section, the power consumption modeling of CMOS sequential circuits aredescribed. It is also discussed the power reduction methodologies for sequential
circuits by the state code assignments for each state.
2.3.1

Probabilistic power model of CMOS sequential circuits

Here we consider the sequential circuit as the nite state machine (FSM), as
shown in Figure 2.12. The most part of CMOS circuits' power consumption is the
dynamic power consumption, caused by charging and discharging load capacitance,
as discussed in the previous section. The dynamic power consumption of sequential
circuits consists of two parts; the power consumption of ip- ops, PFF and that of
combinational logics, Plogic . The power consumption of ip- ops is composed of twoparts; the power consumption by charging and discharging the load capacitance of
ip- ops based on the state transition, PFF(load) and that by charging and discharging
system clock lines, PFF(clock).

PFF(load) depends on the number of ip- ops whose outputs have changed, while
PFF(clock) is almost constant for every clock cycle, whether the all or no ip- ops
have made transition.
This fact implies that there is a possibility of reducing power consumption byload capacitance, PFF(load) , since the way to assign of the binary state code for each

Chapter 2 Power Reduction Methodologies for Image Sensors and CMOS Circuits

22Current
State

Next
State

001

101
Transition w/o output change

FF0 : 1FF1 : 0FF2 : 01
0
1

Transition w/ output change
Figure 2.13: Charging and discharging load capacitance at every state transition.
state in the transition diagram is not unique; it is often determined to minimize thecomplexity of combinational logics.
Assuming that the conditional probabilities of the transition from state i to statei, p are known, the probabilities of occupying state i at each cycle, q should satisfy
the following equation.
i

i;j

q =
i

Xp 1q
N

i;j

(2.18)jj =1

Here N is the number of states in the transition diagram. Using the matrix P ,whose (i; j ) element is p and the vector q , whose i element is q , the Equation(2.18) can be described as follows.
ii;jq = PqP(2.19)The solution of Equation (2.19) under the condition of q = 1 gives the state
probability of each state, q . The product of q and p , p = p 1 q gives thetransition probability at each clock cycle.
It is notable that the number of ip- ops whose output have changed at clock
cycle is equal to the Hamming distance, d between two state. The expectation of
the number of ip- ops whose output have changed at clock cycle should be equal
to the mean Hamming distance, d, as is described as follows.
i

j

i;j

i

i;j

i;j

i

i;j

Chapter 2 Power Reduction Methodologies for Image Sensors and CMOS Circuits

23

XXp 1d
d=
N

N

i;j

(2.20)i;j

i=1 j =1

This d is expected to be as an index of the power consumption in ip- ops.
2.3.2

Power reduction methodologies for CMOS sequential circuits

The simple methodology of reducing PFF in the sequential circuits is to nd thebinary state code assignment for each state which minimizes the mean Hamming
distance, d. There are N ! possible assignments of state codes for all N states, and it
is undesirable to try the all possible assignments to nd the assignment minimizing
d for N states in practical design.
The alternative way to nd the optimal state code assignment is the following
heuristic algorithm.
1. calculate transition probabilities, p and add p and p , as p~ .
i;j

i;j

j;i

i;j

2. sort p~ in order.
i;j

3. assign \0"(decimal) and \1"(decimal) for state i and j whose p~ is the largest.
i;j

4. assign to the state i whose state code has not assigned yet, as one of theavailable state codes whose Hamming distance from state j is minimum, inorder of p~ .
i;jThe simulation results shows that this heuristic algorithm can give the optimal
assignment, with the error of about 4% against the optimum assignment by theexhaustive method, with the calculation time proportional to about O(N 3 ) against
about O(N !) of the exhaustive method.
The simulation results of power consumption and the number of gates in combinational logics by this heuristic assignment compared with both the random assignment and the assignment aiming to minimize the complexity of the combinational
logic[17] are shown in Table 2.1. The results shows about 010% power reduction
against the conventional assignment for minimize logic complexity, and the number

Chapter 2 Power Reduction Methodologies for Image Sensors and CMOS Circuits

24compared withrandom assignment logic minimize assignment
Power in
ip- ops

040%

030%

Power incombinational logic|

Total Power

|

011%
010%

# of gates

|

+11%

Table 2.1: The comparison of power in each part and the number of gates by theassignment for minimum d.
of gates in combinational logic increase about 10%, but the total increase of hardware costs will be smaller than this case, since the number of ip- ops is equal ineach assignments.
2.4

Summary and Conclusion

In this chapter we discussed the power consumption in image sensors, both CCD
sensors and \CMOS" sensors. This chapter also has described the probabilistic
model of power consumption of both the combinational logics and the sequential
circuits. It is shown that these models are adequate to analytically express the
expectation of power consumption. It is also proposed the methodologies to reduce
power consumption of both the combinational logics and the sequential circuits
without modifying the designed functions. The eciency of power reduction in the
combinational logics is up to about 030% against the conventional random input
signal assignment. The eciency of power reduction in the sequential circuits is
up to about 010% against the conventional assignment aiming to minimize thecomplexity of combinational logics.

Chapter 2 Power Reduction Methodologies for Image Sensors and CMOS Circuits

25