Wide-Load-Range Efficiency Improvement for
High-Frequency SiC-Based Boost Converterwith Hybrid Discontinuous Current Mode
Hoai Nam Le, Student Member, IEEE, Jun-Ichi Itoh, Senior Member, IEEE

Abstract--This paper proposes a hybrid current mode between triangular current mode (TCM) and discontinuous current mode
(DCM) in order to improve a wide-load-range efficiency for a high-frequency SiC-based boost converter. At rated load, TCM where
the zero-voltage switching (ZVS) is achieved, is used in order to increase the switching frequency and minimize the boost converter. At
light load, the hybrid current mode (HDCM) where the TCM current is flown during the zero-current interval of DCM, is applied inorder to achieve both ZVS and a reduction of a current ripple. This maintains a high efficiency over a wide load range. A 1-kW
prototype is realized to compare HDCM over continuous current mode (CCM), DCM and TCM. Compared to TCM, the root-meansquare current is reduced up to 56.6% with HDCM. Consequently, the efficiency of HDCM at light load of 0.1 p.u. is improved by
3.1%. Compared to DCM, the average-current ripple in HDCM is reduced by 82.3%, whereas the efficiency of HDCM at light load of
0.1 p.u. is improved by 1.5%. Finally, when the current ripple of CCM is designed to be half of TCM, the efficiency of HDCM at rated
load is improved by 0.9% compared to CCM.
Index Terms--DC-DC power converters, Discontinuous current mode, Triangular current mode, Zero-voltage switching.

I. INTRODUCTIONO

VER the past decades, the increase of the power density has been one of the most important design criteria in powerelectronics due to limited space requirements or weight reductions [1]-[3]. A typical boost DC-DC converter is widely
applied in many power conversion systems, e.g. power conditioning system in photovoltaic systems. Magnetic component, i.e. aboost inductor in the boost converter, accounts for the major volume of the converter [4]. By increasing the switching frequency,
the volume of the boost inductor can be reduced. However, higher switching frequency leads to an increase of switching loss,
which requires larger cooling system. Therefore, a reduction of the switching loss is crucial to high power density design.
In recent years, SiC devices have emerged as promising devices for high efficiency and high density power conversion. The
switching frequency of SiC devices has been push up to several hundreds of kHz in order to reduce the size of the magnetic
component. The following important switching characteristic occurs in the SiC devices; turn-on switching loss is dominant due
to reverse recovery charge or junction capacitor charge of free-wheeling device at hard-switching condition. Soft switching
techniques can greatly reduce the turn-on switching loss, in which resonance between a inductor and a capacitor is utilized inorder to achieve zero-voltage switching (ZVS) [5]-[7]. However, in order to satisfy conditions for ZVS, these methods suffer
many drawbacks such as, e.g. a requirement of additional components, or a restriction of controllable duty ratio. The additional
components not only restricts the minimization of the converter but also complicates the control method, whereas the limitationof the duty ratio restricts the applicable range of ZVS. Therefore, the achievement of ZVS without additional components or thelimited controllable duty ratio is desired.
On the other hand, triangular current mode (TCM) operation is the most simple and effective way to achieve ZVS, and isrecently introduced in the “Little Box Challenge”, i.e. a worldwide competition in order to push the forefront of power density intoday’s converter systems further [8]-[11]. In TCM, turn-off switching loss can be decreased greatly by connecting a snubber
capacitor in parallel with the switching devices, whereas the turn-on switching loss is eliminated by ZVS. Consequently, theswitching frequency can be pushed to hundreds of kHz or several MHz. One of the main drawbacks in TCM applied with pulsewidth modulation (PWM) is that the high current ripple is constant over entire load range. Consequently, it is difficult to achieve
high efficiency at light load when the load current is relatively low. Therefore, it is desired to reduce the current ripple at lightload in order to avoid a sharp decrease in the efficiency [8].

Gate Signal

FWD2

L
A
Vin

Cds2
C

Load

FWD1

Vout

Cds1

iL

EFET1_off

ZVSFET2

EFET1_discharge+Erecovery

This paper proposes a novel concept of a hybrid current
mode between TCM and discontinuous current mode (DCM),
which is entitled hybrid discontinuous current mode (HDCM).
The proposed current mode can achieve a high efficiency over awide load range for a high-frequency SiC-based boost
converter. In HDCM, TCM is applied during zero-current
interval of DCM in order to satisfy the conditions for ZVS.
Consequently, the switching frequency can be increased by
HDCM in order to minimize the converter. Meanwhile, thecurrent ripple is also reduced at light load, which results in the
wide-load-range high efficiency. The remainder of this paper isorganized as follows; in section II, HDCM is proposed in orderto solve the problems of the conventional current modes, thenin section III the design and the control of the boost converter
operated in HDCM are explained. After that, experimental
HDCM operations are presented in section IV. In addition, acomparison of the efficiencies among four current modes, i.e.
TCM, DCM, continuous current mode (CCM) and HDCM,
over a wide load range is carried out. Finally, the advantages of
HDCM over other current modes are clarified based on theseresults.

vCds vCds2

Transition time

vCds1

t

0
Interval:1

2

3

4

1

(a) Switching losses in CCM. In CCM, the free-wheeling diode suffers fromthe significant reverse recovery loss.
Gate Signal
FET1ON

Tsw

Dead timeFET2ONFET1ONt0iL

EFET1_off
ZVSFET2

ZCSFET2

EFET1_discharge
t

0
Vout

vCds vCds2

Transition time

vCds1

t

0
Interval:1

2

3

4

1

(b) Switching losses in DCM. The reverse recovery issues can be alleviatedby DCM. Nevertheless, in DCM, two kinds of switching loss still occur; thehigh turn-off loss because the switching devices is turned off at least twice of
the average current, and the turn-on loss due to the junction capacitor charge.
Gate Signal
Dead timeFET1ONTsw
FET2ON

Dead timeFET1ONt

0

II. HYBRID CURRENT MODE BETWEEN DISCONTINUOUS
CURRENT MODE AND TRIANGLE CURRENT MODEt

ZVSFET2

0
Vout

Fig. 1. Typical non-isolated boost DC-DC converter. The switching loss
reduction is crucial to the high frequency design. In general, there are threecurrent modes to operate the converter: CCM, DCM and TCM.

FET1ON
t

0

FET1
SW1

Dead timeFET2ONFET1ON

SW2

iL

Tsw

Dead time

FET2

iL

EFET1_off

ZVSFET2

EFET2_offtThis section presents the basic principle of the switching0
loss occurrence in the boost converter and points out thedifference between the hard switching and the proposed hybrid
ZVSFET1
current mode which allows for ZVS during the complete Vout vCds vCds2
Transition timeswitching period.
vCds1
Figure 1 depicts a typical non-isolated boost converter,t0
where the junction capacitor of the semiconductor devices are
Interval:1
2
3
4
1
shown as Cds1 and Cds2. In order to minimize the magnetic
component, i.e. the boost inductor L, the switching frequency is (c) Switching losses in TCM.
required to be pushed to hundreds of kHz or even several MHz. Fig. 2. Switching losses in CCM, DCM and TCM. In TCM, the turn-off loss
can be reduced simply by connecting a snubber capacitor in parallel with theHence, the switching loss reduction is crucial to the high power switching devices, whereas the turn-on loss is eliminated by using the boost
density design. There are three conventional current modes to inductor to resonate out the junction capacitor charge before the turn-on, i.e.
operate the boost converter: CCM, DCM and TCM. Note that ZVS. However, the high current ripple is constant over entire load range withthe application of PWM, which decreases the efficiency at light load.
critical current mode (CRM) can be analyzed as same as DCM
without the occurrence of the zero-current interval.
Figure 2 depicts the pattern of the switching losses in each current mode. The switching period in CCM as depicted in Fig.
2(a) is split into two main intervals and two short resonant transitions.
Interval 1 (CCM): During interval 1, the switch SW1 is closed, the input voltage Vin is applied to the inductor L, and theinductor current iL increases linearly. At the end of the interval 1, SW 1 is turned off. Consequently, the turn-off loss occurs on
SW1.
Interval 2 (CCM): During interval 2, a switching transition takes place where the junction capacitor Cds1 is charged and Cds2

Gate Signal
is discharged. When Cds1 is fully charged to the output voltage
Tsw
Vout, the free-wheeling diode FWD2 starts to conduct theDead time
FETON
FET2ON1
inductor current iL. At the end of the interval 2, SW 2 is turned
FET1ONFET1ONFET2ONon at the forward voltage of FWD2, which is considered ast
0
ZVS.
iL EFET1_off
Interval 3 (CCM): During interval 3, the voltage applied to L
DCM
ZVSFET1
is negative and iL decreases linearly. At the end of the interval
TCM
2, SW2 is turned off and the inductor current commutates fromZVSFET2
t
0
FET2 to FWD2. This current commutation clamps the voltage ofSW2 to the forward voltage of FWD2. As a result, the turn-off
Interval:1234
1of SW2 is considered as ZVS.
Interval 4 (CCM): During interval 4, iL continues to Fig. 3. Hybrid discontinuous current mode between DCM and TCM. By
applying TCM during the zero-current interval of DCM, the condition for
decrease. As soon as the dead time has passed, SW 1 is turned ZVS is achieved, whereas the current ripple can still be reduced at light load.
on. The inductor current iL commutates from FWD2 to FET1
which leads to the forceful turn-off of FWD2. This results in thehigh reverse recovery current and the high reverse recovery loss [12]. Note that FET 1 is turned on when Cds1 is fully charged at
the output voltage Vout. Consequently, additional loss coming from the discharge of Cds1 occurs.
On the other hand, the switching period in DCM as depicted in Fig. 2(b) is split into two main intervals and two resonanttransitions.
Interval 1 and Interval 2 (DCM): these intervals are similar to the intervals in CCM.
Interval 3 (DCM): At the end of interval 3, iL reaches zero and SW2 is turned off. Therefore, zero-current switching (ZCS) is
achieved.
Interval 4 (DCM): During interval 4, L, Cds1, and Cds2 form a resonant circuit which starts to oscillate. The behavior of theoscillation depends on the input to output voltage ratio Vin/Vout [9]. Due to this oscillation, at the moment when SW1 is turned onat the end of interval 4, the voltage of Cds1 varies from 0V to Vout depending on the circuit condition. On the other words, SW 1
can still be turned on under the condition that Cds1 is charged and the loss coming from the discharge of Cds1 still occurs. Hence,
the hard switching still occurs in DCM.
In order to allow for ZVS over entire period, TCM has been proposed [8]-[11]. The switching period in TCM as depicted inFig. 2(c) is split into two main intervals and two resonant transitions.
Interval 1 and Interval 2 (TCM): these intervals are similar to the intervals in CCM.
Interval 3 (TCM): Different from DCM, instead of turning off SW 2 when iL reaches zero, SW2 is still kept on in order to let iL
become negative. At the end of interval 3, SW2 is finally turned off. Consequently, the turn-off loss occurs on SW2.
Interval 4 (TCM): During interval 4, a switching transition takes place in which Cds2 is charged and Cds1 is discharged. WhenCds2 is fully charged, FWD1 starts to conduct iL. At the end of the interval 4, SW1 is turned on at the forward voltage of FWD1,
which is considered as ZVS. Note that TCM is basically similar to CCM but the current ripple in TCM is intentionally designed
high enough to let the current become negative in one switching period (cf., Section III) [11].
To conclude, the principle of the ZVS achievement in TCM is to flow a current through the free-wheeling diode before theturn-on of the switches in order to discharge the junction capacitor. Besides, it should be noted that the turn-off loss can be
reduced simply by connecting a snubber capacitor in parallel with the switches. A drawback of TCM, however, is a large current
ripple which decreases notably the efficiency at light load [8]. Therefore, the current ripple reduction of TCM at light load isdesired. In order to reduce the current ripple, one of the conventional methods is to increase the switching frequency at light
load, i.e. the Pulse Frequency Modulation (PFM) [9]-[10]. However, PFM is undesirable in many power electronic systems
because it is difficult to design a filter circuit for the operation across a wide range of frequencies [13]-[14]. On the other hand,in DCM, because the current ripple becomes smaller at light load, the high efficiency can be maintained [15]. As mentioned
above, because DCM still suffers the high turn-on loss, the method to achieve ZVS in DCM is desired. Therefore, this paper
proposes the novel concept where TCM and DCM are combined in order to utilize the advantages of these current modes, i.e.
ZVS in TCM and the current ripple reduction at light load in DCM.
Figure 3 illustrates the concept of the hybrid discontinuous current mode (HDCM) between DCM and TCM. During the zerocurrent interval in DCM, i.e. the interval 4 as depicted in Fig. 2(b), instead of letting the current return to zero, the switches are
modulated in order to flow the TCM current. Consequently, the condition in order to achieve ZVS in DCM can be satisfied by
the TCM current during the interval 4 as shown in Fig. 3. Note that the switching losses during the TCM interval are negligibly
small as explained above. Furthermore, because the total charge during the TCM interval can be controlled to become negligibly
small, the TCM interval has no effects on the average current which is generated by the DCM interval. On the other words, thecurrent ripple at light load can still be reduced by the DCM operation. As a result, both ZVS and the current ripple reduction atlight load are achieved without additional components or the limitation of the duty ratio.

III. BASIC OPERATION OF HYBRID DISCONTINUOUS CURRENT
MODE

Gate Signal
Tsw
FET2ONFET1ONt0

Vout

FET1ON

Tdead
vCds
vCds2

Tdead

Transition time

Transition time

vCds1

t

0
D1Tsw

D2Tsw

D0Tsw

Based on the mechanism of the switching loss occurrence
discussed in Section II, the design and control of the boost
converter for HDCM is described in this section. The derivationof the ZVS condition has to be carried out for two cases:
Vin>Vout/2 and Vin<Vout/2. However, for the sake of brevity, only
the case of Vin>Vout/2 is discussed in the following, whereas thecase of Vin<Vout/2 is derived analogously [9].

A. Converter design
Figure 4 depicts the HDCM operation waveforms of the gate
signal, the junction capacitor voltage and the inductor current at
rated load in case of Vin>Vout/2. HDCM is utilized in order to
Iavg
reduce the current ripple at light load and to allow for ZVS
TR2
Ts
during the complete period. Hence, HDCM basically becomest
2Qc
Qc=CdsVout
t3
0
TCM at rated load.
t1 t2
IR_n
During the positive-current interval Tmain, when SW1 is
2Qc
Ipk_n
turned off at t1, due to the high current peak at rated load, thecurrent is higher than the required positive current IR_p which isFig. 4. HDCM operation waveforms of gate signal, junction capacitor voltage the current value satisfying the condition for the ZVS
and inductor current at rated load in case of Vin>Vout/2. The design of the boost
inductance L and the dead time Tdead is carried out in TCM which allows for achievement of SW2. Similarly, the required negative current
ZVS at rated load.
IR_n stands for the current value which discharges completely
Cds1, i.e. one of the conditions for the ZVS achievement of
SW1. Considering the negative-current interval Tsub, as soon as FET2 is turned off at t3, Cds1 and Cds2 are connected in parallel. In
order to discharge Cds1, the charge Qc has to be removed and, assuming identical switches, the same charge Qc is required tocharge Cds2 to Vout. The larger the negative inductor current is, the shorter the transition time becomes. However, this negative
current should be minimized in order not to increase the current ripple, which causes excessive conduction loss and decreases
the efficiency at rated load. The required negative current IR_n is independent of the output power but only depends on Vin, Vout, Land the selected switch which defines Cds [9]-[10],
Ipk_p

iL

IR_n 

Tmain

Tsub

2CdsVout(2Vin  Vout)...............................(1)L

When FET2 is precisely turned off at the moment iL reaches IR_n, the resonance between L and Cds continues to flow iL until itreaches the negative current peak Ipk_n,

I pk _ n 

2CdsVoutVin............................................(2)L

Assuming that at rated load, the boost converter transmits the average current Iavg to the load over a switching period Tsw andalso generates the negative current Ipk_n for the ZVS achievement, the boost inductance L and the dead time Tdead which achieve
the minimum current ripple are derived as following. First, the positive-curent interval Tmain and the negative-current interval
Tsub are geometrically derived from the corresponding peak current Ipk_p and Ipk_n,

1
1 
Tma in  I p k _ p L  .............................(3) Vo u t  Vin Vin 11 
Tsu b  I p k _ n L  ..............................(4) Vo u t  Vin Vin 
In the boost converter applied with PWM, Tsw is constant, whereas Iavg is the total charge over Tsw,
Tsw  Tmain  Tsub ....................................................(5)1
1I avg  f sw  I pk _ pTmain  I pk _ nTsub  ....................(6)22Substituting (3) and (4) into (5) and (6) and solving for the boost inductance L, (7) is obtained.

Iavg*PI
Controller

Vout*

Vin

Iavg

Vout

Implemented into DSP
D1

PI
Controller
a

a/b

D2

Vin

D0

Vout

Vin
Vout
Cds
Tsw

DR2

DR1

SW1

1

b
0

Implemented into FPGA

0

Duty Generation for
TCM Interval(cf., session III.C)

DR1

Switching Signal
Generation
SW2

DR2

D2
D0
D1
Fig. 5. Control system of boost converter operating in HDCM. A FPGA-based DSP is employed in order to control the boost converter operating in HDCM.
Owing to the online calculation of the duty ratios, a real-time closed-loop control of HDCM can be realized.

L

Start

1

1
1 
f sw2  
 Vo u t  Vin Vin 

2.

Input parameters: D0, Vin, Vout, Cds, Tsw
Calculation of minimum required current peak: Ipk_n, Eq. (2)

1




2 I a vg
 2Cd sVo u tVin  2Cd sVo u tVin  11 f sw   

 Vo u t  Vin Vin  

2

(7)Then, the dead time Tdead is designed longer than thetransition time Ts in order to resonate out completely the charge
in the junction capacitor before the switches are turned on,
I
I 
I
Ts  L p k _ n R _ n  R _ n  .................................(8)Vin  Vo u t  Vin
To conclude, when the boost converter transmits Iavg to theload over Tsw at rated load, the condition to achieve ZVS is that
L and Tdead have to satisfy (7) and (8), respectively.

Calculation of min. required TCM period: TTCM_min, Eq. (11)Calculation of zero current period: Tzero, Eq. (12)Calculation of TCM period number: nTCM, Eq. (13)Calculation of applied TCM period: TTCM , Eq. (14)Calculation of applied current peak: Ipk, Eq. (15)Generating switching pulses: DR1, DR2, Eq. (16)-(17)EndFig. 6. Flowchart of switching signal generation during TCM interval.
Because the TCM current is flown in order to achieve the ZVS condition for
DCM, the losses and the charge from the additional TCM current is required
to be minimized. Furthermore, it is also necessary to achieve ZVS during the
TCM interval.

B. Control system of hybrid discontinuous current mode
Figure 5 depicts the control system of the boost converter operating in HDCM. The voltage and current regulators and thecalculation for the duty ratios are implemented into a digital signal processor (DSP), whereas the switching signals are generated
by a field-programmable gate array (FPGA) based on the duty ratios received from the DSP. In order to regulate the output
voltage Vout in response to the line, the load, and the parameter variations, a PI controller is employed into the voltage regulator
as a major control loop. The output of the voltage regulator, i.e. the average inductor current Iavg*, is then used as a command forthe current regulator. Note that the current regulator which is designed in order to deal with the nonlinearity in DCM has been
researched thoroughly in [16]-[19]. The current regulator outputs the duty ratio D1 of the positive-current interval Tmain as shownin Fig. 4. Based on the relationship between the current slopes during T main [16], the duty ratio D2 of SW2 and the duty ratio D0of the zero-current interval, i.e. the TCM interval, are estimated as follows,

D2  D1

Vin................................................(9)Vout  Vin

D0  1  D1  D2 .................................................(10)Then, the following parameters are used to generate the duty ratios DR1 and DR2 for the TCM interval (cf., Section III.C): theduty ratio D0, the input voltage Vin, the output voltage Vout, the junction capacitor value Cds, and the switching period Tsw.
Finally, the switching signals are generated in the FPGA by comparing the duty ratios D1, D2, DR1 and DR2 with multiple
counters. Owing to the online calculation of the duty ratios, a real-time closed-loop control of the proposed current mode
(HDCM) can be realized.
C. Duty generation for TCM interval
At light load, the negative current in TCM increases due to the constant switching frequency, which increases the ratio
between the current ripple and the average current. Consequently, the efficiency at light load decreases sharply [8], [15].
Therefore, HDCM is applied at light load in order to reduce the current ripple load and to achieve ZVS.

Figure 6 depicts the flowchart of the switching signal generation during the TCM interval in HDCM. It is necessary tocontrol the turn-on period of the switches during the TCM interval as depicted in Fig. 3 so that the following conditions are
satisfied;(i) the TCM interval has no influence on the DCM operation, which implies that the total charge during the TCM interval isrequired to be negligibly small,(ii) the ZVS condition for the next DCM period is satisfied, which implies that the current value at the end of the TCM
interval is required to be adjusted according to the zero-current interval of DCM by controlling the TCM current peak and theTCM period,(iii) the losses from the TCM interval such as the conduction loss are minimized, which implies that the TCM current peak islarge just enough to achieve ZVS over the TCM interval.
Figure 7 depicts the HDCM operation waveforms of the gate signal, the junction capacitor voltage and the inductor current atlight load. Note that only the zero-current interval in which TCM is applied is shown. First, the minimum current peak Ipk_n
which achieves the condition of ZVS for SW 1 is calculated from the total charge stored Qc in the junction capacitor Cds as in (2).
In order to let the inductor current reach the peak Ipk_n, the required TCM period TTCM_min is calculated by (11), 1
1 
TTCM _ min  I pk _ n L  ...................... (11) Vout  Vin Vin Next, the number of the TCM period nTCM is calculated from the zero-current period Tzero as shown in Fig. 6. The zero-current
period Tzero is calculated from the duty ratio D0 [16],Tzero  D0Tsw ........................................................(12)In order to minimize the losses from the TCM interval, the current peak Ipk of the TCM current is required to be minimal.
Consequently, it is necessary to choose the number of the TCM period nTCM as a maximum odd number,

nTCM 

Tzero
TTCM _ min; nTCM is an odd number. ...........(13)

Next, the applied TCM period TTCM is calculated from the zero-current period Tzero and the number of the TCM period nTCM,
T
TTCM  zero .......................................................(14)nTCM
Then, the applied current peak Ipk of the TCM current is calculated as in (15),
TTCM
I pk 1
1  ........................................(15)L  Vout  Vin Vin Finally, the duty ratios DR1 and DR2 of SW1 and SW2 in order to achieve the TCM current peak Ipk is calculated as in (16) and(17), respectively [9],DR1 DR 2 

L
f swVinI p2 k L

f sw (Vout  Vin )2Cd sVo u tVin..........................(16)
L
2
I pk


2CdsVout(Vout  Vin )..(17)L

TABLE I
PARAMETERS OF CIRCUIT AND CONTROLLERS IN EXPERIMENTS.

Gate Signal
FET2ONFET1ONFET1ONFET2ON

t

0
Tdead

vCds

Tdead

Tdead

vCds2

Vout

vCds1

t

0
Ipk

Symbol
Vin
Vout
P

iL

TR2

Ts

TR1

TR2

Ts

TR2

Ts

L
ΔiH
fsw1
fsw2

t

0

2Qc

IR

2Qc

fsw3

Qc=CdsVout-Ipk

nTCM: 1

2

3

TTCM

TTCM

TTCM

3

DiL

2Qc

Corresponding intervals in Fig. 3:
4

Tzero

C
fsamp
fc

zc

1

Fig. 7. HDCM operation waveforms of gate signal, junction capacitor voltage
and inductor current at light load. In order to achieve ZVS for the DCM
operation, the TCM period TTCM is adjusted according to the zero-current
period Tzero. Furthermore, in order to minimize the losses from the additional
TCM current, the current peak Ipk is designed to be just large enough toachieve ZVS for both switches SW1 and SW2 during the TCM interval.
Finally, in order to make the TCM interval has no influence on the DCM
operation, which implies the total charge from the additional TCM current is
negligibly small, the positive and negative values of the current peak Ipk arecontrolled to become equal.

fv

zv

Quantity
Value
Input Voltage
200 V
Output Voltage
350 V
Rated Output Power
1 kW
Experiments for Efficiency Comparison
Switching Device
SCH2080KE(ROHM)
Boost Inductor Value
70 mH
Current Ripple at Rated Loadin TCM, DCM and HDCM
100%
Switching Freq. at Rated Loadin TCM, DCM and HDCM
100 kHz
Maximum Switching Freq.
at Light Load in HDCM
300 kHz
Current Ripple at Rated Loadin CCM50%
Switching Freq. in CCM
200 kHz
Experiment for Load Step Response
Output Capacitor Value
360 mF
Sampling Frequency
25 kHzCutoff frequency (Current Regulator) 500 Hz
Damping factor (Current Regulator) 0.707
Cutoff frequency (Voltage Regulator) 10 Hz
Damping factor (Voltage Regulator) 0.707

As depicted in Fig. 6, the positive and negative values of thecurrent peak Ipk are controlled to be the same, which makes thetotal charge from the additional TCM current negligibly small.
Consequently, the TCM interval has almost no influence on the
DCM operation, which implies that the current ripple can be
reduced at light load by DCM. Hence, by controlling the TCM
current peak during the TCM interval, the proposed current
mode (HDCM) both reduces the current ripple load andachieves ZVS.
IV. LABORATORY SETUP
Table I shows the experimental parameters of the circuit and the controllers. A 1-kW prototype is realized with the SiC
devices and ferrite core N87. At rated load of 1 kW and the switching frequency of 100 kHz, the inductor value is designed by(7) in order to operate the boost converter in TCM. Consequently, three current modes TCM, DCM, and HDCM share the same
operation at rated load. On the other hand, in order to operate the boost converter by CCM under the same condition of the boost
inductor, the switching frequency is increased to 200 kHz. As a result, the inductor current ripple of CCM at rated load is
reduced by half compared to HDCM. On the other words, in order to achieve the same size of the boost inductor by using CCM
with the small inductor current ripple compared to HDCM with the high inductor current ripple, the switching frequency has to
be increased.
A. Basic operations of TCM, DCM, HDCM and CCM
Figure 8-10 depict the waveforms of the TCM, DCM, HDCM and CCM currents, and the junction capacitor voltages under
different conditions of load. At rated load, the current waveforms are same for TCM, DCM and HDCM. The current ripple of
TCM in Fig. 8 is constant against load. On the other hand, at light load, compared to TCM, the current ripple is greatly reduced
by DCM or HDCM. In particular, at light load of 0.2 p.u., the root-mean-square (RMS) current is reduced from 3.7 Arms (TCM)
to 1.8 Arms (DCM) or to 2.1 Arms (HDCM). The RMS current of HDCM is slightly higher than that of DCM due to theemployment of the TCM current during the zero-current interval. Furthermore, as shown in Fig. 9(c)-(d), the positive andnegative values of the TCM current are controlled to be almost the same. Consequently, the addition TCM current has no effects
on the DCM operation. This allows the conventional DCM current control to be applied simply to HDCM [16]-[19]. As shownin Fig. 10, by increasing the switching frequency from 100 kHz to 200 kHz, the boost converter is operated in CCM at rated
load. Compared to TCM, the smaller RMS current is achieved in CCM owing to the increase in the switching frequency.

Junction Capacitor Voltage of
SW1 VCds1(250 V/div)

Junction Capacitor Voltage of
SW1 VCds1(250 V/div)

Junction Capacitor Voltage ofSW2 VCds2(250 V/div)

Junction Capacitor Voltage ofSW2 VCds2(250 V/div)

0V

0V

11(a)
0A

0A

Inductor Current iL(5 A/div) Time(2 ms/div)
RMS current = 6.1 Arms(a) TCM current and junction capacitor voltages at rated load.

(a) DCM current and junction capacitor voltages at light load of 0.6 p.u.

Junction Capacitor Voltage of
SW1 VCds1(250 V/div)

Inductor Current iL(5 A/div) Time(2 ms/div)

Junction Capacitor Voltage of
SW1 VCds1(250 V/div)

Junction Capacitor Voltage ofSW2 VCds2(250 V/div)

0V

0V

0A

0A

Inductor Current iL(5 A/div) Time(2 ms/div)

RMS current = 4.6 Arms(b) TCM current and junction capacitor voltages at light load of 0.6 p.u.
Junction Capacitor Voltage of
SW1 VCds1(250 V/div)

Junction Capacitor Voltage ofSW2 VCds2(250 V/div)

Inductor Current iL(5 A/div) Time(2 ms/div)

RMS current = 1.8 Arms(b) DCM current and junction capacitor voltages at light load of 0.2 p.u.
Junction Capacitor Voltage of
SW1 VCds1(250 V/div)

Junction Capacitor Voltage ofSW2 VCds2(250 V/div)

0V

RMS current = 4.1 Arms

Junction Capacitor Voltage ofSW2 VCds2(250 V/div)

0V
11(b)
0A

0A
Inductor Current iL(5 A/div) Time(2 ms/div)

RMS current = 3.7 Arms(c) TCM current and junction capacitor voltages at light load of 0.2 p.u..
Fig. 8. Waveforms of TCM current and junction capacitor voltages under
different conditions of load.

Inductor Current iL(5 A/div) Time(2 ms/div)

RMS current = 4.2 Arms(c) HDCM current and junction capacitor voltages at light load of 0.6 p.u.
Junction Capacitor Voltage of
SW1 VCds1(250 V/div)

Junction Capacitor Voltage ofSW2 VCds2(250 V/div)

Figure 11 illustrates the waveforms of the gate signal and thejunction capacitor voltage, which is the magnified waveforms
from Fig. 9(a), 9(c), and 10(b). As explained in Fig. 2(b), the 0V
hard switching can still occur in DCM. The switching behavior
and the switching loss of DCM depends on the resonancebetween the boost inductor and the junction capacitors during
the zero-current interval. On the other hand, it is confirmed in 0A
Fig. 11(b) that both the switches SW1 and SW2 are turned on at
Inductor Current iL(5 A/div) Time(2 ms/div)
RMS current = 2.1 Arms
the zero voltage, i.e. ZVS. Furthermore, the turn-off losses can(d) HDCM current and junction capacitor voltages at light load of 0.2 p.u.
be simply reduced by connecting a snubber capacitor parallel to Fig. 9. Waveforms of DCM and HDCM currents, and junction capacitor
the switch in order to delay the rise of the junction voltage. voltages under different conditions of load.
Consequently, low switching loss can be accomplished in orderto further increase the switching frequency and to achieve the high power density. In Fig. 11(c), the occurrence of the hardswitching is confirmed in CCM similarly to DCM. The hard switching in DCM and CCM not only generates high switching loss
but also distorts the gate signal due to the high di/dt of the discharge current from the junction capacitor. The gate signal
distortion can lead to the occurrence of the false triggering in CCM and DCM. In order to avoid the occurrence of the false
triggering during hard switching in CCM and DCM, the main circuit and the gate driver circuit are required to be customized forthe high di/dt of the current, which is undesirable due to the increase in cost. On the other words, the soft switching in HDCM
not only reduces the switching loss but also benefits the design cost of the main circuit and the gate driver circuit.

Junction Capacitor Voltage of
SW1 VCds1(250 V/div)

Junction Capacitor Voltage ofSW2 VCds2(250 V/div)

Gate signal distortion
0V

Vgs1 (10 V/div)

Hard switchingof SW1

0V

VCds1 (250 V/div)
0V
0A

0V
Inductor Current iL(5 A/div) Time(2 ms/div)

Time (400 ns/div)

Vgs2 (10 V/div)

RMS current = 5.3 Arms(a) CCM current and junction capacitor voltages at rated load.
VCds2 (250 V/div)
Junction Capacitor Voltage of
SW1 VCds1(250 V/div)

Junction Capacitor Voltage ofSW2 VCds2(250 V/div)

0V(a) Hard switching in DCM.

0V

Vgs1 (10 V/div)

0V
11(c)

ZVS of SW1
0A

VCds1 (250 V/div)

Inductor Current iL(5 A/div) Time(2 ms/div)

0V
RMS current = 3.5 Arms

Time
(400 ns/div)(b) CCM current and junction capacitor voltages at light load of 0.6 p.u.

Vgs2 (10 V/div)

0V
Junction Capacitor Voltage of
SW1 VCds1(250 V/div)

Junction Capacitor Voltage ofSW2 VCds2(250 V/div)

VCds2(250 V/div)

ZVS of SW20V(b) Soft switching in HDCM.

0V

Gate signal distortion
0A
Inductor Current iL(5 A/div) Time(2 ms/div)

0V

Vgs1 (10 V/div)

Hard switchingof SW1

RMS current = 2.0 Arms(c) CCM current and junction capacitor voltages at light load of 0.2 p.u..
Fig. 10. Waveforms of CCM current and junction capacitor voltages under
different conditions of load.

VCds1 (250 V/div)
0V

0V

V

(10 V/div)gs2
B. Comparisons of RMS current and efficiency among four
current modes
Figure 12 shows the comparisons of RMS current andVCds2 (250 V/div)
Time (400 ns/div)
efficiency among TCM, DCM, HDCM and CCM. Note that the 0V
same boost inductor is used to conduct the experiments of the (c) Hard switching in CCM.
efficiency comparison. First, as shown in the results of the ratio Fig. 11. Waveforms of gate signal and junction capacitor voltage in DCM,
and CCM which is the magnified waveforms from Fig. 9(a), 9(c), andbetween the RMS current IL_rms and the average current Iavg, by HDCM
10(b).
utilizing the variable current-ripple characteristic of DCM, theRMS current in HDCM is reduced greatly compared to TCM.
In particular, at light load of 0.1 p.u., the RMS current of HDCM is reduced by 56.6%. Besides, the RMS current of HDCM at
rated load is as same as that in TCM, because the converter is designed to be operated with TCM at rated load. This design
minimizes the required current ripple in order to achieve ZVS at rated load. Consequently, the efficiency of HDCM at rated load
is as same as that in TCM, whereas at light load, the efficiency is improved up to 3.1% with HDCM. On the other hand, theRMS current of HDCM is slightly higher than that of DCM due to the employment of the TCM current during the zero-current
interval. However, the efficiency of HDCM is higher than that of DCM over entire load range because the hard switching still
occurs in DCM. Note that the variation of the DCM efficiency is quite large because the turn-on loss of the hard switching in
DCM depends on the zero-current interval which changes according to load. Finally, the efficiency of CCM shows a sharp
decline around load of 0.5 p.u. because the boost converter changes the current mode from TCM to CCM as shown in Fig. 10(b)-(c). By applying HDCM, the efficiency at rated load is improved by 0.9% compared to CCM.

Power loss [W]Power loss [W]Figure 13 shows the loss distribution of four current modes
25.0
under different conditions of load. The conduction losses and
0.2
1.0
Conduction loss
Core loss
20.0
the switching losses are obtained from the simulator, i.e.
1.4Turn on loss
Winding loss
2.6
PLECS, whereas the core losses and the winding losses are
Gate driving loss
Turn off loss
15.0
obtained from the inductor modeling software entitled
GeckoMAGNETICS. As shown in Fig. 13(a), the turn-on loss
0.1
0.1
0.1
10.0
in CCM is dominant and this greatly reduces the efficiency at
1.3
1.3
1.3
13.7
rated load. The turn-on loss in DCM varies largely depending
3.5
3.5
3.5
5.0
on the zero-current interval which changes according to load
2.0
2.0
2.0
and the other conditions of the circuit such as the input and
3.0
3.0
3.0
2.3
0.0
output voltage. On the other hand, as shown in Fig. 13 (c), the
CCM
DCM
TCM
HDCM
high conduction loss and inductor loss still occur in TCM even (a) Loss distribution at rated load.
at light load due to the constant current ripple. The losses from12.0
the high current ripple in TCM at light load can be reduced by
Conduction loss
Core loss
0.2
Turn on loss
Winding loss
0.4
applying HDCM. This efficiency improvement at light load is
10.0
1.2
Gate driving loss
Turn off loss
specially desired in the photovoltaic system, where the most
1.6
8.0
frequent operating range locates at light load. Note that the
0.1
0.1
0.7
increase in the gate driving loss when applying HDCM is
0.5
0.2
6.0
0.6
negligibly small compared to the reduction of the other losses.
1.9
2.8

4.0

6.6

2.1

1.3
1.8

2.0

1.0
0.8
CCM
DCM
(b) Loss distribution at load of 0.5 p.u..

1.5
TCM

1.1
HDCM

0.1
0.5

Core loss
Winding loss
Gate driving loss

2.0
0.0

7.0
6.0

Conduction loss
Turn on loss
Turn off loss

Power loss [W]

5.0
4.0
3.0

0.1

0.2
0.3
1.3

0.7
0.6

0.1

2.6
0.3
0.2
0.9
2.0

2.0
1.0

1.9

2.9

2.0

1.9
0.1

1.0

0.2
CCM
TCM
HDCM
DCM
(c) Loss distribution at load of 0.1 p.u..
Fig. 13. Loss distribution of four current modes under different conditions ofload. In the SiC device, the turn-on switching loss is dominant due to thereverse recovery charge or the junction capacitor charge of the free-wheelingdevice at hard-switching condition. Therefore, it is crucial to eliminate theturn-on switching loss in order to increase the switching frequency and still
maintain the high efficiency.
0.0

0.3

8.0

Gate Signal

Ratio between RMS current and average inductor current IL_rms/Iavg

Reduced by 56.6%

FET1ON

7.0

Tsw

Dead timeFET2ON

D1Tsw
t

0

Ipk2

Actual DCM currentiL

Ipk1 DIavg
t

6.0
0

5.0

Theoretical DCM current

Fig. 14. Theoretical and actual DCM currents. Due to the resonance between
the boost inductor and the junction capacitors, the high average-current ripple
occurs in DCM. Consequently, the minimization of the boost inductor in
DCM suffers this high average-current ripple.

CCM

4.0

t2

t1

TCM

3.0

Time (4 ms/div)
ENABLE_HDCM

2.0

HDCM

DCM

0

DCM

HDCM
Inductor Average
Current Iavg(1 A/div)

1.0
Desired ratio between RMS current andaverage inductor current IL_rms/Iavg
0.0

0

0.1

0.2

0.3 0.4 0.5 0.6 0.7
Output Power Pout [p.u.]

0.8

0.9

1.0

(a) Ratio between RMS current and average current.

0A

100

Inductor Current iL(5 A/div)

Maximum efficiency: 98.8%
1 p.u. of output power is 1 kW.

(a) Average current when the current mode is changed from DCM to HDCM
at load of 0.6 p.u..

99
HDCM

Maximum amplitude is 34 mA at around 260 Hz.

0.9%
DCM

98

Harmonic components of DCM averagecurrent ripple DIavg (5 mA/div)

Efficiency h [%]CCM

Frequency(500 Hz/div)

97
0.5%
96
1.5%
95
TCM
94

93

Efficiency improvement by HDCM
compared to other current modes;
1) At light load of 0.1 p.u.:
HDCM versus TCM: 3.1%
HDCM versus DCM: 1.5%
HDCM versus CCM: 0.5%
2) At rated load of 1.0 p.u.:
HDCM versus CCM: 0.9%

0A(b) Harmonic analysis results of DCM average-current ripple.
Compared to DCM, HDCM significantly reduces the current
ripple by 82.3% at the maximum amplitude.

3.1%

0

0.1

0.2

0.3 0.4 0.5 0.6 0.7
Output Power Pout [p.u.]

0.8

0.9

Harmonic components of HDCM averagecurrent ripple DIavg (5 mA/div)

1.0

Maximum amplitude is 6 mA ataround 260 Hz.

(b) Efficiency characteristic.
Fig. 12. Comparison of RMS current and efficiency among TCM, DCM,
HDCM and CCM.

Frequency(500 Hz/div)

0A

C. Average current ripple reduction and Output voltage
regulation
Figure 14 describes the theoretical and actual DCM currents.
At t1, when both the switches SW1 and SW2 are turned off, thetheoretical DCM current remains zero until t2. However, due tothe resonance between the boost inductor and the junction
capacitors, a current flows during the interval from t1 to t2. At t2,(c) Harmonic analysis results of HDCM average-current ripple.
Fig. 15. Average-current ripple reduction by applying HDCM. The

high average-current ripple occurring in DCM worsens the maximum
power point tracking in the photovoltaic system. By applying
HDCM, the average-current ripple can be reduced greatly. This
enables the minimization of the boost inductor.

the theoretical DCM current starts to rise from 0A and reaches
the current peak Ipk1 after the turn-on interval D1Tsw of SW1,
whereas the actual DCM current reaches the current peak Ipk2.
Output Voltage Vout (50 V/div)
0.2 p.u.
0.6 p.u.
The difference between Ipk1 and Ipk2 results in the averageof loadof loadcurrent ripple DIavg. On the other words, the current flowing
Time (20 ms/div)
during t1 and t2 acts as a disturbance to the current regulator.
Furthermore, the amplitude of the current flowing during t1 andInductor Current iL(5 A/div)
t2 is inversely proportional to the boost inductor value. This
relationship has been researched thoroughly in [20].
Consequently, the minimization of the boost inductor in DCM 0A
suffers the high average-current ripple. On the other hand, theTCM current in HDCM is controlled in order to let the current (a) Load step change: 0.2 p.u. to 0.6 p.u..
return to zero before the next switching period (cf., Section III).
Therefore, the average-current ripple can be reduced by theemployment of HDCM.
0.2
0.6 p.u.
0.2 p.u.
Output Voltage Vout (50 V/div)
Figure 15 depicts the experimental results of the averageof loadof loadcurrent ripple reduction by applying HDCM. When the signal of
ENABLE_HDCM becomes high, the current mode changes
Time (20 ms/div)
from DCM to HDCM. The reduction of the average-current
ripple by applying HDCM can be observed from Fig. 15(a).
Inductor Current iL(5 A/div)
Then, the harmonic analysis of the average-current ripple in
DCM and HDCM is conducted and the results are shown in Fig.
15(b)-(c), respectively. As observed from Fig. 15(b), the 0A
average-current ripple in DCM consists of many low-frequency 0V
harmonic components, one of which has the maximum (b) Load step change: 0.6 p.u. to 0.2 p.u..
amplitude of 34 mA around 260 Hz. The average-current ripple Fig. 16. Load transient response by output voltage control with 10 Hz cutoffin DCM decreases the efficiency of the photovoltaic system, frequency. The overshoot voltage and the settling time are 28 V and 56 ms,
errors of which compared to the designed values are 3.6% and 1.8%,
because the maximum power point tracking is decayed with this therespectively [18].
average-current ripple. Furthermore, a large input filter which
has a low cut-off frequency is required if the average-current
ripple in DCM has to be filtered out, because the harmonic components of the average current ripple in DCM occur in the low
frequencies. This problem restricts the minimization of the boost inductor by DCM. The average-current ripple in DCM can also
be reduced by damping the resonance between the boost inductor and the junction capacitors. This can be accomplished by
employing a snubber circuit connected parallel to the switching devices. However, the snubber circuit not only increases theswitching loss as shown in Table I in [20], but also restricts the minimization of the boost converter. On the other hand, as
observed from Fig. 15(c), the harmonic components of the average-current ripple are greatly reduced by applying HDCM. In
particular, compared to DCM, the maximum amplitude of the harmonic components is reduced by 82.3%. Note that the small
average-current ripple still occurs in HDCM due to the limited resolution of the counter in the FPGA which is generated by aclock frequency of 200 MHz. This causes the TCM current cannot exactly return to zero before the next switching period. This
problem can be alleviated by increasing the clock frequency of the FPGA.
Figure 16 shows the load transient response obtained in experiment by the output voltage control with 10-Hz cutoff
frequency. The test is conducted with a load current step from 0.2 p.u. to 0.6 p.u. and vice versa. The overshoot voltage and thesettling time are 28 V and 56 ms, the errors of which compared to the designed values are 3.6% and 1.8%, respectively. The
stability of the voltage control in HDCM is similar to that in DCM because the online calculation of the duty ratios is employed
and the TCM current is controlled to have no influence on the DCM operation. Consequently, this confirms that the real-timeclosed-loop control of HDCM can be realized as same as DCM. Furthermore, the duty generation for the TCM interval can be
carried out with a margin considering the element tolerances, whereas the feedback control ensures the stable operation of
HDCM.
V. CONCLUSION
This paper presented a hybrid current mode between TCM and DCM in order to improve the wide-load-range efficiency forthe high-frequency SiC-based boost converter. In the proposed current mode entitled HDCM, ZVS was achieved without any
additional components as same as the conventional TCM. Consequently, the high power density design was accomplished byusing the SiC devices at high switching frequency. The advantages of HDCM were compared to the other current modes; i.e.
TCM, CCM, DCM.
First, in TCM, the constant current ripple decreased significantly the efficiency at light load. Therefore, HDCM in which
TCM was applied during the zero-current interval of DCM, was introduced in order to reduce the current ripple and to allow forZVS over entire switching period. As a result, under the condition of the same boost inductor, the efficiency of HDCM at lightload of 0.1 p.u. was improved by 3.1% compared to TCM.
Second, in order to operate the boost converter by CCM under the same condition of the boost inductor, the switchingfrequency was increased from 100 kHz to 200 kHz. As a result, the inductor current ripple of CCM at rated load was reduced byhalf compared to HDCM. In CCM, the hard switching occurred due to the discharge of the reverse recovery charge and thejunction capacitor charge. Therefore, the efficiency of CCM at rated load was lower by 0.9% compared to HDCM. Furthermore,
the hard switching in CCM not only generated high switching loss but also distorted the gate signal due to the high di/dt of thedischarge current from the junction capacitor. The gate signal distortion can lead to the occurrence of the false triggering in
CCM. In order to avoid the occurrence of the false triggering during hard switching in CCM, the main circuit and the gate drivercircuit are required to be customized for the high di/dt of the current, which is undesirable due to the increase in cost. On theother words, the soft switching in HDCM not only reduced the switching loss but also benefitted the design cost of the main
circuit and the gate driver circuit.
Finally, the hard switching in DCM can still occur depending on load. Therefore, the efficiency of HDCM was improved by
1.5% at most compared to DCM. Furthermore, due to the resonance between the boost inductor and the junction capacitors, acurrent flew during the interval when both the switches are turned off. This current was the reason of the difference between thetheoretical and actual DCM currents, which generated the average-current ripple. The average-current ripple in DCM decreased
the efficiency of the photovoltaic system, because the maximum power point tracking was decayed with this average-current
ripple. On the other hand, the TCM current in HDCM was controlled in order to let the current return to zero before the next
switching period. Therefore, the average-current ripple could be reduced by the employment of HDCM. As a result, compared to
DCM, the maximum amplitude of the harmonic components in the HDCM average-current ripple was reduced up to 82.3%.
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[1]