Current Harmonic Reduction based onSpace Vector PWM for DC-link Capacitors inThree-Phase VSIs Operating over a
Wide Range of Power Factor
Koroku Nishizawa, Student Member, IEEE, Jun-ichi Itoh, Senior Member, IEEE,
Akihiro Odaka, Member, IEEE, Akio Toba, Member, IEEE, and Hidetoshi Umida, Member, IEEE
Abstract-- This paper proposes a novel space vector pulse
width modulation (SVPWM) strategy to reduce the switchingfrequency-order inverter input current harmonics for a two-level
three-phase voltage source inverter operating over a wide rangeof the load power factor. The fluctuation of the inverter input
current around its average value is minimized by optimization of
the utilized voltage space vectors to reduce the inverter input
current harmonics, which extends the lifetime of the DC-linkelectrolytic capacitors. Furthermore, the proposed strategy canbe adapted to a motor drive system, where a wide variation of theload power factor is desired, by changing the optimized
combinations of the voltage space vectors according to thepolarities of the output phase currents. Experiments withapplication of the novel SVPWM confirm that the inverter input
current harmonics is reduced by up to 29.5% compared to thatwith the conventional SVPWM strategy. Moreover, the analyticaland experimental results confirm that the proposed SVPWM
reduces the inverter input current harmonics in both driving
mode and regenerative braking mode, as well as with any load
power factor.
Index Terms—DC-link capacitor, Inverter input current
harmonics, Space vector pulse width modulation, Three-phase
VSI.

I. INTRODUCTION

T

hree-phase AC motors are widely used in industrial andhousehold applications [1]–[3]. The lifetime extension of
the AC motor drive system has been an intense research topic
for several decades [4]–[6]. The AC motor is supplied withpower from a pulse width modulation (PWM) inverter.
Capacitors in the DC-link part of the PWM inverter, which act
as an energy buffer stage to stabilize the DC-link voltage andguarantee an acceptable DC-link voltage ripple, are required tohave large capacitance. Electrolytic capacitors are generally
employed due to their superior capacitance per volume ratio
compared to film capacitors or ceramic capacitors. However,the system becomes less reliable due to the short lifetime
Manuscript received December 7, 2017; revised February 20, 2018 and
May 22 2018; accepted July 9, 2018.
Koroku Nishizawa and Jun-ichi Itoh are with the Nagaoka University ofTechnology, Niigata 940-2188, Japan (e-mail: koroku_nishizawa@stn.
nagaokaut.ac.jp; itoh@vos.nagaokaut.ac.jp).
Akihiro Odaka, Akio Toba and Hidetoshi Umida are with the Fuji Electric
Co. Ltd., Tokyo 191-8502, Japan (e-mail: odaka-akihiro@fujielectric.com;
toba-akio@fujielectric.com; umida-hidetoshi@fujielectric.com).

expectancy of electrolytic capacitors. In particular, the lifetimeof a DC-link capacitor is related to its current, which isdependent on the switching-frequency-order inverter input
current harmonics [7]. The inverter input current is known to
be a superposition summation of the switched current pulses
from each phase leg of the three-phase PWM voltage source
inverter (VSI), and thus contains many high-order switchingharmonics [8], [9]. In particular, internal heating of anelectrolytic capacitor, which is caused by this inverter input
current harmonics flowing through an equivalent series
resistance (ESR) of the capacitors, constitutes a considerable
restriction of the long lifetime. Specifically, vaporization of
the electrolyte is closely related to the capacitor temperature,and the lifetime of the electrolytic capacitor is approximately
reduced by half if the capacitor core temperature increases by
10℃, according to the Arrhenius equation [10]. Therefore, theDC-link capacitor is a key component that determines the
lifetime of the entire motor drive system, and the DC-link
capacitor lifetime is dependent on the inverter input current
harmonics. It is noted that using film capacitors as DC-link
capacitors could possibly resolve the lifetime problem;
however, film capacitors would make the motor drive systembulky due to its low energy density.
In order to extend the lifetime of the DC-link capacitor,
modulation methods of the VSI which reduce the inverter
input current harmonics have been proposed [11]–[13]. In [11],the near state PWM (NSPWM) has been proposed to reducethe common mode voltage for three-phase VSI. The NSPWM
uses a group of three neighbor voltage vectors to match theoutput and reference volt-seconds. As a result, not only thecommon mode voltage, but also the inverter input current
harmonics can be reduced when the load power factor ishigher than 0.8. However, the NSPWM can be applied only at
high-modulation indices due to the restrictions on the voltage
vector use; therefore, the inverter input current harmonics
cannot be reduced at low-modulation indices with the
NSPWM. The proposed PWM method in [12] is basically thesame as this NSPWM and the effectiveness of this PWM
method on the inverter input current harmonics is analyticallyand experimentally confirmed in detail. The extended double
carrier PWM (Ext-DCPWM), which can reduce the inverter
input current harmonics for all values of the modulation index,

iDC.conv
iC

Edc

iDC.inSup

SectorSvp

iu
iv vuv
iw vvw

+
Cdc

Sun

I

Swp

Svn

vwu

Motor
load

vu*

vv*

vw*

iu

iv

iw

0

Swn

0

0°

Fig. 1.

Three-phase VSI with motor load.

has been presented in [13]. The Ext-DCPWM uses the same
three consecutive voltage vectors as in [11] and [12] at highmodulation indices. In addition, the Ext-DCPWM uses two
nonadjacent voltage vectors and one zero vector to reduce theinverter input current harmonics at low-modulation indices.
However, in the case of a low load power factor, thesemodulation methods increase the inverter input current
harmonics. Therefore, a modulation method that reduces theinverter input current harmonics over a wide load power factor
range is necessary to extend the lifetime of the DC-link
capacitor in a motor drive system, of which the variation of
the load power factor is considerably wide.
This paper proposes a novel space vector PWM (SVPWM)
that reduces the switching-frequency-order inverter input
current harmonics under any load power factor condition, i.e.
both driving and regenerative breaking modes. As a result ofanalytical calculations, the employment of voltage vectors inthis proposed strategy to reduce the inverter input current
harmonics at both high-modulation and low-modulation
indices, and provide the same result as the Ext-DCPWM in[13] under a unity load power factor. The analytical
calculations also provide a way to indicate the effectiveness of
the load power factor on the inverter input current harmonics.
The optimized voltage vectors are selected on the basis of thedetected output phase current polarities to adapt to variationsof the load power factor without detecting it. Therefore, theoriginal contribution of this strategy is the reduction of theinverter input current harmonics over entire region of the load
power factor, which is the crucial problem of past works.
This paper is organized as follows; firstly, analytical resultson the inverter input current of the three-phase VSI arepresented. In particular, the relationship between the inverter
input current and the modulation strategy of the VSI ispresented. Secondly, the methods for reduction of the inverter
input current harmonics by optimization of the voltage space
vectors introduced in [13] are explained. The method used toadapt to the variations of the load power factor is thenpresented. Analytical and experimental results are presented toconfirm the effectiveness in terms of the reduction of theinverter input current harmonics, the impact on the output
phase current quality, inverter efficiency, and the lifetime ofthe electrolytic capacitors.

VI

V

IV

III

II

q

60°

120°

180°

240°

300°

360°

Fig. 2. Waveforms of voltage references and output phase current at unity
load power factor (φ = 0°).

bV2 (1 1 0)

V3 (0 1 0)
II

Sector I

III
V4 (0 1 1)II.

q= taV7 (1 1 1) V0 (0 0 0)IVVI

V1 (1 0 0)Vq: Phase angle

V5 (0 0 1)

Fig. 3.

V*V6 (1 0 1)

Output voltage space vectors of VSI in ab reference frame.

INVERTER INPUT CURRENT HARMONICS ANALYSIS

A. Conventional Space Vector PWM
Fig. 1 shows a three-phase VSI employed in the motor
drive system. The three-phase VSI consists of three halfbridge converters. If the semiconductor switching devices aretreated as ideal switches, then the conduction status of any one
half-bridge converter can be represented by the following
binary switching functions: 1, (Sxp : ON, Sxn : OFF)sx (t )  , ( x  u, v, w).   0, (Sxp : OFF, Sxn : ON)

Fig. 2 shows waveforms of the voltage references and theoutput phase currents at unity load power factor. The output
phase currents of the VSI at steady state operating condition
can be expressed as: iu (t )  I m cos t   





  ,  iv (t )  I m cos  t 
3







iw (t )  I m cos  t  3   






where Im is the maximum value of the output phase current, ωis the fundamental angular frequency, and φ is the load power
factor angle, i.e. the phase shift between the phase current andphase voltage, respectively.

Fig. 3 shows the output voltage space vectors of the VSI in
the ab reference frame. These voltage space vectors can beillustrated on the basis of the Clarke transform. The switching
functions of each phase can become only two different values;
therefore, there are 23 = 8 output voltage space vectors of the
VSI expressed using the switching functions as V (su(t), sv(t),sw(t)). Six of these (V1–V6) are the active vectors and theothers (V0 and V7) are the zero vectors. The voltage reference
vector can also be derived from the voltage reference values
on the basis of the Clarke transform, and can be expressedwith the modulation index m and the phase angle θ:V*  mq . bV2 (1 1 0)
t2
V2
Ts

t
t0
V0 + 7 V 7
2T s
2TsV0 (0 0 0)
V7 (1 1 1)

Fig. 4.





a

t1
V1
Ts

V1 (1 0 0)

Conventional SVPWM strategy.

t

sv

t

sw

t
iDC.in

–iw
iu



0

iDC.in.ave

iu+iv

iv

where ta–tc are the on-duty of each selected voltage space
vector, and a–c represent the number of selected voltage space
vectors, as defined in Fig. 3.
Fig. 4 shows the conventional SVPWM strategy. The
output phase current harmonics are caused by the difference
between the voltage space vector and the voltage reference
vector Vx–V*. Therefore, in the conventional one-carrier
PWM strategies [14]–[20], three voltage space vectors which
are the closest to the voltage reference vector are used tominimize the output phase current harmonics. In the example
shown in Fig. 4, the voltage reference vector is generatedusing two adjacent active vectors, V1 and V2, and the zero
vector, V0 and V7, at each control period when the voltage
reference vector is located in sector I.

SectorIqsu

In the SVPWM, the voltage reference vector sampled ineach control period Ts is generated by synthesizing the three
voltage space vectors Va, Vb, Vc upon the volt-second balance
principle as:ttt
V *  a Va  b Vb  c Vc
TsTs
Ts , 
Ts  ta  tb  tc

V*

V0 V1

V2

V7
Ts

V2

V1 V0

t

Fig. 5. Instantaneous waveform of inverter input current at sector I withconventional SVPWM.



iDC .in .RMS 

3





tk

 
i
  
T
30k  a ,b,c2
DC .in , ks(t ) dq , where tk is the on-duty of the selected voltage space vector,
and iDC.in,k(t) is the instantaneous value of the inverter input
current when the selected voltage space vector is applied. As
shown in (6), the RMS value of the inverter input current
changes according to the choice of the voltage space vectors.

C. Average value of Inverter Input Current
The inverter input current iDC.in can be split into:
1) a current iDC.conv, coming from the converter-side, of
which the average value is constant, and2) a variable current iC, flowing through the DC-link
capacitors.
The average value of iDC.conv is the same as the DC-link
average current value because the DC current does not flow
through the DC-link capacitors. These average currents can be calculated as follows:

B. RMS value of Inverter Input Current
Fig. 5 shows the instantaneous waveform of the inverter
input current at sector I when the conventional SVPWM isapplied. Note that the phase currents are assumed to be almost
constant during a control period. The instantaneous value ofthe inverter input current is the superposition summation of
the switched current pulses from each phase leg and can becalculated as:

iDC .in (t )  s (t )  i (t ) . 

x u ,v, w

xx

The DC-side of the three-phase VSI operates at six-foldfundamental frequency, so that the root-mean-square (RMS)
value of the inverter input current can be calculated byconsidering only a sixth of the fundamental period as:

iDC .conv.ave  iDC .in.ave 


3





tk

i
 
 
T
3
0

k  a ,b ,cDC .in ,ks3 m  I m cos .
4(t )  dq
 



It can be concluded from (7) that the average value of thecurrent coming from the converter-side is not dependent onthe choice of the voltage space vectors, but the modulationindex and the load power factor. Thus, the average value ofthe current coming from the converter-side is always constant,regardless of the choice of the voltage space vectors in thesteady state.

b
V3 (0 1 0)

V2 (1 1 0)
t2
V2
Ts

t3
V3
Ts

D. RMS value of DC-link Capacitor Current
The RMS value of the DC-link capacitor current can bederived by the geometrical difference between the RMS valueof the inverter input current (6) and the average value of thecurrent coming from the converter-side (7) as follows:

V*

q
t1
V1
Ts

a
V1 (1 0 0)

(a)
su



iC .RMS  i

2
DC .in. RMS

i2
DC .conv.ave

.

t


sv

As shown in (8), the RMS value of the DC-link capacitor
current, which affects the lifetime of the DC-link capacitors, isalso dependent on the choice of the voltage space vectors.
Therefore, the lifetime of the DC-link capacitors can beextended by the selection of voltage space vectors that canminimize the RMS value of the inverter input current.
E. Instantaneous RMS value of Inverter Input Current
To minimize the RMS value of the inverter input current,
the optimized combination of the voltage space vectors is
selected based on the instantaneous RMS value of the inverter
input current over one control period, which is derived from
(9) [21]:1 Ts 2iDC .in (t ) dt
Ts 0





t

sw

t
iDC.in

–iw
iu

iu

iv
0

V1

V2

V3
Ts

iDC.in.ave
V2

V1

t

(b)
Fig. 6. Optimized combination of voltage space vectors for minimum RMS
value of inverter input current when iu and iv are positive and iw is negative at
high-modulation indices (a) combination of voltage space vectors and(b) instantaneous waveform of inverter input current.

omission of the zero vector [11]–[13], [22]. Note that, theomission of the zero vector can be achieved only when the tip of the voltage reference vector belongs to the triangle formedt 2
by the tips of the three consecutive voltage space vectors  k iDC
.in ,k (t ) .
shown by the shaded area in Fig. 6(a), i.e. at high-modulationk  a ,b ,c Ts
indices. The area that can be output using three consecutive
Note that a smaller difference between the instantaneous voltage space vectors is the same as that with conventional
value iDC.in, and the average value of the inverter input current SVPWM. Thus, the optimized combinations of the voltage
iDC.in.ave results in a smaller RMS value of the inverter input space vectors for the minimum RMS value of the inverter
current. The RMS value of the inverter input current can thus input current allows the same output voltage limitations as
be reduced by minimizing the fluctuation of iDC.in around the conventional SVPWM to be obtained. The instantaneous
average value, iDC.in.ave. The fluctuation of iDC.in is expressed as inverter input current does not become zero during a control
the shaded areas in the instantaneous waveform of the inverter period, as shown in Fig. 6(b), because the zero vectors are not
input current in Fig. 5. In cases where the conventional applied. Furthermore, when the phase current iu and iv are
SVPWM is applied, two zero vectors, V0 and V7, are used at positive, and iw is negative, the fluctuation of the inverter input
each control period. When the zero vector is applied, the current around the average value can be minimized with thisinstantaneous value of the inverter input current becomes zero, optimized combination of the voltage space vectors (V1, V2,
which leads to the large inverter input current fluctuation and V3) at high-modulation indices, which results in theminimum RMS value of the inverter input current. Note thataround the average value.
there is only one optimized combination of the voltage space
vectors and this optimized combination is dependent on theIII. REDUCTION OF INVERTER INPUT CURRENT HARMONICS
modulation index, phase angle, and load currents. In order to
A. At High Modulation Indices
optimize the combination of the voltage space vectors to
Fig. 6 shows the optimized combination of the voltage obtain the minimum RMS value of the inverter input current,
space vectors to minimize the RMS value of the inverter input at first, the instantaneous values of the inverter input current of
current at high-modulation indices, and when the phase each combination of three voltage space vectors are calculated
currents iu and iv are positive, and iw is negative. As shown in as (5). Then, the combination, which makes the instantaneousFig. 6(a), three consecutive active vectors (V1, V2, and V3) are values of the inverter input current become the closest to theused to generate the voltage reference vector, which results in average value of the inverter input current, is selected.

iDC .in.RMS (Ts ) Modulation
wave [p.u.]

1.2
1.2
Proposed SVPWM
0.8
0.8
0.4
0.4
vu*
0
0.0
-0–0.4.4-0–0.8.8-1–1.2.2
Zero-sequence
1.2 00.0033333
1.2
0.0066667
0.01
0.0133333
0.0166667
0.02
components
0.8
0.8
0.4
0.4
vu*
0.0
0
-0–0.4.4-0–0.8.8
Conventional SVPWM-1–1.2.2
0
60 120 180 240 300 360
00.0033333
0.0066667
0.01
0.0133333
0.0166667
0.02

V3 (0 1 0)

V0 (0 0 0)
t0
V0
Ts

V*

q
t1
V1
Ts

Modulation
wave [p.u.]

t3
V3
Ts

a
V1 (1 0 0)

(a)

su

t

sv

t

sw

t

–iw
iu

iDC.in

iv

iu

0

V3

V0

V1
Ts

iDC.in.ave
V0

V3

t

(b)
Fig. 7. Optimized combination of voltage space vectors for minimum RMS
value of inverter input current when iu and iv are positive and iw is negative at
low-modulation indices (a) combination of voltage space vectors and(b) instantaneous waveform of inverter input current.

B. At Low Modulation IndicesFig. 7 shows an optimized combination of the voltage space
vectors to minimize the RMS value of the inverter input
current at low-modulation indices, and the region when thephase currents iu and iv are positive and iw is negative. As
shown in Fig. 7(a), one active vector (V1), one non-adjacentactive vector (V3), and one zero vector (V0) are used togenerate the voltage reference vector [13], [22]. When the tipof the voltage reference vector belongs to the triangle formedby the tips of these three voltage space vectors (V1, V3, andV0), i.e. at low-modulation indices, the use of the zero vector
at each control period is unavoidable. However, the effect of
the zero current on the fluctuation of the inverter input current
around the average value is low at low-modulation indicesbecause the difference between the zero current and the DClink average current is small. On the other hand, the maximum
possible value of the inverter input current, –iw in Fig. 7(b),causes the largest difference between the instantaneous valueof the inverter input current and the average value, and should
thus be avoided. Therefore, the voltage space vector V2 that
results in the maximum instantaneous value of the inverter
input current when iu and iv are positive and iw is negative, isavoided, and V3 is alternatively selected for the minimum
RMS value of the inverter input current at low-modulation
indices.

Normalized magnitude [p.u.]b

Proposed SVPWM

0.6

0.5
0.4
Conventional SVPWM

0.3
0.2
0.1

0

31

92 15
3 21
4 27
5 33
6 39
7 45
8 51
9

2πft [deg.]Harmonic order

(a)

(b)

Fig. 8. u-phase modulation waveforms and its harmonic contents at
cos φ = 0.866, and m = 0.705 (a) modulation waveforms and (b) triplen
harmonic spectrum.

The selection of switching states in the proposed SVPWM
switches from that shown in Fig. 6 to Fig. 7 by using themodulation index and the phase angle of the voltage
references. First, due to that the loading condition is unknown,
the loading condition is assumed to be high-modulation
indices, i.e. the switching states shown in Fig. 6. Then, the onduties (t1, t2, and t3) of three consecutive active vectors, which
are selected at high-modulation indices, are calculated. Next,
following conditional expressions are calculated based onthese on-duties:
0  t1 , t2 , t3  Ts . If these conditional expressions are satisfied, three selectedconsecutive active vectors are directly used as shown in Fig. 6,
i.e. the high-modulation indices. In contrast, if these
conditional expressions are not satisfied, it means that thevoltage reference vector cannot be generated by synthesizing
three selected consecutive active vectors. Therefore, the onduties of two non-adjacent active vectors and one zero vector,
which are selected at low-modulation indices, are calculated
and these voltage space vectors are used as shown in Fig. 7.
In terms of the number of switching transitions, it can beobserved from Fig. 5 that the number of switching transitionsin the conventional SVPWM is 6 per control period. On theother hand, Figs. 6 and 7 confirm that the number of switchingtransitions in the proposed SVPWM is 4 per control period.
Therefore, the application of the proposed SVPWM leads to ahigher inverter efficiency than that of the conventional
SVPWM because one leg is clamped during each control
period.
C. Modulation Waveform of Proposed SVPWM
Fig. 8 shows the u-phase modulation waveforms and its
harmonic contents. It is obvious that the modulation waveformof the proposed SVPWM has a larger triplen harmonics thanthose of the conventional SVPWM, because of the choice ofswitching states shown in Figs. 6 and 7. These increased
triplen harmonics of the modulation waveform generate thelarger baseband harmonics, the first carrier sidebands, in theline-to-line voltage of the PWM inverter [23].

TABLE I
SECTOR DEFINITIONS OF PROPOSED SVPWM

V*
vb* .error*

Verror v1b   td Ts v3b   td Ts 

A
B
C
D
E
F

*

va .error

 v1a   td Ts 

Vdead

Current polarity(P: Positive, N: Negative)
iu
iv
iw
P
N
N
P
P
N
N
P
N
N
P
P
N
N
P
P
N
P

Sectorv3a   td Ts 

b
V3

II

t3
V
Ts 3

V
Vdead
t3 – td
V3
q
t1
Ts
V
Ts 1
t0 + 2td
V0 t0
t
–
t
1
d
Ts
V1
V
Ts
Ts 0

b V2

V3

*

III

A

V1

Fig. 9. Dead-time error voltage vector in proposed SVPWM when iu and iv
are positive and iw is negative, at low-modulation indices.

V4

D

V7

V0

V5

IV. ADAPTATION TO WIDE LOAD POWER FACTOR RANGE
It should be noted that the reduction effect on the RMS
value of the inverter input current through the use of these
combinations of the voltage space vectors is dependent on theload power factor because the instantaneous value of theinverter input current is dependent on the output phasecurrents. Therefore, it is necessary to deal with the variation of
the load power factor to reduce the inverter input current
harmonics over a wide power factor range, which is a typicalrequirement of the motor drive system.
Table I lists the sector definitions of the proposed SVPWM.
These sectors (A–F) are determined by the combination of theoutput phase current polarities. With these sectors, theconditions of the output phase currents can be recognized [22].
Fig. 10 shows the layout of the proposed sectors in the abreference frame at a unity load power factor. When iu and iv

= 0°
a

V1
F

E

IV

V6
V

D. Dead-time Error Compensation
Fig. 9 shows the dead-time error voltage vector in the
proposed SVPWM at low-modulation indices, and the region
when the phase currents iu and iv are positive and iw is negative.
In fact, the on-duties of each selected voltage space vectors
contain duty cycle errors due to the dead-time td. With thisduty cycle errors, the a-component (v*a.error) and b-component(v*b.error) of the dead-time error voltage vector V*error can becalculated as shown in Fig. 9 [24]. In the proposed SVPWM,
the dead-time error voltage is compensated with feedforward
compensation by subtracting v*a.error and v*b.error from the acomponent (v*a) and b-component (v*b) of the voltage
reference vector, respectively. Note that the v*a.error and v*b.error
are dependent only on the dead-time and the sector (A–F) due
to the fact that the current polarities are unchanged during
each sectors. Only twelve patterns of the calculation for thedead-time error voltage are necessary in advance.

I

B

C

a

Optimized vector
patterns

VI
I ~ VI : Conventional sector
A~F : Proposed sector

Fig. 10. Layout of proposed sectors in ab reference frame at unity load
power factor (φ = 0°).

are positive and iw is negative, i.e. at sector B, the inverter
input current harmonics can be minimized with optimized
combinations of the voltage space vectors V1-V2-V3 or V1-V3V0, as shown in Figs. 6 and 7, respectively. Fig. 10 shows thatthe entire region of sector B is available with these optimized
combinations of the voltage space vectors with a unity load
power factor. Thus, optimized combinations of the voltage
space vectors for reduction of the inverter input current
harmonics are applied over the entire phase angle region forthe case |φ| < 30°, i.e. with a high-load power factor.
Fig. 11 shows waveforms of the output phase currents at aload power factor of 0.643 (φ = 50°), i.e. driving mode. Whenthe load power factor is varied, the proposed sectors shiftaccording to the phase shift of the output phase currents. As aresult, the polarity of iv at the timing of the phase angle θdiffers compared with that when the load power factor is unity,
as shown in Fig. 2. This leads to an increase of the inverter
input current harmonics, even with the same optimized
combinations of the voltage space vectors for a unity load
power factor.
Fig. 12 shows the layout of the proposed sectors in the abreference frame at a load power factor of 0.643 (φ = 50°), i.e.
driving mode. According to the variation of the load power
factor, the proposed sectors are rotated by the phase shift angle,
φ. As shown by the mesh area in Fig. 12, a part of sector B is
not available with the optimized combinations of the voltage
space vectors (V1-V2-V3 or V1-V3-V0) for sector B in the caseof 30° < |φ| < 90°, i.e. at a low-load power factor in driving
mode. In these areas, new combinations of the voltage space
vectors such as three consecutive voltage space vectors or two
non-adjacent voltage space vectors with one zero vector, do
not reduce the inverter input current harmonics but rather

Conventional sector
IV
III
II
I
vu*
vv*

Conventional sector
IV
III
II
I
vu*
vv*

VI

V
vw*

0

VI

V
vw*

0
F

Proposed sector
C
B
A
iu

F

E

D
iv

F

iw

0

iw

Proposed sector
C
B
A
iu

iv

120°

180°

360°

E

D

D

0

q
0°

60°

120°

180°

240°

300°

360°

q

0°

60°

240°

300°

Fig. 11. Waveforms of output phase currents at load power factor of 0.643(φ = 50°), i.e. driving mode.

Fig. 13. Waveforms of output phase currents at load power factor of –1.0
(φ = 180°), i.e. regenerative braking mode.

II

II

V3
III

B
C

V4

Conventional SVPWM
Optimized vector
patterns

b V2

V7

V0

D

F

E

IV
V5

V1

V4

increase it. Hence, the conventional SVPWM is applied inthese areas and the optimized combinations of the voltage
space vectors are applied in other areas, which results in aminimum inverter input current harmonics, even when theload power factor is varied.
Fig. 13 shows the waveforms of the output phase currents
at a load power factor of –1.0 (φ = 180°), i.e. regenerative
braking mode. When the load power factor is –1.0, thepolarities of all phase currents at the phase angle of θ reverse;
however, the absolute values are the same as those when theload power factor is unity, as shown in Fig. 2. This leads to thesame reduction effect on the inverter input current harmonics,
even with the same optimized combinations of the voltage
space vectors for a unity load power factor. Thus, the inverter
input current harmonics can be minimized in regenerative
braking mode as well as in driving mode.
Fig. 14 shows the layout of the proposed sectors in the abreference frame at a load power factor of –1.0 (φ = 180°), i.e.
regenerative braking mode. Even though the proposed sectors
are rotated by 180° according to φ, reduction of the inverter
input current harmonics is possible. Note that the area ofsector B is no longer available with the optimized
combinations of the voltage space vectors (V1-V2-V3 or V1V3-V0) for sector B. Alternatively, the optimized combinationsof the voltage space vectors (V1-V2-V3 or V1-V3-V0) for sector
B are effective in terms of reducing the inverter input current
harmonics for sector E, which is an opposite side sector of

I

E

F
A

V7

V0

= 180°

V1
C

B

IV
V5

I ~ VI : Conventional sector
A~F : Proposed sector

Fig. 12. Layout of proposed sectors in ab reference frame at load power
factor of 0.643 (φ = 50°).

Optimized vector
patterns

D

a

VI
V6

V

III

I = 50°

A

b V2

V3

V6
V

a

VI
I ~ VI : Conventional sector
A~F : Proposed sector

Fig. 14. Layout of proposed sectors in ab reference frame at load power
factor of –1.0 (φ = 180°).
TABLE II
SELECTED VOLTAGE SPACE VECTORS FOR MINIMUM INVERTER INPUTCURRENT HARMONICS

I
II
III
Sector of
conventional
SVPWM
IV
V
VI

Sector of proposed SVPWM
A
B
C
D
E
F
V6-V1-V2 V1-V2-V3
V -V -V V -V -V
V0-V1-V2- 6 1 2 1 2 3 V0-V1-V2or
or
or
or
V7
V7
V6-V7-V2 V1-V0-V3
V6-V7-V2 V1-V0-V3
V
V
1-V2-V3 V2-V3-V4
1-V2-V3 V2-V3-V4
V0-V3-V2V0-V3-V2or
or
or
or
V7
V7
V1-V0-V3 V2-V7-V4
V1-V0-V3 V2-V7-V4
V3-V4-V5
V -V -V V -V -V
V -V -V
V0-V3-V4- 2 3 4 3 4 5 V0-V3-V4- 2 3 4
or
or
or
or
V
V
7
7
V3-V0-V5
V2-V7-V4 V3-V0-V5
V2-V7-V4
V3-V4-V5 V4-V5-V6
V -V -V V -V -V
V0-V5-V4- 3 4 5 4 5 6 V0-V5-V4or
or
or
or
V
V7
7
V3-V0-V5 V4-V7-V6
V3-V0-V5 V4-V7-V6
V
V
4-V5-V6 V5-V6-V1
4-V5-V6 V5-V6-V1
V0-V5-V6V0-V5-V6or
or
or
or
V7
V7
V4-V7-V6 V5-V0-V1
V4-V7-V6 V5-V0-V1
V6-V1-V2
V -V -V V -V -V
V -V -V
V0-V1-V6- 5 6 1 6 1 2 V0-V1-V6- 5 6 1
or
or
or
or
V
V
7
7
V6-V7-V2
V5-V0-V1 V6-V7-V2
V5-V0-V1

sector B in regenerative breaking mode. Thus, the optimized
voltage space vectors in regenerative braking mode areopposite to those in driving mode.
Table II lists the selected voltage space vectors to minimize
the inverter input current harmonics for each combination of
the conventional sector and proposed sector. The
combinations of voltage space vectors in the white-coloredcells represent the optimized combinations of the voltage
space vectors to minimize the inverter input current harmonics
in driving mode. On the other hand, the voltage space vectors= 0° (cos = 1)

0.40
0.30

= 90° (cos = 0)
0.20

every 15°

0.10

0.00
0.0

0.2

0.4

0.6

0.8

1.0

1.2

DC-linkDC-link current
current ripple I DC.in(p.u.)
DC.in(p.u.) [p.u.]

DC-linkDC-link current
current ripple I DC.in(p.u.)
DC.in(p.u.) [p.u.]

0.50

0.50
0.40

= 0° (cos = 1)

0.30

0.20

= 90° (cos = 0)

0.10

every 15°

0.00
0.0

0.2

0.4

Modulationindex mm [-][-]Modulation index
(a)

0.6

0.8

1.0

1.2

Modulation index
Modulationindex m [-]
[-]
(b)

0.50

= 180° (cos = –1)

0.40
0.30

= 90° (cos = 0)
0.20

every 15°

0.10
0.00
0.0

0.2

0.4
0.6
0.8
Modulation index
index mm[-]
Modulation
[-]

1.0

1.2

(a)

DC-linkDC-linkcurrent
current ripple
ripple IIDC.in(p.u.)[p.u.]
DC.in(p.u.) [p.u.]

DC-linkDC-linkcurrent
currentripple
rippleIIDC.in(p.u.)[p.u.]
DC.in(p.u.) [p.u.]

Fig. 15. Analytical results for inverter input current harmonics in driving mode (a) with conventional SVPWM and (b) proposed SVPWM.
0.50

0.40

= 180° (cos = –1)

0.30
0.20

= 90° (cos = 0)

0.10

every 15°

0.00
0.0

0.2

0.4

0.6

0.8

1.0

1.2

Modulation index
Modulationindex m [-][-](b)

Fig. 16. Analytical results for inverter input current harmonics in regenerative braking mode (a) with conventional SVPWM and (b) proposed SVPWM.

in the light-gray-colored cells represent the optimized
combinations in terms of reducing the inverter input current
harmonics in regenerative breaking mode. Furthermore, thecombinations of the voltage space vectors in conventional
SVPWM are listed in the gray-colored cells, i.e. the region
where the inverter input current harmonics cannot be reducedwith the proposed combinations of the voltage space vectors.
Note that in the proposed SVPWM, the load power factor isindirectly detected only by the polarities of the output phasecurrents and the definition of the proposed sectors. Therefore,
the optimized combinations of voltage space vectors tominimize the inverter input current harmonics under any
conditions of the load power factor can be simply employed.

fundamental component of the inverter input current
harmonics is 50 Hz at the rated load. The harmoniccomponents of the inverter input current up to the 20th-order ofthe switching frequency are considered in this evaluation.
Fig. 15 shows the analytical results of the inverter input
current harmonics at load power factor from 0.0 to 1.0, i.e.
driving mode. When the conventional SVPWM is applied, themaximum value of IDC.in(p.u.) is 0.450 p.u. at unity load power
factor and a modulation index of 0.6. On the other hand, when
the optimized combinations of the voltage space vectors for
reduction of the inverter input current harmonics are applied,the value of IDC.in(p.u.) at this point can be reduced by 36.7%.
Furthermore, it is confirmed that the inverter input current
harmonics is reduced under any conditions of the load power
V. ANALYTICAL EVALUATIONS
factor and modulation index. A higher load power factor
The proposed SVPWM was simulated to evaluate the enables a greater reduction effect on the inverter input current
reduction effect on the inverter input current harmonics and harmonics to be obtained. This is because the applied ratio ofcompared with conventional SVPWM. In this paper, the the optimized combinations of voltage space vectors becomesinverter input current harmonics is evaluated as the ratio higher as the load power factor becomes higher.
Fig. 16 shows analytical results for the inverter input
between the RMS value of the inverter input current iDC.in.RMS,
current
harmonics at load power factors from –1.0 to 0.0, i.e.
and the maximum value of the output phase current Im:
regenerative braking mode. When the load power factor is
negative, i.e. regenerative braking mode, the average value of2
 1

iDC .in .RMS
1
the inverter input current is negative. However, if the
I DC .in ( p.u.)   iDC.in.k  ,   modulation index and the absolute values of the load powerIm
I m k 1  2factor are equal, then the inverter input current harmonics
where k is the harmonic order and iDC.in.k is the k-order remains unchanged, irrespective of the polarity of the load
component of the inverter input current harmonics. The power factor, due to the same utilization of the voltage space

Conventional sector
I

VI
IV V
II III

Proposed sectorA

vuv [500V/div.]

B

C

D

E

F

vuv [500V/div.]00iDC.in [20A/div.]

iDC.in [20A/div.]00iu [20A/div.]

iu [20A/div.]00[10 ms/div.][10 ms/div.]

(a)

(b)

Fig. 17. Experimental waveforms at cos φ = 0.866 (φ = 30°), m = 0.705, i.e. driving mode with high load power factor; sector, output line-to-line voltage,
inverter input current and u-phase output current (a) with conventional SVPWM and (b) proposed SVPWM.
100
IDC.in(p.u.) = 0.424 [p.u.]

100

24.4 %

IDC.in(p.u.) = 0.299 [p.u.]

10
Input current [%]Input current [%]

10
1

0.1

1

0.1
0.01

0.01
0.001
10

7.47 %

100

1000
10000
Frequency [Hz]100000

(a)

0.001
10

100

1000
10000
Frequency [Hz]100000(b)

Fig. 18. Harmonic components of inverter input current at cos φ = 0.866 (φ = 30°), m = 0.705, i.e. driving mode with high load power factor (under same
conditions as in Fig. 17) (a) with conventional SVPWM and (b) proposed SVPWM.

vectors and same absolute value of the output phase current.
Thus, the characteristics of the inverter input current
harmonics in regenerative braking mode, as shown in Fig. 16,
are similar to those in driving mode shown in Fig. 15. Thus,
the inverter input current harmonics is solely dependent on themodulation index m, and the absolute value of the load power
factor, |cos φ|.
VI. EXPERIMENTAL RESULTS
The effectiveness of the proposed SVPWM was verified
experimentally. In the experiment, a three-phase induction
motor (MVK8115A-R, Fuji Electric Co., Ltd.) with a rated
power of 3.7 kW was used as the test motor. The test motor
was driven by V/f control with the conventional and proposed
SVPWM, which were implemented into an evaluation board(TMS320C6713, Texas Instruments). The load power factor
was varied by controlling the torque reference of the load
motor.
A. Input Current Harmonics
Fig. 17 shows the operating waveforms of the VSI with theconventional and proposed SVPWM at a load power factor of
0.866 (φ = 30°), i.e. driving mode with a high load power
factor, and a modulation index of 0.705. When the load power
factor is high, the applied ratio of the proposed SVPWM isalso high. In particular, the proposed SVPWM is applied at all
times with a load power factor of 0.866 (φ = 30°). The resultsin Fig. 17 confirm that the width of the step change in the
inverter input current is reduced by application of the
proposed SVPWM. On the other hand, the output phasecurrent with the proposed SVPWM seems to be slightly
distorted than that with the conventional SVPWM.
Furthermore, the transitions between +Edc to –Edc occur in theline-to-line voltage with the proposed SVPWM. This isbecause three voltage space vectors, which are not the closest
to the voltage reference vector, are used to minimize theinverter input current harmonics in the proposed SVPWM.
Note that the averaged line-to-line voltages are sinusoidal
waveforms even though such transitions occur. The transition
between +Edc to –Edc in the line-to-line voltage leads to theincrease of the switching frequency harmonics in the inverter
output voltage, which might cause the motor insulation
breakdown due to the increase of the motor surge voltage. The
effect of the voltage harmonics on the output phase current
distortion is considered in a next sub-section.
Fig. 18 shows the harmonic components of the inverter
input current under the same conditions as in Fig. 17. The
maximum value of the vertical axis (100%) indicates the
maximum value of the output phase current. When theconventional SVPWM is applied, the inverter input current

Conventional sector
I

VI
IV V
II III

Proposed sectorA

vuv [500V/div.]

B

C

D

E

F

vuv [500V/div.]00iDC.in [20A/div.]

iDC.in [20A/div.]00iu [20A/div.]

iu [20A/div.]00[10 ms/div.][10 ms/div.]

(a)

(b)

Fig. 19. Experimental waveforms at cos φ = 0.707 (φ = 45°), m = 0.705, i.e. driving mode with low load power factor; sector, output line-to-line voltage,
inverter input current and u-phase output current (a) with conventional SVPWM and (b) proposed SVPWM.
100
IDC.in(p.u.) = 0.424 [p.u.]

100

24.4 %

IDC.in(p.u.) = 0.299 [p.u.]

10
Input current [%]Input current [%]

10
1

0.1

1

0.1
0.01

0.01
0.001
10

7.47 %

100

1000
10000
Frequency [Hz]100000

(a)

0.001
10

100

1000
10000
Frequency [Hz]100000(b)

Fig. 20. Harmonic components of inverter input current at cos φ = 0.707 (φ = 45°), m = 0.705, i.e. driving mode with low load power factor (under same
conditions as in Fig. 19) (a) with conventional SVPWM and (b) proposed SVPWM.

includes high integer multiples of the switching frequency, themaximum value of which is 24.4%. Application of the
proposed SVPWM reduced the switching frequency
component by 7.47%. Furthermore, the inverter input current
harmonics IDC.in(p.u.), was significantly reduced by 0.299 p.u.
when the proposed SVPWM was applied. On the other hand,
there are higher low-order harmonics of the inverter input
current than those with the conventional SVPWM. This isbecause the distortions of the output phase current with theproposed SVPWM, which can be observed from Fig. 17, also
appear in the inverter input current due to the fact that theinverter input current is the superposition summation of theswitched current pulses from each phase leg, expressed as (5).
However, even though the application of the proposed
SVPWM worsened the low-order harmonics of the inverter
input current, the values of those are less than 1% of the rated
value. Therefore, the worse low-order harmonics of theinverter input current with the proposed SVPWM are notproblem.
Fig. 19 shows the operating waveforms of the VSI with theconventional and proposed SVPWM at a load power factor of
0.707 (φ = 45°), i.e. driving mode with a low load power
factor, and a modulation index of 0.705. When the load poweris low, both the conventional SVPWM and proposed SVPWM
are applied. In particular, the proposed SVPWM is applied

within only three-quarters of the entire phase angle region,
whereas the conventional SVPWM is applied in the otherregion at a load power factor of 0.707 (φ = 45°). Fig. 19
confirms that the step change in the inverter input current ispartially reduced when the proposed SVPWM is applied.
Fig. 20 shows the harmonic components of the inverter
input current under the same conditions as in Fig. 19. Whenthe conventional SVPWM is applied under this low load
power factor condition, the twice switching frequency
component of the inverter input current harmonics becomes a
maximum, the value of which is 22.4%. This value is reducedby 10.6% when the proposed SVPWM is applied. These
results demonstrate that the proposed SVPWM is effective interms of reducing the inverter input current harmonics, evenwhen the load power factor is low.
Fig. 21 shows the measured inverter input current
harmonics in driving mode. The inverter input current
harmonics can be reduced under any load power factor andmodulation index conditions in driving mode. It is also
confirmed that as the load power factor becomes higher, theinverter input current harmonics-reduction effect of the
proposed SVPWM increases.

IIDC.in(p.u.)[p.u.]
DC.in(p.u.) [p.u.]

0.40

0.50

cos φ = 0.866(φ = 30 deg.)Lines : Sim. results
Plots : Exp. results

0.30

cos φ = 0.259(φ = 75 deg.)

0.20

cos φ = 0.707(φ = 45 deg.)

0.10

cos φ = 0.866(φ = 30 deg.)Lines : Sim. results
Plots : Exp. results

0.40[p.u.]
IIDC.in(p.u.)
DC.in(p.u.) [p.u.]

0.50

0.30
0.20

cos φ = 0.259(φ = 75 deg.)cos φ = 0.707(φ = 45 deg.)

0.10
0.00

0.00
0.0

0.2

0.4
0.6
0.8
Modulation
Modulationindex
indexmm[-]
[-]
(a)

1.0

0.0

1.2

0.2

0.4
0.6
0.8
Modulationindex
indexmm[-][-]
Modulation

1.0

1.2

(b)

Fig. 21. Measured inverter input current harmonics in driving mode (a) with conventional SVPWM and (b) proposed SVPWM.
Conventional sector
I

III

II

IV

V

VI

Proposed sector
A

B

C

D

E

F

vuv [500V/div.]

vuv [500V/div.]00iDC.in [50A/div.]

iDC.in [50A/div.]00iu [50A/div.]

iu [50A/div.]00[10 ms/div.][10 ms/div.]

(a)

(b)

Fig. 22. Experimental waveforms at cos φ = –0.588 (φ = 126°), m = 0.481, i.e. regenerative braking mode; sector, output line-to-line voltage, inverter input
current and u-phase output current (a) with conventional SVPWM and (b) proposed SVPWM.
100.000
100

IDC.in(p.u.) = 0.335 [p.u.]

100.000100

25.8 %

IDC.in(p.u.) = 0.293 [p.u.]

1.0001

0.1
0.100
0.010
0.01
0.001
0.001
10

10.7 %

10
10.000

Input current [%]Input current [%]1010.0001.0001

0.1
0.100
0.010
0.01

100

1000
10000
Frequency [Hz]100000

(a)

0.001
0.001
10

100

1000
10000
Frequency [Hz]100000(b)

Fig. 23. Harmonic components of inverter input current at cos φ = –0.588 (φ = 126°), m = 0.481, i.e. regenerative braking mode (under same conditions as inFig. 22) (a) with conventional SVPWM and (b) proposed SVPWM.

Fig. 22 shows the operating waveforms of the VSI with theconventional and proposed SVPWM at a load power factor of–0.588 (φ = 126°), i.e. regenerative braking mode, and a
modulation index of 0.481. Even in regenerative braking mode,the proposed SVPWM is also effective in terms of reducing
the width of the step change in the inverter input current,
which results in a reduction of the inverter input current
harmonics.
Fig. 23 shows the harmonic components of the inverter

input current under the same conditions as in Fig. 22. Whenthe conventional SVPWM is applied, the maximum value ofthe switching frequency component of the inverter input
current harmonics is 25.8% and the inverter input current
harmonics is 0.335 p.u. Fig. 23 confirms that the switchingfrequency component can be reduced by 10.7% and theinverter input current harmonics can be reduced by 0.293 p.u.
by application of the proposed SVPWM, even in regenerative
braking mode. The experimental results in Figs. 17–23

10.0

THD
ofiiuu[%]T HDof[%]8.0

Output line to line voltage [%]cos φ = 0.866(φ = 30 deg.)
Proposed SVPWM

6.0
4.0
2.0
Conventional SVPWM

0.0
0.0

0.2

0.4
0.6
0.8
Modulation index
Modulationindex m [-]
[-]

1.0

1.2

100
6.85 %

10
1

0.1
0.01
0.001

10

100

Fig. 24. Measured total harmonic distortion of output phase current iu atcos φ = 0.866.

1000
10000
Frequency [Hz](a)B. Output Phase Current Harmonics
Fig. 24 shows the total harmonic distortion (THD) of the uphase output phase current at a load power factor of 0.866.
Harmonic components of not switching frequency components
but up to the 40th-order of the fundamental frequency
components are considered in this evaluation. Note that thedead-time error voltage, which is compensated both in theconventional and proposed SVPWM, is estimated from theduty cycle errors due to the dead-time in each sector as shownin Fig. 9. It is shown that the THD of the output phase current
obtained with the proposed SVPWM is slightly higher thanthat obtained with the conventional SVPWM except for the
low value of a modulation index. The increase in THD of theoutput phase current with the proposed SVPWM is caused by
the large triplen harmonics of the proposed modulation
waveform as shown in Fig. 8 and the current detection error
around zero-current-crossing points. In the proposed SVPWM,
the detection values of the current polarities are required inorder to determine the sectors (A–F) according to Table I.
Therefore, the current detection error causes an incorrect
selection of the voltage space vectors, and increases the THDof the output phase current, especially around the output phasecurrent zero-crossings. One of the drawbacks of this strategy
is the worse output phase current THD which is influenced
due to the current polarity detection, which might cause anincrease of the iron loss in the load motor.
Fig. 25 shows the simulation results of the harmoniccomponents of the output line-to-line voltage at a load power
factor of 0.866 and a modulation index of 0.705. In thissimulation, the dead-time is not applied in order to neglect the
influence of the dead-time-induced voltage error. The
application of the proposed SVPWM worsens the switchingfrequency harmonic component from 6.85% of the rated
voltage (188 V) to 24.3%. Consequently, the increase in theswitching frequency component of the line-to-line voltage
induces the increase in the same frequency component of theoutput phase current from 0.360% of the rated current (18 A)

Output line to line voltage [%]100

confirm that the proposed SVPWM is effective in terms of
reducing the inverter input current harmonics for a motor drive
system, which has a considerably wide variation of the load
power factor.

10000024.3 %

10
1

0.1
0.01
0.001

10

100

1000
10000
Frequency [Hz]100000(b)
Fig. 25. Simulation results of harmonic components of output line-to-line
voltage at cos φ = 0.866, m = 0.705 (a) with conventional SVPWM and (b)proposed SVPWM. 100% of the vertical axis indicates the rated voltage of thetest motor (188V). The fundamental frequency is set to 50 Hz, and theswitching frequency is set to 10 kHz, respectively.

to 1.28% with the consideration of the switching frequency of
10 kHz, and 1.58 mH leakage inductance per one phase of thetest induction motor. Finally, the measured THD of output
phase current with the proposed SVPWM at a load power
factor of 0.866 and a modulation index of 0.705, the value of
which is 3.39% shown in Fig. 24, increases by only 0.234
points (= 3.62% – 3.39%) even though the increase ofswitching frequency component of the output phase current is
considered. It can be concluded that the increase in theswitching frequency harmonics in the line-to-line voltage withthe proposed SVPWM has a small influence on the distortionin the output phase current.
C. Inverter Efficiency
Fig. 26 shows the inverter efficiency between conventional
SVPWM and proposed SVPWM at the load power factor of
0.866. The inverter efficiency was measured using Yokogawa
WT1800 power analyzer. The application of the proposed
SVPWM leads to a higher inverter efficiency compared to thatwith the conventional SVPWM due to its less number ofswitching transitions, which is reduced to two-thirds comparedwith the conventional SVPWM.

Inverter efficiency
efficiency [%][%]Inverter

100.0

TABLE IIIFREQUENCY COEFFICIENT OF RATED RIPPLE CURRENT FLOWING THROUGH
ALUMINUM ELECTROLYTIC CAPACITORS

Proposed SVPWM

cos φ = 0.866(φ = 30 deg.)

95.0
Conventional SVPWM

90.0

Frequency [Hz]

50

60

120

360

1 k 10 k or more

Coefficient Kf

0.80

0.82

1.00

1.20

1.35

1.40

85.0
100
IDC.in.freq(p.u.) = 0.303 [p.u.]

80.0
0.2

0.4
0.6
0.8
Modulation index
Modulationindex m
m [-]
[-]

1.0

1.2

Input current/Kf [%]0.0

Fig. 26. Inverter efficiency comparison between conventional SVPWM andproposed SVPWM against different modulation index at cos φ = 0.866.

VII.

CAPACITOR LIFETIME COMPARISON

1

0.1
0.01
0.001
10

The expected lifetime (Ln) of the electrolytic capacitors is
calculated as the multiplication of the lifetime (Lo) at
maximum operating temperature of the capacitor at rated
ripple current and rated voltage, which is specified ondatasheet, by three acceleration rates which are dependent on
the ambient temperature (FT), the ripple current (FI), and theapplied voltage (FV) [10]. In order to compare the lifetime
expectancy of the electrolytic capacitors which is influenced
by only the ripple current, the following assumption isconducted:1) the ambient temperature is constant at the maximum
operating temperature of the capacitor (FT = 1), and2) the applied voltage (Edc) is constant and below the
rated voltage (FV = 1).
Therefore, the expected lifetime of the electrolytic capacitors
can be calculated as follows:

17.4 %

10

100

1000
10000
Frequency [Hz]100000(a)100
Input current/Kf [%]IDC.in.freq(p.u.) = 0.215 [p.u.]

10

5.34 %

1

0.1
0.01
0.001
10

100

1000
10000
Frequency [Hz]100000(b)Ln  Lo  FI ,  Fig. 27. Harmonic components of inverter input current considering

where the Lo is 5000 hours in case of aluminum electrolytic
capacitors (NX series, nichicon [25]), which is used as thesmoothing capacitor in the prototype.
Table III lists the frequency coefficient of rated ripple
current flowing through aluminum electrolytic capacitors [25].
The lifetime of the electrolytic capacitors decreases because of
the heat generated inside electrolyte due to power loss whenripple current flows through ESR of the electrolytic capacitors.
Meanwhile, ESR of the electrolytic capacitors varies
dependently on the current frequency. It is possible tocalculate the normalized inverter input current harmonics(IDC.in.freq(p.u.)) considering the frequency dependence of the
ESR of aluminum electrolytic capacitor by dividing theinverter input current harmonic components by the frequency
coefficient (Kf) as follows:

I DC .in. freq (p.u.) 

1
Im

2

 1 iDC .in.k 


 .

 2 Kf 
k 1 frequency dependence of ESR of aluminum electrolytic capacitor at cos φ =0.866, m = 0.705 (under same conditions as in Fig. 17) (a) with conventional
SVPWM and (b) proposed SVPWM.

Fig. 27 shows the harmonic components of the inverter
input current considering the frequency dependence of the
ESR of aluminum electrolytic capacitor at a load power factorof 0.866 and a modulation index of 0.705 (under the same
conditions as in Fig. 17). The application of the proposed
SVPWM reduces the inverter input current harmonics
IDC.in.freq(p.u.) by 29.0% when the frequency dependence of the
ESR of aluminum electrolytic capacitor is considered.
Assuming that the motor is mostly operated at the load power
factor of 0.866 and the modulation index of 0.705, and thealuminum electrolytic capacitors in the conventional SVPWM
is designed at the worst case of the rated ripple current (i.e., FIas 1), the lifetime expectancy of the electrolytic capacitor canbe given by

Ln _ conv.SVPWM  L0 1  5 000 h. On the other hand, the application of the proposed SVPWM
raises FI to 1.41 due to a current harmonic reduction of 29.0%.
Therefore, the lifetime expectancy of the electrolytic capacitor
with the proposed SVPWM can be given by

Ln _ prop.SVPWM  L0 1.41  7 050 h. Note that the above lifetime calculation is just an example.
However, it can be concluded that the application of the
proposed SVPWM might extend the lifetime of theelectrolytic capacitor about 1.41 times longer at most than thatof the conventional SVPWM.
VIII.

CONCLUSION

A novel SVPWM was proposed to reduce the inverter input
current harmonics of the three-phase VSI over a wide
variation of the load power factor. The inverter input current
harmonics was reduced by optimizing combinations of thevoltage space vectors to minimize the fluctuation of theinverter input current around the average value. This novel
strategy could adapt to a wide range of load power factor bychanging the optimized combinations of the voltage space
vectors according to the polarities of the output phase currents.
It was thus unnecessary to detect the load power factor. The
experimental results confirmed that application of the
proposed SVPWM reduced the RMS value of the inverter
input current by 29.0% at most with the consideration for thefrequency dependence of the ESR of aluminum electrolytic
capacitor. The 29.0% reduction of the RMS value of theinverter input current might lead to the 1.41 times lifetime
extension of the electrolytic capacitors. Moreover, it was
confirmed that the inverter input current harmonics was
reduced over the entire range of the load power factor, i.e. inboth driving mode and regenerative braking mode.
Consequently, the proposed SVPWM can be effectively used
for the reduction of the constant stress on the smoothing
capacitor caused by the inverter input current harmonics,
which strongly accelerates the entire lifetime of the motor
drive system. On the other hand, this strategy increases theload current THD compared with that obtained using theconventional SVPWM. In addition, the application of the
proposed SVPWM worsened the switching frequency
harmonics of the inverter output line-to-line voltage.
REFERENCES
[1]
[2]

[3]

[4]

K. Tobari, and Y. Iwaji, “Quick-Response Technique for Simplified
Position Sensorless Vector Control in Permanent Magnet Synchronous
Motors,” IEEJ Trans. Ind. Appl., Vol. 4, No. 5, pp. 582-588, 2015.
T. Nagano, and J. Itoh, “Parallel Connected Multiple Motor Drive
System Using Small Auxiliary Inverter for Permanent Magnet
Synchronous Motors,” IEEJ Trans. Ind. Appl., Vol. 4, No. 1, pp. 40-48,
2014.
K. Sun, Q. Wei, L. Huang, and K. Matsuse, “An Overmodulation
Method for PWM-Inverter-Fed IPMSM Drive With Single Current
Sensor,” IEEE Trans. Ind. Electron., Vol. 57, No. 10, pp. 3395-3404,
2010.
L. Malesani, L. Rossetto, P. Tenti, and P. Tomasin, “AC/DC/AC PWM
Converter With Reduced Energy Storage in the DC-link,” IEEE Trans.
Ind. Appl., Vol. 31, No. 2, pp. 287-292, 1995.

[5]

W.-J. Lee, and S.-K. Sul, “DC-link Voltage Stabilization for Reduced
DC-link Capacitor Inverter,” IEEE Trans. Ind. Appl., Vol. 50, No. 1, pp.
404-414, 2014.
[6] K. Abe, H. Haga, K. Ohishi, and Y. Yokokura, “Fine Current Harmonics
Reduction Method for Electrolytic Capacitor-Less and Inductor-Less
Inverter Based on Motor Torque Control and Fast Voltage Feedforward
Control for IPMSM,” IEEE Trans. Ind. Electron., Vol. 64, No. 2, pp.
1071-1080, 2017.
[7] M. A. Vogelsberger, T. Wiesinger, and H. Ertl, “Life-Cycle Monitoringand Voltage-Managing Unit for DC-link Electrolytic Capacitors in
PWM Converters in PWM Converters,” IEEE Trans. Power Electron.,Vol. 26, No. 2, pp. 493-503, 2011.
[8] M. H. Bierhoff, and F. W. Fuchs, “DC-link Harmonics of Three-Phase
Voltage-Source Converters Influenced by the Pulsewidth-Modulation
Strategy―An Analysis,” IEEE Trans. Ind. Electron., Vol. 55, No. 5, pp.
2085-2092, 2008.
[9] B. P. McGrath, and D. G. Holmes, “A General Analytical Method for
Calculating Inverter input current Harmonics,” IEEE Trans. Ind. Appl.,
Vol. 45, No. 5, pp. 1851-1859, 2009.
[10] Technical Notes on Aluminum Electrolytic Capacitors, Cat. 8101E-1,
nichicon Corp., Tokyo, available via http://www.nichiconus.com/english/products/pdf/aluminum.pdf[11] E. Ün, and A. M. Hava, “A Near State PWM Method With Reduced
Switching Frequency And Reduced Common Mode Voltage For ThreePhase Voltage Source Inverters,” in Proc. IEEE International Electric
Machines & Drives Conf., pp. 235-240, 2007.
[12] J. Hobraiche, J.-P. Vilain, P. Macret, and N. Patin, “A New PWMStrategy to Reduce the Inverter Input Current Ripples,” IEEE Trans.
Power Electron., Vol. 24, No. 1, pp. 172-180, 2009.
[13] T. D. Nguyen, N. Patin, and G. Friedrich, “Extended Double Carrier
PWM Strategy Dedicated to RMS Current Reduction in DC-link
Capacitors of Three-Phase Inverters,” IEEE Trans. Power Electron., Vol.
29, No. 1, pp. 396-406, 2014.
[14] H. W. Van Der Broeck, H.-C. Skudelny, and G. V. Stanke, “Analysis
and Realization of a Pulsewidth Modulator Based on Voltage Space
Vectors,” IEEE Trans. Ind. Appl., Vol. 24, No. 1, pp. 142-150, 1988.
[15] A. M. Hava, R. J. Kerkman, and T. A. Lipo, “A High-Performance
Generalized Discontinuous PWM Algorithm,” IEEE Trans. Ind. Appl.,
Vol. 34, No. 5, pp. 1059-1071, 1998.
[16] A. M. Hava, and E. Ün, “Performance Analysis of Reduced CommonMode Voltage PWM Methods and Comparison With Standard PWM
Methods for Three-Phase Voltage-Source Inverters,” IEEE. Trans.
Power Electron., Vol. 24, No. 1, pp. 241-252, 2009.
[17] D. Casadei, G. Serra, A. Tani, and L. Zarri, “Theoretical andExperimental Analysis for the RMS Current Ripple Minimization in
Induction Motor Drives Controlled by SVM Technique,” IEEE Trans.
Ind. Electron., Vol. 51, No. 5, pp. 1056-1065, 2004.
[18] A. Mehrizi-Sani, and S. Filizadeh, “An Optimized Space Vector
Modulation Sequence for Improved Harmonic Performance,” IEEE
Trans. Ind. Electron., Vol. 56, No. 8, pp. 2894-2903, 2009.
[19] K. Basu, J. S. Siva Prasad, G. Narayanan, H. K. Krishnamurthy, and R.
Ayyanar, “Reduction of Torque Ripple in Induction Motor Drives Using
an Advanced Hybrid PWM Technique,” IEEE Trans. Ind. Electron., Vol.
57, No. 6, pp. 2085-2091, 2010.
[20] J. Holtz, “Pulsewidth Modulation-a Survey,” IEEE Trans. Ind. Appl.,
Vol. 39, No. 5, pp. 410-420, 1992.
[21] T. Takeshita, “Output Voltage Harmonics Suppression of Matrix
Converters Using Instantaneous Effective Values,” in Conf. Proc. IEEE
Energy Conversion Congress and Exposition, 270_0839, 2010.
[22] K. Nishizawa, J. Itoh, A. Odaka, A. Toba, and H. Umida, “Reduction of
Input Current Harmonics based on Space Vector Modulation for ThreePhase VSI with varied Power Factor,” in Conf. Proc. IEEE Energy
Conversion Congress and Exposition, EC-0318, 2016.
[23] D. G. Holmes, and T. A. Lipo, Pulse Width Modulation for Power
Converters. New York: Wiley, 2003.
[24] S. Ahmed, Z. Shen, P. Mattavelli, D. Boroyevich, and K. J. Karimi,“Small-Signal Model of Voltage Source Inverter (VSI) and Voltage
Source Converter (VSC) Considering the DeadTime Effect and Space
Vector Modulation Types,” IEEE Trans. Power Electron., Vol. 32, No.
6, pp. 4145-4156, 2017.
[25] Datasheet of Aluminum Electrolytic Capacitors (NX series), Cat. 8100D,
nichicon
Corp.,
Tokyo,
availablevia
http://www.nichicon.co.jp/english/products/pdfs/e-nx.pdf.

Koroku Nishizawa (S’16) was born in Nagano,
Japan, in 1992. He received the B.S. degrees inelectrical, electronics and information engineering in2015 from Nagaoka University of Technology,
Niigata, Japan, where he is currently working toward
the Ph.D. degree.
His current research interest includes modulation
method of converters.
Mr. Nishizawa is a student member of theInstitute of Electrical Engineers of Japan.

Jun-ichi Itoh (M’04–SM’13) was born in Tokyo,
Japan, in 1972. He received his M.S. and Ph.D.
degree in electrical and electronic systems
engineering from Nagaoka University of Technology,
Niigata, Japan in 1996, 2000, respectively.
From 1996 to 2004, he was with Fuji Electric
Corporate Research and Development Ltd., Tokyo,
Japan. He was with Nagaoka University ofTechnology, Niigata, Japan as an associate professor.
Since 2017, he has been a professor. His researchinterests are matrix converters, dc/dc converters, power factor correction
techniques, energy storage system and adjustable speed drive systems.
Prof. Itoh received IEEJ Academic Promotion Award (IEEJ TechnicalDevelopment Award) in 2007. In addition, he also received Isao Takahashi
Power Electronics Award in IPEC-Sapporo 2010 from IEEJ, 58th OHM
Technology Award from The Foundation for Electrical Science andEngineering, November, 2011, Intelligent Cosmos Award from Intelligent
Cosmos Foundation for the Promotion of Science, May, 2012, and Third prize
award from Energy Conversion Congress and Exposition-Asia, June, 2013.
Prizes for Science and Technology (Development Category) from theCommendation for Science and Technology by the Minister of Education,
Culture, Sports, Science and Technology, April 2017.
Dr. Itoh is a senior member of the Institute of Electrical Engineers ofJapan, the Society of Automotive Engineers of Japan.

Akihiro Odaka (M’00) was born in Saitama, Japan,
in 1973. He received the B.S. and M.S. degrees from
Tokyo Denki University, Tokyo, Japan, in 1996 and1998, respectively.
Since 1998, he has been with Fuji Electric Co.,
Ltd., Tokyo. His interests are static converters andpower semiconductor application.
Mr. Odaka is a member of the Institute ofElectrical Engineers of Japan.

Akio Toba (M’94) received M.E. degree in 1994
and Ph.D. degree in 2006, both from Tokyo
Metropolitan University, Japan.
In 1994, he joined Fuji Electric Co., Ltd., Japan,
where he has been conducting research anddevelopment of power electronics, motor drives, andelectric machines. From 1997 to 1999, he was avisiting researcher of Wisconsin Electric Machines
and Power Electronics Consortium (WEMPEC) in
the University of Wisconsin, Madison, USA.
Dr. Toba is a senior member of the Institute of Electrical Engineers ofJapan.
Hidetoshi Umida (M’98) was born in Hiroshima,
Japan, in 1956. He received the B.E., M.E., and Ph.D.
degrees in electrical engineering from Tokyo
Institute of Technology, Tokyo, Japan, in 1970, 1981,
and 1984, respectively.
Since 1984, he has been with Fuji Electric Co.,
Ltd., Tokyo, Japan. His research interests are incontrol theory and its application to motor drives andconverters.
He is currently a Chief Engineer with Fuji’s
Corporate R&D Headquarters.
Dr. Umida is a fellow of the Institute of Electrical Engineers of Japan.