CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

40G QSFP+ LR4 10km
CAQS-SPO400-LR4C, Pull-Tab
Features♦

Transmission data rate up to 11.2Gbps per channel♦

QSFP+ MSA compliant♦

Compliant to IEEE 802.3ba specification for
40GBASE-LR4 links♦

4 CWDM un-cooled DFB lasers, using ITU G.694.2
wavelength grid at 1271, 1291, 1311, and 1331 nm ,with AAWG.

♦

High Sensitivity PIN-TIA with AAWG DEMUX.

♦

Up to 10km reach over standard single mode fiber♦

Compliant with QDR/DDR Infiniband data rates♦

Hot pluggable electrical interface♦

Power consumption＜2.5W♦

Operating case temperature 0°C to +70°C♦

3.3V power supply♦

RoHS 6 compliant（lead free）

Applications♦

40G Ethernet♦

Infiniband QDR and DDR interconnects♦

Client-side 40G Telecom connections

Description
The CAQS-SPO400-LR4C is a 4x10G hot pluggable optical transceiver. CA OPTRONICS GROUP
enables the integration of 4 transmitters, 4 receivers and an optical MUX/DeMUX with AAWG into asmall form factor package that delivers a 40 Gbps data link in a compact QSFP footprint. The opticalconnectivity is based on two SMF LC connectors, one for Tx and one for Rx. The Tx and Rx each consistof 4 10Gb/s CWDM channels, whose wavelengths are in the 1300nm range. The QSFP-LR transceiver isdesigned for applications based on the QSFP MSA, IEEE 802.3ba, and 40GBASE-LR4 requirements of
up to 10km reach.

Functional Block Diagram
CA OPTRONICS GROUP INC

Page 1 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

Figure 1: Functional Block Diagram

Absolute Maximum Ratings

CA OPTRONICS GROUP INC

Page 2 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

Parameter

Symbol

Min

Max

Unit

Supply Voltage

Vcc-Tx
Vcc-Rx
Vcc1

-0.5

3.6

V

Storage Temperature Range

TSTG

-40

+85

ºC

Maximum Average Input
OpticalPower per lane (Damage
Threshold)

PIN

3.4

Relative Humidity

RH

dBm
10％to 90％(non-condensing)Operating Conditions
Parameter

Symbol

Min

Max

Unit

Supply Voltage

Vcc-Tx
Vcc-Rx
Vcc1

3.1

3.5

V

Operating Case temperature

TCASE

0

70

ºC

Power Consumption

PDISS

3.5

W

SMF Link Length

LKM

10

km

Max

Units

3.5

Volts

Supply Current

1.0

Amps

Maximum Power Consumption

3.5

Watts

Maximum Power Consumption – LP
Mode

1.5

Watts

Signaling Speed Per Channel

11.2

Gb/s

High Speed Electrical Specifications
Parameter

Min

TypicalGeneralSupply Voltage

3.1

3.3

Transmitter
Transmitter Differential Input
Impedance

100

Transmitter Differential Input Voltage

120

ohms
1200

Transmitter Signaling Speed Operating
Range

mVpp

±20

ppm

Differential Output impedance

100

ohms

Receiver Signaling Speed Operating
Range

±100

ppm

ReceiverCA OPTRONICS GROUP INC

Page 3 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

Differential output voltage

300

850

mV

Rise Time

60

ps

Fall Time

60

ps

Optical Characteristics
Transmitter Specifications – OpticalParameter

Min

TypicalMax

Unit

Lane Wavelength Range

1264.51284.51304.51324.5

1271
1291
1311
1331

1277.51297.51317.51337.5

nm

11.2

Gb/s

2.3

dBm

8.3

dBm

3.5

dBm

Data Rate Per Lane
Average Optical power per lane

-7.6

Total Average Launch power
Optical Modulation Amplitude (OMA),
each lane-4

Extinction Ratio

3.5

dB

Difference in launch power between
any two lanes

6.5

dB

Relative Intensity Noise (RIN)

-128

dB/Hz

Launch Power in OMA minus TDP,
each lane-4.8

Transmitter and dispersion penalty(TDP), each lane
Side-Mode Suppression Ratio(SMSR)
Average Launch Power per lane @TX off state

dBm
2.6

30

dB
dB

-30

dBm

Transmitter Reflectance

-12

dB

Optical return loss tolerance

20

dB

Transmitter Eye Mask definition:
X1, X2, X3, Y1, Y2, Y3

Compliant with 802.3ba standard{0.25, 0.4, 0.45, 0.25, 0.28, 0.4}
5% mask margin over specified ranges of temperature,
voltage and power supply noise at end of life.

Eye Mask Criteria

Receiver Specifications – Optical

CA OPTRONICS GROUP INC

Page 4 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

Parameter

Min

TypicalMax

Unit

Lane Wavelength Range

1264.51284.51304.51324.5

1271
1291
1311
1331

1277.51297.51317.51337.5

nm

3.4

dBm

2.3

dBm

Receive Power, each lane (OMA)

3.5

dBm

Difference in Receive Power between any twolanes (OMA)

7.5

dB

Receiver Reflectance

-26

dB

Receiver Sensitivity (OMA) per lane(@ PRBS 231-1 and BER=10-12)

-11.5

dBm

Receiver 3 dB electrical upper cutoff frequency,
each lane

12.3

GHz

-9.6

dBm

Damage Threshold
Average Receive Power, each lane

-13.7

Stressed Receiver Sensitivity OMA), each lane
RX_ LOS_ Assert Min/Max-30

RX_ LOS_ De-Assert Max
RX_ LOS_ Hysteresis

dBm
-14

0.5

dBm
dB

Recommended Host Board Power Supply Filtering

Figure 2.QSFP voltage supply and filtering scheme

Pin Descriptions

CA OPTRONICS GROUP INC

Page 5 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

Pin

Logic

SymbolName/Description

Ref.

GND

Module Ground

1

1
2

CML-I

Tx2-

Transmitter inverted data input

3

CML-I

Tx2+

Transmitter non-inverted data input

GND

Module Ground

4

1

5

CML-I

Tx4-

Transmitter inverted data input

6

CML-I

Tx4+

Transmitter non-inverted data input

GND

Module Ground

1

7
8

LVTTL-I

MODSEIL

Module Select2

9

LVTTL-I

ResetL

Module Reset

2

VCCRx

+3.3v Receiver Power Supply

10
11

LVCMOS-I

SCL

2-wire Serial interface clock

2

12

LVCMOS-I/O

SDA

2-wire Serial interface data

2

GND

Module Ground

1

13
14

CML-O

RX3+

Receiver non-inverted data output

15

CML-O

RX3-

Receiver inverted data output

GND

Module Ground

16
17

CML-O

RX1+

Receiver non-inverted data output

18

CML-O

1

RX1-

Receiver inverted data output

19

GND

Module Ground

1

20

GND

Module Ground

1

21

CML-O

RX2-

Receiver inverted data output

22

CML-O

RX2+

Receiver non-inverted data output

GND

Module Ground

23
24

CML-O

RX4-

Receiver inverted data output

25

CML-O

RX4+

Receiver non-inverted data output

GND

Module Ground

26
27

LVTTL-O

ModPrsL

Module Present, internal pulled down to GND

28

LVTTL-O

IntL

Interrupt output, should be pulled up on host board

VCCTx+3.3v Transmitter Power Supply

29
30
31

LVTTL-I

1

1
2

VCC1

+3.3v Power Supply

LPModeLow Power Mode2

GND

Module Ground

1

32
33

CML-I

Tx3+

Transmitter non-inverted data input

34

CML-I

Tx3-

Transmitter inverted data input

GND

Module Ground

35
36

CML-I

Tx1+

Transmitter non-inverted data input

37

CML-I

Tx1-

Transmitter inverted data input

GND

Module Ground

38

1

1

Notes:CA OPTRONICS GROUP INC

Page 6 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

1. Module circuit ground is isolated from module chassis ground within the module.
2. Open collector; should be pulled up with 4.7k – 10k ohms on host board to a voltage between 3.15V and3.6V.

QSFP Edge Connector and Pinout Description
The electrical interface to the transceiver is a 38-pin edge connector. The 38-pins provide highspeed data, low speed monitoring and control signals, I2C communication, power and groundconnectivity. The top and bottom views of the connector are provided below, as well as a table
outlining the contact numbering, symbol and full description.

ModSelL Pin
The ModSelL is an input pin. When held low by the host, the module responds to 2-wire serial
communicationcommands. The ModSelL allows the use of multiple QSFP modules on a single 2-wire interface bus.
When
the ModSelL is “High”, the module will not respond to any 2-wire interface communication from thehost.
ModSelL has an internal pull-up in the module.
ResetL Pin
Reset. LPMode_Reset has an internal pull-up in the module. A low level on the ResetL pin for
longer than theminimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module
settings totheir default state. Module Reset Assert Time (t_init) starts on the rising edge after the low level ontheResetL pin is released. During the execution of a reset (t_init) the host shall disregard all status bits
until themodule indicates a completion of the reset interrupt. The module indicates this by posting an IntL

CA OPTRONICS GROUP INC

Page 7 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

signal with
the Data_Not_Ready bit negated. Note that on power up (including hot insertion) the module will
post thiscompletion of reset interrupt without requiring a reset.
LPMode Pin
CA OPTRONICS GROUP QSFP PSM LR4 operate in the low power mode (less than 1.5 W power
consumption)This pin active high will decrease power consumption to less than 1W.
LPModePower_Overide Bit
Power_set Bit
Module Power Allowed
1
0
X
X

0
0
1
1

X
X
1
0

Low Power (< 1.5W)
High Power (< 3.5W)
Low Power (< 1.5W)
High Power (< 3.5W)

ModPrsL Pin
ModPrsL is pulled up to Vcc on the host board and grounded in the module. The ModPrsL isasserted “Low”
when the module is inserted and deasserted “High” when the module is physically absent from thehost connector.
IntL Pin
IntL is an output pin. When “Low”, it indicates a possible module operational fault or a status criticalto thehost system. The host identifies the source of the interrupt by using the 2-wire serial interface. The
IntL pin is
an open collector output and must be pulled up to Vcc on the host board.

The timing for QSFP Soft Control and Status Functions are described as follows:
Parameter

SymbolMax

Unit

Initialization Timet_init2000

ms

Reset Init Assert Timet_reset_init

2μst_serial

2000

ms

t_data2000

ms

Reset Assert Timet_reset2000

ms

LPMode Assert Time

ton_LPMode

100

μs

LPMode Deassert
Time

Toff_LPMode

300

ms

IntL Assert Time

ton_IntL

200

ms

IntL Deassert Time

toff_IntL

500

μs

Rx LOS Assert Time

ton_los

100

ms

Tx Fault Assert Time

ton_Txfault

200

ms

Serial Bus Hardware
Ready Time
Monitor Data ReadyTime

CA OPTRONICS GROUP INC

Conditions
Time from power on2, hot plug or rising edge ofReset until the module is fully functional3This time
does not apply to non-Power Level 0 modules in the
Low Power StateA Reset is generated by a low level longer than theminimum reset pulse time present on the ResetL
pin.
Time from power on2 until module responds to datatransmission over the 2-wire serial bus
Time from power on2 to data not ready, bit 0 of Byte
2, deasserted and IntL asserted
Time from rising edge on the ResetL pin until themodule is fully functional3
Time from assertion of LPMode (Vin:LPMode = Vih)until module power consumption enters lower
Power Level 1
Time for deassertion of LPMode (Vin:LPMode=Vil)until module is fully functional3,5Time from occurrence of condition triggering IntL
until Vout:IntL = Vol
Time from clear on read4 operation of associatedflag until Vout:IntL = Voh. This includes deassert
times for Rx LOS, Tx Fault and other flag bits.
Time from Rx LOS state to Rx LOS bit set(value=1b) and IntL asserted
Time from Tx Fault state to Tx Fault bit set

Page 8 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01(value=1b) and IntL asserted
Time from occurrence of condition triggering flag to
associated flag bit set (value=1b) and IntL asserted
Time from mask bit set(value=1b)1 until associatedIntL assertion is inhibited
Time from mask bit cleared (value=0b)1 until
associated IntlL operation resumes
Time from change of state of Application or Rate
Select Bit1 until transmitter or receiver bandwidth isin conformance with appropriate specification

Flag Assert Time

ton_flag200

ms

Mask Assert Time

ton_mask

100

ms

Mask Deassert Time

toff_mask

100

ms

Application or Rate
Select Change Timet_ratesel

100μsPower_over-ride orPower-set Assert Time

ton_Pdown

100

ms

Time from P_Down bit set (value=1b)1 until module
power consumption enters lower Power Level 1Power_over-ride orPower-set Deassert
Time

toff_Pdown

300

ms

Time from P_Down bit cleared(value=0b)1 until themodule is fully functional3

Note：
1. Measured from falling clock edge after stop bit of read transaction.
2. Power on is defined as the instant when supply voltages reach and remain at or above the minimum levelspecified value.
3. Fully functional is defined as IntL asserted due to data not ready bit, bit 0 byte 2 deasserted. The module should
also meet optical and electrical specifications
4. Measured from falling clock edge after stop bit of write transaction.

Squelch and disable timings are defined in the table below:
Parameter

Max

Unit

ton_Rxsq

80

us

toff_Rxsq

80

us

ton_Txsq

400ms

toff_Txsq

400ms

ton_txdis

100ms

toff_txdis

400

ms

ton_rxdis

100ms

Rx Output Disable
Deassert Time

toff_rxdis

100

ms

Time from Rx Output Disable bit cleared (value =0b)1 until Rx output rises above 90% of nominal

Squelch Disable
Assert Time

ton_sqdis

100msThis applies to Rx and Tx Squelch and is the timefrom bit set (value = 0b)1 until squelch functionality
is disabled.

Squelch Disable
Deassert Time

toff_sqdis

100

ms

This applies to Rx and Tx Squelch and is the timefrom bit cleared (value = 0b)1 until squelch
functionality is enabled

Rx Squelch Assert
Time
Rx Squelch Deassert
Time
Tx Squelch Assert
Time
Tx Squelch Deassert
Time
Tx Disable Assert
Time
Tx Disable Deassert
Time
Rx Output Disable
Assert Time

SymbolConditions
Time from loss of Rx input signal until the squelched
output condition is reached.
Time from resumption of Rx input signals until
normal Rx output condition is reached.
Time from loss of Tx input signal until the squelched
output condition is reached.
Time from resumption of Tx input signals until
normal Tx output condition is reached.
Time from Tx Disable bit set (value = 1b)1 until
optical output falls below 10% of nominal
Time from Tx Disable bit cleared (value = 0b)1 until
optical output rises above 90% of nominal
Time from Rx Output Disable bit set (value = 1b)1
until Rx output falls below 10% of nominal

Note：
1. Measured from falling clock edge after stop bit of read transaction.

QSFP Module Memory Map Description
The QSFP Memory Map, shown in figure 4 below, is used for serial ID, digital monitoring
CA OPTRONICS GROUP INC

Page 9 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

andcertain control functions. The memory structure is arranged into a lower, single address spaceof
128 bytes (0-127) and multiple upper address space pages. The structure permits timelyaccess toaddress in the lower page such as Interrupt Flags, Monitors, Control and variousalarms. The upper
memory pages are used for less time critical tasks such as ID informationfields, Vendor ID, andvarious module and channels thresholds to activate various alarms.The lower page and Upper page00 is always implemented. Upper page 01 is optional andcurrently not available. Upper page 02 is
optional and implemented. Upper page 03 isimplemented.

Figure4.QSFP Memory Map

CA OPTRONICS GROUP INC

Page 10 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

Lower Memory Map Description
The lower 128 bytes of the 2-wire serial bus address space is used to access a variety ofmeasurements and diagnostic functions, a set of control functions, and a means to select which of
the various upper memory map pages are accessed on subsequent reads. This portion of theaddress space is always directly addressable and thus is chosen for monitoring and control
functions that may need to be repeatedly accessed. The definition of Identifier field is the same aspage 00h Byte 128.

Lower Memory Map of the QSFP+ module.
Byte Address

Description

Type

0
1-2
3-21
22-33
34-81
82-85
86-97
98-99
100-106
107-126
127

Identifier(1 Byte)
Status(2 Bytes)
Interrupt Flags(19 Bytes)
Module Monitors(12Bytes)
Channel Monitors(48 Bytes)
Reserved (4 Bytes)
Control(12Bytes)
Reserved(2 Bytes)
Module and Channel Masks (7 Bytes)
Reserved (12 Bytes)
Page Select Byte

Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write

Status Indicator Bits
Byte

Bit

Name

Description
Status Indicators

0All

Identifier (1 Byte)

1

All

Reserved

7

Reserved

2

Equal to 0Dh

6Reserved

5

Reserved

4

Reserved

3

Reserved2

Flat_Mem

Upper memory flat (='0') or paged ('1'). It set high ='1'.

1
0

IntL
Data_Not_Ready

Digital state of the IntL interrupt output pin.
Indicates transceiver has not yet achieved power up andmonitor data is not ready. Bit remains high until data is ready to
be read at which time the device sets the bit low.

The Data_Not_Ready bit is high during module power up and prior to a valid suite of monitor
readings. Once all monitor readings are valid, the bit is set low until the device is powered down.

Channel Status Interrupt Flags
A portion of the memory map (Bytes 3 through 21), form a flag field. Within this field, the statusof LOS and Tx Fault as well as alarms and warnings for the various monitored items is reported. In
normal conditions, the bits in this field are set to '0'. For the defined conditions of LOS, Tx Fault,
module and channel alarms, the appropriate bit or bits are set to '1'.
The Channel Status Interrupt Flags, Module Monitor Interrupt Flags and Channel Monitor
Interrupt Flags are defined below.

CA OPTRONICS GROUP INC

Page 11 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

Byte

3

4

Bit

Name

Description
Channel Status Interrupt Flags

7-4

Reserved

32

Rx4 LOSRx3 LOS

Latched RX LOS indicator, channel 4
Latched RX LOS indicator, channel 31

Rx2 LOS

Latched RX LOS indicator, channel 20
7-4

Rx1 LOSReserved

Latched RX LOS indicator, channel 1

3

Tx4 Fault

Latched TX fault indicator, channel 42

Tx3 Fault

Latched TX fault indicator, channel 31

Tx2 Fault

Latched TX fault indicator, channel 20

Tx1 Fault

Latched TX fault indicator, channel 1

All
Reserved
5
Notes：A portion of the memory map (Bytes 3 through 21), form a flag field. Within this field, the status of LOS andTx Fault as well as alarms and warnings for the various monitored items is reported. In normal conditions, the bits inthis field are set to '0'. For the defined conditions of LOS, Tx Fault, module and channel alarms, the appropriate bit
or bits are set to '1'.

Module Monitor Interrupt Flags

6

7

8

7

L-Temp High Alarm

Latched high temperature alarm

6

L- Temp Low Alarm

Latched low temperature alarm

5

L- Temp High Warning

Latched high temperature warning

4

L- Temp Low Warning

Latched low temperature warning

3-0

Reserved

7

L-Vcc High Alarm

Latched high supply voltage alarm

6

L-Vcc Low Alarm

Latched low supply voltage alarm

5

L-Vcc High Warning

Latched high supply voltage warning

4

L-Vcc Low Warning

Latched low supply voltage warning

3-0

Reserved

All

Reserved

7

L-Rx1 Power High Alarm

Latched high RX power alarm, channel 1

6

L-Rx1 Power Low Alarm

Latched low RX power alarm, channel 1

5

L-Rx1 Power High Warning

Latched high RX power warning, channel 1

4

L-Rx1 Power Low Warning

Latched low RX power warning, channel 1

3

L-Rx2 Power High Alarm

Latched high RX power alarm, channel 22

L-Rx2 Power Low Alarm

Latched low RX power alarm, channel 2

1

L-Rx2 Power High Warning

Latched high RX power warning, channel 20

L-Rx2 Power Low Warning

Latched low RX power warning, channel 2

7

L-Rx3 Power High Alarm

Latched high RX power alarm, channel 3

6

L-Rx3 Power Low Alarm

Latched low RX power alarm, channel 3

5

L-Rx3 Power High Warning

Latched high RX power warning, channel 3

4

L-Rx3 Power Low Warning

Latched low RX power warning, channel 33

L-Rx4 Power High Alarm

Latched high RX power alarm, channel 42

L-Rx4 Power Low Alarm

Latched low RX power alarm, channel 41

L-Rx4 Power High Warning

Latched high RX power warning, channel 40

L-Rx4 Power Low Warning

Latched low RX power warning, channel 4

Channel Monitor Interrupt Flags

9

10

CA OPTRONICS GROUP INC

Page 12 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

11

12

13

14

15-21

7

L-Tx1 Bias High Alarm

Latched high TX Bias alarm, channel 1

6

L-Tx1 Bias Low Alarm

Latched low TX Bias alarm, channel 1

5

L-Tx1 Bias High Warning

Latched high TX Bias warning, channel 1

4

L-Tx1 Bias Low Warning

Latched low TX Bias warning, channel 1

3

L-Tx2 Bias High Alarm

Latched high TX Bias alarm, channel 22

L-Tx2 Bias Low Alarm

Latched low TX Bias alarm, channel 2

1

L-Tx2 Bias High Warning

Latched high TX Bias warning, channel 20

L-Tx2 Bias Low Warning

Latched low TX Bias warning, channel 2

7

L-Tx3 Bias High Alarm

Latched high TX Bias alarm, channel 3

6

L-Tx3 Bias Low Alarm

Latched low TX Bias alarm, channel 3

5

L-Tx3 Bias High Warning

Latched high TX Bias warning, channel 3

4

L-Tx3 Bias Low Warning

Latched low TX Bias warning, channel 33

L-Tx4 Bias High Alarm

Latched high TX Bias alarm, channel 42

L-Tx4 Bias Low Alarm

Latched low TX Bias alarm, channel 41

L-Tx4 Bias High Warning

Latched high TX Bias warning, channel 40

L-Tx4 Bias Low Warning

Latched low TX Bias warning, channel 4

7

L-Tx1 Power High Alarm

Latched high TX power alarm, channel 1

6

L-Tx1 Power Low Alarm

Latched low TX power alarm, channel 1

5

L-Tx1 Power High Warning

Latched high TX power warning, channel 1

4

L-Tx1 Power Low Warning

Latched low TX power warning, channel 1

3

L-Tx2 Power High Alarm

Latched high TX power alarm, channel 22

L-Tx2 Power Low Alarm

Latched low TX power alarm, channel 2

1

L-Tx2 Power High Warning

Latched high TX power warning, channel 20

L-Tx2 Power Low Warning

Latched low TX power warning, channel 2

7

L-Tx3 Power High Alarm

Latched high TX power alarm, channel 3

6

L-Tx3 Power Low Alarm

Latched low TX power alarm, channel 3

5

L-Tx3 Power High Warning

Latched high TX power warning, channel 3

4

L-Tx3 Power Low Warning

Latched low TX power warning, channel 33

L-Tx4 Power High Alarm

Latched high TX power alarm, channel 42

L-Tx4 Power Low Alarm

Latched low TX power alarm, channel 41

L-Tx4 Power High Warning

Latched high TX power warning, channel 40

L-Tx4 Power Low Warning

Latched low TX power warning, channel 4All

Reserved

Module Monitoring Values
Module Monitoring Value is intended to measure module temperature and supply voltage. Theinternally measured Module temperature is represented as a 16-bit signed 2's complement value inincrements of 1/256 degrees Celsius as described below. This representation yields a total range of–128℃ to +127℃. The operational values according to the module specification are consideredvalid between –10℃ and +85℃. The module temperature accuracy is better than ±3 degrees
Celsius over the specified operating temperature and voltage.

Sign

26

25

24 23 22 21 20 2-1 2-2 2-3 2-4 2-5
Temperature word bit weights representation

CA OPTRONICS GROUP INC

Page 13 of 24
www.caoptronicsgroup.com

2-6

2-7

2-8

+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

The internally measured Module supply voltage is represented as a 16-bit unsigned integer
with the voltage defined as the full 16 bit value (0 – 65535) with LSB equal to 100 μVolt, yielding a
total measurement range of 0 to +6.55 Volts. The accuracy of the voltage is than ±3% of thenominal value over specified operating temperature and voltage.

Byte

Bit

Name

Description
Module Monitoring Values

22

All

Temperature MSB

23

All

Temperature LSB

24-25

All

Reserved

26

All

Supply Voltage MSB

27

All

Supply Voltage LSB

28-33

All

Reserved

Internally measured module temperature

Internally measured module supply voltage

Channel Monitoring Values
The Channel Monitors for RX Power and TX Bias are defined in the table below:
Byte
Bit
Name
Description
Description of Channel Monitor Values (Lower Memory Map)
34

All

Rx1 power MSB

35

All

Rx1 power LSB

36

All

Rx2 power MSB

37

All

Rx2 power LSB

38

All

Rx3 power MSB

39

All

Rx3 power LSB

40

All

Rx4 power MSB

41

All

Rx4 power LSB

42

All

Tx1 Bias MSB

43

All

Tx1 Bias LSB

44

All

Tx2 Bias MSB

45

All

Tx2 Bias LSB

46

All

Tx3 Bias MSB

47

All

Tx3 Bias LSB

48

All

Tx4 Bias MSB

49

All

Tx4 Bias LSB

50

All

Tx1 power MSB

51

All

Tx1 power LSB

52

All

Tx2 power MSB

53

All

Tx2 power LSB

54

All

Tx3 power MSB

55

All

Tx3 power LSB

56

All

Tx4 power MSB

57

All

Tx4 power LSB

58

All

VCCTX_MONITOR_MSB

59

All

VCCTX_MONITOR_LSB

CA OPTRONICS GROUP INC

Internally measured RX input power, channel 1
Internally measured RX input power, channel 2Internally measured RX input power, channel 3
Internally measured RX input power, channel 4Internally measured TX bias, channel 1
Internally measured TX bias, channel 2Internally measured TX bias, channel 3
Internally measured TX bias, channel 4Internally measured TX output power, channel 1
Internally measured TX output power, channel 2Internally measured TX output power, channel 3
Internally measured TX output power, channel 4

Page 14 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

60

All

Vcc Rx MSB

Internally measured RX VCC

61

All

Vcc Rx LSB

62

All

VCC1_MONITOR_MSB

63

All

VCC1_MONITOR_LSB

64

All

TEMP1_MONITOR_MSB

65

All

TEMP1_MONITOR_LSB

66-73

All

00h all bytes

Reserved Channel monitor

The description for the Laser Bias current and Receiver Power Monitors are detailed below.
Laser Bias Current: Measured TX bias current is in mA and are represented as a 16-bitunsigned
integer with the current defined as the full 16 bit value (0 – 65535) with LSB equal to2 uA, yielding a
total measurement range of 0 to 131 mA. Accuracy is vendor specific but must be better than ±10%of the manufacturer’s nominal value over specified operating temperature and voltage.
Received Power: Measured RX received optical power is in mW and can represent either average
received power or OMA depending upon how bit 3 of byte 220 (upper memory page00h) is set.
Represented as a 16 bit unsigned integer with the power defined as the full 16 bit value (0 – 65535)
with LSB equal to 0.1 uW, yielding a total measurement range of 0 to 6.5535mW (~-40 to +8.2 dBm).
Absolute accuracy is dependent upon the exact optical wavelength. For the vendor specified
wavelength, accuracy shall be better than ±3 dB over specified temperature and voltage. Thisaccuracy shall be maintained for input power levels up to the lesser of maximum transmitted or
maximum received optical power per the appropriate standard. It shall be maintained down to theminimum transmitted power minus cable plant loss (insertion loss or passive loss) per theappropriate standard. Absolute accuracy beyond this minimum required received input opticalpower range is vendor specific.

Control Bytes
There are 4 control bits to enable or disable each of the 4 transmitter channels. Disabling isdone by setting any one of the 4 bits of byte 86 to '1'. Bits0÷1 of byte 93 controls the LPModefunctionality of the module. The Control Bytes are described below:
Byte
Bit
Name
Description
Description of the Control Bytes.
86

7-4

Reserved

3

Tx4_Disable

Read/write bit that allows software disable of transmitters

2

Tx3_Disable

Read/write bit that allows software disable of transmitters

1

Tx2_Disable

Read/write bit that allows software disable of transmitters

0

Tx1_Disable

Read/write bit that allows software disable of transmitters

87-92

All

Reserved

All bits are ignored and read as ‘0’s upon power up

93

2-7

Reserved

1

Power_set

Power set to low power mode. Default 0.

0Power_over-ride

Override of LPMode signal setting the power mode with software

94-99

Reserved

Module and Channel Masks
The host can control each interrupt event from the QSFP module by masking thecorresponding interrupt bits. When a mask bit is written as '1', an interrupt will not occur for thisCA OPTRONICS GROUP INC

Page 15 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

specific event. When the bit is unmasked ('0'), the QSFP will initiate an interrupt by asserting IntL to
LOW when a specific event occurs. Using interrupt mask bits enable the host to use polling routine if
desirable. The table below depicts the bits and the bytes to mask interrupt events.
Byte
Bit
Name
Description
Description of Module and channel Interrupt masking bits
86

7-4

Reserved

3

Tx4_Disable

Read/write bit that allows software disable of transmitters

2

Tx3_Disable

Read/write bit that allows software disable of transmitters

1

Tx2_Disable

Read/write bit that allows software disable of transmitters

0

Tx1_Disable

Read/write bit that allows software disable of transmitters

87-92

All

Reserved

All bits are ignored and read as ‘0’s upon power up

93

2-7

Reserved

1

Power_set

Power set to low power mode. Default 0.

0Power_over-ride

Override of LPMode signal setting the power mode with software

94-99

Reserved

Module and Channel Masks
The host can control each interrupt event from the QSFP module by masking thecorresponding interrupt bits. When a mask bit is written as '1', an interrupt will not occur for thisspecific event. When the bit is unmasked ('0'), the QSFP will initiate an interrupt by asserting IntL to
LOW when a specific event occurs. Using interrupt mask bits enable the host to use polling routine if
desirable. The table below depicts the bits and the bytes to mask interrupt events.
Byte
Bit
Name
Description
Description of Module and channel Interrupt masking bits
100

101

7-4

Reserved3

M-Rx4 LOS

Masking bit for RX LOS indicator, channel 42

M-Rx3 LOS

Masking bit for RX LOS indicator, channel 31

M-Rx2 LOS

Masking bit for RX LOS indicator, channel 20

M-Rx1 LOS

Masking bit for RX LOS indicator, channel 1

7-4

Reserved3

M-Tx4 Fault

Masking bit for TX fault indicator, channel 42

M-Tx3 Fault

Masking bit for TX fault indicator, channel 31

M-Tx2 Fault

Masking bit for TX fault indicator, channel 2
Masking bit for TX fault indicator, channel 10

M-Tx1 Fault

102

All

Reserved

103

7

M-Temp High Alarm

Masking bit for high Temperature alarm

6

M-Temp Low Alarm

Masking bit for low Temperature alarm

5

M-Temp High Warning

Masking bit for high Temperature warning

4

M-Temp Low Warning

Masking bit for low Temperature warning

3-0

Reserved

104105-106

7

M-Vcc High Alarm

Masking bit for high Vcc alarm

6

M- Vcc Low Alarm

Masking bit for low Vcc alarm5

M- Vcc High Warning

Masking bit for high Vcc warning

4

M- Vcc Low Warning

Masking bit for low Vcc warning

3-0

Reserved

All

Reserved

CA OPTRONICS GROUP INC

Page 16 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

Password and Page SelectBytes 119-126 are reserved for an optional password entry function. The Password entry bytesare write only and will be retained until power down, reset, or rewritten by host. This function may
be used to control read/ write access to vendor specific page 02h. Additionally, module vendors
may use this function to implement write protection of Serial ID and other QSFP+ read only
information. Passwords may be supplied to and used by Host manufacturers to limit write access in
the User EEPROM Page 02h. Password access shall not be required to access QSFP+ defined
data in the lower memory page 00h or in upper pages 00h, 02h and 03h. Note that multiple module
manufacturer passwords may be defined to allow selective access to read or write to various
sections of memory as allowed above. Host manufacturer and module manufacturer passwords
shall be distinguished by the high order bit (bit 7, byte 123). All host manufacturer passwords shall
fall in the range of 00000000h to 7FFFFFFFh, and all module manufacturer passwords in the rangeof 80000000h to FFFFFFFFh. Host manufacturer passwords shall be initially set to 00001011h in
new modules. Host manufacturer passwords may be changed by writing a new password in bytes
119-122 when the correct current Host manufacture password has been entered in 123-126, withthe high order bit being ignored and forced to a value of 0 in the new password. The password entry
field shall be set to 00000000hon power up and reset.
Data
Address

Bit

Name of Field

107-118

All

Reserved119-122All

123-126

All

127

All

Password
Change(optional)
Password Entry Area
(optional)

Value

Entry

Page Select Byte

Area

Description of field

0000h
Read/Write
00000000h
Read/Write
00000000h
Read/Write
00h
Read/Write

Upper Memory Map Page 00h Description
Page 00h consists of the Serial ID and is used for read only identification information. The
Serial ID is divided into the Base_ID Fields, Extended ID Fields and Vendor Specific ID Fields.The
format of the Serial ID Memory Map is shown below.

Upper memory map page 00h general description of the QSFP module.
Address

Size(Bytes)

Name

Base_ID Fields
128
1
129
1
130
1

Identifier
Ext. Identifierconnector

131-1388

Transceiver

139
140

1
1

141

1

142

1

Encoding
BR,nominal
ExtendedCompliance
Length(SMF)143

1

Length(E-50um)

144

1

Length(50 um)

145

1

Length(62.5 um)

CA OPTRONICS GROUP INC

Description of Base ID Field
Identifier Type of serial transceiver
Extended identifier of serial transceiver
Code for connector type
Code for electronic compatibility or opticalcompatibility
Code for serial encoding algorithm
Nominal bit rate, units of 100 MBits/s
RateSelectTags for Extended RateSelect compliance
Link length supported for SMF fiber in km
Link length supported for EBW 50/125 um fiber,
units of 2 m
Link length supported for 50/125 um fiber, units of
1m
Link length supported for 62.5/125 um fiber, units

Page 17 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

146
147
148-163164
165-167
168-183

1
1
16
1
3
16

Length(Copper)
Device Tech
Vendor name
Extended Transceiver
Vendor OUI
Vendor PN

184-1852

Vendor rev

186-187

2

Wavelength188-1892

Wavelength Toleranceof 1 mLink length supported for copper, units of 1 m
Device Technology
QSFP vendor name (ASCII)
Extended Transceiver Codes for InfiniBand
QSFP vendor IEEE company ID
Part number provided by QSFP vendor (ASCII)
Revision level for part number provided by vendor(ASCII)
Nominal laser wavelength (wavelength=value/20 innm)
Guaranteed range of laser wavelength (+/- value)
fromNominalwavelength.
(wavelength
Tol.=value/200 in nm)
Maximum Case Temperature in Degrees C
Check code for Base ID Fields(addresses 128-190)

190
1
191
1
Extended ID Fields
192-1954
196-21116
212-219
8

Max Case Temp
CC_BASE220

1

Diagnostic Monitoring Type

221

1

Enhanced Options

222

1

Reserved

223

1

CC_EXT

Options
Vendor SN
Date code

Vendor Specific ID Fields
224-255
32

Vendor Specific

Byte

Bit

Name of Bit

128

All

Identifier

Rate Select, TX Disable, TX Fault, LOS
Serial number provided by vendor (ASCII)
Vendor’s manufacturing date code
Indicates which type of diagnostic monitoring is
implemented (if any) in the transceiver. Bit 1, 0Reserved
Indicates which optional enhanced features are
implemented in the transceiver.
Reserved
Check code for the Extended ID Fields(addresses
192-222)
Vendor Specific EEPROM

Description
Identifier (Address 128)
0Dh=QSFP+

Extended Identifier (Address 129)

129

7-6

Ext. Identifier

5

3
2
1-0

Reserved
NO CLEI code present in Page
02h
NO CDR in TX
NO CDR in RX
Reserved

All

Connector Type

4'11': Power Class 4 Module (3.5 W max. power
consumption)
0
0
0
0
0

Module Connector Type (Address 130)13007h = LC

Transceiver Definition (Address 131-138)131
132-138All
All

Connection Data
Reserved

02h = 40GBase-LR 4

Module Data Encoding (Address 139)00h = unspecified (It is transparent for all givencodes(01h-05h) in the standard.

139

All

Encoding

140-141142
143-146

All
All
All

Reserved
SMF length support
Reserved

147

7-4

Device Technology

Module Extended Rate and Length (Addresses 140-146)
0Ah (10km)

Device Technology (Address 147)

CA OPTRONICS GROUP INC

04h = (DFB laser at 1310nm).

Page 18 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

0: No wavelength control, 1: Active wavelength control(=0)
0: Uncooled transmitter device, 1: Cooled transmitter (=0)
0: PIN detector, 1: APD detector (=0)
0: Transmitter not tunable, 1: Transmitter tunable (=0)

3
2
1
0

16 Character Vendor Name (Address 148-163)
148-163All“CA OPTRONICS GROUP” (there are 7 ASCII spaces

Vendor Namepadded on theright to get 16 characters.)

Extended Transceiver Codes (Address 164)
164

7-4
3
2
1
0

ReservedEDR Speed (20 Gb/s)
QDR Speed (10 Gb/s)
DDR Speed (5.0 Gb/s)
SDR Speed (2.5 Gbps)

165-167
168-183
184-185

All
All
All

Vendor OUI
Vendor PN
Vendor Rev

0
1 (support QDR per lane)
1 (support DDR per lane)
1 (support SDR per lane)

Vendor Information (Address 165-185)
Organization Unique Identifier
GQS-SPO400-LR4C
Product Revision number

Wavelength and Wavelength Tolerance (Address 186-189)
186-189

Reserved

Maximum Case Temperature (Address 190)
190

All

Standard Temp = 700C = 46h.

Check Code Base (Address 191)
191

All

192

All
7-1
0
7-4

Low 8 bits of the sum of the content of all page00
byte from 128 to 190 inclusive.

CC_BaseModule Options (Address 192-195)
193

3
194

2
1
0
7
6
5

195

h

4
3
2
1
0

Rx Amplitude Programming
Options
Rx_Squelch Disable
implemented
Rx_Output Disable capable
Tx Squelch Disable
implemented
Tx Squelch implemented:
Memory page 02 provided
Memory page 01 provided
RATE_SELECT is
implemented
TX_DISABLE is implemented
TX_FAULT signal implemented
Tx Squelch implemented
TX Loss of Signal implemented

Reserved
Reserved'1' - implemented
Reserved'1' - implemented'1' - implemented'0' – Not implemented'0' – Not implemented'1' - implemented'0' – Not implemented'0' – Not implemented'1' - implemented'1' - implemented'0' – Not implemented'0' – Not implemented
Reserved

Vendor SN (Address 196-211)
196-211

All

Vendor SN

212-213AllYear

214-215

All

Month

216-217
218-219

All
All

Day
Lot Code

220

7-4

Reserved

yy ww cccc (yy – Year, ww – Work week , cccc –Counter)Module Date Code (Address 212-219)
Two low order ASCII digits of year (2000=00).
Two ASCII digits of month (January=01) through(December=12).
ASCII Code of Day of Month (01-31)
Vendor Specific Lot number

Diagnostic Monitoring Type (Address 220)

CA OPTRONICS GROUP INC

Page 19 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

3
2-0

Rx Monitoring is Average
Power ('1') or OMA ('0')
Reserved'1'

Check Code Extended (Address 223)
223

All

224-255

All

Low 8 bits of the sum of the content of all page00 byte
from 192 to 222 inclusive.

CC_EXT

Vendor Specific EEPROM (Address 224-255)
Vendor Specific CodeUpper Memory Map Page Description
Upper Memory Map
Page
01h
02h

03h

Description
Not implemented for user.
Page 02 is optionally provided as user writable EEPROM. The host system mayread or write this memory for any purpose
Byte
Description
Type
Address
128-175
Module Thresholds(48 Bytes)
Read-Only
176-223
Channel Thresholds(48 Bytes)
Read-Only
224-225
Reserved(2 Bytes)
Read-Only
226-239
Vendor Specific Channel Controls(14 Bytes)
Read/Write
240-241
Optional Channel Controls(2 Bytes)
Read/Write242-253
Channel Monitor Masks(12 Bytes)
Read/Write
254-255
Reserved(2 Bytes)
Read/Write

Output Amplitude Control
The output voltage levels of the 4 RX lanes are set using a global register that controls all
fourlanes simultaneously. The register definition and default value are given in the table below.
Output Control per Lane
Default Value

Byte

Size(Bytes)

Name

238

3-0

RX1-RX4 output amplitude‘2’hRx Squelch and Output Disable Control
This enables to control RX_SQ and RX_DIS operation of the transceiver. The default value is'0' upon power up. Therefore Squelch is operational when power up. When '1' is written for specificchannel, then this channel Squelch functionality will be disabled. When writing '1' in
RX_Output_Disable, the output of this specific channel will be disabled.
Squelch and Output Disable Controls
Byte
Bits
Name
Description
240

241

7
6
5
4
7
6
5
4
3-0

Rx4_SQ_Disable
Rx3_SQ_Disable
Rx2_SQ_Disable
Rx1_SQ_Disable
Rx4_ Output _Disable
Rx3_ Output _Disable
Rx2_ Output _Disable
Rx1_ Output _Disable
ReservedRx Squelch Disable, channel 4
Rx Squelch Disable, channel 3
Rx Squelch Disable, channel 2
Rx Squelch Disable, channel 1
Rx Output Disable, channel 4
Rx Output Disable, channel 3
Rx Output Disable, channel 2
Rx Output Disable, channel 1

Channel Monitor Masks
The masking Bits for the Channel Monitor Functions are defined below. When writing '1' in a
specific bit location, then this specific channel interrupt is disabled upon reaching specific threshold

CA OPTRONICS GROUP INC

Page 20 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

parameter. The bits can mask High or Low Warning signals or Alarm signals for each individual
receiving and transmitting channels.
Channel Monitor Masks
Byte
Bits
Name
Description
242

243

244

245

246

7

M-Rx1 Power High Alarm6

M-Rx1 Power Low Alarm5

M-Rx1 Power High warning

4

M-Rx1 Power Low warning3

M-Rx2 Power High Alarm2

M-Rx2 Power Low Alarm1

M-Rx2 Power High warning

0

M-Rx2 Power Low warning

7

M-Rx3 Power High Alarm6

M-Rx3 Power Low Alarm5

M-Rx3 Power High warning

4

M-Rx3 Power Low warning3

M-Rx4 Power High Alarm2

M-Rx4 Power Low Alarm1

M-Rx4 Power High warning

0

M-Rx4 Power Low warning

7
6

M-Tx1 Bias High Alarm
M-Tx1 Bias Low Alarm5

M-Tx1 Bias High warning

4
3
2

M-Tx1 Bias Low warning
M-Tx2 Bias High Alarm
M-Tx2 Bias Low Alarm1

M-Tx2 Bias High warning0
7
6

M-Tx2 Bias Low warning
M-Tx3 Bias High Alarm
M-Tx3 Bias Low Alarm5

M-Tx3 Bias High warning4
3
2

M-Tx3 Bias Low warning
M-Tx4 Bias High Alarm
M-Tx4 Bias Low Alarm1

M-Tx4 Bias High warning0
7
6

M-Tx4 Bias Low warning
M-Tx1 Power High Alarm
M-Tx1 Power Low Alarm5

M-Tx1 Power High warning

4

M-Tx1 Power Low warning

CA OPTRONICS GROUP INC

Masking bit for high RX Power alarm, channel
1
Masking bit for low RX Power alarm, channel 1
Masking bit for high RX Power warning,
channel 1
Masking bit for low RX Power warning, channel
1
Masking bit for high RX Power alarm, channel
2
Masking bit for low RX Power alarm, channel 2
Masking bit for high RX Power warning,
channel 2
Masking bit for low RX Power warning, channel
2
Masking bit for high RX Power alarm, channel
3
Masking bit for low RX Power alarm, channel 3
Masking bit for high RX Power warning,
channel 3
Masking bit for low RX Power warning, channel
3
Masking bit for high RX Power alarm, channel
4
Masking bit for low RX Power alarm, channel 4
Masking bit for high RX Power warning,
channel 4
Masking bit for low RX Power warning, channel
4
Masking bit for high TX Bias alarm, channel 1
Masking bit for low TX Bias alarm, channel 1
Masking bit for high TX Bias warning, channel
1
Masking bit for low TX Bias warning, channel 1
Masking bit for high TX Bias alarm, channel 2
Masking bit for low TX Bias alarm, channel 2
Masking bit for high TX Bias warning, channel
2
Masking bit for low TX Bias warning, channel 2
Masking bit for high TX Bias alarm, channel 3
Masking bit for low TX Bias alarm, channel 3
Masking bit for high TX Bias warning, channel
3
Masking bit for low TX Bias warning, channel 3
Masking bit for high TX Bias alarm, channel 4
Masking bit for low TX Bias alarm, channel 4
Masking bit for high TX Bias warning, channel
4
Masking bit for low TX Bias warning, channel 4
Masking bit for high TX Power alarm, channel 1
Masking bit for low TX Power alarm, channel 1
Masking bit for high TX Power warning,
channel 1
Masking bit for low TX Power warning, channel
1Page 21 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

247

248-255

3
2

M-Tx2 Power High Alarm
M-Tx2 Power Low Alarm1

M-Tx2 Power High warning0

M-Tx2 Power Low warning

7
6

M-Tx3 Power High Alarm
M-Tx3 Power Low Alarm5

M-Tx3 Power High warning

4

M-Tx3 Power Low warning3
2

M-Tx4 Power High Alarm
M-Tx4 Power Low Alarm1

M-Tx4 Power High warning

0

M-Tx4 Power Low warning

All

Reserved

Masking bit for high TX Power alarm, channel 2
Masking bit for low TX Power alarm, channel 2
Masking bit for high TX Power warning,
channel 2
Masking bit for low TX Power warning, channel
2
Masking bit for high TX Power alarm, channel 3
Masking bit for low TX Power alarm, channel 3
Masking bit for high TX Power warning,
channel 3
Masking bit for low TX Power warning, channel
3
Masking bit for high TX Power alarm, channel 4
Masking bit for low TX Power alarm, channel 4
Masking bit for high TX Power warning,
channel 4
Masking bit for low TX Power warning, channel
4

Mechanical Dimensions

Ordering information

CA OPTRONICS GROUP INC

Page 22 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

Part Number

Product
Description
40Gbps QSFP+ LR4,40GE Ethernet, Pull-Tab,10 km on astandardsingle mode fiber

CAQS-SPO400-LR4C

ESDThis QSFP LR4 is specified as ESD threshold 1KV for high speed data pins and 2KV for all others
electrical input pins, tested per MIL-STD-883, Method 3015.4 /JESD22-A114-A (HBM). However,normal ESD precautions are still required during the handling of this module. This transceiver isshipped in ESD protective packaging. It should be removed from the packaging and handled only inan ESD protected environment.

Regulatory ComplianceFeatureLaser Safety
Environmental protection

Standard
IEC 60825-1:2014 (Third Edition)
2011/65/EU

CE EMC

EN55032：2015 EN55024：2010+A1：
2015
EN61000-3-2:2014
EN61000-3-3:2013

FCC

FCC Part 15, Subpart B; ANSI C63.4-2014

Product Safety

EN/UL 60950-1, 2nd Edition, 2014-10-14

Laser Safety
This is a Class 1 Laser Product according to IEC 60825-1:2007. This product complies with 21 CFR
1040.10 and 1040.11 except for deviations pursuant to Laser Notice No. 50, dated (June 24, 2007).
CAUTION:Use of controls or adjustment or performance of procedures other than those specified herein may
result in hazardous radiation exposure

Important Notice
CA OPTRONICS GROUP INC

Page 23 of 24
www.caoptronicsgroup.com+1-510-366-7353

CAQS-SPO400-LR4C 40G QSFP+ LR4 10km R01

Performance figures, data and any illustrative material provided in this data sheet are typical andmust be specifically confirmed in writing by CA OPTRONICS GROUP before they become applicable toany particular order or contract. In accordance with the CA OPTRONICS GROUP policy of continuous
improvement specifications may change without notice.
The publication of information in this data sheet does not imply freedom from patent or otherprotective rights of CA OPTRONICS GROUP or others. Further details are available from any CA
OPTRONICS GROUP sales representative.

sales@caoptronics.com
http://www.caoptronicsgroup.com

CA OPTRONICS GROUP INC

Page 24 of 24
www.caoptronicsgroup.com+1-510-366-7353