Single-phase Solid-State Transformer using
Multi-cell with Automatic Capacitor Voltage
Balance Capability
Jun-ichi Itoh, Kazuki Aoyagi, Keisuke Kusaka and Masakazu Adachi
Department of Electrical, Electronics and Information Engineering
Nagaoka University of Technology
Nagaoka, Niigata, Japan
itoh@vos.nagaokaut.ac.jp, aoyagi@stn.nagaokaut.ac.jp, kusaka@vos.nagaokaut.ac.jp,
m_adachi@stn.nagaokaut.ac.jp

Abstract- In this paper, a single-phase solid-statetransformer (SST) system based on a multilevel topology
using multi-cell is proposed. The proposed SST has an
automatic capacitor voltage balancing capability on a
primary side due to use of a resonant DC-DC converter. The
main contribution of this paper is revealing the fundamental
loss design of the proposed topology connected with a 6.6-kV
grid. It is predicted that the maximum efficiency of full model
SST reaches 99%. The miniature model SST is tested toconfirm the fundamental operation with an input voltage of1320 V, which is 1/5 of the full model. As a result, thesinusoidal input current is obtained with a total harmonic
distortion of 4.3%. Besides, the bidirectional operation isverified. Then, it is confirmed that the primary side capacitor
voltage of each cell is kept constant and balanced without avoltage balance control. Moreover, the loss analysis is derived
in each part and compared with that of the experimental
result. The error of the loss between the experimental result
and the calculation is less than 5%.
Keywords— Solid-State Transformer; Power factor
correction converter; Resonant DC-DC converter; Highfrequency transformer;

I. INTRODUCTION
Recently, a DC distribution system has been actively
researched in order to achieve the energy-saving of thedata-center or the large building [1] [2]. The DC
distribution system is possible to achieve down-sizing andhigh efficiency compared with an AC distribution system[3]. Moreover, a 6.6-kV AC power grid is employed as oneof the power sources.
In general, a transformer is applied between the AC
power grid and the DC distribution system in order toachieve the step-down from 6.6 kV to the distribution
voltage of several hundred volts and obtain galvanic
isolation between the AC power grid and the DC
distribution system [4] [5]. However, the conventionaltransformers are bulky and heavy because the transformers
operate at a grid frequency, e.g., 50 Hz or 60 Hz.
As one of the solutions, a transformer-less converter is
proposed [6]. In the five-level diode-clamped converter,
the high voltage IGBTs with the voltage rating more than
4.5 kV are required. In addition, the balancing circuit isrequired as the auxiliary circuit in order to correct theunbalanced voltage among four capacitors in the DC link.
Besides, it is operated by low switching frequency because
the loss of high voltage rating devices is large compared to
low voltage rating devices. Consequently, large passive
components are required due to low switching frequency
in order to suppress harmonic distortion of input current
and voltage ripple of output DC voltage.
As another solution, solid-state transformers (SST) havebeen attracting attention [7]–[9]. SST is possible tosignificantly reduce the system volume compared to theconventional transformer by introducing high-frequency
switching with the spread use of silicon carbide (SiC) andgallium nitride (GaN) devices [10]. SST simultaneously
achieves the insulation and the step-down function byusing a high-frequency transformer. To sum up, SST has
following advantages [11]:•Reduced size and weight of the system•
Harmonic suppression•
Active/ Reactive power control•
AC voltage adjustment•
DC voltage output
Besides, it is possible to compose the cell converters
based on multilevel topologies, which enable to reduce arequired voltage rating of the switching devices. The cellconverters allow using switching devices with low on-state
resistance and high-speed switching. In addition, theswitching frequency is equivalently increased. Thus, theinductor volume can also be reduced [12]. Consequently,
SST achieves high voltage rating with high switchingfrequency by multilevel topologies.
However, the number of the switches still increases
greatly due to the multistage cell. Moreover, the control
system, which drives the main circuit, is complicatedbecause the number of the gate signal is increased withincreased number of the switch [13]. Moreover, a balance
control for each capacitor on the cells is required in themultilevel system, e.g., modular multilevel converter(MMC) [14]. The balance control may cause an unstable
if a feedback control has a delay due to isolation or signaltransmission [15]. Furthermore, the DC link capacitor witha large capacitance is required in order to maintain theconstant capacitor voltage in each cell [16].

Primary side rec.

Cell No. 1

Snubber
circuit

PFC converter
Lb

S1

Cout

Resonant DC-DC converter Secondary side rec.

Spfc11
Sllc11
C1

S3
Spfc12

vin

Ls

S5

S7

S6

S8

N1 : N2

Vdc1

Vout

Sllc12
Cs

Veq
S2

S4

Csnb
Rsnb

Cell No. 2
Cell No. 3

Fig. 1. Circuit configuration of proposed bidirectional single-phase SST.

In this paper, a simple circuit configuration of thesingle-phase SST is proposed. The proposed SST, which
achieves capacitor voltage balance among cells without acomplex voltage balance control with small primary side
capacitor. Additionally, the proposed circuit reduces thenumber of the switching devices compared to theconventional circuit. The originalities of in this paper areproposing a new SST topology and the automatic voltage
balancing method using a resonant DC-DC converter,
which is connected in parallel in the secondary side. The
contributions of this paper are that the volume of system isreduced and the control is simple. The proposed SST
system is experimentally tested under a derating voltage of1320 V which is 1/5 of the full model. In addition, thebidirectional operation is verified with the input voltage of
200 V to validate a loss distribution. Then, the proposed
SST is designed for a 6.6-kV grid as the input voltage.
II.

SYSTEM CONFIGURATION OF PROPOSED SST

A. Circuit configuration
Figure 1 shows the circuit configuration of the proposed
SST. At the primary side, the output of the full bridge
rectifier is connected to all cells in series. The devices withhigh voltage rating are required on the primary side.
However, it is possible to use the devices with the slower
switching speed because these switches are operated at thegrid frequency. This system is characterized by a multicell input stage based on the full bridge rectifier. Each cellconsists of a boost-type power-factor-correction (PFC)
converter and a resonant DC-DC converter. PFC converter
controls the input current to sinusoidal waveform with theunity power factor. Moreover, the rectified voltage isequally divided among each PFC converter because eachcell at the primary side is connected in series. Thus, thevoltage per cell is reduced. Consequently, at the primaryside, it is possible to apply the switching device with low
voltage rating and low on-state resistance. In the resonant
DC-DC converter, the volume of the transformer isreduced because the transformer operates at highfrequency.
In addition, a large capacitor is used in the output of ageneral PFC converter. In this system, small capacitors is

TABLE I. COMPARISON OF SWITCHING DEVICE BETWEENCONVENTIONAL SST AND PROPOSED SST.
Number of Switching devices
Conventional SST
Proposed SST(PWM rec. + DAB)

Rated Voltage

Number of cell

3.3 kV672

1.7 kV

11

132

92

1.2 kV

16

192

132

52

used because the proposed circuit decouples a power
pulsation at twice the grid frequency in the secondary side.
Table I shows the comparison of the switch number
between the proposed SST and the conventional SST
which includes a PWM rectifier and a dual active bridge
converter [17]. Note that the number of cell is calculatedby the rated voltage of the switch. As shown in table 1, thenumber of devices is reduced by 30% compared toconventional SST. The reason is because the proposed
SST uses only one rectifier for each cell. Consequently,
the proposed circuit increases the utilization rate of circuitcompared the MMC.
B. Control system
Figure 2 shows the control block diagram of the
proposed circuit. The proposed control includes anautomatic current control (ACR) for the boost inductor
current. In the ACR, the boost inductor current is controlled
into full wave rectified waveform in order to correct thepower factor of the grid side. Hence, the inductor current
command value IL* is given by

I L*  I amp sin(t ) 
where Iamp is the amplitude command value of the boost
inductor current. Inductor current command IL* isgenerated by the multiplication of Iamp and the full-wave
rectified waveform with same phase as the input voltage.
In the triangular wave comparator, the gate signal for
PFC is generated by phase shifted carriers. Thus, the input
voltage is equally divided because the switching timing isdifferent. In addition, it is possible to use the switching
device with low voltage rating. Note that the ripple current
is reduced because the inductor voltage is reduced by the

I L*
vin

PLL

Sin

ABS

×

Boost inductor
current control
(ACR)
+
P
-

+

1
m

÷

+
-

Vc1
IL

Vd

NOT

Spfc11
Spfc12

NOT

Spfcm1
Spfcm2

1
0

÷

+
-

Vcm
Phase-shifted 10carrierFig. 3. Control block of PFC converter in proposed circuit.

series connection in the PFC converter. Then, the phaseshift angle θ is given by (2).

2k
 (k  0, 1,m, m 1) 

Meanwhile, the balance control of the primary side
capacitor voltage Vdc1 is not required in this system. The
voltage of the primary side capacitor may be imbalanced
due to the variation of capacitances or a difference oftransient response in general multilevel topology.
However, due to the parallel connection of the resonant
DC-DC converters, which is operated with constant duties,
at the secondary side, the output voltage of each cell is
automatically adjusted. Consequently, the primary side
capacitor voltage is naturally clumped by the voltage
which is decided by the turn ratio and the secondary
voltage because the cell with low voltage is fed more
power from the cell with high voltage. Thus, the voltage
management on the high-voltage side is not required.
Figure 3 shows the switching pulse generation of the
primary side rectifier. The switching pulse is generated bycomparing the input voltage vin and the thresholds voltageof positive/negative (Vthp/Vthn). The switching states arefollowing:•vin > Vthp
Turn on S1 and S4Turn off S2 and S3•
vin < Vthn
Turn on S2 and S3Turn off S1 and S4•Vthn < vin < Vthp
Turn off S1, S2, S3, and S4
In the power running operation, the current flows the
body diode of MOSFET. In the case of regeneration
operation, the current flows the snubber circuit.
Table II shows the switching state of the primary side
rectifier, the resonant DC-DC converter, and the secondaryside rectifier. In the primary side rectifier, the switchingfrequency is set to the grid frequency in order to achieve
the polarity inversion. In the resonant DC-DC converter,
the switching frequency is set to the resonant frequency inorder to achieve ZCS, and the switches are modulated withduty ratio of 50%. Hence, the closed-loop control for the
resonant DC-DC converter is unnecessary. Consequently,
the control is simple in this system because the current

vin

Vthp
Vthn

S1, S4S2, S3Fig. 2. Pulse generation for primary side rectifier.

TABLE II. SWITCHING MODE OF RESONANT DC-DC CONVERTER
AND RECTIFIER.
S 1 ~ S4
Sllc11 ~ Sllc12
S 5 ~ S8
Switching frequency
Duty ratio

50 Hz

50 kHz (= fo)50%

control is achieved by only the switches of PFC (Spfc). In
the secondary side rectifier uses the switching pulse
synchronized with the resonant DC-DC converter.
III. DESIGN OF PROPOSED SST
A. Snubber circuit
In the proposed SST, a snubber circuit is used in order toachieve the bidirectional operation. At regeneration
operation, the continuous current flow is secured because
the boost inductor current flows into the snubber circuit
during the dead-time. Moreover, the snubber circuit also
has to absorb all energy which is generated in the boost
inductor when all gates are off with over current detection.
Thus, the capacitor of the snubber circuit is given by

Csnb 

2
Lb I max
V 2

where Imax is current at over current detection, V is
voltage rise value of capacitor. The resistor of the snubber
circuit is given by

Rsnb 

2Vclamp 2
2
Lb I max
f sw _ rec

where fse_rec is the switching frequency of the primary side
rectifier, and Vclamp is the clamp voltage. The clamp
voltage is designed to have a margin with respect to therated voltage of device. In the miniature model SST, themargin is 20%.
B. Power-factor-correction (PFC) converter
The boost converter corrects the power factor of the gridside because the boost inductor current is controlled intofull-wave rectified waveform same as general PFC circuit[18] [19]. The boost inductor Lb in the PFC circuit is given
by
Lb 

2Vin

4 f eq I Lb

where ΔILb is the ripple current of the inductor current, andfeq is the equivalent switching frequency of the output
voltage Veq. Then, the equivalent switching frequency feq
is given byf eq  m  f sw 
where m is the number of cells, fsw is the switchingfrequency of the PFC circuit. Each cell is operated byphase-shifted carrier. Consequently, the switchingfrequency component in Veq is increased in proportional to
the number of cells. Thus, the size of the boost inductor is
reduced because the inductance is inversely proportional
to frequency.
C. Resonant DC-DC converter
The resonant DC-DC converter generates a highfrequency voltage for the isolated transformer [20]. The
high-frequency operation leads to the minimization of theisolation transformer. In addition, the zero current
switching (ZCS) is achieved by the series resonancebetween the inductor Ls and the capacitor Cs. ZCS greatly
reduce the switching loss of the proposed SST system.
Furthermore, the leakage inductance is designed to be
negligibly smaller than the excitation inductance. Then,the switching frequency fo of the resonant DC-DC
converter is given by (7). From resonance frequency, andthe duty ratio of the switch is set to 50%.
fo 

1
2 Ls Cs

In the proposed SST, the operation mode is always theboost operation with respect of the primary side voltage.
Thus, the turn ratio of the transformer is designed by
N

2Vin
N1


N 2 2mVout

where N1 and N2 are the number of turns forprimary/secondary side of the high-frequency transformer,

TABLE III. CIRCUIT PARAMETER OF PROPOSED SST FOR THE
MINIATURE MODEL

Parameter
Input voltage
Rated output power
Rated output voltage
Snubber capacitor
Sunbber resistance

Symbol
vin
Pout
Vout
Csnb
Rsnb

Value
1320 Vrms
2 kW
320 V
0.2 µF
2.5 MW

Boost inductor

Lb

24 mH
(%Z = 0.87%)

Primary side capacitor
Resonant capacitor
Leakage inductor
Secondary side capacitor
Switching frequency of rec.
Switching frequency of PFC
Resonant frequency
Number of cells
Trans turns ratio

C1
Cs
Ls
Cout
fsw_rec
fsw_pfc
fo
m
N1/N2

48 µF
204 nF
50 µH
8200 µF
50 Hz
10 kHz
50 kHz3
1.0

Vin is the input voltage, Vout is the output voltage, and λ isthe modulation index of the boost converter.
IV. EXPERIMENTAL RESULTS
A. Power running operation
Table III shows the specifications and the circuit
parameters. In this experiment, the fundamental operationis verified with the input voltage of 1320 V which is 1/5 ofthe full model. The prototype has three cells.
Figure 4 shows the waveforms of the input voltage, theinput current, and the output voltage. The operation of theminiature model without the any large distortion is
confirmed. At the input side, it is confirmed that the unity
power factor between the input voltage and the input
current is achieved. The input current THD is 4.3% at the
rated load. At the output side, the step-down operation isachieved because the output voltage is regulated to 320 V.
Figure 5 shows the primary side capacitor voltage ofeach cell when the output power is changed from 0.8p.u.
to 1.0p.u. (2 kW). It is observed that the primary side
capacitor voltage is balanced even during transient
response. Moreover, the maximum value of the primaryside capacitor voltage also shows same value for all cells.
Thus, it is confirmed that the primary side capacitor
voltage is balanced among all cells without the balance
control even when the output power suddenly changes.
Figure 6 shows the output voltage of all cells. From Fig.
6(a), the input voltage is equally divided to each cellbecause the output voltage of all cells forms balanced
multilevel waveform. In Fig. 6(b), it is also confirmed thatthe equivalent switching frequency feq is 30 kHz. The
equivalent switching frequency is determined by theswitching frequency in PFC and the number of the cells.
Figure 7 shows the relationship between efficiency andinput power factor. The maximum efficiency is 89.5% at
the rated load. The reason is that the percentage of loss indevices against the power becomes low. The input powerPrimary side capacitor voltage Vdc1, Vdc2, Vdc3 [100 V/div]

Input voltage vin [2 kV/div]

50 ms

Input current iin [3 A/div]

Output voltage Vout [200 V/div]

0.8p.u1.0p.u (rated power)

10 ms

Fig. 4. Operation waveform at power running.

Fig. 5. Primary side capacitor voltage in each cell.

Output sum voltage of each cell Veq [500 V/div]

Output sum voltage of each cell Veq [500 V/div]

20 µs

5 ms

Fig. 6(b)(a) Whole figure(b) Enlarged figure

Fig. 6. Output voltage of all cells at power running.

95

0.95

25

90

0.90

Efficiency [%]

85

0.85

Efficiency
80

0.80

75

0.75

1p.u. = 2 kW
70
0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.70
1.0

Output power [p.u.]

Fig. 7. Characteristic of efficiency and power factor.

factor is over 0.95 with the output power from 0.5p.u. to
1.0p.u.
Figure 8 shows the relationship of the input current
THD and the output power of the SST. It is confirmed thatthe input current THD is large when the output power islow. The reason is that the rate of the low-order harmonics
component appears remarkably with respect to thefundamental component because the input current is low
when the output power is low.
B. Bidirectional operation
In this experiment, the miniature model SST is tested toconfirm the fundamental operation with the input voltage
of 200 V due to the limitation of the experimental facilities.
Note that the regeneration power supply is connected to

Input current THD [%]

30

cosf

Input power factor cosf

1.00

100

1p.u. = 2 kW
20
15
10
5
0
0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Output power [p.u.]

Fig. 8. Characteristic of input current THD

the output side in order to achieve the regeneration
operation.
Figure 9 shows the bidirectional operation of SST when
the switching from power running to regeneration is tested.
In the power running operation, it is confirmed that theunity power factor between the input voltage and the input
current is achieved. On the other hand, it is confirmed thatthe input current is reversed against the input voltage in theregeneration operation. The input current THD of 4.2% isalso confirmed. In the output sum voltage of each cell, it isconfirmed that the waveform is four-level staircase voltage.
Furthermore, an equivalent switching frequency feq of 30
kHz is also confirmed. Thus, the stable operation of theminiature model without the any large distortion isachieved even when the operation abruptly changes.

Figure 10 shows the primary side capacitor voltage ofeach cell in the bidirectional operation. It is observed fromthe waveform that the primary side capacitor voltage isbalanced among all cells without the balance control evenwhen the operation changes abruptly.

Input voltage vin [300 V/div]

Input current iin [3 A/div]

V. LOSS ANALYSIS AND ESTIMATION FOR FULL MODEL
From Fig. 1, the loss of SST is separated following
components:(i)
Primary side diode bridge(ii) Switching devices of PFC converter(iii) Switching devices of the resonant DC-DC
converter(iv) Secondary side rectifier
Table IV shows the selected devices in each part. In the
proposed SST, the rated voltage of 3.3 kV is used in the
primary side rectifier.
The current which flows into the electrolytic capacitor
includes not only the power ripple component but also theswitching frequency component from the inverter. Thus, it
is very difficult to derive analytically. Hence, the capacitor
ripple current is derived by simulation [21]. The capacitor
ripple current is the function of the output power factor
angle φ and the modulation index , which is a nonlinear
value. Then, the effective value of the capacitor ripple
current is given by

I rms _ cap  K cap ( ,  ) I out 
where Iout is the average value of the output current, andKcap is the coefficient which is obtained by the simulation.
Figure 11 shows the simulation result of Kcap. The
modulation index , which expresses the ratio of the voltage
per cell and the dc-link voltage, is 0.94 in the miniaturemodel SST. Therefore, from Fig. 11, Kcap (1.0, 0.94) is 0.83.
A. Primary side diode bridge
The loss of switches, which is calculated by the onvoltage of the switch and the current through the switch, isgiven byPcon 

1 
von isw d t 
2 0where von is the on-voltage of the switch, isw is the current
through the switch. In this case, von and isw are given by.

Output voltage Vout [50 V/div]

100 msPower running mode

Regeneration mode

Input voltage vin [300 V/div]

Input voltage vin [300 V/div]

Input current iin [3 A/div]

Input current iin [3 A/div]

Output sum voltage ofeach cell Veq [200 V/div]

Output sum voltage ofeach cell Veq [200 V/div]

Output voltage Vout [50 V/div]

Output voltage Vout [50 V/div]

10 ms

10 ms

Fig. 9. Bidirectional operation of proposed circuit.

Primary side capacitor voltage Vdc1, Vdc2, Vdc3 [20 V/div]

Power running mode

Regeneration mode
100 msFig. 10. Primary side capacitor voltage of each cell at bidirectional
operation.

is not considered because the power factor is 1. The lossof the switches in the primary side rectifier is given by (13).
2P
sin(t )  v0 Vin

1  P Pcon _ pri _ rec  ron   
2  Vin Psin(t ) Vin

B. PFC converter
The conduction loss of the switches in PFC is given byvon  ron 2

isw  2

Output sum voltage of each cell Veq [200 V/div]

where ron is the on-resistance of the switch, P is the rated
power of SST. In (11), v0 is defined as zero because the
MOSFETs are used in the prototype. Moreover, the phasedifference between the input voltage and the input current

Pcon _ PFC 1
ron I L2 
2

Psw _ PFC 

1 eon  eoff Vdc P
f 
 Enom I nom Vcell m sw

where Vdc is the voltage of the primary side capacitor, P is
the rated power, m is the number of cell, fsw is the carrier
frequency, eon and eoff are the turn-on and the turn-off
energy per switching from datasheet, Enom and Inom are thevoltage and the current under the measurement conditionof the switching loss from the datasheet, and Vcell is the
input voltage of each cell.
C. Resonant DC-DC converter
The loss of switches in the resonant DC-DC converter
is only the conduction loss because ZCS assume achieving
over all operation regions.
Therefore, the conduction loss is given by

TABLE IV. SELECTED DEVICES OF PROTOTYPE FOR BIDIRECTIONALOPERATION.
Circuit topology

Part

Type

Maximum
rationSingle-phase rectifier

S1 ~ S4-

3300 VPFC converter

Spfc11~Spfc12

Resonant DC-DC
converter

Sllc11 ~ Sllc12

SCT2080KE

1200 V
40 A

Secondary side
rectifierS5 ~ S8

Current coefficient Kcap

where IL is the current effective value through the boost
inductor.
On the other hand, the switching loss of the switches,
which is assumed that it is directly proportional to thevoltage and the current of the switch, is given by

1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0

Power factor cosf

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

modulation index 
2Pcon _ LLC 22
 N  I out  I rms _ cap
1
Ron  2 
2
m2
 N1 

At the secondary side, the conduction loss is given by

I out  I rms _ cap
1
Pcon _ sec_ rec  Ron
2
m2
2

2

D. High-frequency transformer
Iron loss, which occurs in the high-frequency
transformer, is calculated by the magnetic flux density andthe characteristic of the core. The AC magnetic flux
density Bac is given by

Bac 

Vout

4 f o Ae N

where Ae is the effective cross-section of the core, and N is
the turns ratio of the transformer. The core loss value isgiven by the characteristic graph between the core loss
value vs. the magnetic flux density, which is obtained fromthe core material, and the magnetic flux density which is
calculated from (19). Therefore, the iron loss is given by

Piron _ loss  PcvVe 
where Ve is the effective volume of core.
The high frequency transformer of full model SST is
designed by Gecko MAGNETICS which uses improvedimproved Generalized Steinmetz Equation (i2GSE) in
order to calculate the iron loss of the transformer [22].
Consequently, it is possible to select the optimum coreshape, core material and winding shape. From the analysis

Fig. 11. Current coefficient of output capacitor.

of Gecko MAGNETICS, it is confirmed that the loss is
minimum by using EPCOS N95 as the core in the fullmodel SST.
E. Loss distribution
Figure 12 shows the loss distribution obtained from theexperiment and the calculation of the bidirectional
operation. Note that the loss is normalized with theexperimental loss as 100%. The error of the loss between
the experiment and the calculation is less than 5%.
Figure 13 shows the loss distribution of the full model
SST. The loss distribution is calculated with assuming 6.6kV input voltage and a 10-kVA rated power. Then, thenumber of cells is 15 because 1.2-kV switching devices
can be used. From this consideration, a 99% efficiency at
the rated power is expected. Moreover, it is possible toreduce the loss by applying synchronous rectification in
the secondary rectifier.
VI. CONCLUSION
This paper has proposed a miniature model SST, which
has a capacitor voltage balance capability without acontrol. The fundamental operation of SST was confirmedwith the input voltage of 1320 V which is 1/5 of the fullmodel from the experimental results. As a result, thesinusoidal waveform of the input current was obtained
without any large distortion at the primary side. In addition,
the bidirectional operation is confirmed in the proposed
SST with the input voltage of 200 V. Furthermore, theaverage voltage of the primary side capacitor are stableand balanced among all cells without a voltage balance
control.
Finally, the loss equation was derived at each part of thesystem and compared with experimental result. As a result,the error of the loss between the experimental result and100

REFERENCES

80

100% = 21.9 W

100% = 16.5 W

60
40
20
0
Experiment Calculation
Power running

Experiment Calculation
Regeneration

Total loss of 3-cell
Boost inductor
Primary side rec. conduction loss
Output capacitor loss
Secondary rec. conduction loss
HF trans._iron loss
HF trans._copper loss

Inductor_iron loss
Inductor_copper loss
LLC_conduction loss
PFC_switching loss
PFC_conduction loss
Snubber loss

Fig. 12. Loss distribution result by experiment and calculation atbidirectional operation. (Explanatory note corresponds to eachcolor of graph.)120

h = 99.0%
100

Outout capacitor
80

Loss [W]T. Tanaka, Y. Takahashi, K. Natori, and Y. Sato ”High-Efficiency
Floating Bidirectional Power Flow Controller for Next-Generation
DC Power Network,” IEEJ J. Industry Applications, vol. 7, no. 1,
pp. 29-34, (2018)[2] R. Chattopadhyay, S. Bhattacharya, N. C. Foureaux, A. M. Silva,
B. Cardoso F., H. de Paula, I. A. Pires, P. C. Cortizio, L. Moraes,
and J. A. de S. Brito: “Low-Voltage PV Power Integration into
Medium Voltage Grid Using High-Voltage SiC Devices,” IPEC
2014, pp.3225-3232, (2014)[3] T. Nakanishi, K. Orikawa, J. Itoh: “Modular Multilevel Converter
for Wind Power Generation System Connected to Micro-Grid,”
ICRERA2014, No. 219, (2014)[4] L. Wang, D. Zhang, Y. Wang, B. Wu, and H. S. Athab: “Power andVoltage Balance Control of Novel Three-Phase Solid-State
Transformer Using Multilevel Cascaded H-Bridge Inverters for
Microgrid Application,” IEEE Trans. On Power Electronics, Vol.
31, No. 4, pp.3289-3301, (2016)[5] T. Nakanishi, and J. Itoh, ”Control Strategy for Modular Multilevel
Converter based on Single-phase Power Factor Correction
Converter,” IEEJ J. Industry Applications, vol.6, no.1, pp.46-57,(2017).
[6] N. Hatti, Y. Kondo, and H. Akagi, “Five-Level Diode-Clamped
PWM Converters Connected Back-to-Back for Motor Drives,”
IEEE Trans. On Industry Applications, Vol.44, No.4, pp.1268-1276,(2008)[7] M. Nakahara, and K. Wada, “Loss Analysis of Magnetic
Components for a Solid-State-Transformer,” IEEJ Journal ofIndustry Applications, Vol.4, No.7, pp.387-394, (2015)[8] D. Ronanki, and S. S. Williamson: “Evolution of Power Converter
Topologies and Technical Considerations of Power Electronic
Transformer based Rolling Stock Architectures,” IEEE Trans. On
Transportation Electrification, (2017)[9] X. Yu, X, She, X. Zhou and A. Q. Huang: “Power Management for
DC Microgrid Enabled by Solid-State Transformer,” IEEE Trans.,
Vol.5, No.2, pp.954-965 (2014)[10] A. Q. Huang, Q. Zhu, L. Wang, and L. Zhang, “15 kV SiC
MOSFET: An Enabling Technology for Medium Voltage Solid
State Transformers,” CPSS Trans., Vol.2, No.2, pp.118-130 (2017)[11] J. W. Kolar and G. Ortiz: “Solid-State-Transformers: Key
Components of Future Traction and Smart Grid Systems”, IPEC
2014, pp.22-35 (2014)[12] T. Nakanishi, and J. Itoh, ”Design Guidelines of Circuit Parametersfor Modular Multilevel Converter with H-bridge Cell,” IEEJ J.
Industry Applications, vol.6, no.3, pp.231-244, (2017)[13] H. Hwang, X. Liu, J. Kim and H. Li: “Distributed Digital Controlof Modular-Based Solid-State Transformer Using DSP+FPGA,”
IEEE Trans. On Industrial Electronics, Vol.60, No.2, pp.670-680,(2013)[14] T. Nakanishi, and J. Itoh, “Capacitor Volume Evaluation based on
Ripple Current in Modular Multilevel Converter,” 9th International
Conference on Power Electronics, No. WeA1-5, (2015)[15] J. Shi, W. Gou, H. Yuan, T. Zhao and A. Q. Huang: “Research on
Voltage and Power Balance Control for Cascaded Modular SolidState Transformer,” IEEE Trans. On Power Electronics, Vol. 26,
No. 4, pp.1154-1166, (2011)[16] T. Isobe, H. Tadano, Z. He, and Y. Zou: “Control of Solid-StateTransformer for Minimized Energy Storage Capacitors,” IEEE
ECCE, pp.3809-3815, (2017)[17] J. E. Huber, and J. W. Kolar: “Solid-State Transformer: On theOrigins and Evolution of Key Concepts,” IEEE Industrial
Electronics Magazine, Vol. 10, pp.19-28, (2016)[18] T. Nussbaumer, K. Raggl, and J. W. Kolar: “Design Guidelines forInterleaved Single-Phase Boost PFC Circuits,” IEEE Trans. On
Industrial Electronics, Vol. 56, No. 7, pp.2559-2573, (2009)[19] Y. Hayashi, Y. Matsugaki, and T. Ninomiya, ”Capacitively Isolated
Multicell Dc-Dc Transformer for Future Dc Distribution System,”
IEEJ J. Industry Applications, vol. 6, no. 4, pp. 268–277, (2017)[20] M. Sato, R. Takiguchi, J. Imaoka, and M. Shoyama: “A Novel
Secondary PWM Controlled interleaved LLC Resonant Converter
for Load Current Sharing,” IPEMC 2016, pp.2276-2280, (2016)[1]

Loss [%]

the calculation is less than 5%. It is predicted that the
maximum efficiency of full model SST is 99%.

60

40

20

0

Secondary side diode rec.
High-frequency trans.
Conduction loss (LLC)
Switching loss (PFC)
Conduction loss (PFC)
Boost inductor
Primary side diode rec.

Fig. 13. Loss distribution of 6.6 kV/ 10 kW full model SST by
calculation.
[21] J. Itoh, T. Sakuraba, H. N. Le, K. Kusaka: “Requirements for
Circuit Components of Single-Phase Inverter Applied with Power
Decoupling Capability toward High Power Density,” 18th
European Conference on Power Electronics and Applications(EPE'16), DS2a 0291, (2016)[22] J. Muhlethaler, J. Biela, J. W. Kolar, and A. Ecklebe: “Improved
Core-Loss Calculation for Magnetic Components Employed inPower Electronic Systems,” IEEE Trans. On Power Electronics,
Vol. 27, No. 2, pp.964-973, (2012)