CAQM-IR-MPO-XXXC 40Gb/s QSFP+ Parallel Single Mode to MPO AOC up to 2km R01

40Gb/s QSFP+ Parallel Single Mode to MPO AOC up to 2km
CAQM-IR-MPO-XXXCFeatures♦

Full duplex 4 channel 1310nm parallel module♦

Transmission data rate up to 11.3Gbit/s perchannel♦

SFF-8436 QSFP+ compliant♦

Hot pluggable electrical interface♦

Differential AC-coupled high speed data interface♦

4 channels 1310nm FP array♦

4 channels PIN photo detector array♦

Maximum link length of 2km on G652 singlemode fiber (SMF)♦Single Mode 8 fibers MPO(APC) connector receptacle♦

Maximum power consumption 3.5W♦

Housing isolated from connector ground♦

Operating case temperature 0°C to +70°C♦3.3V power supply voltage♦

RoHS 6 compliantApplications♦

Infiniband Connectivity SDR/DDR/QDR♦

10/40 Gigabit Ethernet♦

2/4/8 Gbps Fiber Channel♦

Data Centers and Storage Arrays

Description
QSFP PSM MPO AOC are a high performance, low power consumption, long reachinterconnect solution supporting 40G Ethernet, fiber channel and PCIe. It is compliant with theQSFP MSA and 40GbE PSM4. QSFP PSM MPO AOC is an assembly of 4 full-duplex lanes,
where each lane is capable of transmitting data at rates up to 10Gb/s, providing anaggregated rate of 40Gb/s.

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Figure1. Module Block Diagram
QSFP PSM IR4 is one kind of parallel transceiver. FP and PIN array package is keytechnique, through I2C system can contact with module.

Absolute Maximum Ratings
ParameterSymbol

MinMax

Unit

Supply Voltage

Vcc-0.3

3.6

V

Input Voltage

Vin-0.3

Vcc+0.3

V

Storage TemperatureTst-2085ºC

Case Operating Temperature

Top070ºC

Humidity(non-condensing)

Rh

595%

Recommended Operating Conditions
Parameter

SymbolMin

TypicalMax

Unit

Supply Voltage

Vcc

3.13

3.3

3.47

V

Operating Case temperature

Tca

070

ºC

Data Rate Per Lane

fd

11.3

Gbps

HumidityRh

85%

Power Dissipation

Pm

3.5

W

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Link Distance with G652

RbD2kmParameter

SymboMin

TypicalMax

Unit

Differential input impedance

Zin

90

100110ohm

Differential Output impedanceDifferential input voltage

Zout

90

100110ohm

ΔVin

300

1100

mVp-p

Differential output voltage

ΔVout

500

800

mVp-p

Skew

Sw300

ps

Bit Error Rate

BR

E-12

Input Logic Level High

VIH

2.0

VCC

V

Input Logic Level Low

VIL

00.8

V

Output Logic Level High

VOH

VCC-0.5

VCC

V

Output Logic Level LowVOL00.4

VSpecifications

Note：
1. BER=10^-12; PRBS 2^31-1@10.3125Gbps.
2.
3.

Differential input voltage amplitude is measured between TxNp and TxNn.
Differential output voltage amplitude is measured between RxNp and RxNn.

Optical Characteristics
Parameter

SymbolMin

TypicalMax

Unit

Notes

Transmitter
Centre Wavelength

λc

1260

1310

1355

nm

-

RMS spectral width

∆λ--

3.5

nm

-

Average launch power, each lane

Pout-7.6-

2.4

dBm-

Difference in launch power
between any two lanes (OMA)

Ptx,diff6.5dB-

Extinction Ratio

ER-dB-

TDP

3.2

dB-

Poff-30

dBm-

RT-12

dB

Transmitter and dispersion
penalty (TDP), each lane
Average launch power of OFF
transmitter, each lane
Transmitter Reflectance
Eye Mask coordinates:
X1, X2, X3, Y1, Y2, Y3

3.5-

Hit Ratio= 5x10-5

SPECIFICATION VALUES
0.25, 0.4, 0.45, 0.25, 0.28, 0.4

ReceiverCentre Wavelength

λcStressed receiver sensitivity inOMA, each lane

SEN

CA OPTRONICS GROUP INC

1260

1310

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nm--10.6dBm

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CAQM-IR-MPO-XXXC 40Gb/s QSFP+ Parallel Single Mode to MPO AOC up to 2km R01

Maximum Average power atreceiver input, each lane

2.4dBm-Difference in Receive Powerbetween any Two Lanes(OMA)

Prx,diff

7.5

dB

Receiver Reflectance

RR-12dB-LOS Assert

LOSAdBm-LOS De-Assert

LOSD

dBm

-

LOS Hysteresis

LOSH

dB-

-30
-14
0.5

Note：

1．Measured with conformance test signal at TP3 for BER = 10e-12

Pin Descriptions
PinLogic

1Symbol

Name/Description

Ref.
1GNDModule Ground

2CML-I

Tx2-

Transmitter inverted data input

3CML-I

Tx2+

Transmitter non-inverted data input

GND

Module Ground

415CML-I

Tx4-

Transmitter inverted data input

6CML-I

Tx4+

Transmitter non-inverted data input

GND

Module Ground18

LVTTL-I

MODSEIL

Module Select29

LVTTL-I

ResetL

Module Reset

2

VCCRx+3.3v Receiver Power Supply

71011

LVCMOS-I

SCL

2-wire Serial interface clock212

LVCMOS-I/O

SDA

2-wire Serial interface data

2

GND

Module Ground

114CML-O

RX3+

Receiver non-inverted data output15

CML-O

RX3-

Receiver inverted data output

GND

Module Ground

1316

117

CML-O

RX1+

Receiver non-inverted data output

18CML-O

RX1-

Receiver inverted data output

GND

Module Ground

1119
20

GND

Module Ground

21

CML-O

RX2-

Receiver inverted data output

22

CML-O

RX2+

Receiver non-inverted data output

GND

Module GroundRX4-

Receiver inverted data output

2324

CML-O

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25CML-O

26

RX4+

Receiver non-inverted data output

GND

Module Ground127

LVTTL-O

ModPrsL

Module Present, internal pulled down to GND

28

LVTTL-O

IntL

Interrupt output, should be pulled up on host board

29

VCCTx+3.3v Transmitter Power Supply

30

VCC1+3.3v Power Supply

LPModeLow Power Mode

2GND

Module Ground131

LVTTL-I

32
33

CML-I

Tx3+

Transmitter non-inverted data input

34

CML-I

Tx3-

Transmitter inverted data input

GND

Module Ground

36

CML-I

Tx1+

Transmitter non-inverted data input

37

CML-I

Tx1-Transmitter inverted data input

GND

Module Ground3538211

Notes:
1. Module circuit ground is isolated from module chassis ground within the module.
2. Open collector; should be pulled up with 4.7k – 10k ohms on host board to a voltage between 3.15V and
3.6V.

Figure2. Electrical Pin-out Details
ModSelL Pin
The ModSelL is an input pin. When held low by the host, the module responds to 2-wire serial
communicationcommands. The ModSelL allows the use of multiple QSFP modules on a single 2-wireinterface bus. Whenthe ModSelL is “High”, the module will not respond to any 2-wire interface communication

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from the host.
ModSelL has an internal pull-up in the module.
ResetL PinReset. LPMode_Reset has an internal pull-up in the module. A low level on the ResetL pin forlonger than theminimum pulse length (t_Reset_init) initiates a complete module reset, returning all user
module settings totheir default state. Module Reset Assert Time (t_init) starts on the rising edge after the lowlevel on theResetL pin is released. During the execution of a reset (t_init) the host shall disregard all
status bits until themodule indicates a completion of the reset interrupt. The module indicates this by posting anIntL signal with
the Data_Not_Ready bit negated. Note that on power up (including hot insertion) the module
will post thiscompletion of reset interrupt without requiring a reset.
LPMode Pin
CA OPTRONICS GROUP QSFP PSM IR4 operate in the low power mode (less than 1.5 W
powerconsumption)
This pin active high will decrease power consumption to less than 1W.
ModPrsL Pin
ModPrsL is pulled up to Vcc on the host board and grounded in the module. The ModPrsL isasserted “Low”
when the module is inserted and deasserted “High” when the module is physically absent
from the host connector.
IntL Pin
IntL is an output pin. When “Low”, it indicates a possible module operational fault or a status
critical to thehost system. The host identifies the source of the interrupt by using the 2-wire serial interface.
The IntL pin is
an open collector output and must be pulled up to Vcc on the host board.

Power Supply Filtering
The host board should use the power supply filtering shown in Figure3.

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CAQM-IR-MPO-XXXC 40Gb/s QSFP+ Parallel Single Mode to MPO AOC up to 2km R01

Figure3. Host Board Power Supply Filtering

DIAGNOSTIC MONITORING INTERFACE (OPTIONAL)
Digital diagnostics monitoring function is available on all CA OPTRONICS GROUPQSFP PSM AOCs. A2-wire serial interface provides user to contact with module.
The structure of the memory is shown in Figure 4. The memory space is arranged into alower, single page, address space of 128 bytes and multiple upper address space pages.
This structure permits timely access to addresses in the lower page, such as Interrupt Flagsand Monitors. Less time critical time entries, such as serial ID information and thresholdsettings, are available with the Page Select function.
The interface address used is A0xh and is mainly used for time critical data like interrupt
handling in order to enable a one-time-read for all data related to an interrupt situation. Afteran interrupt, IntL, has been asserted, the host can read out the flag field to determine theaffected channel and type of flag.

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Figure4. QSFP Memory Map

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Figure5. Low Memory Map

Figure6. Page 03 Memory Map

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Figure7. Page 00 Memory Map
Page02 is User EEPROM and its format decided by user.
The detail description of low memory and page00.page03 upper memory please see

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SFF-8436 document.

Timing for Soft Control and Status Functions
Parameter

SymbolMaxUnit

Initialization
Timet_init

2000

ms

Reset Init Assert
Timet_reset_init

2μst_serial

2000

ms

t_data2000

mst_reset2000

ms

LPMode Assert
Time

ton_LPMode

100μs

LPModeDeassert
Time

Toff_LPMode 300

ms

IntL Assert Time

ton_IntL

ms

Serial Bus
Hardware
Ready Time
Monitor Data
Ready Time
Reset Assert
Time200

IntL Deassert
Time

toff_IntL

500

μs

Rx LOS Assert
Time

ton_los100

ms

Tx Fault Assert
Time

ton_Txfault

200msFlag Assert Time

ton_flag200ms

ton_mask

100

ms

toff_mask

100

mst_ratesel

100μs

ton_Pdown

100ms

Mask Assert
TimeMask Deassert
Time
Application orRate SelectChange TimePower_over-rideor Power-setAssert TimeCA OPTRONICS GROUP INC

Conditions
Time from power on2, hot plug or rising edge ofReset until the module is fully functional3This
time does not apply to non-Power Level 0
modules in the Low Power StateA Reset is generated by a low level longer thanthe minimum reset pulse time present on theResetL pin.
Time from power on2 until module responds todata transmission over the 2-wire serial bus
Time from power on2 to data not ready, bit 0 of
Byte 2, deasserted and IntL asserted
Time from rising edge on the ResetL pin until themodule is fully functional3
Time from assertion of LPMode (Vin:LPMode =Vih) until module power consumption enterslower Power Level 1
TimefordeassertionofLPMode(Vin:LPMode=Vil)
until
moduleisfully
functional3,5Time from occurrence of condition triggering IntL
until Vout:IntL = Vol
Time from clear on read4 operation of associatedflag until Vout:IntL = Voh. This includes deassert
times for Rx LOS, Tx Fault and other flag bits.
Time from Rx LOS state to Rx LOS bit set(value=1b) and IntL asserted
Time from Tx Fault state to Tx Fault bit set(value=1b) and IntL asserted
Time from occurrence of condition triggering flagto associated flag bit set (value=1b) and IntL
asserted
Time from mask bit set(value=1b)1 until
associated IntL assertion is inhibited
Time from mask bit cleared (value=0b)1 until
associated IntlL operation resumes
Time from change of state of Application or Rate
Select Bit1 until transmitter or receiver bandwidth
is in conformance with appropriate specification
Time from P_Down bit set (value=1b)1 until
module power consumption enters lower PowerLevel 1

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Power_over-rideor Power-set
Deassert Time

toff_Pdown

300

ms

Time from P_Down bit cleared(value=0b)1 until
the module is fully functional3

Note：
1. Power on is defined as the instant when supply voltages reach and remain at or above the minimum
specified value.
2. Fully functional is defined as IntL asserted due to data not ready bit, bit 0 byte 2 deasserted.
3. Measured from falling clock edge after stop bit of read transaction.
4. Measured from falling clock edge after stop bit of write transaction.

Figure9. Mechanical Specifications

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ESDThis QSFP PSM IR4 is specified as ESD threshold 1KV for high speed data pins and 2KV for
all others electrical input pins, tested per MIL-STD-883, Method 3015.4 /JESD22-A114-A(HBM). However, normal ESD precautions are still required during the handling of this module.
This transceiver is shipped in ESD protective packaging. It should be removed from thepackaging and handled only in an ESD protected environment.

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Ordering information
Part Number
CAQM-IR-MPO-XXXC

Product Description
40Gb/s QSFP+ PSM MPO AOC up to 2km

Important Notice
Performance figures, data and any illustrative material provided in this data sheet are typical and must be
specifically confirmed in writing by CA OPTRONICS GROUP before they become applicable to any particularorder or contract. In accordance with the CA OPTRONICS GROUP policy of continuous improvement
specifications may change without notice.
The publication of information in this data sheet does not imply freedom from patent or other protective rightsof CA OPTRONICS GROUP or others. Further details are available from any CA OPTRONICS GROUP sales
representative.

sales@caoptronicsgroup.com
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