Management TeamELMEC Corporation
Masaaki KAMEYA
Owner, Representative Chairman
CTO
Yumiko KAMEYA
Member of the Board

Akihiko KAMEYA
Member of the Board
CEO, COO
Takayoshi NOTSU (Lawyer, EA)
AuditorMatsue ELMEC Corporation
Akihiko KAMEYA
Member of the board
President, CEO
Yumiko KAMEYA
Member of the board

Kazue KAMEYA
Member of the board

Takayoshi NOTSU (Lawyer, EA)
AuditorPatents List (Differential Signal Balancer)
Title of invention

Abstract

To provide a concentrated constant type electromagnetic delay line inductanceElectromagnetic delay [PROBLEMS]
element which can easily be made as an ultra-small chip shape and obtain a preferable connection
state at each interval. [MEANS FOR SOLVING PROBLEMS] Spiral-shaped inductors L0B, L4A,line inductance
L4B are formed on a first insulating substrate (15) and the inductor L4A is connected in series toelement
the inductor L4B. Spiral-shaped inductors L1, L3, L5 are formed on a second and a third insulating

Country

Filing
Date

Issue
Data

Effective
Date

Patent NOJapan

2004/11/2

2009/11/18

2024/11/2

JP4368352(B2)Japan

2009/9/25

2013/11/27

2029/9/25

JP5352881(B2)USA

2010/9/17

2014/10/21

2030/9/16

US8866566 (B2)EU

2010/9/24

2015/4/22

2030/9/23

EP2302793 (B1)

China

2010/9/21

2014/8/13

2030/9/20

CN102035490 (B)Japan(2009/11/2)

2013/11/13

2030/10/13

JP5341201 (B2)

US Publish

US2007/0035363 A1 WO2005043750 (A1)

substrate (22, 33). Spiral-shaped inductors L2A, L2B, L6A are formed on a fourth insulating
substrate (41) and the inductor L2A is connected in series to the inductor L2B. The first to thefourth insulating substrates (15-41) are stacked on one another and the inductors L0B to L6A areconnected in the longitudinal direction. The inductors L2A and L2B and the inductors L4A and L4B
are divided into two portions in the horizontal direction so as to form one interval and positively
connected to the preceding and the following interval not divided in the horizontal direction.

pass an ultra high-speed differential signal and make it difficult to pass a common mode noise.
Common mode filter To
Lumped—constant differential delay line DL is formed by arranging inductors Lo, being passive
series elements, and capacitors Co, being passive parallel elements, in a differential four terminal
network of a ladder shape composed of the passive series elements and the passive parallel
elements arranged in differential lines 1 and 3. The lumped-constant differential delay line DL is
composed of capacitors Co including two capacitors Co/2 and Co/2, or Co and Co equivalent tothe aforementioned capacitors, having equal values, and connected in series. Inductors L1 to L4
for attenuating a common mode noise are connected between connection points of the capacitors
Co/2 and Co/2 or Co and Co connected in series, and a ground potential, so that attenuation poles
are formed for attenuating the common mode noise together with the capacitors Co/2 and Co.

is provided a common mode filter capable of allowing an ultrahigh speed differential signal to
Common mode filter Theretransmit and hardly allowing a common mode noise to transmit, comprising: a lumped-constantdifferential delay line DL formed by arranging inductors Lo, being passive series elements, andcapacitors Co, being passive parallel elements, in a ladder-shaped differential four terminal
network composed of the passive series elements and the passive parallel elements arranged in
the differential lines 1, 3. In the lumped-constant differential delay line DL, the capacitors Co, being
the parallel elements, are formed of two capacitors connected in series equivalent to each otherand having same values with each other such as Co/2 and Co/2, or Co and Co. Inductors L1 to L4and resistors R1 to R4 for attenuating the common mode noise are connected between connection
points T1 to T4 of the capacitors Co/2 or Co connected in series, and a ground potential, thus
forming a common mode noise attenuating series resonance circuit together with the capacitors
Co/2, Co.

USA

2010/10/13★

2014/9/30

2030/9/16

US8847705 (B2)

China

2010/10/13★

2015/6/10

2030/10/12

CN102474235 (B)an ultrahigh-speed differential transmission line, an ultrahigh-speed differential signal is passed
Common mode filter In
to sufficiently attenuate a common mode signal. A pair of conductor paths (1A, 1B) are formed onJapan

2009/7/7★

2014/1/22

2029/7/7

JP5393786 (B2)

one side surface of a dielectric layer (3) in parallel. A floating ground (5) is formed on the other sidesurface of the dielectric layer (3) so as to face the conductor paths (1A, 1B). The floating ground(5) is not connected to a common ground (7) outside and is independent therefrom. A passive twoterminal circuit (CM1) consisting of a passive circuit element is connected between a connection
point (9) of the floating ground (5) and the common ground (7).

China

2009/7/7★

2015/3/18

2029/7/6

CN102577116 (B)sufficiently attenuate a common mode signal by passing an ultra-high speed differential signal
Common mode filter To
through an ultra-high speed differential transmission line. A common mode filter comprises: a pairJapan(2009/7/27)

2013/10/11

2029/7/26

JP5386586 (B2)USA

2010/7/21★

2014/12/30

2030/7/20

US8922303 (B2)

China

2010/7/21★

2014/9/3

2030/7/20

CN102422533 (B)of conductive lines formed on a first dielectric layer to transmit a differential signal; a plurality of firstdivided floating grounds in a state of being separated from an external ground potential, and facing
the conductive lines, with the first dielectric layer interposed between them, and formed by being
divided into a plurality of numbers in a length direction of the conductive lines, and forming a
distribution constant type differential transmission line for the differential signal, together with theconductive lines;; and a first passive two-terminal network connected between the first divided
floating grounds located at least at an input side or an output side of the first divided floating
grounds, and the external ground potential.

WO Publish

US2012098627 (A1)

Differential Signal Balancer (DSB) CDLD/CDLA TypeImproving P/N balance in the differential transmission line, absorbing common-mode noisein Ultra-High speed differential transmission line
■Appearance forms
CDLD 2 mm×1.25 mm■Features

CDLA 1.2 mm×1 mm

・Non-Magnetic materials applied products by Delay Line Technology
・Available for 10 ～ 28 Gbit/s transmission speed
・Improving P/N Line Balance in Differential Signal
・Absorbing radiative common-mode noise over GHz range■Example (1) Common-mode Removal (25 Gb/s) ■Structure
25 Gb/s Common-mode Noise Removing

25 Gb/s P/N Line Balance Improvement

Huge Noise Spectrum

Unexpected P/N UnbalanceComm Reflection : Dispersied in time domain with Round Trip time in Delay Line
Comm GND Return : Absorbed at resister in Absorbing Circuit
Diff P Line Signal
Comm Reflection Lo-f
Comm Reflection Hi-f
Output (P Line)

Input (P Line)

Delay Line

Delay Line
Comm GND Return

Comm GND Return
Common-mode
Absorbing Circuit(Invisible from Diff)

DSB Inserted
Enough Balanced

DSB Inserted
Enough Removing

Common-mode
Absorbing Circuit(Invisible from Diff)

Comm GND Return

Comm GND Return

Delay Line

Delay Line

Input (N Line)
H: 2 GHz/div, V: 1 mV/divOutput (N Line)

Comm Reflection Hi-f

H: 100 ps/div, V: 100 mV/div

Comm Reflection Lo-f

Diff N Line Signal■Example (2) Smaller Reflection than CMC (Common-mode Choke Coil)
Affection of Impedance Mismatch in 10 Gb/s, USB Type-C, 0.5 m Cable Transmission
No CMC nor DSB

CMC
VpCTLE

Vn

Type-C, 0.5 m*30 ps skew

50100

150

050

100

15075
50
250-25-50-75

50

100

050TX

Vn

Type-C, 0.5 m*30 ps skew

1501001507550250-25-50-75200

CTLERXVn50 ohms termination

050

150
100500-50-100-1500200

100150200

High Zo termination (Acceptable)

50100150200

Time [ps]Time [ps]Time [ps]Vp*DSBRX

High Zo termination (Huge Distortion)

150
100
500-50-100-150200CTLE* Actual measured S-Parameter

50 ohms termination

0200

High Zo termination (Huge Distortion)
Vp & Vn [% ]Vp & Vn [% ]

0150
100
500-50-100-150

TX

50 ohms termination

75
50250-25-50-75*CMCRX

Vp & Vn [% ]Vp & Vn [% ]Type-C, 0.5 m*
30 ps skew

Vp

Vp & Vn [% ]

Thru

TXDSB

* Actual measured S-Parameter

Vp & Vn [% ]* Actual measured S-Parameter■Example (3) 25 Gb/s PAM4 (6.25 GHz Clock) with Skew
CMC

P/N Waveform Plot

10.5

11.0

11.5

12.0

150
100500-50-100-150
10.0

10.5

Time [ns]20406080

100 120 140 160

Time [ps]

12.0

10.5

150
100
500-50-100-1500

20406080

100 120 140 160

Time [ps]

11.0

11.5

12.0

Time [ns]P/N Eye Diagram
Vp & Vn [%]Vp & Vn [%]11.5P/N Eye Diagram
Vp & Vn [%]011.0150100500-50-100-15010.0

Time [ns]P/N Eye Diagram
150100500-50-100-150

P/N Waveform Plot
Vp & Vn [%]150
100500-50-100-150
10.0DSB

P/N Waveform Plot
Vp & Vn [%]Vp & Vn [%]No CMC nor DSB

150
100500-50-100-150020406080100 120 140 160

Time [ps]About ELMEC CorporationCorp. is a world-wide leader in the industry of super-high speed passive
ELMEC Corporation ELMEC
comporments. Since 1981, ELMEC has kept the top supplier of Delay Lines, and M. Kameya

URL：http://www.elmec.co.jp(President/CEO) invents DSBs. ELMEC owns 10+ patents of DSB (Japan and International).