ON Semiconductor
Is Now

To learn more about onsemi™, please visit our website atwww.onsemi.com

onsemi andand other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.

Design and Application
Guide of Bootstrap Circuitfor High-Voltage Gate-Drive
IC
AND9674/D

www.onsemi.com

APPLICATION NOTEINTRODUCTION
The purpose of this paper is to demonstrate a systematic
approach to design high−performance bootstrap gate drive
circuitsforhigh−frequency,high−power,andhigh−efficiency switching applications using a power
MOSFET and IGBT. It should be of interest to powerelectronics engineers at all levels of experience. In the mostof switching applications, efficiency focuses on switchinglosses that are mainly dependent on switching speed.
Therefore, the switching characteristics are very importantin most of the high−power switching applications presented
in this paper. One of the most widely used methods to supply
power to the high−side gate drive circuitry of thehigh−voltage gate−drive IC is the bootstrap power supply.
This bootstrap power supply technique has the advantage ofbeing simple and low cost. However, it has some limitations,on time of duty−cycle is limited by the requirement torefresh the charge in the bootstrap capacitor and serious
problems occur when the negative voltage is presented at thesource of the switching device. The most popular bootstrap
circuit solutions are analyzed; including the effects ofparasitic elements, the bootstrap resistor, and capacitor; on
the charge of the floating supply application.

considered. This method is utilized as a gate drive andaccompanying bias circuit, both referenced to the source ofthe main switching device. Both the driver and bias circuit
swing between the two input voltage rails together with thesource of the device. However, the driver and its floating
bias can be implemented by low−voltage circuit elements
since the input voltage is never applied across theircomponents. The driver and the ground referenced control
signal are linked by a level shift circuit that must tolerate thehigh−voltage difference and considerable capacitive
switching currents between the floating high−side andground−referenced low−side circuits. The high−voltage
gate−drive ICs are differentiated by unique level−shift
design. To maintain high efficiency and manageable power
dissipation, the level−shifters should not draw any current
during the on−time of the main switch. A widely usedtechnique for these applications is called pulsed latch leveltranslators, shown in Figure 1.
Bootstrap Drive Circuit Operation

The bootstrap circuit is useful in a high−voltage gate
driver and operates as follows. When the VS goes below theIC supply voltage VDD or is pulled down to ground (thelow−side switch is turned on and the high−side switch isturned off), the bootstrap capacitor, CBOOT, charges throughthe bootstrap resistor, RBOOT, and bootstrap diode, DBOOT,
from the VDD power supply, as shown in Figure 2. This isprovided by VBS when VS is pulled to a higher voltage by thehigh−side switch, the VBS supply floats and the bootstrap
diode reverses bias and blocks the rail voltage (the low−sideswitch is turned off and high−side switch is turned on) fromthe IC supply voltage, VDD.

HIGH−SPEED GATE−DRIVER CIRCUITRYBootstrap Gate−Drive Technique

The focus of this topic is the bootstrap gate−drive circuit
requirements of the power MOSFET and IGBT in various
switching−mode power−conversion applications. Where
input voltage levels prohibit the use of direct−gate drive
circuits for high−side N−channel power MOSFET or IGBT,
the principle of bootstrap gate−drive technique can be

IN

PULSE GENERATORNOISECANCELLER

R
S

R
Q

Shoot−throughcurrent compensatedgate driver

VB
UVLO

HO

VS

Figure 1. Level−Shifter in High−Side Drive IC© Semiconductor Components Industries, LLC, 2017

August, 2021 − Rev. 3

1

Publication Order Number:AND9674/D

AND9674/D
RBOOT DBOOT

DC SUPPLY
HIN
t

VB
RG1

HO

VDD

Q1

VDD

V S −COM

ILOAD

CBOOT
VS

COM

RG2

LO

t

LOAD
Q2

Freewheeling−V S

Figure 4. VS Waveforms During Turn−off
Cause of Negative Voltage on VS Pin

Bootstrap charge current path

A well−known event that triggers VS go below COM(ground) is the forward biasing of the low−side freewheeling
diode, as shown in Figure 5.
Major issues may appear during commutation, just before
the freewheeling diode starts clamping.
In this case, the inductive parasitic elements, LS1 andLS2, may push VS below COM, more than as describedabove or normal steady−state condition.
The amplitude of negative voltage is proportional to theparasitic inductances and the turn−off speed, di/dt, of theswitching device; as determined by the gate drive resistor,
RGATE, and input capacitance, Ciss, of switching device.
It is sum of Cgs and Cgd, called Miller capacitance.

Bootstrap discharge current path

Figure 2. Bootstrap Power Supply Circuit
Drawback of Bootstrap Circuitry

COM

LO

High Side OFF

ifree

RG2

Q2

GND VS

CBOOT
A

RGATE

Q1
B

GND
−VS

iLOAD

LS1

C

C

LS2
D1

iFree

COUT

Figure 5. Step−Down Converter Applications

Freewheeling Path

CIN

VS

Ls1

LIN

VDC

VB

VDD HO

Q1

iLoad

Ls2

HIN

LIN

RG1
CBOOT

HIN

HO

HVIC

DBOOT
VB

VDD

IN

CDRV

RBOOT

DBOOT

INPUT

DC SUPPLY

VCC

Figure 3. Half−Bridge Application Circuits
www.onsemi.com
2

VOUT

The bootstrap circuit has the advantage of being simple
and low cost, but has some limitations.
Duty−cycle and on time is limited by the requirement torefresh the charge in the bootstrap capacitor, CBOOT.
The biggest difficulty with this circuit is that the negative
voltage present at the source of the switching device duringturn−off causes load current to suddenly flow in thelow−side freewheeling diode, as shown in Figure 3.
This negative voltage can be trouble for the gate driver’s
output stage because it directly affects the source VS pin of
the driver or PWM control IC and might pull some of theinternal circuitry significantly below ground, as shown in
Figure 4. The other problem caused by the negative voltage
transient is the possibility to develop an over−voltage
condition across the bootstrap capacitor.
The bootstrap capacitor, CBOOT, is peak charged by thebootstrap diode, DBOOT, from VDD the power source.
Since the VDD power source is referenced to ground, themaximum voltage that can build on the bootstrap capacitor
is the sum of VDD and the amplitude of the negative voltage
at the source terminal.

AND9674/D
shifter of the high−side gate driver suffers form a lack of theoperation voltage headroom. This should be noted, but
proves trivial in most applications, as the high−side in not
usually required to change state immediately following
a switching event.

VBS

B−Point

VDC + VGS, Miller

C−Point

VDC

OUTPUT

A−Point

INPUT

Figure 6 shows the waveforms of the high−side,N−channel MOSFET during turn−off.

Recovery Time
VGS = B−C Point

Figure 8. Waveforms in Case of Signal Missing
Figure 6. Waveforms During Turn−off
Consideration of Latch−up Problem

Effects in the Undershoot Spike on VS Pin

The most integrated high−voltage gate−drive ICs haveparasitic diodes, which, in forward or reverse break−down,
may cause parasitic SCR latch−up. The ultimate outcome oflatch−up often defies prediction and can range from
temporary erratic operation to total device failure. The
gate−drive IC may also be damaged indirectly by a chain of
events following initial overstress. For example, latch−up
could conceivably result in both output drivers assuminga HIGH state, causing cross−conduction followed by switch
failure and, finally, catastrophic damage to the gate−drive
IC. This failure mode should be considered a possibleroot−cause, if power transistors and/or gate−drive IC are
destroyed in the application. The following theoreticalextremes can be used to help explain the relationships
between excessive VS undershoot and the resulting latch−up
mechanism.
In the first case, an “ideal bootstrap circuit” is used inwhich VDD is driven from a zero−ohm supply with an ideal
diode feed VB, as shown in Figure 9. When the high current
flowing through freewheeling diode, VS voltage is below
ground level by high di/dt. This time, latch−up risk appears
since internal parasitic diode, DBS of the gate driverultimately enters conduction from VS to VB, causing theundershoot voltage to sum with VDD, causing the bootstrap
capacitor to overcharge, as shown Figure 10.
For example, if VDD = 15 V, then VS undershoot in excess
of 10 V forces the floating supply above 25 V, risking
breakdown in diode DBS and subsequent latch−up.

OUTPUT

INPUT

If undershoot exceeds the absolute maximum rating
specified in the datasheet, the gate drive IC suffers damage
or the high−side output is temporarily unresponsive to input
transition as shown in Figure 7 and Figure 8.
Figure 7 shows Latch−up case that the high−side output
does not changed by input signal. In this case, short−circuit
condition occur on external, main, high−side and low−sideswitches in half−bridge topology.

Figure 7. Waveforms in Case of Latch−up

Figure 8 shows Missing case that the high−side output
does not responded to input transition. In this case, the level

www.onsemi.com
3

AND9674/D
VB
VS
VB

VDD

VB below COM

DBS
COM

GND

VS

Gate Driver

Figure 12. VB and VS Waveforms of Case 2
Figure 9. Case 1: Ideal Bootstrap Circuits

A practical circuit is likely to fall somewhere between
these two extremes, resulting in both a small increase of VBS
and some VB droop below VDD, as shown in Figure 13.

VB
VS

VB
VS

HIGH VBSGND

VB close to COM

Figure 10. VB and VS Waveforms of Case 1

Increased VBS

Suppose that the bootstrap supply is replaced with theideal floating supply, as shown in Figure 11, such that VBS
is fixed under all circumstances. Note that using a low
impedance auxiliary supply in place of a bootstrap circuit
can approach this situation. This time, latch−up risk appears
if VS undershoot exceeds the VBS maximum specified indatasheet, since parasitic diode DBCOM ultimately entersconduction from COM to VB, as shown in Figure 12.

VCC

GND

Figure 13. Typical Response of VB and VS

Exactly which of the two extremes is prevalent can bechecked as follows. If the VS pins undershoot spike has
a time length that is on order of tenths of nanoseconds; thebootstrap capacitor, CBOOT, can become overcharged andthe high−side gate−driver circuit has damage byover−voltage stress because it exceeds an absolute
maximum voltage (VBSMAX) specified in datasheet. Design
to a bootstrap circuit, that does not exceed the absolute
maximum rating of high−side gate driver.

VB

Effect of Parasitic Inductances

The amplitude of negative voltage is:

VCC

DBCOM
COM

V S * COM + V FD1 * L S2

dI
dt

(eq. 1)

To reduce the slope of current flowing in the parasitic
inductances to minimize the derivative terms in Equation 1.

VS

Gate Driver

For example: If L/S MOSFET is FCP20N60, the negative
voltage spike between VS and ground is about −21 V in given
condition such as 0.2 A/ns dI/dt, 100 nH Parasitic inductance(LS2) and 10 A peak current of freewheeling. Actually,
0.7~0.9 V forward drop (VFD1) at 10 A forward current ofbody diode in FCP20N60 is negligeable.

Figure 11. Case 2: Ideal Floating Supply

www.onsemi.com
4

AND9674/D• ILKCAP = 0 (Ceramic Capacitor)• IQBS = 120 mA (Maximum)• ILK = 50 mA (Maximum)• QLS = 3 nC
• TON = 25 ms (Duty = 50% at fs = 20 kHz)• ILKDIODE = 10 mA

DESIGN PROCEDURE OF BOOTSTRAPCOMPONENTS
Select the Bootstrap Capacitor

The bootstrap capacitor (CBOOT) is charged every time
the low−side driver is on and the output pin is below the
supply voltage (VDD) of the gate driver. The bootstrap
capacitor is discharged only when the high−side switch isturned on. This bootstrap capacitor is the supply voltage(VBS) for the high circuit section. The first parameter to take
into account is the maximum voltage drop that we have toguarantee when the high−side switch is in on state. The
maximum allowable voltage drop (VBOOT) depends on theminimum gate drive voltage (for the high−side switch) tomaintain. If VGSMIN is the minimum gate−source voltage,
the capacitor drop must be:
V BOOT + V DD * V F * V GSMIN

where:VDD
VF

If the maximum allowable voltage drop on the bootstrap
capacitor is 1.0 V during the high side switch on state, theminimum capacitor value is calculated by Equation 3.
Q Total + (98
10 *9) ) (10010 *9 ) 120
10 *6 ) 50
10 *6
) 10
10 *6)(25
10 *6) ) (310 *9)(eq. 5)+ 105.5
10 *9[C]The value of bootstrap capacitor is calculated as follows:(eq. 2)C BOOT +The value of bootstrap capacitor is calculated by:
Q TOTAL
ΔV BOOTDV BOOT +(eq. 3)

Q TOTALC BOOT

100 nF å DV BOOT + 1.06[V]where QTOTAL is the total amount of the charge supplied by
the capacitor.

150 nF å DV BOOT + 0.7[V](eq. 7)220 nF å DV BOOT + 0.48[V]The total charge supplied by the bootstrap capacitor is
calculated by equation 4:

570 nF å DV BOOT + 0.19[V]Q TOTAL + Q GATE ) (I LKCAP ) I LKGS ) I QBS ) I LK ) I LKDIODE)t ON ) Q LS

(eq. 6)The voltage drop due to the external diode is nearly 0.7 V.
Assume the capacitor charging time is equal to the high−side
on−time (duty cycle 50%). According to different bootstrap
capacitor values, the following equation applies:= Supply voltage of gate driver [V]; and= Bootstrap diode forward voltage drop [V]C BOOT +Q TOTAL
105.5 10 *9+` 106[nF]1
ΔV BOOT

Suggested values are within the range of 100 nF ~ 570 nF,
but the right value must be selected according to theapplication in which the device is used. When the capacitor
value is too large, the bootstrap charging time slows and thelow−side on time might be not long enough to reach thebootstrap voltage.

(eq. 4)

where:QGATEILKGSILKCAP
IQBS
ILK
QLS

= Total gate charge;= Switch gate−source leakage current;= Bootstrap capacitor leakage current;= Bootstrap circuit quiescent current;= Bootstrap circuit leakage current;= Charge required by the internal level
shifter, which is set to 3 nC for all HVgate drivers;tON= High−side switch on time; andILKDIODED = Bootstrap diode leakage current.

Select the Bootstrap Resistor

When the external bootstrap resistor is used, theresistance, RBOOT, introduces an additional voltage drop:
V RBOOT +I CHARGER BOOTt CHARGE(eq. 8)where:ICHARGE = Bootstrap capacitor charging current;
RBOOT = Bootstrap resistance; andtCHARGE = Bootstrap capacitor charging time(the low−side turn−on time).

The capacitor leakage current is important only if anelectrolytic capacitor is used; otherwise, this can beneglected.
For example: Evaluate the bootstrap capacitor value whenthe external bootstrap diode used.
• Gate Drive IC = FAN7382 (ON Semiconductor)• Switching Device = FCP20N60 (ON Semiconductor)• Bootstrap Diode = UF4007• VDD = 15 V
• QGATE = 98 nC (Maximum)• ILKGS = 100 nA (Maximum)

Do not exceed the ohms (typically 5~10 W) that increase
the VBS time constant. This voltage drop of bootstrap diodemust be taken into account when the maximum allowable
voltage drop (VBOOT) is calculated. If this drop is too highor the circuit topology does not allow a sufficient charging
time, a fast recovery or ultra−fast recovery diode can beused.

www.onsemi.com
5AND9674/D
CONSIDERATION OF BOOTSTRAPAPPLICATION CIRCUITS

Figure 15. The bootstrap resistor, RBOOT, provides current
limit only during a bootstrap charging period which
represents when the VS goes below the IC supply voltage,
VCC, or is pulled down to ground (the low−side switch isturned on and the high−side switch is turned off). The
bootstrap capacitor, CBOOT, charge through the bootstrap
resistor, RBOOT, and diode, DBOOT, from the VCC power
supply. The bootstrap diode must have a break−downvoltage (BV) larger than VDC and a fast recovery time tominimize the amount charge feedback from the bootstrap
capacitor to VCC power supply.

Bootstrap Startup Circuit

HIN

HO

COM

VS

RBOOT DBOOT

HIN
LIN

DZ
RGATE

C1

VCC

VB

HIN

HO

LIN

VS

Q1

CBOOT

R2
Q2

R3

COM LO

Load

Figure 15. Adding a Series Resistor with DBOOTThis method has the advantage of being simple forlimiting the current when the bootstrap capacitor is initiallycharged, but it has some limitations. Duty−cycle is limitedby the requirement to refresh the charge in the bootstrap
capacitor, CBOOT, and there are startup problems. Do not
exceed the ohms (typically 5∼10 W) that would increase the
VBS time constant. The minimum on−time for charging thebootstrap capacitor or for refreshing its charge must be
verified against this time constant. The time constantdepends on the values of bootstrap resistance, capacitance,and duty cycle of switching device calculated in following
equation:
t+

Q1
L
D

R1

R4

C BOOTR BOOTD[s](eq. 9)where RBOOT is the bootstrap resistor; CBOOT is thebootstrap capacitor; and D is the duty cycle.

VOUT

VB

VDC

VCC

VDC

COUT

VDD

RSTART

RBOOT DBOOT

CBOOT

INPUT

VDD

DSTART

The bootstrap circuit is useful in high−voltage gate driver,as shown in Figure 1. However, it has a initial startup andlimited charging a bootstrap capacitor problem when thesource of the main MOSFET (Q1) and the negative bias
node of bootstrap capacitor (CBOOT) are sitting at the output
voltage. Bootstrap diode (DBOOT) might be reverse biased
at startup and main MOSFET (Q1) has a insufficientturn−off time for the bootstrap capacitor to maintaina required charge, as shown in Figure 1.
In certain applications, like in battery chargers, the output
voltage might be present before input power is applied to theconverter. Delivering the initial charge to the bootstrap
capacitor (CBOOT) might not be possible, depending on thepotential difference between the supply voltage (VDD) andoutput voltage (VOUT) levels. Assuming there is enoughvoltage differential between input voltage (VDC) and output
voltage (VOUT), a circuit comprised of startup resistor(RSTART), startup diode (DSTART), and Zener diode (DZ) cansolve the problem, as shown in Figure 14. In this startup
circuit, startup diode DSTART serves as a second bootstrap
diode used for charging the bootstrap capacitor (CBOOT) at
power up. Bootstrap capacitor (CBOOT) is charged to theZener diode of DZ, which is supposed to be higher than thedriver’s supply voltage (VDD) during normal operation. The
charge current of the bootstrap capacitor and the Zenercurrent are limited by the startup resistor. For best efficiency,
the value of startup resistor should be selected to limit thecurrent to a low value, since the bootstrap path through thestartup diode is permanently in the circuit.

t+

R BOOTC BOOT
D+

10x1 *6+ 100 [ms]0.1

(eq. 10)

Even with a reasonably large bootstrap capacitor andresistor, the time constant may be large. This method canmitigate the problem. Unfortunately, the series resistor does
not provide a foolproof solution against an over voltage andit slows down the recharge process of the bootstrap
capacitor.

Figure 14. Simple Bootstrap Startup Circuit
Resistor in Series with Bootstrap DiodeIn the first option, the bootstrap circuit includes a small
resistor, RBOOT, in series with bootstrap diode, as shown in

www.onsemi.com
6

AND9674/D
Resistor Between VS and VOUT

VCC

In the second option, the bootstrap circuit includes a small
resistor, RVS, between VS and VOUT, as shown in Figure 16.
Suggested values for RVS are in the range of some ohms.
VCC

CDRV

CDRV

HVIC

IN

VCC

VB

CBOOT

HO

RVS

GND VS

CBOOT

Q1
VOUT

RGATE

L1
DSCHT

Q1

RGATE

GND VSVB

VCC HORBOOT DBOOT
IN

HVIC

VCC

IN

IN

VDC

DBOOT

D1

COUT

VOUT
D1

Figure 18. Clamping Structure

L1
COUT

Relocated Gate Resistor; Double Purpose

The gate resistor sets the turn−on and turn−off speeds in
the MOSFET and provides current limiting for the Schottky
diode during the negative voltage transient of the source
terminal of the main switch. In additional, the bootstrap
capacitor is protected against over voltage by the two diodes
connected to the ends of CBOOT. The only potential hazard
by this circuit is that the charging current of the bootstrap
capacitor must go through gate resistor. The time constant of
CBOOT and RGATE slows the recharge process, which might
be a limiting factor as the PWM duty cycle.
The fourth options includes relocating a gate resistor
between VS and VOUT and a clamp device should bepositioned between ground and VS, as shown in Figure 19,
where a Zener diode and a 600 V diode are placed. The Zener
voltage must be sized according to the following rule:Figure 16. Adding RVS in Bootstrap Circuit

The RVS works as, not only bootstrap resistor, but alsoturn−on and turn−off resistors, as shown in Figure 17. The
bootstrap resistor, turn−on, and turn−off resistors arecalculated by the following equations:R BOOT *+ R BOOT ) R VS

(eq. 11)

R ON *+ R GATE ) R VS

(eq. 12)R OFF *+ R GATE ) R VS

(eq. 13)VCC
RBOOT DBOOT

CDRV

IN
VCC
GND

HO

IBCHG

RVS

D1

L1

IN

IN

COUT

Figure 17. Current Paths of Turn−on and Turn−off

VDC

DBOOT

HVIC

ITURN−OFF

VCC

VOUT

VS

VDD
GND

VB
CBOOT
HO
VS

RGATE
DZ

Clamping Diode for VS and Relocation Gate Resistor

D2

In the third option, the bootstrap relocates a gate resistor
between VS and VOUT and adds a low forward−voltage drop
Schottky diode from ground to VS, as shown in Figure 18.
The difference between VB and VS should be kept inside theabsolute maximum specification in the datasheet and mustbe satisfied by the following equation:
V B * V S t V BS_abs max(eq. 15)

V B * V S t V BS, ABSMAX

ITURN−ON
Q1

CDRV

IN

VB

Q1
VOUT
L1

D1

COUT

Figure 19. Clamping Structure with Zener Diode(eq. 14)www.onsemi.com
7AND9674/D
CHOOSE CURRENT CAPABILITY HVIC
The approximate maximum gate charge QG that can beswitched in the indicated time for each driver current rating
is calculated in Table 1:b. Sinking Current Capability (Turn−off)
I SINK w 1.5= MOSFET gate charge at
VGS = VDD;tSW_ON/OFF = MOSFET switch turn−on / turn−off
time; and
1.5
= empirically determined factor(influenced by delay through thedriver input stages and parasitic
elements).

Switching Time (tSW_ON/OFF)
100 ns2A

133 nC

67 nC

4A

267 nC133 nC

9A

600 nC

300 nC

50 ns

Maximum Gate Charge (QG,MAX)GATE RESISTOR DESIGN PROCEDURE
The switching speed of the output transistor can becontrolled by values of turn−on and turn−off gate resistors
controlling the turn−on and turn−off current of gate driver.
This section describes basic rules for values of the gate
resistors to obtain the desired switching time and speed byintroducing the equivalent output resistor of the gate driver.
Figure 20 shows the equivalent circuit of gate driver andcurrent flow paths during the turn−on and turn−off,including a gate driver and switching devices.

1. For a single 4 A, parallel the two channels of a dual 2 A!

For example, a switching time of 100 ns is:
1 % of the converter switching period at 100 kHz;
3 % of the converter switching period at 300 kHz; etc.
1. Needed gate driver current ratings depend on whatgate charge QG must be moved in switching timetSW−ON/OFF (because average gate current duringswitching is IG):
I G.AV.SW +QG
T sw_on ń off

VDC(eq. 16)

HVIC

2. The maximum gate charge, QG, is read from the
MOSFET datasheet.

t SW [Joules]

VDD(eq. 17)QG
t SW, ON

1Turn−OffLO

ON

RDRV(OFF)

dVOUT
dt
VOUT

OFF

GND

RG(ON)

Cgd
1

Cds
2

RG(OFF)

dVOUT
dt

Cgs

(eq. 18)

where VDS and ID are maximum values during theswitching interval.
4. The approximate current drive capability of gate
driver may be calculated like below
a. Sourcing Current Capability (Turn−on):
I SOURCE w 1.5

RGATE

Cgs

DRIVER

ID

HO

Cgd
2

VS

If channel (V−I) switching loss is dominated by one
switching transition (turn−on or turn−off), size thedriver for that transition. For clamped inductive
switching (the usual case), channel switching loss
for each transition is estimated as:
E SW + 0.5 V DSRDRV(ON)

Turn−OnOFF

VDD

t SWON, OFF + 0.02

ON
DRIVER

VBS

VB

If the actual gate−drive voltage VGS is different fromthe test condition in the specifications table, use the
VGS vs. QG curve instead. Multiply the datasheet
value by the number of MOSFETs in parallel.
3. tSW_ON/OFF is how fast the MOSFET should beswitched. If unknown, start with 2% of the switching
period tSW:
0.02
t SW +
f SW(eq. 20)

where:QG

Table 1. EXAMPLE HVIC CURRENT−DRIVECAPABILITY
NeededCurrent
RatingQG
t SW, OFF

Figure 20. Gate Driver Equivalent Circuit

Figure 21 shows the gate−charge transfer characteristics
of switching device during turn−on and turn−off.

(eq. 19)

www.onsemi.com
8

ID

TSW

90%

90%
VGG

Vg1

VGS
Vg1

Vg2

Vg2

10%

10%

TD(ON) tR

TD(OFF) tF

The following describes how to size the turn−off resistor
when the output dv/dt is caused by the companion MOSFET
turning−on, as shown in Figure 22.
For this reason, the off−resistance must be sized according
to the application worst case. The following equation relates
the MOSFET gate threshold voltage to the drain dv/dt:
VDC
HVIC

ON

Sizing the Turn−On Gate Resistor

RGATE 2

HO

1
dVOUT
dt

Cgs

OFF

Turn−on gate resistor, Rg(ON), can be chosen to obtain thedesired switching time by using switching time, tsw. To
determine a value of resistor using the switching time,
supply voltage, VDD (or VBS), equivalent on resistance(RDRV(ON)) of the gate driver, and switching device
parameters (Qgs, Qgd, and Vgs(th)) are needed.
The switching time is defined as the time spent to reach theend of the plateau voltage (a total Qgs + Qgd has been
provided to the MOSFET gate), as shown in Figure 21.
The turn−on gate resistor calculated as follows:

VS

ILOAD

VDD

Turn−Off
Cgd

VDD

OFF
DRIVERI g(avr) +Cgd

RDRV(ON)

DRIVER

Figure 21. Gate Charge Transfer Characteristics

Q gs ) Q gd

Turn−On

VB

Q[nC]

Load

TOFF_Discharge

VBS

VDS

TON_Charge

VGS − Gate−Source Voltage [V]VDS − Drain−Source Voltage [V]AND9674/D

RG(ON)LO

RDRV(OFF)ON

RG(OFF)

Cds
Cgs

GND

(eq. 21)t SW

V DD ) V gs
R TOTAL + R g(ON) ) T DRV(ON) +Ig(avr)Figure 22. Current Paths: Low−Side Switch
Turned Off, High−Side Switch Turned On(eq. 22)

Ǌ

where Rg(ON) is the gate on resistance and RDRV(ON) is thedriver equivalent on resistance.

ǋ

V gs(th) w (R g(OFF) ) R DRV(OFF))ig+ (R g(OFF) ) R (drv)

dV out
dt

Ǌ

C gd

ǋ

(eq. 25)

Output Voltage Slope

Turn−on gate resistor Rg(ON) can be determined by control
output slope (dVOUT/dt). While the output voltage has
a non−linear behavior, the maximum output slope can beapproximated by:
I g(avr)dV OUT+dt
C gd(off)

Rearranging the equation yields:
C gd(eq. 23)

V DD * V gs(th)C gd(off)dV OUTdt

dV outdt* R (drv)(eq. 26)

Design Example

Determine the turn−on and off gate resistors using the
ON Semiconductor MOSFET with FCP20N60 and gate
driver with FAN7382. The power MOSFET of FCP20N60
parameters are as follows:

Inserting the expression yielding Ig(avr) and rearranging:
R TOTAL +V gs(th)R g(off) v(eq. 24)

Q gs + 13.5 nC, Q gd + 36 nC, C gd + 95pF,

where Cgd(off) is the Miller effect capacitor, specified as Crssin the datasheet.

V GS(th) + 5 V, V GS(th)MIN + 3 V(eq. 27)

Turn−On Gate Resistance
1. If the desired switching time is 500 ns at VDD = 15 V,
the average gate charge current is calculated as:

Sizing the Turn−Off Gate Resistor

The worst case in sizing the turn−off resistor is when thedrain of the MOSFET in turn−off state is forced tocommutate by external events.
In this case, dV/dt of the output node induces a parasitic
current through Cgd flowing in RG(OFF) and RDRV(OFF), as
shown in Figure 22.

I g(avr) +Q gs ) Q gd
t SW

R Total +www.onsemi.com
9+36 nC ) 13.5 nC
ns + 99 [mA] (eq. 28)
500

V DD ) V gs(th)I g(avr)+

15 * 5+ 101 [W]99 mA

(eq. 29)

AND9674/D
R DRV(ON) +V DD

I SOURCE+

15 V+ 43 [W]350 mA1(eq. 30)
C LOAD =4400PF

The turn−on resistance value is about 58 Ω.
2. If dVout/dt = 1 V/ns at VDD = 15 V, the total gate
resistor is as calculated as:
V DD * V GS(th)15 * 595x10 *12x10 9(eq. 31)

V DD
15 V
+
+ 43 [W]I SOURCE
350 mA(eq. 32)

C gd(off)

R DRV(ON) +dV outdt+

Power [W]

R Total +C LOAD =2200PFC LOAD =470PF

The turn−on resistance value is about 62 Ω.

0.01

Turn−Off Gate ResistanceIf dVout/dt = 1 V/ns, the turn−off gate resistor is calculatedas:
R DRV(OFF) +R g(off) v

V gs(th)minC gd

dV out
dt

V DD
15 V
+
[ 23[W]
I SINK
650 mA* R (drv) +0.1(eq. 33)

Gate Driver Power Dissipation

The total power dissipation is the sum of the gate driver
losses and the bootstrap diode losses. The gate driver losses
are comprised of the static and dynamic losses related to theswitching frequency, output load capacitance on high− andlow−side drivers, and supply voltage, VDD.
The static losses are due to the quiescent currents from thevoltage supplies VDD and ground in low−side driver and theleakage current in the level shifting stage in high−side driver,which are dependent on the voltage supplied on the VS pin
and proportional to the duty cycle when only the high−sidepower device is turned on.
The dynamic losses are defined as follows: In thelow−side driver, the dynamic losses are due to two different
sources. One is due to whenever a load capacitor is charged
or discharged through a gate resistor, half of energy that goes
into the capacitance is dissipated in the resistor. The losses
in the gate drive resistance, internal and external to the gate
driver, and the switching loss of the internal CMOS
circuitry. Also, the dynamic losses of the high−side driver
have two different sources. One is due to the level−shifting
circuit and one due to the charging and discharging of thecapacitance of the high side. The static losses are neglected
here because the total IC power dissipation is mainly
dynamic losses of gate drive IC and can be estimated as:
2

V DD [W]

100

1000

The bootstrap circuit power dissipation is the sum of thebootstrap diode losses and the bootstrap resistor losses if any
exist. The bootstrap diode loss is the sum of the forward bias
power loss that occurs while charging the bootstrap
capacitor and the reverse bias power loss that occurs during
reverse recovery. Since each of these events happens once
per cycle, the diode power loss is proportional to switchingfrequency. Larger capacitive loads require more current torecharge the bootstrap capacitor, resulting in more losses.
Higher input voltages (VDC) to the half−bridge result inhigher reverse recovery losses. The total IC power
dissipation can be estimated by summing the gate driver
losses with the bootstrap diode losses, except bootstrap
resistor losses.
If the bootstrap diode is within the gate driver, add anexternal diode in parallel with the internal bootstrap diodebecause the diode losses can be significant. The external
diode must be placed close to the gate driver to reduceparasitic series inductance and significantly lower forward
voltage drop.

3* 23 + 8.6
95x10 *12x10 9

fs

10

Figure 23. Gate Driver Total Power Dissipation(eq. 34)

CL1

Switching frequency [kHz]POWER DISSIPATION CONSIDERATIONSP DGATE + 2

C LOAD =1000PF

0.1

Package Thermal ResistanceThe circuit designer must provide:• Estimate power dissipation of gate driver package• The maximum operating junction temperature
TJ, MAX,OPR, e.g., 120°C for these drivers if derated to
80% of TJ,MAX =150°C• Maximum operating lead temperature TL,MAX,OPR,
approximately equal to the maximum PCB temperature
underneath the driver, e.g., 100°C• Maximum allowable junction−to−lead thermal resistanceis calculated by:(eq. 35)

Figure 23 shows the calculated gate driver power
dissipation versus frequency and load capacitance at VDD =15 V. This plot can be used to approximate the power losses
due to the gate driverq JL, max +www.onsemi.com
10

T J, max ) T L, max
R PKG(eq. 36)

AND9674/D
GENERAL GUIDELINES
Printed Circuit Board Layout

Bootstrap Components

The layout for minimized parasitic inductances is asfollows:• Direct tracks between switches with no loops or deviation• Avoid interconnect links. These can add significant
inductance• Reduce the effect of lead−inductance by lowering
package height above the PCB• Consider co−locating both power switches to reduce track
length• Placement and routing for decoupling capacitor and gate
resistors as close as possible to gate drive IC• The bootstrap diode as close as possible to bootstrap
capacitor

The bootstrap resistor (RBOOT) must be considered insizing the bootstrap resistance and the current developed
during initial bootstrap charge. If the resistor is needed inseries with the bootstrap diode, verify that VB does not fall
below COM (ground), especially during startup andextremes of frequency and duty cycle.
The bootstrap capacitor (CBOOT) uses a low−ESR
capacitor, such as ceramic capacitor. The capacitor from
VDD to COM supports both the low−side driver andbootstrap recharge. A value at least ten times higher than thebootstrap capacitor is recommended.
The bootstrap diode must use a lower forward voltage
drop and switching time as soon as possible for fast recovery,such as ultra−fast.

Table 2. SUMMARY OF HIGH−SIDE GATE DRIVE CIRCUITRY
MethodBasic Circuit

Advantages & Limitations

HIGH−SIDE GATE DRIVERS FOR P−CHANNEL
VCC
Q1

OUT

VOUT
L1

D1

RPULL

VCC

RGATE

GND

VOUT

VDC

VCC

OUT

COUT

GND

Open Collector
PWM
Controller

Can be implemented if the maximum input voltage isless than the gate−to−source break down voltage ofthe device

RGATE

VCC

Simple method, but is not suitable for driving
MOSFET directly in a high−speed application

Q1
VOUT
L1

D1

COUT

PWM
Controller

Direct Drive

VOUT

VDC

PWM
Controller

VCC

VOUT

R2

VCC

Suitable for high−speed application and works
seamlessly with regular PWM controller

R1

OUT

COUT

RBASE

Level−Shifted Drive

L1

D1

VOUT

GND

HIGH−SIDE GATE DRIVERS FOR N−CHANNEL

VOUT
L1

D1

V CC t V GS, MAX and V DC t V CC * V GS, Miller

VOUT

VDC
Floating
Supply
Opto

RGATE

VCC
HO

COUT

DSCHT

PWM
Controller

GND

Easiest high−side application the MOSFEF and canbe driven directly by the PWM controller or by aground referenced driver, but it must meet two
conditions, as follows:

Q1

VCC

Cost impact of isolated supply is significant.
Opto−coupler tends to be relatively expensive,
limited in bandwidth, and noise sensitive

Q1
VOUT

LO

RGATE

L1
Q2

COUT

PWM
Controller

Floating Supply Gate
Drive

VCC
OUT

VDC
RGATE

VCC

Direct Drive

VOUT

GND

www.onsemi.com
11

AND9674/D
Table 2. SUMMARY OF HIGH−SIDE GATE DRIVE CIRCUITRY (continued)
MethodBasic Circuit

Advantages & Limitations

HIGH−SIDE GATE DRIVERS FOR N−CHANNEL

VOUT
RGATE

OUT1
OUT2

Gives full gate control for an indefinite period of time,
but is somewhat limited in switching performance.
This can be improved with added complexity

Q1

T1 RGATE

L1

COUT

VCC
PWM
Controller

VDC

CBLOCK

VCC

Transformer Coupled
Drive

VOUT

GND
VCC

VDC

VCC
OUT

The turn−on times tend to be long for switching
applications. Inefficiencies in the voltage
multiplication circuit may require more than low
stages of pumping

Q1

CDRV

IN

VB

VCC

HO

GND

VS

VOUT

VDC

DBOOT
HVIC

IN

L1

Simple and inexpensive with limitations; such as, theduty cycle and on−time are both constrained by theneed to refresh the bootstrap capacitor.
Requires level shift, with the associated difficulties

Q1

RGATE
D1

L1
COUT

VCC

Bootstrap Drive

D1

COUT

VOUT
GND

CBOOT

PWM
Controller

Charge Pump Drive

VOUT

www.onsemi.com
12

AND9674/D
Consideration Points of Bootstrap Circuit Problem

A−Point

VCC

VBS

DBOOT
B−Point

VDC
IN
HVIC
VCC

HO

VBS = (VCC + VFBD) − (−VS)

A

RGATE

CDRV

Q1

B

VS

Recovery Time
VGS = B − C
Point
i LOAD

LS1
GND

VDC

C−Point

VB
CBOOT

INPUT

VDC + VGS, Miller

C

C
LS2

GND
−VS

D1

i FreeCOUT

Negative voltage transient
at high−side switch turn−off

If Vs goes significantly below
ground, the gate driver canhave serious troubles
The amplitude of the negative voltage is proportional
parasitic inductances and the turn−off speed (di/dt) of
the switching device, Q1, which is determined by gate
resistor, RGATE, and input capacitance, CISS

Figure 24.

www.onsemi.com
13

Latch−up,propagation signal
missing and over−voltage across thebootstrap
capacitor

AND9674/D
Remedies of Bootstrap Circuit Problem

Figure 25.

ON Semiconductor andare trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are notdesigned, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, andexpenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if suchclaim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com◊

TECHNICAL SUPPORTNorth American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910

www.onsemi.com
14

Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative