CAQS-SPO201-DR4CZ 200GBASE-DR4 QSFP56 Optical Transceiver Module R01

200GBASE-DR4 QSFP56 Optical Transceiver ModuleCAQS-SPO201-DR4CZFeaturesHot-pluggable QSFP56 form factor

Built-in 200G PAM4 DSP

Supports 212.5Gb/s aggregate bit rates



Low power dissipation < 5.5W

RoHS 2.0 compliant (lead-free)Commercial case temperature range of 0℃ to 70℃

Single 3.3V power supply

Maximum link length of 500m ~ 2km over SMF

Uncooled 4 channels 1310nm EML



4 channels PIN photo detector array

200GAUI-4 electrical interface

Single MPO12 receptacle with 8° APC

CMIS V4.0 compliant

Built-in digital diagnostic functionality

Applications
IEEE 802.3bs200GBASE-DR4 Ethernet (PAM4)

Description
CA OPTROGROUP CAQS-SPO201-DR4CZ 200GE QSFP56 Optical Transceiver modules aredesigned for using in 200 Gigabit Ethernet links over single-mode fiber. They are compliant with theQSFP MSA and with IEEE 802.3bs 200GBASE-DR4 specification. Digital diagnostics functions areavailable via the I2C interface as specified by CMIS V4.0. The transceiver is RoHS 2.0 compliant andlead-free per Directive 2011/65/EU.

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1CAQS-SPO201-DR4CZ 200GBASE-DR4 QSFP56 Optical Transceiver Module R01

Figure 1. Module Block Diagram

Absolute Maximum Ratings
Parameter

SymbolMinMax

Unit

Supply Voltage

Vcc

-0.3

3.6

V

Input Voltage

Vin-0.3

Vcc+0.3

V

Storage Temperature

Ts-2085℃

Case Operating Temperature

Tc

070℃

Humidity (non-condensing)

Rh

585%

Recommended Operating Conditions
Parameter

SymbolMin

TypicalMax

Unit

Supply Voltage

Vcc

3.13

3.3

3.47

V

Operating Case Temperature

Tc

070℃

Baud Rate per Lane (PAM4)

fd

Power Dissipation

Pm

Fiber Bend Radius

Rb

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26.5625

GBaud/s5.53

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Electrical Specifications
Parameter

SymbolMin

TypicalMax

Unit

Differential Input ImpedanceZin

90100110ohm

Differential Output ImpedanceZout

90100110ohm

Differential Input Voltage Amplitude

ΔVin300900mVpp

Differential Output Voltage Amplitude

ΔVout

300900mVpp

Bit Error Rate Note2

BER

Input Logic Level HighVIH

2.0VccV

Input Logic Level Low

VIL00.8

V

Output Logic Level HighVOH

Vcc-0.5

Vcc

V

Output Logic Level Low

VOL00.4

VMax

Unit

1317.5nm

2.4E-4Note:
Note2. Compliant with 200GBASE-DR4 electrical specification in IEEE802.3bs standard.

Optical Characteristics
Parameter

SymbolMin

TypicalTransmitterλc1304.5Side-mode suppression ratio

SMSR

30

Average Launch Power (each lane)

Pout-5.1

Launch power in OMAouter minus TDECQ

Ptdecq-4.4

Transmitter and dispersion eye closure (each lane)

TDECQ

3.4dB

Average launch power of off transmitter(each lane)

Poff-30dBm

Outer Extinction Ratio

ERCenter Wavelength

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nm
4dBm
dBm

3.5

dB

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Parameter

Symbol

Optical Return Loss Tolerance

ORLTMinTypicalMax

Unit

21.4

dB

1317.5nm

ReceiverCenter Wavelength

λc1304.5

Damage threshold

Rdam

4

Average Receive Power (each lane)
Input (each lane)

Pin-8.1dBm
3dBm

Receiver Power (OMAouter) (each lane) Note3

OMAout2.8

dBm

Stressed Receiver Sensitivity (OMAouter) (each lane)

Sens-4.1

dBm

Receiver Sensitivity (OMAouter) (each lane) Note4

Sen-6.6dB

Note:
Note3. Measured with conformance test signal at TP3 for the BER specified in section 138.1.1 of IEEE 802.3cd.
Note4. Measured with conformance test signal at TP3 for the BER specified in section 138.1.1 of IEEE 802.3cd.

Pin Description
PinLogicSymbol

1Name/Description

GND

Module GroundNote52

CML-I

Tx2-Transmitter inverted data input

3CML-ITx2+

Transmitter non-inverted data input

GND

Module Ground Note5

45CML-I

Tx4-

Transmitter inverted data input

6CML-I

Tx4+

Transmitter non-inverted data input

GND

Module GroundNote578

LVTTL-I

MODSEIL

Module SelectNote69

LVTTL-I

ResetL

Module ResetNote6

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CAQS-SPO201-DR4CZ 200GBASE-DR4 QSFP56 Optical Transceiver Module R01

PinLogic

10SymbolName/Description

VCCRx+3.3V Receiver Power Supply

11

LVCMOS-I

SCL2-wire Serial interface clockNote612LVCMOS-I/O

SDA

2-wire Serial interface dataNote6

GND

Module GroundNote51314

CML-O

RX3+

Receiver non-inverted data output

15CML-O

RX3-

Receiver inverted data output

GND

Module GroundNote51617

CML-O

RX1+

Receiver non-inverted data output

18

CML-O

RX1-

Receiver inverted data output

19

GND

Module GroundNote5

20

GND

Module GroundNote5

21

CML-O

RX2-

Receiver inverted data output

22

CML-O

RX2+

Receiver non-inverted data output

GND

Module GroundNote52324

CML-O

RX4-

Receiver inverted data output

25

CML-O

RX4+

Receiver non-inverted data output

GND

Module GroundNote52627

LVTTL-O

ModPrsL

28

LVTTL-O

IntL

Module Present, internal pulled down to GND
Interrupt output, should be pulled up on host board229

VCCTx+3.3V Transmitter Power Supply

30

VCC1+3.3V Power Supply

LPModeLow Power ModeNote631

LVTTL-I

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PinLogic

32

SymbolName/Description

GND

Module GroundNote533

CML-I

Tx3+Transmitter non-inverted data input

34

CML-I

Tx3-

Transmitter inverted data input

GND

Module GroundNote5

35
36

CML-I

Tx1+

Transmitter non-inverted data input

37

CML-I

Tx1-

Transmitter inverted data input

GND

Module GroundNote5

38

Note:
Note5. Module circuit ground is isolated from module chassis ground within the module.
Note6. Open collector should be pulled up with 4.7K to 10K ohms on host board to a voltage between 3.15V and3.6V.

Figure 2. Electrical Pin-out Details

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ModSelL Pin
The ModSelL is an input pin. When held low by the host, the module responds to 2-wire serial communicationcommands. The ModSelL allows the use of multiple QSFP modules on a single 2-wire interface bus. When theModSelL is "High", the module will not respond to any 2-wire interface communication from the host. ModSelL
has an internal pull-up in the module.

ResetL Pin
Reset. LPMode_Reset has an internal pull-up in the module. A low level on the ResetL pin for longer than theminimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to theirdefault state. Module Reset Assert Time (t_init) starts on the rising edge after the low level on the ResetL pin isreleased. During the execution of a reset (t_init) the host shall disregard all status bits until the module indicatesa completion of the reset interrupt. The module indicates this by posting an IntL signal with the Data_Not_Readybit negated. Note that on power up (including hot insertion) the module will post this completion of reset interrupt
without requiring a reset.

LPMode Pin
CA OPTRONICS GROUP QSFP28 modules operate in the low power mode (less than 1.5 W power
consumption). This pin active high will decrease power consumption to less than 1W.

ModPrsL Pin
ModPrsL is pulled up to Vcc on the host board and grounded in the module. The ModPrsL is asserted "Low"when the module is inserted and deasserted "High" when the module is physically absent from the hostconnector.

IntL Pin
IntL is an output pin. When "Low", it indicates a possible module operational fault or a status critical to the hostsystem. The host identifies the source of the interrupt by using the 2-wire serial interface. The IntL pin is an opencollector output and must be pulled up to Vcc on the host board.

Power Supply Filtering
The host board should use the power supply filtering shown in Figure 3.

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CAQS-SPO201-DR4CZ 200GBASE-DR4 QSFP56 Optical Transceiver Module R01

Figure 3. Host Board Power Supply Filtering

DIAGNOSTIC MONITORING INTERFACE
Digital diagnostics functions are available via the I2C interface as specified by CMIS V4.0. The CMIS
management memory is shown in Figure 4.

Due to eight-bit addresses, the management memory is divided in Lower Memory (addresses 00h through 7Fh)and Upper Memory (addresses 80h ~ FFh).

The addressing structure of the additional internal management memory is shown in Figure 5. The
management memory is arranged as a unique and always host accessible address space of 128 bytes (LowerMemory) and as multiple upper address subspaces of 128 bytes each (Pages), only one of which is selected as
host visible in Upper Memory. A second level of Page selection is possible for Pages for which several
instances exist (e.g. where a bank of pages with the same Page number exists).

This structure supports a flat 256 byte memory for passive copper modules and permits timely access toaddresses in the Lower Memory( e.g. Flags and Monitors). Less time critical entries, e.g. serial ID informationand threshold settings, are available with the Page Select function in the Lower Page.

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CAQS-SPO201-DR4CZ 200GBASE-DR4 QSFP56 Optical Transceiver Module R01

Figure 4. CMIS Bank Page Memory Map

The CMIS memory structure also provides address expansion by adding additional upper pages as needed.
Upper pages 00-02 all contain static, non-volatile advertising registers. Upper page 01 provides revision codes
and advertising registers that indicate the capabilities of the module. Upper page 02 provides thresholds formonitored functions. Upper page 03 provides a user read/write space.

The lower page, upper pages 00h-03h and bank 0 page 10h-11h are supported in our module.

Figure 5. Additional Supported Bank Page Memory Map
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The Lower Memory – Page 00h
The Lower Memory consists of the lower 128 bytes of the 256 byte two-wire serial bus addressable space.
The Lower Page is used to access a variety of module level measurements, diagnostic functions and control
functions, as well as to select which of the various Upper Pages in the structured memory map are accessed bybyte addresses greater or equal than 128.

Figure 6. The Lower Memory Overview

The Upper Memory – Page 00h
Upper page 00h contains static read-only module identification information.

Figure 7. Page 00h Memory Overview
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CAQS-SPO201-DR4CZ 200GBASE-DR4 QSFP56 Optical Transceiver Module R01

The Upper Memory – Page 01h (Advertising)Upper page 01h contains advertising fields that define properties that are unique to active modules and cable
assemblies.

Figure 8. Page 01h Memory Overview

The Upper Memory – Page 02h (Module and Lane Thresholds)
Upper Page 02h contains the module-defined thresholds for module-level and lane-specific monitors. Thepresence of Page 02h is advertised in bit 7 in Page 00h byte 2.

Figure 9. Page 02h Memory Overview

The Upper Memory – Page 10h (Lane and Data Path Control)
The upper memory map page 10h is a banked page that contains lane dynamic control bytes. The presence ofPage 10h is advertised in bit 7 in Page 00h byte 2.
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CAQS-SPO201-DR4CZ 200GBASE-DR4 QSFP56 Optical Transceiver Module R01

Figure 10. Page 02h Memory Overview

The Upper Memory – Page 11h (Lane Status)
The upper memory map page 11h is a banked page that contains lane dynamic status bytes. The presence ofPage 11h is conditional on the state of bit 7 in Page 00h byte 2. All fields on Page 11h are read-only.

Figure 11. Page 11h Memory Overview

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CAQS-SPO201-DR4CZ 200GBASE-DR4 QSFP56 Optical Transceiver Module R01

Mechanical Dimensions

Figure 12. Mechanical Specifications

Regulatory Compliance
CA OPTRONICS GROUP CAQS-SPO201-DR4CZ QSFP56 transceivers are Class 1 Laser Products. They
are compliant withthe following standards:
FeatureLaser Safety

Electrical Safety
Environmental protection

CE EMCFCC

CA OPTRONICS GROUP INCStandard
IEC 60825-1:2014 (3rd Edition)
IEC 60825-2:2004/AMD2:2010
EN 60825-1-2014
EN 60825-2:2004+A1+A2
EN 62368-1: 2014
IEC 62368-1:2014
UL 62368-1:2014
Directive 2011/65/EU with amendment(EU)2015/863
EN55032：2015
EN55035：2017
EN61000-3-2:2014
EN61000-3-3:2013
FCC Part 15, Subpart B
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Complies with FDA performance standards for laser products except for deviations pursuant to Laser Notice No.
50, dated June 24, 2007.

References
1. QSFP MSA
2. CMIS V4.0
3. IEEE 802.3cd 200GBASE-SR4 specification
4. Directive 2011/65/EU of the European Parliament and of the Council, “on the restriction of the use of certain
hazardous substances in electrical and electronic equipment,” July 1, 2011.

CAUTION:Use of controls or adjustment or performance of procedures other than those specified herein may result inhazardous radiation exposure.

Ordering Information
Part Number

Product Description

CAQS-SPO201-DR4CZQSFP56, 200GBASE-DR4 Transceiver, 500m over SMF, DSP version.

Important Notice
Performance figures, data and any illustrative material provided in this data sheet are typical and must be
specifically confirmed in writing by CA OPTRONICS GROUP before they become applicable to any particularorder or contract. In accordance with the CA OPTRONICS GROUP policy of continuous improvement
specifications may change without notice.

The publication of information in this data sheet does not imply freedom from patent or other protective rights ofCA OPTRONICS GROUP or others. Further details are available from any CA OPTRONICS GROUP sales
representative.
E-mail :sales@caoptronicsgroup.com
Official Site:www.caoptronicsgroup.com

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