CAQS-SPO101-LR4CB 100GBASE-LR4 QSFP28 Optical Transceiver Module R01

100GBASE-LR4 QSFP28 Optical Transceiver ModuleCAQS-SPO101-LR4CBFeatures♦

4 channels full-duplex transceiver modules♦

Transmission data rate up to 26Gbps per channel♦

4 x 26Gb/s DFB-based LAN-WDM Cooling transmitter♦4 channels PIN ROSA♦Internal CDR circuits on both receiver and transmitter channels♦Low power consumption <3.5W♦Hot Pluggable QSFP form factor♦Up to reach 10km for G.652 SMF♦Duplex LC receptacles♦

Operating case temperature 0℃ to +70℃

♦3.3V power supply voltage♦RoHS compliant(lead free)

Applications♦

IEEE 802.3ba 100GBASE LR4Description
This product is a 100Gb/s transceiver module designed for optical communication applications compliant to100GBASE-LR4 of the IEEE P802.3ba standard. The module converts 4 input channels of 25Gb/s electrical data
to 4 channels of LAN WDM optical signals and then multiplexes them into a single channel for 100Gb/s opticaltransmission. Reversely on the receiver side, the module de-multiplexes a 100Gb/s optical input into 4 channels ofLAN WDM optical signals and then converts them to 4 output channels of electrical data.

The central wavelengths of the 4 LAN WDM channels are 1295.56, 1300.05, 1304.58 and 1309.14 nm asmembers of the LAN WDM wavelength grid defined in IEEE 802.3ba. The high performance cooled LAN WDM
DFB transmitters and high sensitivity PIN receivers provide superior performance for 100Gigabit Ethernet
applications up to 10km links and compliant to optical interface with IEEE802.3ba Clause 88 100GBASE-LR4requirements.

The product is designed with form factor, optical/electrical connection and digital diagnostic interface according tothe QSFP+ Multi-Source Agreement (MSA). It has been designed to meet the harshest external operating
conditions including temperature, humidity and EMI interference.

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1CAQS-SPO101-LR4CB 100GBASE-LR4 QSFP28 Optical Transceiver Module R01

Figure1. Module Block Diagram
Absolute Maximum Ratings
ParameterSymbol

MinMax

Unit

Supply Voltage

Vcc-0.3

3.6

V

Input Voltage

Vin-0.3

Vcc+0.3

V

Storage TemperatureTst-2085℃

Case Operating Temperature

Top070℃

Humidity(non-condensing)

Rh585%Damage Threshold, each Lane

TH

5.5

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Recommended Operating Conditions
Parameter

SymbolMin

TypicalMax

Unit

Supply Voltage

Vcc

3.13

3.3

3.47

V

Operating Case temperature

Tca

070℃

Data Rate Per Lane

fdHumidity

Rh

Power Dissipation

P

Link Distance with G.652

D0.002

Parameter

SymbolMin

Power Consumption
Supply Current

25.78125
5Gbps
85%

3.5W

10km

Max

Unit

P

3.5W

Icc

1.06

A2000

ms

4.0V

Electrical Specifications
TypicalTransceiver Power-on
Initialization TimeTransmitter(each Lane)
Single-ended Input Voltage
Tolerance-0.3

AC Common Mode Input Voltage
Tolerance

15mV

Differential Input Voltage

50mVppDifferential Input Voltage Swing

Vin

Differential Input Impedance

Zin

90

100900mVpp

110

Ohm

4.0

V

7.5mV

Receiver(each Lane)
Single-ended Output Voltage-0.3

AC Common Mode Output Voltage

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Parameter

SymbolMinDifferential Output Voltage Swing

Vout300

Differential Output Impedance

Zout90

Typical100

Max

Unit

850mVpp110Ohm

Note：

Power-on Initialization Time is the time from when the power supply voltages reach and remain above theminimum recommended operating supply voltages to the time when the module is fully functional.

Optical Characteristics
Table 3 - Optical Characteristics
QSFP28 100GBASE-LR4
Parameter

SymbolMin

TypicalMax

Unit

L0

1294.531295.56

1296.59nm

L11299.021300.051301.09nm

L21303.541304.581305.63nm

L31308.091309.141310.19nm

Notes

Lane WavelengthTransmitter

SMSR

SMSR

Total Average Launch Power

PTAverage Launch Power,each Lane
OMA, each Lane

30dB
10.5dBm

PAVG

-4.3

4.5dBmPOMA-1.3

4.5dBm5dB

1

Difference in Launch Powerbetween any Two Lanes

Ptx,diff(OMA)
Launch Power in OMA
minus Transmitter andDispersion Penalty (TDP),

-2.3

dBm

each Lane
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QSFP28 100GBASE-LR4Parameter

Symbol

TDP, each Lane

TDP

Extinction Ratio

ER

RIN20OMA

RIN-130

TOL

20dB

RT-12dB

Optical Return LossTolerance
Transmitter ReflectanceMin

TypicalMax

Unit

2.2

dB4

Notes

dBdB/HzEye Mask coordinates:{0.25, 0.4, 0.45, 0.25, 0.28, 0.4}

X1, X2, X3, Y1, Y2, Y3
Average Launch Power OFF
Transmitter, each Lane

Poff-30

2dBm

ReceiverDamage Threshold,each Lane

THd

5.5dBmTotal Average Receive
Power
Average Receive Power,-10.6

each Lane
Receive Power (OMA),
each Lane
Receiver Sensitivity (OMA),
each Lane
Stressed ReceiverSensitivity (OMA),
each Lane

SEN

10.5dBm

4.5dBm

4.5dBm

-8.6dBm-6.8dBm

5.5dB

34

Difference in Receive Powerbetween any Two Lanes

Prx,diff(OMA)
LOS Assert

LOSA-18dBmLOS Deassert

LOSD

-15

dBm

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CAQS-SPO101-LR4CB 100GBASE-LR4 QSFP28 Optical Transceiver Module R01

QSFP28 100GBASE-LR4Parameter

SymbolMin

LOS Hysteresis

LOSH

0.5

TypicalMax

Unit

NotesdB

Receiver Electrical 3 dB
upper Cutoff Frequency,

Fc31GHzeach Lane
Conditions of Stress Receiver Sensitivity Test (Note 5)
Vertical Eye ClosurePenalty, each Lane
Stressed Eye J2 Jitter,each Lane
Stressed Eye J9 Jitter,each Lane

1.8dB

0.3

UI

0.47

UI5

Note：

1. Even if the TDP < 1 dB, the OMA min must exceed the minimum value specified here.
2. See Figure 4 below.
3. The receiver shall be able to tolerate, without damage, continuous exposure to a modulated optical

input signal having this power level on one lane. The receiver does not have to operate correctly atthis input power.
4. Measured with conformance test signal at receiver input for BER = 1x10-12.
5. Vertical eye closure penalty and stressed eye jitter are test conditions for measuring stressed receiversensitivity. They are not characteristics of the receiver.

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CAQS-SPO101-LR4CB 100GBASE-LR4 QSFP28 Optical Transceiver Module R01

Pin Descriptions
PinLogic

1

SymbolName/Description

Ref.

GND

Module Ground

12

CML-I

Tx2-

Transmitter inverted data input

3CML-I

Tx2+

Transmitter non-inverted data input

GND

Module Ground

415CML-I

Tx4-

Transmitter inverted data input

6CML-I

Tx4+

Transmitter non-inverted data input

GND

Module Ground

178LVTTL-I

MODSEIL

Module Select29

LVTTL-I

ResetL

Module Reset

2

VCCRx+3.3v Receiver Power Supply

1011

LVCMOS-I

SCL

2-wire Serial interface clock212

LVCMOS-I/O

SDA

2-wire Serial interface data

2GND

Module Ground11314CML-O

RX3+

Receiver non-inverted data output

15CML-O

RX3-

Receiver inverted data output

GND

Module Ground16

117CML-O

RX1+Receiver non-inverted data output

18

CML-O

RX1-

Receiver inverted data output

19

GND

Module Ground

120

GND

Module Ground1

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PinLogic

SymbolName/Description

21

CML-O

RX2-

Receiver inverted data output

22

CML-O

RX2+

Receiver non-inverted data output

GND

Module Ground

2324

CML-O

RX4-

Receiver inverted data output

25

CML-O

RX4+

Receiver non-inverted data output

GND

Module Ground

26

Ref.

1127

LVTTL-O

ModPrsL

Module Present, internal pulled down to GND

28

LVTTL-O

IntL

Interrupt output, should be pulled up on host board

29

VCCTx+3.3v Transmitter Power Supply

30

VCC1+3.3v Power Supply

LPModeLow Power Mode2

GND

Module Ground131

LVTTL-I

32
33

CML-I

Tx3+

Transmitter non-inverted data input

34

CML-I

Tx3-

Transmitter inverted data input

GND

Module Ground

35
36

CML-I

Tx1+

Transmitter non-inverted data input

37

CML-I

Tx1-

Transmitter inverted data input

GND

Module Ground38

21

1Notes:1. Module circuit ground is isolated from module chassis ground within the module.
2. Open collector; should be pulled up with 4.7k – 10k ohms on host board to a voltage between 3.15Vand 3.6V.

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CAQS-SPO101-LR4CB 100GBASE-LR4 QSFP28 Optical Transceiver Module R01

Figure2. Electrical Pin-out Details
ModSelL Pin
The ModSelL is an input pin. When held low by the host, the module responds to 2-wire serial communicationcommands. The ModSelL allows the use of multiple QSFP modules on a single 2-wire interface bus. Whenthe ModSelL is “High”, the module will not respond to any 2-wire interface communication from the host.
ModSelL has an internal pull-up in the module.

ResetL PinReset. LPMode_Reset has an internal pull-up in the module. A low level on the ResetL pin for longer than theminimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings totheir default state. Module Reset Assert Time (t_init) starts on the rising edge after the low level on theResetL pin is released. During the execution of a reset (t_init) the host shall disregard all status bits until themodule indicates a completion of the reset interrupt. The module indicates this by posting an IntL signal with
the Data_Not_Ready bit negated. Note that on power up (including hot insertion) the module will post thiscompletion of reset interrupt without requiring a reset.

LPMode Pin
CA OPTRONICS GROUP QSFP28 LR4 operate in the low power mode (less than 1.5 W power
consumption)This pin active high will decrease power consumption to less than 1W.

ModPrsL PinModPrsL is pulled up to Vcc on the host board and grounded in the module. The ModPrsL is asserted “Low”
when the module is inserted and deasserted “High” when the module is physically absent from the hostconnector.

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CAQS-SPO101-LR4CB 100GBASE-LR4 QSFP28 Optical Transceiver Module R01

IntL Pin
IntL is an output pin. When “Low”, it indicates a possible module operational fault or a status critical to thehost system. The host identifies the source of the interrupt by using the 2-wire serial interface. The IntL pin is
an open collector output and must be pulled up to Vcc on the host board.

Power Supply Filtering
The host board should use the power supply filtering shown in Figure3.

Figure3. Host Board Power Supply Filtering
DIAGNOSTIC MONITORING INTERFACE (OPTIONAL)
The following digital diagnostic characteristics are defined over the normal operating conditions unlessotherwise specified.
Parameter
Temperature monitor absoluteerror
Supplyvoltagemonitorabsolute error
Channel RX power monitor
absolute error
Channel Bias current monitorChannel TX power monitor
absolute errorSymbol

MinMaxUnits

Notes

DMI_Temp-3+3degC

DMI _VCC

-0.1

0.1

V

Over full operating range

DMI_RX_Ch-22dB

1

DMI_Ibias_Ch

-10%

10%mA

DMI_TX_Ch-22dB

Over operating
temperature range

1Notes:Due to measurement accuracy of different single mode fibers, there could be an additional +/-1 dB fluctuation,
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or a +/- 3 dB total accuracy.

Digital diagnostics monitoring function is available on all Gigalight QSFP28 LR4. A 2-wire serial interface
provides user to contact with module.
The structure of the memory is shown in Figure 5. The memory space is arranged into a lower, single page,address space of 128 bytes and multiple upper address space pages. This structure permits timely access toaddresses in the lower page, such as Interrupt Flags and Monitors. Less time critical time entries, such asserial ID information and threshold settings, are available with the Page Select function.
The interface address used is A0xh and is mainly used for time critical data like interrupt handling in order toenable a one-time-read for all data related to an interrupt situation. After an interrupt, IntL, has been asserted,
the host can read out the flag field to determine the affected channel and type of flag.

Figure5. QSFP Memory Map

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CAQS-SPO101-LR4CB 100GBASE-LR4 QSFP28 Optical Transceiver Module R01

Figure6. Low Memory Map

Figure7. Page 03 Memory Map

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CAQS-SPO101-LR4CB 100GBASE-LR4 QSFP28 Optical Transceiver Module R01

Figure8. Page 00 Memory Map
Page02 is User EEPROM and its format decided by user.
The detail description of low memory and page00.page03 upper memory please see SFF-8436 document.

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CAQS-SPO101-LR4CB 100GBASE-LR4 QSFP28 Optical Transceiver Module R01

Timing for Soft Control and Status Functions
ParameterSymbolMaxUnit

Initialization Timet_init

2000msReset Init Assert Timet_reset_init

2μs

Serial Bus Hardware
Ready Timet_serial

2000

ms

Monitor Data ReadyTime

t_data2000

ms

Reset Assert Timet_reset2000

ms

LPMode Assert Time

ton_LPMode

100

μs

IntL Assert Time

ton_IntL200

ms

IntL Deassert Time

toff_IntL

500

μs

Rx LOS Assert Time

ton_los100

ms

Tx Fault Assert Time

ton_Txfault

200

ms

Time from Tx Fault state to Tx Fault bit set andIntL asserted

Flag Assert Time

ton_flag200

msTime from occurrence of condition triggering flagto associated flag bit set and IntL asserted

Mask Assert Time

ton_mask

100

ms

Time from mask bit set4 until associated IntL
assertion is inhibited

Mask Deassert Time

toff_mask

100

msTime from mask bit cleared4 until associated IntlL
operation resumes

ModSelL Assert Time

ton_ModSelL

100

μs

100

μs

ton_Pdown

100

ms

Time from P_Down bit set 4 until module power
consumption enters lower Power Level

toff_Pdown

300

ms

Time from P_Down bit cleared4 until the module
is fully functional3

ModSelL Deassert TimePower_over-ride orPower-set Assert TimePower_over-ride orPower-set DeassertTime

toff_ModSelLConditions
Time from power on1, hot plug or rising edge ofReset until the module is fully functional2
A Reset is generated by a low level longer thanthe minimum reset pulse time present on theResetL pin.
Time from power on1 until module responds todata transmission over the 2-wire serial bus
Time from power on1 to data not ready, bit 0 of
Byte 2, deasserted and IntL asserted
Time from rising edge on the ResetL pin until themodule is fully functional2
Time from assertion of LPMode (Vin:LPMode =Vih) until module power consumption enterslower Power Level
Time from occurrence of condition triggering IntL
until Vout:IntL = Vol
Time from clear on read3 operation of associatedflag until Vout:IntL = Voh. This includes deassert
times for Rx LOS, Tx Fault and other flag bits.
Time from Rx LOS state to Rx LOS bit set andIntL asserted

Time from assertion of ModSelL until module
responds to data transmission over the 2-wire serialbus
Time from deassertion of ModSelL until the module
does not respond to data transmission over the 2-wireserial bus

Figure9. Timing Specifications
Note：
1. Power on is defined as the instant when supply voltages reach and remain at or above the minimum specified value.
2. Fully functional is defined as IntL asserted due to data not ready bit, bit 0 byte 2 deasserted.
3. Measured from falling clock edge after stop bit of read transaction.

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CAQS-SPO101-LR4CB 100GBASE-LR4 QSFP28 Optical Transceiver Module R01

4. Measured from falling clock edge after stop bit of write transaction.

Mechanical Dimensions

Figure10. Mechanical Specifications

Regulatory Compliance
CA OPTRONICS GROUP CAQS-SPO101-LR4CB transceivers are Class 1 Laser Products. They meet therequirements of thefollowing standards.
FeatureStandard
IEC 60825-1:2014 (3rd Edition)
IEC 60825-2:2004/AMD2:2010
EN 60825-1-2014
EN 60825-2:2004+A1+A2

Laser Safety

EN 62368-1: 2014
IEC 62368-1:2014
UL 62368-1:2014

Electrical Safety

Environmental protection

CE EMCCA OPTRONICS GROUP INC

Directive 2011/65/EU with amendment(EU)2015/863
EN55032：2015
EN55035：2017
EN61000-3-2:2014
EN61000-3-3:2013

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CAQS-SPO101-LR4CB 100GBASE-LR4 QSFP28 Optical Transceiver Module R01

FeatureStandardFCC Part 15, Subpart B
ANSI C63.4-2014

FCC

ESD
This transceiver is specified as ESD threshold 1kV for SFI pins and 2kV for all other electrical input pins,
tested per MIL-STD-883, Method 3015.4 /JESD22-A114-A (HBM). However, normal ESD precautions are stillrequired during the handling of this module. This transceiver is shipped in ESD protective packaging. It
should be removed from the packaging and handled only in an ESD protected environment.

References
1. SFF-8436 QSFP+
2. Ethernet 100GBASE-LR4

Ordering information
Part Number
CAQS-SPO101-LR4CBProductDescription
100GE, QSFP28, 100GBASE-LR4, LAN_WDM 10km

Important Notice
Performance figures, data and any illustrative material provided in this data sheet are typical and must be
specifically confirmed in writing by CA OPTRONICS GROUP before they become applicable to any particularorder or contract. In accordance with the CA OPTRONICS GROUP policy of continuous improvement
specifications may change without notice.
The publication of information in this data sheet does not imply freedom from patent or other protective rightsof CA OPTRONICS GROUP or others. Further details are available from any CA OPTRONGROUP sales
representative.

sales@caoptronicsgroup.com
https://www.caoptronicsgroup.com/

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