Mega-hertz High-power WPT system with Parallel-connected inverters
using current balance circuit
Masamichi Yamaguchi, Keisuke Kusaka and Jun-ichi Itoh
NAGAOKA UNIVERSITY OF TECHNOLOGY
1603-1, Kamitomioka-chou, Nagaoka, Niigata, Japan
Tel.: +81 / (258) – 47.9533.
Fax: +81 / (258) – 47.9533.
E-Mail: m_yamaguchi@stn.nagaokaut.ac.jp, Kusaka@vos.nagaokaut.ac.jp,
Itoh@vos.nagaokaut.ac.jp
URL: http://itohserver01.nagaokaut.ac.jp/itohlab/en/index.html

Acknowledgements
This work was supported by Council for Science, Technology and Innovation(CSTI), Crossministerial Strategic Innovation Promotion Program (SIP), “Energy systems of an Internet of Energy(IoE) society” (Funding agency : JST).

Keywords«Current balancing», «Transformer», «Gallium Nitride (GaN)», «Wireless power transmission», «High
frequency power converter».

Abstract
This paper proposes a new current balancer for the megahertz WPT system. The proposed balancer
achieves a current balance between the parallel connection inverter on the transmission side of the WPTsystem. The balancer consists of two transformers without any additional control to achieve a current
balance. The output side of a conventional balancer is not isolated from the input side of the balancer.
The proposed balancer isolates the output side and the input side of the balancer. A turn ratio of two
transformers is derived by magnet flux under the current balancing condition. Furthermore, the proposedbalancer also has the capability of the impedance matching. The leakage inductance of two transformers
is applied to achieve an impedance matching with an additional capacitor. The experimental results
reveal that the current balance is achieved even if the phase of the output voltage of each inverter has adifference of approximately 8 ns.

Introduction
In recent years, battery chargers have been developed rapidly by increasing the interest in small
mobility, for example, drones. Notably, wireless power transfer (WPT) systems for battery chargers
have been actively studied for safety and convenience [1–2]. Then, the rapid charging is required toreduce the charging time. Although, the WPT system charger takes a long time to charge the onboard
batteries. Thus, increasing the output power of the WPT system to at least ten kilo watts is urgent.
On the other hand, the WPT systems with a transmission frequency of 85 kHz have been commonlyused because the WPT system for EVs charger is normalized with 85 kHz. Although, over ten kilowatt
system with 85 kHz is bulky and heavy as the charging system of the small mobility. One of the leading
causes is a transfer coil. The transfer coil in 85 kHz has a ferrite core at a transmission coil and a receivercoil. Then, the cursing distance of the mobility is affected directly by the weight of the receiver coil thatis mounted to the mobility.
Then, applying megahertz band frequency is one of the solutions to decrease the weight and the sizeof the transfer coil because the air-core coil is able to be applied as the transfer coil by using megahertz

frequency. Thus, the megahertz operation in the WPT system has been actively studied [3–8]. The WPTsystem employs a GaN device [9–10] to achieve the megahertz operation in a kilowatt order system.
Thus, the increase of the output power of the WPT system in megahertz operation is necessary forthe small mobility. A parallel connection of the GaN devices or the inverter circuits [11–12] has beenstudied to achieve a kilowatt order system. Then, the current unbalance occurs between paralleledcircuits or devices to delay the switching timing. The current unbalance causes thermal unbalance, which
destroys the devices. Thus, the current balancing method is necessary for paralleled circuits or devices.
However, it is difficult to apply an accurate control to synchronize switching timings of each device
or circuit still in the megahertz operation because the control period should be shorter than a few nanosecond. Thus, the current balancing method should be composed of the passive components without
additional current control. So far, a current balancer circuit for the paralleled inverters in megahertz
operation has been studied [13]. The balancer consists of two transformers without any additional
control. Although, the wire connection at the balancer circuit is complicate especially of the over threeparallel configurations because the primary side is non-isolated from and the secondary side of the twotransformers.
This paper proposes the new current balancer, including impedance matching capability, to increase
the output power with the parallel connection inverters. The advantage of the proposed balancer is thatthe configuration of the circuit is simple, and it is easy to expand into the three paralleled configurations.
Moreover, the proposed balancer has the capability of an impedance transform to match the impedanceof the load. Thus, Zero-Voltage-Switching(ZVS) is achieved in the parallel-connected inverters in any
load condition. First, the balance circuit is theoretically analyzed to derive the circuit parameters in thebalance condition. Then, the operation of the proposed balance circuit and ZVS is demonstrated by thesimulation and the fundamental experiments in the megahertz operation in the several conditions.

Conventional balancer circuit
Figure 1 shows the configuration of the parallel-connected inverter using a non-isolated balancer[13]. The balancer consists of two transformers. The primary side of each transformer is connected tothe output of each inverter. The secondary side of each transformer is connected to a transfer coil inseries. Two transformers have the same design parameters and have no magnetic coupling with eachother.
On the other hand, two transformers have a leakage inductance. The leakage inductance appears
between the inverters and the transfer coil. Thus, the resonant capacitance should be modified to keep
the resonant condition. When the leakage inductance has a large value, the voltage of the transfer coil isdecreased even if the resonant condition is achieved by adjusting the resonant capacitance. Thus, thetransfer power is regulated by the leakage inductance of the balancer circuit.

Proposed balancer circuit
Figure 2 shows the proposed configuration of the balancer circuit. The primary side and thesecondary side of each transformer are isolated. The primary side of each transformer is also connectedto the output of each inverter.
Inv. #1

VDC

i1

Tr1 : Lpri

vinv1

Inv. #2

Tr1 : Lsec

i3

Tr2 : Lsec
v3

M

Secondary
side

M
i2

Tr2 : Lpri

vinv2
Balancer circuit

Fig. 1. Configuration of the conventional balancer circuit in parallel-connected inverter system.

Parameters of balancer circuit
Figure 3 shows the detail of the balancer circuit. In the balancer circuit, the transformer currents i1,
i2, and i3 are sinusoidal because the transmission coil and the capacitor in the WPT system consider the
resonant load. Each voltage v1, v2, and v3 are expressed asd
v1 = N1,
dtd= N1 (1 − k2 ) ,dt
dv2 = N1 (3 − k4 ) ,dtddv3 = N2 (2 − k1 ) + N2 (4 − k3 ) ,dt
dt
1v3 = ( v1 + v2 ) ,2ii1 = i2 = 3 ,
2

(1)
(2)
(3)
(4)
(5)

where Φ1 is the magnet flux produced by the primary side of the Tr1, Φ2 is the magnet flux producedby the secondary side of the Tr1, Φ3 is the magnet flux produced by the primary side of the Tr2, Φ4 is
the magnet flux produced by the secondary side of the Tr2, N1 is the number of turns in the primary side,and N2 is the number of turns in the secondary side. Each magnetic flux under the current condition (5)is considered as
1 = 3 ,2 =4 ,thus, the voltage equation is expressed by (1), (2), (3), (4), (6), and (7) as
2 N2

(6)
(7)

d
d
2 − 2k1 = 2N1 dt(1 − k2 ) ,dt(8)then, the magnetic flux Φ1 and Φ2 are considered as the same value when the coupling factor k is unity.
k =1,
(9)
1 = 2 ,(10)

Inv. #1

VDC

Secondary
side

i3

i1
M

vinv1

Tr1 : Lsec

v3

Tr1 : Lpri
Inv. #2

i2
M

vinv2
Tr1 : Lpri

Tr1 : Lsec

Balancer circuit

Fig. 2. Configuration of the proposed balancer circuit in parallel-connected inverter system.
i1

i3


v1

Tr1 : N1

Tr1 : N2

v3

i2


v2

Tr2 : N1

Tr2 : N2

Fig. 3. Configuration of proposed balancer circuit.

The turn ratio of the transformer to achieve the current balance is expressed by using (8), (9), and (10)
as
N1
=2,
N2

(11)

the turn ratio for the current balance (11) is the same as for the non-isolated balancer[13].

Impedance matching using leakage inductanceTwo transformers in the proposed balancer also have the leakage inductance between the inverters
and the transfer coil. The leakage inductance of the proposed balancer is the same as that of the nonisolated balancer[13] because the turn ratio is also the same. The leakage inductance of the balancer
Lleakage, which is composed of two transformers, is derived in [13] as
Lleakage = 4 Lsec (1 − k ) ,(12)
where Lsec is the self-inductance of the secondary side of each transformer. Then, the leakage inductanceappears in series on the secondary side of the balancer[13].
Although the balancer has the leakage inductance, the inductance has the capability of the impedance
matching using the additional capacitor. Figure 4 (a) shows the connection of the additional capacitor,and (b) shows the equivalent circuit for the impedance matching capability in the proposed balancer. The
leakage inductance of the balancer Lleakage and the additional capacitor Cm compose the impedance
matching circuit. The load considers the resistor RL because the power factor of the WPT system is unity
under operation in resonant frequency.
The additional capacitor Cm is determined to match the impedance of the load and the inverter. Thus,
the modification of the resonant capacitance is not needed to achieve the resonant condition. Moreover,the ZVS operation of two inverters becomes easy because the impedance matching circuit adjusts the
impedance to the ZVS condition at the input terminal of the matching circuit. Then, the input impedanceZin is expressed as
Zin = jX L −jRL X C
RL − jX C .

(13)Then, the input impedance Zin must be satisfied the following condition to achieve the impedance
matching.
Rout = Re  Zin  ,(14)
X out = Im  Zin  ,(15)
where Rout is the resistance of the output impedance, Xout is the reactance of the output impedance at theinverter circuit. The capacitance Cm and the inductance Lleakage under the impedance matching is
expressed as
Inv. #1

VDC

i1

Secondary
side

i3
M

vinv1

Tr1 : Lsec

v3

Cm

Tr1 : Lsec

Balancer circuit

Tr1 : Lpri
Inv. #2

i2
M

vinv2
Tr1 : Lpri(a) Connection of proposed balancer and additional capacitor.
Lleakage
Zin

Cm

RL

(b) Equivalent circuit
Fig. 4. Impedance matching capability in proposed configuration.

Cm =

1

RL

−1

,
 RL RoutX
Cm RL 2
Lleakage = out + 1 +  2Cm 2 RL2 .

(16)

Table I. Simulation parameters.
Main circuit(17)

Thus, the self-inductance of the transformer byusing (12) and (17) is determined as
Lsec =

 X out1
Cm RL 2+
4 (1 − k )   1 +  2Cm 2 RL 2  .

(18)

DC link voltage

V DC

300 V

Switching frequency

Fs

6.78 MHz

Duty

d

40%

Parasitic capasitanceat drain-source of GaN-FET

C ds

127 pF

Output resistance of inverter

R out

10.0 

Output reactance of inverter

X out

10.0 

Balancer

Simulation results
Table I shows the simulation parameters. The
transfer coil and the secondary side of the WPTsystem consider the resonant load. The capacitor of
the GaN-FET between drain and source isconsidered as Cds in the simulation to accurately
simulate the output voltage of the inverter. Then, theload resistance RL is selected to 50  to check the
impedance matching, although the required
impedance is around 15  to achieve the ZVS
operation The simulation was implemented by
PLECS(Plexim Inc.).

Impedance matching capacitorCm939 pF

Leakage inductance of balancer

L leakage

0.70 H

Coupling factork

0.9

Inductance of secondary side

L sec

1.76 H

Inductance of primary sideL pri

7.0 HLr

5.8 H

Resonant capacitanceCr

95.0 pF

Load resistanceRL0.0 

Load
Resonant inductance

Current balance working

450
300
150

v1
v2

Output current [A]Output voltage [V]Figure 5 shows the each inverter’s output voltage and current without the amplitude difference andthe phase difference of the output voltage. Each output voltage is the same amplitude and phase. The
coupling factor k is 0.9. The output current of each inverter is balanced.
Figure 6 shows the output voltage and the current of each inverter with the phase difference of theoutput voltage. The phase of the inverter #2 is set to a 5.0% delay. Each current becomes the same
amplitude with the phase difference of the output voltage. The output voltage of the each inverter
achieves ZVS operation.
Figure 7 shows the output voltage and current of each inverter when each output voltage has adifferent phase and amplitude. The voltage amplitude of the inverter #2 is decreased to half the value ofthe inverter #1. The phase of the inverter #2 is set to a 10.0% delay. Each current is also made balanced,
and the ZVS operation is almost achieved.

0
-150
-300
-450

100 ns/div

40

i3

20

i1

0

i2

-20
-40

100 ns/div

450
300
150

v1

0
-150
-300
-450

v2
100 ns/div

Output current [A]Output voltage [V](a) Output voltage.
(b) Output current.
Fig. 5. Output voltage and current without voltage difference and phase difference.
40

i3

20
i1

0
-20
-40

100 ns/div(a) Output voltage.
(b) Output current.
Fig. 6. Output voltage and current with phase difference.

i2

Impedance matching
Figure 8 shows the output voltage and the current of each inverter with different load resistance. The
load resistance RL is selected to 30  and 100  to check the effect of the impedance matching. Then,the capacitor Cm and the leakage inductance Lleakage is modified to match the impedance. Table II shows
the matching parameters with the RL changing. The phase of the inverter #2 is set to a 5.0% delay. Eachcurrent i1 and i2, and the total output current i3 have no difference with load difference between 30 and 100 . Moreover, both inverters also achieve ZVS operation with load difference. This result
indicates that the input impedance of the balancer kept constant by the additional capacitor Cm and theleakage inductance Lleakage.

Experimental results

450
300
150

v1
v2

0
-150
-300
-450

Output current [A]Output voltage [V]Figure 9 shows the prototype balancer and the parallel connection inverters in the experiment. The
prototype balancer consists of two air-core transformers. The output of the balancer connects with theresonant load as the transfer coil and the secondary side of the WPT system. Table III shows the eachparameter of the experimental verification. The GaN-transistors (PGA26E07BA: 600 V, 26 A,
Panasonic) are used for the mega-hertz switching in each inverter.

100 ns/div

40

i3

20

i1

0

i2

-20
-40

100 ns/div

450
300
150

v1

0
-150
-300
-450

v2
100 ns/div

Output current [A]Output voltage [V](a) Output voltage.
(b) Output current.
Fig. 7. Output voltage and current with voltage amplitude and phase difference.
40v2
100 ns/div

Output current [A]Output voltage [V]

-150
-300
-450

i2

-20
-40

100 ns/div(b) Output current (RL:30 ).
v1

0

i1

0

(a) Output voltage (RL:30 ).
450
300
150

i3

20

40

i3

20
i1

0
-20
-40

100 ns/div(c) Output voltage (RL:100 ).
(d) Output current (RL:100 ).
Fig. 8 Output voltage and current with difference of load resistance.
Table II. Balancer parameter with load difference.
Load resistance R L = 30.0 
Impedance matching capacitorCm1107 pF

Leakage inductance of balancer

L leakage

0.57 H

Inductance of secondary side

L sec

1.42 H

Impedance matching capacitor

Cm

704 pF

Leakage inductance of balancer

L leakage

0.94 H

Inductance of secondary side

L sec

2.35 H

Load resistance R L = 100 i2Balancer

Resonant load

f 130 mmTrans2

Inv.2

Trans1Inv.1(a) Prototype balancer(b) Overview of experimental circuit.
Fig.9 Experimental circuit.
Table III. Balancer parameters.
Main circuit

DC link voltage

V DC

200 V

Switching frequency

Fs

6.78 MHz

Duty

d

20%

Output resistance of inverter

R out

10.0 

Output reactance of inverter

X out

10.0 

Impedance matching capacitor

Cm

940 pF

Inductance of primary sideL pri

4.7 H

Inductance of secondary sideL sec

1.3 H

Coupling factor

k

0.84

Resonant inductanceLr

5.3 H

Resonant capacitanceCr

105 pF

Load resistance

RL

50.0 

Balancer

Load

Current balance working
Figure 10 shows the output voltage and the current of the paralleled inverters in the experiment using
the prototype balancer. Note that the impedance matching capacitor Cm is not implemented to confirm
the fundamental balance operation. Thus, the load resistance is 20.0  to achieve the ZVS. The operation
frequency is 5.25 MHz because the resonant frequency of the resonant load is decreased by the leakage
inductance in the balancer. The DC-link voltage is 150V. The output current iinv1 and iinv2 is balanced even
if the phase of the voltage has a difference of approximately 5 ns in figure 10(b). The difference between
the maximum value of the current is 5.6%. Therefore, the balancer working is achieved fundamentally
without any additional control in megahertz operation.

Impedance matching
Figure 11 shows the output voltage and the current of the paralleled inverters with impedance
matching capacitor Cm. The load resistance is 50.0  to verify the impedance matching. The operation
frequency is 6.78 MHz. The phase difference between the output voltage vinv1 and vinv2 is approximately
8 ns in figure 11(b). The output current iinv1 and iinv2 is balanced even if the output voltage has the phasedifference. The output voltage vinv2 achieves the ZVS operation completely. The vinv1 does not achieve
ZVS operation because of the phase of the vinv1 is delayed from the vinv2. The total output is 620 W at theload resistor RL in figure 11(a).

vgs1_inv1

5 V/div

0vinv1

200 V/div

0
0
0

iinv1

0

iinv2

40 ns/divvinv1

200 V/div

0
0

vinv2

vgs1_inv1

5 V/div

0

vinv2

0

iinv1

0

iinv2

40 ns/div
2 A/div

2 A/div(a) Without phase difference(b) With phase difference (5 ns)
Fig. 10. Output voltage and current in experiment without impedance matching (5.25 MHz).
00

5 V/div

vgs1_inv1

200 V/div

0

0
vinv1

0

vinv2

0

iinv2

0
5 A/div

5 V/div

200 V/div

iinv1

vinv1

vinv2

iinv1

0
20 ns/div

vgs1_inv1

5 A/div

iinv2
20 ns/div(a) Without phase difference(b) With phase difference (8 ns)
Fig. 11. Output voltage and current in experiment with impedance matching (6.78 MHz).

Conclusion
In this paper, the new current balancer, including impedance matching capability for megahertz
operation, was proposed. The proposed balancer consists of two transformers without any additional
control to achieve the current balance. The turn ratio of two transformers to achieve the current balancing
was derived theoretically based on the magnet flux under the current balancing condition. The
impedance matching condition is also derived by the leakage inductance of the balancer and the
additional capacitor. The simulation results verified the operation of the proposed balancer under theamplitude and the phase difference condition. The input impedance of the balancer kept constant with
the impedance matching capability. The experimental result with proposed balancer achieved current
balance with a phase difference of the output voltage approximately 8 ns. In addition, the ZVS operationis almost achieved in the each inverter by impedance conversion using additional capacitor.

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