CAQM-8LC-XXXC 40Gb/s QSFP+ Parallel Single Mode(2KM)to 8 x LC Active Optical Cable R01

40Gb/s QSFP+ Parallel Single Mode(2KM)to 8 x LCConnector Breakout Active Optical Cable

CAQM-8LC-XXXCFeatures♦

Full duplex 4 channel 1310nm parallel active opticalcable♦

Transmission data rate up to 11.3Gbit/s per channel♦

SFF-8436 QSFP+ compliant♦

Hot pluggable electrical interface♦

Differential AC-coupled high speed data interface♦

4 channels 1310nm FP array♦

4 channels PIN photo detector array♦

Maximum link length of 2km on G652 single mode fiber(SMF)♦8x LC connector(APC)♦Maximum power consumption 3.5W♦

Housing isolated from connector ground♦

Operating case temperature 0°C to +70°C♦

3.3V power supply voltage♦RoHS 6 compliantApplications♦

Infiniband Connectivity SDR/DDR/QDR♦

10/40 Gigabit Ethernet♦

2/4/8 Gbps Fiber Channel♦

Data Centers and Storage Arrays

Description
QSFP PSM TO 8xLC Breakout AOC are a high performance, low power consumption, long reachinterconnect solution supporting 40G Ethernet, fiber channel and PCIe. It is compliant with the QSFP MSA
and 40GbE PSM4. QSFP PSM TO 8xLC Breakout AOC is an assembly of 4 full-duplex lanes, where eachlane is capable of transmitting data at typical rate of 10.3125Gb/s, providing an aggregated rate of 41.25Gb/s.
These breakout cables connect to a 40G QSFP+ port of a switch on one end and to four 10G SFP+
Transceivers of a switch on the other end.

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Absolute Maximum Ratings
Parameter

SymbolMinMax

Unit

Supply Voltage

Vcc-0.3

3.6

V

Input Voltage

Vin-0.3

Vcc+0.3

V

Storage TemperatureTst-2085ºC

Case Operating Temperature

Top070ºC

Humidity(non-condensing)

Rh

595%

Recommended Operating Conditions
Parameter

SymbolMin

TypicalMax

Unit

Supply Voltage

Vcc

3.13

3.3

3.47

V

Operating Case temperature

Tca

070

ºC

Data Rate Per Lane

fd

11.3

Gbps

HumidityRh

85%

Power Dissipation

Pm

3.5W

Link Distance with G652

RbD2kmParameter

SymbolMinTypicalMax

Unit

Differential input impedanceZin

90100110ohm

Differential Output impedanceDifferential input voltage amplitude

Zout

90100110ohm

ΔVin

300

1100

mVp-p

Differential output voltage amplitude

ΔVout

500

800

mVp-p

Skew

Sw300

ps

Bit Error Rate

BR

E-12

Input Logic Level High

VIH

2.0

VCC

V

Input Logic Level Low

VIL

00.8

V

Output Logic Level High

VOH

VCC-0.5

VCC

V

Output Logic Level Low

VOL00.4

V

10.3
5Specifications

Note：
1. BER=10^-12; PRBS 2^31-1@10.3125Gbps.
2.
3.

Differential input voltage amplitude is measured between TxNp and TxNn.
Differential output voltage amplitude is measured between RxNp and RxNn.

Optical Characteristics
Parameter

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SymbolMin

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Max

Unit

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Notes

CAQM-8LC-XXXC 40Gb/s QSFP+ Parallel Single Mode(2KM)to 8 x LC Active Optical Cable R01

Transmitter
Centre Wavelength

λc

1260

1310

1355

nm

-

Spectral width(RMS)

∆λ--

3.5

nm

-Average launch power, each lanePout-7.6-2.4dBm-

Difference in launch power
between any two lanes (OMA)

Ptx,diff

6.5

dB-

Extinction Ratio

ER-dB-

TDP

3.2

dB-

Poff-30

dBm

-

RT-12

dB

Transmitter and dispersion
penalty (TDP), each lane
Average launch power of OFF
transmitter, each lane
Transmitter Reflectance
Eye Mask coordinates:
X1, X2, X3, Y1, Y2, Y3

3.5-

Hit Ratio =5x10-5SPECIFICATION VALUES
0.25, 0.4, 0.45, 0.25, 0.28, 0.4

ReceiverCentre Wavelength

λcStressed receiver sensitivity inOMA, each lane

SEN1260

1310

Maximum Average power atreceiver input, each lane

1335

nm-

-10.6

dBm

1

2.4

dBm

-

Difference in Receive Powerbetween any Two Lanes(OMA)

Prx,diff

7.5

dB

Receiver Reflectance

RR-12

dB-

LOS Assert

LOSA

dBm

-

LOS De-Assert

LOSD

dBm

-LOS Hysteresis

LOSH

dB-

-30
-14
0.5

Note：

1．Measured with conformance test signal at TP3 for BER = 10e-12

Pin Descriptions
PinLogic

1

SymbolName/Description

Ref.

GND

Module Ground

12

CML-I

Tx2-

Transmitter inverted data input

3CML-I

Tx2+

Transmitter non-inverted data input

4GND

Module Ground

5CML-I

Tx4-

Transmitter inverted data input

6CML-I

Tx4+

Transmitter non-inverted data input

GND

Module Ground

1MODSEIL

Module Select278

LVTTL-I

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9LVTTL-I

10ResetL

Module Reset

VCCRx+3.3v Receiver Power Supply

211

LVCMOS-I

SCL

2-wire Serial interface clock212

LVCMOS-I/OSDA2-wire Serial interface data

2

GND

Module Ground

114CML-O

RX3+

Receiver non-inverted data output

15CML-O

RX3-

Receiver inverted data output

GND

Module Ground

1316

117

CML-O

RX1+

Receiver non-inverted data output

18

CML-O

RX1-

Receiver inverted data output

19

GND

Module Ground

120

GND

Module Ground

121

CML-O

RX2-

Receiver inverted data output

22

CML-O

RX2+

Receiver non-inverted data output

GND

Module Ground

23

1

24

CML-O

RX4-

Receiver inverted data output

25

CML-O

RX4+

Receiver non-inverted data output

GNDModule Ground27

LVTTL-O

ModPrsL

Module Present, internal pulled down to GND

28

LVTTL-O

IntL

Interrupt output, should be pulled up on host board

29

VCCTx+3.3v Transmitter Power Supply

30

VCC1+3.3v Power Supply

LVTTL-I

LPModeLow Power Mode2

GND

Module Ground

1

33

CML-I

Tx3+

Transmitter non-inverted data input

34

CML-I

Tx3-

Transmitter inverted data input

GND

Module Ground

26

31
32

35
36

CML-I

Tx1+

Transmitter non-inverted data input

37

CML-I

Tx1-

Transmitter inverted data input

GND

Module Ground38

111Notes:
1. Module circuit ground is isolated from module chassis ground within the module.
2. Open collector; should be pulled up with 4.7k – 10k ohms on host board to a voltage between 3.15V and3.6V.

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Figure2. Electrical Pin-out Details
ModSelL Pin
The ModSelL is an input pin. When held low by the host, the module responds to 2-wire serial communicationcommands. The ModSelL allows the use of multiple QSFP modules on a single 2-wire interface bus. Whenthe ModSelL is “High”, the module will not respond to any 2-wire interface communication from the host.
ModSelL has an internal pull-up in the module.
ResetL PinReset. LPMode_Reset has an internal pull-up in the module. A low level on the ResetL pin for longer than theminimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings totheir default state. Module Reset Assert Time (t_init) starts on the rising edge after the low level on theResetL pin is released. During the execution of a reset (t_init) the host shall disregard all status bits until themodule indicates a completion of the reset interrupt. The module indicates this by posting an IntL signal withthe Data_Not_Ready bit negated. Note that on power up (including hot insertion) the module will post thiscompletion of reset interrupt without requiring a reset.
LPMode Pin
CA OPTRONICS GROUP QSFP AOC operate in the low power mode (less than 1.5 W powerconsumption)This pin active high will decrease power consumption to less than 1.5W.
ModPrsL Pin
ModPrsL is pulled up to Vcc on the host board and grounded in the module. The ModPrsL is asserted “Low”
when the module is inserted and deasserted “High” when the module is physically absent from the hostconnector.
IntL Pin
IntL is an output pin. When “Low”, it indicates a possible module operational fault or a status critical to thehost system. The host identifies the source of the interrupt by using the 2-wire serial interface. The IntL pin is
an open collector output and must be pulled up to Vcc on the host board.

Power Supply Filtering

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The host board should use the power supply filtering shown in Figure3.

Figure3. Host Board Power Supply Filtering

DIAGNOSTIC MONITORING INTERFACE (OPTIONAL)
Digital diagnostics monitoring function is available on all CA OPTRONICS GROUP QSFP PSM AOCs. A 2wire serialinterface provides user to contact with module.
The structure of the memory is shown in Figure 4. The memory space is arranged into a lower, single
page, address space of 128 bytes and multiple upper address space pages. This structure permits timely
access to addresses in the lower page, such as Interrupt Flags and Monitors. Less time critical time entries,
such as serial ID information and threshold settings, are available with the Page Select function.
The interface address used is A0xh and is mainly used for time critical data like interrupt handling in orderto enable a one-time-read for all data related to an interrupt situation. After an interrupt, IntL, has beenasserted, the host can read out the flag field to determine the affected channel and type of flag.

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Figure4. QSFP Memory Map

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Figure5. Low Memory Map

Figure6. Page 03 Memory Map

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Figure7. Page 00 Memory Map
Page02 is User EEPROM and its format decided by user.
The detail description of low memory and page00.page03 upper memory please see SFF-8436 document.

Timing for Soft Control and Status Functions

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ParameterSymbolMax

Unit

Initialization Timet_init2000

ms

Reset Init Assert Timet_reset_init

2μst_serial

2000

mst_data

2000

ms

Reset Assert Timet_reset2000

ms

LPMode Assert Time

ton_LPMode

100

μs

LPMode Deassert
Time

Toff_LPMode 300

ms

IntL Assert Time

ton_IntL

ms

Serial Bus Hardware
Ready Time
Monitor Data ReadyTime

200

IntL Deassert Time

toff_IntL

500

μs

Rx LOS Assert Time

ton_los100

ms

Tx Fault Assert Time

ton_Txfault

200

ms

Flag Assert Time

ton_flag200

msMask Assert Time

ton_mask

100msMask Deassert Time

toff_mask

100

ms

Application or Rate
Select Change Timet_ratesel

100μsPower_over-ride orPower-set Assert Time

ton_Pdown

100ms

Power_over-ride orPower-set Deassert
Time

toff_Pdown

300

ms

Conditions
Time from power on2, hot plug or rising edge ofReset until the module is fully functional3This
time does not apply to non-Power Level 0
modules in the Low Power StateA Reset is generated by a low level longer thanthe minimum reset pulse time present on theResetL pin.
Time from power on2 until module responds todata transmission over the 2-wire serial bus
Time from power on2 to data not ready, bit 0 of
Byte 2, deasserted and IntL asserted
Time from rising edge on the ResetL pin until themodule is fully functional3
Time from assertion of LPMode (Vin:LPMode =Vih) until module power consumption enterslower Power Level 1
TimefordeassertionofLPMode(Vin:LPMode=Vil)
until
moduleisfullyfunctional3,5Time from occurrence of condition triggering IntL
until Vout:IntL = Vol
Time from clear on read4 operation of associatedflag until Vout:IntL = Voh. This includes deasserttimes for Rx LOS, Tx Fault and other flag bits.
Time from Rx LOS state to Rx LOS bit set(value=1b) and IntL asserted
Time from Tx Fault state to Tx Fault bit set(value=1b) and IntL asserted
Time from occurrence of condition triggering flagto associated flag bit set (value=1b) and IntL
asserted
Time from mask bit set(value=1b)1 until
associated IntL assertion is inhibited
Time from mask bit cleared (value=0b)1 until
associated IntlL operation resumes
Time from change of state of Application or Rate
Select Bit1 until transmitter or receiver bandwidth
is in conformance with appropriate specification
Time from P_Down bit set (value=1b)1 until
module power consumption enters lower PowerLevel 1Time from P_Down bit cleared(value=0b)1 until
the module is fully functional3

Note：
1. Power on is defined as the instant when supply voltages reach and remain at or above the minimum specified value.
2. Fully functional is defined as IntL asserted due to data not ready bit, bit 0 byte 2 deasserted.
3. Measured from falling clock edge after stop bit of read transaction.
4. Measured from falling clock edge after stop bit of write transaction.

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Figure9. Mechanical Specifications

ESD
This AOC is specified as ESD threshold 1KV for high speed data pins and 2KV for all others electrical input
pins, tested per MIL-STD-883, Method 3015.4 /JESD22-A114-A (HBM). However, normal ESD precautions
are still required during the handling of this module. This transceiver is shipped in ESD protective packaging.
It should be removed from the packaging and handled only in an ESD protected environment.

Ordering information
Part Number
CAQM-8LC-XXXC

Product Description
XXX=different cable lengths on G652 single mode fiber(SMF)

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XX(X)Cable Length on G652 single mode fiber (SMF)03003=3m05005=5m10010=10m

20020=20m

50

050=50m

100

100=100m10001000=1km

2000

2000=2km

Important Notice
Performance figures, data and any illustrative material provided in this data sheet are typical and must be
specifically confirmed in writing by CA OPTRONICS GROUP before they become applicable to any particularorder or contract. In accordance with the GIGALIGHT policy of continuous improvement specifications maychange without notice.
The publication of information in this data sheet does not imply freedom from patent or other protective rights
of CA OPTRONICS GROUP or others. Further details are available from any CA OPTRONICS GROUP sales
representative.

sales@caoptronicsgroup.com
http://www.caoptronicsgroup.com

CA OPTRONICS GROUP INC

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