APPLICATION NOTE
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MOSFET Basic
AN-9010/D
SUMMARY
The Bipolar Power Transistor (BPT), as a switching
device for power applications, had a few disadvantages.
This led to the development of the power Metal Oxide
Semiconductor Field Effect Transistor (MOSFET).
The power MOSFET is used in applications suchas Switched Mode Power Supplies (SMPS), computer

peripherals, automotive, and motor control. Continuous
research has improved its characteristics for replacing
the BJT. This application note is a general descriptionof power MOSFETs and a presentation of some of onsemi’s
product specifications.

HISTORY
The theory behind the Field Effect Transistor (FET) has
been known since 1920~1930, which is 20 years before
the bipolar junction transistor was invented. At that time,
J.E. Lilienfeld of the USA suggested a transistor model
having two metal contacts on each side with a metallic plate(aluminum) on top of the semiconductor. The electric fieldat the semiconductor surface, formed by the voltage
supplied at the metallic plate, enables the controlof the current flow between the metal contacts. This was theinitial concept of the FET. Due to lack of appropriate
semiconductor materials and immature technology,
development was very slow. William Shockely introduced
Junction Field Effect Transistors (JFETs) in 1952. Dacey

and Ross improved on it in 1953. In JFETs, Lilienfeld’s
metallic field is replaced by a P−N junction, the metal
contacts are called source and drain, and the field effectelectrode is called a gate. Research in small−signal
MOSFETs continued without any significant improvements
in power MOSFET design, until new products wereintroduced in the 1970s.
In March of 1986, Fairchild® formed with nine people
and began research on power MOSFETs. 1990’s, Fairchildhas developed a QFET® devices using planar technology
and low−voltage POWERTRENCH® products using trenchtechnology.

© Semiconductor Components Industries, LLC, 2000

August, 2022 − Rev. 2

1

Publication Order Number:
AN−9010/D

AN−9010/D

ÇÇÇÇ
ÇÇÇÇ
ÄÄÄÄÄÄÄÄ
ÄÄÄÄÄÄÄÄ

FETS

Gate

SourceJunction Field Effect Transistors (JFETs)

There are two types of JFETs: an N−channel type anda P−channel type. They both control the drain−to−source
current by the voltage supplied to the gate. As shown in
Figure 1 (a) , if the bias is not supplied at the gate, the current
flows from the drain to the source. When the bias is suppliedat the gate, the depletion region begins to grow and reduces
the current, as shown in Figure 1 (b). The reason for thewider depletion region of the drain, compared to the source
depletion region, is that the reverse bias of the gate and thedrain, VDG (= VGS + VDS), is higher than the bias between
the gate and the source, VGS.

Drain

N

P

VDS
(a) VGS Gate−Source Voltage is Not Supplied
VGS

ÇÇÇÇ
ÄÄÄÄÄÄÄÄ
ÄÄÄÄÄÄÄÄ
Gate

Source

Drain

N

Drain

Depletion
region

N

P
P

P

VDS

VDS

Gate

(b) VGS (Gate−Source Voltage) is Supplied

Figure 2. Structure of a Depletion Type MOSFET
and Its Operation

Source(a) VGS (Gate−Source Voltage) is Not Supplied

GateÄÄÄÇÇÇÇÄÄÄÄÄÄ ÄÄÄ

SourceDepletion
region

Drain

Drain

N

N

N

P
P

P

VDS
Gate

VDS

VGS

(a) VGS (Gate−Source Voltage) is Not Supplied
VGS

ÇÇÇÇ
ÇÇÇÇ
ÄÄÄÄÄÄÄÄ
ÄÄÄÄÄÄÄÄ

SourceGate(b) VGS (Gate−Source Voltage) is Supplied

Drain

SourceFigure 1. Structure of JFET and Its Operation

N

N

Metal Oxide Semiconductor Field Effect Transistors(MOSFETs)P

The two types of MOSFETs are depletion type andenhancement type, and each has a N/P–channel type. The
depletion type is normally on and operates as a JFET (refer
to Figure 2). The enhancement type is normally off, whichmeans that the drain−to−source current increases as thevoltage at the gate increases. No current flows when no
voltage is supplied at the gate (refer to Figure 3).

VDS(b) VGS (Gate−Source Voltage) is Supplied

Figure 3. Structure of a Enhancement TypeMOSFET and Its Operationwww.onsemi.com
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AN−9010/D
STRUCTURE OF A MOSFETÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉLateral Channel Design

The drain, gate, and source terminals are placed on thesurface of a silicon wafer. This is suitable for integration, but
not for obtaining high power ratings because the distance
between source and drain must be large to obtain better
voltage blocking capability. The drain−to−source current isinversely proportional to the length.

SourceN+Gate

P−bodyVertical Channel DesignN+P−bodyN − epitaxial layer

The drain and source are placed on the opposite sides ofa wafer. This is suitable for a power device, as more spacecan be used as source. As the length between the source anddrain is reduced, it is possible to increase thedrain−to−source current rating and increase the voltage
blocking capability by growing the epitaxial layer (drain
drift region).

N + substrate
Drain(a) VMOSFET Vertical

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
SourceGate

1. The VMOSFET Design: the first to becommercialized, this design was has a V−groove at
the gate region, as shown in Figure 4 (a). Due tostability problems in manufacturing and a highelectric field at the tip of the V−groove, VMOSFETs
were replaced by DMOSFETs.
2. The DMOSFET Design: has a double−diffusion
structure with a P−base region and a N+ source
region, as shown in Figure 4 (b). It is the mostcommercially successful design.
3. The UMOSFET Design: As shown in Figure 4 (c),this design has a U−groove at the gate region. Higher
channel density reduces the on−resistance ascompared to the VMOSFETs and the DMOSFETs.
UMOSFET designs with the trench etching process
were commercialized in the 90’s.

N+N+

P−bodyP−bodyN − epitaxial layer
N + substrate
Drain(b) DMOSFET Vertical

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
SourceN+N+

P−bodyGate

P−bodyN − epitaxial layer
N + substrate
Drain(c) UMOSFET VerticalFigure 4. Vertical Channel Structure

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AN−9010/D
CHARACTERISTICS OF A MOSFET

drain current is not limited externally, it is destroyed by thesecond breakdown. The N+ source region and the P−typebody region must be shorted by metallization to prevent theparasitic BJT from turning on.
If the VDS rate of increase is large in the high speed
turn−off state, there is a voltage drop between the base andthe emitter, which causes the BJT to turn on. This isprevented by increasing the doping density of the P− body
region, which is at the bottom of the N+ source region, andby lowering the MOSFETs switching speed, by designing
the circuit so that the gate resistance is large. Due to thesource region being short, another parasitic component, thediode, is formed. This is used in half− and full−bridge
converters.

Advantages

High Input Impedance − Voltage−Controlled Device −Easy to Drive
To maintain the on−state, a base drive current 1/5th or
1/10th of collector current is required for thecurrent−controlled device (BJT). A larger reverse base drive
current is needed for the high−speed turn−off of thecurrent−controlled BJT. Due to these characteristics, basedrive circuit design becomes complicated and expensive.
On the other hand, a voltage−controlled MOSFET is aswitching device driven by a channel at the semiconductor’s
surface due to the field effect produced by the voltage
applied to the gate electrode, which is isolated from thesemiconductor surface. Because the required gate current
during switching transient, as well as the on and off states,
is small; the drive circuit design is simpler and lessexpensive.

SourceGate

ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉN+

UniPolar Device − Majority Carrier Device − Fast
Switching Speed

P−bodyWide Safe Operating Area (SOA)
It has a wider SOA than the BJT because high voltage andcurrent can be applied simultaneously for a short duration.
This eliminates destructive device failure due to second
breakdown.

N − epitaxial layer
N + substrate

Forward−Voltage Drop with Positive Temperature
Coefficient − easy to use in Parallel
When the temperature increases, forward−voltage drop
also increases. This causes the current to flow equally
through each device when they are in parallel. Hence, the
MOSFET is easier to use in parallel than the BJT, which has
a forward− voltage drop with a negative temperature
coefficient.

Drain

Figure 5. MOSFET Vertical Structure Showing
Parasitic BJT and Diode
Output Characteristics

ID characteristics are due to VDS in many VGS conditions(refer to Figure 6).
→ It is divided into the ohmic region, the saturation(= active) region, and the cut−off region.

Disadvantage

In high breakdown voltage devices over 200 V, theconduction loss of a MOSFET is larger than that of a BJT,
which has the same voltage and current rating due to the on−state voltage drop.

Table 1. OUTPUT CHARACTERISTICS REGIONS
Ohmic
RegionBasic Characteristics• Vertically oriented four−layer structure (N+ P N− N+)• Parasitic BJT exists between the source and the drain.
The P−type body region becomes base, the N+ source
region becomes an emitter and the N−type drain region
becomes the collector (refer to Figure 5). The breakdown
voltage decreases from BVCBO to BVCEO, which is
50 ~ 60% of BVCBO when the parasitic BJT is turned on. In
this state, if a drain voltage higher than BVCEO is supplied,the device falls into an avalanche breakdown state. If the

A constant resistance region. If the drain−to−source
voltage is zero, the drain current also becomes zero
regardless of gate−to−source voltage. This region is at
the left side of the VGS – VGS(th) = VDS boundary line
(VGS – VGS(th) > VDS > 0). Even if the drain current isvery large, in this region the power dissipation is
maintained by minimizing VDS(on).

Saturation A constant−current region. It is at the right side of
the VGS – VGS(th) = VDS boundary line. Here, theRegiondrain current differs by the gate−to−source voltage,and not by the drain−to−source voltage. Hence, thedrain current is called saturated.
ColumnHeadwww.onsemi.com
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Called the cut−off region because the gate−to−source
voltage is lower than the VGS(th) (threshold voltage).

AN−9010/D
tOX is thickness of the gate oxide;
W is channel width; andLis channel length.

[VGS − VGS(th) = VDS ]

iD
Ohmic

Active

VGS5

VGS5 > VGS4 > VGS3 > VGS2 > VGS

VGS4
VGS3
VGS2
VGS1

0

Cutoff

A parabolic transfer curve exists in a logic−level device
according to Equation 1. In a power MOSFET, this is true
only in the low ID of the transfer curve and the other areas
show linearity. This is because the mobility of the carrier is
not constant, but decreases due to the increase of the electricfield along with the increase of ID at the inverse layer.

VGS < VGS(th)

BVDSS

vDS

Figure 6. Output Characteristics

Transfer Characteristics
iD characteristics due to VGS in the active region (refer toFigure 7).
ID equation due to VGS:ǒ

Ǔi D + K v GS * V GS(th)

iD

2

W
K + m nC OX
2L

ActualLinearized(eq. 1)

where
mn is majority−carrier mobility;
COX is gate oxide capacitance per unit area;

0

VGS(th)Figure 7. Transfer Curve

COX = eOX / tOX;eOX is dielectric constant of the silicon dioxide;

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VGS

AN−9010/D
CHARACTERISTICS OF MOSFET IN ON AND OFF
STATEpushed into the semiconductor bulk. The holes that have notbeen pushed into the bulk are neutralized by the electrons
that have been dragged by the positive charge of the holes
from the N+ source. If the supplied voltage keeps increasing,the density of the free holes of the body and the free electronsof the interface becomes equal. At this point, the freeelectron layer is called an inversion layer. The inversion
layer enables the current flow by becoming the conductive
pass (= channel) of the MOSFETs drain and source.

OFF State

BVDSS
This is the maximum drain−to−source voltage the
MOSFET can endure without the avalanche breakdown of
the body− drain P−N junction in off state (where the gate andsource are shorted). The measurement conditions are
VGS = 0 V, ID = 250 mA, and the drift region’s (N– epitaxy)
length is determined by the BVDSS. Avalanche,reach−through, punch−through, Zener, and dielectric
breakdowns are the factors that drive breakdown. Three ofthese factors are described below:

Threshold Voltage:

The gate−to−source voltage, which forms the inverse
layer, is called VGS(th) (= threshold voltage).
VGG1

ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ

Avalanche Breakdown:

The mobile carriers’ sudden avalanche breakdown causedby the increasing electric field in the depletion region of thebody−drain P−N junction up to a critical value. It is the main
factor among others that drives breakdown.

N+

Reach−Through Breakdown:

Ionized acceptors

A special case of avalanche breakdown occurring when
the depletion region of the N– epitaxy contacts the N+
substrate.

Depletion region boundaryP

Punch−Through Breakdown:(a) Formation of Depletion Region

N−

An avalanche breakdown occurring when the depletion
region of the body−drain junction contacts the N+ source
region.

VGG2ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉIDSSThe drain−to−source leakage current when it is an off state
where the gate is being shorted with the source. The increasein IDSS, which is sensitive to temperature, is large with theincrease in temperature, while the increase in BVDSS is very
little.

N+

Free electronsP
N−

Turn−On Transient

Process of Channel Formation
When a small positive gate−to−source voltage is supplied
to the gate electrode (refer to Figure 8 (a)).
A positive charge induced in the gate electrode inducts thesame amount of negative charge at the oxide – siliconinterface (P–−body region, which is underneath the gate
oxide). The holes are pushed into the semiconductor bulk by
an electric field and the depletion region is formed by theacceptors with a negative charge.

(b) Formation of Inversion Layer
VGG3

ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉN+Formation of the Inversion Layer:

Inversion layerP

As the positive gate−to−source voltage increases (refer toFigure 8 (b) and Figure 8 (c)), the depletion region becomeswider towards the body and begins to drag the free electrons
to the interface. These free electrons are created by thermal
ionization. The free holes, created with free electrons, areN−

VGG3 > VGG2 > VGG1(c) Formation of Inversion Layer

Figure 8. Process of Channel Formationwww.onsemi.com
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AN−9010/D
ON State

To understand the characteristics, shown in Figure 9, notethe voltage drop at VCS(x) due to ohmic resistance when ID
is flowing at the inverse layer. VCS(x) is the channel−to−source voltage from the source at a distance of x. This
voltage is equal to the VGS–Vox(x) at all x points. Vox(x) is
the gate−to−body voltage crossing the gate oxide from thesource at a distance of x and it has the maximum value at VDS
at x = L (the drain end of the channel). As shown in
Figure 9 (a), when low voltage VDD = VDD1 is supplied, low
ID (= ID1), which has almost no voltage drop of VCS(x),flows. As Vox(0) ~ Vox(L) is constant, the thickness of theinversion layer remains uniform. As higher VDD is supplied,
ID increases, the voltage drop of VCS(x) occurs, and thevalue of Vox(x) decreases. These reduce the thickness of theinversion layer starting from x = L. Because of this, theresistance increases and the graph of ID starts to become flat,as opposed to increasing with the increment of VDD. When
Vox(L) = VGS – VDS = VGS(th), as ID increases, the inversion
layer at x = L doesn’t disappear due to the high electric field(J = sE) formed by the reduction in thickness, and maintains
the minimum thickness. The high electric field not only
maintains the minimum thickness of the inversion layer, italso saturates the velocity of the charge carrier at
Vox(L) = VGS – VDS = VGS(th).
The velocity of the charge carrier increases with theincrease in the electric field initially and, at a certain point,
is saturated. Silicon starts saturating when the electric fieldreaches 1.5 x 104 [V/cm] and the drift velocity of the electronis 8 x 106 [cm/s]. At this point, the device goes into the active
region. When a higher VDD is supplied, as shown in
Figure 9 (b), the electric field at x = L increases more and thechannel region that maintained the minimum thickness
expands
towards
thesource.
VDS
becomes
VDS > VGS – VGS(th), due to the increase of VDD, and ID is
kept constant.

Drain current (ID) changes due to the increase in drain−to−source voltage (VDD) (VGS is constant). ID starts to flow
when the channel has formed and VDD is supplied. When the
VGS is a constant value and the VDD is increased, the ID also
increases linearly. As shown in the MOSFET output
characteristics graph, when the real VDD goes over a certain
level, the rate of increase in ID decreases slowly. Eventually,
it becomes a constant value independent of VDD andbecomes dependent on VGS.

ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
VDD1

VGS

Vox (x)inversion

VCS (x)n+ID1

xdepletionpn−

ÉÉÉÉÉÉÉÉÉÉÉÉn+(a) Spatially Uniform

Velocity
saturation region

ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
VDD2

VGS

Vox (x)VCS (x)n+depletion

inversion

ID2Turn−off Transient

The reverse process of the turn−on transient describedabove is the turn−off transient.

L
p

n−

ÉÉÉÉÉÉÉÉÉÉÉÉn+(b) Spatially Non−Uniform

Figure 9. Inversion Layer Thickness Changes due tothe Increase of the Drain−to−Source Voltage (VDD)
where VDD1 < VGS – VGS(th), VDD2 > VGS – VGS(th),ID2 (Saturation Current) > ID1

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AN−9010/D
User’s manual

whereis the dielectric constant of the gate oxide;eox
tox
is the gate oxide thickness;
COX is gate−oxide capacitance per unit area; andAN+O is the area of overlap of the gate electrodeover the N+ emitter.

Characteristics of Capacitance

The three types of parasitic capacitance are:

• Input capacitance:
Ciss = Cgd + Cgs• Output capacitance:
Coss = Cgd + Cds• Reverse transfer capacitance: Crss = Cgd

CP is the capacitance between the gate and p−body. It isaffected by the gate, the drain voltage, and the channel
length. The CP is the only component that is influenced by
the change of the drain voltage (VDS) among other Cgs
components. When VDS increases, the depletion region
expands to the P−body and decreases the value of CP. Even
if the VDS increases up to breakdown voltage, there is almost
no change in the value of CP, as the depletion region doesn’t
exceed 10% of the P−body. Hence, the change of Cgs due to
VDS is very small.

The following figures show the parasitic capacitance.

ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ

CO

Gate

CP

N+

P−body

tO
tox

Cgd

CN +

Wd(epi.)

X/2
Cds

Cgd: Capacitance between Gate and Drain
This is influenced by the voltage of the gate and the drain.
When there are variations in VDS, the area under Cgd(n–− drift region meeting with the gate oxide) is changed,
and the value of the capacitance is affected. As shown inEquation 2, when VDS >> fB, the capacitance decreases as

N−drift

Figure 10. Vertical Structure, Parasitic CapacitanceDrain

VDS increases with the relation of C gd T ǒ1 * k ǸV DSǓ.

Cgd
C gd (per unit area) + C OX

Cds

Gate
Cgs

Figure 11. Equivalent Circuit, Parasitic Capacitance

CGS : Capacitance between Gate and Source

W d(epi.) +C gs + C O ) C N ) C P

CO is the capacitance between the gate and source metal:

tO
AO

Ǔ

2W d(epi.)
X(eq. 2)Ǹ

2k se o(V DS ) f B)qC B

As Cgd increases (1 + gfsRL (load resistance)) times dueto the Miller effect, it prominently decreases the frequency
characteristics.

åI AO
tO

where
eI

1*

where
X
is the length between adjoining cells;
COX
is gate−oxide capacitance per unit area;
Wd(epi.) is the width of the depletion region in theepitaxial layer(= N− drift region); andSourceCO +ǒFrequency Response of Power MOSFET

is the dielectric constant of the intervening
insulator;
is the thickness of the intervening insulator; andis the area of the overlap between the source
and gate electrode.

The frequency response of the power MOSFET is limitedby the charging and discharging of the input capacitance. If
the Cgs and Cgd, which determine the input capacitance,
become smaller; it is possible to work in high frequency. As
the input capacitance is unrelated to the temperature, the
MOSFET’s switching speed is unrelated to the temperature.

CN+ is the capacitance between the gate and the N+ source
diffusion region:
C N) +

å ox A N )Ot ox

+ C OXA N )O

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AN−9010/D
Cds: Capacitance between Drain and Source
The capacitance varies due to the variation of the Cds
thickness, which is the junction thickness of the P−body and
the N– drift region, with the change of VDS:
C ds (per unit area) +

Ǹ

VDD

DF

q ks eo CB

VGG

where
q

Cgd1

RG

2 ǒV DS ) f BǓis elementary electronic charge;(= 1.9 × 10−19 [C]) ks = silicon dielectric
constant;

iG

Cd

Cgs

(a) t0 ~ t1 at the Diode−Clamped Inductive Load Circuiteo

is the permeability of free space(8.86 × 10−14 [F/cm]);
CB is epitaxial layer background concentration[atoms / cm3];
VDS is drain−to−source voltage; and
fB

IO

VDD

DF

is diode potencial.
VGG

as VDS increases with the relationship of C ds T 1ń ǸV DS .
Characteristics of the Gate Charge

Cd

Cgd1

RG

As shown in the equation above, VDS >> fB Cds decreases

IO

iG

Cgs

(b) t1 ~ t2 at the Diode−Clamped Inductive Load Circuit

It is the amount of charge required during MOSFET
turn−on or turn−off transient.
The types of charges are:

VDD

• Total Gate Charge: Qg (The amount of charge during

IO

t0 ~ t4)• Gate−Source Charge: Qgs (The amount of chargeduring t0 ~ t2)• Gate−Drain (Miller) Charge: Qgd (The amount ofcharge during t2 ~ t3)

Ĥ

RG

Cgd1

+
VGG

_

Figure 12 shows the gate−source voltage, gate−source
current, drain−source voltage, and drain−source current
during turn−on. They are divided into four sections to show
the equivalent circuits at the diode−clamped inductive load
circuit.

iGĤ(c) t2 ~ t3 at the Diode−Clamped Inductive Load Circuit
VDD

IO

VGS(t)VGG

RG

VDS(t)

VDD
Va

VGG

iG

Cgd2

rDS(on)iD(t)VGS(th)iG(t)IO(d) t3 at the Diode−Clamped Inductive Load Circuit

VDS(on)
0
to

t1

t2

t3

Figure 13. Equivalent Circuits of the MOSFET with
Turn−on Divided into 4 Periods at the
Diode−clamped Inductive Load Circuitt4

Figure 12. VGS(t), IG(t), VDS(t), ID(t) When Turned On

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AN−9010/D
t0 ~ t1

VGS (t)As IG charges Cgs and Cgd, VGS increases from 0 V up to
VGS(th). The graph of increasing VGS(t) seems to be
increasing linearly, but it is, in fact, an exponential curve
having a time constant of t1 = RG(Cgs + Cgd1). As shown in
Figure 13 (a), VDS is still equal to VDD and ID is zero. The
MOSFET is still in the turn−off state.

10 [V]

Device: FQP10N20

Division:

0 [V]

VGS increases exponentially, passing VGS(th), and, as VGS
continues to increase, ID begins to increase and reaches fullload current (IO). So Va varies to IO condition in t2. When ID
is smaller than IO and when it is in a state where the DF is
being conducted, VDS maintains the VDD. Figure 14 shows
the voltage a little less than VDD. This is caused by thevoltage drop due to the existing inductance in the line.
Figure 14 shows the VGS(t) measuring the Va variation inaccordance with iD conditions in turn−on state.
10 [V]VDD = 40 [V]Test conditons:

t1 ~ t2

VGS (t)

VDD = 160 [A]VDD = 100 [V]

IO = 10 [A]
IO = 7 [A]
IO = 3 [A]

IO = 10 [V]VGS = 10 [V]VGS(t): 2 V/div.
Time: 1 ms/div.

Figure 15. VGS(t) in Accordance with the VDD
Condition
t3 ~ t4

t3 ~ t4 is the period where it operates in an ohmic region.
The VGS increases up to VGG with a time constant of
t2 = RG (Cgs + Cgd2).
Drain−Source On Resistance (RDS(on))ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
Gate

RN +

RCH

Division:

0 [V]P−bodyRJ

Device: FQP10N20
Test conditons:

N+

RA

VDS = 160 [V]VGS = 10 [V]VGS(t): 2 V/div.
Time: 1 ms/div.

Figure 14. VGS(t) in Accordance with ID Conditions

RD

N−driftÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉRS

N−substrate

Drain

t2 ~ t3

VGS is a constant value in accordance with the transfer
characteristics as it is in an active region where ID is the fullload current (IO). So, IG can only flow through Cgd and is
obtained by Equation 3.
iG +Figure 16. The Vertical Structure of a MOSFET
Showing Internal ResistanceIn a MOSFET, RDS(on) is the total resistance between thesource and the drain during the on state. It is an importantparameter, determining maximum current rating and loss.
To reduce RDS(on), the integrity of the chip and trenchtechnique are used. This can be stated as in Equation 5:

V GG * V a
RG(eq. 3)

VDS can be configured as the following ratios:
dv DG
dt

+

dv DS
dt

+

iG
C gd

+

RN

V GG * V a
R GC gd)) R CH ) R A ) R j ) R D ) R S(eq. 5)

where
RN+ The resistance of the source region with N+
diffusion. It only uses a small portion ofresistance compared to other components thatform RDS(on). It can be ignored in high−voltage
power MOSFETs.
RCH The resistance of the channel region, which is thedominant RDS(on) factor in low−voltage
MOSFETs. This resistance can be varied by theratio of the channel’s width to the length, the(eq. 4)This is the region where the MOSFET is still operating in
the active region and, as the VDS decreases, it gets closer tothe ohmic region. When VDD increases, t2 ~ t3 (flat regionof VGS) also increase.
Figure 15 graphs VGS(t) and shows the variation of t2 ~ t3(flat region of VGS) in accordance with the VDD condition.
At t3, VDS becomes VDS(on)=IO ⋅ RDS(on) and the transient
is completed. The MOSFET is placed at the boundary ofentering the ohmic region from the active region.

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AN−9010/D

RA

RJ

RD

RS

Low VGS(th)thickness of the gate oxide, and the gate drive
voltage.
As the gate drive voltage is supplied, charges startto accumulate in N– epi surface (the plate underCgd) and forms a current path between thechannel and the JFET region. The resistance of
this accumulation region is RA. The resistancevaries by the charge in the accumulation layer andthe mobility of the free carriers at the surface. If
the gate electrode is reduced, its effect is the sameas reducing the length of the accumulation layer,
so the value of RA is reduced while RJ increases.
The N– epi region between the P−bodies is called
the JFET region because the P−body region acts
like the gate region of a JFET. The resistance of
this region is RJ.
The resistance occurring from right below theP−body to the top of the substrate is RD and is themost important factor in high−voltage
MOSFETs.
The resistance of the substrate region. It can beignored in high−voltage MOSFETs. In
low−voltage MOSFETs, where the breakdown
voltage is below 50 V, it can have a large effect on
RDS(on).

When the VGS(th) of the N−channel power MOSFET
becomes negative due to the existence of charges in the gate
oxide, it shows the characteristics of a normally on state,
where the conductive channel exists even in a zero− gate bias
voltage. Even if VGS(th) is positive and the value is verysmall, there could be a turn−on either by the noise signal of
the gate terminal or by the increasing gate voltage duringhigh−speed switching.
VGS(th) can be controlled by the gate oxide thickness.
Normally, gate oxide is kept thick in a high−voltage device
so the VGS(th) is set at 2 V ~ 4 V. Gate oxide is kept thin ina low−voltage device (logic level) so VGS(th) is 1 V ~ 2 V.
Additionally, VGS(th) can be controlled by background
doping (the density of P−body for the N−channel power
MOSFET). It increases in proportion to the square root of
the background doping.
Temperature Characteristic
VGS(th) decreases as the temperature increases. The rate ofdecrease can be varied by the gate oxide thickness andbackground doping level. In other words, the decrease rateincreases when the gate oxide becomes thicker and thebackground doping level increases.
Transconductance (gfs)

Transconductance is the gain in the MOSFET, expressedin Equation 7. It represents the change in drain current by thechange in the gate−source bias voltage:

Additional resistances can arise from non−ideal contact
between the source/drain metal and the N+ semiconductor
regions, as well as from the leads used to connect the device
to the package.
RDS(on) increases with the temperature (positive
temperature coefficient) because the mobility of the holeand electron decreases as the temperature rises. The RDS(on),at a given temperature of a P/N−channel power MOSFET
can be estimated with the following equation.
R DS(on) (T) + R DS(on) (25°C) (

where
T

T 2.3
)
300

g fs +ƪ ƫ
DI DS

DV GS V(eq. 7)DS

VDS should be set so that the device can be activated in thesaturation region. VGS should be supplied so that the IDS
becomes half of the maximum current rating. gfs varies
depending on the channel width/length and the gate oxide
thickness. As shown in Figure 17, after VGS(th) is applied, gfs
increases dramatically with the increase in the drain current
and becomes a constant after drain current reaches a certain
point (at higher values of drain current). If gfs is high enough,high current handling capability can be gained from the low
gate drive voltage. High−frequency response is also
possible.

(eq. 6)is absolute temperature.

This is an important characteristic of device stability andparalleling. It doesn’t need any external circuit assistance tohave good current sharing when RDS(on) increases with thetemperature and is connected in parallel.

iD

g fs +

Threshold Voltage (VGS(th))

ActualThis is the minimum gate bias that enables the formationof the channel between the source and the drain. The draincurrent increases in proportion to (VGS – VGS(th))2 in thesaturation region.

DI DS
DV GS

LinearizedHigh VGS(th)0

It is difficult to design gate drive circuitry for the power
MOSFET because a high gate bias voltage is needed to turnit on.

VGS(th)VGS

Figure 17. Transfer Curve & gfs

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AN−9010/D
Drain−to−Source Leakage Current (IDSS)

Temperature Characteristic
gfs decreases as the temperature increases due to the
reduction of mobility. Equation 8 is similar to the RDS(on)and temperature relationship; it is possible to know the gfs
changes by the changes in temperature:g fs(T) + g fs(25°C) (

where
T

T *2.3)300

IDSS can be measured by providing the maximum
drain−to− source voltage and 80% of the voltage(TC = 125°C) in the off state, where the gate is shorted to thesource. IDSS is more sensitive to the temperature than
BVDSS and it has a positive temperature coefficient.

(eq. 8)Gate−to−Source Voltage (VGS)

VGS represents the maximum operating gate−to−source
voltage. The negative voltage handling capability enables
the enhancement of the turn−off speed by providing reverse
bias to the gate and the source.

is absolute temperature.

Drain−Source Breakdown Voltage (BVDS Breakdown
Voltage Temperature Coefficient (DBV/DTJ)

Gate−Source Leakage, Forward / Reverse (IGSS)BVDSS is the maximum drain−to−source voltage where
the MOSFET can endure without the avalanche breakdownof the body−drain pn junction in off state (where the gate andsource are shorted). The measurement conditions are
VGS = 0 V, ID = 250 mA, and the length of the drift region(N– epitaxy) is determined by the BVDSS. Avalanche,reach− through, punch−through, Zener, and dielectric
breakdowns are the factors that drive breakdown.

IGSS is measured by providing the maximum operatinggate− to−source voltage (VGS) between the gate and thesource. Forward or reverse direction is determined by thepolarity of the VGS. IGSS is dependent on the quality of thegate oxide and device size.
Switching Characteristics (td(on), tr, td(off), tf)

Power MOSFETs have good switching characteristics as
there is no storage delay caused by the minority carrier andno variation caused by the temperature. Figure 19 shows theswitching sequence divided into sections.

Temperature Characteristic
As junction temperature increases, it does so linearly.
Whenever it goes up 100°C, 10% of BVDSS at 25°C
increases (refer to the breakdown voltage temperature
coefficient (DBV/DTJ) and Figure 18 breakdown voltage vs.
temperature).

Vout

Vin

90 [%]

10 [%]trtd(on)tontd(off)tf
toff

Figure 19. Resistive Switching Waveforms

Figure 18. Breakdown Voltage vs. Temperature

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AN−9010/D
Table 2. SWITCHING CHARACTERISTICS
Turn−On Delay (td(on)):This is the time for the gate voltage, VGS, to reach the threshold voltage VGS(th). The input capacitance during
this period is Cgs+Cgd. This means that this period is the charging period to bring up the capacitance tothe threshold voltage.

Rise Time (tr):

It is the period after the VGS reaches VGS(th) to complete the transient. It can be divided into two regions.
One is the period where the drain current starts from zero (increasing with the gate voltage in accordancewith the transfer characteristics) and reaching the load current. The other region is when the drain voltage
starts to drop and reaches the on−state voltage drop. As shown in the gate charge characteristics graph,
the VGS maintains a constant value as the drain current is constant in this region where the voltage
decreases. During the rise time, as both the high voltage and the high current exist in the device, highpower dissipation occurs. The rise time should be reduced by reducing the gate series resistance andthe drain−gate capacitance (Cgd). After this, the gate voltage continues to increase up to the supplied voltage level; but, as the drain voltage and the current are already in steady state, they are not affected during
this region.

Turn−Off Delay (td(off)):

The gate voltage operates in the supplied voltage level during On state and, when the turn− off transient
starts, it starts to decrease. The td(off) is the time for the gate voltage to reach the point where it is required
to make the drain current become saturated at the value of load current. During this time, there are nochanges to the drain voltage and the current.

Fall Time (tf):Fall time is the time where the gate voltage reaches the threshold voltage after td(off). It is divided into theregion where the drain voltage reaches the supply voltage from On−state voltage and the region where
the drain current reaches zero from the load current. As there is a lot of power dissipation in the tr region
during turn−on state, the power dissipation occurs in the tf region during turn−off state. Hence, tf must be
reduced as much as possible. After this, the gate voltage continues to decrease until it reaches zero. As
the drain voltage and the current are already in steady state, they are not affected during this region.

Single–Pulsed Avalanche Energy Unclamped
Inductive Switching (EAS)

underneath the source is large enough; the parasitic bipolartransistor becomes active and can result in device failure.
Figure 20 shows the drain voltage and the current when asingle pulse (width: tP) is supplied at the unclamped
inductive load circuit.

MOSFET Turn−Off (Inductive Load Circuit)
While in on state (supplying positive voltage exceeding
the threshold voltage in N−channel device), the electrons
flow into the drain from the source through the inversion
layer (= channel) of the body surface and form a current flowfrom the drain to the source. If it is an inductive load, thiscurrent increases linearly. To turn off the MOSFET, the gate
voltage must be removed or a reverse voltage applied so that
it eliminates the inversion layer of the body surface. Oncethe charge at the inversion layer begins to dissipate and thechannel current (drain current) begins to reduce, theinductive load increases the drain voltage so that it maintains
the drain current. When the drain voltage increases, the draincurrent is divided into the channel current and thedisplacement current. Displacement current is the current
generated as the depletion region is developed at thedrain−body diode and it is proportional to dvDS/dt (the ratioof drain voltage rise by the time). The dvDS/dt is limited by
how fast the gate is discharged and by how fast thedrain−body depletion region is charged. The charge of thedrain−body depletion region is determined by Cds and themagnitude of the drain current. When the drain voltage
increases and cannot be clamped by an external circuit UIS(Unclampled Inductive Switching), the drain−body diodestarts to build the current carriers through avalanche
multiplication and the device falls into a Sustaining Mode.
While in Sustaining Mode, all the drain current (avalanche
current) goes through the drain−body diode and is controlled
by the (channel current equals to zero) inductor load. If thecurrent (leakage current, displacement current (dvDS/dt
current), and avalanche current) flowing at the body region

BVDSS
IAS

ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ

ID (t)
VDD

tp

tAV

VDS (t)Time

Figure 20. Unclamped Inductive Switching
Waveforms

ID(t) can be changed by the inductor load size, supply
voltage (VDD), and the gate pulse width (tP). The shaded
area of the avalanche region (tAV) shows the dissipationenergy (EAS). Calculate EAS and tAV with Equation 9:
E AS +BV DSS
1
2
L L I AS
2
BV DSS * V DD
t AV +

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L L I ASBV DSS(eq. 9)AN−9010/D
False Turn−on

Power MOSFET Failure Characteristics during InductiveTurn−OffIt has the same electrical characteristics as the second
breakdown of the bipolar transistor. It is independent fromdvDS/dt. By maintaining the gate turn−off voltage constantly
and changing the magnitude of the external gate resistance,
the magnitude of the gate turn−off current changes. Thischanges the dVDS/dt. If dVDS/dt current causes a device
failure, the voltage that can lead to a second breakdown
should be decreased with an increase in dVDS/dt. Whenmeasuring the second breakdown voltage while changing
the external gate resistance (changing dVDS/dt), the highest
voltage should be measured at the highest dVDS/dt(according to “Turn−Off Failure of Power MOSFETs,” byDavid L. Blackburn). The voltage at which failure occurs
increases with temperature. Critical current reduces astemperature increases. Critical current represents the
maximum value of the drain current that can safely turn off
the device in an unclamped mode. At currents exceeding
this, a second breakdown occurs. It is not related to themagnitude of the load inductance. The avalanche current
from the drain−body diode activates the parasitic bipolartransistor. This causes the MOSFET to fail.

In off state, a sudden increase in drain voltage changes thevoltage across the parasitic capacitance between the drain
and the gate and develops displacement current (a) of
Cdv/ dt. If voltage exceeding VGS(th) develops between thegate and source due to the displacement current and thegate−to− source impedance (Zgs), it triggers a false turn−onof the MOSFET. The parasitic capacitance between thedrain and gate can be Cgd or larger than Cgd, depending on
the circuit layout. Zgs is the impedance of the drive circuitand can be presented as a series of R, L battery components.
Due to the false turn−on, the device falls into acurrent−conduction state and, in severe cases, high power
dissipation develops in the device and results in destructive
failure. Equation 10 shows the voltage drop VGS across Zgs,
and dv/dt capability in this mode:
V GS + Z gs C gd

V GS(th)ƪdvdtƫ + Z C
gs

Repetitive Avalanche Rating (EAR, IAR)

It represents avalanche energy for each pulse under
repetitive conditions.

IAR

It represents the maximum avalanche current and is thesame as the ID rating of the device.

In off state, a sudden increase in drain voltage changes thevoltage across Cdb, and it develops current (b) flowing
through Rb. When the voltage across the Rb goes over Vbe(emitter−base forward bias voltage where the parasitic
bipolar transistor is turned on, approximately 0.7 V), theparasitic bipolar transistor is turned on. When the parasitic
bipolar transistor is turned on, the breakdown voltage of thedevice is reduced from BVCBO to BVCEO, which is 50 ~ 60%
of BVCBO. If a drain voltage larger than BVCEO is supplied,the device falls into an avalanche breakdown. If this draincurrent is not limited externally, the device can be destroyedby the second breakdown. The following equation shows the
dv/dt capability in this mode:

When high dv/dt is supplied at the drain, there is apossibility of current conduction in the power MOSFET. In
some cases, this can destroy the device. Below are someinstances of device turn−on due to dv/dt.
Static dv/dt
Drain
a
b
Cdb

ƪdvdtƫ + RVC

dv
NPN
Cgs
Zgs

(eq. 10)

Parasitic Transistor Turn−on

Drain−to−Source dv/dt Ratings

Gate

gd

To increase dv/dt capability, a gate drive circuit with very
low impedance should be used and VGS(th) must be
increased. In a drive circuit with low impedance, the cost ishigh and increasing the VGS(th) is associated with rise in
RDS(on). As VGS(th) has a negative temperature coefficient,
the possibility of a false turn−on increases as the temperaturerises. Typically, gate voltage doesn’t go over the thresholdvoltage and the high device resistance limits the device
current. Device destruction due to false turn−on is rare.

EAR

Cgd

ƪdvdtƫ

be

dt

b

Rb

db

(eq. 11)Equation 11 reveals that the dv/dt capability is determinedby the internal device structure. For high−dv/dt capability,
the Rb value must be small. This is achieved by increasing
the doping level of the P−body region and reducing thelength of the N+ emitter as much as possible. Rb is also
affected by the drain voltage. As the drain voltage increases,
the depletion layer expands and enlarges the Rb value. When

SourceFigure 21. Equivalent Circuit of a N−Channel
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AN−9010/D
the temperature rises, Rb is increased by the reduction ofmobility. As the Vbe decreases, the possibility of turn−on of
the parasitic transistor increases. As the base and the emitterare shorted by the source contact, the Rb value is very small.
This occurs only if the dv/dt is enormously large.
In a false turn−on, the dv/dt can be controlled externally.
In a parasitic transistor’s turn−on, the dv/dt is determined bydevice design. This is the difference between these modes.

DUT
VDS
−
IS

RG

Dynamic dv/dt
If there is a sudden current interruption, such as a clamped
inductive turn−off in high−speed switching, the device isdestroyed by concurrent stresses caused by high draincurrent, high drain−source voltage, and displacement
current at the parasitic capacitance.

L

Drive

Same Type as DUT
VDD

VGS

* dv/dt controlled by RG* IS controlled by pulse period

Figure 23. Diode Recovery dv/dt Test Circuit

Diode Recovery dv/dt
This is the main cause of dv/dt failure in specificapplications, such as circuits using a body drain diode. The
datasheet gives the maximum value for dv/dt. Exceeding
this value causes device failure due to excessive dioderecovery dv/dt. Figure 22 shows a motor control circuit
application with a diode recovery dv/dt problem.

VGS(Driver)D+

10 [V]IFM , Body Diode Forward Current
IS
(DUT)

di/dt

Body Diode Reverse Current, IRM
Q1

Q

VDD
−

Motor
Q3

trr
a

b

10 [%] of IRM

Body Diode Recovery
dv/dt

2

i1

GatePulseWidth
GAtePulsePeriod

VDS
(DUT)

Q4
i2

VF (= VSD )VDDBody Diode Forward Voltage Drop

Figure 24. Diode Reverse Recovery Waveforms
Figure 22. Motor Control Circuit

The value of di/dt and dv/dt becomes larger as RG is
reduced. trr can be obtained by measuring the part shown in
the wave of IS where the di/dt (measured from the point
where it is 50% of IFM above the ground to the point where
it is 75% of IRM below the ground) is 100 A/ms. Qrr can becalculated as (IRM × trr)/2. dv/dt can be measured from thepoint where it is between 10~90% of VDD with the di/dt
condition (measured from the point where it is 50% of IFM
above the ground to the point where it is 75% of IFM below
the ground). IS (continuous source current) and ISM (pulsed– source current) represent the current rating of the source−
drain diode, IS = ID (continuous drain current), and
ISM = IDM (drain current – pulsed).

First Q1 and Q4 are conducted and put in a state where
current I1 passes. If Q1 is turned off to control the speed ofthe motor, the current flows through the parasitic diode(freewheeling diode) of Q3 as I2. The parasitic diode of Q3
falls into a forward bias state and, due to the characteristicof the diode, the minority charge begins to accumulate.
When Q1 is turned on, the current again becomes I1 and theminority charge accumulated in the parasitic diode, Q3, isremoved by the diode reverse−recovery current (Figure 23
section a of IS). Once the minority charge is removed to acertain level, the depletion region of the body drain diodeexpands and makes more reverse−recovery current(Figure 23 section b of IS). If this turns on the parasitic
bipolar transistor, Q3 is destroyed. Figure 23 and Figure 24
show the diode recovery dv/dt test circuit and waveforms.
From this test; dv/dt, VSD (diode forward voltage), trr(reverse− recovery time), and Qrr (reverse−recovery charge)
data can be obtained. In the test, the VDD value must be lessor equal to the BVDSS. Typically, the VDD is set at 80% of
BVDSS and the pulse period of the driver VGS must be
controlled so that the IS can become the continuous draincurrent ID.

Thermal Characteristics (TJ, RqJC, RqSA, ZqJC(t))

The power loss of the device turns into heat and increases
the junction temperature. This degrades device
characteristics and reduces its life span. It is very important
to lower the junction temperature by discharging heat fromthe chip junction. The thermal impedance (ZqJC(t)) is used
to monitor the above.
Thermal characteristics terminology:• Junction Temperature (TJ)

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AN−9010/D• Case Temperature (TC): Temperature at a pointR qJC +of the package that has the semiconductor chip inside.
• Heat Sink Temperature (TS)• Ambient Temperature (TA): Temperature of thesurrounding environment of the operating device.
• Junction−to−Case Thermal Resistance (RqJC)• Case−to−Sink Thermal Resistance (RqCS)• Sink−to−Ambient Thermal Resistance (RqSA)
Compoun

Chip

D

TJ

Case−to−Ambient Thermal Resistance (RqCA )This is the thermal resistance from the heat sink to theambient and it is determined by heatsink design.

TC

Heat Sink¬

Ambient

Thermal Response Characteristics
Figure 27 shows the thermal response curve. As show in
Figure 27, the graph of the thermal response, shows thechange of junction−to−case thermal impedance (ZqJC(t))
due to the change of the square−wave pulse duration with afew duty factor conditions. ZqJC(t) determines the junction
temperature rise with the Equation 14. (considering power
dissipation to be a constant value (PDM) during the
conduction period, it becomes saturated to the maximum
value of (RqJC) as it reaches low frequency or DC operation
where the duty factor D = 1. Figure 28 shows the junction
temperature rise with the increasing duty factor.

TS

TA

Figure 25. Thermal Discharge Path at Chip Junction

Junction

Case

PD

TJ

Sink

TC

Ambient
RqSA

RqCS

RqJC

TS

(eq. 13)This is the thermal resistance from the package case to theheat sink. It can vary due to the package and the mounting
method to the heat sink.

¯
Case[°CńW]

Case−to−Sink Thermal Resistance (RqCS )

S

®

PD

Condition TC = 25°C means the infinite heat sink ismounted.
Infinite heat sink means the case temperature of the
package is equal to the environment temperature. It is theheat sink, which can realize TC = TA.

­G

TJ * TCTA

T Jmax * T C + R qJC @ P DM

(eq. 14)

Figure 26. Circuit Based on Thermal Resistance

As shown in Figure 25, the heat produced at the chipjunction normally discharges over 80% in the direction of① and about 20% in the direction of ②③④. The pathof the thermal discharge is the same as the movement of thecurrent and is represented in Figure 26 after considering
thermal resistance. This is true only for DC operation. Most
MOSFETs are used in switching operations with a fixed duty
factor. Thermal capacitance should be taken into
consideration, along with thermal resistance. The thermal
resistance from the chip junction to the ambient is RqJA
(junction−to−ambient thermal resistance) and the equivalentcircuit can be expressed as Equation 12.
R qJA + R qJC ) R qCS ) R qSA

Figure 27. Transient Thermal Response Curve
PDM
t11

t12
t2

Junction Temperature(TJ )T(eq. 12)

J12

TJ11

Junction−to−Case Thermal Resistance (RqJC )RqJC is the internal thermal resistance from the chipjunction to the package case. Once the size of the die isdecided, this thermal resistance of pure package is only
determined by the package design and lead frame material.
RqJC can be measured under the condition of TC = 25°C andcan be written as Equation 13:

TC

0

t11

t12

Time (t)Figure 28. Resistance; Charge in Junction
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AN−9010/D
A single−pulse curve determines the thermal resistancefor repetitive power pulses having a constant duty factor (D),as shown in Equation 15.
R qJC(t) + R qJC @ D ) (1 * D) @ S qJC(t)Linear derating factor is calculated by:
1
R qJC(eq. 19)(eq. 15)

Safe Operating Areas (SOA)

where
ZqJC(t) is the thermal impedance for repetitive
power pulses with a duty factor of D;
SqJC(t)ID
IDM

SOA (FBSOA)
It defines the maximum value of the drain−source voltage
and drain current that guarantees safe operation when thedevice is at the forward bias.

is the thermal impedance for a single pulse;
is continuous drain current; andis drain current, pulsed.

As shown in Equation 16, the ID rating is determined by
the heat removal ability of the device. Figure 10 in thedatasheet, maximum drain current vs. case temperature,shows increasing permissible ID as TC decreases.
I D(T C ) +Ǹ

T Jmax * T C

R DS(on) (T Jmax ) @ R qJC(eq. 16)

whereis the maximum value ofRDS(on)(TJmax)
on−resistance in an appropriate drain current
1
condition ( @ I D in datasheet) at TJmax. as
2
maximum RDS(on) specified is at TC = 25°C.
RDS(on) (TJmax) could be analogized by the graph ofon−resistance vs. temperature;
RqJC
TC

Figure 29. Maximum Safe Operating Area

Boundaries
Figure 29 shows the maximum safe operation area.
In Figure 29, the right line: maximum drain−source
voltage rating.
The horizontal line: DC is the maximum rated continuous
drain current at TC = 25°C. For MOSFETs, excluding
package limitations, maximum rated continuous draincurrent can be determined by the RDS(on)(TJmax), as inEquation 20.

is maximum junction−to−casethermal resistance; andis case temperature.

In real device applications where it is not feasible tomaintain the temperature at TC = 25°C, the ID (60 ~ 70% of
ID at TC = 25°C) at TC = 100°C is a more usable
specification.

I D(T C ) +Drain Current − Pulsed (IDM )The drain current over continuous drain current rating
should not go over the maximum junction temperature. The
maximum upper limit is IDM. IDM is about four times thevalue of ID, as shown in Equation 17.
I DM + I D (T C + 25[°C] )4

R DS(on) (T Jmax ) @ R qJC

I DM + I D(T C )(eq. 20)

4(eq. 21)

The Upper Limit with Positive (+) Slope

The boundary where the power can be limited by thedrain− to−source on resistance.

(eq. 17)

The Upper Limit with Negative (−) Slope

It is determined by the transient thermal impedance andthe maximum junction temperature.

Total Power Dissipation (PD), Linear Derating Factor
2

T Jmax * T C

Single pulse is the maximum rated drain current, pulsed:

Repetitive rating: Pulse width limited by maximum
junction temperature.

P D(T C ) + I D (T C ) @ R DS(on)(T Jmax) +ǸT Jmax * T C
R qJC(eq. 18)

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AN−9010/D

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Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative