Revelation of Soft-Switching Operation
for Isolated DC to Single-phase AC Converterwith Power Decoupling
Nagisa Takaoka, Jun-ichi Itoh
Dept. of Electrical Engineering
Nagaoka University of Technology
Nagaoka, Niigata, Japanntakaoka@stn.nagaokaut.ac.jp, itoh@vos.nagaokaut.ac.jp
Abstract— This paper discuses soft-switching range in an
isolated single-phase matrix converter with a center-tapped
transformer for HVDC (high voltage direct current) power
feeding systems. The proposed converter consist of a full bridge
inverter, a high frequency transformer and a matrix converter
which it does not require a bulky electrolytic capacitor. The power
decoupling operation is accomplished by the center-tapped
transformer and a small LC buffer. In comparison with aconventional DC to single-phase AC converter without power
decoupling operation, the proposed circuit partly achieve the Zero
Voltage Switching (ZVS) operation of the full bridge inverter on
the primary side of the transformer. In this paper, a principle of
ZVS using the LC buffer circuit is described. From a simulation
result, the soft-switching operation is confirmed at low load
current region by using the LC buffer. Meanwhile it isexperimentally confirmed that the proposed power decoupling
method reduces the DC bus current ripple by 85.1%. In addition,
the ZVS operation on the primary side of the proposed DC tosingle-phase AC converter is confirmed in experiment.
Keywords—matrix converter; power decoupling; Zero voltage
switching;I.

INTRODUCTION

Recently, power consumption of ICT (information andcommunication technology) equipment in buildings andfactories has been drastically increased. As a solution forenergy saving, a High Voltage Direct Current (HVDC) power
feeding system has been developed previously [1-2]. In the
HVDC power feeding system, a DC bus of 380 V is applied inorder to obtain high efficiency and low cost due to the reductionof converters and cables, compared to conventional AC or DC
48 V power feeding system. A DC to single-phase AC converter
is required because the HVDC power feeding system isconsidered to not be able to replace entirely the conventional
AC power feeding system in the near future. In addition, the DC
to single-phase AC converter requires isolation capability
between the DC bus and the AC output side for safety.
One of the most significant problems, a power ripple whichis generated by a single-phase load becomes a twice of acommercial frequency. In past works, some circuit topologies
with power decoupling capability have been studied [3-5].

However, these circuits restrict the down-sizing because thecircuits employ not only passive components but also additionalswitching devices for the power decoupling. In order toovercome this problem, the authors have already proposed thepower decoupling method for the isolated DC to single-phase
AC converter in [6-7]. The proposed system consists of a fullbridge inverter, a center- tapped transformer, a small LC buffer
and a matrix converter. The proposed converter does not require
extra switching devices for the power decoupling. In addition,
smaller size compared to the conventional system is also
expected because the bulky electrolytic capacitor is not required.
The modulation method of the matrix converter used in [7] isapplied with PDM (Pulse Density Modulation)which is ZVS(Zero Voltage Switching) is achieved by synchronization of thegate pulses of the matrix converter with zero voltage term of thesecondary voltage of the transformer. Therefore, the PDM candrastically reduce the switching loss in the secondary side.
However, in order to achieve higher efficiency, the switchingloss in the primary side is also necessary to be reduced in the
proposed converter.
This paper discusses the achievement of the ZVS conditionat the primary side of the isolated DC to single-phase AC
converter using matrix converter. The primary converter canpartly achieve ZVS even when a differential current which
delivers the power to the secondary side of transformer is below
the lower limit value. Moreover, when the matrix converter
output voltage is zero, the proposed converter can partly
achieve ZVS. These reason is that there is the constant common
current of the buffer circuit is overlapping to the transformer
current.
This paper is organized as follows; first, the circuit
configuration of the proposed DC to single-phase AC converter
and the principle of the power decoupling are described; second,the ZVS condition at the primary inverter are method; finally,
the fundamental operation waveforms of the proposed system
when the ZVS condition is achieved at the primary side isevaluated by simulations and experiments.

II.

Ibus

CIRCUIT TOPOLOGY

Fig. 1 shows a conventional isolated DC to single-phase AC
converter. The conventional circuit comprises a full bridge
inverter, a high frequency transformer and a rectifier-inverter
system. The full bridge inverter outputs square voltage at highfrequency in order to reduce the transformer volume. The
secondary rectifier converts the high frequency voltage to DC
voltage and the PWM inverter controls the output filter capacitor
voltage by feedback control. When the load current is sinusoidal
waveform and achieves the unity power factor, the instantaneous
output power pout is expressed by (1).
pout  2Vload sino t   2 I load sino t  Vload I load 1  cos 2o t   Pout 1  cos 2o t Fig. 2 shows the isolated DC to single-phase AC converter
using a matrix converter and a small LC buffer which is
proposed in this paper. The matrix converter is employed as asecondary converter in order to eliminate the DC-link capacitor
which is used in Fig. 1. In addition, a center-tapped transformer
links the full bridge inverter to the matrix converter for isolationand the power decoupling which results in reducing the DC bus
current ripple. A buffer circuit including a buffer capacitor Cbuf
and a buffer inductor Lbuf is used to absorb the power ripple. It
should be noted that a charge and a discharge to compensate thepower ripple is implemented at Cbuf.
Fig. 3 shows the principle of the power decoupling with Cbuf.
In order to yield the DC bus current without the ripple, therelationship among the output power pout, a DC bus power pbus
and the charged power pbuf is defined as (2).

Full bridge Inverter

Cout Rload

vout

Diode rectifier

vload

PWM inverter

Fig. 1. A Conventional isolated DC to single-phase AC converter. The
conventional converter uses a bulky electrolytic capacitor Cdc to absorb a power
ripple caused by single-phase load.

Aibus phase
vap

Cds

Sap
Vbus

Bphase
Cds
vbp

Sbp
iinv
vinv

van

Cds

San

S2ap
ia

is

ib

vs

ibuf
Lbuf

Cds

vbn Cbuf

Sbn

Full bridge Inverter

iout

S2bp

iload

Lout
Cout Rload

vout

vload

S2bn

S2an
vbuf

Matrix converter

Buffer circuit

Fig. 2. A Proposed isolated DC to single-phase AC converter. The secondary
converter is replaced with a matrix converter in order to eliminate a DC-linksmoothing capacitor. In addition, a center-tapped transformer and a small LC
buffer are employed to achieve a power decoupling without additionalswitching devices.
vCbuf
VCmax
VCmin

Vbus

t

0

Ibus

＋

vload
vload  2Vload sin o t 

t

0

ibuf

＋

iload

charget0＋iload  2 I load sin o t 

t

0

t

0

t

0

discharge
pbus

pbuf

pout

chargedischarge＝

where, the polarity of pbuf is defined as positive when Cbuf ischarged. It should be noted that the capacitance of the buffer
capacitor is smaller than one in the conventional converter
because the power ripple is compensated by varying the buffer
capacitor voltage vCbuf not by the large capacitance. On the other
hand, the inductor in the buffer circuit is used for the current
control in the power decoupling, which is equivalent to controlof pbuf. The buffer current control is carried out by the full bridge
inverter. The full bridge inverter can outputs independently adifferential mode voltage to excite the transformer and acommon mode voltage to compensate the power ripple with the
LC buffer, owing to the center-tapped transformer. Therefore,
the proposed converter does not require additional switching
devices for the power decoupling and number of devices in the
proposed converter is as same as one of the conventional circuit.

Cdc

＝



Lout

Vbus

＝

pbuf  Pout cos2o t  iout iload

N1 N2



where, Vload is the load voltage (RMS), Iload is the load current(RMS), Pout is the output mean power and ωo is the output
angular frequency. A ripple component shown in the second
term of (1) should be bypassed in order to obtain a constant DC
current in the DC bus. Hence, this system has to adopt a bulky
electrolytic capacitor Cdc to absorb the power ripple.



Ldc

＝
t

0

Input powerpbus [W]t0

Buffer powerpbuf [W]0tOutput power
pout [W]Fig. 3. A principle of the power decoupling with the buffer capacitor. A buffer
power to compensate the power ripple is charged or discharged at Cbuf. As aresult, the DC bus current without the ripple component is obtained.

III.

CONTROL STRATEGY

A. Full Bridge Inverter
Fig. 4 shows the modulation method of the full bridge
inverter. As mentioned above, the full bridge inverter outputs adifferential mode voltage vdif to excite the transformer and acommon mode voltage vcom to compensate the power ripple.
Therefore, a differential mode voltage reference vdif* and acommon mode voltage reference vcom* are set as input
parameters in Fig. 4. It should be noted that the gain of 0.5 isinserted to only the path of vdif* because the reference potentialof vdif* is different from one of vcom*. In order to obtain the
maximum secondary voltage of the transformer, vdif* is set to 1
p.u.. On the other hand, vcom* is calculated by a PI controller inthe buffer current control to compensate the power ripple asmentioned in chapter IV
Fig. 5 shows the operation modes of the full bridge inverter.
The hatched gray line indicates the turned off switch and theblack solid line shows the current pathway. Fig. 5 (a) and (b)illustrate the differential mode when the DC bus power istransferred. In this mode, the transformer is excited. In addition,
the buffer circuit voltage, which is equivalent to vcom, is constantat Vbat/2. On the other hand, Fig. 5 (c) and (d) show the common
mode to control the buffer current ibuf in order to compensate thepower ripple. In the common mode, the transformer is not
excited because vdif becomes zero. By this method, the fullbridge inverter can control vdif and vcom independently because
only one of the differential mode vdif and the common mode vcom
is varied at one time. This results in that the proposed converter
does not require additional switches for the power decoupling.
B. Power Decoupling Method
In order to absorb the power ripple caused by the singlephase load, the buffer current reference ibuf* is calculated frompout* and the chargeable energy of Cbuf. First of all, the buffer
capacitor energy WCbuf is presented by (3).
WCbuf tt0

pbuf d t P cos2  d (3)
t0

out

o

vdif*=1

1/2
vcom*

+

S1an
1
0

-1

vCbuf VbusP
 out sin2ot  4
oCbuf(4)

where, VC0 is the initial voltage of Cbuf and VC0 is Vbus/2. Finally,
ibuf* is derived by using the output power reference Pout*.
*ibuf  Cbuf

dvCbufdt*

Pout cos 20 t 
*



2

*



(5)

Vbus
P
 out sin2o t 4o Cbuf

It should be noted that Pout* is calculated by a load resistance.
Therefore, the power ripple is compensated by using the buffer
current control with the current reference ibuf* as shown (5).

S1bn

Carrier

S1bp(a) Block diagram

S1ap

S1bp
vcom

S1an

vdif
Lbuf

S1bn

Cbuf

(b) Definition of vdif and vcom
Fig. 4. A modulation method of a full bridge inverter. A differential mode
voltage reference vdif* excites the transformer and a common mode voltage
reference vcom* is used to compensate the power ripple with the LC buffer.
S1ap

S1bp

S1ap
vcom

S1an

S1an

vcom
S1an

S1bn

(b) Differential mode 2.

S1bp

S1ap

S1bn

vdif

(vdif = -Vbat, vcom = Vbat/2)(vdif = Vbat, vcom = Vbat/2)(a) Differential mode 1.

S1ap

S1bp

vdif

S1bn

(vdif = 0, vcom = Vbat)(c) Common mode 1.

2

+
-

vcom

where, t0 is the start time of operation. If t0 is zero, vCbuf which
need to compensate the power ripple is calculated as following
by using (3).

S1ap

-

S1bp
vcom

vdif
S1an

vdif

S1bn
(vdif = 0, vcom = 0)(d) Common mode 2.

Fig. 5. Operation modes of the full bridge inverter at the primary side. The
primary side of the proposed system has two mode; a differencial mode which
delivers the power to the secondary side of transformer and a common mode
which reduce the the power ripple.

C. Matrix Converter
The matrix converter used as a secondary converter in the
proposed system is applied with the PDM of [7]. The PDM issuitable for the direct AC to AC converter which provides asinusoidal voltage at commercial frequency from a highfrequency voltage, such as the proposed system. The PDM treats
the high-frequency input voltage as pulses and synthesize theoutput voltage with a density of the input voltage pulses. A halfcycle of the input voltage pulses are used as the minimum unit

of the output voltage waveform. The matrix converter switches
are turned on in zero voltage period of the input voltage
waveform. In consequence, the matrix converter achieves ZVS(zero voltage switching) which results in decreasing a switchingloss. This is the reason that the PDM is applied to the matrix
converter in this paper.
IV.

ZVS OPERATION OF PRIMARY CONVERTER

The basic operation of ZVS for the proposed converter is
explained in this chapter. In the proposed circuit, if thetransformer current discharges in the drain-to-source
capacitance Cds during dead time, the switching becomes ZVS.
It should be noted that if the buffer current which flows power
decoupling circuit as shown in chapter III discharges in Cds
during dead time, the switching also becomes ZVS.
A. Conduction Mode at Secondary Side of Transformer
The effects of parasitic elements in the transformer and theload inductance Lload are neglected for the simplicity. In thiscondition mode, the matrix converter does not output zerovoltage and the load current flows to the secondary transformer.
In order to achieve ZVS in primary side, the relationship among
the buffer current, the output current of MC and the current ineach other arm of the full-bridge current is required.
In the conventional DC to AC converter without the power
decoupling circuit in reference [8], the load current equals to thetransformer current by assuming that the exciting current issmall enough to be neglected. Therefore, the switching devices
which achieve ZVS are determined by the pole of thetransformer current. The relationship between the pole of thetransformer current and the ZVS-achieving switching devices is
as follows.
1) ia > 0:
San, Sbp
2) ia < 0:Sap, Sbn
On the other hand, in the proposed converter, the transformer
current overlaps with the common current. Thus, the currents ia,
ib in each arm are presented by (6)-(7).

1ia (t )  idif (t )  ibuf (t )
2

(6)

1
ib (t )  idif (t )  ibuf (t )2(7)where, ibif (t) is the transformer current and changes according
to the output current of MC, ibuf (t) is the buffer current in the
power decoupling circuit and changes according to the output
power. If the maximum output current is Im, (6)-(7) are rewritten
as (8)-(9).
ia (t )  I m sin(o t ) Pave cos 20t 
1
2 V 2
P
bus
 ave sin2o t 4o Cbufib (t )  I m sin(o t ) 

As above stated, the phase current in primary inverter is the sumof the buffer current and the output current. Therefore, both the
ZVS-achieving switching devices and the ZVS range aredetermined by the pole of transformer current, the buffer current
and phase ϴ=ωot.
In order to achieve ZVS in the primary inverter, the current
ia, ib in each phase are required to be higher than the lower limit
value ilim. If the current ia, ib in each phase is below ilim thecharges in the drain-to-source capacitance Cds cannot bedischarged completely during dead time. The lower limit value
ilim which achieves ZVS in the primary side is presented by (10).

ilim 

CdsVbusTdead



B. Zero Voltage Mode at Secondary Side of Transformer
Fig. 6 shows the current path-way of the proposed circuit
when the matrix converter outputs zero voltage. When PDM isapplied for the secondary converter, the converter outputting
zero voltage makes p-n line become open. In the conventional
circuit without the power decoupling circuit, the secondarytransformer current becomes zero. Therefore, the primary
inverter does not have the transformer current meet the condition
for (10) to achieve ZVS. On the other hand, in the proposed
circuit, by applying the center-tapped transformer and the power
decoupling circuit as shown in chapter 3 to compensate theripple component, the buffer current becomes the sinusoidal
wave at 100 Hz. Hence, in the proposed converter, thetransformer current flows according to the buffer current evenwhen the matrix converter outputs zero voltage. The pole of thetransformer current is decided by the pole of the buffer current.
Thus, the ZVS-achieving switching devices are decided by theload current and phase because the buffer current are decided by
the load current iout (t). In this paper, the ZVS condition of the
ZVS-achieving switching devices which varies depending on
the load current iout (t) and the phase are discussed using
simulation.
The current to discharge completely the drain-to-source
capacitance Cds has to meet (10). Therefore, the boundary
condition of the buffer current ibuf (t) to achieve ZVS at primaryside is presented by (11).

Pave cos 20t 
1
2 V 2
P
bus
 ave sin2o t 4o Cbufibuf 

4CdsVbus
TdeadAs shown above, this proposed converter can achieve bothZVS in the primary inverter and the power decoupling whereas

the in reduction of the DC bus current ripple is also
accomplished. In addition, because ZVS can be achieved in the
primary inverter, the proposed converter is expected to achievea downsizing and lower loss.
V.

ibus
Sap

Sbp

is

ia

Vbus

ib

A. Simulation Results in Steady State
In order to verify the proposed ZVS method of the primary
inverter described in chapter IV, ZVS achievable range in the
inverter at primary side is discussed using simulation.

Fig. 8 shows the gate-source voltage and the drain-source
voltage at rated load. Fig. 8 (a), (b), and (c) shows the waveformof domain A, B, and C in Fig.7, respectively. In Fig. 8, the gatesource voltage rises after the drain-source voltage drops to zerodue to the resonance between the drain-source capacitance andthe leakage inductance of the transformer. Therefore, the ZVSof the inverter at primary side is achieved. It is confirmed from
Fig. 8, the switching devices which achieve ZVS agree with thedomain shown in Fig. 7. As a result, each switches of the primary
inverter achieve ZVS in corresponding domain. Thus, it ispossible to reduce the switching loss of the inverter at primary
side.

Snu

ibuf

iout
vout

Snv

Fig. 6.
A relationship between a switching operation and current path-way
in the proposed circuit when the matrix converter outputs zero voltage.
TABLE I.

Table 1 shows the simulation condition for the isolated
single-phase matrix converter with the proposed power
decoupling method as drawn in Fig. 2. It should be noted thatthe output voltage of MC is 100 Vrms, the output power is 1 kW,
the output frequency is 50 Hz, and the power factor of the output
current is 1.

SIMULATION CONDITION OF PROPOSED SYSTEM.
1.0 kW

DC bus voltage

380 Vdc

0.5 mH

Turn ratio N1/N2

1

Buffer C (Cbuf)

400 mF

Load current

10 Arms

Drain to source
capacitance Cds

1.125nF

Carrier frequency offull bridge inverter

100 kHz

Carrier frequency ofmatrix converter

10 kHzRated power
Buffer L (Lbuf)

Output current
15

B

10

Current [A]Fig. 7 shows the relationship between the absolute value ofthe output current iout and the phase ϴ=ωot. In Fig. 7, in thedomain around the highest value of the output current, both legs
achieve ZVS, because the current which discharges completely
the drain-to-source capacitor Cds is high enough. On the other
hand, in the domain around the least value of the output current,
the buffer current approaches the maximum value. Therefore,
the primary inverter achieves ZVS only if the buffer current
meets the criterion shown in (11). In contrast, the red area in Fig.
7 shows the period in which the top arm at the primary inverter
do not achieve ZVS during the zero voltage period of the matrix
converter, and the other area shows the period in which thebottom arm at the primary inverter do not achieve ZVS during
the zero voltage period of the matrix converter. It should be
noted that the red area and other area is the region which can get
the current to achieve ZVS if the matrix converter do not output
zero voltage. In the zero voltage period of the matrix converter,
the reason why the ZVS-achieving switching devices change isthat the pole of the buffer current changes according to the phaseof the output current. As the result, in the proposed converter,
the transformer current to achieve ZVS still flows through thebuffer circuit even during the zero voltage period of the matrix
converter shown in section IV-A. Finally, in the 0 A vicinity ofthe buffer current, this proposed converter does not achieve ZVSat the primary inverter because the buffer current do not meet
(11).

Sbn

Spv

vs

SIMULATION AND EXPERIMENTAL RESULTS
San

Spu

ZVS region

Burrer current

A. Conduction
Mode of MC

50-5

Sap SanSbn SbpA

B. 0 V Mode of MC

C

-10

-15

1
2π

3
2π

π

: San Sbn
: Sap Sbp

2π

The phase of the output current ωot
Fig.7.
A characteristic of the output current, the buffer current and thephase of the output current. The area which achieve ZVS at primary side is
decided the pole of the buffer current.
400
0
-400

Inverter voltage vinv [V]

400
0
-400

400
0
-400

0
-20

20
0
-20

Transformer current iinv [A]20
20

0
-20

1.0
0.0
400
0
1.0
0.0

Gate signal of Sap at the inverter
1.0
0.0

1.0
0.0

ZVS

Terminal voltage vap [V] 4000Gate signal of Sbn at the inverter
1.0
ZVS

1.0
0.0

0.0

Terminal voltage vbn [V] 400
400
0

1.0
0.0
1.0
0.0

Gate signal of Sup at the matrix converter
1.0
0.0

Gate signal of Svp at the matrix converter
Buffer current ibuf [A]
2.0

6.0

[µs]

(a) Range of low
load current

ZVS

400
0

0

8
4
0

ZVS

400
0

1.0
0.0

1.0
0.0
1.0
0.0

Output current iout [A] 20

20
0
-20

0
-20
2.0

6.0

(b) Zero voltage
is outputted term

2.0

6.0

[µs]

(c) Range of highload current

Fig.8. Extended waveform of a switching pattern for each periods of output
current. Fig. 8(a), (b), and (c) shows the waveform of domain A, B, and C in
Fig.7.

B. Experimental Results in Steady State
Fig. 9 (a) and (b) shows the waveform with and without thepower decoupling method. In Fig. 8(a), the buffer capacitor
voltage does not change because the full bridge inverter does not
output the common mode AC voltage. As a result, the DC bus

current has a power ripple component at 100 Hz. In contrast, theproposed power decoupling method provides the common mode
AC voltage to fluctuate the buffer capacitor voltage. As a result,the power ripple component in the DC bus current is decreased.

Fig. 11 shows experimental waveforms of the proposed
converter with Vbus of 350 V, vgrid of 100 Vpeak, Tdead of 500 ns
and an R-L load of 500 W. From Fig. 11, the gate-source voltage
in Sbn rises after the drain-source voltage drops in Sbn to zero dueto the resonance between the drain-source capacitance of Sbn andthe buffer inductance. In addition, it is confirmed from Fig. 11that the switching devices achieve ZVS when the condition of
the output current value calculated by (10) is satisfied.
VI.

CONCLUSION

In this paper, in order to achieve high efficiency without any
additional passive components, ZVS achievable range and thecondition for the inverter at primary side of the transformer
using the proposed power decoupling circuit are discussed. In
this proposed system, even when the transformer’s differential
current which delivers the power to the secondary side oftransformer is below the lower limit value to achieve ZVS or
when the matrix converter outputs zero voltage, the proposed
converter still achieves ZVS, because there is the buffer current
overlapping to the transformer current. In addition, both the ZVS
operation and the power decoupling are achieved which results
in reducing the DC bus current ripple at the same time. As aresult, the ripple of the DC bus current is suppressed by 85.1%
by experiments. Moreover, in experimental results, the ZVS
operation on the primary side of the transformer is confirmed.

0
0

[2]
[3]
[4]
[5]

[6]

0

Output voltage (LPF) vout 100 V/div

4 ms/div(a)

Without the power(b) With the power
decoupling method.
decoupling method
Fig.9. Input and output waveforms in a steady state.

70

Without the power decoupling method

60
50

40

Reduced by 85.1%

30

20
10

With the power decoupling method0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Harmonic number
Fig. 10. Harmonic analysis of the DC bus current. The power decoupling
method reduces the DC bus current ripple by 85.1% compared to when the
power decoupling is not applied.

0Gate-source voltage of
Sbn 10 V/div
Drain-source voltage of
Sbn 250 V/div

0

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H.Takahashi, N.Takaoka, R.R.Rodriguez, J.Itoh: ”Power
Decoupling Method for Isolated DC to Single-phase AC Converter
using Matrix Converter”，IECON2014, pp.3337-3343 (2014)0

Buffer current ibuf 5 A/div
Buffer capacitor voltage VCbuf 100 V/div

0

REFERENCES[1]

0

Harmonic component [%](100%: DC component)

Fig. 10 shows a harmonic analysis of the DC bus current. It
should be noted that the fundamental frequency is the output
frequency at 50 Hz. From the result, it is understood that without
the power decoupling method, the power ripple component at
100 Hz is 62.6% compared to an average current. In contrast, theproposed method reduces the 100 Hz component to 9.30%
because the buffer capacitor voltage fluctuation absorbs thepower ripple at 100 Hz. As a result, the ripple of the DC bus
current is suppressed by 85.1%.

DC bus current Ibus 5 A/div

Inverter voltage Vinv 500 V/div

00

Output current iout 10 A/div

400 ns/div

Fig.11.
Experimental waveform at 50% rated power. The gate-source
voltage in Sbn rises after the drain-source voltage drops in Sbn to zero due to theresonance between the drain-source capacitance of Sbn and the buffer
inductance.
[7]

[8]

N. Takaoka, H. Takahashi, J. Itoh: "Voltage error compensation
method for PDM in power decoupling conducted by isolated singlephase matrix converter and center-tapped transformer.",NO.SPC15-055,MD-15-055 (2015)
R. Oshima , H. Takahashi , J. Itoh: "Zero voltage switching method
for an isolated DC - 3 phase AC converter using AC - 3 phase AC
direct converter at secondary side of transformer"NO.SPC-15006,MD-15-006 (2015)