CAQS-MPO101-SR4C100GBASE-SR4 100m QSFP28 Optical Transceiver R01

100GBASE-SR4 100m QSFP28 Optical Transceiver
CAQS-MPO101-SR4CFeatures♦

Hot-pluggable QSFP28 form factor♦

4 channels full-duplex transceiver module♦

Supports 103.125Gb/s aggregate bit rate♦

4 channels 850nm VCSEL array♦

4 channels PIN photo-detector array♦

Internal CDR circuits on both receiver and transmitterchannels♦

Supports CDR bypass♦

2.5W maximum power dissipation♦Maximum link length of 70m on OM3 MMF and 100m on OM4 MMF♦Single MTP/MPO receptacle♦Operating case temperature range: 0 to 70℃♦Single 3.3V power supply♦RoHS compliant (lead free)

Applications♦100GBASE-SR4 100G Ethernet

Description
CA OPTRONICS GROUP 100GBASE-SR4 100m QSFP28 optical transceiver, 100G QSFP28 SR4 (GQSMPO101-SR4C) is designed for use in 100-Gigabit Ethernet links up to 100m over Multi-Mode Fiber (MMF). It
is compliant with the QSFP28 MSA and IEEE 802.3bm 100GBASE-SR4 and CAUI-4. Digital diagnostics
functions are available via the I2C interface, as specified by the QSFP28 MSA. It integrates 4 data lanes ineach direction with 4×25.78125Gb/s bandwidth. The electrical interface uses a 38-contact edge type connector.
The optical interface uses a 12-fiber MTP/MPO connector. This module incorporates CA OPTRONICS GROUP
proven circuit and VCSEL technology to provide reliable long life, high performance, and consistent service.

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CAQS-MPO101-SR4C100GBASE-SR4 100m QSFP28 Optical Transceiver R01

Figure 1. Module Block Diagram

The 100GBASE-SR4 QSFP28 is a parallel transceiver with the key technique of VCSEL and PIN array package,and can be can contacted through I2C system.

Absolute Maximum Ratings

Parameter

SymbolMinMax

Unit

Supply Voltage

Vcc-0.3

3.6

V

Input Voltage

Vin-0.3

Vcc+0.3

V

Storage Temperature

Ts-2085ºC

Case Operating Temperature

Tc

070

ºC

Humidity (non-condensing)

Rh

595%

Recommended Operating Conditions

Parameter

SymbolMin

TypicalMax

Unit

Supply Voltage

Vcc

3.13

3.3

3.47

V

Operating Case temperature

Tc

070

ºC

Data Rate Per Lane

fdHumidityRh

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Parameter

SymbolPower Dissipation

Pm

Fiber Bend Radius

RbMin

TypicalMax

Unit

22.5

W

3cm

Electrical Specifications

Parameter

SymbolMin

TypicalMax

Unit

Differential Input Impedance

Zin

90

100110ohm

Differential Output Impedance

Zout

90

100110ohm

Differential Input Voltage Amplitude1

ΔVin

300

1100

mVp-p

Differential Output Voltage Amplitude2

ΔVout

500

800mVp-p

Skew

Sw300psBit Error Rate

BER

Input Logic Level High

VIH

2.0

Vcc

VInput Logic Level Low

VIL

00.8

V

Output Logic Level HighVOHVcc-0.5

Vcc

V

Output Logic Level Low

VOL00.4

V

5×10-5Note:
1. Differential input voltage amplitude is measured between TxnP and TxnN.
2. Differential output voltage amplitude is measured between RxnP and RxnN.
Optical Characteristics

Parameter

SymbolMin

TypicalMax

Unit

840

850

860

nm

0.6

nm

2.4dBmTransmitter
Center Wavelengthλc

RMS Spectral Width∆λAverage Launch Power (each lane)

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Parameter

SymbolMin

Optical Modulation Amplitude (each lane)

OMA-6.4

Transmitter and Dispersion Eye Closure (each lane)

TDEC

Extinction Ratio

ER

Average Launch Power of OFF Transmitter (each lane)

Poff

Eye Mask Coordinates1: X1, X2, X3, Y1, Y2, Y3

TypicalMax

Unit3dBm

4.3

dB

3

dB-30

dB

{0.3, 0.38, 0.45, 0.35, 0.41, 0.5}

Receiverλc

Center Wavelength840

Stressed Receiver Sensitivity in OMA2
Average Power at Receiver-10.3Input (each lane)
Receiver ReflectanceRR

LOS Assert

LOSA

LOS De-Assert – OMA

LOSDLOS Hysteresis

LOSH

850860nm-5.2dBm

2.4dBm-12dB-30dBm-7.5dBm

0.5dB

Note:
1. Hit Ratio = 5×10-5
2. Measured with conformance test signal at TP3 for BER=10-5

Pin Description

PinLogic

1

SymbolName/Description

GND

Module Ground1

2

CML-I

Tx2-

Transmitter inverted data input

3

CML-I

Tx2+

Transmitter non-inverted data input

GND

Module Ground1

Tx4-

Transmitter inverted data input

45CML-I

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PinLogicSymbol

6CML-I

Tx4+

Transmitter non-inverted data input

GND

Module Ground1

7Name/Description

8

LVTTL-I

MODSEIL

Module Select2

9

LVTTL-I

ResetL

Module Reset2

VCCRx+3.3V Receiver Power Supply

1011

LVCMOS-I

SCL

2-wire Serial interface clock2

12

LVCMOS-I/O

SDA

2-wire Serial interface data2

GND

Module Ground1

1314CML-O

RX3+

Receiver non-inverted data output

15CML-O

RX3-Receiver inverted data output

GND

Module Ground1

1617

CML-O

RX1+

Receiver non-inverted data output

18CML-O

RX1-

Receiver inverted data output

19

GND

Module Ground1

20

GND

Module Ground1

21

CML-O

RX2-

Receiver inverted data output

22

CML-O

RX2+

Receiver non-inverted data output

GND

Module Ground1

2324

CML-O

RX4-

Receiver inverted data output

25

CML-O

RX4+

Receiver non-inverted data output

GND

Module Ground1

2627

LVTTL-O

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ModPrsL

Module Present, internal pulled down to GND

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PinLogicSymbol

28

LVTTL-O

IntL

Name/Description
Interrupt output, should be pulled up on host board2

29

VCCTx+3.3V Transmitter Power Supply

30

VCC1+3.3V Power Supply

LPModeLow Power Mode2

GND

Module Ground1

31

LVTTL-I

3233

CML-I

Tx3+

Transmitter non-inverted data input

34

CML-I

Tx3-

Transmitter inverted data input

GND

Module Ground1

3536

CML-I

Tx1+

Transmitter non-inverted data input

37

CML-I

Tx1-Transmitter inverted data input

GNDModule Ground1

38

Note:
1. Module circuit ground is isolated from module chassis ground within the module.
2. Open collector should be pulled up with 4.7K to 10K ohms on host board to a voltage between 3.15V and3.6V.

Figure 2. Electrical Pin-out Details

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CAQS-MPO101-SR4C100GBASE-SR4 100m QSFP28 Optical Transceiver R01

ModSelL Pin
The ModSelL is an input pin. When held low by the host, the module responds to 2-wire serial communicationcommands. The ModSelL allows the use of multiple QSFP modules on a single 2-wire interface bus. When theModSelL is "High", the module will not respond to any 2-wire interface communication from the host. ModSelL
has an internal pull-up in the module.

ResetL PinReset. LPMode_Reset has an internal pull-up in the module. A low level on the ResetL pin for longer than theminimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to theirdefault state. Module Reset Assert Time (t_init) starts on the rising edge after the low level on the ResetL pin isreleased. During the execution of a reset (t_init) the host shall disregard all status bits until the module indicatesa completion of the reset interrupt. The module indicates this by posting an IntL signal with the Data_Not_Readybit negated. Note that on power up (including hot insertion) the module will post this completion of reset interrupt
without requiring a reset.

LPMode Pin
CA OPTRONICS GROUP QSFP28 modules operate in the low power mode (less than 1.5 W power
consumption). This pin active high will decrease power consumption to less than 1W.

ModPrsL Pin
ModPrsL is pulled up to Vcc on the host board and grounded in the module. The ModPrsL is asserted "Low"when the module is inserted and deasserted "High" when the module is physically absent from the hostconnector.

IntL Pin
IntL is an output pin. When "Low", it indicates a possible module operational fault or a status critical to the hostsystem. The host identifies the source of the interrupt by using the 2-wire serial interface. The IntL pin is anopen collector output and must be pulled up to Vcc on the host board.

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CAQS-MPO101-SR4C100GBASE-SR4 100m QSFP28 Optical Transceiver R01

Power Supply Filtering
The host board should use the power supply filtering shown in Figure 3.

Figure 3. Host Board Power Supply Filtering
Optical Interface Lanes and Assignment
The optical interface port is a male MPO connector .The four fiber positions on the left as shown in Figure 4,
with the key up, are used for the optical transmit signals (Channel 1 through 4). The fiber positions on the rightare used for the optical receive signals (Channel 4 through 1). The central four fibers are physically present.

Figure 4. Optical Receptacle and Channel Orientation

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CAQS-MPO101-SR4C100GBASE-SR4 100m QSFP28 Optical Transceiver R01

DIAGNOSTIC MONITORING INTERFACE (OPTIONAL)
Digital diagnostics monitoring function is available on all CA OPTRONICS GROUP QSFP28 transceivers. A 2wire serial interface provides user to contact with module.

The structure of the memory is shown in Figure 5. The memory space is arranged into a lower, single page,address space of 128 bytes and multiple upper address space pages. This structure permits timely access toaddresses in the lower page, such as Interrupt Flags and Monitors. Less time critical time entries, such as serial
ID information and threshold settings, are available with the Page Select function.

The interface address used is A0xh and is mainly used for time critical data like interrupt handling in order toenable a one-time-read for all data related to an interrupt situation. After an interrupt, IntL, has been asserted,
the host can read out the flag field to determine the affected channel and type of flag.

Figure 5. QSFP28 Memory Map
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CAQS-MPO101-SR4C100GBASE-SR4 100m QSFP28 Optical Transceiver R01

Figure 6. Low Memory Map

Figure 7. Page 03 Memory Map

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CAQS-MPO101-SR4C100GBASE-SR4 100m QSFP28 Optical Transceiver R01

Figure 8. Page 00 Memory Map
Page02 is User EEPROM and its format decided by user.

The detail description of low memory and Page 00. Page 03 upper memory please see SFF-8436 document.

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CAQS-MPO101-SR4C100GBASE-SR4 100m QSFP28 Optical Transceiver R01

Timing for Soft Control and Status Functions

Parameter

SymbolMaxUnit Conditions

t_init2000

ms

t_reset_init

2μst_serial

2000

ms

Monitor Data Ready Timet_data2000

ms

Reset Assert Timet_reset2000

ms

LPMode Assert Time

ton_LPMode

100μs

ton_IntL200

ms

Initialization Time

Reset Init Assert Time
Serial Bus Hardware
Ready Time

IntL Assert TimeTime from power on1, hot plug or rising edge of Reset
until the module is fully functional2
A Reset is generated by a low level longer than theminimum reset pulse time present on the ResetL pin.
Time from power on1 until module responds to datatransmission over the 2-wire serial bus
Time from power on1 to data not ready, bit 0 of Byte 2,
deasserted and IntL asserted
Time from rising edge on the ResetL pin until themodule is fully functional2
Time from assertion of LPMode (Vin: LPMode=VIH) until
module power consumption enters lower Power Level
Time from occurrence of condition triggering IntL until
Vout: IntL=VOL
Time from clear on read3 operation of associated flag

IntL Deassert Time

toff_IntL

500μs

until Vout: IntL=VOH. This includes deassert times for Rx
LOS, Tx Fault and other flag bits.

Rx LOS Assert Time

ton_los100

ms

Tx Fault Assert Time

ton_Txfault

200

ms

Flag Assert Time

ton_flag200

ms

Mask Assert Time

ton_mask

100

ms

Mask Deassert Time

toff_mask

100

ms

ModSelL Assert Time

ton_ModSelL

100μs

Time from Rx LOS state to Rx LOS bit set and IntLasserted
Time from Tx Fault state to Tx Fault bit set and IntLasserted
Time from occurrence of condition triggering flag toassociated flag bit set and IntL asserted
Time from mask bit set4 until associated IntL assertionis inhibited
Time from mask bit cleared4 until associated IntlL
operation resumes
Time from assertion of ModSelL until module responds
to data transmission over the 2-wire serial bus
Time from deassertion of ModSelL until the module

ModSelL Deassert Time

toff_ModSelL

100μs

does not respond to data transmission over the 2-wireserial bus

Power_over-ride orPower-set Assert TimePower_over-ride orPower-set Deassert TimeCA OPTRONICS GROUP INC

ton_Pdown

100ms

toff_Pdown

300ms

Time from P_Down bit set4 until module power
consumption enters lower Power Level
Time from P_Down bit cleared4 until the module is fully
functional3

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CAQS-MPO101-SR4C100GBASE-SR4 100m QSFP28 Optical Transceiver R01

Note：
1. Power on is defined as the instant when supply voltages reach and remain at or above the minimum
specified value.
2. Fully functional is defined as IntL asserted due to data not ready bit, bit 0 byte 2 deasserted.
3. Measured from falling clock edge after stop bit of read transaction.
4. Measured from falling clock edge after stop bit of write transaction.

Mechanical Dimensions

Figure 9. Mechanical Specifications
Regulatory Compliance
CA OPTRONICS GROUP CAQS-MPO101-SR4C transceivers are Class 1 Laser Products. They meet therequirements of thefollowing standards.
FeatureStandard
IEC 60825-1:2014 (3rd Edition)

Laser Safety

IEC 60825-2:2004/AMD2:2010
EN 60825-1-2014
EN 62368-1: 2014

Electrical Safety

IEC 62368-1:2014
UL 62368-1:2014

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CAQS-MPO101-SR4C100GBASE-SR4 100m QSFP28 Optical Transceiver R01

FeatureStandard

Environmental protection

Directive 2011/65/EU with amendment(EU)2015/863
EN55032：2015

CE EMC

EN55035：2017
EN61000-3-2:2014
FCC Part 15, Subpart B

FCC

ANSI C63.4-2014

References
1.
2.

QSFP28 MSA
Ethernet 100GBASE-SR4 IEEE802.3bm

Ordering Information

Part Number

Product Description

CAQS-MPO101-SR4C

QSFP28 SR4, 103.125Gb/s, 850nm, 100m, MMF, MTP/MPO

Important Notice
Performance figures, data and any illustrative material provided in this data sheet are typical and must be
specifically confirmed in writing by CA OPTRONICS GROUP before they become applicable to any particularorder or contract. In accordance with the CA OPTRONICS GROUP policy of continuous improvement
specifications may change without notice.

The publication of information in this data sheet does not imply freedom from patent or other protective rights ofCA OPTRONICS GROUP or others. Further details are available from any CA OPTRONICS GROUP sales
representative.

E-mail:sales@caoptronicsgroup.com
Official Site:www.caoptronicsgroup.com

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