Space Vector Modulation for a Single Phase toThree Phase Converter Using an Active Buffer
Yoshiya Ohnuma * and Jun-ichi Itoh ** Nagaoka University of Technology,1603-1 Kamitomioka-cho
Nagaoka city Niigata, Japan
Abstract-- This paper proposes a space vector modulation
scheme for a new single phase to three phase power
converter that using an active buffer. The proposed circuit
is based on the control theory of an indirect matrix
converter which can successfully reduce the volume of thesmoothing capacitor in the DC link part. The proposed
circuit needs to control the output voltage and the buffer
current at the same time. In order to reduce the output
voltage and the input current harmonics, a space vector
modulation scheme is proposed.
In this paper, the basic operation of the proposed method
is confirmed by experimental results. The input current
THD and the output current THD around the fundamental
component frequency are 3.34% and 6.65%, respectively.
Moreover the capacitor current THD in the input filter andthe output voltage THD that is below than 15 kHz switchingfrequency are improved by 10% and 17% because theswitching waveforms becomes symmetrical shape. The
validity of the proposed method is confirmed with theseresults.
Index Terms—Space vector modulation, Converter
control, Single-to-three-phase converter, Capacitor volume
reduction,

I. INTRODUCTION
Three-phase motors recently have been started into
household appliances, offering more advantages such as
smaller size, lower energy consumption, high power
factor and low torque ripples. However, current
conventional household electronics equipment uses
single-phase motors, and household wiring is only
designed for single-phase uses. A suitable single-phase to
three-phase converter is therefore essential in order to use
in the three-phase motor in home appliances to saveenergy-consumption. One of the most significant
problems for a single-to-three-phase converter is the
production of power ripple at twice the frequency of thepower grid.
A conventional converter consists of a diode rectifier,a three-phase inverter, and a large energy buffer, such as
an electrolytic capacitor, to absorb the power ripple at theDC link. A power factor correction (PFC) rectifier is also
required in order to suppress the input current harmonics[1]-[4]. However, almost all of PFC circuits require
additional switching devices or diodes that cause
substantial power loss over a conventional circuit. In
addition, a PFC circuit requires a large reactor for boost
up function. So the size of the converter is larger than theconventional one.
On the other hand, in order to compensate the power

ripple at twice the frequency of the power grid, somestrategies have been proposed, such as DC active filters,
power decoupling methods[5]-[8]. Certainly, these
topologies can reduce capacitance of the DC link
capacitor with the power ripple store in sub-capacitanceusing an additional circuit. However this additional
circuit requires more switches and a large reactor.
Consequently, the additional circuit increases the total
power consumption.
AC/AC direct converters, such as matrix converters,
have also been studied. AC/AC direct converters are
smaller in size, lower in cost, and have longer lifetimes,
since the large energy buffer is not required. Numbers ofmatrix converter schemes have been proposed for singleto-three-phase conversion. In one example, power ripple
is absorbed by the inertial moment of a motor [9].This
method does not require additional components over thatof the conventional converter, yet the application of thisapproach is limited due to the speed or torque ripple. In
another approach, the single-phase power supply andenergy capacitor are connected to the input side of thethree-phase matrix converter [10]. However, this method
requires 18 switching devices, detracting from theadvantages of a three-phase design.
The authors have already proposed a single-to-threephase power converter using an active buffer to reduce
the size of DC link capacitor [11]. The proposed
converter uses the concept of an indirect matrix converter
that coupled with an active buffer to absorb the power
ripple. The size of the converter can be reduced because
the converter does not require a large smoothing
capacitor in the DC link part and a boost up reactor.
However, the switching pattern for the inverter is anasymmetry because the carrier uses a trapezoidal carrier.
As a result, the harmonics in the input current and theoutput current are increased. Besides, it is difficult toapply a current feedback control because the averagevalue of the current cannot detect at the peak of carrier
when an asymmetrical carrier is used.
This paper proposes a control method that using aspace vector modulation for the proposed converter. The
space vector modulation can generate a symmetricalswitching pattern to reduce the harmonics [12], [13].
Firstly, the basic operation of the proposed method is
introduced. Next, the control method of the space vector
modulation is explained. After that, the proposed method
is demonstrated in the experimental results. In addition,the validity of the proposed method is confirmed bycomparing with the conventional trapezoidal carrier ordouble-edge carrier.

Figure 1 shows a block diagram of the proposed
converter. The converter is based on an indirect matrix
converter topology, where the rectifier is operated as acurrent source rectifier, and the inverter stage is operated
as a voltage source inverter. A buffer circuit consisting ofa small capacitor and a switch is inserted into the DC link
to absorb power ripple, which has a frequency that is
twice of the power supply. It should be note that thebuffer circuit is also used as a snubber circuit forprotection purpose.
Figure 2 shows the circuit topology of the proposed
converter. A simple and cheap diode rectifier is used as
the rectifier stage converter, since most household
appliances do not require a regeneration mode from theoutput power. Zero-current switching for the buffer
switch and diodes in the rectifier is achieved by matching
to the switching timing of the zero-voltage vector output
in the inverter. In this manner, there is no switching loss
at the buffer switch or recovery loss at the diode rectifier.

1 phaseAC/DCconverter

DC/AC
converter(Current source
rectifier)(Voltage source
inverter)M
3 phaseEnergy Flow

Buffer circuit
Fig. 1. Block diagram of the proposed system.

Input filter

II. CIRCUIT TOPOLOGY

Energy Flow

Fig. 2. Proposed circuit diagram.

III. CONTROL STRATEGY
A. Principle of the power ripple compensation
Figure 3 shows the compensation principle of a power
ripple. When both the input voltage and input current
waveform are sinusoidal, the instantaneous input power
pin is expressed as,

Fig. 3. Compensation principle of power ripple.

pin = VIN I IN sin 2 (ωt )=1
1
V IN I IN − V IN I IN cos(2ωt )
2
2

(1),

where, VIN is the peak single-phase voltage, IIN is the peaksingle-phase current, ω is the single phase angularfrequency.
From (1), the power ripple that contains twice thefrequency appears at the DC bus link part.
In order to absorb the power ripple, the buffer circuit
instantaneous power pbuf, is required by (2). Note that themean power of the buffer circuit is zero because thebuffer circuit absorbs ripple only. Therefore, a small
capacitor can be used in the buffer circuit.
pbuf =

1
V IN I IN cos(2ωt )2(2)Consequently, the instantaneous output three-phasepower pout can be constant (3).
p out =

1
Vout I out
2(3)

B. Duty commands for each switch
Figure 4 shows the equivalent circuit of the proposed
converter. The input current of the inverter idc is divided

Fig. 4. Equivalent circuit of the proposed system.

by SC into the capacitor current ic and rectifier current irec.
Note that the zero-period current iz is a virtual current, asgiven by the inverter; when the inverter outputs zerovoltage vectors. Then, the equivalent circuit consists ofthree switches; SREC, SC, SZ, which are related as⎡irec ⎤ ⎡d REC ⎤⎢ i ⎥ = ⎢ d ⎥ ⋅i
⎢ c ⎥ ⎢ C ⎥ dc⎢⎣ iz ⎥⎦ ⎢⎣ d Z ⎥⎦(4),

where, dREC, dC, and dZ are the duty ratios of SREC, SC, and
SZ. Note that the duty ratios are constrained bycontinuous current (Idc) is given byd REC + d C + d Z = 1(5).

The duty ratio of the rectifier dREC is controlled so as toobtain a sinusoidal waveform for the single-phase current
irec. Then these values are described by

Fig. 5. Space vectors for an inverter.

irec = I IN sin (ωt )

(6),

I IN
sin (ωt )
I dc

(7).

d rec =

The capacitor current ic is controlled to absorb thepower ripple from the power supply through the charge ordischarge of the capacitor depending on the direction of
the capacitor current.
ic =VIN I INcos(2ωt )2vC(8)Since it is not possible to flow the negative capacitor
current (charge current) when the direction of Idc is
positive, Idc is to be controlled as negative by the rectifier
when the charge current mode is selected. Therefore theduty ratio dc can be obtained asdC =VIN I INcos(2ωt )2vC I dc

d Z = 1 − d C − d REC

(9),
(10).

Meanwhile, the ratio of IIN divided by Idc can beobtained as follows from the maximum voltage transfer
ratio;

I IN
2VC 0
=
I dc 2VC 0 + VIN(11)where VC0 is the buffer average-voltage.
Finally, dREC and dC can be obtained as (12) from (7),(9) and (11).
2VC 0⎧⎪d REC = 2V + V sin (ωt )
⎪
C0
IN
⎨
V
V
IN C 0⎪d =cos(2ωt )⎪⎩ C vC (2VC 0 + VIN )(12)

C. Control for the capacitor voltage
In an ideal condition, an instantaneous voltage ofcapacitor fluctuates according to the command of thecapacitor average voltage VC0. The instantaneous
capacitor voltage vc is calculated from the output powerand capacitance, as shown in equation (13)2vC = VC 0 −

pout

ωC

sin(2ωt )(13).
However, the voltage of capacitor does not agree withthe reference voltage (13) because of the dead time effectin the inverter. Therefore, a PI control is applied to the
proposed circuit to control the capacitor voltage. The
output values of the PI controller add to the dc which is
calculated by (12) as shown in Fig.6.
D. The pulse generation method by space vector
modulation
Figure 5(a) shows a fundamental output voltage vector
for a voltage source inverter. In order to implement theinverter vector command v*, approximate two vectors are
required, and the duty ratios of these vectors arecalculated by using the projection of the vector
commands in the α axis(vα) and in the β axis(vβ) as
following.

⎧ vα = V1α T1 + V2α T2 + V0α TZ⎪⎨v β = V1β T1 + V2 β T2 + V0 β TZ
⎪ 1= T +T +T
1
2
Z
⎩

(14)

where, T1, T2 and Tz are the output duty ratios of V1 vector,
V2 vector and zero vector, respectively.
Therefore, the duty ratios T1, T2 and Tz can be obtained
by
T1 =

1 vα
A vβ

V2α
V2 β

T2 =

1 V1α
A V1β

vβ

vα

TZ = 1 − (T1 − T2 )

(15).
⎛
V
⎜∵ A = 1α
⎜
V1β
⎝

V2α ⎞
⎟
V2 β ⎟⎠

Finally, the output duty ratios for each switch are
obtained from (10), (12) and (15).

VINp Input filter

Area1 Area2 Area3 Area4 Area5 Area6

Sc
vc

VINp
VC0*
vc

dREC
Duty
cal.(12) dC +iu,iv,i*vc* vc+cal.(13)sup~swniu iv iw

Eq.(10)CarrierPI+
T1rec,T1c,
T2rec,T2c,Tzz
5Capacitor voltage controlv*

SVM
Eq.(15)

Dischargesc

sc
sup~swn

T1
T2
Tz

Chargevin
PLLw

Table 1. Switching table.

R-L load

State1
State2
State3
State4
State5
State1
State2
State3
State4
State5

110
100
000
100
110
110
100
000
001
011

010
110
111
110
010
010
110
111
101
001

011
010
000
010
011
011
010
000
100
101

001
011
111
011
001
001
011
111
110
100

101
001
000
001
101
101
001
000
010
110

100
101
111
101
100
100
101
111
011
010

※ The number of ”1”means switch is Turn on
Example:110→Sup=ON,Svp=ON,Swp=OFF

Vectorinfo.

Fig. 6. Control block diagram.

T1REC = T1 ⋅ d REC

T1C = T1 ⋅ d C

T1Z = T1 ⋅ d Z

T2 REC = T2 ⋅ d REC

T2C = T2 ⋅ d C

T2 Z = T2 ⋅ d Z(16)

In order to reduce the number of the switching times,
all zero vectors should be summarized to one.
TZZ = T1Z + T2 Z + TZ

(17)

Figure 5(b) shows the output vectors diagram when thebuffer capacitor is in the discharge mode. In contrast,
figure 5(c) shows the output vectors diagram when thebuffer capacitor is in the charge mode. Since thecapacitor voltage is always larger than the input voltage
in the proposed circuit, the vectors for the capacitor
voltage are located outside of the inverter vectors. In the
discharge mode (Fig. 5 (b)), the voltage vector outputs avector in a sequence as V2rec(110)→V1rec(100)→V0(000)→
V1C(100)→V2C(110). On the other hand, in the charge
mode (Fig. 5 (c)), the voltage vector outputs a buffer
voltage vector at an opposite direction. That is, thevoltage vector outputs a vector in a sequence as V2rec(110)→V1rec(100)→V0(000)→V5C(001)→V4C(011). So, while thevoltage vectors output the buffer voltage vectors, thebuffer will be charged.
Table 1 shows the switching table of the proposed
method; space vector modulation. Table 1 confirms thateach time only one switch is turned on or off whenswitching state is moved from one to another state.
Figure 6 shows the control block diagram of the
proposed circuit. According to (12), the duty ratio
commands are calculated by the single-phase angle θinstead of ωt, the peak single-phase voltage VIN, the*capacitor average voltage command VC0 and the capacitor
voltage vC are detected from the voltage sensor. Each duty
ratios are calculated from Equation (15) using inverter*
vector command v . Then, the output duty ratios of each
vector are calculated by (16) and (17). Finally, theswitching pattern is obtained from a triangle carrier and aswitching table (Table 1).

Fig. 7. Relations between capacitor voltage and DC link voltage.

E. Maximum output voltage

In order to compensate the power ripple at the
maximum output voltage, the theoretical DC link voltage
Vdc can be expressed as

1
I dcVdc = VIN I IN
2
VC 0
Vdc =
VIN
2VC 0 + VIN(18)Figure 7 shows the relation between the capacitor
voltage and the DC link voltage requested by (18) whenthe voltage is normalized by the peak value of the single
phase voltage VIN. As a result, even the VC0 is infinity, themaximum DC link voltage is limited to VIN/2. That is, themaximum output voltage is less than half of VIN.
IV. COMPARISON OF SWITCHING FREQUENCY
Figure 8 shows the carrier and switching pattern of the
proposed and conventional method sequentially. As
shown in Figure 8(a), the proposed method can easily
generate symmetric switching pattern during switching
period T due to the use of triangle carrier. On the other
hand, the conventional method in figure 8(b) uses
asymmetric switching pattern because of use of
trapezoidal carrier. Then drec is controlled by the upslope

of the carrier, and dc is controlled by the downslope of thecarrier. Asymmetric carrier results that the input current
and the output current contains more harmonics. In orderto prevent the harmonics increase, the switching patternshould be a symmetry type carrier as shown in figure 8(c).
However, this double-edge carrier results the efficiency
becomes lower because the number of switching times isincreased.
Table 2 shows characteristics of each control method
about a switching pattern. The switching times of the
proposed method are 4 times less than the conventional
method. That is the switching loss of the proposed
method reduces by about 2/3 times compared to theconventional method which is using the double edge
operation. Note that the proposed method can detect the
average current of the output current during at every halfof switching period because the symmetrical pulse
pattern is used.
V. EXPERIMENTAL RESULTS
In order to demonstrate the validity of the proposedsystem, a 1-kW class prototype circuit has been tested.
Table 3 shows the experimental conditions, a capacitor of
50 μF was used for a 1-kW output power. In thiscondition, the capacitor voltage fluctuates from 163 V to
392 V. Figure 9(a) shows the operation waveforms of the
proposed method with the space vector modulation. From
the result, sinusoidal waveforms without distortion are
obtained at the input current and the output current.
Figure 9(b) shows single-phase waveforms andcapacitor voltage waveform. The capacitor voltage iscontrolled form 400 V to 150 V of twice the frequency of
the input voltage according to the proposed strategy.
Figure 10 shows the input power factor in respects tothe output power of the proposed circuit. The input power
factor (P.F.) of over 99 % is obtained even if a dioderectifier is used as input circuit. The reason of low power
factor in the light load region is because the lead current
flows in the capacitor of the input filter initially.
Figure 11 shows the total harmonics distortion (THD)of the input current and the output current. The minimum
value for the input current THD is 3.34% and the output
current THD is 6.65%. Please note that the experimental
condition for the input reactor is 2.3% and the load
reactor of 3% for rated power are used. It should be also
noted that THD is calculated by using harmonics
components less than 1 kHz. The input current harmonics
in the proposed circuit is much lower than standard ofIEEE 61000-3-2.
Figure 12 shows the efficiencies between the proposed
method and the conventional methods. The maximum
efficiency of the proposed method is 0.3% lower than theconventional single-edge method. However, the proposed
method is 0.7 % higher than the conventional doubleedge method. Therefore, the validity of the proposed
method can be confirmed. It is noted that the proposed
converter outputs low voltage and high current whichcauses the conduction loss increases in the power
converter.
Figure 13 shows a THD comparison between theFig. 8. Switching patterns.
Table 2. Comparison of number of switching times.

Type of control
methodSwitchingTimes

Switchingform

Minimum
current
detection time

Proposed method

8 TimesSymmetry
carrier

Half ofswitching
period6 Times

Asymmetry A switching
carrier
period12 Times

Symmetry A switching
carrier
periodConventional method(trapezoidal carrier)Conventional method(double-edge carrier)

Table 3. Experimental parameters.

(a)Input and output waveforms.
(b) Input and capacitor voltage waveforms.
Fig. 9. Experimental result with space vector modulation.

THD of input and output current [%]

1

0.98

0.96

0.94

0.92

0.9
0

200

400

600

Output power [W]

800

1000

Fig. 10 Input power factor.

Fig. 12. Efficiency of each control method.

proposed method and the conventional method. The
proposed method can improve the output voltage THDfrom 200% to 183%. In addition, the proposed method
can improve the capacitor current THD in the input filter
from 72.7% to 62.6%. As a result, this can confirm thatthe proposed method is able to reduce the volume of thecapacitor or the reactor in the input filter. In addition, theiron loss of the motor, the torque ripple and noise will be

Fig. 11 THD of input and output current.

Fig. 13. Comparison of THD between
the proposed method and the conventional method.

improved by the proposed method because the harmonics
of the output voltage is reduced.
VI. CONCLUSIONSIn this paper, a space vector modulation for a single tothree phase converter using an active buffer to absorb thepower ripple has been proposed. The proposed method
achieves a double edged modulation with low switchingcounts compared with the conventional method. Besides,
a symmetrical PWM pattern is formed at the peak of thecarrier. From the experimental results, the proposed
method improves the harmonic distortion around theswitching frequency component. Therefore, thedownsizing in the input filter can be achieved. In addition,
the delay in the current detection can be minimized, andas a result high performance can be achieved in theapplication of adjustable speed drive system.
This study was supported by Industrial Technology
Grant Program in 2009 from New Energy and Industrial
Technology Development Organization (NEDO) of Japan.

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