The 13th Symposium on Accelerator Science and Technology, Suita, Osaka, Japan, October 2001

MULTI-HARMONIC RF ACCELERATION SYSTEM FOR MEDICALPROTON SYNCHROTRON
H. Nishiuchi, K. Saito, *M. Kametani, *K. Ike and *K. Umekita
Hitachi, Ltd. Power & Industrial Systems R&D Laboratory
7-2-1 Omika-cho, Hitachi-shi, lbaraki-ken, 319-1221 Japan*Hitachi, Ltd. Mechanical Engineering Research Laboratory
502 Kandatsu-cho, Tsuchiura-shi, lbaraki-ken, 300-0013 JapanAbstract
We have been developing an RF acceleration systemfor medical proton synchrotron. In order to reduce thebeam loss by space-charge effect in a low energy domain,
the multi-harmonic RF acceleration method is effective,
in which the second and the third harmonic signals aresuperposed on the fundamental signaL We have applied
the high-speed digital signal processing techniquedeveloped originally, to fulfill real-time feedback controlof the frequency, phase and amplitude of the second andthe third harmonic signals as well as the fundamental
signal.

system, digital control system, RF amplifier and RFcavity.

1 INTRODUCTION
We have supplied the proton synchrotron system to the
Wakasa-wan Energy Research Center (WERC) and theProton Medical Research Center (PMRC) at theUniversity of Tsukuba. As for the accelerator system for
proton therapy, simple control and stable beam supply
are demanded because of a few operators. Therefore, wehave developed the FINEMET® core loaded typeun-tuned RF cavity and the RF digital control systemusing a direct digital synthesizer [1]. These equipments
can generate a high voltage and realize simple frequency
control.
The accelerator system, which we have beendeveloping, is a small synchrotron system with low
energy beam injection. Generally, in the low energy
domain, the beam loss by the space-charge effect isexpected. In order to reduce this beam loss,"multi-harmonic RF acceleration" is effective. The
multi-harmonic RF acceleration is the method to mitigate
the space-charge effect by keeping peak beam density
low. The harmonic signals with the integral multiple
frequencies of the fundamental signal are superposed on
RF acceleration voltage, and the resulting bunched beam
waveform is flattened.
It is important to control the phase and amplitude of
the harmonic signals relative to the fundamental signal,in order to carry out the multi-harmonic RF acceleration.
Therefore, the high-speed digital signal processing
system that can realize the multi-harmonic RFacceleration is under development.

2 SYSTEM OVERVIEW
Figure 1 shows the block diagram of the present RF
acceleration system. The RF acceleration system consistsof five sub-systems: B-clock system, analog control

Figure 1:Block diagram of the present RF acceleration
systemThe B-clock signal based on the output signal from theB-monitor, which detects change of magnetic field
intensity, is outputted by the B-clock system, and it istransmitted to the digital control system. The maximum
clock-rate is 100kHz, corresponding to a 0.2 gaussincrease. The analog control system has five feedback
loops: Automatic Voltage Control loop (AVC), radial
beam position control loop (AR loop), two kinds ofsynchrotron-oscillation suppression loops (A<!> and 2fsloop), and phase-difference detection loop (PD). The
digital control system updates the fundamental RF
frequency data by the B-clock signal. And the digitalcontrol system carries out feedback operation by thefrequency correction data from the analog signal
processing system. The frequencies of the harmonic
signals are obtained by carrying out the integral multipleof the feedback operation result. These operations haveto be processed in less than 2fls [2]. In the digital control
system, the phase feedback operation of the output RF
signal and the amplitude control are processed in parallelwith these frequency controls. The above operation
results are set on the digital synthesizers, respectively.
The fundamental signal and the harmonic signals arecombined after amplitude control by the analog controlsystem. The combined signal is amplified with the RF-238-

The 13th Symposium on Accelerator Science and Technology, Suita, Osaka, Japan, October 2001

amplifier, and fed to the RF cavity. As shown above, thedigital control system has to control the frequencies,
phases, and amplitudes of the fundamental and harmonic
signals on real-time. We have applied "SRC (SuperReal-time Controller)" to the multi-harmonic RF
acceleration system in order to realize theabove-mentioned real-time control. The original SRC
was developed for the intelligent robot control system [3]in which both high-speed 110 processing andcomplicated operation processing were demanded.

The I/0 unit has 110 interface for each control system,and the 110 interface connects to the FPGA unit. The
motion control system processes the frequency control inwhich the high-speed feedback less than 2!ls is required.
The intelligent control system processes the phase andamplitude control in which many I/0 control andcomplicated processing less than lOlls are required.
Table 1: Specifications of the RF digital control
system0.5-10 MHz
Frequency Range
24 bits (4.2Hz/LSB)
Frequency Resolution
12 bits (0.08deg/LSB)
Phase Resolution
12 bits (0.37VILSB)
Amplitude Resolution
16 Mbytes (SRAM)
Pattern Memory Capacity
140 MHz (double edge)
System Clock Frequency
Synthesizer Clock Frequency 70 MHz

3 SUPER REAL-TIME CONTROLLER
Figure 2 shows the block diagram of the digital control
system adopting the SRC, and Table 1 shows thespecifications of the digital control system.
From viewpoint in processing the SRC is divided into
two independent parallel control systems, that is, motion
control system and intelligent control system, in order toattain a real-time performance. Furthermore, the SRC has
the shared memory system (Dual Port RAM system,DPR) that can be accessed from the intelligent control
system and the motion control system. A PC forcommunication control (RF Server) can also access to
DPR via communication interface (COM I/F). The COM
1/F has the data transmission capability of more than
11Mbps. The DPR makes transfer of data possible is in
the mutual processing system.
The hardware unit of the SRC consists of baseprocessor and I/0 units. The base processor unit isprovided with CPU and memory for the motion control
and intelligent control system, respectively. In thissystem, the CPU of the base processor unit carries out asetup and initialization of pattern or constant data that aretransmitted from the RF-server to the I/0 unit.
Pr?cessing of real-time control is carried out by FPGA
umt prepared for the I/0 unit.

An FPGA unit is divided into the three control blocks
that is, the frequency controller, phase and amplitud~controller and memory controller. Each controller has
particular FPGAs. The frequency controller performs thefundamental frequency feedback, the calculation of thesecond and the third harmonics frequencies and RF
signals output management. The phase and amplitudecontroller processes the phases of the second and third
harmonic signals and the amplitudes of the fundamental
and harmonics signals. The memory controller manages
the pattern data address by the B-clock signal andT-clock signal.
The I/0 and the base processor units are connected
through Direct Access Channel (DA Ch.) in order torealize high-speed data transmission. In the SRC, thesame simple and high-speed processing as memory
access is realized for data transfer with the I/0 interface.
The pattern and constant data that are used for RF
Ethernet

PC! Bus!Ill :Frequency control system

0 :Phase and amplitude control system
Figure 2 : Block diagram of the digital control system in the RF aceleration system-239-The 13th Symposium on Accelerator Science and Technology, Suita, Osaka, Japan, October 2001

acceleration are set up from a synchrotron control system
via Ethernet. Those data are received with the RF Server,and transmitted to the SRC via COM 1/F. The patterndata transmitted from the RF Server is saved in thememory (16MByte) on 1/0 unit, and the constant data
are saved at constant register on the FPGA unit.

3.1 Frequency Control
The frequency of the digital synthesizer is calculated
as follows. The frequency correction voltages (LlR andil<J>) are sampled at a high-speed ADC (H-ADC). The
frequency correction voltages are converted into thefrequency correction data, which are added to thefrequency data of the fundamental signal updated by the
B-clock signal. The second and third harmonic frequency
data are calculated based on the fundamental frequency,respectively.
It is necessary to reduce an error of the setting
frequency of the digital synthesizer between the multiple
RF signals. In order to suppress the error of thefrequency data between the digital synthesizers low,frequency resolution of the digital synthesizer must behigh. By expressing frequency data in 24 bits, theaccuracy of 4.2Hz/LSB is acquired by a control clock of
70MHz.

3.2 Amplitude Control
It is necessary to superpose the harmonic signals to thefundamental signal at the desired amplitude rate. The
amplitude values are prepared beforehand for thefundamental signal and the harmonic signals by patterndata. The amplitude values are updated with the control
clock (T-clock) in a cycle of 50kHz and set to the AVC
circuit during acceleration control. The AVC circuit isequipped for each frequency component to realize thedesired amplitude values.

3.3 Phase Control
The phase of the harmonic signals must follow changeof the synchronous-phase of the fundamental signal. Thissynchronous-phase is determined from the amplitude
value of the fundamental signal and the rate of change ofmagnetic field strength. The amplitude value of thefundamental signal is controlled by the T-clock signal.
The phase data of the harmonic signals are also
beforehand prepared by pattern data and are updated by
the T-clock signal.
Moreover, in order to obtain the desired bunched beam
waveform, it is necessary to suppress the phase error of
the fundamental and harmonic signals below into±!degree. The output phase error between RF signals is
caused by a difference of the output timing between thedigital synthesizers. Furthermore, the output signal froma digital synthesizer is delayed with the individual
difference of the analog circuit. The maximum frequencyof the fundamental signal that can be combined with thesecond and the third harmonic signals is 3.3MHz becauseof the upper limitation of the operation frequency rangeof the RF acceleration system. The phase error of±!degree at the frequency of this fundamental signal isconverted into time of less than lns. Therefore, an errorof even one control clock for output timing is not allowed.
For a constant error like the output phase delay between
the multiple RF signals, the frequency characteristic of a
RF circuit is measured and the frequency-dependent
correction data based on the measurement are beforehand
prepared on pattern data. The frequency-dependent
correction data of the fundamental and harmonic signals
are update by the B-clock signal. For an inconstant error
like a temperature drift, choosing a circuit element withthe sufficient temperature characteristic is essential.
As shown above, phase control of the harmonic signals
needs to add the data updated with the two different
asynchronous control clocks one by one, and needs to set
the data on the digital synthesizers. In this system, byphase and amplitude controller, the two control patterndata are updated asynchronously, and addition operation
is carried out one by one. Furthermore, phase feedback
operation is carried out by phase-difference detection
data extracted by medium-speed ADC. By the phasefeedback operation, stable formation of optimal bunch
waveform is attained, even when the frequency
characteristic of the RF acceleration system changes.

4SUMMARIES

We have been developing an RF digital control system
realizing the multi-harmonic RF acceleration to reducethe beam loss by the space-charge effect in the low
energy domain. It is necessary that the frequency, phase,and amplitude of the fundamental signal and theharmonic signals to be controlled on real-time.
In order to realize these real-time controls, we haveapplied our original "SRC (Super Real-time Controller)"to this system. The SRC consists of the motion control
system for frequency control and the intelligent control
system for the phase and amplitude control. Processingof real-time control is carried out by FPGAREFERENCES[1] K. Saito et al., "RF Accelerating System for a
Compact Ion Synchrotron" PAC 2001, now printing.
[2] M. Kanazawa et al., "HIMAC RF system with adigital synthesizer" Nucl. Instr. and Meth. A 443 (2000)
205-214.
[3] N. Miyake et al., "Hardware and Software
Architecture for Intelligent Robot Control" IEEE
IROS'94 J-122, pl.
[4] A. Schnase et al., "An RF-Synthesizer for
Fundamental and Precisely Adjusted Higher Harmonics"
EPAC 1994, pp.l963-1965-240-