CAQD-MPO401-SR8CB(MPO24) /CAQD-MPO401-SR8CC(MPO16) 400G QSFP56 DD SR8 Optical Transceiver Module R02

400G QSFP56 DD SR8 Optical Transceiver Module
CAQD-MPO401-SR8CB(MPO24)
CAQD-MPO401-SR8CC(MPO16)
Features♦8 channels full-duplex transceiver modules♦

Transmission data rate up to 53Gbps per channel♦

8x53Gbps PAM4 transmitter and PAM4 receiver♦

8 channels 850nm VCSEL array♦

8 channels PIN photo detector array♦

Internal CDR circuits on both receiver and transmitter channels♦Power consumption <10W♦

Hot Pluggable QSFP DD form factor and Compliant with CMIS♦

Maximum link length of 70m on OM3 Multimode Fiber (MMF)and 100m on OM4 MMF with FEC♦

MPO24 PC connector receptacle (B version)♦MPO16 APC connector receptacle (C version)♦Built-in digital diagnostic functions♦

Operating case temperature 0℃ to +70℃♦

3.3V power supply voltage♦

RoHS compliant(lead free)

Applications♦

IEEE 802.3cd 200GBASE-SR4

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CAQD-MPO401-SR8CB(MPO24) /CAQD-MPO401-SR8CC(MPO16) 400G QSFP56 DD SR8 Optical Transceiver Module R02

Description
CA OPTRONICS GROUP CAQD-MPO401-SR8CB is a Eight-Channel, Pluggable, Parallel,
Fiber-Optic QSFP Double Density for 2x200 Gigabit Ethernet Applications. This transceiver is a highperformance module for short-range multi-lane data communication and interconnection applications. It
integrates eight data lanes in each direction with 8x26.5625GBd. Each lane can operate at 53.125Gbps
up to 70 m using OM3 fiber or 100 m using OM4 fiber with FEC. These modules are designed tooperate over multimode fiber systems using a nominal wavelength of 850nm. The electrical interface
uses a 76 contact edge type connector. The optical interface uses a MTP24/MPO24 PC connector (orMPO16/MTP16 APC connector ). The Common Management Interface Specification (CMIS) for QSFP
DD modules, This module incorporates CA OPTRONICS GROUP Technologies proven circuit andVCSEL technology to provide reliable long life, high performance, and consistent service.

Figure1. Module Block Diagram

2x200GBASE-SR4 QSFP DD is one kind of parallel transceiver. VCSEL and PIN array package iskey technique, through I2C system can contact with module.

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2CAQD-MPO401-SR8CB(MPO24) /CAQD-MPO401-SR8CC(MPO16) 400G QSFP56 DD SR8 Optical Transceiver Module R02

Absolute Maximum Ratings
Parameter
Supply Voltage
Input Voltage
Storage Temperature
Case Operating Temperature
Humidity(non-condensing)SymbolVcc
VinTst
TopRh

Min
-0.3
-0.3
-2005

Max
3.6
Vcc+0.3
857095Unit
VV℃℃%

Recommended Operating Conditions
Parameter
Supply Voltage
Operating Case temperature
Data Rate Per Lane
Humidity
Power Dissipation

Symbol
Vcc
TcafdRh
PmMin
3.130Symbol
Zin
ZoutΔVinΔVout
SwBER

Min9090

Typical
3.3

Max
3.47
7085
10UnitV℃
GBd%WMax110
110900900300
2.4E-4

Unitohmohm
mVp-p
mVp-pps-26.5625
5Electrical Specifications
Parameter
Differential input impedanceDifferential Output impedanceDifferential input voltage
Differential output voltage
Skew
Bit Error Rate
Near-end Eye Width at 10^-6probability(EW6)
Near-end Eye Height at 10^-6probability(EH6)
Far-end Eye Width at 10^-6probability(EW6)
Far-end Eye Height at 10^-6probability(EH6)
Near-end Eye Linearity

Typical
1001000.265

UI70mV

0.20

UI30mV

0.85-Note：
1. BER=2.4E-4; PRBS31Q@26.5625GBd. Pre-FEC
2.

Differential input voltage amplitude is measured between TxnP and TxnN.

3.

Differential output voltage amplitude is measured between RxnP and RxnN.

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CAQD-MPO401-SR8CB(MPO24) /CAQD-MPO401-SR8CC(MPO16) 400G QSFP56 DD SR8 Optical Transceiver Module R02

Optical Characteristics
Table 3 - Optical Characteristics
ParameterSymbolMin

TypicalMax

UnitNotes

Transmitter
Centre Wavelength

λc840

850860nm-

RMS spectral width
Average launch power,
each lane
Optical Modulation
Amplitude(OMAouter), each lane

∆λ--0.6nm-

Pout-6.5-

4dBm-

OMA-4.5

3dBm-

4.5

dB-

dB-

-30

dB-

860nm

-

（-6.5，-3.4）

dBm

1

Stressed Receiver
Sensitivity in OMAout-3

dBm

1

Maximum Average powerat receiver , each lane
input, each lane

4dBm

-

Transmitter and dispersion
eye closure(TDEC),eachlane

TDEC

Extinction Ratio

ER3-Average launch power ofOFF
transmitter, each lane
ReceiverCentre WavelengthλcReceiver Sensitivity inOMAoutRXsen

Minimum Average powerat receiver , each lane

840

850-7.9

Receiver Reflectance
LOS Assert-12-10

LOS De-Assert – OMA
LOS Hysteresis

dBm

-7.5
0.5

dB-dBm

-dBm

-dB-

Note：
1． Measured with conformance test signal at TP3 for BER = 2.4E-4 Pre-FEC

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4CAQD-MPO401-SR8CB(MPO24) /CAQD-MPO401-SR8CC(MPO16) 400G QSFP56 DD SR8 Optical Transceiver Module R02

Pin Description

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CAQD-MPO401-SR8CB(MPO24) /CAQD-MPO401-SR8CC(MPO16) 400G QSFP56 DD SR8 Optical Transceiver Module R02

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CAQD-MPO401-SR8CB(MPO24) /CAQD-MPO401-SR8CC(MPO16) 400G QSFP56 DD SR8 Optical Transceiver Module R02

Figure2. Electrical Pin-out Details

ModSelL Pin
The ModSelL is an input signal that must be pulled to Vcc in the QSFP-DD module. When held low by
the host, the module responds to 2-wire serial communication commands. The ModSelL allows the useof multiple QSFP-DD modules on a single 2-wire interface bus. When ModSelL is “High”, the module
shall not respond to or acknowledge any 2-wire interface communication from the host.

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CAQD-MPO401-SR8CB(MPO24) /CAQD-MPO401-SR8CC(MPO16) 400G QSFP56 DD SR8 Optical Transceiver Module R02

In order to avoid conflicts, the host system shall not attempt 2-wire interface communications within theModSelL de-assert time after any QSFP-DD modules are deselected. Similarly, the host must wait atleast for the period of the ModSelL assert time before communicating with the newly selected module.
The assertion and de-asserting periods of different modules may overlap as long as the above timing
requirements are met.

ResetL Pin
The ResetL signal shall be pulled to Vcc in the module. A low level on the ResetL signal for longer thanthe minimum pulse length (t_Reset_init) (SeeTable 13 ) initiates a complete module reset, returning

all user module settings to their default state.

InitMode Pin
InitMode is an input signal. The InitMode signal must be pulled up to Vcc in the QSFP-DD module. The
InitMode signal allows the host to define whether the QSFP-DD module will initialize under hostsoftware control (InitMode asserted High) or module hardware control (InitMode deasserted Low).
Under host software control, the module shall remain in Low Power Mode until software enables thetransition to High Power Mode, as defined in Section 7.5. Under hardware control (InitMode de-assertedLow), the module may immediately transition to High Power Mode after the management interface isinitialized. The host shall not change the state of this signal while the module is present. In legacy QSFPapplications, this signal is named LPMode. See SFF-8679 for signal description.

ModPrsL Pin
ModPrsL must be pulled up to Vcc Host on the host board and grounded in the module. The ModPrsL isasserted “Low” when the module is inserted and deasserted “High” when the module is physicallyabsent from the host connector.

IntL Pin
IntL is an output signal. The IntL signal is an open collector output and must be pulled to Vcc Host on
the host board. When the IntL signal is asserted Low it indicates a change in module state, a possible
module operational fault or a status critical to the host system. The host identifies the source of theinterrupt using the 2-wire serial interface. The IntL signal is deasserted “High” after all set interrupt
flags are read.

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CAQD-MPO401-SR8CB(MPO24) /CAQD-MPO401-SR8CC(MPO16) 400G QSFP56 DD SR8 Optical Transceiver Module R02

Power Supply Filtering
The host board should use the power supply filtering shown in Figure3.

Figure3. Host Board Power Supply Filtering

Optical Interface Lanes and Assignment
The optical interface port is a male MPO24(MTP24) PC connector for CAQD-MPO401-SR8CB

The optical interface port is a male MPO16(MTP16) APC connector for CAQD-MPO401-SR8CC

Figure 4. Optical Receptacle and Channel Orientation

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9CAQD-MPO401-SR8CB(MPO24) /CAQD-MPO401-SR8CC(MPO16) 400G QSFP56 DD SR8 Optical Transceiver Module R02

DIAGNOSTIC MONITORING INTERFACE
Digital diagnostics monitoring function is available on all CA OPTRONICS GROUP QSFP DDproducts. A 2-wire serial interface provides user to contact with module.

This subsection defines the Memory Map for a CMIS Module used for serial ID, digital monitoring andcertain control functions. The interface is mandatory for all CMIS devices. The interface has been
designed largely after the QSFP memory map. The memory map has been changed in order toaccommodate 8 electrical lanes and limit the required memory space. The single address approach isused as found in QSFP. Paging is used in order to enable time critical interactions between host andmodule.

The structure of the memory is shown in Figure 5. The memory space is arranged into a lower, single
page, address space of 128 bytes and multiple upper address space pages.This structure supports a flat
256 byte memory for passive copper cables and permits timely access to addresses in the lower page, e.g.
Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings, areavailable with the Page Select function. The structure also provides address expansion by adding
additional upper pages as needed. Upper pages 00-02 all contain static, non-volatile advertising registers.
Upper page 01 provides revision codes and advertising registers that indicate the capabilities of themodule. Upper page 02 provides thresholds for monitored functions. Upper page 03 provides a user
read/write space. The lower page and upper page 00 are required for passive copper cables and arealways implemented. In addition, upper pages 1, 2 and bank 0 pages 10h and 11h are required for activemodules. See CMIS Document Table 40 for details regarding the implementation of optional upper
pages and the bank pages.

Bank pages are provided to provide the ability to support modules with more than 8 lanes. Bank 0
provides lane-specific registers for the lower 8 lanes. Each additional bank provides support for anadditional 8 lanes.

Reserved bytes are for future use and shall not be used and shall be set to 0. Other organizations shallcontact the managing organization or the editor of this document to request allocations of registers. The
use of custom bytes is not restricted and may be vendor defined. The use of registers defined as custom
may be subject to additional agreements between module users and vendors.

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CAQD-MPO401-SR8CB(MPO24) /CAQD-MPO401-SR8CC(MPO16) 400G QSFP56 DD SR8 Optical Transceiver Module R02

Figure5. QSFP DD Memory Map

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CAQD-MPO401-SR8CB(MPO24) /CAQD-MPO401-SR8CC(MPO16) 400G QSFP56 DD SR8 Optical Transceiver Module R02

Mechanical Dimensions

Figure6. Mechanical SpecificationsRegulatory Compliance
CA OPTRONICS GROUP CAQD-MDO401-SR8C(B/C) transceivers are Class 1 Laser Products. They arecompliant with the following standards:
FeatureStandard

Laser Safety

IEC 60825-1:2014 (3rd Edition)
IEC 60825-2:2004/AMD2:2010
EN 60825-1-2014
EN 60825-2:2004+A1+A2

Electrical Safety

EN 62368-1: 2014
IEC 62368-1:2014
UL 62368-1:2014

Environmental protection

Directive 2011/65/EU with amendment(EU)2015/863

CE EMC

EN55032：2015
EN55035：2017
EN61000-3-2:2014
EN61000-3-3:2013

FCC

FCC Part 15, Subpart B
ANSI C63.4-2014

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Reference Documents
1. QSFP DD MAS Rev4.0
2. CMIS V4.0
3. IEEE802.3cd 200GBASE-SR4
4. OIF CEI-56G-VSR-PAM4

CAUTION:Use of controls or adjustment or performance of procedures other than those specified herein may result inhazardous radiation exposure.

Ordering information
Part Number
CAQD-MPO401-SR8CB

CAQD-MPO401-SR8CC

Product Description
QSFP DD, 2x200GBASE-SR4, 70m on OM3 Multimode Fiber (MMF)and 100m on OM4 MMF ,withDSP Power consumption <10W, MPO24(MTP24) PC connector
QSFP DD, 2x200GBASE-SR4, 70m on OM3 Multimode Fiber (MMF)and 100m on OM4 MMF ,withDSP Power consumption <10W, MPO16(MTP16) APC connector

Important Notice
Performance figures, data and any illustrative material provided in this data sheet are typical and must be
specifically confirmed in writing by CA OPTRONICS GROUP before they become applicable to any
particular order or contract. In accordance with the CA OPTRONICS GROUP policy of continuous
improvement specifications may change without notice.
The publication of information in this data sheet does not imply freedom from patent or other protective
rights of CA OPTRONICS GROUP or others. Further details are available from any CA OPTRONICSGROUP sales representative.

E-mail:sales@caoptronicsgroup.com
Official Site:www.caoptronicsgroup.com

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