CAQD-SPO201-LR8C 200G QSFPDD LR8 Optical Transceiver Module R01

200G QSFPDD LR8 Optical Transceiver Module
CAQD-SPO201-LR8CFeatures♦

8 channels full-duplex transceiver modules♦

Transmission data rate up to 26Gbps per channel♦

8 x 26Gb/s DFB-based LAN-WDM Cooling transmitter♦

8 channels PIN ROSA♦Internal CDR circuits on both receiver and transmitter channels♦

Support CDR bypass♦

Low power consumption <7.5W♦Hot Pluggable QSFP DD form factor and Compliant with CMIS

♦Up to 10km reach for G.652 SMF♦

Duplex LC receptacles♦

Built-in digital diagnostic functions♦Operating case temperature 0℃ to +70℃

♦3.3V power supply voltage♦RoHS2.0 compliant (lead free)

Applications♦IEEE 802.3ba 100GBASE-LR4Description
The CA OPTRONICS GROUP CAQD-SPO201-LR8C is an Eight-Channel, Pluggable, Fiber-Optic
QSFP DD LR8 for 2×100 Gigabit Ethernet Applications. This transceiver is a high performance module
for data communication and interconnect applications. It integrates eight data lanes in each direction
with 208Gbps bandwidth. Each lane can operate at 26Gbps up to 10km over G.652 SMF. Thesemodules are designed to operate over single mode fiber systems using LAN-WDM 8 wavelengths. Theelectrical interface uses a 76 contact edge type connector. The optical interface uses duplex LCconnector. This module incorporates CA OPTRONICS GROUP proven circuit and Optical technology toprovide reliable long life, high performance, and consistent service.

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CAQD-SPO201-LR8C 200G QSFPDD LR8 Optical Transceiver Module R01

Figure1. Module Block Diagram

Absolute Maximum Ratings
ParameterSymbolMinMaxUnit

Supply Voltage

Vcc-0.33.6V

Input Voltage

Vin-0.3

Vcc+0.3

V

Storage TemperatureTst-2085℃

Top

070℃

Humidity(non-condensing)

Rh

595%

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CAQD-SPO201-LR8C 200G QSFPDD LR8 Optical Transceiver Module R01

Recommended Operating Conditions
Parameter

SymbolMin

TypicalMax

Unit

Supply Voltage

Vcc

3.13

3.3

3.47

V

OperatingCase
Temperature

Tc

070℃

Data Rate Per Lane

fdHumidityRhPower Dissipation

Pm

Fiber Bend Radius

Rb25.78125

Gbps

585%

7.5W

10km0.002

Electrical Specifications
ParameterSymbol

Min

TypicalMax

Unit

Differential Input ImpedanceZin

90100110ohm

Differential Output ImpedanceZout

90100110ohm

Differential Input Voltage Amplitude1

ΔVin

190

700

mVp-p

Differential Output Voltage Amplitude2

ΔVout

300

850

mVp-p

Input Logic Level HighVIH

2.0VccV

Input Logic Level Low

VIL

00.8

V

Output Logic Level High

VOH

Vcc-0.5

Vcc

V

Output Logic Level Low

VOL00.4

V

Note:
1. Differential input voltage amplitude is measured between TxnP and TxnN.
2. Differential output voltage amplitude is measured between RxnP and RxnN.

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CAQD-SPO201-LR8C 200G QSFPDD LR8 Optical Transceiver Module R01

Optical Characteristics
Table 3 - Optical Characteristics
100GBASE-LR4
Parameter

SymbolMin

TypicalMax

Unit

L0

1272.55

1273.54

1274.54nm

L11276.89

1277.89

1278.89nm

L21281.25

1282.26

1283.27

nm

L31285.65

1286.66

1287.68nm

L41294.53

1295.56

1296.59

nm

L51299.02

1300.051301.09nm

L61303.541304.58

1305.63nm

L71308.091309.141310.19nm

Notes

Lane Wavelength

Transmitter

SMSR

SMSR

Total Average Launch Power

PTAverage Launch Power,each Lane
OMA, each Lane

30dB
10.5

dBm

PAVG

-4.3

4.5

dBm

POMA-1.3

4.5

dBm

5

dB

1

Difference in Launch Powerbetween any Two Lanes

Ptx,diff(OMA)
Launch Power in OMA
minus Transmitter and-2.3

Dispersion Penalty (TDP),

dBmeach Lane
TDP, each Lane

TDP

Extinction Ratio

ERCA OPTRONICS GROUP INC

2.24

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4CAQD-SPO201-LR8C 200G QSFPDD LR8 Optical Transceiver Module R01

100GBASE-LR4Parameter

SymbolRIN20OMARIN

-130

TOL

20dB

RT-12dB

Optical Return LossTolerance
Transmitter ReflectanceMin

TypicalMax

Unit

Notes

dB/Hz

Eye Mask coordinates:{0.25, 0.4, 0.45, 0.25, 0.28, 0.4}

X1, X2, X3, Y1, Y2, Y3
Average Launch Power OFF
Transmitter, each Lane

Poff

-30

2dBm

ReceiverDamage Threshold,each Lane

THd

5.5

dBm

Total Average Receive
PowerAverage Receive Power,-10.6

each Lane
Receive Power (OMA),each Lane
Receiver Sensitivity (OMA),
each Lane
Stressed Receiver
Sensitivity (OMA),
each Lane

SEN

10.5dBm

4.5dBm

4.5dBm

-8.6dBm-6.8dBm

5.5

dB

34

Difference in Receive Powerbetween any Two Lanes

Prx,diff(OMA)
LOS Assert

LOSA

-18

dBm

LOS Deassert

LOSD-15dBmLOS Hysteresis

LOSH

Receiver Electrical 3 dB
upper Cutoff Frequency,

CA OPTRONICS GROUP INC

dB

0.5

Fc

31

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5CAQD-SPO201-LR8C 200G QSFPDD LR8 Optical Transceiver Module R01

100GBASE-LR4
Parameter

SymbolMin

TypicalMax

UnitNotes

1.8dB

50.3

UI

0.47

UI

each Lane
Conditions of Stress Receiver Sensitivity Test (Note 5)
Vertical Eye Closure
Penalty, each Lane
Stressed Eye J2 Jitter,each Lane
Stressed Eye J9 Jitter,each Lane
Note：

1. Even if the TDP < 1 dB, the OMA min must exceed the minimum value specified here.
2. See Figure 4 below.
3. The receiver shall be able to tolerate, without damage, continuous exposure to a modulated optical

input signal having this power level on one lane. The receiver does not have to operate correctly atthis input power.
4. Measured with conformance test signal at receiver input for BER = 1x10-12.
5. Vertical eye closure penalty and stressed eye jitter are test conditions for measuring stressed receiversensitivity. They are not characteristics of the receiver.

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CAQD-SPO201-LR8C 200G QSFPDD LR8 Optical Transceiver Module R01

Pin Description

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CAQD-SPO201-LR8C 200G QSFPDD LR8 Optical Transceiver Module R01

Figure2. Electrical Pin-out Details

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CAQD-SPO201-LR8C 200G QSFPDD LR8 Optical Transceiver Module R01

ModSelL Pin
The ModSelL is an input signal that must be pulled to Vcc in the QSFP-DD module. When held
low by the host, the module responds to 2-wire serial communication commands. The ModSelL
allows the use of multiple QSFP-DD modules on a single 2-wire interface bus. When ModSelL
is “High”, the module shall not respond to or acknowledge any 2-wire interface communicationfrom the host.

In order to avoid conflicts, the host system shall not attempt 2-wire interface communications
within the ModSelL de-assert time after any QSFP-DD modules are deselected. Similarly, thehost must wait at least for the period of the ModSelL assert time before communicating with thenewly selected module. The assertion and de-asserting periods of different modules mayoverlap as long as the above timing requirements are met.

ResetL Pin
The ResetL signal shall be pulled to Vcc in the module. A low level on the ResetL signal forlonger than the minimum pulse length (t_Reset_init) (SeeTable 13 ) initiates a complete

module reset, returning all user module settings to their default state.

LPMode Pin
LPMode is an input signal. The LPMode signal shall be pulled up to Vcc in the QSFP-DD
module (see Table 2). LPMode is used in the control of the module power mode.
See CMIS Section 6.3.1.3.

ModPrsL PinModPrsL must be pulled up to Vcc Host on the host board and grounded in the module. TheModPrsL is asserted “Low” when the module is inserted and deasserted “High” when themodule is physically absent from the host connector.

IntL Pin
IntL is an output signal. The IntL signal is an open collector output and must be pulled to Vcc
Host on the host board. When the IntL signal is asserted Low it indicates a change in module
state, a possible module operational fault or a status critical to the host system. The hostCA OPTRONICS GROUP INCwww.caoptronicsgroup.com+1-510-366-7353

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CAQD-SPO201-LR8C 200G QSFPDD LR8 Optical Transceiver Module R01

identifies the source of the interrupt using the 2-wire serial interface. The IntL signal isdeasserted “High” after all set interrupt flags are read.

Power Supply Filtering

The host board should use the power supply filtering shown in Figure3.

Figure3. Host Board Power Supply Filtering

DIAGNOSTIC MONITORING INTERFACE
Digital diagnostics monitoring function is available on all CA OPTRONICS GROUP QSFP DDproducts. A 2-wireserial interface provides user to contact with module.

This subsection defines the Memory Map for a CMIS Module used for serial ID, digitalmonitoring and certain control functions. The interface is mandatory for all CMIS devices. Theinterface has been designed largely after the QSFP memory map. The memory map has beenchanged in order to accommodate 8 electrical lanes and limit the required memory space. The
single address approach is used as found in QSFP. Paging is used in order to enable time
critical interactions between host and module.

The structure of the memory is shown inCA OPTRONICS GROUP INC

Figure 5 . The memory space is arranged into awww.caoptronicsgroup.com+1-510-366-7353

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CAQD-SPO201-LR8C 200G QSFPDD LR8 Optical Transceiver Module R01

lower, single page, address space of 128 bytes and multiple upper address space pages. Thisstructure supports a flat 256 byte memory for passive copper cables and permits timely accessto addresses in the lower page, e.g. Flags and Monitors. Less time critical entries, e.g. serial ID
information and threshold settings, are available with the Page Select function. The structure
also provides address expansion by adding additional upper 1pages as needed. Upper pages
00-02 all contain static, non-volatile advertising registers. Upper page 01 provides revision
codes and advertising registers that indicate the capabilities of the module. Upper page 02
provides thresholds for monitored functions. Upper page 03 provides a user read/write space.
The lower page and upper page 00 are required for passive copper cables and are always
implemented. In addition, upper pages 1, 2 and bank 0 pages 10h and 11h are required for
active modules. See CMIS Document Table 40 for details regarding the implementation ofoptional upper pages and the bank pages.

Bank pages are provided to provide the ability to support modules with more than 8 lanes. Bank
0 provides lane-specific registers for the lower 8 lanes. Each additional bank provides support
for an additional 8 lanes.

Reserved bytes are for future use and shall not be used and shall be set to 0. Otherorganizations shall contact the managing organization or the editor of this document to request
allocations of registers. The use of custom bytes is not restricted and may be vendor defined.
The use of registers defined as custom may be subject to additional agreements between
module users and vendors.

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CAQD-SPO201-LR8C 200G QSFPDD LR8 Optical Transceiver Module R01

Figure4. QSFP DD Memory Map

Mechanical Dimensions

Figure5. Mechanical Specifications
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CAQD-SPO201-LR8C 200G QSFPDD LR8 Optical Transceiver Module R01

Regulatory Compliance
CA OPTRONICS GROUP GQD-SPO201-LR8C transceivers are Class 1 Laser Products. They arecompliant with thefollowing standards:
FeatureStandard
IEC 60825-1:2014 (3rd Edition)
IEC 60825-2:2004/AMD2:2010
EN 60825-1-2014
EN 60825-2:2004+A1+A2
EN 62368-1: 2014
IEC 62368-1:2014
UL 62368-1:2014

Laser Safety

Electrical Safety
Environmental protection

Directive 2011/65/EU with amendment(EU)2015/863
EN55032：2015
EN55035：2017
EN61000-3-2:2014
EN61000-3-3:2013
FCC Part 15, Subpart B
ANSI C63.4-2014

CE EMC

FCC

References
1. QSFP DD MAS Rev5.0
2. CMIS V4.0
3. IEEE802.3ba 100GBASE-LR4
4. OIF CEI-528G-VSR

CAUTION:Use of controls or adjustment or performance of procedures other than those specified herein may resultin hazardous radiation exposure.

Ordering information
Part Number
CAQD-SPO201-LR8C

CA OPTRONICS GROUP INC

Product Description
QSFP DD, 2x100GBASE-LR4, Duplex LC,up to 10km G.652 SMF

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Important Notice
Performance figures, data and any illustrative material provided in this data sheet are typicaland must be specifically confirmed in writing by CA OPTRONICS GROUP before they become
applicable to any particular order or contract. In accordance with the CA OPTRONICS GROUP
policy of continuous improvement specifications may change without notice.

The publication of information in this data sheet does not imply freedom from patent or otherprotective rights of CA OPTRONICS GROUP or others. Further details are available from any
CA OPTRONICS GROUP sales representative.

E-mail:sales@caoptronicsgroup.com
Official Site:www.caoptronicsgroup.com

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