2013 Symposia on VLSI Technology and Circuits
Suzaku ITime

June 11th (Tuesday)

Suzaku III

Suzaku II

Shunju I

Shunju II

Registration

7:30-17:00

8:20-11:50

Circuits Short Course

8:20-11:50

T1 "Welcome and Plenary Session"

Circuits Workshop
T1-1

8:30-8:45

T1-2

8:45-9:25 (Plenary)

TSMC

System Scaling and Collaborative Open Innovation

T1-3

9:25-10:05 (Plenary)Welcome and Opening Remarks
8:30-10:05

Qualcomm
System Design Considerations for Next Generation Wireless Mobile Devices
Technologies

T2: Highlight

8:20-11:50 Circuits Short Course

8:20-11:50 Circuits Workshop

10:30-12:10

T2-1

10:30-10:55

Intel

A 22nm High Performance Embedded DRAM SoCTechnology Featuring Tri-Gate Transistors and MIMCAP
COB

T2-2

10:55-11:20

IBM
Research

High-Performance Si1-xGex Channel on Insulator Trigate PFETs Featuring an Implant-Free Process andAggressively- Scaled Fin and Gate Dimensions,T2-3

11:20-11:45

GLOBALFOUNDRIESFirst Demonstration of Strained Ge-in-STI IFQW pFETs Featuring Raised SiGe75% S/D, Replacement Metal
Gate and Germanided Local Interconnects

T2-4

11:45-12:10

Panasonic

Thin Organic Photoconductive Film Image Sensors with
Extremely High Saturation of 8500 electrons/μm 2

T3-1

13:30-13:55

T4-1

13:30-13:55 (Invited)

The Univ.
of TokyoExamination of Physical Origins Limiting Effective
Mobility of Ge MOSFETs and the Improvement by
Atomic Deuterium Annealing

AlteraManufacturability Optimization and Design
Validation Studies for FPGA-Based, 3D
Integrated Circuits

T3-2

13:55-14:20

T4-2

13:55-14:20 (Invited)

The Univ.
of Tokyo

Enhancement of High-Ns Electron Mobility in IBM
Research
Sub-nm EOT Ge n-MOSFETs

T3: Ge MOSFET

13:30-15:35

13:40-17:00 Circuits Short Course

13:40-17:00 Circuits Workshop

T4: (FS) 3D System and Packaging

T3-3

14:20-14:45

GNC

Enhancement o f Hole Mobility and Cut - Off Characteristics ofStrained Ge Nanowire pMOSFETs by Using Plasma Oxidized TSMC
GeOx Inter-Layer for Gate Stack

T4-3

14:20-14:45
An Integrated Air Gap Structure to Achieve HighPerformance TSV Interconnects for 28nm 3D-IC
Integration

T3-4

14:45-15:10

T4-4

14:45-15:10

Stanford
Univ.

Fabrication of GeSn-On-Insulator (GSOI) to Enable
Monolithic 3D Co-Integration of Logic and Photonics

Seoul
National
Univ.

A New Guard-Ring Technique to Reduce Coupling
Noise from Through Silicon Via (TSV) Utilizing
Inversion Charge Induced by Interface Charge

T3-5

15:10-15:35

T4-5

15:10-15:35

National
Univ. ofSingapore

Uniaxially Strained Germanium-Tin (GeSn) Gate-AllAround Nanowire PFETs Enabled by a Novel TopDown Nanowire Formation Technology

TSMC

High-Performance Inductors for Integrated FanOut Wafer Level Packaging (InFO-WLP)

T5-1

15:50-16:15

The Univ.
of Tokyo

Strained Extremely-Thin Body In 0.53Ga0.47As-OnToshiba
Insulator MOSFETs on Si Substrates

T5: III-V MOSFET

15:50-17:30

20:00-22:00

Scaling Challenges of Packaging in the Era of
Big Data

T6: (FS) 3D and Emerging Memory
T6-1

15:50-16:15 (Invited)
Bit Cost Scalable (BiCS) Technology for Future
Ultra High Density Storage Memories

T5-2

16:15-16:40

T6-2

The Univ.
of TokyoHigh Performance Extremely-Thin Body InAs-OnInsulator MOSFETs on Si with Ni-InGaAs Metal S/D by
Contact Resistance Reduction Technology

Panasonic Characteristics and Retention Properties for Highly

T5-3

16:40-17:05

T6-3

16:40-17:05

Stanford
Univ.

Optimal Device Architecture and HeteroIntegration Scheme for III-V CMOS

SamsungEnhancement of Switching Margin by Utilizing Superior
Pinned Layer Stability for Sub-20nm Perpendicular
STT-MRAM

T5-4

17:05-17:30

T6-4

17:05-17:30

GNC

Demonstration of InGaAs/Ge Dual Channel
CMOS Inverters with High Electron and Hole
Mobility Using Staked 3D Integration

IBM Almaden
ResearchCenterRecovery Dynamics and Fast (Sub-50ns) Read Operation
with Access Devices for 3D Crosspoint Memory Based on
Mixed-Ionic-Electronic-Conduction (MIEC)

16:15-16:40 (Invited)
Comprehensive Understanding of Conductive Filament
Reliable ReRAM

Joint Rump Session

Technology Rump Session 1

Technology Rump Session 2

SOC vs. 3D IC in the More-than-Moore Era

Low Voltage - How Low Can We Go?

Novel Hierarchy in Emerging Memory

June 10th (Monday) 8:10-17:15 / Shunju I
Technology Short Course:
2013 Silicon Nanoelectronics Workshop: June 9th (Sunday) 08:30-18:30, 10th (Monday) 08:30-17:00 / Suzaku III
2013 Spintronics Workshop on LSI:
June 10th (Monday) 19:00-22:00 / Suzaku II2013 Symposia on VLSI Technology and Circuits
Suzaku ITime

June 12th (Wednesday)

Suzaku III

Suzaku II

Shunju I

Shunju II

Registration

7:30-17:00

C1 "Welcome Session"
C1-1

8:30-8:45

Welcome and Opening Remarks
8:30-9:50"Executive Panel "C1-2

8:45-9:50

Executive Panel (4 presentations)C3(JFS): 3D Integrated Circuits & Applications

10:30-12:35

C2: Imagers
C2-1

10:30-10:55

TSMC

An Extra Low-Power 1Tbit/s Bandwidth PLL/DLL-Less eDRAM PHY Using 0.3V Low-Swing IO
for 2.5D CoWoS Application

AptinaJapan

A 1-inch Optical Format, 14.2M-Pixel, 80fps CMOS
National
Image Sensor with a Pipelined Pixel Reset and Readout Univ. of
Operation
SingaporeC3-2

10:55-11:20

C2-2

10:55-11:20

T7-2

TSMC

3D IC Heterogeneous Integration of GPS RF Receiver, Baseband, and DRAM on CoWoS with
System BIST Solution

Univ. of
MichiganA 5.9μm-Pixel 2D/3D Image Sensor with
Background Suppression over 100klx

Samsung

C3-3

11:20-11:45

11:20-11:45

T8-3

11:20-11:45

Fudan
Univ.

Reliability Significant Improvement of Resistive
Switching Memory by Dynamic Self-Adaptive Write
Method

11:45-12:10

3D Stackable Vertical-Gate BE-SONOS NAND Flash with Layer-Aware Program-and-Read
MacronixInternational Schemes and Wave-Propagation Fail-Bit-Detection against Cross-Layer Process Variations

T8-1

10:30-10:55

A New Expandible ZnS-SiO2 Liner Stressor for
N-Channel FinFETs

imec

Modeling RRAM Set/Reset Statistics Resulting in
Guidelines for Optimized Operation

10:55-11:20

T8-2

10:55-11:20

3 Dimensional Scaling Extensibility on Epitaxial Source
Drain Strain Technology toward Fin FET and Beyond

A Novel High Performance WOX ReRAM Based
MacronixInternational on Thermally-Induced SET Operation

C2-3

11:20-11:45

T7-3

Panasonic

An Ultra-Low Noise Photoconductive Film Image
Sensor with a High-Speed Column Feedback Amplifier
Noise Canceller

Effects of Layout and Process Parameters on
SEMATECH Device/Circuit Performance and Variability for 10nm
Node FinFET Technology

11:45-12:10

C2-4

11:45-12:10

T7-4

11:45-12:10

T8-4

CEA, Leti

A 0.9 pJ/bit, 12.8 GByte/s WideIO Memory Interface in a 3D-IC NoC-Based MPSoC

Columbia
Univ.

A 100-fps Fluorescence Lifetime Imager inStandard 0.13-μm CMOS

imec

Quantum Well Band Calculations and Their Impact on
Device Isolation and Work Function Requirements for
SiGe and III/V Strained Heterostructure FinFETs

Macronix
A Novel Conducting Bridge Resistive Memory Using aInternational Semiconducting Dynamic E-Field Moderating Layer

C3-5

12:10-12:35

C2-5

12:10-12:35

T7-5

12:10-12:35

T8-5

ASET

Scalable 3D-FPGA Using Wafer-to-Wafer TSV Interconnect of 15 Tbps/W, 3.3 Tbps/mm 2

Univ. of
Texas

820-GHz Imaging Array Using Diode-Connected
NMOS Transistors in 130-nm CMOS

GNC

Superior Cut-Off Characteristics of Lg=40nm W fin=7nm
Stanford
Poly Ge Junctionless Tri-Gate FET for Stacked 3D
Univ.
Circuits Integration

C5-1

13:55-14:20

C4-1

13:55-14:20

JJ1-1

13:55-14:20 (Invited)

T9-1

13:55-14:20

MediaTek

A 75.1dB SNDR 840MS/s CT ΔΣ Modulator with 30MHz Bandwidth and 46.4fJ/conv FOM in
55nm CMOS

Hong Kong
Univ. of Sci.
and Tech.

A 200-Channel 10μW 0.04mm2 Dual-Mode
Acquisition IC for High Density MEA

TSMC

Enabling Circuit Design Using FinFETs throughClose Ecosystem Collaboration

LEAP

Charge Injection Super-Lattice Phase Change Memory
for Low Power and High Density Storage Device
Applications

C5-2

14:20-14:45

C4-2

14:20-14:45

JJ1-2

14:20-14:45

T9-2

14:20-14:45

Univ. of
MichiganA 69dB SNDR, 25MHz BW, 800MS/s Continuous-Time Bandpass ΔΣ ADC Using DAC Duty
Cycle Control for Low Power and Reconfigurability

A Neurochemical Pattern Generator SoC with SwitchedCase WesternElectrode Management for Single-Chip Electrical Stimulation
Reserve Univ.
and 9.3μW, 78pArms, 400V/s FSCV SensingIntel

A 3.6GB/s 1.3mW 400mV 0.051mm 2 Near-Threshold
Voltage Resilient Router in 22nm Tri-Gate CMOS

A Scalable Volume-Confined Phase Change
MacronixInternational Memory Using Physical Vapor Deposition

C5-3

14:45-15:10

C4-3

14:45-15:10

JJ1-3

14:45-15:10

T9-3

14:45-15:10

Intel

A 66dB SNDR 15MHz BW SAR Assisted ΔΣ ADC in 22nm Tri-Gate CMOS

National
Chiao Tung
Univ.

A 28.6μW Mixed-Signal Processor for Epileptic
Seizure Detection

imec

Layout-Induced Stress Effects in 14nm & 10nm
FinFETs and Their Impact on Performance

LEAP

Novel Highly Scalable Multi-Level Cell for STTMRAM with Stacked Perpendicular MTJs

C5-4

15:10-15:35

C4-4

JJ1-4

15:10-15:35

T9-4

IBM Microelectronics

Process and Local Layout Effect Interaction on a
LEAPHigh Performance Planar 20nm CMOS

C5-5

15:35-16:00

Oregon State A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-Based ADC with On-Chip Deterministic Digital
Univ.
Background Calibration in 90nm CMOS

T10: More than Moore

19:00-21:00

10:30-10:55

C3-4

National
A 379nW 58.5dB SNDR VCO-Based ΔΣ Modulator for Bio-Potential Monitoring
Taiwan Univ.

16:10-17:50

T7-1

T8: ReRAM 1

10:30-10:55

C5: Delta-Sigma Modulators

13:55-16:00

T7: Advanced FinFET

C3-1

C4: Circuits for Biomedical Applications

15:10-15:35
A 1024-Channel CMOS Microelectrode-Array System

ETH Zurich with 26’400 Electrodes for Recording and Stimulation ofElectro- Active Cells In-Vitro

12:10-12:35
Dopant Selection Rules for Extrinsic Tunability of HfO x
RRAM Characteristics: A Systematic Study

JJFS1: Design Enablement

C4-5

15:35-16:00

Hong Kong
Univ. of Sci.
and Tech.

A 51fA/HZ0.5 Low Power Heterodyne Impedance
STARC
Analyzer for Electrochemical Impedance Spectroscopy

JJ1-5

T9: PCRAM and MRAM

15:10-15:35
Top-Pinned Perpendicular MTJ Structure with aCounter Bias Magnetic Field Layer for Suppressing a
Stray-Field in Highly Scalable STT-MRAM

15:35-16:00

T9-5

15:35-16:00

0.5V Image Processor with 563 GOPS/W SIMD and 32bit
CPU Using High Voltage Clock Distribution (HVCD) and
Adaptive Frequency Scaling (AFS) with 40nm CMOS

RenesasElectronics

Low-Current Domain Wa l l Mot ion MRAM with
Perpendicularly Magnetized CoFeB/MgO Magnetic
Tunnel Junction and Underlying Hard Magnets

T11-1

16:10-16:35

C6: Application Specific Wireless Transceivers(break)T11: NAND and 3D NVM

T10-1

16:10-16:35

C6-1

16:10-16:35

JJ1-6

Univ. of
California

Benefits of Segmented Si/SiGe p-Channel MOSFETs forAnalog/RF Applications

Broadcom

A 2dB NF Receiver with 10mA Battery Current
Suitable for Coexistence Applications

Intel Mobile
Communicati Design for ESD Protection at Its Limits
ons Group

T10-2

16:35-17:00

C6-2

16:35-17:00

JJ1-7

Toshiba

Scaling Strategy for Low Power RF Applications with Multi Gate Oxide Dual Work Function(DWF) MOSFETs Utilizing Self-Aligned Integration Scheme

Mstar Semiconductor

A Low-Cost SAW-Less GSM/GPRS SoC with Integrated Univ. ofConnectivity and 32-kHz Crystal Removal in 55nm
Tsukuba

T10-3

17:00-17:25

C6-3

17:00-17:25

SamsungTime of Flight Image Sensor with 7μm Pixel and 640x480 Resolution

Panasonic

A 1.15V Low Power Mobile ISDB-Tsb/Tmm/T and ST Microelectronics
DVB-T Tuner SoC in 40nm CMOSFirst Demonstration of a Full 28nm High-k/Metal Gate
Study of the Interference and Disturb Mechanisms of SplitMacronix
Page 3D Vertical Gate (VG) NAND Flash and Optimized
Circuit Transfer from Bulk to UTBB FDSOI Technology
International Programming Algorithms for Multi-Level Cell (MLC) Storage
through Hybrid Integration

T10-4

17:25-17:50

C6-4

17:25-17:50

JJ1-9

17:25-17:50

T11-4

17:25-17:50

Univ. of
California

A MEMS-Based Charge PumpIntel

Two-Channel Receiver Back-End Using Statistically
Calibrated HRM with >70dB 3rd and 5th Harmonic
Rejection for Carrier Aggregation in 32nm CMOS

ST Microelectronics

2.6GHz Ultra-Wide Voltage Range Energy
Efficient Dual A9 in 28nm UTBB FD-SOI

Stanford
Univ.

3D Vertical RRAM – Scaling Limit Analysis andDemonstration of 3D Array Operation

JJ1-8

16:10-16:35 (Invited)

A Novel Bit Alterable 3D NAND Flash Using JunctionMacronix
Free P-Channel Device with Band-to-Band TunnelingInternational
Induced Hot-Electron Programming

16:35-17:00

T11-2

Application of Low-Noise TIA ICs for Novel Sensing of
MOSFET Noise up to the GHz Region

A New Read Method Suppressing Effect of Random
Seoul
Telegraph Noise in NAND Flash Memory by Using
National Univ
Hysteretic Characteristic

16:35-17:00

17:00-17:25

T11-3

17:00-17:25

Joint Banquet

2013 Symposia on VLSI Technology and Circuits
Suzaku ITime

Suzaku II

June 13th (Thursday)

Suzaku III

Shunju I

Shunju II

Registration

8:00-17:00

C7 "Plenary Session"
C7-1

T12: ReRAM 2

8:45-9:25 (Plenary)T12-1

8:30-8:55
Understanding of the Intrinsic Characteristics
and Memory Trade-Offs of Sub-μA Filamentary
RRAM Operation

Samsung

Perspectives on Mobile Devices and Their Impact on Semiconductor Technologies

imec

C7-2

9:25-10:05 (Plenary)T12-2

8:55-9:20

Corning

Glass for the Future: Displays and Semiconductors

imec

RTN Insight to Filamentary Instability and Disturb
Immunity in Ultra-Low Power Switching HfOx and AlOx
RRAM

T12-3

9:20-9:45

8:30-10:10

Self-Rectifying Bipolar TaOx/TiO2 RRAM with
National
Chiao Tung Superior Endurance Over 1012 Cycles for 3D
Univ.
High-Density Storage- Class Memory

T12-4

9:45-10:10
Multi-Layer Tunnel Barrier (Ta2O5/TaOx/TiO2)

POSTECH Engineering for Bipolar RRAM Selector

Applications

C8: Pipeline ADCs
C8-1

T13: RTN

10:30-10:55

T13-1

10:30-10:55

C9(JFS) Emerging Memories
C9-1

10:30-10:55

IBM T. J.

10:30-10:55

1Mb 0.41 μm2 2T-2R Cell Nonvolatile TCAM with
Two-Bit Encoding and Clocked Self-Referenced
Sensing

imec

Highly Scalable Effective Work Function Engineering
Approach for Multi-VT Modulation of Planar and FinFETBased RMG High-k Last Devices for (Sub-)22nm Nodes

C9-2

10:55-11:20

T14-2

10:55-11:20

TohokuUniv.

Fabrication of a 99%-Energy-Less Nonvolatile MultiFunctional CAM Chip Using Hierarchical Power Gating for a
Massively-Parallel Full-Text-Search Engine

imec

Heated Implantation with Amorphous Carbon
CMOS Mask for Scaled FinFETs

T14-3

11:20-11:45

Broadcom

A 5.4GS/s 12b 500mW Pipeline ADC in 28nm
CMOS

Toshiba

Experimental Study of Channel Doping Concentration
WatsonImpacts on Random Telegraph Signal Noise and Successful
Research
Noise Suppression by Strain Induced Mobility Enhancement

C8-2

10:55-11:20

T13-2

10:55-11:20

OregonState Univ.

A 75.9dB-SNDR 2.96mW 29fJ/Conv-Step
Ringamp-Only Pipelined ADC

Beijing Univ. New Characterization Method and Impacts on Logic

CenterDeep Understanding of AC RTN in MuGFETs throughCircuits

C8-3
11:20-11:45
10:30-12:35 Oregon State A 70MS/s 69.3dB SNDR 38.2fJ/Conversion-

T14: Process Technology
T14-1

T13-3

11:20-11:45

C9-3

11:20-11:45

Step Time- Based Pipelined ADC

Univ. of
Minnesota

RTN Induced Frequency Shift Measurements
Using a Ring Oscillator Based Circuit

Toshiba

GLOBALA 250-MHz 256b-I/O 1-Mb STT-MRAM with Advanced
Perpendicular MTJ Based Dual Cell for Nonvolatile Magnetic FOUNDRI
Caches to Reduce Active Power of Processors
ES

NFET Effective Work Function Improvement via
Stress Memorization Technique in Replacement
Metal Gate Technology

C8-4

11:45-12:10

T13-4

11:45-12:10

C9-4

11:45-12:10

11:45-12:10

Stanford
Univ.

A 12-Bit, 200-MS/s, 11.5-mW Pipeline ADC
Using a Pulsed Bucket Brigade Front-End

imec

Degradation of Time Dependent Variability Due
to Interface State Generation

TohokuUniv.

Barrier Height Reduction to 0.15eV and Contact Resistivity
A 1.5nsec/2.1nsec Random Read/Write Cycle 1Mb
The
STT-RAM Using 6T2MTJ Cell with Background Write Pennsylvani Reduction to 9.1×10-9 Ω-cm2 Using Ultrathin TiO2-x
a State Univ. Interlayer between Metal and Silicon
for Nonvolatile e-Memories

C8-5

12:10-12:35

C9-5

12:10-12:35

Univ. of
California

A 10-Bit 800-MHz 19-mW CMOS ADC

National
Tsing Hua
Univ.

Area-Efficient Embedded RRAM Macros with Sub-5ns
Random-Read-Access-Time Using Logic-Process Parasitic- ST Micro
BJT- Switch (0T1R) Cell and Read-Disturb-Freeelectronics
Temperature-Aware Current-Mode Read Scheme

JJ2-1

14:20-14:45 (Invited)

T15-1

Univ

T14-4

T14-5

12:10-12:35
64nm Pitch Interconnects: Optimized for
Designability, Manufacturability and Extendibility

Luncheon Talk
12:45-14:05

Otowa
Electric

Symbiosis with Lightning Which Is One of
the Most Spectacular Natural Phenomenon

C10: PLL Building Blocks

C11: Low Power Wireless

KAIST

imec

A 0.9V Low-Power 0.4-6GHz Linear SDR
Receiver in 28nm CMOSIBM SRDC

Fully-Depleted Planar Technologies and Static
RAM

Innovative Through-Si 3D Lithography for Ultimate
ST MicroSelf-Aligned Planar Double-Gate and Gate-All-Aroundelectronics
Nanowire Transistors

C10-2

14:45-15:10

C11-2

14:45-15:10

JJ2-2

14:45-15:10

T15-2

14:45-15:10

A 0.11mm 2, 5.7-to-6.7GHz, Parametrically Pumped
Quadrature LC-VCO with Digital Outputs

Texas
An Ultra Low Power, Reconfigurable, MultiInstruments Standard Transceiver Using Fully Digital PLL

RenesasElectronics

A 20nm 0.6V 2.1μW/MHz 128kb SRAM with No Half
Select Issue by Interleave Wordline and Hierarchical
Bitline Scheme

Toshiba

Systematic Understanding of Channel-Size
Dependence of Low-Frequency Noise in 10nmDiameter Tri-Gate Nanowire MOSFETs

JJ2-3

15:10-15:35

T15-3

15:10-15:35

FDSOI Process/Design Full Solutions for Ultra Low
Leakage, High Speed and Low Voltage SRAMs

CEA,
LETI

Scaling of Ω-Gate SOI Nanowire N- and P-FET Down
to 10nm Gate Length: Size- and OrientationDependent Strain Effects

15:35-16:00

15:10-15:35

C11-3

Keio Univ

A 720μW 873MHz-1.008GHz Injection-Locked
Frequency Multiplier with 0.3V Supply Voltage in
90nm CMOS

NTTIntermittent Transmitter Circuit with Novel Feedback Source
ST MicroMicrosystem
Follower Amplifier for Solar Powered 5-mm-Cubic Wirelesselectronics
Integration Labs Sensor Nodes with 1/20λ Dipole Antenna

C10-4

15:35-16:00

C11-4

STARC

93% Power Reduction by Automatic Self Power Gating(ASPG) and Multistage Inverter for Negative Resistance(MINR) in 0.7V, 9.2μW, 39MHz Crystal Oscillator

Purdue Univ. VCO-PA-LNA-Switch-Modulator Co-Design for Low

C12-1

15:10-15:35

15:35-16:00

14:20-14:45

JJ2-4

15:35-16:00

T15-4

LEAP

Ultralow-Voltage Operation of Silicon-on-Thin-BOX(SOTB) 2Mbit SRAM Down to 0.37 V Utilizing
Adaptive Back Bias

National
Performance of GAA Poly-Si Nanosheet (2nm)
Chiao-Tung Channel of Junctionless Transistors with Ideal
Univ.
Subthreshold Slope

A -90dBm Sensitivity Wireless Transceiver Using
Power Insect- Based Wireless Sensor Networks

T17-1

16:15-16:40

C13: Linear Regulators and DC-DC Converters

T17: Late News Session
16:15-16:30

C13-1

16:15-16:40

JJ2-5

16:15-16:40 (Invited)

National
Chiao Tung
Univ.

A 0.6V Resistance-Locked Loop Embedded Digital
Low Dropout Regulator in 40nm CMOS with 77%
Power Supply Rejection Improvement

AIST

Enhancing SRAM Performance by Advanced FinFET
Device and Circuit Technology Collaboration for 14nm GNC
Node and Beyond(break)T16: Beyond CMOS
T16-1

16:15-16:40

Oregon State A 2.5GHz 5.4mW 1-to-2048 Digital Clock
Univ.
Multiplier Using a Scrambling TDC

Univ. of
California

Record Extrinsic Transconductance (2.45 mS/μm at
VDS = 0.5 V) InAs/In0.53Ga0.47As Channel MOSFETs
Using MOCVD Source-Drain Regrowth

C12-2

T17-2

16:30-16:45

C13-2

16:40-17:05

JJ2-6

16:40-17:05

T16-2

IBM Semi
conductor

Experimental Analysis and Modeling of Self Heating
Effect in Dielectric Isolated Planar and Fin Devices

KAIST

High-Gain Wide-Bandwidth Capacitor-Less LowDropout Regulator with Zero Insertion Utilizing
Frequency Response of Inner Loops

Intel

Dual-VCC 8T-Bitcell SRAM Array in 22nm Tri-Gate
CMOS for Energy-Efficient Operation across WideDynamic Voltage Range

Panasoni
Ferroelectric Memristor to Enable On-Chip Patternc
Recognition

T16-3

16:40-17:05

Seoul
A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with
National Univ. Two-Cycle Locking Time and Dither-Free Tracking

20:00-22:00

14:20-14:45

C10-3

C12: Clock and Frequency Generation

16:15-18:20

T15: Nanowire

14:20-14:45
A 9b, 1.12ps Resolution 2.5b/Stage Pipelined Timeto- Digital Converter in 65nm CMOS Using TimeRegister

Stanford
14:20-16:00 Univ

C11-1

JJFS2: SRAM

C10-1

Synthetic Electric Field Tunnel FETs: Drain Current
Multiplication Demonstrated by Wrapped Gate
Electrode Around Ultrathin Epitaxial Channel

16:40-17:05
Neural Network Based on a Three-Terminal

C12-3

17:05-17:30

T17-3

16:45-17:00

C13-3

17:05-17:30

JJ2-7

17:05-17:30

Broadcom

A 288fs RMS Jitter Versatile 8-12.4GHz WideBand Fractional-N Synthesizer for SONET and
SerDesRenesasElectronics

High-Voltage Complementary BEOL-FETs on Cu
Interconnects Using N-type IGZO and P-type SnO
Dual Oxide Semiconductor Channels

National
Chiao Tung
Univ.

A Pseudo-Noise Coded Constant-Off-Time (PNC-COT)
Control Switching Converter with Maximum 18.7 dBm PeakSpur Reduction and 92% Efficiency in 40 nm CMOS

National
Nano DeviceLabs.

A 10 nm Si-Based Bulk FinFETs 6T SRAM with
Performance of Threshold Switching in
Multiple Fin Heights Technology for 25% Better Static Samsung
Chalcogenide Glass for 3D Stackable Selector
Noise Margin

17:05-17:30

C12-4

17:30-17:55

C13-4

17:30-17:55

JJ2-8

17:30-17:55

T16-4

17:30-17:55

Univ. of
Minnesota

A 32nm, 0.9V Supply-Noise Sensitivity Tracking PLL for
Improved Clock Data Compensation Featuring a Deep
Trench Capacitor Based Loop Filter

Univ. of
FloridaA 10V Fully-Integrated Bidirectional SC Ladder
Converter in 0.13μm CMOS Using NestedBootstrapped Switch Cells

National
Tsing Hua
Univ.

A 210mV 7.3MHz 8T SRAM with Dual Data-Aware
Write-Assists and Negative Read Wordline for High
Cell- Stability, Speed and Area-Efficiency

LEAP

Bidirectional TaO-Diode-Selected, Complementary
Atom Switch (DCAS) for Area-Efficient, Nonvolatile
Crossbar Switch Block

C13-5

17:55-18:20

JJ2-9

17:55-18:20

Intel Corp.

A 0.45-1V Fully Integrated Reconfigurable Switched
Capacitor Step-Down DC-DC Converter with HighDensity MIM Capacitor in 22nm Tri-Gate CMOSIntel

A 22nm 2.5MB Slice On-Die L3 Cache for the
Next Generation Xeon® Processor

Circuits Rump Session 1

Circuits Rump Session 2

The Best Logic and Memory Interface Technology for 2D/2.5D/3D Ics

Analog Designer’s Play-Ground Beyond 20nm,
Is it Circuit Physics or Auto Place & Route?

2013 Symposia on VLSI Technology and Circuits
Suzaku ITime

Suzaku II

Circuits Registration

8:00-15:00

C14: Image Processing

8:30-10:10

C15: All Digital Phase-Locked Loops

C14-1

8:30-8:55

The Univ. ofManchester

A 100,000 fps Vision Sensor with Embedded
535GOPS/W 256x256 SIMD Processor Array

C15-1
Broadcom

C14-2

8:55-9:20

C15-2

KAIST

A 125,582 Vector/s Throughput and 95.1% Accuracy
Univ. ofANN Searching Processor with Neuro-Fuzzy Vision
TwenteCache for Real-Time Object Recognition

C14-3

9:20-9:45

Univ. of
ZurichA 240x180 10mW 12us Latency Sparse-Output
RambusVision Sensor for Mobile Applications

8:30-8:55
2

C15-3

An 8.5 mW, 0.07 mm ADPLL in 28 nm CMOS with
Sub-ps Resolution TDC and < 230 fs RMS Jitter

C16: Embedded Non-Volatile Memory
C16-1

8:30-8:55

Texas
Instruments

A MCU Platform with Embedded FRAM Achieving 350nA
Current Consumption in Real-Time Clock Mode with Full
State Retention and 6.5μs System Wakeup Time

8:55-9:20

8:55-9:20

C16-2

A 12GHz 210fs 6mW Digital PLL with Sub-Sampling
Binary Phase Detector and Voltage-Time Modulated
DCO

A 0.6V 8 pJ/write Non-Volatile CBRAM Macro
ADESTO
Embedded in a Body Sensor Node for Ultra Low
Technologies
Energy Applications

9:20-9:45

C16-3

9:20-9:45

A 25GHz 100ns Lock Time Digital LC PLL with
an 8-Phase Output ClockToshiba

A 38% Access Time Improvement in 40nm CMOS
Technology with Triple-Wire-Program-Cell Schemefor High Density MROM

C14-4

9:45-10:10

C15-4

9:45-10:10

C16-4

9:45-10:10

National
TaiwanUniv.

A 1062Mpixels/s 8192x4320p High Efficiency
Video Coding (H.265) Encoder Chip

IBM T. J.
WatsonResearch

A 28GHz Hybrid PLL in 32nm SOI CMOS

TSMC

A 28nm ROM with Two-Step Decoding Scheme andOD-Space-Effect Minimization to Achieve 30% Speedand 190mV Vmin Improvement

C17-1

10:30-10:55

C18-1

Princeton
Univ.

A Fully Self-Powered Hybrid System Based on
CMOS Ics and Large-Area Electronics for LargeScale Strain Monitoring

National Tsing An RF Energy Harvester with 35.7% PCE at PIN
KAIST
Hua Univ.
of –15 dBm

A 12Gb/s 0.92mW/Gb/s Forwarded Clock Receiver
Based on ILO with 60MHz Jitter Tracking Bandwidth
Variation Using Duty Cycle Adjuster in 65nm CMOS

C17-2

10:55-11:20

C18-2

Texas
Instruments

A ±0.4°C Accurate High-Speed Remote Junction
Delft Univ.
Temperature Sensor with Digital Beta Correction andof Tech.
Series-Resistance Cancellation in 65nm CMOS

C17: Sensors

C18: Power Management Techniques
10:30-10:55

C19: Clocking and Memory Interface
C19-1

10:30-10:55

10:55-11:20

C19-2

10:55-11:20

A Self-Calibrating RF Energy Harvester
Generating 1V at -26.3 dBm

FujitsuLabs.

An 8-to-16GHz 28nm CMOS Clock Distribution
Circuit Based on Mutual-Injection-Locked Ring
Oscillators

C17-3

11:20-11:45

C18-3

11:20-11:45

C19-3

11:20-11:45

KAIST

A 70dB SNR Capacitive Touch Screen Panel
Readout IC Using Capacitor-Less Trans-Impedance
Amplifier and Coded Orthogonal Frequency-Division
Multiple Sensing Scheme

Univ. of
Michigan

A Ripple Voltage Sensing MPPT Circuit for
Ultra-Low Power Microsystems

Samsung

A Sub-1.0V 20nm 5Gb/s/pin Post-LPDDR3 I/OInterface with Low Voltage-Swing Terminated Logic
and Adaptive Calibration Scheme for Mobile
Application

C17-4

11:45-12:10

C18-4

11:45-12:10

C19-4

11:45-12:10

KAIST

An Integrated Pulse Wave Velocity Sensor Using BioHanyang
Impedance and Noise-Shaped Body Channel
Univ.
Communication

A 6.0-W Bi-Directional DC-DC Converter for
Wireless Power Transceiver in 0.35-μm
BCDMOS

Samsung

A Heterogeneous Dual DLL and Quantization Error
Minimized ZQ Calibration for 30nm 1.2V 4Gb
3.2Gb/s/pin DDR4 SDRAM

C17-5

12:10-12:35

C18-5

12:10-12:35

C19-5

12:10-12:35

Columbia
Univ.

Integrated CMOS Quantitative Polymerase
Chain Reaction Lab-on-Chip

Texas
Instruments

A Stackable, 6-Cell, Li-Ion, Battery Management IC for
Electric Vehicles with 13, 12-bit ΣΔ ADCs, Cell Balancing,and Direct-Connect Current-Mode Communications

Rambus

10:30-12:35

C20: Medical Processing

C21: Nyquist Converters

A 400MHz - 1.6GHz Fast Lock, Jitter Filtering
ADDLL Based Burst Mode Memory Interface

C22: Wireline Transceivers

C20-1

13:55-14:20

C21-1

13:55-14:20

C22-1

National
Taiwan Univ.

A Self-Powered CMOS Reconfigurable MultiSensor SoC for Biomedical Applications

IBM
Research

A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power
Capacitive Reference Buffers in 32 nm Digital SOI
CMOS

Texas A&M A 10 Gb/s 2-IIR-Tap DFE Receiver with 35 dB
Univ.
Loss Compensation in 65-nm CMOS

C20-2

14:20-14:45

C21-2

14:20-14:45

C22-2

14:20-14:45

Princeton
Univ

A Low-Power Microprocessor for Data-Driven
Analysis of Analytically-Intractable PhysiologicalSignals in Advanced Medical Sensors

Broadcom

A 13-Bit 9GS/s RF DAC-Based Broadband
Transmitter in 28nm CMOS

Texas
A&M Univ.

A 6b 10GS/s TI-SAR ADC with Embedded 2Tap FFE/1- Tap DFE in 65nm CMOS

14:45-15:10

C21-3

14:45-15:10

C22-3

14:45-15:10

An 8.5mW 5GS/s 6b Flash ADC with Dynamic
Offset Calibration in 32nm CMOS SOIBroadcomp

A 2.8 mW/Gb/s Quad-Channel 8.5-11.4 Gb/s
Quasi-Digital Transceiver in 28 nm CMOS

C22-4

15:10-15:35

C20-3
13:55-16:00 National

Chiao Tung
Univ.

A 48.6-to-105.2μW Machine-Learning Assisted
Carnegie
Cardiac Sensor SoC for Mobile Healthcare Monitoring Mellon Univ.

13:55-14:20

C20-4

15:10-15:35

C21-4

15:10-15:35

National
Chung
Cheng Univ.

A 0.36V, 33.3μW 18-Band ANSI S1.11 1/3-Octave
Filter Bank for Digital Hearing Aids in 40nm CMOS

Keio Univ.

A 0.0058mm 2 7.0 ENOB 24MS/s 17fJ/conv.
OregonThreshold Configuring SAR ADC with Source Voltage
State Univ.
Shifting and Interpolation Technique

C20-5

15:35-16:00

C21-5

15:35-16:00

C22-5

15:35-16:00

National
Taiwan Univ.

A 401GFlops/W 16-Cores Signal Reconstruction
Platform with a 4G Entries/s Matrix Generation
Engine for Compressed Sensing and Sparse
Representation

imec

A 2.1 mW 11b 410 MS/s Dynamic Pipelined SAR
ADC with Background Calibration in 28nm Digital
CMOS

OregonState Univ.

A Fast Power-On 2.2Gb/s Burst-Mode Digital
CDR with Programmable Input Jitter Filtering

C23: Embedded Processing

16:15-17:55

June 14th (Friday)

Suzaku III

C24: Millimeter Wave Transceivers andC23-1

16:15-16:40

C24-1

ETH Zurich

A 1Gbps LTE-Advanced Turbo-Decoder ASIC in National
Taiwan Univ.
65nm CMOS

16:15-16:40
A Fully-Integrated 77GHz Phase-Array Radar Systemwith 1TX/4RX Frontend and Digital Beamforming
TechniqueC23-2

16:40-17:05

C24-2

16:40-17:05

WasedaUniv

A 1.59Gpixel/s Motion Estimation Processor with 211-to- 211 Search Range for UHDTV Video
EncoderHong Kong
Univ. of Sci.
&Tech.

A 4-Element 60-GHz CMOS Phased-Array Receiverwith Transformer-Based Hybrid-Mode Mixing andClosed- Loop Beam-Forming Calibration

C23-3

17:05-17:30

C24-3

17:05-17:30

NTT
Microsystem
IntegrationLabs.

A 96.5% Energy-Reduced Lookup Engine with an
Unused-Rules-Exception Scheme for Greening
Networks

Texas
Instruments

160GHz Pulsed Transmitter with Packaged
Antenna Array in 65nm CMOS

C23-4

17:30-17:55

C24-4

17:30-17:55

Univ. of
Michigan

Shortstop: An On-Chip Fast Supply Boosting
TechniqueUniv. of
California

A Low-Power 60-GHz CMOS Transceiver for
WiGig Applications

A 5Gb/s 2.6mW/Gb/s Reference-Less Half-Rate
PRPLL-Based Digital CDR

Shunju I

Shunju II