Minimum Neutral Clamp Capacitor Design
Considering Voltage Saturation
for a Three-Level Inverter
Jun-ichi Itoh1, Takaaki Tanaka1
1

Nagaoka University of Technology, 1603-1 Kamitomioka, Nagaoka, Niigata, Japan

Abstract—Neutral point clamped inverter has a voltage
fluctuation problem at the neutral point capacitor. This
paper discusses the minimum value of the neutral point
capacitor considers the voltage command saturation with
applying the voltage fluctuation suppression control method.
This paper clearly demonstrates the stable relationships
among the input voltage, output voltage and the capacitancevalue. In addition, the minimization design procedure ofcapacitance value basis on this analysis is demonstrated.
The validity of the design method is confirmed byexperimental results.
Index Terms— Minimum capacitance design, Three level
inverter, Vector control, Neutral point voltage fluctuation

I. INTRODUCTION
Neutral-point-clamped three-level inverters have been
actively studied recently because this converter shows anadvantage in reducing the output voltage harmoniccomponent [1]. Three-level inverters have been applied toadjustable speed drive systems such as, UPS and PV
inverter [2]. Three-level inverter shows several
advantages better than the two-level inverter; 1)
downsizing of the filter, 2) harmonic components areequivalent to the two-level inverters even the switchingfrequency has been reduced and 3) high output voltage
can be obtained with the use of low resistance voltage
switching devices.
However, neutral-point-clamped inverter connects twocapacitors in the DC link part to supply the neutral point
voltage. A known problem is that the voltage fluctuation
occurs at the neutral-point capacitor, which has afrequency three times higher than the output frequency,
depending on the load power factor or output voltage.
The voltage fluctuation causes poor performances such aslarge harmonic components in the power gridinterconnections and in the case of adjustable speed drive
applications, ripple occurs at the torque and speed.
Suppression control methods for the voltage
fluctuations have been proposed [3-5]. There are two
suppression control methods; the first method adds zero
phase voltage command to each phase voltage commandin the carrier comparison modulation [2-4]; the second
method utilizes two vectors of the same direction andamplitude which differs from the direction of the neutral
point current in space vector modulation [5].

However, these suppression methods are constrainedby two factors; the output voltage limitation of theinverter and the load power factor. Therefore, thecapacitance value is designed to large amplitude in orderto suppress the voltage fluctuation. Additionally, thisvoltage fluctuation greatly depends on the input andoutput conditions such as the modulation index, the load
power factor and the load current. The exceeded
capacitance value that is larger than the necessity
capacitance value increases the cost and also the volumeof the circuit. That is, the design of the minimum
capacitance value in corresponds to the input and output
condition should be studied and analyzed. This paper
discusses the design method for achieving the minimum
value of the neutral clamp capacitor in a three-level
inverter in order to obtain higher power density. The
behavior of the voltage fluctuation using a balance
control on the voltage command saturation has been
analyzed [3]. Furthermore, the minimum capacitancevalue is discussed at each operation point based on the
speed-torque curve (NT curve) of a PM motor with id = 0
control and flux-weakening control.
Firstly, the suppression method for the neutral point
voltage fluctuation is described in this paper. Next, thedesign procedure of the capacitance value with considers
upon the voltage command saturation is mentioned
according to load power factor. Thirdly, the procedure
designed based on the torque T and rotating speed N withconsiders to the switching ripple and dc-link fluctuationis shown. Finally, the validity of the design method is
confirmed by the simulation results and 1-kW experiment
prototype.
II. PROBLEM OF THREE-LEVEL INVERTERS
A. The configuration of the main circuit
Figure 1 shows the circuit configuration of a threelevel inverter. Two switches Q2x, Q3x (x = u or v or w)
and clamping diodes D1x, D2x are added to output zero
phase voltage. The output voltage consists of three-level;
Vin / 2, 0, -Vin / 2, low harmonic components in the output
waveform can be obtained.
Figure 2 shows the principle of the unipolar
modulation in a carrier based modulation. In thismodulation, the three values of a phase voltage vuo aredetermined by the magnitude relationship between theupper carrier, lower carrier, and phase voltage command.
If a phase voltage command is larger than upper carrier,vuo is determined +Vin / 2. If a phase voltage command issmaller than lower carrier, vuo is determined －Vin / 2.
The other is outputted zero voltage.
B. Suppression control of the neutral point voltage
fluctuation
Figure 3(a) shows each phase voltage commands areadded with the third harmonic for the improvement ofvoltage utilization ratio and the neutral point voltage vnp.
The simulation condition is following, modulation index
a=1.00, power factor of load cos=0.80, input
capacitance C=200 F. From Fig. 3(a), it is confirmedthat the neutral point voltage fluctuates at a frequency
that is three times higher than the output frequency. This
fluctuation is due to the flow of neutral point current inp to
the load. The neutral point current inp is calculated bymultiplying the duty of the neutral point current inp at per
switching period with the phase current. inp can be
expressed by

Fig. 1. Circuit configuration of the neutral-point-clamped threelevel inverter.

i np  D u 0  iu  D v 0  i v  D w 0  i w .................................. (1)where Du0, Dv0, Dw0 is the duty of each switches
connected to the neutral point and iu, iv, iw are phasecurrents.
In the unipolar modulation, the value of the phasevoltage at a switching period contains of two values
including the zero value from Fig. 2. Therefore, Du0, Dv0,
Dw0 are obtained by (2) assuming that the switchingfrequency is high and the neutral point current ripple isneglected due to its small value.
 Du 0  1  v u*  v 0***
 Dv 0  1  v v  v 0
 D w 0  1  v w*  v 0*...................................................... (2)where vu*, vv*, vw* are the phase voltage command andv0* is the zero phase voltage command.
The neutral point current inp is calculated bysubstituting (2) into (1). Then the current inp is obtained
by





Fig. 2. Unipolar modulation for the neutral-point-clamped threelevel inverter.









(a) Without suppression control.

inp  1  v*u  v*0  iu  1  v*v  v*0  iv  1  v*w  v*0  iw .. (3)The fluctuation of the neutral point voltage Δvnp issuppressed to add each phase voltage commands to v0* as
inp = 0 is solved by (3). Figure 3(b) shows a simulation
waveform of neutral point voltage vnp with the applicationof suppression control. The amplitude of the voltage
fluctuation is reduced from approximately 30V to 20V.
The remained fluctuations are resulted from where thevalue of the phase voltage commands added into v0*,
which it needs to be inp = 0, is higher than the limit of theinverter output voltage. Therefore, the capacitance values
are designed to be larger value due to the reason voltage
fluctuation cannot be suppressed completely at highmodulation index.

(b) With suppression control.
Fig. 3. The effect of voltage fluctuation suppression control(Upper: Each phase voltage command, Lower: Neutral point
voltage).

III. DESIGN METHOD TO OBTAIN MINIMUMCAPACITANCE VALUE
A. Relations between the capacitance value andoperation conditions
As discussed in previous section, the modulation index
or the power factor effects the voltage fluctuation. In thissection, the design method to obtain minimum
capacitance value is discussed when the suppression
control show at section II (B) is applied.
The neutral point voltage is calculated by integrating
the (3). Then the voltage vnp is obtained by
v np 

1
i np dt ............................................................... (4)Cwhere C is the value of one sided dc link capacitance.
Knowing the neutral point voltage vnp is fluctuating
periodically, the fluctuation band of the neutral point
voltage is calculated by integrating | inp | at finv / 6. Thenthe voltages fluctuation Δvnp is obtained by
Δv np synchronous motor with id=0 control and a fluxweakening control are considered in stable state.
1) PM motor with id=0 control:
Figure 5(a) shows a phasor vector diagram of a PM
motor with the applying of the control keeping d-axis
current id to zero. The relationship between (6) and theparameter of the motor can be expressed from (8) to (11)
a

2 2Vu
................................................................... (8),Vin  pN / 30 ................................................................. (9),iqT....................................................... (10),
Iu 

3
3 p
cos  ea  RI aea  RI a 2  LI a 2.................................... (11),where Vu is the phase voltage, p is the pairs of the poles,

1 1 / 6 finv
inp dt ..................................................... (5)C 0However, it is difficult to solve by the algebra
calculation because the integration part in (5) is a nonliner function due to the absolute functions. Then, adimensionless coefficient is introduced to (5). As a result,the voltage function is expressed by
Δvnp 

2 I uv  / 6
2 I uv
inp / 2 I uv d k ( a,cos ) ................ (6)2Cω 02Cω

where Iuv is the line current,  is the angular output
frequency,  is the output phase angle, and k(a, cos) is thedefined the charge coefficient.
Figure 4 shows relationship among the chargecoefficient k(a, cos), the modulation index a and the load
power factor cos. The modulation index is defined by
23/2 × maximum phase voltage / dc link voltage. This
figure is obtained by calculating the integration part in (6).
In conclusion, the admittances of the neutral point
capacitance Cp and Cn are obtained by (7) fromnormalizing (6) using Table1.
Y pu 

I uv_pu
2 Δv np_pu

k(a,cos) ...................................................... (7)The admittance Ypu which can keep lower than thedesired Δvnp at static state is obtained by substituting k(a,cos) into (7).
For instance, under an operation condition where theneutral point voltage is lower than 10% of the input
voltage, the load power factor = 0.9, and the modulationindex a = 1.1. From the calculation, the admittance Ypu is
61.3% (=313F@ 10kW, 200Vrms, 50Hz ).
B. Design method according to operation points ofmotor
In section III (A), the design of the capacitance value
which is calculated from a, cos, Iu, Δvnp was shown. In
this section, the design procedure of the capacitance value
from torque T, the motor speed N and Δvnp will be
discussed. In addition, a surface permanent magnet

Fig. 4. Charge coefficient k(a, cos) in (4) : Relation between
charge coefficient and power factor of load and modulation index.
Table 1: Definition of normalized value for Fig. 2.

Normalizedvalue
Δvnp pu
Vuv puIuv puYpu

Standard valueVinLine voltage rating: Vuv n [Vrms]
Line current rating: Iuv n [Arms]
Iuv n / Vuv n
q

LIa
Va

RIa
ea

LIa

RIa

Va

ea

・

Ia

・

Ia

d

(b) flux-weakening control(a) id = 0 control
Fig.5. Phasor vector of PM motor.

 is the main flux, iq is the q axis current, ea is the speed
electromotive force, R is the armature resistance, and L isthe armature self-inductance.
The speed electromotive force ea is expressed byea   .................................................................... (12).

By substituting (9), (10) and (12) into (11), the power
factor of the load is expressed by.
pN
30

cos  RTp....................... (13).

2

 pN
RT   NLT  30   p    30 


 

2

2

2

...................... (14).

By substituting (14) into (8), the relationship between themodulation index and the motor parameter is obtained by
2
a
Vin

2

2

 pN
RT   NLT  ................... (15).

 


30
   30 
p


2
3

2) PM motor with flux-weakening control:
Figure 5(b) shows a phasor vector diagram for the PM
motor with the applying of flux-weakening control. The
d-axis current is defined by max Vom  2  
  Ld i q.............................. (16),



id 
Ld
2





where max[Vom] is the line to line voltage in case of R <<1.
The relationship between the phase current Iu in (6)and the motor parameter is expressed by
∴

Ia

Iu 

3

2

id  iq2

................................................ (17).

3The complex power Pc is obtained by

2
2 ........................ (18).
Pc  Va Ia  ea iq  RI a  j ea id  LI a

The effective power P is the real part in (18). The power
P is expressed byP  ea iq  RI a2............................................................ (19).

The power factor of load cos is leaded from (18) and(19). The factor is obtained bycos  PP
cea iq  RI a2

e i  RI   e i  LI 
2 2

a q

a

.............. (20).

2 2

a d

a

By substituting (10), (12) (16) and (17) into (20), the load
power factor is known.
Then the phase voltage Vu is obtained by
Vu 

Pc
3 Ia



1
3

2

2

2

  i

2  iq RI a   ea d  LI a  ............. (22).
ea
3  Ia  Ia

C. Design method including switching ripple
The definition of Δvnp shown in the previous section
did not consider the switching ripple. In this section, thephenomenon are considered into the design ofcapacitance.
The maximum value of switching ripple is defined by 2Cf2 I .................................................. (23),
u

sw

 pN
RT   NLT 

 


p   30 
3  301

2
Vin

max v np _ sw 

Then the phase voltage Vu is obtained by
Vu 

a

2

 iq
  i
 ... (21).
 RI a   ea d  LI a 
ea
I
I
a
a

 


By substituting (21) into (8), the relationship between themodulation index and motor parameter is obtained bywhere fsw is the switching frequency of the inverter.
The fluctuation of the neutral point voltage with being
considered on the switching ripple and the input voltage
fluctuation is defined byvnp  vnp  maxvnp _ sw '........................................... (24)

Finally, the capacitance value is obtained byC

2 I u k ( a ,cos  )  .................................. (25)
1  2Iu'2v np  2 f inv


D. Example on the design of obtaining minimum
capacitance
The power supply interface system using the motor
drive of electrical vehicle is supposed. In this system, theinput voltage of three-level inverter Vin is the output
voltage of DC to DC converter. Hence, The ACcomponent of Vin is supposed zero amplitude.
Figure 6 shows the speed-torque curve (NT curve) of
the PM motor when the minimum capacitance conditions
are considered. Point A shows the starting operation (lowspeed high torque). Point B is the high speed light loadcondition. Then, point C delivers the maximum speed andtorque with id = 0 control. Lastly, point D shows the
maximum speed and torque with the application of fluxweakening control.
The capacitance value is designed at the point of
maximum Δvnp. Hence, the T and N of this point are
shown. Δvnp increases with falling frequency andincreasing current as evidenced by (6). So, the maximum
Δvnp should be the point A as low speed high torque,point B or D as high d axis current or point C as hightorque.
According to above-mentioned, minimum capacitancevalue is designed under the following conditions: themotor parameter as Table2, Vin = 240V, fsw = 10kHz, Δvnp
< 5%. Δvnp at point A, B, C and D are calculated by (6).
The modulation index a and power factor of the load cosare set for each point; (a=0.19, cos=0.96, Iu=11.3A) @A, (a=1.00, cos=0.14, Iu=15.3A) @ B, (a=1.00,
cos=0.954, Iu=11.3A) @ C, (a=1.00, cos=0.67,
Iu=17.7A) @ D by (13) and (15). Therefore, thecapacitance value should be determined at point B. In
conclusion, capacitance value is designed 133F by (25)and Fig. 4.
Figure 7 shows the components of neutral point

voltage fluctuation each operation point in case ofdesigning capacitance value = 133F. Each stacked bar
chart is constructed from neutral point voltage fluctuation
at three times higher than output frequency Δvnp andmaximum value of switching ripple Δvnp_sw. The
switching ripple Δvnp_sw is larger than Δvnp as result of
enough suppressing Δvnp by applying suppression control.
And, the maximum value of Δvnp_sw. is 9.38 V at the point
D. However, the total voltage fluctuation of neutral point
Δvnp’ has maximum value at the point B as the worst
value of the load power factor.

1

0.6

V. EXPERIMENTAL RESULTA 1-kW load prototype was tested and verified thedesign method. The experimental conditions are follows,
input voltage Vin is 200 V, output frequency finv is 50 Hz,
switching frequency fsw is 10 kHz, DC link capacitance C
is 100 F.
Figure 10 shows two results to demonstrate theid = 0 control Flux weakening
controlCmode 2mode 1Dmode 3mode 4B

0.1
0.1

IV. SIMULATION RESULTS

0.54
Speed N [p.u.]

1

Fig.6. Speed torque curve for capacitor design.

vnp [V]

Table 2. PM motor parameters for design example.
3.0 kW
Rating output Pr
Rating speed Nr
12000 rpm
Armature resistance R
63.5 mArmature Self-inductance L
556 H
Back-emf coefficient
34.2 mV･s/rad
Armature pairs of poles p
6
Moment of inertia
0.174 N･m/A
Rating Torque Tr
4.0 N･mRating armature current
21 Arms

Fig.7. Design value of neutral point voltage fluctuationeach operation point.

vnp [V]The neutral point voltage fluctuation in cause ofchanging torque and speed is considered by simulation.
The simulation condition follow section III (D). Figure 8
shows the value of neutral point voltage fluctuation
operated the motor in each operating mode in Fig. 6. By
Fig.8, the values are suppressed within design value.
Figure 9 show simulation waveforms in case oftransition of mode 1, 2, 3 and 4 in Fig. 6. Eachwaveforms are the mechanical angular frequency m, thed axis current id, the q axis current iq and the neutral point
voltage vnp.
Figure 9(a) shows simulation results of operating the
motor at mode 1 in Fig. 6. The load torque is changed
from 0 to 4 N・m. The maximum value of neutral point
voltage max[Δvnp’] is 1.88 V. This value is within design
value. The voltage fluctuation three times higher than
output frequency is suppressed enough.
Similarly, Figure 9(b) shows result of operating the
motor at mode 2 in Fig. 6. The maximum value of neutral
point voltage max[Δvnp’] is 3.89 V. This value is also
within design value.
Figure 9(c) shows result of operating the motor atmode 3. The maximum value of neutral point voltage
max[Δvnp’] is 11.9 V. This value is within design value.
Δvnp is not suppressed due to power factor deterioration
depending on increasing d-axis current by the fluxweakening control. At 100 ms, The transitional
fluctuation is caused. After now, this phenomenon isconsidered to the design method.
Then, Figure 9(d) shows result of operating the motor
at mode 4. The load torque is changed from 0 to 0.9 N・
m. The maximum value of neutral point voltage
max[Δvnp’] is 9.11 V. This value is within design value.
Δvnp is not suppressed due to power factor deterioration
depending on increasing d-axis current by the fluxweakening control.

A

Fig.8. Simulation result of the value of neutral point fluctuationeach operation mode

validity of the suppression control method. Figure 10(a)shows the results without the suppression control, neutral
point voltage vnp, u phase voltage vu, and u phase current
iu. Note that the waveforms of vu and iu are applied withm

0 rad/s

250(rad/s) / divm250(rad/s) / div

0 rad/siq

20 A/div

iq
0A

20 A/div

0A

id

id
T

T

1 (N・m) / div

1 (N・m) / div
0 N・m
0 N・m

vnp

vnp

5 V/div

5 V/div

vnp

120 V

120 V

vnp
0 ms

50 ms

100 ms(a) mode 1

150 msm

200 ms0 ms

250(rad/s) / divm

0 rad/s

50 ms

100 ms(b) mode 2

150 ms200 ms250(rad/s) / div

0 rad/s

iq

iq

20 A/div

20 A/div

0A

0A

id

id
1 (N・m) / divTT

1 (N・m) / div

0 N・m

5 V/div

vnp

0 N・m

vnp

vnp

5 V/div

120 V
120 V

vnp
0 ms

50 ms

100 ms(c) mode 3

150 ms200 ms

0 ms

50 ms

100 ms(d) mode 4

150 ms200 msFig.9. Simulation waveforms changing torque or speed.

low pass filter of cutoff frequency 1 kHz. Figure 10(b)shows experimental results with the suppression control
method. Knowing from the vnp, it is confirmed that the
suppression control successfully reduced the voltage

fluctuation from 30V to 6V.
The design method is also evaluated in term ofexperiment by using the same prototype. The capacitancevalue can be designed by substituting the band of neutralpoint voltage Δvnp into (7). However, here, equation (7)is evaluated by the voltage fluctuation instead of thecapacitance value.
Figure 11 shows the two waveforms for the neutral
point voltage vnp, u-v line voltage vuv when themodulation index a is1.0 and the load power factor cos
is 0.855. Low pass filter is applied to each waveform.
Figures 11(a) and 11(b) show the simulation waveforms
and experimental waveforms, respectively. In theexperimental, the neutral point voltage vnp consists ofripple due to the error on current detection and dead time
period. Δvnp in Fig.11 (a) and (b) demonstrate that theneutral point voltage is fluctuating at a frequency threetimes than the output frequency finv.
Figure 12 shows the relationships between the voltage
fluctuation of the neutral point voltage and the load
power factor cos. The modulation index a is kept 1.0,
and only the load inductance is varied. This operation
correspond the acceleration with the flux-weakening
control such as mode 3 in Fig. 6. The solid line is thecalculated result. The circle mark and triangle mark are
the simulation results and experimental results,
respectively. The calculated results and the simulation
results show an approximately equal. On the other hands,
an error rate of 11.9% is between the calculation and theexperimental result at cos= 0.797. however, theexperimental result is suppressed under calculation result.
The error is because of the influence of the dead time.
Similarly, Figure 13 shows the relationship between
the voltage fluctuation of the neutral point voltage and themodulation index a. This operation correspond theacceleration with the id = 0 control such as mode 2 in Fig.
6. The load power factor cos is kept 0.85. The results
between the calculation and experiment have two kindsof errors. One is happening at the range of modulationindex exceeds 1.0, the experimental results are varied
from the calculation results due to the same reason. The
other is the range of modulation index under 0.95. Error
ratio between the calculation and experimental result is
30% at a = 1.05. That is, experimental result is more thancalculation result.
To examine this cause, Figure 14 shows theexperimental waveforms at modulation index = 0.8. The
output current of the inverter shows a distortion. The
average of the neutral point voltage is designed to output
at 100V. However, the experimental result shows only
75V. The reason is which the algorism of the suppression
control does not feedback the detection value of neutral
point voltage. Therefore, the imbalance of two input
capacitance voltage cannot be compensated. The
imbalance would be solved by applying the balancemethod using the detection value of the neutral point
voltage [7].
VI. CONCLUSIONSIn this paper, the design method of the capacitancewith considering on the voltage saturation was discussed.

(a) Without suppression control(b) With suppression control
Fig.10. Result of suppression control.(a :1.0, cos: 0.847).

vnp(2V/div)

vnp

100

20msec/div

vuv(100V/div)0(a) Simulation waveforms
vnp (5V/div)100

vnp = 6.0V
vuv (250V/div)0(b) Experimental waveforms
Fig.11.

The waveforms of neutral point voltage and output

voltage when the modulation index a is 1.0 and Power factor cos
is 0.855.

This paper proposed to is shown for minimize the volume
of circuit by minimizing the capacitance value of a threelevel inverter and obtain a high power density results.
The capacitance values are confirmed can be minimized,
which consists of the modulation index, the load power
factor, and the output frequency. The voltage fluctuationfrom the analysis results agreed with that of theexperimental results, which was tested on a 1-kW
prototype circuit. In future work, the design on thecapacitance including the transient states will beconsidered.
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Fig. 12.

Relationship between power factor and the voltage

fluctuation of neutral point with simulation results.

Fig. 13. Relationship between modulation factor and thevoltage fluctuation of neutral point with simulation results.

Fig.14. Simulation result (Modulation index a : 0.8，Powerfactor cos: 0.847).