Product Specification
Part Name: OLED (or OEL) Display Module
Customer Part ID:
Allvision Part ID: OD104
Ver: D
Customer:Approved byApproved byNotes:
1. Please contact us before assigning your product based on this module specification
2. The information contained herein is presented merely to indicate the characteristics and performance ofour products. No responsibility is assumed by us for any intellectual property claims
or other problems that may result from application based on the module described herein.

Part Number : OD104

Ver:D

Revised History
Part Number

Revision

OD104

A
B
C
D

Revision Content
New
RIREF=390K 变更为 RIREF=910K
亮度寄存器（0X81）参数 0XCF 变更为 0X66
亮度寄存器（0X81）参数 0X66 变更为 0XCF
寄存器（0xD9）的参数 0x1F 变更为 0xF1
更改亮度值Revised on
20130225
20130522
20130529
20150112

Page 1 of 38iPart Number : OD104

Ver:D

Contents
Revision History ................................................................................................................................i
Contents ..................................................................................................................................... ii~iii
1. Basic Specifications
1.1 Display Specifications
1.2 Mechanical Specifications
1.3 Active Area / Memory Mapping & Pixel Construction
1.4 Mechanical Drawing
1.5 Pin Definition
1.6 Block Diagram
1.6.1 VCC Supplied Externally1.6.2 VCC Generated by Internal DC/DC Circuit
2. Absolute Maximum Ratings
3. Optics & Electrical Characteristics
3.1 Optics Characteristics
3.2 DC Characteristics
3.3 AC Characteristics
3.3.1 68XX-Series MPU Parallel Interface Characteristics
3.3.2 80XX-Series MPU Parallel Interface Characteristics
3.3.3 Serial Interface Characteristics (4-wire SPI)
3.3.4 Serial Interface Characteristics (3-wire SPI)
3.3.5 I2C Interface Characteristics

4. Functional Specification
4.1 Commands
4.2 Power down and Power up Sequence
4.2.1 Power up Sequence
4.2.2 Power down Sequence
4.3 Reset Circuit
4.4 Actual Application Example
4.4.1 VCC Supplied Externally
4.4.2 VCC Generated by Internal DC/DC Circuit

5. Reliability
5.1 Contents of Reliability Tests
5.2 Failure Check Standard

6. Outgoing Quality Control Specifications
6.1 Environment Required
6.2 Sampling Plan
6.3 Criteria & Acceptable Quality Level
6.3.1 Cosmetic Check (Display Off) in Non-Active Area
6.3.2 Cosmetic Check (Display Off) in Active Area
6.3.3 Pattern Check (Display On) in Active Area

7. Package Specifications
8. Precautions When Using These OEL Display Modules
8.1 Handling Precautions
8.2 Storage Precautions
8.3 Designing Precautions
8.4 Precautions when disposing of the OEL display modules
8.5 Other Precautions

Page 2 of 38iiVer:DPart Number : OD104

1. Basic Specifications
1.1 Display Specifications
1)
2)
3)

Display Mode:
Display Color:
Drive Duty:

Passive Matrix
Monochrome (Blue)
1/64 Duty

1.2 Mechanical Specifications
1)
2)
3)
4)
5)
6)
7)

Outline Drawing:
Number of Pixels:
Panel Size:
Active Area:
Pixel Pitch:
Pixel Size:
Weight:According to the annexed outline drawing
128  64
26.70  19.26  1.4 (mm)21.744  10.864 (mm)0.17  0.17 (mm)0.154  0.154 (mm)1.54 (g)

1.3 Active Area / Memory Mapping & Pixel Construction

P0.17x128-0.016=21.744
"A"

0.17
0.154

P0.17x64-0.016=10.864

0.17
0.154

Segment 127( Column 1 )Common 0

Segment 0( Column 128 )Common 1( Row 63 )( Row 64 )Common 62

Common 63( Row 1 )Detail "A"
Scale (10:1)( Row 2 )Page 3 of 38

30

5

R/W#

D/C#

6
Customer Approval
Signature1.4± 0.1
0.7

D6

D4

D5

D7

D2

D0

E

D1

D3

RES#

BS2

CS#

VSS

BS0

VDD

BS1

C1P

VBAT

NC

C1N

11
12.0± 0.3

4.75mm
Tolerance
Dimension ± 0.3
Angle
±1

General Roughness

By
Date

Title

( Row 1 )Common 62

0.17
0.154

Drawn
HONG
20130306

E.E.

Segment 0

Panel / E.

B

P.M.

( Row 2 )Common 63( Row 64 )Common 1( Column 128 )Detail "A"
Scale (10:1)

Part No: OD104

P0.17x64-0.016=10.864

Unit

Unless Otherwise Specified

0.1± 0.03

Common 0( Column 1 )( Row 63 )Date
20130306

P0.17x128-0.016=21.744

Segment 127

"A"

0.154
0.17

C2P

C2N

1. Color: Blue
2. Driver IC: SSD1306
3. FPC Number: QUT1306P01 B
4. Interface:
8-bit 68XX/80XX Parallel, 3-/4-wire SPI, I2 C
5. General Tolerance: ± 0.30

Notes:

12

Active Area 0.96"
128 x 64 Pixels

VCDMH

16.0± 0.1
P0.70x(30-1)=20.3± 0.05 (W0.40± 0.03)
0.85± 0.1
22± 0.2

1

NC

10

VSS

26.7± 0.2 (Panel Size)
26.7± 0.2 (Cap Size)
25.7± 0.2 (Polarizer)
23.744 (V/A)
21.744 (A/A)

IREF

Remove Tapet=0.15mm Max
Polarizer
t=0.2mm0.5± 0.5(1.478)(2.478)VCC(31.26)
3M #1318B
15x8x0.063mm

10.864 (A/A)
12.864 (V/A)
14.4± 0.2 (Polarizer)
14.9± 0.2 (Cap Size)
19.26± 0.2 (Panel Size)
NC

2-R0.4± 0.05
Contact Side

(2.1)
(1.1)
Glue

Material

Drawing Number

SymbolN.C. (GND)
C2P
C2N
C1P
C1N
VBAT
N.C.
VSS
VDD
BS0
BS1
BS2
CS#
RES#
D/C#
R/W#
E/RD#
D0
D1
D2
D3
D4
D5
D6
D7
IREF
VCOMH
VCC
VLSS
N.C. (GND)

Rev.
A

Scale
1:1

Sheet
1 of 1

Size
A3

Soda Lime / Polyimide

Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

RemarkOriginal Drawing

1.4

Contact Side

Item
A

Part Number : OD104
Ver:D

Mechanical Drawing

Page 4 of 38

Part Number : OD104
1.5

Ver:D

Pin Definition

Pin Number

SymbolI/O

Function

9

VDD

P

8

VSS

P

28

VCC

P

29

VLSS

P

Power Supply for Logic
This is a voltage supply pin. It must be connected to external source.
Ground of Logic Circuit
This is a ground pin. It acts as a reference for the logic pins. It must beconnected to external ground.
Power Supply for OEL Panel
This is the most positive voltage supply pin of the chip. A stabilization capacitor
should be connected between this pin and VSS when the converter is used. It
must be connected to external source when the converter is not used.
Ground of Analog Circuit
This is an analog ground pin. It should be connected to VSS externally.

26

IREF

I

27

VCOMH

O

Power Supply

DriverCurrent Reference for Brightness Adjustment
This pin is segment current reference pin. A resistor should be connected
between this pin and VSS. Set the current at 12.5A maximum.
Voltage Output High Level for COM Signal
This pin is the input pin for the voltage output high level for COM signals. A
capacitor should be connected between this pin and VSS.

DC/DC Converter
6

VBAT

P

4/5
2/3

C1P / C1N
C2P / C2N

I

Power Supply for DC/DC Converter Circuit
This is the power supply pin for the internal buffer of the DC/DC voltage converter.
It must be connected to external source when the converter is used. It should beconnected to VDD when the converter is not used.
P o s i t i v e T e r m i n a l o f t h e F l y i n g I n v e r ti n g C a p a c i t o r
Negative Terminal of the Flying Boost Capacitor
The charge-pump capacitors are required between the terminals. They must be
floated when the converter is not used.

Interface
10
11
12

BS0
BS1
BS2

I

14

RES#

I

13

CS#

I

15

D/C#

I

17

E/RD#

I

Communicating Protocol Select
These pins are MCU interface selection input. See the following table:
BS0
BS1
BS2
I2C
0
1
0
3-wire SPI
100
4-wire SPI000
8-bit 68XX Parallel001
8-bit 80XX Parallel0
1
1Power Reset for Controller and DriverThis pin is reset signal input. When the pin is low, initialization of the chip is
executed. Keep this pin pull high during normal operation.
Chip SelectThis pin is the chip select input. The chip is enabled for MCU communication only
when CS# is pulled low.
Data/Command Control
This pin is Data/Command control pin. When the pin is pulled high, the input at
D7~D0 is treated as display data. When the pin is pulled low, the input at D7~D0
will be transferred to the command register.
When the pin is pulled high and serial interface mode is selected, the data at SDIN
will be interpreted as data. When it is pulled low, the data at SDIN will betransferred to the command register. In I2C mode, this pin acts as SA0 for slave
address selection.
For detail relationship to MCU interface signals, please refer to the Timing
Characteristics Diagrams.
Read/Write Enable or Read
This pin is MCU interface input.
When interfacing to a 68XX-series
microprocessor, this pin will be used as the Enable (E) signal. Read/write operation
is initiated when this pin is pulled high and the CS# is pulled low.
When connecting to an 80XX-microprocessor, this pin receives the Read (RD#)
signal. Data read operation is initiated when this pin is pulled low and CS# ispulled low.
When serial or I2C mode is selected, this pin must be connected to VSS.

Page 5 of 38

Part Number : OD104

Ver:D

1.5 Pin Definition (Continued)
Pin Number

SymbolI/O

FunctionInterface (Continued)

16

R/W#

I

18~25

D0~D7

I/O

7

N.C.

-

1, 30

N.C. (GND)-

Read/Write Select or Write
This pin is MCU interface input.
When interfacing to a 68XX-series
microprocessor, this pin will be used as Read/Write (R/W#) selection input. Pull
this pin to “High” for read mode and pull it to “Low” for write mode.
When 80XX interface mode is selected, this pin will be the Write (WR#) input.
Data write operation is initiated when this pin is pulled low and the CS# is pulledlow.
When serial or I2C mode is selected, this pin must be connected to VSS.
Host Data Input/Output Bus
These pins are 8-bit bi-directional data bus to be connected to themicroprocessor’s data bus. When serial mode is selected, D1 will be the serial
data input SDIN and D0 will be the serial clock input SCLK. When I2C mode isselected, D2 & D1 should be tired together and serve as SDAout & SDAin in
application and D0 is the serial clock input SCL.
Unused pins must be connected to VSS except for D2 in serial mode.

Reserve
Reserved Pin
The N.C. pin between function pins are reserved for compatible and flexible
design.
Reserved Pin (Supporting Pin)
The supporting pins can reduce the influences from stresses on the function pins.
These pins must be connected to external ground as the ESD protection circuit.

Page 6 of 38

Part Number : OD104

Ver:D

1.6 Block Diagram
1.6.1 VCC Supplied Externally~

Common 31~ ~ ~Common 0

Segment 0

Segment 127~

Common 32

Common 63

Active Area 0.96"
128 x 64 Pixels

VLSS

D7

~

IREF
VCOMH
VCC

D0

VDD
BS0
BS1
BS2
CS#
RES#
D/C#
R/W#
E/RD#

C2P
C2N
C1P
C1N
VDDB
VSS

SSD1306

C5
C1
C2

R1
C3
C4

MCU Interface Selection:
BS0, BS1 and BS2
Pins connected to MCU interface: CS#, RES#, D/C#, R/W#, E/RD#, and D0~D7
C1, C3: 0.1μF
C2:
4.7μF
C4, C5: 4.7μF / 16V X7R
R1:
910kΩ, R1 = (Voltage at IREF - VSS) / IREF

Page 7 of 38

Part Number : OD104

Ver:D

1.6.2 VCC Generated by Internal DC/DC Circuit~

Common 31~ ~ ~Common 0

Segment 0

Segment 127~

Common 32

Common 63

Active Area 0.96"
128 x 64 Pixels

C6

C5

C2

C1

VLSS

IREF
VCOMH
VCC

~

D7

D0

VDD
BS0
BS1
BS2
CS#
RES#
D/C#
R/W#
E/RD#

VSS

C2P

C2N
C1P

C1N
VDDB

SSD1306

C3
C4R1

MCU Interface Selection:
BS0, BS1 and BS2
Pins connected to MCU interface: CS#, RES#, D/C#, R/W#, E/RD#, and D0~D7
C1, C2: 1μF
C3:
2.2μF
C4:
4.7μF / 16V X7R
C5, C6: 1μF / 16V X5R
R1:
910kΩ, R1 = (Voltage at IREF - VSS) / IREF

Page 8 of 38

Part Number : OD104

Ver:D

2. Absolute Maximum Ratings
Parameter

Symbol

Min

Max

Unit

Notes

Supply Voltage for Logic

VDD

-0.3

4

V

1, 2

Supply Voltage for Display

VCC

0

16

V

1, 2

Supply Voltage for DC/DC

VBAT

-0.3

5

V

1, 2

Operating Temperature

TOP

-40

85

C

Storage Temperature

TSTG

-40

85

C

3

2

Life Time (120 cd/m )10,000-hour

4Life Time (80 cd/m2)

30,000

-

hour

4

2

50,000-hour

4Life Time (60 cd/m )Note 1: All the above voltages are on the basis of “VSS = 0V”.
Note 2: When this module is used beyond the above absolute maximum ratings, permanent breakage of themodule may occur. Also, for normal operations, it is desirable to use this module under theconditions according to Section 3. “Optics & Electrical Characteristics”. If this module is usedbeyond these conditions, malfunctioning of the module can occur and the reliability of the module
may deteriorate.
Note 3: The defined temperature ranges do not include the polarizer.
The maximum withstoodtemperature of the polarizer should be 80C.
Note 4: VCC = 12.0V, Ta = 25°C, 50% Checkerboard.
Software configuration follows Section 4.4 Initialization.
End of lifetime is specified as 50% of initial brightness reached. The average operating lifetime atroom temperature is estimated by the accelerated operation at high temperature conditions.

Page 9 of 38

Part Number : OD104

Ver:D

3. Optics & Electrical Characteristics
3.1 Optics Characteristics
Characteristics

SymbolConditions

Min

Typ

Max

Unit

Brightness(VCC Supplied Externally)

Lbr

Note 5

100

-

-

cd/m2

Lbr

Note 6

80

100

-

cd/m2

C.I.E. (Blue)

(x)
(y)

C.I.E. 1931

0.12
0.22

0.16
0.26

0.20
0.30

Dark Room ContrastCR-

2000:1

-

-

Free

-

degree

Min

Typ

Max

Unit

1.65

2.8

3.3

V

8.5

9.0

9.5

V

-

4.2

V

Brightness(VCC Generated by Internal DC/DC)

Viewing Angle* Optical measurement taken at VDD = 2.8V, VCC = 12V & 7.25V.
Software configuration follows Section 4.4 Initialization.
3.2 DC Characteristics
Characteristics

SymbolSupply Voltage for Logic

VDD

Supply Voltage for Display(Supplied Externally)

VCC

Supply Voltage for DC/DC
Supply Voltage for Display(Generated by Internal DC/DC)

VBAT

Conditions
Note 5(Internal DC/DC Disable)

High Level Input

VIH

Internal DC/DC Enable
3.5
Note 6
7.0(Internal DC/DC Enable)
IOUT = 100μA, 3.3MHz 0.8VDD

Low Level Input

VIL

IOUT = 100μA, 3.3MHzHigh Level Output

VOH

IOUT = 100μA, 3.3MHz 0.9VDD

-

VDD

V

Low Level Output

VOL

IOUT = 100μA, 3.3MHz0-

0.1VDDV

Operating Current for VDD

IDD

-

180

300

μA

Operating Current for VCC(VCC Supplied Externally)

ICC

Note 7

-

9

15

mA

Operating Current for VBAT(VCC Generated by Internal DC/DC)

IBAT

Note 8

-

25.6

32.0

mA

Sleep Mode Current for VDD

IDD, SLEEP

-

1

5

μA

Sleep Mode Current for VCC

ICC, SLEEP

-

2

10

μA

VCC

0

-

7.5

V

-

VDD

V

-

0.2VDD

V

Note 5 & 6: Brightness (Lbr) and Supply Voltage for Display (VCC) are subject to the change of the panel
characteristics and the customer’s request.
Note 7:
VDD = 2.8V, VCC = 12V, 100% Display Area Turn on.

Note 8:VDD = 2.8V, VCC = 7.25V, 100% Display Area Turn on.

* Software configuration follows Section 4.4 Initialization.

Page 10 of 38

Part Number : OD104

Ver:D

3.3 AC Characteristics
3.3.1.1 68XX-Series MPU Parallel Interface Timing Characteristics:
SymbolDescription

Min

Max

Unit

tcycleClock Cycle Time

300

-

ns

tAS

Address Setup Time

5

-

ns

tAH

Address Hold Time

0

-

ns

tDSW

Write Data Setup Time

40

-

ns

tDHW

Write Data Hold Time

7

-

ns

tDHR

Read Data Hold Time

20

-

ns

tOH

Output Disable Time

-

70

ns

tACC

Access Time

-

140

ns

Chip Select Low Pulse Width (Read)

120

Chip Select Low Pulse width (Write)

60

-

ns

Chip Select High Pulse Width (Read)

60

Chip Select High Pulse Width (Write)

60

-

ns

tR

Rise Time

-

40

ns

tF

Fall Time

-

40

ns

PWCSL
PWCSH

* (VDD - VSS = 1.65V to 3.3V, Ta = 25°C)

Page 11 of 38

Part Number : OD104

Ver:D

3.3.1.2 68XX-Series MPU Parallel Interface with Internal Charge Pump

68xx parallel interface
Vin
R2
D

C2
Q1

G
Q2

G
GPIO

S

C1

D

S
R3

C6

C5

CS#
RES#
D/C#
R/W#
E
D[7:0]

R1
C4
C3

N.C. (GND)
C2P
C2N
C1P
C1N
VBAT
N.C.
VSS
VDD
BS0
BS1
BS2
CS#
RES#
D/C#
R/W#
E/RD#
D0
D1
D2
D3
D4
D5
D6
D7
IREF
VCOMH
VCC
VLSS
N.C. (GND)

UT-0206-P05

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

GND

Recommended Components:
C1, C2:1μF / 16V, X5R
C3:
2.2μF
C4:
4.7μF / 16V, X7R
C5, C6:1μF
R1:910kΩ, R1 = (Voltage at IREF - VSS) / IREF
R2, R3:47kΩ
Q1:
FDN338P
Q2:
FDN335N
Notes:
VDD:
1.65~3.3V, it should be equal to MPU I/O voltage.
Vin:
3.5~4.2V* VBAT will be connected to VDD when VCC be connected to external source (12V), R1 should be
replaced as 910 kΩ.

Page 12 of 38

Part Number : OD104

Ver:D

3.3.2.1 80XX-Series MPU Parallel Interface Timing Characteristics:
SymbolDescription

Min

Max

Unit

tcycleClock Cycle Time

300

-

ns

tAS

Address Setup Time

10

-

ns

tAH

Address Hold Time

0

-

ns

tDSW

Write Data Setup Time

40

-

ns

tDHW

Write Data Hold Time

7

-

ns

tDHR

Read Data Hold Time

20

-

ns

tOH

Output Disable Time

-

70

ns

tACC

Access Time

-

140

ns

tPWLR

Read Low Time

120

-

ns

tPWLW

Write Low Time

60

-

ns

tPWHR

Read High Time

60

-

ns

tPWHW

Write High Time

60

-

ns

tCS

Chip Select Setup Time

0

-

ns

tCSH

Chip Select Hold Time to Read Signal

0

-

ns

tCSF

Chip Select Hold Time

20

-

ns

tR

Rise Time

-

40

ns

tF

Fall Time

-

40

ns

* (VDD - VSS = 1.65V to 3.3V, Ta = 25°C)( Read Timing )( Write Timing )Page 13 of 38

Part Number : OD104

3.3.2.2

Ver:D

80XX-Series MPU Parallel Interface with Internal Charge Pump

80xx parallel interface
Vin
R2
D

C2
Q1

G
Q2

G
GPIO

S

C1

D

S
R3

C6

C5

CS#
RES#
D/C#
WR#
RD#
D[7:0]

R1
C4
C3

N.C. (GND)
C2P
C2N
C1P
C1N
VBAT
N.C.
VSS
VDD
BS0
BS1
BS2
CS#
RES#
D/C#
R/W#
E/RD#
D0
D1
D2
D3
D4
D5
D6
D7
IREF
VCOMH
VCC
VLSS
N.C. (GND)

UT-0206-P05

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

GND
Recommended Components:
C1, C2:1μF / 16V, X5R
C3:
2.2μF
C4:
4.7μF / 16V, X7R
C5, C6:1μF
R1:910kΩ, R1 = (Voltage at IREF - VSS) / IREF
R2, R3:47kΩ
Q1:
FDN338P
Q2:
FDN335N
Notes:
VDD:
1.65~3.3V, it should be equal to MPU I/O voltage.
Vin:
3.5~4.2V* VBAT will be connected to VDD when VCC be connected to external source (12V), R1 should be
replaced as 910 kΩ.

Page 14 of 38

Part Number : OD104

Ver:D

3.3.3.1 Serial Interface Timing Characteristics: (4-wire SPI)
SymbolDescription

Min

Max

Unit

tcycleClock Cycle Time

100

-

ns

tAS

Address Setup Time

15

-

ns

tAH

Address Hold Time

15

-

ns

tCSS

Chip Select Setup Time

20

-

ns

tCSH

Chip Select Hold Time

10

-

ns

tDSW

Write Data Setup Time

15

-

ns

tDHW

Write Data Hold Time

15

-

ns

tCLKL

Clock Low Time

20

-

ns

tCLKH

Clock High Time

20

-

ns

tR

Rise Time

-

40

ns

tF

Fall Time

-

40

ns

* (VDD - VSS = 1.65V to 3.3V, Ta = 25°C)

Page 15 of 38

Part Number : OD104
3.3.3.2

Ver:D

4-wire Serial Interface with Internal Charge Pump
4-w ire serial interface

V in
R2
D
Q2

C2
Q1

G

G
G PIO

S

C1

D

S
R3

C5

C6

C S#
R E S#
D /C #R4R5SCLK
S D INR1
C4C3

N .C . (G N D )
C 2P
C 2N
C 1P
C 1N
VDDB
N .C .
V SS
VDD
B S0
B S1
B S2
CS#
RES#
D /C #
R /W #
E /R D #
D0
D1
D2
D3
D4
D5
D6
D7
IR E F
VCOM HVCC
V LSS
N .C . (G N D )UT-0206-P05

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

GND

Recommended Components:
C1, C2:1μF / 16V, X5R
C3:
2.2μF
C4:
4.7μF / 16V, X7R
C5, C6:1μF
R1:910kΩ, R1 = (Voltage at IREF - VSS) / IREF
R2, R3:47kΩ
R4, R5:4.7kΩ
Q1:
FDN338P
Q2:
FDN335N
Notes:
VDD:
1.65~3.3V, it should be equal to MPU I/O voltage.
Vin:
3.5~4.2V* VBAT will be connected to VDD when VCC be connected to external source (12V), R1 should be
replaced as 910 kΩ.

Page 16 of 38

Part Number : OD104

Ver:D

3.3.4.1 Serial Interface Timing Characteristics: (3-wire SPI)
SymbolDescription

Min

Max

Unit

tcycleClock Cycle Time

100

-

ns

tCSS

Chip Select Setup Time

20

-

ns

tCSH

Chip Select Hold Time

10

-

ns

tDSW

Write Data Setup Time

15

-

ns

tDHW

Write Data Hold Time

15

-

ns

tCLKL

Clock Low Time

20

-

ns

tCLKH

Clock High Time

20

-

ns

tR

Rise Time

-

40

ns

tF

Fall Time

-

40

ns

* (VDD - VSS = 1.65V to 3.3V, Ta = 25°C)

Page 17 of 38

Part Number : OD104

3.3.4.2

Ver:D

3-wire Serial Interface with Internal Charge Pump
3-wire serial interface
Vin
R2
D
Q2

C2
Q1

G

G
GPIO

S

C1

D

S
R3

C5

C6

CS#
RES#
R4
R5
SCLK
SDIN

R1
C4
C3

N.C. (GND)
C2P
C2N
C1P
C1N
VDDB
N.C.
VSS
VDD
BS0
BS1
BS2
CS#
RES#
D/C#
R/W#
E/RD#
D0
D1
D2
D3
D4
D5
D6
D7
IREF
VCOMH
VCC
VLSS
N.C. (GND)

UT-0206-P05

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

GND

Recommended Components:
C1, C2:1μF / 16V, X5R
C3:
2.2UF/16V
C4:
4.7μF / 16V, X7R
C5, C6:1μF/16V
R1:
910kΩ, R1 = (Voltage at IREF - VSS) / IREF
R2, R3:47kΩ
R4, R5:4.7kΩ
Q1:
FDN338P
Q2:
FDN335N
Notes:
VDD:
1.65~3.3V, it should be equal to MPU I/O voltage.
Vin:
3.5~4.2V* VBAT will be connected to VDD when VCC be connected to external source (12V), R1 should be
replaced as 910 kΩ.

Page 18 of 38

Part Number : OD104

Ver:D

3.3.5.1 I2C Interface Timing Characteristics:
SymbolDescription

Min

Max

Unit

tcycleClock Cycle Time

2.5

-

μs

tHSTART

Start Condition Hold Time

0.6

-

μs

Data Hold Time (for “SDAOUT” Pin)0

Data Hold Time (for “SDAIN” Pin)

300

-

ns

Data Setup Time

100

-

ns

tSSTART

Start Condition Setup Time
(Only relevant for a repeated Start condition)

0.6

-

μs

tSSTOP

Stop Condition Setup Time

0.6

-

μs

tHD
tSD

tR

Rise Time for Data and Clock Pin

300

ns

tF

Fall Time for Data and Clock Pin

300

ns

tIDLE

Idle Time before a New Transmission can Start

-

μs

1.3

* (VDD - VSS = 1.65V to 3.3V, Ta = 25°C)

Page 19 of 38

Part Number : OD104

3.3.5.2

Ver:D

I2C Interface with Internal Charge Pump
I 2 C in te r f a c e

V in
R2
D
Q2

C2
Q1

G

G
G P IO

S

C1

D

S
R3

C5

C6

RES#
R4
R5
SCL
SDA

R1
C4
C3

N .C . ( G N D )
C 2P
C 2N
C 1P
C 1N
VDDB
N .C .
V SS
VDD
BS0
BS1
BS2
CS#
RES#
D /C #
R /W #
E /R D #
D0
D1
D2
D3
D4
D5
D6
D7
IR E F
VCOM HVCC
V LSS
N .C . ( G N D )UT-0206-P05

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

GND

Recommended Components:
C1, C2:1μF / 16V, X5R
C3:
2.2μF
C4:
4.7μF / 16V, X7R
C5, C6:1μF
R1:910kΩ, R1 = (Voltage at IREF - VSS) / IREF
R2, R3:47kΩ
R4, R5:4.7kΩ
Q1:
FDN338P
Q2:
FDN335N
Notes:
VDD:
1.65~3.3V, it should be equal to MPU I/O voltage.
Vin:
3.5~4.2V
The I2C slave address is 0111100b’. If the customer ties D/C# (pin 15) to VDD, the I2C slave address
will be 0111101b’.
* VBAT will be connected to VDD when VCC be connected to external source (12V), R1 should be
replaced as 910 kΩ.

Page 20 of 38

Part Number : OD104

Ver:D

4. Functional Specification
4.1 Commands

Refer to the Technical Manual for the SSD1306
4.2 Power down and Power up Sequence
To protect OEL panel and extend the panel life time, the driver IC power up/down routine should include
a delay period between high voltage and low voltage power sources during turn on/off. It gives the
OEL panel enough time to complete the action of charge and discharge before/after the operation.
4.2.1 Power up Sequence:
1. Power up VDD / VBAT
2. Send Display off command
3. Initialization
4. Clear Screen
5. Power up VCC
6. Delay 100ms(When VCC is stable)
7. Send Display on command

VDD onB

B

VCC /VBAT on
B

B

Display on
VCC
B

VDD
B

VSS/Ground
B

B

Display off

4.2.2 Power down Sequence:
1. Send Display off command
2. Power down VCC / VBAT
3. Delay 100ms(When VCC / VBAT is reach 0 and panel iscompletely discharges)
4. Power down VDD

VCC / VBAT off
B

B

B

VDD off
B

B

VCC/VBAT
B

B

VDD
B

VSS/Ground
B

B

Note 13:1) Since an ESD protection circuit is connected between VDD and VCC inside the driver IC, VCC
becomes lower than VDD whenever VDD is ON and VCC is OFF.
2) VCC / VBAT should be kept float (disable) when it is OFF.
3) Power Pins (VDD, VCC, VBAT) can never be pulled to ground under any circumstance.
4) VDD should not be power down before VCC / VBAT power down.
4.3 Reset Circuit
When RES# input is low, the chip is initialized with the following status:
1. Display is OFF
2. 12864 Display Mode
3. Normal segment and display data column and row address mapping (SEG0 mapped to column
address 00h and COM0 mapped to row address 00h)
4. Shift register data clear in serial interface
5. Display start line is set at display RAM address 0
6. Column address counter is set at 0
7. Normal scan direction of the COM outputs
8. Contrast control register is set at 7Fh
9. Normal display mode (Equivalent to A4h command)

Page 21 of 38

Part Number : OD104

Ver:D

4.4
Actual Application Example
Command usage and explanation of an actual example
4.4.1 VCC Supplied Externally<Power up Sequence>

VDD/VCC off StateSet Display Offset
0xD3, 0x00

Set Entire Display On/Off
0xA4Power up VDD(RES# as Low State)

Set Display Start Line
0x40

Set Normal/Inverse Display
0xA6

Power Stabilized(Delay Recommended)

Set Charge Pump
0x8D, 0x10

Clear Screen

Set RES# as High(3μs Delay Minimum)

Set Segment Re-Map
0xA1

Power up VCC & Stabilized(Delay Recommended)

Initialized State(Parameters as Default)

Set COM Output Scan Direction
0xC8

Set Display On
0xAF

Set Display Off
0xAE

Set COM Pins Hardware Configuration
0xDA, 0x12(100ms Delay Recommended)

Initial Settings
Configuration

Set Contrast Control
0x81, 0xCF

Display Data Sent

Set Display Clock Divide Ratio/Oscillator Frequency
0xD5, 0x80

Set Pre-Charge Period
0xD9, 0Xf1

Set Multiplex Ratio
0xA8, 0x3F

Set VCOMH Deselect Level
0xDB, 0x30

If the noise is accidentally occurred at the displaying window during the operation, please reset
the display in order to recover the display function.

Page 22 of 38

Part Number : OD104

Ver:D<Power down Sequence>

Normal Operation

Power down VCC(100ms Delay Recommended)

Set Display Off
0xAE

Power down VDD

B

B

VDD/VCC off State<Entering Sleep Mode>

Normal Operation

Power down VCC

Set Display Off
0xAE

Sleep Mode

<Exiting Sleep Mode>

Sleep ModeSet Display On
0xAF

Power up VCC & Stabilized(Delay Recommended)(100ms Delay Recommended)

External setting{
RES=1;
delay(1000);
RES=0;
delay(1000);
RES=1;
delay(1000);
write_i(0xAE);

Normal Operation/*display off*/

write_i(0x00);
write_i(0x10);/*set lower column address*//*set higher column address*/

write_i(0x40);/*set display start line*/

write_i(0xB0);/*set page address*/

Page 23 of 38

Part Number : OD104

Ver:D

write_i(0x81);
write_i(0xCF);/*contract control*//*128*/

write_i(0xA1);/*set segment remap*/

write_i(0xA6);/*normal / reverse*/

write_i(0xA8);
write_i(0x3F);/*multiplex ratio*//*duty = 1/64*/

write_i(0xC8);/*Com scan direction*/

write_i(0xD3);
write_i(0x00);/*set display offset*/

write_i(0xD5);
write_i(0x80);/*set osc division*/

write_i(0xD9);
write_i(0Xf1);/*set pre-charge period*/

write_i(0xDA);
write_i(0x12);/*set COM pins*/

write_i(0xdb);
write_i(0x30);/*set vcomh*/

write_i(0x8d);
write_i(0x10);/*set charge pump disable*/write_i(0xAF);}/*display ON*/

void write_i(unsigned char ins)
{

}

DC=0;
CS=0;
WR=1;
P1=ins;
WR=0;
WR=1;
CS=1;

/*inst*/void write_d(unsigned char dat){
DC=1;
Page 24 of 38

Part Number : OD104

}

CS=0;
WR=1;
P1=dat;
WR=0;
WR=1;
CS=1;

Ver:D

/*data*/void delay(unsigned int i){while(i>0)
{
i--;
}
}

Page 25 of 38

Part Number : OD104

Ver:D

4.4.2 VCC Generated by Internal DC/DC Circuit<Power up Sequence>

VDD/VBAT off StateSet Multiplex Ratio
0xA8, 0x3F

Set Entire Display On/Off
0xA4Power up VDD(RES# as Low State)

Set Display Offset
0xD3, 0x00

Set Normal/Inverse Display
0xA6

Power Stabilized(Delay Recommended)

Set Display Start Line
0x40

Clear Screen

Power up VDDB
(100ms Delay Recommended)

Set Segment Re-Map
0xA1

Set Charge Pump
0x8D, 0x14

Set RES# as High(3μs Delay Minimum)

Set COM Output Scan Direction
0xC8

Set Display On
0xAF

Initialized State(Parameters as Default)

Set COM Pins Hardware Configuration
0xDA, 0x12

Power Stabilized(100ms Delay Recommended)

Set Display Off
0xAE

Set Contrast Control
0x81, 0xCF

Display Data Sent

Initial Settings
Configuration

Set Pre-Charge Period
0xD9, 0xF1

Set Display Clock Divide Ratio/Oscillator Frequency
0xD5, 0x80

Set VCOMH Deselect Level
0xDB, 0x30

If the noise is accidentally occurred at the displaying window during the operation, please reset
the display in order to recover the display function.

Page 26 of 38

Part Number : OD104

Ver:D<Power down Sequence>

Normal Operation

Power Stabilized(100ms Delay Recommended)

Set Display Off
0xAE

Power down VBAT
(50ms Delay Recommended)

Set Charge Pump
0x8D, 0x10

Power down VDD

VDD/VBAT off State

B<Entering Sleep Mode>

Normal Operation

Set Charge Pump
0x8D, 0x10

Set Display Off
0xAE

Power down VBAT

Sleep Mode

<Exiting Sleep Mode>

Sleep Mode

Set Charge Pump
0x8D, 0x14

Power Stabilized(100ms Delay Recommended)Power up VBAT
(100ms Delay Recommended)

Set Display On
0xAF

Normal Operation

Internal setting（Charge pump）{
RES=1;
delay(1000);
RES=0;
delay(1000);
RES=1;
delay(1000);
write_i(0xAE);/*display off*/
write_i(0x00);
write_i(0x10);/*set lower column address*//*set higher column address*/
Page 27 of 38

Part Number : OD104

Ver:D

write_i(0x40);/*set display start line*/

write_i(0xB0);/*set page address*/

write_i(0x81);
write_i(0xCF);/*contract control*//*128*/

write_i(0xA1);/*set segment remap*/

write_i(0xA6);/*normal / reverse*/

write_i(0xA8);
write_i(0x3F);/*multiplex ratio*//*duty = 1/64*/

write_i(0xC8);/*Com scan direction*/

write_i(0xD3);
write_i(0x00);/*set display offset*/

write_i(0xD5);
write_i(0x80);/*set osc division*/

write_i(0xD9);
write_i(0Xf1);/*set pre-charge period*/

write_i(0xDA);
write_i(0x12);/*set COM pins*/

write_i(0xdb);
write_i(0x30);/*set vcomh*/

write_i(0x8d);
write_i(0x14);/*set charge pump enable*/write_i(0xAF);}/*display ON*/

void write_i(unsigned char ins)
{
DC=0;
CS=0;
WR=1;
P1=ins;
WR=0;
WR=1;
CS=1;

/*inst*/Page 28 of 38

Part Number : OD104

Ver:D

}
void write_d(unsigned char dat)
{
DC=1;
CS=0;
WR=1;
P1=dat;/*data*/
WR=0;
WR=1;
CS=1;
}
void delay(unsigned int i){while(i>0)
{
i--;
}
}

Page 29 of 38

Part Number : OD104

Ver:D

5. Reliability
5.1 Contents of Reliability Tests
Item

Conditions

High Temperature Operation

70C, 240 hrs

Low Temperature Operation-40C, 240 hrs

High Temperature Storage

85C, 240 hrs

Low Temperature Storage-40C, 240 hrs

High Temperature/Humidity Operation

60C, 90% RH, 120 hrs

Thermal Shock-40C  85C, 24 cycles
60 mins dwell

Criteria

The operational
functions work.

* The samples used for the above tests do not include polarizer.
* No moisture condensation is observed during tests.
5.2 Failure Check Standard
After the completion of the described reliability test, the samples were left at room temperature for 2
hrs prior to conducting the failure test at 235C; 5515% RH.

Page 30 of 38

Part Number : OD104

Ver:D

6. Outgoing Quality Control Specifications
6.1 Environment Required
Customer’s test & measurement are required to be conducted under the following conditions:Temperature:
23  5C
Humidity:
55  15% RH
Fluorescent Lamp:
30W≥ 50cmDistance between the Panel & Lamp:
Distance between the Panel & Eyes of the Inspector: ≥ 30cm
Finger glove (or finger cover) must be worn by the inspector.
Inspection table or jig must be anti-electrostatic.
6.2 Sampling Plan
Level II, Normal Inspection, Single Sampling, MIL-STD-105E
6.3 Criteria & Acceptable Quality Level
Partition

AQL

Definition

Major

0.65

Defects in Pattern Check (Display On)

Minor

1.0

Defects in Cosmetic Check (Display Off)6.3.1 Cosmetic Check (Display Off) in Non-Active Area
Check ItemClassification

Criteria
X > 6 mm (Along with Edge)
Y > 1 mm (Perpendicular to edge)
X

Panel General Chipping

Y

Minor

X

Y

Page 31 of 38

Part Number : OD104

Ver:D

6.3.1 Cosmetic Check (Display Off) in Non-Active Area (Continued)
Check ItemClassification

Criteria
Any crack is not allowable.

Panel Crack

Minor

Copper Exposed(Even Pin or Film)

Minor

Film or Trace Damage

Minor

Terminal Lead Prober Mark

Acceptable

Glue or Contamination on Pin(Couldn’t Be Removed by Alcohol)

Minor

Ink Marking on Back Side of panel(Exclude on Film)

Acceptable

Not Allowable by Naked Eye Inspection

Ignore for Any

Page 32 of 38

Part Number : OD104

Ver:D

6.3.2 Cosmetic Check (Display Off) in Active Area
It is recommended to execute in clear room environment (class 10k) if actual in necessary.
Check ItemClassification

Criteria

Any Dirt & Scratch on Polarizer’s
Protective Film

Acceptable

Ignore for not Affect the Polarizer

Scratches, Fiber, Line-Shape Defect(On Polarizer)

Minor

Dirt, Black Spot, Foreign Material,(On Polarizer)

Minor

Dent, Bubbles, White spot
(Any Transparent Spot on Polarizer)

Minor

Fingerprint, Flow Mark(On Polarizer)

Minor

IgnoreW ≤ 0.1
W > 0.1
n≤1
L≤2
L>2
n=0
Φ ≤ 0.1
Ignore0.1 < Φ ≤ 0.25
n≤1
0.25 < Φn=0Φ ≤ 0.5
 Ignore if no Influence on Display
0.5 < Φn=0

Not Allowable* Protective film should not be tear off when cosmetic check.
** Definition of W & L & Φ (Unit: mm): Φ = (a + b) / 2
LW

b: Minor Axis
a: Major Axis

Page 33 of 38

Part Number : OD104

Ver:D

6.3.3 Pattern Check (Display On) in Active Area
Check ItemClassification

No Display

Major

Missing Line

Major

Pixel Short

Major

Darker Pixel

Major

Wrong Display

Major

Un-uniform

Major

Criteria

Page 34 of 38

Part Number : OD104

Ver:D

7. Package Specifications
EPE COVER FOAM 351x212x1,
ANTISTATIC x 1 Pcs
x 1 pcs (Empty)
16
B Pcs Tray Vacuum packing
ModuleEPE PROTECTTIVE
x 15
A pcs

Staggered Stacking

Tray 420x285 mm
T=0.8mmExsiccator x 2 pcs
Brimary
Primary Box
Box C4 SET
SETWrapped with adhesive tape
x 16
B pcs

Vacuum packing bag

EPE PROTECTTIVE
370mm x 280mm x 20mm

CARTON BOX

Label
Primary L450mm x W296 x H110, B wave
x C4Pcs

Univision Technology Inc.
Part ID :Label

Lot ID :Q'ty :QC :Carton Box L464mm x W313mm x H472mm, AB wave
(Major / Maximum)

Item

Quantity

Module810

per Primary Box

Holding Trays

(A)

15

per Primary Box

Total Trays

(B)

16

per Primary Box (Including 1 Empty Tray)

Primary Box

(C)

1~4

per Carton (4 as Major / Maximum)

Page 35 of 38

Part Number : OD104

Ver:D

8. Precautions When Using These OEL Display Modules
8.1 Handling Precautions
1)
2)
3)
4)
5)

6)

Since the display panel is being made of glass, do not apply mechanical impacts such us droppingfrom a high position.
If the display panel is broken by some accident and the internal organic substance leaks out, be
careful not to inhale nor lick the organic substance.
If pressure is applied to the display surface or its neighborhood of the OEL display module, the cellstructure may be damaged and be careful not to apply pressure to these sections.
The polarizer covering the surface of the OEL display module is soft and easily scratched. Pleasebe careful when handling the OEL display module.
When the surface of the polarizer of the OEL display module has soil, clean the surface. It takes
advantage of by using following adhesion tape.
* Scotch Mending Tape No. 810 or an equivalent
Never try to breathe upon the soiled surface nor wipe the surface using cloth containing solvent
such as ethyl alcohol, since the surface of the polarizer will become cloudy.
Also, pay attention that the following liquid and solvent may spoil the polarizer:* Water* Ketone* Aromatic Solvents
Hold OEL display module very carefully when placing OEL display module into the system housing.
Do not apply excessive stress or pressure to OEL display module. And, do not over bend the filmwith electrode pattern layouts. These stresses will influence the display performance. Also,
secure sufficient rigidity for the outer cases.

7) Do not apply stress to the driver IC and the surrounding molded sections.
8) Do not disassemble nor modify the OEL display module.
9) Do not apply input signals while the logic power is off.
10) Pay sufficient attention to the working environments when handing OEL display modules to prevent
occurrence of element breakage accidents by static electricity.
* Be sure to make human body grounding when handling OEL display modules.
* Be sure to ground tools to use or assembly such as soldering irons.
* To suppress generation of static electricity, avoid carrying out assembly work under dry
environments.
* Protective film is being applied to the surface of the display panel of the OEL display module.
Be careful since static electricity may be generated when exfoliating the protective film.
11) Protection film is being applied to the surface of the display panel and removes the protection film
before assembling it. At this time, if the OEL display module has been stored for a long period oftime, residue adhesive material of the protection film may remain on the surface of the display
panel after removed of the film. In such case, remove the residue material by the method
introduced in the above Section 5).
12) If electric current is applied when the OEL display module is being dewed or when it is placed underhigh humidity environments, the electrodes may be corroded and be careful to avoid the above.

Page 36 of 38

Part Number : OD104

Ver:D

8.2 Storage Precautions
1)

2)

When storing OEL display modules, put them in static electricity preventive bags avoiding exposure
to direct sun light nor to lights of fluorescent lamps. and, also, avoiding high temperature and highhumidity environment or low temperature (less than 0C) environments. (We recommend you tostore these modules in the packaged state when they were shipped from Allvision technology Inc.)At that time, be careful not to let water drops adhere to the packages or bags nor let dewing occur
with them.
If electric current is applied when water drops are adhering to the surface of the OEL display
module, when the OEL display module is being dewed or when it is placed under high humidity
environments, the electrodes may be corroded and be careful about the above.

8.3 Designing Precautions
1)
2)
3)
4)
5)
6)
7)
8)

The absolute maximum ratings are the ratings which cannot be exceeded for OEL display module,
and if these values are exceeded, panel damage may be happen.
To prevent occurrence of malfunctioning by noise, pay attention to satisfy the VIL and VIH
specifications and, at the same time, to make the signal line cable as short as possible.
We recommend you to install excess current preventive unit (fuses, etc.) to the power circuit (VDD).
(Recommend value: 0.5A)
Pay sufficient attention to avoid occurrence of mutual noise interference with the neighboring
devices.
As for EMI, take necessary measures on the equipment side basically.
When fastening the OEL display module, fasten the external plastic housing section.
If power supply to the OEL display module is forcibly shut down by such errors as taking out themain battery while the OEL display panel is in operation, we cannot guarantee the quality of thisOEL display module.
The electric potential to be connected to the rear face of the IC chip should be as follows: SSD1306* Connection (contact) to any other potential than the above may lead to rupture of the IC.

8.4 Precautions when disposing of the OEL display modules
1)

Request the qualified companies to handle industrial wastes when disposing of the OEL display
modules. Or, when burning them, be sure to observe the environmental and hygienic laws andregulations.

8.5 Other Precautions
1)

2)

3)

4)

When an OEL display module is operated for a long of time with fixed pattern may remain as anafter image or slight contrast deviation may occur.
Nonetheless, if the operation is interrupted and left unused for a while, normal state can berestored. Also, there will be no problem in the reliability of the module.
To protect OEL display modules from performance drops by static electricity rapture, etc., do nottouch the following sections whenever possible while handling the OEL display modules.
* Pins and electrodes* Pattern layouts such as the FPC
With this OEL display module, the OEL driver is being exposed.
Generally speaking,semiconductor elements change their characteristics when light is radiated according to theprinciple of the solar battery. Consequently, if this OEL driver is exposed to light, malfunctioning
may occur.
* Design the product and installation method so that the OEL driver may be shielded from light in
actual usage.
* Design the product and installation method so that the OEL driver may be shielded from lightduring the inspection processes.
Although this OEL display module stores the operation state data by the commands and theindication data, when excessive external noise, etc. enters into the module, the internal status may

Page 37 of 38

Part Number : OD104

5)

Ver:D

be changed. It therefore is necessary to take appropriate measures to suppress noise generationor to protect from influences of noise on the system design.
We recommend you to construct its software to make periodical refreshment of the operation
statuses (re-setting of the commands and re-transference of the display data) to cope withcatastrophic noise.

Warranty:
The warranty period shall last twelve (12) months from the date of delivery. Buyer shall be completed toassemble all the processes within the effective twelve (12) months. We shall be liable for replacing any
products which contain defective material or process which do not conform to the product specification,
applicable drawings and specifications during the warranty period. All products must be preserved, handle andappearance to permit effi cient handling during warranty period. The warranty coverage would be
exclusive while the returned goods are out of the terms above.

Notice:No part of this material may be reproduces or duplicated in any form or by any means without the written
permission of us. We reserves the right to make changes to this material without notice. We do not assume
any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use
in any product or circuit and, further, there is no representation that this material is applicable to products
requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property
rights is granted by implication or otherwise, and there is no representation or warranty that anything madein accordance with this material will be free from any patent or copyright infringement of a third party. This
material or portions thereof may contain technology or the subject relating to strategic products under the control
Foreign Exchange and Foreign Trade Law of Hong Kong SAR and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.

Page 38 of 38