Ⅱ-9. Instrumentation

RIKEN Accel. Prog. Rep. 52 (2019)

Fast beam interlock system for BigRIPS separator
K. Yoshida∗1
The fast beam interlock system for the BigRIPSseparator1) was designed and constructed in 2014 andhas been in operation since then to protect the beamline equipment from hitting the misaligned intensive
primary beams due to magnet failure. The interlock
system utilizes four compact RIO systems (cRIO) of
National Instrument Co. Ltd. as the processing modules and continuously monitors the power supplies of
34 magnets placed at the primary beam line and BigRIPS, where a primary beam is transported. The
current monitor signals from the power supplies are
digitized by ADCs in cRIO every 2 µs and comparedwith the pre-deﬁned upper and lower limits. A fault
signal is generated if the digitized values are beyond
these limits. The fault signals are merged into otherfault signals and fed to the beam chopper system tocut oﬀ the beam. The total response time, which isdeﬁned as the time between an analog signal drift anda beam stopping at the third focus (F3) of BigRIPS,
was ∼200 µs for a 48 Ca 345 MeV/nucleon beam.
During the operation of fast interlock system, theoriginal system was found to be weak for the ﬂuctuation of input noises. The noise of current monitor
signals is not always stable. If the noise suddenly increases, the interlock system detects it as the drift ofthe current output and generates the fault signal. The
beam is then stopped by the beam chopper. This happens a few times per day during the beam time.
The inspection of the current monitor signal using a
digital storage type oscilloscope revealed the existenceof two types of noise: a bi-polar ringing-like noise withhigh frequency (more than 2 MHz), a short unipolar
pulse whose duration is approximately 20 µs. The latter was created with the discharge of electrostatic deﬂector EDC of the SRC. To prevent the detection ofthese noises, noise ﬁlters are inserted in the analog input lines.
One such noise ﬁlter is a passive low-pass ﬁlter. EMI
ﬁltering capacitor EMIFIL DDS1 0.022 µF of Murata
was installed at the current monitor outputs of magnet
power supplies. The moving average method was also
implemented after the ADC of cRIO system, considering the average of 2 to 16 successive digital values fromthe ADC. Because ADC provides the converted value
every 2 µs, the averaging takes place between 4 and32 µs. By installing the EMI ﬁlter and taking the average of 16 successive AD values, the ringing like noise
was completely eliminated from the system. However,the short pulse noise could still be detected because
the pulse was slower than the EMI ﬁlter and unipolar
pulses were not eliminated by averaging.
∗1RIKEN Nishina Center- 131 -Fig. 1. Logic diagram of upgraded fast interlock system.

To eliminate the short pulse noise, a time-over-limit
detection mechanism was further added to the interlock logic. This was accomplished by installing a bitshift register on the output of the comparator, which
compared the digitized signal and pre-deﬁned limits.
Each output of the comparator was stored in the ﬁrst
bit of the bit-shift register. The remaining bits of theregister were pre-shifted by one bit before storing theﬁrst bit. Thus, the 16 bit register stored 16 successive comparison results. A failure signal was generated
when all 16 bits were in the “on” state. With this algorithm, the failure signals were only generated for theinput signals whose amplitudes exceeded the limit by
32 µs. Therefore, the deviation of input signals shorter
than 32 µs was completely ignored.
The interlock logic was modiﬁed as shown in Fig. 1
by modifying the FPGA program code in the cRIO system and no hardware modiﬁcation was required. The
actual modiﬁcation was performed in April 2018 andsince then, the fast beam interlock system has been
operated with no noise.
Reference1) K. Yoshida et al., RIKEN Accel. Prog. Rep. 47, 169(2014).