Novel Control Strategy for Single-Phase to Three-Phase Power Converter
Using an Active Buffer
Yoshiya Ohnuma and Jun-ichi Itoh
Nagaoka University of Technology
1603-1 Kamitomioka-cho
Nagaoka city Niigata, Japan
Tel. / Fax: +81/ (258) – 47.9563.
E-Mail: itoh@vos.nagaokaut.ac.jp
URL: http://itohserver01.nagaokaut.ac.jp/itohlab/index.html

Keywords«Single-to-three-phase converter», «Power factor correction», «Converter control», «Capacitor
volume reduction»

Abstract
A novel single-to-three-phase power converter that allows a smaller smoothing capacitor in theDC link is proposed. Large smoothing capacitors are conventionally required in such converters toabsorb power ripple at twice the frequency of the power supply. The proposed topology consists of an
indirect matrix converter and an active snubber to absorb the power ripple, and does not require areactor or large smoothing capacitor. The fundamental operations of the proposed converter are
confirmed through simulations and experiments.

1. Introduction
Three-phase motors have recently started to be introduced into household appliances, offering
advantages such as smaller size and lower energy consumption. However, conventional household
electronics are based on single-phase motors, and household wiring is only designed for single-phaseuse. A suitable single-phase to three-phase converter is therefore essential in order to use energysaving three-phase appliances in the home. One of the most significant problems for a single-to-threephase converter is the production of power ripple at twice the frequency of the power supply.
A conventional converter consists of a diode rectifier, a three-phase inverter, and a large energy
buffer, such as an electrolytic capacitor, to absorb the power ripple on the DC link. A power factor
correction (PFC) rectifier is also required in order to suppress input current harmonics. Many
approaches on designing a suitable converter have been proposed based on the use of a PFC rectifieror DC active filter. However, almost all such converters require another switching device that causes
substantial power loss over a conventional circuit.
AC/AC direct converters, such as matrix converters, have also been studied. AC/AC directconverters are smaller in size, lower in cost, and have longer lifetimes, since the large energy buffer is
not required. Numbers of matrix converter schemes have been proposed for single-to-three-phaseconversion. In one example, power ripple is absorbed by the inertial moment of a motor [1]. Thismethod does not require additional components over that of the conventional converter, yet theapplication of this approach is limited due to the speed or torque ripple. In another approach, thesingle-phase power supply and energy capacitor are connected to the input side of the three-phasematrix converter [2]. However, this method requires 18 switching devices, detracting from theadvantages of a three-phase design.
In the present paper, a novel single-to-three-phase power converter involving smaller energy
buffer capacitors is proposed. The proposed converter is constructed based on a single-phase input
indirect matrix converter coupled with an active snubber circuit without a reactor or electrolytic
capacitor [3]. The active snubber circuit is used as an active buffer to absorb power ripple. The valuesof the capacitor can be reduced by controlling the capacitor voltage variation, allowing for the use ofsmall buffer capacitors such as film capacitors. The fundamental operations and validity of theproposed converter are confirmed by simulation and experimental results, which demonstrate good
waveforms of the input/output current and output voltage.

2. Circuit topology
A. Conventional circuit
Figure 1(a) shows a conventional single-to-three phase power converter circuit. Since this circuit
consists of a single-phase diode bridge rectifier and a three-phase inverter, it is a very simple circuit
topology. Thus, this circuit efficiency is very high. However, many harmonics components areincluded in the input current. Therefore this circuit can not meet the international standard regarding
harmonic currents, such as IEC 61000-3-2, without a DC reactor or any related devices.
Figure 1(b) shows a conventional single-to-three phase power converter circuit with power factor
correction. In order to suppress the harmonic currents, a boost chopper is added to DC link in Fig. 1(a).
This circuit can obtain sinusoidal waveforms of the input current because the boost chopper controls
the input current with a current regulator. However, this converter requires a large boost reactor andanother switching device that causes substantial power loss. In addition, conventional circuits require alarge smoothing capacitor to absorb power ripple at twice the frequency of the power supply.

(a) Diode rectifier and Inverter type(b) Diode rectifier and Boost chopperand Inverter typeFig. 1 Conventional circuits

B. Proposed circuit
Figure 2 shows a block diagram of the proposed converter. The converter is based on an indirect
matrix converter topology, where the rectifier is operated as a current source rectifier, and the inverter
stage is operated as a voltage source inverter. A buffer circuit consisting of a small capacitor and aswitch Sbuf is inserted into the DC link to absorb the power ripple with twice the frequency of thepower supply. Note that the buffer circuit is also used as a snubber circuit for the purpose of circuit
protection.

Fig.2 Proposed system block diagram.

Fig. 3 Proposed circuit with single switch in buffer circuit.
Figure 3 shows the specific circuit topology of the proposed converter. A simple and cheap dioderectifier is used as the rectifier stage converter, since most household appliances do not require aregeneration mode from the output power. Zero-current switching of the buffer switch and diodes in
the rectifier are achieved by matching the switch timing to the zero-voltage vector output of theinverter. In this manner, there is no switching loss at the buffer switch or recovery loss at the dioderectifier.

3. Control strategy
A. Principle of the power ripple compensation

Figure 4 shows the compensation principle of a power ripple. When both the input voltage andcurrent waveform is sinusoidal, the instantaneous input power, pin is expressed as,
pin = V IN I IN sin 2 (ωt )1
1(1)= VIN I IN − V IN I IN cos(2ωt )22where, VIN is peak single-phase voltage, IIN is peak single-phase current, ω is angular frequency of
single-phase.
From (1), the power ripple with twice the frequency appears on the DC bus link part.
In order to absorb the power ripple, the buffer circuit instantaneous power, pbuf, is required by (2).
Note that the mean power of the buffer circuit is zero because the buffer circuit absorb only ripple.
Therefore, a small capacitor can be used in the buffer circuit.
1
pbuf = V IN I IN cos(2ωt )(2)
2Consequently, the instantaneous output three-phase power, pout can be constant (3).
1pout = Vout I out(3)2

Fig. 4 Compensation principle for the power ripple.

Fig. 5 Equivalent circuit of the proposed system.

B. Control approach

Figure 5 shows the equivalent circuit of the proposed converter. In the equivalent circuit, the DC
link voltage Vdc and the input current of the inverter Idc are defined as the average value during one
cycle of the inverter carrier.
The input current of the inverter Idc is divided by Sbuf into the capacitor current ic and rectifier
current irec. Note that the zero-period current iz is a circulation current, as given by the rectifier output
zero-voltage vectors. The equivalent circuit then consists of three switches; SREC, SC, SZ, which are
related as follows.
⎡irec ⎤ ⎡d REC ⎤⎢ i ⎥ = ⎢ d ⎥⋅I(4)⎢ c ⎥ ⎢ C ⎥ dc⎢⎣ iz ⎥⎦ ⎢⎣ d Z ⎥⎦Here, dREC, dC, and dZ are the duty ratios of SREC, SC, and SZ, respectively, Note that the duty ratios areconstrained by a continuous current (Idc) as follows.
d REC + d C + d Z = 1(5)
The term dREC is controlled so as to obtain a sinusoidal waveform for the single-phase current irec, as
described in (6) and (7).
irec = I IN sin (ωt )
(6)
I IN
(7)
sin (ωt )I dc
The ic is controlled to absorb the power ripple of the power supply through the charge or discharge ofa capacitor depending on the direction of capacitor current.
V I(8)ic = IN IN cos(2ωt )2vC
Since negative capacitor current (charge current) is not possible when the direction of Idc is positive, Idc
is to be controlled as negative by the rectifier when the charge current mode is selected. Therefore theduty ratio dc can thus be obtained as follows.
V I(9)d C = IN IN cos(2ωt )2vC I dc
d Z = 1 − d C − d REC(10)
Meanwhile, the ratio of IIN divided by Idc can be obtained as follows from the maximum voltage
transfer ratio;d rec =

I IN
2VC 0
=
I dc 2VC 0 + VIN
where VC0 is the buffer average-voltage.
Finally, dREC and dC can be obtained as (12) from (7), (9) and (11).
2VC 0⎧⎪d REC = 2V + V sin (ωt )
⎪
C0
IN
⎨
V
V
IN C 0⎪d =cos(2ωt )⎪⎩ C vC (2VC 0 + VIN )

(11)

(12)

C. Maximum input voltage for the three-phase side

When compensation of the power ripple at the maximum output voltage, the theoretical DC link
voltage Vdc can be expressed as
1
I dcVdc = VIN I IN
2
(13)
VC 0
Vdc =
VIN
2VC 0 + VIN
Figure 6 shows the relation between the capacitor voltage and the DC link voltage requested by(13) when normalized the peak single phase voltage VIN. Therefore even the VC0 is infinity, themaximum DC link voltage is limited to VIN/2. That is, the maximum output voltage is less than half of
VIN.

D. Pulse generation method

Figure 7 shows the PWM pattern generation using a carrier comparison strategy. To obtain a PWM
pulse according to (10) and (12), the command dREC+dZ is compared with a triangular carrier. The
pulse patterns are then obtained by⎧⎪ sC = sRECZ(14)⎨⎪⎩ sZ = sREC ⋅ s RECZ
where, sC is the gate pattern for SC, sZ is the gate pattern for SZ, sRECZ is the gate pattern obtained by
dREC +dZ, and sREC is the gate pattern obtained by dREC.
A special trapezoidal carrier is used to generate the PWM pattern of the inverter. In order togenerate the zero-voltage vectors according to sZ, the inverter side carrier is set to 1 or -1 when sZ is in
the on state. The slope of the inverter side carrier is controlled by the voltage ratio between vREC andvC. As a result, the same voltage is obtained in one carrier cycle, while the differential voltage of vCand vREC is provided to the inverter.
The voltage command of the inverter is obtained using a trapezoidal carrier. It should be noted thatthe inverter commands must be inverted when Sc is in the on state, which corresponding to thecapacitor charge mode.
The gate pattern sbuf of the capacitor switch is obtained by a conversion from gate pattern sC. The
capacitor voltage is always higher than the output voltage. Since sC is not active when sZ is active, therelationship between sbuf and sINV can be expressed assbuf = sREC
(15)

DC link voltage Vdc( p.u. )Figure 8 shows the control block diagram of the proposed circuit. From (12), the duty ratio
commands are calculated from the single-phase angular frequency, the peak single-phase voltage andFig. 6 Relations between capacitor voltage and DC link voltage.

the capacitor voltage. The gate pulses are given in order to compare the duty command with thetrapezoidal carrier, and the gate pattern is converted to sbuf by (15).
The inverted commands controller is used during the capacitor current ic is in negative direction.
When the ic requires the negative direction, the switching patterns are reversed. Note that the control
for capacitor voltage refers to chapter 4.

4. Consideration of the capacitor value
A. Minimum value of the buffer circuit capacitor

The minimum capacitance in the buffer circuit requires to compensate the power ripple can be
determined by electric energy and the fluctuation capacitor voltage. The minimum capacitance tocompensate for the power ripple, WC, is obtained by (16) because WC equals to the electric power ofthe single phase side for half cycle.
1

4f
1
WC = VIN I IN ∫ sin (2ωt )dt
0
2(16)
VIN I IN Pout==2ωω
Moreover, the electric storage energy in the capacitor is requested from the relation between theelectric power and the voltage of the capacitor by (17).

1dREC + dZ
dREC
0

sREC
sZ
sC
1

Inverted commands

Vu*
Vv*

Inverted commands

Vw*

Inverter side carrier

Vv*

Vw*

Vu*

-1

Zero voltage Zero voltage
area
area

Zero voltage Zero voltage
area
area

Fig. 7 Relations between duty commands and inverter side carrier and inverter commands
R-L load

VIN=141V
Input filter
vIN
PLL
VIN
VC0*
vC
iu,iv,iv

sbuf
vC
sbuf
Carrier10dDuty RECcal.(12) dC +vC* vC* +cal.(21)iu iv iwsu, sv, sw+

Eq.(5)+PI

Capacitor voltage controls
vu*,vv*,vw*

Pulse sREC
transform sZ
sC(14)
Trapezoidal
carrier
generator
Invertedcommands+
controller v **,v **,v **uFig. 8 Control block diagram.

vwsu, sv,sw

WC =

1
1
2
2
CVC max − CVC min
2
2

(17)

where, WCmax is the maximum voltage, WCminis the minimum voltage of the buffer capacitor.
Therefore, the minimum capacitance in the buffer circuit is obtained by (18) from (16) and (17).
C=

2WC
2

VC max − VC min

2

(18)

Figure 9 shows the relations between necessary capacitor and output voltage. The conditions of
the calculation are used where VCmax is 400 V, VCmin is 150 V.
The minimum capacitance requires for a 1 kW rated output power is 46.3 μF. Therefore, a film
capacitor of small capacity can be used instead of an electrolytic capacitor. Note that the maximum
value of the current of the capacitor reaches the peak value of the three-phase current.
Next, the maximum voltage of the capacitor voltage is discussed. The electric power of the capacitor,
Wcom, is obtained by integration of (2) and (3).
Wcom = W pri −Poutsin (2ωt )
2ω

(19)

where, Wpri is the initial electric energy in the buffer capacitor. On the other hands, Wpri can be
expressed by (20)1
2
W pri = CVC0(20)
2
Therefore, instantaneous capacitor voltage vC is given by (21)
1
1
P
2
2
CvC = CVC0 − out sin (2ωt )
2
2
2ω
p
2
vC = VC0 − out sin (2ωt )(21)
ωC
The rated voltage of the buffer capacitor increased when in case of low capacitance, low output
frequency for the single phase.

B. Control method of the capacitor voltage
Practically, the capacitor voltage does not agree with (21) due to the voltage error by thecommutation and on-state drop of the power device. Thus, the capacitor voltage is controlled by the PI
regulator in order to correspond to the theoretical value. From (21), the vC* command is calculated by(21) where the output power is obtained by the output voltage command and the output current. Then,the output of the PI regulator is added to the dc from (12).

5. Simulation results

Capacitance of buffer [ F]

The operation of the proposed circuit is demonstrated here by simulation, given the conditions
listed in Table 1. In the simulation, the capacitor of 50 μF is used for the output power of 1000 W. In
this case the capacitor voltage fluctuates from 163 V to 392 V. It is note that this simulation does not

Fig. 9 Relations between capacitor voltage and DC link voltage.

vin
[V]
iin (LPF)
[A]
vC
[V]
vuv (LPF)
[V]

vuv
[V]

FFT of iin

iu[A]

FFT of vuv

consider about the commutation time for inverter.
Figure 10 shows the simulation results for the proposed control method. The input current iin andoutput voltage vuv(LPF) were observed using a low-pass filter (LPF) with a cut-off frequency of 1 kHz
in order to confirm the low frequency distortion on the waveforms. In each case, good sinusoidal
waveforms without distortion are obtained for the input current, output voltage, and output current.
Figure 11 shows the harmonic analysis of the total harmonic distortion (THD) of the input and output
currents. As a result, the THD of the input and output currents are less than 2%.

6. Experimental results
In order to demonstrate the proposed system, a 1-kW class prototype circuit has been tested. The
experimental conditions are the same as the simulation, in Table 1. Note that three-phase R-L load isused to confirm the principle of the proposed converter.
Figure 12 shows the operation waveforms for the conventional circuit (Fig. 1 (a)), which consistsof a diode rectifier, an inverter, and a capacitor of 50 μF in the DC link. The three-phase current
contains large distortion that doubles the frequency of the power grid. The distortion current of the
motor causes the increasing in losses.
Figure 13(a) shows the operation waveforms of the proposed circuit. Good sinusoidal waveforms
are obtained for the single-phase current and three-phase current, with a single-phase power factor ofover 99%. The proposed system can achieve high efficiency because the current distortion of the
Input voltage [250V/div]0

Input current [20A/div]0
Output voltage(line) [100V/div]0
Output Current [30A/div]0[10ms/div]
Fig. 12 Experimental results (Conventional circuit).

Input current THD [%]Output current THD [%](a) Input and output waveforms.
(b) Input and capacitor voltage waveforms.
Fig. 13 Experimental results (Proposed circuit).

Loss [W]

Efficiency,
Input power factor[%](a) THD of input current.
(b) THD of output current.
Fig. 14 THD of input and output current.

→

Eig. 15 Efficiency and input power factor

Fig. 16 Analysis of converter loss

motor is very low.
Figure 13(b) shows single-phase waveforms and capacitor voltage waveform. The capacitor
voltage is controlled form 400 V to 150 V of twice the frequency of the input voltage according to the
proposed strategy
Figure 14 shows the total harmonics distortion (THD) of the input and output current for theconventional circuit, as shown in Fig.1 (a), with a 50-μF capacitor and that of the proposed circuit.
The THD is calculated by less than 1-kHz harmonics. When the output power is low, the input current
THD of the conventional circuit is high because the input current in the conventional circuit only
flows at around the peak of the input voltage. The input current THD in the conventional circuit
improves according to the increasing of output power. The reason is because the period for the flow of
input current becomes long as the output power increase. The reason is because the period for the flowof input current becomes long as the output power increase. Therefore, the conventional circuitexchanges the behavior of the THD between input current and output current. However the proposed
circuit obtains low THD in both results by using the active buffer control. At the output power of 1

kW, the input and output current THD are 3.9 % and 5.1 % respectively. The output current THD in
the proposed circuit decreases to less than 1/10 times in compared with that of the conventional circuit.
In other words, these experimental results confirmed that the proposed circuit can compensate thepower ripple of twice the frequency of the power supply.
Figure 15 shows the efficiency and the input power factor of the proposed circuit. The input power
factor (P.F.) of over 99 % and high efficiency of 88.1 % are obtained in spite of the low output voltage
of 50 V.
Figure 16 shows the loss analysis using the circuit simulator for the proposed circuit. The circuit
simulator is PSIM, Powersim Inc. and DLL file (Dynamic Link Library) [15]. The switching loss does
not occur in the rectifier diode and the buffer switch. On the other hands, the conduction loss of
inverter dominates 55 % of the total loss. The reason is that the proposed method increases the inverter
current because the charge current of the buffer capacitor flows in the inverter. However the proposed
circuit does not require a power factor correction circuit. Moreover the proposed circuit is small in size.
Therefore these experimental results confirmed that the validity of the proposed circuit.

7. Conclusion
A novel circuit and control method for a single-to-three-phase power converter was proposed. The
proposed circuit provides the ZCS operation using the zero vector period of the inverter stage. The
validity of the method is confirmed by simulations and experiments. The experimental results indicatethat for a 1kW-class prototype circuit, the power ripple at twice the frequency of the power supply canbe adequately suppressed using a buffer capacitor of only 50 μF. The input current THD of 3.9 % andunity power factor are obtained even if the power factor correction circuit is very simple.

References[1] H.Haga, I.Takahashi, K.Ohishi: “Unity Power Factor Operation Control Method For Single-phase to Threephase Matrix Converter”, IEEJ Vol.124-D No.5, pp510-516,(2004)[2] M.Saito, N.Matsui: “A Single- to Three-phase Matrix Converter for a Vector-Controlled Induction Motor”,
IAS2008, pp1-6, (2008)[3] K.Kato, J.Itoh: “Control method for a three-port interface converter using an indirect matrix converter withan active snubber circuit”, EPE-PEMC 2008, pp581-588(2008)[4] T.Hirao, T.Shimizu, M.Ishikawa, K.Yasui: “Discussion on modulation methods for flyback-type singlephase inverters with enhanced power decoupling for photovoltaic AC module systems”, IEEJ IPEC,
pp.1419-1425, (2005)[5] F.Shinjo, K.Wada, T.Shimizu:”A Single-Phase Grid-Connected Inverter with a Power Decoupling Function”,
PESC 2007, pp.1245-1249, (2007)[6] Thiwanka Wijekoon, Christian Klumpner, Patric Wheeler: “Improvement of output voltage capability of atwo stage direct power converter under unbalanced input voltage”, EPE2005, No.597, (2005)[7] H.Haga, I.Takahashi, K.Ohishi: “Direct Torque IPM Motor Control Method to Obtain Unity Power Factor
Using a Single-phase Diode Rectifer”, IEMDC2003, pp.1078-1083 vol.2, (2003)[8] M.Saito: “A Novel Single/Three-phase Matrix Converter ForHigh Power Integration”, EPE-PEMC2008,
pp.2439-2444, (2008)[9] Lixiang Wei, Thomas A.Lipo: “Investigation of 9-switch Dual-bridge Matrix Converter Operating under
Low Output Power Factor”, IEEE Industry Applications Society IAS’03,pp.176-181 (2005 )[10]C.Liu, B.Wu, N.Zaargari, D.Xu: ”A Novel Three-phase Three-leg AC/AC Converter Using Nine IGBTs”,
PESC 2007, pp. 2685-2690, (2007)[11]J.Itoh, I.Sato, A.Odaka, H.Ohguchi, K.Kodachi: “A Novel Approach to Practical Matrix Converter Motordrive System with RB-IGBT” IEEE-Trans, Vol.20, issue 6, pp.1356-1363, Nov. (2005)[12]J.W.Kolar, M.Baumann, F.Schafmeister, H.Ertl: “Novel Three Phase AC-DC-AC Sparse Matrix Converter”,
APEC2002, pp777-791vol.2, (2002)[13]C.Klumpner, F. Blaabjerg: “A new generalized two-stage direct power conversion topology to
independently supply multiple AC loads from multiple power grids with adjustable power loading”
PESC2004, pp.2855-2861 vol.4 (2004)[14]C. Klumpner, T. Wijekoon, P. Wheeler: “Active Compensation of Unbalanced Supply Voltage for TwoStage Direct Power Converters Using the Clamp Capacitor” PESC05, pp.2376-2382, (2005)[15]J. Itoh, T. Iida, A. Odaka: “Realization of High Efficiency AC link Converter System based on AC/AC
Direct Conversion Techniques with RB-IGBT” Industrial Electronics Conference, Paris, ,PF-012149,(2006)