APPLICATION NOTE
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FAN9672/FAN9673 Tips and Tricks
AND9925/D
INTRODUCTION[1−2] and another application note [3] were written morecommonly, focusing on making the design process easier tofollow. They aim at most typical applications: universal
input range (90 to 264 Vac) and European input range(180 to 264 Vac) with design equations simplified according
to pre−assumed designed values.
This application note means to explain those functions interms that are more general. Information here makes readers
understand this controller better. Moreover, when one wants
to design PFC pre−regulator beyond the limitation set by
the pre−assumed designed values, these pieces of
information are beneficial for one to play around with thiscontroller.

FAN967x is multi−channel interleaved continuous−
conduction−mode (CCM) power−factor−correction (PFC)
controller. It is intrinsically an average−current−mode
PWM controller that makes average inductor current trackreal−time input−voltage waveform. FAN9672 has two gate
outputs, and FAN9673 has three, which control threeparallel−connected boost converters. By making gate−drive
signals in each channel interleaved, it reduces switchingripple of both input current and output voltage.
Since FAN967x has abundant of functionalities to make
PFC pre−regulator (PFC converter) works flawlessly,
functional description and design guideline on data sheets

DBP
RB1

VIN

CB+
AC LineIn

EMI
Filter

LPFC1

DPFC1

LPFC2

DPFC2

LPFC3

DPFC3

VPFC

RFB1

COUT

RFB2
RB1

SPFC1

RA1

S PFC2SPFC3RFRSEN 3CFB3Driver Circuit

RA2

RSEN 2
Driver Circuit

RB2

Driver Circuit

RSEN1

RFB3

CF1
CF2
RB3

OPFC1

CS1+

CS1−

OPFC2

CS2+

CS2−

OPFC3

CS3+

IAC

CB1

CB2

BIBO

CSS

RB4

VEA

SS

CILIMIT2
RILIMIT2IEA1ILIMIT2MCU

RDY

MCU signal (DC)PVO

FAN9673
IEA2

IEA3

LS

RLS
CGC

LPK

CM1

CM2

CM3

GND

RLPK

RI

ILIMIT

RRI

VIR

RILIMIT

RRLPK

RLPK
CLPK

CVC2
RVC1
CVC1
CIC12
RIC1

CIC11
CVI22

RIC2

CIC21
CIC32

RIC3

CIC31

VDD

GC

RGC

MCU

CS3−
FBPFC

Channel Enable

CRLPK

CVDD
Standby PowerCVIR RVIRCILIMIT

Figure 1. Typical Application Circuit of FAN9673© Semiconductor Components Industries, LLC, 2019

May, 2024 − Rev. 3

1

Publication Order Number:
AND9925/D

AND9925/D

Programmable
Voltage − loop
Regulator
Gain
Modulator
Peak
Detector

PVO

VEA

FBPFC

ILIMITILIMIT2

VDD

VIR

SS

29

3

7

28

16

31
SS

2

30

GMV

ÌÌÌ
ÌÌÌ
ÌÌÌ

VDD
24V/23V

1.2V / RRI

2.5V

1/4X

0.3V
VVEA

B

LPK

8

Peak Detector

RLPK

6

Ratio

IAC

32

IEA1

10

CS1+

23

CS1−

22

IEA2

11

CS2+

21

CS2−

20

IEA3

12

CS3+

19

CS3−

18

LS

17

GC

4

VVIR < 1.5V, FR
VVIR > 3.5V, HV

60uA

Brown Out,
Protection

VEA

VEA LPD

VFBPFCRM

Imo

VVEA > VSSPFC UVP

2.75V/2.5V

PFC OVP

VBIBO−UVP −ː VBIBO−UVPVBIBOAC UVP

Voltage−mode PWM

Current Regulators

ILIMIT2
CS1

S

SET

Q

R CLRQ

GMI1

CM1

S

LPT1

27

OPFC1

26

OPFC2

25

OPFC3

9

RDY

SET

Q

R CLRQIEA_SAW1ILIMIT2
CS2

Dead1

LinearPredict
Inductor
Current
Emulator

20uA

0.5V

C

A

VDD OVP

10uA

S

SET

Q

R CLRQ

GMI2

CM2

S

LPT2

SET

Q

R CLRQIEA_SAW2ILIMIT2
CS3

Dead2

S

SET

Q

R CLRQ

GMI3

CM3

S

LPT3

SET

Q

R CLRQ

5V

IEA_SAW3

55uA

13

14

15

CM1

CM2

CM3

55uA

UVLO

VDD

Dead3
Brown In/Out
FR: 1.05V/1.9V
HV: 1.05V/1.75V

Oscillator

Brown out

VGMV−
FR: 2.4V/1.25V
HV: 2.4/1.55V

55uA

ChannelManagement

5

1

24

RI

BIBO

GND

Figure 2. Simplified Block Diagram of FAN967x
Overview of Block Diagram

input voltage, the peak of input voltage and the VEA.
The current command is proportional to the VEA signal.
High current−command signal makes high regulation target
for inductor currents, which leads to the high input current.
As a result, VEA voltage is proportional to the operating
wattage condition of the PFC power converter.
Between the gain modulator and the GMI error amplifiers,
there are channel−management blocks. This block acts as again for reducing current command signal fed into the GMI
error amplifiers for managing power in each PFC channel.
Figure 3 illustrates the signal flow of the PFC control
mechanism described above. Other blocks in Figure 2 thatare not mentioned in this section are peripherals forparameters setting, status indication, and protections.

Figure 2 shows the block diagram of FAN9673. It is
the same drawing in the datasheet of FAN9673, except thatits functional purposes group related blocks. Block diagramof FAN9672 is almost identical to this one, except it reduceschannel number by one.
FAN967x is a multi−channel interleaved pulse−widthmodulation (PWM) controller, which modulates its duty tomake inductor current track input−voltage waveform.
The PWM block receives control voltages generated by
GMI1~3. GMI1~3 are trans−conductance error amplifiers,
used to make inductor current of each channel track a current
command. These GMI generate signals IEA1~3, serving as
control voltage of the PWM block.
Three sets of differential−input CS pins sense inductor
currents. Current−sense (CS) signals are then further
processed by linear−predict (LPT) blocks, explained later.
An FBPFC pin senses an output voltage of the PFC stage.
Another trans−conductance error amplifier GMV takes
the FBPFC signal. GMV is used to regulate FBPFC voltage.
Some additional elements are inserted between FBPFC and
GMV input to change regulation target for the FBPFC otherthan 2.5 V. GMV generates an error signal VEA, feeding intoa gain modulator section.
A gain modulator generates the current command for
the GMI. It takes signals that represent the real−time value of

Inductor Current
Signal (CS)

Output Voltage
Signal (FBPFC)
PVO

Linear Predict

GMV

GMI

IEA

Gate
DriverPWM

Gate Drive
Signal (OPFC)

VEA
Peak
Detector

Current
ChannelCommandGain
Management
Modulator

Input Voltage
Signal (IAC)

Figure 3. Signal Flow of PFC Control Mechanism

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AND9925/D
Input Sensing and Peak Detection

FAN967x detects input voltage from IAC pin. IAC pin isa current−mirror input. Its input impedance is much smaller
than an external RIAC resistor, making its input current asbufferdelay

where VIN is the real−time input voltage. By considering
rectified sinusoidal input for the PFC stage, (eq. 1) can bere−write as
V IN.PEAK@ |sin(w @ t)|
R IAC

Figure 5. Block of Input Voltage Detection
V RLPK >V PEAK +0.2V
Step −up tracking(eq. 2)where w stands for angular frequency of the ac−input
voltage.
An RLPK pin mirrors IIAC as a sourcing current. With aresistor connecting to the RLPK pin, the input−voltage
information in a current−signal format, IIAC , becomes a
voltage signal, VRLPK .

V PEAKV RLPKV PEAK −HOLD *0.95
t UPDATE =3.5m s

VIN
VVEA
RIAC

VBIAS

IAC

B
A GainModulator
C

Peak Detector
RLPK
VRLPK

Update V PEAK andreset V PEAK −HOLD

Figure 6. Algorithm of Peak Detector

Current
Command

In an extreme AC−input sag situation, FAN967x blanks
updating of VPEAK . This AC−OFF mechanism is as depicted
in Figure 7. When VRLPK keeps lower than a VAC−OFF fortAC−OFF, FAN967x triggers AC−OFF. AC−OFF is released
when VRLPK > VAC−ON while updating of VPEAK keeps
blanking for the following 5 ms. It is worth noting that the
IEA signal, which is the control voltage of PWM, is pulled
low during the AC−OFF situation.
Timing specification in Figure 6 and Figure 7 are designed
values in FAN967x. These values are optimized for typical
50~60 Hz ac input.

I IAC
ZIN

VPEAK
bufferupdate(eq. 1)I IAC + V INńR IAC

I IAC(t) +VPEAK−HOLD

VRLPKAC−OFFLPKRRLPKFigure 4. Block of Input Voltage Detection

VRLPK replicates the shape of the input−voltage
waveform. A peak detector block processes VRLPK signal to
track its cycle−by−cycle peak value. The basic algorithm ofpeak detector is as depicted in Figure 6. An intermittent
signal VPEAK−HOLD traces rising VRLPK and hold the peakvalue until triggering of a reset event. The reset is triggered
when VRLPK keeps lower than VPEAK−HOLD *0.95 for atUPDATE duration. Upon reset is triggered, VPEAK updates
with the last VPEAK−HOLD value. This algorithm is designed
to update VPEAK at the valley of VIN waveform, so tominimize disturbance of PFC operation due to VPEAK
variation. The VPEAK signal is then sent to LPK pin and gain
modulator.
When the peak of VIN suddenly increases, anothermechanism update VPEAK in a much faster pace by detecting
VRLPK > VPEAK + 0.2 V, which is also depicted in Figure 6.
This mechanism acts only when VRLPK exceeds VPEAK by
0.2 V. However if VRLPK is higher than VPEAK but not thatmuch, VPEAK will not be updated until the criterion of VRLPK< VPEAK−HOLD*0.95 is satisfied.

No VPEAK updatetBLANK=5ms

VPEAK
VRLPK
VAC−ON=VPEAK*0.2
VAC−OFF=VPEAK*0.1
tAC−OFF=2.5ms
IEA pull low

Figure 7. Blanking VPEAK Update During AC−OFF

FAN967x generates the VLPK signal to be utilized byother circuitries, such as a microcontroller unit (MCU) for
acquiring input−voltage information. LPK pin can provide
a signal to a high input impedance port. LPK pin’s output

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3

AND9925/D
same as VCS with OPFC is in on state. When OPFC is off,the LPT block generates a synthesized part of the current
signal by discharging a capacitor from the last peak value of
VCS.
If the inductor current is sensed by a current−sense resistor
RCS all the time, the slope of the sensed signal during tOFF
should be

impedance is around 5 kW. Sinking too much of current from
LPK pin makes its voltage drop.
There is a known situation that a drop in VLPK signal fora short time can happen. We observed the phenomenon when
PFC converter is designed to work in low−power detection
mode (VVEA <VVEA−OFF ), or burst mode, with a high input
power. VIN can be a little bit higher when input current (IIN )cuts off. The slightly elevated VIN may make the updating of
VPEAK trigger two times during one valley of rectified VAC .
That makes VPEAK updated with a wrong value. It recovers
within one−fourth of the ac−input period. If LPK signal isused by other circuitry to have protection based on the input
voltage detection, consider adding a blanking time morethan one−fourth of the ac−input period for a smootheroperation.

(V OUT * V IN) @ R CS
L

In the LPT block, the slope of the synthesized waveformis(V FBPFC * V GC)
1.5n @ R LS

Rectified V AC
VIN

V PEAKV RLPKV PEAK−HOLD

3.5ms

Figure 8. A situation That Makes VPEAK (VLPK) Drop
Linear−Predict Function for Rebuilding Inductor
Current

R GC +

Constant−frequency CCM PFC controls its average
inductor current to track input−voltage waveform. CS pin of
FAN967x is designed to simplify current−sense circuitry.
You can directly put current−sense resistor at the source
terminal of power switches of a boost converter. With thisconnection, the controller gets the inductor current
information when the power switch is in ON state. Since
controlling a CCM PFC requires average inductor current
information, FAN967x implements a linear−predict
function for the reconstruction of the inductor current signal.
slope :V IN
@ R CSL

VCS
tON

slope :

(eq. 4)

VFBPFC represents the output voltage. GC pin is similar to
RLPK pin, which gets a sourcing current mirrored from IAC
pin. In other words, VGC contains the input−voltage
information. By putting a resistor RGC on GC pin,
VGC−to−VIN ratio is adjusted to be identical with
VFBPFC−to−VOUT ratio. As a result, (VFBPFC – VGC )become a replicate of (VOUT − VIN ). After VGC level being
correctly set, RLS is adjusted to make the slope of thesynthesized waveform (eq. 3) matched with pseudo sensed
inductor current waveform (eq 4). In short, the GC pin isused to set a ratio, making input voltage signal comparablewith output voltage signal; and, LS pin is used to set theslope of synthesized signal, mimicking behavior of theactual inductance applied in the boost converter.
The description above implies how the design equations of
RGC and RLS are derived.

Switching operation halted due tolow−power detection

Rectified I IN

(eq. 3)

R IAC
R FB3
@
R FB1)R FB2)R FB3
1, if V IR t 1.5
2, if V IR u 3.5

ƪ

R LS +

R FB3
L
1
@
@
R FB1)R FB2)R FB3 R CS 1.5n

(eq. 6)

Synthesized
current signal

VBIAS

IAC

IIAC

VCS
VFBPFCZIN
GC(V FBPFC * V GC)
1.5n @ R LS

ƫ(eq. 5)

VGC

Linear Predict

LS

RGC

RLS

Figure 10. Simplified Block Diagram ofLinear−Predict Function

Synthesized

Common−mode and Differential−mode Filter for
Current−Sense Signal

tOFF

Because of multi−channel nature, FAN967x controller ishard to stay close to current−sense (CS) resistors. Long PCB
trace between the CS resistors and the controller makethe CS signals prone to be noisy. FAN967x takes
the current−sense signals as differential−input signals which
reject the induced common−mode noise on the PCB trace.

Figure 9. Linear−Predict Function

A linear−predict (LPT) block manipulates VCS before
feeding into the GMI error amplifier. The current signal is thewww.onsemi.com
4

AND9925/D
A resistance value connecting between VIR and GND
decides the voltage on the VIR pin. The voltage on the VIR
pin needs to be set higher than 3.5 V or lower than 1.5 V.
Avoid anything in between.
The setting on the VIR pin changes some internal signalsof FAN967x, which are collected in Table 1. A KRLPK
constant appears in the table. According to the test cases of
VLPK, which can be found in electrical characteristics inthe datasheet, KRLPK is 2.465.

Although differential input rejects common−mode noise
inherently, the common−mode voltage on each of the input
pin still affects the operation of the controller.
A common−mode filter is generally implemented to filter
out the common−mode noise. Figure 11. shows a schematicofthecommon−modefilter.
Bandwidthofthe common−mode filter is
f BW*comon +1
2p @ R f @ C C(eq. 7)

Table 1. Effects of VIR Setting

noise

Rf Cc

RCS
Rf Cc

VVIR

CS+
CS-

noise

Figure 11. Common−mode Filter for CS Pin

Due to a mismatch between the resistors and capacitors in
the common−mode filter, common−mode noise may befiltered differently between CS+ and CS−. As a result,a differential−mode noise appears on the CS signals. To
tackle with the differential−mode noise, we add a capacitor
to filter out the differential−mode noise.
With the resultant CS filter in Figure 12, which combines
common−mode
anddifferential−modefilters,
the bandwidth of a low−pass filter for the differential CS
signals becomes1
f BW*diff +2p @ 2R f @ ǒC d ) 12 @ C cǓ

(eq. 8)Cd
Rf Cc

Optimized for

Universal−input
range (90~264 Vac)

European−input
range (180~264 Vac)

Recommended
RIAC

6 MW

12 MW

VBIBO Brown−in
Level1.90 V

1.75 V

VBIBO Brown−out Level

1.05 V

1.05 V

VFBPFC for
RDY = HIGH

2.4 V

2.4 V

VFBPFC for
RDY = LOW

1.25 V

1.55 VIRLPKKRLPK*IIAC

2*KRLPK*IIAC

VLPKPeak of
2*KRLPK*IIAC*RRLPKPeak of
4*KRLPK*IIAC*RRLPK“C” input of gain
modulator

Peak of
2*KRLPK*IIAC*RRLPKPeak of
2*KRLPK*IIAC*RRLPKIIAC

2*IIAC

Signals of the Gain Modulator

Gain modulator generates a current command for inductor
current to follow. Inductor current of PFC converter shouldhave the same shape of input voltage, be proportional toerror signal VVEA , and have magnitude inverse−proportional
to the magnitude of the input voltage. In this condition,
the current command decreases when the amplitude of input
voltage increases without waiting for the output voltage torespond. That is, input power is kept unchanged bya feed−forward control. More, VVEA is ideally decided bypower requirement and less related to fluctuation in input
voltage.
To realize the characteristics mentioned above, gain
modulator is designed to have its output signal proportional
to A · B/C2, where A, B and C are its input signals depicted
in Figure 13.

noise

RCS

> 3.5 VIGC

The bandwidth of the filter should be set based on noisethat is generated in actual design result. In a 5 kW reference
design for FAN9673 with 40 kHz of switching frequency,
we set fBW−common at 154 kHz and fBW−diff at 51.3 kHz.

Rf Cc

< 1.5 V

CS+
CS-

noise

Figure 12. CS Pin Filter
Effect of Input Range Setting

VIR pin of FAN967x sets two different modes that
optimize for universal input range and European input
range, respectively. This pin sources a constant current.

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5AND9925/D
VIN
IL
+

RFB1
CO

RIAC
IIAC

V RM + K @

ÌÌÌ
ÑÑÑ
ÑÑÑ
ÌÌÌ
ÑÑÑ
ÌÌÌ

IAC

A

C

B

VFBPFC
RFB2

RCS

A

VLPK

Figure 13. describes the output of gain modulator as acurrent signal, which is converted to a voltage signal by aresistor RM . So, current command is named as VRM , meaning
voltage across the RM resistor.

VOUT

Peak
Detector

Current Command(C. Comd.)

C

IMO

B

RM

(eq. 9)Replacing A, B, and C terms in (eq. 9) by its real input
signals, VRM can be re−write as
V RM(t) +Gain Modulator

Current Command
A B+K(C. Comd.)
C2

VEA

A@B
@ RM
C2

K RM @ I IAC.PEAK @ (V VEA * 0.6) @ |sin(w @ t)|(2 @ K RLPK @ I IAC.PEAK @ R RLPK) 2(eq. 10)In (eq. 10), a KRM constant replaced K ⋅ RM, and IIAC.PEAK
represents the peak value of IAC signal in (eq. 2). Electricalcharacteristics table on the datasheet provides several test
cases of VRM . The test cases set RRLPK as 12.4 kW, whichmakes VLPK = VIN.PEAK /100 when RIAC is set according toTable 1. More, VFBPFC = 2.25 V makes VVEA be pulled high.
Gain modulator reacts to VVEA with a linear range of 0.6 to
5.6 V with a 0.6 V voltage shift. Calculation from those test
cases shows that KRM is about 6000. Note that the linear
range of VRM is up to 0.8, which may happen in the lowest
input voltage condition.
VRM is inverse proportional to IIAC.PEAK . When the input
voltage increases, IIAC.PEAK increases as well. As a result,
VRM reduces to a lower value. Ideally, VVEA should keep
unchanged, if only the input voltage changes but the loading
is unchanged. In actual implementation, VVEA may stilldecrease slightly due to propagation delays in control signal,such as gate−driver delay and CS−pin filter delay.
Since VCS tracks the current command VRM , VRM equationand the maximum wattage in the design specification of
the PFC converter determine RCS as

2.5 V
VFBPFC

Figure 13. Gain Modulator

V IN
V PEAK
IAC
V VEA
V RM

(current
command )IL

Figure 14. Behavior of Gain Modulator in Line
TransientPO

R CS +VO

K RM @ R IAC @ (V VEA.MAX * 0.6)22

8 @ K RLPK @ R RLPK @ P MAXńN CH(eq. 11)

where PMAX is specified maximum power of PFC converter,and NCH is the number of channels of the multi−channel PFC
converter. VVEA.MAX is a maximum VVEA voltage under
PMAX condition. VVEA.MAX is generally set around 4~5 V.
Set VVEA.MAX properly by setting RCS , so that the control
signals in FAN967x can be high enough to achieve a stable
operation.
In a universal−input design, VRM tends to be smaller thanwhen the PFC converter operates in high−line input
conditions. As shown in Figure 16, VRM in system set to
RIAC = 12 MW and VVIR = 5 V for European input range
becomes higher than set to RIAC = 6 MW and VVIR = 0 V,
which has a better signal−to−noise ratio and better usage of
its resolution. At the same time, since doubled RIAC make
IIAC reduce to half under the same VIN condition, FAN967x
doubles IRLPK and IGC so that RRLPK and RGC settings canbe the same.

VVEA
VRM

(current
command)IL

Figure 15. Behavior of Gain Modulator in Load
Transientwww.onsemi.com
6

AND9925/DHigh VINRIAC = 6 MW
VVIR = 0 V

Low VIN
RIAC = 6 MW
VVIR = 0 V

High VINRIAC = 12 MW
VVIR = 5 VvˆOUT

Gvd (s)VINd̂Voltage
DividervˆFBiˆL

Gid (s)Gmv (s)IIAC

Due toparallelconnection

Fm

RCS/NCH

VRM

vˆCS

vˆIEA

−

Gmi (s)

IRLPK

S

+

vˆVEA

vˆRM Gain

Modulator

Figure 18. Control Block Diagram of FAN967x

IGC

VIEA

Figure 16. VIN Related Signals under Different VIRand RIAC Setting
VIN

OPFC

V PFC

vˆOUT

iˆL
RCS

• VCS , VIEA ± , duty cycle ±
±

IL

5V

VRAMP

dˆ

Figure 19. PWM in FAN967x

vˆCS
CS+
LS

gmi

LPT

CM

CI1

T I(s) 5 G id(s) @ R CS @ G mi(s) @ F m

ˆ

IEA vIEA

CM

RIAC
IAC
LPK

v̂VEA VEA
RV1
CV2

RI1

Current−Tracking Loop
There are two feedback loops in the control block diagram[4], one is for making inductor current track the current
command. The gain of this loop is

CS−

CV1

RM

IMO

v̂RM

CI2

Drive
Logic

Peak
Detecter

OSC

2.5V

where Gid(s) is duty−cycle−to−inductor−current transfer
function of boost converter [5], Gmi(s) represents GMI error
amplifier and setting on IEA pins, and Fm is modulation gainof PWM. As a voltage−mode PWM, modulation gain is thereciprocal of the amplitude of a ramp signal, VRAMP,
depicted in Figure 19.

OPFC
RI

RFB1+FB2

gmv

v̂FB

PVO

FBPFC

(eq. 12)RFB3

F m + 1ńV RAMP

Figure 17. Control Loop of FAN967x

Gid(s) in [5] is repeated as (eq. 14), where COUT is
capacitance of the output capacitor, rC is equivalent series
resistance of the output capacitor, RLOAD is equivalent
resistance of the output loading, L is inductance of power
inductor in each channel, and D is duty cycle of OPFC
signal. D = (1– VIN/VOUT) By assuming that rL and rC aresmall and RLOAD is large, (eq. 14) can be simplified as(eq. 15).

Figure 17 shows a full view of all blocks involved in PFC
control. The figure shows only one channel for simplicity.
PVO block’s effect is to change effective reference voltage
for FBPFC, so it does not affect the control signal insmall−signal point of view. In full load condition, channel
management (CM) block is no more than a unity−gainbuffer, so we neglect it in analyzing the control loops.

s)

V OUT R LOAD ) 2 @ r cÀL
G id(s) 5 +@@d
L
R LOAD ) r cs2 )ƪG id(s) +C(eq. 13)

ƪ ǒ

Ǔ

1

ǒ LOADń2)rcǓ

C@ R

r R
)r )R
r (1*D)
OUT L LOAD CLOAD CL@C(R)r )OUT LOAD C

V OUT
@
L

s

(1*D) 2s 2 ) L@C
OUT

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7

2

ƫ)L

ƫ

(eq. 14)s)(1*D) 2R
L@C

OUT

LOAD

)r L

ǒRLOAD)rCǓ
(eq. 15)

AND9925/D
To make inductor track current command well,
the bandwidth of the current−tracking loop need to set highenough. When the complex pole formed by L and COUT is
at a frequency much lower than the control bandwidth of
TI (s), we can further simplify Gid(s) as
G id(s) +

V OUT
s@L

Figure 20 shows comparison data resulted in both
simplified (eq. 17), in full (eq. 14), and via simulation.
The simplification removes low−frequency components
and focus on frequency range around control bandwidth.
Voltage−Regulation Loop

Except for the current−tracking loop, there is anothercontrol loop for regulating the output voltage. By breaking
the loop at the position of àFB in Figure 18, we can derive theloop gain as (eq. 18), where GMOD is the effective gain of thegain modulator, Gvd (s) is duty−cycle−to−output−voltage
transfer function of boost converter, VFBPFC /VOUT is theeffective gain of a voltage divider for PFC output voltage,and Gmv (s) represents GMV error amplifier. TI (s) in the
denominator is divided by NCH . Because all the channels areconnected in parallel, so as the current−tracking loop.
Bandwidth of the voltage−regulation loop is generally
lower in PFC converters. Within the bandwidth of thevoltage−regulation loop, TI (s) is much larger than one. So,
terms in (eq. 18) that relates to the boost power stage andthe current−tracking loop can be manipulated as (eq. 19).
Gvd (s) in [4] is repeated as (eq. 20).
By neglecting rC and rL , Gid (s) in (eq. 14) can be
simplified as (eq. 21). Substituting (eq. 20) and (eq. 21) into
(eq. 19) results in (eq. 22). Again, assuming rC is small and
RLOAD is large, we can simplify (eq. 22) as (eq. 23).
GMOD can be derived from (eq. 10) as (eq. 24).
Substituting (eq. 11), (eq. 22), and (eq. 24) into (eq. 18), loop
gain of the voltage−regulation loop can be written as(eq. 25).

(eq. 16)

With (eq. 13) and (eq. 16), (eq. 12) can be simplified as(eq. 17), which is the same as the design equation inapplication note AN4165/D.
T I(s) +V OUT @ R CS
@ G mi(s)s @ L @ V RAMP

200

fIC

Simple eqn.
Full eqn.
Simulation

Gain (dB)1000Phase (degree)

*100
10
0

(eq. 17)

0

100

3

4

1×10

fIC

1×10

5

1×10

*50
*100
*150
*180
*200
10

100

1×10

3

1×10

4

1×10

5

Frequency (Hz )Figure 20. Comparison of TI (s) Equations
Loopgain(s) + G MOD @G mi(s) @ F m

1 ) T I(s)ńN CH@ G vd(s) +G mi(s) @ F m
1 ) T I(s)ńN CH

G id(s) +N
V IN@ CH +@
G id(s) R CS
V OUT @ C OUT

G id(s)ǒǒ1 ) s @ C OUT @ r CǓ 1 *s2 ) C

V OUT@
L

G vd(s)G MOD(t) 5

V FBPFC@ G mv(s)V OUT(eq. 18)

G mi(s) @ F m @ G vd(s)G (s) N+ vd @ CH
G id(s) R CS
G id(s) @ R CS @ G mi(s) @ F mńN CH

V IN@
G vd(s) +L @ C OUT

G vd(s)@ G vd(s) @

@

OUT

1
@R

s@L
(1*D) 2@R

LOAD

(eq. 19)Ǔ

(eq. 20)(1*D) 2LOADs ) L@C

OUTs ) C @(R1
ń2)
OUT
LOAD
s2 ) COUT

1@R(eq. 21)(1*D) 2LOADs ) L@Cǒǒ1 ) s @ C OUT @ r CǓ 1 *
s)C

OUT
s@L

(1*D) 2@R

LOAD

Ǔ N

1
@(R
ń2)
OUT
LOAD

@

CH

R CS

N CH
N
V
1
+ IN @@ CH
R CS
V OUT s @ C OUT R CS

(eq. 23)

K RM @ I IAC.PEAK @ |sin(wt)|
K @ R IAC @ V IN.PEAK @ |sin(wt)|
à RM
+
+ RM
2
2
2
2
à VEA
ǒ2 @ K
Ǔ
8K
R
V
@I
@R
RLPK

IAC.PEAK

RLPK

www.onsemi.com
8(eq. 22)

RLPK

RLPK

IN.RMS(eq. 24)

AND9925/D
Loopgain(s) +(V IN.PEAK @ |sin(wt)|) 2
V IN.RMS

2

Loopgain(s) ac*cycle +

@

V
P MAX
1 @
1
@
@ FBPFC @ G mv(s)V OUT s @ C OUT (V VEA.MAX * 0.6) V OUT(eq. 25)

P MAX @ I OUTV
1@@ FBPFC @ G mv(s)s @ C OUT (V VEA.MAX * 0.6) @ V OUT @ I OUT V OUT@IP MAX @ I OUT
K
V
1
1
+
@
@ FBPFC @ G mv(s) +@ MAX OUT @ 2.5 @ G mv(s)5
V OUT
s @ C OUT (V VEA.MAX * 0.6) @ P OUT V OUT
s @ C OUT

beneficial for overall efficiency. FAN967x’s CM pins areused to manipulate enabling or disabling of the respective
channel. Note that CM1 disables all channels at once.
Two different ways can be used by interfacing with CM
pin, as depicted in Figure 22. When using an external circuit
to send a logic signal, a logic HIGH and LOW signal
controls CM pin voltage to activate or deactivate eachchannel. In this way, any VCM level in between is not used.
The other is to set a voltage on the CM pin by a resistor
based on the maximum sourcing current of the CM pin. This
voltage becomes a threshold voltage for VVEA to decide
whether a channel should be disabled or enabled. When
VVEA >55 mA*RCM , the respective channel is in fulloperation. Otherwise, FAN967x gradually reduces the ratioof wattage that the channel delivers until it is fully disabled.
Also, note that all channels shut down when VVEA <VEA−OFF (0.3 V).

In real application, input voltage is sinusoidal waveform.
By averaging (eq. 25) over one period of input voltage,a simplified loop−gain equation can be derived as (eq. 26),
where IOUT is rated output current, POUT is rated output
power, PMAX refers to maximum delivered power when
VVEA = VVEA.MAX , and KMAX ≡ PMAX /POUT. Since VVEA has
5 V of linear range, VVEA.MAX – 0.6 = 5.
When programming output voltage (PVO) function is not
activated, the control loop regulates VFBPFC to 2.5 V. Thus,(eq. 26) becomes the design equation referred in applicationnote AN4165/D. However, if the RCS value is notdetermined exactly as indicated by (eq. 11), (eq. 18)
combined with (eq. 23) and (eq. 24) can serve as design
equation.
The voltage−regulation loop gain is drawn in Figure 21.
The simple equation refers to (eq. 23), while the fullequation refers to (eq. 22). A computer simulation result is
put together for comparison. Although (eq. 22) gives a resultthat is closer to simulation result, (eq. 23) is reasonable to be
used for design purpose.
40

fVC

Gain (dB)

Channelenablesignalfrom MCU

Simple eqn.
Full eqn.
Simulation

20

0

CM

S2

Channeldisablelevel setby resistor

CM

RCM

0

Figure 22. Interfacing CM Pin

*20

*40

Disable01

Phase (degree)(eq. 26)

10

fVC

100

1×10

3

VCM

*50

*100

4V

VVEA−based
channelmanagement
setting range

Enable0V

Figure 23. VCM Operating Range

*150
*180
*200
1

10

100

1×10

Figure 24 shows the concept of CM−pin behavior.
A comparator compares VCM and VVEA , and its output
adjusts CM−pin sourcing current and the gain between VRM
and GMI error amplifier. The gain and the CM−pin sourcing
current changes together, as described in Figure 25. When
the CM−pin sourcing current drops to 17.5 mA, which is
31.8% of its maximum value 55 mA, the gain drops to 0%
and the respective channel is disabled.

3

Frequency (Hz)Figure 21. Comparison of Loop−Gain Equations
How Channel Management Works

In a multi−channel PFC converter, to disable somechannels according to different load conditions can bewww.onsemi.com
9AND9925/D
V CS

LinearPredict

VRM

Gain

the amplitude of the current command is not too much larger
than the possible offset voltage. The offset voltage becomesprominent to the current command, which makes delivered
power of each channel be not identical. Some channels may
even not operate since their valid current command issmaller than the negative offset voltage, which means
the channel current will be regulated to zero.
To overcome the uncertainty by the offset voltage ofthe GMI error amplifier, we recommend adding graduallyoperating channel number according to output power byusing channel−management function. Reduced channel
number in light load condition forces the required current
command signal to be higher. So, it alleviates the effect of
the offset voltage.

G MI

V IEA

CM

V VEA

PWM

R CM
OSC Phase −angle Control

OSC

Figure 24. Conceptual Block Diagram of CM Pin
VVEA
55μA*RCM

VCM
17.5μA* RCM

IAC

Gain

VCS
Peak
Detecter

LPK

100%

GMI
VIEA

VRM
RM

VEA

VOS = −20 ~+ 20mV

0%

Figure 25. Interaction of VVEA and VCM
Figure 26. Input Offset of GMI Error Amplifier

Offset in GMI error amplifier

Input offset is a particular non−ideal characteristic in mostof the amplifiers. In FAN967x, the design target of the GMI
error amplifier is to have zero input−offset voltage. By
trimming during IC production, the offset voltage of the GMI
error amplifier of the first channel is very close to zero. For
the other channels, assuming VOS ranges from −20 to 20 mV
is reasonable due to production variation.
VOS of the GMI error amplifier distorts the shape of
the inductor current, which means that total harmonic
distortion (THD) can be affected, in light−load conditions.
When VOS is with a negative value, the average inductor
current goes lower due to negatively shifted current
command (see VCS−B in Figure 27). Around the valley ofthe rectified input−voltage signal, the current command
becomes zero. When VOS is positive, the average inductor
current goes higher (see VCS−C in Figure 27). Aroundthe valley of the rectified input−voltage signal, the input
voltage is zero while the current command is above zero.
Both conditions make the shape of the input current
distorted.
Effect of VOS on THD is minor in heavy−load conditions.
In light−load conditions, its effect becomes muchremarkable. Our experience is that when offset is negative,
THD measurement result tends to be higher (worse), while
higher−order harmonics have lower energy (better), andvice versa.
Another effect of the offset is current imbalance acrosschannels in light−load condition. If we connect all CM pin
to ground, all channel should be in full operation. They
should deliver the same amount of power. However, in lightload condition, such as VVEA ≈ 1 V and high input voltage,

VIN

No
offsetVRM

Negative
offset

VRM −20mV

Positive
offset

VRM + 20mV

Average V CS−A
0 mV

Average V CS−B
−20 mV

VIEA−A

Average V CS−C
+20 mV
VIEA−B
VIEA−C
0V

Figure 27. Effect of VRM Offset to Average VCS
Protections

FAN967x has lots of built−in protections, covering faults
on input voltage, output voltage, over current, and improper
IC operating conditions.
ILIMIT2, GC, and RLPK pins have pin−open protection.
VILIMIT2−OPEN, VGC−OPEN, and VRLPK−OPEN are relatedparameters for pin−open protection. ILIMIT1 pin does nothave the same open−circuit protection as ILIMIT2.
ILIMIT1 sets a threshold voltage of VRM, which already hasinternal highest value of 0.8 V. Since there is a highest VRM,
an open−circuit protection for ILIMIT1 is not necessary.
When protection is triggered, FAN967x shuts down its
OPFC and IEA signals. Soft start resets as well. FAN967x
resumes operation when fault condition is cleared.

www.onsemi.com
10AND9925/D
Table 2. Collection of Protections in FAN967x

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Category

Protections

Input
voltage

Brown in/out
Sag

Triggering condition

Start operating when input voltage is high enough.
Input voltage drops for a while.

AC−OFF

Input−voltage signal (IAC) is missing or too low.

FBPFC UVP

Output voltage is too low or FBPFC pin open.

FBPFC OVP

Output voltage is too high.

Overcurrent

ILIMIT1

Limit current command VRM.

ILIMIT2

Pulse−by−pulse current limiting for CS.

IC
operatingconndition

VEA−OFF

Low−power detection a.k.a. burst mode.

VDD−UVLO

Supply voltage is not high enough.

VDD−OVP

Supply voltage is too high.

Outputvoltage

OTP

Chip junction temperature is too high.

ILIMIT2
open

ILIMIT2 pin is opened.

GC open

GC pin is opened.

RLPK open

RLPK pin is opened.

References[1] FAN9672, Two−Channel Interleaved CCM PFC Controller, Data Sheet
https://www.onsemi.com/pub/Collateral/FAN9672−D.PDF[2] FAN9673, Three−Channel Interleaved CCM PFC Controller, Data Sheet
https://www.onsemi.com/pub/Collateral/FAN9673−D.PDF[3] AN4165/D, Design Guideline for a 5−kW 3−Channel Interleaved CCM PFC Using FAN9673
https://www.onsemi.com/pub/Collateral/AN4165−D.PDF[4] R. B. Ridley, B. H. Cho and F. C. Y. Lee, ”Analysis and interpretation of loop gains of multiloop−controlledswitching regulators (power supply circuits),” in IEEE Transactions on Power Electronics, vol. 3, no. 4, pp.
489−498, Oct. 1988.
[5] B. Bryant and M. K. Kazimierczuk, ”Small−signal duty cycle to inductor current transfer function for boost PWM
DC−DC converter in continuous conduction mode,” 2004 IEEE International Symposium on Circuits and Systems(IEEE Cat. No.04CH37512), 2004, pp. V−856−V−859 Vol.5.

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