Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT3111-KMC
DC-40Gbps Single-Channel CML-to-PCML Level ShifterExhibits low jitter and limited temperature variation over industrial temperature range

Fabricated in SiGe for high performance, yield, and reliability

Power consumption: 260mW

Custom CQFP 24-pin package

vee

Fully differential output PCML interface with on-chip single-ended 50Ohm termination to thepositive supply railgndvcc

Fully differential input CML interface with on-chip single-ended 50Ohm termination to ground

gnd



gnd

High-speed broadband digital signal level up-shifter

gnd

vee

gnd

gnd

inp

outp

ASNT3111

gnd

gnd

inn

outn

gnd

gnd

Rev.2.1.2

1

gnd

vcc

gnd

gnd

gnd

vee

vee

February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION

gnd
inp
innvcc505050outp
outn50vee

vcc

Fig. 1. Functional Block Diagram

The ASNT3111-KMC SiGe IC shown in Fig. 1 provides a voltage shift for high-speed data and clock
CML signals from the levels associated with negative power supplies to the levels associated withpositive power supplies.
The part’s inputs support the CML logic interface with on chip 50Ohm termination to gnd and may be
used differentially, AC/DC coupled, single-ended, or in any combination. In the first mode, the input
signal’s common mode voltage should comply with the specifications shown in ELECTRICAL
CHARACTERISTICS. In the second mode, the input termination provides the required common mode
voltage automatically. The part’s outputs support the PCML logic interface with on chip 50Ohm
termination to vcc and may be used differentially, AC/DC coupled, single-ended, or in any combination.
The differential DC signaling is recommended for optimal performance.
Fig. 2 and Fig. 3 below demonstrate the chip’s simulated performance.

Fig. 2. Simulated DC Transfer Function

Rev.2.1.2

2February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Fig. 3. 40Gbps Simulated Output Eye Diagrams at Different Conditions

POWER SUPPLY CONFIGURATIONThe chip operates from two independent power supplies related to gnd: negative vee=-3.3V and positivevcc=+3.3V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground.
Table 1. Absolute Maximum Ratings

Parameter
Min Max Units
Negative Supply Voltage (vee)-3.6
V
Positive Supply Voltage (vcc)+3.6
VPower Consumption
0.29
W
RF Input Voltage Swing (SE)1.0
V
Storage Temperature-40 +100ºC
Operational Humidity
1098%
Storage Humidity
1098%
Rev.2.1.2

3February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

TERMINAL FUNCTIONSTERMINAL

Namevcc
gnd

DESCRIPTIONType
CML Differential inputs with internal SE 50Ohm termination to gnd
input
PCML Differential outputs with internal SE 50Ohm termination to vcc.
output Require external SE 50Ohm termination to vcc
Supply and Termination Voltages
Description
Pin Number
Positive power supply (+3.3V)5, 15
External ground (0V)2, 3, 4, 6, 8, 10, 12, 14, 16, 17, 18, 20, 22, 24

vee

Negative power supply (-3.3V)

Nameinpinnoutpoutn

No.
2123
1191, 7, 13, 19

ELECTRICAL CHARACTERISTICSPARAMETERveegndvcc
Ignd
Ivcc
Power consumption
Junction temperature
Data rate
Swing
CM Voltage Level
Data rate
Logic “1” level
Logic “0” level
Rise/Fall times
Additive Jitter

Rev.2.1.2

MIN

TYP MAX UNIT
COMMENTS
General Parameters
-3.1
-3.3
-3.5
V
±6%
0.0
V
External ground
3.1
3.3
3.5
V
±6%
42mA
18mA
260mW
-2550
125°C
HS Input Data (inp/inn)
DC40Gbps
0.05
1.0V
Differential or SE, p-p
vcc-0.8vcc
VMust match for both inputs
HS Output Data (outp/outn)
DC40Gbps
Vvcc
vcc-0.4
VWith external 50Ohm DC termination
11ps
20%-80%<1ps
Peak-to-peak

4February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATIONThe chip die is housed in a custom 24-pin CQFP package shown in Fig. 4. Even though the package
provides a center heat slug located on the back side of the package to be used for heat dissipation,ADSANTEC does NOT recommend for this section to be soldered to the board. If the customer wishes
to solder it, it should be connected to the vcc plain that is ground for the negative supply or power for thepositive supply.

Fig. 4. CQFP 24-Pin Package Drawing (All Dimensions in mm)

Rev.2.1.2

5February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

The part’s identification label is ASNT3111-KMC. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

REVISION HISTORY
Revision
2.1.2
2.0.2
2.0.1

Date
02-2020
07-2019
03-2013

1.1.1

01-2013

1.0

11-2011

Rev.2.1.2

Changes
Updated Package Information
Updated Letterhead
Corrected title
Updated description
Added pin out diagram
Added power supply configuration section
Added absolute maximum ratings section
Revised electrical characteristics
Revised package information section
Added package mechanical drawing
Revised electrical characteristics section
Revised package information section
First release6

February 2020