Inverter Output Current Overshoot Suppression
during Fault Ride-through Operation for Threephase Grid-tied Inverter with Minimized Inductor
Satoshi Nagai, Hiroki Watanabe and Jun-ichi Itoh
Nagaoka University of Technology
Nagaoka, Niigata, Japansatoshi_nagai@stn.nagaokaut.ac.jp; hwatanabe@vos.nagaokaut.ac.jp; itoh@vos.nagaokaut.ac.jp

Abstract— This paper proposes an inverter output current
overshoot suppression technique for a three-phase grid-tied
inverter with a minimized inductor during a fault-ride throughoperation. The inverter output current overshoots at the gridvoltage drop or recovery with the low inductance. In order tosuppress the current overshoot, the inverter output vector which
reduces the slope of the output current overshoot toapproximately zero is derived from the equations of theinstantaneous active and reactive current at the voltage drop
and recovery. Moreover, it is impossible to detect the gridvoltage phase during grid voltage drop whose voltage is down to
0 V. Thus, a maximum-medium-minimum voltage detection andvoltage pole detection circuit is applied in order to detect thegrid voltage sectors. Furthermore, the three-phase inverter
outputs nearly equals the grid voltage with the look-up table
which depends on the grid voltage sector at the grid voltage
recovery. As experimental results, the inductor current
overshoot rate is reduced by 49% at the voltage recovery withthe proposed voltage vector output compared to the counter
voltage vector output.
Keywords—three-phase grid-tied inverter, low inductance,
fault ride-through, current overshoot

I. INTRODUCTION
In recent years, renewable energy such as photovoltaics(PV), wind turbine and fuel cell systems have been actively
studied for energy saving to reduce fossil energy sources [1][3]. In order to transmit the renewable energy to the grid, agrid-tied inverter is used. The grid-tied inverter is required toreduce the size. In particular, the inverter-side inductors
occupy the majority of the inverter volume. Thus, theinductors are required to reduce the size. High-frequency
inverter operation with Silicon carbide (SiC) or Gallium
nitride (GaN) devices reduces the inductance under the same
condition of the current ripple, resulting in the reduction of theinductor volume. However, the low inductance leads to thedecrease in the disturbance suppression performance of thecurrent controller. The inverter output current distorts due tothe low disturbance suppression performance. The inverter
output current distortion is caused by the disturbance such as
the dead-time induced error voltage. Therefore, the increaseof the disturbance suppression performance is required to thegrid-tied inverter with the low inductance [4].
On the other hand, the grid-tied inverter is required to meeta fault ride-through (FRT) operation during the voltage sag[5]-[13]. However, low inductance of the grid-tied invertercauses the inverter output current overshoot at the grid voltage
drop and recovery. The inverter output current overshoot leads
to overcurrent protection of the inverter, resulting in the
disconnection between the inverter and the grid during thevoltage sag. In addition, the maximum inverter output current
at the grid voltage recovery has to be suppressed less than

150% of the rated inverter output current peak value in thesteady-state operation [12]. Therefore, it is necessary to
suppress the inverter output current overshoot during thevoltage sag. Several conventional FRT operations have been
proposed, in which the DC-link voltage control, and the output
power control method are applied during the voltage sag [5][6]. However, these conventional methods have notconsidered the inverter output current overshoot at the voltage
drop and recovery. The FRT operation with the counter
voltage vector output operation has been proposed [14]. The
counter voltage vector output operation suppresses theinductor current overshoot with the reverse voltage vector
output for the inductor current at the grid voltage drop andrecovery. The inductor current is instantaneously reduced withthe counter voltage vector output. Furthermore, the inverter
operation is continued by releasing the counter voltage vector
output after one carrier period. However, the current
overshoot occurs in the inductor due to the transient response
by following current command from reduced current with thecounter voltage vector output. In addition, it is impossible todetect the grid voltage during zero-voltage ride-through(ZVRT) because the grid voltage is 0 V. Thus, at the gridvoltage recovery, the current overshoot occurs in the inductor
because the inverter cannot output the voltage considering thegrid voltage. Therefore, in order to achieve the ZVRT
operation and suppress the current overshoot at the gridvoltage recovery, it is necessary to synchronize quickly thegrid and inverter output voltage at the voltage recovery.
This paper proposes a control method for three-phase gridtied inverter output vectors that achieves the suppression of
the inverter output current overshoot at the voltage drop andrecovery. Moreover, the current overshoot suppression
method is proposed when the phase information detection
failure occurs in the phase locked loop (PLL) output. The
proposed method uses a three-phase maximum-mediumminimum voltage detection and voltage pole detection circuit.
The circuits detect the grid voltage phase area (sector) in every
30 deg. The inductor current overshoot is suppressed by the
inverter output voltage in each phase with the detected sector
and the voltage recovery detection signal. The original idea of
this paper is that the inverter output current overshoot issuppressed by changing the inverter output vector dependingon the condition of the grid voltage such as the voltage dropor recovery. In addition, the inductor current overshoot issuppressed at the grid voltage recovery in the ZVRT operationeven when the grid voltage phase is not detected. The inverter
output vector is derived by the instantaneous active andreactive current during the voltage sag. Moreover, the inverter
output vector is controlled so that the slope of the inverter
output current becomes zero after the voltage drop or recovery.
The proposed control method is verified by a 1-kW prototype.

II. CONVENTIONAL FRT OPERATION

Output power: 1 kw

A. FRT operation with current controller
Figure 1 shows a three-phase grid-tied inverter circuit. The
three-phase two level inverter is evaluated in this paper. Notethat the inductor impedance %Z is 0.38% for the output
impedance of the inverter to reduce the size. The inductanceis designed in [14].

S1
Vdc
400 V

Figure 2 shows a control block diagram of a conventional
current controller for the grid-tied inverter. Note that PI is thecontroller, iL is the inductor current, iL_det is the inductor
current detection value, iL* is the inductor current command,vac is the grid voltage, vac_det is the grid voltage detection value,vdead is the dead-time error voltage, s is Laplace operator andTdelay is the detection delay time. Moreover, the inverter output
switches to the reactive current from the active current whenthe voltage sag is detected. In addition, Digital Signal
Processor (DSP) is used in the conventional current control.
However, the control of DSP has the sampling and detection
delay time. Thus, the inductor current overshoots at thevoltage drop or recovery due to the control and detection delay
time and the low inductance.

vˆdis c
 vdis _ PI  c LiL _ det   c LiL _ det s  cB. Counter voltage vector output method
The counter voltage vector output is applied to suppress
the current overshoot at the voltage drop and recovery [14].
The principal of the counter voltage vector output is expressed
as follows. The circuit equation of the three-phase inverter isexpressed asv p   pL  L  i p  vac v      q    L pL   iq   0 (2),where vp and vq are the instantaneous active and reactive
voltages of the inverter, ip and iq are the instantaneous active
and reactive currents of the inverter, L is the inductance, vac is
the grid voltage,  is the grid angular frequency, p is the

S4

iLb

L

iLc

L

vac
200 Vrms(Line to line)

S6

Controller
DSP
vac_det
iL* +

+

PI

-

iL_dete+

Main circuit
+ v
vdead
+ vdis ac
1
Vdc +
sL

1
V dc

iL

 sTdelay

Figure 2. Control block diagram of conventional current controller. The
current control with DSP has the sampling and detection delay time.
Controller
DSP
iL* +
iL_detwhere c is the cutoff angular frequency of DOB, vdis_PI is
additional value of the PI output and the DOB output. The
high-gain DOB is implemented in a high-speed controller as
Field-Programmable Gate-Array (FPGA) to increase thedisturbance suppression performance. The inverter output
current total harmonic distortion (THD) with the high-gain
DOB is achieved below 5% during normal operation with low
inductance [4]. The high-gain DOB implemented in FPGA
achieves the high cutoff frequency operation. Thus, thedisturbance for the inverter current controller is estimated in
wideband. Note that the grid voltage is compensated by thefeedforward compensation in the FPGA. However, thisconventional control method leads to the inductor current
overshoot due to the detection and sampling delay time of thegrid voltage at the voltage drop or recovery.

S2

L: %Z = 0.38%

Switching freq.: 100 kHz
Figure 1. Three-phase grid-tied inverter with minimized inductor. The
inductor impedance %Z is 0.38% of the inverter normalized impedance.
(%Z is inductor impedance ratio for the output impedance of theinverter.)Figure 3 shows the conventional current controller
applying the high-gain disturbance observer (DOB) [4], [15],[16]. The disturbance estimation voltage vˆdis by DOB isexpressed as

S5 iLaS3-

PI

Main circuit
+ vac
vdead
+ vdis1
V +vac_detFPGA
vdis_PI + + 1+
dc+ vˆdis
V dc
+
+ c
+
- s  ccL
iL_detiLsLe

 sTdelay

Figure 3. Control block diagram of conventional current controller withhigh-gain DOB. The high-gain DOB is implemented in FPGA tocompensate the disturbance with wideband.

differential operator, and the power factor is unity. Note thatthe resistance of the inductor is ignored.
First, considering the inverter operation at the voltage drop.
In order to satisfy the grid code even at the worst case, theZVRT operation is evaluated, where vac in (2) becomes 0 V
from the grid voltage peak value at the voltage drop. Thus, theactive and reactive inductor currents ip and iq are expressed as



ip 

vp

L

sin t vqL1  cos t   i p 0 cos t  iq 0 sin t



iq 

vp

L

1  cos t  vqL i p 0 sin t  iq 0 cos tsin twhere t is time, ip0 and iq0 are the active and reactive inductor
currents at the steady-state operation. Differentiating (3) and(4), the current slope of ip at the moment of the voltage drop
becomes positive, whereas the current slope of iq becomesapproximately zero. After the moment of the voltage drop, inorder to minimize the current overshoot, the instantaneous
active and reactive inverter output voltages vpfrt, vqfrt arecontrolled such that the current slope of ip after the moment of
the voltage drop becomes negative as much as possible,
whereas the current slope of iq should be maintained at zero.
Thus, the instantaneous active and reactive inverter output
voltages vpfrt, vqfrt are derived from following equations

di p



L

cos t 

vqfrt
Lsin t(0 1 0) b

(5)

dt



v pfrtsin t 

vqfrt

cos tLL i p 0 cos t  iq 0 sin t  0(1 1 1)(0 1 1) vpfrt(6).

Solving (5) and (6) with vpfrt, vqfrt as variables, theinstantaneous active and reactive inverter output voltages
become as vpfrt =  , vqfrt = -Lip0. However, the inverter
output voltage is limited to Vdc/2. In addition, vqfrt nearly
equals to zero when the low inductance is applied. Therefore,
the inverter output current reduction effectiveness becomesthe maximum, when the instantaneous active and reactive
inverter output voltage are set as vpfrt = -Vdc/2, vqfrt = 0.
Consequently, the output voltage vector is equal to reverse
vector for the inverter output current (the counter voltage
vector).



iq 


vp

vq

sin t 
1  cos t 
L
L

v
 ac sin t  i p 0 cos t  iq 0 sin t
L

vp

(7)

v

1  cos t   q sin t

LLv
 ac 1  cos t   i p 0 sin t  iq 0 cos t
L

(8),

where the current slope of the active current ip at the momentof the voltage recovery is negative, whereas the slope of thereactive current iq is approximately zero. Similarly, after the
moment of the voltage recovery, in order to minimize thecurrent overshoot, the instantaneous active and reactive
inverter output voltages vpfrt, vqfrt are controlled such that thecurrent slope of ip after the moment of the voltage recovery
becomes positive as much as possible, whereas the current
slope of iq should be maintained at zero. Therefore, the active
and reactive inverter output voltage vpfrt and vqfrt are derived asfollowing equations





di p
dt

diq
dt





v pfrtvqfrt

vac
cos t
L
LL i p 0 sin t  iq 0 cos t  v pfrtcos t 

vqfrt

sin t vacsin tL
LL i p 0 cos t  iq 0 sin t  0
sin t cos t 

(9)

(10).

ip

vac

a
(1 0 0)(0 0 0)(0 0 1)(1 0 1)(a) Voltage drop.

(0 1 0) b(1 1 0)(1 1 1) vpfrt
ip(0 1 1)

Second, considering the inverter operation at the voltage
recovery. In order to satisfy the grid code even at the worst
case, the ZVRT operation is evaluated, where vac in (2)changes from 0 V to the grid voltage peak value at the voltage
recovery. Similar to the inverter operation at the voltage drop,
the active and reactive currents ip and iq at the voltage recovery
are expressed asip (1 1 0) i p 0 sin t  iq 0 cos t  diq

v pfrtdtvac(0 0 0)(0 0 1)a(1 0 0)(1 0 1)(b) Voltage recovery.
Figure 4. Counter voltage vector output for FRT operation. The counter
voltage vector output achieves the inverter output current reduction at
the voltage drop and recovery.

Solving (9) and (10) with vpfrt, vqfrt as variables, theinstantaneous active and reactive inverter output voltages
become as vpfrt = Vdc/2, vqfrt = 0. The output voltage vector
equals to the counter voltage vector.
Figure 4 shows the vector diagram of the counter voltage
vector output at the grid voltage drop and recovery. The
inverter output voltage becomes the reverse vector against theinverter output current vector at the voltage drop and recovery.
In particular, the counter voltage vector output is achieved by
the momentary gate-block, when the grid voltage fluctuation
is detected. After the momentary gate-block is completed, thecounter voltage vector output is released to continue theinverter operation during the voltage sag. However, thecurrent overshoot might still occur in the inductor due to thetransient response because the instantaneous inverter output
current is reduced by applying the counter voltage vector
output at the voltage drop and recovery [14]. In the otherwords, only the momentary gate-block cannot suppress thecurrent overshoot.
III. PROPOSED VOLTAGE VECTOR OUTPUT FOR FRTOPERATION
In order to suppress the overshoot current due to thetransient response after the completion of the momentary gateblock, the inverter output voltage vector at the voltage
recovery is operated as that the differential of the inverter
output current is zero in (9), (10). Thus, equation (9) is
modified as follows



di p
dt



v pfrtvqfrt

vac
cos t
L
LL i p 0 sin t  iq 0 cos t  0
cos t 

sin t 

IV. VOLTAGE RECOVERY DETECTION METHODAFTER GRID-PHASE DETECTION FAILURE
It is necessary to detect the grid voltage phase at the gridvoltage recovery in order to carry out the proposed vector
output. However, it is impossible to synchronize the gridphase by applying PLL during voltage sag whose voltage isdown to 0 V. Thus, the grid phase after the grid recovery
cannot be predicted. Therefore, a maximum-mediumminimum voltage detection and voltage pole detection circuit
is applied to detect the grid phase after the grid voltage
recovery.
Table I shows the grid voltage sector with the maximummedium-minimum voltage detection and voltage pole
detection circuit, whereas Figure 6 shows the proposed
inverter output voltage in each phase when the grid voltage
recovers at the sector shown in Table I. Note that Max. is the
maximum voltage phase among three-phase voltages, Min. is
the minimum voltage phase, Mid. pos. is the positive pole inmedium voltage phase, and Mid. neg. is the negative pole inmedium voltage phase. Furthermore, the number of sector istwelve by dividing every 30 deg. Hence, the inductor currentb phasegrid voltage

c phasegrid voltage

1000Sector 9

Sector 8a phase5 ms/div
Inverter voltage

Sector 7

1.0

b phasec phaseInverter voltage Inverter voltage

Sector 6-200

Sector 5-100

Sector 4

Figure 5 shows the proposed inverter output voltage vector
at the voltage recovery. The inverter output voltage vpfrt issame as the grid voltage at the voltage recovery. This control
ensures that the differential of the inverter output current iszero at the grid voltage recovery. Thus, the inverter output
current overshoot is possible to suppress without the
momentary gate-block operation. On the other hand,considering the inverter operation at the voltage drop, in
which the active and reactive inverter output voltage vector
should become vpfrt = vac, vqfrt = 0 according to (5), (6).
However, it is impossible to obtain the voltage drop value inadvance. Therefore, the counter voltage vector output is still
applied at the voltage drop. However, in order to suppress thecurrent overshoot after releasing the counter voltage vector
output, the integrator of DOB in Fig. 3 is initialized to reduce
the error between the actual and estimated disturbance value.

a phase
200 grid voltage

Sector 3

Considering the inverter operation at the voltage recovery, inwhich the active and reactive inverter output voltage vector
should become vpfrt = vac, vqfrt = 0 according to (10), (11).
Therefore, in order to suppress the current overshoot andtransient response at the voltage recovery, the inverter output
voltage should output same as the grid voltage value. However,
the inverter output voltage is affected by the dead-time error
voltage in practical. Thus, in order to output the inverter output
voltage which equals to vac, the inverter output voltage
command should consider the dead-time error voltage vdead forthe grid voltage vac.

c phaseSector 2

Figure 5. Proposed voltage vector output for FRT operation at thevoltage recovery. The proposed voltage vector suppresses the current
overshoot and the transient response at the voltage recovery.

Sector 1(1 0 1)

Sector 12(1 0 0)

Sector 11(0 0 1)(0 0 0)ab phaseSector 10

ip

vac

Duty ratio for vacabcSector 1
Max. Mid. neg. Min.
1
-1/2  3 / 2Max. Mid. pos. Min.
Sector 2
1/2
-1
3/2
1/2
-1
Sector 3 Mid. pos. Max.
Min.
3/2
Sector 4 Mid. neg. Max.
-1/2
1
Min.
 3/2
-1/2
Max. Mid. neg.  3 / 2
Sector 5
1
Min.
1/2
Min.
Max. Mid. pos. -1
Sector 6
3/2
Min. Mid. pos. Max.
1/2
-1
Sector 7
3/2
Min. Mid. neg. Max.  3 / 2 -1/2
1
Sector 8
Sector 9 Mid. neg. Min.
-1/2  3 / 2
1
Max.
Sector 10 Mid. pos. Min.
Max.
1/2
-1
3/2
-1
Min. Mid. pos. 3 / 2
Sector 11 Max.
1/2
1Min. Mid. neg.
Sector 12 Max.
 3 / 2 -1/2

Sector No. a phase

Grid and inverter voltage [V](1 1 1) vpfrt(0 1 1)

Table I. Proposed output vector at grid voltage recovery.

(1 1 0)

Sector area
detection signal(0 1 0) b

0.0
Figure 6. Concept of inverter output voltage for inductor current
overshoot reduction.

overshoot at the voltage recovery is suppressed with theinverter output voltage in Table I. The inverter output voltage
value in Table I is near the grid voltage value at the voltage
recovery. Moreover, the inverter output voltage in each phasefor every sector is maximum value of the grid voltage in eachphase of every sector as Fig. 6. As the results, the inverter
output voltage is kept up higher than the grid voltage, resulting
the current overshoot is suppressed.
Figure 7 shows the flowchart for the inverter operation
with the proposed voltage vector output to suppress the current
overshoot. The sector for the grid voltage is divided to twelve
areas with the maximum-medium-minimum voltage detection
and voltage pole detection as Table I. Moreover, the duty ratioof the inverter output voltage is derived for every sector as
Table I. Furthermore, the proposed inverter output voltage is
outputted when the grid voltage recovery is detected, thecounter voltage vector is outputted when the grid voltage dropis detected, and the steady state operation is carried out when
the grid voltage drop and recovery are not detected.
V. PROPOSED FRT OPERATION METHOD FOR
CURRENT OVERSHOOT SUPPRESSION
Figure 8 shows the control block diagram of the proposed
FRT control with minimized inductor, corresponding the gridphase detection failure during the voltage sag. Note that vx isthe voltage detection value of the each phase, vsag_x is thedetection signal of grid disturbance in each phase (x = a, b, c),iLd*, iLq* is the current command in dq-axis, iLd_det, iLq_det is theinductor current detection value in dq-axis, vacd_det, vacq_det isthe grid voltage detection value in dq-axis, and Vac is the gridphase voltage peak. The current control is achieved by the PI
controller. In addition, the high-gain DOB which is
implemented in FPGA is applied to compensate thedisturbance for the current controller such as the dead-timeerror voltage as Fig. 3. The grid voltage drop and recovery
detection signals drop_det and recover_det become one at thevoltage drop and recovery. Moreover, the voltage drop andrecovery are detected with the analog circuit at high speed.
Thus, the voltage drop or recovery operation is divided bythese signals. The counter voltage vector output is carried out
by the voltage drop signal drop_det. Moreover, proposed
voltage vector output is carried out by the voltage recovery
signal recover_det. The integrator of DOB is initialized tozero at the voltage drop and recovery in order to reduce thecurrent overshoot. On the other hand, the inverter output
vector to reduce the current overshoot is outputted by referring
the sector detection in Table I with the grid voltage recovery
signal recover_det and the table of MUX1 in Fig. 8. The

output period of inverter vector suppressing current overshootis short enough for the grid frequency. In this paper, the period
is two cycles of switching period (switching period is 10 s).
The operation period of proposed vector includes the wait time
to update in order that the grid voltage detection value
becomes the actual grid voltage value after releasing the
proposed vector operation. The wait time to update the gridvoltage detection is as the grid voltage detection delay time.
Figure 9 shows the voltage sag detection circuit and thevoltage drop and recovery signal generator for the proposed
voltage vector output operation. Note that vx is the phasevoltage (x = a, b, c), Vac_th is the threshold of voltage sag
detection for a high-pass filter (HPF) output. The voltage sag
detection circuit is composed in analog circuit such as HPF
and a comparator. The voltage sag is detected at high speed by
the analog circuit. Furthermore, the voltage drop and recovery
signals drop_det and recover_det are generated in the FPGA
using the voltage sag detection signal vsag_x and voltage
detection value of q axis vacq_det. In addition, the proposed
voltage vector output period is set to two cycle of the carrier
period to continue the inverter operation. Thus, application of
the analog circuit and FPGA reduce the delay time of the
proposed voltage vector output operation.

START
Detection of Max., Mid.,
Min., and polarity
for grid voltage

Figure 10 shows the operation waveform of the voltage
sag detection circuit and the grid voltage drop and recovery
signals generator. The HPF output HPFout overshoots at thegrid voltage fluctuation. In addition, the HPF output HPFout iscompared with the threshold Vac_th. Thus, the voltage-sag
detection circuit output vsag_x becomes the low signal at thevoltage drop or recovery. After that, the voltage drop andrecovery signals drop_det and recover_det are generated in
the FPGA by the low signal of voltage-sag detection circuit
output vsag_x and voltage detection value of q axis vacq_det as in
MUX2 of Fig. 8.

Detection of grid voltage
sector No. from Table. I
Decision of output voltage
duty ratio from sector No.
in Table. I

YES
Output of proposed vector
for current-overshootsuppression

NO
NO

Detecting gridvoltage drop
YES
Counter voltage
output operation

Steady-state
operation

VI. EXPERIMENTAL RESULTS
Table II shows the experimental conditions for the FRT
operations. The inductance designed in [14] is applied to theprototype. The carrier frequency is 100 kHz, whereas the
sampling frequency of the current controller (Auto current

END

Figure 7. Flowchart for proposed voltage vector output to suppress
current overshoot at voltage drop and recovery.
MUX1
2
sector1
Vacda_frt_0
Vac 3 / 2
db_frt_0 -Vac/2
Vac/2
-Vac
dc_frt_0 Vac 3 / 2

3
Vac/2

va, vb, vc
3

Vac 3 / 2-Vac

6
sector4
5-Vac
da_frt_0 -Vac/2 Vac 3 / 2
db_frt_0
Vac
Vac
Vac 3 / 2
dc_frt_0 Vac 3 / 2 -Vac/2
Vac/2
8
sector97-Vac
da_frt_0
Vac 3 / 2 -Vac/2
db_frt_0-Vac/2 Vac 3 / 2
Vac/2
-Vac
Vac
dc_frt_0 Vac 3 / 2
12sector
10
11
Vac/2
Vac
da_frt_0
Vac 3 / 2
db_frt_0-Vac-VacVac 3 / 2
dc_frt_0 Vac 3 / 2-Vac/2Vac/2

3

Detection board

iLd*

+
-

PI

iLd_det

iLq*

+
-

PI

iLq_det
DSP

MUX2
MUX3
0
vsag_x1 recover_det 0 1
vacq_det< vac*0.8  vac*0.8 da 'da da_frt0
drop_det
0
1'
ddb db_frtb1
00
recover_det
dc 'dc dc_frt- : Don’t care

MUX2

recover_det

vacq_det+-

vacd_det+ vdis_PI_d + ++ vˆdis _ d
iLd_det dq
DOB eq. (1)/3fvacq_det+ vdis_PI_q + ++ vˆdis _ q
iLq_det
DOB eq. (1)va, vb, vc
3

FPGA

drop_det

vsag_xVoltage-sag
detection circuit

Max. Mid. Min.
detection
Polarity
detection
Detection board

+
-

S1
S2
da '

db

S3
S4

MUX3

db '

db_frt
+
-

not

da

da_frt

S5

dc

S6
dc '
recover_det

dc_frtCarrier

Voltage sector
detection

Detecting gridvoltage recovery

sectorVac

da_frt_0+-

db_frt_0+-

dc_frt_0

+
-

MUX1

sectorda_frtdb_frtdc_frtCarrier

Figure 8. Control block diagram of proposed FRT control with minimized inductor corresponding to detection failure of grid phase information. The
current overshoot at the voltage recovery is suppressed with the table of MUX1 and the voltage recovery detection signal.

Figure 12 shows the magnified waveform at the voltage
drop with the conventional FRT operation applying the highgain DOB, and the counter voltage vector output. Note thatthe counter voltage vector output is applied in the proposed
FRT operation at the voltage drop operation. In Fig. 12 (a),the current overshoot occurs in the inductor at the moment of
the voltage drop with the conventional FRT operation
applying the high-gain DOB. Furthermore, inverter operation
stops due to the large current overshoot. The current
overshoot occurs in the inductor due to the delay time for the
update of inverter output voltage considering the
instantaneous value of the grid voltage at the voltage drop.
The delay time for the update of inverter output voltage iscaused by the detection and sampling delay time and thecalculation delay time of controller. On the other hand, theinductor current overshoot at the voltage drop is suppressedby the application of the counter voltage vector output. The
delay time for the update of inverter output voltage is reducedwith the counter voltage vector output applying the voltage
drop detection with the analog circuit and FPGA. Thus, thecurrent overshoot with the counter voltage vector output issuppressed by the high speed operation compared with theconventional FRT operation applying the high-gain DOB. In
particular, the inductor current overshoot rate with two
methods at the voltage drop are 335% (conventional FRT
operation with the high-gain DOB) and 118% (counter
voltage vector output) of the rated inductor current peak,
respectively. The current overshoot is reduced by 217%.
Figures 13 and 14 show the magnified waveform at thevoltage recovery with the counter voltage vector output, andthe proposed voltage vector output. In Fig. 13, the inductor
current is reduced by the counter voltage vector output at thevoltage recovery. However, the current overshoot occurs in
the inductor after releasing the counter voltage vector. The

HPF

Vac_th++-FPGA
vsag_xvacq_det

MUX2-Vac_thdrop_det
recover_det

MUX2 in Fig. 8.
Up edge periodof output signal(Cutoff frequency: 800 Hz): Two cycle ofcarrier period
Figure 9. Voltage sag detection circuit and voltage drop and recovery
signal generator. The voltage drop and recovery signals are generated at
fast speed by applying the analog circuit and FPGA.
vx+

HPFoutGrid voltage [V]

400
200

Voltage sag

0-200

HPF output andGate-block threshold-400
HPF output

Positive thresholdfor voltage sag

Negative thresholdfor voltage sag

1.0

drop_det
signalFigure 11 shows the experimental results of the ZVRT
operations with the three methods. The three methods are theconventional FRT operation with the high-gain DOB, thecounter voltage vector output, and the proposed voltage vector
output. Note that the grid voltage drop and recovery occur inthe grid at the a phase voltage peak. In Fig. 11 (a), the inverter
output stops at the voltage drop with the conventional FRT
operation with the high-gain DOB. However, In both Fig. 11(b) and (c), the inverter operation is possible to continue witheither the counter voltage vector output or the proposed
voltage vector output at the voltage drop and recovery.
However, the current overshoot is different in each method.

Analogcircuit

The signal becomes highat the grid voltage drop.

0.0
1.0

recover_det
signalregulator: ACR) is 20 kHz which is implemented in DSP, andthe sampling frequency of the high-gain DOB is 100 kHz
which is implemented in FPGA. Furthermore, the detection
delay time of the voltage drop and recovery is less than 6.0 s.
In this experiment, ZVRT operations are verified with theconventional FRT operation applying the high-gain DOB, thecounter voltage vector output, and the proposed voltage vector
output. Moreover, the grid voltage drop and recovery
occurrence at the voltage peak is evaluated in order to verify
the worst condition for the current overshoot rate, where theinductor current is negative direction peak value when thevoltage recovery occurs in the grid at the positive peak value.
In addition, the current controller cannot keep the phase
information at the voltage recovery due to the ZVRT operation
causing error between the PLL information and the gridvoltage phase without grid voltage detection value.

0.0

The signal becomes high at
the grid voltage recovery.
10 ms/div

Figure 10. Operation of voltage sag detection circuit and voltage drop
and recovery signals generator.
Table II. Experimental conditions
Ang. fre. of ACR n

Output power Pout 1 kW
DC link vol. Vdc 400 V

4000 rad/s

Samp. fre. of ACR fsamp 20 kHz
Grid voltage vac 200 Vrms Samp. fre. of DOB fso 100 kHz(line to line)
Cutoff fre. of DOB fc
2 kHz
L 0.48 mH
Conv.-side
tdead 500 ns(0.38%) Dead time
Induc. (%Z)
C 2.2 F
Filter cap.
tsag_d < 6.0 sVolt. sag det.
Carrier fre.
fcry 100 kHz delay timecurrent overshoot occurs in the inductor due to that the
reduced inductor current follows the current command. Thus,
the transient response should be reduced to suppress thecurrent overshoot. The inductor current overshoot rates withthe counter voltage vector output at each phase voltage
recovery operation are 169%, 171%, and 170%. Moreover, thecounter voltage vector output operation does not meet the FRT
requirements due to that the current overshoot rate exceeds
150%. On the other hand, the inductor current overshoot in
Fig. 14 is suppressed by the proposed voltage vector output
compared with Fig. 13. The proposed voltage vector is
outputted approximately as same as the grid voltage at the gridvoltage recovery. Thus, the inductor current is kept because
the inductor current slope becomes zero. Therefore, thetransient response and the current overshoot at the voltage
recovery are suppressed by the proposed method. The
inductor current overshoot rates with the proposed method ateach phase voltage recovery operation are 123%, 132%, andVoltage dropa phase

Grid voltage 100 V/div00c phase

Inductor current 5 A/div
0

Grid voltage 100 V/divb phasea phaseMaximum current
14.2 A (355%)c phase

Inductor current 5 A/div0b phase250 s/div

100 ms/div(a) Conventional FRT operation with high-gain DOB.
Voltage drop(a) Conventional FRT operation with high-gain DOB.
a phase

Grid voltage 100 V/div00c phase

Inductor current 5 A/div
0

Grid voltage 100 V/divb phasea phaseMaximum current 4.73 A (118%)0b phaseVoltage recovery

Inductor current 5 A/div
250 s/div

100 ms/div(b) Conventional FRT operation with counter voltage vector output.
Voltage dropc phase(b) With counter voltage vector output.
Figure 12. Experimental results at the a phase voltage drop operation.
The inductor current overshoot is suppressed with the counter voltage
vector output.

Grid voltage 100 V/div

the current overshoot less than 150% at the voltage recovery.
Therefore, the validity of the proposed method was confirmedwith the experimental results.

0

Inductor current 5 A/div

In future work, the verification of the asymmetricalvoltage sag operation will be considered.
REFERENCES

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Voltage recovery

100 ms/div(c) Proposed voltage vector output operation.
Figure 11. Experimental results for the ZVRT operation at the a phasevoltage drop and recovery. The counter voltage vector output and the
proposed voltage vector output continue the inverter output during thevoltage sag.

131%. Hence, the proposed FRT operation meets the FRT
requirements due to that the current overshoot rate is less than
150%. Furthermore, the current overshoot rates with theproposed FRT operation at each phase voltage recovery
operation are reduced by 46% (a phase), 39% (b phase), and
39% (c phase).

[2]

[3]

[4]

VII. CONCLUSION
This paper proposed the inductor current overshootsuppression method at the grid voltage recovery with theinverter output vector considering the transient response.
Moreover, the current overshoot suppression method was
proposed when the phase information detection failure occurs
in the PLL output. The inductor current overshoot rate was
reduced by 46% at the voltage recovery with the proposed
FRT operation compared to the counter voltage vector output.
Moreover, the proposed method met the FRT requirements as

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250 s/div(b) b phase voltage recovery operation.

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