ICG-1020S
Miniature Dual-Axis OIS-Optimized MEMS Gyroscope
GENERAL DESCRIPTIONAPPLICATIONSThe ICG-1020S dual-axis MEMS angular rate sensor isdesigned for optical image stabilization (OIS) applications insmartphone camera modules and other mobile devices.



The ICG-1020S supports up to 32 kHz ODR for backward
compatibility to other InvenSense dedicated OIS gyroscopeproducts. This device provides extremely low RMS noise as
well as noise density.

FEATURESThe high-resolution gyros support a programmable full-scale
range of ±46.5 dps to ±374 degrees/sec, fast sample rate at
up to 32 KHz, low phase delay including a fast 20 MHz SPI
interface, very low rate noise at 4 mdps/√Hz, and extremely
low power consumption at 2.5 mA. Precise sensitivity control
allows a calibration-less strategy for gyroscope to saveproduction cost and time by eliminating the shake table.

AXES
X,Y

TEMP RANGE-40°C to +85°C

Small 2.3 x 2.3 x 0.65 mm LGA Package
Very Low 4 mdps/√Hz Rate Noise
Extremely tight sensitivity eliminates OIS dynamic
calibration
LPF with 40, 80, 160, 250 and 500 Hz settings
Programmable high-pass filters at 0.05 to 10 Hz toremove offset drift due to temperature & PCB warp
Independent ODR v. LPF selection for the most
optimized performance
Narrow FSR Range from ±46.5 dps to ±374 dps
High Resolution at up to 700 LSB/(º/s)
Fast Start Up Time; Sleep to Ready at 35 ms
SPI (3 & 4 Wire) Interface
Fast 20 MHz SPI Interface
Temperature sensor for offset temp compensation
Wide 1.7 V to 3.6 V Supply Voltage Range
Low 5 mW Active Power & 6μA Sleep Mode
Self-test allows quick gyro functionally check
High 10,000g Shock SurvivabilityORDERING INFORMATIONPART
ICG-1020S

Smart Phone Camera Modules
Digital Still Camera and Video Cameras
High Resolution / Low Noise Applications

PACKAGE
12-Pin LGA†Denotes RoHS and Green-Compliant Package

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TYPICAL OPERATING CIRCUITBLOCK DIAGRAM
VDD
CLOCK
Gen

POR

Factory
Test Modes

OTP Factory
Calibration
SPI SLAVEREGOUT

GND
Single
XY
Gyro
Drive

CV

ADC

Gyro Digital Filter

CV

ADC

Gyro Digital Filter

SENSOROUTPUT

INTC

NC

CSN
SDO
SDI / SDIO
SCLK

INT

12

NC

11

VDD

10

INT

1

9

CSN

2

8

RSV-G

3

7

REGS
Temp
SensorADC

Temp Sensor Digital Filter
StatusRegisters

Automatic Gain
Control

ChargePump

Self test

Reference
Gen

Voltage
Regulator

InvenSense reserves the right to change the detailspecifications as may be required to permit
improvements in the design of its products.

Trims andconfig ckts

Control
Registers

InvenSense Inc.
1745 Technology Drive, San Jose, CA 95110 U.S.A+1(408) 988–7339
www.invensense.com

4

5

6

SDO

SDI/SDIOSCLKRESV-G

C2
0.1µF, ±10%
10V

REGOUT

Document Number: DS-000149
Revision: 1.0
Release Date: 07/01/2016

C1
0.1µF, ±10%
5V

ICG-1020S
TABLE OF CONTENTS
General Description ................................................................................................................................................................................ 1
Ordering Information ............................................................................................................................................................................. 1
Block Diagram ........................................................................................................................................................................................ 1
Applications............................................................................................................................................................................................ 1
Features ................................................................................................................................................................................................. 1
Typical Operating Circuit ........................................................................................................................................................................ 1
1.

Introduction...............................................................................................................................................................................4
1.1

Purpose and Scope ..................................................................................................................................................................... 4

1.2

Product Overview ....................................................................................................................................................................... 4

1.3

Applications................................................................................................................................................................................ 4

2.

Features .....................................................................................................................................................................................5

3.

Electrical Characteristics ............................................................................................................................................................6
3.1

4.

Timing Characteristics ................................................................................................................................................................8
4.1

5.

6.

7.

Absolute Maximum Ratings ....................................................................................................................................................... 7

SPI Timing Diagrams (4- wire and 3-wire) .................................................................................................................................. 8

Application Information........................................................................................................................................................... 10
5.1

Pin Description ......................................................................................................................................................................... 10

5.2

Pin Configuration ..................................................................................................................................................................... 10

5.3

Typical Operating Circuit .......................................................................................................................................................... 11

5.3

Block Diagram .......................................................................................................................................................................... 11

5.5

System Bus Logic Levels ........................................................................................................................................................... 12

5.6

Digital Filter setting and performance ..................................................................................................................................... 13

Digital Interface ....................................................................................................................................................................... 14
6.1

SPI Interface ............................................................................................................................................................................. 14

6.2

SPI Operation ........................................................................................................................................................................... 14

Package Information ................................................................................................................................................................ 15
7.1

Part Number Identification ...................................................................................................................................................... 16

8.

Register Map ........................................................................................................................................................................... 17

9.

Register Descriptions ............................................................................................................................................................... 19
9.1

Registers 02, 09, 14-18, 112-116 - X and Y Axes Digital Low Pass Filter Coefficients ............................................................... 19

9.2

Registers 19 to 22 – Gyroscope offset adjustment ................................................................................................................... 20

9.3

Register 25 – Sample Rate Divider ........................................................................................................................................... 20

9.4

Register 26 – Configuration ..................................................................................................................................................... 21

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

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ICG-1020S
9.5

Register 27 – Gyroscope Configuration .................................................................................................................................... 22

9.6

Register 38 – DLPF and HPF Reset and Auto Zero .................................................................................................................... 23

9.7

Register 55 – INT Pin / Bypass Enable Configuration ............................................................................................................... 23

9.8

Register 56 – Interrupt Enable ................................................................................................................................................. 24

9.9

Register 58 – Interrupt Status .................................................................................................................................................. 24

9.10

Registers 65 and 66 – Temperature Measurement .................................................................................................................. 24

9.11

Registers 67 to 70 – Gyroscope Measurements ....................................................................................................................... 25

9.12

Register 107 – Power Management 1 ...................................................................................................................................... 26

9.13

Register 117 – Who Am I .......................................................................................................................................................... 26

9.14

Register 118 – SPI Bus Selection ............................................................................................................................................... 2710.

High Pass Filter, HLPF, Setting Pin Description ..................................................................................................................... 28

11.

Revision History ................................................................................................................................................................... 29

Compliance Declaration Disclaimer ..................................................................................................................................................... 30

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

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ICG-1020S
1. INTRODUCTION
1.1 PURPOSE AND SCOPE
This document is a product specification, providing a description, specifications, and design-related information on the ICG-1020S
MotionTracking device. The device is housed in a small 2.3 x 2.3 x 0.65 mm LGA Package.

1.2 PRODUCT OVERVIEWThe ICG-1020S is digital output, 2 Axis MEMS gyroscope IC optimized for Optical Image Stabilization applications in mobile devices
such as Smartphones, Tablets and Digital Still Cameras. The single structure vibratory MEMS rate gyroscope detects rotation about
the X and Y axis. When the gyro is rotated about any of the sense axes, the Coriolis effect causes a vibration that is detected. The
resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate.
This voltage is digitized using individual on-chip 16-bit Analog-to-Digital Converters (ADCs) to sample each axis. The FSR range is
optimized for image stabilization applications where the narrower range improves hand jitter detection accuracy. User-selectablelow-pass filters enable a wide range of cut-off frequencies.
The ICG-1020S uses fixed clocking scheme that results in a fixed ODR up to 32 kHz for the host to sample the raw gyro output. The
combination of multiple options for DLPF cut-off frequency (40/160, 80/320, 160/640, 250, and 500 Hz) and very low noise provides
the best performance in OIS applications where high bandwidth and low noise provide fast and stable servo loop, resulting in
extended exposure times with lower possibility of blur

1.3 APPLICATIONS

Smart Phone Camera Modules
Digital Still Camera and Video Cameras
High Resolution / Low Noise Applications

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

Page 4 of 30

ICG-1020S
2. FEATURES
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Small 2.3 x 2.3 x 0.65 mm LGA Package
Very Low 4 mdps/√Hz Rate Noise
Extremely tight sensitivity eliminates OIS dynamic calibration
LPF with 40, 80, 160, 250 and 500 Hz settings
Programmable high-pass filters at 0.05 to 10 Hz to remove offset drift due to temperature & PCB warp
Independent ODR v. LPF selection for the most optimized performance
Narrow FSR Range from ±46.5 dps to ±374 dps
High Resolution at up to 700 LSB/(º/s)
Fast Start Up Time; Sleep to Ready at 35 ms
SPI (3 & 4 Wire) Interface
Fast 20 MHz SPI Interface
Temperature sensor for offset temp compensation
Wide 1.7 V to 3.6 V Supply Voltage Range
Low 5 mW Active Power & 6μA Sleep Mode
Self-test allows quick gyro functionally check
High 10,000g Shock Survivability

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

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ICG-1020S
3. ELECTRICAL CHARACTERISTICS(Typical Operating Circuit, VDD = 2.5 V and TA = 25°C, unless otherwise noted.)
PARAMETERCONDITIONS
Sensor Specifications

MIN

TYP

MAX

UNIT

NOTES

GYRO SENSITIVITY
Full-Scale Range

FS_SEL = 0 (default)
FS_SEL = 1
FS_SE L =2
FS_SEL = 3

±46.5
±93
±187
±374

º/s
º/s
º/s
º/s

1

Sensitivity Scale Factor

FS_SEL = 0
FS_SEL = 1
FS_SEL = 2
FS_SEL = 3

700
350
175
87.5

LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)

1

+25°C

16
±1

bits
%

1

±2

%

2

±0.1
±2
±2

%
%
%

2
1
2

Gyro ADC Word Length
Sensitivity Scale Factor Tolerance
Sensitivity Scale Factor Variation Over
Temperature-20°C to +75°C

Nonlinearity
Cross-Axis Sensitivity

Best fit straight line; 25°C
Manufacturing Tolerance
Characterized PCB level

Initial ZRO Tolerance

25°C
PCB Level

±3
±15

º/s
º/s

1
2

ZRO Variation Over Temperature
GYRO NOISE PERFORMANCE
Total RMS Noise-20°C to +75°C
FS_SEL = 0, Fchoice_B = 0
DLPFCFG = 0 (3.36 kHz)DLPFCFG = 2 (40 Hz)
DLPFCFG = 2 (80 Hz)
DLPFCFG = 2 (160 Hz)
DLPFCFG = 2 (250 Hz, default)
DLPFCFG = 2 (500 Hz)

±3

º/s

2

0.85
0.03
0.04
0.06
0.07
0.09

º/s-r m sº/s-r m sº/s-r m sº/s-r m sº/s-r m sº/s-r m s

2
5
5
5
5
5

Group Delay

DLPFCFG = 0 (3.36 kHz)DLPFCFG = 2 (40 Hz)
DLPFCFG = 2 (80 Hz)
DLPFCFG = 2 (160 Hz)
DLPFCFG = 2 (250 Hz)
DLPFCFG = 2 (500 Hz)
Bandwidth 1 Hz to10 Hz
Bandwidth 0.1 Hz to 1 Hz
At 10 Hz

0. 17
6.41
3.09
1.59
1.07
0.61
0.012
0.004
0.004

175GYRO ZERO-RATE OUTPUT (ZRO)

Low-frequency RMS noise
Rate Noise Spectral Density
GYRO MECHANICAL
Mechanical Frequency
Useful mechanical signal BW
Ultrasonic Wash Frequenciesº/s-r m sº/s-r m sº/s/√Hz

6
6
6
6
6
6
1
1
1

36

29
1.6
40

kHz
kHz
kHz

1
1
4

1.7

3.6

V

2

1

100

ms

2

2.5

mA

1

6

µA

1

25
35

ms
ms

1
2
2

25.6

VDD POWER SUPPLY
Operating Voltage Range
Power-Supply Ramp Rate

Monotonic ramp. Ramp rate is 10% to 90% of
the final value

Normal Operating Current

Two Axes Active

Sleep Mode Current
GYRO START-UP TIMEZRO Settling
OPERATING TEMPERATURE RANGE̅̅̅̅)DIGITAL INPUTS (AD0, SCLK, SDI, 𝐂𝐒
VIH, High Level Input Voltage
Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

DLPFCFG=0, to ±1º/s of Final
From Sleep Mode to ready
From Power On to ready

27

ms

-40

+85

ºC

0.7*VDD-0.5

VDD+0.5VV

0.3*VDD

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ICG-1020S
PARAMETERCONDITIONS

MIN

TYP

VIL, Low Level Input Voltage
CI, Input Capacitance
DIGITAL OUTPUT (INT, SDO)
VOH, High Level Output Voltage
VOL1, LOW-Level Output Voltage
VOL.INT1, INT Low-Level Output Voltage
Vhys, Hysteresis
VOL1, LOW-Level Output Voltage
IOL, LOW-Level Output Current
Output Leakage Current
tof, Output Fall Time from VIHmax to VILmax

Frequency Variation over Temperature

NOTES

pF

0.1*VDD

0.1

3 mA sink current
VOL = 0.4 V
VOL = 0.6 V
Cb bus capacitance in pf

INTERNAL CLOCK SOURCE
Fchoice_B = 0 and SMPLRT_DIV ≥ 0Fchoice_B = 1 and SMPLRT_DIV ≥ 1

Clock Frequency Initial tolerance

UNIT

2
0.9*VDD

CI, Capacitance for Each I/O pin
Sample Rate

MAX

<5

Fchoice_B = 1 and SMPLRT_DIV = 0
CLK_SEL = 0, 6; 25°C
CLK_SEL = 1,2,3,4,5; 25°C
CLK_SEL = 0,6
CLK_SEL = 1,2,3,4,5

VVV

0.1*VDD
0 to 0.4
3
6

V
V
mA
mA

2
2
2

100
20+0.1Cb to
250
< 10

nA
ns

2
2

pF

8

kHz

2
2
1
2

32
-5
-1

+5
+1
-10 to +10
±1

%
%
%
%

2
2
2
2
2

Notes:
1. Tested in production
2. Derived from validation of characterization of parts, not guaranteed in production
3. Assumes environmental noise less than 2dps
4. Please refer to Ultrasonic Wash Application Note
5. Calculated based on specified rate noise
6. Guaranteed by design. Corner frequency is specified for each individual DLPF filter (-3dB for DLPFCFG = 2 and -6dB for DLPFCFG = 3)

3.1

ABSOLUTE MAXIMUM RATINGS

Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these conditions is not implied. Exposure to the absolute maximum ratings conditions forextended periods may affect device reliability.
PARAMETERRATING

Supply Voltage, VDD-0.5 V to 4.0 V

REGOUT-0.5 V to 2 V

CSN, SCLK, SDI/SDIO, SDO-0.5 V to VDD

Acceleration (Any Axis, unpowered)

10,000g for 0.2 ms

Storage Temperature Range-40°C to +125°C

Electrostatic Discharge (ESD) Protection
Latch-Up

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

2 kV (HBM); 250 V (MM)JEDEC Class II (2),125°C, ±100 mA

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ICG-1020S
4. TIMING CHARACTERISTICS
4.1 SPI TIMING DIAGRAMS (4- WIRE AND 3-WIRE)SYMBOLPARAMETER

MIN

TYP

MAX

UNIT

NOTES

13

-

-

ns

1

SDI Setup Time

5

-

-

ns

1

SDI Hold Time

7.5

-

-

ns

1

-

-

30

ns

1

SCLK Clock Frequency

-

-

20

MHz

1

SCLK High Period

24

-

-

ns

1

SCLK Low Period

24

-

-

ns

1

tHD.SDO SDO Hold Time

4

-

-

ns

1

A

tSU.CSCS Setup Time

B

tSU.SDIC

tHD.SDI

D

tVD.SDO DO Valid Time

E

fSCLK

F

tHIGH

G

tLOW

H

CONDITIONS

Cload = 20pF

I

tHD.CS

25

-

-

ns

1

J

tDIS.SDO SDO Output Disable TimeCS Hold Time

-

-

32

ns

1

-

tBUF

400

-

-

ns

1

CS high time between transactions

Note 1: Derived from validation or characterization of parts, not guaranteed in production.

CSN

A

E

F

I

SCLK

B

SDI

C

G

MSB INLSB IN

D

SDIO

SDO

H

MSB OUTJLSB OUT

Figure 1a. SPI Timing Diagrams for 4- and 3-Wire CPOL = 1

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

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ICG-1020S

Figure 2b. 3-Wire interface timing with CPHA = 1 and CPOL = 0/1
3-wire Interface Clocks Data into the Slave on the Clock's Rising Edge and Data Out of the Slave on the Clock's Falling Edge

For 3-wire SDI will operate as SDIO and will go to high Z when CSN is at logic 1. SDIO will obey SDI timing when operating as input
and SDO timing when operating as output.

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

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ICG-1020S
5. APPLICATION INFORMATION
5.1

5.2

PIN DESCRIPTIONPIN NUMBERPIN NAME

PIN DESCRIPTION

1
2
3
4
5
6
7
8
9
10,12
11

INT
CSN
RSV-G
SDO
SDI / SDIOSCLKREGOUT
RSV-G
VDD
RSV-N
GND

Interrupt Output (Totem Pole or Open-Drain)
SPI Chip Select Input
Reserved Pin, Connect to GND
SPI Serial Data Output 4-wire SPI / Float During Power-Up 3-wire SPISPI Serial Data Input in 4-wire SPI / Serial Data In Out In 3-wire SPISPI Serial Clock Input
On-Chip Regulator Output. Connect to GND through a 0.1 μF Capacitor
Reserved Pin. Connect to GND
Power Supply. Bypass to GND with a 0.1 μF Cap
Reserved Pin. No Connect
Power Supply Ground

PIN CONFIGURATION
NC

12

INT

NC

11

VDD

10

1

9

CSN

2

8

RSV-G

3

7

4

5

6

SDO

SDI/SDIO

SCLK

C2
0.1µF, ±10%
10V

RESV-GREGOUT
C1
0.1µF, ±10%
5V

Figure 2. Package: LGA 2.3 x 2.3 x 0.65 mm, Top View

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

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ICG-1020S
5.3 TYPICAL OPERATING CIRCUIT
NC

NC

12

INT

11

VDD

10

1

9

CSN

2

8

RSV-G

3

7

4

5

6

SDO

SDI/SDIO

SCLK

C2
0.1µF, ±10%
4V

RESV-GREGOUT
C1
0.1µF, ±10%
2V

Figure 8. ICG-1020S typical application diagram (4-wire SPI bus)

5.3

BLOCK DIAGRAM
VDD
CLOCK
Gen

POR

Factory
Test Modes

OTP Factory
Calibration
SPI SLAVEREGOUT

GND
Single
XY
Gyro
Drive

CV

ADC

Gyro Digital Filter

CV

ADC

Gyro Digital Filter

CSN
SDO
SDI / SDIOSCLKSENSOROUTPUT

INTC

INT

REGS
Temp
SensorADC

Temp Sensor Digital Filter
StatusRegisters

Automatic Gain
Control

ChargePump

Self test

Reference
Gen

Voltage
Regulator

Trims andconfig ckts

Control
Registers

Figure 4. Block Diagram

Figure 4 identifies the key blocks. Two-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning with two axis XY
configuration. After the signal is digitized, data is processed through a digital filter and output through sensor data registers. The
device communicates via a register-selectable SPI serial interface. SPI provides both 4 and 3 wire options for compatibility to OIS
controllers. Other blocks include on-board clocking, temperature compensation and bias circuits.
The sensor data registers contain the latest gyro data. They are read-only registers, and are accessed via the Serial Interface. Data
from these registers may be read anytime.
The reference generator and voltage regulator section generate the internal supply and the reference voltages and currents requiredby the ICG-1020S with its input as unregulated VDD of 1.7 V to 3.6 V. The voltage regulator output is bypassed by a 0.1 µF capacitor
at REGOUT pin.
Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

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ICG-1020S
5.5

SYSTEM BUS LOGIC LEVELS
VDD

VDD

SystemProcessor

VDD
INT

INT

CSN

CSN

SCLK

SCLK

SDO

SDI / SDIO

SDI

SDO
Signal levels must
be at
GND or VDD

GND

ICG-1020S

GND

Figure 9. System Bus Logic Levels

As shown in Figure 8, the recommended logic levels for signal and data lines are 0 V and VDD.

ICG

+Y

-10
2

0S

+X

Figure 3. Orientation of Axes of Sensitivity and Polarity of Rotation
Axis Orientation and Rotation Polarity
Note the Pin 1 Identifier for ICG-1020S

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

Page 12 of 30

ICG-1020S
5.6 DIGITAL FILTER SETTING AND PERFORMANCE
Filter choices in ICG-1020S product has been created to allow the user the flexibility of choice in tradeoffs between noise andlatency. The filter structure consists of the base decimation filters, designed to clean-up ADC noise as well as to band-limit device
noise; followed by the high-pass filters, which can be used to reduce offset drift, regardless of its origin; followed by a choice of 2 ndorder bi-quadratic filter with 5 fixed corner frequency settings (40/160, 80/320, 160/640, 250, and 500 Hz). This is illustrated infigure 5.

Fully Programmable

ADC

Decimator &Trim

HPF BlockHPF1 & 2

5 Fixed Settings

Mux

DLPF Block
DLPF1(2nd order)

HPF_Order[1:0]

Mux

Gyro code [15:0]

DLPF_CFG[1:0]

Figure 5. ICG-1020S Digital Signal Path

More detailed information about how to set these filters will be given in register map section.

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

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ICG-1020S
6. DIGITAL INTERFACE
6.1 SPI INTERFACEThe Serial Peripheral Interface Bus (SPI) provides both 4- and 3-wire modes. The 4-wire SPI uses two control and two data lines. The
ICG-1020S always operates as a Slave device during SPI operation. With respect to the Master, the Serial Clock output (SCLK), theData Output (SDO) and the Data Input (SDI) are shared among the Slave devices. The Master generates an independent Chip Select(CSN) for each Slave device; CSN goes low at the start of transmission and goes back high at the end. The SDO line remains in a highimpedance (high-z) state when the device is not selected, so it does not interfere with any active devices.
The 3-wire SPI uses two control and one data lines. The ICG-1020S always operates as a Slave device during SPI operation. With
respect to the Master, the Serial Clock output (SCLK), and the Data Input/Output (SDIO) are shared among the Slave devices. The
Master generates an independent Chip Select (CSN) for each Slave device; CSN goes low at the start of transmission and goes backhigh at the end. The SDIO line remains in a high-impedance (high-z) state when the device is not selected, so it does not interferewith any active devices.
SPI slave supports CPOL = CPHA = 0 and CPOL = CPHA = 1.

6.2

SPI OPERATION
1.
2.
3.
4.
5.

6.

Data is delivered MSB first and LSB last.
Data is latched on rising edge of SCLK.
Data should be transitioned on the falling edge of SCLK.
SCLK frequency is 20 MHz max.
SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the
SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte contains the Read/Write bit
and indicates the Read (1) or Write (0) operation.
The following 7 bits contain the Register Address. For multiple-byte Read/Writes, data is two or more bytes;
SPI Address format
MSB
R/W A6

A5

A4

A3

A2

A1

LSB
A0

SPI Data format
MSB
D7 D6

D5

D4

D3

D2

D1

LSB
D0

SPI supports Single or Burst Read/Writes.

4-wire SPI

3-wire SPISPI Master

SPI Master

CSN1
CSN2
SCLK
SDO

CSN1
CSN2
SCLK
SDIO

SDI

SPI Salve 1

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

SPI Salve 2

SPI Salve 1

SDO

SDI / SDIO

CSN

NC

SCLK

SDO

SDI / SDIO

CSN

SCLK

SDO

SDI / SDIO

CSN

SCLK

SDO

SDI / SDIO

CSN

SCLK

NC

SPI Salve 2

Page 14 of 30

ICG-1020S
Figure 6. SPI 4-wire and 3-wire Master to Slave Connection

As shown in Figure 6, each SPI slave requires its own CSN line. SDO, SDI/SDIO and SCLK lines are shared. Only one CSN line is active(low) at a time ensuring that only one slave is selected at a time. The CSN lines of other slaves are held high which causes theirrespective SDO (4-wire SPI), and SDI / SDIO (3-wire SPI) pins to be high-Z.

7. PACKAGE INFORMATION

60

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

5

Page 15 of 30

ICG-1020S
TOP VIEWPart number
Lot traceability code

G20S
XXXXX
YWW Z

Z = “E” for Engineering Samples
Z = Blank for MP

Y = Year CodeWW = Work Week

7.1

PART NUMBER IDENTIFICATION
Product
ICG-1020S

Top Mark
Production Parts

Engineering Samples

G20S“E” on the last line

For the latest packaging information, assembly recommendations and landing patterns (footprints), please refer to InvenSense
MEMS Handling Application Note.

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

Page 16 of 30

ICG-1020S
8. REGISTER MAP
The register map for the ICG-1020S is listed below.
Addr
(Hex)

Addr
(Dec.)

Register Name

Serial
I/F

Bit7

02

02

DLPF_b1_H_Yaxis

R/W

DLPF_b1_int_Y[1:0]09

09

DLPF_b1_L_Yaxis

R/W

0E

14

DLPF_b0b2_H_Xaxis

R/W

0F

15

DLPF_b0b2_L_Xaxis

R/W

10

16

DLPF_b1_H_Xaxis

R/W

11

17

DLPF_b1_L_Xaxis

R/W

12

18

DLPF_b0b2_H_Yaxis

R/W

13

19

XG_OFFS_USRH

R/W

14

20

XG_OFFS_USRL

R/W

X_OFFS_USR[7:0]1521

YG_OFFS_USRH

R/W

Y_OFFS_USR[15:8]

16

22

YG_OFFS_USRL

R/W

Y_OFFS_USR[7:0]1925

SMPLRT_DIV

R/W

SMPLRT_DIV[7:0]

1A

26

CONFIG

R/W

-

1B

27

GYRO_CONFIG

R/W

XG_ST

YG_ST

-

26

38

HPF_DLPF_Rst_AZ

R/W

-

-

-

-

37

55

INT_PIN_CFG

R/W

INT_LEVEL

INT_OPEN

LATCH_INT_EN38

56

INT_ENABLE

R/W

-

-

3A

58

R

-

-

41

65

TEMP_OUT_H

R

TEMP_OUT[15:8]

42

66

TEMP_OUT_L

R

TEMP_OUT[7:0]4367GYRO_XOUT_H

R

GYRO_XOUT[15:8]

44

68

GYRO_XOUT_L

R

GYRO_XOUT[7:0]4569

GYRO_YOUT_H

R

GYRO_YOUT[15:8]

4670

GYRO_YOUT_L

R

GYRO_YOUT[7:0]

6A

106

USER_CTRL

R/W

-

6B

107

PWR_MGMT_1

R/W

70

112

DLPF_b0b2_L_Yaxis

R/W

71

113

DLPF_a1_H

R/W

72

114

DLPF_a1_L

R/W

73

115

DLPF_a2_H

R/W

74

116

DLPF_a2_L

R/W

75

117

WHO_AM_I

R

-

76

118

SPI_SEL

R/W-

INT_STATUS

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

DLPF_b1_float_Y[13:8]
DLPF_b1_float_Y[7:0]

DLPF_b0b2_int_X[1:0]

DLPF_b0b2_float_X[13:8]
DLPF_b0b2_float_X[7:0]

DLPF_b1_int_X[1:0]

DLPF_b1_float_X[13:8]
DLPF_b1_float_X[7:0]

DLPF_b0b2_int_Y[1:0]

DLPF_b0b2_float_Y[13:8]
X_OFFS_USR[15:8]

HPF_Order[1:0]

DEVICE_RESETSLEEP

HPF_CFG[2:0]

DLPF_CFG[1:0]--

FCHOICE_B-

HPF_AZHPF_Reset

DLPF_Reset

INT_RD_CLEAR

-

-

-

-

-

-

-

-

-

DATA
_RDY_EN

-

-

-

-

-

DATA
_RDY_INT

FS_SEL [1:0]-

SIG_CON
D_RST--

CLKSEL[2:0]

DLPF_b0b2_float_Y[7:0]
DLPF_a1_int[1]DLPF_a1_float[13:8]
DLPF_a1_float[7:0]

DLPF_a2_int[1:0]

DLPF_a2_float[13:8]
DLPF_a2_float[7:0]
WHO_AM_I[6:1]---

SPI_mode-

Note: Register Names ending in _H and _L contain the high and low bytes, respectively, of an internal register value.
Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

Bit0

Page 17 of 30-

ICG-1020S
In the detailed register tables that follow, register names are in capital letters, while register values are in capital letters anditalicized. For example, the GYRO_XOUT_H register (Register 67) contains the 8 most significant bits, GYRO_XOUT[15:8], of the 16bit X-Axis gyroscope measurement, GYRO_XOUT.

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

Page 18 of 30

ICG-1020S
9. REGISTER DESCRIPTIONSThis section describes the function and contents of each register.

9.1

REGISTERS 02, 09, 14-18, 112-116 - X AND Y AXES DIGITAL LOW PASS FILTER COEFFICIENTSDLPF_B1_H_YAXIS, DLPF_B1_L_YAXIS, DLPF_B0B2_H_XAXIS, DLPF_B0B2_L_XAXISDLPF_B1_H_XAXIS, DLPF_B1_L_XAXIS, DLPF_B0B2_H_YAXIS, DLPF_B0B2_L_YAXISDLPF_A1_H, DLPF_A1_L, DLPF_A2_H, DLPF_A2_L
Type: Read/Write
Addr
(Hex)

Addr
(Dec.)

Register Name

Bit7

02

02

DLPF_b1_H_Yaxis

DLPF_b1_int_Y[1:0]09

09

DLPF_b1_L_Yaxis

0E

14

DLPF_b0b2_H_Xaxis

0F

15

DLPF_b0b2_L_Xaxis

10

16

DLPF_b1_H_Xaxis

11

17

DLPF_b1_L_Xaxis

12

18

DLPF_b0b2_H_Yaxis

70

112

DLPF_b0b2_L_Yaxis

71

113

DLPF_a1_H

72

114

DLPF_a1_L

73

115

DLPF_a2_H

74

116

DLPF_a2_L

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

DLPF_b1_float_Y[13:8]
DLPF_b1_float_Y[7:0]

DLPF_b0b2_int_X[1:0]

DLPF_b0b2_float_X[13:8]
DLPF_b0b2_float_X[7:0]

DLPF_b1_int_X[1:0]

DLPF_b1_float_X[13:8]
DLPF_b1_float_X[7:0]

DLPF_b0b2_int_Y[1:0]

DLPF_b0b2_float_Y[13:8]
DLPF_b0b2_float_Y[7:0]

DLPF_a1_int[1]DLPF_a1_float[13:8]
DLPF_a1_float[7:0]

DLPF_a2_int[1:0]

DLPF_a2_float[13:8]
DLPF_a2_float[7:0]

Description:
The DLPF can be configured to have different corner frequencies as shown in table below. The default -3dB cornerfrequency is set at 250Hz. The “b” coefficients are axis specific, while “a” coefficients are common to both axes (X and Y).
Also “b0” and “b2” coefficients are equal and have been combined into a single coefficient “b0b2”. The format of thesecoefficients is 2 bits integer plus 14 bits floating point. They are represented in 2’s complement format.

-3dB Corner Freq.
DLPF_b0b2_Yaxis
DLPF_b1_Yaxis
DLPF_b0b2_Xaxis
DLPF_b1_Xaxis
DLPF_a1
DLPF_a2

40/160 Hz
0x00040x00080x00040x0008
0x82D7
0x3D38Parameter Value (Hex)80/320 Hz
160/640 Hz
250 Hz0x00110x001C0x00110x001C
0x85AF
0x3A8F0x00400x006D0x00400x006D
0x8B590x35940x00950x01000x00950x01000x91AE0x307C

500 Hz
0x02120x03870x02120x0387
0xA2EE
0x24BD

Parameters:
DLPF_b0b2_Yaxis 16-bit b0 & b2 (b0=b2) coefficients of DLPF for Y-axis
DLPF_b1_Yaxis
16-bit b1 coefficient of DLPF for Y-axis
DLPF_b0b2_Xaxis 16-bit b0 & b2 (b0=b2) coefficients of DLPF for X-axis
DLPF_b1_Xaxis
16-bit b1 coefficient of DLPF for X-axis
DLPF_a1
16-bit a1 coefficient of DLPF for both X and Y axes
DLPF_a2
16-bit a2 coefficient of DLPF for X both and Y axes

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

Page 19 of 30

ICG-1020S
9.2

REGISTERS 19 TO 22 – GYROSCOPE OFFSET ADJUSTMENTXG_OFFS_USRH, XG_OFFS_USRL, YG_OFFS_USRH, YG_OFFS_USRL
Type: Read/Write
Addr
(Hex)

Addr
(Dec.)

Register Name

13

19

XG_OFFS_USRH

X_OFFS_USR[15:8]

14

20

XG_OFFS_USRL

X_OFFS_USR[7:0]1521

YG_OFFS_USRH

Y_OFFS_USR[15:8]

16

22

YG_OFFS_USRL

Y_OFFS_USR[7:0]

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Description:
These registers are used to remove DC bias from the sensor outputs. The values in these registers are subtracted from thegyroscope sensor values before going into the sensor registers (see registers 67 to 70). Resolution of each bit is 21 mdps perbit.
Parameters:
XG_OFFS_USR_H/L
16-bit offset of X gyroscope (2’s complement)
YG_OFFS_USR_H/L
16-bit offset of Y gyroscope (2’s complement).

9.3

REGISTER 25 – SAMPLE RATE DIVIDER
SMPRT_DIV
Type: Read/Write
Addr
(Hex)

Addr
(Dec.)

19

25

Register Name

Bit7

Bit6

Bit5

Bit4

SMPLRT_DIV

Bit3

Bit2

Bit1

Bit0

SMPLRT_DIV[7:0]

Description:
This register specifies the divider from the gyroscope output rate that can be used to generate a reduced Sample Rate.
When this register is effective, the Sample Rates are shown in table below:
FCHOICE_B

SMPLRT_DIV

Sample Rate

DLPF_CFG
0x

0≥08 kHz / (SMPLRT_DIV+1)(DLPF bypassed)

10(DLPF Enabled)

0x
1

≥1

8 kHz / SMPLRT_DIV(DLPF bypassed)

10(DLPF Enabled)

0x
1

0

32 kHz(DLPF bypassed)

10(DLPF Enabled)

Parameters:
SMPLRT_DIV

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016-3dB Corner Frequency (Hz)3600
40, 80, 160, 250, 500
4000
160, 320, 640
8900
160, 320, 640

8-bit unsigned value. The Sample Rate is determined by dividing the gyroscope output rate by thisvalue.

Page 20 of 30

ICG-1020S
9.4

REGISTER 26 – CONFIGURATIONCONFIG
Type: Read/Write
Addr
(Hex)

Addr
(Dec.)

1A

26

Register Name

Bit7

Bit6

Bit5

CONFIG-HPF_Order[1:0]

Bit4

Bit3

Bit2

Bit1

HPF_CFG[2:0]

DLPF_CFG[1:0]

Description:
Please refer to section 8 on how to set the HPF parameters and description of the “m” factor.
HPF_Order[1:0]10

11

HPF_CFG[2:0]“m” factor-3dB corner (Hz)-3dB corner (Hz)

000
001
010
011
100
101
110
111

9
11
12
13
14
15
16
17

10
2.5
1.25
0.625
0.312
0.156
0.078
0.039

15
3.75
1.872
0.936
0.468
0.234
0.117
0.059

Parameters:
HPF_Order[1:0]0x – Bypass high-pass filters
10 – Select one high-pass filter
11 – Select two high-pass filters in series (2nd order high-pass)

HPF_CFG[2:0]

Selects the “m” factor, which determines high-pass filter -3dB cornerfrequency.(see section 8)

DLPF_CFG[1:0]0x – Bypass DLPF
10 – Select to enable DLPF

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

Bit0

Page 21 of 30

ICG-1020S
9.5

REGISTER 27 – GYROSCOPE CONFIGURATIONGYRO_CONFIG
Type: Read/Write
Addr
(Hex)

Addr
(Dec.)

Register Name

Bit7

Bit6

Bit5

1B

27

GYRO_CONFIG

XG_ST

YG_ST

-

Bit4

Bit3

FS_SEL [1:0]

Bit2

Bit1

Bit0

-

-

FCHOICE_B

Description:
This register is used to trigger gyroscope self test and configure the gyroscopes’ full scale range.
Gyroscope self-test permits users to test the mechanical and electrical portions of the gyroscope. When self-test is
activated by setting XG_ST, YG_ST bits in register 27, the on-board electronics will actuate the appropriate sensor. Thisactuation will move the sensor’s proof masses over a distance equivalent to a pre-defined Coriolis force. This proof mass
displacement results in a change in the sensor output, which is reflected in the output signal. The output signal is used toobserve the self-test response. The self-test response (STR) is stored in the sensor data output registers 67 – 70. This selftest-response is used to determine whether the part has passed or failed self-test
This self-test response must be within the limits provided in product specification document for the part to pass self-test.
Otherwise, the part is deemed to have failed self-test.
FS_SEL selects the full scale range of the gyroscope outputs according to the following table.
FS_SEL0

Full Scale Range± 46.5 °/s

1± 93 °/s2± 187 °/s3

± 374 °/s

FCHOICE_B, in conjunction with DLPF_CFG (Register 26), and SMPLRT_DIV (Register 25) is used to choose the gyroscope
output settings, such as filter bandwidth and sample rate, as described in register 25 (SMPRT_DIV) section.
Bit 5 and 1-2 are reserved.
Parameters:
XG_ST
Setting this bit causes the X axis gyroscope to perform self test.
YG_ST
Setting this bit causes the Y axis gyroscope to perform self test.
FS_SEL
2-bit unsigned value. Selects the full scale range of gyroscopes.
FCHOICE_B
1-bit unsigned value used to choose the gyroscope output setting.

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

Page 22 of 30

ICG-1020S
9.6

REGISTER 38 – DLPF AND HPF RESET AND AUTO ZERO
HPF_DLPF_Rst_AZ
Type: Read/Write
Addr
(Hex)

Addr
(Dec.)

26

38

Register Name

Serial
I/F

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

HPF_DLPF_Rst_AZ

R/W

-

-

-

-

-

HPF_AZHPF_Reset

DLPF_Reset

Description:
Both High Pass Filter (HPF) and Low Pass Filter (DLPF) can be reset. In addition, HPF can be Auto Zeroed.
In case of HPF, the reset command clears the HPF filter state, while the auto-zero command loads the filter state with filter
input. This will result in the following response for a filter input of DCin+ACin (an input with DC and AC components):a) HPF output prior to reset or Auto Zero (AZ)  ACinb) HPF output right after reset  DCin+ACinc) HPF output right after AZ  0
Please refer to section 8 on how to set the HPF.

9.7

Parameters:
HPF_AZ

When this bit is equal to 1, HPF is Auto Zeroed.

HPF_Reset

When this bit is equal to 1, HPF is reset.

DLPF_Reset

When this bit is equal to1, DLPF is reset.

REGISTER 55 – INT PIN / BYPASS ENABLE CONFIGURATION
INT_PIN_CFG
Type: Read/Write
Addr
(Hex)

Addr
(Dec.)

Register Name

37

55

INT_PIN_CFG

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

INT_LEVEL

INT_OPEN

LATCH_INT_ENINT_RD_CLEAR----

Description:
This register configures the behavior of the interrupt signals at the INT pins.
Parameters:
INT_LEVEL
When this bit is equal to 0, the logic level for the INT pin is active high.
When this bit is equal to 1, the logic level for the INT pin is active low.
INT_OPEN
When this bit is equal to 0, the INT pin is configured as push-pull.
When this bit is equal to 1, the INT pin is configured as open drain.
LATCH_INT_EN
When this bit is equal to 0, the INT pin emits a 50us long pulse.
When this bit is equal to 1, the INT pin is held high until the interrupt is cleared.
INT_RD_CLEAR
When this bit is equal to 0, interrupt status bits are cleared only by reading INT_STATUS(Register 58)
When this bit is equal to 1, interrupt status bits are cleared on any read operation.

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

Page 23 of 30

ICG-1020S
9.8

REGISTER 56 – INTERRUPT ENABLE
INT_ENABLE
Type: Read/Write
Addr
(Hex)

Addr
(Dec.)

Register Name

38

56

INT_ENABLE

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

-

-

-

-

-

-

-

DATA
_RDY_EN

Description:
Bits 7 through 1 are reserved.
Parameters:
DATA_RDY_EN

9.9

When set to 1, this bit enables the Data Ready interrupt. The Data Ready interrupt is triggered
when all the sensor registers have been written with the latest gyro sensor data.

REGISTER 58 – INTERRUPT STATUS
INT_STATUS
Type: Read Only
Addr
(Hex)

Addr
(Dec.)

3A

58

Register Name

INT_STATUS

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

-

-

-

-

-

-

-

DATA
_RDY_INT

Description:
This register shows the interrupt status when gyro data is ready to be read. This bit will clear after the register is read.
Bits 7 through 1 are reserved.
Parameters:
DATA_RDY_INTThis bit automatically sets to 1 when a Data Ready interrupt is generated.
The bit clears to 0 after the register has been read.

9.10 REGISTERS 65 AND 66 – TEMPERATURE MEASUREMENTTEMP_OUT_H and TEMP_OUT_L
Type: Read Only
Addr
(Hex)

Addr (Dec.)

Register Name

41

65

TEMP_OUT_H

TEMP_OUT[15:8]

42

66

TEMP_OUT_L

TEMP_OUT[7:0]

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Description:
These registers store the most recent temperature sensor measurement.
Temperature measurements are written to these registers at the Sample Rate as defined in Register 25.
These temperature measurement registers, along with the gyroscope measurement registers, are composed of two sets ofregisters: an internal register set and a user-facing read register set.
The data within the temperature sensor’s internal register set is always updated at the Sample Rate. Meanwhile, the userfacing read register set duplicates the internal register set’s data values whenever the serial interface is idle. Thisguarantees that a burst read of sensor registers will read measurements from the same sampling instant. Note that if burst
reads are not used, the user is responsible for ensuring a set of single byte reads correspond to a single sampling instant bychecking the Data Ready interrupt.
The range of temperatures covered by this sensor register is from -123C to +123C.
Parameters:
TEMP_OUT 16-bit signed value.
Stores the most recent temperature sensor measurement.
Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

Page 24 of 30

ICG-1020S
9.11 REGISTERS 67 TO 70 – GYROSCOPE MEASUREMENTS
GYRO_XOUT_H, GYRO_XOUT_L, GYRO_YOUT_H, and GYRO_YOUT_L
Type: Read Only
Addr (Hex)

Addr (Dec.)

Register Name

43

67

GYRO_XOUT_H

Bit7

Bit6

Bit5

GYRO_XOUT[15:8]

Bit4

Bit3

44

68

GYRO_XOUT_L

GYRO_XOUT[7:0]4569

GYRO_YOUT_H

GYRO_YOUT[15:8]

4670

GYRO_YOUT_L

GYRO_YOUT[7:0]

Bit2

Bit1

Bit0

Description:
These registers store the most recent gyroscope measurements. Gyroscope measurements are written to these registers at
the Sample Rate as defined in Register 25.
The gyroscope sensor registers continuously update at the user selectable ODR sample rate whenever the serial interface isidle. It is recommended to use burst reads on host interface to guarantee a read of sensor registers will read measurementsfrom the same sampling instant. Note that if burst reads are not used, the user is responsible for ensuring a set of single
byte reads correspond to a single sampling instant by checking the Data Ready interrupt. Failing to do so, may result inreading the low and high byte of the same sensor from different samples which could appear as noise peaks to the user for
example. The following should be considered for single byte read mode:
1. Data_RDY_INT gets generated any time the sensor registers get updated with the sensor data. The frequency of thisinterrupt is the same as the ODR which is user selectable. The INT Configurations, INT status register and INT pin can be
configured using the user register 37h, 38h and 3Ah.
2. The sensor register outputs are 16 bits (2 bytes). Both bytes should be read at the same time in order to get reliable datausing burst mode. If a single byte read is used, the host needs to read the bytes back to back after Data_RDY_INT is set
to ensure both bytes are from same sample.
3. The sensor registers should be read at a faster rate than the selected ODR with the read cycle preferably completed for
all the sensors to get consistent and reliable output.
Each 16-bit gyroscope measurement has a full scale defined in FS_SEL (Register 27). For each full scale setting, thegyroscopes’ sensitivity per LSB in GYRO_xOUT is shown in the table below:
FS_SEL

Parameters:
GYRO_XOUTGYRO_YOUT

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

Full Scale Range

LSB Sensitivity

0± 46.5 °/s

700 LSB/°/s1± 93 °/s

350 LSB/°/s2± 187 °/s

175 LSB/°/s3± 374 °/s

87.5 LSB/°/s

16-bit 2’s complement value.
Stores the most recent X axis gyroscope measurement.
16-bit 2’s complement value.
Stores the most recent Y axis gyroscope measurement.

Page 25 of 30

ICG-1020S
9.12 REGISTER 107 – POWER MANAGEMENT 1
PWR_MGMT_1
Type: Read/Write
Addr
(Hex)

Addr
(Dec.)

6B

107

Register Name

Bit7

Bit6

Bit5

Bit4

Bit3

PWR_MGMT_1

DEVICE_RESET

SLEEP

-

-

-

Bit2

Bit1

Bit0

CLKSEL[2:0]

Description:
This register allows the user to configure the power mode and clock source. It also provides a bit for resetting the entire
device, and a bit for disabling the temperature sensor.
By setting SLEEP to 1, the device can be put into low power sleep mode.
An internal 20MHz oscillator or the gyroscope based clock (PLL) can be selected as the device clock source. The PLL is thedefault clock source upon power up. In order for the gyroscope to perform to spec, the PLL must be selected as the clock
source.
When the internal 20MHz oscillator is chosen as the clock source, the device can operate while having the gyroscopes
disabled. However, this is only recommended if the user wishes to use the internal temperature sensor in this mode.
The clock source can be selected according to the following table.
CLKSEL

Clock Source

0Internal 20MHz oscillator

1

PLL

2

PLL

3

PLL

4

PLL

5

PLL

6

Internal 20MHz oscillator

7

Reserved

For further information regarding the device clock source, please refer to the relevant Product Specification document.
Bits 5 through 3 are reserved.
Parameters:
DEVICE_RESETWhen set to 1, this bit resets all internal registers to their default values.
The bit automatically clears to 0 once the reset is done.
SLEEP
When set to 1, this bit puts the device into sleep mode.
CLKSEL
3-bit unsigned value. Specifies the clock source of the device.

9.13 REGISTER 117 – WHO AM I
WHO_AM_I
Type: Read Only
Addr
(Hex)

Addr
(Dec.)

Register Name

Bit7

75

117

WHO_AM_I

-

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

WHO_AM_I[5:0]-

Description:
This register is used to verify the identity of the device.
The default value of the register is 0x88.
Bits 0 and 7 are reserved.
Parameters:
WHO_AM_I Contains the 6-bit device identifier.

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

Bit0

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ICG-1020S
9.14 REGISTER 118 – SPI BUS SELECTIONSPI_SEL
Type: Read/Write
Addr
(Hex)

Addr
(Dec.)

Register Name

Bit7

Bit6

Bit5

Bit4

76

118

SPI_SEL

-

-

-

-

Bit3

Bit2

Bit1

Bit0

SPI_mode--

Description:
The default value of this register is 0 which corresponds to 4-wire SPI. Setting this bit to 1 enables the 3-wire SPI operation.
Bits 0 to 1 and bits 3 to 7 are reserved.
Parameters:
SPI_mode
When set to 1, this bit enables 3-wire SPI operation.
The default value of zero corresponds to 4-wire SPI.

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

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ICG-1020S
10. HIGH PASS FILTER, HLPF, SETTING PIN DESCRIPTIONAs mentioned, the purpose of high-pass filters is to attenuate or eliminate the effect of slow varying offset that may result from the
gyro or the substrate PCB warp due to heat. The customer can choose from 1st or 2nd order high-pass filter of varying bandwidths.
The digital high-pass filter transfer function for each individual filter can be described in Z-domain as 𝐻ℎ𝑝𝑓 (𝑧) =𝑧−1, 𝑤ℎ𝑒𝑟𝑒 𝑚 = 9,11,12,13,14,15,16,17
The filter phase delay can be computed from
2𝜋𝑓
2𝜋𝑓
sin(
)
sin(
)
𝑓𝑠
𝑓𝑠
−1
−1
𝜃(𝑓) = 𝑡𝑎𝑛 (⁄) − 𝑡𝑎𝑛 (
⁄
)
2𝜋𝑓
2𝜋𝑓
cos (
)−1
cos (
) − 1 + 2−𝑚
𝑓𝑠
𝑓𝑠
𝜃(𝑓)
While the group delay is calculated by this equation,/𝑓 , where 𝑓𝑠 is equal to 8kHz.
360⁰ 𝑠Corner frequency selection for all HPF settings can be found in table, located in register map section.

Magnitude (dB)𝑧−1+2−𝑚

m=17
\\

m=16

m=15

m=14

Figure 7. 1st order HPF frequency response for coefficient m=13,14,15,16
The high pass filter(s) can also be reset or auto-zeroed by writing and then clearing HPF_reset and HPF_AZ bits in User register
space. The reset command clears the HPF filter state, while the auto-zero command loads the filter state with filter input. This will
result in the following response for a filter input of DCin+ACin:a) HPF output prior to reset or AZ  ACinb) HPF output immediately after reset  DCin+ACinc) HPF output immediately after auto-zero  0
The choice of HPF (bypass, 1st order or 2nd order) is selected by programming HPF_Order[1:0] bits.
The HPF filter corner (“m”-coefficient) can be selected by programming HPF_CFG[2:0].

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

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ICG-1020S
11. REVISION HISTORYREVISIONDATE

REVNUMBERDESCRIPTION

07/01/2016

1.0

Initial Release

Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

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ICG-1020S
COMPLIANCE DECLARATION DISCLAIMER
InvenSense believes the environmental and other compliance information given in this document to be correct but cannot
guarantee accuracy or completeness. Conformity documents substantiating the specifications and component characteristics are on
file. InvenSense subcontracts manufacturing and the information contained herein is based on data received from vendors andsuppliers, which has not been validated by InvenSense.

This information furnished by InvenSense is believed to be accurate and reliable. However, no responsibility is assumed by
InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use. Specifications
are subject to change without notice. InvenSense reserves the right to make changes to this product, including its circuits andsoftware, in order to improve its design and/or performance, without prior notice. InvenSense makes no warranties, neither
expressed nor implied, regarding the information and specifications contained in this document. InvenSense assumes noresponsibility for any claims or damages arising from information contained in this document, or from the use of products andservices detailed therein. This includes, but is not limited to, claims or damages based on the infringement of patents, copyrights,
mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by
implication or otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information
previously supplied. Trademarks that are registered trademarks are the property of their respective companies. InvenSense sensors
should not be used or sold in the development, storage, production or utilization of any conventional or mass-destructive weapons
or for any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment,
transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime
prevention equipment.
©2016 InvenSense, Inc. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion,
MotionApps, Digital Motion Processor, AAR, and the InvenSense logo are trademarks of InvenSense, Inc. Other company andproduct names may be trademarks of the respective companies with which they are associated.

©2016 InvenSense, Inc. All rights reserved.
Document Number: DS-000149
Revision: 1.0
Rev Date: 07/01/2016

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