Miniaturization of the Boost-up type
Active Buffer Circuit in a Single-phase Inverter
Hiroki Watanabe, Kazuhiro Koiwa, Jun-ichi ItohYoshiya Ohnuma, Satoshi Miyawaki

Department of Electrical Engineering
Nagaoka University of Technology
Nagaoka, Niigata, Japanhwatanabe@stn.nagaokaut.ac.jp

Nagaoka Power Electronics Co.Ltd
Nagaoka, Niigata, Japanohnuma@npe.co.jp

Abstract— This paper discusses miniaturization of asingle-phase grid connected inverter, which has power
decoupling function for PV. The power ripple of twice gridfrequency is compensated in the proposed circuit with thesmall capacitor (50 F) at 200 W. However, the buffer
inductor in the proposed circuit becomes large because thebuffer inductor current is fluctuated at twice grid frequency
by power ripple compensation, and the switching ripple islarge at the peak current. In this paper, in order to reduce
the size of the buffer inductor, the buffer inductance is
optimized in terms of the volume and efficiency according to
the switching frequency. As an experimental result, it isconfirmed that the input current ripple is reduced by 90 %in the proposed circuit, and the output current THD is
3.5 %. On the other hand, the buffer inductance is reduced
by 73 % at 64 kHz of the switching frequency. In addition,
the volume of the proposed circuit can be reduced by 37%
in compared to the conventional circuit. Finally, from theevaluation of the power density using the Pareto front curve,
the proposed circuit can design the high power density incompared to the conventional circuit.
Keywords— grid connected inverter;
compensation; loss analysis; power density

I.

power ripple

INTRODUCTION

The dramatically cost down of photovoltaic (PV) has
urged the uses of solar energy becoming popular in theinterest of energy saving. In general, the power
conversion system employs a grid-connected inverterwith the boost-up chopper to connect the PV modules toa single-phase grid system.
The grid-connected inverter for the PV applications
can be categorized into two types. The first type uses alarge power capacity inverter to connect multiple
numbers of PV modules in a series connection. The
second type employs a small power capacity inverter,
which is also known as the “micro-inverter”, and then it
is connected to each of the single PV cell [1]-[4]. The“micro-inverter” offers better features because of thefollowing reasons; (i) Maximum Power Point Tracking
control (MPPT) can be easily applied in each of theindividual PV cell. (ii) Optimal design for control issimple. (iii) Capacity of the PV system can be easily
modified due to the simple structure.
However, micro-inverters have problems regarding

cost and size, since the micro-inverter need a lot of
numbers for PV system in comparison with the first typesystem which only employs a large power capacity
single-phase inverter.
Although the lifetime of a PV module is namely 25
years, the lifetime of the electrolytic capacitor is typically
1000-7000 hours at 105 degree Celsius operating
temperature. As a result, periodically maintenance isrequired for the conventional micro-inverter. Besides, thevolume of the electrolytic capacitor dominates the total
volume of the micro-inverter. Moreover, the initialcharging for the electrolytic capacitor is needed.
In order to remove the large electrolytic capacitor,
power decoupling methods between DC side and AC side
known as the DC link active filters have been studied
such as [5]-[9].
These topologies technically can reduce thecapacitance value of the DC link capacitor. However,extra devices and passive components are required.
Consequently, the efficiency is degraded. Additionally,
the cost is higher because of the additional circuit.
The authors have proposed a circuit topology, which
comprises the single-phase inverter and the active buffer
based on a boost-chopper between DC side and AC side[10]. The active buffer circuit is employed to achieve
boost-up function for PV voltage and to decouple thepower fluctuation with a small capacitor simultaneously.
The proposed circuit has the following features; (i) A
resonant DC/DC converter is applied with the zerocurrent switching (ZCS), (ii) the miniaturization and cost
reduction are achieved because general 6 in 1 modules
can be used in proposed circuit. However, the buffer
inductor current in the proposed circuit should becontrolled to twice frequency of the power grid in order
to compensate the power fluctuation. As a result, thevolume of the boost-up inductor becomes large incomparison to a general boost chopper.
In this paper, the volume of the buffer inductor in the
proposed circuit is evaluated by experiment. In order toreduce the size of the buffer inductor, the buffer
inductance is optimized according to the switchingfrequency. Although, the switching loss in the active
buffer is increased, the copper loss of the inductor isreduced at the same ripple current.
The remainder of this paper is organized as follows;
first, the constitution of the proposed circuit is shown.
After that, the principle of the power decoupling control
strategy is described. In addition, the designing thebuffer capacitor and buffer inductor for miniaturization
is described. Finally, the power density of the proposed
circuit is evaluated using the Pareto front curve.
II.

CIRCUIT CONFIGURATION

Figure 1 shows the circuit configuration of aconventional micro-inverter for PV. The DC voltage ofthe single PV cell is relatively low, generally ranging
from 25 V to 50 V. On the other hand, the power gridvoltage is typically from 110 V to 240 V. For the reason,
the boost-up chopper is necessary for the grid-connected
inverter. Ldc and Cdc are the components of an input filter
to remove the switching ripple in the DC link
The power ripple which has twice of the power gridfrequency occurs in the input DC current. Because of
the large current ripple, the effeciency of the PV isdecreased. In order to suppress the power ripple, thelarge electolytic capacitor is connected to the DC linkpart. The electrolytic capacitor requires large space andan initial charge circuit. Thus, regular maintenance isrequired. As a result, the conventional circuit becomesbulky and high cost.
Figure 2 (a) shows the circuit configuration of theisolated resonance DC/DC converter. This circuit boost
the input voltage vin tenfold ， and the zero current
switching (ZCS) control is applied to reduce theswitching loss.
Figure 2 (b) shows the circuit configuration of theactive buffer and inverter circuit. The active circuit
consists of a single-phase inverter, a boost-up chopperand a small capacitor C5 to absorb the power ripple. In
comparison with the conventional circuit, the advantagesof the propsed circuit are smaller size and longer lifetime
because the small film or ceramic capacitor is usedinstead of an electrolytic capacitor. In addition, thenumber of the components in the proposed circuit is notincreased from the conventional micro-inverter as shownin Figuer 1.
III.

POWER DECOUPLING AND CONTROL STRATEGY

Figure 3 shows the principle of the power decoupling
between the DC and AC sides. When both the input
voltage and current waveforms are sinusoidal, theinstantaneous output power pout is expressed as
pout 

Vout I out(1  cos 2t ) 
2where, Vout is the peak voltage, Iout is the peak current,
and the angular frequency of the output voltage. From (1),the power ripple, that contains twice frequency of thepower grid, appears at the DC link.

Fig.1 Conventional circuit for PV micro inverter.

(a) Isolated resonance DC/DC converter.

(b) Active buffer, inverter circuit.
Fig.2 Circuit configuration of the proposed circuit.

Fig.3 Compensation principle of the power ripple with active buffer.

In order to absorb the power ripple, the instantaneous
power pbuf of an active buffer, should be controlled by1
pbuf  V out I out cos 2t 
2where, the polarity of the pbuf is defined as positive when
the active buffer discharges. It is noted that the mean
power of the active buffer is zero because the active
buffer does not generate the power.
Figure 4 shows the control block diagram for the
proposed system. It is noted that automatic voltage
regulator (AVR) is implemented to control the voltage ofthe buffer capacitor Cb. However, high speed response istransformer secondary voltage vrec and buffer capacitor
voltage vc can be expressed by (6).

required in the AVR because the control reference signal
frequency is twice of the single-phase power gridfrequency. In order to solve this problem, controlling thecapacitor voltage which is implemented on the rotationald-q frame, has been discussed in Refs. [11]. In thismethod, the AVR does not require a high speed response.
However, the control structure is complicated owing tousing the rotational frame. The automatic current control(ACR) is applied to the active buffer circuit. In addition,in order to control the output voltage, the AVR is applied
to the inverter.
In the paper, the current reference iamp* which
intendeds to compensate the power ripple is added into
the buffer inductor current reference of an ACR. Thus,
the AVR which has high speed response is not requiredin the proposed circuit. The instantaneous buffer inductor
current reference iL* is expressed by (3)vinv  vrec  vc 
It is note that, the inverter input voltage vinv isfluctuated owing to the power ripple from single phasegrid. In addition, maximum power point tracking (MPPT)
is implemented in order to keep the output power at the
maximum point. In order to control the DC link voltage
vinv, the reference value of the AVR is higher than thegrid voltage. However, the buffer capacitor voltage vc
fluctuates owing to twice frequency of the single-phasegrid. As a result, the distortion in the output current
occurs. Additionally, in order to solve this problem, aband eliminate filter (BEF) is applied in the detection
value of the DC link voltage Further the AVR controls
the average value of the DC link voltage. In order toconnect the single phase grid, it is necessary that thephase angle of the inverter output current corresponds to
the grid voltage using the PLL.
Figure 5 shows the maximum power point tracking(MPPT), known as the hill climbing method. The MPPT
is controlled in four modes as illustrated as mode1,
mode2. In mode1, the input current is increased toobserve the maximum point of input power. In mode2,
the present value is compared with the last value, if thepresent value of the input power is lower than 20% of theprevious maximum power point, then the input current isincreased in order to maintain the point of maximum
power. As a result, the input power is controlled by (7)iL  iamp  iin ＝ic  iin 
*

*

*

*

*

where, iamp* is the power ripple compensation current
reference, and iin* is the DC component in the buffer
inductor current.
The power ripple compensation current reference iamp*
is calculated by output power pout and buffer capacitor
voltage vc Thus, the power ripple compensation current isexpressed by (4)iamp  ic 
*

*

pout
cos(2t ) 
vc

Pth  Pin  Pmax 

On the other hand, the DC component in the buffer
inductor current iin* is expressed by (5)

iin 
*

IV.

pin
vin

A. Buffer capacitor C5
The buffer capacitor C5 is expressed from Pout whichis the electric storage energy to compensate the power
ripple, by (8)where, pin is the input power, and vin is the transformer
secondary voltage. Then, the current reference iamp* andthe DC current iin* are calculated by (4) and (5).
Relationship among the DC link voltage vinv,*

Detection of
sensors

Vout
*
Iout

Vc
vin
iin
Vout
*

Detection of
sensors

Vinv

*

-

PLL
iout_cmd

*

iamp

*

*

+ iL +

iin

MPPT

PI

vinv_ lpf*

Vout I out
cos[2 ]Vc*+

DESIGN METHOD OF THE COMPONENT

+

*

-

PI

vconv

+
-

SW3
SW4

+
-

SW5
SW6
SW7
SW8


iout _ cmd Sin[ ]
*

+

-

PI

BEF
v dc
iout 30Hz to 200Hz

vout

*

CarrieriL
Fig.4 Control block diagram for the proposed circuit.

C5 

2 Pout
2
Vc rcPin

Area1 Area2
Mode 2

Pmax

Pthwhere, rc is the ratio of the voltage ripple that isexpressed by (9)Mode 1P2

Vc / 2rc Vc

B. Buffer inductor L1
The buffer inductance L1 is designed from ripple
current of buffer inductor current iL. L1 is obtained by
(10).

Iin
I1 I2 ・・・・・・ Impp
Input current[A]Fig.5. Behavior of the operation point in MPPT.

400350Capacitance of C5

where, V is the pulsatile voltage. In order to reduce theC5, V is fluctuated widely. In other words, the peakvoltage increases. Thus, C5 is needed to design less thanthe blocking voltage.
Figure 6 shows the relationship between the V andthe capacitance of C5. According to Figure 6, the C5 isreduced by 50 F at 63.6 V. In this paper, C5 is used theceramic capacitor what blocking voltage is 200 V.

P1

300
250
200
100
50

Vin Vout  Vin10)
L1 
2rl I in f sw Vout

where, rc is the ratio of the voltage ripple that isexpressed by (11)63.6V@50 F

150

0

0

50

100 150200 250
Pulsatile voltage [V]300

Fig.6 Relationship between the pulsatile voltage and capacitanceof C5.

From (10), Relationship between the buffer inductanceLf and switching frequency fsw is inverse variation. Thus,
Lf can reduce by increasing the switching frequency.
Figure 7 shows the relationship between buffer
inductance and carrier frequency. As shown in fig.7, theinductance can be reduced by 73% when the switchingfrequency is 64 kHz.
V.

EXPERIMENTAL RESULTS

A. Fundamental operation
In order to demonstrate the validity of the proposed
circuit, the proposed circuit is demonstrated by using a
200-W prototype. In is noted that the proposed circuit isconnected to 200 V grid. Table 1 lists the experimental
parameters.
Figure 8(a) shows the experimental results without thepower decoupling control. It is noted that, the active
buffer is operated as the boost-up-chopper, that the power
ripple is not compensated. According to Figure 8(a), theinput current ripple is fluctuated at approximately 6 A(peak-to -peak).
Figure 8(b) shows the operation waveforms that thepower decoupling control is applied. As a result, the input

Inductance value[mH]40

I / 2rl  L
IL

350

30

20

10

0

20

40
Carrier frequency[kHz]60

Fig.7 Relationship between buffer inductance and carrier
frequency.
Table1. Experimental condition.
Rated Power Pout

200W

Input voltage Vin

36V

Grid voltage Vout

200V

Grid frequency f

50Hz

DC/DC converter
Switchingfrequency fsw Active buffer , Inverter

150kHzResponseangularfrequency

64kHz

ACR(active buffer)

4000rad/s

ACR(Inverter)

4000rad/s

AVR

50rad/s(a) Without proposed control(b) With proposed control
Fig. 8 Experimental results of the power decoupling control.

(a) Without proposed control(b) With proposed control
Fig.9 Buffer capacitor voltage and buffer inductor current.

1.4

1p.u.=1A

1.2

Without power decoupling control

1

With power decoupling control

0.8

87.7% reduced

0.6
0.4
0.2
0
1

2

3

4
5
6
Harmonic number
Fig. 10 Harmonic analysis.

7

Current ripple factor [%]current fluctuation is reduced to less than 0.5 A (peakto -peak). In addition, the output power factor is 0.99 at
the maximum point. Additionally, the output current
waveform is sinusoidal waveform.
Figure 9(a) shows the buffer capacitor voltage andbuffer inductor current waveforms without the power
decoupling control. According to Figure 9(a), thebuffer inductor current is not fluctuated twice
frequency of a single phase grid.
Figure 9(b) shows the buffer capacitor voltage andbuffer inductor current waveforms with the power
decoupling control. According to figure 9(b), thebuffer capacitor voltage Vc is fluctuated at
approximately 65.2 V (peak to peak) due to the power
decoupling control. The results illustrated that thebuffer inductor current is fluctuating because the active
buffer circuit is decoupling the power fluctuation.
Figure 10 shows the result of harmonic analysis. As
the result, the second order harmonic component isreduced by 87.7% compared to that without the power
decoupling control. However, the second orderharmonic component is not suppressed by 12.3%. Thisis because; (i) the compensation value is not enough at
200 W, and (ii) the phase of buffer power pbuf is notagreed to the single-phase power grid.
Figure 11 shows the buffer inductor current ripple
characteristics for the switching frequency. According
to Figure 11, the experimental results almost agreewith the design value. Thus, the validity of the design
is confirmed. However, the experimental results arelower than the design value. This is because theinductance value is large than the design value. Thus,
the experimental value conforms to theoretical value
by using the design value.
Figure 12(a) show the efficiency and power factorof the proposed system in subjecting to the output
power. According to Figure 12(a), the maximum
efficiency of the DC/DC converter is 96.2%, and the
maximum efficiency of the inverter which includes theactive buffer is 95.5%. However, when the output
power is 50W, the efficiency becomes low owing to
low power factor.
Figure 12(b) shows the output current THD and
input current ripple of the proposed system insubjecting to the output power. According to Figure12(b), the input current ripple is 12.3% when the
output power is 150 W. In addition, the output current
THD of the inverter is less than 5% when the output
power is more than 100 W.
Figure 13 shows the experimental results of the
MPPT. In this paper, the MPPT is demonstrated inthree conditions. When the maximum input power ischanged at 100 W, 150 W, and 200 W, the maximum
power is tracked by MPPT control. In order to simulate
the output power of PV, the resistor is connected to the
DC power supply in series. The input current isincreases when the output power is increased. As theFig.11 Buffer inductor current ripple factor.

8results, the voltage drop of the resistor is increased. In
other words, the input voltage of the converter
decreases. For this reason, the maximum power point
can be obtained. However, when the maximum input
power is 200W, the fluctuation of the power differs in
the previous condition, this cause that the input current
limit is set to 8 A. In order to solve this problem the
input current limit becomes higher. On the other hand,the fluctuation of the input power is large. This isbecause the permissible fluctuation range of the input
power is wide. Thus, in order to decrease thefluctuation of the input power, it is necessary to expend
the permissible fluctuation range of the input power.

Volcooling (b) Input current ripple and output current THD.
Fig.12 Load characteristics.

Input power[W]C. High power density design
Figure 16 (a) shows the volume comparative resultsof the conventional circuit and proposed circuit. It isnoted that, the volume of the heat sink is calculatedusing CSPI (Cooling System Performance Index) [13].
The volume of the heat sink Volcooling is expressed by

THD of output current andinput current ripple [%]B. Loss analysis
Figure 14 shows the loss analysis results. According
to Figure 14, the no load loss is large compared toother loss. This is because the stray capacitance of theswitching device is large. In order to reduce the no load
loss, It is necessary to optimize the switching device interms of converter capacity. Furthermore, the volumeof the buffer inductor can be reduced the volume.
However, the switching loss increases owing to theswitching frequency. In order to reduce the switching
loss, the active buffer applies the zero voltage
switching (ZVS).
Figure 15 shows the relationship between the carrier
frequency and efficiency. According to Figure 15, theefficiency of the active buffer and inverter is decreased
when the switching frequency increased. This isbecause the no load loss and switching loss increase.
According to figure 3 and figure 15, relationshipbetween the high efficiency and miniaturization of thevolume of the input inductor has a trade-off. Thus, theefficiency is evaluated with the power density [12].

(a) Efficiency and power factor.

Fig.13. Experimental results of MPPT.

Ploss
1


Rth  CSPI (T j  Ta )  CSPI

where, Rth is the thermal resistance of the coolingsystem, Tj is is the junction temperature of theswitching device, Ta is the ambient temperature, andPloss is the power loss of the switching device. Table 2
lists the parameters to calculate the volcooling.
In this figure, the volume of the proposed system iscompared to the conventional circuit without theisolated DC/DC converter. It is noted that thesmoothing capacitor Cdc is designed from the ripple
current and ripple voltage. The maximum ripple
current is expressed by

Fig.14 Converter loss analysis results.

iripple Vmax I max
cos 2t 13
Vdc

100
98

where, Vmax is maximum grid voltage, and Imax is
maximum output current of inverter, Vdc is DC link
voltage. Capacitor current ic is expressed by

Active buffer

96
94
Inverter92

dv
ic  Cdc c 
dt

90

from (14), Cdc is expressed bywhere, t is reciprocal number of the twice gridfrequency component. vc and ic equal to the ripple
voltage and ripple current.They are needed to design lessthan 10% of maximum value. From (13) and (15), Cdc
need more than 500F.
According to figure 16 (a), the volume of proposed
circuit is reduced by 37%. This is because the smoothing
capacitor is not needed in the proposed circuit, and thesmall capacitor can be applied C5. Thus, the proposed
circuit is smaller than the conventional circuit.
Figure 16 (b) shows the volume comparison when theswitching frequency increases to 64 kHz. According tofigure 16 (b), the volume of the proposed circuit at 64
kHz switching frequency is reduced by 61% incomparison that the switching frequency is 16 kHz. Thisis because the volume of the buffer inductor can be
reduced by increasing the switching frequency. However,the volume of the heat sink increases owing to theswitching loss. Thus, relationship between the highswitching frequency and miniaturization of the volume of
the buffer inductor has a trade-off. In addition, in order toreduce the volume of the heat sink. It is necessary to
improve the efficiency.
Figure 17 shows the Pareto front curve of theconventional circuit and proposed circuit at the range ofswitching frequency from 20 kHz to 300 kHz. The
inductor volume is evaluated by the Area product [14]According to Figure 17, the power density of the
proposed circuit is high more than the conventional
circuit. The constitution of the proposed circuit is equal
to the conventional circuit nearly. However, the proposed
circuit no need the smoothing capacitor on DC link, andbuffer capacitor is small. Thus, the proposed circuit candesign the high power density more than the conventional
circuit. Experimental verification by high power density
design is the future work.
VI.

CONCLUTION

This paper discussed the miniaturization of the boostup type active buffer in a single-phase grid connected
inverter. The proposed circuit was experimented by using

86
10

30
40
50
60
70
Carrier frequency [kHz]Fig.15 Relationship between the carrier frequency and efficiency.

20

Table.1. parameters to calculate the volume.

350
300
250
Volume [cm3]ict 
vc

37%

200
150

Smoothing capacitor(conventional circuit)
Buffer capacitor(proposed circuit)
Buffer reactor
Switch S3 to S8Heat sink

100
50
0

Conventional
circuit

Proposedcircuit(a) Volume estimates of the proposed circuit.

Volume [cm3]

Cdc 

88

(b) Volume comparison when the switching frequency increase to
64kHz.
Fig.16 Volume estimates for the proposed circuit.

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Efficiency [%]a 200W prototype. From the volume estimate, the volume
of proposed circuit is reduced by 37% in compared to theconventional circuit. This is because the proposed circuit
has no the small capacitor can be used as the buffer
capacitor and C5, can apply the small capacitor. From theexperimental results, the output THD is 3.5% at 200 W
output power, and the input current fluctuation is reducedby 90% owing to the power decoupling control. From theevaluation of the power density using the Pareto front
curve, the power density of the proposed circuit is higher
than that of the conventional circuit. Thus, high power
density for the proposed circuit can be designed.
In the future work, the efficiency will be increased.

Fig.17 Pareto front curve of the conventional circuit and proposed
circuit.