High-efficiency of MHz Inverter Constructed fromFrequency Multiplying Circuit
Koji Orikawa, Jun-ichi Itoh
Department of Electrical Engineering
Nagaoka University of Technology
Nagaoka, Japanorikawa@vos.nagaokaut.ac.jp

Abstract— This paper discusses a verification of an inverter
outputs MHz frequency which is over the switching frequency.
The proposed inverter consists of a multi-phase inverter using
silicon switching devices and multi-core transformers. By thefrequency multiplying, high switching frequency compared withthe output frequency is not required. Moreover, the series
resonance using a leakage inductance of the multi-coretransformers and a resonant capacitor is applied in order toachieve sinusoidal output voltage. A prototype circuit isexperimentally verified and theoretically analyzed in terms ofzero voltage switching (ZVS). As a result, it is confirmed that theprototype circuit can output sinusoidal output voltage of 2.5
MHz with the switching frequency of 500 kHz. In addition, arequired dead time for zero voltage switching is theoreticallyanalyzed and experimentally verified using the prototype circuit.

I.

INTRODUCTION

Recently, high-efficiency high-frequency inverters which
output MHz frequency are increasingly received attentions forapplications of plasma generators and wireless power transfer[1-3]. For those applications, voltage with MHz band
frequency is required.
As one of conventional high frequency inverters, power
linear amplifiers using transistors are used. However, theefficiency of the power linear amplifier is low in principle. On
the other hand, Class E inverters have been studying because
they can achieve very high efficiency due to ZVS and zeroderivative switching (ZDS) [4, 5]. In addition, wide band gap
semiconductors such as silicon carbide (SiC) and gallium
nitride (GaN) are used recently. As a result, increasing its
efficiency is accelerating even though the output frequency isseveral MHz to several tens of MHz because their switching
speed is higher than that of conventional Si devices [6]. In
addition, in order to obtain higher efficiency by reducing
switching losses, ZVS or zero current switching (ZCS) isapplied. However, the output frequency is limited by theswitching frequency even though the wide band gapsemiconductors are used because their performance is limited.

This paper verifies experimentally the effect of ZVS on theproposed circuit based on the frequency multiplying method[7] by measuring the input power and the output power. The
proposed circuit outputs a frequency which is over a switchingfrequency while other circuit cannot achieve high output
frequency which is over the switching frequency. Therefore,
not only wide band gap semiconductors are used but also
conventional Si devices can be used in the proposed circuit
because the switching frequency is lower than the output
frequency. This paper is organized as follows; first, theprinciple of the proposed circuit is described. Then, anoperation of the proposed circuit is theoretically analyzed
using an equivalent half-bridge circuit in terms of ZVS forhigh efficiency. Finally, a validity of the condition which
achieves ZVS is experimentally verified at series resonantcondition by measuring the input power and the output power.
II.

PROPOSED CIRCUIT BASED ON FREQUENCY
MULTIPLYING METHOD

Figure 1 shows the circuit configuration of the proposedcircuit in a five-phase inverter model. The primary side of themulti-core transformer [8] is connected in parallel. A commonconnection point of the primary side of the transformer isconnected to the neutral point of DC link capacitors Cdc. On
the other hand, the secondary side of the multi-coretransformer is connected in series. The resonant capacitor
which is used for the series resonance with the leakage
inductance of the multi-core transformer is connected to thesecondary side of the multi-core transformer. Note that themagnetizing inductance is neglected.
Figure 2 shows the principle the proposed frequency
multiplying method. In the five phase voltage-type inverter,
each of the voltage phases is shifted by 72 degree and operated
with square wave modulation. As a result, the output
frequency fout is expressed as following
f out  N  f sw Tsw

Multi-phase inverter
Spy

Spx

Spw

Spv

Spu
Cdc
Vinvuo
vvo

uvo
Snu

Vin/2
Resonancev
0capacitor uo-V /2
in72 deg.
r2 Cr
Vin/2
vvo
0-Vin/2
iload
72 deg.
Vin/2
fout  N  f swvwo
0-Vin/2
vload
72 deg.

Leakageinductance n=N1/N2iu
l1 r1 N1 N2 l2w
Snw

SnvxSnxvwo
Sny yCdc

Rloadvxo
vyoMulti-coretransformers

Output frequency fout: 2.5 MHzSwitching frequency fsw: 500 kHz
Number of phase N: 5Vin/2
vxo
0-Vin/2

72 deg.

Vin/2
vyo
0-Vin/2
Vin/2
vload 0-Vin/2
Tsw/5

Figure 1. Configuration of proposed circuit.

where fsw is the switching frequency and N is the numberof phase in the multi-phase inverter.
Therefore, the multi-phase inverter outputs high frequency
which is over the switching frequency even though low
switching frequency is applied. In addition, cooling is easier
because the heat which is generated from the multi-phase
inverter can be dissipated for a number of switches.
III.

PRINCIPLE OF ZERO VOLTAGE SWITCHING

This chapter describes the principle of ZVS in the
proposed circuit for reduction of the switching loss.
Fig. 3(a) shows a half bridge equivalent circuit of the
proposed circuit. In Fig. 3(a), an upper switch is S1. On theother hand, a lower switch is S2. A DC link capacitor Cdc isassumed to be a voltage source. R is resistance components
transformed to the primary side of the multi-core transformer,
which includes a wire resistance r1 and r2 and a load resistance
Rload. L is inductance components transformed to the primaryside of the multi-core transformer, which includes a leakage
inductance l1 and l2. C is an equivalent resonant capacitor. Cr
is a resonant capacitor connected to the secondary side of themulti-core transformer. By analyzing the operation of the
proposed circuit, R, L, C and Cr are expressed by (2), (3), (4)and (5) using the turn ratio of the winding in the multi-coretransformer n and the resonant frequency fr.
R  N  r1  n 2  Rout  r2 (2)L  N  l1  n 2  l2

(3)

1
2f r 2 L(4)C2N Cr   1  C  n 2C
 N2 (5)Fig. 3(b) shows two gate signals of the equivalent circuitwith the dead time Td. In this paper, ZVS when S2 is turned onis focused.

Figure 2. Principle of frequency multiplying.

Fig. 3(c) and (d) show the gate signals, two corresponding
drain-source voltage and the current of a neutral point of theDC link voltage when hard-switching occurs or ZVS isachieved.
A. Operation modes
Figure 4 shows operation modes of the proposed circuit. A
condition which achieves ZVS is decided by the dead time andcircuit parameters. By analyzing Fig. 4, the required dead time
Td which achieves ZVS is obtained as following.
1) Mode I
The Mode I is a period before the dead time starts. In theMode I, the switch S1 is on-state and the switch S2 is off-state.
Note that the current ISw flows to the S1. In this paper, theperiod which the Mode I ends is defined as t=0.
2) Mode II
In the Mode II, the S1 is turned off and the period of thedead time starts. The Mode II is kept until the voltage ofparasitic capacitance in S1 is charged up to the input voltage or
the voltage of the parasitic capacitance in S2 is discharged tozero. Note that the period which the Mode II ends is defined
as t=T1. Therefore, Td should be longer than T1 because theparasitic capacitance of drain-source is still charged ordischarge until t=T1.
3) Mode III
First, note that the period which the Mode III ends isdefined as t=T2. The current polarity of the neutral point of theDC link voltage is changed at t=T2. When the dead time Td isshorter than T1+T2, S2 is turned on while the drain-source
voltage of S2 is zero. Therefore, ZVS is achieved.
4) Mode IV
If the dead time Td is larger than T1+T2, the parasitic
capacitance of drain-source in S2 is charged. In this case, S2 isturned on while the drain-source voltage of S2 is not zero.
Therefore, ZVS is not achieved.
The required dead time which achieves ZVS Td isexpressed by (6) using T1 and T2. It is noted that the circuit
parameters satisfy (7).

T1  Td  T1  T2
C p R  2(6)LR

T1  2 LC p Sin 1(7)Hard-switching

Cp

Vds1

Dead time
Td

OFF

Equivalent load
R
L CON
S2i2

io=i1-i2

Zero voltage switching

Dead time
TdS1S1 V  1Lin 2 I sw  2ICp L  sw C p 
(8)

ONi1
Vin
24Vin
2

S2

Cp Vds2Vin2OFFVin
Vds10(a)VinDead time Td

Vds20ON
S1

IT1ioOFF0T2

T2

ONtt

S2
Mode I
With resonance capacitor
0(Without resonance capacitor)

OFFFig. 3(c), (d)

IIIII
T1(b)

IV
T1+T2

VI

II0

T1<T1+T2<Td

T1<Td<T1+T2(c)(a) Half bridge equivalent circuit.
(b) Gate signals with dead-time.

S1

EquivalentloadVin
2S2

Hard-switching
Mode I(Fig. 3(c))
Zero voltage switching
Mode I(Fig. 3(d))(a) S1:On, S2:Off.

(d)(c) Enlarged waveforms at hard-switching.
(d) Enlarged waveforms at zero voltage switching.
Fig. 3. Principle of zero voltage switching.

i1
Vin
2

III IVV
T1
T1+T2

i1
Cp Vds1

Vin2

S1

Equivalentload

i2
Cp Vds2

Vin
2

S2

i1
Cp Vds1

Vin2

S1

Equivalentload

i2
Cp Vds2Vin2S2Mode II,III,IV

Mode V

Mode II,III

Mode IV,V(b) S1:Off, S2:Off (During dead time)
Fig. 4. Operation modes of the proposed circuit.

(c) S1:Off, S2:On

Cp Vds1

i2
Cp Vds2T2  Tan1    K1 R 
2 LC  2 L 

1(9)

2(10)

Vin Vc (T1 )RK 2
LIT 12L(11)where T1 is the period which the Mode II ends, T2 is theperiod of the Mode III. In other words, At T2, the current
polarity of equivalent load is changed.  is the natural angularfrequency, K is the coefficient, IT1 is the current of theequivalent load at t=T1, Vc(T1) is the voltage of the equivalent
resonant capacitor at t=T1.

IV.

EXPERIMENTAL RESULTS

Specifications of a prototype circuit is as following. The
number of phase in the multi-phase inverter N is five. In orderto obtain the output frequency fout of 2.5 MHz, the switchingfrequency fsw is 500 kHz. The input voltage Vin is 48 V. A load
resistance is 33.3  which is a non-inductive resistance.
A. Operation waveforms
Figure 5 shows the experimental waveforms at ZVS
condition. The dead time Td = 97.1 ns which satisfies (6) isused. From Fig. 5(a), it is confirmed that the load voltage isalmost sinusoidal waveform due to the series resonance.
Fig. 5(b) and (c) show two gate signals, the drain-source
voltage of S2 and the primary current of the multi-coretransformer. From the result, there is no rise of vds2 during thedead time because the dead time which satisfies (6) is used.
Figure 6 shows the experimental waveforms at hard-vgs(S1)20 (V)

vgs(S1)

vgs(S2)20 (V)

vgs(S2)0vgs(S1,S2)0vgs(S1,S2)

vload

vload

20 (V)

20 (V)

0vload0vloadiload

1 (A)

iload

200 (ns)

1 (A)

200 (ns)0iload0iload(a) Load voltage and load current.

vgs(S1)20 (V)(a) Load voltage and load current.

vgs(S1)

vgs(S2)20 (V)

vgs(S2)0vgs(S1,S2)0vgs(S1,S2)

vds2

vds2

20 (V)

20 (V)

200 (ns)

200 (ns)
0
vds2
0iu

iu

0
vds2
0iu

5 (A)

iu

5 (A)

(b) drain-source voltage and primary current of multi-core transformer. (b) drain-source voltage and primary current of multi-core transformer.

vgs(S1)20 (V)

vgs(S1)

vgs(S2)

vgs(S2)

vds2

vds2

20 (V)

20 (V)

0vds2
0iu

20 (V)

0vgs(S1,S2)0vgs(S1,S2)iu

5 (A)

20 (ns)(c) Enlarged waveforms of (b)Figure 5. Experimental waveforms at ZVS (Td=97.1 ns).

0
vds2
0iu

iu

5 (A)

20 (ns)(c) Enlarged waveforms of (b)Figure 6. Experimental waveforms at hard-switching (Td=117.6 ns).

From these experiments, the proposed circuit obtains highefficiency because zero voltage switching is achieved eventhough the output frequency is 2.5 MHz.
B. Input and output power measurement
Figure 7 shows the measured input and output power ofthe prototype circuit at low power when the dead time varies.
It is noted that the load resistance is constant. The input andoutput power are the highest at ZVS condition because theswitching loss is the lowest and dead time is the shortest. On
the other hand, at hard-switching condition, the input power isdecreased with the increasing dead time. In addition, theoutput power is decreased because the switching loss becomes
higher.
V.

CONCLUSION

This paper described the high-frequency inverter which
outputs MHz frequency based on the multiplying frequency
method. By the frequency multiplying, the proposed circuit
outputs high frequency which is over the switching frequency.
First, the required dead time which achieves ZVS was derived
by using the equivalent circuit. Finally, the prototype circuit
was experimentally verified. It was confirmed the prototype
circuit can output 2.5 MHz with the switching frequency of
500 kHz at ZVS condition.
REFERENCES
[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

H. Fujita, H. Akagi, S. Shinohara: “A 2-MHz 6-kVA Voltage-Source
Inverter Using Low-Profile MOSFET Modules for Low-Temperature
Plasma Generators”, Power Electronics, IEEE Transactions on , Vol.14,
No.6, pp. 1014-1020 (1999)
Y. Sakamoto, K. Wada, T. Shimizu: "A 13.56 MHz Current-outputtype Inverter Utilizing An Immittance Conversion Element", EPEPEMC 2008, pp. 288-294 (2008)
S. Suzuki, T. Shimizu: "A Study on Efficiency Improvement of Highfrequency Current Output Inverter based on Immittance Conversion
Element", IPEC 2014, pp. 1166-1172 (2014)
J. A. García, R. Marante, M. de las Nieves Ruiz Lavín: “GaN HEMTClass E2 Resonant Topologies for UHF DC/DC Power Conversion”,
Microwave theory and techniques, IEEE Transactions on , Vol.60,
No.12, pp. 4220-4229 (2012)
J. M. Burkhart, R. Korsunsky, D. J. Perreault: “Design Methodology
for a Very High Frequency Resonant Boost Converter”, PowerElectronics, IEEE Transactions on , Vol.28, No.4, pp. 1929-1937(2013)
H. Zhou, W. Liu, E. Persson: "Evaluation of GaN, SiC andSuperjunction in 1 MHz LLC Converter", PCIM2015, pp. 600-605(2015)
K. Orikawa, J. Itoh: "Experimental Verification of MHz Inverter
Constructed from Frequency Multiplying Circuit with Soft-Switching",
PCIM2015, pp. 635-642 (2015)
G. Ortiz, J. Biela, D. Bortis, J. W. Kolar: “1 Megawatt, 20 kHz,Isolated, Bidirectional 12kV to 1.2kV DC-DC Converter for Renewable
Energy Applications”, The 2010 International Power Electronics
Conference, pp. 3212-3219 (2010)

ZVS

25

Input power Pin (W)Output power Pout (W)switching condition which does not satisfy (6). In Fig. 6, thedead time Td = 117.6 ns. Therefore, hard-switching occurs
because vds2 is increased during the dead time.

Hard-switching
Input power Pin20Fig. 515Output power Pout

Fig. 610fsw : 500 (kHz)fout : 2.5 (MHz)Vin : 48 (V)

5090

100

110
120
Dead time Td (ns)130

Figure 7. Input power and output power.

140