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Automotive Smart Power
Module, The 1200 V
ASPM34 Series,
Application Note
AND90041

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INTRODUCE
The 1200 V ASPM34 series extends the existingIntelligent Power Module product portfolio, qualifying
them to meet the performance and reliability requirementsof automotive auxiliary motor drives in Hybrid and Electric
Vehicle application. This application note supports the1200 V ASPM34 series. It should be used in conjunction
with the 1200 V ASPM34 datasheets and application noteAN−9076 (Mounting Guidance).

APPLICATION NOTE
gate−driving High−Voltage Integrated Circuit (HVIC), a
new Insulated−Gate Bipolar Transistor (IGBT) of advanced
silicon technology, and improved Direct Bonded Copper(DBC) substrate base transfer mold package. The 1200 V
ASPM34 achieves reduced board size and improved
reliability compared to existing discrete solutions. Target
applications are inverter motor drives for Auto−motive use,such as E−compressor, Oil pump, Fuel pump, Water pump,cooling fans and other auxiliary motors in Hybrid andElectric Vehicles.
A design advantage integrates an NTC thermistor for
temperature measuring of power chips (e.g. IGBTs,
Fast−Recovery Diode (FRDs) on the same substrate. Most
customers want to know the exact temperature of powerchips because temperature affects the quality, reliability, andlongevity of products. This desire is thwarted because
integrated power chips (e.g. IGBTs, FRD) inside modules
operate in high−voltage conditions. Therefore, instead of
directly sensing the temperature of power chips, customers
have been using an external NTC thermistor for sensing thetemperature of the module or heat−sink. This method
doesn’t accurately reflect the temperature of powercomponents due to cost, but is simple. The NTC thermistorof the 1200 V ASPM34 is integrated with the power chips
on the same ceramic substrate and therefore more accuratelyreflects the temperature of power chips.

Figure 1.
Design Concept

The 1200 V ASPM34 design objective is to provide aminimized package and a low power consumption modulewith improved reliability. This is achieved by applying new

Figure 2. External View and Internal Structure of the 1200 V ASPM34© Semiconductor Components Industries, LLC, 2020

May, 2021 − Rev. 1

1

Publication Order Number:AND90041/D

AND90041
Key Features• Single−Grounded Power Supply Supported• Built−in NTC Thermistor for Temperature Monitoringgate drivers and protection• Low−Loss, Short−Circuit Rated IGBTs• Very Low Thermal Resistance by Adopting DBC
Substrate• Built−In Bootstrap Diode and Dedicated Vs Pins
Simplify PCB Layout• Separate Open−Emitter pins from Low−Side IGBTs for
Three−Phase current sensing• Adjustable Over−Current Protection via Integrated• Automotive Qualified (AEC−Q100, Q101 and AQG324)• 1200 V ASPM34, 3−Phase IGBT inverter with Integraland Management

Sense−IGBTs• Isolation Rating of 2500 VRMS / 1 min• Pb−Free and RoHS compliant
PRODUCT DESCRIPTION
Ordering Information

N F V A 2 50 12 XX X X

Customized Option
None : Standard
Lead forming
1 : Short Lead /Zig Zag /Double N
2 : Long Lead /Flat /Flat N

Voltage Rating
65 : 650 V
12 : 1200 V

Configuration
A : Inverter

Package type
2 : ASPM 34
3 : ASPM 27
9 : ASPM 14

Silicon Technology
NP : NPT Trench IGBT
L3 : Field Stop Trench IGBT
L4 : Field Stop Trench IGBT
Current Rating
30 : 30A rating
40 : 40A rating
50 : 50A rating

Automotive
None : Standard
V : Auto Qualified
IPM & SPM
N :ON Semiconductor

Figure 3. Ordering Information
Product Line−up

Motion Control Design Tool is recommended to find out theright the 1200 V ASPM34 product for the desired
application.

Table 1 shows the basic line up without package
variations. Online loss and temperature simulation tool,
Table 1. PRODUCT LINE−UP
Target Application

DeviceIGBT Rating

Motor Rating (Note 1)

Isolation Voltage

E−compressor, Oil pump,
Fuel pump, Water pump,
Cooling FansNFVA22512NP2T

25 A / 1200 V

3.7 kW / 440 VAC

NFVA23512NP2T

35 A / 1200 V

5.5 kW / 440 VAC

VISO = 2500 VRMS
(Sine 60 Hz, 1−min
All Shorted Pins Heat Sink)

NFVA25012NP2T

50 A / 1200 V

7.5 Kw / 440 VAC

1. These motor ratings are simulation results under following conditions: VAC = 440 V, VDD = 15 V, TC = 100°C, Tj = 150°C, fPWM = 5 kHz,PF = 0.8, MI = 0.9, Motor efficiency = 0.75, overload 150% for 1min.
These motor ratings are general ratings, so may be changed by conditions.

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2

3

www.onsemi.com(16 ) CFOD
(15 ) VFO
(14 ) IN (WL)
(13 ) IN (VL)
(12 ) IN (UL)
(11 ) COM (L)(10 ) VDD(L)(6) NV(8) RTH(9)VTH(7) NU(17 ) CSC

(5) NW(18 ) RSC

(22 ) VBD(U)(21 ) VDD(UH )(20 ) COM (H)(19 ) IN (UH )(24 ) VS(U)(23 ) VB(U)

(3) V

(4) U

(27 ) VBD(V)(26 ) VDD(VH)(25 ) IN (VH)

(29 ) VS(V)(28 ) VB(V)(32 ) VBD(W )(31 ) VDD(WH )(30 ) IN (WH )

(2) W

(1) P

(34 ) VS(W )(33 ) VB(W )AND90041
PACKAGEInternal Circuit Diagram

There is the internal circuit diagram of the 1200 V
ASPM34 as shown in Figure 4.

Figure 4. The 1200 V ASPM34 Version Internal Circuit

Pin Description

Figure 5 shows the location of pins and the names of the1200 V ASPM34 series.

Figure 5. Package Top−View and Pin Assignment

AND90041
In the later section illustrates the internal structure of themodule in more detail. The detail functional descriptions areprovided in Table 2.
Table 2. PIN DESCRIPTION
Pin No.

Name

Description

1

P

Positive DC Link Input

2

W

Output for W Phase

3

V

Output for V Phase

4U

Output for U Phase

5

NW

Negative DC Link Input for W Phase

6

NV

Negative DC Link Input for V Phase

7

NU

Negative DC Link Input for U Phase

8

RTH

Series Resistor for Thermistor (Temperature Detection)

9

VTH

Thermistor Bias Voltage

10

VDD(L)

Low−Side Bias Voltage for IC and IGBT Driving

11

COM(L)

Low−Side Common Supply Ground

12

IN(UL)

Signal Input for Low−Side U Phase

13

IN(VL)

Signal Input for Low−Side V Phase

14

IN(WL)

Signal Input for Low−Side W Phase

15

VFO

Fault Output

16

CFOD

Capacitor for Fault Output Duration Selection

17

CSC

Capacitor (Low−Pass Filter) for Short−Circuit Current Detection Input

18

RSC

Resistor for Short−Circuit Current Detection

19

IN(UH)

High−Side Common Supply Ground

20

COM(H)No Connection

21

VDD(UH)High−Side Bias Voltage for U Phase IGBT Driving

22

VBD(U)

Anode of Bootstrap Diode for High−Side U Phase

23

VB(U)

High−Side Bias Voltage for U Phase IGBT Driving

24

VS(U)

High−Side Bias Voltage Ground for U Phase IGBT Driving

25

IN(VH)

Signal Input for High−Side V Phase26

VDD(VH)High−Side Bias Voltage for V Phase IC

27

VBD(V)

Anode of Bootstrap Diode for High−Side V Phase

28

VB(V)

High−Side Bias Voltage for V Phase IGBT Driving

29

VS(V)

High−Side Bias Voltage Ground for V Phase IGBT Driving

30

IN(WH)

Signal Input for High−Side W Phase

31

VDD(WH)High−Side Bias Voltage for W Phase IC

32

VBD(W)

Anode of Bootstrap Diode for High−Side W Phase

33

VB(W)

High−Side Bias Voltage for W Phase IGBT Driving

34

VS(W)

High−Side Bias Voltage Ground for W Phase IGBT Driving

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AND90041
Detailed Pin Definition and Notification

Pin: RSC• Resistor Connection Pin for Short−Circuit Current
Detection.
• Low−side sense IGBT current flows through this pin.
Short−circuit and over−current can be detected at this pin
through an external resistor. (Refer to Figure 45)• If using three shunt resistors at N terminals for OCP and
SCP without sense detecting from RSC, RSC should beconnected to COM.

Pins: VB(U)−VS(U), VB(V)−VS(V), VB(W)−VS(W)• High−side bias voltage pins for driving the IGBT /high−side bias voltage ground pins for driving the IGBTs.
• These are drive power supply pins for providing gate
drive power to the high−side IGBTs.
• By virtue of the ability of bootstrap, the circuit scheme isthat no external power supplies are required for thehigh−side IGBTs.
• Each bootstrap capacitor is charged from the VDD supply
during ON state of the corresponding low−side IGBT.
• To prevent malfunctions caused by noise and ripple in the
supply voltage, a low−ESR, low−ESL filter capacitor
should be mounted very close to these pins.

Pin: CSC• Short−Circuit and Over−Current Detection Input Pin.
• The current sense current detecting resistor (RSC) should

be connected between CSC and COM pins to detectover−current and short−circuit current. (Refer toFigure 45)• The shunt resistor should be selected to meet the detectionlevels matched for the specific application. The RC filter
should be connected to the CSC pin to eliminate noise.
• The connection length between the shunt resistor and CSC
pin should be minimized.

Pins: VDD(L), VDD(WH), VDD(VH), VDD(UH)• Low−Side Bias Voltage Pin / High−Side Bas Voltage.
• These are control supply pins for the built−in ICs.
• These four pins should be connected externally.
• To prevent malfunctions caused by noise and ripple in the
supply voltage, a low−ESR, low−ESL filter capacitor
should be mounted very close to these pins.

Pin: VFO• Fault output pin.
• This is the fault output alarm pin. An active LOW output

Pins: COM(L), COM(H)• Low−Side Common Supply Ground pins.
• These are supply ground pins for the built−in ICs.
• These two pins should be connected externally.
• Important! To avoid noise influences, the main poweris given on this pin for a fault state condition in the
ASPM34.
• The alarm conditions are: Short−Circuit Current
Protection (SCP), and low−side bias Under−Voltage
Lockout (UVLO).
• The VFO output is open drain configured. The VFO
signal line should be pulled to the 5 V logic power supply
with approximately 4.7 kW resistance.

circuit current should not be allowed to flow through thispin.

Pins: VBD(UH), VBD(VH), VBD(WH)• Anode Pins of Bootstrap Diode pins.
• These are pins to connect internal bootstrap diode for eachhigh−side bootstrapping.
• External resistor should be connected between these pins
and each VDD(xH).

Pin: VTH• Thermistor Bias Voltage.
• This is the bias voltage pin of internal thermistor. This pinshould be connected to the 5 V logic power supply.

Pins: IN(UL), IN(VL), IN(WL), IN(UH), IN(VH), IN(WH)• Signal Input Pins.
• These pins control the operation of the built−in IGBTs.
• They are activated by voltage input signals. The terminals
are internally connected to a Schmitt−trigger circuitcomposed of 5 V−class CMOS.
• The signal logic of these pins is active HIGH. The IGBT
associated with each of these pins is turned ON when asufficient logic voltage is applied to these pins.
• The wiring of each input should be as short as possible toprotect the 1200 V ASPM34 against noise influences.
• To prevent signal oscillations, an RC coupling as
illustrated in Figure 45 is recommended.

Pin: RTH• Thermistor Bias Voltage.
• For case temperature (TC) detection, this pin should beconnected to an external series resistor.

• The external series resistor should be selected to meet thedetection range matched for the specification of eachapplication. (For details, Refer to Table 22)

Pin: P• Positive DC−link pin.
• This is the DC−link positive power supply pin of theinverter.

• It is internally connected to the collectors of the high−side
IGBTs.

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5AND90041• To suppress surge voltage caused by the DC−link wiringor PCB pattern inductance, connect a smoothing filter
capacitor close to this pin (Tip: metal film capacitor istypically used).

Pins: NU, NV, NW• Negative DC−link pins.
• These are the DC−link negative power supply pins (power
ground) of the inverter.

• These pins are connected to the low−side IGBT emittersof the each phase.
• These pins have to be connected shunt resistor (one or
three) for current sensing.
Pins: U, V, W

Figure 6. Vertical Structure for Heat Dissipation• Inverter output pins for connecting to the inverter load(e.g. motor).

Package Structure

Since heat dissipation is an important factor limiting thepower module’s current capability, the heat dissipation
characteristics of a package are important in determining theperformance. A trade−off exists among heat dissipation
characteristics, package size, and isolation characteristics.
The key to good package technology lies in the optimization
package size while maintaining outstanding heat dissipation
characteristics without compromising the isolation rating.
In 1200 V ASPM34, technology was developed with
DBC substrate that resulted in good heat dissipation
characteristics. Power chips are attached directly to the DBC
substrate. This technology is applied 1200 V ASPM34
achieving improved reliability and heat dissipation.
Figure 6 and Figure 7 show the package outline and thecross−sections of the 1200 V ASPM34 package.

Figure 7. Distance for Isolationwww.onsemi.com
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AND90041
Detailed Package Outline Drawings

Figure 8. Package Outline Drawing

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7AND90041
Marking Specification

Figure 9. Marking Layout
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AND90041
PRODUCT SYNOPSIS
This section discusses electrical specification,
characteristics and mechanical characteristics.
Absolute Maximum Rating (TJ = 255C, Unless
Otherwise Specified)
Table 3. INVERTER PART (BASE ON NFVA25012NP2T)
SymbolVPN
VPN(Surge)

Parameter

Conditions

Rating

Unit

Supply Voltage

Applied between P –NU, NV, NW

900

VSupply Voltage (Surge)

Applied between P – NU, NV, NW

1000

V

1200

V

VCES

Collector – Emitter Voltage±IC

Each IGBT Collector Current

TC = 100°C, TDD ≤ 15V, TJ ≤ 150°C (Note 2)

50

A

±ICP

Each IGBT Collector Current (Peak)

TC = 25°C, TJ ≤ 150°C, Under 1 ms Pulse Width(Note 3)

75

A

PC

Collector Dissipation

TC = 25°C per One Chip (Note 3)

TJ

Operating Junction Temperature(Note 3)

IGBT and Diode

347

W

VCES = 960 V−40~150°C

VCES = 1200 V−40~125

Driver IC−40~150

2. These values had been made an acquisition by the calculation considered to design factor.
3. The maximum junction temperature rating of power chips integrated within the 1200 V ASPM34 products is 150°C.

Table 4. CONTROL PART
SymbolParameter

Conditions

RatingUnit

VDD

Control Supply Voltage

Applied between VDD(H), VDD(L) − COM

20

V

VBS

High−Side Control Bias Voltage

Applied between VB(U)−VS(U), VB(V)−VS(V),VB(W)−VS(W)

20

V

VIN

Input Signal Voltage

Applied between IN(UH), IN(VH), IN(WH), IN(UL),
IN(VL), IN(WL) − COM−0.3~VDD + 0.3

VVFO

Fault Output Supply Voltage

Applied between VFO – COM−0.3~VDD + 0.3

VIFO

Fault Output Current

Sink Current at VFO Pin

2

mA

VSC

Current Sensing Input Voltage

Applied between CSC − COM−0.3~VDD + 0.3

V

Rating

Unit

1200

V

Table 5. BOOTSTRAP DIODE PART
SymbolParameter

VRRM

Maximum Repetitive Reverse Voltage

Conditions

IF

Forward Current

TC = 25°C, TJ ≤ 150°C (Note 3)

1.0

A

IFP

Forward Current (Peak)

TC = 25°C, TJ ≤ 150°C, Under 1 ms Pulse Width(Note 3)

2.0

A

Tj

Operating Junction Temperature(Note 5)−40~150°C

Conditions

Rating

Unit

VDD = VBS ≤ 16.5 V, VPN ≤ 800 V, TJ = 150°C
Non−repetitive3

ms

Table 6. TOTAL SYSTEM
SymbolParametertSC

Short Circuit Withstand Time

TSTG

Storage Temperature

VISO

Isolation Voltage

60 Hz, Sinusoidal, 1−Minute, Connect Pins toHeat Sink

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9−40~150

°C

2500

Vrms

AND90041
Table 7. THERMAL RESISTANCE
SymbolParameter

Rth(j−c)Q

Junction to Case Thermal Resistance(Note 4)
Package Stray InductanceRth(j−c)F
Ls

Conditions

Min

Typ

Max

Unit

Inverter IGBT Part (per 1/6 Module)

−

−

0.36

°C/W

Inverter FWD Part (per 1/6 Module)

−

−

0.66

P to NU, NV, NW (Note 5)

−

32

−

nH

4. For the measurement point of case temperature (TC), please refer Figure 10. DBC discoloration and Picker Circle Printing allowed, pleaserefer to application note AN−9190 (Impact of DBC Oxidation on SPM® Module Performance).
5. Stray inductance per phase measured per IEC 60747−15.

Figure 10. Case Temperature (TC) Detecting Point

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10AND90041
Electrical Characteristic (TJ = 255C, Unless Otherwise
Specified)
Table 8. INVERTER PART (BASE ON NFVA25012NP2T)
SymbolParameter

VCE(SAT)

Collector–Emitter
Saturation Voltage

VDD, VBS = 15 V,
VIN = 5 V

FWDi Forward Voltage

VIN = 0 V

VF
HS

tON

Condition

Switching Times

Min

Typ

Max

Unit

IC = 50 A, TJ = 25°C

−

2.20

2.80

V

IC = 50 A, TJ = 150°C

−

2.75

3.25

V

IF = 50 A, TJ = 25°C

−

2.40

3.00

V

IF = 50 A, TJ = 150°C

−

2.25

2.85

V

0.90

1.40

2.00

ms

−

0.50

0.95

ms

VPN = 600 V, VDD = 15 V, IC = 30 A TJ = 25°C,
VIN = 0 V ↔ 5 V, Inductive Load
See Figure 12 (Note 6)tC(ON)
tOFF

−

1.10

1.70

ms

tC(OFF)

−

0.15

0.55

ms

trr

−

0.20

−

ms

tON

0.50

1.00

1.60

ms

tC(ON)

−

0.50

0.95

ms

tOFF

−

1.10

1.70

ms

tC(OFF)

−

0.25

−

ms

trr

−

0.15

−

ms

−

−

3

mA

LS

ICES

Collector – Emitter
Leakage Current

TJ = 25°C, VCE = VCES

6. tON and tOFF include the propagation delay time of the internal drive IC. tC(ON) and tC(OFF) are the switching time of IGBT itself under the
given gate driving condition internally. For the detail information, please see Figure 11 and Figure 12.
15 V
Only for low side switchingLine stray Inductance < 100 nH

One−Leg Diagram of ASPM34
VB

P

VDD
IN
Switching Pulse

HO

Inducotor

VS

600 V

COM

15 V

OUT
VDD

LO

Inducotor

IN
Switching Pulse
COM

N

Line stray Inductance < 100 nH

Figure 11. Switching Evaluation Circuit

Figure 12. Switching Evaluation Circuit andSwitching Time Definition

Table 9. BOOTSTRAP DIODE PART (BASE ON NFVA25012NP2T, Tj AS SPECIFIED)
SymbolParameter

Condition

Min

Typ

Max

Unit

VF

Forward Voltage

IF = 1.0 A, Tj = 25°C

−

2.2

−

V

trr

Reverse−Recovery TimeIF = 1.0 A, dIF / dt = 50 A/ms, TJ = 25°C

−

80

−

ns

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AND90041
Table 10. CONTROL PART (BASE ON NFVA25012NP2T)
SymbolIQDDHParameter
Quiescent VDD Supply
Current

IQDDL
IPDDH

Operating VDD Supply
Current

IPDDL

Condition

Min

Typ

Max

Unit
mA

VDD(UH,VH,WH) = 15 V,
IN(UH,VH,WH) = 0 V

VDD(UH) − COM(H),VDD(VH) − COM(H),VDD(WH ) − COM(H)

−

−

0.15

VDD(L) = 15 V, IN(UL,VL,WL) = 0 V

VDD(L) – COM(L)

−

−

4.80

VDD(UH,VH,WH) = 15 V,
fPWM = 20 kHz, Duty = 50%,
Applied to one PWM Signal
Input for High Side

VDD(UH) – COM(H),VDD(VH) – COM(H),VDD(WH) – COM(H)

−

−

0.30

mA

VDD(L) = 15 V, fPWM = 20 kHz,
Duty = 50%, Applied to One
PWM Signal Input for Low SideVDD(L) – COM(L)

−

−

15.5

mA

IQBS

Quiescent VBS Supply
Current

VBS = 15 V, IN(UH,VH,WH) = 0 V

VB(U) – VS(U),VB(V) – VS(V),VB(W) – VS(W)

−

−

0.30

mA

IPBS

Operating VBS Supply
Current

VDD = VBS = 15 V,
fPWM = 20 kHz, Duty = 50%,
Applied to One PWM Signal
Input for High Side

VB(U) – VS(U),VB(V) – VS(V),VB(W) – VS(W)

−

−

12.0

mA

VFOH

Fault Output Voltage

VDD = 15 V, VSC = 0 V, VFO Circuit: 4.7 kW to 5 V Pull−up

4.5

−

−

V

VDD = 15 V, VSC = 1 V, VFO Circuit: 4.7kW to 5 V Pull−up

−

−

0.5

VFOL
ISEN

Sensing Current of Each
Sense IGBTVDD = 15 V, VIN = 5 V, RSC = 0 W,
No Connection of Shunt Resistor
at NU,V,W Terminal

Ic = 50 A

−

43

−

mA

VSC(ref)

Short−Circuit Trip Level

VDD = 15 V (Note 7)

CSC – COM(L)

0.43

0.50

0.57

V

ISC

Short Circuit Current
Level for Trip

RSC = 13 W (±1%), No Connection of Shunt Resistor at
NU, V, W Terminal (Note 7)

−

75

−

A

Supply Circuit,
Under−Voltage Protection

Detection Level

10.3

−

12.8

V

Reset Level

10.8

−

13.3

UVBSD

Detection Level

9.5

−

12.0

UVBSR

Reset Level

10.0

−

12.5

50

−

−

ms

CFOD = 2.2 nF

1.7

−

−

ms

Applied between IN(UH,VH,WH) – COM(H),
IN(UL,VL,WL) – COM(L)

−

−

2.6

V

0.8

−

−

−

47

−

−

2.9

−

UVDDD
UVDDR

tFOD

Fault−Out Pulse Width

VIN(ON)ON Threshold Voltage

VIN(OFF)

OFF Threshold Voltage

RTH

Resistance of Thermistor(Note 8)

CFOD = Open

See Figure 13(Note 9)at TTH = 25°C
at TTH = 100°C

7. Short−circuit current protection is functioning only at the low-sides.
8. The fault−out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation:
tFOD = 0.8 x 106 x CFOD [s].
9. TTH is the temperature of thermistor itself. To know case temperature (TC), conduct experiments considering the application.

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kWAND90041

Figure 13. Temperature Profile of VTS (Typical)

Table 11. RECOMMENDED OPERATING CONDITIONS (BASE ON NFVA25012NP2T)
SymbolParameter

Condition

Min

Typ

Max

Unit

VPN

Supply Voltage

Applied between P − NU, NV, NW

300

600

800

V

VDD

Control Supply Voltage

Applied between VDD(UH,VH,WH) – COM(H),VDD(L) – COM(L)

14.0

15.0

16.5

V

VBS

High−Side Bias Voltage

Applied between VB(U) − VS(U),VB(V) – VS(V), VB(W) − VS(W)

13.0

15.0

18.5

V

dVDD/dt, dVBS/dt

Control Supply Variation

−1

−

1

V/ms

tdead

Blanking Time for Preventing
Arm−Short

For Each Input Signal

2.0

−

−

ms

fPWM

PWM Input Signal−40°C ≤ TC ≤ 125°C, −40°C ≤ TJ ≤ 150°C

−

−

20

kHz

VSEN

Voltage for Current Sensing

Applied between NU, NV, NW – COM(H,L)(Including Surge Voltage)

−5

−

5

V

PWIN(ON)

Minimum Input Pulse Width

VDD = VBS = 15 V, IC ≤ 75 A, Wiring
Inductance between NU,V,W and DC
Link N < 10 nH (Note 10)

2.5

−

−

ms

2.5

−

−

−40

−

150

°C

Min

Typ

Max

Unit

0

−

+150

mm

Recommended 1.0 N·m

0.9

1.0

1.5

N·m

Recommended 10.1 kg·cm

9.1

10.1

15.1

kg·cm

PWIN(OFF)
TJ

Junction Temperature

10. This product might not make response if input pulse with is lee than the recommended value.

Table 12. MECHANICAL CHARACTERISTICS
Parameter

Condition

Device Flatness

See Figure 14

Mounting Torque

Mounting Screw: M4
See Figure 15

Terminal Pulling Strength

Load 19.6 N

10

−

−

s

Terminal Bending Strength

Load 9.8 N, 90° Bend

2

−

−

Times

Module Weight

−

50

−

g

Weightwww.onsemi.com
13

AND90041

Figure 14. Flatness Measurements Position

NOTES:
11. Do not make over torque when mounting screws. Much mounting torque may cause DBC crack, as well as bolts Al heat sink destruction.
12. Avoid one−sided tightening stress, Figure 15 shows the recommended torque order for mounting order for mounting screws. Uneven
mounting can cause the DBC substrate of package to be damaged. The pre−screwing torque is set to 20~30% of maximum torque rating.

Figure 15. Mounting Screw Torque Orderwww.onsemi.com
14

AND90041
OPERATION SEQUENCE FOR PROTECTIONS
Short Circuit Protection

The 1200 V ASPM34 uses a sense current detecting
resistor (RSC) for the short circuit current detection, as
shown in Figure 16. LVIC has a built−in short−circuitcurrent protection function. This protection function senses
the voltage to the CSC pin. If this voltage exceeds the
VSC(ref) (the threshold voltage trip level of theshort−circuit) specified in the device datasheets (typ.
VSC(ref) is 0.5 V), a fault signal is asserted and the all low
side IGBTs are turned off. Typically, the maximum
short−circuit current magnitude is gate−voltage dependent:
higher gate voltage (VDD & VBS) results in larger
short−circuit current. To avoid potential problems, themaximum short−circuit trip level is set below 1.7 times thenominal rated collector current. The LVIC short−circuitcurrent protection−timing chart is shown in Figure 17.

1200 V ASPM34PI SC (Short−Circuit Current)

HVIC
UH

VH

C

Short−
Circuit!

UL
CSC
LPF
Circuitof SCP

RF
C SC

RSC

WL

VL
NV

NU

R SC

SC Trip Level : V SC (REF )I SC (Short−Circuit Current)

Figure 16. Operation of Short−Circuit Protection

A7

SET

RESET
Soft turn−off for small voltage
spike (to prevent of L*di/dt
effect)Protection circuit state
A4
A3

SC

External filter is recommended
with 1~2 ms time constant

NW

Operates protection function. ( All LS IGBTs are shutdown)

p

A6

A2

Motor
W
V
U

LVIC

Lower arms control input

Lower arms gate input

WH

External filter delay + internal
IC delay + IGBT off delay <SCWT (Typical 2~3 ms).

A1
A8

Output Current

IC filtering < 500 ns.
SC Reference Voltage

Sensing Voltage (of RSC )Fault Output Signal

A5

t FOD

NOTES:
13. A1 - normal operation: IGBT on and carrying current.
14. A2 - short−circuit current detection (SC trigger).
15. A3 - hard IGBT gate interrupt.
16. A4 - IGBT turns OFF by soft−off function.
17. A5 - fault output timer operation start with internal delay (typ. 2.0 ms), tFOD = controlled by CFOD.
18. A6 - input “L”: IGBT OFF state.
19. A7 - input “H”: IGBT ON state, but during the active period of fault output the IGBT doesn’t turn ON.
20. A8 - IGBT keeps OFF state

Figure 17. Timing Chart of Short−Circuit Protection Function

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15

Fault−out duration (tFOD):
Controlled by CFOD.

AND90041
Under−Voltage Lockout Protection (Low−side UVLO)

The LVIC has an Under−Voltage Lockout protection(UVLO) function to protect the low−side IGBTs fromoperation with insufficient gate driving voltage. A timing
chart for this protection is shown in Figure 18.

Input Signal

Protection Circuit
State
Fault signal keep until
recover VDDR

RESET

SET

RESET

UV DDR

Control
Supply Voltage
IGBT don’t turn On until
inputting next ON signal(L ⇒ H, Edge trigger)

B1

UV DDD
B2

B6
To prevent malfunction by noise,
Filter time is around 10 ms

B3
B7

B4

RestartOutput Current

All Low− side IGBT are lockedwith VFO signal
High−level (no fault output)
B5

NOTES: (Low−Side Protection Sequence)
21. B1 − control supply voltage rise: after the voltage rises UVDDR, the circuits starts to operate when the next input is applied (L ⇒ H)
22. B2 − normal operation: IGBT ON and carrying current.
23. B3 − under−voltage detection (UVDDD).
24. B4 − IGBT OFF in spite of control input is alive.
25. B5 − Fault output signal starts.
26. B6 − under−voltage reset (UVDDR).
27. B7 − normal operation: IGBT ON and carrying current. If fault−out duration (tFOD) by external capacitor at CFOD pin is longer than UVDDR
timing, fault output and IGBT state are cleared after tFOD.

Figure 18. Timing Chart of Low−side Under−Voltage Protection Function

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AND90041
Under−Voltage Lockout Protection (High−side UVLO)

voltage. A timing chart for this protection is shown in
Figure 19. The fault−out (FO) alarm is not given for low
HVIC bias conditions.

The HVIC has an under−voltage lockout function toprotect the high−side IGBT from insufficient gate driving

Input Signal
Protection Circuit
State

RESET

SET

RESET

UV BSR
Control
Supply Voltage

C1

UV BSDC2

IGBT don’t turn On until
inputting next ON signal(L ⇒ H, Edge trigger)

C5
C3

C4

RestartC6

All Low−side IGBT are locked
without VFO signal

Output Current
Fault Output Signal

To prevent malfunction by noise,
Filter time is around 11 ms

High−level (no fault output)

NOTES: (High−Side Protection Sequence)
28. C1 − control supply voltage rises: after the voltage reaches UVBSR, the circuit starts when the next input is applied (L ⇒ H).
29. C2 − normal operation: IGBT ON and carrying current.
30. C3 − under−voltage detection (UVBSD).
31. C4 − IGBT OFF in spite of control input is alive, but there is no fault output signal.
32. C5 − under−voltage reset (UVBSR).
33. C6 − normal operation: IGBT ON and carrying current

Figure 19. Timing Chart of High-Side Under-Voltage Protection Function

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17

AND90041
KEY PARAMETER DESIGN GUIDANCE
N−side three IGBTs are turned off and the fault signal istransmitted from the 1200 V ASPM34 to MCU. Since
repetitive short circuit is not allowable, IGBT operation
should be immediately halted when the fault signal is given.
Figure 21 shows “RSC resistance vs. trip current” curve of
NFVA22512NP2T under the shunt resistor = 0 W condition.
For current sensing, apply an external shunt resistor ateach N terminal. Sensing voltage from RSC pin is influenced
by an external shunt resistor, as shown in Figure 22.
For adequate RSC value in a three−shunt structure, the RSC
value needs to be considered by the N−terminal shunt
resistor value and target protection current level.

For stable operation, there are recommended parameters
for passive components and bias conditions, considering
operating characteristics of the 1200 V ASPM34.
Selection of RSC Resistor for Protection

Figure 20 is an example circuit of the short−circuit
protection using the RSC resistor. Sense IGBT is employed
for the low side. The designer can use the RSC pin for
Over−Current Protection (OCP) and Short−CircuitProtection (SCP) without an external shunt resistor at the
N−terminal. The line current on RSC is detected and theprotective operation signal is passed through the RC filter.
If the current exceeds the VSC(ref), all the gates of the
HVIC. Level Shift. Gate Drive. UVLO
VS

VDC
3∅

Motor

IC [A]LVIC

VDD. Gate Drive. UVLO
. SCP

VFO

RSC

CSC

COM
V CSC

RF

C SC

100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10

Short Circuit
Current (ISC)

R SC

Trip Current Level @ VSC(ref) = 0.5 V
at shunt resistor = 0 W at N terminals
Tj = −40°C
Tj = 25°C
Tj = 150°C

0

5

10

15

20

25

30

35

40

45

50

55

60

RSC Resistance [W]Figure 21. RSC Resistance vs. Trip Current Level
for Protection at Variable Junction Temperature of
NFVA22512NP2T

Figure 20. Current Path in Short−Circuit Condition
by Leg Short Circuit

Trip Current Level @ Vsc = 0.5 V, RSC = 13 W
100

100

95

95

95

TJ = −40°C
TJ = 25°C
TJ = 150°C

90
85
80

TJ = −40°C
TJ = 25°C
TJ = 150°C

90
85
80

85
80

70

70

65

65

65

60

60

60

55

55

55

45

75

IC [A]

75

70

50

50
45

50
45

40

40

40

35

35

35

30

30

30

25

25

25

20

20

15

15

10

0

2

4

6

8

10

12

14

16

18

20

10

TJ = −40°C
TJ = 25°C
TJ = 150°C

9075

IC [A]IC [A]

Trip Current Level @ Vsc = 0.5 V, RSC = 47 W

Trip Current Level @ Vsc = 0.5 V, RSC = 27 W

100

20
15
0

2

4

6

8

10

12

14

16

18

20

10

0

2

4

6

8

10

12

14

16

Shunt Resistor at N Terminal [mW]

Shunt Resistor at N Terminal [mW]

Shunt Resistor at N Terminal [mW]

a)

b)

c)

Figure 22. Trip Current Level vs. Shunt Resistor of NFVA22512NP2T(a): RSC = 13 W, (b): RSC = 27 W, (c): RSC = 47 W

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18

18

20

AND90041
Trip Current Level @ VSC(ref) = 0.5 V
at shunt resistor = 0 W at N terminals

130
120

Tj = −40°C
Tj = 25°C
Tj = 150°C

110
100

IC [A]

90
80
70
60
50
40
30
20
0

5

10

15

20

25

30

35

40

RSC Resistance [W]Figure 23. RSC Resistance vs. Trip Current Level
for Protection at Variable Junction Temperature of
NFVA235(50)12NP2T

Trip Current Level @ Vsc = 0.5 V, RSC = 13 W

Trip Current Level @ Vsc = 0.5 V, RSC = 47 W

100

100

95

95

95

TJ = −40°C
TJ = 25°C
TJ = 150°C

90
85
80

TJ = −40°C
TJ = 25°C
TJ = 150°C

90
85
80

85
80

70

70

65

65

65

60

60

60

55

55

55

45

75

IC [A]

75

70

50

50
45

50
45

40

40

40

35

35

35

30

30

30

25

25

25

20

20

15

15

10

0

2

4

6

8

10

12

14

16

18

20

10

TJ = −40°C
TJ = 25°C
TJ = 150°C

9075

IC [A]IC [A]

Trip Current Level @ Vsc = 0.5 V, RSC = 27 W

100

20
15
0

2

4

6

8

10

12

14

16

18

20

10

0

2

4

6

8

10

12

14

16

Shunt Resistor at N Terminal [mW]

Shunt Resistor at N Terminal [mW]

Shunt Resistor at N Terminal [mW]

a)

b)

c)

Figure 24. Trip Current Level vs. Shunt Resistor of NFVA235(50)12NP2T(a): RSC = 8.2 W, (b): RSC = 16 W, (c): RSC = 30 W

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19

18

20

AND90041• Average DC Current:

Shunt Resistor Selection at N−Terminal for Current
Sensing & Protection

IDC_AVG + VDC_Link ń (Pout → Eff)

Where: Eff = Inverter efficiency

P• The power rating of shunt resistor is calculated by:

HVIC. Level Shift. Gate Drive. UVLOVSP SHUNT + (I 2 DC_AVG

VDC. Gate Drive. UVLO. SCP

VFO

5 V Line

NW
NV

Vref .

NU
VCSC

CSC

Vref .

RSC

CSC

COM

RF
RSC

RSC should be connected
to COM when it is not
used for current detection

Vref .

Figure 25. Recommended Circuitry for Over−Current& Short−Circuit Protection without RSC Pin Usage(eq. 1)

If the deviation of shunt resistor is limited below ±5%:
R SHUNT(typ) + R SHUNT(min) ń 0.95
1.05

(eq. 2)• The Actual SC Trip Current Level becomes:
I SC(typ) + V SC(typ) ń R SHUNT(typ)→ I SC(min) + V SC(min) ń R SHUNT(max)(eq. 3)• Inverter Output Power:
P OUT + Ǹ3
V O_LL +Ǹ3
Ǹ2

V O_LL
MI

I RMS
1
2

Conditions

Min

Typ

Max

Unit

Specification at
TJ = 25°C, VDD = 15 V

0.43

0.50

0.57

V

n Shunt Resistor Calculation Examples Calculation
Conditions:• DUT: NFVA25012NP2T• Tolerance of shunt resistor: ±5%• T.C.R: 350 ppm/°C• SC Trip Reference Voltage:
VSC(min) = 0.43 V, VSC(typ) = 0.50 V, VSC(max) = 0.57 V• Maximum Load Current of Inverter (IRMS): 12 Arms
• Maximum Peak Load Current of Inverter (IC(max)): 25 A
• Modulation Index(MI): 0.9• DC Link Voltage(VDC_Link): 600V
• Power Factor(PF): 0.8• Inverter Efficiency(Eff): 0.95
• De−rating Ratio of Shunt Resistor at TSHUNT = 100°C:
70% (refer to Figure 26.)
• Safety Margin: 20%

I SC(max) + V SC(max) ń R SHUNT(min)→ R SHUNT(max) + R SHUNT(typ)Margin) ń De−rating Ratio(eq. 7)

Table 13. OCP & SCP LEVEL (VSC (REF))
SPECIFICATION

If using three shunt resistors at N terminals for OCP and
SCP without sense detecting from RSC, RSC should beconnected to COM. The external RC time constant from the
N−terminal shunt resistor to CSC must be lower than 2 ms inshort circuit for stable shutdown.
The proper shunt resistance can be calculated by simple
equations as below.
VSC(ref) = min.0.43 V / typ. 0.5 V / max. 0.57 V(see Table 13.)
• Shunt Resistance:→ R SHUNT(min) + V SC(max) ń I SC(max)

R SHUNT

Where:
IDC_AVG: Average load current of inverter
RSHUNT: Shunt resistor typical value at TC = 25 [°C]
De-rating ratio:
Shunt resistor at TSHUNT = 100 [°C] from datasheet ofshunt resistor
Margin: Safety margin determined by customer’s system.

LVIC

VDD

(eq. 6)n Calculation Results:

PF

V DC_Link(eq. 4)• ISC(min) = Ic(max) = 25 A
• RSHUNT(max) @ Tj = 150°C = VSC(min) / Isc(min) =(eq. 5)• RSHUNT(max) = RSHUNT(max) @ Tj = 150°C / [1 + T.C.R

0.43 V / 25 A = 17.2 mW

x (150°C − 25°C)] = 17.2 mW / (1 + 350 x 10−6%/°C x
100°C) = 16.6 mW• RSHUNT(typ) = RSHUNT(max) / 1.05 = 15.8 mW• RSHUNT(min) = RSHUNT(typ) x 0.95 = 15.0 mW• ISC(typ) = VSC(typ) / RSHUNT(typ) = 0.5 V / 15.8 mW =31.6 A• ISC(max) = VSC(max) / RSHUNT(min) = 0.57 V / 15.0 mW =38.0 A

Where:
VO_LL: Inverter Output Lin to LineMI = Modulation Index
VDC_Link = DC link voltage
IRMS = Maximum load current of inverter
PF = Power Factor

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20

AND90041
Ǹ3• V O_LL + Ǹ

2
Ǹ3
+
Ǹ2

• P OUT + Ǹ3

+ Ǹ3

MI

1
2

0.9

0.5

Short−Circuit Current Withstanding Time (SCWT) of the1200 V ASPM34. When the RSC voltage exceeds the SCPlevel, this is applied to the CSC pin via the RC filter. The RC
filter delay (T1) is the time required for the CSC pin voltage
to rise to the referenced SCP level. The LVIC has an internalfilter time (logic filter time for noise elimination: T2).
Consider this filter time when designing the RC filter of
VCSC.

V DC_Link
600 V + 330.7 V

V O_LL I RMS PF
330.7 V 12 A 0.8 + 5499 W• IDC_AVG = (POUT / Eff) / VDC_Link = 5499 W / 0.95 /600 V = 9.65 A• PSHUNT = (I2DC_AVG x RSHUNT(max) x Margin) / Derating
Ratio = (9.652 x 0.0166 x 1.2) / 0.7 = 2.65 W(Therefore, the proper power rating of shunt resistor isover 3.0 W)
When over−current events are detected, the 1200 V
ASPM34 series shuts down all low−side IGBTs and sends
out the fault−out (FO) signal. Fault−out pulse width is fixed;
minimum value is 50 ms.
To prevent malfunction, it is recommended that an RC
filter be inserted at the CSC pin. To shut down IGBTs within
3 ms when over−current situation occurs, a time constantof 1.5~2 ms is recommended.

Low side IGBTG−E Voltage

Min

Typ

Max

Unit

RShunt

15.0

15.8

16.6

mW

Operation SC Level

25.0

31.6

38.0

A

t3

Fault
Output Signal

t2

IGBT
Current

Csc
Voltage

Table 14. OPERATION SHORT−CIRCUIT RANGE OFFNVA22512NP2T
Conditions

Over current conditiont1

Detection pointIGBT
C−E Voltage
Short circuit condition

t1
Low side IGBTG−E Voltage
t3

Fault
Output Signal

IGBT
Current

Csc
Voltaget2

Detection pointIGBT
C−E Voltage

Figure 26. De−rating Curve Example of Shunt
Resistor (from RARA Elec.)

NOTES:
34. t1: From CIN detection to gate driver LO shut down
35. t2: From CIN detection to collector current 10%
36. From CIN detection to fault out signal activation

Time Constant of Internal Delay

An RC filter is prevents noise−related Short−Circuit
Current Protection (SCP) circuit malfunction. The RC time
constant is determined by the applied noise time and the

Figure 27. Timing Diagram

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AND90041
Table 15. TIME TABLE OF OVER AND SHORT CIRCUIT CONDITIONS; VSC(ref) TO LOW SIDE GATE, COLLECTORCURRENT AND VFO
Over Circuit Condition

Ref. Condition
VDCbus = 600 V, VDD = 15 V
Devicet1 [ms]t2 [ms]Short Circuit Conditiont3 [ms]t1 [ms]t2 [ms]t3 [ms]Tj [5C]

Typ

Max

Typ

Max

Typ

Max

Typ

Max

Typ

Max

Typ

Max

25

1.90

2.40

2.40

3.00

3.45

4.30

2.25

2.80

2.50

3.15

3.75

4.70

150

1.80

2.25

2.30

2.90

3.10

3.90

2.15

2.70

2.40

3.00

3.45

4.30

NFVA23512NP2T

37. To guarantee safe short−circuit protection under all operating conditions, CSC should be triggered within 1.0 ms after short−circuit occurs.
(Recommendation: SCWT < 5.0 ms, Conditions: VDC = 800 V, VDD = 16.5 V, TJ = 150°C).
38. It is recommended that delay from short−circuit to CSC triggering should be minimized.

Fault Output Circuit

5V−LineMCU

1200 V ASPM 34

RPF = 4.7 kW
IN(UH), IN(VH), IN(WH)

Table 16. FAULT−OUTPUT MAXIMUM RATINGS
Item

Condition

RatingUnit

VFO

Fault Output
SupplyVoltage

Appliedbetween
VFO−COM−0.3~VDD + 0.3

VFault Output
Current

Sink Current
at VFO Pin

2

IN(UL), IN(VL), IN(WL)

Typ. 5 kW

Input
Noise
FilterGate
DrivertIN(FLT) = Typ. 450 ns for turn on
Typ. 250 ns for turn off

CPF =1 nF

mACOM

Figure 29. Recommended CPU I/O Interface Circuit

SymbolItem

Conditions

Min

Max

Unit

VFOH

Fault
OutputSupplyVoltage

VDD = 15 V, VSC = 0,
VFO Circuit: 4.7kW to
5 V Pull−Up

4.5

−

V

−

0.5

V

The input and fault output maximum rated voltages areshown in Table 18. Since the fault output is open drain, its
rating is VDD + 0.3 V, 15 V supply interface is possible.
However, it is recommended that the fault output be
configured with the 5 V logic supplies, which is the same as
the input signals. It is also recommended that thede−coupling capacitors be placed at both the MCU and1200 V ASPM34 ends of the VFO signal line, as close as
possible to each device. The RC coupling at each input (parts
shown dotted in Figure 29) can be changed depending on the
PWM control scheme used in the application and the wiring
impedance of the PCB layout.
The input signal section of the 1200 V ASPM34 series
integrates a 5 kW (typical) pull−down resistor. Therefore,
when using an external filtering resistor between the MCU
output and the 1200 V ASPM34 input, attention should begiven to the signal voltage drop at the 1200 V ASPM34 input
terminals to satisfy the turn−on threshold voltage
requirement.

Because VFO terminal is an open−drain type; it should be
pulled up via a pull−up resistor. The resistor must satisfy theabove specifications.
0.40
Tj = 150°C

0.35
0.30

VFO [V]

Gate
DriverVFO

Table 17. ELECTRICAL CHARACTERISTICS

VFOL

Level−Shift
CircuitTyp. 5 kW

Symbol

IFO

Input
Noise
Filter

0.25
0.20
0.15
0.10
0.05
0.00
0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

Table 18. MAXIMUM RATINGS OF INPUT AND VFO
PINS

2.0

IFO [mA]

Figure 28. Voltage−Current Characteristics of VFO
Terminal
Circuit of Input Signal (IN(xH), IN(xL))

Figure 29 shows the I/O interface circuit between the
MCU and 1200 V ASPM34. Because the 1200 V ASPM34
input logic is an active HIGH and there are built−in
pull−down resistors, external pull−down resistors are notneeded.

SymbolItem

Condition

Rating

Unit

VIN

Input Signal
Voltage

Appliedbetween IN(xH),
IN(xL)−COM(x)−0.3~
VDD + 0.3

V

VFO

Fault Output
SupplyVoltage

Appliedbetween
VFO−COM(L)−0.3~
VDD + 0.3V

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AND90041
Selection of Bootstrap Capacitor Considering Initial
Charging
Adequate on−time of the low−side IGBT to fully charge
the bootstrap capacitor is required for initial bootstrap
charging. The initial charging time (tcharge) can becalculated by:

Table 19. INPUT THRESHOLD VOLTAGE RATINGS(VDD = 15 V, TJ = 255C)
SymbolItem

Condition

Min

Max

Unit

VIN(ON)Turn−On
Threshold
Voltage

IN(UH), IN(VH),
IN(WH)−COM(H)

−

2.6

V

VIN(OFF)

Turn−Off
Threshold
Voltage

IN(UL), IN(VL),
IN(WL)−COM(L)

0.8

−

V

t charge + C BSVB
VDD(H)
COM(H)VDD

VS
VDD(L)CVDD

DBS (Integrated )P

VB
VDD HVIC

HO
VDC

VS

COM

VDD
LVIC

COM(L)V CC
V CC * V BS(min) * V F * V LS

ąD = Duty ratio of PWM.
When the bootstrap capacitor is charged initially; VDD
drop voltage is generated based on initial charging method,VDD line SMPS output current, VDD source capacitance,and bootstrap capacitance. If VDD drop voltage reaches
UVCCD level, the low side is shutdown and a fault signal isactivated. To avoid this malfunction, related parameter andinitial charging method should be considered. To reduce
VDD voltage drop at initial charging, a large VDD source
capacitor and selection of optimized low−side turn−on
method are recommended. Adequate on−time duration of
the low−side IGBT to fully charge the bootstrap capacitor is
initially required before normal operation of PWM starts.
Figure 32 shows an example of initial bootstrap charging
sequence. Once VDD establishes, VBS needs to be charged
by turning on the low−side IGBTs. PWM signals are
typically generated by an interrupt triggered by a timer witha fixed interval, based on the switching carrier frequency.
Therefore, it is desired to maintain this structure without
creating complementary high−side PWM signals. The
capacitance of VDD should be sufficient to supply necessary
charge to VBS capacitance in all three phases. If a normal
PWM operation starts before VBS reaches VUVLO reset
level, the high−side IGBTs cannot switch without creating
a fault signal. It may lead to a failure of motor start in some
applications. If three phases are charged synchronously,
initial charging current through a single shunt resistor may
exceed the over−current protection level. Therefore, initialcharging time for bootstrap capacitors should be separated,
as shown in Figure 32. The effect of the bootstrap
capacitance factor and charging method (low−side IGBT
driving method) is shown in Figure 33.

1200 V ASPM34
VBD

InWhere:
VF = Forward voltage drop across the bootstrap diode;
VBS(min) =The minimum value of the bootstrap capacitor;
VLS = Voltage drop across the low−side IGBT or load; andOperation of Bootstrap Circuit
The VBS voltage, which is the voltage difference between
VB (U, V, W) and VS (U, V, W), provides the supply to the
HVIC within the 1200 V ASPM34 series. This supply must
be in the range of 13.0 V~18.5 V to ensure that the HVIC canfully drive the high−side IGBT. The under−voltage lockout
protection for VBS ensures that the HVIC does not drive thehigh−side IGBT if the VBS voltage drops below a specificvoltage (refer to the datasheet). This function prevents the
IGBT from operating in a high−dissipation mode.
There are a number of ways in which the VBS floating
supply can be generated. One of them is the bootstrap
method described here. This method has the advantage ofbeing simple and inexpensive. However, the duty cycle andon−time are limited by the requirement to refresh the charge
in the bootstrap capacitor. The bootstrap supply is formed by
a combination of a bootstrap diode, resistor, and capacitor.
The current flow path of the bootstrap circuit is shown in
Figure 30. When VS is pulled down to ground (low−side
IGBT turn−on or low−side FRD freewheeling), thebootstrap capacitor (CBS) is charged through the bootstrap
diode (DBS) and the resistor (RBS) from the VDD supply.

CBS

1
D

(eq. 8)Bootstrap Circuit Design

RBS

R BS

LO

COM
RSC

N

Figure 30. Current Path of Bootstrap Circuit for
the Supply Voltage (VBS) when Low−Side IGBT
Turns On

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23

AND90041
V PN
0V

V DD
0V

V BS
0V

Section of charge pumping for V BS
: Switching or Full Turn on
ON

V IN(L)
0V
Start PWM
V IN(H)OFF

0V

Figure 31. Timing Chart of Initial Bootstrap Charging

VDC
VDD

Bootstrap capacitor charging ( W phase)
IN(WL)
Bootstrap capacitor charging ( V phase)
IN(VL)
Bootstrap capacitor charging ( U phase)
IN(UL)
Bootstrap capacitor charging period

System operating periode

Figure 32. Recommended Initial Bootstrap
Capacitors Charging Sequence

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24

AND90041

IN (WL, VL, UL) [5 V/div.]

V FO is activated by UVCCD

VFO [5 V/div.]
VDD [5 V/div.]

C BS = 33 m F

C BS = 100 m F

VB−VS [5 V/div.]
All low side turns on

All low side turns on
at a same time

at a same time

Time [2 ms/div.]

V FO is activated by UVCCDC BS = 100 m F

C BS = 100 m F

All low side turns on

Only one low side turns on

at a same time

V FO is activated by UVCCDC BS = 100 m F

C BS = 100 m F

All low side turns on withAll low side turns on withf SW = 5 kHz, Duty = 50%

f SW = 5 kHz, Duty = 25%

Figure 33. Initial Charging According to Bootstrap Capacitance and Charging Method(Ref. Condition: VDD = 15 V/300 mA, VDD Capacitor = 220 mF, Bootstrap Capacitor = 100 mF, RBS = 20 W)• Leakage current in the bootstrap diode• CBS capacitor leakage current (ignored

Selection of Bootstrap Capacitor Considering Operating
The bootstrap capacitance can be calculated by
C BS +

I leakfornon−electrolytic capacitors)• Bootstrap diode reverse recovery charge
Practically, 12.0 mA of ILeak is recommended for the1200 V ASPM34 family. By considering dispersion andreliability, the capacitance is generally selected to be
2~3 times the calculated one. The CBS is only charged when
the high−side IGBT is off and the VS(x) voltage is pulled
down to ground.
The on−time of the low−side IGBT must be sufficient tofor the charge drawn from the CBS capacitor to be fully
replenished. This creates an inherent minimum on−time of
the low−side IGBT (or off−time of the high−side IGBT).

Dt

DV BS

(eq. 9)Where:
ąDt: maximum on pulse width of high−side IGBT;ąDVBS: the allowable discharge voltage of the CBS(voltage ripple)
ILeak: maximum discharge current of the CBS.
Mainly via the following mechanisms:• Gate charge for turning the high−side IGBT on• Quiescent current to the high−side circuit in HVIC
• Level−shift charge required by level−shifters in HVIC

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AND90041
Calculation Example of Bootstrap Capacitance A

should be selected based on the operating conditions.
Bootstrap voltage ripple is influenced by bootstrap resistor,
load condition, output frequency, and switching frequency.
Check the bootstrap voltage under the maximum loadcondition in the system. Figure 35 shows example ofVB(x)−VS(x) ripple voltage during operation.

Conditions: DVBS = 0.1 [V], ILeak = 4.5 [mA]110

Minimum Value
Recommend Value
Commercial Capacitance

100 [mF]

100
90

Bootstrap Capacitance, C BS [mF]80

CBS_min = (ILEAK x Dt) / DVBS

70

Continuous Sinusoidal Current Control

60
50

47 [mF]40
33 [mF]30
22 [mF]20
10 [mF]

10
0

0

2

4

6

8

10

12

6.8 [mF]

14

16

18

20

Switching Frequency, FSW [kHz]Figure 34. Capacitance of Bootstrap Capacitor on
Variation of Switching Frequency

Based on switching frequency and recommended DVBS

Figure 35. Recommendation of Bootstrap Ripple
Voltage during Operation• ILeak: circuit current = 12.0 mA (Refer to the Table 20)• DVBS: discharged voltage = 0.1 V (recommended value)• Dt: maximum on pulse width of high−side IGBT = 0.2 ms

Built−in Bootstrap Diode

When the high−side IGBT or FRD conducts, the bootstrap
diode (DBS) supports the entire bus voltage. A withstandvoltage of more than 1200 V is recommended for thebootstrap diode. It is important that this diode should be fast
recovery (recovery time < 100 ns) to minimize the amountof charge fed back from the bootstrap capacitor into the VDD
supply. Normally, bootstrap circuit consists of bootstrap
diode (DBS), bootstrap resistor (RBS), and bootstrap
capacitor (CBS). I−V characteristics of 1200 V ASPM34
bootstrap diode are shown in Figure 36 and Figure 37. The
bootstrap resistor (RBS) slows down the dVBS/dt and limits
initial charging current (Icharge) of bootstrap capacitor. To
prevent large inrush current at initial bootstrap capacitor
charging, an additional series resistor should be used for
current limitation. Large inrush current can result inover−current protection and stress of bootstrap diode.
Guaranteed pulse current of bootstrap diode is limited by
2 A; therefore, minimum 10 W series resistor should be used
for the current limitation. Generally, tens of W is
recommended as RBS. For the selection of RBS, pulse power
rating should be considered for initial charging of bootstrap
capacitor. To use a large bootstrap capacitor, high pulse
power rating is required for the bootstrap resistor. An
example of resistor pulse power rating is shown in Figure 38.

(depends on application)

C BS_min +I leak

Dt

DV BS

+

4.5 mA

0.2 ms

0.1 V

+ 19

10 *6
(eq. 10)→ More than 2 times → 18 mF (22 mF STD value)
Table 20. OPERATING VBS SUPPLY CURRENT
SymbolConditions

Device

Max

Unit

IPBS

VDD = VBS = 15 V,
fPWM = 20 kHz,
Duty = 50%,
Applied to one
PWM Signal Input
for High−SideNFVA23512NP2T

12.0

mA

39. The capacitance value can be changed according to theswitching frequency, the capacitor selected, and therecommended VBS voltage of 13.0~18.5 V (from datasheet). The
above result is just a calculation example. This value can bechanged according to the actual control method and lifetime of
the component.

Calculation Example of Bootstrap Capacitance B
Based on operating conditions, UVBS function, andallowable recommended VB(x)−VS(x).
To avoid unexpected under−voltage protection and tokeep VBS within recommended value, bootstrap capacitancewww.onsemi.com
26

AND90041
I−V characteristics of integrated bootstrap diodewith series resistor

1.0

RBS = 20 W, TJ =25°C

0.9
0.8
0.7

0.07

0.06

Main Operating Area of
Bootstrap Circuit

0.05

0.5

0.04

0.4

IF [A]

If [A]

0.6

0.3

0.02

0.01

0.2

Zoom in

0.1
0.0

0.03

0.00
0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

VF [V]

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

Vf [V]

Figure 38. Example of Pulse Power Curve ofResistor (from KAMAYA OHM)

Figure 36. I−V Characteristics of Integrated
Bootstrap Diode Series with Series Resistor

Circuit of NTC Thermistor (Temperature Monitoring ofModule)

The characteristics of 1200 V ASPM34 bootstrap diodeare:• Fast recovery diode: 1200 V/1 A• trr: 80 ns (typical)

1200 V ASPM34 series include a Negative Temperature
Coefficient (NTC) thermistor for temperature sensing inside
the module. This thermistor is located in the DBC substratewith the power chip (IGBT/FRD) and accurately reports thetemperature of the power chip (see Figure 39 and
Figure 40.). Normally, circuit designers use two kinds ofcircuit for temperature protection (monitoring) by NTC
thermistor. One is circuit by Analog−Digital Converter(ADC). The other is circuit by comparator. Figure 42 andFigure 43 show examples of both circuits for NTC
thermistor.

Table 21. SPECIFICATION FOR BOOTSTRAP DIODE
SymbolParameter

Conditions

Typ

Unit

VF

Forward−Drop
Voltage

IF = 1A,
TC = 25°C

2.2

V

trr

Reverse−Recovery
Time

IF = 1 A,
TC = 25°C,
dIF/dt = 50 A/ms

80

ns

3.0
2.5

IF [A]

2.0
1.5

I−V characteristics of integrated bootstrap diodewithout series resistor
TJ = −40°C
TJ = 25°C
TJ = 100°C
TJ = 125°C
TJ = 150°C

1.0

80.00 mm0.5
33.00 mm

LVIC

0.0
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
VF [V]NTC

HVICx3Figure 37. I−V Characteristics of Integrated
Bootstrap Diode Series without Series Resistor

BSDx3

IGBTx6FWDx6

Figure 39. 1200 V ASPM34
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27

AND90041

R3

CFOD
VFO
IN(WL)
IN(VL)
IN(UL)
COM(L)VDD(L)CSC

RSC

1200 V ASPM34

MCU

Figure 40. Location of NTC Thermistor in 1200 V
ASPM34

TYP

450

MAX

5
4

Output Voltage of R TH [V]Resistance [W]

500

R2

C1

R TH

Figure 43. OT Protection Circuit by Comparator

600
MIN

NTC

I/O Port

C2

550

V TH

R1

R TH

NTC Thermistor

VBD(U)VDD(UH)
COM(H)
IN(UH)

VB(U)

VS(U)

IN(VH)VBD(V)VDD(VH)

VB(V)

VS(U)

IN(WH)VBD(W)VDD(WH)

VS(W)
VB(W)

NFVA2xxxxxxxx
XXX XXXXX

V DD

RTH
VTH

NV

NU

NW

U

V

P

W

V DD

400

V OUT(min)V OUT(typ)V OUT(max)VDD = 5.0 V

3

350
300
250

VDD = 3.3 V

2

200
150

1

100
50
0
−20 −10 0020

10 20 30 40 50 60 70 80 90 100 110 120
Temperature TTH [°C]

V DD

NTC

R TH

ADC Port

1200 V ASPM34

MCU

40

50 60 70 80 90 100 110 120
Temperature TThermistor [°C]

Figure 44. V−T Curve of Figure 42

Figure 41. R−T Curve of NTC Thermistor

V TH

V−T Curve at VDD = 5.0, 3.3 V, RTH = 6.8 kW
30

R TH

Figure 42. OT Protection Circuit by MCU

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28

AND90041
Table 22. R−T TABLE OF NTC THERMISTORTNTC (5C)

Rmin (kW)

Rcent (kW)Rmax (kW)TNTC (5C)

Rmin (kW)

Rcent (kW)Rmax (kW)0153.8063

158.2144

162.732761

10.459410.800711.15201

146.0956

150.1651

154.3326

62

10.0746

10.4091

10.75362

138.8168142.5725

146.415263

9.705810.0336

10.37143

131.9431

135.4081

138.9502

64

9.3522

9.673410.00464

125.4497

128.6453

131.9091

65

9.01339.32799.6525

5

119.3135

122.2594

125.2655

66

8.68828.99639.3145

6

113.5129116.2273

118.9947

67

8.37648.67828.98997108.0276

110.5275

113.0739

68

8.07738.37278.67828

102.8388

105.1398

107.4814

69

7.79028.07958.3787997.9288

100.0454

102.1974

70

7.51477.79798.09101093.281295.2267

97.203171

7.2496

7.52687.813811

88.880390.6673

92.481072

6.99507.2663

7.54741284.711986.351988.014873

6.75057.01607.29131380.7624

82.2661

83.789474

6.51576.77557.04501477.019078.3963

79.790375

6.2901

6.54436.80821573.4700

74.7302

76.004376

6.07396.3227

6.58101670.104271.2558

72.418977

5.8662

6.10966.36241766.911267.962069.022478

5.66655.9046

6.152118

63.881264.8386

65.803979

5.47455.70755.94981961.0050

61.8759

62.753080

5.28995.51785.754920

58.273959.0647

59.860181

5.11295.33585.56802155.6798

56.396157.1160

82

4.94265.16075.387922

53.215253.862854.512783

4.77884.99215.21452350.8732

51.4569

52.042284

4.62114.82995.047524

48.6469

49.171549.696985

4.46944.67364.886625

46.5300

47.0000

47.4700

86

4.32284.52264.73102644.456744.9360

45.415987

4.18174.37714.581127

42.4868

42.973743.461888

4.04594.23694.436628

40.6147

41.1075

41.602189

3.91504.10194.297329

38.8351

39.332339.831990

3.78903.9717

4.162930

37.142837.643138.146391

3.66753.84634.033431

35.532936.0351

36.5408923.55053.72533.908432

34.001134.504135.011193

3.43773.6087

3.787933

32.543333.0462

33.553494

3.32903.49633.671634

31.1555

31.6573

32.164095

3.2242

3.38783.559335

29.8340

30.333930.839296

3.12353.28363.451536

28.5760

29.0734

29.576497

3.0264

3.18303.347337

27.3776

27.871728.372098

2.93283.08603.246838

26.2356

26.7260

27.222899

2.84252.9923

3.149739

25.1472

25.6332

26.1261100

2.75532.90193.055940

24.1094

24.5907

25.0792101

2.67122.81462.965441

23.1198

23.5960

24.0796102

2.59012.73032.8779www.onsemi.com
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AND90041
Table 22. R−T TABLE OF NTC THERMISTOR (continued)
TNTC (5C)

Rmin (kW)

Rcent (kW)Rmax (kW)TNTC (5C)

Rmin (kW)

Rcent (kW)Rmax (kW)42

22.1759

22.6466

23.1249103

2.51172.64892.793343

21.2753

21.7401

22.2129104

2.43602.57032.711744

20.4158

20.8746

21.3416105

2.36302.49432.632745

19.5953

20.0478

20.5088106

2.29212.42062.556046

18.8120

19.2580

19.7126107

2.22362.34932.481947

18.0638

18.5032

18.9514108

2.15752.28052.410248

17.3492

17.7818

18.2234

109

2.0936

2.21392.340949

16.6663

17.092117.5269110

2.03192.14962.273950

16.0137

16.4325

16.8605111

1.97252.08772.209451

15.389915.8016

16.2227112

1.91512.02782.147052

14.7934

15.198115.6122113

1.8596

1.96992.086653

14.2230

14.6205

15.0277114

1.80601.91392.028254

13.6773

14.0677

14.4678115

1.7541

1.85981.971655

13.1552

13.5385

13.9316116

1.7042

1.80761.917156

12.6556

13.0318

13.4178117

1.65591.7572

1.864457

12.1774

12.5465

12.9255118

1.6092

1.70831.813458

11.7195

12.0815

12.4536

119

1.564

1.6611

1.763959

11.2810

11.6361

12.0011120

1.5203

1.6153

1.716160

10.8610

11.2091

11.5673

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AND90041
PRINT CIRCUIT BOARD (PCB) DESIGN
General Application Circuit Example

Figure 45 shows a general application circuitry ofinterface schematic with control signals connected directly
15V line(33) VB(W)

R1 20R, 1/4W

R2 100R,
1/8W

Ga ti ng WH

C1
47uF
35V

C2
104

D1 1N
474 9A(30) IN(WH)(34) VS(W)C3102(28) VB(V)R3 20R, 1/4W

R4 100R,
1/8W

Ga ti ng WH

C4
47uF
35V

C5
104

D2 1N
474 9A(25) IN(VH)(29) VS(V)C6102(23) VB(U)R5 20R, 1/4W

R6 100R,
1/8W

Ga ti ng WH

C19
100 uF
16V

C20
104

C7
47uF
35V

C8
104

D3 1N
474 9A

R12 1.0K
1/8W(16) CFOD

R11 100R,
1/8W(15) VFO

Fault
C13
102

C14
102

(19) IN(UH)(17) CSC
C16
222

C15
202

R10 5.1K
1/8W(20) COM(H)(24) VS(U)C9102

5V lineR7(14) IN(WL)

Ga ti ng WL

R8(13) IN(VL)

Ga ti ng VL

R9(12) IN(UL)

Ga ti ng UL

R7~9: 100 R, 1/8W
C10~12: 102

C10
~
C12

(11) COM(L)(10) VDD(L)C17
220 uF
35V

OUT

COM

IN

VS

W (2)

VB

VDD

OUT

COM
IN

VS

V (3)

Motor

C21
104

VDC

VB

(22) VBD(U)(21) VDD(UH)

C24
104

VDD

(27) VBD(V)(26) VDD(VH)
C23
104

P (1)

VB

(32) VBD(W)(31) VDD(WH)

C22
104

to a MCU. Figure 45 shows guidance of PCB layout for the1200 V ASPM34 series.

C18
104

VDD

OUT

COM
IN

VS

U (4)

OUT(UL)C(SC)NW (5)C(FOD)VFO
OUT(VL)

IN(WL)

NV (6)
IN(VL)
IN(UL)COM

OUT(WL)NU (7)

5V lineVTH (9)VDD

D4
1N474 9A

(18) RSC

R13 100R

RTH (8)

Temp
Moni tori ng

RTH
RSC

Figure 45. General Application Circuitry for the 1200 V ASPM34 Series

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31

C26
102

www.onsemi.com

32

Isolation distance
between highvoltage .
(Recommend
insert PCB cutting )In the short −circuit
protection circuit ,please select the
RC time constantin the range 1.5~
2usec .

To MCU andPower Source

Capacitor and Zener diodeshould be placed closely toterminals

GND

15V

5V

NTC

Fau lt

WL

VL

UL

100

100

100

24V
1.0W

Figure 46. Print Circuit Board (PCB) Layout Guidance for the 1200 V ASPM34
47uF
35V

20R

47uF
35V

20R

47uF
35V

20R

RSC

82R

Th

CSC

202

VS(W)

VB(W)

VDD(WH)
VBD(W)

IN(WH)

VS(U)

VB(V)

VDD(VH)VBD(V)

IN(VH)

VS(U)

VB(U)

IN(UH)
COM(H)VDD(UH)VBD(U)

NV
NW

VTH

P

W

V

U

NU

RTH

VDD
COM(L)
IN(UL)
IN(VL)
IN(WL)
VFO
CFOD
682

Main
Electrolytic
Capacitor

The main electrolytic capacitor
should be placed to snubber
capacitor as close as possible

Power Source Copper

Snubber
Capacitor

Connect toMoter

Place sunbber capacitor
between P and N andclosely to terminals

Power GND Copper

1200V ASPM 34 Design for PCB Layout (Direct coupling )

472

100

VH
WH

100

UH

24V
1.0W

a

24V
1.0W

a

100

24V
1.0W

a

The VIN RC lters h ou l d b e p l ac ed
to ASPM34 as
c l o s e as po s s i b l e.

Th e c apac i to r an d Zen er b etw een It i s Rec o m m en d t o c o nn ec t c on t r o l G ND A n d Pow er G ND at o n ly Wi r in g p at t er n in d u c t an ce s ho u l d
VD D an d CO M s ho u ld be pl ac ed
a p o in t . (Don ’ t u sed co p p er p at t er n an d d on ’ t m ak e a c l o s e lo o p i n b e m i n im i zed (Rec o m m en d l es sthan 10nH)
to ASPM34 as c l os e as p os s i bl e. GND p att er n ) A nd t h is w ir in g s h ou l d b e as s h o r t as p os s i bl e

AND90041

PCB Layout GuidanceAND90041
PACKING INFORMATION

Figure 47. Packing Informationwww.onsemi.com
33

AND90041
RELATED RESOURCES
FAM65V05DF1 Product Folder
NFVA33065L32, NFVA34065L32, NFVA35065L32 Product Folder
AN−9086 − 600 V SPM [3 Series Mounting Guidance

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