Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT3010-PQB
DC-2Gbps LVDS/CMOS/LVDS Converter and Signal Splitter

True LVDS Transmitter output interface

Flexible selection of enabling and operational modes of the channels

High-impedance states of disabled CMOS outputs

Single +3.3V power supplyIndustrial temperature rangePower consumption: 115mW with all 4 channels enabledStandard MLF/QFN 40-pin packagevccd1p

crlr1

d1n

qm1

d2pqm2d2nvee

crlr2

vcc

ASNT3010

q1p

crlt1

q1n

dm1

q2p

dm2

q2ncnc

crlt2

1vee

vcm

vcc

rfp

vee

rfb2_2

rfbL

vcc

vee

nc

nc

Rev.6.1.2

veed

vcc

Programmable LVDS/CML/ECL Receiver input interface

rfb1_1

rfb2_1

Optional DS (Data/Strobe) encoding/decoding for compatibility with Space Wire Standard

oncml

oneclOptional signal splitter function with selectable inversion

veclvee

2-channel LVDS-to-CMOS converter (Receiver) and 2-channel CMOS-to-LVDS converter(Transmitter)ncFebruary 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
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DESCRIPTION

d1p
d1n
oncml
vecl
onecl
d2p
d2n
q1p
q1n

q2p
q2n

Mux
2:1

UIB

Mux
2:1

UIB

LVDS

LVDS

Mux
2:1

CML to
CMOS

qm1

RCB

crlr1
crlr2

CML to
CMOS

qm2

CMOS
to CML

vcm

TCB

crlt1
crlt2

CMOS
to CML

Mux
2:1
Fig. 1. Functional Block Diagram

ASNT3010-PQB is a bi-directional 4-channel digital interface converter. The part shown in Fig. 1
includes two individual receiver channels with programmable LVDS/CML/ECL differential inputs
d1p/d1n, d2p/d2n, and CMOS outputs qm1, qm2; as well as two individual transmitter channels withCMOS inputs dm1, dm2 and LVDS differential outputs q1p/q1n, q2p/q2n.
All channels can be independently enabled or disabled by control signals crlr1, crlr2, crlt1, crlt2. When areceiver channel is disabled, the corresponding CMOS output drivers are set to a high impedance (high-Z)
state. The individual receiver or transmitter channels can be combined into a corresponding Space Wire
receiver or transmitter with an optional data/strobe (DS) encoding or decoding respectively. The
assignment of the data and strobe, or data and clock signals to the individual channels is user-selectable.
Dual transmitter and/or receiver channels can be used for splitting one of the input signals into two exact
copies at the two corresponding outputs. The signal at the second output can be inverted using the second
input as a selector (a differential DC signal must be applied to the LVDS input). Detailed instructions forusing this operational mode are available on request.
The converter operates from a single +3.3V power supply. The device is characterized for operation from−25°C to 125°C of junction temperature.
Rev.6.1.2

2February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Universal IB
The proprietary Universal Input Buffer (UIB) is designed to support one of three interfaces: LVDS, CML,or ECL. The type of interface is defined by two CMOS control signals oncml and onecl as shown in
Table 1. In the ECL mode, it is required that the pin vecl is terminated to the specified voltage.
Table 1. LS Input Interface Selection

oncml
onecl
Interface type Internal termination vecl, Vvee (default) vee (default)
LVDS
100Ohm differential not used
ECL
50Ohm SE to vecl
vcc-2.0
veevccCML
50Ohm SE to vcc
not usedvcc
vee
Not allowedvcc
vcc
In the LVDS mode, the buffer exceeds the requirements of standards IEEE Std. 1596.3-1996 andANSI/TIA/EIA-644-1995. UIB is designed to accept differential signals with amplitudes above 60mV
peak-to-peak, DC common mode voltage variation between the negative (vee) and positive (vcc) supply
rails, and AC common mode noise with a frequency up to 5MHz and voltage levels ranging from 0 to
2.4V. It can also receive single-ended signals with swings above 60mVp-p and threshold voltages between
vee and vcc.

CML-to-CMOS Converter
The CML-to-CMOS converter represents the output buffer of the receiver. It includes a signal converter
based on a current mirror architecture and an output CMOS driver. The block operates at a data rate up to2Gbps.

CMOS-to-CML Converter
The input CMOS-to-CML converter represents the input buffer of the transmitter. It is designed as astandard CML buffer with additional resistive dividers required for handling rail-to-rail CMOS signals.

LVDS Output Buffer
The proprietary LVDS output buffer utilizes NPN HBTs that are available in standard BiCMOS
technologies. It accepts internal CML signals and converts them into output LVDS signals. The bufferutilizes a special architecture that ensures operation at data rates up to 2Gbps with a low power
consumption level of 19mW. The buffer satisfies all the requirements of the IEEE Std. 1596.3-1996 andANSI/TIA/EIA-644-1995.

Internal Data Processing Circuitry
The internal parts of all 4 channels include an XOR and multiplexer 2:1 CML cells. When activated, theXOR performs the DS encoding or decoding required by the Space Wire protocol, while the multiplexer
operates as a selector of either the channel’s input signal or the XOR-processed signals. Thecorresponding control signals are generated by the receiver or transmitter control blocks (RCB or TCB)
from the 3-state external control signals.
Each channel can function as an independent converter, as well as a data/strobe or clock/strobe Space
Wire encoder/decoder in accordance with Table 2 or Table 3. In the second mode, the device can also
Rev.6.1.2

3February 2020

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2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
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perform the 1-to-2 data splitting operation. The notations Out1, Out2, In1, and In2 in the tables represent
the logic states of the corresponding outputs and inputs, either differential or single-ended.
Table 2. Receiver Operational Modes
Modecrlr1

crlr2

Channel 1 out (qm1)
High-Z

Channel 2 out (qm2)
High-Z2 channelsveevee
N/C (Default)
High-Z
Out2=In2
2 channels
veeHigh-Z
Out2=In2
2 channels
veevcc
Out1=In1
High-Z2 channels N/C (Default)vee
Out1=In1
Out2=In2
2 channels N/C (Default) N/C (Default)
Out1=In1
Out2=XOR(In1, In2), orSW or N/C (Default)
vcc
Out2=(+/-)In1 if In2=”0”/”1”
splitter
Out1=In1High-Z
2 channelsvccvee
N/C (Default) Out1=XOR(In1, In2), or
Out2=In2
SW orvcc
Out1=(+/-)In2
if
In1=”0”/”1”
splitter
Out1=In1
Out2=In2
2 channels
vcc
vcc
Table 3. Transmitter Operational Modes
Modecrlt1

crlt2

Channel 1 outs (q1p/q1n)
Equal undefined levels

Channel 2 outs (q2p/q2n)
Equal undefined levels

2 channelsveevee
N/C (Default)
Equal undefined levels
Out2=In2
2 channels
veeEqual undefined levels
Out2=In22 channels
veevccOut1=In1
Equal undefined levels
2 channels N/C (Default)vee
Out1=In1
Out2=In2
2 channels N/C (Default) N/C (Default)
Out1=In1
Out2=XOR(In1, In2), or
SW or N/C (Default)
vcc
Out2=(+/-)In1 if In2=”0”/”1”
splitter
Out1=In1
Equal undefined levels
2 channelsvccvee
N/C (Default) Out1=XOR(In1, In2), or
Out2=In2
SW orvcc
Out1=(+/-)In2 if In1=”0”/”1”
splitter
Out1=In1
Out2=In2
2 channels
vcc
vcc

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 4 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vee).

Rev.6.1.2

4February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.comTable 4. Absolute Maximum Ratings

Parameter
Supply Voltage (vcc)
Power Consumption
CMOS Input Voltage Swing
LVDS Input Voltage Swing (Diff.)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max
3.6130vcc-vee1.0+90+10098
98

Units
VmW
V
VºC
ºC%%

TERMINAL FUNCTIONS
Name

NumberTypeDESCRIPTION

vcc
vee
veed
vecl
nc
rfbL
rfb2_2rfb2_1
rfb1_1
rfp
crlt2
crlt1
crlr1
oncml
onecl
crlr2
vcm
dm2
dm1
qm2
qm1
d1p
d1nd2pd2nq1pq1nq2pq2n3,8,16,22,25
2,6,10,17,29
21
28
1,11,30,404524
237121520262735
91314181931
32
33
3436
37
38
39

PSPSPSPS
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
DC voltage
Input
Input
OutputOutput
Input
Input
Input
Input
OutputOutputOutputOutputPositive power supply
Negative power supply (analog ground)
Negative power supply (digital ground)
ECL input termination voltage
Floating package pins
Internal reference voltages. Used only in test
operational modes. For normal operation must beleft not connected.

Rev.6.1.2

Transmitter channel 2 activation control signal
Transmitter channel 1 activation control signal
Receiver channel 1 activation control signal
Activation of the input CML termination mode
Activation of the input ECL termination mode
Receiver channel 2 activation control signal
CMOS input threshold voltage, default=(vcc+vee)/2Transmitter channel 2 SE CMOS input
Transmitter channel 1 SE CMOS input
Receiver channel 2 SE CMOS output
Receiver channel 1 SE CMOS output
Receiver channel 1 LVDS direct input
Receiver channel 1 LVDS inverted input
Receiver channel 2 LVDS direct input
Receiver channel 2 LVDS inverted input
Transmitter channel 1 LVDS direct output
Transmitter channel 1 LVDS inverted output
Transmitter channel 2 LVDS direct output
Transmitter channel 2 LVDS inverted output

5February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
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ELECTRICAL CHARACTERISTICSPARAMETERMIN
TYP MAX UNIT
COMMENTS
General Parameters
3.14
3.3
3.47
V
±5%
vcc
0.0
V
LVDS groundvee
0.0
VCMOS groundveed
vcc-2.0V
ECL input termination
vecl
Ivcc35mA
All channels enabledPower consumption
7.0mW
1 Receiver channel, DC20.0mW
1 Transmitter channel
115.0mW
All channels enabled
Junction temperature
-2550
125°C
LVDS Inputs (d1p/d1n, d2p/d2n)
Data Rate
0.0
2.0Gbps
DC common mode voltage
VDC voltage
veevccAC common mode voltage
vee
2.4
V
AC signal <5MHz
Sensitivity
60mV
CMOS Inputs (dm1, dm2)
Data Rate
0.0
1.0Gbps
Logic “1” levelvcc -0.4
V
Logic “0” level
0.4
V
LVDS Outputs (q1p/q1n, q2p/q2n)
Voltage Swing
320mVEach SE output
CM voltage
1.2
1.25
V
Impedance
77122
Ohm
DC test45115
Ohm
AC test (0-2Gbps)
Total current
5.2
5.7mA
From vcc
Output current
1727mA
Shorted to vee
4.5
7.0mA
Shorted together
Rise/Fall Times
TBD
pS
20%-80%CMOS Outputs (qm1, qm2)
Logic “1” levelvcc -0.2
V
Logic “0” level
0.2
V
Rise/Fall Times
TBD
20%-to-80%
Duty Cycle
45%
50%
55%
CMOS Control Inputs (crlr1, crlr2, crlt1, crlt2)
Logic “1” levelvcc -0.4
V
Logic “0” level
0.4
VRev.6.1.2

6February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
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PACKAGE INFORMATIONThe chip die is housed in a standard 40-pin QFN package shown in Fig. 2. It is recommended that thecenter heat slug located on the back side of the package is soldered to the vee plain that is ground for thepositive supply.
The part’s identification label is ASNT3010-PQB. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

ASNT3010
Fig. 2. QFN 40-Pin Package Drawing (All Dimensions in mm)

Rev.6.1.2

7February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
6.1.2
6.0.2
6.0.1

Date02-2020
07-2019
03-2013

5.0
4.009-2009
02-2008

3.0
2.0
1.006-2007
04-2007
01-2007

Rev.6.1.2

Changes
Updated Package Information
Updated Letterhead
Revised title
Revised description
Added pin out diagram
Corrected block diagram
Revised Operational Modes tables
Added absolute maximum ratings
Revised electrical characteristics
Revised package information
Added package mechanical drawing
Added revision history
Updated format
Revised electrical characteristics
Revised electrical characteristics section
Revised packaging information section
Revised electrical characteristics section
Revised terminal functions section
First release

8February 2020