TND6330/D
Rev. 5, July − 2022

Using Physical and Scalable
Simulation Models to EvaluateParameters and Application Results© Semiconductor Components Industries, LLC, 2020

July, 2022 − Rev. 5

1

Publication Order Number:
TND6330/D

Using Physical and
Scalable Simulation
Models to EvaluateParameters andApplication Results
Prepared by:“ON” STATIC REGION CURVES
Drain Current versus Drain−Source Voltage with
Gate−Source Voltage as Parameter(First Example: NTHL040N65S3F)

The on−region characteristic or curve shows how thedrain current changes due to the drain to source voltage withthe gate to source voltage used as a parameter. This curve is
given in all university books describing MOSFETs (seeFigure 1) and also in data sheet (see Figure 2).
The “on” characteristic or curve is made of two regions:• The linear or ohmic region: it corresponds to the region
where the MOSFET behaves as a resistor (called
RDSon).
• The saturation or active region: it corresponds to theregion where the curve is almost flat and the MOSFET
operates like a current source.

Heinrich Kamamen
Field Application Engineer
Didier Balocco
Technical Marketing Engineer

ABSTRACT
Physical and scalable modeling technique is an advanced
SPICE modeling approach based on process and layout
parameters which enables design optimization through a
direct link between SPICE, physical design, and process
technology. Physical and scalable models are available fornearly all discrete power components from the onsemi web
site. The models’ accuracy allows the user to extract device
parameters (like in a data sheet) for a given operating point
when these parameters are not in the data sheet. Thesemodels give a real picture on how the device will perform ina real application. Power device losses are not guessed with
an empirical formula but obtained in a real circuit including
all the parasitics (like layout, passive parasitics,...). Key
information, like junction temperature, can be also
monitored to determine the device mission profile used inreliability calculations.

These curves depend mostly on the voltage applied to thegate.
We can find this on−region curve in “MOSFET Basics”
application note from onsemi [6] in the Figure 1 below.
ActiveOhmic

Cutoff<<<<Figure 1. Typical On−Region Curve froma University Book

INTRODUCTION
Physical and scalable modeling has been described byJames Victory in papers [1], [2], [3] and tutorial [4]. Thesemodels are based on silicon (or silicon carbide or gallium
nitride) equations and the geometry of the device. They are
not obtained by curves fitting. They are behavioral models.
They are linked to technology platform and device are
obtained by scaling. They include packaging parasitics.
Thermal dependence is also calculated step by step during
simulation using the electro−thermal equivalence. This will
be shown in this paper.
The simulators’ (Orcad, SIMetrix and LTspice) setup is
explained in the following reference [5].
This paper will focus on simple simulation schematic
description to extract device parameters like on resistanceand output capacitor values as a function of the operating
point.
The difference between models with and without thermal
dependency will be also explained.
The paper will also describe the results (like junction
temperature, losses,...) obtained on a full boost stage
diagram.

In specification, this curve is shown in a log scale. For
example, for the NTHL040N65S3F, SuperFET3 Fast
recovery 40 mW, the curve is the one in Figure 2.

Figure 2. On−Region Curve from Data Sheetwww.onsemi.com
2

To extract this characteristic on SIMetrix, a 3−pintransistor model was used and two voltage sources wereconnected to the transistor: one between the drain and source
pin, the other between the gate and the source pin as shownin the Figure 3.
VDrainI−V
XY Probe

NTHL040N65S3F_3p

Figure 6. On−Region Simulation List Setup
Q

Simulation was performed for a temperature of 25°C.
On the schematic Figure 3, we added an “X−Y Probe” toplot the drain current versus the drain−to−source voltage.
We obtained the Figure 7.

VDD

VGG

Figure 3. On−Region Simulation Schematic

For the simulation configuration, see Figure 4, we choosea dc sweep analysis mode for the drain to source voltage
source (VDD).

Figure 7. On−Region Curve Simulation Results

Using a list with the same values as the gate−to−source
voltage used for the specification curve and also using alogarithmic scale for X and Y axes, we obtained the curve
shown in Figure 8:

Figure 4. On−Region Simulation Setup

The multi−step analysis was enabled for the voltage
source (VGG) in order to use gate−to−source as a parameterfor the on−region characteristics (see Figure 5).

Figure 5. On−Region Multi−Step Setup
Figure 8. On−Region Curve Simulation Results

A list was created in order to define possiblegate−to−source voltage values (See Figure 6).

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3With the same test conditions, the comparison of
Figures 2 and 8 shows how the simulation results (done with
our MOSFET model) match perfectly with the value
obtained during the lab measurement and extracted from thedatasheet.

The model uses the electro−thermal equivalence where
Voltage represents the Temperature and the Current
represents the Power dissipated. The case temperature is set
to the system temperature using a voltage source. The
voltage−source value is set with the SIMetrix variable“Temp” storing the system temperature. The systemtemperature can be set to 25°C in the option tab insidesimulation setup windows (see Figure 11).

Drain Current versus Drain−Source Voltage with
Gate−Source Voltage as Parameter(Second Example: NTMFS5C604N)

Now, if we use a medium voltage MOSFET model, likethe NTMFS5C604N, and the same simulation schematic as
Figure 3. For the drain−to−source voltage, we use the same
setup. We obtained the following results (see Figure 9) using
a linear scale as found in literature.

Figure 11. System Temperature Setup

We need to add a 1−MΩ resistor on the “junction
temperature” pin to help the solver to converge. On top of theI−V “XY Probe”, we have a second plot using a “XY Probe”
to monitor the junction temperature behavior.
We obtain the curves of Figure 12.

ÊÊÊÊÊÊÊÊÊÊÊÊÊÊ
ÊÊÊÊÊÊÊÊÊÊÊÊÊÊ
ÊÊÊÊÊÊÊÊÊÊÊÊÊÊ
ÊÊÊÊÊÊÊÊÊÊÊÊÊÊ
ÊÊÊÊÊÊÊÊÊÊÊÊÊÊ
ÊÊÊÊÊÊÊÊÊÊÊÊÊÊ
ÊÊÊÊÊÊÊÊÊÊÊÊÊÊ

Tj(Q) / °C

600

Figure 9. On−Curve Simulation Results

In this simulation, the results obtained are far beyond the
MOSFET specifications. So, they are not valid. The model
is only valid within specification limits.
If we use a 5−pin model to monitor the junction
temperature, we have the following simulation schematic(Figure 10).
VDrainVGS=9V

VGS=5V

175°C

25
0 0.5
VDS/V

1

1.5

VGS=4V

2

2.5

3

3.5

4 4.5
500mV/divÊÊÊÊÊÊÊÊÊÊÊÊÊÊ
ÊÊÊÊÊÊÊÊÊÊÊÊÊÊ

300
Y

250

Temp

Tj

Tj

ID / A

X

280A

200
150

100

VDD

Tcase

Thermal runaway

50{Temp}
VGG

300

100

I−V

Q

400

200

XY Probe

NTMFS5C604N_5P

500

0

Solv
1Meg

0 0.5
VDS/V

TCase

1

1.5

2

2.5

3

3.5

4 4.5
500mV/div

Figure 12. On−Curve Simulation Results with 255C
Constant Temperature Package

Even if we maintain the package temperature at 25°C, we
have the junction temperature rising above 175°C

Figure 10. On−Curve Simulation Schematic witha Constant Temperature Package

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4

(maximum junction temperature specified) while thecurrent flowing in the drain pin is above 280 A (maximum
rating current at 25°C).
If we analyze the results in Figure 12, we can note:• For a gate−to−source voltage equal to 4 V, we see athermal runaway in the saturation region. The current
increases faster and faster while the voltage rises up.
The junction temperature rises above 175°C before thedrain current reaches the 280 A specification limit.
• For a gate−to−source voltage equal to 5 V, the device
stays in the ohmic region but the junction temperaturerises to 175°C before it gets to 280−A drain current
limit.
• For a gate−to−source voltage equal to 9 V, the device
stays in the ohmic region but the drain current rises to
280 A limit before it gets to 175°C junction
temperature.

The switch on−resistance should be much smaller than theon−resistance of the device to simulate (or measure).
The switch is made with a 1 mW on−resistance affected by
200°C hysteresis. The switching time is set to 10 ns.
Simulating the previous schematic, we obtained thecurves shown in Figure 15:

Tj(Q) / °C

160

120

100
80
60
40

25
0.5
0
VDS/V
VGS=10V

ID / A12

1.5

Thermal runaway

3500mV/div
2.5

VGS=8V
VGS=7V250

If we stop the current flow when the current reached 300 A
or when the junction temperature reached 175°C, we will
stay within specification limits.
We limit the drain−to−source current source to 300 A. We
use a switch driven by the junction temperature to short thecurrent source when the temperature gets above 175°C. We
implement a very large hysteresis to avoid a new turn on
when the device cools down.
Figure 13 describes the following simulation schematic:
VDrainVGS=4V140

VGS=6V200
VGS=5V

150

100

VGS=4.5V

50

0

VGS=4V

0.5
0
VDS/V

1

1.5

2

3
500mV/div
2.5

Figure 15. On−Curve Simulation Results up to
280 A and 1755C Junction Temperature with 255C
Case Temperature

I−V
XY Probe

Y

When the thermal protection operates, as it is not an
ON/OFF switch, the drain current goes immediately to zerowith a stay horizontal line. These flat lines have been
purposely removed from the graph above (in Figure 15) for
clarity sake.
For a gate−to−source voltage equal to 4 V, a thermal run
away can be seen. The curve in the saturation or active
region rises up again and the junction temperature rises likean exponential curve. This happens when thedrain−to−source voltage reaches around 2 V. The junction
temperature curve slope changes very fast from 40°C to
175°C.

Temp

X

Tj
NTMFS5C604N_5P
Q

Tj
Tcase
SC

VGG

{Temp}
TCase

Solv
1Meg

IDD
1m Pulse(0 280 0 1 1 0 2)

On−curve Comparison between Specification and
3−pin and 5−pin Models Results for NTHL040N65S3F

Figure 13. On−Curve Simulation Setup with Current
and Junction Temperature Shutdown

In the specification, to measure the on−curve, we use
250 ms pulse to limit self−heating and the case at 25°C. See
Figure 2.
Using the 3−pin model in Figure 3 and the setup given in
Figures 4, 5 and 6, we obtain the curve on Figure 8.
The 3−pin model gives almost the same results because in
the 3−pin model the self−heating doesn’t affect the dietemperature. It can be similar to maintain the die in aconstant temperature environment or consider an infinite
heatsink that has a thermal impedance equal to zero.
Now, if we use the 5−pin model and limit the temperaturerise to stay within the specification limits, we can use theHere is the setup (Figure 14) for the switch shorting thecurrent source.

Figure 14. Switch Setup to Short the Current Source

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5schematic in Figure 16 to obtain the on−curve in continuous
operation mode.
VDrainI−V

SC

XY Probe

NTHL040N65S3F_5p

When the thermal protection operates, as it is not an
ON/OFF switch, the drain current goes immediately to zerowith a stay horizontal line. These flat lines have been
purposely removed from the graph above (in Figure 18) for
clarity sake.
We can see the effect of the self−heating and we have theuseful curve in continuous mode operation.
To precisely emulate the datasheet characteristics, a
250 ms−transient pulse of each drain−to−source bias
condition needs to be simulated. The drain−current at theend of the pulse is sampled for each voltage source pulse.
Subsequently the ID vs. VDS plot is constructed. This setup
is not shown here in SIMetrix because it requires using
SIMetrix scripting capability, however, it has been verified
in PSpice.

Tj

Tj

Q
Tcase

VGG

{Temp}
TCase

Solv
1Meg
VDD

1m Pulse(0 20 0 1 1 0 2)

On Resistance Value versus Drain Current
Figure 16. On−Curve Simulation Setup with Voltage
and Junction Temperature Shutdown

This characteristic shows how the on−resistance valuechanges with the drain current and the gate−to−source
voltage. To obtain this characteristic, we connected a current
source between the drain and source pin as shown in the
Figure 19.

To stop the curve when the junction temperature reaches
150°C, we use a switch driven by the junction temperature.
Compare to Figure 13, we use a voltage source and inverse
the operation of the voltage−switch that turn off whentemperature reaches 150°C. The switch setup is given in
Figure 17.

VDrainV(P)/I(Sns)
RDSon

RDSon
Ron−I

I(sns)OUT

XY Probep

NTHL040N65S3F_3p

Q

IDD

VGG

Figure 17. Switch Setup to Open the Voltage Source

Simulating the previous schematic (Figure 16), we
obtained the curves shown in Figure 18.

Figure 19. On Resistance versus Drain Current
Simulation Schematic

Simulation was performed on the NTHL040N65S3F
MOSFET 3−pin model and a 25°C temperature was used forthis simulation. See Figure 11 to setup this systemtemperature.
In this simulation setup, we applied a dc sweep on thedrain current. We enabled the multi−step analysis on thegate−to−source voltage, same as in Figure 3 to simulate
on−region curves.
To calculate the on resistance, we use an arbitrary source
to make the division between drain−to−source voltage by thedrain current. We obtained a voltage directly proportional to
the “on” resistance. See Figure 22 for an arbitrary function
setup example.
To display the resistance value curve, we use X−Y probe.
The X axis is connected to the drain current and the Y axis
is connected to the on resistance arbitrary function.
After simulation, we get the following curve (Figure 20).

Figure 18. On−Curve Simulation Results up to
200 A and 1505C Junction Temperature with 255C
Case Temperature

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6For this simulation, a 10−V gate−to−source voltage wasused as in the datasheet. A 32.5−A current source was set inorder to match the value given in the specification.
A voltage source equal to the simulation temperature(with the SIMetrix variable “Temp”) is used to have the X
axis for the X−Y probe. The X−Y probe Y axis is connected
to arbitrary function output.
Figure 20. On−Resistance Value versus
Drain−Current Simulation Results

On the plot above, we can see there is slight difference
between the resistance curve obtained during the simulation
performed with the NTHL040N65S3F MOSFET model andthe curve shown in the datasheet.
In fact, for a 100−A drain current and a 10−V
gate−to−source voltage, the difference between thesimulation results and the datasheet measurement is almost
1.25 mW. This corresponds to a 3% relative difference. Thisis acceptable.

Figure 22. Arbitrary Function Setup

We will run an operating point calculation (on top of thedc sweep simulation in Figure 23) with an ambient
temperature equal to 25°C. This is defined by checking the
DCOP (dc operating point) simulation and the temperaturein the red box in the Figure 23.

On Resistance Value versus TemperatureWith this curve, we can see how the on−resistance changes
with the temperature. The temperature has an impact on the
charge carrier agitation, and this will affect the transistor
on−resistance value.
In switching applications, during turn−on, the current
starts flowing through the transistor. It has the effect ofincreasing the junction temperature by self−heating. As aresult, the on−resistance value will increase during turn on
due to temperature increase caused by current flowing.
We will use almost the same schematic (see Figure 21) as
the previous simulation (in Figure 19) featuring the arbitrary
function block to calculate the on−resistance value. We add
a parameter to normalize the curve with the 25°C value (seeFigure 22). We plotted the X−Y curve as a function of thetemperature (instead of the drain current in the previous
chapter).

Figure 23. On−Resistance Value versus
Temperature Operating Point Simulation Setup

VDrainV(P)/I(Sns)/RDSon25C
RDSon

RDSon

We placed also a “Bus annotation marker” in theschematic of Figure 21 to show the arbitrary−function result(the on−resistance value) at the operating point.

RDSon−TemperatureI(sns)XY Probe

OUTp33.5196m

Q
32.5
IDD

NTHL040N65S3F_3p
10
VGG

VTemp
{Temp}

Figure 24. On−Resistance Value versus
Temperature dc Sweep Simulation Setup

Figure 21. On−Resistance versus Temperature
Simulation Schematic

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7

We setup the simulation to run a dc sweep on thetemperature as shown in the Figure 24 above.
1. We set the arbitrary function block parameter
RDSon25C equal to 1 as shown in Figure 22.
2. We run the simulation a first time.
3. We get the 25°C on resistance with the bus
annotation marker (33.5196m as shown in
Figure 21).
4. We also get the on−resistance value as a functionof the temperature. (See Figure 25)
5. We set the arbitrary function parameter
RDSon25C equal to this bus annotation marker
result.
6. We run the simulation a second time.
7. The bus annotation marker should have a value
very close or equal to 1 if the arbitrary function
block parameter was properly/accurately set.
8. We get the normalized on resistance versus
temperature as shown in Figure 26.

Figure 26. Normalized On−Resistance Value versus
Temperature Simulation Results
On Resistance Value versus Time (Dynamic Analysis)

Setting the parameter (RDSon25C equal to 1), then,changing the operating point (VGG and IDD), the on
resistance versus temperature can be obtained for any
operating point depending on the desired application asshown if Figure 25.

The 5−pin models are very useful when you want to know
the junction temperature behavior depending on the mission
profile.
In this exercise, we assumed to have a low frequency
pulsed current from 1 A to 40 A going through a switch. We
made the hypothesis: the switch case is attached to a constanttemperature heatsink (without any thermal interface). Thistemperature is chosen to be the system temperature andmodeled by a voltage source with a value equal to theSIMetrix variable “Temp” representing the systemtemperature. Using Figure 11, we set this systemtemperature to 25°C.
We want to analyze how the on−resistance value changes.
So, we will reuse the same arbitrary function to calculate theon resistance on the fly. See Figure 22 for thearbitrary−function setup. (Here, we will not use the“RDSon25C” parameter.) We obtain the schematic shown in
Figure 27.
VDrainV(P)/I(Sns)
RDSon
RDS

Figure 25. On−Resistance Value versus
Temperature Simulation Results

I(sns)

OUT

RDS

p

In Figure 25, we can measure 33.5196m for theon−resistance at 25°C. We will use this value for thearbitrary function parameter RDSon25C to re−run thesimulation and obtain the normalized on−resistance curve
shown in Figure 26.
The plot Figure 26 is similar to the one in the specification.

Tj
ID

Tj

Tj

NTHL040N65S3F_5p
Q

Tcase
Solv

10

{Temp}

VGG

TCase

1Meg

IDD

Pulse(1 40 50m 1m 1m 24m 50m)

Figure 27. On−Resistance Analysis versus Time
Simulation Schematic

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8

On simulation schematic Figure 29, we will use an X−Yprobe to plot the transfer characteristic and the temperature
will be set via the “Multi−Step” simulation list.

We will plot the drain current (using a current probe )for reference. We will monitor the on resistance and thejunction temperature, so we add two more probes (voltage
probe ) as shown in Figure 27.

VDrainID−VGSXY Probe

NTHL040N65S3F_3p

Q

20
VDD

VGG

Figure 29. Transfer Characteristic Simulation Setup

We defined a dc sweep for the gate−to−source voltage anda multi−step analysis on the temperature by creating a list of
temperature values to be used for this simulation.

Figure 28. Dynamic Analysis Results for the On
Resistance and the Junction Temperature versus
Time

In Figure 28, we can notice the sudden change in the on
resistance when the drain current moves rapidly from 1 A to
40 A and backward. This phenomenon was predicted by the
curve obtain in Figure 20 (on resistance versus draincurrent). We can also see the effect of the self−heating or
cooling of the device itself during the plateau phase of thecurrent (1 A and/or 40 A).
The system is stable after a 200−ms transient. The
maximum junction temperature is 36°C and the minimum is
30°C. The junction temperature oscillates between thesetwo values. We could have also calculated the averagetemperature over a cycle using an “Average PerCycle
Probe”, for example.

Figure 30. Transfer Characteristic Simulation Results

Figure 30 above shows a good agreement between thesimulation result obtained with our transistor model and thedatasheet parameters (or characterization curves).
OUTPUT CAPACITANCE
For switching application, the output capacitor called Cossdefined as Coss = (CDS + CGD @ VGS = 0 V) is an importantparameter as it impacts the transistor switching losses. In
fact, every time the MOSFET turns on, the energy stored in
output capacitance dissipatesin the transistor. The lower the
Coss is the better it is. Coss is a non−linear capacitance andhighly depends on the drain−to−source voltage.
There are 3 to 4 types of output−capacitance values foundin the specification.
The capacitance types are called:• Small signal value,• Effective value,

TRANSFER CHARACTERISTIC VERSUSTEMPERATURE
The transfer characteristic shows how the drain current
changes with the gate−to−source voltage. The
drain−to−source voltage is fixed. From this simulation
setup, the MOSFET transconductance can be extracted. The
simulation was done with a 20−V drain−to−source voltage(similar as the data sheet setup) and for various temperature
values.

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9• Energy related value,• Charge related value.
In this chapter, the way to extract these values bysimulation will be explained.
Small Signal Value (1st Method: Transient Simulation).

To measure the small−signal capacitor, a low−amplitude
sinusoidal voltage is superimposed to a dc drain−to−source
voltage source. The peak−to−peak value of the drain current
is measured for several values of drain−to−source
continuous voltage and is used to compute the capacitancevalues.
The following equation defines the capacitor admittanceas a function of the ratio of the peak−to−peak current andpeak−to−peak voltage:
2p

f

C oss +

Figure 33. Small−Signal Capacitance
Pre−Simulation Setup

We run the transient analysis for 10 ms but storing value
only after 8 ms to display the steady−state operation andavoid the initial transient operation.
We obtain the following current waveforms in Figure 34:(Drain Current) Peak*to*Peak(Drain * to * Source Voltage) Peak*to*Peak(eq. 1)

We will use 20−mV peak−to−peak sinusoidal voltage
source with frequency equal to 1 MHz in series with thedrain−to−source continuous voltage as shown in Figure 31.
We added a current probe
on the drain pin of thetransistor to measure the drain current.
VDrainID
Q
NTHL040N65S3F_3p
VDD
Sin({VDD} {VMeas} {FMeas} 0 0)

Figure 34. Drain Current Waveforms when the dc
Drain−to−Source Voltage Change

Figure 31. Small−Signal Capacitance
Pre−Simulation Schematicin Figure 34, please note the presence of a dc current offset(around 32 mA) corresponding to the drain−to−source
leakage current.
Solving equation (1) to get COSS , we obtain the following
formula:Parameters have been used to define the dc
drain−to−source voltage (VDD), the small−amplitude
sinusoidal voltage (VMeas) and its frequency (FMeas).
The statements below have been added to the SIMetrix“Command Window” (see Figure 32.) Pressing F11 showsor hides this panel.

C oss +

2p

1

f

+

(Drain Current) Peak*to*Peak(Drain * to * Source Voltage) Peak*to*Peak(eq. 2).ParamFMeas=1Meg.Param VMeas=10m.Param VDD=400

We implement this formula in an arbitrary−function probe
to dynamically calculate COSS during simulation and plot its
value, as shown in Figure 35. Since the measurement
frequency has been defined as a parameter in the “Command
Window” with the statement “.Param”, we need to use thefunction “GetDotParamValue(‘Parameter Name’)” toretrieve and use the parameter value. p is also treated as aparameter and obtained the same way.

Figure 32. Parameters Statements inthe “Command Window”

We create a “Multi−Step” transient simulation setup using
the parameter VDD with the following setup in Figure 33:

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10Small Signal Value (2nd Method: AC Simulation).

PeakToPeak(I(sns))/PeakToPeak(V(p))/(2*GetDotParamValue(’Pi’)*GetDotParamValue(’FMeas’))VDrainIn ac simulation, SIMetrix offers the possibility to sweep
other parameters than frequency. Here, we will set thefrequency to 1 MHz and sweep the drain−to−source dc
voltage.
Using eq.(1), the COSS value can be calculated in theac simulation via the following expression:

I(sns)p

Coss

Q
NTHL040N65S3F_3p
VDD
Sin({VDD} {VMeas} {FMeas} 0 0)

C oss +

2p

I Dac
f V DSac(eq. 3)The previous expression will be implemented in a special
arbitrary−function probe to solve the COSS values dependingon drain current and drain−to−source voltage as shown on
schematic Figure 38.

Figure 35. Small−Signal Capacitance Simulation
Schematic with Arbitrary Probe

SIMetrix offers the possibility to plot a signal (here thearbitrary−function probe’s results) as a function of the swept
value (here the parameter VDD representing the continuous
drain−to−source voltage value). This is done selecting the“Performance analysis” mode for the Multi−Step setup (seeFigure 36). The swept value becomes the graph X−axisvariable. The expression results are plotted on the Y−axisvalues.
Here is the setup of the arbitrary probe in Figure 36:

VDrainI(sns)/(2*{Pi}*1Meg)
Coss
I(sns)Q

400 AC 1 0
VDD

NTHL040N65S3F_3p

Figure 38. Small−Signal Capacitance Value
Simulation Schematic

In ac simulation, SPICE linearizes the circuit after
calculating the dc operating point. As the circuit is linear, we
can apply any ac voltage amplitude without any saturation
risk. To simplify the calculation, we can apply 1 V for the ac
voltage amplitude.
The simulation setup can be found Figure 39:

Figure 36. Arbitrary Probe Setup

After running the simulation, we get the graph displayedin Figure 37 using the same scales as the specification curve.

Figure 39. Small−Signal Capacitance Value
Simulation Setup

Figure 37. Small−Signal Capacitor Value versus
Continuous Drain−to−Source Voltage

The “Multi−Step” box should be unchecked. The swept
values are the one for the continuous drain−to−source
voltage: from 100 mV to 650 V, using 25 points per decade.
Additional setup needs to be placed under the “Define”
button (see Figure 39) to set the way the sweep analysis will

These measurements fit the datasheet results. As an
example, for a drain−to−source equal to 400 V, we measured
a COSS value of 142 pF in Figure 37 and this matches with
140 pF given in the datasheet.

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11be performed. In Figure 40, we define the device to sweep(VDD, the voltage source) and the ac frequency to be
1 MHz. The ac amplitude is set to 1 V.

Solving this equation to determine the output−capacitor
values, we obtain the following formula:Time

C oss +
RD

lnǒ

V

DD

Ǔ

V DD
*V (Time)DS(eq. 5)

As previously done, this formula is used in an arbitrary
function (or voltage source) to get the COSS value directly on
the schematic (see Figure 42). We use an X−Y Probe to plot
the COSS value versus drain−to−source voltage.
Figure 40. Small−Signal Capacitance Value
Simulation Sweep mode Additional Setup

VDrainY

The obtained simulation curve can be seen in Figure 41.

Coss_EffectivepCoss−VDS

X

OUT

IC
0

Coss
time/(RD*ln(BVDSS/(BVDSS−V(p))))Q
NTHL040N65S3F_3p

RD
{RD}

{BVDSS}
VDD

Figure 42. Effective−Capacitance Value Simulation
Schematic

The values for the resistor (RD) and the voltage source(VDD) are set with parameters in the “Command Windows”(F11). The values are 100 kΩ and 650 V respectively. There
are shown in the Figure 43.

Figure 41. Small−Signal Capacitance Value
Simulation Results.Param RD=100k.Param BVDSS=650

This curve (Figure 41) matches with the specification
curve. In the “Dynamic Characteristics” table, thesmall−signal output capacitor is given for a drain−to−source
voltage equal to 400 V. We measured a COSS value equal
to 142 pF on the simulated curve above and this matcheswith 140 pF given in the specification.
The two methods give the same results.

Figure 43. Parameters Statements in the“Command Window”

We set an initial condition for the drain−to−source voltage
to be equal to 0 V when the simulation begun using the “IC”
pseudo−component, meaning the output capacitor is emptyof charges (see Figure 42).
The obtained simulation curve can be seen in Figure 44.
In the “Dynamic Characteristics” table, the effective
output capacitor is given for a drain−to−source voltage equal
to 400 V. In Figure 44, we measured a COSS value equal
to 1305 pF in the simulated curve and this matches with
1366 pF given in the specification.

Effective Value

The effective−capacitor value is defined in [7] as theequivalent linear capacitor storing the same amount ofcharge/energy with a voltage source equal to the breakdown
voltage value while a 100−kW series resistor charges theoutput capacitor. This value can be used to calculate theswitching time in resonant topologies.
The charging equation for the linear capacitor in thisconfiguration is given by:
V DS(Time) + V DDǒ1 * e *Timeń(RD Coss)Ǔ

(eq. 4)“Time” is the SIMetrix variable representing the current
simulation time.

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12

Coss−VDS

VDrainY
2*SDT(V(p)*I(sns))/V(p)/V(p)Coss_EnergyI(sns)

X

OUT
IC
0

p
Coss

1m
IDD

Q
NTHL040N65S3F_3p

Figure 44. Effective−Capacitance Value Simulation
Results
Figure 45. Energy−related Capacitance Value
Simulation Schematic

Energy−related Value

The energy stored in a capacitor is expressed by thefollowing equation:dW + v(t)

i(t)

d(t)

(eq. 6)

And, the final energy for a constant capacitor can be
express by the following equation:
W + 1 CV 22(eq. 7)

If we integrate eq.(6) and replace in eq.(7), we can extract
the capacitor value.
2
C oss +ŕTime

V DS(t)

I D(t)dt

02

V DS (Time)(eq. 8)We use a current source to charge the output capacitor
instead of a voltage source (in the effective−value setup).
Here also, we use this formula in an arbitrary function to get
the COSS value directly. We invoked the integral function“SDT()” to determine the numerator.
We also placed an initial condition for the drain to source
voltage to be equal to 0 V when the simulation begun using
the “IC” pseudo−component, meaning the output capacitor
is empty of charges.
We obtain the simulation schematic shown in Figure 45.
Figure 46 displays the obtained simulation curve.
In the “Dynamic Characteristics” table, the effective
output capacitor is given for a drain−to−source voltage equal
to 400 V. We measured a COSS value equal to 245 pF on thesimulated curve above and this matches with 247 pF givenin the specification.

Figure 46. Energy−related Capacitance Value
Simulation Results
Charge−related Value

The charge stored in a capacitor is expressed by thefollowing equation:dQ + i(t)d(t)(eq. 9)And, the final charge for a constant capacitor can be
express by the following equation:
Q + CV(eq. 10)If we integrate eq.(9) and replace in eq.(10), we canextract the capacitor value.

ŕC oss +

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13

Time

I D(t)dt

0

V DS(Time)(eq. 11)average breakdown drain−to−source voltage (BVDSS). In
the specification, only the minimum is given.

We use a current source to charge the output capacitor.
Same here, we use this formula in an arbitrary function todetermine the COSS value directly. We use the integral
function “SDT()” to calculate the stored amount of charges.

VDrainXY Probe
XY Probe

Coss−VDS

VDrainY
SDT(I(sns))/V(p)Coss_Charge
I(sns)

X

OUT
IC
0

p

Q

1m
IDD

NTHL040N65S3F_3p
Q
NTHL040N65S3F_3p

Coss

1m
IDD

Figure 49. Breakdown Voltage Simulation
Schematic

To simulate the breakdown voltage versus temperature,
we will use a current source ramping up to 2 mA and plot the“off” characteristic. See Figure 49 schematic. (Thespecified minimum drain−to−source breakdown voltage
value is given for 1 mA.)
The “off” state is obtained by shorting the gate to thesource.
We will use an X−Y Probe to plot the drain−to−source
voltage versus the drain current in “off” state as represented
in Figure 50.

Figure 47. Charge−related Capacitance Value
Simulation Schematic

We also placed an initial condition for the drain to source
voltage to be equal to 0 V when the simulation begun using
the “IC” pseudo−component, meaning the output capacitor
is empty of charges. We obtain the simulation schematicfrom Figure 47.
Figure 48 shows the obtained simulation curve.

Figure 48. Charge−related Capacitance Value
Simulation Results

Figure 50. Breakdown Voltage Simulation Results
versus Temperature

In Figure 50, we can note a leakage current variation withtemperature. We can measure 23 mA, 33 mA and 254 mA for
respectively −55°C, 25°C and 150°C die temperature at adrain−to−source voltage equal to 400 V. We see a big
leakage current increase between 25°C and 150°C.

BREAKDOWN VOLTAGE
The model gives the average values. The model isaccurate within the specification limits. Results outside
specification limits are not warranted by onsemi.
Nevertheless, the model can operate beyond the limits
with relatively good accuracy and can predict values like thewww.onsemi.com
14

PwrDBSW
IN

PwrDiode{CBoost}OUT

I(Sns)*V(P,N)

CB{LBoost} IC=0
{RBoost}I(sns)iLB

RB

BOOST POWER STAGE

p

LB

OUT

n

The drain to source breakdown voltage is equal to 648 V,
708 V and 781 V for respectively −55°C, 25°C and 150°C
die temperature as shown in Figure 50.

Out
DB

FFSB0665A_4p

Tcase

Tj

I(Sns)*V(P,N)
PwrDrainI(sns)

Setup

{Vin}
Vin

In this chapter, we will use these scalable and physicalmodels in a real application. We will study a boost converter
stage with an Easy Drive SuperFET 3 and a 650−V SiC
diode.
We will use the FCH040N65S3 for the boost switch. It isa 40−mΩ 650−V Easy Drive SuperFET 3 MOSFET.
For the boost diode, we will select the FFSB0665A. It isa SiC 6−A 650−V single diode.
The specification for the power stage is the following:• Input voltage: 300 V,• Output voltage: 420 V,• Inductor current: 4 A,
• Inductor current ripple: 2 A,
• Switching frequency: 100 kHz,• Case temperature: 90°C,• Gate drive voltage: 10 V,• Gate series resistor: 8 Ω.

OUT

PwrTB

p
n

TB−Tj
Tj

FCH040N65S3_F155_5p
TB{Rgate}

DB−Tj

Tcase

esrCout{RCout}

RGate
RT
1Meg

Gate
n

Case

p

PwrDrv

OUT{Ths}
VHeatSink

I(sns)
Drive

PwrDrv

RD
1Meg

IN

Per Cycle Mean(PwrDB)

Mean

IN

PwrDB

Per Cycle Mean(PwrTB)

Mean

TIMING
Clk+

Cout{Cout}
IC={Vout*1.01}

PwrGateI(Sns)*V(P,N)

Per Cycle Mean(PwrDrv)

IN

PwrTB

TIMINGClk

PWM

TIMINGUPWM
SinglePWM
DMin=0.05 DMax=0.8

PWM

UFeedBack
FeedBack−Type 3 ++

Comp

Comp

Out

OUT

Meas

Duty
Clk

Zero=0 One=1 Tswr=10n+VMin=0 VMax={VDrv}+Idrv=2 Rdrv=100m

Mean

Clk

Comp

UDriveGate−Driver

Drive

Iout
{Iout}

Ramp
Duty

Clk

Ramp

Meas

Figure 51. Boost Power Stage SchematicIn the annex section, the same schematic is shown in abigger size in Figure 59.

To avoid long stabilization time, we will close the loop.
We will use a type 3 compensator with a voltage−mode pulse
width modulator.
We will use arbitrary functions to calculate losses in thediode, in the MOSFET and the power to drive the MOSFET.
The “Per Cycle” measurement will be used to obtain the
average losses for each cycle.
The schematic is shown in Figure 51.

Results

In Figure 52, we can see the power stage waveforms. We
can observe a power stage reaching a stable point after
10 ms. The output voltage is equal to 420 V with a 300−V
input voltage and an average current in the “pure” inductor(LB) equal to 4 A with ±1 A of ripple.

Figure 52. Boost Power Stage Waveforms

We can zoom at the simulation end (see Figure 53) and see
the output voltage ripple plus the “real” (i.e. with parasitic
capacitor CB in parallel) inductor current with the spikeduring the switch turn on and off. We can also plot theswitching node voltage.

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15

We can also measure the losses in the switching deviceson the waveforms from Figure 55.
When the power stage operates in stable conditions, thelosses amount is around 5.0 W in the switch and 3.9 W in thediode. To drive the switch, we need around 260 mW.

Figure 55. Averaging per Cycle Power Losses
Measurement
Analysis Beyond the Waveforms

Using this power stage, we will analyze the effect of theinductor parasitic capacitor on the diode and switch losses.
We will use four different values for this parasitic capacitor:
1 pF (almost nothing), 10 pF, 100 pF and finally 1 nF (a bad
inductor).
In Figure 56, we can see the diode is not affected by thiscapacitor nor the driving power needed for the switch.

Figure 53. Zoom on Boost Power Stage Waveforms

With the 5−pin model for the MOSFET and the 4−pinmodel for the SiC diode, we can see (Figure 54) how muchthe junction temperature increases for each device.
The FCH040N65S3 (40−mΩ 650−V Easy Drive
SuperFET 3 MOSFET) boost switch junction temperature
increases by 1.5°C while the FFSB0665A (6−A 650−V SiC
diode) boost diode junction temperature increases by 7.7°C.
The diode package is a DPACK while the MOSFET isencapsulated in a TO247. The package size explains thetemperature increase differences.

Figure 56. Diode Losses and Switch Driving Powerversus Inductor Parasitic Capacitor

However, the switch losses increase with this capacitor as
shown in Figure 57. We move from a 3.9 W loss budget with
1−pF parasitic−inductor capacitor to 14.0 W with a 1−nF
parasitic−inductor capacitor. The switch junction
temperature is affected accordingly.

Figure 54. Junction Temperature Waveforms

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16

Figure 58. Junction Temperature Change when the
Switch Turns On

If we zoom on the junction temperature waveform(Figure 58), we can see a sudden change of the temperature.
This happens when the switch is turned on. At this particular
moment, the switch output capacitor is rapidly discharged
into the switch. It creates losses but the inductor parasitic
capacitor is rapidly charged also bringing losses into theswitch due to the high peak located on top of the “ideal”
inductor current.

Figure 57. Switch Losses and Junction
Temperature versus Inductor Parasitic Capacitor

We can measure the following values on the Figure 57:
Table 1. LOSSES AND TEMPERATURE VS
INDUCTOR PARASITIC CAPACITOR VALUE (CB)CB

LossesJunction Temperature Increment

1 pF

3.9 W

1.1°C

10 pF

4.0 W

1.2°C

100 pF

4.9 W

1.4°C

1 nF

14.0 W

4.1°C

Optimizing the Power Stage

Now, using the same schematic, we can compare several
MOSFETs and diodes to optimize the boost stage losses.
We keep the 100−pF inductor parasitic capacitor because
this is a realistic value. The output power is equal to 1.2 kW.
We obtain the following Table 2 after several trials usinga TO220 package for the diode and a TO247 for the
MOSFET.
The last configuration with a 10−A SiC new generation
diode (FFSP1065B) and 99−mΩ Easy Drive SuperFET 3(FCH099N65S3) gives less losses... However, a 10−A SiC
diode for an average output current equal to 2.8 A could beconsider oversized thus expensive.
Running all these configurations can help to find the goodcompromise between performances and cost.

This analysis in Table 1 shows that not only the diode andswitch performances are important to determine powerstage losses, but, also the performances (or quality) of theboost inductor. The inductor losses are not so muchdependent on the parasitic inductor capacitor but the switch
losses are highly dependent on it. This parasitic inductor
capacitor has the same effect as the switch output capacitor
with a different operating mode. This parasitic capacitor
plays the same role (increasing losses) and appears likebeing in parallel with the switch output capacitor.

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17

Table 2. LOSSES COMPARISON TABLE VERSUS DIODE AND TRANSISTOR PART NUMBERS
D TJ
Diode

Drive
LossesMOSFET
Losses

Diode
Losses

Total
Losses

1.4°C

7.3°C

0.26 W

4.75 W

4.44 W

9.45 W

1.5°C

10.0°C

0.26 W

4.98 W

3.88 W

9.12 WFFSP0865A

1.5°C

4.1°C

0.26 W

5.26 W

3.63 W

9.15 WFFSP1065A

1.6°C

3.9°C

0.26 W

5.46 W

3.41 W

9.13 W

FCH040N65S3

FFSP1265A

1.7°C

3.7°C

0.26 W

5.67 W

3.28 W

9.21 W

FCH040N65S3

FFSP0665B

1.4°C

13.5°C

0.26 W

4.80 W

3.80 W

8.86 W

FCH040N65S3

FFSP1065B

1.5°C

5.4°C

0.26 W

5.09 W

3.30 W

8.65 W

FCH067N65S3

FFSP0665B

1.6°C

13.6°C

0.15 W

3.90 W

3.80 W

7.85 W

FCH099N65S3

FFSP0665B

1.3°C

13.6°C

0.11 W

3.79 W

3.78 W

7.68 W

FCH125N65S3R0

FFSP0665B

1.7°C

13.6°C

0.09 W

3.85 W

3.79 W

7.73 W

FCH099N65S3

FFSP1065B

1.5°C

9.4°C

0.11 W

4.16 W

3.30 W

7.57 W

MOSFET (TB)

Diode (DB)D TJ
MOSFET

FCH040N65S3

FFSP0465A

FCH040N65S3

FFSP0665A

FCH040N65S3
FCH040N65S3

CONCLUSION
In this paper, we demonstrated the ability of the physicaland scalable models to predict discrete components
operation.
We can use these models to reproduce specification curves
or parameters with very simple simulation setup. All these
setups have been explained and results have been shown.
We can also use the models to extract parameters or
generate curves when they are not available in thespecification. For example, the on resistance change withtemperature or with self−heating using models
implementing “Junction temperature” and “Casetemperature” extra pins. We can also see how self−heating
affects a given operating area by monitoring the junction
temperature.
They could also be used to determine parameters at adifferent operating point than the one given in thespecification. For example, with the effective capacitor
value, we can get the value for all drain to source possible
voltage.
Finally, we have used these physical and scalable models
in a real application simulation. We have created a boost
power stage and run the simulations to get more information.
We analyzed the losses in the switch as a function of inductor
parasitic capacitor. We also calculate losses for several partnumbers to determine the optimum boost stage
configuration (MOSFET and diode).
Physical and scalable models can really help a designer toanalyze components characteristics and optimize
application performances.
REFERENCES[1] “A Physically Based Scalable SPICE Model for
Shielded−Gate Trench Power MOSFETs”
Proceedings of the 2016 28th International
Symposium on Power Semiconductor Devices and ICs(ISPSD)[2] “A Physically Based Scalable SPICE Model for
Silicon Carbide Power MOSFETs”
Applied Power Electronics Conference (APEC) 2017[3] “Physically Based, Scalable SPICE Modeling
Methodologies for Modern Power Electronic Devices”
Technical note TND6260[4] “SPICE Modeling Tutorial”, Technical note TND6248[5] “How to use Physical and Scalable Models with
SIMetrix, OrCAD and LTspice” Application note
AND9783[6] “MOSFET Basics” Application note: AN−9010[7] “Characterizing the dynamic output capacitance of a
MOSFET”, EDN

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18

ANNEX: BOOST SCHEMATIC ZOOM
PwrDB

SW
PwrDiode{CBoost}I(Sns)*V(P,N)
OUT

CB{LBoost} IC=0
{RBoost}RB

I(sns)

iLB

p

LB

OUT

n

IN

Out

I(Sns)*V(P,N)
PwrDrain

DB FFSB0665A_4p

I(sns)
OUT
p
n

Tj

PwrTB

Tcase

{Vin}
Vin

TB−Tj
Tj

FCH040N65S3_F155_5p
TB{Rgate}

DB−Tj

Tcase

esrCout{RCout}

RGate

n

Case

p

PwrDrv

OUT{Ths}
VHeatSink

I(sns)
Drive

PwrDrv

PwrGateI(Sns)*V(P,N)

Per Cycle Mean(PwrDB)

Mean

IN

PwrDB

+

Per Cycle Mean(PwrTB)

Mean

TIMING
Clk

Drive

RD
1Meg

Cout
{Cout}
IC={Vout*1.01}

Per Cycle Mean(PwrDrv)
IN

Iout{Iout}

RT
1Meg

Gate

IN

PwrTB

TIMINGClk

PWM

TIMING
Clk

Comp
UPWM
SinglePWM

UDriveGate−Driver
DMin=0.05 DMax=0.8

PWM

UFeedBack
FeedBack−Type 3 ++

Comp

Comp
Meas

Duty
Clk

Zero=0 One=1 Tswr=10n+VMin=0 VMax={VDrv}+Idrv=2 Rdrv=100m

Ramp
Duty

Clk

Ramp

Figure 59. Boost Power stage Schematic

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19

Mean

Meas

Out

OUT

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onsemi,, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of theinformation, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or useof any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance mayvary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any licenseunder any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
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