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0B

ER-OLED0.96 Series
1B

2B

OLED Display Datasheet

ISO9001
Registered Company

sira

CERTIFICATION

011

EastRising Technology Co., Limited
Attention:
4B

A. Some specifications of IC are not listed in this datasheet. Please refer to the IC datasheet for more details.
B. The related documents for interfacing, demo code, ic datasheet are all available, please download from www.buydisplay.com.
C. Please pay more attention to “Quality Control” in this Datasheet. We assume you already agree with these criterions when you place an orderwith us. No more recommendations.
7B

REV

DESCRIPTION

1.0

Preliminary Release

8B3

1B6

URL:

RELEASE DATE

9B4

10B5

12B7

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13B8

Document Name: ER-OLED0.96 Series Datasheet-Rev1.0

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ORDERING INFORMATION
54B197

Order Number
Part Number(Order Number)

Description

ER-OLED0.96-1YB

0.96”OLED Display Module in Blue and Yellow Color

ER-OLED0.96-2B

0.96”OLED Display Module in Blue Color

ER-OLED0.96-3W

0.96”OLED Display Module in White Color

ER-DBO0.96

Testing or Demo Board for ER-OLED0.96 Series Products

Image
H

ER-OLED0.96-1YB ↑URL:

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H

ER-OLED0.96-2B ↑ER-OLED0.96-3W↑

Document Name: ER-OLED0.96 Series Datasheet-Rev1.0

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Contents
Revision History ................................................................................................... i
Notice ................................................................................................................... ii
Contents .............................................................................................................. iii
1. Basic Specifications .................................................................................. 1~5
1.1
1.2
1.3
1.4
1.5
1.6

Display Specifications .................................................................................................1
Mechanical Specifications ...........................................................................................1
Active Area & Pixel Construction ...............................................................................1
Mechanical Drawing....................................................................................................2
Pin Definition...............................................................................................................3
Block Diagram .............................................................................................................5
1.6.1 VCC Supplied Externally ....................................................................................5
1.6.2 VCC Generated by Internal DC/DC Circuit........................................................6

2. Absolute Maximum Ratings .......................................................................... 7
3. Optics & Electrical Characteristics ......................................................... 8~13
3.1 Optics Characteristics ..................................................................................................8
3.2 DC Characteristics .......................................................................................................8
3.3 AC Characteristics .......................................................................................................93.3.1 68XX-Series MPU Parallel Interface Timing Characteristics ...........................93.3.2 80XX-Series MPU Parallel Interface Timing Characteristics .........................10
3.3.3 Serial Interface Timing Characteristics (4-wire SPI).......................................11
3.3.4 Serial Interface Timing Characteristics (3-wire SPI).......................................123.3.5 I2C Interface Timing Characteristics ...............................................................13

4. Functional Specification ....................................................................... 14~15
4.1 Commands .................................................................................................................14
4.2 Power down and Power up Sequence ........................................................................144.2.1 Power up Sequence ..........................................................................................144.2.2 Power down Sequence .....................................................................................14
4.3 Reset Circuit...............................................................................................................14
4.4 Actual Application Example ......................................................................................15

5. Reliability ...................................................................................................... 16
5.1 Contents of Reliability Tests......................................................................................16
5.2 Lifetime......................................................................................................................16
5.3 Failure Check Standard..............................................................................................16

64. Quality Control ............................................................................................17

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1. Basic Specifications
1.1 Display Specifications
1)
2)

Display Mode:
Drive Duty:

Passive Matrix
1/64 Duty

1.2 Mechanical Specifications
1)
2)
3)
4)
5)
6)
7)

Outline Drawing: According to the annexed outline drawing
Number of Pixels: 128 × 64
Panel Size:
26.70 × 19.26 × 1.45 (mm)Active Area:
21.744 × 10.864 (mm)Pixel Pitch:
0.17 × 0.17 (mm)Pixel Size:
0.154 × 0.154 (mm)Weight:1.54 (g)

1.3 Active Area & Pixel Construction
P0.17x128-0.016=21.744
"A"

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0.17
0.154

P0.17x64-0.016=10.864

0.17
0.154

Segment 127( Column 1 )Common 32

Segment 0( Column 128 )Common 0( Row 63 )( Row 64 )Common 63

Common 31( Row 1 )Detail "A"
Scale (10:1)( Row 2 )Document Name: ER-OLED0.96 Series Datasheet-Rev1.012±0.3(2.35)

1

10

D /C#

R/W#

C S#

RES#

VCC

D3

D6

D1

D4

E/RD#

D2

D0

BS1

V DD

BS2

N .C.

VBAT

VSS

BS0

C 1N

C 2N

C1P

C2P

12±0.216±0.1 (Alignment Mark)
P0.70x(30-1)=20.3±0.05 (W0.40±0.03)
0.85±0.1
22±0.2W 0.4

30

2-R0.4±0.05

N .C. (GND)

Active Area 0.96"
128 x 64 Pixels

D5

0.5±0.5(1.478)(2.478)V COMH26.7±0.2 (Panel Size)
26.7±0.2 (Cap Size)
25.7±0.5 (Polarizer)
23.744 (V/A)
21.744 (A/A)

IREF

11.204 (A/A)
13.204 (V/A)
14.4±0.5 (Polarizer)
15.5±0.2 (Cap Size)
19.26±0.2 (Panel Size)(31.26)D7

5

8

Document Name: ER-OLED0.96 Series Datasheet-Rev1.0

Remove Tapet=0.15mm Max
Unit

Tolerance±0.3
Dimension
Angle
±1

mm

Unless Otherwise Specified

General Roughness

0.154
0.17
Detail "A"
Scale (10:1)(1.613)

By
Date

Title

E.E.
James Wang
20100622

20100622

Drawn

20100622

Panel / E.
Ivy Lo

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

20100622

P.M.
Cherry Lin

ER-OLED0.96 Series Folding Type OEL Display Module
Pixel Number: 128 x 64, COG Package

Jaffery

Pin
1
2
3
4
5
6
7
8

Rev.
A

Scale
1:1

Sheet
1 of 1

Size
A3

Soda Lime / Polyimide

Material

Drawing Number

C2P
C2N
C1P
C1N
VBAT
N.C.
VSS
VDD
BS0
BS1
BS2
CS#
RES#
D/C#
R/W#
E/RD#
D0
D1
D2
D3
D4
D5
D6
D7
IREF
VCOMH
VCC
VLSS
N.C. (GND)

N.C. (GND)

SymbolRemarkOriginal Drawing

Date20090120

EastRising Technology Co.,Ltd.

0.1±0.03

0.17
0.154

Item
A

OLED Display Datasheet

buydisplay.com

R

1.45±0.1(1.6)

N .C. (GND)

15.05

V LSS

(2.098)(1.098)0.5±0.5
3M #1318B Polarizer
15x8x0.063mm t=0.2mm

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Glue

URL:
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Contact SideR

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1.4 Mechanical Drawing

4
4.75
6.887

12.00

2

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1.5 Pin Definition
Pin Number

Symbol

Type

9

VDD

P

8

VSS

P

Function

Power Supply
Power Supply for Logic
This is a voltage supply pin. It must be connected toexternal source.

Ground of Logic Circuit
This is a ground pin. It acts as a reference for the logic
pins. It must be connected to external ground.

Power Supply for OEL Panel
28

VCC

P

29

VLSS

P

This is the most positive voltage supply pin of the chip.
A stabilization capacitor should be connected between
this pin and VSS when the converter is used. It must beconnected to external source when the converter is not
used.

Ground of Analog Circuit
This is an analog ground pin. It should be connected to VSS
externally.

DriverCurrent Reference for Brightness Adjustment
26

IREF

I

This pin is segment current reference pin. A resistor
should be connected between this pin and VSS. Set thecurrent lower than 12.5μA.

Voltage Output High Level for COM Signal
27

VCOMH

O

This pin is the input pin for the voltage output high level
for COM signals. A capacitor should be connected
between this pin and VSS.

DC/DC Converter
Power Supply for DC/DC Converter Circuit
6

4/5
2/3

VBAT

C1P / C1N
C2P / C2N

P

I

This is the power supply pin for the internal buffer of the
DC/DC voltage converter. It must be connected toexternal source when the converter is used. It should beconnected to VDD when the converter is not used.

Positive Terminal of the Flying Inverting Capacitor
Negative Terminal of the Flying Boost Capacitor
The charge-pump capacitors are required between theterminals. They must be floated when the converter is
not used.

InterfaceCommunicating Protocol Select
10
11
12

BS0
BS1
BS2

I

14

RES#

I

These pins are MCU interface selection input. See thefollowing table:
BS0
BS1
BS2
I2C
0
1
0
3-wire SPI
1
0
0
0
0
4-wire SPI
0
8-bit 68XX Parallel
0
0
1
0
1
1
8-bit 80XX Parallel

Power Reset for Controller and DriverURL:

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This pin is reset signal input. When the pin is low,
initialization of the chip is executed.

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1.5 Pin Definition (Continued)
Pin Number

SymbolI/O

FunctionInterface (Continued)
Chip Select
13

CS#

I

This pin is the chip select input. The chip is enabled for
MCU communication only when CS# is pulled low.

Data/Command Control

15

D/C#

I

This pin is Data/Command control pin. When the pin ispulled high, the input at D7~D0 is treated as display data.
When the pin is pulled low, the input at D7~D0 will betransferred to the command register.
For detail
relationship to MCU interface signals, please refer to theTiming Characteristics Diagrams.
When the pin is pulled high and serial interface mode isselected, the data at SDIN is treated as data. When it ispulled low, the data at SDIN will be transferred to thecommand register. In I2C mode, this pin acts as SA0 forslave address selection.

Read/Write Enable or Read

17

E/RD#

I

This pin is MCU interface input. When interfacing to a
68XX-series microprocessor, this pin will be used as the
Enable (E) signal. Read/write operation is initiated when
this pin is pulled high and the CS# is pulled low.
When connecting to an 80XX-microprocessor, this pin
receives the Read (RD#) signal. Data read operation is
initiated when this pin is pulled low and CS# is pulled
low.

Read/Write Select or Write

16

R/W#

I

This pin is MCU interface input. When interfacing to a
68XX-series microprocessor, this pin will be used as
Read/Write (R/W#) selection input. Pull this pin to“High” for read mode and pull it to “Low” for write
mode.
When 80XX interface mode is selected, this pin will be
the Write (WR#) input. Data write operation is initiatedwhen this pin is pulled low and the CS# is pulled low.

Host Data Input/Output Bus
18~25

D0~D7

I/O

N.C.

-

These pins are 8-bit bi-directional data bus to beconnected to the microprocessor’s data bus. When serial
mode is selected, D1 will be the serial data input SDIN
and D0 will be the serial clock input SCLK. When I2C
mode is selected, D2 & D1 should be tired together andserve as SDAout & SDAin in application and D0 is theserial clock input SCL.

Reserve
Reserved Pin
7

The N.C. pins between function pins are reserved forcompatible and flexible design.

Reserved Pin (Supporting Pin)
1, 30

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N.C. (GND)-

The supporting pins can reduce the influences fromstresses on the function pins. These pins must beconnected to external ground.

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1.6 Block Diagram
1.6.1 VCC Supplied Externally~

Common 31~ ~ ~Common 0

Segment 0

Segment 127~

Common 32

Common 63

Active Area 0.96"
128 x 64 Pixels

VLSS

IREF
VCOMH
VCC

~

D7

D0

VDD
BS0
BS1
BS2
CS#
RES#
D/C#
R/W#
E/RD#

C2P
C2N
C1P
C1N
VBAT
VSS

SSD1306

C5
C1
C2

R1
C3
C4

MCU Interface Selection:
BS0, BS1 and BS2
Pins connected to MCU interface: CS#, RES#, D/C#, R/W#, E/RD#, and
D0~D7
C1, C3: 0.1μF
C2, C4: 2.2μF
C5:4.7μF X7R
R1:
560kΩ, R1 = (Voltage at IREF – VSS) / IREF

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1.6.2 VCC Generated by Internal DC/DC Circuit~

Common 31~ ~ ~Common 0

Segment 0

Segment 127~

Common 32

Common 63

Active Area 0.96"
128 x 64 Pixels

C6

C5

C2

C1

VLSS

IREF
VCOMH
VCC

~

D7

D0

VDD
BS0
BS1
BS2
CS#
RES#
D/C#
R/W#
E/RD#

VSS

C2P

C2N
C1P

C1N
VBAT

SSD1306

C3
C4R1

MCU Interface Selection:
BS0, BS1 and BS2
Pins connected to MCU interface: CS#, RES#, D/C#, R/W#, E/RD#, and
D0~D7
C1, C2, C5, C6: 1μF
C3:
2.2μF
C4:
4.7μF X7R
R1:
390kΩ, R1 = (Voltage at IREF – VSS) / IREF

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2. Absolute Maximum Ratings
Parameter

Symbol

Min

Max

Unit

Notes

Supply Voltage for Logic

VDD

-0.3

4

V

1, 2

Supply Voltage for Display

VCC

0

11

V

1, 2

Supply Voltage for DC/DC

VBAT

-0.3

5

V

1, 2

Operating Temperature

TOP

-30

70

°C

-

Storage Temperature

TSTG

-40

80

°C

-

Note 1: All the above voltages are on the basis of “VSS = 0V”.
Note 2: When this module is used beyond the above absolute maximum ratings,
permanent breakage of the module may occur. Also, for normal operations, it isdesirable to use this module under the conditions according to Section 3.
“Optics & Electrical Characteristics”. If this module is used beyond these
conditions, malfunctioning of the module can occur and the reliability of themodule may deteriorate.

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3. Optics & Electrical Characteristics
3.1 Optics Characteristics
Characteristics
SymbolBrightness
Lbr(VCC Supplied Externally)
Brightness
Lbr(VCC Generated by Internal DC/DC)(x)
C.I.E.
(y)Dark Room Contrast
CR

Conditions
With Polarizer(Note 3)
With Polarizer(Note 4)
Without Polarizer

View Angle

Min

Typ

Max Unit

100

120

-

cd/m2

80

100

-

cd/m2

0.12 0.16 0.20
0.22 0.26 0.30
- >2000:1 >160--

degree* Optical measurement taken at VDD = 2.8V, VCC = 9V & 7.25V.
Software configuration follows Section 4.4 Initialization.

3.2 DC Characteristics
Characteristics

SymbolConditions

Min

Typ Max Unit

Supply Voltage for Logic
Supply Voltage for Display(Supplied Externally)
Supply Voltage for DC/DC
Supply Voltage for Display(Generated by Internal DC/DC)High Level Input

VDD

-

1.65

2.8

3.3

V

VCC

Note 3

8.5

9

9.5

V

VBAT

Internal DC/DC Enable

3.5

-

4.2

V

VCC

Note 4

7

7.25

7.5

V

VIH

-

-

VDD

V

Low Level Input

VIL-

0.8×VDD
0-

V

High Level Output

VOH-

Low Level Output

VOL

IOUT = 100μA, 3.3MHz 0.9×VDD
IOUT = 100μA, 3.3MHz 0

0.2×VDD
VDD

Operating Current for VDD

IDD

Operating Current for VCC(VCC Supplied Externally)

ICC

Operating Current for VBAT(VCC Generated by Internal DC/DC)

IBAT

V

-

-

-

Note 5-

0.1×VDD V
180 300 μA
7.3
9.1 mA

Note 6

-

12.3

15.4

mA

Note 7

-

18.8

23.5

mA

Note 8

-

25.6

32.0

mA

Sleep Mode Current for VDD IDD, SLEEP

-

-

1

5

μA

Sleep Mode Current for VCC ICC, SLEEP

-

-

1

5

μA

Note 3 & 4: Brightness (Lbr) and Supply Voltage for Display (VCC) are subject to thechange of the panel characteristics and the customer’s request.
Note 5:
VDD = 2.8V, VCC = 9V, 50% Display Area Turn on.
Note 6:
VDD = 2.8V, VCC = 9V, 100% Display Area Turn on.
Note 7:
VDD = 2.8V, VCC = 7.25V, 50% Display Area Turn on.
Note 8:VDD = 2.8V, VCC = 7.25V, 100% Display Area Turn on.
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3.3 AC Characteristics
3.3.1 68XX-Series MPU Parallel Interface Timing Characteristics:
Symbol Description

Min

Max

Unit

tcycleClock Cycle Time

300

-

ns

tAS

Address Setup Time

0

-

ns

tAH

Address Hold Time

0

-

ns

tDSW

Write Data Setup Time

40

-

ns

tDHW

Write Data Hold Time

7

-

ns

tDHR

Read Data Hold Time

20

-

ns

tOH

Output Disable Time

-

70

ns

tACC

Access Time

-

140

ns

Chip Select Low Pulse Width (Read)

120

Chip Select Low Pulse width (Write)

60

-

ns

Chip Select High Pulse Width (Read)

60

Chip Select High Pulse Width (Write)

60

-

ns

tR

Rise Time

-

40

ns

tF

Fall Time

-

40

ns

PWCSL
PWCSH

* (VDD - VSS = 1.65V to 3.3V, Ta = 25°C)

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3.3.2 80XX-Series MPU Parallel Interface Timing Characteristics:
Symbol Description

Min

Max

Unit

tcycleClock Cycle Time

300

-

ns

tAS

Address Setup Time

10

-

ns

tAH

Address Hold Time

0

-

ns

tDSW

Write Data Setup Time

40

-

ns

tDHW

Write Data Hold Time

7

-

ns

tDHR

Read Data Hold Time

20

-

ns

tOH

Output Disable Time

-

70

ns

tACC

Access Time

-

140

ns

tPWLR

Read Low Time

120

-

ns

tPWLW

Write Low Time

60

-

ns

tPWHR

Read High Time

60

-

ns

tPWHW

Write High Time

60

-

ns

tCS

Chip Select Setup Time

0

-

ns

tCSH

Chip Select Hold Time to Read Signal

0

-

ns

tCSF

Chip Select Hold Time

20

-

ns

tR

Rise Time

-

40

ns

tF

Fall Time

-

40

ns

* (VDD - VSS = 1.65V to 3.3V, Ta = 25°C)( Read Timing )( Write Timing )URL:www.buydisplay.com

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3.3.3 Serial Interface Timing Characteristics: (4-wire SPI)
Symbol Description

Min

Max

Unit

tcycleClock Cycle Time

100

-

ns

tAS

Address Setup Time

15

-

ns

tAH

Address Hold Time

15

-

ns

tCSS

Chip Select Setup Time

20

-

ns

tCSH

Chip Select Hold Time

10

-

ns

tDSW

Write Data Setup Time

15

-

ns

tDHW

Write Data Hold Time

15

-

ns

tCLKL

Clock Low Time

20

-

ns

tCLKH

Clock High Time

20

-

ns

tR

Rise Time

-

40

ns

tF

Fall Time

-

40

ns

* (VDD - VSS = 1.65V to 3.3V, Ta = 25°C)

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3.3.4 Serial Interface Timing Characteristics: (3-wire SPI)
Symbol Description

Min

Max

Unit

tcycleClock Cycle Time

100

-

ns

tCSS

Chip Select Setup Time

20

-

ns

tCSH

Chip Select Hold Time

10

-

ns

tDSW

Write Data Setup Time

15

-

ns

tDHW

Write Data Hold Time

15

-

ns

tCLKL

Clock Low Time

20

-

ns

tCLKH

Clock High Time

20

-

ns

tR

Rise Time

-

40

ns

tF

Fall Time

-

40

ns

* (VDD - VSS = 1.65V to 3.3V, Ta = 25°C)

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3.3.5 I2C Interface Timing Characteristics:
Symbol Description

Min

Max

Unit

tcycleClock Cycle Time

2.5

-

us

tHSTART

Start Condition Hold Time

0.6

-

us

Data Hold Time (for “SDAOUT” Pin)0

Data Hold Time (for “SDAIN” Pin)

300

-

ns

100

-

ns

0.6

-

us

tSSTOP

Data Setup Time
Start Condition Setup Time
(Only relevant for a repeated Start
condition)
Stop Condition Setup Time

0.6

-

us

tR

Rise Time for Data and Clock Pin

300

ns

300

ns

-

us

tHD
tSD
tSSTART

tF

Fall Time for Data and Clock Pin
Idle Time before a New TransmissiontIDLE
can Start* (VDD - VSS = 1.65V to 3.3V, Ta = 25°C)

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1.3

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4. Functional Specification
4.1. Commands
Refer to the Technical Manual for the SSD1306

4.2 Power down and Power up Sequence
To protect OEL panel and extend the panel life time, the driver IC power up/downroutine should include a delay period between high voltage and low voltage powersources during turn on/off. It gives the OEL panel enough time to complete theaction of charge and discharge before/after the operation.
4.2.1 Power up Sequence:
1.
2.
3.
4.
5.
6.

Power up VDD
Send Display off command
Initialization
Clear Screen
Power up VCC
Delay 100ms(When VCC is stable)
7. Send Display on command

VDD on
VCC on
Display on
VCC
VDD
VSS/Ground4.2.2 Power down Sequence:
1. Send Display off command
2. Power down VCC
3. Delay 100ms(When VCC is reach 0 and panel
is completely discharges)
4. Power down VDD

Display off
VCC off
VDD off
VCC
VDD
VSS/Ground

4.3 Reset Circuit
When RES# input is low, the chip is initialized with the following status:
1. Display is OFF
2. 128×64 Display Mode
3. Normal segment and display data column and row address mapping (SEG0mapped to column address 00h and COM0 mapped to row address 00h)
4. Shift register data clear in serial interface
5. Display start line is set at display RAM address 0
6. Column address counter is set at 0
7. Normal scan direction of the COM outputs
8. Contrast control register is set at 7Fh
9. Normal display mode (Equivalent to A4h command)

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4.4 Actual Application Example
Command usage and explanation of an actual example<Initialization>

Set Display Off
0xAE

Set Segment Re-Map
0xA1

Set Entire Display On/Off
0xA4

Set Display Clock Divide Ratio/Oscillator Frequency

0xD5, 0x80

Set COM Output Scan Direction
0xC8

Set Normal/Inverse Display
0xA6

Set Multiplex Ratio
0xA8, 0x3F

Set COM Pins Hardware Configuration
0xDA, 0x12

Clear Screen

Set Display Offset
0xD3, 0x00

* Set Contrast Control
0x81, 0x9F(1) / 0xCF(2)Set Display On
0xAF

Set Display Start Line
0x40

* Set Pre-Charge Period
0xD9, 0x22(1) / 0xF1(2)* Set Charge Pump
0x8D, 0x10(1) / 0x14(2)Set VCOMH Deselect Level
0xDB, 0x40

* Written Value for Parameters(1)
Î VCC Supplied Externally(2)
Î VCC Generated by Internal DC/DC Circuit
If the noise is accidentally occurred at the displaying window during the operation,please reset the display in order to recover the display function.

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5. Reliability
5.1 Contents of Reliability Tests
Item

Conditions

High Temperature Operation

70°C, 240 hrs

Low Temperature Operation-30°C, 240 hrs

High Temperature Storage

80°C, 240 hrs

Low Temperature Storage-40°C, 240 hrs

Criteria

The operational
functions work.

High Temperature/Humidity Operation 60°C, 90% RH, 120 hrs-40°C ⇔ 85°C, 24 cycles
Thermal Shock60 mins dwell* The samples used for the above tests do not include polarizer.
* No moisture condensation is observed during tests.

5.2 Lifetime
End of lifetime is specified as 50% of initial brightness reached.
Parameter

Min

Max

Unit

Condition
2

Notes

Operating Life Time 10,000-hr

100 cd/m , 50% Checkerboard

6

Storage Life Time-hr

Ta = 25°C, 50% RH-

20,000Note 6: The average operating lifetime at room temperature is estimated by theaccelerated operation at high temperature conditions.

5.3 Failure Check Standard
After the completion of the described reliability test, the samples were left at room
temperature for 2 hrs prior to conducting the failure test at 23±5°C; 55±15% RH.

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6. QUALITY CONTROL
6.1 EastRising Environment Required
Customer’s test & measurement are required to be conducted under the following conditions:Temperature:
23±5℃
Humidity:
55±15% RH
Fluorescent Lamp:
30W
Distance between the Panel & Lamp:≥50cm
Distance between the Panel & Eyes of the Inspector:≥30cm
Finger glove (or finger cover) must be worn by the inspector.
Inspection table of jig must be anti-electrostatic.
6.2 EastRising OLED Display Criteria & Acceptable Quality Level
Partition

AQL

Definition

Major

0.65

Defects in Pattern Check (Display On)

Minor

1.0

Defects in Cosmetic Check (Display Off)6.2.1 EastRising Cosmetic Check (Display Off) in Non-Active Area
Check ItemClassification

Criteria
X>6mm (Along with Edge)
Y>1mm (Perpendicular to edge)

X

Panel General Chipping

Minor

Y

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6.2.2 EastRising Cosmetic Check (Display Off)in Non-Active Area (Continued)
Check ItemClassification

Criteria
Any crack is not allowable

Panel Crack
Minor

Copper Exposed(Even Pin or Film)

Minor

Film or Trace Damage

Minor

Termial Lead Prober Mark

Acceptable

Glue or Contamination on Pin

Minor

Ink marking on Back Side of Panel(Exclude on Film)

Acceptable

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Not Allowable by Naked Eye Inspection

Ignore for Any

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6.2.3 EastRising Cosmetic Check (Display Off) in Active Area
EastRising recommends to execute in clear environment (class 10k) if actual in necessary.
Check ItemClassification

Any Dirt & Scratch on Polarizer’s
Protective Film

Acceptable

Scratches,Fiber,Line-Shape Defect(On Polarizer)

Dirt, Black Spot, Foreign Material(On Polarizer)

Criteria
Ignore for not Affect the Polarizer

Minor

Minor

W≤0.1
W＞0.1
L≤2
L＞2

IgnoreΦ≤0.1

Ignore
n≤1
n＝0

n≤1
n＝0

0.1＜Φ≤0.25
0.25＜Φ
Φ≤0.5

Ignore if no Influence on Display
0.5＜Φ
n＝0

Dent,Bubbles,White Spot
(Any Transparent Spot on Polarizer)

Minor

Fingerpint ,Flow Mark(On Polarizer)

Minor

Not Allowable* Protective film should not be tear off when cosmetic check.
* Definition of W & L &Φ(Unit:mm): Φ=(a+b)/2

L

b: Minor Axis

W
a: Major Axis

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6.2.4 EastRising Pattern Check (Display On) in Active Area

URL:

Check ItemClassification

No Display

Major

Missing Line

Major

Pixel Short

Major

Darker Pixel

Major

Wrong Display

Major

Un-uniform

Major

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Criteria

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7.PRECAUTIONS for USING
7.1 Handling Precautions
1) Since the EastRiisng OLED display panel is being made of glass, do not apply mechanical impacts such
us dropping from a high position.
2) If the display panel is broken by some accident and the internal organic substance leaks out, be careful
not to inhale nor lick the organic substance.
3) If pressure is applied to the display surface or its neighborhood of the EastRising OLED display module,
the cell structure may be damaged and be careful not to apply pressure to these sections.
4) The polarizer covering the surface of the OLED display module is soft and easily scratched.
be careful when handling the OLED display module.

Please5) When the surface of the polarizer of the OLED display module has soil, clean the surface. It takes
advantage of by using following adhesion tape.
* Scotch Mending Tape No. 810 or an equivalent
Never try to breathe upon the soiled surface nor wipe the surface using cloth containing solvent such as
ethyl alcohol, since the surface of the polarizer will become cloudy. Also, pay attention that the following
liquid and solvent may spoil the polarizer:* Water* Ketone* Aromatic Solvents
6) Hold EastRising OLED display module very carefully when placing OLED display module into the system
housing. Do not apply excessive stress or pressure to OLED display module. And, do not over bend
the film with electrode pattern layouts. These stresses will influence the display performance. Also,
secure sufficient rigidity for the outer cases.
7) Do not apply stress to the driver IC and the surrounding molded sections.
8) Do not disassemble nor modify the OLED display module.
9) Do not apply input signals while the logic power is off.
10) Pay sufficient attention to the working environments when handing EastRising OLED display modules
to prevent occurrence of element breakage accidents by static electricity.
* Be sure to make human body grounding when handling OLED display modules.
* Be sure to ground tools to use or assembly such as soldering irons.
* To suppress generation of static electricity, avoid carrying out assembly work under dry environments.

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ER-OLED0.96 Seriesbuydisplay.com* Protective film is being applied to the surface of the display panel of the OLED display module.
Be careful since static electricity may be generated when exfoliating the protective film.
11) Protection film is being applied to the surface of the display panel and removes the protection film
before assembling it. At this time, if the EastRising OLED display module has been stored for a long periodof time, residue adhesive material of the protection film may remain on the surface of the display panel after
removed of the film. In such case, remove the residue material by the method introduced in the above
Section 5).
12) If electric current is applied when the OLED display module is being dewed or when it is placed underhigh humidity environments, the electrodes may be corroded and be careful to avoid the above.
7.2 Storage Precautions
1) When storing EastRising OLED display modules, put them in static electricity preventive bags avoiding
exposure neither to direct sun light nor to lights of fluorescent lamps. and, also, avoiding hightemperature and highhumidity environment or low temperature (less than 0℃) environments. (We recommend you to store
these modules in the packaged state when they were shipped from EastRising.) At that time, be careful
not to let water drops adhere to the packages or bags nor let dewing occur with them.
2) If electric current is applied when water drops are adhering to the surface of the OLED display module,
when the OLED display module is being dewed or when it is placed under high humidity environments,
the electrodes may be corroded and be careful about the above.
7.3 Designing Precautions
1) The absolute maximum ratings are the ratings which cannot be exceeded for OLED display module,
and if these values are exceeded, panel damage may be happen.
2) To prevent occurrence of malfunctioning by noise, pay attention to satisfy the VIL and VIH specifications
and, at the same time, to make the signal line cable as short as possible.
3) We recommend you to install excess current preventive unit (fuses, etc.) to the power circuit (VDD).
(Recommend value: 0.5A)4) Pay sufficient attention to avoid occurrence of mutual noise interference with the neighboring devices.
5) As for EMI, take necessary measures on the equipment side basically.
6) When fastening the OLED display module, fasten the external plastic housing section.

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7) If power supply to the EastRising OLED display module is forcibly shut down by such errors as taking out
the main battery while the OLED display panel is in operation, we cannot guarantee the quality of this
OLED display module.
7.4 Precautions when disposing of the EastRising OLED display modules
1) Request the qualified companies to handle industrial wastes when disposing of the OLED display
modules. Or, when burning them, be sure to observe the environmental and hygienic laws andregulations.
7.5 Other Precautions
1) When an OLED display module is operated for a long of time with fixed pattern may remain as an afterimage or slight contrast deviation may occur. Nonetheless, if the operation is interrupted and left unused
for a while, normal state can be restored. Also, there will be no problem in the reliability of the module.
2) To protect OLED display modules from performance drops by static electricity rapture, etc., do not touch
the following sections whenever possible while handling the OLED display modules.
* Pins and electrodes* Pattern layouts such as the FPC
3) With this OLED display module, the OLED driver is being exposed. Generally speaking, semiconductor
elements change their characteristics when light is radiated according to the principle of the solar battery.
Consequently, if this OLED driver is exposed to light, malfunctioning may occur.
* Design the product and installation method so that the OLED driver may be shielded from light in actual
usage.
* Design the product and installation method so that the OLED driver may be shielded from light during
the inspection processes.
4) Although this OLED display module stores the operation state data by the commands and the indication
data, when excessive external noise, etc. enters into the module, the internal status may be changed. It
therefore is necessary to take appropriate measures to suppress noise generation or to protect frominfluences of noise on the system design.
5) We recommend you to construct its software to make periodical refreshment of the operation statuses(re-setting of the commands and re-transference of the display data) to cope with catastrophic noise.

That’s the end of the datasheet.

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