Ⅲ-1. Atomic & Solid State Physics (Ion)

RIKEN Accel. Prog. Rep. 49 (2016)

Evaluation ofof single
single event
event transienttransienterror
error rate
rate related
related toto operation
operation frequency
frequency
Evaluationon
64bit SOI
SOImicro
micro processor
processor
on 64bitA. Maru,䠆1 K. Sakamoto,*1 H. Shindou,*1 S. Kuboyama,䠆1 and K. Suzuki䠆1Silicon on Insulator (SOI) devices are the focus for recent
electronic applications due to their excellent characteristics
which are low power consumption and possibility ofminiaturization. They also have excellent characteristics
with regard to the angle of radiation tolerance. Single event
latch up (SEL) has never occurred in SOI devices due totheir cross-sectional structure. Since the SOI transistor has
been electrically isolated from others by buried oxide(BOX), electrical circuits with excellent single event upset(SEU) and single event transient (SET) tolerance can becomposed by using SOI transistors. In addition, the Japan
Aerospace Exploration Agency (JAXA) focused on SOI
devices for space applications and has been continuously
involved in research and development since 2005. JAXA
has developed the Micro Processer Unit (MPU) andApplication Specific Integrated Circuit (ASIC) for space
applications by combining SOI devices and radiation
hardness by design (RHBD) techniques.1) They are used innumerous spacecraft. Recently, it was reported in certain
project that many SEUs were observed in the SOI productused in satellites. Reported error rates of SEUs on the orbit
was higher than the calculated error rates from radiation
tests on the ground. Therefore, it was suggested that some
defects exist in this device.
From our analysis, it was identified that one defect in thisdevice was due to a parasitic diode on the drain area of theSOI transistor, as shown in Fig.1. We identified the parasitic
diode was created in one fabrication process of the SOItransistor, so we tried to fix this defect by changing theprocess condition of the SOI transistor. The evaluation
results of the SOI device, which was fabricated using afixed process condition indicated that it had high radiation
tolerance. Under static test conditions, no error wasobserved on this device. However, a few errors wereobserved under dynamic test conditions (continuousmemory data read/write condition). It is presumed that thecause of this error is temporal read miss due to SET.

In the case of error due to SET, the error rate depends on
the operation frequency of the device. Therefore weevaluated the error rate operation frequency dependence of
this SOI device for calculating the error rate on the orbit.
The test sample was irradiated with a Kr-ion beam of 713
MeV using the RIKEN RILAC+RRC. Total fluence was setto 5×107 ~ 1×108 ions/cm2 at the chip surface. The
operation frequency of the device was set to 0.5, 5, 50 MHz.
The irradiation test was performed under dynamic testconditions.

Fig. 2. SOI device irradiation test result under a dynamic
test condition.
Figure 2 shows the data of error cross section which
depends on operation frequency. The operation frequency
dependence was not observed within the uncertainty of thedata. Note that the value of error cross section is extremely
low, so this error seldom occurs. Based on the evaluation
results of error cross section, the calculated error rate on theorbit can be almost ignored.
The SOI device which was fabricated using the fixed
process condition, indicated excellent radiation tolerance.
We confirmed that the error rate on the orbit of this device
can be almost ignored because the SET error cross section
value is extremely low. Operation frequency dependence ofSET error cross section could not be observed clearly, so wewill evaluate this device with a wider frequency range infuture work.
Reference1) A. Makihara et al., RADECS, Vol.1 (2011), 164-168.

Fig. 1. Cross-sectional structure image of SOI transistor with
unintentionally formed parasitic diode.

䠆1Japan Aerospace Exploration Agency- 209 -