Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT3112-KMC
DC-32Gbps Dual-Channel Linear Signal Level Down-Shifter

Differential input linearity range up to 800mV

Differential gain of approximately 0dB

Exhibits low jitter and limited temperature variation over industrial temperature range

Fabricated in SiGe for high performance, yield, and reliabilityPower consumption: 1.15W

Custom CQFP 24-pin packageveeFully differential output CML-type interface with on-chip single-ended 50Ohm terminations toground

gnd



out1n

Fully differential input CML-type interface with on-chip single-ended 50Ohm terminations to thepositive supply rail

gnd



out1p

High-speed broadband level down-shifter for analog or digital signals

gnd

vcc

gnd

gnd

in1p

out2p

ASNT3112

gnd

gnd

in1n

out2n

gnd

gnd

Rev. 1.2.2

1

gnd

in2n

gnd

in2p

gnd

vcc

veeFebruary 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION

Vcc

Vcc

5050

In1p
In1n5050

Vcc
Vcc

Out1p
Out1nVeeVcc

5050

In2p
In2n5050

Vcc

Out2p
Out2nVeeFig. 1. Functional Block Diagram

The ASNT3112-KMC SiGe IC shown in Fig. 1 provides a voltage shift for high-speed data and clock
signals from levels associated with positive power supplies to levels associated with negative powersupplies.
The part’s inputs support the CML logic interface with on chip 50Ohm termination to gnd and may beused differentially, AC/DC coupled, single-ended, or in any combination. In the first mode, the input
signal’s common mode voltage should comply with the specifications shown in ELECTRICAL
CHARACTERISTICS. In the second mode, the input termination provides the required common mode
voltage automatically. The part’s outputs support the PCML logic interface with on chip 50Ohm
termination to vcc and may be used differentially, AC/DC coupled, single-ended, or in any combination.
The differential DC signaling mode is recommended for optimal performance.
Figures 2, 3 & 4 below demonstrate the chip’s simulated performance.
Rev. 1.2.2

2February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Fig. 2. Simulated DC Amplitude Gain Compression

Fig. 3. Simulated Frequency Gain Compression

Rev. 1.2.2

3February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Fig. 4. Eye Diagrams of 36Gbps PRBS 27-1 Input (Yellow) and Output (Green) Signals

POWER SUPPLY CONFIGURATIONThe chip operates from two independent power supplies related to gnd: negative vee=-3.3V and positivevcc=+3.3V .

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings may cause damage to this product and/or lead toreduced reliability. Functional performance is specified over the recommended operating conditions forpower supply and temperature only. AC and DC device characteristics at or beyond the absolutemaximum ratings are not assumed or implied. All min and max voltage limits are referenced to ground.
Table 1. Absolute Maximum Ratings

Parameter
Min Max Units
Supply Voltage (vee)-3.6
V
Supply Voltage (vcc)+3.6
VPower Consumption
1.2W
RF Input Voltage Swing (SE)1.0
V
Storage Temperature-40 +100ºC
Operational Humidity
1098%
Storage Humidity
1098%

Rev. 1.2.2

4February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

TERMINAL FUNCTIONSTERMINAL

Namevcc
gnd

DESCRIPTIONType
CML Differential inputs with internal SE 50Ohm termination to vcc
input
CML
input
CML Differential outputs with internal SE 50Ohm termination tooutput gnd. Require external SE 50Ohm termination to gnd
CML
outputSupply and Termination Voltages
Description
Pin Number
Positive power supply (+3.3V)
1, 19
0V external ground2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24

vee

Negative power supply (-3.3V)

Name
in1p
in1n
in2p
in2n
out1p
out1n
out2p
out2n

No.
2123
3517
15
1197, 13

ELECTRICAL CHARACTERISTICSPARAMETERTYP MAX UNIT
COMMENTS
General Parameters-3.1-3.3-3.5
V
±6%
vee
0.0
V
External ground
gnd
3.1
3.3
3.5
V±6%
vcc
Ignd
210mA
Ivcc
135mA
Power consumption
1150mW
Junction temperature -40
25125°C
HS Input Data (in1p/in1n, in2p/in2n)
Data rate
DC32
Gbps
Swing
0.05
1.0
V
Differential or SE, p-p
CM Voltage Level
vcc-0.8
vcc
VMust match for both inputs
Linearity range
800mV
Differential
HS Output Data (out1p/out1n, out2p/out2n)
Data rateDC32Gbps
GaindB
Differential input and output
0CM Level-375
mV With external 50Ohm DC termination
Additive Jitter<1ps
Peak-to-peak
Rev. 1.2.2MIN

5February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATIONThe chip die is housed in a custom 24-pin CQFP package shown in Fig. 5. Even though the package
provides a center heat slug located on the back side of the package to be used for heat dissipation,ADSANTEC does NOT recommend for this section to be soldered to the board. If the customer wishes
to solder it, it should be connected to gnd.

Fig. 5. CQFP 24-Pin Package Drawing (All Dimensions in mm)

Rev. 1.2.2

6February 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

The part’s identification label is ASNT3112-KMC. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

REVISION HISTORY
Revision
DateChanges
1.2.2
02-2020 Updated Package Information
1.1.2
07-2019 Updated Letterhead
1.1.1
05-2013 Inserted measured eye diagram
Corrected power consumption specifications
Corrected electrical characteristics
1.0.1
03-2013 First release

Rev. 1.2.2

7February 2020