New Methodologies inSmart Card Security DesignY.GRESSUS
Methodology and Secure ASIC development manager, Bull CP8

Japan Security Conference
Summary Trends
 Opportunities New methodologies
 Concurrent Secure development
 Top down methodology
 Concurrent Secure development Design for reuse Intellectual Property IP development
 IP integration process Formal methods
Page 2© Bull CP8, 2001

 Conclusion

Japan - Security Conference
Trends Productivityz Decrease the development time frame. (“time tomarket”)
z Rapid prototyping for customer demonstrationz Rapid adaptation to customer needs Flexibility and adaptabilityz Generic platform developmentz Multi application support (applications and OSindependence)z Hardware and software independence Openness and Security

Page 3© Bull CP8, 2001

z open and securez Multiple partners for R&D tasks sharing and/or
business modelz Without compromising the security requirements

Japan - Security Conference
Opportunities Design to costz More integrated function for the same price More power and capacity
z 1Mips up to 25-30Mips on less than 25 mm2 designz Increase memory size More integrationz Take into account the technology evolutionz Hardware IP integration (7816,USB, RF…)

 New HW and SW architecture

Page 4© Bull CP8, 2001

z 16/32bit CISC/RISC processorz Security model and Multi-layers architecturez IP based development for both HW and SW

Japan - Security Conference
An example:

ZePlatform from Bull/CP8 :The 32 bit platform

Page 5© Bull CP8, 2001

ZePlatform : software concept and modularity
AppletNativeApplis.

Loader

VM
API

Card
Admin.
sign(key,*in,*out)

I/OManager

Card
Manager

MemoryManager

CryptoServerread(*addr,len)Hardware Drivers
HardwarePage 6© Bull CP8, 2001

Japan - Security Conference
How to develop a modular and secure
platform ?
How to reach the goals of productivity,flexibility, openness and security ?
 Apply a new methodology based on:

Page 7© Bull CP8, 2001

 Concurrent secure development
 Security and CC assurances Intellectual Property (IP), design andevaluation capabilities reuse IP protection and test Integration process mastery Multi developers and /or multi sitemanagement

Japan - Security Conference
Concurrent Secure developmentObjectives

Page 8© Bull CP8, 2001

 Decrease the global development timeframe by concurrent development tasks
 Integrate and assure the security
requirements and deliverables for evaluation
all over the development cycle (AssuranceClass) Firewalling between the layers/modules indevelopment to allow multi sites anddevelopers teams
 Tests development at each stage of theprocess Control throughout development cycle byusing appropriate tools

Japan - Security Conference Concurrent Secure development - Needs
 Structural and modular architecture:z Clear interface communication definitionz IP building processz Designed for re-use

 tools for tasks and configuration
management.
 Development Life cycle support
 Means and tools to ensure the IP
development , test and integration
 Organizational measures to support thedevelopment process .
Page 9© Bull CP8, 2001

Japan - Security Conference A top-down methodology
 From market requirements to the IC
 To guarantee an IC and its SW right the firsttime
 Which takes into account the CC
requirements at the first stage of the design According to the security level objective
 Based on means and tools to support:

Page 10© Bull CP8, 2001z Multiple languages (HDL,C/C++,Java,formal..)z Multiple IP representations levels includingfunctional and security featuresz Formal methodsz Life cycle and project managementz Standard development cyclez Multiple development sites

Japan - Security Conference
CC Assurance Class
correspondence
ACM

ADV

AUT
CAP

TSP
SPM

SCP

FSP
RCR
HLD

ATE
IND
COV
FUN
DPTFUNRCR
LLD

DPTFUN

RCR
IMP

Page 11© Bull CP8, 2001

DPTFUNJapan - Security Conference
Development process: Reduce Time to market
System design
Current
Methodology

HW design
HW debug
SW design
SW debug
Evaluation

Rom CodeProductNewMethodology

System design
HW design
HW debug
SW design50%

SW debug
Evaluation capabilityEvaluation

Page 12© Bull CP8, 2001

Rom CodeproductJapan - Security Conference Design for Re-use New challenge for a design team Implies a robust and correct design based onz Structural approach architecturez Good specification (complete and stable)z Clear interfaces definition for re usability

 Designed for portability
z Use of standard languages (HDL, ANSI-C….)

Page 13© Bull CP8, 2001

 Designed to be verified into a variety ofverification tools. HW platform independent.
 Well verified before integration by using
appropriate test benches Protected for exchange and integration

Japan - Security Conference IP development
 Re use capabilities concepts to be integrated
at the design partitioning stage. Associatedto the modularity
 Support abstractions levels (e.g.CC: ADVclass FSP, HLD,LLD,IMP representations) Unique description for functional andsecurity features for model levels
representation
 Modular test strategy according to the needsof security test (e.g. CC: ATE class)depending on the targeted EAL level
 IP integration process Split in two phases:Page 14© Bull CP8, 2001z Pre integration methods and Final integration

Japan - Security Conference
From the IP’s design to the final
integration for product
IP’s development
IP’s pre integration

IP1IP2Integration

OSLIB

JVM
IP3

Pre-Integration

FinalIntegration

Applets
IPnPage 15© Bull CP8, 2001

IP’s creation, development andmodular tests

Pre Integration
processand test

Time frame

Integration
processand test

Japan - Security Conference IP Pre integrationz Eliminate over the development phase the missinterpretation of the specification and interfaces
definitionz Assure an independent development based on
the interfaces definition and tests exchanges
z Assure a progressive and bottom up integrationof the IP
z Minimize the debug activity by reducing the sizeof the code to be verified
z Reduce the final integration phase by Putting inplace a strategy which allow :{ To test the IP independently from each others{ zero knowledge{ Based on the communication interface
specification
Page 16© Bull CP8, 2001

z Guarantee and protect the IP integrity

Japan - Security Conference
Formal methods
 To be compliant with the Assurance Level 5
requirements and more.
 Use of the most advanced techniques of semi
formal and formal methods:z Semi-formal/formal methods choice (UML, B ….)
z Define and use a dedicated language (Java, Coq…)z Define a translation methods from the Functional
Security requirements (informal information's) tothe TSP model (formal)z Coherency proof Started earlier at the development phase
Page 17© Bull CP8, 2001

Japan - Security Conference
Security Policy formalization - Methodology overview
Informal security
policy (textual)

Formalization

Logicalexpressions
modelizationtranslation

FormalProperties (Coq)
TSP model

Coherencyproof

AbstractMachine
FSP model (Coq)
Refining & Proof

Common Criteria references:
TSP model: TOE Security Policy model
FSP model: Functional Specification model
HDL model: High Level Design model
Page 18© Bull CP8, 2001

Formal HLD
Model (Coq)Semi Formal HLD
Modeltranslation

Japan - Security ConferenceConclusion New methods become a reality to Reduce the development time Assure the mandatory correspondence
between the standard development flow and
the CC requirements for evaluation without
extra effort
 Guarantee a right design the first time Allow the co-design activity
 Security level guarantee by formal methods.

Page 19© Bull CP8, 2001

 These methods have been specified andset up in the European collaborative
Project: MASSC (A MEDEA initiative) andnow applied for the ZePlatform dev.