High-Voltage Isolated Square Waveform Converterwith DC-Offset Voltage for Physical Vapor
Deposition (PVD) Applications
Koki Yamamoto
Dept. of Electrical, Electronics, and Information Engineering
Nagaoka University of Technology
Nagaoka, Japan
s213187@stn.nagaokaut.ac.jp

Takashi Ohno
Dept. of Science of Technology Innovation
Nagaoka University of Technology
Nagaoka, Japans225058@stn.nagaokaut.ac.jp

Hiroki Watanabe
Dept. of Electrical, Electronics, and Information Engineering
Nagaoka University of Technology
Nagaoka, Japanhwatanabe@vos.nagaokaut.ac.jp

Jun-ichi Itoh
Dept. of Science of Technology Innovation
Nagaoka University of Technology
Nagaoka, Japan
itoh@vos.nagaokaut.ac.jp

Abstract— This paper proposes two isolated asymmetricrectangular waveform converters for high voltage pulse voltage
generation from 100 V to -2 kV in surface coating by the physicalvapor deposition (PVD) method. The PVD method is a surface
coating method using chemical reactions of materials such asargon gas. The surface shape of the target sample is regulatedby the external square waveform converter, which requires thecapability of variable duty control and variable amplitudeoperation in order to manage the coating performance. This
paper presents details of a circuit configuration that enables
variable duty control from 0 - 100% and variable amplitudeoperation to 100 V. Furthermore, the load model in the PVD
method is also shown to clarify the behavior of the square
waveform converter. The experimental results show that theswitching duty is variable by 50%, 20% and 80% with thepositive voltage amplitude adjusted by 25% of the peak voltage.

bipolar high-voltage converter is proposed in order to reducethe voltage applied to switching devices. The proposed
converter is configured with two bidirectional DC-DC boost
converters. The converter has a boost function by charge anddischarge of two inductors to generate high-voltage bipolar
output pulses from a low input DC voltage. However, a highwithstand voltage is required for two of the four switching
devices used in this converter. Furthermore, the output
bipolar voltage is limited to a 50% duty cycle.

Keywords— Isolated square waveform converter, Thin film
coating equipment, PVD method, High voltage pulse generation.

I. INTRODUCTION
A thin film coating technology has been widely used to
improve the wear resistance of metal components, such as
cutting tools. The coating method is classified into two
categories: chemical vapor deposition (CVD) and physicalvapor deposition (PVD) methods. The CVD method ischaracterized by a high deposition rate, limited gas variety,and high temperatures in the deposition process. On the other
hand, the PVD method is widely used because of attractive
advantages, e.g., 1) variety of thin-film materials, 2) lowtemperature deposition, and 3) high thin-film adhesion. The
PVD method requires the external bipolar voltage source
during the surface coating process in order to adsorb thecoating material to the target sample [1]-[2]. This voltage
source requires square waves of asymmetrical high-voltage,
pulse width adjustment an operating frequency of 300 kHz or
higher.
The conventional circuit provides asymmetrical highvoltage square waves by connecting two converters withdifferent output voltage polarities. However, this circuit
requires two DC input voltages of several kilovolts andseveral hundred volts. Besides, the conventional circuits
require the switching devices with high-withstand voltages
operating at several kilovolts. In [3], a boost inverter-based

XXX-X-XXXX-XXXX-X/XX/$XX.00 ©20XX IEEE

A bipolar pulse generator based on a Marx generator is
proposed in order to control the pulse width with several
switching devices and capacitors [4]-[6]. The Marx generator
outputs a bipolar voltage with an H-bridge circuit connected
in series on the load side. Furthermore, this circuit generates
bipolar voltage without the need for an H-bridge by using adouble power charging Marx generator or a cascade of
positive and negative Marx generators. However, this circuit
is a high cost because it requires a large number of highwithstand voltage components.
A half-bridge modular multilevel converter (HB-MMC)
is proposed in order to reduce the voltage per switching
device [7]-[12]. The HB-MMC arm is configured withseveral half-bridge sub-modules connected in series. The
half-bridge submodule is configured with two switching
devices and a capacitor. This topology is composed of twoarms that charge the capacitors in parallel. The bipolar
voltage is generated by controlling the discharge sequence.
Furthermore, the duty cycle of the output bipolar voltage isvaried by setting the switching sequence of each arm.
However, the HB-MMC requires more complex control inorder to maintain a balanced voltage across the capacitors.
This paper proposes an isolated asymmetrical square
waveform converter configured with the two isolated
converters to achieve voltage control, pulse width control,high switching frequency, and low input voltage. The
originality of this paper is that the high-withstand switching
device is not needed on the output side because the squarewave voltage is boosted by the transformer. Furthermore, theproposed converter achieves variable duty cycle control andoutput voltage amplitude adjustment by combining the pulse
generator circuit and a DC offset circuit. Experimental resultsfrom a prototype outputting a pulse voltage range of 25 V to

minas several hundred voltages demonstrated variable duty
cycle control and amplitude adjustment functions.
This paper is organized as follows. Section II introduces
the circuit configuration of the square waveform converterand basic operation waveform. Section III describes thecontrol method of the proposed circuit. Section IV explains
the load estimation method of the coating equipment. Section
V presents experimental results to verify the validity of the
proposed circuit.

Pulse generator circuit

S1

Vin

S2

Dr2

Dr2

II. CIRCUIT CONFIGURATION

C1

Fig. 1 shows the circuit configuration of the proposedsquare waveform converter. This circuit is configured with apulse generator circuit and a DC offset circuit. The pulse
generator circuit provides the high-frequency square wave
voltage with an amplitude from 0 V to -2 kV. The transformerof the pulse generator circuit has a three-winding
configuration with one input and two outputs. The input
voltage vLm1 of the three-winding transformer is a square wave
voltage with only AC components after the DC component
has been blocked by the blocking capacitor Cblk. The output
voltage vLm2 of the three-winding transformer is rectified to a
DC voltage by diode Dr1 and smooth capacitor Cs1. The output
voltage vLm3 of the three-winding transformer is an AC voltage
with the primary transformer Lm1 voltage as higher by the turnratio. The pulse generator output voltage vsq is the sum of vLm2
and vLm3. The DC offset circuit provides DC voltage with amaximum voltage of 100 V. Furthermore, the power flow in
the DC offset circuit changes depending on the polarity of vsq.
As vsq outputs a positive voltage, a current flows through theload because the capacitor C3 discharges electric charge. As
vsq outputs a negative voltage, a current flows to the input sidethrough diode Dr2 when the capacitor C3 stores an electriccharge. Thus, asymmetric square wave voltages are applied to
the load from a maximum pulse voltage of 100 V to -2 kV.
Besides, the diode clamp snubber circuit is applied on thesecondary side in order to avoid resonance between the wiring
inductance and the load capacitance component.

C2

Fig. 2 shows the switching pattern of the pulse generator
circuit at a 50% duty cycle. The pulse generator circuit
operates in two operating modes. In mode I, the DC voltageof the load is supplied from the DC offset circuit. The fullbridge inverter circuit applies a positive voltage to the primaryside of the transformer. In this case, the current flows indifferent directions in the two windings on the output side oftransformer Tr.1. Therefore, the output transformer secondary
voltage vsq is 0 V because the transformer secondary voltagesof vLm2 and vLm3 are canceled out. The DC voltage of the DC
offset circuit is applied to the load because the pulse generator
circuit and the DC offset circuit are connected in series. In
mode II, A negative voltage is applied to the transformer
primary side by a full-bridge inverter, which applied anegative voltage of several kilovolts peak to the load. The
winding Lm2 on the output side of the transformer Tr.1 does not
output voltage because a reverse bias is applied to the rectifier
diode Dr1. The output voltage is the sum of the smoothing
capacitor voltage vCs1 of the rectifier circuit and the secondarytransformer output voltage vLm3.
Fig. 3 shows the switching pattern of the DC offset circuit
at a 50% duty cycle. The DC offset circuit operates in twomodes, as the pulse generator circuit. In mode I in Fig. 3, thecurrent iL1 of inductor L1 increases linearly because half of theDC voltage is output on the secondary side of transformer Tr.2.

Clamp
snubber
Lwire iout
Tr.1
Cs1
S3 L
Lm2 vLm2Dr1 VCs1 C3 Dsn
le1+
Rsn Csn Coating vout
iTr.1
Lm1
iDr1
load
vsq
Lm3 vLm3
S4 Cblk n :n :n
1 2 3
i
Vdc

L1

S5

Lle4 Tr.2

S6

vLm4
Lm4
n1´: n2´ S7

L2

iL1

ICs2

iL2
S8

Cdc

VCdc

DC offset circuit
Fig. 1 Circuit configuration of proposed square waveform converter.
Swiching duty D1
S1 S4
S2 S3

ON
ON
OFF

OFF
ON

ON
OFF

OFF
ON
(n2/n1)Vin

vLm2(vLm3)-(n2/n1)Vin(n2/n1)Vin

VCs1
vsq

-(2n2/n1)Vin
Vdc
Vdc

VCdc
(VC3)
vout

-(2n2/n1)Vin
iDr1
iDr2
iout

MODE

I

Ⅱ

I

Ⅱ

I

Fig. 2 Switching waveforms during square wave voltage output forpulse generator.

Swiching duty D2
S5 S8
S6 S7
vLm4
VCdc

ON
ON
OFF

OFF
ON

ON
OFF

OFF
ON

Vin/2
-Vin/2
Vdc

iL1

iL2
Ⅱ
I
MODE
I
Ⅱ
I
Fig. 3 Switching waveforms during DC offset voltage output for DC
offset circuit.

In mode II of Fig. 3, the current iL2 of inductor L2 increases
linearly because negative voltage is output on the secondaryside of transformer Tr.2. As a result, the output current ICs2 ofthe DC offset circuit is twice the value of the inductor currents
iL1 and iL2. Thus, the output voltage VCs2 is half the rms value
Vin / 2 for the secondary voltage vLm4 of transformer Tr.2.
III. CONTROL METHOD OF THE PROPOSED CIRCUIT
Fig. 4 shows the control block diagram of the proposed
circuit. The two isolated converters each operate in an openloop control. The pulse width of the square wave is controlledfrom 0% to 100% by varying D1 from 0 to 1.0. The switching
duty D2 varies the duty cycle from S5 to S8 of the DC offset

circuit. The switching duty D2 is required in order to vary theDC voltage at the output voltage Vdc of the DC offset circuitin the range of 0 to 100 V.
Fig. 5 shows the switching pattern when the duty cycle D1of the pulse generator circuit is varied. The secondarytransformer output voltage vLm2 has a voltage waveform with
AC components only, because the DC components are cut off
by the blocking capacitor Cblk. The relationship between the
DC voltage Vblk of Cblk and the duty cycle D1 is expressed asn V (1 − 2D1 ).................................................... (1),Vblk = 2 inn1

Output pulse voltage control
Swiching duty D1
Duty

Fig. 5(a) shows the voltage waveforms when the duty
cycle D1 is less than 50%. In this case, the average AC voltage
Vacavg increases in the positive direction at the secondary
output voltage vLm2 of transformer Tr.1. Furthermore, the DC
voltage Vblk is added to the peak voltage Vacpeak and the bottom
voltage Vacbot at vLm2. Fig. 5(b) shows the voltage waveforms
when the duty cycle D1 exceeds 50%. In this case, the average
AC voltage Vacavg increases in the negative direction at thesecondary output voltage vLm2 of transformer Tr.1. Furthermore,
the DC voltage Vblk reduces the peak voltage Vacpeak and thebottom voltage Vacbot in vLm2. Moreover, the capacitor voltage
VCs1 after half-wave rectification of vLm2 is added to thesecondary voltage vLm3 of the transformer Tr.1. As a result, thevoltage amplitude Vp-p has a negative voltage range below 0 V.
Therefore, the termination voltage vsq of the pulse generator
circuit outputs a high-voltage pulse with a wide duty cycle
range.

0

Carrier
DC offset voltage control

Swiching duty D2(D2 0.5)

Vdc *

Vdc = D2 (1 − D2 )Vin .................................................... (2),where D2 is the duty cycle of the DC offset circuit.
Fig. 7 shows the principle of operation of an RCD clamp
snubber [13]. The RCD clamp snubber suppresses resonancecaused by the capacitive component of the load and theinductance of the wiring. The snubber capacitor Csn absorbs
the ringing energy in the load voltage. The snubber resistor
Rsn consumes the energy charged in Csn. The snubber resistor
Rsn is calculated from the relationship between the discharge
loss of Csn and the resonance bottom of the load voltage
Vout_min expressed as

Rsn =(Vout _ min )2
PRs...................................................... (3),

S5，S8
S6，S7

Vin

1

CarrierFig. 4 Control block diagram of proposed square waveform converter.
vLm3Ton1

vLm3

Vac peak+Vblk
Vac avg

Vac peak+Vblk

Ton1

Vp-p
Vac bot +Vblk

Vac avg
Vac bot +Vblk
VCdc(VC3)

VCdc(VC3)
Vac peak+Vblk

Vac peak+Vblk

vsq

vsq
Vp-p

S1 S4

S1 S4

S2 S3

S2 S3

(a) Duty D1 < 50%(b) Duty D1 > 50%
Fig. 5 Switching patterns of pulse generator circuit with variable Duty.
vLm4

Fig. 6 shows the switching pattern when the duty cycle D2of the DC offset circuit is less than 50%. The average value ofthe AC voltage Vacavg increases in the positive direction
because the voltage-time product relationship changes
depending on duty cycle D2 in the half-bridge inverter on the
primary side of transformer Tr.2. Therefore, the relationshipbetween the voltage division ratio of the capacitor voltages
VC1 and VC2, and the current ratio of the inductor currents iL1
and iL2 changes depending on the duty cycle D2. The
relationship between the DC output voltage Vdc and duty cycle
D2 is expressed as

S2，S3

1

0

where Vin is the input voltage, n1 is the number of primary
turns of transformer Tr.1 and n2 is the number of secondary
turns of transformer Tr.1.

S1，S4(0 – 1.0)

Ton2
VCs1
Vac avg
VCs2

VCdc(VC3)
Vdc
iL1

iL2

S5 S8

S6 S7

Fig. 6 Switching patterns of DC offset circuit with variable Duty
(Duty<50%).

where Vout_min is the resonance bottom value of the load
voltage, and PRs is the power dissipation in the snubber
resistor.
The snubber capacitor Csn is calculated from therelationship between Rsn and the switching period. it isexpressed as

Csn

Tsw1
.............................................................(4),
Rsnwhere Tsw1 is the switching period of the pulse generator
circuit.

IV. PARAMETER ESTIMATION OF COATING LOAD MODEL
A. Equivalent circuit model and parameter
identification method
The proposed circuit is required to output a highfrequency bipolar voltage without ringing during transientstates. However, the coating equipment behavior is unclear
because of its non-linear characteristics. Thus, it is necessary
to clarify the load model in order to analyze the operation of
the proposed circuit. This chapter estimates the load
parameters of the coating equipment using experimental
waveforms.
Fig. 8 shows the operating waveforms of the coating
equipment applying the proposed circuit. The coating load isanalyzed from five operation modes.
In mode I, the load voltage vout rises before S1 is turned on
because the energy stored in the leakage inductance Lle4 isdischarged by the flow of negative current. In mode II, theload voltage rises sharply to a positive voltage as the load
current direction becomes positive because capacitor Cs1
discharges its electric charge through the freewheeling diodesof switches S1 and S4. Thus, the load voltage vout in this mode
becomes a positive voltage because the power is regenerated
from the secondary side to the primary side of transformer
Tr.1. In mode III, the load current waveform transiently rises
as current flows through the RLC series circuit caused bytransformer leakage inductance, load resistance components,and smoothing capacitors. In mode IV, the load current drops
sharply in the negative direction while the load voltage drops
slightly from its peak value Vpeak because of the energy stored
in the leakage inductance is discharged during the dead time
Tdead. In mode V, the load voltage vout and the load current
iout are resonant due to the leakage inductance, the wiring
inductance, and the capacitive component of the coating
equipment.
Fig. 9 is the equivalent circuit of the coating equipment
based on Fig. 8 in the state of plasma generation during thesurface coating of the target sample. The equivalent circuit
becomes an RLC circuit including the leakage inductance Lle,
the wiring inductance Lwire, and the smoothing capacitor Cs1.
The equivalent circuit for the plasma-generated state behavesas the positive charge layer (ion sheath) characteristics inside
the equipment for diodes Dout1 and Dout2. According to Fig. 9,
the current flows in the RLC series circuit with Rout1, Lle, Lwire
and Cs1 when a positive voltage is applied. In mode III in Fig.
8, Rout1 is calculated by the time constants of Rout1 and Lle andLwire expressed as(L + L )Rout1 = le wire ....................................................... (5),Tsw1=1/fsw1
vgs1

S1 S4
S2 S3 vgs2
vout
0

ON
OFF

OFF

OFF
ON

-(2N2/N1)Vout
VCsn

Vout_min
vCsn

VCsn

0

Fig. 7 Operating Principle of RCD clamp snubber during switching.

Swiching duty D1
S1 S4
0
S2 S3
0

Dead time Tde ad

ON

OFF

OFF

ON

vout
0

Vpe ak

iout

a1

a2

0

MODE V I Ⅱ

Ⅲ

Ⅳ

IⅡ

V

Fig. 8 Switching pattern when the proposed circuit is applied to thecoating load.

Lle

iout

Lwire
Dout1 Dout2

Tr.1
vout
n1:n2
Cs1



where Rout1 is the resistance component when a positive
voltage is applied, and τ is the time constant of the series
circuit of Rout1, Lle, and Lwire. According to Fig. 9, the current
flows through the RC circuit in parallel with the L in series
when a negative voltage is applied. In mode V of Fig.8, Lle,
Lwire, and the load capacitance component Cout resonate. Thus,
Cout is expressed from the resonance frequency expression as1...................................... (6),Cout =
2
2
4 f rin ( Lle + Lwire )where frin is the resonance frequency of Lle, Lwire, and Cout.
The resistance component Rout2 when a negative voltage
is applied is expressed by (7) from the relationship between
the transfer function of the circuit by L in series and RC inparallel.

ON

OFF
ON

Rout1

Rout2 Cout

VCs1
Coating load modelFig. 9 Equivalent circuit model for coating load with square wave
voltage applied.

Rout 2 =1
2

( Lle + Lwire ) .........................................(7),Cout

The damping coefficient ζ is expressed asln(a1 / a2 ) =.........................................(8),2
4 2 + ln(a1 / a2 )
where a1 is the resonance bottom value of vout in mode V of
Fig.8， and a2 is the second resonance bottom value of vout inmode V of Fig.8.

Vin

40 V

n1:n2:n3

6:10:10fsw1

50 kHzfrinτ

833 kHz6.30 µsLle

6.52 μH

Lwire

1.00 μF

Rout1

1.19 Ω

Switching Frequency(Pulse generator circuit)
Resonance frequency
Time constant
Leakage inductor(Pulse generator circuit)
Wiring inductanceResistance component(Positive pulse voltage applied)
Capacitance component
Resistance component(nagative pulse voltage applied)

B.

Cout

4.85 nF

Rout2

54.7 Ω

Parameter Identification Result

Table Ⅰ shows the parameters in the simulation using theload model. The simulation parameters shown in Table Ⅰ are
set to low-voltage and low-frequency conditions to equal theexperimental parameters in the coating load.
Fig. 10 shows the operating waveforms compared to theexperimental and simulation results. According to the turnoff timing in Fig. 10., the load voltage Vout resonates due tothe transformer leakage inductance Lle, the wiring inductance
Lwire, and the load capacitance component Cout because theresistance component Rout2 is small, which has little damping
effect on the LC resonance. The load voltage vout at turn-on
timing shown in Fig. 10 does not resonate because the current
does not flow through the capacitive component Cout of theload as shown in Fig. 9. Table II shows the results ofcomparing the operating waveforms for ringing amplitude
and period. The load voltage waveforms in Table II show thatthe ringing amplitude ΔV has an error of 7.62% and theringing period Δt1 has an error of 8.21%, which are within
10% of each other. Furthermore, the load current waveforms
in Table II show that the error in the ringing amplitude ΔI is
7.96% and the error in the ringing period Δt2 is 1.34%, which
are within 10% of each other. Thus, (5)-(8) applied to theparameter identification are valid.
V. EXPERIMENTAL RESULTS
Table Ⅲ shows the experimental conditions for the
proposed circuit. The switching frequency of the pulse
generator circuit is set to 300 kHz, which is required for thecoating equipment. The number of winding turns of the threewinding transformer is set to n1:3 turns, n2:8 turns, and n3:8
turns respectively to output a negative voltage of 2 kV at 400
V input voltage. The basic operation of the proposed circuit
is verified using a resistance load. Note that the RCD clamp
snubber circuit is not applied because the experimental load
is an inductive load that does not resonate.
Fig.11 shows the operating waveforms when the duty
cycle D1 of the primary side H-bridge of the pulse generator
circuit is set to 50%, 20%, and 80%. Fig. 11(a) shows theasymmetrical square wave voltage at a switching duty D1 of
0.5. The DC offset voltage of output voltage VCs2 is set to 25
V. This corresponds to the DC voltage Vdc calculated bysubstituting the experimental conditions of an input voltageof 100 V and a duty cycle D2 of 0.5 into (2). The ringing
occurs during the transient phenomenon of the load voltage.
The ringing of the load voltage occurs from resonance caused

Experimental value
Simulation valueTurn-ontiming0
Load voltage[V]Input voltage
Number of winding turns

FOR

-50

Dt1

-100

Dt1

-150

DV DV

Turn-offtiming-200
4Load current[A]TABLE Ⅰ. ELEMENTPARAMETERSUSEDIDENTIFICATION OF COATING LOAD PARAMETERS
SymbolElement
Value

a2

Dt2
Dt2

2
0

DI

-2
-4

a1

DI
10

20

30

40 [μs]

34

36

38

Fig. 10 Comparison of experimental results with coating load andsimulation results with the equivalent circuit model.
TABLE Ⅱ.
COMPARISON OF ERROR RATESBETWEEN
EXPERIMENTAL
RESULTSAND
EQUIVALENT CIRCUIT MODEL SIMULATION RESULTS
Experimental Simulation
value
value

Error rate

Name

SynbolLoad Voltage
ringing amplitude
Load voltage
ringing cycle
Load current
ringing amplitude

ΔV

45.0 V41.5 V

7.62%

Δt1

1.30 μs

1.28 μs8.21%

ΔI1.80 A

1.94 A

7.96%

Load current
ringing cycle

Δt2

1.30 μs

1.28 μs

1.34 %TABLE Ⅲ.
EXPERIMENTAL PARAMETERS WITHRESISTIVE LOADS OF THE PROPOSED CIRCUIT
PROTOTYPE
Element

SymbolValue

Input voltage
Swiching frequency(Pulse generator circuit)
Swiching frequency(DC offset circuit)
Dead time
Number of winding turns(Pulse generator circuit)
Magnetizing inductor(Pulse generator circuit)
Leakage inductor(Pulse generator circuit)
Number of winding turns(DC offset circuit)
Magnetizing inductor(DC offset circuit)
Leakage inductor(DC offset circuit)
Boost inductor
DC capacitor
Output side capacitor
Blocking capacitor
Load resistanceVinfsw_sq

100 V
300 kHz

fsw_dc100 kHzTde ad100 nsn1:n2:n3

3:8:8

Lm1

278 µH

Lle1

1.47 µHn1´:n2´

13.5:13.5

Lm2

875 µH

Lle2
L1，L2
C1，C2
C3
Cblk
Rout

2.19 µH
100 µH
50 µF
20 µF
25 µF
200

by the leakage inductance and stray capacitance in the threewinding transformer. The resonant frequency of the ringing
agrees with the resonant frequency of the three-windingtransformer due to its leakage inductance of 2.22 µH andstray capacitance of 183 pF. Fig.11(b) shows theasymmetrical square wave voltage at a switching duty D1 of
0.2. As shown in Fig.11(b), the ringing of the load voltage
occurs due to resonance caused by the leakage inductance andstray capacitance of the three-winding transformers, the sameas in Fig.11(a). However, the load voltage vout shown in Fig.
11(b) has a larger resonance amplitude at turn-on or turn-off
than in Fig. 11(a) because the current rises sharply as the turnon period becomes short. Fig.11(c) shows the asymmetricalsquare wave voltage at a switching duty D1 of 0.8. As shownin Fig.11(c), the resonance effect is small due to leakage
inductance and stray capacitance because of the slow rise incurrent caused by the long turn-on period.
Fig. 12 shows the operating waveforms when the duty D2of the switches S5-S8 in the DC offset circuit is changed to10%. Fig. 12. shows that setting D2 of 0.1 results in a Vdc of
10 V. The Vdc value of 9.0 V calculated by substituting theexperimental conditions into (2) agrees with the measured
value within an error of about 10%. Comparing the load
voltage Vout in Fig. 11(a) and Fig. 12, the effectiveness of thevariable amplitude function was confirmed as the positive
pulse voltage amplitude reduced from 25 V to 10 V.
VI. CONCLUSION
This paper proposed an isolated square waveformconverter for PVD applications. The proposed circuitachieves variable duty and pulses positive voltage amplitude
adjustment functions by combining two isolated converters.
In addition, the load model parameters were identified inorder to clarify the nonlinear load behavior. As a result ofparameter identification, the amplitude and period of theringing generated in the load voltage and load current wereagreed within an error of 10%. The experimental results showthat the adjustment functions of the pulse width and offset
voltage of the asymmetrical square wave voltages are
obtained by changing switching duty D1 and D2, respectively.
Future work includes verifying operation when a PVD
application is connected as a load.
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pulse-generator with sequential charging for water treatment
applications", IEEE Trans. Ind. Electron., vol. 63, no. 12, pp. 78987907, Dec. 2016.

Duty=50%Square waveform voltage vsq[400 V/div][1.00 µs/ div]0

DC offs et voltage VCs 2[25 V/div]0

Load voltage vo ut[400 V/ div]

[50 V/div]

25 V

Pulse voltage output
with Duty=50%00Load current iout [2.00 A/div](a) Operating waveform of the proposed circuit.
Vin＝100 V，Rout=200 Ω，D1=50%，D2＝50%
S1_Drain-Source voltage[100 V/div]0[1.00 µs/div]
Duty=20%

Transformer voltage(secondary s ide)
vtr .1 [200 V/div]00Load voltage vo ut[200 V/div]
Pulse voltage output
with Duty=20%

0Transformer current(primary side)[20.0 A/div](b) Operating waveform of the proposed circuit.
Vin＝100 V，Rout=200 Ω，D1=20%，D2＝50%
S1_Drain-Source voltage[100 V/div][1.00 µs/div]

Duty=80%00Transformer voltage(secondary s ide)
vtr .1 [400 V/div]

Pulse voltage output
with Duty=80%0Load voltage vout[400 V/div]
0
Transformer current(primary side)[10.0 A/div](c) Operating waveform of the proposed circuit.
Vin＝100 V，Rout=200 Ω，D1=80%，D2＝50%
Fig. 11 Operating waveform for variable duty control.
Square waveform voltage vsq[400 V/div]

Duty=50%[1.00 µs/div]0

DC offs et vol tage VCs 2[10 V/div]0
Load voltage vout [400 V/div]

0

Pulse voltage output
with Duty=50%[50 V/div]

10 V

0Load current iout [2.00 A/ div]

Vin＝100 V，Rout=200 Ω，D1=50%，D2＝10%
Fig. 12 Operating waveform for variable amplitude control.
[10] L. L. Rocha, J. F. Silva and L. M. Redondo, "Multilevel high-voltage
pulse generation based on a new modular solid-state switch", IEEE
Trans. Plasma Sci., vol. 42, no. 10, pp. 2956-2961, Oct. 2014.
[11] L. L. Rocha, J. F. Silva and L. M. Redondo, "Multilevel high-voltage
pulse generation based on a new modular solid-state switch", IEEE
Trans. Plasma Sci., vol. 42, no. 10, pp. 2956-2961, Oct. 2014.
[12] Yingjian Zhuge, Junrui Liang, Minfan Fu, Teng Long, Haoyu Wang,"Comprehensive Overview of Power Electronics Intensive Solutionsfor High-Voltage Pulse Generators", IEEE Open Journal of PowerElectronics, vol.5, pp.1-20, 2024.
[13] A. Hren, J. Korelic and M. Milanovic, "RC-RCD clamp circuit forringing losses reduction in a flyback converter", IEEE Transactions on
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2006.