ZVRT Capability of Single-phase Grid-connected Inverterwith High-speed Gate-block and Minimized LCL Filter Design
Satoshi Nagai, Keisuke Kusaka and Jun-ichi ItohStudent member, IEEE, Member, IEEE, Senior member, IEEE,
Nagaoka University of Technology, Japan
1603-1, Kamitomioka-machi
Nagaoka, Niigata, Japansatoshi_nagai@stn.nagaokaut.ac.jp; kusaka@vos.nagaokaut.ac.jp; itoh@vos.nagaokaut.ac.jp
Abstract -- This paper proposes a Zero-Voltage Ride-Through(ZVRT) method and an LCL filter design method to meet theFault Ride-Through (FRT) requirements for a single-phase gridconnected inverter with a minimized LCL filter. A high inverteroutput-current overshoot occurs at a grid voltage sag and a gridvoltage recovery, when a low-inductance LCL filter design isemployed in order to minimize the filter volume. In order tosuppress the current overshoot, a high-speed gate-block
operation and the design method of the minimized LCL filter areproposed. In particular, the filter design considers the delay timein the gate-block operation in order to clarify the reduction
limitation of the inductance in the LCL filter. As a result, themaximum inverter-output-current overshoot is suppressed to146% by the high-speed gate-block operation and the designed
LCL filter, where the impedances of an interconnected inductor
and a filter inductor are 1.0% and 0.78% of the inverter
normalized impedance, respectively. Therefore, it is possible tomeet the FRT requirements with the proposed ZVRT method
even with the minimized LCL filter.
Index Terms—Grid-connected inverter, Zero-voltage ridethrough, Minimized LCL filter, High-speed gate-block, Output
current overshootI.

INTRODUCTION

In recent years, grid-connected inverters in photovoltaic,
fuel cell, and wind turbine systems, have been actively
studied for energy saving [1]-[3]. The grid-connected inverter
is required to meet the Fault-Ride-Through (FRT)
requirements of the grid code [4]-[9]. During a grid fault suchas a short circuit occurs, the inverter has to continue to flow
the current into the grid in order to assist the recovery of thegrid. Moreover, at the grid voltage recovery, the fluctuationof the grid voltage might cause the current overshoot. In orderto prevent the overcurrent flowing to the grid and load, thetransitional maximum inverter output current is required toless than 150%, if the rated inverter output current peak value
is considered as 100% [10]. Generally, high-inductance filters,e.g. L or LC filters, can simply meet the FRT requirements.
For instance, the interconnected inductor impedance isdesigned at 2.1% of the inverter impedance to carry out the
FRT operation in [4]. However, such high-inductance filters
lead to a large filter volume.
The inverter is desired to have a small volume to increase
power density [11]-[12]. In particular, the interconnectedinductor that occupies a majority of the inverter size is highly
demanded to reduce the size. By reducing the inductance, it ispossible to reduce the volume of the inductor. A highswitching frequency with SiC or GaN devices is applied in theterm of a same current ripple in order to reduce theinductance of the interconnected inductor. Moreover, in order
to effectively reduce the current ripple components of theinverter output current, the grid-side inductor is employed inorder to form the LCL filter which has a high attenuation rate[13]-[14].
Figure 1 shows a circuit configuration of a single-phasegrid-connected inverter with an LCL filter, where L1 is theinterconnected inductor, Lf is the filter inductor, Cf is the filter
capacitor, S1 to S4 are switching devices, and vconv is theinverter output voltage. In this paper, an H-bridge singlephase two-level inverter is employed due to its simplicity.
The inverter output current overshoot significantly increases
due to the high grid voltage fluctuation at grid short-circuit
faults when the inductance of the filter is reduced with the
LCL filter design; consequently, the inverter is stopped by theover current protection and disconnected from the grid.
Therefore, if the inductance is reduced by increasing theswitching frequency when considering only the suppression
for the output current harmonics in the grid code, it is
impossible to suppress the inverter output current overshootdue to the low inductance, i.e. the violation of the FRT
requirements.
In [4], the FRT operation with the constant peak current
strategy has been demonstrated in the experiment; however,
the method of [4] does not consider the Zero-Voltage RideThrough (ZVRT) operation and the low-inductance filter. In
S1

Vdc

S3
iL1

iLf

L1

Lf

vconv
S2

Cf

vc

vac

S4
iL1detvcdet

vacdetFig. 1. Single phase inverter circuit with LCL filter. The interconnectedinductor L1 and the filter inductor Lf are reduced by increasing theswitching frequency.

[6], the FRT operation with the voltage amplitude and theoutput power control has been proposed. Nevertheless, thismethod introduces a long delay time for the control. Thus, thehigh inverter-output-current overshoot occurs with the lowinductance filter. In [9], the FRT operation with the peakvalue control method has been proposed to detect the voltage
fault. In particular, the detection value of the grid voltage isused to suppress the current overshoot. However, the highinverter-output-current overshoot still occurs due to the long
delay time of the computation. In [15], the ZVRT operation
for minimized LC filter with a momentary high-speed gateblock method is proposed. The gate-block operation is carriedout when the inverter output current reaches a current
threshold. However, the ZVRT operation has been notconsidered for the minimized LCL filter. Thus, it is necessary
to achieve the ZVRT operation with the minimized LCL filter.
In this paper, the ZVRT operation method meeting the
FRT requirements is proposed with a high-speed gate-block
operation and a design method of the LCL filter. Moreover,the suppression of the maximum inverter output current
overshoot at the voltage sag is aimed to less than 150%, if the
rated inverter output current peak value is considered as
100%, in order to meet the FRT requirements. In [16], theZVRT operation with the minimized LCL filter isdemonstrated when the voltage drop and recovery occur at thevoltage phase of 90 degree. In this paper, additional
experimental results with a Low-Voltage Ride-Through(LVRT) operation and when the voltage drop and recovery
occur at different voltage phase are demonstrated. The
original idea of this paper is follow; the high-speed gate-block
operation that is reduced the detection and the control delay
time is applied with the minimized LCL filter to suppress theinverter output current overshoot. The gate-block operation iscarried out when the grid voltage fluctuation such as voltage
drop or recovery is detected. In addition, in order to suppress
the output current overshoot and meet the FRT requirements,
it is necessary to design the LCL filter considering the delay
time of the grid fault detection. The LCL filter is designed byderiving the equation of the inverter output current at the gridvoltage recovery with the gate-block operation. This ensuresthat the inverter output current overshoot which includes theresonance current of the grid-side LC filter is less than 150%of the rated output current peak at the voltage recovery. TheZVRT operation meeting FRT requirements is demonstrated
with a 1-kW prototype.
II. ZERO-VOLTAGE RIDE-THROUGH METHOD FORMINIMIZED-LCL-FILTER GRID-CONNECTED INVERTERA.

Conventional FRT Method
In order to minimize the LCL filter, the inductance andcapacitance are reduced by increasing the switchingfrequency of the inverter. Due to the reduction of theinductance in the LCL filter, the high inverter-output-current
overshoot occurs at the grid voltage drop and recovery.

DSP
vacdet
0


2

PLL
MUX

θ'

θ

+ +
vfrt

θfrt

MUX
Normal FRT
operation
0
1

θfrt

vfrt

 2

0

VFRT_thvacdet

HPF

1



u2
u

+
vac_max

+

+
-

vfrt

2

Fig. 2. Reactive current control method for FRT operation. Whenvoltage sag occurs, the phase ' is advanced by /2 from .

FRT Control

DSP

sin(θ' )

iL1*

+
-

PI

iL1detsign

Controller
vcdet
+ +

+

Main circuit
+ v
vdead
+ vdis c

1+ V dcVdc Td fsw

e

Vdc

+ -

1
sL1

iL1

 sTdelay

Fig. 3. Control block diagram of conventional FRT operation. In theconventional method, the current controller is implemented by
DSP.

Consequently, the grid-connected inverter is stopped by theover current protection, and cannot continue the operation
with the reduced inductance.
Figure 2 shows a reactive current control method for an
FRT operation. The grid voltage phase  is locked by phaselocked-loop (PLL) based on the grid voltage detection value
vacdet. During the voltage sag, the voltage sag detection signal
vfrt becomes one, and the inverter output current command
phase ' is the sum of the present grid voltage phase  and /2.
The reactive current control is achieved by generating acurrent command value with the current phase '. Note thatthe voltage sag is detected by the detection of the grid voltage
maximum value vac_max. After that, the grid voltage peakthreshold for the reactive current control VFRT_th is comparedwith vac_max; when vac_max is dropped to less than VFRT_th, thereactive current command is generated. Note that HPF stands
for the high pass filter, and  is the grid angler frequency.
Figure 3 shows the control block diagram of theconventional FRT operation where iL1* is the interconnectedinductor current command, vcdet is the filter capacitor voltage
detection value, Vdc is the input DC voltage, Td is the deadtime period, iL1det is the interconnected-inductor current
detection value, fsw is the switching frequency and Tdelay is thedelay time of the inductor current detection, vdead is the deadtime error voltage, vc is the filter capacitor voltage, vdis is thedisturbance voltage, iL1 is the interconnected inductor current.
The current controller is implemented by digital signal
processor (DSP). Moreover, a dead-time error voltage of theinverter output is compensated by using the dead-time error
voltage feedforward compensation at a steady-state operation.
The grid current is distorted by the grid disturbance due to theincreasing disturbance gain, when the inductance of theinterconnected inductor becomes low. This also leads to thegreatly increase in the inverter output current overshoot at thevoltage sag.
Figure 4 shows the control block diagram of theconventional FRT operation with a disturbance observer(DOB) [17]-[23]. DOB is implemented by digital hardware infield-programmable gate array (FPGA) to construct a highgain DOB. Thus, the disturbances such as dead time error
voltage and voltage drop of switching devices arecompensated at high speed. The disturbance voltage v̂dis isestimated from the inter-connected-inductor current iL1 andthe output of the PI controller vL* assin(θ' )

+

iL1*

PI

-

vL*

+ +
+

c

iL1dets cvconv* 1

Main circuit
+ v
vdead
+ vdis c
Vdc +

V dc

e

sc L1s  c

+ -

1
sL1

iL1
 sTdelay

iL1detFig. 4. Control block diagram of conventional FRT operation with
DOB. In this method, DOB is implemented by FPGA tocompensate wideband disturbances.

vacdetGate-block OC_L
signalgenerator
TRIP_

Voltage-sag
detection circuit

Detection board
vcdet
DSP
vL* + + 1
+
*
iL1
PI
+ Vdc
c v̂dissin(θ' )where ωc is the cutoff angular frequency of DOB, and s is the
Laplace operator. Moreover, the current controller is addedwith the detected voltage of the filter capacitor vcdet for a
voltage-feedforward compensation. Consequently, the deadtime voltage error is compensated by the high-gain DOB,
whereas the grid voltage is compensated by the voltage
feedforward. However, the overshoot of the inverter output
current becomes significantly fast at the grid voltage drop andrecovery with the low-inductance LCL filter. The disturbancecompensation with the voltage feedforward and the high-gain
DOB cannot detect the grid fault immediately due to the delay
time of the detection and the sampling; consequently, when
the short grid failure occurs, the maximum inverter output
current overshoot of higher than 150% occurs with theminimized LCL filter. Therefore, the high-speed currentovershoot suppression is necessary in order to suppress theovershoot of the inverter output current iLf at the grid faults.
Proposed ZVRT Method
Figure 5 shows the control block diagram of the highspeed gate-block operation with the high-gain DOB for the
ZVRT operation. In order to suppress the inverter output
current overshoot, the gate-block operation is carried out by
the detection of the grid voltage fluctuation. By filtering thegrid voltage with a voltage-sag detection circuit, the gateblock signal OC_L is generated by the gate-block signal
generator. After that, the gate-block operation is carried out at
the grid voltage drop or the voltage recovery. By using thegate-block operation, the ZVRT operation is achieved.
Furthermore, in order to achieve the ZVRT operation at highspeed response, the gate-block control is implemented bydigital hardware in FPGA, whereas the voltage-sag detection
is constructed by analog circuit. Therefore, the detection
delay time of the gate-block operation is minimized, i.e. oneof the main factors to reduce the overshoot. In addition, theproposed method is implemented with the high-gain DOB as
in Fig. 4 in order to reduce the inverter output current
distortion with the low inductance of the interconnectedinductor [23]. The reason is because the effect of the deadtime error voltage significantly increases due to the decrease

DSP FPGA vcdet

+
-

S2

+
-

s c

iL1det

S1

FPGA

-1

sc L1s  c

S3

+
-

S4

CarrieriL1det e sTdelay

iL1

Fig. 5. Control block diagram of ZVRT operation with high-speed gateblock operation. By using the gate-block operation, the inverter
output current overshoot is suppressed at the grid voltage drop andrecovery.
Analogcircuit-Vac_GB
HPF
vacdetB.

Vac_GB
+

FPGA

+
+
-

HPFout

1
0

MUX1



c
s L
*
vˆdis vL  c 1 iL1det c  sc  sController

FRT Control

OC_L

GB_signal
z-1
MUX1
GB_signal 1 0
OC_L 0 1

Up edge period: Carrier period(80 kHz)(Cutoff frequency: 800 Hz)

Fig. 6. Block diagram of voltage-sag detection circuit and gate-block
signal generator. In order to detect the voltage sag, the HPF is
implemented in the analog circuit.

of the disturbance suppression performance with the low
inductance.
C.

High-speed Gate-block Operation
Figure 6 shows the construction of the voltage-sag
detection circuit and the gate-block signal generator, where
HPFout is the output of HPF, Vac_GB is the gate block threshold.
In the high-speed gate-block operation that is applied to the
proposed method, it is necessary to generate the gate-block
signal to carry out the gate-block operation at the detection
time of the grid voltage drop and recovery. The output of thehigh-pass filter (HPF), which filters the grid voltage,overshoots at the grid voltage drop and recovery. The HPF
cutoff frequency is designed to be higher than the gridfrequency, in order to operate HPF as a differentiator at thevoltage sag. In particular, the HPF cutoff frequency isdesigned to approximately 800 Hz in this paper. Moreover,Voltage sag

0
-200
-400

HPF output andGate-block threshold

Grid voltage vac [V]200

HPFoutGate-block positive threshold
Vac_GB

Gate-block negative threshold-Vac_GB

1.0

Gate-block period is
carrier period

0.0 10 ms/div

Fig. 7. Voltage-sag detection and gate-block signal generation during
voltage sag. The gate-block signal is generated at the grid voltage
drop and recovery.
Grid voltage vac
Gridvoltagepeak Vac

III. OPTIMAL DESIGN OF MINIMIZED LCL FILTER
Derivation of Output Current at Grid Voltage Recovery
A current resonance occurs in the grid-side LC filter whena grid voltage sag occurs. The inverter output current
overshoots due to the combination of the resonance current
and the steady-state current. The ability of the gate-block
operation in H-bridge inverter to suppress resonances in thegrid-side LC filter depends on the LCL filter design. Thus, itis necessary to design the parameters of the LCL filter withthe grid-side LC filter resonance to meet the FRT
requirements. The equation of the inverter output current atthe voltage recovery is derived to design the LCL filter.
Figure 8 shows the transient phenomenon of the inverter
output current with the LCL filter at the grid voltage recovery.
Area (i) of Fig. 8 shows the time from the voltage recovery towhen the gate-block operation is carried out (0 ≤ t ≤ tbd). Area(ii) shows the time after the gate-block operation (t ≥ tbd).
Note that tbd is the delay time from the voltage sag to when
the gate-block operation is carried out. In the area (i), thedelay time tbd is the sum of the delay time of the gate-block
operation such as the detection delay time of the analog
circuit and the control delay time of the gate-block operationin the FPGA. The inverter-output-current maximum value
iLf_max and the time reaching the maximum current timax are
calculated in area (ii). In addition, the LCL filter is designed
in order that the inverter output current maximum value is lessthan the maximum inverter output current overshoot of 150%

400

OC_L signal

the grid fault signal is generated by comparing the HPF
output overshoot HPFout and the gate-block threshold Vac_GB.
At the comparison step between the HPF output and the gateblock threshold Vac_GB, the comparator output is low when the
HPF output exceeds the threshold Vac_GB. The threshold Vac_GB
is determined so that the gate-block operation is not carriedout in the normal operation as following simple consideration.
In the normal operation, the HPF output becomes the
maximum at the zero-crossing points of the grid voltage.
Meanwhile, the HPF output at the grid voltage drop andrecovery greatly exceed the HPF output during the normal
operation. Thus, the threshold Vac_GB is set higher than the
HPF output at the zero-crossing points of the grid voltage. In
this paper, the threshold Vac_GB is set to 5 times of the HPF
output at the zero-crossing points of the grid voltage.
Furthermore, the gate-block period is same as carrier period.
Therefore, it is possible to continue the inverter output by the
momentary gate-block operation. After that, the gate-block
signal OC_L is input to AND circuit.
Figure 7 shows the simulation result of the voltage-sag
detection and the gate-block signal generation at the gridvoltage drop and recovery. The HPF output overshoots at thegrid voltage drop and recovery. After that, the gate-block
signal is generated when the HPF output overshoots. Thus,
the gate-block operation for the ZVRT operation is carriedout by the proposed control.

0A.

Voltagerecoverytime

0s

Inverter output
Current iLf

Gate-block
(i)

0

(ii)
time

tbd

Rated
current
peak -ILfiLf_maxith

Gate-block signal
H
L

time

Fig. 8. Transient phenomenon of inverter output current iLf with LCL
filter during voltage recovery. The LCL filter has to be designed inorder that the maximum current iLf_max is less than the limitation ithof the current overshoot according to FRT requirements.

ith.
Figure 9 shows the circuit model with the LCL filter after
the gate-block operation (t ≥ tbd) in the area (ii) of Fig. 8. The
equation of the inverter output current during the transientinterval is derived by considering the LCL filter circuit fromthe viewpoints of the inverter and the grid separately. Afterthe gate-block operation, the inverter output voltage Vconv isapplied to the inverter-side LC filter to inject the current of

iL1
Vconvu(t - tbd)

L1
Cf

iLf

iLf  I Lf sin(t  i )Lf



Vacu(t)iCf

Fig. 9. Circuit model with LCL filter after gate-block operation. The
transient phenomenon of Inverter output voltage and grid voltage
are considered.

the reverse vector to the inverter output current. The inverter
output voltage equals to the input DC voltage Vdc. Whenconsidering the inverter output side, the rated inverter output
current peak –ILf flows until the gate-block operation iscarried out. Thus, the positive inverter output voltage Vconv isapplied after the gate-block operation to flow the current withthe positive direction. In Fig. 9, the circuit equations arederived as shown in (2)-(4)

Vconv stbdVe
 sL1I L1 ( s)  sL f I Lf ( s)  ac ss
I Cf ( s)sC f sL f I Lf ( s) 

Vac

s

I L1 (s)  I Lf (s)  I Cf (s) 







1
L1  L f

 L1  L f  
L1C f L f  L1t Vac sin(t  v ) sin 
L1  L f  L f
LC L 
 1 f f 

 L1  L f  sign  sin(t  i ) Vconv sin t  tbd    L1C f L f 1  x  0sign  x    0  x  0  
1  x  0 






Where is the angular frequency of the grid. The worst caseat the voltage recovery is when the output current reaches thenegative peak and the grid voltage returns to the positive peak.
Therefore, the minimized LCL filter is designed from (5). In
order to design the LCL filter meeting the inverter output
 current overshoot less than 150%, the period until the inverter
output current reaches maximum entitled timax as shown in Fig.
8 is derived as follows. First, considering (7) as the filter
inductor resonance voltage component vLf_res(t),

Vconv (t  tbd )  Vac t
L1  L f

1
L1  L f

L1  L fwhere IL1 (s) is Laplace transform of the interconnectedinductor current iL1, ILf (s) is Laplace transform of the filter
inductor current iLf, Icf (s) is Laplace transform of the filter
capacitor current icf, and Vac is the grid voltage peak. By using(2)-(4) and the rated inverter output current peak ILf, the filter
inductor current iLf is expressed asiLf   I Lf sign  sin(t  i ) Vconv (t  tbd )  Vac sin(t  v )t

vLf _ res (t ) 
L1
Vac sin Lf Vconv sin L1  L f t
L1C f L f t  tbd 
L1C f L f
L1  L f

When the differentiate equation for (7) becomes zero, thetime reaching the maximum inverter output current timax isderived as L1  L f 
L1C f L f  L1t   
 Vac sin 
L1  L f  L f
L1C f L f ti max  L1  L f Vconv sin t  tbd  L1C f L f




tbd
 L1 Vac 1 L f Vconv




2

 L1 Vac 2 L C L
2L C V  L V2
 1 1 f f  1 f ac   1 ac tbd
 L f Vconv
 L1  L f

L1  L f Vconv  L f Vconv
 L1 Vac 1 L f Vconv


It is obvious that the timing of the voltage recovery in the
short grid failure is unknown. Thus, by considering the gridvoltage phase at the voltage recovery v and the inverter
output current phase i, (5) is converted to (6)






where the approximation of sin( x)  x  x3 / 6 is applied to(7) to derive (8). By substituting timax in (8) to t in (5), themaximum inverter output current after the gate-block
operation iLf_max is derived. Moreover, it is possible to meetthe requirements with any damping resistor, when the LCL
filter without the damping resistor is designed to meet therequirements. Thus, the consideration of the over-current
suppression with a damping resistor is omitted in this paper.
In addition, the maximum inverter output current at thevoltage drop is also derived by the circuit model of Fig. 9.
The maximum inverter output current at the voltage dropiLf_max_dp is expressed as

Input: vac, fsw, tbd, Vdc, Pout and ith

Calculation of inductance for interconnectedinductor L1 by %Z of output impedance (11)Calculation of inductance L1_rip by output current
ripple rate meeting grid code requirements (12)L1_rip < L1

NO

YES

iLf _ max_ dp  I Lf 
1
L1  L f

Vconv (2tbd  ti max_ dp )Calculation of capacitance for filter capacitor Cf by
cutoff frequency of inverter side LC filter (13)L1  L f

 L1  L f

L1C f L f 
ti max_ dp  tbd   
2Vconv sin L1  L f 
LC L 1 f f







 
 L1  L f
  L1  L f

Vac  Vconv  sin 
ti max_ dp   Lf  L1C f L f


 

where timax_dp is the duration from the voltage drop to when
the output current reaches the maximum value. Note that (9)is considered under the condition that the voltage drop occurs
at the grid voltage peak as a worst case of the inverter output
current overshoot. Moreover, timax_dp is derived asti max_ dp 

Set filter-inductor value Lf
to zeroSet filter-inductor value Lf
to zeroIncrease Lf
NO

Lf < L1NO
YES
Calculation of cutoff frequency ofgrid-side LC filter (14)

fLC_cut_g <0.1 fsw

NO

YES

Flowchart of LCL filter design
Figure 10 shows the flowchart of the LCL filter design
method. Inputs of the LCL filter design flowchart are thespecifications of the inverter, such as the grid voltage vac, theswitching frequency fsw, the gate-block delay time tbd, the DClink voltage Vdc, the inverter output power Pout, and the
maximum inverter output current overshoot of 150% ith. First,
the inverter side LC filter is designed from the specificationof the inverter. The interconnected inductor L1 is designed
from the normalized value %Z of the inverter output
impedance. The inductance of the interconnected inductor L1
is derived as shown in (11)

% Z L1 vac 2 PoutDerivation of maximum
inverter output current atvoltage drop iLf_max_dp by (9)iLf_max_dp = ith
NO
YES
YES
Set high filter-inductance Lf of (5) or (9)1  L1  L f Vac
 1


2  L f Vconv
L1 

Derivation of maximum
inverter output current
iLf_max by substituting timax tot in (5)iLf_max_dp = ith

Output: L1, Cf, Lf

B.



Calculation of time reaching
maximum inverter output
current at voltage drop
timax_dp (10)Increase Lf

tbd  L1C f Vac1  L1  L f Vac
tbd 2  
 1 
 tbd 2  Vconv
2  L f Vconv

1  L1  L f Vac
 1


2  L f Vconv


Calculation of time reaching
maximum inverter output
current at voltage recovery
timax (8)

Fig. 10. Flowchart of LCL filter optimized design for grid-connected
inverter. The LCL filter is designed to meet the FRT requirements
and reduce the inverter output current overshoot less than 150%.

where %ZL1 is the normalized impedance of theinterconnected inductor, vac is rms value of the grid voltage
and Pout is inverter output power. The output current ripple isdefined in the grid code. The inductance to meet the required
current ripple L1_rip is expressed as

L1_ rip 

Vac Vdc  VacI L1 f sw Vdc



where IL1 is the required current ripple. If the inductance L1
is less than L1_rip, the interconnected inductor L1 should beredesigned. Moreover, the interconnected inductor is

Cf 

1

 2 f

L
2

LC _ cut _ inv

1

After that, the filter inductor Lf is determined to meet theinverter output current overshoot less than 150% at thevoltage recovery according to (5) and (8). Furthermore, thefilter inductor Lf is determined to meet the inverter output
current overshoot less than 150% at the voltage drop
according to (9) and (10). The filter inductance Lf is set tohigher one which is derived in (5) or (9). If the interconnectedinductor L1 is less than the filter inductor Lf, the inverter side
LC filter should be redesigned when determining the filter
inductor. In addition, considering the suppression of theswitching-frequency-order harmonic, if the cutoff frequencyof the grid-side LC filter fLC_cut_g is higher than 10% of theswitching frequency, the inverter side LC filter should beredesigned. The cutoff frequency of the grid-side LC filter
fLC_cut_g is expressed as
f LC _ cut _ g 

1
2 L f C f

Outputs of the LCL filter design flowchart are theinterconnected inductance L1, the filter capacitance Cf, andthe filter inductance Lf. The difference between the proposed
LCL filter design and the conventional LCL filter design suchas [25] is the consideration of the suppression of the inverter
output current overshoot at the voltage sag. Note that theconsideration of the reduction for the harmonic components issame in both the proposed and conventional LCL filter design.
Table I shows the calculation result of the LCL filter
design based on the flowchart of Fig. 10. The interconnectedinductor impedance is 1.0% of the inverter normalized
impedance, whereas the filter inductor is 0.78%. The filter
capacitor is determined to let the cutoff frequency of inverter
side LC filter be 10 kHz (one sixteenth of equivalentswitching frequency). In the calculation result with thedesigned LCL filter, the maximum output current overshoot issuppressed less than 150%. Furthermore, the LCL filter inTable I is designed with a margin in order to ensure themaximum inverter output current overshoot less than 150%.
Moreover, in order to reduce the resonance current in the
LCL filter, a damping resistor Rf is connected to the filter
capacitor in series. The resistance of the damping resistor isselected to consume below 0.1% of the inverter output power;
therefore, the voltage drop of the damping resistor is ignored.
Considering only the normal operation, it is possible tofurther reduce the total inductance of the LCL filter in the

INITIAL CONDITION AND CALCULATION RESULT OF LCLFILTER DESIGN.
Initial condition
Grid voltage Vac
DC-link voltage Vdc
Output power Pout
Rated inverter output current ILf
Inverter output voltage Vinv
Carrier frequency fcry
Equivalent switching frequency fsw
Gate-block delay time tbd
Inverter output current limit
by FRT requirement ith
Calculation result
Interconnected inductor L1
Filter capacitor Cf
Filter inductor Lf
Maximum inverter output current
at voltage recovery iLf_max
Maximum inverter output current
at voltage drop iLf_max_dp%Z of inductor L1 and Lf [%]TABLE I.

283 V
380 V
1 kW
7.07 A
380 V
80 kHz160 kHz
3.0 msILf×1.5

1.29 mH
0.2 mF0.99 mH-10.3 A
(145%)
10.1 A(143%)

1.40

0.35

1.20

0.30

1.00

Filter capacitor Cf

0.25

0.80 Interconnected Inductor L1

0.20

0.60

0.15

%Y of capacitor Cf [%]designed to reduce the switching ripple components of theinverter output current less than 0.3%, in order to meet thecurrent quality [24]. The filter capacitor Cf is determined fromthe cutoff frequency of the inverter-side LC filter fLC_cut_inv.
The filter capacitor Cf is expressed as

Filter Inductor Lf
0.40
0

2.00
4.00
6.00
8.00
Delay time for gate-block operation [ms]

0.10
10.0

Fig. 11. Relationship between delay time of gate-block operation anddesign parameters of minimized LCL filter in 1-kW system. The
LCL filter parameter is designed in order that the maximum
inverter output current overshoot is 150%.

conventional LCL filter design [26] compared with theproposed LCL filter design. However, when considering thedelay time for the gate-block operation in the ZVRT, thereduction of the total inductance is restricted in order to meet
the FRT requirements. Therefore, the proposed LCL filter
design clarifies this reduction limitation of the total
inductance.
Figure 11 shows the characteristics of the delay time forthe gate-block operation and the minimized LCL filter
parameter when the maximum inverter output current
overshoot is 150%. In this design, the LCL filter is designed
as follows; the cutoff frequency of the inverter side LC filter
is 10 kHz, the cutoff frequency of the grid-side LC filter is 12
kHz, and the maximum inverter output current overshootbecomes 150% at the voltage recovery. In Fig. 11, when the
delay time for the gate-block operation is short, theinterconnected inductor and the filter inductor are possible toOutput current fundamental
frequency: 50 Hz

Grid Voltage vac [V]Inverter output current ripple ratio [%]

400
200
0
-200
-400
15
10

Inverter output current iLf [A]

5
0
-5
-10
10 ms/div-15(a) Waveform of ZVRT operation.

400
200
0
-200
15
10

9.9 A (140%)

50-5Inverter output current iLf [A]

200 ms/div(b) Voltage drop operation.

400

Grid Voltage vac [V]

200
0
-200
5

Inverter output current iLf [A]

0
-5
-10
-15

10.2 A (144%)

200 ms/div(c) Voltage recovery operation.
Fig. 12. Simulation result of grid failure with minimized LCL filter byusing proposed design method. The maximum inverter output
current overshoot is suppressed to become less than 150%.

minimize. This is because when the delay time for the gateblock operation is short, the effect of the inverter output
current overshoot caused by the short grid failure is small. On
the other words, the interconnected-inductor value and thefilter-inductor value are limited by the delay time for gateblock operation.

Grid code requirements
for current ripple
Simulation result

10.01
1.0e-4

Carrier frequency: 80 kHz

1.0e-6Equivalent switchingfrequency: 160 kHz

1.0e-81.0e-101.0e-12

1

2

3

4
5
6
7
Harmonic order

8

9

10

Fig. 13. Simulation result of harmonic analysis for switching frequency
components with designed LCL filter. The switching components areenough low compared with the output current frequency.

C.

Grid Voltage vac [V]100

Simulation of ZVRT with designed LCL filter
In order to confirm validity of the designed LCL filter inTable I, the ZVRT operation with the designed LCL filter isevaluated in simulation. Figure 12 shows the simulation
results of the ZVRT with the proposed high-speed gate-block
method. By using the proposed high-speed gate-block method,
the inverter output current is suppressed to 9.9 A at the gridvoltage drop as shown in Fig. 12 (b) (Overshoot: 140%).
Moreover, at the grid voltage recovery, the inverter output
current overshoot is suppressed to 10.2 A as shown in Fig. 12(c) (Overshoot: 144%). Thus, the grid-connected inverter withthe minimized LCL filer meets the inverter output current
overshoot less than 150% by using the proposed high-speed
gate-block method. Comparing the inverter output current
overshoot between the calculation value and the simulation
value at the voltage recovery and drop, the error rates are
2.2% and 2.1%. Thus, the validity of the LCL filter design
method meeting the FRT requirements is confirmed.
Moreover, the error between the calculation value and thesimulation value occurs due to the damping resistor, theprecision of approximation and the steady-state current at thegrid voltage recovery is constant value in the calculation.
Therefore, by using the high-speed gate-block method and the
optimized LCL filter design method, it is possible tominimize the LCL filter and still meet the FRT requirements.
Figure 13 shows the simulation result of the harmonic
analysis for the output current with the designed LCL filter in
the normal operation in order to confirm the effect of theharmonic component, e.g. switching frequency. In Fig. 13, theswitching-frequency-order harmonic components of theoutput current are very low compared with the output current
fundamental frequency component (50 Hz). In particular, thesimulation result of the switching ripple components meetsless than 0.3% for the standard such as IEEE Std. 1547 [24].
Note that the switching ripple components are greatly lower
than the grid code requirement values, because the total
inductance of the filter which meets the FRT requirements ishigher than that which meets the harmonic restraint.

Vdc

iL1

iLf

L1

Lf
vc

vconv

Cf

Lg
vacdetvac

S4Fig. 14. Circuit configuration with grid impedance Lg. In actual gridconnection, there is grid impedance between the inverter output andthe grid voltage.
150
145
140
135
130
125

Lg : Grid inductance
Lf : Inductance of filter inductor

00

20

40
60
Lg / Lf [%]

80

100

Fig. 15. Simulation results of maximum inverter output current overshootat grid voltage recovery and ratio between grid inductance Lg andfilter inductance Lf. When the grid impedance is low, the maximum
output current overshoot becomes high.
TABLE II. EXPERIMENTAL CONDITION.

IV. EXPERIMENTAL RESULT
Table II shows the experimental condition. The LCL filter
that designed in Table I is used. Note that in the experiment,in order to consider the worst case of the grid, the ZVRT
operation is confirmed without the grid inductor. The
designed LCL filter is tested under three FRT methods; theconventional FRT method I in which the controller is shownin Fig. 3 with the grid voltage feedforward, the conventional
FRT method II in which the controller is shown in Fig. 4 withboth the grid voltage feedforward and the high-gain DOB,
and the proposed FRT method in which the controller isshown in Fig. 5 with the grid voltage feedforward, the highgain DOB and the high-speed gate-block function.
Figure 16 shows the experimental result of the ZVRT
operation with the conventional FRT method I with only thegrid voltage feedforward. After the grid voltage drop, theinverter output current overshoots to 41.2 A (Overshoot:583%). After that, the inverter operation is halted owning tothe over current protection. Due to the detection and thesampling delay, the inverter output current overshoot with theminimized LCL filter is large. As a result, the inverter output
current reaches the over current threshold. Thus, it is
impossible to continue the inverter output during the voltage
sag with the minimized LCL filter by using the conventional
FRT method I.
Figure 17 shows the experimental result for the ZVRT
operation of the conventional FRT method II with both thegrid voltage feedforward and the high-gain DOB. In Fig. 17(a), it is possible to continue the operation after both thevoltage drop and the voltage recovery because the high-gain
DOB suppresses the current overshoot. However, in Fig. 17

S3

S2

Maximum output
current overshoot [%]D. Consideration of inverter maximum output current
overshoot with grid impedance
Figure 14 shows the circuit diagram considering a grid
inductor connected to the LCL filter at the grid-side. The
effect of the grid impedance for the FRT capability by using
the proposed high-speed gate-block method is confirmed
under the condition that there is grid impedance in the actual
grid. As shown in Fig. 14, it is impossible to directly detect
the grid voltage vac, because the detection point of the gridvoltage is between the grid inductor Lg and the filter inductor
Lf.
Figure 15 shows the simulation results of the relationshipbetween the maximum inverter output current overshoot at thegrid voltage recovery and the ratio between grid impedance
and filter inductance Lg/Lf. Note that the filter-inductor value
Lf is 0.99 mH (%Z of 0.78%) which is designed in Table I.
The grid impedance Lg is changed from zero to the filterinductor value Lf. As shown in Fig. 15, the maximum inverter
output current overshoot decreases when the grid impedance
Lg increases, the inverter output current variation is reducedby the increase in the grid impedance Lg.

S1

Output power Pout 1 kW
DC link vol. Vdc 380 V

Filter cap.
Carrier fre.
200 Vrms Ang. fre. of ACR

Cf
fcry

0.2 mF80 kHzn 6000 rad/s
L1 1.29 mH Samp. fre. of ACR fsamp 20 kHz(1.0%) Samp. fre. of DOB fso 80 kHz
2 kHz
Filter Induc. Lf 0.99 mH Cutoff fre. of DOB fc(0.78%) GB delay time(%Z)
tdelay < 3 ms
Grid voltage vac
Inter. Induc.
(%Z)

Conventional
FRT method I

Conventional
FRT method II

Proposed
FRT method

Fig. 3Fig. 4

Fig. 5

Voltage
Feedforward
High-gain
DOB
High-speed
Gate-block
Block diagram(b)-(c), the inverter output current maximum values at thevoltage drop and the voltage recovery are 13.2 A (Overshoot:187) and 12.3 A (Overshoot: 174%), respectively. Thus, it is
impossible to reduce the maximum inverter output current
overshoot less than 150% at the voltage recovery. If thesampling frequency for the disturbance compensation
increases in order to reduce the computation time of the highgain DOB, it might be possible to suppress the inverter output
current overshoot less than the threshold value of over current
protection. However, due to the delay time of the detection
and the sampling, the maximum inverter output current
overshoot exceeds 150% with the minimized LCL filter that iscomposed by the minimized interconnected inductor (%Z of
1.0%) and filter inductor (%Z of 0.78%). As a conclusion, it
is necessary to reduce the detection delay time to reduce the50 ms/div

0

50 ms/div

Grid voltage vac 250 V/div

0

Grid voltage vac 250 V/div
Output current iLf 10 A/div(b) Voltage drop00

Output current iLf 10 A/div(b) Voltage drop(c) Voltage recovery(a) Waveform of ZVRT operation.

(a) Waveform of ZVRT operation.
200 ms/div

0

Grid voltage vac
250 V/div

200 ms/div0

Maximum current 41.2 A(583%)

Grid voltage vac 250 V/div

0

Grid voltage vac 250 V/div

Maximum current
13.2 A (187%)
Output current iLf 10 A/div

Output current iLf
10 A/div00

Output current iLf 10 A/div
200 ms/div(b) Voltage drop operation.
Fig. 16. Experimental results of grid failure with conventional FRT
method I with only grid voltage feedforward. The inverter output
current overshoot is large due to the detection and the samplingdelay at the voltage drop.

inverter output current overshoot less than 150% with theminimized LCL filter and meet the FRT requirements.
Figure 18 shows the experimental result of the ZVRT
operation with the proposed FRT method in which the highspeed gate-block method is applied, under the conditions
when the voltage drop and recovery occur at the grid voltage
phase of 90 degree. By using the proposed FRT method, theinverter output current overshoot at the grid voltage drop in
Fig. 18 (b) is 10.3 A (Overshoot: 146%) , whereas theinverter output current overshoot at the grid voltage recovery
in Fig. 18 (c) is 10.3 A (Overshoot: 146%). Moreover, thegate-block operation is confirmed at the voltage drop andrecovery in Fig. 18 (d). Therefore, it is confirmed that thegrid-connected inverter with the minimized LCL filter meetsthe FRT requirements and the inverter output current less than
150% by the proposed high-speed gate-block method and thedesigned LCL filter. There is an error of 1.1% between the
maximum current overshoot of the calculation result and theexperimental result at the grid voltage recovery. The error iscaused by the approximation when deriving the equation, andthe inconsideration of the damping resistor. In addition, theactive power recovery operation after the grid voltage
recovery is considered. After the grid voltage recovery, theoutput current phase which is added to the PLL phase isdecreased gradually from /2 to zero. The reduction speed is(b) Voltage drop operation.

0

Maximum current 12.3 A (174%)(c) Voltage recovery operation.

Fig. 17. Experimental results of grid failure with conventional FRT
method II by applying DOB. The inverter output current overshootexceeds 150% due to the delay for disturbance compensation
caused by the detection and the sampling delay.

approximately 10/9 ms/deg. In Fig. 18 (e), the output power
recovery period is 95 ms after the grid voltage recovery.
Therefore, the output power recovery operation is also
confirmed to meet the FRT requirements.
Figure 19 shows the experimental result of the ZVRT
operation with the proposed FRT method, under theconditions when the voltage drop and recovery occur at thegrid voltage phase of 0 degree. When the grid faults occur atthe voltage phase of 0 degree, the momentary voltage
fluctuation does not occur and the gate-block operation is not
carried out. However, the inverter output current overshootdoes not occur in this case. Thus, the inverter output current
overshoot is suppressed without the proposed gate-block
operation during the grid fault at the grid voltage phase of 0
degree. As a conclusion, the main contribution of the
proposed FRT method is the high-speed gate-block operationand the low-inductance LCL filter design method. Meanwhile,the detection of the grid faults can be achieved by several
separate or combined methods, e.g. the use of HPF to detect
the rapid change of the grid voltage, or the overshoot current
detection, in which the current detection values is comparedwith a threshold by an analog circuit. By considering thedelay time of each grid fault detection method, the same highspeed gate-block operation and the low-inductance LCL filter
design method proposed in this paper can be applied.

Figure 20 and 21 show the experimental results of the
LVRT operation with the proposed FRT method. The
experimental results are considered with the grid voltage
down from 100% to 20% at the grid phase of 90 degree and 0
degree. In Fig. 20, the maximum inverter output current
overshoot is suppressed to less than 150% with the gate-block
operation at the voltage drop and recovery. Similarly to Fig.
19, in Fig. 21, it is possible to continue the operation of theinverter without the gate-block operation. Therefore, it isconfirmed that the LVRT operation is also achievable withthe proposed method.

0

Output current iLf 10 A/div
0(b) Voltage dropV.

CONCLUSION

In this paper, the ZVRT operation of the single-phase gridconnected inverter with the minimized LCL filter was verified.
In particular, the high-speed gate-block method that is
implemented in analog circuit and FPGA was proposed;
moreover, the minimized LCL filter design method waspresented in order to satisfy the FRT requirements and reducethe inverter output current overshoot less than 150%. It was
confirmed through the experimental results that the maximum
inverter output current overshoot during the voltage sag was
suppressed to become less than 150% by the proposed highspeed gate-block method and the design of the LCL filter. In
particular, the interconnected inductor was minimized to
1.0% of %Z and the filter inductor is minimized to 0.78%
of %Z in the 1-kW prototype. Therefore, by applying the
proposed method, it is possible to reduce the size of LCL
filter and still meet the FRT requirements.
In future, the ZVRT operation for the three-phase gridconnected inverter with the minimized output filter will beconsidered. Furthermore, the design of the minimized output
filter will be also evaluated.
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50 ms/div

Grid voltage vac 250 V/div(c) Voltage recovery(a) Waveform of ZVRT operation.

0

Grid voltage vac 250 V/div

0

Grid voltage vac 250 V/div

Maximum current
10.3 A (146%)0

Output current iLf 10 A/div0

Output current iLf 10 A/div

Maximum current 10.3 A(146%)
200 ms/div

200 ms/div(b) Voltage drop operation.

(c) Voltage recovery operation.

Grid voltage vac 250 V/div
0

Grid voltage vac
250 V/div0Gate-block signal OC_L 5 V/div
Gate-block00Gate block signal OC_L 5 V/div
Gate-block

0

0

[1]

50 ms/div

Inverter
output voltage
250 V/div

50 ms/div

Inverter
output voltage
250 V/div(d) Gate-block signal at voltage drop and recovery.
Grid voltage vac 250 V/div0

Output power recovery:
95 ms

0

Output current iLf 10 A/div

20 ms/div(e) Output power recovery
Fig. 18. Experimental results of grid failure at grid phase of 90 degreewith proposed ZVRT method. By applying the proposed method,
it is possible to continue the operation of the inverter, and satisfy
the FRT requirements.

50 ms/div

Grid voltage vac 250 V/div

50 ms/div

Grid voltage vac 250 V/div
00

Output current iLf 10 A/div

Output current iLf 10 A/div
00(b) Voltage drop(b) Voltage drop(c) Voltage recovery0

Grid voltage vac 250 V/div

0

Grid voltage vac 250 V/div0

Without overshootover the rated current

0

200 ms/div

Without overshootover the rated current

Gate-block signal OC_L 5 V/div0

50 ms/div

Inverter
output voltage
250 V/div

Output current iLf 10 A/div0

Output current iLf 10 A/div
200 ms/div(b) Voltage drop operation.

0(c) Voltage recovery operation.
50 ms/div0Gate block signal OC_L 5 V/div

Gate-block signal OC_L 5 V/div

Without
Gate-block

Gate-block

0

0

0

0

50 ms/div

Inverter
output voltage
250 V/div

Grid voltage vac 250 V/div

Without overshootover the rated current peak

Grid voltage vac 250 V/div
Grid voltage vac
250 V/div000

200 ms/div(c) Voltage recovery operation.

Grid voltage vac 250 V/div

Without
Gate-block0

Output current iLf 10 A/div
200 ms/div(b) Voltage drop operation.

0

Grid voltage vac 250 V/div

Maximum current
9.4 A (133%)

Output current iLf 10 A/div0(c) Voltage recovery(a) Waveform of LVRT operation.

(a) Waveform of ZVRT operation.

Grid voltage vac
250 V/div
Gate block signal OC_L 5 V/div

0

Gate-block0

50 ms/div

Inverter
output voltage
250 V/div

Inverter
output voltage
250 V/div(d) Gate-block signal at voltage drop and recovery.

(d) Gate-block signal at voltage drop and recovery.

Fig. 19.
Experimental results of grid failure at grid phase of 0 degreewith proposed ZVRT method. Without the gate-block operaiton, it
is possible to continue the operation of the inverter, and satisfy the
FRT requirements.
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0

Output current iLf 10 A/div
0(b) Voltage drop

Keisuke Kusaka (S’13, M’16) was born in Miyagi,
Japan, in 1989. He received his B.S. and M.S.
degrees in electrical, electronics and informationfrom Nagaoka University of Technology, Niigata,Japan in 2011, 2013, respectively. From 2015 to
2016, he was with Swiss Federal Institute ofTechnology in Lausanne (EPFL), Switzerland as a
trainee. In 2016, he received his Ph.D. degree inenergy and environment science from Nagaoka
University of Technology. He was with Nagaoka
University of Technology, Niigata, Japan as a researcher from 2016 to 2018.
Since 2018, he has been with Nagaoka University of Technology, Niigata,Japan as an assistant professor. His current research interests include theareas of IPT systems and high-frequency converters.
He received the Second Prize Paper Award in IPEC-Niigata 2018 fromIEEJ.

(c) Voltage recovery(a) Waveform of LVRT operation.

0

Grid voltage vac 250 V/div

0

Grid voltage vac 250 V/div
Without overshootover the rated current

Output current iLf 10 A/div
00

200 ms/div

Without overshootover the rated current

Output current iLf 10 A/div
200 ms/div(b) Voltage drop operation.

(c) Voltage recovery operation.
50 ms/div

Grid voltage vac 250 V/div
0

Grid voltage vac
250 V/div0Gate-block signal OC_L 5 V/div
Without Gate-block0

Satoshi Nagai (S’15) was born in Niigata, Japan, in
1987. He received his B.S. and M.S. degrees inelectrical and electronics engineering from Niigata
University, Niigata, Japan in 2011, and electrical,
electronics and information engineering from
Nagaoka University of Technology, Niigata, Japan in
2017, respectively. Since 2011, he has been with
Diamond Electric Mfg. Co., Ltd., Japan. Presently, he
is a Ph.D. candidate at Nagaoka University ofTechnology, Niigata, Japan. He is the student
member of IEEJ and IEEE. His current research interests include control
techniques and design of grid-tied systems.

50 ms/div

Grid voltage vac 250 V/div0

50 ms/div

Inverter
output voltage
250 V/div

Gate block signal OC_L 5 V/div0

Without Gate-block0

Inverter
output voltage
250 V/div(d) Gate-block signal at voltage drop and recovery.
Fig. 21.
Experimental results of grid failure at 0 degree of grid phasewith proposed method in LVRT operation (Grid voltage down to20%). Without the gate-block operaiton, it is possible to continue
the operation of the inverter, and satisfy the FRT requirements.
Dr. Kusaka is a member of Institute of Electrical Engineers of Japan,
Society of Automotive Engineers of Japan and the IEEE.
Jun-ichi Itoh (M’04, SM’13) was born in Tokyo,
Japan, in 1972. He received his M.S. and Ph.D.
degree in electrical and electronic systems
engineering from Nagaoka University ofTechnology, Niigata, Japan in 1996, 2000,
respectively. From 1996 to 2004, he was with Fuji
Electric Corporate Research and Development Ltd.,Tokyo, Japan. He was with Nagaoka University ofTechnology, Niigata, Japan as an associate
professor. Since 2017, he has been a professor. His
research interests are matrix converters, dc/dc converters, power factor
correction techniques, energy storage system and adjustable speed drive
systems.

He received IEEJ Academic Promotion Award (IEEJ TechnicalDevelopment Award) in 2007. In addition, he also received Isao Takahashi
Power Electronics Award in IPEC-Sapporo 2010 from IEEJ, 58th OHM
Technology Award from The Foundation for Electrical Science andEngineering, November, 2011, Intelligent Cosmos Award from Intelligent
Cosmos Foundation for the Promotion of Science, May, 2012, and Third
prize award from Energy Conversion Congress and Exposition-Asia, June,
2013. Prizes for Science and Technology (Development Category) from theCommendation for Science and Technology by the Minister of Education,
Culture, Sports, Science and Technology, April 2017.
Dr. Itoh is a senior member of the Institute of Electrical Engineers ofJapan, the Society of Automotive Engineers of Japan and the IEEE.