APPLICATION NOTE
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High-Side SmartFETs with
Analog Current Sense
AND9733/D
APPLICATION SYSTEM OVERVIEW
The design flow for any device initiates with a holistic
understanding of the target application environment
followed by specification creation around the required
performance in application. The close interaction withapplication and an intricate dependence (of a device’s
performance) on external conditions necessitate adopting asystem level approach for a design guide. Therefore, before
discussing the device specifics, it is imperative tounderstand the application environment, behavior of typicalloads and their interaction with the high side switches.

INTRODUCTION AND SCOPE
This application note describes the structure and design
philosophy of onsemi High Side SmartFETs, and serves asa guide to understand the operation of the device in specificapplications. The scope of this document is limited to
SmartFETs with analog current sense output. The following
section covers the application details and behavior of
specific application loads. This is followed by Section
Power FET and Protection that provides details on thephysical structure of the power element− the vertical power
FET and different technologies employed to realize thepower FET. This section also includes the protection
features incorporated within the device that enable it toprotect itself in case a system failure condition exists.
Section Application interface and control describes theapplication interface to the SmartFET and provides
recommendations for the peripheral circuit for the desired
operation. The switching characteristics of the device whiledriving typical automotive loads are explained in Section
Switching Characteristics
The subsequent section elaborates the operation of theanalog current sense and fault reporting through thediagnostic output multiplexed with the current sense output.
Since the fault flagging conditions could be different fordifferent devices in the family, it is always recommended torefer to individual product datasheets for the specificdiagnostic truth table. This document encompasses the
typically observed fault conditions and describes the
behavior of device and expected the current sense operation
for those faults. Finally, the last section provides anunderstanding of the thermal response of the device and also
outlines the interpretation of thermal data and curves
published in the product datasheets. This would help indesigning the correct application heat sinking and PCB
layout to obtain the optimal thermal performance from thedevice.
The document also provides specific examples andnumerical calculations while explaining certain concepts. It
should be noted that unless otherwise mentioned, the values
mentioned in these examples should be considered only
typical and not defining any bounds on the performance ofthe device. For all maximum ratings, the respective productdatasheets should be referred. In addition, any layouts orcircuit blocks depicted in this document are exemplary anddo not necessarily represent an actual die or a real circuit
schematic drawing of a specific device. Lastly, thewaveforms have been idealized to explain the behavior ofdevice inputs/outputs under certain scenarios.

 Semiconductor Components Industries, LLC, 2015

August, 2023 − Rev. 2

Smart High Side Switches − Motivation

The “end requirement” from a high side SmartFET is toswitch loads, and there are different alternatives, available
in market, towards that end. Relays, for instance, have beenused for long in the industry to switch various automotive
loads, especially those requiring high current activation.
With a continual reduction in the weight and size of
automotive components and assemblies, there has been an
evident transition from relays to semiconductor switches
that take up less area and also offer improved noise
immunity and lower electromagnetic interference ascompared to relays.
A p−n junction diode is an easy to use semiconductor
switch that solves the basic requirement of switching.
However, the power dissipations and high conduction losses
do not render them as a viable alternative in the modern
automotive environment with aggressive target specs on
improving efficiency and cutting down system losses.
Further, the bipolar nature of the conduction element
involves minority carrier injection and extraction duringswitching that limits the speed in application. Devices like
SCR’s (Silicon controlled rectifiers) and triacs also facesimilar challenges. Bipolar transistors have high output
current drive capabilities and lower conduction losses (thandiodes) but require an input current drive that makes them
undesirable as a switching element. They are widely used insemiconductor industry, however, for bandgap generationand voltage regulation purposes. Applications requiringhigh voltage breakdown with a reasonably high output
current drive, such as fuel ignition, typically employ IGBTs
as the switching element. Since the output stage in an IGBT
is bipolar, the minority carrier extraction, as for any p−njunction, limits the turn−on/turn−off rates. With a focus on
all the performance metrics discussed above, a FET is themost likely and widely used candidate for switching
automotive loads. Ease of input drive, high input

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impedance, fast switching and a wide SOA (Safe OperatingArea) help in achieving the optimal switching performance.

Figure 2. H−Bridge Switching Configuration

With the increasing complexity in application (to render
more features available to the user), the probability of asystem failure condition also increases. This requires theswitch to protect itself in case of operation outside theintended regime, most likely due to a system failure
condition (such as output short circuit to GND) existing.
From a cost point of view, adding smarts to a switch
eliminates the cost of replacement (in certain safety criticalapplications, the whole module needs to be replaced in casea device fails) and reduces the system cost over an extended
period. While adding control and logic features to the power
FET, due care has to be exercised in the device design stage
to ensure the required module reliability.

Figure 1. High−Side Switch vs Low−Side
Switch in an Application

Figure 1 depicts two of many topologies used forswitching loads in an application. With a high side switch,
the load is always connected to the ground and theconnection to the supply is switched; with a low side switch,
the load is always connected to the power supply and theconnection to GND is switched. The switch is typicallyhoused inside a control unit or, ECU. The load line is thecable length that connects the load to the pin connector on
the ECU. Depending on the load type and its location in thevehicle, this load line could be fairly long, thereby,
increasing the likelihood of a short to chassis ground which
could be a severely stressful condition for the load in alow−side configuration. This makes the high side switchesa preferred choice for load switching. In addition, in cases
where a parasitic impedance path to GND exists in thesystem (as would be described in later sections thattemperature and humidity can create leakage resistances
over time), the leakage levels are higher in a low side
configuration where power supply is always connected to
the load. With the advancement in charge pump design andtechnology, it is relatively convenient to integrate charge
pump with the power element, enabling N−channel FETs to
be used in high side configuration in a small chip size.
Some applications also use an H−Bridge switching
configuration to drive bi−directional loads− for example, adoor lock/unlock motor. An H−bridge utilizes two pairs ofhigh side and low side switches as shown below:

Hide Side SmartFET Solutions

onsemi High Side SmartFETs are offered in monolithic ordual die solutions. Figure 3 highlights, in dashed rectangles,
the two sections of a SmartFET− the control circuit(consisting both analog, digital controls and the chargepump) and a power section (consisting the power DMOS
and sense elements for temperature and current sensing). In
a monolithic solution, as the name suggests, both these
sections are integrated on the same substrate while in a dual
die solution, these two sections are realized on two different
substrates and connected with inter−die bonds. The relativeorientation and integration of the two dies depends onrequired package dimensions and device’s long term
reliability. Section Monolithic vs Dual Die Technology
provides a detailed description of these solutions along with
their benefits and drawbacks.

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Control Logic andConditioning Block

VBATTApplication Environment and Loads

Power FET and
Sensing Block

VD

The automotive application environment is vastlydifferent and typically more aggressive in requirements thanother applications like industrial, consumer etc. Standards
including AEC−Q100 require automotive switches toadhere to a minimum standard of quality, reliability androbustness under extremes of ambient variations(temperature, pressure humidity etc.).
Consider, for example, a scenario of switching a bulb load.
As will be described later in this section, incandescent lamps
require an inrush current at turn−on, which is higher than thenominal drive current. The bulb load in this example is an H4
type headlamp rated for a nominal power of 55 W at 12.8 V.
The inrush current required at an ambient temperature of~300 K (27 C) is ~75 Amp. The cable lengths inautomotive environments can be long, and consequently thecable resistance can be significant. For a cable impedance of
20 mW, the inrush results in a ~1.5 V drop across the cablefor a few milliseconds, (until the bulb is sufficiently turnedon). Further, a typical connection to the supply in an
automotive environment is switched through protection
relays and fuses (housed inside the junction box). These may
also present impedance to the inrush and limit the voltage
swing available for the operation of high side switch. It is
assumed (in this hypothetical case) that this drop is ~ 1V. In
addition to losses in the supply line, there are losses in the
GND line as well. Modules, in automotive environment, areconnected to chassis GND through a resistive network forprotection purposes. This network adds to the losses,
averaged to ~1V for this example. This implies that losses
in the automotive application could easily lead to a 20~25%
drop in the supply voltage at a nominal VBATT = 14 V for areadily observed situation of a headlamp turn−on. The highside switch should be able to operate under reduced battery
voltages. It should be noted that “operation” in this regard
encompasses a fully turned on charge pump, available
protection for current limitation (if required) during inrush
and a complete diagnosis feature set. Now, consider a bulb
turn−on at cold ambient temperatures. At low temperatures,
the battery voltage will further droop and the inrush required
for the lamp turn on will increase− both these factors createa stringent environment for switch operation. All onsemi
high−side SmartFETs typically operate well down to 8 V
and certain devices also spec an extended battery voltage
down to 4.5 V (Refer to specific product datasheets for low
voltage operation). Section Under−Voltage Operation
describes the LV124 spec and under−voltage behavior.
While the above discussion is focused more on droops in
the battery voltage, transient overshoots in the supply
voltage are also seldom observed in automotive
applications− especially in cases like a jump start, or analternator load dump (Refer to Section Over−Voltage
Protection for details). The high−side switch should be able
to protect itself against such events. In case the load is

SupplyVoltage Monitoring

SupplyBiasing

ThermalProtection

IN
C

DEN

í
Inductive
Clamping

Control
Input/
OutputBufferCurrent
Limitation

ChargePump

Load Current Sense
Open Load/Underload Detection

OUT

CS

LOAD

NCVXXXX
GND

Figure 3. Block Diagram Highlighting the PowerFET And The Control Section

Within the power FET section, the technology can vary
between a planar and a trench gate stack for the vertical
DMOS (Refer Section Planar vs Trench FET). The choice ofsolution for a particular device is primarily governed by thenormalized on state resistance targeted in a given package(a trench FET, in general, will have a lower on−state
resistance than a planar FET for a given silicon area) whileconsidering other factors including, but not limited to,required output current drive and sense capability, and thethermal response of the die (Refer Section Understanding
the Thermal Network for details on the thermal behavior).
In addition, manufacturability and process costs are also
considered before determining the technology for a given
device. onsemi High Side SmartFETs are designed
considering that the performance parameters, protection anddiagnostic feature set, and the desired operation inapplication are not affected by the underlying technology.
It should be highlighted here that some high−side
SmartFETs are equipped with one−time programmabletrims (OTP) in the form of an array of fuses that areprogrammed at the end of production line. The “trimming”
process starts by evaluating the performance of“untrimmed” devices first. Based on any deviation from thedesired spec, these trims (or fuses), then serve as inputs to thecontrol logic, which subsequently alters the performance on
silicon to closely align it with the spec. Implementing sucha sequence allows for an improved tolerance on timing andprotection parameters such as the short circuit current limit,
switching times etc.; reduces device−to−device variability;and provides an enhanced design flexibility. The trim
structures realized on the die undergo the required reliability
stress and are ensured to adhere to lifetime operation
standards. The devices with trim capability can only be
programmed at the end of the production line and are notoffered to be programmed in field by the customers forsafety concerns. Effect of trims on the product performance
will be discussed individually for specific blocks andparameters through this document.

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switched repetitively in a PWM operation, for instanceconsidering the bulb load again where the intensity of lightis controlled with a PWM drive, the controller should
modulate the RMS voltage across the bulb (by modulating
the PWM duty cycle) to minimize fluctuations in theintensity. Another key consideration with the automotive
environment is the EMI performance in the system. With
increasing electronics content in the modern day automotive
applications, every component should be designed while
guaranteeing conformance to the required EMI/EMC
standards and minimizing the cross−coupled noise bothinternal and external to an application.
The switching characteristics of a high side SmartFET,
therefore, should account for EMI implications as well, in
addition to losses. In multi−channel devices, there should be
no interference between channels, especially when one
channel is reading fault state.
As discussed before, that chassis in an automotive
application is considered as system GND, the high sideswitch should be robust enough to handle and protect itself
in case of an output shorted to GND (a highly likely systemfault condition in high−side applications). This is usuallyachieved by limiting the load current and incorporating
thermal shutdown (Refer section Short Circuit OUT to
GND−Current Limitation and Temperature/Power
Limitation for details) in the device. AEC−Q100−012 (Refer[4]) describes the typical automotive short circuit condition
set and also quantifies the performance of a device (in termsof number of cycles) against a short circuit event.
The calculations and estimated losses presented in thissection above are exemplary and should not be extended asa representative of generic automotive condition set. In
general, cable dimensions (and associated losses), power
supply distribution fuse/relay specs, ground connections
etc. are all OEM dependent, and OEM specifications should
be referred to while making a selection for a high−sideswitch in an application.

other hand, is typically achieved with DC−DC conversion
stages that bring down the voltage required for turning on anarray. Figure 4 depicts a parallel cluster of LEDs driven bya high side SmartFET. Each array has n number of LEDs inseries. RPROTECT limits the current through the cluster. In
case one LED goes faulty and reads open circuit (ashighlighted in red in Figure 4), the other arrays will still
operate and conduct. The current through the load module,
however, will change and the high side SmartFET should be
able to indicate this change through analog current senseread−out. Since typical automotive LED loads are driven at
low current levels of the order of a few mill− amperes (Refer
Figure 5), it is challenging to precisely reflect the smallchange in current and thereby diagnose an open circuit of aparticular LED string. As will be discussed in Current Sense
and Diagnostic, the current sense accuracy reduces at smallload currents; different design schemes have been
implemented in onsemi High Side SmartFETs to improvesense accuracy (Refer section Current Sense De−Saturation
at Light Loads).

Resistive Loads
Typical resistive loads in automotive applications
comprise (but are not limited to) LEDs, heating elements inseats, transmission and engine management systems, airbag
squibs, air flow sensors etc. LEDs, or Light Emitting Diodes
are current controlled loads, −in other words the light output
is directly proportional to the drive current, or the input
electrical energy. The operation of an LED is very similar tothat of any diode; except for the semiconductor material
employed for fabrication that emits photons on electronic
excitation (quantum of light) instead of phonons (quantumof mechanical vibration) − as in a Si diode. The color output
depends primarily on the energy band−gap of the starting
material (Refer [1]).
The input drive circuit is controlled through either current
regulation or voltage regulation across the LED load. A
current is usually limited by stacking multiple arrays ofLEDs (within a module) in parallel and adding a limiting
resistor in series with the array. A voltage regulation, on the

Most automotive applications employ a PWM drive
scheme to modulate the intensity of output light; theswitching characteristics of the high−side switch should becompatible with the application’s PWM requirements.
Resistive Switching provides the details on LED switching.
LEDs have been gradually replacing the traditional
incandescent sources of light for both vehicles’ interior andexterior lighting applications. High energy efficiency(proportional conversion of electrical energy into light),
betterlight
output(output
light
is
more
directional/anisotropic as compared to bulbs that have a
diffused output spectrum), ease of drivability (LEDstypically require a low input power and a drive circuit withminimum complexity) and a longer operating life (LEDs do
not comprise of a filament, or any internal component that
may fatigue over time) are the primary motivations driving
OEMs towards LED loads as a viable alternative for
automotive lighting. A few shortcomings, for instance, theVD

NCVXXXXíIN

Control
Logic

DEN

R PROTECTCS

Load Current Sense

OUT
1

GND
2

n

GND

Figure 4. High Side Switch Driving a Parallel
Cluster LED Array

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components may be required to protect against reverse
battery conduction, overvoltage scenarios etc.

high initial cost and challenges in achieving an efficient
thermal management (especially for applications likeheadlight) still need to be addressed. Figure 5 summarizes
the typical automotive LED applications and their drive
requirements.

VD

NCVXXXX

Option2íINControl
Logic

DEN

OUT
CS

Option1

Load Current Sense

GND

Series L−R Load

GND

Figure 6. High Side Switch Driving a
Parallel Cluster LED Array

It should be noted that the clamping schemes describedabove are only indicative. Other circuit configurations withexternal clamping may also be used. However, detailed
calculations of power handling capabilities of the external
components, analysis of protection during reverse battery
and overvoltage situations as well as estimation of theassociated leakage levels should be done before employing
these topologies.

Figure 5. Typical Automotive Applications
Utilizing LEDs

Inductive Loads
Inductive loads mostly include different motors inapplications such as wipers, starters, door modules, HVAC,
fuel injectors, electric power steering, throttle control etc. In
addition, there are relays used in engine and body control
applications. While driving inductive loads, the primaryconcern is to limit the magnitude of the output voltage when
the inductor begins to discharge. All onsemi High Side
SmartFETs have an integrated protection clamp for thispurpose. The mechanism of active clamping is explained in
section Inductive Switching. Another concern with theinductive loads is the inductive discharge energy capabilityof the high side SmartFET. The product datasheets specify
the single pulse and repetitive pulse energy capability acrossa range of inductors at defined starting ambient temperatures(Refer section Inductive Switching for equations describing
the energy dissipation in the high side switch). Exceeding
the energy rating may irreversibly damage the device. The
protection features will not be active once the input
command is turned to trigger inductive flyback.
To protect the device from high energy dumps during
inductive discharge, some applications employ afree−wheeling diode and external clamping. Figure 6 shows
two such options marked inside the dashed red rectangles.
A series L−R load is depicted because all inductive loads
have an associated parasitic resistance. While parallelingacross the load, the available voltage to discharge theinductor is just a diode drop, which may lead to a prolonged
discharge. The clamp voltage in the second option will
depend on the breakdown of the external diode (thebreakdown should be lower than that of the integrated
clamps within the device). In both cases, the diode should becapable of handling the power dumped in the inductive
discharge. While implementing these designs, extra

Bulb Loads
An incandescent bulb is very different in operation thanthe LED light sources discussed in section Resistive Loads.
The bulb comprises of a tungsten filament in a glass
enclosure filled with inert gases such as argon or xenon, forinstance. The contact wires carry current in and out of thefilament supported by mounts and caps for mechanicalsupport and casing. When an electric current is forced
through the tungsten filament, the temperature of thefilament increases and eventually it starts to glow thus
emitting light. Most of the input electrical energy isconverted into heat and rest is converted into light. The light
conversion efficiency of incandescent lamps is inferior tothat in other light sources like LEDs, CFLs etc. However, a
low cost of manufacturing and availability across different
power ratings make it the most widely used light source inthe present day automotive applications.
The electrical behavior of a bulb is capacitive, with thehigh current required in the beginning for heating thefilament gradually decaying to a nominal current requiredfor operation. This initial high current is called the bulb
inrush. The resistance presented by a “cold” bulb (the term
cold describes the initial turn on, or the inrush) is lower thanthat in a steady state operation. The steady state resistancedepends on the desired final filament temperature (For mostbulbs, the desired filament temperature is 2900~3200 K).
Describing the closed loop electro−thermal operation of abulb: On the application of an electrical voltage source, thecurrent across the bulb depends on the dynamic resistivity of

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transient thermal stresses in case of system failure
conditions such as output short circuit to GND, the bulb
turn−on characteristics are impacted if the inrush required
for the bulb turn−on is greater than the internal current limit.
In such case, the device attempts to turn on the bulb with are−try strategy (refer section Re−try Strategy). The idealizedwave−set in Figure 8 and Figure 9 depicts the bulb turn−on
scenario with and without the re−try strategy.

the filament (which is a function of temperature). The
instantaneous temperature of the filament depends on its
thermal resistance (and the thermal resistance of thecontacts) and the input power (which in−turn depends on
instantaneous current), thereby making it an iterative model.
There are various models that predict this closed loop
resistivity profiles using look−up tables or empiricalequations (Refer [2]).
Typically, automotive lamps specify a rated power at anominal voltage. The nominal resistance of the filament canbe calculated as:
R NOM +

V 2 NOM

Input
Command(eq. 1)

P NOM

where VNOM and PNOM are the rated voltage and power.
Based on empirical data, the dynamic resistance can be
estimated as a function of instantaneous temperature using
an “inrush factor”:
R(T) + R NOM @

ǒ Ǔ
T REF
T

Bulb Turn−ON with
Re−try Strategy

VIN

t

IOUT

t

ILIM

INOM

const

t1

(eq. 2)t2
tBulb_ON

T is the instantaneous filament temperature, TREF is thedesired filament temperature and “const” is an empiricalconstant (Refer [3]). The latter part of the multiplier in Eq. 2
is the inverse inrush factor. The inrush current profile can be
simulated using the dynamic resistance profile assuming aknown stable voltage across the bulb.
Figure 7 below lists the applications widely using
incandescent bulbs along with the rated power of the bulbs.

Figure 8. Bulb Turn−On With Retry Strategy

Input
Command

Bulb Turn ON without
Re− try Strategy

VINt

InrushCurrent

INOM

tBulb_ON
IOUTt

Figure 9. Bulb Turn−On Without Retry Strategy

Referring to the waveforms above, tBulb_ON is the timerequired to turn on the bulb− in most cases, it is the timeinterval in which the instantaneous current drops to ~0.5*
peak inrush current. The specifications for this parameterare OEM dependent. With internal current limitation,
tBulb_ON increases as the device toggles in and out ofdifferential thermal shutdown. The root mean squared
current over the ILIM cycles and the consequential power atthe beginning of the last re−try should result in an equivalent
electro−thermal resistance profile (of the bulb) as in the casewith no re−try after a period of tBulb_ON. While selecting adevice for an application, it should be considered thattBulb_ON in the worst case condition (typically in case of low
ambient temperatures when a high inrush is required at low
available battery voltages) should be within the limits
defined by the OEM. Measured maximum inrush currents
for certain standard automotive bulb loads have beentabulated in Figure 10. Measurements were performed byforcing a stable differential voltage of ~12.8 V across the

Figure 7. Typical Automotive Applications Utilizing
Incandescent Bulbs

It is critical to understand the output current drive
capability of the high side switch with respect to the inrush
profile required for the application bulb. onsemi High Side
SmartFETs are equipped with the current limitation feature
to protect themselves in case of overload situations (Refersection Short Circuit OUT to GND−Current Limitation).
Extended operation at the current limit forces the device torepeatedly turn off and on because of the thermal shutdown
mechanisms(RefersectionTemperature/Power
Limitation). While such protection is desirable to limit the

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those switching other conventional loads such as lighting, or
resistive elements. A few instances of these differentiating
requirements include the difference in retry strategy in caseof a short circuit to ground, current sense ratio specs,
operating temperature range, number of output channels,
reverse battery protection, slew rates etc. Most of theserequirements would be discussed individually in therespective sections to highlight the required adaptability indesign as the market impetus shifts progressively towards
power distribution using smart switches.

bulb (For an accurate inrush profile, the voltage across thebulb should be stable, any parasitic resistive drops in themeasurement system may yield a low inrush current becauseof a reduction in the voltage available to turn the bulb on).
The maximum inrush depends on the electrical
specifications (primarily, electrical wattage) and thephysical construction of the bulb. The injected power in thebulb is dissipated as conducted power across the filament
and the radiated power. The physical structure of the bulb
determines the distribution of power and thereby also
impacts the instantaneous temperature and inrush profiles.

Functional Safety Overview:

With the advent of smart switches in more safety criticalapplications such as SRS (Secondary Restraint Systems,
including airbags, pre−tensioners and braking), power
distribution and transmission, among others, dueconsideration and adherence to functional safety standards
has been more important than ever. Standards such as
ISO26262 elucidate a designer’s approach to incorporate
features while conforming to safety functions described in
the standard. It should be noted that the emergence andapplication of these standards is recent which makes it
difficult for the semiconductor manufacturers acrossindustry to re−design their products in hindsight. To address
this predicament, onsemi provides product specific (oncustomer request) Failure Mode Distribution Analysis,design and package specific FIT rates, and block wise
impact on safety functions in the form of an open FMEDA.
Further, these FIT rates are provided based on multiple
standards−such as IEC 62380, SN29500 etc. understandingthat different standards may be employed across customers
for analysis. This information helps the customers design thesystem with the necessary failsafe mechanisms built in forsafety critical applications per the desired mission profile
over the intended lifetime. For specific functional safety
requests, it is recommended to contact the respective field
representatives.

Figure 10. Measured Maximum Inrush For
Typical Automotive Bulbs @ V ~ 12.8 V

It should be noted that measured bulb inrush are only
typical and do not represent the extremes of variations in thebulb performance. In addition, the inrush profiles may varyacross bulb manufacturers. Devices recommendations(against specific bulbs) can be provided on customer
requests.
Relay and Fuse Replacements
There has been evident focus on component weight andsize reduction in all automotive applications in order toachieve higher system efficiency. Also, with extensive
electrification in vehicles, there has been a growing
requirement to replace existing switching and protection
components with solid state solutions. Towards thisobjective, various onsemi High Side SmartFETs aretargeted at replacing application relays (relays are usuallyheavier and consume a significant area on the PCB). It is
recommended to refer to the product datasheets for specificsuitable applications. In addition, the ultra−low ohmic
devices (with typical RDS(ON), for instance, between
0.53 mW) are targeted to replace protection fuses and offer
an E−fuse solution. The smart high side switch creates a
closed loop protection scheme with fault reporting and theintegrated protection features protect the E−fuse fromgetting damaged− thereby reducing the replacement cost(over vehicle’s lifetime) associated with the fuses.
While the relay and fuse replacing SmartFET solutions
utilize the standard set of features available across theportfolio, there are some key application requirements thatdifferentiates the design approach for these SmartFETs fromPOWER FET AND PROTECTION
Power MOSFET

This section describes the structure and different
topologies of the power element, or the DMOS. The power
element in a high side device is comprised of a large numberof vertical N−channel FET cells laid out in parallel with thedrain as the substrate for an improved heat spreading andreduced thermal density over the drain area. Optimal design
and area considerations of the power FET are critical indetermining the key electrical performance metrics
including, but not limited to, RDS(ON), max current
capability, breakdown voltage, current sensing, temperaturesensing etc. Based on technology, parametric requirements
and geometrical constraints, a “planar”, or a “trench”
configuration could be employed in onsemi’s high−side
SmartFETs. Following is the depiction of the two structuraldesigns.

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The former design has a planar, or a lateral gate and channel
with near surface channel conduction, while the latter design
has a vertical Gate and channel going into the depth of the
body (See figures 11 a) and 11 b) for details).

Planar vs Trench FET
As discussed above, the vertical power element may beplanar, or a trench structure. The terms “planar”, and“trench” here, refer to the Gate Stack Structure which
consists of the poly gate, underlying oxide and the channel.

SourceMetal

SourcePoly

Dielectricn+n+Dielectricmetal

p -Enhpoly Si gate

p - Enh
p-tub

p-tub

gate oxide
n+

n+

p+

channeln+channelPoly Gatep+

Poly Gate

n+

Gate
Oxide

n-epi

n epi

Substrate

Substrate

Drain

Drain

A)

B)

Figure 11. Exemplary Layout Depicting the Gate, Channel and Carrier Flow in a) Planar FET and b) Trench FET

and digital sections, it is challenging to monolithicallyintegrate the two elements (FET and controller) within agiven package size. This is where technologies likechip−on−chip are utilized to optimize the “packagereal−estate”. Further, the control circuit needs to be fully
isolated from the FET using isolation structures. Following(Figure 12) is an exemplary representation of a monolithichigh−side device. Bond pads to the controller and power
FET, and various sense elements (Temp Sense, Current
Sense) are also shown in the die image below.

The conventional, or the planar FET is thermally efficientand easy to manufacture with low “mask steps”, while thetrench counterpart offers a tighter cell pitch (resulting in
better specific RDS(ON)) yielding the ability to pack morecells within the given chip “real−estate”. The following tablesummarizes the key differences in the two designs,
differentiating the performance as Hi (Good), or Lo(Moderate) against a specific characteristic.
Table 1. PERFORMANCE COMPARISON IN PLANAR
AND TRENCH VERTICAL POWER FETS
PlanarFET

TrenchFETSpecific RDS(on) − mW *mm@

Lo

Hi

Thermal Stability

Hi

Lo

Energy Capability for Similar FET area

Hi

Lo

Ease of Manufacturability

Hi

Lo

Cell Pitch

Lo

Hi

Parameter/Characteristic

Monolithic vs Dual Die Technology
A monolithic high side device has the power element(vertical N−FET) and the control circuit fabricated on thesame substrate/starting Si. The term “dual die”, on the other
hand, refers to having two separate die for power FET andcontroller within the same package. A monolithic design
renders least mismatch and offsets between the FET and thecontroller; however, at sufficiently low specific RDS(ON)levels with a complex control circuitry comprising of analog

Figure 12. Representation Of a Monolithic
High−Side Smart FET Design

It should also be considered that while most of thehigh−end SmartFET control circuitry is based on CMOS
logic, it is always challenging to incorporate a back sidedrain technology in a monolithic configuration withisolation between CMOS substrate and back side drain.

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8

AND9733/D
A dual−die technology manages the interaction between
the FET and control circuit through inter−die bonds which
require additional front−end masking, sacrificial die area forbonding, and back−end assembly and processing steps.
Because of different starting silicon for the two elements,
there are some inherent process mismatches associated withdual−die technology devices. Figure 13 depicts a high level
block diagram representation for such technologies.

Channel1

VBAT

Voltage Monitoring

SupplyBiasing

ThermalProtection
OutputControl

IN1
Input /
OutputBufferDENíInductive
Clamping
Current
Limitation

Load Current Sense
Open Load/ Underload Detection

DS
CS

OUT1

Channel2

VBB

Control and Protection
equivalent to Channel 1

í

IN2

OUT2

Bond Pads

NCVXXXXD
GND

Figure 14. Example Circuit Block Diagram for a
Dual Channel High−Side SmartFET
Power MOS

Controller

Charge Pump−Principle of Operation

An efficient charge pump design is extremely critical toachieve the desired performance from a High−Side FET. To
make sure the FET is fully turned on in the RDS(ON) region(of the output characteristic curve), the gate potential needs
to be boosted over and above the battery (drain potential) to
provide sufficient overdrive to the N−FET. A charge pump,as the name suggests, essentially acts as this boost circuit andensures maximum RDS(ON) for a given die area. Though, ina strict definition, a charge pump is integral to the control
circuit, however, since its characteristics are directly tied tothe performance of the power FET, it is being discussed inthis section.
In addition to generating sufficient gate charge, anefficient charge pump must provide a stable gate drive withsmooth turn on and turn−off characteristics, and should be
realized on a minimum die area. Typical charge pump
networks employ stages of switched capacitor boost
networks, though; this is not the only method to generatehigh voltages.
Figure 15 is a block diagram representation of a charge
pump operation. Based on the command from the input
control circuit, an oscillator produces a set of “de−phased”
output signals which then are fed into the boost network as
shown in the figure on the right. These signals control theswitches and charge the capacitive ladder. The difference inthe phases results in accumulation of charge/generation ofhigh voltage at the output of this network.

Inter−Die Bonds b /w
Controller and FET

Figure 13. Representation of a Dual−Die
High−Side SmartFET Design

The advantage with this technology is the ease in
substitution of FETs with different sizes and RDS(ON) levels
while maintaining the compatibility with the controller
across a specific product family.
Depending on the application requirements, and productfamily segment, onsemi High Side SmartFETs could be
fabricated on either of these technologies.
Multi−Channel Devices
Some applications require multi−channel devices for
operating parallel loads (Refer section Application System
Overview). Such devices are required to have independent
power N−FETs with identical parametric and behavioral
performance. Each power FET, or “channel”, has its
independent sensing elements, and the diagnostics are
typically multiplexed. A challenge with these devices is toisolate the operation of the two channels, especially in casewhere one of the channels is in a fault condition. Figure 14
below presents a circuit schematic detailing different blocks
in a dual channel High−side device, for instance.

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9AND9733/D
devices and technologies within the onsemi High Side
SmartFET portfolio. Following is a depiction of a typicalsupply voltage spec.
V (V BATT )32 −−−40 V

28 V

Performance /Lifetime Not Guaranteed
Over −Voltage ShutdownÎÎÎÎOut of Spec Performance

Normal Operation

5V
3 .2 V−0 .3 V 0 V

ÎÎIncreased RDSon
Protection active, Outputs active

V D Under −voltage , Outputs Off

Reverse Battery Protection

Figure 15. Charge Pump−Operational Block
Diagram−16 V
Performance

A charge pump output may be regulated to make surethere are no gate voltage overshoots by pulling back on the
booster, once the device is closing into complete turn−on.
This may increase the time to achieve the full−scale gate
overdrive required for the RDS(On), but improves the gate
control stability and reduces overshoots.
In some devices, oscillator frequency is trimmed in
production. This ensures tight tolerance across population
around the nominal switching times specified in thedatasheet. Different technologies (within the onsemi HighSide SmartFET product portfolio) may or may not have aninternal regulator. Depending on the gate potential required,the boost stages can be cascaded to multiply the charge ateach stage.
The internal spread spectrum is used along with theoscillator to suppress any spectral energy spikes producedby the oscillator, and ensures good EMI performance. It
should be noted that switching speed of the device is also
contingent on the rate at which the charge pump can boost
the gate voltage and how fast can the gate be “unloaded”.
While it is desirable to have a fast charge pump response, it
should be designed in a way not to infringe with the EMI
requirements.

/Lifetime Not Guaranteed

Figure 16. Device Operation Across TypicalSupply Voltage Specification

Supply Voltage

As described in the chart above, the normal operation is
guaranteed (unless otherwise specified in the productdatasheet) across a range of 5 V – 28 V. The electricalperformance (in terms of typical RDS(ON), switching speeds,
current sense etc.) and expected behavior (in terms ofprotection and diagnostics) may deviate out of spec outside
this range. Below the under−voltage threshold, the device
turns off and turns back on with a hysteresis. Reverse Battery
protection for controller and FET, as described later in thissection, is achieved through internal clamping structures
and the body diode respectively. Reverse battery thresholdfor typical devices is −16 V (sustained for a defined timeinterval), below which, the expected lifetime, reliability andperformance may be irreversibly affected. Some devices
may employ an over−voltage shutdown feature to prevent
the FET and controller from high voltage transientsobserved during events like a Load Dump; other devices
offer over−voltage protection through internal clamp
structures, and lifetime/performance of the device may becompromised if operated in this high voltage region. The
over−voltage shutdown threshold may be different acrossdevices.

Typical Supply Voltage Specs
onsemi High−Side SmartFETs have been designed tooperate across typical battery voltage range for an
automotive environment accounting for application
variations around the nominal value as described later in thissection. The operating voltage range is typically specified as
5 V −28 V, however, some specific datasheet parameters
may be characterized and guaranteed across a narrower
range, for instance 8 V to 18 V. The range and thecorresponding electrical specs guaranteed will differ across

Under−Voltage Operation
onsemi High Side SmartFETs have an under−voltage
shutdown mechanism when the supply voltage droops too
low to support device operation. This feature also prevents
the device from flagging any false/out of spec outputs ordiagnostic signals. The under−voltage threshold differs
across devices with typical spec in the range of 3 V~ 4 V. An
under−voltage shutdown event has an associated hysteresis
to prevent aberrant turn on and turn off because of a potential
noisy power source in the vicinity of threshold.

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10AND9733/D
Some of the low RDS(ON) higher power SmartFETs havean under−voltage recovery delay timer designed in. Thisfeature helps protect the device when an under−voltage
condition is triggered consequential to the battery voltage
pulled down (by its output impedance) in a high current
conduction scenario such as short circuit current limit. Oncethe device safely shuts down and the current decays, thebattery voltage rises again. In the absence of the alluded
feature, the device will turn back on again into the shortcircuit as VBATT > VBATT_MIN, overriding the built−in cool
down time (Refer section Short Circuit OUT to GND −Current Limitation). The repetitive retries can be stressful
for the die especially in case of high current devices
observing a persistent short circuit. Incorporating a delay
timer, spaces out such retries and allows the die to “cooldown” sufficiently before the next retry. Figure 20 explains
this phenomenon. Refer to product datasheets for details on
UV delay specification.

V OUT

V UV

V BATT_ Min

V BATT

Figure 17. Under−Voltage Turn Off With
Hysteresis

Such low voltage events are most likely observed in an
automotive environment in case of cranking (vehicle
starting) conditions when the battery voltage can fall to a low
value for a brief event before rising eventually. The
difficulty is compounded in case of “cold cranking” when
the battery voltage further droops at low ambient
temperatures. As per the LV 124 automotive spec forelectrical and electronic components in motor vehicles up to
3.5 tons, the supply voltage trajectory while cold cranking
is described in the following wave−set.

Figure 19. Idealized Wave−Set Depicting The
Device Behavior During Under−Voltage
Figure 18. LV124 Spec−Battery Voltage
Trajectory During a Cold Start Event

The worst case low voltage per this spec 3.2 V. Certain
onsemi High−Side devices like NCV84012A comply withthis standard, while devices such as NCV84160 haveunder−voltage shutdown triggered at 3.5 V slightly above
the minimum voltage spec of 3.2 V. The output anddiagnostic behavior in an under−voltage event is describedin Figure 19.

Figure 20. Under−voltage Recovery Delay

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11

AND9733/D
the zener breakdown, and turns the FET on by developing a
potential across the Gate−Source impedance. The load
impedance at the output limits the current through the FET.
If the FET was initially on, it will stay on unless the device
incorporates an over−voltage shutdown, as mentioned in
section Typical Supply Voltage Specs. A separate clamp
structure limits the voltage drop across the control section to
ZVD, and the ground impedance network limits the current
through these clamps. The protection diodes at the logic
inputs clamp these inputs to a diode below the GND
potential. The protection clamp for current sense, ZSense inHigh−Side SmartFETs is referenced to the supply rail. As astandard practice, onsemi recommends external clamps at
the current sense output to limit the voltage observed at the
input A/D stage of the microcontroller. Also, it isrecommended to have external protection resistors at the I/O
pins interfacing with the microcontroller to prevent the
microcontroller clamp structures from excessive current.
An extended operation in the high voltage regime may
impact the lifetime, robustness and performance of thedevice.
Device layout, terminations and metal routings are also
carefully designed for superior transient high voltage
robustness. The devices are subjected to standard ISO pulses
and rated on the max ESD transient capability per the humanbody model and machine model (Charge Device Model
Ratings are also provided for certain devices). Refer toproduct datasheets for specifications.

Over−Voltage Protection
Over−voltage scenarios, in an automotive environment,
primarily occur because of high voltage transients
conducted/coupled across the supply line (including
alternator load dump), electro−static discharge (ESD) andjump start events. In a load dump event, the battery
connection to the alternator (which provides the charging
current to the battery) is lost, and the output current becomes
unregulated, and thereby the loads connected to thealternator observe a significant increase in the supply
voltage until the alternator regulator responds and cuts backon the drive current. A vehicle manufacturer specifies thecharacteristics of the load dump pulse by defining thevoltage and time period for this pulse. In addition, standards
like ISO 7637−2: Electrical Transient Conduction AlongSupply Line Only (Refer [5]), also define specific ISO pulse
profiles and load dump test cases. Over the recent years, theuse of transient voltage suppressors at the alternator have led
to the relaxation of load dump requirements in the form ofa “suppressed load dump” spec (typically around 35 V for
12 V applications). This has allowed for scaling down thefeature size on the die facilitating low RDS(ON) devices inshrunk packages such as NCV84012A. In case of a jump
start, the vehicle battery is being charged by a high voltage
source to start the engine, for instance, the battery of a truck,or a double car battery (usually to compensate for the line
losses in the long charging cables). For a jump start, again,
the pulse characteristics are defined by the OEM. A jump
start event is less stressful than a load dump condition. Most
automotive loads are required to sustain these high voltage
events as specified by the OEM. onsemi High−Side
SmartFETs have internal clamp structures designed toprotect the FET and the controller against high voltage
spikes.

Inductive Flyback
While switching an inductive load, the voltage at theoutput terminal may observe a considerable negative swing
dependent on the rate of current decay at device turn off andthe effective inductance being discharged. The Drain−Gate
protection clamps limit the magnitude of this swing andprovide an “active clamping” of the output potential to
VBATT − VCLAMP, where VBATT is the drain potential and
VCLAMP is the breakdown voltage of the protection clamps.
Active clamping reduces the stress inflicted on the clamp
diodes and improves the heat dissipation during inductive
discharge by distributing the current density though theentire FET area. Such an approach is preferred over a
scenario where the back−side body diode avalanches (i.e.
breaks down) and discharges the inductor. For further details
on the output behavior, clamp functionality and inductiveenergy capability, refer section Inductive Switching.

High Voltage
Pulse
VD

ID_OV

ZSENSERSENSE
VBAT

OutputCS

Protection

ZVD

RDEN

Clamp

Control
Logic

Diag_EN
RIN

VIN

RCS

VOUT
ZESD

IL
GND

RGND

IGND

RL

Loss of Power Supply
If the supply connection to the drain terminal is lost, aHigh−Side Smart FET protects itself by disabling the powerdevice and the control section. Both OUT and Current Sense
read “Lo” during a loss of supply event. In a case where theconnection to the supply is lost during inductive switching(or if the wiring harness is sufficiently inductive), there has
to be a flyback path for the current to be discharged. This
path would include the protection diode for the control
section (ZVD, see Figure 19 ) limited by the external groundFigure 21. Schematic Representation ofOver−Voltage Protection Clamp Structures in a HighSide SmartFET

Referring Figure 21, there is a protection clamp for the
power FET from Drain−Gate that limits the voltage swing at
the output. In case the FET was initially off, this protection
clamp conducts if the voltage at the drain terminal exceeds

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AND9733/D
Short Circuit
Output to Battery

resistor. Since the protection diodes are not as capable as thepower FET to handle the inductive flyback energy, this may
damage the High−Side Device in cases of high energy
dissipations. In such cases, due considerations in systemdesign should be given, for instance, by including
freewheeling diodes to provide a path for the current flow
during inductive discharge.

Input
Command

VIN
InrushShort Circuit to Power Supply
A short circuit to power supply event is depicted below.
IDC

0–5V

IN

OUT
CS

ILOAD

DEN

RCS

ILOAD
t

VBATT

VD

VSHORT = VBATT
VBATT

t

VSHORT= VBATT
Sensing
Current

VOUT

t

Load
GND

RGND

VSENSE

Figure 22. A Short Circuit Event to Power
Supplyt

Figure 23. Idealized Wave−Set Describing OUT
Short to VBATT Event

The above figure describes the short circuit of VBATT line
to the two output terminals− OUT or CS. In the former case,the load will conduct irrespective of the input command.
Assuming that the drain terminal is strictly tied to the battery(i.e. no potential drops between battery and drain
connections), there is no power dissipated across the device,
but the event could be severely stressful for the load. The
idealized set of waveforms in Figure 23 describes a transient
OUT short to VBATT event occurring in case of a typical bulb
inrush. Load current and voltage increases transiently;
VSENSE drops to zero because the FET will be off during thistime. In Figure 22, it is to be noted that the current is being
measured close to the load and does not represent the output
current coming out of the OUT terminal (which would bezero in a SHORT to VBATT event).

If there is an impedance path between battery and drain
connections, it may be possible that the source potential (ina short circuit to VBATT event) is higher than drain’s,
resulting in an inverse current through the body diode. Sucha situation, though unlikely in an automotive environment,
can be very stressful for the device.
In case of VBATT short to Current Sense, the OUT terminal
and the load will operate normally, however a voltage equal
to VBATT will be observed at the CS pin which could
potentially stress the I/O interface of the microcontroller’s
A/D. As described in section Operational Methodology, it isalways recommended to put in external clamps at the CS pin
to prevent high voltages at this node. Figure 24 shows the
behavior of OUT and Sense nodes in case of CS short to
VBATT.

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AND9733/D
Short Circuit CS toBattery
Input
CommandVD
INOUT

V SENSEV BATT

CS
DEN

V IN

Load

t

R CS

GND

InrushIDC

GND
NETWORK

ILOAD

RGND

t

Figure 25. Schematic Representation of
Ground Network in an Application

V OUT

While the resistance does offer device protection, it also
raises the GND potential depending on the device’s
operating GND current. This potential, if high enough, canalter the threshold of the power FET and also limit theheadroom rail available for the operation of the analog
circuitry within the control section. There is, therefore, a
tradeoff in the selection of this resistance. A high value forthis resistance implies a low limiting current duringover−voltage/reverse battery connections, but would also
raise the ground potential significantly.
The diode helps in reducing the GND potential byshunting the resistance during normal operation, and also
blocks the reverse voltage (upto its breakdown). It, however,does not help during an over−voltage situation. Unlessotherwise suggested, as a typical value, a 1 kW resistor isrecommended to be used in parallel with a diode, or astandalone resistance of ~150 W can be used as the GND
impedance. For device specific recommendations, refer tothe corresponding product datasheets.

t

V BATTV SENSEt

Figure 24. Idealized Wave−Set Describing CS
Short to VBATT Event
Ground (GND) Operation

Recommended GND Circuit
Understanding and employing an optimal ground network
is imperative in an application involving High−Side FETs.
As a standard practice, it is not recommended to tie thedevice GND pin directly to the vehicle, or chassis GND. As
explained later in this section, this protects the High−Side
FET under some specific system failure conditions. A
typical ground network has been highlighted (in red) in
Figure 25 − a resistance connected in parallel with (optional)
diode. The resistor a) limits the current through theprotection clamps, ZVD (see Figure 21) in case of an
overvoltage event, b) prevents the power dissipation in thedevice in case of a reverse battery connection (the protection
clamps are forward biased in a reverse battery connection,
see Figure 26), or in case of loss of battery during an
inductive flyback.

Reverse Battery Protection
When the polarity/connection to the battery terminals is
flipped, a reverse current would flow through the device as
depicted in Figure 26. The protection diodes and resistors
along with the direction of reverse current have also beenshown in this block level schematic. The intrinsic body
diode of the power FET would conduct a current IREV andthe power through this diode is limited by the load itself. In
the control section, a ground current, IGND_REV is conductedby the forward biased overvoltage protection clamps, ZVD;

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AND9733/D
IIN_REV and IDEN_REV conduct through the internal
microcontroller network into the protection resistors RIN
and RDEN respectively. These currents flow through the
ESD zener clamps for the digital inputs and eventually add
to the current across ZVD. The resistors at the logic inputs,
RIN and RDEN, limit the current through the ESD structures;and the ground resistor represented by ZGND, limits thecurrent, and hence, the power dissipation across ZVD. A
reverse current, ICS_REV flows into the CS pin through thesense resistance RCS and is fed back into the negative
terminal of the battery through the forward biased
overvoltage protection diode ZSENSE.

Low−ohmic devices intended primarily for relay and fuse
replacement applications, such as NCV84008A,
NCV84004A etc., are equipped with a ReverseON featurethat turns on the output FET in an upside down configuration
when a reverse battery voltage is observed. Such an
operation helps reduce the power dissipation in the device byshunting the body diode and limiting the conduction losses
in reverse mode. Fig. 27 highlights the conduction paththrough the FET instead of the body diode. Further, a reverse
battery blocking mechanism in the ground path ensures a
low GND current (Refer to specific product datasheets for
max allowed reverse battery spec) and allows to undersize
the external GND resistor.
In addition to ReverseON, the certain devices also offer an
InverseON feature in which the body diode conduction is
once again shunted and over−riden by FET turn on if thesource potential exceeds that at the drain. Such a condition
could be prompted when the output of the FET observes a
hard short circuit to battery in the application as explainedin the section Short Circuit to Power Supply. The RDS(ON)offered by the FET in case of reverse battery, or inverse
current conduction is specified in the respective productdatasheets.

ID_REVVD

ZSENSEMCU

RSENSE
VBAT
CS

ZCL
ZVD

RDEN

Control
Logic

IDEN_REV

IREV

Diag_ENRIN
VIN

IIN_REV

VOUT
ZESD

RCS

GND
ICS_REVZL

IGND_REVZGNDFigure 26. Current Flow and Protection
During Reverse Battery Operation
ID_REV
VD
MicroController

RSENSE

ZIS

CS

ZCL

RIN

IN

IIN(REV)
RCS_ENZVD
Control
Logic

CS_EN

VBATT
ZBody

ICS_EN(REV)FET turned
ON in Reverse
Polarity

ZESD

RCS

IGND_REVGND

ICS(REV)

RGND

cFigure 27. Reverse Battery Protection with ReverseON

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15

OUT
IOUT_REVZL

AND9733/D
It is to be noted that the reverse current in the output stage
is not “blocked” in either of the cases described above;rather, the power dissipation is limited by employing FET
conduction along with external protection resistors. Certain
applications such as fuse and/or relay replacements require
an external reverse battery blocking mechanism in the
power path to prevent any current conduction in case ofreverse battery connection to protect the loads downstream.
For the maximum capability of a device (in terms of
maximum time and reverse voltage withstood) in reverse
polarity mode, refer to specific product datasheets. For loads
requiring a reverse current blocking, special care must be
exercised (for instance, incorporating reverse battery
blocking circuit elements) while working with theseHigh−Side devices. None of the protection features areavailable in the reverse battery mode.

Loss of Module
GND
Input
Command

V IN

I OUT

V OUT

The idealized wave−set in Figure 29 shows the output
behavior in a loss of GND event.
Short Circuit OUT to GND − Current Limitation
In case of an unprotected FET, if the load gets shorted out
to GND, there is nothing to limit the current and the power
dissipation in the FET (the current eventually be limited by
the device trans−conductance, or the current capacity of the
supply, or the max capability of the bond wires) which could
damage the device. To prevent such a situation of
uncontrolled conduction, onsemi High−Side devices areequipped with a current limiter logic that limits the
maximum current in a device during a short circuit event.
The maximum allowed current differs across devices andtechnologies and can be looked up in the product datasheet.
Figure 30 describes the scenario of OUT short circuit toground− when the switch on the right is closed, the OUT
node gets shorted to ground. The device observes a potential
difference of VBATT across Drain−Source (ignoring any
parasitic line resistance, and the resistance of the short).

ZSENSERSENSEVBAT

RCS_DISZCL

Control
Logic

Diag_EN
RIN
VIN

RCS

VOUT
ZESD

IGND
GND

t

Figure 29. Idealized Wave−Set Showing the Output
Current and Voltage Behavior in a Loss of GND
Event.

VD

ZVD

t

V BAT

Loss of Ground
When the GND (Ground) connection to the device is lost,
it will turn OFF the output FET and the control section. A
loss of GND could occur at the module level (where theconnection of the module GND to ECU GND is lost), or at
the ECU level− where the entire ECU, including the
microcontroller, loses the connection to the chassis GND. In
both the cases, there is no return path/reference available forthe control circuitry in the device. Any parasitic GND
connections to the module should be avoided in the ECU
design.
The block diagram below depicts such a situation.

CS

t

ZL

ZGND

Figure 28. Block Diagram Depicting a Loss of GND
Situation. The Load Remains Connected to the
Chassis GND, However, the Module GND is Lost.

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AND9733/D

0–5V

IN

temperatures. The turn on times t1 and t2 depend on thethresholds for differential and absolute thermal shutdowns
respectively (thresholds in terms of absolute and differential
temperature limits are defined and specified in the productdatasheets); and turn off times t3 and t4 depend on theircorresponding hysteresis. In addition, the heat sinking andthe thermal environment would also impact these timescales. As the device heats up, the circuit controlling thethermal shutdown also observes an increase in temperature
which could potentially result in a time lag before these timeintervals reach their steady state value.
The current fold−back feature is not universally present
across all onsemi High Side devices (Refer to specificproduct datasheets for details). For some devices, a stable
RMS current is defined post the absolute thermal shutdown
threshold with no fold−back. Such a behavior is presented in
Figure 32.

VD

VOUT = GND

OUT
CS

VBATT

DEN

Load
RCS

GND

ZGND

Figure 30. A Short Circuit Event to GroundTypically, this maximum current, ILIM, is decided basedon device’s thermal capacity (taking inputs such as size,
active silicon area, package etc.), and its intended
application. For instance, if the intended application is todrive a bulb load with a high inrush current, the ILIM would
have to be set accordingly to ensure the bulb turn−on within
the required time. Refer section Bulb Loads for more details
on driving bulb loads.
If the short to GND persists, the die temperature would
eventually rise even though the current is limited. To
preclude high temperature gradients, onsemi High−Side
FETs incorporate a restart strategy based on differential andabsolute
temperaturesensing(RefersectionTemperature/Power Limitation for more information ontemperature sensing). The idealized set of waveforms below
depicts the exemplary output current behavior in a shortcircuit event:

VIN

VIN

IOUT

t1

t3

t2

t2

Shutdown

t3

t4

Figure 32. Idealized Wave−Set Describing theCurrent Limit Behavior Without “Fold−Back”

The current limit circuitry has, in most onsemi High−Side
FETs, a slightly negative coefficient of variation withtemperature to avoid any regenerative increase in current for
device safety. Once, the junction temperature reaches theabsolute thermal shutdown limit, the peak and the duty cycleof the ILIM pulses stabilizes eventually to yield a steady state
RMS current, which is defined in the product datasheet. It
should be noted that ILIM is also dependent on the battery
voltage, (i.e. the Drain−Source voltage in this case), and isusually specified against a typical battery voltage, or a
voltage range. Some devices, like NCV84012A, may also
have an ILIM roll off at high Drain−Source voltages to reduce
the power dissipation at these high voltages. In case of a“Soft Short” when the resistance in the output conduction
path (including the resistance of the short) is high enoughsuch that the output current does not reach the max limit−
ILIM_SC1, the thermal protection in the form of Differential
and Absolute thermal shutdown and toggling would still beavailable.
Other than the two current limitation philosophies
depicted in Figure 31 and Figure 32, some devices, such as
NCV84012A, may incorporate a peak current detect basedturn−off in case of a short circuit to GND. The design
approach is explained in Figure 33, where the device shutstt1tAbsolute Temperature

ILIMSC_2

Absolute Temperature
Shutdown

stabilize to yield asteady RMS current

Fold−backCurrent

IOUT

Duty cycle and peak

ILIMSC_1t

ILIMSC_1

tt4

Figure 31. Idealized Wave−Set Describing theCurrent Limit Behavior with “Fold−Back”

As the device turns on into a short circuit, the current islimited to ILIMSC_1 (also referred to as ILIM_Hi). When the
differential temperature swing reaches its threshold (Refer
Temperature/Power Limitation), the power FET is turned
off and turns back on with a hysteresis. The device keeps on
toggling on and off with a maximum saturation current of
ILIMSC_1 until the absolute temperature of the die reaches
the maximum limit and thereafter the output current “folds
back” to a lower value, ILIMSC_2, to limit the power
dissipation, and thereby the temperature rise at high junction

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AND9733/D
off the output stage when the drain current exceeds theinternal threshold for current limit, thereby avoiding thehigher power dissipation as in case of a linear current limit
controlled by thermal shut−down.

VINtÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Load
Condition

Short Circuit to GND

IPK_H

Peak Foldback in case of High VDS
and/or Jump−Start

IPK_L

t

IOUT
tcool_down

tcool_down

Figure 33. Idealized Wave−Set Describing Peak Detect Based Current Limit
Temperature/Power Limitation

Such a design scheme becomes imperative for devices
with high current limits realized on dense technologies
where the high power dissipation (in a linear current limit)
can be detrimental for the die, and needs to be controlled bya precise peak based turn−off and timer based re−startinstead of regulating the current. The “cool−down” timer
tcool_down is defined in the control logic based on the safe
operating area measurements performed on the technology.
Most of these devices also employ a high VDS (as in case of
a “hard” short circuit), and/or high VD (as in case ofjump−start) based current limit fold−back. Further, if theabsolute or the differential temperature on the die rises overrepetitive retries, the longer cool down time enforced bythermal sensors (as explained in the following section)
prevails. The majority of devices equipped with this feature
also have the capability for trimming the current thresholds
and associated timers, offering more design flexibility anda lower device−to−device variability. Refer to productdatasheets for specifications on these timer specs, peakdetect thresholds and tolerances in the measured peaks.
With reference to relay and fuse replacement solutions,the peak detect based current limit is the preferred choice ofdesign that provides a controlled response in case of a shortcircuit event and avoids dissipating high power in the loads.
On the other hand, applications such as lighting or switchingcapacitive loads require a steady current over a duration forinrush management. This trade−off is often handled bydialing in peak current thresholds and cool down timers(using trims) pertinent to the load that the device is expected
to drive.

Absolute and Differential Temperature Sensing
Fast and accurate temperature sensing serves to protect
onsemi−High Side FETs in cases of overload and/or highpower dissipation events such as Short Circuit OUT to
GND. Exceeding device’s thermal capacity is one of themost plausible failure modes in the application, which
necessitates employing control elements that could sense
and turn off the device when the junction temperaturereaches a given threshold. Such a mechanism is termed as
Absolute Thermal Shutdown, or simply referred to as TSD(Thermal Shutdown). The typical thermal Shutdown
threshold in onsemi High−Side FETs is ~175C, unlessotherwise specified in the product datasheet. The device
turns back on after the die has “cooled down” to a lower
temperature. Thermal shutdowns have a hysteresis
associated with the turn on to avoid continual thermal
toggling around the threshold. There are often many
challenges associated with an efficient TSD design− whereshould the temperature be sensed on the die considering thelayout constraints; what should be the optimum tripping
point and hysteresis for device shutdown, generating areference circuitry with minimal variations acrosstemperature etc.
While an absolute thermal shutdown precludes the
detrimental damage in case of high power dissipation
events, it does not prevent the device from observing
temperature gradient during these events, which canseverely affect the lifetime, performance and robustness of

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AND9733/D
DTSD, the extent of thermal transient observed in each retryis attenuated and the device can withstand more such shortcircuit pulses, i.e. an improvement in device lifetime androbustness is observed. The re−try strategy is further
explained in the next section. Certain onsemi High−side
Smart FETs are also equipped with a “back−up” temperature
sensor laid out within the control section to protect thedevice from catastrophic failures.
In the context of SmartFETs with shrunk die sizes, a fast
thermal response is indispensable for ensuring the survival
off the die in case of transient high power dissipation. The
peak current detect is generally designed to meet inrush
requirements but may not be sufficient to protect the device
under certain conditions. In situations where the short
impedance is very small, and a high Drain−Source voltage
could occur, the peak current detect may not respond fastenough to the extreme thermal transient experienced by thedie. In that case DTSD will take over and ensure that thethermal transient does not exceed the capability of thedevice. Additionally, a fast absolute thermal shutdown
protection can occur when short circuit events happen atelevated temperatures. In this event, thermal sensors are
required to safely turn−off the device before the definedpeak is attained. This necessitates the sensing andpropagation delay to be optimized for a response time on theorder of a few tens of microseconds. Applications such as
power distribution often operate at higher junction
temperatures requiring a higher thermal shutdown thresholdin addition to a fast thermal response.

the device. For instance, considering a case of a cold bulb
inrush, where the ambient temperatures are low and bulb
filament needs to be warmed up sufficiently (Refer section
Bulb Loads), a high inrush current is conducted through thedevice which raises the die temperature. In a hypotheticalexample, where the device ambient temperature is −40Cand absolute thermal shutdown would occur at ~ 175C, thedevice would observe a thermal gradient of more than 200C
which may stress the device and significantly reduce thelifetime in case of multiple such events. In some cases these
thermal transients result in a thermo−mechanical overstrain
which may potentially induce mechanical damages such as
die cracks, or delamination. To prevent such a situation, aDifferential, or Delta Temperature Sensing and Shutdown(DTSD) mechanism is employed that senses the differential
between the max and min die temperatures as shown in
Figure 34.
VBB
Vref _Tjmax
TSD _Tjmax

Periphery

CenterVthx _1

TSD _deltaTj

Vthx _2
Power FET Section
Vref _deltaTj
I_TSD 1

I_TSD 2Control Section

Figure 34. Absolute and Differential
Temperature Sensing

Re−try Strategy
Idealized wave−set in Figure 35 describes the trajectory of
the thermal response in a High Side device mapped against
the output current in case of Short Circuit OUT to GND. Thiswave−set essentially adds the temperature curve to theexample elucidated in the last section.

Two sense elements are placed− one close to the center ofthe power FET (that typically observes the max
temperature), and the other close to the periphery of thepower FET. Since there is a time lag associated with thethermal wave propagation, there is always some differencein the temperature sensed by the two sensors− with thesensor is the centered sensor reading a higher temperature.
If the temperature difference exceeds as set threshold, thedevice is turned off and turns on with a hysteresis. Figure 31
depicts the exemplary electrical equivalent that emulates thethermal behavior described above. The sensed voltages arecompared with (thermally) stable references Vref_Tjmax and
Vref_deltaTj, and the output is sent to the block that eventually
makes the decision to/not to turn off the FET.
Another advantage with this Differential Thermal
Toggling is the potential improvement in the Repetitive
Short Circuit Performance (RSC). The standard from
Automotive Electronics Council− AEC−Q100−012, details
the short circuit reliability characterization of smart powerdevices. In the worst case, device switches an impedance
network representative of a short circuit in an automotive
environment, and the performance is quantified in gradesfrom A through O (For test setup details and performanceclassification, refer to AEC−Q100−012). Better
performance implies a greater number of pulses survived
under the given test and external stimuli conditions. WithILIMSC_1
ILIMSC_2
IOUT

t
t3

t2

t1

t4
TTSD
TTSD_RSTTTSD_HYS

DTJ_RST

TJ
DTJt
Absolute Temperature
Shutdown

Figure 35. Idealized Waveform Describing theTemperature Trajectory in an OUT Short Circuit to
GND Event.

At the beginning of the first pulse, with no power
dissipation, the peak junction temperature is equal to theperipheral, or the ambient temperature. As the current rises
to the max limit ILIM_SC1, the temperature rises with a more

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AND9733/D
current limit peak is detected, the device is safely turned−off
and the counter is incremented. The two parameters−nCOUNT and rCOUNT are specified in the respective productdatasheets. The first nCOUNT retries are spaced relatively
closer (implying tcool_down < tauto−retry) in time toprovide the required inrush for capacitive loads. In case acurrent limit is still detected after nCOUNT retries, the shortis then classified as persistent and retries are spaced at longer
intervals in time to prevent repetitive over−stress. Once thecounter increments to nCOUNT+rCOUNT , the output stage is“latched−off” and disabled until one of the counter reset
conditions is met. Figure 36 depicts the enable based counter
reset method where the fault counter is reset if device isexternally disabled for t > tEN(Rst) (Refer datasheets fortiming specification). There may be other reset conditions
specific to a device been elaborated in the respective productdatasheet. While the figure uses short circuit current limit as
an example, the same principle also applies to retries in caseof thermal and/or differential thermal shutdown. In devices
with timer−counter based retry, the time tcool_down isreplaced by (typically longer) thermal hysteresis driventurn−off time. Further, the counter is also multiplexed
between the two protection schemes. This implies that thecounter value is not over−written as the two protection
mechanisms interchangeably control the output stage.

pronounced increase at the center of the die. When the
difference in the two temperatures, DTJ, exceeds the defined
limit (usually 60C in onsemi High−Side Devices, unlessotherwise specified), the power FET is turned off until thedevice cools down by DTJ_RST , and thereafter restarts withanother ILIM_SC1 pulse. The temperature at the edge of thedie increases with each retry cycle as shown in the
waveform. Once the peak junction temperature reaches theabsolute thermal shutdown limit, TTSD, the device turns on
and off with the hysteresis− TTSD_HYS. As explained in
section Short Circuit to OUT to GND−Current Limitation,
not all onsemi High Side FETs have a current fold−back, andthe waveforms shown here are just for instance.
The turn on times and hysteresis are chosen with a
trade−off between the max temperature transient observedby the die (it is desirable to have a short retry period to avoid
large temperature swings), and the ability of a device to turnon a bulb within the given time (long retry periods aredesirable to deliver the required bulb inrush with least
number of retries).
In contrast to the thermally controlled retry strategy,
devices with peak detect current limit employ a fixed timer
based retry strategy as discussed before. The number of
retries can be indefinite, or internally limited via a counteras in NCV84012A. Figure 36 presents an idealized wave−set
in case of a timer−counter based retry strategy. Once at EN (Rst )

V IN
Load
ConditionÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

t

Short Circuit to GND

I PK

I OUT

t
t cool _ down

Fault
Counter0t auto _ retry

1

2

n COUNTt auto _retry

n+1

n COUNT +r COUNT

0

Figure 36. Idealized Wave−Set Describing Timer−Counter based Short Circuit Retry Strategy

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AND9733/D
recommended to externally limit the same by the
microcontroller in the application. The repetitive toggling of
the device impacts the long term reliability and lifetime.
While there is no maximum cap for the number of allowed
retries, some estimates based on Coffin−Manson analysis
specific to the application can be provided on special
requests. For certain applications, the load is permanently
disabled by the microcontroller if the short persists after agiven number of ignition cycles.

Building on the relay and fuse replacement discussion
through this note, a short circuit event in such applications
does not require the device to retry− successive retrying inshort circuit can be catastrophic for the loads connected in
the vehicular network through this smart fuse. Having
internal trims for the number of retries eases off the design
approach for the retry strategy in onsemi SmartFETs where
the nCOUNT and rCOUNT can be trimmed to “1” and “0”respectively in production to cater to a fuse replacement
solution.
If the number of retries in a short circuit to GND event is
not internally limited, Figure 36, for example, then it iswww.onsemi.com
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AND9733/D
APPLICATION INTERFACE AND CONTROLPin Interface

The control logic block includes the gate driving (chargepump) circuitry, protection and diagnostic control of thepower FET. The input commands and output signals fromthis block may differ within the family of onsemi high side
devices (as explained further in this section). The only directinterface input to the power FET is VD (or the battery
connection) and the direct output is OUT, or the source
connection to the power FET. Following circuit diagram
describes the recommended interface to these pin terminals.

VBATT
ZVD

CSUPPLY

CVD

GND

VDD

SPU

RIN

RPU

VD

OUT

IN
OUT

RPD

RDEN
Micro
Controller

OUT

COUT

ZL

DEN

RA/D

RSENSE

A/D

CS
GND

VSS
CCS

ZCS

RCS
RGND

Figure 37. Recommended Pin Interface to onsemi High Side SmartFETs

rail−to−rail voltage for the device operation. This could
especially be challenging under low battery voltage
conditions such as cold cranking, making it difficult for thedevice to operate with nominal protection and diagnostic
capabilities. Section Typical Supply Voltage Specs
mentions the typical operating voltage ranges. Further, incase of sufficient potential drop between VBATT and VD, an
output short to VBATT can create an inverse current scenario
which could be highly stressful for the device.
The resistors RIN (at the input pin) and RDEN (atdiagnostic enable pin) are interfaced between the
microcontroller and the high side device. It should be notedthat different devices within the onsemi high side SmartFET
family may have different topologies for enabling/disabling
the diagnostic output (Refer CS Enable/Disable Logic)
through a digital signal, and the term DEN has been used forgeneric purposes here. Further, based on the specific device
topology, the input command could also be active−high or
active−low. Unless otherwise mentioned, an active highdigital command will be considered through this document
while referring to the input signal. The resistors in series
with these digital inputs protect the microcontroller output
in case of an over−voltage event and also limit the current
through the internal ESD structures, ZESD to these pins
(Refer Figure 26) in case of a reverse battery operation. In
addition, these resistors also prevent the high−side device

As in a typical automotive environment, the extremes inthe supply voltage VBATT are limited by a stack of zener
protection diodes (ZVD), and a capacitive network(CSUPPLY/CVD) filters the transient surges on the supply
line. Although onsemi high side SmartFETs do offer
overvoltage protection (in cases like transient load dump, orjump start), this circuit interface is neverthelessrecommended to avoid device operation under abnormal
supply voltage conditions. Further, when the voltage spikes
at the drain terminal are inflicted because of an inductive
flyback consequential to fast output current discharge suchas in case of a current limit turn−off, the capacitive networkat the drain helps dampen the oscillations and reduce thefeed through to the internal digital circuit aiding a stabledevice operation. The absence of these capacitors may
increase the susceptibility of the device to the voltage
transients which can also affect the performance such as
in−built digital timers. In many cases, the EMI performanceof the device is also specified under the assumption that theexternal drain and output capacitors are connected. For
maximum impact, these capacitors are recommended to beplaced close to the drain pin on the application PCB, as
compared to the zener voltage suppressors, which are
typically placed close to the alternator. The parasitic cable
impedance in the VD connection to the supply should be
minimized in the application as it reduces the available

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AND9733/D
peripheral network at the OUT pin consisting of the switch
SPU and resistor RPU serve for off state open load
diagnostics. The resistor RPU needs to be sized inaccordance with the leakage resistance for the specificdevice, and the switch eliminates the power dissipation (orthe leakage current) through this resistor when off state open
load diagnostics is not required. For details on the resistor
selection criteria, see section Open Load Diagnostics. The
pull down resistor, RPD is employed to diagnose a shortcircuit to battery event and differentiates this fault from off
state open load through output voltage read−out (Refersection Short Circuit to Battery). Specific recommended
values for these resistors can be referred to in the productdatasheets.
Many SmartFET’s have “No Connect (NC)” pins, often
present to ensure package compatibility across family of
devices (such as single and dual channels). While in mostcases these pins are not connected internally and do notaffect performance of the device, some devices utilize thesepins especially for digital trim programming in production
and design mode analysis. In these devices, it is always
recommended to short these pins to GND through aprotection resistor to avoid any inadvertent operation.
Specific datasheets should be referred to for recommended
connections to NC pins.

from finding any parasitic grounds (throughmicrocontroller) in case of a loss of ground situation. Whilethese series resistors do offer protection as described above,it is important to have an understanding of how to size these
resistors. The sizing implications are mainly driven by the
microcontroller drive current capabilities, and the required
input current and voltage to turn on and turn off the device
input. A bigger resistor would imply a bigger potential drop,and consequently the microcontroller should output a higher
voltage to ensure sufficient turn−on voltage for the device
input stage. Likewise, while reducing the resistor value, theoutput voltage level should guarantee a proper deviceturn−off.
V OUT_MICRO + V RIN ) V IN ) V GND(eq. 3)where VOUT_MICRO is the output voltage from themicrocontroller, VRIN is the potential drop across the series
resistor RIN, VIN is the input voltage required at the input
stage of the high side device (for turn on/turn off) and VGND
is the potential drop across the ground impedance. A similar
equation applies for the DEN pin as well.
In some applications, protection clamps are also placed at
the device input pins (specifically where the output stage ofthe microcontroller can observe surges or where theprotection structures within the microcontroller are notpresent). For specific recommended values for these
resistors, refer to product datasheets.
The network interfaced to the current sense pin consists ofa sense resistor RCS, a current limiting (through the zener
clamp) resistor RSENSE, a zener clamp ZCS to limit thevoltage swing at CS output (the voltage at CS output can rise
all the way up to VD) and an RC noise filter for the
microcontroller’s input A/D stage. The analog current sense
output as well as the fault state output current from the CS
pin is converted into a voltage across RCS and subsequently
digitized by the micro’s A/D stage. For further details on theselection of RCS and the behavior of CS output, refer tosection CS Pin Interface and Sensing the Current.
The GND pin is recommended to be connected to aparallel combination of a diode DGND and a resistor RGND
(in some cases, only a resistor can suffice as the GND
network depending on the value of resistor chosen). The
GND network protects the device in case of an overvoltage
event and also limits the current in case of a reverse battery
connection. The details of the GND circuit operation and thesuggested values for the diode and resistor are mentioned in
section Recommended GND Circuit. A loss of groundsituation is also depicted in section Loss of Ground.
The output terminal is connected to the desired
application load ZL with an output capacitor, COUT, toprotect the load from transient output voltage swings. The
value for this capacitance should be chosen not to interferewith the typical switching frequencies for a given device(generally recommended in the product datasheets). Typical
automotive loads and the corresponding output behavior aredetailed in section Application Environment and Loads. The

Input Control and Hysteresis

The application microcontroller commands the input (andthe diagnosis enable/disable pin) with digital (standard logic
level) signals which then drive the output FET and also
control the diagnosis through current sense. The block
diagram in Figure 38 depicts the control and conditioning of
this digital command inside the device.
VBATT

VD

Reference
Bias

Control
Logic

IN

VIN
HYST

Input
Filter

OUT

ESD
Clamp

RGND

Figure 38. Block Diagram Showing Input
Control and Hysteresis

The first stage in signal conditioning is to filter any
transient noise associated with microcontroller’s output
with a low pass filter stage. An integrated ESD clamp zener

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AND9733/D“guaranteed” to be turned off only below VINL_MAX.
Therefore, it is imperative to reiterate that all signal levels
between VINL_MAX and VINH_MIN should be avoided in theapplication. For typical VIN_HYST levels, refer to productdatasheets.
After the hysteresis block, a switch controls the command
fed into the control logic block which then drives the charge
pump to turn on/off the output stage. In addition, this signal
is also fed to the current sensing control for diagnosis. A
similar circuit block as in Figure 38 is employed for the
diagnostic enable/disable (DEN) signal as well.
The circuit interface in Figure 37 depicts a single channel
device. In case of a multi−channel device, the input control
circuitry is duplicated over all channels within the device.
The recommended peripheral circuit stays same for inputs
and outputs across channels. The analog current sense
output is generally shared by all the channels and a digitalchannel select input (see product datasheets of multichannel
devices for details) multiplexes the sense outputs ofdifferent channels into a single CS output. The
microcontroller interface to this digital channel select input
and the controlling circuit block (inside the device) is
identical to other digital inputs.

(referenced to the ground terminal) limits the voltage swings
observed at the input terminal. In case of an overvoltage
event, the digital inputs are clamped to a diode drop less thanthe GND potential, while in a reverse battery situation these
zeners break down and the current is limited through theseries gate resistors (Refer sections Over−Voltage
Protection and Reverse Battery Protection for details on
overvoltage behavior and reverse battery protection
respectively). A hysteresis circuit (comprising of a
MOSFET with an adjustable potential divider stage at itsgate) conditions the input command and drives a switch as
shown in Figure 39 (the hysteresis circuit is included in theblock marked as VIN_HYST). Hysteresis prevents the device
from repetitive switching most likely in case of a noisy input
signal (some low frequency noise remains unfiltered after
the input filter stage).

SWITCHING CHARACTERISTICS
Optimal switching performance is the primary
operational requirement from any MOSFET. This includes
achieving the desired switching speed with sufficient drive
capabilities for the desired load while minimizing the losses
during switching. onsemi High Side SmartFETs aredesigned to cater to switching requirements over a range andtypes of loads. This section deliberates the behavior of aHigh Side SmartFET while switching typical applicationloads− resistive, inductive and bulb (capacitive) loads.

Figure 39. Input Signal Level and Hysteresis

As explained in Figure 39, two primary logic levels aredefined for the input signal. VINL_MAX is the maximum low
level voltage to ensure output FET turn off; and VINH_MIN
is the minimum high level voltage to ensure output FET turnon. These levels are mentioned in the respective productdatasheets. Any input level in between these two creates an
undefined state and the output FET could either be on or off.
Such a situation should be avoided− in other words, an input
signal level between VINL_MAX and VINH_MIN should be
avoided by application microcontroller. Figure 39 also
explains the concept of input hysteresis. In case of input
signal noise, an absence of hysteresis can cause the transistor
to switch on and off repetitively as it crosses the thresholdrequired for turn on. Adding hysteresis ensures that thetransistor stays on until the falling transition of the input
signal crosses over the hysteresis threshold thereby
preventing the unnecessary switching and associatedswitching energy losses. It should be noted that thehysteresis threshold defined in Figure 39 (VIN_HYST) is only
typical and could vary within the window defined by two
logic levels. While the output FET should turn off below thehysteresis threshold on a falling input transition, it is

Resistive Switching

Resistive loads are the most typical of an application
environment; and with the increasing use of LEDS for
automotive lighting solutions (both interior and exterior
lighting− refer section Resistive Loads), the thrust forresistive loads is compounding. While resistive loads do not
associate with the asymmetrical polarity challenges (as ininductive loads, relays etc.), they often require higher
switching speeds with dynamic current sensing anddiagnostics− for instance, PWM of an LED load. Further, if
the same device is used to switch alternatively between ahigh wattage bulb load and a string of LEDs, the transition
from one load to another should be smooth while
complementing the high power drive capability (for a bulb)
with a precision current sensing required for an LED load.

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AND9733/D
datasheet. As mentioned before, while switching loads, thecurrent sensing and diagnostic delays need to be considered(See Figure 56 for current sense timing parameters). The
PWM frequency and duty cycle should be set such that thedevice is able to output the proportional sense current andreport fault, if any, with each cycle of the input command.
onsemi’s family of high side SmartFETs meets theswitching speed requirements for most automotive loads.
The switching energy losses primarily depend on the
charging and discharging of input (CGS), transfer (CGD) andoutput (CDS) capacitances. These capacitances are acontribution of the parasitic device effects and depend
mainly on the geometrical feature size. A transistor with ahigher active Si area may have a lower RDS(ON) (andtherefore lower conduction losses) but the switching losses
could be significant because of increased device
capacitances. All these factors are accounted for in during
the design and layout stages to achieve the optimal
performance. In addition, these losses also depend on theapplication frequency and should be considered by the OEM
while defining a requirement specification.
While a higher switching speed helps in reducing
switching losses and also satisfies the PWM requirements,
it is not necessarily always desirable in the application
because of a possibility of infringing with EMI/EMC
requirements. For this reason, the speed of the device iscontrolled and sometimes even compromised to ensurecompliance with the required EMI performance. This slew
rate control is better conceptualized in Figure 41.

The idealized wave−set in Figure 40 depicts the output
behavior under resistive switching:
VIN

ton

td_on

VOUT

toff

td_off

90%

90%

70%

70%

SRon

SRoff

30%

30%

10%

10%

t

Figure 40. Input and Output Transitions During
Resistive Switching

The time intervals and the corresponding timing markers
on the voltage waveform trajectories have been indicated in
Figure 40. The definitions are as follows (unless otherwise
mentioned in the datasheet):td_on: the delay time from the rising edge of input command
to 10% of output voltage
ton: total turn on time from rising edge of the input command
to 90% of output voltage
td_off: the delay time from the falling edge of input command
to 90% of output voltage

VIN

toff: total turn off time from falling edge of the input
command to 10% of output voltage

ton

toff

t

SRon: Slew rate from 30% to 70% of output voltage during
turn on

td_on

VOUT

SRoff: Slew rate from 70% to 30% of output voltage during
turn off
The relative difference between turn on and turn off slew
rates is referred to as slew rate matching. Certain onsemi
High Side Devices, for instance, NCV84012A,
NCV84008A etc. have a sleep mode feature incorporated(typically when both input command and diagnostic control
have been deactivated for a given time) to reduce the leakage
levels. The turn on times in cases where the device isactivated from a sleep mode may differ from the usual turnon times. Refer to respective product datasheets for
specifications on switching time intervals with sleep mode.
The turn on and turn off delays are mainly associated withenabling and disabling the charge pump, and the slewing is
generally controlled with an active circuit at the gate of thepower FET. These timing parameters are specified against
a set of conditions such as load resistance, battery voltage,
ambient temperature etc. The conditions and the timing
specifications can be looked up in the specific producttd_off

90%

90%

70%

70%

SRon

SRoff

30%
10%

30%
10%

t

Figure 41. Input and Output Transitions With
Slew Rate Control During Resistive Switching

As depicted in the waveforms above, the output FET turns
on relatively slowly as the charge pump is enabled. This isfollowed by a fast gate charge ramp up, and as the output
reaches its steady state level (i.e. the transistor is fully on),charge pump regulates and pulls back on the gate charge to
avoid any overshoots. The regulation mechanism may or
may not be present depending on the specific control
technology (Refer section Charge Pump−Principle ofOperation). At turn−off, the gate charge is removed rapidly
as the charge pump is disabled in the beginning which iswww.onsemi.com
25

AND9733/D
followed by a slow controlled discharge. These different
regions of fast or steady gate charge (and discharge) render
design flexibility in controlling the EMI performance whileachieving the desired switching speed. It should be notedthat the slope transitions in Figure 41 have been indicatedrather conspicuously to conceptualize the mechanism. In
practice, output voltage transitions are smooth and do not
involve any kinks or dips.
In addition to the EMI implications cited above, somedevices exhibit reduced slew rates (turn on slew inparticular), at loads heavier than nominal. These loads are
generally observed in the application during short circuit
events− could be a “soft short” or “hard short” depending on
the short impedance. Slowing down the turn on trajectory
provides an improved control over the current limit profilethat allows to reduce and (in some cases) even eliminate
oscillations while attempting to regulate the output stage athigh current levels. The switching speed (and consequently
switching energy) and slew rate matching at short circuitloads, therefore, are often traded−off for a stable operation
with no overshoots/undershoots in current limit.
In
fuse
replacement
applications,externallyprogrammable slew rates are seldom required todifferentiate the turn on (after cranking) from a short circuit
event. Reducing the slew rate externally at power on
provides the inrush required to energize the capacitive loads
downstream. A fast turn on slew, on the other hand, leads tothe output current ramped up quickly to the short circuit
threshold which permanently latches off the output stage.
While onsemi High Side SmartFETs currently do not offer
an externally programmable slew rate feature, the slew
control at heavy loads discussed above is a step in the
direction of targeting fuse replacement solutions. Since afuse is rarely required to switch (periodically) in theapplication, the switching speed and PWM requirements fora fuse replacement SmartFET are not as stringent as that forother conventional applications.

VD
PowerFET
Drain to Gate
Clamping (ZCL)
VBATT

VDS

VIN

Control
Logic
VOUT

IL
L

IGND

RGND

RL

Figure 42. Inductive Switching Block Diagram

When the input command is turned High, the inductor getscharged to a peak current determined by the magnitude ofinductance, drain potential VD, line resistance, RL and the“dwell time” (time for which the device is turned on). The
output potential at this time is VD−VDSON. Once the input
command is turned Low, the output current starts to decay,
and a voltage is developed across the inductor that opposes
this current decay. Since the discharge voltage and current
in an inductor bear opposing polarities, the output terminal
observes a negative swing. In the absence of overvoltage
protection clamp diodes, this swing will be limited by thebreakdown (or avalanche) of the body diode. Such asituation can be stressful for the device as a confined area on
the die (in the vicinity of the body diode) will conduct a highcurrent density and can lead to the generation of localized“hot−spots” on the die. Further, avalanching the body diodeeach time during inductive switching may compromise its
long term reliability. To avoid this, an active Gate−Source
circuit is enabled at the time of device turn off, and controls
the conduction path comprising of Drain−Gate clamp
diodes, Gate−Source impedance and the inductive load.
When the voltage across the Gate−Source impedance
reaches the required input threshold of the device, the output
FET turns on and conducts the current discharged by the
inductor with the return path through the battery and supply
ground. This mechanism is termed as “active clamping” andthe current density in this case is distributed across the entire
active area of the power FET which prevents the formationof any local current constriction channels. In applications
where the output voltage is sensed by the microcontroller,
active clamping limits the magnitude of output voltage

Inductive Switching

Relays and inductive loads are integral to the operation ofmost automotive applications. Inductive loads do not switch
with the same polarity on the output terminal and the inverse
voltage swing at the output terminal needs to be limited
during the inductive flyback event. This is typically doneusing the Drain−Gate over−voltage protection diodes, ZCL.
Figure 42 is a block diagram representation of an inductive
switching scenario.

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26

AND9733/D
observed by micro, thereby protecting its I/O interface. If thebattery during an inductive flyback event is disconnected (orthe battery connection is lost), the return path in an inductive
discharge would consist of the protection diodes for thecontrol logic circuit and the device’s ground impedance
network. This circuit path is not designed to conduct suchhigh power events and may get damaged. Such a case can be
avoided by employing free−wheeling diodes for providing
a return path for inductive discharge.
The idealized wave−set in Figure 43 describes the output
current and voltage transitions while switching an inductor.

VINt
td_off

VBAT

t

VOUT
td_on

ZCL

IOUT

t

Figure 43. Input and Output Transitions During Inductive SwitchingThis effective inductance is greater than the physicalinductance L, and the energy discharged is calculated as:

The waveforms above neglect any parasitic line resistanceas well as the internal resistance of the inductive load. In caseof a significant series resistance, the output current
trajectories would not be linear and exhibit an exponential
curvature marked by a time constant, t = L/R. It should be
noted that the output voltage attained in the reverse direction
is a function of battery voltage:
V OUT + V D * V ZCL

E+(eq. 4)

1
2@ L @ I pk
2

t av +

E + V CL @

Ť

V ZCL
V D * V ZCLŤ(eq. 7)

Ť ǒ

I pk @ R
L@ In 1 *V D * V ZCL
R

L
RL

@
2

ǒ

ǓŤ

(eq. 8)

ǒV D ) ǒV D * V ZCLǓ @ In 1 *I pk @ R
V D * V ZCLǓ(eq. 9)(eq. 5)The energy ratings are specified in the product datasheets
for a single pulse inductive discharge as well as over a
Repetitive Clamp (RCL) event. An RCL test subjects thedevice to repetitive clamp cycles while discharging an
inductive load. In the context of onsemi High Side
SmartFETs, the switching frequency is sufficiently low toensure that the die “cools down” to ambient temperature at
the beginning of each charging cycle (Refer Section
Understanding the Thermal Network for understanding theimpact of inductive switching on die temperature). The RCL
rating, in terms of max current switched at a given

Where Ipk is the peak current inductor is charged to. In theapplication, however, the discharge is not ideal, and thepower supply stays connected all through the charge anddischarge cycles. This reduces the available voltage todischarge the inductor, and consequently increases thedischarge or the avalanche time, tav. This effect isconceptualized in an “effective inductance” discharged
where
L eff + L @ŤThe calculations and equations above do not include theeffect of series line resistance. Taking that into account, theavalanche time and the inductive discharge energy are statedas follows.

Where VZCL is the breakdown voltage of the overvoltage
protection clamp diodes.
The inductive discharge capability of a device is usuallyquantified by the metric− SCIS (Self Clamped Inductive
Switching) energy. In an ideal inductive discharge event,considering no losses, the energy can be calculated as:
E+

Ť

V ZCL
1
2
@ L @ I pk @V D * V ZCL
2(eq. 6)www.onsemi.com
27

AND9733/D
inductance and ambient temperature, is defined over 1
million cycles of operation. Intuitively, this rating is lower
than the Single Pulse Inductive Switching rating. These
ratings are typically plotted over a range of inductors andtemperatures to help the customers select the inductive load
and the corresponding drive current accordingly (Theenergy dissipated across the device at a given inductanceshould not be more than the rated energy per the datasheet).

Input
Command

VIN

t

IOUT

t

ILIM

INOM

Bulb Switching

Bulbs in principle emulate the transient output
characteristics of a capacitive network with the current
being maximum at the time of turn on gradually decreasing
towards the steady state current determined by the resistanceat full turn on. The high side device should be able to support
the required inrush profile for bulb turn−on. A change in thefilament resistance (through the turn on period) gives rise toa non−linear impedance profile. Section Bulb Loads
describes the electrical characteristics of typical bulb loads−
for instance, wattage, inrush etc. and also suggests thesuitable onsemi High Side SmartFET to switch specific bulb
loads. The phenomenon of bulb inrush and the strategies forhandling inrush− with, or without auto retries are also
explained in section Bulb Loads.
The dynamic switching behavior and operating mode ofa high side FET during a bulb control is quite different fromthat in case of LED or inductive loads. Although bulbs havesame output polarity (at turn on and turn off) similar to a
resistive load, the retries during the inrush phase have thedevice working in linear mode with the maximum current
limited to ILIM. With the last retry, the device transitions
from linear to RDS(ON) mode as the current approaches thenominal current. This transition should be smooth and avoid
any jitters/abrupt output level or current changes to avoid
undesired flickering of the bulb post inrush. The situation isdepicted in the idealized wave−set on the right showing theoutput current transitions during a bulb turn on.
At t = 0, when the device is turned on, the current gets
limited to ILIM and the device “regulates” as it turns on andoff with differential thermal shutdown threshold andhysteresis (refer section Temperature/Power Limitation) for
the subsequent retries. The gate of the output FET iscontrolled by the ILIM control circuit that overrides the
charge pump. The last couple of retries have beenhighlighted in red, and this is where the device stops
regulating and charge pump takes over the gate control. The
ILIM control circuit is expected to switch in and out without
associating any crosstalk with the charge pump operation.

tBulb_ON

Figure 44. Output Current Transitions in
Re−Tries During Bulb Inrush

While differential thermal shutdown reduces the transient
thermal stresses on the device, it increases the time required
to sufficiently (typically when the load current decays to half
the inrush) turn on a bulb with re−tries. In devices where theshort circuit is primarily controlled by current limit peakdetect methodology (Refer Section Short Circuit OUT to
GND − Current Limitation), the bulb turn on times may
further be impacted to ensure safe operation of theSmartFET. The peak current threshold and cool down times
are therefore designed to balance the trade off between
recommended bulb inrush requirements while guaranteeinga safe operation of the device. The high side device should
be selected appropriately such that it is able to turn on thebulb in the required upper limit for the turn on time (refersection Bulb Loads).
Since the time required to turn on the bulb will also dependon the line parasitic impedance which may change acrossapplications, it becomes difficult to recommend a SmartFET
specific to a bulb. To circumvent this challenge, turn−on
times are measured in a standard circuit configuration per
Figure 45. The voltage at the drain of the SmartFET is
actively regulated at the desired reference level by a highprecision fast op−amp driving the high side referenced
regulator. The parasitic resistance is minimized by using
thick and short cables for drain and output connections. The
active circuit eliminates any drop in the drain voltage as
observed by the SmartFET as it is conducting high levels of
inrush current. The schematic does not describe connections
to other terminals such as CS, DEN, GND etc. Theseterminals need to be interfaced per the standard application
circuit and will not have any perceptible impact on the inrush
timing. Recommendations are always made per the worst
case scenario where the bulb observes an ambient

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28

AND9733/D
temperature of −40C and the DUT (Device Under Test) is
placed at room temperature ambient. It should be noted that
this measurement circuit is employed only to allow for astandardized bulb recommendation across the family of
devices, and is not the required circuit in the actual
application. Refer Section Application Interface andControl for details on recommended application circuit.
Another consideration while switching bulbs is thepossibility of an intermittent loss of or dip in the supply
voltage. The high side switch should be able to “react” fast
post the battery voltage reaches the nominal value, andsource in the required inrush profile with minimal delay toensure bulb turn on in desired time.

VD
VBAT
SENSE
FET

IN

POWER
FET

IFAULT

OUT

Fault ?
DEN

GND

CS

R LOADR CS
RGND

Figure 46. Block Diagram Depicting the Current
Sensing Mechanism

Sense Cell

OUT
GATE

VD
Figure 47. Current Sense − Device Operating
Principle

Figure 45. Bulb Inrush Timing Measurement Circuit

As stated above, the power and sense FETs have common
gate and drain terminals; the major challenge in a current
sense design is minimizing the difference in the source
potentials. In theory, a true current mirror operates in current
regulation mode with minimal dependence on
Drain−Source voltage (such that the sensed current is solely
dependent on the relative aspect ratios of the two FETs).
However, for the applications under consideration here, thepower FET is required to be turned fully on as a switch, witha strong dependence of current on the Drain−Source voltage.
Thus, any offset in the source potentials will deviate thesensed current (or the Sense Ratio), from its expected value.
The block diagram includes a high gain op−amp that forces
the two sources at the same potential. In an ideal scenario,
when there is no offset between the source potentials, theratio of the currents in the Power and Sense FETs is directly
calculated from the geometrical (Active Area) ratios

CURRENT SENSE AND DIAGNOSTICS
onsemi High−Side Smart FETs are equipped with ananalog current sense (CS) output. This output serves two
objectives− a) Depicts the level of output current flowing
through the power MOS and b) Indicates an existing fault
condition, if any (For details on fault conditions, refer tosection Current Sense Behavior in Normal and Fault States).
Operational Methodology

The current in the power FET is sensed through a “Sense
FET” integrated within the device. This Sense FET isusually a small mirrored branch−out from the power FET, or
the DMOS, with the drain and gate terminals tied to those of
the DMOS. Figure 46 is a block diagram depicting thecurrent sense mechanism, and Figure 47 describes thedevice principle (using a trench−FET as an example):www.onsemi.com
29

AND9733/D(represented by the constants K1/2 in Eq. 11), given the two
FETs have perfectly matched electrical, physical andstructural characteristics. However, such a design is hard toachieve in practice. The offsets in the analog circuitry(primarily, the op−amp), and the transistor mismatches
associate an error factor with the absolute sense ratio, whichbecomes more pronounced at light loads (Refer section
Current Sense Accuracy Improvement at Light Loads andCurrent Sense Calibration)
2

I LOAD + I OUT + K 1 @ ǒV OV1Ǔ @ ǒ1 ) aV DS1Ǔ2

I SENSE + K 2 @ ǒV OV2Ǔ @ ǒ1 ) aV DS2ǓSR +(eq. 10)Figure 48. Exemplary Layout Highlighting Current
Sense Block And Sense FeedI LOADI SENSEThe dashed rectangle in red encloses the “Sense Feed” thatbridges the sense transistor to the control logic section. Any
parasitic conduction paths between the two FETs (Sense andPower) should be taken into consideration during the design
stage. Intuitively, a device with higher sense ratio is difficult
to layout and fabricate than that with a small sense ratio
because of smaller geometries associated with the Sense
FET.

KX is the constant accounting for device’s physicaldimensions,
VOVX is the overdrive voltage
a is the channel length modulation coefficient
VDSX is the drain−source voltage drop, and
SR is the sense ratio.

CS Pin Interface and Sensing the Current

As shown in Figure 46, the current flowing through theSense FET is measured as the voltage across the sense
resistor, RCS. The load current is then estimated using thesense ratios specified in the product datasheets under
different conditions. In case a fault condition exists, thefault−state current source over−rides and CS pin reads afault−state voltage. The fault state current, (and thecorresponding voltage measured across RCS) is typicallyhigher than the maximum sensed current under normal
operation, to distinguish the fault condition from no−fault
condition. Both the normal state and fault state sense
currents exhibit a dependence on temperature (with aslightly negative coefficient of variation) and battery
voltage. As the battery voltage droops, the current source,
driven by the op−amp output, runs out of the required“head−room” and fails to regulate eventually. This results in
the reduction of sense current. The next section describes theselection criteria for the sense resistor to ensure the desired
behavior from the CS output. The Diagnostic Enable (DEN)pin enables/disables the current sense output and could beeither an active high or active low logic input depending on
the specific device (Refer section CS Enable/Disable
Logic). In addition to an efficient circuit design, a reliablecurrent sensing also requires an optimal (and stable) layout.
Highlighting (in red) the current sensing section from
Figure 12 in the die image on the right, it is desirable to havethe sense FET relatively centered within the power FET andany constrained geometrical features should be avoided fora uniform current density.

This section describes the current sense pin interface tothe microcontroller. Figure 49 below focusses on the current
sense block only from Figure 37. The resistance, RCS, senses
the current output from the CS pin. The voltage developed
across RCS scales linearly with the magnitude of RCS, given
a constant sense current is sourced by the CS pin. This
assumption is valid, only until certain values of RCS. For
really high sense resistors (typically > 10 kW), the internalcurrent source fails to regulate (because of headroom
limitations, as mentioned before) and the current coming outof the CS pin decreases, thus saturating the voltage across
RCS. Such a behavior is plotted in Figure 50. The voltage,
VSENSE, across RCS, increases linearly until V (SENSE) SAT
and then saturates.

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AND9733/D
VBAT

Additionally, high precision small sense resistors can be
expensive and may raise the system cost. Considering these
implications, the sense resistor should be chosen optimally−
typically a value in the range of 1 kW ~ 5 kW isrecommended. The product datasheets should be referred tofor any specific recommendations.
In addition to the voltage headroom limitation, the sense
ratio accuracy also depends on the drive current capabilityof the analog circuitry, particularly the current source
feeding the sense FET (Referring Figure 51, the PMOS
current source driven by the op−amp). In case of very highload current, the sense current attains its maximum value
defined by the capability of the internal current source. Any
further increase in the load current does not increase thesense current and therefore, the sense ratio starts to deviateeven if sufficient voltage headroom is available for theoperation of internal analog circuit elements. Thismaximum sense current is typically defined well below thelower limit for the fault state sense current, and is specified
in the product datasheets.
The discussion above suggests that the potential at the CS
pin may rise all the way up to VBATT in certain situations.
This could potentially stress/damage the A/D stage of the
microcontroller, especially in cases of high battery voltages.
To prevent such a scenario, an external clamp, ZCS, is
recommended as shown in Figure 49. The resistor RSENSE
limits the current through ZCS. The RC network comprisingof RA/D and CCS is the recommended low pass filter for the
input A/D. The values for these components are specified in
the datasheets, and may also be chosen by the customer to fit
the requirements of their respective A/D stage.

ZVS
CSUPPLY
SPU
VDD

VDD

RIN

RPU

VD

OUT

IN
OUT

RPD

RDEN
Micro
OUT
Controller

COUT

ZL

DEN

RA/D

RSENSE

A/D

CS
GND

VSS
CCS

ZCS

RCS
RGND

DGND

Figure 49. Microcontroller Interface to CS Pin

VBATT
VSAT

VSENSECS Enable/Disable Logic

RCS

Different logic topologies may be used within onsemi
High−Side Smart FETs for enabling/disabling the analog
current sense output. For instance, NCV84160 employs aCurrent Sense Disable logic input that disables (turns off)
the CS output on receiving a Hi (logic level) commandsignal. In other words, follows an active low logic for CS
operation. Other devices, such as NCV84140 and
NCV84012A have an active high Current Sense Enable
logic input that turns on the CS output on receiving a Hi
(logic level) command signal from the microcontroller. In
multi−channel devices where the CS outputs are
multiplexed through a select input pin, the Enable/Disable
logic is common to all the channels (See Figure 14). For
current sense enable/disable philosophy for a specificdevice, refer to the corresponding product datasheet. The
signal conditioning circuitry, logic levels and hysteresis for
CS Disable/Enable pin is similar to that for the input pin.
Section Input Control and Hysteresis deliberates on the
input control logic and signal conditioning. The ESD
protection diode, ZESD, to GND (See Figure 21) limits thepotential observed at this pin and also provides protection incase of a reverse battery situation. It is recommended to use
a protection resistor while interfacing this node to themicrocontroller (See RDEN in Figure 49).

Figure 50. Variation of Sense Voltage vs RCS

The V (SENSE) SAT level, though typically close to VBATT,
may change across devices and technologies, and specificproduct datasheets should be referred to for sense saturation
voltages. As the sense current decreases, the sense ratio
increases and the error factor associated with the estimationof load current becomes more pronounced, which isundesirable. The discussion so far focused on the operation
in a normal, or non−fault state. If a fault condition exists, thefault state current source (Refer Figure 46) is active andforces current out of the CS pin. Depending on the specificdevice design, VSENSE may rise all the way up to VBATT(less a marginal drop across the internal circuit elements) forlarge RCS values, as in NCV84160, for example; or have afixed saturation point below VBATT. To summarize, too largeof a sense resistor, may saturate the sense voltage creating anerror in the output sense current (and therefore, the estimatedload current). Also, it is difficult to differentiate (withsufficient confidence) between the fault and no−fault state
VSENSE for high values of RCS. In case too low of a value ischosen for the sense resistor, the sensed voltage may be too
small to be sampled by the A/D of the microcontroller.

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AND9733/D
Current Sense Accuracy Improvement at Light Loads

mitigates the associated error factor. If the load current isfurther reduced, the gate voltage is further reduced to get a
constant Drain−Source drop below a certain threshold forlight loads. The parameter, termed as “Output Voltage Drop
Limitation”, and the corresponding light load threshold canbe looked up in the specific product datasheet. Since
RDS(ON) at such light loads is less of a concern, the on state
resistive drops are traded off for improving the current sense
accuracy. Figure 52 explains the variation of Drain−Sourceand Gate−Source voltages in the De−Saturation mode.
At high load currents, the Gate−Source voltage is driven
high to the maximum capability of the charge pump, and theDrain−Source voltage scales linearly with the current− Inessence, the device behaves like a low ohmic resistor. Belowa certain threshold of load current (i.e. the light loadcondition), the Gate−Source voltage is pulled down and theDrain−Source voltage thereafter is fixed at a level− VSAT. In
this region, the device is operating in the linear, or
non−RDS(ON) mode and load current bears a square−law
relationship to the Gate−Source voltage. The mechanism istherefore called as De−Saturation. The current reduces tozero (in practice there is some minimal subthresholdleakage) once the Gate−Source voltage droops below thethreshold voltage, VTH.

An accurate estimation of load current requires anaccurate measurement of sense current and a stable sense
ratio over the desirable range of loads. While the former
concern is central to the accuracy of the measurement
system (the onus of which lies with the application user), thelatter is more of a device design challenge. This challenge
compounds at small load currents (referred to as light loadcondition) where the voltages across the FET(Drain−Source and Gate−Source) become comparable to theprocess offsets and mismatches. Following equation
summarizes the two major concerns at low load currents:
SR Err +

ǒ

1
1)

V OFF
V DS

@

Ǔ ǒ

1
1)D

V th
V OV

Ǔ

(eq. 11)

Where,
SRErr is the error factor associated with the Sense Ratio,
VOFF is the input offset of the op−amp (See Figure 51), andDVth is the threshold mismatch between the power and thesense FETs.
As per Eq. 11, the error factor in the sense ratio isdependent on the input offset of the op−amp (that forces thetwo source nodes together) and on the threshold mismatchin the two FETs.

VDS
VGS
[V]

VD

delta VthCurrent
delta betadelta Tj Sense Cell

VGS

VDS

Main
Transistor
VTH
VSAT

VoffsetILOAD[A]Figure 52. Variation of Drain−Source andGate−Source Voltages in De−Saturation Mode

OUT

Below are the example characterization curves for aHigh−Side Smart FET in De−Saturation mode depicting thetemperature dependence.

CS

Figure 51. Circuit Schematic Depicting Error inSense Ratio Due to Op−Amp Offsets and Process
Mismatches

TJ = 150 C

V DS (V)At light loads, the drain−to−source voltage of the power
FET droops too low and is at par with the op−amp input
offset voltage making the first factor in Eq. 11 dominant in
the determination of sense ratio. Depending on the polarityof the op−amp offset, the sense ratio may diverge above or
below the nominal value.
To alleviate the above issue, a “De−Saturation” circuit isemployed that pulls down the charge pump and cuts back thegate voltage, thereby, increasing the RDS (ON) (and hence,
the VDS drop) of the device. The increased VDS drop

TJ = 25 C

TJ = -40 C

ILOAD (A)Figure 53. VDS Dependence on Load Current
Across Temperature

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AND9733/D
The Output Voltage Drop Limit is pretty stable acrosstemperature. The threshold current changes because of achange in RDS(ON) with temperature.
The idealized plot below delineates the improvement insense ratios with the De−Saturation mechanism:

scaled at light loads to maintain a constant current sense ratio
per the spec. A major challenge with such a mechanism is todefine the ratio of the output FET “fingers” to be switched
off as well as ensuring synchronization of the split fingers
especially under stressful conditions such as current limit.
Since the VDS of the power FET scales with the output
current at light loads (unlike de−saturation where a constant
VDS is attained per Figure 55), the threshold for light load
operation is defined in terms of output current instead of theoutput voltage drop limitation. In case of the conventionalde−saturation mechanism, it is desirable to have the two
FETs closely matched to reduce any threshold relatedoffsets. The architecture of the fault reporting circuit(Figure 55) is not altered between the two different lightload accuracy improvement techniques.
It is to be noted that the sense ratio also drifts withtemperature and load currents (especially at lighter load
currents). A calibration routine described in section Current
Sense Calibration helps in improving the accuracy over thedesired load current range.

Sense Ratio

Nominal Sense Ratio
Truncated Sense Ratio with De -Saturation

Sense Ratio Deviation without De -Saturation

ILOAD
[A]

Figure 54. Improvement in Current Sensing
Accuracy with De−Saturation

While the approach described above reduces the Sense
Ratio error associated with the op−amp offset, a reduction in
Gate−Source voltage would make the second factor (Refer
to Eq. 11) − threshold mismatch, dominant in determinationof the error. As the gate voltage is reduced, the overdrive forthe two FETs becomes comparable to the mismatch in thethreshold voltages which once again deviates the Sense
Ratio from its nominal value. In order to achieve superior
current sense accuracies at light loads, the new family ofHigh Side SmartFETs, such as NCV84008A, NCV84012A
etc. employ a split FET control current sensing mechanism
instead of de−saturation. The principle of operation isdepicted in Figure 55. The predicament in the form of adominant op−amp offset at light loads is addressed byturning off a part of the power FET instead of regulating it
at low gate voltages. The required increase in RDS(ON)(which subsequently increases the VDS compared to theoffset) at light loads, is therefore, achieved without driving
the output stage at low gate overdrive voltages which
eliminates the Vth mismatch error. The sense output is also

Figure 55. Split FET Current Sensing Mechanism

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AND9733/D
Current Sense Behavior in Normal and Fault Statesa high impedance stage (for e.g. a broken array of series LED
string). Such a condition will be detected and flagged by thedevice as a fault. The analog current sense pin in such an
event will output the fault state current−typically higher thanthe currents sensed during normal operation and a highfault−state sense voltage will be sensed across the sense
resistor. Figure 57 explains the Off State Open Loaddetection mechanism.

Normal State Operation
During normal operation, the sensed current output (or thevoltage sensed across the sense resistor) is proportional to
the load current. For a reasonably sized sense resistor (SeeCS Pin Interface and Sensing the Current), the sense voltage
at nominal loads is lower than fault state sense voltage tounambiguously detect a fault condition. For devices like
NCV84012A, that have the current sense fault level within
the range of saturated overload sense current (Refer
datasheet), a sense fault level is displayed in the OFF state
as well as described in the following sections. Refer toproduct datasheets for specs on fault and nominal state sense
currents and voltages. The timing diagram in Figure 56
mentions the important current sense timing parameters
while switching nominal loads.
Unless mentioned otherwise, the CS timing parametersreferenced to the Enable/Disable signal are termed astCS_High1/tCS_Low1; and the parameters referenced withrespect to the Input command are termed astCS_High2/tCS_Low2. The wave−set shown in Figure 56 also
depicts the response of current sense signal to changing load
currents. The signal DS refers to the Diagnostic Select− thisselects the channel to be sensed in case of a multi−channel
device. The typical values and range for these timing
parameters are mentioned in the respective productdatasheets. For any PWM operation, the current sense
timings need to be considered in addition to the device turnon and turn off timings. The frequency of the PWM
operation must not exceed the CS switching capability toensure reliable current sensing and diagnostics.
VIN

tON

SPU

VOL_OFFIFAULTCS

tCS_High2 t CS_Low1

tCS_High1

d tCS_High2

RLEAK
RGND

In an automotive environment, an “absolute open load”
condition would almost never exist, i.e. there will always besome leakage path to GND (attributing to temperature,humidity, system parasitics etc.) even if the load is open.
This impedance is represented by RLEAK in the figure above.
A potential is thus developed at the output node which is thensensed by a comparator and compared against a thresholdvoltage. An external pull−up resistor, RPU is recommended
to be connected to the output terminal which, in case of anopen load, pulls up the output node to battery and ensures thedetection of an open load. This resistor is typicallycomplemented by a switch, SPU, to avoid the undesired
leakage through RPU when open load detection is not
required.
The value of RPU needs to be selected after considering thetypical application loads, system parasitics and leakages inoff state (RLEAK). It should be sized such that the voltage at
the output node (or the potential divider created by RLEAK
and RPU) should be sufficient to flag an open load fault.
Towards this approach, there will be a max limit to RPU. In
addition, the resistor should be able to handle the power
dissipation which puts a minimum limit to RPU. For specific
RPU recommendations for a device, refer to the productdatasheet.
The comparator network mentioned above is designed tohave a high input impedance stage interfaced to the output
node to reduce the leakages associated with the open loaddetection circuit. Typical Off State Open Load leakage
levels in onsemi High Side SmartFETs are < 10 mA (Referto product datasheets for specs). It should also be noted thatthe output voltage in this circuit is being compared againstttCS_DSDS

RLOAD

Figure 57. Off State Open Load Diagnosis Principlet

VSENSE

GND

RCS

t

DEN

OUT

DEN

tON

IOUT

RPU

IN

t

tOFF

VD

VBATT

t

Figure 56. Current Sense Timing With Nominal
Load Switching

Open Load Diagnostics
OFF State
Under normal conditions in off state, when the input
command is Lo, the output should be pulled down to GND
by the load. An open load condition will exist in case theconnection to the load is lost, or the load itself wears out into

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AND9733/D
a threshold referenced to VBATT. In other words, thisthreshold will scale with the battery voltage and will always
be certain volts lower than the battery voltage. For instancein NCV84012A, the typical output threshold voltage (foropen load detection) is 1.3 V to 2.3 V below VBATT. This
design topology may not be true for all onsemi High Side
SmartFETs. In NCV84160, for e.g., the output thresholdvoltage is referenced to ground and is typically in the rangeof 2 V ~ 4 V irrespective of the battery voltage (as long as
VBATT is within the recommended operating range). For
such devices, the voltage at the comparator’s negative input
in Figure 57 is referenced to GND. The current sense output
current in case of open load fault is generally similar to thatin case of ON state faults (such as in case of current limit).
Some devices, like NCV84012A, offer fault differentiationin the form of different CS output current levels
corresponding to different application failure modes.
Product datasheets describe the range of CS output current
for different faults. Refer to product datasheets for specificinformation on open load detection.
Once an open load is detected, the fault state current
source (Figure 57) will override the CS output. There isalways a finite delay time before the current sense output isflagged high as depicted in the idealized wave−set in
Figure 58. The off−state open load timing and control logic
spec differs across devices. NCV84160, for example has atypical delay timing spec of 350 ms whereas NCV84012A
has this parameter specified at a typical of 70 ms. Further, thelatter device incorporates a counter based fault
differentiation in OFF State. The counter based retry
methodology is explained in Section Re−try Strategy. If thecounter value is non−zero at the time of externally disabling
the device (VIN : Hi ³ Lo), it is implied that a fault in theform of over−load/ over−temperature was present in thepreceding switch ON cycle. In such case, the respective ON
State fault output takes precedence over the OFF state fault
until the counter reset conditions (described in the productdatasheets) are satisfied. This is done to provide fault
information to the microcontroller in OFF state before it
attempts to enable the SmartFET again, for instance in a
PWM operation. OFF State faults, while critical to diagnose,
are not as detrimental to the device as repetitive
overload/over−temp conditions and are therefore given alower priority than the latter. In case the counter is zero in
OFF state, then the CS output is determined solely by OSOL
fault being present or not.

VIN

VOL

t

VOUT

DEN
VSENSE _Faultt

td_OL_OffVSENSEtt

Figure 58. Off State Open Load Delay Timing

ON State
When the input command to the device is Hi, the output
is pulled up close to VBATT. If no load is present, minimal
leakage current flows (typically < 50 mA) through thedevice as discussed above. The sense current and therefore,
the voltage sensed across RCS are also small, and have been
approximated as zero in the idealized wave−set in Figure 58.
Such low sense currents make it challenging to distinguishbetween an underload and open load condition. Further,while driving an LED load, where the drive currents for the
LED could be in milli−Amps, it could again be difficult tounambiguously differentiate open load from a nominal LED
load. Deviation from nominal sense ratios at these small load
currents adds to the difficulty in detection of an open load
during on state.
Short Circuit to Battery
A short circuit to VBATT at the output can be detected by
the same circuit discussed above for off state open load
diagnosis by adding a pull down resistor, RPD externally as
shown below in Figure 59.
The pull down resistor differentiates an off state open load(in which case the voltage at the output node is created by the
RPU−RPD potential divider) from a short circuit to VBATT(where the voltage at the output node is equal to VBATT,
assuming a perfect short). In either case, the comparator willdetect a fault and the voltage sensed at the output can be used
for discriminating analysis. In addition, this resistor also
provides a path to GND in case of a floating output node. In
on state, the load current will be zero (in case of an ideal
short), or extremely small (in case of a resistive short to
VBATT). The sense currents would consequently be small aswell posing a similar challenge as discussed in open load
during on state.

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AND9733/D

SPU

VBATT

latter comes into operation at light loads. Some devices, as
discussed in section Short Circuit OUT to GND−Current
Limitation, may have a peak detect based current limit
protection with a timer/counter−based retry strategy. The
fault diagnosis in these devices is not different from the ones
that employ linear current limit regulation. There are
however some subtle differences as highlighted in the next
section. The current sense response in case of an overload
situation is depicted in the idealized wave−set in the next
section in a short circuit to GND event.

SC to
VBATT

VD
VOL_OFF

RPU

IN

IFAULT

OUT

DEN

CS

GND

RPD

Short Circuit to GND
In a short circuit to ground event, the output current gets
limited by the current limiter mechanism explained above.
When the differential temperature of the die exceeds the set
threshold, the device turns off and then toggles until the shortcircuit condition persists and/or the input command is Hi.
The current sense output is as below:

RLOAD

RCS
RGND

Figure 59. Short Circuit to VBATT Detection

Current Limitation
As discussed in section Short Circuit OUT to
GND−Current Limitation, all onsemi High Side SmartFETs
are equipped with a current limiter circuit that protects thedevice in case of overload situations by limiting the
maximum current through the device. An overload situation
is detected by the device as a fault condition, and the sense
voltage is correspondingly flagged high. The circuit
schematic in Figure 60 describes the principle of operation.

VINtILIMSC_2

Fold−backCurrent

ILIMSC_1
IOUT

VD

t
t1

VSENSE_Fault

Reference
Bias

ILIM
Sense

To
ChargePump

Main
Transistort2

Absolute Temperature
Shutdown

t3

t4
tCS_Low2

tCS _High2VSENSEt

Figure 61. CS Behavior in a Short Circuit to GND
Event

The CS timing parameters are similar to the ones
discussed in section Normal State Operation. The example
here considers a device with fold−back current post absolute
thermal shutdown. The current sense response would,
however, be similar for a device with no fold−back. As thedevice successively goes into thermal shutdown followed byanother ILIM pulse, the current sense should not toggle andthe CS pin should output a stable fault−state current/voltage.
For this purpose, the hysteresis of the current sense output
is designed to be greater than that for the output current. This
characteristic will be discussed using the waveforms in thenext section. In practice, as the device heats up during a shortcircuit event, the current sense output may reduce slightly in
amplitude (because of a slightly negative temperature
coefficient). Also, with the high current pulses, the battery
voltage may droop transiently (depending on supply’s series
impedance). In such case, the current sense output will
follow the battery and may droop transiently. In both thescenarios, the CS droop is minimal and will not affect thedigitized current sense readout (for fault indication) at the
microcontroller.

VREF
OUT

GND

Figure 60. Current Limitation−Operating
Principle

The ILIM circuit block includes a sense FET (different
from the regular current sense FET) feeding a comparator.
When the load current reaches a certain threshold known as
ILIM (characterized as a voltage VREF here), the gate voltage
is pulled down as shown above. The ILIM circuit block will
override the charge pump. The device will no longer be
operating in the RDS(ON) mode and will output a maximum
saturated current. A separate sense device for current
limitation isolates the CS output from this block, thus
providing a stable current sense output. The ILIM operationis very similar in principle as the De−saturation mechanism.
The former becomes active in case of an overload, and thewww.onsemi.com
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AND9733/D
In devices with a counter based retry strategy, such as
NCV84012A, the current sense transitions in case of atransient short circuit to GND are depicted in Figure 62. As
a current limit peak is detected in short circuit, the internalcounter is incremented and the sense output flags a fault. For
more information on timing parameters, refer to section
Re−try Strategy. As the short circuit is removed and anominal load is connected, the output transitions into INOM.
The current sense, however, stays at the fault level for a time
defined as the blanking period. This feature is also present
in devices with linear current limit and is employed toprevent successive fault to nominal transitions in current
sense in case of intermittent short circuit to GND such as

physical wire de−bouncing. It should be noted that thecurrent sense fault level in SmartFETs like NCV84012A
may be lower than that in case of overload conditions (Referto product datasheet for sense fault current range). Once theinput command is disabled, the current sense once again
displays the current limit fault encountered in the preceding
ON cycle. The fault is displayed until the reset condition in
the form of a diagnostic enable pulse is forced. The otherreset condition forced by input enable is presented in Section
Re−try Strategy. If an open load fault is present, thecorresponding fault level at sense output will be present after
the counter is reset. Refer section Open Load Diagnostics fordetails.

tILIM_ResetÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ

VIN
Load

Short Circuit

IPKt

Nominaltd_off

INOM

t

IOUT

ILIM
Counter

td_ontcool_down

01

tauto_retry

n

2

0

t>ttILIM_CS_EN_Resett

DEN
tfault_blank

VSENSE _Fault
VSENSE _NOMt

VSENSE
Figure 62. CS Behavior in Counter Based Retry Strategy

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AND9733/D
microcontroller’s A/D stage, and thus will not affect thedigitized current sense output.

Over−temperature Operation
If the differential temperature, or the absolute temperatureof the die exceeds the set threshold (Refer section
Temperature/Power Limitation), the device protects itself
and goes into thermal shutdown. The current sense outputs
a fault state current in case of a thermal shutdown event. The
operation in this regime is depicted using an exemplary bulb
turn−on scenario.

Underload
Sections Short Circuit to Battery and Current Limitation
discuss the challenge while discerning an underload
condition from an open load and/or SC to VBATT during onstate. Some devices, NCV84012A for instance, distinguishthe underload condition by forcing a sense current <ILoad/KNom (the nominal sense current at that load) below
the output current threshold defined for the underload. For
small load currents, the sense ratio accuracy deteriorates andmakes it difficult to recognize if the low level of sensed
current indicates an underload condition, or is it thedeviation in the sense ratio that is misleading in theestimation of load current when the true load current isabove the underload threshold. The threshold for underload
should be carefully set considering the open load
impedance, intended application nominal loads and thedevice leakage. On one hand, there should be sufficientmargin between the underload and open load thresholds sothat the sensed current can distinguish between the two (withreasonable CS accuracy); and on the other hand theunderload threshold cannot be set too high considering theloads such as LEDs require low nominal drive currents. For
typical thresholds, refer to the specific product datasheets.

Input
Command

t

VIN
ILIM
INOM

t

IOUT
DtON DtOFF
tBulb_ON

DTJ_RST

TJ
tCS_High2

TTSD

DTJ

t
tCS_Response

VSENSE_Fault
VSENSE_Nom
VSENSEt

Current Sense Calibration

Figure 63. Thermal Toggling During Bulb Turn−On

While onsemi High Side SmartFETs are designed to offer
stable sense ratios, some inaccuracy is bound to be present
because of the offsets in the analog circuitry (refer section
Current Sense Accuracy Improvement at Light Loads) anddrifts with temperature, stress and load current. The
tolerances and drifts are mentioned in the respective productdatasheets. To further reduce these tolerances, a convenientcalibration scheme can be performed at the EOL (End ofLine) testing by the ECU (microcontroller) manufacturer.
Before discussing the calibration procedure, the “problem
statement” and the associated challenge is presented below.
With an ideal sense ratio, the relationship between thesense and output currents is described as:Assuming that the ambient temperature (at t = 0) was nothigh enough to trigger absolute thermal shutdown, thedevice goes into a current limitation operation mode as ittries to turn the bulb on. The current sense flags a fault foroverload and the device subsequently undergoes thermal
shutdown followed by another ILIM pulse, and so on. The
current sense output stays Hi indicating the fault state. As thebulb turns on and the device transitions into normal
operation, (for details on bulb turn on, refer to section Bulb
Loads) the temperature of the die reduces and current sense
output follows the load current trajectory. The time
tcs_Response can be considered as the “thermal hysteresis” of
the CS output. In other words, the current sense output stays
Hi for some time after the device moves out of a fault
condition. This eliminates the unnecessary toggling of thecurrent sense output in case of ILIM and thermal shutdown
events. This response time is only for diagnostic purposes
and bears no correlation to the ability of the device in turning
on a bulb. For specs on typical tcs_Response times, refer to thespecific product datasheet. It should be noted that the CS
output transition from nominal to fault state may not be as“smooth” as depicted in the idealized wave−set above. Thistransition involves turning off of the fault state current
source and turning on the nominal state CS circuit (Refer
Figure 46), and may exhibit sporadic noise spikes during thisswitching. Nonetheless, these high frequency spikes will beeasily filtered by the RC network (Figure 49) preceding theI SENSE +1@ISR OUT(eq. 12)

Representing this graphically,

ISENSEy = mx

IOUT

Figure 64. Sense Current vs Output Current With An
Ideal Sense Ratio

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AND9733/D
The slope of the line is given by the sense ratio. The offsetsof the analog circuitry (Refer Eq. 11 From sections Current
Sense Accuracy Improvement at Light Loads) manifest
themselves as a sense offset current. In other words, there
would be a finite sense current flowing out of the CS pin
when the load/output current is essentially zero. This can bemodelled as:
I SENSE +1@I) I OFFSR OUTISENSEy = m’x + c(eq. 13)
IOUT

where IOFF is the offset current. This offset varies fromone device to another and also has a temperaturedependency. The graphical representation is depicted in
Figure 65. The curves in red have the offset errors included.
The curvatures at small load currents (where the curve
deviates from a straight line equation) are the improvements
rendered by the De−saturation or Split−FET control circuit.
With no accuracy improvement technique, the sense current
would exhibit a higher deviation at low load currents.
The divergence at further reduced load currents arises(primarily) because of the threshold variation between the
power and sense FETs.

Figure 66. Sense Current vs Output Current
With Offset And Slope Error Boundary Curves(see dashed plots)

Both these errors are temperature, load current dependentand device dependent. Further, due to continuous
temperature cycling, power cycling and stressing the device,
the CS Ratio “drifts” over temp and lifetime. This drift isalso load current dependent, and is usually guaranteed bydesign. Product datasheets typically define and tabulate
default maximum and minimum sense ratio and/or sense
current at a given load current. This window includes
contribution from both the offset as well as slope errors, andessentially represents an ISENSE− IOUT curve similar to Fig
6.19. Any part shipped out of the factory will have an overall
accuracy within the bounds of the tolerances specified at
different load currents.
In order to understand the implications of these errors, an
output current level− IOUT1 is chosen.
Ideally, the sense current at this load, is given by ISENSE1(See Figure 67). However, due to inaccuracies in the sense
ratio, as discussed above, the sensed current could be
anywhere between the boundary curves which leads to anerror in the estimated load current between IOUT1’ and
IOUT1’’.

ISENSEy = mx +c

IOUT

Figure 65. Sense Current vs Output Current With
Offset Error and De−Saturation Mechanism

It should be noted that the current coming out of the CS pin
is always positive. Therefore the bottom curve does notindicate a negative sense offset; rather it just signifies that incase of negative op−amp offset, a certain load current levelneeds to be achieved before getting a finite sense current outof the CS pin.
In addition to the offset error, the sense ratio may digressfrom its nominal value across supply and load current range,and device−to−device variability. Graphically, this can bemodelled as a slope error associated with the curves above,and is more pronounced at high load currents. Figure 66
shows the boundary condition curves with the maximum
and minimum slope errors.
I SENSE +1@I) I OFFSRȀ OUTISENSEISENSE 1

IOUT 1’ IOUT 1 IOUT 1’’

IOUT

Figure 67. Error In The Estimated Load
Current With Inaccuracies In Sense Ratio(eq. 14)is the sense ratio inclusive of the slope error.

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39

AND9733/D
At low load currents, the boundary conditions will changewith the flipped polarity of the slope error (Figure 68).
Nonetheless, the challenge (in accurate estimation of load
current) would be similar as discussed above.

Table 2. Current Sense Ratio Spec− NCV84045
Sense Ratio
Load Current (A)

Min

Typ

Max

0.05

350

1455

1800

0.5

500

1330

1740

0.7

760

1290

1630

1.5

970

1200

1420

4.5

1090

1190

1340

ISENSEy = m’x +c

Now, measuring the current sense voltage at two load
currents, for instance, at 0.5 Amp and at 4.5 Amp andsubsequently putting in those values in the equations below,
slope and intercept can be calculated.

IOUT
m1 +

Figure 68. Sense Current vs Output Current With
Offset And Slope Error Boundary Curves For Light
Loads

SRȀ
@ * I OFF @ SRȀ
R SENSEThe calibration routine requires these slopes andintercepts to be stored in microcontroller’s memory. Thisequation is then used to estimate load currents by measuring
sense voltages at those loads, thereby eliminating the slope
error and intercept error. The current sense drift acrosstemperature cycles and stress over lifetime still persists. The
table below summarizes the current sense drift spec in
NCV84045. This table implies that, once calibrated, theallowed drift over power and temperature cycling across
lifetime is within the specified tolerances that are equivalent
to the relative errors in the estimation of load current fromthe measured sense voltage.

(eq. 15)This can be represented by the straight line equation
below.

Table 3. Current Sense Drift Spec in NCV84045
Current Sense DriftI OUT + m 1 @ V SENSE ) c 1

Load (A)

Min

Max

0.05

−25

25

0.5

−20

20

0.7

−15

15

1.5

−10

10

4.5

−5

5

(eq. 16)

Where(eq. 17)and c 1 + 0.5 * m 1 @ V SENSE

With the default current sense accuracy (as published in
the product datasheet), there could be a significant error
factor in the estimation of load current. The calibration
routine at EOL helps improving current sense accuracy overthe desired load range. This procedure involves measuring
the sense voltages at two known output currents and thenrecording this data in the non−volatile memory of the
microcontroller. Since, in the final applications, a sense
voltage would be “measured” and a load current would be“estimated” thereafter, the Eq. 14 above need to be
re−arranged as follows:
I OUT +

4.5 * 0.5
V SENSE2 * V SENSE1

SRȀ
m1 +
and c 1 + * I OFF @ SRȀ
R CS

Measuring two points on this line would render the valuesof slope and intercept for a particular device. Once thesevalues are known for a device, the output current can be
estimated, with reasonable accuracy, for any other load bymeasuring the sense voltage and substituting the calibrated
slope and intercept. Since the calibration routine is generally
not performed across a temperature range (to save test time,
resources and microcontroller memory overheads), the drift
error associated with the sense ratios would still be present.
Considering the current sense measurements in NCV84045
as an example, the current sense ratios are specified asfollows:

It should be considered that the temperature variability
and tolerance of sense resistor has not been accounted here
which will add to the error factor associated with estimatedload current. Further, the temperature drift of offset error,
though minimal, has also been ignored. The calibration
routine, thus, offers a significant improvement in load
current estimation. In some cases (where the overall test
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40

AND9733/D
could also be performed. In this technique, the slope in
Eq.14 (which is inversely proportional to the differential
sense ratio estimated from the ISENSE − ILOAD curve) is“assumed” as typical (defined by the centered CS ratio per
the spec), and the intercept is calculated by a single
measurement point assuming typical slope. The current
sense improvement rendered by this technique, however, is
not as good as the two point calibration method discussed
above.

ÎÎÎ}ÎÎÎ}ÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏ}Junction

0 J −C

SiliconBack metal
SolderTab
SolderCopper trace

Low thermal
resistance

0 C −A

Moderate
thermalresistance

Cover

Thermal Flux exchangewith other devices on
board

High therma
resistanceAmbient Air

UNDERSTANDING THE THERMAL NETWORK
Understanding and accurate estimation of a device’s
thermal response has been a long standing challenge withregards to the automotive applications where external
conditions can vary in extremes. Thermal overstress, in theform of transient or continual temperature swings,
exceeding device’s thermal capacity is one of the mostencountered failure modes in the field, especially for powerdevices that frequently observe these transients throughtheir lifetime. Further, with the continuous miniaturizationof silicon feature geometries, die and packages sizes, thelikelihood of generating “thermal fractures” increases. This
necessitates a comprehensive understanding of the thermal
response of the device and the influences of the external
factors such as the device mounting conditions, application
boards, peripheral heat sources/sinks etc. From a design’s
point of view, the layout, structure and the protection
features (incorporated in the device) should be designed
considering the implications on the thermal performance inthe target application. This section describes thecontribution of the above mentioned internal and external
factors in determining and/or achieving the desired thermal
behavior in the system. In addition, the associated metrics
that quantify the thermal performance and thecorresponding exemplary datasheet specifications will also
be explained in this section. Lastly, the design philosophy ofprotection features, such as current limitation and thermal
shutdown (both absolute and differential), vis−a−vis thethermal ameliorations rendered will be discussed.

= thermal flux

Figure 69. Thermal Resistance Physical
Ladder in Application

Before explaining the layer structure above, it is assumed
that a power pulse is applied to the device. In such case, thetemperature of the device and the “surrounding
environment” will increase, and heat will start to flow in theform of thermal flux. Once the power is turned off, thetemperature will start to decay and will eventually attainsteady state, or equilibrium.
Now, the junction of the device observes maximum
temperature swings assuming a uniform current density
through the device with no surface defects. Since thejunction is confined to rather shallow depths, maximum
temperature is observed in the near−surface region. In caseof non−uniform current densities, one section of thenear−surface region conducts more current thereby creating
thermal hot−spots (which may irreversibly damage the die)that make it difficult to model the average junction
temperature. The next layer in the path of thermal flux iscollectively called as “silicon” which includes the substrate,
epitaxial layers and any implants (not in the vicinity of thejunction). The thickness of the die plays a critical role inachieving the required thermal performance, especially overshort duration power events (as will be discussed later). The
thicker the die, the more is the time required for the heat toflow out of the device, and the more is the thermal resistancepresented to the thermal flux. This entails a parametrictrade−off as a higher epitaxial thickness is required forsupporting the required breakdown voltage and ensuring themechanical stability of the wafer (especially for large wafer
diameters). Further, the material of the substrate, presenceof any volumetric defects also affects the flow of heat out ofthe device. For instance, devices realized on
silicon−on−insulator substrates may be better in terms of
reduced leakages and a lesser likelihood of latch−up, but
exhibit a higher thermal resistance than Si substrates. On theother hand, materials like SiC (silicon carbide) exhibit ahigher thermal conductivity than Si. Therefore, the material
and physical properties of the substrate should be decided
considering the desired thermal performance from the final
device.

Thermal Resistance − Physical Interpretation

Transient as well as steady state thermal resistance is theparameter readily used in the semiconductor industry toquantify the thermal performance of a device. Thisparameter is usually specified in the product datasheet undera certain set of conditions (refer section Datasheet
Parameters and Specifications). While mathematically, theparameter is described as C/Watt, i.e. the temperaturechange consequential to the power applied to the device; thephysical representation is analogous to its electricalcounterpart− a quantity obstructing/resisting the heat flow
(analogous to electrical current) by developing a thermal
potential (analogous to electrical voltage) across it.
Figure 69 depicts the layer by layer structure, or the thermal
potential divider ladder in an application.

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AND9733/D
periods, going up to a few seconds, the application
conditions (as described in the above paragraph) have agreater influence on the thermal resistance. As the systemreaches equilibrium over long pulse periods (typically morethan 100s of seconds), the device itself has minimal
contribution in the steady state thermal resistance, and thethermal performance only depends on the test conditions. It
should be noted that these time periods are only estimatesand assume that the pulse period and the power levels
applied are well within the boundary conditions defined forthe device and do not interfere with the thresholds definedfor the protection circuitry− for instance, thermal shutdown.
Thermal resistance in case of repetitive power pulse
events depend on the duty cycle. Depending on the duty
cycle, the heat accumulated in a power pulse may, or may not
be “carried over” to the subsequent pulse, thereby
confounding the analysis. Further, there is a time lag
between the electrical power wave and the consequent
thermal wave which must be taken into account during thethermal analysis over a repetitive pulse event. See below for
the simulated thermal wave for a hypothetical power profile
on an exemplary device.

After the substrate, the next layer in the ladder is the backside metal followed by the solder. All products in the onsemi
high−side SmartFET family have a back side drain contact
to manage the high power requirements by distributing thecurrent density over the entire substrate contact area. Choiceof metal also determines the thermal resistance. The
structure depicted in Figure 69 assumes a back side tab, oran “exposed pad” connection for the drain terminal (which
may or may not be present depending on the device andtechnology). This is usually realized using solder as the
conductive die−attach to the tab. The solder layer should be
uniform in thickness and conformal to the drain contact.
Voids in solder have been a known failure mode leading tohigh transient thermal resistance. On the source side, power
metallization for the source contact and the set of bond wires
determine and limit the thermal performance of the device(refer section Improving the transient thermal performancefor impact of bond wires). Until the tab layer (inclusive ofthe lead frame, mold compound and the package), a one
dimensional heat flow model is (reasonably) assumed withthermal flux flowing vertically. The thermal resistance until
this point is collectively termed as qJunction−Case, orqJunction−Pin (in case there is no back side exposed pad), or
qJunction–Soldering Point. Once, the heat starts to flow out of the
package, the lateral flux sourced in by any other heat sourcesin the vicinity of the concerned device need to be taken into
account as well, and the model may transpire into adimensional heat flow network, which is typically morechallenging to analyze and estimate. This assumption,
however, does not always hold true for multi−channel
devices where the adjacent channels could be conducting
power and dissipating heat laterally into the die, thus
complicating the analysis. After the package layer, themounting and application conditions determine the thermal
resistance. These include the amount of solder, the Cu heatspreader area on the application PCB, the length and widthof traces, number of layers in the PCB, any internal planes
for heat conduction, characteristics of the epoxy used, if any,
between the application PCB and the ECU casing etc.
Section Understanding the Datasheet Curves discusses theimpact of some of these factors on the thermal resistance ofthe system. Adding the resistance contribution of all theseladders yields the overall Junction−to−ambient thermal
resistance in the application.
The extent of heat flow within the ladder structure
discussed above depends on the pulse timings and duty
cycle. From empirical as well as simulation results, it isestimated that up to a few 100 ms in a single pulse power
event, the die active area, technology and physical attributes
determine the thermal resistance and the outside application
environment has minimum contribution towards the thermal
response over short pulse durations. As the (single) pulse
period is increased, the lead frame, package, moldcompound etc. begin to have an impact on the thermal
performance. This impact is usually pronounced for thepulse periods of a few milliseconds. For longer pulse

Figure 70. Simulation Depicting The Lag in The
Thermal Wave For An Arbitrary Power Profile
Improving the transient thermal performance

As discussed in the previous section, transient thermal
resistance over relatively short periods of time (typicallylimited to a few milliseconds) depends more on the device
than on the application conditions. The “device” here
includes contribution from both the die and the package.
Since the geometrical and physical attributes of the die are
primarily driven to optimize performance parameters like
conduction losses and breakdowns, there is little scope ofany enhancements in the die itself to improve the thermal
capability. Package enhancements, on the other hand, arerelatively more tenable and can significantly improve thetransient thermal performance over single pulse as well as
repetitive pulse enhancements.
Certain onsemi High−Side SmartFETs (depending ontechnology and application requirements) incorporate an
exposed pad, or tab connection for the drain terminal towww.onsemi.com
42

AND9733/D
monolithic devices that have the control circuit placed next
to the control logic with narrow spaces for routing
feed−through signals. Laying out a clip and maintaining its
conformity over the entire FET area is often challenging. In
such cases, other avenues for improving thermal
performance are explored− including, but not limited to,changing the top metal stack composition and thickness,increasing the number and/or thickness of bond wires.
Further, for devices with lower power requirements, clip
placement faces economic and technological constraints
with a small silicon area available for bonding. These
devices employ bond wires for drain and source connections
to the lead frame. Thermal performance is enhanced by
employing multiple bond wires as well as (in some cases)
multiple stitches for each such bond wire. Other packageenhancements, like improving the mold compound
chemistry and optimizing bond parameters to avoid
generation of “thermal ruptures”, are also applied.
Overall, the bond type and top metal stack are governedby the ease of manufacturability and the required
electro−thermal performance from the specific device.

improve the heat dissipation. Figure 71 shows the thermal
flux flow through an exposed pad. An E−pad connection
offers a superior transient thermal performance over similar
sized devices with a pin−out, or a combination of pins for thedrain connection (bonded to the back side drain with bondwires).

Figure 71. Thermal Flux Flow With The E−Pad For
Drain Terminal

Datasheet Parameters and Specifications

With the E−pad, the solder and spreader area on theapplication PCB is also increased which provides additional
heat sinking and helps improve heat dissipation over longer
pulse durations (> 1 sec).
In addition to the drain terminal, the other node in the pathof the power flow is the source terminal. Source contact, top
power metal and bond−out to the lead frame, all have an
impact on the transient thermal performance andconsequently in determining the maximum power handlingcapability of the device. Since most of the power dissipation
happens over shallow junction depths, it is imperative toconsider the thermal conductivity and thickness of thesource top metal especially while designing high power
density devices. Some of the high power onsemi SmartFETs
have copper top metal instead of the conventional Al alloy
to offer improved thermal resistance. In case of extremely
low RDS(ON) devices (such as NCV84004A, NCV84006A
etc.), the overhead electrical losses associated with the“back−end technology” including bond wires tend to limit
the parametric performance of the device. For such devices,an alternative bonding in the form of “copper clip” provides
superior electrical and thermal performance. The clip covers
the entire active area of the power FET and instantaneouslytransfers heat from silicon to the lead frame, thus acting as
a top side heat sink.
While beneficial in case of low RDS(ON) high powerdevices, clip layout and placement is an important concern
for the stability of the die in case of high power dissipation.
Any unexposed area around the edges of the clips can create
a localized hotspot and serve as the site for thermal runaway.
Addressing this concern is particularly important in case of

Thermal Resistance−Physical Interpretation describes thephysical interpretation of thermal resistance. This
interpretation, though imperative for understanding thethermal network, may not be plausible to model, simulate
and specify mathematically in the product datasheets toquantify and compare the thermal performance of a device.
Foster and Cauer Networks
For datasheet purposes, for a given die and package,transient as well as steady state thermal measurements are
performed in a controlled environment under laboratory
setup conditions and thermal resistance is measured byrecording the temperature change consequential to a known
power pulse. This temperature change is typically measured
by analyzing the parametric changes in a pre−calibrated
on−chip thermometer, such as the forward drop of a body
diode in case of a power FET. This thermometer should bespatially close to the junction and in certain cases is speciallyfabricated to model thermal profiles. The thermal ground,which is ambient in case of Junction−to−Ambient
measurements and case/pin in case of Junction−to−Case/
Junction−to−Pin measurements, is kept stable at a fixed
temperature through forced convection and heat sinking (toquickly dissipate heat from the system ground). In addition,
thermal simulations are performed on the device withavailable modelling tools such as SPICE, ANSYS etc. Oncethe measurements are done and plotted, a mathematical R−C
model is simulated to fit this measured curve. Figure 72
shows the simulated Foster R−C network.

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AND9733/D

Figure 72. Foster R−C Network Model

Figure 73. Cauer R−C Network Model

The R’s and C’s are connected such that they yield a time
constant unique to each “rung” in the ladder, where:ti + Ri * Ci

Although the sum of resistances in the Cauer network
ladder also yields the overall thermal resistance, theindividual rungs are not same as the Foster network. The
variations in the system conditions can be better
conceptualized by observing corresponding variations in the
Cauer R−C network (The relationship between several
physical contributors, with similar time constants, and theirmathematical equivalents is rather complex). A Cauer
network is generally difficult to model and transpose fromone device to another, and is generally computed from their
Foster counterparts using known algorithms.
The datasheets for onsemi High−Side SmartFET family
may or may not include these R−C models depending on thespecific product. These models, can however, be provided
on specific requests from the customer.

(eq. 18)

The contribution of each rung is inversely proportional to
its time constant, and the rungs with longer time constants
have a more pronounced contribution as the system
progresses towards steady state. Having stated this, theresistances and corresponding time constants in a foster
network, however, have no physical significance, i.e., they
are uncorrelated to the physical ladder structure described in
section Thermal Resistance−Physical Interpretation.
Further, the order and number of rungs in the ladder is also
arbitrary and can be changed. In other words, a Foster ladder
is a purely mathematical model to fit the measured thermal
resistance curve. The more the number of rungs, the betteris the precision and the lower is the error factor relative to theactual curve. The advantage of using a foster model is its
ease of simulation. Once an R−C network is available for one
device, it is relatively easy to create R−C models (andconsequently generate transient thermal resistance curves)for other devices in the family by changing inputs to thesimulated model− such as device active area for the power
FET, total silicon area etc. The sum of the R’s in the ladder
gives the overall Junction−to−Ambient thermal resistance ofthe system.
Another type of R−C ladder is the Cauer Network, shown
below in Figure 73. In this network, the capacitors are allconnected to the system’s thermal ground, and the R’s andC’s in each ladder bear a direct correlation to the physicalladder structure. Intuitively, it can be observed from theladder that rungs closer to the junction will be charged(thermally) first and the rungs towards the ground will only
be charged once the rungs above are saturated with heat. The
rungs closer to the junction, therefore, can be related with thedevice and package, and the rungs closer to the ambient
ground can be related to external application conditions(such as PCB), however, with no clear demarcation between
the device and its periphery.

Understanding the Datasheet Curves
Thedatasheets
tabulatethesteadystate
junction−to−ambient and junction−to−case/pin/soldering
point thermal resistances, unless otherwise specified.
Transient thermal resistances are also plotted along with. It
should be noted that these resistances are specified against
a set of application and mounting conditions such as PCB Cu
spreader area and thickness, FR4 area, number of board
layers etc. The published curves are valid only under these
conditions and should not be used to make junction
temperature estimates in case the conditions in applicationdiffer from that mentioned in the datasheet. Along the sameline of thought, any comparative analysis (within theonsemi product portfolio or comparison to competitor
devices) will render reliable results only if the test
conditions are uniform. Towards this end, certain standards
defining the board geometries and properties are followed−
for instance JEDEC JESD 51−3, 51−7 etc. Refer torespective product datasheet for the set of conditions
followed while describing the thermal resistance. Consider,Figure 74 for example, the Junction−to−ambient transient
thermal resistance curve for NCV84160:

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AND9733/D

Figure 75. Transient Thermal Resistance Exemplary
Curve−NCV84160 For Min Pad Front Cu Area

Figure 74. Transient Thermal Resistance Exemplary
Curve NCV84160

The steady state thermal resistance increases by ~16%, inthis case, for a 200 mm2 reduction in front Cu spreader area.
As another example, a ~75% increase in the FR4 area is
expected to yield a ~7% reduction in the steady state
resistance (FR4 properties are generally associated withreally long time constants per Figure 73, and a perceived
impact is evident only for longer pulse durations). The data
presented here is valid only for this particular scenario andshould not be extended to other devices for which the test
conditions and the corresponding impact on thermal
resistance may vary.
Assuming that in a particular application, the test
conditions are identical to those specified against the
published curved in Figure 74, an approximated calculation
is described below to estimate the average junction
temperature in a hypothetical inductive switchingenvironment.
Consider that a 1 mH inductor is switched with a peakcurrent of 5 Amp at an ambient temperature of 25C and abattery voltage of 14 V. The series resistance in the output
conduction path has been ignored (may not necessarily betrue in the real application). The scenario is depicted in theidealized wave−set below:

It should be noted that terms q and R(t) are
interchangeably used to describe the thermal resistance of adevice. The curve above plots the thermal resistance over a
single pulse as well as a PWM power pulse train (defined bya duty cycle). The measurement conditions specify a single
layer PCB with an FR4 area of 4.8 cm *4.8 cm, a front 1
ounce Cu spreader area of ~ 200 mm2 (generally accounted
only for drain and source terminals), back side plane covered
with 1 ounce Cu spreader with no internal planes. In
addition, it is assumed that no other heat source is operatingin the vicinity of the device under test that could potentiallyinfluence the thermal profile of the system. The length oftraces/test wires, placement of vias (if any), and orientationof the test board and stability of ambient temperature(usually achieved through forced convection) are also
known to impact the thermal response, amongst many otherfactors. The thermal resistance spec is, therefore, valid only
under the above mentioned conditions, and cannot beapplied universally to any other application condition. To
quantify the effect of change in application conditions, thecurve in Figure 75 depicts the thermal resistance for thesame device (NCV84160) under same conditions as above
except that the front Cu spreader area is changed from 200
mm2 to min pad (with Cu area present only at the soldering
points for the package pins).

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AND9733/D

VIN

~VD

t

~13.2VtVOUTt ON ~0.38 ms

Ipk

In case of repetitive switching, the duty cycle curve should
be referred to instead of the single pulse curve. For instance,
if the inductance per Figure 76 is switched at a frequency of
100 Hz, the time period is calculated as 10 msec. The duty
cycles for the charge and discharge event can then be
calculated as 0.38/10 ~ 3.8% and 0.16/10 ~ 1.6%
respectively. These curves can be interpolated for an
estimated thermal resistance, and junction temperature canbe calculated in a similar way as described above.
The calculation here assumes an averaged rectangularpower profile equivalent for the inductive charge anddischarge events which is not exactly accurate and may notnecessarily be true in every application. The purpose of theabove exercise was to demonstrate the interpretation and useof thermal resistance curves. In case the dynamic
temperature change is of interest, the instantaneous power
profile needs to be fed into a calculator that utilizes the foster
R−C model (refer section Foster and Cauer Networks) andperforms piece−wise integration using a set formulae toestimate the corresponding temperature profile. Suchprofiles can be provided on specific customer requests.
In all the aforementioned calculations and R−C networks,
junction−to−ambient thermal resistance model has beenshown. This is because of its greater relevance in practicalscenarios. While a junction−to−case (or junction−to−pin)thermal resistance may seem like a convenient tool toestimate junction temperature by simply recording the casetemperature during a power event, it could be misleading to
use the published junction−to−case thermal resistancenumbers. The premise behind a junction−to−casemeasurement is the assumption that the “case” of the device
is treated as the “thermal ground”, and should remain at a
fixed known temperature regardless of dynamic changes in
the junction temperature. Such a condition is difficult toachieve in practice, and nearly impossible over shorttransients where case temperature sways with the variations
in dynamic power levels. Further, most temperaturerecording devices like thermocouples have response times
way higher than typical power transients applied in
automotive PWM applications, making it difficult to predict
the exact case temperature. The junction−to−ambient
counterpart, comparatively, is more reliable in the sense thatambient temperature can be controlled (through proper heatsinking and controlled air flow) more precisely in case of
dynamic power changes.

tAVAL~
0.16msZCL ~ 46V

~5 A
IOUT

t

Figure 76. Idealized Wave−Set in a Hypothetical
Inductive Switching Event− Calculating the Junction
Temperature

The tON and tAVAL are calculated as ~0.38 ms and ~0.16
ms using the equations below.
t ON +

L @ I pk

(eq. 19)

V D * V DSONt AVAL +L @ I pk

ŤV D * V

ZCLŤ(eq. 20)

The average power dissipations during the charging andthe avalanche event can then be approximated as 2 Watts and
80 Watts respectively. These power levels have been
calculated assuming an ideal straight line decay curve for thecurrent during charge and discharge cycles. In a realapplication, the average power levels should rather bemeasured directly (most measuring equipment’s canperform mathematical exercises to output measured
powers) than performing these approximated calculations.
Now, referring to the set of curves in Figure 74, the x−axisdefines the time period of the power pulse and the y−axisspecs the thermal resistance for different duty cycle
operations. Extrapolating the thermal resistance from thesingle pulse curve at ~ 0.38 ms (for the charge cycle) as ~1.2 C/Watt, the temperature rise can be calculated as 1.2*2~ 2.4 C. With a similar extrapolation for the discharge
event, the temperature rise can be calculated as 0.8*80 ~64 C. Adding this temperature rise to the ambient
temperature, the junction temperature at the end of the SCIS
event can be calculated as 25 + 2.4 + 64 ~ 92 C.

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AND9733/D
Design Philosophy − Protection Featurestemperature on the die, and c) the required delta fordifferential temperature sensing to limit the transient
thermal stresses. Placement of these sensors becomes
further challenging in the devices that incorporate a clip
covering the active source area. Layout for the current sense
structures as well considers a uniform current density while
avoiding constriction channels that could potentially create
hotspots on the die. In addition to the layout, the analog
control circuitry for these protection features also needs tobe designed for the required thermal performance. The
thresholds for control activation and the temperature
coefficients of the circuit elements are primarily consideredwhile designing this circuitry.

The protection features in onsemi High Side SmartFETs,
particularly − current limitation and temperature shutdown
are designed taking into account the thermal performance ofthe device. While low power devices employ linear current
limit with thermally driven retry strategy, high powerdevices realized on dense technologies use a more precise
current limit peak detect turn off and a timer based retry
strategy. From a layout standpoint, a thermal map of the die
is simulated to assess the region’s most sensitive (in terms oftemperature changes) to the inflicted power. The
temperature sense structures are laid out to optimize a) the
maximum die temperature, b) linearity of sensors w.r.t max

REFERENCES[1] https://chem.libretexts.org/Textbook_Maps/Inorganic_Chemistry_Textbook_Maps/Map%3A_Inorganic_Chemistry_(Wikibook)/Chapter_10%3A_Electronic_Properties_of_Materials%3A_Superconductors_and_Semiconductors/10.4_
Semiconductors%3A_band_gaps%2C_colors%2C_conductivity_and_doping[2] Intusoft Newsletter, October 1988, pp 11−6 to 11−7, http://www.intusoft.com/nlpdf/nl11.pdf.
[3] S. Ben−Yaakov, M.M. Peretz, B. Hesterman, “A SPICE compatible behavioral electrical model of a heated tungsten
filament”, Twentieth Annual IEEE Applied Power Electronics Conference and Exposition, vol. 2, pp. 1079−1084, 2005.
[4] http://www.aecouncil.com/Documents/AEC_Q100−012.pdf[5] https://www.iso.org/standard/50925.html

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AND9733/D
Table 4. GLOSSARY OF ABBREVIATIONS
#

Table

1

DMOS

Double Diffused MOS

Description

2

N−FET

N Channel Field Effect Transistor

3

CMOS

Complementary MOSFET pair

4

OEM

Original Equipment Manufacturer

5

ZVD

Over−Voltage/ESD Clamp for the control section in a High Side Device

6

ZSenseOver−Voltage/ESD Clamp for the Current Sense Output

7

ZESD

ESD protection diodes for logic inputs

8

A/D

Analog to Digital Converter

9

I/O

Input/Output

10

RMS

Root Mean Square

11

ECU

Electronic Control Unit

12

PWM

Pulse Width Modulation

13

LED

Light Emitting Diode

14

RSC

Repetitive Short Circuit

15

SR

Sense Ratio

16

SRErr

Error Factor in Sense Ratio

17

TSD

Temperature Shutdown

18

DTSD

Differential/Delta Thermal Shutdown

19

IOUT

Output (Drain−Source) Current

20

CS

Current Sense Terminal

21

OUT

Output Terminal

22

VOFF

Input Offset of CS op−amp

23

Vth

Threshold Voltage of Power FET

24

RLEAK

Leakage Resistance during open load condition

25

ILOAD

Current through the load− may differ from IOUT

26

GND

Ground Terminal

27

VBATT

Battery Voltage

28

IL(OFF)

Off−State Output Leakage Current

29

VD

30

VIN_HYST

31

VIN

32

VSENSE

Voltage at the Sense Terminal measured across the sense resistor,
equivalent to “VCS”

33

ICS_REV

Current through the CS pin in case of Reverse Battery Connection,equivalent to “−ICS”

Drain Voltage
Input Hysteresis window
Voltage at the input terminal

34

RCS

Sense Resistor to Ground

35

IREV

Current through Body−Diode during reverse battery, equivalent to “−IOUT”

36

ILIM_SC1/ILIM_Hi

Current Limit − High37

ILIM_SC2/ILIM_Lo

Fold Back Current Limit

38

ILIM

Typical Current Limit

39

RDS(ON)40

VCLAMP/ZCL

Channel Resistance in ON State, equivalent to “RON”
Over−Voltage Active Clamping Structure for SCIS events, equivalent to“VOUT_CL”

41

VDS_SAT

Output Voltage Drop Limitation at Light Loads, equivalent to “VDS_ON”

42

IGND_REV

Current through the GND pin in case of Reverse Battery Connection

43

ZGND

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AND9733/D
Table 4. GLOSSARY OF ABBREVIATIONS
#

Table

Description

44

RDEN

45

tCS_High1

CS_EN High to CS High delay time46

tCS_Low1

CS_EN Low to CS Low delay time47

tCS_High2

VIN High to CS High Delay Time48

tCS_Low2

VIN Low to CS Low Delay Time

49

ton

VIN Rise to 90% VOUT

50

toff

VIN Fall to 10% VOUT

51

tD_ON

Turn−On Delay Time, to 10% VOUT, VD = “ ” V, RL = “ ” Ohms

52

tD_OFF

Turn−Off Delay Time, to 90% VOUT, VD = “ ” V, RL = “ ” Ohms

53

tskew

Differential Pulse Skew

54

TTSD

Thermal Shutdown Threshold

55

TTSD_HYS

Thermal Shutdown Hysteresis

56

DTJ_RST

Delta Thermal Shutdown Hysteresis

57

VOV

Over voltage Protection

58

RIN

Input Resistance interfaced to microcontroller

59

DEN

Current Sense/Diagnostic Enable Terminal, equivalent to “CS_EN”

60

RCS

Sense Resistor to Ground

61

RPU

Pull up resistance for Off State Open Load Detection and Pull down
resistance to detect Short Circuit Output to battery

62

SPU

Switch to control RPU connection to battery

63

RA/D

Protects micro controller during over voltage and reverse polarity.

64

RGND

Ground Resistance

65

ZCS

ESD structure (internal) connected from VD to CS terminal.

66

SOA

Safe operating area

67

IGBTs

Insulated gate bipolar transistor

68

SCR

Silicion controlled rectifier

69

EMI

Electro magnetic interferance

70

RPROTECT

Protection resistor for cluster load

71

tav /tAVAL

Avalanche time in an inductive discharge event

72

Ci

Capacitive ladder for thermal network

73

Ri

Resistance ladder for thermal network

74

tiTime constant for a thermal network

75

qJunction–Soldering Point76

qJunction−Pin

Junction to pin thermal resistance78

qJunction−Case

Junction to case thermal resistance

79

EOL

80

Knom/SR

81

SC

82

tcs_Response

83

VREF

Reference voltage for comparator

84

DS

Diagnostic Select, equivalent to “CS_SEL”

85

CCS

Capacitor for the current sense filter

86

V (SENSE) SAT

87

Kx

Constant accounting for device’s physical dimensions

88aChannel length modulation coefficient

Diagnosis Enable/Disable Resistance interfaced to microcontroller,
equivalent to “RCSE”

Junction to soldering point thermal resistanceEnd of life
Nominal current sense ratio
Short circuit
Current sense response time

Saturation voltage at CS pin

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AND9733/D
Table 4. GLOSSARY OF ABBREVIATIONS
#

Table

Description

89

RCL

Repetitive clamp switching

90

Ipk

Peak current in SCIS event

91

Leff

Effective inductance in a SCIS event

92

SCIS

Self−clamped inductive switching

93

VZCL

Breakdown voltage of the overvoltage protection clamps

94

VDSON

On state potential drop

95

RL

Load resistance

96

CDS

Drain to source Capacitance

97

CGD

Gate to drain Capacitance

98

CGS

Gate to source capacitance

99

SRoff

Slew Rate during turn off

100

SRon

Slew rate during turn on

101

VINH_MIN

Minimum high level input voltage

102

VINL_MAX

Maximum low level input voltage

103

RPD

Pull down resistor for short circuit to detection

104

COUT

Output capacitor

105

ZL

Load impedance

106

DGND

Ground network diode

107

VGND

Voltage across the ground resistor

108

VRIN

Voltage across the input resistor

109

VOUT_MICRO110

CSUPPLY

Supply capacitor

111

VNOM

Nominal rated bulb voltage

112

PNOM

Nominal rated bulb power

113

Vref_deltaTj

Reference Voltage for DTSD comparator

114

Vref_Tjmax

Reference voltage for DTSD comparator

115

IDEN_REV

Reverse current through DEN terminal

116

IIN_REV

Reverse current through input terminal

117

PCB

Printed circuit board

118

tBulb_ON

Time required to turn on the bulb

119

TREF

Desired bulb filament temperature

Voltage at the logic output of the microcontroller

onsemi,, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of theinformation, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or useof any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance mayvary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any licenseunder any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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