Reduction of DC-link current harmonics for Three-phase VSI
over Wide Power Factor Range using Single-Carrier-Comparison
Discontinuous PWM
Koroku Nishizawa*, Jun-ichi Itoh*, Akihiro Odaka**, Akio Toba**, and Hidetoshi Umida***
Nagaoka University of Technology
1603-1 Kamitomioka-cho, Nagaoka city Niigata, Japan
Tel., Fax: +81 / (258) – 47.9533.
E-Mail: koroku_nishizawa@stn.nagaokaut.ac.jp, itoh@vos.nagaokaut.ac.jp
URL: http://itohserver01.nagaokaut.ac.jp/itohlab/jp/index.html**
Fuji Electric Co., Ltd.
1 Fuji-cho, Hino city Tokyo, Japan
Tel.: +81 / (42) – 583.6118.
Fax: +81 / (42) – 586.9665.
E-Mail: odaka-akihiro@fujielectric.com, toba-akio@fujielectric.com,
umida-hidetoshi@fujielectric.com
URL: http://www.fujielectric.co.jp/

Keywords«DC-link current harmonics», «Three-phase voltage source inverter», «Discontinuous PWM»

Abstract
This paper proposes a novel discontinuous PWM (DPWM) in order to reduce dc-link current
harmonics of a voltage source inverter (VSI) over wide load-power-factor range. This modulation
method, which requires only one carrier, contributes to a lifetime extension of smoothing capacitors ina motor drive system. Furthermore, by realizing this modulation method with only one carrier, a highcost hardware such as a field-programmable gate array (FPGA) is not necessary. By adding an offset tovoltage references of conventional DPWM, and shifting two unclamped voltage references in every half
control period, the dc-link current harmonics are reduced even when load power factor changes. It isclarified by experiments that the proposed DPWM reduces the dc-link current harmonics by 18.4% at
most at modulation index of 0.705 and load power factor of 0.819.

I.

Introduction

Three-phase AC motors are widely used in both the industrial and household applications [1]-[7].
Recently, lifetime extension of AC motor drive systems has been actively researched [8]-[9].
Generally, electrolytic capacitors are used as a smoothing capacitor in dc-link of three-phase VSI.
The smoothing capacitor absorbs inverter dc-link current harmonics, and eventually deteriorates as aresult of exothermic reaction of its electrolyte. Therefore, the lifetime of the smoothing capacitor is themost critical issue for the lifetime extension of the whole motor drive system. In order to extend thelifetime of the smoothing capacitor, a method applying film capacitors instead of the electrolytic
capacitor as the smoothing capacitor has been proposed [10]. However, this method makes the motor
drive system bulkier because of low energy density of the film capacitors compared to the electrolytic
capacitors.
On the other hand, it is also possible to extend the lifetime of the smoothing capacitor by reducing
the dc-link current harmonics of VSI. Therefore, modulation methods of VSI, which reduce the dc-linkcurrent harmonics of VSI, have been also proposed [8]-[9], [11]. In [8]-[9], double carriers, which
consist of an original triangular carrier and a second triangular carrier whose phase is opposite to thefirst one, are used for the modulation as a double-carrier-comparison pulse width modulation (PWM).
In particular, the dc-link current harmonics are reduced by minimizing the zero vector period bycomparing only one voltage reference with the inverse triangular carrier and comparing the other voltage
references with the original carrier. However, this method leads to a constraint of the digital hardware
due to the generation of the inverse triangular carrier. Furthermore, when the load power factor becomes
lower than 0.866, the dc-link current harmonics cannot be reduced by these methods.
As another approaches to minimize the dc-link current harmonics, a novel space vector PWM(SVPWM) has been proposed in [11]. In this SVPWM, the output voltage space vectors are selected inorder that the zero vector period is shortened. Besides, by changing the output voltage space vectors
according to polarities of output phase currents, the SVPWM in [11] can adapt to the variation of theload power factor. However, the employment of the proposed SVPWM also leads a constraint of thedigital hardware because the SVPWM needs to not only compare the on-duties of the selected output
voltage space vectors with single carrier but also decide the gating signals based on the carriercomparison results in order to realize the optimized combinations of the output voltage space vectors
for the reduction of the dc-link current harmonics.
This paper proposes a novel carrier-comparison DPWM which uses only one carrier in order toreduce the switching-frequency-order dc-link current harmonics of VSI and eliminates the need of thecomplex digital hardware. In other words, the proposed DPWM can be simply implemented by thegeneral-purpose micro-computer for power electronics. In order to use just only one carrier, two
unclamped phase voltage references of the conventional DPWM are shifted in every half control period.
This leads to a smaller fluctuation of the dc-link current around its average value, which reduces the dclink current harmonics. Furthermore, by adding an offset to all voltage references of the DPWM in orderto optimize the phase of clamped voltage reference and its clamped value, the dc-link current harmonics
are reduced even when the load power factor varies.
This paper is organized as follows; first, the reduction method of the dc-link current harmonics byusing the novel voltage references of the DPWM is introduced. Next, the mechanism to adapt thevariation of the load power factor is explained. Finally, the effectiveness of the proposed DPWM is
confirmed by simulation and experiment.

II.

Proposed PWM method to reduce dc-link current harmonics of VSI

A. Conventional discontinuous PWM

Fig. 1 shows a three-phase VSI employed in the motor drive system. The three-phase VSI consistsof three half bridges. If the semiconductor switching devices are assumed to be ideal, the conduction
status of each half bridge can be represented by the binary switching functions as 1, (Sxp : ON, Sxn : OFF)sx  
, ( x  u, v, w)
 0, (Sxp : OFF, Sxn : ON)

Edc

iDC.conv

iDC.in

iC

Sup

Svp

(1).

Swp
iu
iv vuv
iw vvw

+
Cdc

Sun

Svn

Fig. 1. Three-phase two-level VSI employed in motor drive system.

Swn

vwu

Motor
load

Output phase currents of the VSI at steady state operating condition can be expressed as iu  I m cos 2 ft   





 
 iv  I m cos  2 ft 
3







iw  I m cos  2 ft  3   




(2),

where, Im is the maximum value of the output phase current, f is the fundamental frequency, and φ is theload power factor angle, i.e. the phase difference between the phase voltage and phase current,
respectively.
Fig. 2 shows the normalized voltage references of the continuous PWM (CPWM) and DPWM and
an offset for the DPWM at the modulation index of 0.8. These voltage references of the DPWM are
obtained by adding the offset v*offset to the voltage references of the CPWM [12]. The voltage referencesof the CPWM and DPWM and the offset are expressed as * vu .CP WM  m  cos2 ft 

 
 *


 vv.CP WM  m  cos 2 ft 
3 


 
 *

vw.CP WM  m  cos 2 ft  3 
*v*x.DPWM  v*x.CPWM  voffset,

 1  vmax*
voffset 1  vmin(3),

x  u, v, w

(4),

if vmax  vmin ,if vmin ＜vmax ,(5),

v  max[ vu*.CPWM, vv*.CPWM, vw* .CPWM]
and  max***
 vmin  min[ vu .CPWM, vv.CPWM, vw.CPWM ]where, m is the modulation index.
v*x.CPWM
uv*voffsetw

Normalized voltage references [-]1.21.211.0
0.80.80.60.6
0.40.40.20.2
00.0
-0.2
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1
-1.2
-1.2

v *x . DPWM

60 90 120 150 180 210 240 270 300 330 360
0.0016667
00 30
0.0033333
0.005
0.0066667
0.0083333
0.01
0.0116667
0.0133333
0.015
0.0166667
0.0183333
0.02

50 deg.
(zoomed at Fig. 3 and Fig. 4)

2 ft [deg.]

Fig. 2. Normalized voltage references of CPWM, conventional DPWM and offset at m = 0.8.

Fig. 3 shows the zoomed-in waveform of the dc-link current of VSI iDC.in and the switching functions
su ~ sw with the conventional DPWM at the modulation index of 0.8, the phase angle of 50 degrees andthe unity load power factor. The instantaneous value of the dc-link current of VSI is the superpositionsummation of the switched current pulses from each phase leg [13] and calculated asiDC.in  s  i 

x u ,v, w

x

(6).

x

The shaded area in the instantaneous waveform of the dc-link current of VSI in Fig. 3 indicates thetime integral of the difference between the instantaneous value and average value of the dc-link currentof VSI. This difference is absorbed by the smoothing capacitor. Therefore, the shaded area in Fig. 3
expresses the instantaneous root-mean-square (RMS) value of the current flowing into the smoothing
capacitor, which is calculated as22iC . RMS Ts   iDC.in. RMS Ts   iDC.in
1 Ts 2iDC.in. RMS Ts  
iDC.indt


Ts 0
and 
3
i
m  I m cosDC.in 

4


(7).

where, Ts is the control period, Im is the maximum value of the output phase current of VSI and φ is theload power factor angle. It is obvious that the shaded area, expressing the dc-link current harmonics of
VSI, becomes larger when the fluctuation of the dc-link current around its average value is large [14].
In the case of the conventional DPWM, the center of the gate pulses is the same as the center of thecontrol period. As a result, the overlapping period of the gate pulses becomes the longest at any time.
This leads to the large fluctuation of the dc-link current around its average value, i.e. the large dc-linkcurrent harmonics.
B. Proposed discontinuous PWM

The operations of the proposed DPWM change corresponding to the load power factor. At the unity
load power factor, two unclamped voltage references of the conventional DPWM are shifted in every
half control period to reduce the dc-link current harmonics. On the other hand, when the load power
factor becomes low, first, three voltage references is added with an offset, then, two unclamped voltage
references are shifted in half control period.

1

Triangular carrierv *u.DPWM
v *v.DPWM*
v w.DPWM

-1

su
sv
sw
iu+iv
iu

iDC.iniDC.inTs

Fig. 3. Zoomed-in waveforms of dc-link current and switching functions with conventional DPWM at m = 0.8, 2πft = 50 deg., cos φ = 1.

B-I. Operation at unity load power factor
Fig. 4 shows the zoomed-in waveform of the dc-link current of VSI and the switching functions withthe proposed DPWM at the modulation index of 0.8, the phase angle of 50 degrees and the unity load
power factor. In the proposed DPWM, the fluctuation of the dc-link current around its average value isreduced by displacing the center of the gate pulses. Note that the proposed voltage references are realizedbased on the premise that the voltage references can be updated at the positive peak and negative peakof the carrier by the general-purposed micro-computer for power electronics. In particular, the voltage
references of the proposed DPWM for the reduction of the dc-link current harmonics are generated asfollows:

1.
2.

Splitting the control period into “DOWN” and “UP” periods.
Shifting two voltage references, other than the clamped voltage reference of the DPWM, toreach 1 or -1 one after the other in these periods asIn “DOWN” period:
2va*.DP WM  1
v 
1


if va*.DP WM  0,1
v  *
2vb.DP WM  1

if vb*.DP WM  0,

*
a

*
b



if va*.DP WM＜0.

(8)

if vb*.DP WM＜0.

In “UP” period:1
va*   *
2va.DP WM  1

if va*.DP WM  0,

2v *
1
v   b.DP WM
1

if vb*.DP WM  0,*b

if va*.DP WM＜0.

(9)if vb*.DP WM＜0.

where, a and b indicate phases whose the voltage references are not clamped, i.e. the u and v
phases in Fig. 4 for example, v*a.DPWM and v*b.DPWM are the conventional voltage references, v*aand v*b are the shifted voltage references in the proposed DPWM.
Note that the average values of these shifted voltage references in the control period are as same as thoseof the conventional voltage references. With these shifted voltage references, the overlapping period of
the switching functions is shortened. Consequently, this leads the reduction of the dc-link current
harmonics.
1v *v
Triangular carrierv *u.DPWM
v *v.DPWM
v

v *u

*
w.DPWM

v w*-1“DOWN” period“UP” period

su
sv
sw
iu+iv
iDC.iniu
iDC.iniv
TsFig. 4. Zoomed-in waveforms of dc-link current and switching functions with proposed DPWM at m = 0.8, 2πft = 50 deg., cos φ = 1.

However, note that the reduction effect on the dc-link current harmonics of the proposed DPWM
depends on the load power factor because the instantaneous value of the dc-link current of VSI depends
on the output phase currents. Therefore, it is necessary to deal with the variation of the load power factor
in order to reduce the dc-link current harmonics of VSI over wide power factor range, which is a typicalrequirement of the motor drive system.
B-II. Operation over wider load-power-factor range

Table I shows the definitions of the sectors which are determined by the combination of the detected
output phase currents of VSI. These sectors (A~F) are necessary to recognize the conditions of the output
phase currents.
Fig. 5 shows the conventional and shifted voltage references at the modulation index of 0.8 and theload power factor of 0.966 (φ = 15 deg.). In order to employ the proposed DPWM to any condition of
the load power factor, first, three conventional voltage references v*x.DPWM (x = u, v, w) are added withthe offset v*offset.2 to obtain the voltage references with the offset v*x.PDPWM. Note that the offset value
v*offset.2 is optimized according to the conditions of the output phase currents and the clamped phase. In
the case of sector B, for example, where iu and iv are positive and iw is negative, the switching functionof w phase must be 0 to obtain the minimum fluctuation of the dc-link current around its average value.
If the switching function of w phase becomes 1 during sector B, the instantaneous value of the dc-linkcurrent becomes negative, which leads to the large fluctuation of the dc-link current around its averagevalue, i.e. the large dc-link current harmonics. Next, two unclamped phase voltage references are shiftedin every half control period according to (8)-(9), which results in the voltage references v*x of the
proposed DPWM.

TABLE I
SECTOR DEFINITIONS OF PROPOSED DPWM.
Current polarity
Optimized
Sector(P: Positive, N: Negative)
clamped value
KOCV
iu
iv
iw
A

P

N

N

B

P

P

N

1
-1

C

N

P

N

1

D

N

P

P

-1

E

N

N

P

1

F

P

N

P

-1

Proposed Sector
E
D
C

B

A

F
A

Output phase currents
0

iu

iv

iw

Voltage references of conventional DPWM***
vu.DPWM
vv.DPWM
vw.DPWM
0*

Adding offset voffset.2
0

Voltage references with voffset.2 at  = 15 deg.
***
vu.PDPWM
vv.PDPWM
vw.PDPWM*

0

Voltage references of proposed DPWM at  = 15 deg.
v*u
v*v
vw*
0

2 ft

45°

105°

165°

225°

285°

345°

Fig. 5. Proposed voltage references at m = 0.8, cos φ = 0.966 (φ = 15 deg.). v*x.PDPWM are generated by adding an offset v*offset.2 to v*x.DPWM
in order to keep the clamped period of the voltage reference at each proposed sector. The voltage references of the proposed DPWM v*x
are finally generated by shifting two unclamped voltage references of v*x.PDPWM in every half control period.

Proposed Sector
D
C

F
B

A

Output phase currents
iv

iu

0

F

E

iw

Voltage references of conventional DPWM***
vu.DPWM
vv.DPWM
vw.DPWM
0*

Adding offset voffset.2
0

Voltage references with voffset.2 at  = 45 deg.
***
vv.PDPWM
vw.PDPWM
vu.PDPWM*

0

Voltage references of proposed DPWM at  = 45 deg.
Applying conventional DPWM
v*u
v*v
vw*
0

2 ft 15°

75°

135°

195°

255°

315°

Fig. 6. Proposed voltage references at m = 0.8, cos φ = 0.707 (φ = 45 deg.). In gray periods, the voltage references of the conventional
DPWM are applied to avoid the overmodulation operation due to adding the v*offset.2.

In the proposed DPWM, by adding the offset to all voltage references of the conventional DPWM,
the phase of the clamped voltage reference and its clamped value are adjusted optimally for the reductionof the dc-link current harmonics of VSI at each proposed sector. The voltage references v*x.PDPWM of the
proposed DPWM and the offset v*offset.2 adding to the conventional voltage references v*x.DPWM iscalculated as*
v*x.PDPWM  v*x.DPWM  voffset.2 ,x  u, v, w, KOCV  vu*.PWM
**and voffset.2   K OCV  vv .PWM*
K
 OCV  vw.PWM

if sector  A, D,
if sector  B, E,(10),

if sector  C, F.

where, KOCV is the optimized clamped value of the voltage reference at each proposed sector, as shownin table I.
Fig. 6 shows the proposed voltage references at the load power factor of 0.707 (φ = 45 deg.). Whenthe load power factor is lower than 0.866 (φ < 30 deg.), the periods when the absolute values of the
proposed voltage references v*x.PDPWM becomes more than 1 due to adding the offset v*offset.2 at each sector.
Therefore, the voltage references v*x.DPWM of the conventional DPWM are applied in these periods asshown in the shaded areas in Fig. 6, in order to avoid the overmodulation operation. Accordingly, thephase of the clamped voltage reference is not the optimized value for the reduction of the dc-link current
harmonics in these periods. Thus, the shifting of two unclamped voltage references in every half control
period are not performed in these periods.

III.

Simulation and experimental results

The performances of the conventional and proposed DPWM are investigated by simulation andexperiment. The switching frequency of VSI is 10 kHz. In the experiment, a three-phase induction motor(MVK8115A-R, Fuji Electric Co., Ltd.), the rated power of which is 3.7 kW, is used as a test motor.
The load power factor is varied from 0.259 to 0.819, in the case of driving mode, by controlling thetorque of a load motor.

Fig. 7 shows the u-phase voltage reference, the measured line voltage, the dc-link current and uphase output line current of VSI with each modulation method at the modulation index of 0.705 and theload power factor of 0.819. When the load power factor is 0.819, the applying interval of the proposed
DPWM is long and two unclamped voltage references are shifted in half control period as shown in Fig.
7(b). It is confirmed that the width of the step change in the dc-link current of VSI is reduced by applying
the proposed DPWM. On the other hand, the switching-frequency-order harmonic components of theoutput line voltage are worsened by the proposed DPWM as it could be predicted since an instantaneousvoltage error during the control period is higher with the gate pulses of the proposed DPWM than thosewith the conventional DPWM.
Fig. 8 shows the harmonic components of the dc-link current of VSI under the same conditions as
Fig. 7. The value of 100% at the vertical axis means the maximum value of the output phase current. By
applying the proposed DPWM, the switching-frequency-order harmonic components of the dc-linkcurrent is reduced by 5.49%.
Fig. 9 shows the simulation and experimental results of the dc-link current harmonics with each
modulation method when the modulation index and the load power factor is varied respectively. Notethat the dc-link current harmonics are evaluated as IDC.in(p.u.), which is the RMS value of the dc-linkcurrent (IDC.in.RMS) normalized by the maximum value of the output current (Im) of VSI.
I
1
I DC.in(p.u.)  DC.in. RMS 
Im
Im

 1

iDC.in.k 2
k 1 


2(11),

where, k is the harmonic order and iDC.in.k is the k-order component of the dc-link current harmonics. The
fundamental component of the dc-link current harmonics is 50 Hz at rated load. The harmonicvu* [2.0 -/div.]*
vu.DPWM[2.0 -/div.]00

vuv [500 V/div.]

vuv [500 V/div.]00iDC.in [20 A/div.]

iDC.in [20 A/div.]00iu [20 A/div.]

iu [20 A/div.]00[10 ms/div.][10 ms/div.](a) With conventional DPWM.

(b) With proposed DPWM.

Fig. 7. u-phase voltage reference, line voltage, dc-link current and u-phase output line current of VSI at m = 0.705 and cos φ = 0.819.

100

100
IDC.in(p.u.) = 0.412 [p.u.]

20.9 %

IDC.in(p.u.) = 0.336 [p.u.]

1

0.1
0.01
0.001
10

15.4 %

10
Input current [%]Input current [%]

10

1

0.1
0.01

100

1000
10000
Frequency [Hz](a) With conventional DPWM.

100000

0.001
0.001
10

100

1000
10000
Frequency [Hz](b) With proposed DPWM.

100000Fig. 8. Harmonic components on dc-link current of VSI at m = 0.705 and cos φ = 0.819 (under same conditions of Fig. 7).
The fundamental frequency is 30 Hz. By the employment of the proposed DPWM, the switching-frequency-order harmonic component isreduced by 5.5%.

components of the dc-link current up to 20th-order of the switching frequency are considered in thisevaluation because the switching frequency harmonic components of the dc-link current with theconventional and proposed DPWM above 20th-order are small and comparable as shown in Fig. 8. The
dc-link current harmonics are reduced over entire range of the modulation index and the load power
factor by applying the proposed DPWM. At the load power factor of 0.819, i.e. the high load power
factor, the value of IDC.in(p.u.) is reduced by 18.4% at most by applying the proposed DPWM comparedto that of the conventional DPWM. It is also confirmed that as the load power factor becomes lower, thedc-link current-harmonic-reduction effect of the proposed DPWM decreases because the applying
interval of the proposed DPWM is short as shown in Fig. 6. However, when the load power factor islow, the dc-link current harmonics are also low. On the other words, the large dc-link current harmonics
in the case of the high load power factor which can be drastically reduced by applying the proposed
DPWM should be focused.
Fig. 10 shows the total harmonic distortion (THD) of the u-phase output line current at the load
power factor of 0.819. The harmonic components of the u-phase output line current up to 40th-order ofthe fundamental frequency are considered in this evaluation. Although the proposed DPWM reduces the
dc-link current harmonics, it also worsens the output voltage harmonics as a trade-off as shown in Fig.
7. However, the worsened components by the proposed DPWM is the switching-frequency-orderharmonic components. This means that the impacts of the employment of the proposed DPWM on the
low-order harmonic components of the output line voltage and phase current is low. Therefore, the load
current qualities of the conventional and proposed DPWM are comparable.

0.50

0.50

cos φ = 0.819(φ = 35 deg.)Lines : Sim. results
Plots : Exp. results

Lines : Sim. results
Plots : Exp. results
0.40

IDC.in(p.u.) [p.u.]

IDC.in(p.u.) [p.u.]

0.40
0.30
0.20

cos φ = 0.707(φ = 45 deg.)cos φ = 0.259(φ = 75 deg.)

0.10

cos φ = 0.819(φ = 35 deg.)

0.30
0.20

cos φ = 0.707(φ = 45 deg.)cos φ = 0.259(φ = 75 deg.)

0.10

0.00

0.00
0.0

0.2

0.4

0.6

0.8

1.0

1.2

0.0

0.2

Modulation index m [-](a) With conventional DPWM.

0.4

0.6

0.8

1.0

1.2

Modulation index m [-](b) With proposed DPWM.

Fig. 9. Simulation and experimental results of dc-link current harmonics with each modulation method when modulation index and load
power factor are varied respectively.

THD of iu [%]

14.0
12.0

cos φ = 0.819(φ = 35 deg.)

10.0

Conventional DPWM (fsw = 10 kHz)

8.0
6.0
4.0

Proposed DPWM (fsw = 10 kHz)

2.0
0.0
0.0

0.2

0.4

0.6

0.8

1.0

1.2

Modulation index m [-]Fig. 10. Measured total harmonic distortion of u-phase output line current with each modulation method at cos φ = 0.819.
The switching frequency is 10 kHz.

IV.

Conclusion

This paper proposed the novel DPWM to reduce the dc-link current harmonics of VSI over entire
load power factor range. This modulation method, which required only one carrier, contributed to thelong lifetime of the smoothing capacitor in the motor drive system. By realizing this modulation methodwith only one carrier, high cost hardware such as FPGA was not necessary. The dc-link current
harmonics were reduced by adding an offset to the all voltage references of the conventional DPWM,
and shifting two unclamped voltage references in every half control period. These optimized the phaseof the clamped voltage reference and its clamped value for the reduction of the dc-link current harmonics
of VSI even when the load power factor varied.
The effectiveness of the proposed DPWM was confirmed by the simulation and experiment. These
results confirmed that the dc-link current harmonics were reduced by 18.4% at most at the load power
factor of 0.819 by applying the proposed DPWM. Moreover, it was also confirmed that the dc-linkcurrent harmonics were reduced over entire range of the load power factor.

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