DATA SHEET
www.onsemi.com

8 MHz, Rail-To-Rail, CMOS
Operational Amplifier

51
SC70−5
CASE 419A

NCS20161, NCS20162,
NCS20164, NCV20161,
NCV20162, NCV20164

TSOP−5/SOT23−5
CASE 483

8The NCS20161, NCS20162, and NCS20164 are a family of single,
dual and quad operational amplifiers (op amps) that provide 8 MHz
gain−bandwidth product while consuming 500 A of quiescentcurrent per channel. The NCS2016x has an input offset voltage of
0.3 mV and operates from 1.8 V to 5.5 V supply over a wide
temperature range (−40°C to 125°C). The rail−to−rail input and output
operation allows the use of the entire supply voltage range. Thus, thisseries of op amps offers superior performance over many industry
standard parts. These devices are AEC−Q100 qualified when denotedby the NCV prefix.
With low current consumption and low supply voltage operation inindustry standard packages, the NCS20161 series is ideal for sensor
signal conditioning and low voltage current sensing applications in
automotive, consumer and industrial markets.

1
Micro8]/MSOP8CASE 846A

14

SOIC−8CASE 751

14
1
TSSOP−14
CASE 948G

1
SOIC−14CASE 751A

DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 2 of this data sheet.

Features• Gain−Bandwidth Product: 8 MHz• Low Supply Current per Channel: 500 A typ (VS = 5.5 V)• Low Input Offset Voltage: ±0.3 mV• Wide Supply Range: 1.8 V to 5.5 V• Wide Temperature Range: −40°C to +125°C• Rail−to−Rail Input and Output• Unity Gain Stable• Available in Single, Dual and Quad Packages• NCV Prefix for Automotive and Other Applications Requiring

ORDERING INFORMATION
See detailed ordering and shipping information on page 3 ofthis data sheet.

Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
CompliantApplications• Automotive• Battery Powered / Portable• Sensor Signal Conditioning• Low Voltage Current Sensing• Filter Circuits• Unity Gain BufferThis document contains information on some products that are still under development.
onsemi reserves the right to change or discontinue these products without notice.
© Semiconductor Components Industries, LLC, 2021

July, 2024 − Rev. 3

1

Publication Order Number:
NCS20161/D

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
MARKING DIAGRAMS
Single Channel Configuration
NCS20161, NCV20161
5
XXMG
G

XXXAYWG
G
1

SC70−5
CASE 419A

TSOP−5/SOT23−5
CASE 483

Dual Channel Configuration
NCS20162, NCV20162
8

8
20162
ALYW
G

XXXX
AYWG
G

1

1
Micro8]/MSOP8CASE 846A

SOIC−8CASE 751

Quad Channel Configuration
NCS20164, NCV20164
14

14
XXXX
XXXX
ALYWG
G

20164GAWLYWW
1

1
TSSOP−14
CASE 948G

SOIC−14CASE 751A

XXXXX = Specific Device CodeA
= Assembly Location
WL, L = Wafer Lot
Y= YearWW, W = Work Week
G or G = Pb−Free Package(Note: Microdot may be in either location)www.onsemi.com
2

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
Single Channel Configuration
NCS20161, NCV20161
5

1

OUT

1

IN+

VDD

5

VDD

4

OUT

+
2

VSS

−

3

IN+

2

−

+

VSS

4

3

IN−

IN−

SC70−5
SQ3 Pinout

SOT23−5 (TSOP−5)
SN2 Pinout

Quadruple Channel Configuration
NCS20164, NCV20164
Dual Channel Configuration
NCS20162, NCV20162
OUT 1

1

IN− 1

2

IN+ 1

3

VSS

8

VDD

−

7

OUT 2

+

−

6

IN− 2

+

5

IN+ 2

4

Micro8/MSOP8, SOIC−8

OUT 1

1

IN− 1

2

−

− 13 IN− 4

IN+ 1

3

+

+

VDD

4

IN+ 2

5

+

+

10 IN+ 3

IN− 2

6

−

−

9

IN− 3

OUT 2

7

8

OUT 3

14 OUT 4

12 IN+ 4
11 VSSTSSOP−14, SOIC−14

Figure 1. Pin Connections
ORDERING INFORMATION
Package

Shipping†

TBD

SC70

3000 / Tape and Reel

TBD

SOT23−5/TSOP−5

3000 / Tape and Reel

TBD

SC70

3000 / Tape and Reel

TBD

SOT23−5/TSOP−5

3000 / Tape and Reel

TBD

Micro8/MSOP84000 / Tape and Reel

Device*Configuration

Automotive

Marking

NCS20161SQ3T2G**

SingleNo

NCS20161SN2T1G**
Yes

NCV20161SQ3T2G**
NCV20161SN2T1G**
NCS20162DMR2G**

Dual

No

NCS20162DR2G
NCV20162DMR2G**

20162

SOIC−82500 / Tape and Reel

Yes

TBD

Micro8/MSOP84000 / Tape and Reel

20162

SOIC−82500 / Tape and ReelNo

20164G

SOIC−142500 / Tape and Reel

TBD

TSSOP−142500 / Tape and Reel20164G

SOIC−142500 / Tape and Reel

TBD

TSSOP−142500 / Tape and Reel

NCV20162DR2G
NCS20164DR2G

Quad

NCS20164DTBR2G**
NCV20164DR2G
NCV20164DTBR2G**

Yes†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAPCapable.
**In Development. Contact local sales office for more information.

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3

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
ABSOLUTE MAXIMUM RATINGS (Note 1)
SymbolRating

Limit

Unit

Supply Voltage (VDD – VSS)

VS

−0.3 to 6

V

Common Mode Input Voltage

VI

VSS−0.3 to VDD+0.3

V

Differential Input Voltage

VID

VDD – VSS+0.2

V

Maximum Input Current

II

±10

mA

Maximum Output Current (Note 2)

IO

±100

mA

Continuous Total Power Dissipation (Note 2)

PD

200

mW

Maximum Junction Temperature

TJ

150

°C

Storage Temperature Range

TSTG−65 to 150_C

Mounting Temperature (Infrared or Convection – 20 sec)

Tmount260_C

ESD Capability (Note 3)

HBM
CDM

2500
1500

V

Latch−Up Current (Note 4)

ILU

100

mA

Moisture Sensitivity Level (Note 5)

MSL

Level 1

Human Body Model
Charge Device ModelStresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS for Safe Operating Area.
2. Continuous short circuit operation to ground at elevated ambient temperature can result in exceeding the maximum allowed junction
temperature of 150°C. Output currents in excess of the maximum output current rating over the long term may adversely affect reliability.
Shorting output to either VDD or VSS will adversely affect reliability.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JEDEC standard Js−001−2017 (AEC−Q100−002)
ESD Charged Device Model tested per JEDEC standard JS−002−2014 (AEC−Q100−011)
4. Latch−up Current tested per JEDEC standard JESD78E (AEC−Q100−004)
5. Moisture Sensitivity Level tested per IPC/JEDEC standard: J−STD−020A

OPERATING RANGES
Symbol

Min

Max

Unit

Operating Supply Voltage (VDD − VSS)

Parameter

VS

1.8

5.5

V

Differential Input Voltage

VID

−

VS

V

Common Mode Input Voltage Range

VCM

VSS – 0.1

VDD + 0.1

V

Ambient Temperature

TA

−40

125

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.

THERMAL CHARACTERISTICS (Note 6)
Junction−to−Ambient
Thermal ResistanceJA

Junction−to−Case Top
Thermal ResistanceJT

Junction−to−Board
Thermal Resistance
JB

Unit

SOIC−8

205

32

116

°C/W

SOIC−14

138

8

100

°C/W

Package

6. Thermal parameters are based on a 2s2p board following JESD51−7 (JEDEC).

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4

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
ELECTRICAL CHARACTERISTICS AT VS = 1.8 V to 5.5 V

TA = 25°C; RL ≥ 10 k connected to mid−supply; VCM = VOUT = mid−supply unless otherwise noted.
Boldface limits apply over the specified temperature range, TA = −40°C to 125°C. (Note 7)
Min

Typ

Max

Unit

VS = 5 V

−

±0.3

±2.1

mV

VS = 5 V

−

−

±2.6

mV

VS = 5 V

−

±1.5

−

V/°C

−

±5

−

pA

−

±5

−

pA

−

100

−

dB

−

4

−

pF

VS = 5.5 V, VCM = VSS − 0.1 V to VDD − 1.4 V

80

103

−

dB

VS = 5.5 V, VCM = –0.1 V to 5.6 V

57

79

−

VS = 1.8 V, VCM = VSS − 0.1 V to VDD − 1.4 V

−

91

−

VS = 1.8 V, VCM = –0.1 V to 1.9 V

−

71

−

VS = 1.8 V, VSS + 0.04 V < VO < VDD – 0.04 V,
RL = 10 k

−

100

−

VS = 5.5 V, VSS + 0.05 V < VO < VDD – 0.05 V,
RL = 10 k

101

108

−

VS = 1.8 V, VSS + 0.06 V < VO < VDD – 0.06 V,
RL = 2 k

−

97

−

VS = 5.5 V, VSS + 0.15 V < VO < VDD – 0.15 V,
RL = 2 k

−

113

−

Output sourcing current VS = 5 V

−

40

−

mA

Output sinking current, VS = 5 V

−

50

VDD −
VOH

VS = 5.5 V, RL = 10 k

−

3

20

mV

VS = 5.5 V, RL = 2 k

−

−

60

VOL −
VSS

VS = 5.5 V, RL = 10 k

−

3

20

VS = 5.5 V, RL = 2 k

−

−

60

Unity Gain Bandwidth

UGBW

VS = 5 V, G = +1

−

8

−

MHz

Slew Rate at Unity GainSR

VS = 5 V, G = +1

−

3.5

−

V/s

Phase Marginm

VS = 5 V, G = +1

−

52

−

_

Gain Margin

Am

−

11

−

dB

Settling Time to 0.1%

tS

VS = 5 V, VIN = 2 V step, G = +1, CL = 100 pF

−

0.5

−

μs

Settling Time to 0.01%

tS

VS = 5 V, VIN = 2 V step, G = +1, CL = 100 pF

−

1

−

μs

Overload Recovery TimetOR

VS = 5 V, VIN x gain > VS

−

1

−

μs

Open Loop Output Impedance

ZOL

VS = 5 V, f = 10 MHz

−

240

−



VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1,
f = 1 kHz−

0.0008−%VS = 5 V, f = 1 kHz

−

20

−

nV/√HzVS = 5 V, f = 10 kHz

−

10

−

Parameter

SymbolConditions

INPUT CHARACTERISTICS
Input Offset Voltage

Offset Voltage Drift

VOS
dVOS/dT

Input Bias Current (Note 7)

IIB

Input Offset Current (Note 7)

IOS

Channel Separation
Input CapacitanceCommon Mode Rejection Ratio

DC
CIN
CMRR

OUTPUT CHARACTERISTICS
Open Loop Voltage Gain

Short Circuit Current

Output Voltage Swing from VDD

Output Voltage Swing from VSS

AVOL

ISC

dB

mV

AC CHARACTERISTICSNOISE CHARACTERISTICS
Total Harmonic Distortion plus Noise
Input Referred Voltage Noise

THD+n
en

7. Performance guaranteed over the indicated operating temperature range by design and/or characterization.

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5

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
ELECTRICAL CHARACTERISTICS AT VS = 1.8 V to 5.5 V (continued)
TA = 25°C; RL ≥ 10 k connected to mid−supply; VCM = VOUT = mid−supply unless otherwise noted.
Boldface limits apply over the specified temperature range, TA = −40°C to 125°C. (Note 7)
Parameter

SymbolConditions

Min

Typ

Max

Unit

NOISE CHARACTERISTICS
Input Referred Current Noiseinf = 1 kHz

−

20

−

fA/√HzInput Voltage Noise, Peak−to−Peak

En

VS = 5 V, f = 0.1 Hz to 10 Hz

−

5

−

μVPP

Power Supply Rejection Ratio

PSRR

VS = 1.8 V – 5.5 V, VCM = VSS

−

8

80

μV/V

Power Supply Quiescent Current

IQ

Per channel, no load

−

500

800

μA

SUPPLY CHARACTERISTICS

7. Performance guaranteed over the indicated operating temperature range by design and/or characterization.

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6

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
TYPICAL CHARACTERISTICS(AT TA = 25°C, VCM = MID−SUPPLY, CL = 20 PF, RL = 10 K TO MID−SUPPLY, UNLESS OTHERWISE NOTED)
25
20

105 Units

NUMBER OF UNITSNUMBER OF UNITS

20

VS = 5 V

15
10

18

VS = 5 V

16

105 Units

14
12
10
8
6
4

5

2
−1.0

−0.6

−0.2

0.2

0.6

1.0

0

1.4

1500

1000
500
0
−500
VS = 5.5 V

1

2

3

4

1000
500
0
−500
−1000

VS = 1.8 V−1500

5 typical units−2000−0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

COMMON MODE VOLTAGE (V)COMMON MODE VOLTAGE (V)Figure 4. Input Offset Voltage vs. Common
Mode Voltage at 5.5 V Supply

Figure 5. Input Offset Voltage vs. Common
Mode Voltage at 1.8 V Supply

2000

2000

1500

1500

INPUT OFFSET VOLTAGE (V)

INPUT OFFSET VOLTAGE (V)

5 typical units−2000−0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

1000
500
0
−500

−1500

0

Figure 3. Input Offset Voltage Drift Distribution

1500

−1000

−1

Figure 2. Input Offset Voltage Distribution
2000

−1500

−2

INPUT OFFSET VOLTAGE DRIFT (V/°C)

2000

−1000

−3

INPUT OFFSET VOLTAGE (mV)

INPUT OFFSET VOLTAGE (V)

INPUT OFFSET VOLTAGE (V)0
−1.4

VS = 5.5 V
VCM = mid−supply

−2000
−50

5 typical units
−25

0

25

50

75

100

125

150

1000
500

VS = 1.8 V
VCM = mid−supply

0
−500
−1000
−1500
−2000
−50

−25

0

25

50

75

100

125

150

TEMPERATURE (°C)

TEMPERATURE (°C)

Figure 6. Input Offset Voltage vs. Temperature
at 5.5 V Supply

Figure 7. Input Offset Voltage vs. Temperature
at 1.8 V Supply

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7

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
TYPICAL CHARACTERISTICS(AT TA = 25°C, VCM = MID−SUPPLY, CL = 20 PF, RL = 10 K TO MID−SUPPLY, UNLESS OTHERWISE NOTED)
160
OPEN LOOP VOLTAGE GAIN (V/V)

100

Phase

80
60
Gain
40
20
0
−20

VS = 5 V
10

100

1K

10K

100K

1M

80
60
40
20
0
−50

0
−10
AV = 1
AV = −1
AV = 10

0.8

100

1K

10K

100K

1M

0.6

400

VS = 5.5 V

300
200
100

−25

0

25

50

75

100

125 150

TEMPERATURE (°C)

Figure 10. Closed Loop Gain vs. Frequency

Figure 11. Input Current vs. Temperature

0.4
0.3
0.2
0.1

VS = 5.5 V
0

125 150FREQUENCY (Hz)

0.5

0

100

IIB+
IIB−
IOS

−100
−50

10M

TA = −40°C
TA = 25°C
TA = 85°C
TA = 125°C

0.7

75

0

VS = 5.5 V
1050

Figure 9. Open Loop Gain vs. Temperature

500

−50

25

Figure 8. Open Loop Gain vs. Frequency

20

−40

0

TEMPERATURE (°C)

600

−30

−25

FREQUENCY (Hz)OUTPUT VOLTAGE SWING TO VSS (V)GAIN (dB)

100

10M

10

OUTPUT VOLTAGE SWING TO VDD (V)

120

30

−20

VS = 5.5 V
VS = 1.8 V

140

INPUT CURRENT (pA)

GAIN (dB) AND PHASE (°)

120

10

20

30

40

0.7

TA = −40°C
TA = 25°C
TA = 85°C
TA = 125°C

0.6
0.5
0.4
0.3
0.2
0.1
0

VS = 5.5 V
0

10

20

30

40

50

OUTPUT CURRENT (mA)

OUTPUT CURRENT (mA)

Figure 12. Output Voltage Swing High

Figure 13. Output Voltage Swing Low

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860

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
TYPICAL CHARACTERISTICS(AT TA = 25°C, VCM = MID−SUPPLY, CL = 20 PF, RL = 10 K TO MID−SUPPLY, UNLESS OTHERWISE NOTED)
120

120

VIN = 0 dBm

10080
PSRR (dB)

CMRR (dB)

80
60
40
20
VS = 1.8 V
VS = 5.5 V
10

100

1K

10K

100K

1M

20

−40

10M

VS = 1.8 V, PSRR+
VS = 1.8 V, PSRR−
VS = 5.5 V, PSRR+
VS = 5.5 V, PSRR−

5

−3
−4

VS = 5.5 V

0

4
3
2
1

VCM = −0.1 V to 4.1 V
−25

10M

Figure 15. PSRR vs. Frequency

−1

−7
−50

100K

Figure 14. CMRR vs Frequency
6

−6

1K

FREQUENCY (Hz)

0

−5

10

FREQUENCY (Hz)PSRR (V/V)

CMRR (V/V)

40

−20

−2

25

50

75

100

125

0
−50

150

VS = 1.8 V to 5.5 V
−25

0

25

50

75

100

125

TEMPERATURE (°C)

TEMPERATURE (°C)

Figure 16. CMRR vs Temperature

Figure 17. PSRR vs. Temperature

VOLTAGE NOISE DENSITY (nV/√Hz)

4
3
2
VOLTAGE (V)

60

0

0
−20

VIN = −10 dBm

100

1
0
−1
−2
VS = 5.5 V
VS = 1.8 V

−3
−4

180

VS = 5 V

160
140
120
100
80
60
40
20
0

10

100

1K

10K

100K

TIME (1 s/div)

FREQUENCY (Hz)Figure 18. 0.1 Hz to 10 Hz Noise

Figure 19. Voltage Noise Density vs.
Frequency

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9

150

1M

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
TYPICAL CHARACTERISTICS(AT TA = 25°C, VCM = MID−SUPPLY, CL = 20 PF, RL = 10 K TO MID−SUPPLY, UNLESS OTHERWISE NOTED)
−90
−95
−100

−20
−30

−105
−110

−90
10

100

1K

−100

10K

1

Figure 21. THD+n vs. Output Amplitude
510

510
500
490
480
−25

0

25

50

75

100

125

500
490
480
470
460
450

150

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)Figure 22. Quiescent Current Per Channel vs.
Temperature

Figure 23. Quiescent Current Per Channel vs.
Supply Voltage

0.08

3

0.06

2

0.04
0.02
0

VOLTAGE (V)VOLTAGE (V)

0.1

Figure 20. THD+n vs. Frequency

520

Input
Output

−0.02
−0.04

−0.06
−0.10
−0.12

0.01

AMPLITUDE (VRMS)

VS = 5.5 V

470
−50

0.001

FREQUENCY (Hz)

530

−0.08

−60
−80

QUIESCENT CURRENT (A)

QUIESCENT CURRENT (A)

540

−40
−50
−70

−115
−120

VS = 5.5 V
RL = 2.2 k to mid−supply
VIN = 0.5 VRMS
AV = −1−10

THD+n (dB)

THD+n (dB)0

VS = 5.5 V
RL = 2.2 k to mid−supply
VIN = 0.5 VRMS
AV = 110

Input
Output−1

VS = 5.5 V−2

AV = 1−3

VS = 5.5 V
AV = 1

TIME (0.2 s/div)

TIME (1 s/div)

Figure 24. Small Signal Step Response

Figure 25. Large Signal Step Responsewww.onsemi.com
10

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
TYPICAL CHARACTERISTICS(AT TA = 25°C, VCM = MID−SUPPLY, CL = 20 PF, RL = 10 K TO MID−SUPPLY, UNLESS OTHERWISE NOTED)

SUPPLY VOLTAGE (V)

4

0.3

3

0.2

2

0.1

1
Output00

VDD = 2.75 V
VSS = −2.75 V−1

VOUT TO FINAL VALUE (V)

VDD

3

0.4

−0.1

−1

−3

−0.3

−3

−4

−0.4

−4

TIME (1 s/div)

TIME (100 s/div)

Figure 26. Power Up

Figure 27. No Phase Reversal
160
OPEN LOOP VOLTAGE GAIN (dB)

40
20
0

Sourcing
Sinking

VS = 5 V

−20
−40
−60
−80
−50

−25

0

25

50

75

100

140
120
100
80
60
40
VS = 5.5 V

20
0

125

0

0.5 1.0

1.5 2.0 2.5 3.0 3.5

4.0 4.5 5.0 5.5

TEMPERATURE (°C)

OUTPUT VOLTAGE (V)Figure 28. Short Circuit Current vs.
Temperature

Figure 29. Open Loop Gain vs. Output Voltage

1.5

1

0.5
0

VS = 5.5 V
AV = −1
CL = 100 pF

−0.5

−1
−2
−3

−1.0

−4

−1.5

−5

1.5

5

1.0

4
Input
Output0.5
032

VS = 5.5 V
AV = −1
CL = 100 pF

−0.5

1

−1.0

0

−1.5

−1

TIME (500 ns/div)

TIME (500 ns/div)

Figure 30. Output Low−to−High Settling Time

Figure 31. Output High−to−Low Settling Timewww.onsemi.com
11VOUT TO FINAL VALUE (mV)0
Input
OutputVOUT TO FINAL VALUE (mV)

1.0

INPUT VOLTAGE (V)OUTPUT CURRENT (mA)

0

−2

VSS

60

INPUT VOLTAGE (V)

1

−0.2

−2

Input
Output2
VOLTAGE (V)4

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
TYPICAL CHARACTERISTICS(AT TA = 25°C, VCM = MID−SUPPLY, CL = 20 PF, RL = 10 K TO MID−SUPPLY, UNLESS OTHERWISE NOTED)
100

300

90
250

80
IMPEDANCE ()EMIRR (dB)

70
60
50
40
30
20

150
100
50

10
0

200

10M

100M

0

10G

1G

VS = 5 V
10K

100K

1M

FREQUENCY (Hz)FREQUENCY (Hz)Figure 32. EMIRR vs. Frequency

Figure 33. Open Loop Output Impedance vs.
Frequency

060
VS = 5 V

VS = 5 V
50
PHASE MARGIN (°)

CROSSTALK (dB)

−20
−40
−60
−80
−100
−120

10M

40
30
20
10

10

100

1K

10K

100K

1M

0

10M

0

50

100

150

200

250

FREQUENCY (Hz)CAPACITIVE LOAD (pF)

Figure 34. Channel Separation vs. Frequency

Figure 35. Phase Margin vs. Capacitive Loadwww.onsemi.com
12

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
TYPICAL CHARACTERISTICS(AT TA = 25°C, VCM = MID−SUPPLY, CL = 20 PF, RL = 10 K TO MID−SUPPLY, UNLESS OTHERWISE NOTED)
50
40

40

35
30
25
20
15
10
5
0

50

100

150

200

250

30
25
20
15
Rising Edge
Falling Edge

5
0

300

0

50

100

150

200

250

300

CAPACITIVE LOAD (pF)

CAPACITIVE LOAD (pF)

Figure 36. Overshoot vs. Capacitive Load for
AV = 1Figure 37. Overshoot vs. Capacitive Load for
AV = −1

1.5

3.0
VS = 5.5 V
AV = −10

1.0
0.5

2.0

0

1.5

−0.5
−1.0
−1.5

VS = 5.5 V
AV = −10

2.5

VOLTAGE (V)VOLTAGE (V)35

10Rising Edge
Falling Edge0

VS = 5.5 V
AV = −145

OVERSHOOT (%)

OVERSHOOT (%)

50

VS = 5.5 V
AV = 1

45

−2.0

1.0
0.5
0
−0.5

Input
Output

−2.5
−3.0

Input
Output−1.0−1.5

TIME (1 s/div)

TIME (1 s/div)

Figure 38. Negative Overvoltage Recovery

Figure 39. Positive Overvoltage Recovery

www.onsemi.com
13

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
APPLICATION INFORMATION
events (within the limits specified) trigger the protection
structure so the operational amplifier is not damaged.
In order to safe guard against excessive voltages across theop amp’s inputs, external clamp diodes can be used as shownin Figure 40. The four low−drop fast diodes (Schottky
preferred) are used in parallel with the internal structure todivert the excessive energy to the supply rails where it canbe easily dissipated or absorbed by the supply capacitors.
The application designer should also take into account thatthese external diodes add leakage currents and parasitic
capacitance that must be considered when evaluating theend−to−end performance of the amplifier stage.

The NCS20161 family of operational amplifiers is
manufactured using onsemi’s CMOS process. Products inthis class are general purpose, unity−gain stable amplifiers
and include single, dual and quad configurations.
Rail−to−Rail Input with No Phase Reversal

The NCS2016x operational amplifiers are designed toprevent phase reversal or any similar issues when the input
pins potential exceed the supply voltages by up to 100 mV.
The input stage of the NCS20161 family consists of two
differential CMOS input stages connected in parallel: thefirst is constructed using paired PMOS devices and it
operates at low common mode input voltages (VCM); thesecond stage is build using paired NMOS devices to operate
at high VCM. The transition between the two input stages
occurs at a common mode input voltage of approximately
VDD−1.3V.

Limiting Input Currents

In order to prevent damage/ improper operation of theseamplifiers, the application circuit must limit the current
flowing through the input pins. A possible solution ispresented in Figure 40 by means of the two added series
resistors. The minimum value for the input resistors should
be calculated using Ohm’s Law so they limit the input pin
current to less than the absolute maximum values specified.
The application designer should take into account that these
resistors also add parasitic inductance that must be
considered when evaluating performance.
Combining the current limiting resistors with the voltage
limiting diodes creates a solid input protection structure, thatcan be used to insure reliable operation of the amplifier evenin the hardest conditions.

Limiting Input Voltages

In order to prevent damage and/or improper operation ofthese amplifiers, the application circuit must never expose
the input pins to voltages or currents higher than the
Absolute Maximum Ratings.
The internal ESD structure includes special diodes toprotect the input stages while maintaining a low input bias
current (IIB). The input protection circuitry clamp the inputs
when the signals applied exceed more than one diode drop
below VSS or one diode drop above VDD. Very fast ESD

VDD

VDD

VDD
IN+

+

IN+

+

IN+

+

IN−

−

IN−

−

IN−

−

VSS

VSS

VSS

Figure 40. Typical Protection of the Operational Amplifier Inputs
Rail−to−Rail Output♦ degraded phase margin

The maximum output voltage swing is dependent of theparticular output load. According to the specification, theoutput can reach within 20 mV of either supply rail whenload resistance is 10 k. The VOL and VOH graphs shows theload drive capabilities of the part under different conditions.
Output current is internally limited to the typical values
listed in the Electrical Characteristics table.

♦ lowered bandwidth♦ gain peaking of the frequency response♦ overshoot and ringing of the step response

While the NCS2016x series op amps are capable of driving
capacitive loads up to 100 pF, adding a small resistor inseries to the output (RISO in Figure 41) will increase thephase margin. This leads to higher stability by making theequivalent load more resistive at high frequencies.

Capacitive Loads

Driving capacitive loads can create stability problems forvoltage feedback op amps, as it is a known possible cause for:www.onsemi.com
14

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
The unity gain buffer is recommended here (Figure 42).
The ADC’s internal sampling capacitor requires a buffer
front−end to recharge it faster than the sampling time, andthis problem is even worse if more channels are sampled by
the same ADC using an internal multiplexer. In order toachieve a settling time shorter than the multiplexedsampling rate, an RC stage is recommended between thebuffer and the ADC input. The RISO resistor’s value should
be low enough to charge the capacitor quickly, but at thesame time large enough to isolate the capacitive load fromthe amplifier output to preserve phase margin. Whentransients are generated by the sensor’s output, first the two
amplifier inputs see a high differential voltage between
them, then the output settles and brings the inverting input
back to the correct voltage.
Let us take an example of a 0.1 V to 4 V sensor signal. To
successfully accommodate it, the differential input range of
the NCS2016x is close to the supply range and the output
will match the input. The differential input voltage is limited
only by the ESD protection structure and not byback−to−back diodes between inputs.

VDD

IN+

+

IN−

−

RISO

CL
VSS

Figure 41. Driving Capacitive Loads

Simulating the application with onsemi’s Spice model isa good starting point for selecting the isolation resistor’svalue. Bench testing the frequency and step response can beused to fine−tune the value according to the desired
characteristic.
Unity Gain BandwidthInterfacing a high impedance sensor’s output toa relatively low−impedance ADC input usually requires anintermediate stage to avoid unwanted interference of the two
devices, and this stage needs to have a high input impedance,
a low output impedance, and high output current.
VDD

ADC
sensor

+

RISO

−
CL

Csampling

VSS

Figure 42. Unity Gain Buffer Stage for Sampling with ADC
Power Supply Bypassing

crosstalk, increased current consumption, or add noise to the
supply rails.

For AC, the power supply pins (VDD and VSS for split
supply, VDD for single supply) should be bypassed locallywith a quality capacitor in the range of 100 nF as close as
possible to the amplifier supply pins. Ceramic capacitors arerecommended for their low ESR and good high frequency
response.
For DC, a bulk capacitor in the range of 1 μF placed within
inches distance from the op amp can provide the additional
current needed to drive higher loads.

VDD

VDD

Unused Operational Amplifiers

+

+

−

−

VSS

Occasionally not all the op amp channels offered in thequad packages are needed for a specific application. They
can be connected as “buffering ground” as shown in
Figure 43, a solution that does not need any extra parts.
Connecting them differently (inputs split to rails, left
floating, etc.) can sometimes cause unwanted oscillation,

Figure 43. Unused Operational Amplifiers

www.onsemi.com
15

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
PCB Surface Leakage

PCB Routing Recommendations

If it is critical to obtain the lowest input bias current, the
PCB’s surface leakage should be considered. Dry
environment surface current increases further when theboard is exposed to humidity, dust or chemical
contamination. For harsh environment conditions,protecting the entire board surface (with all the exposed
metal pins and soldered areas) is advised. Conformal coatingor potting the board in resin proves effective in most cases.
An alternate solution for reduced leakage is the use of
guard rings around sensitive pins and pads. A proper guard
ring should have low impedance and be biased to the same
voltage as the sensitive pin so that no current flows in
between them.
For an inverting amplifier, the non−inverting input is
usually connected to supply’s ground (or virtual ground at
half the rail voltage in single supply applications) so it canrepresent a good ring solution. When routing the PCB traces,
create a closed perimeter around the inverting input pad (which
carries the signal) and connect it to the non−inverting input.
For a non−inverting amplifier, use a similarly shaped(rectangle or circle) copper trace around the non−inverting
input pad (which carries the signal) and connect it to theinverting input pin, which presents a much lower impedance
thanks to the feedback network.

In addition to amplifying the useful signal, op amps canalso pick the high frequency noise together with the signal
and amplify it accordingly, if the design allows it. In orderto reach the values specified in the Electrical Characteristics
tables and to avoid high frequency interference issues, it isrecommended that the PCB layout follows the basic
guidelines listed below:♦ A dedicated layer for the ground plane should be
used whenever possible and all supply decoupling
capacitors should connect to it by vias
♦ Copper traces should be as short as possible♦ High current paths should not be shared by small
signal or low current traces♦ If present, switching power supply blocks should be
kept away from the analog sensitive areas to avoid
potential conducted and radiated noise issues♦ When different circuit taxonomies share the sameboard, it is recommended to keep separated thepower areas, the digital areas and the small signal
analog areas. Small−signal components in the signal
path should be placed as close as possible to theamplifier input pins
♦ Metal shielding the sensitive areas and the“offender” blocks may be required in some cases

www.onsemi.com
16

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE M

www.onsemi.com
17

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
PACKAGE DIMENSIONSSOIC−8 NB
CASE 751−07
ISSUE AK−X−NOTES:
1. DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

A
8

5

S

B

0.25 (0.010) M Y

M

1
4

−Y−

K

G
C

DIM
A
B
C
D
G
H
J
K
M
N
S

N X 45 _SEATING
PLANE−Z−

0.10 (0.004)
HD
0.25 (0.010) M

Z Y S

M

J

X S

STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1

SOLDERING FOOTPRINT*

1.52
0.060

7.0
0.275

4.0
0.155

0.6
0.024

1.270
0.050
SCALE 6:1

mm Ǔǒinches*For additional information on our Pb−Free strategy
and soldering details, please download theonsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com
18

MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20

INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
PACKAGE DIMENSIONSTSOP−5 3.00x1.50x0.95, 0.95P
CASE 483
ISSUE P

www.onsemi.com
19

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
PACKAGE DIMENSIONS
Micro8CASE 846A−02
ISSUE K

*For additional information on our Pb−Free strategy
and soldering details, please download theonsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com
20

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
PACKAGE DIMENSIONSTSSOP−14 WB
CASE 948G
ISSUE C
14X K REF

0.10 (0.004) M
0.15 (0.006) T U

T U

V

S

S

N
14

2X L/20.25 (0.010)

8

M
B
−U−

L
PIN 1
IDENT.

N
F

7

1

0.15 (0.006) T U

NOTES:
1. DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLDFLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALLNOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.

S

S

DETAIL E

ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
K

A
−V−

K1

J J1

SECTION N−N−W−

C
0.10 (0.004)−T− SEATING
PLANE

D

H

G

DETAIL E

DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M

SOLDERING FOOTPRINT
7.06
1

0.65
PITCH

14X

0.36

14X

1.26

DIMENSIONS: MILLIMETERS

www.onsemi.com
21

MILLIMETERSINCHESMINMAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177−−−
1.20−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_

NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164
PACKAGE DIMENSIONSD
14

SOIC−14 NB
CASE 751A−03
ISSUE LA
B
8

NOTES:
1. DIMENSIONING AND TOLERANCING PERASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE PROTRUSIONSHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.

A3
E

H

L
1

DETAIL A

7
13X b

0.25 M B M

0.25 M C A S

B S

0.10

e

DETAIL AhA

X 45 _M

A1

C SEATING
PLANE

DIM
A
A1
A3
b
D
E
e
H
h
L
M

MILLIMETERSINCHES
MIN
MAX
MIN
MAX
1.35
1.75 0.054 0.068
0.10
0.25 0.004 0.010
0.19
0.25 0.008 0.010
0.35
0.49 0.014 0.019
8.55
8.75 0.337 0.344
3.80
4.00 0.150 0.157
1.27 BSC
0.050 BSC
5.80
6.20 0.228 0.244
0.25
0.50 0.010 0.019
0.40
1.25 0.016 0.049
0_
7_
0_
7_

SOLDERING FOOTPRINT*
6.50

14X

1.18
1

1.27
PITCH

14X

0.58

DIMENSIONS: MILLIMETERS*For additional information on our Pb−Free strategy
and soldering details, please download theonsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.

onsemi,, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of theinformation, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or useof any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance mayvary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any licenseunder any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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For additional information, please contact your local Sales Representative at
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onsemi Website: www.onsemi.com◊

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