Inductance-Independent Nonlinearity Compensation forSingle-Phase Grid-Tied Inverter Operating in bothContinuous and Discontinuous Current Mode
Hoai Nam Le, Student Member, IEEE, Jun-ichi Itoh, Senior Member, IEEE

Abstract— This paper proposes a control for a single-phase grid-tied inverter operating in both continuous (CCM) anddiscontinuous current (DCM) to minimize inductors without worsening a current total harmonic distortion (THD). In a
conventional CCM/DCM control, an inductance is required in a DCM nonlinearity compensation; consequently, the control
becomes inductance-dependent. In the proposed control, a duty ratio at a previous calculation period is utilized to compensate forthe DCM nonlinearity and detect current modes independently from the inductance. A 4-kW 100-kHz prototype of the inverterwith two designs of the inductor is realized to confirm the effectiveness of the proposed control. When the inductor impedance,
which is normalized by an inverter impedance, is reduced from 1.8% to 0.5%, volume and material cost of the inductor are reduced
by 51% and 62%, respectively, whereas the loss at a light load of 0.1 p.u. is reduced by 35%. However, due to this inductor
minimization, the current THD at a rated load increases from 2.3% to 8.7% with the conventional control, which violates the gridcurrent harmonic constraint regulated by standard IEEE-1547. The proposed CCM/DCM control reduces the current THD from
8.7% to 2.1%, which enables the inductor minimization and satisfies the grid standard.
Index Terms— Current control, Single-phase grid-tied inverters, Continuous current mode, Discontinuous current mode,
Nonlinear control systems.
This paper is the updated version of the paper entitled “Mixed conduction mode control for inductor minimization in grid-tied
inverter” presented at PEDS2017 (December 12-15, 2017, Hawaii, USA). In the manuscript, all the old experimental results are
replaced with the new experimental results and the comparisons with the conventional methods are also demonstrated.
Corresponding author-

Ph.D., Prof. Jun-ichi ItohAffiliation: Nagaoka University of Technology
Postal address: 1603-1 Kamitomioka-machi, Nagaoka, Niigata, Japan (Postal code: 940-2188)
Tel: +81-258-47-9563 Fax: +81-258-47-9563
Email: itoh@vos.nagaokaut.ac.jp

I. INTRODUCTION
Over last decades, the application of photovoltaic systems (PV) to residential areas has accelerated due to a continuously
decrease in solar panel price. In the residential PV systems, single-phase grid-tied inverters are required in order to transmit solar
DC power into AC single-phase grid. High efficiency and compact size with low cost are requirements for these inverters in orderto further assist the penetration of the PV systems into the residential areas. In such grid-tied inverters, LCL filters are generally
employed between the output of the inverter and the AC single-phase grid in order to suppress current harmonics and meet gridcurrent harmonic constraints as defined by standards such as IEEE-1547 [1]. Inductors in the LCL filters account for major volume
and cost of the inverter, which can be decreased by a low-inductance LCL filter design [2]-[6]. However, the reduction of theinductance implies a design of a high current ripple due to a high dc-link-voltage-to-inductance ratio. This high current ripple
results in a current distortion phenomenon entitled zero-current clamping, in which the current distortion increases notably as thecurrent ripple increases [7]-[12].
When the zero-current clamping occurs, the inverter operation changes from continuous current mode (CCM) to discontinuous
current mode (DCM), which is well-known for its strong nonlinear behavior. In particular, the DCM operation exhibits a nonlinear
duty-ratio-to-current transfer function, which significantly changes the converter dynamic; consequently, the current distortion
increases when the same CCM controller is used to control the DCM current [13]-[15]. In past few years, many researches focusing
on compensation methods for the DCM nonlinearity have been reported to solve this problem [14], [16]-[22]. However, a criticalpenalty of those methods is that the nonlinearity compensation for DCM is dependent on the inductance. In the residential PV
systems, the inductors with high tolerance are generally employed in the inverter; furthermore, the grid-tied inverter is required todeal with severe changes of the ambience, i.e. the inductance varies frequently. When actual inductances are different fromnominal values, the stability of such inductance-dependent control methods can no longer be guaranteed.
This paper proposes a current control method for the single-phase grid-tied inverter operating in both CCM and DCM, which is
independent from the inductance, in order to achieve the inductance reduction without worsening the current total harmonic
distortion (THD). The original idea in this paper is that the DCM nonlinearity compensation is constructed by utilizing a duty ratio
at a previous calculation period instead of using the inductance. Furthermore, the current mode is also determined without using theinductance by the comparison of the output duty ratios. Consequently, the proposed CCM/DCM current control can be applied
widely in the residential PV systems in order to minimize the LCL filters and further reduce the cost of the overall system. This
paper is organized as follows; in Section II, the zero-current clamping phenomenon is explained together with the problems of theconventional DCM nonlinearity compensation methods, then in section III, the CCM/DCM current control based on the
inductance-independent DCM nonlinearity compensation is proposed as the main part of this paper. Finally, the effectiveness ofthe proposed CCM/DCM current control is confirmed in section IV.

SW1

SW2

L/2

Lf /2

iout

ig

Vdc

Cf
L/2

SW2

vCf

vg

Lf /2

SW1

Fig. 1. Single-phase grid-tied inverter. An H-bridge inverter with a LCL filter is analyzed due to its simple configuration, which provides high fault-tolerant
reliability. The inverter is operated under bipolar modulation and the impedance of each grid line is designed equally in order to minimize a common-mode current.

As development steps of the proposed current control, first, the DCM current control method for unipolar inverters has been
proposed in [23]; next, this DCM current control method has been modified for bipolar inverters in [24]; finally, the current control
method for bipolar inverters operating in both CCM and DCM under different power factor has been proposed in [25]. This paper
is an updated version of [25] with additional improvements and substantial contributions such as: detailed analysis guidelines forthe DCM nonlinearity compensation which can be applied for numerous topologies are provided in section III; furthermore, newexperimental results of inverter dynamic under CCM and DCM operation, analysis on efficiency improvement with loss
breakdown, investigation on inductor cost reduction, and comparisons with the conventional current control method on
computation time are demonstrated in section IV.

II. ZERO-CURRENT CLAMPING PHENOMENON AND PROBLEMS OF CONVENTIONAL DISCONTINUOUS-CURRENT-MODENONLINEARITY COMPENSATION METHODSThis section presents the cause of the zero-current-crossing distortion in the vicinities of the zero-current crossing and thedrawbacks of the conventional DCM nonlinearity compensation methods.
Fig. 1 depicts the circuit configuration of the single-phase grid-tied inverter. Although many DC/AC converter topologies suchas, e.g. modular multilevel converters or flying capacitor multilevel converters [26]-[27], have been proposed for the grid-tied
inverter, a typical H-bridge inverter is analyzed due to its simple configuration, which provides high fault-tolerant reliability [28].
The LCL filter is used as an interface between the inverter and the grid in order to suppress the current harmonics of the inverter
output current iout. Compared to L filters or LC filters, the LCL filter can obtain effective switching harmonics attenuation withlower inductance requirements [29]. Meanwhile, in recent years, the application of wide bandgap semiconductor devices such as
SiC or GaN enables the inverter to push the switching frequency up to several hundreds of kHz, which further reduces theinductance of the LCL filter. However, the low-inductance LCL filter design significantly increases the zero-current-crossing
distortion, ipso facto, that cannot satisfy the grid current harmonic constraints [7]-[12].
Fig. 2 describes the zero-current clamping phenomenon. When a dead-time is not in use, the inverter output current flows
continuously over entire a switching period; hence, a sinusoidal current waveform is obtained. However, the zero-current clampingW/o dead time

With dead time

Fig. 2(b)Fig. 2(c)00Zerocurrentcrossing
distortion

Inverter output current
iout (10 A/div)
Time (10 ms/div)(a) Inverter output current w/o dead time and with dead timeInverter output current iout (3 A/div)

Time (5 ms/div)

With dead time00

Inverter output current
iout (3 A/div)

W/o dead time
1
0

SW2

Time (5 ms/div)

Dead time

1

SW1

SW1

Zero-current
clamping

SW20(b) Zoom-in current and switching signals w/o dead time(c) Zoom-in current and switching signals with dead time

Fig. 2. Zero-current clamping phenomenon and zero-current-crossing distortion. The dead-time causes the zero-current clamping phenomenon in the vicinities ofthe zero-current crossing, which changes the inverter operation from CCM to DCM. The low current loop gain in DCM worsens the current response and causes thezero-current-crossing distortion. Note that the long dead-time is employed for better illustration.

phenomenon occurs during the dead-time interval when the dead-time is applied in order to avoid an instantaneous turn-on of both
two switching devices in one leg. Due to this phenomenon, the inverter operation changes from CCM to DCM, which exhibits anonlinear duty-ratio-to-current transfer function. In particular, the open loop gain in DCM is much lower than that in CCM as
shown in Fig. 8 of [14]; consequently, the current distorts in the vicinities of the zero-current crossing due to the low current
response in DCM when the same CCM controller is operated under DCM. The length of the zero-current clamping interval
depends on the current ripple of the inverter output current iout, the dead-time-to-switching-period ratio, and the power level.
Therefore, the zero-current-crossing distortion is severe when the low-inductance design of the LCL filter is employed, i.e. thedesign of the high current ripple. The increase in the inverter-side inductance L and the decrease in the dead time shorten thezero-current clamping interval and might reduce the zero-current-crossing distortion; however, the filter volume becomes large andthe dead time is limited by the switching speed of the switching devices.
One of the approaches to deal with the zero-current-crossing distortion is to eliminate the zero-current clamping phenomenon. In[30], the turn-on and turn-off moment of the switching devices are adjusted when the current is in the vicinities of the zero-current
crossing in order to maintain the continuous flow of the current over entire a switching period. Hence, the current control
performance remains unchanged and the zero-current-crossing distortion does not occur. However, the turn-on and turn-offmoments are varied according to the current ripple, which is a function of the inverter-side inductance L, i.e. an
inductance-dependent method.
As other solutions, many current control methods for converters operating both in CCM and DCM have been proposed [14],[16]-[22]. A CCM/DCM control for practical applications has to deal with two main challenges; the DCM nonlinearity
compensation and the mode detection between CCM and DCM. In the adaptive dead-time compensation method and the turn-off
transition compensation method [16]-[17], the dead-time-induced error-voltage compensation is modified and fed forward into the
output of the controller in order to compensate for the DCM nonlinearity when the zero-current clamping phenomenon occurs.
Nevertheless, both methods exhibit the requirements which restrict the employment over a wide range of application. In particular,
adjustment parameters for the adaptive dead-time compensation must be properly tuned for each individual system [16].
Meanwhile, accurate device parameters, e.g. parasitic capacitances, are required for the turn-off transition compensation method[17]. Meanwhile, the conventional CCM grid-voltage feed forward is modified as shown in Fig. 10 of [14] or [22] to compensate
the DCM nonlinearity, whereas the mode is simply detected by comparing the output of the feed forward. One of the disadvantagesof this method is that, the feed forward for DCM is a function of the inductance, which still makes the control stability sensitive tothe circuit parameter.
In [18], the DCM nonlinearity compensation is avoided by the design of a wide bandwidth current controller, whereas the mode
detection is achieved by the zero-current detection. The wide bandwidth current controller can deal with the low open loop gain in
DCM; however, this design requires a high speed microcontroller per se and is undesirable in term of cost reduction. In addition,
the zero-current detection faces the challenge where the current does not remain at zero during the zero-current clamping interval.
Instead, the actual current oscillates in the net comprised of the inverter-side inductor and parasitic capacitors of the switching
devices [19]. Therefore, the zero-current detection must be tuned whenever any circuit components are changed. In [20]-[21], theDCM nonlinearity compensation is also avoided by the design of a DCM current feed forward control. The principle of the DCM
current feedforward control is to design the controller based on the reduced-order model or the full-order model [14]. An advantageof the feedforward control is the unrequired current sensor. However, a mismatch between the nominal values and the actual valuesof the circuit parameters still results in an instability of the control system. As the motivation for the achievement of the inductance
reduction without worsening the current THD, it is necessary to realize the DCM nonlinearity compensation and the mode
detection with a feature as inductance-independence.

III. INDUCTANCE-INDEPENDENT CURRENT CONTROL FOR CONTINUOUS CURRENT MODE AND DISCONTINUOUS CURRENT MODE
This section proposes the inductance-independent current control for the single-phase grid-tied inverter operating in both CCM
and DCM as the main part of this paper. First, the derivation of the DCM nonlinearity compensation, in which the use of theinductance is eliminated by the duty ratio at previous calculation period, is explained in section III.A. Next, the mechanism of theMode 1SW1Mode 2SW2Mode 3

SW2

SW1

SW1

vL

Vdc

SW2

vL

L

iout

Vdc

SW1

SW2

vg

SW1

L

iout
Vdc

SW2

Current peak
ipeak

vg

SW1

Average current
iavg

D1Tsw

0

vL

L

iout

vg

Inverter output
current iout

SW2

D2Tsw

D3Tsw

t

Tsw

Fig. 3. Current path and inverter output current waveform in DCM when the grid voltage is positive. The zero current interval D3Tsw occurring in DCM introduces
the nonlinearities into the transfer function [13]-[15].

mode detection between CCM and DCM without using the inductance is explained in section III.B.
A. Discontinuous-Current-Mode Nonlinearity Compensation by Duty Ratio at Previous Calculation Period
Fig. 3 depicts the current path and the inverter output current waveform in DCM when the grid voltage is positive. The filter
inductor Lf and the filter capacitor Cf are omitted due to the simplification. In order to derive the nonlinearity compensation for
DCM, the circuit model in DCM is required. First, let D1, D2 and D3 denote the duty ratios of the first, the second and thezero-current interval. Average small signal modeling technique is used to model the inverter for the current control loop design[13]. The inductor voltage in mode 1, mode 2 and mode 3 is given by (1)-(3), respectively,

vL1  Vdc  vg ........................................................ (1)vL2   Vdc  vg .................................................. (2)vL3  0 .................................................................. (3)where Vdc is the dc-link voltage and vg is the grid voltage. Then, the inductor voltage during a switching period is expressed by (4),







vL  D1vL1  D2vL2  D3vL3  D1 Vdc  vg  D2 Vdc  vg

.............................................................................. (4)The average current and the current peak of the inverter output current are given by (5)-(6), respectively,i peak D1  D2  ............................................. (5)2
Vdc  vg
i peak 
D1Tsw ............................................. (6)L
where Tsw is the switching period. Substituting (6) into (5) and solving the equation for the duty ratio D2, then the duty ratio D2 isiavg 

expressed by (7),D2 

2 Liavg
D1Tsw (Vdc  vg )

 D1 ..................................... (7)

vg

1
D1
[0~1]

VL

Vdc

2

1
sL

iavg

Nonlinear factor
Vdc + vg
D3
iavg
0.5ipeak(Vdc - vg)Tsw
2L

0.5ipeak

Do not exist
in CCM
because1
iavg equals to
0.5ipeakiavg

Fig. 4. Circuit model of inverter operating in DCM. The current control loop gain in DCM depends on the average current, i.e. the nonlinearities occurring in the
duty-ratio-to-current transfer function and the grid-voltage-to-current transfer function.

Substituting (7) into (4) in order to remove the duty ratio D2, and representing (4) as a function of the duty ratio D1, (8) is obtained,L
2 Liavg
 vL  Vdc  2 D1  1  vg  Vdc  vg 1 
dt
Vdc  vg D1Tsw 



diavg









.............................................................................. (8)Then, the circuit model in DCM is established based on (8) [13].
Fig. 4 illustrates the circuit model of the inverter operating in DCM. The dash line part does not exist when the inverter operates
in CCM because the average current iavg equals to the half current peak ipeak/2; in other words, the CCM operation makes thezero-current interval D3Tsw shown in Fig. 3 disappear. However, the zero-current interval D3Tsw induces the nonlinearity into thetransfer functions when the inverter operates in DCM, which worsens the current response in DCM when the same controller isapplied for both CCM and DCM [13]-[15]. Therefore, the output of the controller is necessary to be compensated when the inverter
operates in DCM. The derivation of the compensation for the DCM nonlinearity is explained as follows. First, the circuit model inFig. 4 is linearized at steady-state points. In particular, the dc-link voltage, the grid voltage, the average current and the duty ratio
when the inverter operates in the steady-state points can be expressed by (9)-(12), respectively,

Vdc  Vdc _ s  vdc .................................................. (9)vg  vg _ s  vg .................................................. (10)iavg  iavg _ s  iavg .............................................. (11)D1  D1_ s  D1 .................................................. (12)where Vdc_s, vg_s, iavg_s and D1_s are the dc-link voltage, the grid voltage, the average current and the duty ratio at the steady-state
points, whereas Vdc_s, vg_s, iavg_s and D1_s are the small signals of the dc-link voltage, the grid voltage, the average current andthe duty ratio, respectively. The fluctuation of the dc-link voltage is considered to be small; consequently, the small signal of the
dc-link voltage, i.e. the dc-link voltage dynamic, Vdc_s is negligible. The circuit model in Fig. 4 is linearized at the steady-state
points by substituting (9)-(12) into (8) [13].
Fig. 5 depicts the linearized circuit model of the inverter operating in DCM. In order to simplify the coefficients iavg_s in thevg
2D1_s2TswVdc_s + 2Liavg_s
D1_sTsw(Vdc_s - vg_s)
D1

1
sL

4Vdc_siavg

2L(Vdc_s + vg_s)
D1_sTsw(Vdc_s - vg_s)
Fig. 5. Linearized circuit model of inverter operating in DCM. The current control of DCM obtains the same dynamic as in CCM by compensating the DCM
nonlinearity at the output of the controller.

vg

Duty-ratio-dependent factors(do not exist in CCM)

4Vdc_s2D1_s(Vdc_s – vg_s)(Vdc_s + vg_s)
D1

4Vdc_s

1
sL

iavg

2L(Vdc_s + vg_s)
D1_sTsw(Vdc_s - vg_s)
Fig. 6. Simplified and linearized circuit model. The value of the duty ratio D1_s at steady-state points is required in order to compensate for the duty-ratio-dependent
factors occurring when the inverter operates in DCM.

linearized circuit model, the relationship between the coefficients iavg_s and the duty ratio D1_s at the steady-state points are derived
by substituting the differential of the inductor average current diavg/dt in (8) as zero [13]-[14],iavg _ s 

D1_2 sTswVdc _ s Vdc _ s  vg _ sL Vdc _ s  vg _ s...................... (13)Then, (13) is substituted into Fig. 5 in order to express all the coefficients as functions of the duty ratio D1_s.
Fig. 6 shows the simplified and linearized circuit model. Two duty-ratio-dependent factors occur in the duty-ratio-to-current
transfer function and the grid-voltage-to-current transfer function when the inverter operates in DCM. If theseduty-ratio-dependent factors are compensated at the output of the controller, the same CCM current dynamic can be obtained when
the inverter operates in DCM; therefore, the value of the duty ratio D1_s at the steady-state points is necessary. In the conventional
DCM nonlinearity compensation method [14], the value of D1_s is estimated based on (14), which is derived from (13),

D1_ s 
V

 .......................... (14)v Liavg _ s Vdc _ s  vg _ s
TswVdc _ s

dc _ sg_swhere iavg_s, Vdc_s, and vg_s are extracted from the detection values of the average current, the dc-link voltage and the grid voltage. It
is obvious that (14) is a function of the inductance L; consequently, the conventional DCM nonlinearity compensation method is

vg
z-1
z
(i) Duty-ratio-dependent factor in
grid-voltage-to-current transfer function
2Vdc_s2D1_s2(Vdc_s + vg_s)2
D1

2Vdc_sD1_s(Vdc_s - vg_s)
Vdc_s + vg_s

z-1
z

Tsw
L(z-1)VL

Δiavg(ii) Duty-ratio-dependent factor in duty-to-current transfer function

Fig. 7. Discretized circuit model of inverter operating in DCM. The original idea of the DCM nonlinearity compensation is to estimate the duty ratio at thesteady-state points by the duty ratio at the previous calculation. Consequently, the inductance is not required in the DCM nonlinearity compensation.

(ii) Compensation for duty-ratio-dependent
factor in duty-to-current transfer function

Conventional
CCM controller
iavg*

Controller

Nonlinearity compensation calculated by equation (14)iavg

(Vdc + vg)
TswVdc(Vdc - vg)

L

iavg

*

Controller
iavg

D1_s
D1

Conventional CCM controller(a) Conventional DCM nonlinearity compensation in [14]VL*aVdc + vg
2Vdc(Vdc - vg)
b
2

z-1
z

D1

D1[k-1]

2Vdc(Vdc + vg)2
vg

a/b

x2

z-1

D1
(i) Compensation for duty-ratio-dependent factor in
grid-voltage-to-current transfer function(b) Proposed DCM nonlinearity compensation

Fig. 8. Conventional and proposed DCM nonlinearity compensation. The main difference between the conventional and proposed method is that, the DCM
nonlinearity compensation is constructed by utilizing the duty ratio at the previous calculation period; hence, this makes the control system inductance-independent.

inductance-dependent. The characteristic of circuit-parameter-dependency prevents the conventional method from the applicationof the residential PV systems, where the accurate value of L is difficult to obtain as mentioned in section II. On the other hand, theestimation of D1_s by the duty ratio at the previous calculation period is proposed to avoid the dependency of L as the originality ofthis paper. Hence, the circuit model of the inverter operating in DCM is necessary to be analyzed in the discrete model of Fig. 6.
Fig. 7 depicts the discretized circuit model of the inverter operating in DCM. The duty-ratio-dependent factors in Fig. 7 arenecessary to be set as 1 when the circuit operates in DCM in order to compensate the DCM nonlinearity at the output of thecontroller designed in CCM. In particular, the steady-state values of Vdc_s and vg_s are obtained by the detection values of the dc-link
voltage and the grid voltage, whereas the steady-state duty ratio D1_s are estimated by the duty ratio D1[k-1] at the previous
calculation period.
Fig. 8 illustrates the conventional DCM nonlinearity compensation in Fig. 10 of [14], and the proposed DCM nonlinearity
compensation. The same principle of two methods is the estimation of D1_s in order to compensate for the DCM nonlinearity. In theconventional method, D1_s is estimated by using the current command iavg* and (14); consequently, this leads to the
inductance-dependence. On the other hand, in the proposed method, D1_s is estimated by using the duty ratio D1[k-1] at the previous

Mode 1SW1Mode 2SW2

SW1Mode 3

SW2

SW1

vL

Vdc

SW2

vL

L

iout

vg

Vdc

vg

SW2

vL

L

iout

SW1

Inverter output
current iout

SW2

SW1

D1Tsw

iout
Vdc

SW2
D2Tsw

L
vg

SW1

D3Tsw

Tsw

0

Current peak ipeak

Average current
iavg

Fig. 9. Current path and inverter output current waveform in DCM when the grid voltage is negative. The same analysis procedure when the grid voltage is positive
can be applied with the negative grid voltage.

calculation period, which provides the control system inductance-independence and the same CCM current response when the
inverter operates in DCM [15]. Note that the above analysis is conducted when the grid voltage is positive; however, the same
analysis procedure can be applied when the grid voltage is negative. For the sake of brevity, the derivation for the circuit model in
DCM for the negative grid voltage is simplified as follows.
Fig. 9 depicts the current path and the inverter output current waveform in DCM when the grid voltage is negative. The same
circuit model of Fig. 4 is obtained even when the grid voltage is negative; therefore, the similar DCM nonlinearity compensation isapplied with the negative grid voltage. However, the applying order of mode 1 and mode 2 in Fig. 9 is flipped compared to that inFig. 3, which implies that the output of the controller system D1 in Fig. 8(b) has to be applied to the switch SW 1 when the gridvoltage is positive, and inversely, D1 has to be applied to the switch SW2 when the grid voltage is negative. This switching signal
generation is the main difference between the DCM operation and the CCM operation, where the switching signal of SW 2 in CCM
is the inverse switching signal of SW1. In the DCM operation, the inverse switching signal of each switch does not equal to theswitching signal of the other switch due to the occurrence of the zero-current interval D3Tsw. Meanwhile, the polarity of vg in Fig.
8(b), which should always be positive, becomes negative when the grid voltage is negative because vg is extracted from thedetection value of the grid voltage. Therefore, the simple solution is to modify vg in Fig. 8(b) into the multiplication of vg and thepolarity of iavg*.
Fig. 10 illustrates the proposed DCM current control for the grid-tied inverter and the variation of the duty ratio in DCM.
Compared to Fig. 8(b), the multiplication of vg and the polarity of iavg* is used in the compensation of the duty-ratio-dependent
factors in order to obtain the DCM current dynamic as same as CCM regardless of the polarity of the grid voltage. The
determination in which the output of the control system should be applied to SW1 or SW2, can be carried out by the comparison of

(ii) Compensation for duty-ratio-dependent
factor in duty-to-current transfer functiona
D1
VL*
Vdc + vgsign(iavg*) ab
Controller
2Vdc[Vdc - vgsign(iavg*)]b
D1[k-1]
2Vdc2
|x|
* 2
[V + v sign(i )]Conventional
CCM controller
iavg*
iavg

dc

vg

z-1
z

g

avg

x2

(i) Compensation for duty-ratio-dependent factor in
grid-voltage-to-current transfer function

z-1

-1

DSW1

SW1

DSW2

SW2

0

1

Variation of duty ratio in DCM
iout
iavg

DutySW2

DutySW1(D1)

SW1:OFF

SW2:OFF01
0-1

SW1:OFF

Fig. 10. Proposed DCM current control system for single-phase grid-tied inverter and variation of duty ratio in DCM. The polarity of D1 is used to determine if D1
should be applied to SW1 or SW2 in order to avoid the interruption of the continuous change of D1.

the polarity of the grid voltage vg or the current command iavg*. However, this method might interrupt the continuous change of D1,
because the actual current phase iavg is lag compared to that of the current command iavg*. Instead, the polarity of D1 is used todetermine if D1 should be applied to SW1 or SW2 in order to avoid the interruption of the continuous change of D1. As mentioned
above, the switching signal generation in DCM differs from that in CCM because both the switches SW1 and SW2 must be turned
off during the zero-current interval D3Tsw, which cannot be realized by the use of the inverse switching signal as in CCM.
Therefore, the idea to operate the inverter under DCM is the alternate switching of SW 1 or SW2 dependently on the polarity of D1.
Meanwhile, another difference between the CCM operation and the DCM operation observed from the variation of the duty ratio isthat, the duty ratio of CCM only varies only around the value of 0.5, whereas the duty ratio in DCM decreases to zero when the
average current reaches zero. The reason of the difference in the duty ratio variation is that the duty-ratio-to-current transfer
function in CCM is linear, which implies the duty ratio does not relate to the average current but only the change of the average
current, whereas the duty-ratio-to-current transfer function in DCM is nonlinear, which means the duty ratio depends on the
average current. The proposed DCM current control system is employed when the inverter is operated entirely in DCM even at a
rated load. However, this design results in an extremely high current ripple, which significantly increases a conduction loss in theswitching devices and requires a larger heat sink [6], [30]. Therefore, a design of a moderate current ripple, in which the inverter
operates in both CCM and DCM, is preferred in order to minimize the LCL filter without increasing the inverter loss.
B. Current Mode Determination
Fig. 11 indicates the relationship among the CCM duty, the DCM duty and the current mode. The current mode detection
between CCM and DCM is necessary when the inverter is designed to operate in both CCM and DCM. One of the conventional
current mode detection method is the detection of the zero current in DCM [18]. However, the zero current detection faces many
challenges in practical applications, one of which is the current oscillation during the zero-current interval D3Tsw shown in Fig. 3
and Fig. 9. In particular, this current oscillation is caused by the energy oscillation between the inductor L and the parasitic
capacitance of the switches, which becomes more severe with a low inductance L and a high switching frequency [19]. As another

0.6

DCM
DutyDCM＜DutyCCM

Duty ratio

0.5

CCM
DutyDCM≧DutyCCM

Mode transition point

0.4

DutyDCM
DutyCCM

0.3
0.2

Inductor current value
at boundary between
CCM and DCM iBCM

0.1
0

0

0.5

1.0
1.5
Average Current [A]

2.0

2.5

Fig. 11. Relationship among CCM duty, DCM duty and current mode. When the circuit operates in DCM, the DCM duty becomes smaller than the CCM duty andvice versa. The current mode determination is realized independently from the inductor value by using this relationship of the duty ratios.

typical approach, the detection value of the average current iavg or the average current command iavg* is compared with the current
value iBCM at the boundary between CCM and DCM; if iavg is larger than iBCM, CCM is determined as the operation mode and viceversa [20]. However, the inductance is used in the calculation of iBCM which implies the current mode determination is
inductance-dependent. Consequently, when the actual inductor value is different from the nominal value, the current mode cannot
be accurately determined by the conventional method. On the other hand, the proposed current mode determination focuses on therelationship among the CCM duty DutyCCM, the DCM duty DutyDCM and the current mode. In particular, if DutyCCM is larger than
DutyDCM, DCM becomes the operation mode and vice versa. Note that DutyCCM is independent from the average current, whereas
DutyDCM changes with the variation of the average current (cf. Fig. 10 of section III.A). In general, DutyCCM is the output value ofthe controller, which implies the calculation for DutyCCM is independent from the inductance. If the proposed DCM nonlinearity
compensation in section III.A is employed, the calculation for DutyDCM also becomes inductance-independent. Consequently, if therelationship between DutyCCM and DutyDCM is used to determine the current mode, the inductance-independent current mode
determination is achieved. In other words, the proposed inductance-independent DCM nonlinearity compensation in section III.A
leads to the inductance-independent current mode determination.
Fig. 12 describes the conventional CCM current control system, the conventional CCM/DCM current control system, and the
proposed inductance-independent CCM/DCM current control system with the waveform of the current mode alternation. In theconventional CCM current control system, when a typical PI controller is employed, the grid voltage feedforward is required inorder to enhance the disturbance suppression. Although the inductance might be used in the design of the controller, theconventional CCM current control system is inductance-independent per se if the bandwidth of the controller is properly designed[31]. Note that the grid voltage feedforward can be eliminated if the proportional-resonant (PR) controller is applied [32]-[33].
Meanwhile, a typical two-level dead-time compensation is employed to compensate the dead-time-induced error voltage [34]-[35].
Nevertheless, the conventional CCM current control system cannot compensate for the DCM nonlinearity when the zero-current
phenomenon becomes noticeable as the current ripple increases. In the conventional CCM/DCM current control system, first, bothConventional CCM controller

Dead-time compensation

iavg*

0.5

C

DutyCCM [-1~1]

iavg

1
Vdc
vg

Dead-time generation
SW1*

sign(iavg )fswTd 1
NOT0
Grid voltage feedforward (unnecessary if a PR controller is used [32]-[33])SW2(a) Conventional CCM current control system

Conventional CCM controller
Duty
iavg*

C

SW1

iavg
L

DutyDCM_s [-1~1](Vdc + vg)
TswVdc(Vdc - vg)

sign(iavg*)
|x|

NOT

*

sign(iavg )fswTd
Dead-time-1
compensation

Steady-state DCM duty generation, cf. Fig. 8(a)SW21Dead-time
generation

|x|
vg

1
Vdc

0

0.5
DutyCCM_s [-1~1]

0.5sign(iavg*)
Steady-state CCM duty generation

Current mode determination(b) Conventional CCM/DCM current control system, cf. Fig. 10 of [14]Conventional CCM controller DCM duty generation (cf. Fig. 10 in section III.A)a
DutyDCM [-1~1] Duty
Vdc + vgsign(iavg*) abC
2[Vdc - vgsign(iavg*)]biavg
sign(iavg*)fswTd
2Vdc
|x|
|x|
NOT
2
Dead-time[Vdc + vgsign(iavg*)]-1
compensation
z-1
vg
x2
z-1
z
1
|x|
0

Current mode alternation

iavg*

vg

iavg

0A

SW2
Dead-time
generation
0

0.5
1
Vdc

iout

SW1

Duty

DutyCCM [-1~1]
0.5sign(iavg*)

CCM duty generation

Current mode
determination

DutyDCM

DutyCCM(c) Proposed inductance-independent CCM/DCM current control system with waveform of current mode alternation.
Fig. 12. Conventional CCM current control system, conventional CCM/DCM current control system, and proposed inductance-independent CCM/DCM current
control system with waveform of current mode alternation. The constant-gain conventional CCM current control system cannot compensate for the DCM
nonlinearity, whereas the conventional CCM/DCM current control system is dependent on the inductance. On the other hand, the proposed CCM/DCM current
control system compensates for the DCM nonlinearity and determines the current mode independently from the inductance.

the steady-state DCM duty DutyDCM_s and the steady-state CCM duty DutyCCM_s are generated. Then, these two duty ratios arecompared to each other; the smaller duty ratio is feed forward to the output of the controller to compensate for the grid voltage
disturbance in CCM or the nonlinearity in DCM. It is obvious that the conventional CCM/DCM current control system is

TABLE I
EXPERIMENTAL PARAMETERS.
Circuit Parameter
Vdc
Dc-link voltage
350 Vvg
Grid voltage
200 Vrms
Pn
Nominal power
4 kW
Switching device (SiC MOSFET) SCT303AL (ROHM)
Core material and Litz wire
Ferrite N87, 504/f0.1
fg
Grid frequency
50 Hz
Cdc
Dc-link capacitance2720 mF
Cf
Filter capacitance
4 mF
Lf
Filter inductance
20 mH
fsw
Switching frequency 100 kHz
Current Controller Parameter
fsamp
Sampling frequency
25 kHzz
Damping factor
1.2
fc
1 kHz
Cutoff frequency
Td
500 nsDead time
Gate drive unit

Heat sink and switching devices
h = 60 mm
Dc-link
capacitor

Dc-link
snubber
capacitorl = 260 mm

w = 80 mm

Fig. 13. 4-kW 100-kHz prototype of single-phase grid-tied inverter. SiC switching devices are chosen to operate the inverter at high switching frequency of 100
kHz, whereas two switching devices are connected in parallel to reduce the conduction loss in each device and enable the employment of natural cooling.
Meanwhile, four electrolytic capacitors of 680-mF are connected in parallel at the dc link to absorb the single-phase power fluctuation and maintain a low dc-link
voltage ripple.

dependent on L. In the proposed CCM/DCM current control system, first, both the DCM duty DutyDCM and the CCM duty DutyCCM
are generated. Then, the absolute value of these two duty ratios are compared to each other; the smaller duty ratio is used togenerate the switching signal for the switches. Note that the absolute operators are used with the consideration of the negative gridvoltage as shown in the waveform of the current mode alternation in Fig. 12(c). The original idea of the inverter control for theoperation in both DCM and CCM is that as first step, the duty ratio at the previous calculation period is used to compensate theDCM nonlinearity regardless of L, then two outputs of the inductance-independently generated duty ratios are compared to eachother in order to determine the current mode. Consequently, the CCM/DCM current control system can perform the current control
independently from L.

IV. LABORATORY SETUP
Table I depicts the experimental parameters, whereas Fig. 13 shows the 4-kW 100-kHz prototype of the single-phase grid-tied

%ZL = 1.8% (L = 560 mF)
VolL = 844 cm3(1.0 p.u.)%ZL = 0.5% (L = 160 mF)
VolL = 413 cm3(0.49 p.u.)
w = 46 mm

h = 69 mm

h = 66 mm

w = 90 mm

l = 71 mm(a) First design with inverter-side inductor impedance of 1.8%

l = 65 mm(b) Second design with inverter-side inductor impedance of 0.5%

Fig. 14. Prototypes of inverter-side inductors under different conditions of inductor impedance. Note that only one inductor in one line indicated by L/2 in Fig. 1 isshown, whereas the impedance, the inductance and the inductor volume (including bobbins) are calculated from two inductors in two lines. In particular, theinductor volume is reduced by 51% due to the reduction of the inverter-side inductor impedance %ZL from 1.8% to 0.5%.

inverter. With a relatively mature development, SiC switching devices are chosen to operate the inverter at the high switchingfrequency of 100 kHz; consequently, the LCL filter can be minimized due to a design of a high cutoff frequency. A natural coolingmethod is preferred for the residential PV systems in order to eliminate a periodic maintenance of cooling fans. Electrolytic
capacitor with high ratio between the capacitance and volume is chosen to absorb the single-phase power fluctuation as a passive
energy buffer method [27]. These capacitors are designed with a consideration of a capacitor current ripple to avoid a temperaturerise due to an equivalent series resistance of capacitors, which is the main cause of the lifetime decrease of the electrolytic capacitor[36]. Note that the operation frequency of the microcontroller is synchronized with the sampling frequency of 25 kHz despite of thehigh switching frequency of 100 kHz; this enables the use of general-purpose microcontrollers. Furthermore, PI controller ischosen to use in the residential PV system due to its mature development and research. The dead time design is conducted inconsideration of the following factors: the maximum drain current of 60 A, the gate resistor of 3 , the maximum ambient
temperature of 50oC, and the high-volume production.
Fig. 14 depicts the prototypes of the inverter-side inductors L under different conditions of the inductor impedance %ZL. Notethat in the LCL filter design, the inductor impedance, which is normalized by the inverter total impedance, is generally used tocompare the inductance. Ferrite is chosen to be the core material in order to minimize the core loss at the switching frequency of
100 kHz, whereas Litz wire is used to minimize the winding loss coming from the proximity effect and the skin effect [37]. The
inverter-side inductor impedance is minimized with the consideration of the increase in the conduction loss of the switching
devices due to the high inductor current ripple [30]. It can be observed that the inductor volume (including bobbins) is reduced by
51% when the inverter-side inductor impedance %ZL is reduced from 1.8% to 0.5%. Note that the minimization of the inverter-side
inductor impedance is also restricted due to the practical limits of the sampling frequency, the current sensor measurement, and thecurrent control bandwidth. For instance, the grid-tied inverter is required to meet the fault-ride-through (FRT) requirements of thegrid code [38]; one of the regulations is that the current overshoot rate below 150% of the maximum current at rated load must be
maintained even when the grid faults occur, e.g. the short-circuit of the grid. In the practical application, there is delay time in thecurrent detection due to the current sensor or the sampling frequency. Consequently, the smaller the inductance is reduced, themore difficult to achieve the current overshoot rate below 150% of the maximum current at the rated load it becomes during thegrid faults.
A. Operation Verification
Fig. 15 describes the inverter operation waveforms with the conventional CCM current control at a rated load of 4 kW and at alight load of 2 kW under two conditions of %ZL. Fig. 15(a)-(b) shows the operation waveforms at the rated load of 4 kW, whereas
Fig. 15(c)-(d) shows the operation waveforms at the light load of 2 kW. Fig. 15(a), (c) shows the operation waveforms with %ZL of
1.8%, whereas Fig. 15(b), (d) shows the operation waveforms with %ZL of 0.5%. The grid current THD (up to 40th order of theharmonic component) is measured by a YOKOGAWA WT1800 power meter. As mentioned in section II, the length of thezero-current clamping interval depends on the current ripple of the inverter output current iout, the dead-time-to-switching-period
ratio, and the power level. Note that the low-inductance design leads to the high switching current ripple; therefore, when %ZL is
reduced from 1.8% to 0.5%, the grid current THD at the rated load of 4 kW increases from 2.3% to 8.7% as shown in Fig. 15(a)-(b).
Similarly, comparing Fig. 15(a)-(b) with Fig. 15(c)-(d), when the power level decreases from 4 kW to 2 kW, the grid current THD
increases from 2.3% and 8.7% to 3.9% and 12.4%, respectively. According to standards such as IEEE-1547 [1], the grid current
THD at the rated load must be lower than 5%; hence, the inductor impedance design of 0.5% with the conventional CCM current
control system, of which the grid current THD at the rated load is 8.7%, does not satisfy the harmonic constraint. Consequently, it
is confirmed by experimental results that the inductance reduction with the conventional CCM current control, of which the aim toachieve the small volume and low cost of the inductors, is limited due to the zero-current distortion.
Fig. 16 describes the inverter operation waveforms with the proposed CCM/DCM current control at the rated load of 4 kW andat the light load of 2 kW under two conditions of %ZL. Fig. 16(a)-(b) shows the operation waveforms at the rated load of 4 kW,
whereas Fig. 16(c)-(d) shows the operation waveforms at the light load of 2 kW. Fig. 16(a), (c) shows the operation waveforms
with %ZL of 1.8%, whereas Fig. 16(b), (d) shows the operation waveforms with %ZL of 0.5%. It can be observed clearly from Fig.
16(b), (d) that the inverter is intentionally operated under DCM in the vicinities of the zero-current crossing. Due to the DCM
nonlinearity compensation, the same current dynamic as CCM is achieved during the DCM interval; consequently, the zero-current
distortion is eliminated. In particular, the proposed CCM/DCM current control reduces the grid current THD at the rated load from
8.7% to 2.1% compared to that of the conventional CCM current control with %ZL of 0.5%. Therefore, the proposed CCM/DCM
current control enables the minimization of the inverter-side inductor impedance without violating the harmonic constraintAc-coupling dc-link voltage Vdc_ac_coup. (10 V/div)

Ac-coupling dc-link voltage Vdc_ac_coup. (10 V/div)

Grid voltage
vg (500 V/div)

Time(10 ms/div)

Grid voltage
vg (500 V/div)

Time(10 ms/div)

Grid currentig (40 A/div)

THDig=2.3%

Grid currentig (40 A/div)

THDig=8.7%

Inverter
output current
iout (40 A/div)

Zero-current
distortion

Zero-current
distortion

Inverter
output current
iout (40 A/div)(a) Conventional CCM control, %ZL=1.8%, rated load of 4 kW(b) Conventional CCM control, %ZL=0.5%, rated load of 4 kW

Ac-coupling dc-link voltage Vdc_ac_coup. (10 V/div)

Ac-coupling dc-link voltage Vdc_ac_coup. (10 V/div)

Grid voltage
vg (500 V/div)

Time(10 ms/div)

Grid voltage
vg (500 V/div)

Time(10 ms/div)

Grid currentig (20 A/div)

THDig=3.9%

Grid currentig (20 A/div)

THDig=12.4%

Inverter
output current
iout (20 A/div)

Zero-current
distortion(c) Conventional CCM control, %ZL=1.8%, light load of 2 kW

Inverter
output current
iout (20 A/div)

Zero-current
distortion(d) Conventional CCM control, %ZL=0.5%, light load of 2 kW

Fig. 15. Operation waveforms of conventional CCM control at rated load of 4 kW and at light load of 2 kW under two conditions of %ZL. The low-inductance design
results in the high current ripple, which increases the zero-current distortion with the conventional CCM control. Consequently, the grid current THD of 8.7% at the
rated load with %ZL of 0.5% does not satisfy the harmonic constraint regulated by standards such as IEEE-1547 [1].

regulated by standards such as IEEE-1547 [1].
Fig. 17 depicts the comparison of the grid current THD and the power factor characteristics of the conventional CCM current
control and the proposed CCM/DCM current control. Fig. 17(a)-(b) shows the grid current THD with %ZL of 1.8% and 0.5%,
whereas Fig. 17(c)-(d) shows the power factor with %ZL of 1.8% and 0.5%, respectively. In Fig. 17(a)-(b), the proposed

Ac-coupling dc-link voltage Vdc_ac_coup. (10 V/div)

Ac-coupling dc-link voltage Vdc_ac_coup. (10 V/div)

Grid voltage
vg (500 V/div)

Time(10 ms/div)

Grid voltage
vg (500 V/div)

Time(10 ms/div)

Grid currentig (40 A/div)

THDig=0.6%

Grid currentig (40 A/div)

THDig=2.1%

Inverter
output current
iout (40 A/div)

DCM
interval

Inverter
output current
iout (40 A/div)

DCM
interval

DCM CCM DCM(a) Proposed CCM/DCM control, %ZL=1.8%, rated load of 4 kW(b) Proposed CCM/DCM control, %ZL=0.5%, rated load of 4 kW

Ac-coupling dc-link voltage Vdc_ac_coup. (10 V/div)

Ac-coupling dc-link voltage Vdc_ac_coup. (10 V/div)

Grid voltage
vg (500 V/div)

Time(10 ms/div)

Grid voltage
vg (500 V/div)

Time(10 ms/div)

Grid currentig (40 A/div)

THDig=1.2%

Grid currentig (40 A/div)

THDig=3.6%

Inverter
output current
iout (40 A/div)

DCM
interval

Inverter
output current
iout (40 A/div)

DCM
interval

DCM(c) Proposed CCM/DCM control, %ZL=1.8%, light load of 2 kW

CCM

DCM

(d) Proposed CCM/DCM control, %ZL=0.5%, light load of 2 kW

Fig. 16. Operation waveforms of proposed CCM/DCM control at rated load of 4 kW and at light load of 2 kW under two conditions of %ZL. Even with %ZL of 0.5%,
the proposed CCM/DCM current control can still maintain the grid current THD at the rated load below 5%, which satisfies the harmonic constraint regulated bystandards such as IEEE-1547 [1].

CCM/DCM current control reduces the current distortion at the rated load by 73.9% and 75.9% with %ZL of 1.8% and 0.5%
compared to those of the conventional CCM current control, respectively. Moreover, the grid current THD over entire load range
from 0.1 p.u. to 1.0 p.u. is reduced with the proposed CCM/DCM current control. Consequently, the power factors of the proposed
CCM/DCM current control over entire load range from 0.1 p.u. to 1.0 p.u. with %ZL of 1.8% and 0.5% are improved compared toGrid current distortion THDig [%]50

1 p.u. equals to 4 kW.
fsw = 100 kHz, Td = 500 ns%ZL = 1.8%98Conventional CCM
current control

7

Current THD constraint in IEEE-1547(Requirement: THD<5%)6
5

Proposed CCM/DCM
current control
Current distortion
reduced by 73.9%

4
3
2
1
0

1 p.u. equals to 4 kW.
fsw = 100 kHz, Td = 500 ns%ZL = 0.5%45Grid current distortion THDig [%]10

40

Conventional CCM
current control

3530

Proposed CCM/DCM
current control
Current THD constraint in IEEE-1547(Requirement: THD<5%)

25
20
15

Current distortion
reduced by 75.9%

10
5

0

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Output power Pout [p.u.](a) Grid current THD characteristic of %ZL=1.8%0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Output power Pout [p.u.](b) Grid current THD characteristic of %ZL=0.5%
1

1
0.995
0.99

0.95

Conventional CCM current control

0.98

Proposed CCM/DCM current control

0.975
1 p.u. equals to 4 kW.
fsw = 100 kHz, Td = 500 ns%ZL = 1.8%

0.97
0.965

Power factor improved by 2.5%

0.96

Power factor

Power factor

0.985

Conventional CCM current control

0.9
Proposed CCM/DCM current control

0.85
1 p.u. equals to 4 kW.
fsw = 100 kHz, Td = 500 ns%ZL = 0.5%

0.8Power factor improved by 27.1%

0.75

0.955
0.7

0.95
0

0.1

0.2

0.3 0.4 0.5 0.6 0.7 0.8
Output power Pout [p.u.](c) Power factor characteristic of %ZL=1.8%

0.9 1.0

0

0.1

0.2

0.3 0.4 0.5 0.6 0.7 0.8
Output power Pout [p.u.]

0.9

1.0

(d) Power factor characteristic of %ZL=0.5%

Fig. 17. Grid current THD and power factor characteristics of conventional CCM current control and proposed CCM/DCM current control. The proposed
CCM/DCM current control reduces the current distortion at the rated load by 73.9% and 75.9% with %ZL of 1.8% and 0.5% compared to those of the conventional
CCM current control, respectively. Furthermore, the power factors of the proposed CCM/DCM current control over entire load range from 0.1 p.u. to 1.0 p.u.
with %ZL of 1.8% and 0.5% are also improved compared to those of the conventional CCM current control.

those of the conventional CCM current control as shown in Fig. 17(c)-(d), respectively. In particular, the power factor at the lightload of 0.1 p.u. with %ZL of 0.5% is improved by 27.1% when the proposed CCM/DCM current control is applied.
Fig. 18 describes the inverter operation waveforms with the proposed CCM/DCM current control under low power factor with
%ZL of 0.5%. During normal operation, the grid-tied inverter is required to operate at unity power factor with maximum power
point tracking in order to extract as much energy as possible from the PV panels [32]. However, when the grid variations occur, i.e.
frequency instability or grid voltage sag, the grid-tied inverter is also necessary to operate under low power factor [33]. As shownin Fig. 18, the proposed CCM/DCM current control still maintains a low grid current THD under the low power factor.

0V

Grid voltage
vg (500 V/div)

Grid currentig (40 A/div)

0V

THDig=2.6%

0A

Grid currentig (40 A/div)

Inverter
output current
iout (40 A/div)

0A

0A(a) Inverter operation with low power factor of 0.9 (Lagging)

Grid voltage
vg (500 V/div)

Grid currentig (40 A/div)(b) Inverter operation with low power factor of 0.8 (Lagging)

0V

THDig=2.8%

Grid voltage
vg (500 V/div)

Grid currentig (40 A/div)

THDig=3.0%

0A

0A

0A

THDig=2.6%

0A

Inverter
output current
iout (40 A/div)

0V

Grid voltage
vg (500 V/div)

Inverter
output current
iout (40 A/div)(c) Inverter operation with low power factor of 0.9 (Leading)Inverter
output current
iout (40 A/div)
0A(d) Inverter operation with low power factor of 0.8 (Leading)Fig. 18. Proposed CCM/DCM current control operation under low power factor with %ZL of 0.5%. When the grid variations occur, i.e. frequency instability or gridvoltage sag, the grid-tied inverter is necessary to operate under a low power factor in order to avoid more serious events, e.g. power outage or voltage flickering.

Fig. 19 describes the inverter operation waveforms with the proposed CCM/DCM current control under step load change with
%ZL of 0.5%. Fig. 19 (a)-(b) shows the current response with the step load change from 60% to 100% and vice versa, whereas Fig.
19 (c)-(d) depicts the current response with the step load change from 10% to 50% and vice versa, respectively. Note that the step
load change in Fig. 19 (a)-(b) occurs in the vicinities of the zero-current crossing, i.e. the DCM interval, whereas the step loadchange in Fig. 19 (c)-(d) occurs at the current peak, i.e. the CCM interval. It is observed that the transient waveform has low
overshoot and fast convergence regardless of the moment of the step load change occurrence.
B. Comparison of Efficiency, Inductor Material Cost and Computation Time
Fig. 20 depicts the efficiencies and the loss distribution with the proposed CCM/DCM current control with %ZL of 1.8% and0.5%. The efficiencies are measured by a YOKOGAWA WT1800 power meter, whereas the semiconductor device losses and theinductor losses are obtained from simulators, i.e. PLECS and GeckoMAGNETICS. In Fig. 20(a), the maximum efficiency of
97.9% is achieved with %ZL of 0.5% from the load range of 0.6 p.u. to 0.9 p.u., whereas the efficiency at the rated load of 4 kW isGrid current ig (20 A/div)

Grid current ig (20 A/div)

Occurrence of step load change

Occurrence of step load change
Inverter output current iout (20 A/div)

Inverter output current iout (20 A/div)

Time (20 ms/div)

Time (20 ms/div)(a) Current response with step-up load change from 60% to 100%(b) Current response with step-down load change from 100% to 60%

Grid current ig (20 A/div)

Grid current ig (20 A/div)

Occurrence of step load change

Occurrence of step load change
Inverter output current iout (20 A/div)

Inverter output current iout (20 A/div)

Time (20 ms/div)

Time (20 ms/div)(c) Current response with step-up load change from 10% to 50%(d) Current response with step-down load change from 50% to 10%

Fig. 19. Proposed CCM/DCM current control operation under step load change with %ZL of 0.5%. The transient waveform has low overshoot and fast convergencewhen the step load change occurs either in the vicinities of the zero-current crossing, i.e. the DCM interval, or at the current peak, i.e. the CCM interval.

100
90

98.0

%ZL = 0.5%

80

0.4
16.8

97.5
97.0
%ZL = 1.8%

96.5
96.0

Loss reduction of 35%

95.5
95.0

1 p.u. equals to 4 kW.
fsw = 100 kHz, Vdc = 350 V, vg = 200 Vrms
SiC devices: SCT303AL
Asynchronous switching

94.5
94.0

0

0.1

0.2

0.3 0.4 0.5 0.6 0.7
Output power Pout [p.u.](a) Efficiency characteristics

70
Converter loss [W]

Conversion efficiency h [%]Maximum efficiency of 97.9%

0.8

0.9

1.0

Loss reduction of 8.3%

2.4
8.7

1 p.u. equals to 4 kW.
SiC devices: SCT3030AL
Core material: Ferrite N87
Litz wire: 7/3/24 f0.1mm

Semiconductor device losses

60
50 47.7

Conduction loss Switching loss
46.1
Inductor losses

40
30

Winding loss

Core loss

0.1 Loss reduction of 29.5%
2.0
0.3
26.8
26.7
1.0
16.2
10
11.1
1.3
1.4
0
%ZL=1.8%%ZL=0.5%%ZL=1.8%%ZL=0.5%
Load: 1.0 p.u. Load: 1.0 p.u. Load: 0.1 p.u. Load: 0.1 p.u.

20(b) Loss distribution

Fig. 20. Efficiency and loss distribution with proposed CCM/DCM current control with %ZL of 1.8% and 0.5%. The maximum efficiency of 97.9% is achieved overa wide load range from 0.6 p.u. to 0.9 p.u.. The switching loss and conduction loss of SiC devices occupies for a majority of the converter loss. Therefore, theefficiency might be further improved by the application of GaN devices to reduce the switching loss and the employment of the synchronous switching to reduce theconduction loss.

97.8%. The efficiency with %ZL of 0.5% is higher than that with %ZL of 1.8% over entire load range; in specific, the loss at the lightload of 0.1 p.u. with %ZL of 0.5% is reduced by 35% compared to that with %ZL of 1.8%. This efficiency improvement especiallybenefits the PV application with a frequent variation between the light load operation and the heavy load operation. In Fig. 20(b),the converter losses with %ZL of 1.8% and 0.5% at the rated load of 1.0 p.u. and the light load of 0.1 p.u. are demonstrated. At the
rated load of 1.0 p.u., compared to %ZL of 1.8%, the conduction loss and the core loss with %ZL of 0.5% increase, whereas theswitching loss and the winding loss with %ZL of 0.5% decrease. The increase in the conduction loss and the core loss occurs due tothe increase of the current ripple when %ZL is reduced from 1.8% to 0.5%. On the other hand, the reduction of %ZL requires lesswinding wire in the inductor; consequently, the winding loss of the inductor decreases. Regarding to the switching loss, there are
two main factors causing the decrease in the switching loss when %ZL is reduced from 1.8% to 0.5%: the increase in the current
ripple, and the DCM operation in the vicinities of the zero-current crossing. First, compared to the low current ripple, the highcurrent ripple makes the semiconductor devices turn off at higher current and turn on at lower current, which results in the increasein the turn-off switching loss and the decrease in the turn-on switching loss. In SiC-MOSFET, the turn-on switching loss areusually higher than the turn-off switching loss due to the occurrence of the diode reverse recovery and the parasitic capacitancedischarge at the turn on. Hence, the increase in the current ripple benefits the reduction in the switching loss. Second, during theDCM operation, the turn-on loss is significantly reduced due to zero-current turn-on. Hence, the increase in the current ripple
results in longer DCM intervals around the zero-current crossing points, which helps to reduce the switching loss. This switchingloss reduction effect with the DCM operation is clearly observed at the light load of 0.1 p.u., where the DCM interval becomes
longer. In particular, at the light load of 0.1 p.u., compared to %ZL of 1.8% (low current ripple, short DCM intervals), the switchingloss of %ZL of 0.5% (high current ripple, long DCM intervals) is reduced from 16.2 W to 11.1 W. Furthermore, it can be concluded
from Fig. 20(b) that the switching loss and conduction loss of SiC devices occupies for a majority of the converter loss. Therefore,
the efficiency might be further improved by the application of GaN devices to reduce the switching loss and the employment of thesynchronous switching to reduce the conduction loss. Note that the difference in the loss reduction between Fig. 20(a) and (b),occurs due to the loss calculation error in the simulators.
Fig. 21 describes the cost breakdown of the inverter-side inductor material under two designs of %ZL. The ferrite core material
can provide a lower core loss at the high switching frequency of several hundreds of kHz compared to other core materials such as,e.g. silicon steel, amorphous iron or nanocrystals [41]-[42]. Nevertheless, a ferrite characteristic of a low saturation flux density
requires a large amount of the core material. Consequently, the core material cost dominates the overall inductor material cost.

1.00

Inductor material cost
reduction of 62%

0.08

Inductor material cost (Normalized)

0.90
0.80

0.22

0.70
Winding (Litz wire)

0.60

Bobbin (EE shape)
0.50Core (Ferrite)

0.40

0.03
0.07

0.70
0.30
0.20

0.28

0.10
0.00
%ZL=1.8%%ZL=0.5%

Fig. 21. Cost breakdown of inverter-side inductor material under two designs of %ZL. A cost reduction of 62% in the inductor material is achieved when decreasing
the inverter-side inductor impedance from 1.8% to 0.5%. Note that the cost calculation is based on the actual price of the prototype components, and is normalized
by the %ZL design of 1.8%.

TABLE IICOMPUTATION TIME IN CLOCK CYCLES OF CURRENT CONTROL LOOP.

Computationtime[clock cycles]
PI controller
Grid voltage
feedforward
CCM duty
generation
DCM duty
generation
Current mode
determination
Dead-timecompensation
Total

Conventional Conventional
Proposed
CCM
CCM/DCM
CCM/DCM
control
control
control(cf. Fig. 12(a)) (cf. Fig. 12(b)) (cf. Fig. 12(c))
15

15

15

4

0

0

0

8

9

0

36

37

0

12

12

8

8

8

27 (1 p.u.)

79 ( 2.9 p.u. )81 (3.0 p.u.)

Furthermore, a cost reduction of 62% in the inductor material is achieved with the decrease in the inverter-side inductor impedancefrom 1.8% to 0.5%.
Table II shows the approximate computation time for all the arithmetic operations in three current control loops shown in Fig. 12.
Both division and square root digital calculations are time-consuming computation involving multiple clock cycles. In particular,when a STM32 Cortex-M4 microcontroller is applied to process 32-bit floating-point single-precision data, 14 clock cycles are
required for a division or square root calculation, whereas 1 clock cycle is required for an addition or subtraction and 3 clock cycles
are required for a multiplication [43]. Note that the computation time for the division calculations can be shorten by using a look-up
table [44]. In the conventional CCM current control, only additions and multiplication are required for three operations, i.e. the PI

controller, the grid voltage feedforward and the dead-time compensation. Therefore, the computation time of the conventional
CCM current control is the shortest with 27 clock cycles. In the conventional CCM/DCM current control, a square root calculationis required to compute the DCM duty ratio as shown in Fig. 12(b), and two additional operations, i.e. the DCM duty generation andthe current mode determination, are necessary. Meanwhile, in the proposed CCM/DCM current control, a square root calculation is
unnecessary; however, multiple additions and multiplications are required in order to generate the DCM duty as shown in Fig.
12(c). Therefore, the computation time of the conventional and proposed CCM/DCM current control becomes approximately 3
times longer than that of the conventional CCM current control. Hence, the minimization of the inverter-side inductor is a trade-off
between the computation time and the grid current THD.

V. CONCLUSION
This paper presented a current mode control for the single-phase grid-tied inverter operating in both CCM and DCM in order toreduce the filter inductance without worsening the grid current THD. The proposed CCM/DCM current control satisfied theharmonic constraint defined in the grid standard such as IEEE-1547 even when the inverter-side inductor impedance issignificantly reduced from 1.8% to 0.5%. The proposed CCM/DCM current control was compared with the conventional CCM
current control and the conventional CCM/DCM current control.
First, with the employment of the conventional CCM current control, the grid current THD increased from 2.3% to 8.7% due tothe zero-current clamping phenomenon when the inductor impedance was minimized from 1.8% to 0.5%. The conventional CCM
current control could not compensate for the DCM nonlinearity to maintain the same current dynamic when the zero-current
clamping occurred. On the other hand, the proposed CCM/DCM current control compensated for the DCM nonlinearity andreduced the grid current THD from 8.7% to 2.1% even with the low inductor impedance of 0.5%. Consequently, this inductor
impedance minimization achieved the reductions of 51%, 62% and 35% in the inductor volume, the inductor material cost and theinverter loss at the light load of 0.1 p.u., respectively. However, these improvements was traded off by the long computation time ofthe proposed CCM/DCM current control which was 3 times longer than that of the conventional CCM current control.
Second, in the conventional CCM/DCM current control, the inductance must be used in the DCM nonlinearity compensation,
which made the control system dependent on the circuit parameter. This restricted the application of the conventional CCM/DCM
current control method to the residential PV systems, where the accurate value of the inductance was generally difficult to obtain.
On the other hand, the proposed CCM/DCM current control utilized the duty ratio at the previous calculation in order to bothcompensate for the DCM nonlinearity and detect the current modes regardless of the inductance.
A further research topic in this field is the development of the CCM/DCM current control for other topologies where theoperation in both CCM and DCM can provide improvements such as, e.g. boost converters, three-phase grid-tied inverters,

modular multilevel converters or flying capacitor multilevel converters, etc. The analysis procedure of the DCM nonlinearity andthe approach of the CCM/DCM current control in this paper are demonstrated in detail for the single-phase grid-tied inverter.
However, the derivation steps of the proposed CCM/DCM current control in this paper can be contributed as analysis guidelines forother converters.
REFERENCES[1]IEEE Application Guide for IEEE Std 1547, IEEE Standard for Interconnecting Distributed Resources With Electric Power Systems, IEEE Standard
1547.2-2008, 2009.

[2]

M. Liserre, F. Blaabjerg and S. Hansen, “Design and control of an LCL-filter-based three-phase active rectifier,” in IEEE Transactions on Industry
Applications, vol. 41, no. 5, pp. 1281-1291, Sept.-Oct. 2005.

[3]

G. Zeng, T. W. Rasmussen, and R. Teodorescu, “A novel optimized LCL-filter designing method for grid connected converter,” in Proc. 2nd IEEE Int. Symp.
Power Electron. Distrib. Generat. Syst., vol. 2, Jun. 2010, pp. 802–805.

[4]

J. Verveckken, J. F. Silva, and J. Driesen, “Optimal analytic LCL filter design for grid-connected voltage-source converter,” in Proc. EuroCon, Jul. 2013, pp.
823–830.

[5]

L. Shen, G. Asher, P. Wheeler, and S. Bozhko, “Optimal LCL filter design for 3-phase space vector PWM rectifiers on variable frequency aircraft powersystem,” in Proc. 15th Eur. Conf. Power Electron. Appl. (EPE), Sep. 2013, pp. 1–8.

[6]

R. A. Barrera-Cardenas, J. Zhang, T. Isobe and H. Tadano, "A comparative study of output filter efficiency and power density in Single-Phase Grid-Tied
Inverter using continuous or discontinuous current mode operations," 2017 19th European Conference on Power Electronics and Applications (EPE'17
ECCE Europe), Warsaw, 2017, pp. 1-10.

[7]

J.-W. Choi and S.-K. Sul, “A new compensation strategy reducing voltage/current distortion in PWM VSI systems operating with low output voltages,” IEEE
Trans. Ind. Appl., vol. 31, no. 5, pp. 1001–1008, Sep./Oct. 1995.

[8]

S. Bolognani, L. Peretti, and M. Zigliotto, “Repetitive-control-based selfcommissioning procedure for inverter nonidealities compensation,” IEEE Trans. Ind.
Appl., vol. 44, no. 5, pp. 1587–1596, Sep./Oct. 2008.

[9]

J. Schellekens, R. Bierbooms, and J. Duarte, “Dead-time compensation for PWM amplifiers using simple feed-forward techniques,” in Proc. XIX Int. Conf.
Electr. Mach., Sep. 2010, pp. 1–6.

[10] Y. wang, Q. Gao, and X. Cai, “Mixed PWM modulation for dead-time elimination and compensation in a grid-tied inverter,” IEEE Trans. Ind. Electron., vol.
58, no. 11, pp. 4797–4803, Oct. 2011.
[11] M. A. Herran, J. R. Fischer, S. A. Gonzalez, M. G. Judewicz and D. O. Carrica, “Adaptive Dead-Time Compensation for Grid-Connected PWM Inverters ofSingle-Stage PV Systems,” in IEEE Transactions on Power Electronics, vol. 28, no. 6, pp. 2816-2825, June 2013.
[12] H. Haga, K. Sayama, K. Ohishi, and T. Shimizu, “Fine Voltage Control Based on Frequency Separation Two-Degrees-of-Freedom Control for Single-Phase
Inverter,”in IEEJ J. Industry Applications, vol.5, no.6, pp.413-421, 2016.
[13] J. Sun, D.M. Mitchell, M. F. Greuel, P. T. Krein, and R. M. Bass: “Averaged Modeling of PWM Converters Operating in Discontinuous Conduction Mode,”IEEE Trans. Power Electron., vol.16, no. 4, pp.482-492, Jul. 2001.
[14] K. D. Gusseme, D. M. V. de Sype, A. P. V. den Bossche, and J. A. Melkebeek, “Digitally Controlled Boost Power-Factor-Correction Converters Operating in
Both Continuous and Discontinuous Conduction Mode,” IEEE Trans. Power Electron., vol. 52, no. 1, pp. 88-97, Feb. 2005.
[15] H. N. Le, K. Orikawa and J. I. Itoh, “Circuit-Parameter-Independent Nonlinearity Compensation for Boost Converter Operated in Discontinuous Current
Mode,” in IEEE Transactions on Industrial Electronics, vol. 64, no. 2, pp. 1157-1166, Feb. 2017.

[16] M. A. Herran, J. R. Fischer, S. A. Gonzalez, M. G. Judewicz and D. O. Carrica, “Adaptive Dead-Time Compensation for Grid-Connected PWM Inverters ofSingle-Stage PV Systems,” in IEEE Transactions on Power Electronics, vol. 28, no. 6, pp. 2816-2825, June 2013.
[17] T. Mannen and H. Fujita, “Dead-Time Compensation Method Based on Current Ripple Estimation,” in IEEE Transactions on Power Electronics, vol. 30, no.
7, pp. 4016-4024, July 2015.
[18] C. W. Clark, F. Musavi, and W. Eberle, “Digital DCM Detection and Mixed Conduction Mode Control for Boost PFC Converters,” IEEE Trans. PowerElectron., vol. 29, no. 1, pp. 347-355, Jan. 2014.
[19] K. D. Gussemé, David. M. V. D. Sype, A. P. M. V. D. Bossche, J. A. Melkebeek, “Input-Current Distortion of CCM Boost PFC Converters Operated in
DCM,” IEEE Trans. Power Electron., vol. 54, no. 2, pp. 858-865, Apr. 2007.
[20] T. S Hwang, and S. Y. Park, “Seamless Boost Converter Control Under the Critical Boundary Condition for a Fuel Cell Power Conditioning System,” IEEE
Trans. Power Electron., vol. 27, no. 8, pp. 3616-3626, Aug. 2012.
[21] D. Yamanodera, T. Isobe and H. Tadano, "Application of GaN device to MHz operating grid-tied inverter using discontinuous current mode for compact andefficient power conversion," 2017 IEEE 12th International Conference on Power Electronics and Drive Systems (PEDS), Honolulu, HI, 2017, pp. 1003-1009.
[22] Y. Kwon, J. Park, and K. Lee, "Improving Line Current Distortion in Single-Phase Vienna Rectifiers Using Model-Based Predictive Control," in Energies,
vol. 11, no. 5, pp. 1-22, May 2018.
[23] H. N. Le and J. Itoh, "Current THD reduction for grid-connected inverter operating in discontinuous current mode," 2016 IEEE International Conference on
Sustainable Energy Technologies (ICSET), Hanoi, 2016, pp. 270-275.
[24] H. N. Le and J. Itoh, "Current THD reduction for high-power-density LCL-filter-based grid-tied inverter operated in discontinuous current mode," 2017 19th
European Conference on Power Electronics and Applications (EPE'17 ECCE Europe), Warsaw, 2017, pp. 1-10.
[25] H. N. Le and J. Itoh, "Mixed conduction mode control for inductor minimization in grid-tied inverter," 2017 IEEE 12th International Conference on PowerElectronics and Drive Systems (PEDS), Honolulu, HI, 2017, pp. 893-900.
[26] T. Nakanishi, and J. Itoh, “Design Guidelines of Circuit Parameters for Modular Multilevel Converter with H-bridge Cell,” in IEEJ J. Industry Applications,vol.6, no.3, pp.231-244, May 2017.
[27] Y. Lei, C. Barth, S. Qin, W. Liu, I. Moon, A. Stillwell, D. Chou, T. Foulkes, Z. Ye, Z. Liao, and R. C. N. Pilawa-Podgurski, “A 2-kW Single-Phase
Seven-Level Flying Capacitor Multilevel Inverter With an Active Energy Buffer,” in IEEE Transactions on Power Electronics, vol. 32, no. 11, pp.
8570-8581, Nov. 2017.
[28] V. V. S. Pradeep Kumar and B. G. Fernandes, “A Fault-Tolerant Single-Phase Grid-Connected Inverter Topology With Enhanced Reliability for Solar PV
Applications,” in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 5, no. 3, pp. 1254-1262, Sep. 2017.
[29] R. N. Beres, X. Wang, M. Liserre, F. Blaabjerg and C. L. Bak, “A Review of Passive Power Filters for Three-Phase Grid-Connected Voltage-Source
Converters,” in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 4, no. 1, pp. 54-69, Mar. 2016.
[30] D. Bortis, D. Neumayr and J. W. Kolar, “ηρ-Pareto optimization and comparative evaluation of inverter concepts considered for the GOOGLE Little Box
Challenge,” 2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL), Trondheim, 2016, pp. 1-5.
[31] M. Kazmierkowski, R.Krishnan, and F.Blaabjerg, Control in Power Electronics. Selected Problems, Academic Press 2002, ISBN 0-12-402772-5.
[32] D. N. Zmood and D. G. Holmes, “Stationary frame current regulation of PWM inverters with zero steady-state error,” in IEEE Transactions on PowerElectronics, vol. 18, no. 3, pp. 814-822, May 2003.
[33] R. Teodorescu, F. Blaabjerg, M. Liserre and P. C. Loh, “Proportional-resonant controllers and filters for grid-connected voltage-source converters,” in IEEProceedings - Electric Power Applications, vol. 153, no. 5, pp. 750-762, Sep. 2006.
[34] S. Jeong and M. Park, “The analysis and compensation of dead-time effects in PWM inverters,” IEEE Trans. Ind. Electron., vol. 38, no. 2, pp. 108–114, Apr.
1991.

[35] S. Hwang and J. Kim, “Dead time compensation method for voltage-fed PWM inverter,” in IEEE Trans. Energy Convers., vol. 25, no. 1, pp. 1–10, Mar. 2010.
[36] N. Agarwal, A. Arya, M. W. Ahmad and S. Anand, “Lifetime Monitoring of Electrolytic Capacitor to Maximize Earnings From Grid-Feeding PV System,”in IEEE Transactions on Industrial Electronics, vol. 63, no. 11, pp. 7049-7058, Nov. 2016.
[37] J. Mühlethaler, “Modeling and Multi-Objective Optimization of Inductive Power Components”, Ph.D. dissertation, Dept. Inform. Technol. Elect. Eng., Swiss
Federal Inst. Technol. Zurich, Zurich, Switzerland, 2012.
[38] P. Rodriguez, A. V. Timbus, R. Teodorescu, M. Liserre and F. Blaabjerg, "Flexible Active Power Control of Distributed Power Generation Systems During
Grid Faults," in IEEE Transactions on Industrial Electronics, vol. 54, no. 5, pp. 2583-2592, Oct. 2007.
[39] S. Jain and V. Agarwal, “A single-stage grid connected inverter topology for solar PV systems with maximum power point tracking,” IEEE Trans.PowerElectron., vol. 22, no. 5, pp. 1928–1940, Sept. 2007.
[40] Y. Yang, H. Wang and F. Blaabjerg, “Reactive Power Injection Strategies for Single-Phase Photovoltaic Systems Considering Grid Requirements,” in IEEE
Transactions on Industry Applications, vol. 50, no. 6, pp. 4065-4076, Nov.-Dec. 2014.
[41] V. Leonavicius, M. Duffy, U. Boeke and S. C. O. Mathuna, “Comparison of realization techniques for PFC inductor operating in discontinuous conductionmode,” in IEEE Transactions on Power Electronics, vol. 19, no. 2, pp. 531-541, Mar. 2004.
[42] M. S. Rylko, B. J. Lyons, J. G. Hayes and M. G. Egan, “Revised Magnetics Performance Factors and Experimental Comparison of High-Flux Materials forHigh-Current DC–DC Inductors,” in IEEE Transactions on Power Electronics, vol. 26, no. 8, pp. 2112-2126, Aug. 2011.
[43] Floating point unit demonstration on STM32 microcontrollers, Application note, May 2016, STMicroelectronics.
[44] Sh. F. Lim, and A. M. Khambadkone, “A Simple Digital DCM Control Scheme for Boost PFC Operating in Both CCM and DCM,” IEEE Trans. PowerElectron., vol. 47, no. 4, pp. 1802-1812, Aug. 2011.