Experimental Verification of MHz Inverter Constructedfrom Frequency Multiplying Circuit with Soft-Switching
Koji Orikawa, Nagaoka University of Technology, Japan, orikawa@vos.nagaokaut.ac.jp
Jun-ichi Itoh, Nagaoka University of Technology, Japan, itoh@vos.nagaokaut.ac.jp

Abstract
This paper discusses a verification of an inverter outputs MHz frequency without fastswitching semiconductor switches. The proposed inverter consists of a multi-phase inverter
using silicon switching devices and multi-core transformers. By the frequency multiplying, theproposed circuit can output high frequency over the switching frequency. Moreover, theseries resonance using a leakage inductance of the multi-core transformers and a resonantcapacitor is applied in order to achieve sinusoidal output voltage. A prototype circuit isexperimentally verified and theoretically analyzed in terms of soft-switching. As a result, it isconfirmed the prototype circuit can output sinusoidal output voltage of 2.5 MHz with theswitching frequency of 500 kHz. In addition, a required dead time for zero voltage switchingis theoretically analyzed and experimentally verified using a prototype circuit.

1.

Introduction

Recently, high-efficiency high-frequency inverters which output MHz frequency are
increasingly received attentions for applications of wireless power transfer for EV chargers
and plasma generators, and so on [1,2]. 6.78 MHz and 13.56 MHz are candidates for those
applications as output frequency of the high-frequency inverters. On the other hand, wide
gap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) are used widely
due to fast-switching and low conduction loss. However, power consumption of a gate drive
circuit becomes large in order to drive wide gap semiconductor [3]. In addition, it is difficult tocontrol a gate signal of each switch due to low gate threshold voltage of SiC and GaN.
Class E inverters have been studying because they can achieve very high efficiency due tozero voltage switching (ZVS) and zero-derivative switching (ZDS) [4-7]. However, design ofcircuit parameters is difficult and it is designed by simulation. On the other hand, the inverter
which can output high frequency over the switching frequency have been proposed by theauthors [8]. In [8], the fundamental operation of the proposed circuit has been experimentally
verified. In the proposed circuit, the switching frequency is lower than the output frequency.
dv/dt of gate-source voltage is not high because semiconductor devices which have slow
speed can be used. Therefore, the proposed circuit can supress EMI noise. However, thenumber of switch is large compared with that of conventional single phase inverter, the class
E inverter, and so on. As a result, the switching loss at each phase of the multi-phase
inverter should be reduced. In order to reduce the switching frequency, ZVS is effective.
However, the condition which achieves ZVS in the proposed circuit has not been clarified sofar.
This paper verifies experimentally the proposed circuit based on the frequency multiplying
method using silicon switching devices and theoretically analyzed it in terms of the softswitching. The proposed circuit can output frequency which is over switching frequency. First,
the principle of the proposed circuit is described. Then, an operation of the proposed circuit istheoretically analyzed using an equivalent half-bridge circuit. Finally, a validity of thecondition which achieves ZVS is experimentally verified at both cases without resonance andwith resonance.

2.

Proposed circuit based on frequency multiplying method

2.1.

Circuit configuration

Figure 1 shows the circuit configuration of the proposed circuit in a five-phase inverter
model. The primary side of the multi-core transformer [9] is connected in parallel. A common
connection point of the primary side of the transformer is connected to the neutral point of
DC link capacitors Cdc. On the other hand, the secondary side of the multi-core transformer isconnected in series. The resonant capacitor which is used for the series resonance with theleakage inductance of the multi-core transformer is connected to the secondary side of themulti-core transformer. Note that magnetizing inductance is neglected.
Figure 2 shows the principle of the proposed frequency multiplying method. In the fivephase voltage-type inverter, each of the voltage phases is shifted by 72 degree and operated
with square wave modulation. As a result, the output frequency fout is expressed by (1) using
the switching frequency fsw and the number of phase in the multi-phase inverter N.
f out  N  f sw

(1)

Therefore, the multi-phase inverter can output high frequency which is over the switchingfrequency even low switching frequency is used. If SiC switching devices are used in the
proposed circuit, increasing of the output frequency and capacity of power converters is easy.
In addition, cooling is easier because the heat generated from the multi-phase inverter canbe dissipated for a number of switches.

2.2.

Principle of zero voltage switching (ZVS)

Figure 3 describes the principle of ZVS in the proposed circuit for reduction of theswitching loss. Fig. 3(a) shows a half bridge equivalent circuit of the proposed circuit. In Fig.
3(a), the DC link capacitor Cdc is assumed to be a voltage source. R is resistancecomponents transformed to the primary side of the multi-core transformer, which includes awire resistance r1 and r2 and a load resistance Rload. L is inductance components transformed
to the primary side of the multi-core transformer, which includes a leakage inductance l1 andl2. C is an equivalent resonant capacitor. Cr is a resonant capacitor connected to thesecondary side of the multi-core transformer. By analyzing the operation of the proposed
circuit, R, L, C and Cr are expressed by (2), (3), (4) and (5) using turn ratio of the winding in
the multi-core transformer n and the resonant frequency fr.
Tsw

Multi-phase inverter
Spy

Spx

Spw

Spv

Spu

vuo

Cdc
Vin

vvo

u
v

o
Snu

Vin/2
Resonancev
0capacitor uo-V /2
inC
72 deg.
r
r2
Vin/2
vvo
0
-Vin/2iload
72 deg.
Vin/2
fout  N  f sw
vwo
0
-Vin/2vload
72 deg.
Vin/2
Rload
vxo
0
-Vin/2

Leakageinductance n=N1/N2
iu
l1 r1 N1 N2 l2

Snv

w
Snw

vwo

x
Snx

Cdc

Sny

y

vxo
vyo

Multi-core transformers
Output frequency fout: 2.5 MHz
Switching frequency fsw: 500 kHz
Number of phase N: 5

(Without resonance capacitor)(With resonance capacitor)

Fig. 1. Configuration of proposed circuit.

Vin/2
vyo
0
-Vin/2
Vin/2
vload
0
-Vin/272 deg.

Tsw/5

Vin/2
vload 0-Vin/2

Fig. 2. Control method.

R  N  r1  n2  Rout  r2 

 (4) C  n C (5)C  1/ 2f r  L(2) L  N  l1  n 2  l2 (3)

2

2

r

Figure 4 shows operation mode of the proposed circuit. A condition which achieves ZVS isdecided by the dead time and circuit parameters. In this section, the required dead time for
ZVS in the proposed circuit at both cases without the resonant capacitor and with theHard-switching
ON

i1
Vin
2

Cp

io=i1-i2

L

R

L C

Vds1

Dead time
Td

Dead time
Td

S1
R

Zero voltage switching

OFF
ON
S2

i2

Equivalent load
S2

Cp Vds2

Vin
2

OFF
Vin
Vds1
0

(a)

Vin

Dead time Td

Vds2
0

ON
S1

IT1
io

OFF

0

T2

T2

ON

t

t

S2
Mode I
With resonance capacitor
0(Without resonance capacitor)

OFF
Fig. 3(c), (d)

II

(b)

III
IV V
T1
T1+T2
(T1_r) (T1_r+T2_r)

I

II
0

T1<T1+T2<Td(T1_r<T1_r+T2_r<Td_r)(c)

III IVV
T1
T1+T2(T1_r) (T1_r+T2_r)
T1<Td<T1+T2
T1_r<Td_r<T1_r+T2_r(d)(a) Half bridge equivalent circuit. (b) Gate signals with dead-time.
(c) Enlarged waveforms at hard-switching.
(d) Enlarged waveforms at zero voltage switching.
Fig. 3. Principle of zero voltage switching.
i1
Vin
2

S1

Equivalent
load
Vin
2

i1
Cp Vds1

Hard-switching
Mode I(Fig. 3(c))
Zero voltage switching
Mode I(Fig. 3(d))(a) S1:On, S2:Off

S1

Equivalent
load

i2

S2

Vin
2

Cp Vds2Vin
2i1
Cp Vds1

S1

Equivalent
load

i2

S2

Vin
2

Cp Vds2Vin
2

Cp Vds1i2

S2Mode II,III,IV

Mode V

Mode II,III

Mode IV,V(b) S1:Off, S2:Off(c) S1:Off, S2:On

Fig. 4. Operation modes of the proposed circuit.

Cp Vds2

resonant capacitor is theoretically discussed by analyzing the operation modes of theequivalent circuit.
The case without the series resonancei) Mode I
The Mode I is a period before the dead time starts. In the Mode I, the switch S1 is on-state
and the switch S2 is off-state. Note that the current ISw flows to the S1. In this paper, theperiod which the Mode I ends is defined as t=0.
ii) Mode II
In the Mode II, the S1 is turned off and the period of the dead time starts. The Mode II is
kept until the voltage of parasitic capacitance in S1 is charged up to the input voltage or thevoltage of the parasitic capacitance in S2 is discharged to zero. Note that the period which
the Mode II ends is defined as t=T1. By solving the circuit equation of Fig. 3(a), the drainsource voltage of S1 vds1 is expressed by (6). Note that 1 is the natural angular frequency
and K1 is the coefficient. 1 and K1 are expressed by (7) and (8).


V 
K

 R 
vds1 (t )  in 1  exp t  cos 1t  1 sin t  (6) 1 
2 
1 2 L 




2

1
I
R
 R 

 Sw (8) (7) K1 
2 L C pVin
2 LC p  2 L 

where Vin is the input voltage.
By solving (6) = 0, the T1 which the Mode II ends is expressed by (9), provided that the circuit
parameters satisfy (10).
2








 V  1L4Vin /  in 
 2 I sw  2
 L  I sw
 Cp 
 C 


p 




T1  2 LC p Sin 1(9)

C p R  2

L
R

(10)

On the other hand, the current of the neutral point of the DC link voltage at t=T1 is expressedby (11) using K2, which is the coefficient value. K2 is expressed by (12).
K R 
I T 1  i1 T1   i2 T1   I Sw exp 
T1  cos 1T1  2 sin 1T1 
1
 2 L 


(11)

K2 

Vin
R

(12)
2 LI Sw 2 Liii) Mode III
In the Mode III, Vin/2 is applied to the equivalent load of the equivalent circuit. Therefore,
the current of the neutral point of the DC link voltage is expressed by (13). The time T2 which
the current polarity of the neutral point of the DC link voltage is changed is expressed bysolving (13) = 0. From (13) = 0, T2 is obtained by (14). If the dead time Td is larger than T1+T2,
the parasitic capacitance of drain-source in S2 is charged. In this case, S2 is turned on while
the drain-source voltage of S2 is not zero. Therefore, ZVS cannot be achieved. As a result,
the required dead time which achieves ZVS Td is expressed by (15) using T1 and T2.
V   t Vio t    I T 1  in e L  in (13)
2R 
2R

R

T2 

L  2 RI T 1  (14)ln1 
R 
Vin 

T1  Td  T1  T2 (15)The case with the series resonancei) Mode I
When the resonant capacitor is connected, the resonance occurs among the equivalentleakage inductance, the equivalent resonant capacitor and the parasitic capacitances ofdrain-source. Therefore, not only the current of S1 ISw1 but also the current of S2 ISw2 flows.

ii) Mode II
In the Mode II, vds1 is expressed by (16)vds1 (t ) 



Vin 
K

 R 
t  cos 2t  3 sin 2t 
1  exp 
2 
2 2 L 




(16)

where 2 is the natural angular frequency and K3 is the coefficient. 2 and K3 areexpressed by (17) and (18).
2 

1  2C p   R 
1 


2 LC p 
C   2 L 

2

K3 

(17)

R I Sw1  I Sw2
2L
C pVin(18)

From (16) = 0, T1_r which the Mode II ends can be obtained. However, T1_r is almost same
to T1, provided that (7) is assumed to be satisfied.
On the other hand, the current of the neutral point of the DC link voltage at t=T1_r isexpressed by (19) using K4, which is the coefficient value. K4 is expressed by (20).
IT1 i1 T1   i2 T1 (19) K 4 K R 
 I Sw1  I Sw2 exp 
T1  cos  2T1  4 sin  2T1 
2
L



2


 2C p  R
Vin
1 

(20)
2 LI Sw1  I Sw2  
C  2 Liii) Mode III
In the Mode III, Vin/2 is applied to the equivalent load of the equivalent circuit. Therefore,
the current of the neutral point of the DC link voltage is expressed by (21) by solving thetransient phenomenon of the equivalent circuit. Note that 3 is the natural angular frequency
and K5 is the coefficient. 3 and K5 are expressed by (22) and (23).
K R 
io  I T 1 exp t  cos 3t  5 sin 3t  (21) 3 
3
 2 L 


1
 R 


2 LC  2 L 

2Vin Vc (0)R(22) K 5  2
(23)
LIT 1
2L

where Vc(0) is the voltage of the equivalent resonant capacitor at t=T1_r.
The time T2_r which the current polarity of the neutral point of the DC link voltage is changedin the Mode III is obtained by (24) from (21) = 0. As a result, the required dead time Td_r
which achieves ZVS when the resonant capacitor is connected is expressed by (25) using T1
and T2_r.
cos 3T2 

3.
3.1.

K5

3

sin 3T2  0(24)

T1  Td _ r  T1  T2 _ r(25)

Experimental results
The case without the series resonance

Figure 5 shows fundamental waveforms without the series resonant capacitor. In Fig. 5,
the dead time which satisfies (15) is used. The switching frequency and the output frequency
is 500 kHz and 2.5 MHz. A resistance of 33.3  is connected as a load. The input voltage Vin
is 48 V. From Fig. 5, it is confirmed that vload is not a square waveform because theimpedance of leakage inductances is large at the output frequency of 2.5 MHz.
Figure 6 and 7 show experimental waveforms which include two gate signals, the drainsource voltage of S2 and the primary current of the multi-core transformer. In theseexperiments, the dead time is changed. In
Fig. 6(a) and Fig. 7(a), the dead time which
satisfies (15) is used. In Fig. 7(a), after thepolarity of the output current in U-phase iu ischanged, vgs2 is turned on rapidly. Therefore,
the parasitic capacitance drain-source in the
S2 is not charged. As a result, ZVS isachieved because vds2 is zero when vgs2 isturned on.
On the other hand, in Fig. 7(b) and (c),the used dead time does not satisfy (15).
vds2 has a resonance between the leakage
inductance and the parasitic capacitances of0vgs(S1,S2)

vgs(S2)

vgs(S1)10 (V)vload

20 (V)

iload

500 (mA)

0
vload

0
iload
200 (ns)Fig. 5. Fundamental waveforms
without resonance capacitor(T1<Td<T1+T2, Td=112.7 ns).
vgs(S1)0
vgs(S1,S2)

vgs(S1)

vgs(S2)

vgs(S2)10 (V)

10 (V)0vgs(S1,S2)

vds2

20 (V)

vds2
0
vds2

1 (A)

iu

20 (V)

0
vds2

iu

1 (A)

0
iu

0
iu

20 (ns)200 (ns)Fig. 7(a)(a) T1<Td<T1+T2 (Td=112.7 ns).

0
vgs
(S1,S2)

vgs(S1)(a) T1<Td<T1+T2 (Td_r=112.7 ns).
vgs(S1)

vgs(S2)10 (V)

vgs(S2)10 (V)0vgs(S1,S2)

vds2

20 (V)

vds2
0
vds2

1 (A)

iu
0
iu

20 (V)

0
vds2

iu

1 (A)

0
iu
200 (ns)

20 (ns)Fig. 7(b)(b) T1<T1+T2<Td (Td=151.2 ns).

(b) T1<T1+T2<Td (Td=151.2 ns).
vgs(S1)0
vgs(S1,S2)

vgs(S1)

vgs(S2)

vgs(S2)10 (V)

10 (V)0vgs(S1,S2)

vds2

20 (V)

vds2
0
vds2

1 (A)

iu

0
vds2

20 (V)

iu

1 (A)

0
iu

0
iu
200 (ns)

20 (ns)Fig. 7(c)(c) T1<T1+T2<Td (Td=160.6 ns).
Fig. 6. Whole waveforms without series resonance.

(c) T1<T1+T2<Td (Td=160.6 ns).
Fig. 7. Enlarged waveforms of Fig. 6.

drain-source during the dead time.
Therefore, in Fig. 7(b) and (c), ZVS is notachieved when vgs2 is turned on. From Fig. 7,
the validity of the theoretical discussion in
the chapter II was experimentally confirmed.

0
vgs(S1,S2)

vgs(S1)

vgs(S2)10 (V)

20 (V)

vload
0
vload

3.2.
The case with the series
resonance

1 (A)

iload
0
iload

Figure 8 shows the fundamental
waveforms when the series resonance isapplied. The resonance capacitor isconnected to the secondary side of themulti-core transformers. In Fig. 8, the dead200 (ns)Fig. 8. Fundamental waveforms
with resonant capacitor(T1<Td_r<T1_r+T2_r,Td_r=98.5 ns).
vgs(S1)0
vgs(S1,S2)

vgs(S1)

vgs(S2)10 (V)0vgs(S1,S2)

vds2

vds2
0
vds2
0
iu

10 (V)

20 (V)

20 (V)
4 (A)

iu

0
vds2
0
iu

vgs(S2)4 (A)iu

200 (ns)

20 (ns)Fig. 10(a)(a) T1<Td_r<T1_r+T2_r (Td_r=98.5 ns).

(a) T1<Td_r<T1_r+T2_r (Td_r=98.5 ns).
vgs(S1)0
vgs(S1,S2)

vgs(S1)

vgs(S2)0
vgs(S1,S2)

vds2

vds2
0
vds2
0
iu

10 (V)

10 (V)

20 (V)

20 (V)
4 (A)

iu

0
vds2
0
iu

vgs(S2)4 (A)iu
20 (ns)200 (ns)Fig. 10(b)(b) T1<T1_r+T2_r<Td_r (Td_r=109.7 ns).

(b) T1<T1_r+T2_r<Td_r (Td_r=109.7 ns).
vgs(S1)0
vgs(S1,S2)

vgs(S1)10 (V)

10 (V)0vgs(S1,S2)

vds2

vds2
0
vds2
0
iu

vgs(S2)20 (V)
4 (A)iu
200 (ns)

0
vds2
0
iu

vgs(S2)20 (V)

4 (A)iu
20 (ns)Fig. 10(c)(c) T1<T1_r+T2_r<Td_r (Td_r=123.7 ns).
Fig. 9. Whole waveforms with series resonance.

(c) T1<T1_r+T2_r<Td_r (Td_r=123.7 ns).
Fig. 10. Enlarged waveforms of Fig. 9.

time which satisfies (25) is used. From Fig. 8, it is confirmed that the load voltage is almost
sinusoidal waveform due to the series resonance.
Figure 9 and 10 show experimental waveforms which include two gate signals, the drainsource voltage of S2 and the primary current of the multi-core transformer when the resonantcapacitor is connected. In Fig. 9(a) and Fig. 10(a), there is no rise of vds2 during the deadtime because the dead time which satisfies (25) is used. Therefore, not only when the series
resonance is not applied but also when the series resonance is applied, ZVS is achieved.
Therefore, the sinusoidal output at soft-switching on the proposed circuit is achieved. On theother hand, in Fig. 10(b) and (c), the used dead time does not satisfy (25). Therefore, hardswitching occurs because vds2 is increased during the dead time. From these experiments,
the proposed circuit can obtain high efficiency even the output frequency is 2.5MHz.

4.

Conclusion

This paper describes the high-frequency inverter outputs MHz frequency without fastswitching devices. By the frequency muliplying, the proposed circuit can output highfrequency over the switching frequency. First, the required dead time which achieves ZVS
was calculted by using the equivalent circuit. Finally, the protoype circuit was experimentally
verified. It was confirmed the prototype circuit can output 2.5 MHz with the switchingfrequency of 500 kHz at ZVS condition. In addition, it was experimentally confirmed that only
when the series resonance is not applied but also when the series resonance is applied, ZVS
is achieved.

5.
[1]

[2]
[3]

[4]

[5]

[6]

[7]

[8]

[9]

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