Our Embedded Dream of the“Invisible” Future
Since the invention of semiconductor chips, the evolution of mankind’s culture, society and lifestyle has accelerated at a pace never before experienced.
Information processing and communications networks have benefited from thisevolution, fulfilling an important role as driving forces for the industry.
Progressing from a time when people believed that a minimal number ofcomputers would be sufficient for the world, we have reached the stage wherecomputers are personally available and sophisticated semiconductor technology
is implemented in a wide-range of equipment, such as mobile phones, personal
digital assistants (PDAs), game consoles, digital televisions, and automobiles. In
the future, computing functions with broadband connections will be invisibly
embedded into the environment surrounding us in our daily lives. It will be a worldof ubiquitous computing where everyone can enjoy information and services anytime and anywhere.
Embedded in our genetic code, our dream of the “invisible” future is driving
us on to the next stage of evolution.

12 TOKYO ELECTRON

The Rapidly Expanding Scale and Scope ofSemiconductor ApplicationsThe world of the “invisible” future will consume a huge volume of semiconductorchips. Semiconductors will be embedded in everything, and large addressing space formemory and massively parallel processing with a numerous array of processors willrealize intelligent functions. Demand for application-specific system on a chip (SOC) isalready rapidly increasing for a broad range of market segments. We are headed into
the “Semiconductor Big Bang” in both scale and scope of applications.

Expansion of Worldwide Semiconductor Market

$54B

$226B

$300-350B

19902000

2010
Source: Dataquest, TEL estimate

Nano-scale, High-speed, andEnergy-saving Requirements
Miniaturization of integrated circuits is progressing toward the nano-scale. In thefuture, they will be invisibly embedded in everything, finally realizing ubiquitous computing. This growing demand for intelligent processing for high-speed execution of complicated, large-scale algorithms accelerates chip shrinkage and high-speed capability. But
shrinkage and high-speed requirements create heat dissipation problems. In addition tothese problems, lower energy consumption is required, especially for semiconductor
chips that are used for mobile gears to achieve long hours of battery-powered outdoor
usage. To solve these problems, we are challenged to introduce new technologies.

13Every Product Demonstrates
Key Process Innovations
Major changes are taking place in processes and materials for semiconductor manufacturing. To meet the technological challenges of greater scales of integration, higher speeds and lower energy consumption, the industry needs stateof-the-art technologies, such as lithography for finer geometries, low-resistanceinterconnect, low-k intermetal dielectric films, and ultra-thin gate dielectric films.
TEL is committed to the development of these cutting-edge technologies, andproviding its customers with “best-of-breed solutions” based on its proprietary
technology and a world-class lineup of products.

Terminology
1. Lithography
This technique is used to transfer the circuit
pattern from a photomask to the wafer’ssurface. A stepper-scanner is used toexpose the pattern onto a photoresist-coated wafer. The exposed wafer is then developed to reveal the pattern.
2. Low-k dielectric film
As design rules become finer and the space
between interconnects becomes narrower,
the speed of electrons traveling throughinterconnects is more easily affected by theamount of parasitic capacitance in the intermetal dielectric film, causing them to slow
down. To solve this problem, it is effective to
use low-k film.

Dielectric Film and Gate Electrode Formation
The transistors used in large scale integrations (LSIs) comprise an electrode anddielectric film stacked on silicon, and a source and drain into which impurities aredoped. In a high-speed logic chip, the main problem that arises is the delay in the electric signal, particularly in the gate section. To try and minimize or eliminate this problem,
development efforts are focusing on further miniaturization of the transistor itself, theuse of low-resistance gate electrodes, formation of ultra-thin gate dielectric film, anddiscovery of materials and processes to support even thinner film formation.

Thermal Processing System(Single Wafer)

Thermal Processing System(Flexible Batch)TM

TELFORMULA

SRTF

Featuring a newly developed
heater capable of high-speed
temperature control, this system
handles a wide range ofoxidation and LP-CVD processessequentially. It can flexibly
process one to 25 wafers.

This system is a rapid thermal
process system that uses hot-wall
furnace technology. It achieves
substantial reductions in cost andenergy consumption.

Design Rule=130nm

Coater/ Developer

CLEAN TRACK ACT® series

CoSi

180nm

Poly-Silicon
SiON

SiO2

SourceDrain

Attached to exposure equipment,
this system coats and develops
photoresists on the wafer surface.
The CLEAN TRACK ACT® series ishighly reliable and holds anoverwhelming share of the market.

Old Type Gate
Advanced Gate
(Logic Device)

Cleaning System

Plasma Process System

UW SeriesTrias™ SPA

This system cleans particles andcontaminations attached to the surface
of a wafer using acid and ozone
solutions. Its reduced chemical
requirements and smaller footprint lower
the Cost of Ownership.

This system uses plasma to perform
nitridation of gate films. Its damagefree plasma enables chipmakers toform highly reliable and low leakage
gate films.

14 TOKYO ELECTRON

3. Making thinner gate dielectric film
Based on the scaling law, if the gate length
and width and its dielectric film thickness
are made smaller and thinner, the electric
current, voltage, signal delay time, and otherperformance specifications of a transistor
will improve.

Copper Interconnect and Intermetal
Dielectric Film Formation
The most advanced chips exhibit a high degree of integration, with tens of millionsof transistors on a single chip. Interconnect is highly miniaturized and the space between
interconnects is minimal. Consequently, the signal delay in the electric circuitry cannot beneglected. To combat this problem, the aluminum interconnect and SiO2 dielectric film
are being replaced with copper interconnect and low-k dielectric materials in the latest
processes. With logic chips in particular, multilayer circuitry is an essential technology,
and the industry is actively developing technologies for interconnect integration.

CU ECMD

NuTool™ 2000 (Product of NuTool Inc., U.S.A.)
A copper electroplating system that utilizes special
proprietary technology to greatly reduce the amountof polishing required after copper film deposition.

SOD Coater

CLEAN TRACK ACT® seriesThis system deposits low-k
intermetal dielectric films using thespin-on coating method. The system
is expected to make great inroads
into the intermetal dielectric film
market, beginning with the 100nm
generation.

Aluminum + SiO2Interconnect

Plasma Etch SystemTelius™
A plasma etch system for dielectricfilms that demonstrates superior
capabilities for high-end
applications, such as deep trenchand self align contact etching.

Cleaning System

PR Series

Copper + Low-k DielectricInterconnect

The system removes post-etching
polymers using chemical reactions
and spray technology. The unique
double slide chamber achieves highcleaning performance and shortened
process times.

Single Wafer CVD System

Trias™
Using heat and plasma, this systemforms metal films or barrier films.
This system claims the highest shareof the market for DRAM applications.

15

Providing Further Valueas a Leading SupplierAs personal digital electronics and an array of new products become popular in markets, semiconductor demand will progressively shift to products withshort life cycles. Because diversification of IC applications is proceeding simultaneously, chipmakers are anticipated to increasingly specialize in design andincrease their reliance on equipment suppliers for semiconductor manufacturing
processes. Foundries are also expected to expand their commissioning of equipment suppliers for advanced processes for the designs created by fabless makers.

As Chipmakers Orient “What to Make,”
Tool Suppliers Must Come Up with“How to Make It.”
During the dawning of the age of semiconductors, the equipment suppliers’ onlyrole was providing hardware. However, opportunities have increased for equipment
suppliers to contribute a new type of value-added content, in the form of expertise.
Equipment suppliers can offer the total process recipe, and supply integrated solutions
for multiple adjoining processes, or supply the systems that can self-optimize theprocesses with fewer manual operations. Leveraging its expansive product lineup andworld-class R&D capabilities, TEL is concentrating on providing further added value toits customers.

Broadening Spectrum of the Role of Semiconductor Equipment Suppliers

FAB Management
Manufacturing
Technology
Process Control

Process Integration

Process Recipe
Production Tool
Manufacturing
1970s

16 TOKYO ELECTRON

1980s

1990s

2000s

Advanced Process Control
Advanced process control (APC) is the automation of process control functions
performed in individual systems or between systems to keep process stability and higher yield stability. So far, this function has been mainly achieved through the interventionof people in production lines by monitoring the quality of the product or checking
whether mistakes have occurred.

Why Yield Management is Important
Semiconductor manufacturing utilizes state-of-the-art technologies in the fields ofphysics and chemistry. However, due to its technological complexities, there is no guarantee that every chip will be perfect. Since the proportion of good to bad product is aquestion of survival for chipmakers, increasing yield is one of the most important issues
for them from cost and speed-of-launch perspectives. Because APC contributes in lowering chipmakers’ production costs, it will be one of the chief factors in differentiating
semiconductor production equipment in the near future.
Enhanced Yield with APC

Number of chips

With APC
100

Number of chips

Without APC
10000

Higher product yield

Good product yield
increases under APC

TEL’s Integrated Metrology Software —a Solution for APC
In February 2001, TEL purchased Timbre Technologies Inc., of the United States,
acquiring its Optical Digital Profilometry™ metrology software. Compared with conventional SEM, ODPTM greatly reduces the time to measure critical dimensions, cross sectional profile and film thickness. In our R&D efforts, we have vigorous programs under
way to develop APC technologies at the equipment level, incorporating this technology
into our greatest area of strength, lithography processes (Etch and Clean Track) forprocess monitoring.
Scanning
Electron Microscope

Optical Digital Profilometry
550500
450
400
350
300
250
200
150
100
500-300 -200 -100

Measurement time
About 1 hour0100

200300Measurement time
A few seconds

Measurement time is for one point cross section on a wafer.

17