HD-6402
CMOS Universal Asynchronous
Receiver Transmitter (UART)

March 1997

Features

Description• 8.0MHz Operating Frequency (HD-6402B)

The HD-6402 is a CMOS UART for interfacing computers ormicroprocessors to an asynchronous serial data channel.
The receiver converts serial start, data, parity and stop bits.
The transmitter converts parallel data into serial form andautomatically adds start, parity and stop bits. The data word
length can be 5, 6, 7 or 8 bits. Parity may be odd or even.
Parity checking and generation can be inhibited. The stopbits may be one or two or one and one-half when transmitting 5-bit code.

• 2.0MHz Operating Frequency (HD-6402R)• Low Power CMOS Design• Programmable Word Length, Stop Bits and Parity• Automatic Data Formatting and Status Generation• Compatible with Industry Standard UARTs• Single +5V Power Supply

The HD-6402 can be used in a wide range of applications
including modems, printers, peripherals and remote dataacquisition systems. Utilizing the Intersil advanced scaled
SAJI IV CMOS process permits operation clock frequencies
up to 8.0MHz (500K Baud). Power requirements, by comparison, are reduced from 300mW to 10mW. Status logic
increases flexibility and simplifies the user interface.

• CMOS/TTL Compatible Inputs

Ordering Information
PACKAGETEMPERATURE RANGE

2MHz = 125K BAUD

8MHz = 500K BAUD

PKG. NO.

Plastic DIP-40oC to +85oC

CERDIP-40oC to +85oC

HD1-6402R-9

HD1-6402B-9

F40.6

SMD#

-55oC to +125oC

5962-9052501MQA

5962-9052502MQA

F40.6

HD3-6402R-9

HD3-6402B-9

E40.6

PinoutHD-6402 (PDIP, CERDIP)
TOP VIEW
VCC

140 TRCNC

239 EPEGND

338 CLS1RRD

437 CLS2

RBR8536 SBS

RBR7635 PI

RBR6734 CRL

RBR5833 TBR8RBR4

932 TBR7RBR31031 TBR6RBR21130 TBR5RBR11229 TBR4PE

1328 TBR3FE

1427 TBR2OE

1526 TBR1SFD

1625 TRO

RRC

1724 TRE

DRR

1823 TBRLDR

1922 TBRE

RRI

2021 MRCAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

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File Number2956.1

HD-6402
Functional Diagram(32)
TBR8(24) TRE

(33)

(30)
(31)(28)(29)(26)(27)

TBR1TRANSMITTER BUFFER REGISTER(22) TBRE †PARITY
LOGIC

STOP(23) TBRLTRANSMITTER REGISTER

TRANSMITTERTIMING AND
CONTROL(40) TRCSTART

MULTIPLEXER(25) TRO(38) CLS1(37) CLS2(34) CRL(21) MR(36) SBS(16) SFD(39) EPE(35) PI

CONTROLREGISTER(20) RRI(17) RRC

MULTIPLEXERRECEIVER
TIMING AND
CONTROL(18) DRR

STOP
LOGIC

(19) DR †STARTLOGICRECEIVER REGISTERPARITY
LOGIC

RECEIVER BUFFER REGISTER
3-STATE(16) SFD(4) RRDBUFFERS† RBR8† THESE OUTPUTS ARE
THREE-STATE

† OE
(15)

† FE
(14)

† PE
(13)

† RBR1(5) (6) (7) (8) (9) (10) (11) (12)Control Definition
CONTROL WORD

CHARACTER FORMAT

CLS 2

CLS 1PIEPE

SBSSTART BITDATA BITS

PARITY BIT

0000015ODD

10000115ODD

1.50001015EVEN

10001115

EVEN

1.5001

X

015NONE

1001X

115NONE

1.50100016

ODD

10100116ODD

20101016EVEN10101116EVEN

2011X016NONE

1011x116NONE

21000017ODD

11000117ODD

21001017EVEN

11001117EVEN

2101X

017NONE

1101x117NONE

21100018ODD

11100118ODD

2

110

1018

EVEN

11101118

EVEN

2111X

018NONE

1111x118NONE

25-2

STOP BITS

HD-6402
Pin Description
PIN TYPE SYMBOLPIN TYPE SYMBOLDESCRIPTION

1VCC †

Positive Voltage Supply

2NC

No Connection

3GNDGround

DESCRIPTION22OTBREA high level on TRANSMITTER BUFFER REGISTER EMPTY indicates the transmitter buffer registerhas transferred its data to the transmitter registerand is ready for new data.

23

I

TBRL

A low level on TRANSMITTER BUFFER REGISTER LOAD transfers data from inputs TBR1TBR8 into the transmitter buffer register. A low tohigh transition on TBRL initiates data transfer tothe transmitter register. If busy, transfer is automatically delayed so that the two characters aretransmitted end to end.

24OTREA high level on TRANSMITTER REGISTER EMPTY indicates completed transmission of a character including stop bits.

25

OTRO

Character data, start data and stop bits appear serially at the TRANSMITTER REGISTER OUTPUT.

26

I

TRB1

Character data is loaded into the TRANSMITTERBUFFER REGISTER via inputs TBR1-TBR8. For
character formats less than 8 bits the TBR8, 7 and
6 inputs are ignored corresponding to their programmed word length.

4I

RRD

A high level on RECEIVER REGISTER DISABLE
forces the receiver holding out-puts RBR1-RBR8
to high impedance state.

5ORBR8The contents of the RECEIVER BUFFER REGISTER appear on these three-state outputs. Word formats less than 8 characters are right justified toRBR1.

6O

RBR7

See Pin 5-RBR87O

RBR6

See Pin 5-RBR88O

RBR5

See Pin 5-RBR89O

RBR4

See Pin 5-RBR810O

RBR3

See Pin 5-RBR811O

RBR2

See Pin 5-RBR812O

RBR1

See Pin 5-RBR813OPEA high level on PARITY ERROR indicates receivedparity does not match parity programmed by control
bits. When parity is inhibited this output is low.

27

ITBR2

See Pin 26-TBR1.

28

I

TBR3

See Pin 26-TBR1.

A high level on FRAMING ERROR indicates thefirst stop bit was invalid.

29

I

TBR4

See Pin 26-TBR1.

30

I

TBR5

See Pin 26-TBR1.

31

I

TBR6

See Pin 26-TBR1.

32

I

TBR7

See Pin 26-TBR1.

33

I

TBR8

See Pin 26-TBR1.

34

ICRL

A high level on CONTROL REGISTER LOAD
loads the control register with the control word. The
control word is latched on the falling edge of CRL.
CRL may be tied high.

35

I

PI

A high level on PARITY INHIBIT inhibits parity generation, parity checking and forces PE output low.

36

ISBS

A high level on STOP BIT SELECT selects 1.5stop bits for 5 character format and 2 stop bits forother lengths.

37

I

CLS2

These inputs program the CHARACTERLENGTH SELECTED (CLS1 low CLS2 low 5 bits)(CLS1 high CLS2 low 6 bits) (CLS1 low CLS2high 7 bits) (CLS1 high CLS2 high 8 bits.)

38

I

CLS1See Pin 37-CLS2.

39

I

EPE

When PI is low, a high level on EVEN PARITY
ENABLE generates and checks even parity. A lowlevel selects odd parity.

40

ITRC

The TRANSMITTER REGISTER CLOCK is 16X
the transmit data rate.

1415OOFE
OE

A high level on OVERRUN ERROR indicates thedata received flag was not cleared before the last
character was transferred to the receiver bufferregister.

16I

SFD

A high level on STATUS FLAGS DISABLE forces
the outputs PE, FE, OE, DR, TBRE to a high impedance state.

17IRRCThe Receiver register clock is 16X the receiverdata rate.

18IDRRA low level on DATA RECEIVED RESET clears
the data received output DR to a low level.

19

O

DRA high level on DATA RECEIVED indicates acharacter has been received and transferred tothe receiver buffer register.

20

I

RRI

Serial data on RECEIVER REGISTER INPUT isclocked into the receiver register.

21

I

MR

A high level on MASTER RESET clears PE, FE,
OE and DR to a low level and sets the transmitter
register empty (TRE) to a high level 18 clock cycles
after MR falling edge. MR does not clear the receiver buffer register. This input must be pulsed at least
once after power up. The HD-6402 must be master
reset after power up. The reset pulse should meet
VIH and tMR. Wait 18 clock cycles after the fallingedge of MR before beginning operation.

† A 0.1µF decoupling capacitor from the VCC pin to the GND is recommended.

98

7

6

5

4

3

2

1

32

33

34

35

36

37

38

39

40

10

11

12

13

14

15

16

17

18

19

20

HD-6402

31

30

29

28

27

26

25

24

23

22

21

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HD-6402
Transmitter Operation
The transmitter section accepts parallel data, formats the dataand transmits the data in serial form on the Transmitter Register Output (TRO) terminal (See serial data format). Data isloaded from the inputs TBR1-TBR8 into the Transmitter Buffer
Register by applying a logic low on the Transmitter Buffer
Register Load (TBRL) input (A). Valid data must be present atleast tset prior to and thold following the rising edge of TBRL. If
words less than 8 bits are used, only the least significant bits
are transmitted. The character is right justified, so the leastsignificant bit corresponds to TBR1 (B).

The rising edge of TBRL clears Transmitter Buffer Register
Empty (TBRE). 0 to 1 Clock cycles later, data is transferredto the transmitter register, the Transmitter Register Empty(TRE) pin goes to a low state, TBRE is set high and serial
data information is transmitted. The output data is clocked byTransmitter Register Clock (TRC) at a clock rate 16 times thedata rate. A second low level pulse on TBRL loads data into
the Transmitter Buffer Register (C). Data transfer to thetransmitter register is delayed until transmission of the current data is complete (D). Data is automatically transferred tothe transmitter register and transmission of that character
begins one clock cycle later.

1TBRL
TBRE
1/2 CLOCK

0 TO 1 CLOCKTREDATATROABCEND OF LAST STOP BITDFIGURE 1. TRANSMITTER TIMING (NOT TO SCALE)

Receiver Operation
Data is received in serial form at the Receiver Register Input(RRI). When no data is being received, RRI must remainhigh. The data is clocked through the Receiver Register
Clock (RRC). The clock rate is 16 times the data rate. A lowlevel on Data Received Reset (DRR) clears the Data
Receiver (DR) line (A). During the first stop bit data is transferred from the Receiver Register to the Receiver Buffer
Register (RBR) (B). If the word is less than 8 bits, theunused most significant bits will be a logic low. The output

character is right justified to the least significant bit RBR1. Alogic high on Overrun Error (OE) indicates overruns. Anoverrun occurs when DR has not been cleared before thepresent character was transferred to the RBR. One clock
cycle later DR is reset to a logic high, and Framing Error(FE) is evaluated (C). A logic high on FE indicates an invalid
stop bit was received, a framing error. A logic high on ParityError (PE) indicates a parity error.

BEGINNING OF FIRST STOP BITRRI
7 1/2 CLOCK CYCLES
RBR1-8, OE, PE
DRRDRFE
1 CLOCK CYCLEA

BCFIGURE 2. RECEIVER TIMING (NOT TO SCALE)

START BIT

1, 11/2 OR 2 STOP BITS

5-8 DATA BITS

LSBMSB†PARITYFIGURE 3. SERIAL DATA FORMAT

5-4† IF ENABLED

HD-6402
Start Bit Detection
The receiver uses a 16X clock timing. The start bit could haveoccurred as much as one clock cycle before it was detected,
as indicated by the shaded portion (A). The center of the start
bit is defined as clock count 7 1/2. If the receiver clock is asymmetrical square wave, the center of the start bit will belocated within ±1/2 clock cycle, ±1/32 bit or 3.125% giving a
receiver margin of 46.875%. The receiver begins searchingfor the next start bit at the center of the first stop bit.

CLOCK
COUNT 71/2 DEFINEDCENTER OF START BIT

STARTARRI INPUT

71/2 CLOCK CYCLES
81/2 CLOCK CYCLESFIGURE 4.

Interfacing with the HD-6402

RECEIVER
RB1

TRANSMITTER
TBR1
TBR8

TRO

RS232
DRIVER

RS232
RECEIVERRRI

DIGITALSYSTEM

HD-6402

HD-6402

CONTROL

CONTROL
RB1RB8CONTROLCONTROL

RRI

RS232
RECEIVER

RS232
DRIVER

TRO

TBR1

TBR8
TRANSMITTER

RB8RECEIVER

FIGURE 5. TYPICAL SERIAL DATA LINK

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DIGITALSYSTEMHD-6402
Absolute Maximum Ratings

Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage Applied. . . . . GND -0.5V to VCC +0.5V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Typical Derating Factor . . . . . . . . . . . . 1mA/MHz Increase in ICCOP

Thermal Resistance (Typical)
θJA
θJC
CERDIP Package . . . . . . . . . . . . . . . . 50oC/W
12oC/W
PDIP Package . . . . . . . . . . . . . . . . . . . 50oC/W
N/A
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationof the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range
HD-6402R-9, HD6402B-9 . . . . . . . . . . . . . . . . . . .-40oC to +85oC

DC Electrical Specifications VCC = 5.0V ± 10%, TA = -40oC to +85oC (HD-6402R-9, HD-6402B-9)
LIMITS
SYMBOLPARAMETERMINMAXUNITSCONDITIONS

VIH

Logical ‘‘1’’ Input Voltage

2.0-

V

VCC = 5.5V

VIL

Logical ‘‘0’’ Input Voltage

-0.8

V

VCC = 4.5V

IIInput Leakage Current-1.01.0µA

VIN = GND or VCC, VCC = 5.5V

VOH

Logical ‘‘1’’ Output Voltage

3.0
VCC -0.4-V

IOH = -2.5mA, VCC = 4.5V
IOH = -100µA

VOL

Logical ‘‘0’’ Output Voltage

-0.4

V

IOL = +2.5mA, VCC = 4.5V

IO

Output Leakage Current

-1.0

1.0µA

VO = GND or VCC, VCC = 5.5V

ICCSBStandby Supply Current-100µA

VIN = GND or VCC; VCC = 5.5V,
Output Open

ICCOP

Operating Supply Current (See Note)-2.0mA

VCC = 5.5V, Clock Freq. = 2MHz,
VIN = VCC or GND, Outputs OpenNOTE: Guaranteed, but not 100% tested

Capacitance TA = +25oC
LIMIT
PARAMETERSYMBOL

CONDITIONSTYPICAL

UNITS

Input Capacitance

CIN

Freq. = 1MHz, all measurements are referenced to device GND

25pF

Output Capacitance

COUT

25pF

AC Electrical Specifications VCC = 5.0V ± 10%, TA = -40oC to +85oC (HD-6402R-9, HD6402B-9)
LIMITS HD-6402R
SYMBOLPARAMETER

LIMITS HD-6402B

MINMAXMINMAXUNITS

CONDITIONS
CL = 50pF
See Switching Waveform(1) fCLOCK

Clock Frequency

D.C.

2.0

D.C.

8.0

MHz

(2) tPW

Pulse Widths, CRL, DRR, TBRL

150-75-ns(3) tMR

Pulse Width MR

150-150-ns(4) tSET

Input Data Setup Time50-

20-ns(5) tHOLD

Input Data Hold Time60-20-ns(6) tEN

Output Enable Time-160-35ns5-6

HD-6402
Switching Waveforms

CLS1, CLS2, SBS, PI, EPETBR1 - TBR8VALID DATA

SFD
RRD

VALID DATATBRLSTATUS OR
RBR1 - RBR8CRL
(4)
tSET
tPW
(2)

tHOLD
(5)

(4)
tSET

tHOLD
(5)

tEN
(6)

tPW
(2)

FIGURE 6. DATA INPUT CYCLE

FIGURE 7. CONTROL REGISTER LOADCYCLE

FIGURE 8. STATUS FLAG OUTPUTENABLE TIME OR DATA OUTPUT ENABLE TIME

A.C. Testing Input, Output WaveformINPUT

OUTPUT

VIH + 20% VIH

VOH
1.5V

1.5V

VIL - 50% VIL

VOL

FIGURE 9.
NOTE: A.C. Testing: All input signals must switch between VIL - 50% VIL and VIH + 20% VIH. Input rise and fall times are driven at 1ns/V.

Test CircuitOUTCL(SEE NOTE)FIGURE 10.
NOTE: Includes stray and jig capacitance, CL = 50pF.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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