Galvanic Isolation System for Multiple Gate Drivers
with Inductive Power Transfer—Drive of Three-phase inverter—

Keisuke Kusaka, Masakazu Kato

Koji Orikawa, Jun-ichi Itoh

Dept. of Energy and Environment Science
Nagaoka University of Technology
Nagaoka, Niigata, Japan
kusaka@stn.nagaokaut.ac.jp,
katom@stn.nagaokaut.ac.jp

Dept. of Science of Technology Innovation
Nagaoka University of Technology
Nagaoka, Niigata, Japanorikawa@vos.nagaokaut.ac.jp,
itoh@vos.nagaokaut.ac.jp

Abstract—Medium-voltage motor drive systems, mediumvoltage inverters, which have an input voltage and an output
voltage of 3.3 kV or 6.6 kV, are widely used in industry
applications. In the medium-voltage inverter, robust galvanic
isolation among a control circuit and each gate drive supplies isrequired in order to drive high-voltage switching devices. In
present, a transformer, which is designed to satisfy the safety
standards, provides galvanic isolation. However, transformers
prevent cost reduction of the isolation system. In this paper, thegalvanic isolation system using only printed circuit boards areproposed. Moreover, a three-phase inverter is driven using theisolation system in order to confirm the utility of the isolation
system. The proposed system transmits power from thetransmitting board to six receiving boards using eachtransmitting coils made on the printed circuit boards. The air
gap among the printed circuit boards assumes galvanic isolation.
From the experimental results, it is confirmed that the threephase inverter can be driven by the proposed galvanic isolation
system.
Keywords—inductive power transfer; wireless power transfer;gate driver; mediium-voltage inverter

I. INTRODUCTION
Medium-voltage motors, which have a rated voltage of 3.3
kV or 6.6 kV, are widely used for high-power applications suchas fans and blowers in industry [1]. For medium-voltage
motors, a system voltage of a three-phase medium voltage
inverter has also risen to 3.3 kV or 6.6 kV [1-4]. In suchmedium-voltage inverter, robust galvanic isolation is required
among a control circuit and each gate driver supply. The
standards of galvanic isolation for adjustable speed electrical
power drive systems [5], which are published by theInternational Electrotechnical Commission (IEC), are wellknown safety regulations. When the working voltage of theinverter is 8.0 kV, the safety standards require a minimum
clearance of 14 mm and a creepage distance of 81 mm withfollowing conditions; comparative tracking index (CTI) is 100
CTI < 400 with a pollution degree of 2 [5].

978-1-4673-7151-3/15/$31.00 ©2015 IEEE

Isamu Hasegawa, Kazunori Morita,
Takeshi Kondo
Research & Development Group
MEIDENSHA CORPORATION
Numazu, Shizuoka, Japan

In the conventional system, galvanic isolation is achieved
by isolation transformers with cores. However, they tend todrive up cost of the isolation system because severe
malfunction in the medium-voltage system has to be avoided.
Moreover, the transformers are typically heavy and bulky inorder to obtain the high-voltage isolation. For example, thetypical dimensions of the isolation transformer, which has an
isolation voltage of 20 kVrms for 10 s, are 200 mm × 200 mm ×
200 mm at a weight of approximately 5.5 kg [6]. Thesetransformers are required at each the gate driver supplies. Thus,
the downsizing and cost reduction of the galvanic isolation
system have been difficult to achieve.
In order to achieve cost reduction and downsizing of theisolation system for power converters, a single-chip DCisolated gate drive integrated circuit (IC) has been proposed [79]. It supplies power using a microwave from the bottom layerof a sapphire substrate to the top layer. A transmission
frequency of the system is 5 GHz. The galvanic isolation isassumed by sapphire substrates. Thus, it achieves thedownsizing of the isolation. However, the safety standards on acreepage distance are not satisfied. It means that it cannot be
used for the medium-voltage inverter.
In [10-12], optical isolation method using optical fibers
have been proposed. Gate signal and power is supplied throughthe optical fiber. However, the transmitted power is limited up
to 100 mW per one fiber. The power is not sufficient to drive agate drive circuit and auxiliary circuit such as a protection
circuit of switching devices. Furthermore, if optical fibers arerepeatedly bent, it increases the risk of disconnection of wire.
Meanwhile, an isolation system using printed circuit boards(PCBs) has been proposed by J. W. Kolar et al [6]. The poweris supplied from the coil mounted on a transmitting board to
the coil mounted on a receiving board. It is similar principle ofa coreless transformer [13]. However, one transmitting sidetransmits power to only one receiving side as one-by-one (1×1)
in this system. Many pairs of the transmitting board and thereceiving board are required at each of gate driver supplies.

Galvanic isolation Receiving boards#1
vdc1
Transmitting board
C1#0
Medium-voltage inverter
vin1
L0

C0
vinv
24V

#2

fsw = 2 MHz

6.6 kVGate
driver#3#6
Inductive power transfer

Fig. 1. Concept of galvanic isolation system.

Receiving boards

0

10

25

300 mm

15

#1

#2

#3

50

First, the system configuration of the proposed isolation
system is described from next chapter. Then, the design
method of the resonance capacitors for multiple receiversystem is mathematically clarified. Thirdly, the fundamental
characteristics of the proposed system with a resistance load
are provided. Finally, a three-phase inverter is driven with theproposed system in order to confirm the utility of the proposedsystem.

Proposed galvanic isolation system····

In this paper, the galvanic isolation system, which isconstructed by only PCBs, is proposed. Then, the three-phase
inverter with the proposed isolation system is experimentallytested in order to confirm the utility of the isolation system.
The isolation system transmits power from one transmittingboard to six receiving boards (1 × 6) beyond an air gap of 50
mm by inductive power transfer. The isolation system
contributes cost reduction of the isolation system. Besides, theisolation with the air gap of 50 mm easily satisfies the standardof the clearance and a creepage distance when the system
voltage of the inverter is 6.6 kV. Moreover, the air gap of 50
mm decreases common-mode current, which is induced byhigh-dv/dt switching of the medium voltage inverter. Thiseffectively increases the reliability because common-mode
current may cause malfunctions in the gate drive circuit and thecontrol circuit [14].

Figure 2 shows the schematic view of the propose isolation
system. The overall size is 300 × 150 × 150 mm. The
transmitting board and the receiving boards are placed in the
chassis made from acrylic. Distance between each thereceiving boards and the transmitting board is kept at 50 mm
for galvanic isolation. This air gap meets definition of thecreepage distance and the clearance. The galvanic isolation tosatisfy the safety standards is achieved by the air gap. The air
gap is wide enough to fulfill the safety standards of the IEC [5]when the system voltage of a medium-voltage inverter is 6.6

15

Transmitting board

#0

150

#4

90

A. System Configuration
Figure 1 shows the concept of the proposed galvanic
isolation system. The proposed system consists of the seven
PCBs; one transmitting board and six receiving boards, andchassis made from acrylic. The transmitting board is connectedto the auxiliary power supply of 24 V in the medium-voltage
inverter. On the other hand, the receiving boards are connectedto the gate drivers. The transmitting boards supply power to thesix receiving boards with the inductive power transfer beyond
the air gap. Power factor from the view point of the power
supply decreases with decreasing magnetic coupling between
the transmitting board and the receiving boards. In order tocancel out the reactance of the leakage inductance, resonancecapacitors are inserted into the transmitting coil and thereceiving coils in series. This technique is commonly used in
the inductive power transfer system. In particular, a techniquefor inserting capacitors in series into both a transmitting coiland a receiving coil is known as the “S/S compensation” [1518]. Using the S/S compensation, the power is effectivelytransmitted by the inductive power transfer even at weakmagnetic coupling.

0

II. PROPOSED GALVANIC ISOLATION SYSTEM

50

#5
50

#6
50
Unit: [mm]Fig. 2. Schematic view of proposed isolation system.

kV. Note that this 50-mm an air gap is designed with asufficient margin.
Furthermore, this configuration is effective to improve thereliability. A malfunction may be caused by the leakage current,
which is induced by high dv/dt switching of switching devices[14]. The proposed isolation system reduces the parasitic
capacitances between the transmitting board and the receiving
boards. The leakage current, which flows to the controller ofthe medium-voltage inverter, will be suppressed. The parasitic
capacitances between the transmitting board and the receiving
boards are corresponded to parasitic capacitances between a
primary winding in a transformer.
Figure 3 and 4 show the schematics of the transmittingboard and the receiving board, respectively. The transmittingboard #0 consists of a high-frequency inverter, a series
resonance capacitor, and a transmitting coil. The inverter isoperated by a square wave operation with an output frequencyof 2 MHz. On the other hand, the receiving boards #1–6 consistof receiving coils, series resonance capacitors, the diode bridge
rectifiers. As the diodes, silicon-carbide (SiC) schottky barrier
diodes are used for high-frequency operation. The thickness ofthe copper film and PCB for both boards is 175 m and 1.6

300
245
231





PG  f c  Qg   Qg   VGE   VGE  From eq. (1), the power consumption of each gate drive
circuit is calculated as about 240 mW where the switchingfrequency of the medium voltage inverter is 4 kHz, total gatecharges ±Qg are ±1000 nC and the gate-emitter voltage is ±15
V. Note that the values, which is used in this calculation, aretypical value of IGBT (VCE = 1700 V, IC = 150A). Considering
power loss in a gate driver circuit and power consumption
except the gate resistance, the power of at least 1 W is required
per one receiving board as the output power of the isolation
system.
C. Evaluation of Parasitic Capacitance
The parasitic capacitance between the transmitting board
and the receiving boards is evaluated. The parasitic
capacitances between the transmitting board and the receiving
boards should be suppressed because parasitic capacitances
reduce the isolation performance. The parasitic capacitancesamong the boards correspond to the capacitance between a
primary winding and a secondary winding in the conventional
isolation transformer. In particular, considering a use of SiCMOSFETs for a medium-voltage inverter, suppression of theparasitic capacitance is strongly required. The reason is that
SiC-MOSFET will improve the switching speed due to its highelectronic mobility [19]. However, the large common-mode
current is induced by high dv/dt. In order to prevent themedium-voltage inverter from malfunction, the common-mode
current has to be suppressed.
The parasitic capacitance is calculated using simplified
model. It is difficult to calculate the exact parasitic capacitancebecause the shapes of the conductors on the transmitting board
and the receiving boards are complicated. The parasitic
capacitance is evaluated in the worst-case assumptions. The
space between the transmitting board and the receiving boards
is assumed as a parallel-plate capacitor. The capacitance of aparallel plate capacitor with air is calculated by (2), where air

150

43.5

29.5

1.0
1.0

150

Unit: [mm]InverterFig. 3. Schematics of transmitting board. (Top view)
50
45
30

29.25



Capacitors
C0
InverterGate drive
circuits

Control
circuit45.25

Figure 5 shows the five-level diode-clamped multilevel
inverter as the medium voltage inverter, which has a rated
output voltage of 6.6 kV and a rated output power of 1 MVA[2]. Each switching device is a string of three 1.7-kV IGBTs
connected in series. The power consumption of a gate
resistance PG of an IGBT is calculated by (1) where fc is acarrier frequency, Qg is total gate charge and VGE are gateemitter voltage of IGBT.

R10

R10

90

B. Required Rated Power of Gate Driver Supplies
The isolation system transmits the power consumption for
the gate drivers. In this subsection, the required power of theeach gate driver is estimated.

18.6

mm, respectively. Besides, the capacitors are inserted to thecoils in series to cancel out the reactance from the view pointof the power supply. This technique is well-known as seriesseries compensation (S/S) in research field of wireless powertransfer. The resonance conditions are described below.

0.5
0.5

Capacitors

Rectifier

RectifierUnit: [mm]Fig. 4. Schematic of receiving board. (Top view)
Five-level PWM rectifier

6.6kV

PWM inverter

6.6kV
M

Fig. 5. Configuration example of 6.6-kV, 1-MVA five-level diodeclamped medium voltage inverter.

is the permittivity of air, S is the area of the parallel plate, and dis the distance between the boards.

I0

L0(1-∑kn0)

N0:N1-6n=1, 2, ∙∙∙, 6

r0

C0

L0k10

L1 

k10 L0
a2

r1 C1

I1

V1 Receiving board
#1

L2 

k 20 L0
a2

r2 C2

I2

V2

#2

k L
L3  30 2 0
a

r3 C3

I3

V3

#3

k 40 L0
a2

r4 C4

I4

V4

#4

k L
L5  50 2 0
a

r5 C5

I5

V5

#5

k60 L0
a2

r6 C6

I6

V6

#6

k10



S
C   air 
d



L0k20
k20

Let S be 90 mm × 50 mm and d be 50 mm as thedimensions of the system; then, the parasitic capacitance C of
the isolation system is below 0.80 pF for the worst-caseassumptions. This shows that the proposed isolation systemdecreases the parasitic capacitance in comparison with theconventional isolation systems with a transformer [20-21].

V0

Transmitting
board
#0

k40
L0k50
k50
L6 

B. Evaluation fo the Equivalent Circuit
In order to evaluate the validity of the equivalent circuit, theF-matrix of the frequency characteristic (which is defined by
Eq. (2)) analyzed by 3-D electromagnetic analysis (Agilent,
Momentum) is compared with the F-matrix calculated by theequivalent circuit. The F-matrix shows the relationship of asystem between the input port #i and output port #j based on
voltage and current. The suffixes I and j indicate the number ofPCBs( i, j = 0, 1, ∙∙∙, 6). For simplicity, the F-parameter fromone board #i to another board #j is indicated as F(i, j).



Figure 7 shows the definitions of the F-parameters in the
proposed system. In this evaluation, only the characteristics ofthe coils are evaluated. Thus, the resonance capacitors areomitted because the evaluation of the equivalent circuit of thetransmission coils is the main purpose of this section.

Fig. 6. Equivalent circuit of proposed isolation system.
Receiving board
Transmitting board F(1,0)#0F(0,1)

Coil

Figure 6 shows the equivalent circuit of the proposed
isolation system without converters where L0–6 are the selfinductances of each coil, kij is the coupling coefficient between
boards #i and #j, N0–6 are the numbers of turns, r0–6 are theequivalent series resistances, and a is the turn ratio defined as
N1–6 / N0.

k60
Ideal transformer

F(1,1)50W#1
F(1,2)

F(2,1)
F(2,0)
F(0,0)50W

Coil

A. Derivation of Equivalnet Circuit
The equivalent circuit with multiple receiving coils isprovided in [22]. The equivalent circuit of the proposed system
is derived by changing the equivalent circuit in [22]. In [22],the magnetic coupling among the receiving coils is assumed.
However, the magnetic coupling among the receiving coils canbe ignored in the proposed system due to the positional
relationship of the receiving boards.

Bij Vj   
Dij  I j 

L4 

L0k60

The design of resonance capacitors are discussed in thissection. First, an equivalent circuit of the proposed isolation
system is introduced. Then the validity of the equivalent circuit
model is clarified by a comparison of the F-matrix between theequivalent circuit model and a 3-D electromagnetic analysis.

V   A
Vi    Fi, j  j    ij I 
 I j   Cij
 i
  

k30
L0k40

III. DESIGN OF RESONANCE CAPACITORS



L0k30

F(0,2)#2

F(0,3)#3

F(3,0)

F(4,0)
F(0,4)
F(5,0)#4#5

F(0,5)
F(6,0)
F(0,6)#6

Fig. 7. Definition of F-parameters.

The ideal power supply with resistances of 50 Wfor the
inner impedance is connected instead of the converters. The
inner impedance is necessary because the F-parameters arecalculated from the analysis results of scattering parameters (Sparameters) by a simulator.
Figure 8 shows each of the F-parameters between thetransmitting board and receiving board #1. The solid line
shows the F-parameter analyzed from 3-D electromagnetic
analysis. The dashed-dotted line shows the F-parameter
calculated from the equivalent circuit. The dotted line shows
the F-parameter calculated from the equivalent circuit withcorrection coefficients, which are mentioned later. The Fparameter with the 3-D electromagnetic analysis has a selfresonance at a frequency of approximately 7 MHz. However,
the equivalent circuit model does not consider self-resonancebecause the self-resonance frequency is far from the operating
frequency. This is one of the reasons for the error between 3
MHz and 10 MHz.
Moreover, the F-parameter with the equivalent circuit hasoffsets of approximately 10 dB between 100 kHz and 3 MHz.
The reason for the error is the difference between the numbersof the actual windings and effective windings. This means thata portion of the windings is not effective to induce the voltage.
This is a specific problem when a transmitting coil is placed on
PCBs. The difference can be corrected using a correction
coefficient a. The corrected turn-ratio a´ of the transformer isrepresented as Eq. (4) using the correction coefficient a. The
dotted line shows the F-parameter with the equivalent circuit
considering the correction coefficient in Fig. 8. The correction
coefficients, which are derived by trial and error, are a1–6 =2.26, 2.28, 2.27, 2.26, 2.28, and 2.27, respectively, in the
prototype. The difference in the correction coefficients iscaused by the difference in the positions of the receiving
boards. The correction coefficients are necessary in a timedomain analysis in order to exactly analyze the circuit
performance.

C16  Lle 16  Lm16 



N1

N2

TABLE I.





VDC

24

V

Switching frequency

fsw

2.00

MHz

Transmitting coil

L0

20.3

H

Receiving coils

L1-6

14.8

H

Transmitting coil

R0

790

mW

Receiving coils

R1-6

690

mW

Transmitting board #0

C0

310

pF

Receiving boards #1-6

C1-6

430

pF

Receiving board #1

k01

0.017

Receiving board #2

k02

0.025

Receiving board #3

k03

0.018

Receiving board #4

k04

0.017

Receiving board #5

k05

0.025

Receiving board #6

k06

0.017






1 
1 
r   R   j  Lle 1  Lm1   r0  j  Lle 0  6Lm1 C 0  1
C1  





1 

6 2 L2m r1  R   j  Lle 1  Lm1 
C1 


120

3-D model (Agilent momentum)
Equivalent circuit without correction coefficient a
Equivalent circuit with correction coefficient a

80

B10

40

A10
D10

0

C10

-40
Self resonance

-80
0.1
6



Coupling coefficients(between the receiving
coils and transmitting
coil)

F-parameters [dB]


V 
1 
 
Iinv  inv r1  R1   j Lle 1  Lm1 


 

C
1 





SPECIFICATIONS OF PROTOTYPE

Equivalent
series resistances

The F-parameter of the equivalent circuit considering thecorrection coefficient shows agreement with one of theelectromagnetic analyses between 100 kHz and 3 MHz.

61
 L16 
2

Input voltage (DC)capacitances

C. Design of Resonance Capacitors
Figure 9 shows the equivalent circuit of the proposedsystem with the converters. In the following calculation, therectifiers are assumed as load resistances R1–6. The resonancecapacitors should be designed to cancel out the reactanceowing to the leakage inductance [18]. From the equivalentcircuit, the output current of the inverter is expressed as Eq. (5)using  expressed as (6) when all of the parameters on thereceiving boards and the coupling coefficients are the same.
The prime parameters are the parameters referred to theprimary side.

The equations show that the resonance capacitors should beresonated with each self-inductance.

Self-inducancesa  a

1

2

1

10

Frequency f [MHz]Fig. 8. F-matrix between transmitting board #0 and receiving board #1.

5

Gate drivers for high-frequency inverter
Receiving board #1

Rectifier

#2

#3

#5

#6

In order to correct the load power factor, reactance of the eq.
(5) has to be zero. Thus, the resonance conditions are derived
as (5) and (6) where  = 2f is the output angular frequency.
From Eq. (5) and (6), the resonance conditions are provided
as Eq. (7) and Eq. (8).

Transmitting board #0

#4



C0 

1
1

 2 Lle0  Lm1  Lm 2    Lm 6   2 L0 Transmitting coilHigh-frequency Inverter

Fig. 9. Prototype of isolation system.

Receiving coilIV. EXPERIMENTAL VERIFICATIONSInverter output voltage vinv [50V/div]

A. System setup of the prototype
Figure 9 shows the photograph of the prototype. The
transmitting board, which is shown in Fig. 3, and the receiving
boards, which are shown in Fig. 4, are placed as shown in Fig.
2. The chassis is made from acrylic except for clinchers
because eddy current losses should be suppressed.

0

Table I shows the specifications of the prototype. The
laminated ceramic capacitors for resonance are selected tosatisfy the resonance conditions shown as (7) and (8). Note thatthe coupling coefficients between the boards are simulated
values because it is difficult to measure the accurate coupling
coefficient in experiment.

0

C. Efficiency Characteristic
Figure 11 shows the measured total efficiency of the
proposed system. The total efficiency is defined by Eq. (9),where Pin is the input DC power of the isolation system. The
total efficiency is the ratio of the input power and the sum of
the output power for all of the receiving boards. Note that thesame resistance loads are connected to all of the receiving
boards as a load.

h Poutn n 1, 2 , , 6

Pin0
Input voltage of rectifier vin2 #2 [10V/div]

Output voltage of receiving board vdc1 #1 [5V/div]

0200[ns/div]

Fig. 10. Operation waveforms of proposed system with resistance loads
of 38 W.
(n = 1, 2, ∙∙∙, 6)

50
Efficiency h [%]B. Fundamental Characteristics
Figure 10 shows the operation waveforms of the proposed
isolation system. Note that the resistances of 38 W areconnected at the outputs of the system instead of the gate
drivers for simplicity. The inverter is operated at a frequency of
2 MHz. The DC voltages are obtained as the outputs ofreceiving board #1. The other boards obtained DC voltages,
similarly.

Input voltage of rectifier vin1 #1 [10V/div]40
R = 45 W

30
20
10

R=0W

0

5

10

15

20

25

Poutn [W]
Total output powern1
, 2,, 6

Fig. 11. Efficiency characteristic.

 100 

6
Receiving board #5

The maximum efficiency is 46.9% at an output power of
16.6 W. In the isolation system for a medium-voltage inverter,
low efficiency can be acceptable because the power loss in theisolation system is considerably smaller than the rated power ofa medium-voltage inverter (i.e., 1 MW). Thus, the isolation
system is designed to give priority to the isolation performanceover the efficiency.
D. Output Power and Output Voltage Characteristic
Figure 12 represents the relationship between the output
voltage and the output power. In the proposed system, theoutput voltage is determined by the output power. Thus, DCDC converters for voltage regulation have to be connected into
the subsequent stage of the system. It means that, input voltage
range of the DC-DC converter provides a lower limit and an
upper limit of the output power. In the following experiments,
the DC-DC converters, which have an input voltage range from
4.5 V to 18 V, are used. Thus, it is found that the output powerof the receiving boards #3 have to be larger than 1.4 W.
Moreover, the output power of the receiving boards #2 have to

Output power Pout(n) [W](n = 1, 2, ∙∙∙, 6)

5
#2

4
3
2

#6

Pmin5

#1
Pmin3

#4

#3

1
0

Vmin
4.5 5

10

15

Output voltage Vout(n) [V](n = 1, 2, ∙∙∙, 6)

Fig. 12. Output power v.s. Output voltage on each board.

be larger than 2.6 W. The difference among the boards iscaused by the difference of the coupling coefficient. In view ofusing the same receiving boards, the difference in the coupling
coefficient should be small.

E. Drive of Three-phase Inverter
Figure 13 shows the system configuration for a drive test ofa three-phase inverter. A three-phase inverter is driven by thegate drive circuits with proposed isolation system. The
proposed system is designed with assuming to be used in a
diode-clamped five-level inverter. However, two-level inverter,

C1

High-frequency inverter output voltage vinv [50V/div]

0

vDC1

Input voltage of rectifier vin1 #1 [10V/div]

S1 S 3

0

#2

L0

+

C0

The transmitted power is supplied to the gate driver circuit
through the DC-DC converter, which assumes the voltage

200V
50 Hz

Receiving boards#1
Transmitting board#0which has a rated voltage of 200 V, is used for simplicity. The
inverter DC voltage is 283 V, a carrier frequency is 10 kHz,and an output frequency is 43 Hz.

Output voltage of three-phase inverter vuv [500V/div]

#3

vinv
S2 S 4#4

fsw = 2 MHz

Gatedriver#5

Gatedriver0
Output current of three-phase inverter iu [2A/div]0#6

10[ms/div]

3-phasevuv inverteriu(a) Output voltage and current of three-phase inverter
High-frequency inverter output voltage vinv [50V/div](a) Three-phase inverter with proposed system

0
Input voltage of rectifier #1 [10V/div]

Gate driver+15V

0

Photocoupler

DC

Output voltage of three-phase inverter vuv [500V/div]

0
28W

G1-6

DC

-15V

Output current of three-phase inverter iu [2A/div]
G1-60

Control PWM signal
circuit10[s/div](b) Circuit configuration of gate driver in (a)(b) Zoomed waveforms of (a)Fig. 13. System configuration for experiments with three-phase inverter.
Inverter output voltage vinv [50V/div]

High-frequency inverter output voltage vinv [50V/div]0
Input voltage of rectifier vin1 #1 [10V/div]00Input voltage of rectifier vin1 #1 [25V/div]

Output voltage of three-phase inverter vuv [500V/div]00
Output voltage VDC1 (#1) [10V/div]0

Output current of three-phase inverter iu [2A/div]0Gate-emitter voltage vGE1 (#1) [25V/div]

200[ns/div]

0100[s/div]

Fig. 14. Operation waveforms of gate drivers with proposed system.

(c) Zoomed waveforms of (b)Fig. 15. Operation waveforms of three-phase inverter with proposed
isolation system.

regulation to ±15 V. The resistances of 28 W are connected inparallel to the DC-DC converters in the gate drive circuits forthe protection of the DC-DC converters. Note that thephotocouplers (Toshiba, TLP250) are used in order to drive the
IGBTs in spite of the deficient isolation distance because an
isolation of the PWM signal is not a main topic of this paper.
Figure 14 shows the operation waveforms the gate drivers
with focusing on the gate-emitter voltage of IGBTs. The DC
voltages are obtained on the output of the receiving boards.
Moreover, a gate-emitter voltage of ±15 V is obtained as an
output voltage of the gate drivers.
Figure 15 shows the operation waveforms. Fig. 15 (a)focuses on the operation waveforms of the three-phase inverter.
Fig. 15 (b) focuses on a output voltage of the three-phase
inverter. The switching waveform with PWM is obtained. Fig.
15 (c) shows the output voltage of the high frequency inverter
and input voltage of the receiving board #1. From the
waveforms, it is confirmed that the three-phase inverter isdriven using a proposed isolation system.
V. CONCLUSION
In this paper, a three-phase inverter is driven by the
proposed galvanic isolation system with only printed circuitboards. The proposed system transmits power from thetransmitting board to six receiving boards using coils made by
the printed circuit boards. This contributes to the cost reductionof the isolation system. First, the fundamental characteristic of
the isolation system is experimentally demonstrated. The
maximum efficiency is 46.9% at an output power of 16.6 W.
Then, the two-level inverter, which has a rated voltage of 200
V, is driven using a proposed isolation system. From theseexperiments, it is confirmed that the proposed galvanic
isolation system can be used in a medium-voltage inverter as
an isolation system.
ACKNOWLEDGMENT
This work was supported by Japan Society for the
Promotion of Science (JSPS); Grant-in-Aid for JSPS Fellows(14J10028).
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