NVIDIA RISC-V Story

4th RISC-V Workshop 7/2016

Outlines
Introduce NVIDIA falcon CPU
Why a new CPU?
Introduce NV-RISCVNVIDIA Falcon overview
Securebuscsb

SHA
scp-cmdi/f

CFG
BUS

2ext
CSB

ext
IRQ
to
IRQ
hostICD

pf1
pf2
ifetch
dec
ex
wb

AES
IMEM

DMA

dma toFBIF

DMEM

EMEM IFext membus

PIPE

interru
pts

priv
1
priv

vectored
IRQ

RSA/ECC

csb

int
CSB

Falcon = FAst Logic CONtroller
Introduced over 10 years ago, andused in >15 different hardware
engines today
Design for flexibility
Design for long memory latency
Design for low area
Design for security

FALCONMISC

TMRPICMTHD
CTXSW
ctsw toFBIF

ptimer from
hostmethods fromhostctxsw fromhostWhy Falcon Next Gen?
New use cases requiring more horsepower & feature
Wide addressing range
More performance
Not limit to code size
Rich OS support

Falcon has limits
Small addressing range
Poor performance (0.67DMIPS/Mhz, 1.4Coremark/Mhz)
No D$No rich OS support

Falcon Next Gen – Options
Buy
ARM (A,R family)
Synopsys (ARC family)
MIPSCadence

BuildImprove falconMove to a new ISA (And this is when RISC-V came into the picture..)CPU comparison
Conclusion –RISC-V is the right direction to next generation of ISA
Build our own implementation of RISCV core
Item

Requirement

ARM A53

ARM A9ARM R5

SNPS HS

RISC-V Rocket

Falcon(improved)Core perf>2x falcon

Yes

Yes

Yes

Yes

Yes

No

Area (16ff)<0.1mm^2No

No

Yes

Yes

Yes

Yes

Security

Yes

TZ

TZ

No

No

Yes

Yes

TCM

Yes

Yes

NoYes

Yes

NoYes

L1 I/D $Yes

Yes

Yes

Yes

Yes

Yes

Yes

Addressing

64bit

Yes

NoNoNoYes

No

Extensible ISA

Yes

NoNo

No

Yes

Yes

Yes

Safety(ECC/Parity)

Yes

Yes

Yes

Yes

Yes

Yes

Yes

FunctionalSimulation
modelYes

Yes

NoNoYes

NoYes

Introducing NV-RISCV

Summary: Falcon -> NV RISC-V
FalconNV-RISCV

FalconNV-RISCV

ISA

Falcon-ISA

RISCV-RV64

Address Width

32/24

64

Data width

3264

GPR Num.

1632

Stage

65

Micro-arch

In-order issue
out-of-order exec

In-order issue
out-of-order exec

out-of-order WB (diff regs)

in-order WB

WAW Hazard

Stall

ROBCache

No D cache

I/D configurable

TCM

I/D configurable

I/D configurable

Prediction

staticBTB/BHT/RAS

Load-store

In-orderLoad out-of-order

Memory protection

NoMPU

Address mapping

TCM tagging

Base and boundFalcon Next Gen with RISCV
RISCV plugged-in as 2ndcore
Back compatibility on
interface, easy tointegrate
Isolation between security
and non-security
applications

NV-RISCV Core perf/area
Area data under 16ff
Core (TSMC)

Falcon (Today)

RISCV rocket chip

NV-RISCV

BOOM

Dhrystone (no inline)

0.67

1.72

1.9~2.0

N/A

EEMBC Core Mark

1.4

2.3

~2.5

3.91Core Area(mm2)

0.03

0.055
(no FPU, no L2)

0.05~0.06

N/A

Frequency(GHz)

1.5~1>1.5

N/ACache design to tolerate large latency
Configurable cache size/line size/associativity/write policy
Cache Optimizations
Store Buffer
Write merging
Line-fill Buffer
Victim Buffer
Stream buffer
SW pre-fetch (future)
L2 (future)
Banked cache (future)

I/DTCMD$ perf - btree (8k nodes)
Millions

Total cycles (8k nodes, 64KB D Cache), less is better60

400.00%371.35%350.00%50

300.00%40

250.00%220.53%30200.00%
169.02%150.00%20100.00%
10100.00%
50.00%

00.00%
RISCV

FalconRISV optimized

Total cycles

Total cycles (normalized)

Falcon ideal

RISCV – Area of Interests to NV
Tool chain
Tool for automotive – To meet ISO26262/ASIL-D or SIL3 requirements
Tool for debug – To debug ucode on silicon/FPGA/emulator
Tool for performance tuning – For ucode profiling and tuning
Tool for flexibility – That users can easily customize ISA
Other compiler features – ILP32/LP64

Security
Crypto instruction & extensions

More instructions
Cache instruction – pre-fecth/invalidate/flush…

Conclusion
Falcon is NVIDIA proprietary control processor
New use-cases require more feature and performance from falcon

It is hard to improve the current CPU/ISA to meet all new requirements
We evaluated different options in the market, result showed that RISC-V is overallbest choice as next generation of falcon
We will build a new core from RISC-V ISA

Thank You!