Proceedings of the 11th Annual Meeting of Particle Accelerator Society of Japan
August 9-11, 2014, Aomori, Japan

PASJ2014-SAP110

SOFTWARE UPGRADE OF DSP AND FPGA CONTROLSYSTEMS FOR J-PARC LINAC
Z. Fang, K. Futatsukawa, Y. Fukui, T. Kobayashi, S. Michizono, KEK
F. Sato, S. Shinozaki, E. Chishiro, JAEA
Abstract
For the proton linear accelerator (LINAC) at the Japan
Proton Accelerator Research Complex (J-PARC), the RF
fields at acceleration RF cavities are controlled by an
FPGA (Field-Programmable Gate Array)-based digital
feedback (FB) control system installed in a compact PCI(cPCI). Recently, the software of DSP and FPGA
programs for the low-level RF (LLRF) control systems of
the J-PARC LINAC is upgraded. Firstly, a function of
inspecting cavity pickup and cavity reflection signals is
added to the LLRF control systems so that any of
instabilities could be monitored in real-time, and aninterlock due to larger RF cavity reflection amplitude will
be applied to the fast interlock sysem. Secondly, an
intelligent sag compensation and automatic FPGA
calibration are programmed so that the RF wavforms incase of FB OFF and FB ON can be almost the same.
Furthermore, a new function of separating the chopped
beam automatically to two scrapers is being developed
using FPAG control systems. The details on the software
upgrade of the DSP and FPGA programs will be reported
in this paper.

compact PCI (cPCI) is applied to the low level RF(LLRF) control systems of the J-PARC LINAC. In the972-MHz high-β accelerator section, each klystron feeds
RF power to one ACS (Annular Coupled Structure)cavity. The block diagram of the RF feedback control for
972-MHz RF station is shown in Fig. 1. The compact PCI(cPCI) consists of a CPU (Central Processing Unit), an IO(Input/Output), a DSP (Digital Signal Processor) with
FPGA, a Mixer&IQ (Mixer & IQ-modulator), and an
RF&CLK (Clock) board [3-4].
Circulator
972 MHzKLY

RF input

972-MHz Cavity
RF pickup2

RF pickup1

ATT_drivefRF:
972 MHz

ATT1

IQ
modulator

Q input

fLO:
960 MHzI input

ATT2

ATT4

Mixer

Mixer

Mixer

Mixer

12MHz

12MHz

12MHz

12MHz

ADC2

ADC1
ADC1_I_ref
ADC1_Q_ref
ADC2_I_ref
ADC2_Q_ref

ATT3

ADC3

ADC4
ADC4_limit

I

Q

DAC1

DAC2
FPGA board

INTRODUCTION

ADC4_limit_ILK

The J-PARC LINAC is operated at a repetition rate of
25 Hz with a beam pulse width of 500 μs. After installingthe 972-MHz high-β accelerator section into the J-PARC
LINAC behind the 324-MHz low-β section, the proton
beam energy was successfully upgraded to 400 MeV inJanuary 2014. For the 400-MeV LINAC, there are 48 RF
stations and 64 cavities in total. For each RF station, one
RF source is used to feed RF power to the RF cavities. In
the 324-MHz low-β section, three solid status amplifiers
and twenty 324-MHz klystrons are used as the RF sources.
In the 972-MHz high-β section, twenty five 972-MHz
klystrons are used. For each RF source, a low level RF(LLRF) control system unit is applied [1-2].The RF
signals including the RF amplitude and phase at the RF
cavities are controlled by an FPGA (Field-Programmable
Gate Array)-based digital feedback (FB) control systeminstalled in a compact PCI (cPCI) [3-4]. Recently, thesoftware of DSP and FPGA programs for the low-level
RF (LLRF) control systems of the J-PARC LINAC is
upgraded.

FUNCTION OF INSPECTING CAVITYPICKUP AND CAVITY REFLECTION
SIGNALS
The digital feedback (FB) control system installed in a

Figure 1: Block diagram of the RF feedback control for
972-MHz RF station.
In the RF&CLK board, RF (972 MHz), LO (Local
Oscillator, 960 MHz), and clock (48 MHz) signals are
generated. The LO (960 MHz) output signals from the
RF&CLK board will be used in the down-converters(Mixers) to detect the RF signals from the RF cavity. The
output signals with an intermediate frequency (IF) of 12
MHz from the down-converters will be acquired directlyby the ADCs in the FPGA board. The sampling frequencyof the ADCs is 48 MHz. Two pickup signals, one RF
input signal, and one RF reflection signals of the ACS
cavity, will be detected by the 4 ADCs in the FPGA
board as shown in Fig. 1. One FPGA board consists of
two FPGAs (Xilinx XC2V2000). The FPGA0 is used forreal-time feedback processing of the accelerating field.
After separating the I (in-phase) and Q (quadrature)components from the IF signals for the two cavity pickup
signals, a PI (Proportional-Integral) feedback control isconducted to obtain a stable RF field at the RF cavity.
The FPGA1 is used for measuring I and Q components of
the RF input and reflection signals of the RF cavity. Allof the RF signal data will also be sent to the DSP (Digital
Signal Processor).
Besides measuring the I and Q components of the RF- 828 -

Proceedings of the 11th Annual Meeting of Particle Accelerator Society of Japan
August 9-11, 2014, Aomori, Japan

PASJ2014-SAP110

signals, recently a function of inspecting RF cavity
reflection amplitude and RF cavity pickup signals in
real-time are added into the LLRF control systems.
At first, the function of inspecting RF cavity reflection
amplitude (ADC4_amp) is conducted by comparing witha limit setting (ADC4_limit) which is set beforehand. In
the case of the reflection amplitude (ADC4_amp) larger
than the limit setting (ADC4_limit), namely, ADC4_amp> ADC4_limit, the DAC output will be reset to 0 so as toprotect the RF systems. In the meantime, an interlock
signal(ADC4_limit_ILK)
will
come
out:
ADC4_limit_ILK = 1. Furthermore, this interlock signal(ADC4_limit_ILK) will be applied to the fast interlock
sysem to stop beam for protecting the accelerator.
On the other hand, the function of inspecting RF
cavity pickup signals (ADC1_I/Q and ADC2_I/Q) during
feedback ON is carried out by comparing with a reference
setting (ADC1_I/Q_ref and ADC2_I/Q_ref) which issaved beforehand during normal operation with FB ON.
Then, if cavity pickup signal is far away from thereference setting, for example, ADC1_I- ADC1_I_ref >50, all of the ADC data for cavity pickups, input, andreflection, and DAC data, will be saved for later
investigations on the RF systems. By using this function,
any of instabilities of the RF cavity pickup signals during
FB ON could be monitored in real-time for our RF
systems.

which was already set in the LLRF control systems.
Finally, the correct sag compensation coefficient will
be applied to DSP program for generating a feed-forward
setting table of I and Q components (FF_I_t and FF_Q_t)
as the following,t +t 
t +t 
FF _ I _ t = A _ t × 1 − Δα (t − 1 2 ) ⋅ cos θ − Δφ (t − 1 2 ) ;


2 
2 
t +t 
t +t 
FF _ Q _ t = A _ t × 1 − Δα (t − 1 2 ) ⋅ sinθ − Δφ (t − 1 2 ) ,
2 
2 



where t is from 0 to 1023 μs, and A_t and θ are theamplitude and phase of reference setting, respectively.
After sag compensation, the amplitude and phase at theflat top of RF output signals from klystron to cavity will
be a constant even with FB OFF, as shown in the red
curve of Fig. 2.
Before sagcompensation
After sagcompensation

T_sag_start

T_sag_stop

Figure 2: RF amplitude waveform with FB OFF before
and after sag compensation.

INTELLIGENT SAG COMPENSATION
AND AUTOMATIC FPGA CALIBRATION
For the J-PARC LINAC the beam is operated in apulse mode with a width of 500 μs. The pulsed highvoltage applied to klystron is of a width of 700 μs for
324-MHz RF stations, and 650 μs for 972-MHz RF
stations, respectively. There is a sag in the flat top of thehigh voltage waveform. Thus, the RF output waveformfrom klystron to cavity also drops in the flat top with FB
OFF, as shown in the blue curve in Fig. 2. Recently, an
intelligent sag compensation is being carried out by using
the DSP control program.
At first, a sag coefficient for amplitude and phase(Δα_test and Δφ_test) is measured by detecting theamplitude (At1 and At2) and phase (φt1 and φt2) of RF
cavity pickup signals at two sampling points (T_sag_startand T_sag_stop),
At 2 − At1t −t ;
Δα _ test = 2 1
At1 + At 22

Δφ _ test =φt 2 − φt1 ,t2 − t1
where t1 = T_sag_start, and t2 = T_sag_stop.
Then, a correct sag compensation coefficient for
amplitude and phase (Δα and Δφ) is calculated out as,Δα = Δα0 + Δα_test;
Δφ = Δφ0 + Δφ_test,
where Δα0 and Δφ0 are sag compensation coefficients

Figure 3: RF amplitude waveform with FB OFF and FB
ON.
Moreover, by applying an automatic FPGA calibration
as following, the same RF field will be obtained for FB
OFF and FB ON, as shown in Fig. 3.
DAC_amp_cali_new=Amp_ref/ADC_amp×DAC_amp_cali_old;
DAC_pha_cali_new=Pha_ref-ADC_pha+DAC_pha_cali_old,
where, DAC_amp_cali_new and DAC_pha_cali_new are thecorrect calibration parameters for DAC amplitude andphase, DAC_amp_cali_old and DAC_pha_cali_old are theold calibration parameters for DAC amplitude and phase,
Amp_ref and Pha_ref are the amplitude and phase of FB
reference setting, and ADC_amp and ADC_pha are theamplitude and phase of ADC.
By using the functions of intelligent sag compensation
and automatic FPGA calibration, the RF power in thecavity will not change with FB switching between ON
and OFF, and they are very helpful for accelerator
operation, especially for switching operation mode
between RF cavity conditioning and beam acceleration.

- 829 -

Proceedings of the 11th Annual Meeting of Particle Accelerator Society of Japan
August 9-11, 2014, Aomori, Japan

PASJ2014-SAP110FUNCTION OF SEPARATING CHOPPED
BEAM AUTOMATICALLY TO TWOSCRAPERSAt the J-PARC LINAC, presently one scraper is usedas dump of chopped beam after the chopper. However, weare planning to increase the proton beam current from 20
to 50 mA in the soon future, and the beam power will beover the limitation of the scraper. Therefore, two scrapers
will be applied after the chopper.
Then, a function of separating the chopped beam
automatically to the two scrapers is considered by using
FPGA program in the LLRF control systems. Figure 4
shows the schematic diagram of one chopper with two
scrapers at the J-PARC LINAC. Moreover, two ways forseparating beam are considered: 1) separating beam bymacro-pulse of RF gate signals, and 2) separating beamby intermediate-pulse of chopping signals.

Figure 4: Schematic diagram of one chopper with two
scrapers at the J-PARC LINAC.

macro-pulse of RF gate signals. The other input signal is“Chop_signal”, which is used for the second way:
separating beam by intermediate-pulse of chopping signal.
Then, in Fig. 5, the separating way is decided by the input
parameter “Trig_pha_rev_way” which is defined on thetouch panel (TP) of the PLC (Programmable Logic
Controller) of the LLRF control system. Furthermore, aswitch “Trig_pha_rev” is also set by the PLC TP for
turning this function ON or OFF.
Figure 6 shows a schematic view of timing signals forchopper station, and RF amplitude and phase of the
chopper output for separating beam by intermediate-pulseof chopping signal. The chopped beam separation isrealized by using the FPGA program. All of the input
timing signals and reversion setting shown in Fig. 5 andFig. 6 will be detect by the FPGA, and a phase reversionof the I and Q output signals is carried out tracking all of
the input signals including the chopping signal in realtime. The RF phase reversion can be easily taken out by
using I_out=- I_in, and Q_out=-Q_in. Thus, the beam
will be chopped to a revered direction so that the beam isseparated to two scrapers. Of course, we need to adjust
the chopping-signal delay once before the application of
the system to the beam operation in order to assure thatthe timing of the phase reversion is at the bottom of the
RF amplitude. By using this design, we can see that, theabove two ways for beam separation becomes available in
one control system and could be chosen easily just with
one button on the PLC TP.

SUMMARY
Figure 5: Phase-reversion function block inserted in the
FPGA output circuits.

Software for the DSP and FPGA programs is
upgraded. By applying function of inspecting cavity
pickup and cavity reflection signals, instabilities could bemonitored in real-time, and an interlock due to larger RF
cavity reflection amplitude could be applied to the fastinterlock sysem. With intelligent sag compensation andautomatic FPGA calibration, the RF wavforms in case of
FB OFF and FB ON could be almost the same.
Furthermore, a new function of separating the chopped
beam automatically to two scrapers is being developed
using FPAG control systems.

REFERENCES

Figure 6: Schematic view of timing signals for chopper
station, and RF amplitude and phase of the chopper
output.
In order to realize the function of separating beam, aphase-reversion function block is inserted in the FPGA
output circuits for the FPGA program as shown in Fig. 5.
In Fig. 5, there are two timing input signals to thephase-reversion function block. One input signal is“Trig_pha_rev”, which is a trig signal with a repetition
rate of 12.5 Hz used for the first way: separating beam by[1] S. Anami et al, “Control of the Low Level RF System
for the J-PARC Linac”, Proceeding of LINAC 2004,
739-741, Germany.
[2] S. Anami et al, “J-PARC Linac Low Level RF
Control”, Proceedings of the 1st Japan Particle
Accelerator Conference and the 29th Linear
Accelerator Meeting in Japan, 296-298, 2004.
[3] S. Michizono et al, “Digital Feedback System for
J-PARC Linac RF Source”, Proceeding of LINAC
2004, 742-744, Germany.
[4] S. Michizono et al, “Digital LLRF Feedback Control
System for the J-PARC Linac”, Proceedings of the 2nd
Annual Meeting of Particle Accelerator Society ofJapan and the 30th Linear Accelerator Meeting inJapan, 147-149, Jul. 2005.

- 830 -