Medium-term Management Plan
Progress and TEL Initiatives
May 31, 2017
Toshiki Kawai
Representative Director, President & CEOFY2017 Financial Highlights
Operating Income andOperating Margin

Net Sales and Gross Profit Margin(Billion Yen)

(Billion Yen)

900

200

799.7

Net sales
Gross profit margin

600

613.1
39.6%

40.2%

150

40.3%

33.0%

Net income

17.6%

15.0%

100

13.0%
11.8%

116.7
100

88.1

19.1%

ROE

155.6

14.4%

497.2
31.9%

19.5% 20.0%(Billion150Yen)

Operating margin
663.9

612.1

Operating income

Net Income and ROE

10.0%

115.2

50

71.8
300

1.0%
6.0

5.3%

5.0%

50

2.5%

0

-19.4

32.2

12.5
0





-3.3%

0.0%

0

FY2013 FY2014 FY2015 FY2016 FY2017

FY2013 FY2014 FY2015 FY2016 FY2017

77.8

-50

FY2013 FY2014 FY2015 FY2016 FY2017

Net sales increased by 20% YoY, highest ever SPE* sales
Set new record highs for GPM, OPM and net income
ROE of 19.1% (+6.1pts YoY). Further increased capital efficiency

CORP IR / May 31, 2017

* SPE: Semiconductor Production Equipment2

FY2018 Financial Estimates
FY2017(Actual)(Billion Yen)FY2018 (Estimates)
1st half

2nd half

Full year

Full year
YoY change

Net sales

799.7

480.0

500.0

980.0

+22.5%

SPE

749.8
49.3

451.0
29.0

459.0
41.0

910.0
70.0

+21.4%+41.7%

Gross profit

322.2

202.0

210.0

412.0

+89.7

Gross profit margin

40.3%

42.1%

42.0%

42.0%

+1.7pts

Operating income

155.6

104.0

112.0

216.0

+60.3

Operating margin

19.5%

21.7%

22.4%

22.0%

+2.5pts

Net income attributable toowners of parent

115.2

79.0

84.0

163.0

+47.7

Net income per share (Yen)702.26481.48511.96993.44+291.18

FPD*

Expect sales growth to exceed market growth,
generating record high profits for second consecutive year
CORP IR / May 31, 2017

* FPD: Flat Panel Display Production Equipment

3

Current Progress with Medium-term Financial Targets
Medium-term financial targets

WFE*

FY2015(Actual)

FY2016(Actual)

FY2017(Actual)

FY2018(Estimate)

Market size

$31.9B$31.4B

$35B

$38B

$30B

$37B

Net sales
Operatingmargin¥613.1B¥663.9B¥799.7B¥980.0B¥720.0B¥900.0B

14.4%

17.6%

19.5%

22.0%

20%

25%

ROE

11.8%

13.0%

19.1%

-

15%

20%

Steady improvement in results.
Continue to focus on improving profit margins* WFE (Wafer Fab Equipment): The semiconductor production process can be divided into two sequential sub-processes: front-end (wafer fabrication) and back-end (assembly and test)
production. WFE is used in the front-end production process. Equipment for wafer-level packaging is not included in the WFE market size here.

CORP IR / May 31, 20174

Outperform the Market
 Continue to achieve earnings increases greater than market
growthFY2017 results (compared to FY2016)⇒
TEL sales growth +20.4% (WFE market growth* +11.5%)
Operating income growth +33.3%
FY2018 plan (compared to FY2017)⇒
TEL sales growth +22.5% (WFE market growth* +8.6%)
Operating income growth +38.7%* WFE market growth rates are for the calendar year Expand market share for etching system, thermal processing
system, and cleaning system
CORP IR / May 31, 20175

Era of IoTAutonomous
driving

IoT
AI

FintechAR/VRSocialmedia

AI robotsDNAanalysis

The amount of data is dramatically increasing withthe growing number of connected devices
CORP IR / May 31, 20176

Infrastructure Evolution Supporting the IoT Era

High speed, high reliability, low latency, the number of connected devices

5G Network
Compared to 4G: Speed: 100x
Data latency: 1/50th# of connectable devices: 100x

5G, the next generation communications standard, will establish
the infrastructure for an IoT society
CORP IR / May 31, 2017

7

The Evolution of Society
Socialmedia

Finance

Manufacturing

AI

Traffic

MedicalReal time systems will be built onsociety’s cloud systems
Semiconductors will be increasingly integrated
throughout society
CORP IR / May 31, 20178

Expansion of ＷFE Market
Equipment for wafer-level packaging is not included in the WFE market size here($ Billion)

50

$40B~

40

$30B

30

$20B

20
10
0

$10B
1990

1995

2000

2005

2010

2015

Source: 2001-2013 SEMI
2014-2018 VLSI “Chip Market Research Services Equipment Database, 1Q17 Update” Apr. 2017. Graph created by TEL using above data

Semiconductor industry is heading for its next growth phase
CORP IR / May 31, 20179

Growing Use of Displays as Interface Devices
スマートフォンはインターフェイス
デバイスへ

Smartphone

Head mounted display

Heads-up display

Digital signage touchscreen

Functionalities sought in displays:
ultra-high resolution・large scaled・
low power consumption・flexibility

Further growth expected in the display market
CORP IR / May 31, 201710

New Medium-term Financial Targets (toward FY2020)
Equipment for wafer-level packaging is included in the WFE market size here

WFE

Market size

$42B

$45B

Net sales¥1,050B¥1,200B

24%

26%

Operating margin
ROE (Return on Equity)

20-25%

Targets adjusted due to changes in market conditions
CORP IR / May 31, 201711

New Organization: Development & Production GroupAs of June 1, 2017



Improve development flexibility as we enter
new growth phase

Merge Yamanashi and Tohoku
plants, establish TTS*––President & CEO
Toshiki Kawai

Combine technology and increase efficiency
Move process integration functions to plants,
accelerate commercialization

Technology Strategy Division to advancefuture technologies/technological integration
focused on the IoT era

Development &Production group Main products
Dev. & Production
1st Division

Deposition systems

Dev. & Production
2nd Division

Etching systems,
Dry cleaning systems

Dev. & Production
3rd Division

Coater/developers,
Wet cleaning systems

Dev. & Production
4th Division

Test systems,
FPD dry systems

Technology Strategy* TTS: Tokyo Electron Technology Solutions Ltd.

CORP IR / May 31, 2017

Division12

Miyagi Plant: New Development/Logistics Buildings
New
Development
Building

135m

Floor area: 11,600㎡(CR-related: 7,000㎡)

Development
Building
17,165㎡
130m

Logistics Building

New development building:construction scheduled for completionby the end of August, 2018

(under construction)

Production
Building

Office Building

Tokyo Electron Miyagi Ltd.
New development building and logistics building

Create and optimize customer value through joint R&D withcustomers, R&D integration, and continued improvement
CORP IR / May 31, 201713

Summary Semiconductors and FPDs entering a new growth phase– Revised WFE market outlook and financial targets (market outlook of$42B-$45B)

 Optimize R&D structure to adapt to future business environment– Establish five development divisions, ensure a flexible development structure– Establish TTS to strengthen deposition business (technology
integration/efficiency)– Move Process Integration Center to TTS, accelerate product development

 Expand etching business to respond to further growth– Increase production, improve efficiency by constructing logistics building– Accelerate development of added-value products by constructing new
development building
CORP IR / May 31, 201714

SPE R&D Strategy

Sadao Sasaki
Representative Director, Executive Vice President & General Manager,
Development & Production Division

Contents
 Growing demand for leading-edge technology: Opportunities for TEL– TEL Technology Vision 2030

 R&D strategy progress– Demand for leading-edge technology and TEL R&D strategy– Unifying development to integrate TEL proprietary technologies

 Medium-term plan: Progress on business focus areas(Etching, Deposition, Cleaning Systems)

CORP IR / May 31, 201716

Growing Demand for Leading-edge Technology: Opportunities for TEL
TEL Technology Vision 2030

CORP IR / May 31, 2017

17

TEL Technology Vision 2030

Semiconductors
Semiconductors
forfor all
all industries
industries

Energize discussion of future technologies achievable by 2030 and
TEL’s contribution to these
CORP IR / May 31, 201718

Automatic
Operation

Building the World of 2030

Smart Society

AI/Deep Learning
Advanced Architecture

Advanced CMOS Technology

CPS/IoT
Communication
Technology
Integrated Analog Device
Image Processing
Edge/Cloud Computing
Storage Class Memory
Emerging Memory

Advanced Lithography

Critical FEOL/BEOL Solution
Material Challenges

Charge/Create Energy

Lower Energy
Consumption

Personal Medical

Neuromorphic
Computing

Advanced Packaging

Core
Technology

Ubiquitous
3D Printing Manufacturing Flexible DisplayIntelligent Fab System

Biotechnology

Leading-edge Technology Customer Satisfaction

Robot
Environment

Virtual Reality
Industry Collaboration/Co-Creation

Rapid growth in semiconductor applications in a range of areas,
more sophisticated technology requirements
CORP IR / May 31, 2017

19

TEL Growth Strategy

Solution provider
for all industries

2030

Solution provider
for the semiconductor
industry
Current
2030
TEL technology contributes to the evolution of semiconductors,
the importance of which is growing in all industries

CORP IR / May 31, 201720

R&D Strategy Progress

CORP IR / May 31, 201721

Demand for Leading-edge Technology and TEL Strategy••

3D NAND

DRAM

Logic

Enhance multi-layering &production capacity

Deliver 1X miniaturization

Develop leading-edge 5 & 3nm

Improve capacitor
performance to further
increase storage
Apply high aspect ratio
etching and new materials•

High selectivity process
Pursue further processaccuracy and improve
productivity•••

Develop patterningtechnology for scaling
Develop new materials,
selective deposition

Pursue internal and external collaboration to accelerate development ofinnovative integrated technologies (process solution development,
next-generation platform development)
CORP IR / May 31, 201722

Increase R&D Spend (R&D Investment in Focus Areas)¥94.0B(Billion Yen)
100

75

73.2

83.8

78.6
71.3

New product/
technology R&D
investment

76.2

SPE business

50

25

0

Cross-BU
R&D investment

Cross-BU development andcollaboration
Other businesses: development offundamental technologies

FY13

FY14

FY15

FY16

FY17

FY18(E)

Actively invest in creating further integrated technologies andgrowth areas
23
CORP IR / May 31, 2017

Patterning Strategy
EPE*/CDU**challenges

Establish self-aligned patterningtechnologies with multiple major
customers
Advance R&D in close communication with customers
Expand on-site evaluation

Full commercializationof EUV

Collaborate with leading-edge
consortia and equipment/materials
manufacturers
imec, SRC, AIST, simulation tool vendors, etc.

Limitations ofmeasuring instruments* EPE: Edge placement error** CDU: Critical dimension uniformity*** TTCA: TEL Technology Center, America
CORP IR / May 31, 2017

Enhance internal evaluation/R&D
facilities
Established Process Integration Center
R&D by function at three facilities (TTCA***, Koshi, Hosaka)

24

3D NAND Key Process Technologies and TEL’s Solutions
CLEAN TRACK™

TactrasTM

Plasma dry etch
• Word line isolation• Channel hole
• Multi-level contact

Lithography
LITHIUS Pro™ Z• Word line isolation• Channel hole
• Multi-level contact• Staircase

Multi-level contact

Chemical dry etch
• Source line pre-clean
CertasTM

Word line

Staircase

EXPEDIUSTM-i

Wet etch• Replacement word line
CELLESTATM-i

Wet clean• Bevel clean
CORP IR / May 31, 2017

ChannelWord line isolation (Slit)
Source line

Single wafer deposition• Word line barrier• Multi-level contact barrier• Source line barrier

Thermal process (batch deposition)• Block oxide (high-k)• Charge trap (ALD SiN)
• Channel Si• Cap Si TELINDY PLUSTM
Atomic layer deposition• Core oxide

NT333TM

Triase+TM25

Expanding Business Opportunities in the 3D NAND Market

2D
miniaturization

Equipment ratio for 3D NAND*

Equipment ratio forprevious
2D
NANDNAND capex*

Multi-layering, high A/R:

Lithography
Deposition

OthersCoating/developing

Cleaning
Deposition* TEL estimate
CORP IR / May 31, 2017

Etching< 15%

3D NAND
stacking

・Increase in number of layers etched・Pursuit of high process accuracy
decreases productivity⇒ More equipment units needed

Etching> 50%
26

SPE Business Strategy: Strengthen Deposition Technology R&D
 Establish Tokyo Electron Technology Solutions– Unify development resources by merging Tokyo Electron Yamanashi and Tokyo Electron Tohoku

 Established Process Integration Center (PIC)– Cross-BU process module development
Sapporo Develop next-generation platform– Incorporate new controllers (AI software)

Oshu
Tokyo Electron
Yamanashi<Nirasaki(Fujii/Hosaka)>

Tokyo Electron Kyushu<Kumamoto (Koshi/Ozu)>

Taiwa

Tokyo Electron
TohokuNirasakiAkasaka

Tokyo Electron Miyagi
Headquarters
R&D/manufacturing/
technology

CORP IR / May 31, 2017

Tokyo Electron HQ

27

SPE Business Strategy: Deposition Systems
ALD system

Thermal processing system

NT333™

TELINDY PLUS™

Atomic layer
deposition

Oxidation/diffusion
CVD
¥111B

(batch)Single wafer
deposition system

Sputtering system fornext-generation devices

Triase+™

EXIM™

MRAM
deposition

Metallization（Ti/TiN）
¥120B

¥30B

R&D
POR

Bring together the results of CY2014-16
R&D activities and move to the production
preparation stage

Aim to expand earnings based on new technologies for further
miniaturization, new structures, and next-generation semiconductors
CORP IR / May 31, 2017

* Figures reflect TAM estimated by TEL

28

SPE Business Strategy: Cleaning Systems
 Expand sales of CELLESTA™ single wafer cleaning system– Expand applications based on backside and bevel cleaning * and drying technologythat prevents pattern collapse during the post-etch cleaning processes Secure key 3D NAND processes through batch cleaning

Single wafer cleaning system
CELLESTA™

– Provide high quality and productivity in the metal etching, polysilicon etching, andnitride film removal processes required for precise controllability

 Apply best known coater/developers methods to cleaning systembusiness– Share leading-edge technology and expertise by unifying R&D
Market share

CY14 (Actual)

CY15 (Actual)

CY16 (Actual)

Cleaning system

19%

18%

20%

Batch cleaning system
EXPEDIUSTM

・・・

CY19 (Target)>24%* Bevel cleaning: process for removing film from the outer part of the wafer

CORP IR / May 31, 201729

Summary Formulated TEL Technology Vision 2030 to facilitate further business growth– Capture growth from diversifying semiconductor demand Aim for growth through strategic advancement of collaborations withcustomers and consortia, further strengthening of existing products, andcross-BU synergistic effects– Advance patterning solution R&D– Integrate technologies (3D NAND development solutions, integrate deposition facilities)

 Strengthen business through strategic investment in focus areas– Deposition business: speed up new product development through selection andconcentration– Cleaning business: enhance products and improve market share by applying best known
coater/developers methods
CORP IR / May 31, 201730

Corporate Development Strategy: Growth Opportunities
through Integration
Akihisa Sekiguchi, PhD
Vice President & General Manager
Advanced Semiconductor Technology Division

Contents
 Device roadmap and issues in integration– Memory technology roadmap:

DRAM, 3D NAND

– Logic technology roadmap:

FEOL, MOL, BEOL

 The importance of Process Integration Center (PIC) within our worldwide R&D

CORP IR / May 31, 201732

Device Evolution

Nano-wire

FinFET

3D structure
Planar3D NAND
High A/R
DRAM

[nm]
1000

ArF
100

i-Line

10

1
1990

KrF

180

130

110

immersion
90

65

45

CORP IR / May 31, 2017

1996

EUV

22
14

resolution
wavelength
1993

32

scaling
1999

2002

2005

2008

2011

2014

10

2017

7

5

2020
33

Device Roadmap and Issues in Integration
Memory:DRAM, 3D NAND
Logic:
FEOL, MOL, BEOL

CORP IR / May 31, 201734

DRAM Roadmap
Node

2Y

1X

1Y

Cell layout

1Z
6F2

i-ArF

Cell
transistor

EUV

Structure

Burried WL, FinFET

Material

W/TiN/SiON

Cellcapacitor

Lithography

Structure
Material

Cylinder structure
TiN/ZAZ/TiN

Difficulty level of scaling has risen beyond 1Y
CORP IR / May 31, 201735

DRAM Challenge
Dry etching

Hard mask

 High aspect ratio capacitor (HARC) hole formation
 High selectivity etch (for insulator etch)

HARC dry etch

Film deposition
Capacitor insulator dep

Capacitor electrode dep

 High selectivity hard mask (for insulator etch)
 Conformal & low leakage insulator for capacitor
 Conformal & low resistance electrode for capacitor

Wet oxide film removal

Cleaning/wet etching Prevention of pattern collapse
 High aspect ratio structure cleaning

Challenges involving high aspect ratio structures dominate
CORP IR / May 31, 201736

3D NAND Roadmap
Layer

ONON
stack

48 layers

ONON

64 layers

96 layers

128 layers> 128 layers

Charge trap structure

ONON film stack optimization
O-SiO2
N-SiN

Adjacent CMOS circuit & memory cell layout
Cell on CMOS

OPOP
stack
O-SiO2
P-Poly-Si

OPOP

Floating gate structure

Vertical gate NAND
3D ReRAMStack
Triple level ⇒Quad level cell

OPOP film stack optimization/Memory cell on CMOS (cell on CMOS)

Increasing layers drives high aspect ratio and process challenges
37

3D NAND Challenges
Dry etch
Hardmask
Staircase etchfor contact

 High aspect ratio etch
 High selectivity (versus stack films)

Depositon
WL metal dep

Cell stack etch

Cell stack deposition

 Reduction of ONON/OPOP stack warpage
 High selectivity hardmask
 Conformal functional film for flash
 High mobility channel
 Metal gate

Hardware

Clean/wet etch Handling warped wafers

 Removal of nitride films in 3D structures

Etch and deposition of films for high aspect ratio structures challenging
CORP IR / May 31, 201738

Device Roadmap and Issues in Integration
Memory:DRAM, 3D NAND
Logic:
FEOL, MOL, BEOL

CORP IR / May 31, 201739

FEOL Roadmap
Node16-14 nm

10 nm

7 nm

5 nm

< 3.5 nmLateral nanowire

Vertical nanowire

Transistor
structure
Reducing shortchannel effectFinFET

Channelmaterial
Higher mobility
Estimated using IEDM, VL, IITC papers

Structural changes in transistor concurrent with scaling
CORP IR / May 31, 201740

FEOL Challenges

 Short channel effect control (on/off ratio)– New structure Channel mobility
FinFET– New channel material

 Parasitic resistance reduction– Source/Drain activation enhancement– Low resistance silicide Parasitic capacitance reduction– Low dielectric constant material

Nanowiretransistor

 Variability reduction– Chamber matching, physical dimension
controlChanges in transistor structure leading to changes in device performance
CORP IR / May 31, 201741

MOL Roadmap
16-14 nm

Node

10 nm

7 nm

5 nm

< 3.5 nmWrap around contact

Diamond epi

Source/Drain
shape
Self aligned contact
Replacement contact

Contact
schemeW

Co

Contact metal

Estimated using IEDM, VL, IITC papers
Scaling, overlay, and contact resistance increase
are issues
CORP IR / May 31, 201742

MOL Challenges
 Parasitic resistance– New structure, lower resistancematerial needed for reduction

 Narrow trench gap fill
– High aspect ratio structure gapfill

 Overlay– Self aligned process Variability
Contact structure– Chamber matching

Scaling causes problems such as contact resistance increase
CORP IR / May 31, 201743

BEOL Roadmap
Node16-14 nm

10 nm

7 nm

5 nm

< 3.5 nmSelf aligned via formation

Dual damascene

Self aligned via (SAV)
Self aligned block

Wiringformation
schemeNon SAV

Metal wiring

SAV

Cu : ECD
Ta/TaN PVD

Cu

Cu alternatives
Ru, Co, CoAl

Post Cu

Estimated using IEDM, VL, IITC papers

Scaling & overlay issues leading to evaluation of new integration schemes

CORP IR / May 31, 201744

BEOL Challenges

 Low resistance– Cu: thinner barrier layer– Cu alternatives: Ru, Co, CoAl, Parasitic capacitance reduction– Low dielectric constant film, air gap– Etch damage reduction: low temp etch, replacement
schemes– Lower dielectric constant etch stop layer

 Narrow trench gap fill
– Liner layer, alternative metals

 Overlay– Self aligned process Reliability (migration etc.)– Wiring cap layers

Migration period from Cu to other metals, parasitic capacitance still an issue
CORP IR / May 31, 201745

Importance of Process Integration Center (PIC)in the Context of Worldwide Development

CORP IR / May 31, 201746

Global Development Locations
United States
Korea
imec (Belgium)
TEL Technology Center, America
TEL Technology Center Korea

Taiwan

CEA-Leti(France)Japan
Albany NanoTech
TEL Technology Solutions
Process Integration Center (PIC)TEL Technology Center, Taiwan

Tokyo Electron Kyushu
Tokyo Electron Miyagi

IME(Singapore)
TEL development locations
Consortia

Worldwide development accelerated due to strengthening of PIC function
CORP IR / May 31, 201747

Process Integration Center (PIC) Mission
Customer’s technology roadmap
TEL process-integrated solutions
TEL product development roadmap
 Expand business through collaboration with customers
 Add value to TEL products by synchronizing product development and PIC solutions

 Develop competitive solutions in advance in order to make solid proposals based on
proven solutions
 Support overall TEL development by making sample wafers with high quality and shortlead time, and by providing insights with knowledgeable analysis

Higher level technical collaboration with partners
CORP IR / May 31, 201748

Process Integration Center (PIC) Function
Process tools

Analytical tools

Etch

Clean
CELLESTA™ -i

Tactras™ Vigus™

Analysis and measurement(Particle, ellipsometer, XRF, overlay)

Certas™

Cross sectional analysis(SEM, STEM, FIB, others)

Surface analysis(TXRF, XPS, XRD, AFM, others)

Lithography
CLEAN TRACK™
LITHIUS Pro™ Z

Triase+™ / EXIM™

TELINDY PLUS™

Deposition

NT333™

Faster development by centralizing process and analytical tools
CORP IR / May 31, 201749

Summary How to plan ahead and develop new tools based on device
evolution is key

 The success of the Patterning Solutions Project has led to the
kickoff of Process Integration Center (PIC). It expands on thescope of activities beyond just patterning Enhancement of the worldwide development organization bystrengthening PIC will lead to TEL’s competitiveness Continue to create technology innovation through close
collaboration with our customers and partners
CORP IR / May 31, 201750

Etching System: Business Strategies

Yoshinobu Mitano
Vice President & General Manager, ES BU

Etching System Market Outlook
Etching system market by application
WFE market

($B)
50
40

37.0

40.0

Overall WFE market+25% on CY15
42.0

>42.0

($B)

Significant NAND
market expansion

10

33.3

NAND

30

5

20

DRAM
10
0

6.4

7.4

9.0

11.0

11.0

CY15

CY16

CY17

CY18

CY19

TEL estimates

Etching system
market +70% on CY15

Logic, other
0
CY15

CY16

CY17

CY18

CY19

TEL estimates (new equipment only)

3D NAND driving 70% growth in etching system market from
CY15 to CY19
CORP IR / May 31, 201752

3D NAND Business Opportunities
Increase in 3D NAND HARC* processes

Ratio of etching systems in NAND
CY12-14

CY19

Etching systems
15%

Other systems
85%

Investment per 10k/wspm** ($M)

6X

9X

12X

HARC processes

30

40

50

Other etching processes

80

80

80

Etching process total

110

120

130

(multi-level contact/word line isolation/channel)

Etching systems
50%
Other systems
50%（Greenfield, TEL estimates）

9X

TEL estimates

3D NAND 6X

3D NAND HARC* processes

CY17

CY18

CY19

6X

6X/9X

9X

Multi-levelcontact
Word line
isolation (Slit)

Channel(Memory hole)

Expand HARC processes by increasing number of stacked layers* HARC (High aspect ratio contact) process: a process for forming holes that requires advanced processing technology

CORP IR / May 31, 2017** wspm: wafer starts per month53

3D NAND: Approach and Results
 Maintained a 100% share of the multi-level contact processes. Plan to further
increase revenues by integrating mask process to improve productivity

 Captured new customer PORs with 9X generation word line isolation.
Aim to increase our position by integrating mask process Realize the capture of channel processes through new technology
Improve productivity byintegrating processes

A single system that combines
mask and main processes
normally processed by different
systems
 Improved productivity

Mask process

Main process

Expand our position by dramatically improving profile and productivity
CORP IR / May 31, 201754

Logic: Approach and Results
 Maintained high interconnecting dielectric etchingprocess market share

Interconnects
Advanced patterning Aim to expanded advanced patterning applications
RLSA™ plasma source

Plasma etch systems
Tactras™ RLSA™

Realize high selectivity
through low electron
temperature plasma

ALE concept process

Achieve high-level of control overdimension variation

Aim to increase sales by differentiating our technology in
7nm and finer advanced patterning
CORP IR / May 31, 201755

DRAM: Approach and Results Captured BEOL processes by leveraging expertise in logic through our strength in damascene
processes
 Captured development PORs with all customers using 1Y generation capacitor process (HARC)
 Realized reduced patterning costs for customers by combining etching steps.
Currently using successes with strategic customers to expand market share in other customers
Interconnects

Capacitor(HARC)

Simplify process and raise productivity by
combining multiple etching steps

Currently achieving success in all DRAM focus processes
in line with plan
CORP IR / May 31, 2017

56

Action to Increase Profitability New products focused on the high-end market

 Active capex in R&D
 Reduce customer support expenses through products with improved addedvalue Optimize logistics
 Further reduce fixed cost ratio

Tokyo Electron Miyagi’s new development and logistics buildings

Plan to raise sales and profits through technologicaldifferentiation and improving production efficiency
CORP IR / May 31, 201757

Summary Expect significant expansion of etching system market driven by 3D NAND
and patterning We are enhancing our positions in logic and memory focus areas
 Actively investing in R&D in response to further market expansion

 Focus on HARC, patterning, and BEOL processes that utilize our strengths.
Aim to raise profitability by increasing market share to over 30% by CY19

Market share
Etching system

CORP IR / May 31, 2017

CY14 (Actual) CY15 (Actual) CY16 (Actual)
28%

21%

23%

・・・

CY19 (Target)
>30%

58

FPD Business Strategy

Tsuguhiko Matsuura
Vice President & General Manager, FPD BUDisplay Trends
Technology inflection creates greater business opportunities
Increasing screen size

OLED
Color filter

Emissive
layer

LCD
TFT

TFT

Backlight

LCD

Increasing resolution

OLED

Design flexibility

TV
FHD

4K

Smartphones 300 ppi
CORP IR / May 31, 2017

8K
700 ppi

Flexible, edge bent, free format
60

FPD Business Medium-term Plan
 Increase share and profitability in market that has begun to grow again
 FY2020 target: sales ¥80.0B, operating margin over 20%（Billion Yen)
100

40%

80

30%

60

20%

Sales
40

10%

20

0%

0

-10%

FY2015FY2016FY2017FY2018 (E)Operating margin

FY2020(Medium-term plan)

CORP IR / May 31, 201761

Medium-term Plan Progress: Highlights
 TEL’s product strategy for a new PICP™* etching system is progressing
according to plan Expanding the G10.5 equipment business
2015
G10.5
G8.5

2016

2017

2018

2019

Coater/developers andetching system

PICP etching system forlarge-sized panels
PICP etching system for small- and medium-sized panels

G6

New Betelex™ platform
OLED process (G6H)

Higher profitability for all panel generations
CORP IR / May 31, 2017

* PICP: Plasma source for producing extremely uniform high density plasma on substrate

62

Opportunity – G10.5 Equipment Market
 Greater than expected investment and market expansion

 Maintain high market share through technological differentiation (large area plasma
suppression, air floating coater）
G10.5 TFT array equipment market

Eight 65 inch TV panel substrate possible（$M）3,500

“65

3,000

3,370 mm

2,500

2,000
1,500
1,000
500
0
2017

2018

2019

Results based on IHS Markit, Technology Group “Display Supply Demand & Equipment Tracker, Q1 2017”. Results are not anendorsement of Tokyo Electron. Any reliance on these results is at the third party's own risk. Visit technology.ihs.com for more details.

CORP IR / May 31, 2017

2,940 mm63

Opportunity – Metal Oxide/LTPS
 Higher sophistication of etching technology and increased number of processes

TFT

a-Si

Metal oxide

LTPS

Further new
needs

Representationof structure

Application

LCD TV
Monitor

OLED TV
TabletSmartphone(LCD/OLED)

Number of
masks

5

6-8

9 - 13Dry etchprocesses

3a-Si, SiNx

3
SiO, SiNx-11
SiO, Metal

CORP IR / May 31, 2017

Flexible displays＋2 processes
OLED process(G6 half size)＋3-4 processes

64

Opportunity – Growth of OLED TV Market
 Introduced inkjet printing system to meet production demand from 2018
 Material utilization significantly more efficient than current evaporation method

Increase in OLED TV manufacturers

OLED TV area demand8

New manufacturers in Japan6

Mm2 / YR

Toshiba
REGZA X910 series
Launched March 2017Sony
BRAVIA A1
To be launched June 2017
Panasonic
VIERA TH-65EZ1000/EZ950 series
To be launched June 2017

7

5
4
3

2
1
0
2016 2017 2018 2019 2020 2021

CORP IR / May 31, 2017

Results based on IHS Markit, Technology Group “Display Supply Demand & Equipment
Tracker, Q1 2017”. Results are not an endorsement of Tokyo Electron. Any reliance on theseresults is at the third party's own risk. Visit technology.ihs.com for more details.

65Summary
 Increase share and profitability in market that has begun togrow again
Greater than expected business expansion

FY2020 target: sales ¥80.0B, operating margin over 20%

 For leading-edge production process, focus on areas where
we have technological superiority– High performance PICP etching system– G10.5 compatible etching system and coater/developers– Inkjet printing system for OLED TV
CORP IR / May 31, 201766

Financial Model

Tetsuro Hori
Representative Director, Executive Vice President & General Manager

Financial Model: Concept

 TEL is changing its financial model to match the larger
scale of the semiconductor market

 Financial model: Change in WFE* market scale– In our financial model announced in 2015 we presented a range
according to economic conditions (WFE $37B-$30B)(Equipment for wafer-level packaging is not included)– Our new financial model presents a forecast range for FY2020.
We expect the WFE market to reach a size of $42B to $45B
(Equipment for wafer-level packaging is included)* WFE (Wafer Fab Equipment): The semiconductor production process can be divided into two sequential sub-processes: front-end (wafer fabrication) and back-end (assembly and test)
production. WFE is used in the front-end production process.

CORP IR / May 31, 201768

Financial Model (toward FY2020)(Billion Yen)FY2017(Actual)

FY2018(Estimate)

WFE $37B

WFE $40B

FY2020(Medium-term plan)
WFE $42B
WFE $45B

Net sales

799.7

980.0

1,050.0

1,200.0

SPE
FPD

749.8
49.3

910.0
70.0

970.0
80.0

1,120.0
80.0

322.2

412.0

452.0

522.0

Gross profit margin

40.3%

42.0%

43.0%

43.5%

SG&A expenses

166.5

196.0

200.0

210.0

SG&A expense ratio

20.8%

20.0%

19.0%

17.5%

Operating income

155.6

216.0

252.0

312.0

Operating margin
Net income attributableto owners of parent

19.5%

22.0%

24.0%

26.0%

115.2

163.0

180.0

220.0

Gross profit

CORP IR / May 31, 201769

SPE Sales (WFE $45B)
 TEL continues to plan for growth in sales above market growth(Billion Yen)FY2017(Actual)
WFE $37B

FY2018(Estimate)
WFE $40B

FY2020(Medium-term plan)
WFE $45B

Growth(FY17-FY20)
WFE +22%

749.8

910.0

1,120.0+49%

New equipment

550.3

660.0

810.0

+47%

Field solutions

199.4

250.0

310.0

+55%

Sales

 Differentiate our technology in products and continue to win PORs
 Meet expanding demand for field solutions

CORP IR / May 31, 201770

FPD Sales
 Plan to expand sales based on differentiated technology andhigh-market-share products(Billion Yen)FY2017(Actual)

FY2018(Estimate)

FY2020(Medium-term plan)

Growth(FY17-FY20)

49.3

70.0

80.0

+62%

New equipment

40.5

60.0

70.0

+73%

Field solutions

8.8

10.0

10.0

+13%

Sales

 In OLED panels where high level technology is in demand,differentiate with cutting-edge PICP™* technology
 Further expand sales for G10.5, where TEL has a high market share Continue development of inkjet printing system for OLED TVs* PICP: Plasma source for producing extremely uniform high density plasma on substrate

CORP IR / May 31, 201771

Gross Profit (WFE $45B)
 Gross profit margin: up 3.2pts(Billion Yen)FY2017(Actual)Gross profit
Gross profit margin

FY2018(Estimate)

FY2020(Medium-term plan)

Growth(FY17-FY20)

322.2

412.0

522.0

+62%

40.3%

42.0%

43.5%

+3.2pts

 Raise marginal profit ratio of core SPE products– Timely introduction of new products to an expanding market– Lower cost ratio through product quality improvements Raise marginal profit ratio of FPD production equipment

CORP IR / May 31, 201772

SG&A Expenses (WFE $45B)
 SG&A expense ratio: improve by 3.3pts(Billion Yen)FY2017(Actual)
SG&A expenses
SG&A expense ratio

FY2018(Estimate)

FY2020(Medium-term plan)

Growth(FY17-FY20)

166.5

196.0

210.0

+26%

20.8%

20.0%

17.5%

-3.3pts

 Cost reductions through integration of development units– Establish Tokyo Electron Technology Solutions Ltd.
– Realized benefits of integration of Coater/Developers and Cleaning System business units Raise business productivity, control fixed costs– Improve business efficiency of service divisions– Control development expenses at level appropriate to balance with current profitability
CORP IR / May 31, 201773

R&D Expenses, Capex Plans
 Implement product development needed for growth, while raising efficiency andmaintaining profits
 Capex (development + production facilities) to be limited to around ¥15.0B annually(Billion Yen)
100

R&D expenses
81.5

73.2

78.6

94.0
71.3

76.2

100.0-110.0

83.8

50

0

FY2012 FY2013 FY2014 FY2015 FY2016 FY2017 FY2018(Estimate)(Billion Yen)
Depreciation
Capex
50
42.0
39.5

25

24.1 21.726.6

24.8
12.7

0

CORP IR / May 31, 2017

20.8
13.1

19.2 20.617.8
13.3

24.0

FY2012 FY2013 FY2014 FY2015 FY2016 FY2017 FY2018(Estimate)

FY2020(Medium-term plan)

≒25.0
≒15.0

FY2020(Medium-term plan)74

Assets and Capital Efficiency (Sales ¥1,200B Model) Accounts receivable turnover

EPS and ROE
(Yen)
1,000

– Current approx. 60 days: Appropriate

EPS
800

 Inventory turnover– Current 108 days

ROE

702

20- 25%600

461→ Target 95 days

19.1%

400

13.0%
200

 ROE
– Current 19%→

Target 20-25%

0FY2016FY2017

FY2020(Target)ROE = (Net income attributable to owners of parent /Average total equity) x 100(%)

CORP IR / May 31, 201775

Medium-term Financial Targets (toward FY2020)
Aim for sustained growth in corporate value and continue to develop nextgeneration products while maintaining a global standard level of profitability
WFE*

Market size

$42B

$45B

Net sales¥1,050B¥1,200B

24%

26%

Operating margin
ROE (Return on Equity)

20-25%• WFE (Wafer fab equipment): The semiconductor production process can be divided into two sequential sub-processes: front-end (wafer fabrication) and back-end (assembly and test)
production. WFE is used in the front-end production process. Front-end production equipment includes equipment for wafer-level packaging.

CORP IR / May 31, 201776

Capital Policy, Shareholder Returns
 Approach to capital policy– While closely monitoring the business environment and our necessary cash balance, wewill strive to raise ROE through earnings maximization and asset turnover improvement toefficiently utilize shareholders equity

 Approach to shareholder policy– Business trends in our industry can be volatile and our policy is to link dividend payments
to business performance– However, to assure stable returns to our shareholders, we will utilize our sound financial
foundation to establish a minimum DPS payment

Dividend payout ratio:

50%

Annual DPS of not less than ¥150
We will review our policy if the company does not generate net income for 2 consecutive fiscal years

We will flexibly consider share buybacks
CORP IR / May 31, 201777

Summary Steadily work to achieve our FY2020 financial model Further strengthen product competitiveness, aim for sales growth
greater than market growth Raise development efficiency and business productivity, further
improve profitability

Pursue a global standard level of profitability,
aim for sustained growth in corporate value

CORP IR / May 31, 201778

Appendix

CORP IR / May 31, 201779

Field Solutions (FS) Business: Medium-term Plan
FS business strategy

Field Solutions sales
WFE$45B

400¥320.0B

350

WFE$42B

300¥270.0B
260.0

250
200
150

170.0
77.0

185.0

208.0

115.0

93.0

Used equipment
and modification

120.0

180.0

105.0

115.0

FY16

FY17

150.0

Parts and services

 Contribute to improving customer
productivity– Provide added-value services using
remote connections

50

0
FY15

– Provide upgrades andremanufactured equipment that
handle new applications

93.0

80.0
145.0

100

140.0

 Respond to new customer needs
driven by IoT

FY18 (E)FY20(Medium-term plan)(Installed base of 62,000 units)

Increase earnings in both the used equipment/modification and parts/service
segments through a business model that utilizes makers’ strengths
CORP IR / May 31, 201780

SPE Business Strategy: Deposition System
Aim to expand earnings based on new technologies for further
miniaturization and next-generation semiconductors
ALD system

CVD system

 Achieve both high quality film formation and highproductivity needed for miniaturization and for 3D
structure with semi-batch system
ALD system market ¥150.0B

 Differentiate in memory through our clear lead inbatch system productivity
 Achieve high quality metallization to enable further
miniaturization

CAGR >10%¥90.0B

Semi-batch ALD system
NT333™

2014

2015

2016

2017

2018

Batch system
TELINDY PLUS™

2019

Source: TEL estimate

Market share

CY14 (Actual)

CY15 (Actual)

CY16 (Actual)

Deposition system

38%

38%

37%

Metallization system
Triase+™

・・・

Source: Gartner, “Market Share: Semiconductor Wafer Fab Equipment, Worldwide, 2016”, 30 March 2017, Charts/graphics created by Tokyo Electron based on Gartner research.
Deposition System: Tube CVD + Atomic layer deposition tools + Oxidation/diffusion furnaces + Nontube LPCVD

CORP IR / May 31, 2017

CY19 (Target)

>47%
81

Adjustment to Share Results due to Product Recategorization(etching system, cleaning system) From CY2016 dry cleaning systems have been recategorized under etching system, and actual
shares for etching system and cleaning system for CY2014, CY2015 and CY2016 have beenadjusted to reflect thisBeforeadjustment

Market share

CY2014

CY2015

CY2016

Etching system

26%

19%

21%

Cleaning system

24%

23%

25%

CY2014

CY2015

CY2016

28%

21%

23%

19%

18%

20%

(Including dry cleaning systems)

Afteradjustment

Market share
Etching system(Including dry cleaning systems)

Cleaning system

CORP IR / May 31, 201782 Disclaimer regarding forward-looking statement
Forecast of TEL’s performance and future prospects and other sort of information published are made based on information available
at the time of publication. Actual performance and results may differ significantly from the forecast described here due to changes invarious external and internal factors, including the economic situation, semiconductor/FPD market conditions, intensification of sales
competition, safety and product quality management, and intellectual property-related risks.
 Processing of numbers
For the amount listed, because fractions are rounded down, there may be the cases where the total for certain account titles does notcorrespond to the sum of the respective figures for account titles. Percentages are calculated using full amounts, before rounding.
 Exchange risk
In principle, export sales of Tokyo Electron’s mainstay semiconductor and FPD panel production equipment are denominated in yen.
While some settlements are denominated in dollars, exchange risk is hedged as forward exchange contracts are made individually at
the time of booking. Accordingly, the effect of exchange rates on profits is negligible.
 Disclaimer regarding IHS Markit data (Page 63, 65)
The IHS Markit reports and information referenced herein (the "IHS Markit Materials") are the copyrighted property of IHS Markit Ltd. (“IHS Markit”) and represent data, research,opinions or viewpoints published by IHS Markit, and are not representations of fact. The IHS Markit Materials speak as of the original publication date thereof (and not as of thedate of this offering document). The information and opinions expressed in the IHS Markit Materials are subject to change without notice and IHS Markit has no duty or
responsibility to update the IHS Markit Materials. Moreover, while the IHS Markit Materials reproduced herein are from sources considered reliable, the accuracy andcompleteness thereof are not warranted, nor are the opinions and analyses which are based upon it. To the extent permitted by law, IHS Markit shall not be liable for any errors
or omissions or any loss, damage or expense incurred by reliance on the IHS Markit Materials or any statement contained herein, or resulting from any omission. No portion of
the IHS Markit Materials may be reproduced, reused, or otherwise distributed in any form without the prior written consent of IHS Markit. Content reproduced or redistributed with
IHS Markit’s permission must display IHS Markit’s legal notices and attributions of authorship. IHS Markit and the IHS Markit globe design are trademarks of IHS Markit. Other
trademarks appearing in the IHS Markit Materials are the property of IHS Markit or their respective owners.

 Disclaimer regarding Gartner data (Page 81)
All statements in this presentation attributable to Gartner represent Tokyo Electron’s interpretation of data, research opinion or viewpoints published as part of a syndicatedsubscription service by Gartner, Inc., and have not been reviewed by Gartner. Each Gartner publication speaks as of its original publication date (and not as of the date of thispresentation). The opinions expressed in Gartner publications are not representations of fact, and are subject to change without notice.

CORP IR / May 31, 2017

FPD: Flat panel display

83