ISSUE 2, 2024

How to use an ideal diodecontroller as a scalable input
bypass switch in solar applications
How anti-aliasing filter design
techniques improve active RFconverter front ends
Designing 4mA to 20mA
loop-powered transmitters
Impact of voltage reference noise on
ADC ENOB and noise-free resolution

Table of contents

02

How to use an ideal diode controller
as a scalable input bypass switch insolar applications
Solar optimizers can now support higher input voltages thanks
to efficiency improvements gained by lower conduction losses
for a given power level and lower system costs. This article
discusses a scalable bypass circuit solution using a floatinggate ideal diode controller to address challenges related to
bypass switches with wide voltage support in solar power
applications.

Designing 4mA to 20mA loop-poweredof voltage reference noise on
07 transmitters
20 Impact
ADC ENOB and noise-free resolution
Industrial field transmitters are essential to process
automation. The majority of these transmitterscommunicate with the PLC or DCS systems
through a 4mA to 20mA current loop, which offersa highly robust connection in harsh industrial
environments. This article explains the design
targets and boundaries of a 4mA to 20mA
transmitter circuit, as well as different
implementations of loop-powered, 4mA to 20mA
transmitters, performance differences and where
each is used.

While every analog-to-digital converter (ADC) has
a specified number of bits, perhaps it is more
important to consider the effective number ofbits (ENOB). Careful voltage reference selection
and implementation are essential to improve theprecision and accuracy of your ADC signal chain.
Learn how to implement a voltage reference in to
improve performance in this article.

anti-aliasing filter design
13 How
techniques improve active RFconverter front ends

When using an anti-aliasing filter between the
output of an FDA and the input of the ADC, there
will be several trade-offs to consider during theimplementation process. These include filter
order and topology, or whether you will need backtermination or series resistances to enhance theinterface between the FDA and the ADC. In thispaper, we explain these AAF nuances and how
to circumvent any huddles encountered in yournext design.

ISSUE 2, 2024

Analog Design Journal

How to use an ideal diode controller asa scalable input bypass switch in solar
applications
Yang Wu
Analog Field Applications Engineer
China East Sales
Abhijeet Godbole
Systems Engineer
Analog Power Products
Dilip Jain
Systems Manager
Analog Power Products

Introduction

ideal diode controller. This circuit addresses challenges
related to bypass switches with wide voltage support inIn solar photovoltaic (PV) systems, module-level power

solar power applications such as solar power optimizers,

electronics (MLPE) improve power-yield performance

rapid shutdown and PV junction boxes.

under certain conditions, especially in shade. Once

What is a solar power optimizer?

considered a costly specialty category, MLPE is now
one of the fastest-growing market segments in the solar

Figure 1 illustrates a PV system with a solar powerindustry. A solar power optimizer is one type of MLPE

optimizer installed on an individual PV panel.

that optimizes the power output of the PV panel andPV1

increases efficiency.

PV2

PVn
DC+

PV String

Conventional solar power optimizers use a P-N junction

Solar Panel

Solar Panel

AC
Inverter
DC-AC

Solar Panel

Grid

diode or a Schottky diode for the bypass circuit. When
String Inverterhigh current flows through the diode, the high-power
Power
Optimizer

dissipation can cause severe thermal issues because

Power
Optimizer

Power
Optimizer
DC–of the diode’s relatively high forward voltage drop. An

Figure 1. PV system with a solar power optimizer.

improved method uses a metal-oxide semiconductor
field-effect transistor (MOSFET) with a lower voltage drop

Think of a power optimizer as a compromise between

than diodes to overcome the high-power loss.

a microinverter and a string inverter. It is installed
on individual solar panels like a microinverter, but its

Additionally, solar optimizers can now support higher

function has nothing to do with converting DC to AC

input voltages – up to 150V transient with two PV panels

electricity. A power optimizer tracks the maximum power

in series – thanks to the efficiency improvements gainedof each solar panel in real time and regulates the output

by lower conduction losses for a given power level,

voltage before sending it to the inverter. Therefore, theand lower system costs. In this article, we’ll discuss

inverter can process much more electricity. The resulta scalable bypass circuit solution using a floating-gate

How to use an ideal diode controller as a scalable input bypass switch in solar
applications

is optimized power-yield performance for every single

2

Issue 2, 2024

Analog Design Journal
solar panel, regardless of orientation to the sun, shade or

into the inverter input. Deploying the optimizers to theeven damage to one or more panels. Solar systems withcorresponding PV panels obtains the highest efficiency,

power optimizers installed at each PV panel can be 20%

as shown in Figure 2. The PV string is actually connected

to 30% higher in efficiency compared to one without anby the outputs of the optimizer. If any one of the solar

individual panel-level optimizer.

panels fails, then the PV string voltage can collapse,
as all of the PV panels are connected in series. An

Output bypass function of a solar power
optimizer

output bypass circuit provides a parallel path to thestring current around the damaged optimizer. Figure 2

For high-power solar inverters, connecting multiple PV

shows how the bypass function works when one of thepanels in series achieves a high DC input voltage goingPV panels breaks.

Solar Power Optimizer
PLC Comm.

PV +

VO +

Input
EMI Filter

Solar Panel
PV –

MPPT
DC-DC
(Buck)

Bypass Circuit
VO –Connection flow
withbypass switch

Solar Power Optimizer
PLC Comm.

PV +

VO +
StringInverterInput
EMI Filter

BrokenSolar Panel
PV –

MPPT
DC-DC
(Buck)VO –Solar Power Optimizer
PLC Comm.

PV +

VO +

Input
EMI Filter

Solar Panel
PV –

MPPT
DC-DC
(Buck)

Connection flow
withbypass switch

Bypass Circuit
VO –Figure 2. Output bypass junction of a solar power optimizer.

Output bypass circuit solutions

diode solution, using an N-channel MOSFET, which has
a much lower voltage drop and lower power losses

There are typically two kinds of solutions for the bypass(because of low RDS(on)), is an alternative. There are still

circuit. The common way to achieve bypass functionality

some drawbacks, however:to use P-N junction diodes or Schottky diodes, as shownin Figure 3. It’s low cost, easy to use and can achieve a• The MOSFET is not a stand-alone solution –very high reverse voltage based on the diode selected.

it requires a control circuit to operate it as a

There are drawbacks, however, such as a high forward

switch, usually a microcontroller (MCU) with discrete

voltage drop (0.5V to 1V), which causes higher power

MOSFET driver circuit.

dissipation and larger printed circuit board requirements.

• The MCU needs power from the PV panel. So if

In order to overcome the disadvantages of the bypass

How to use an ideal diode controller as a scalable input bypass switch in solar
applications

the PV panel is badly damaged or fully covered by

3Issue 2, 2024

Analog Design Journal
shadows or shade, then the MCU will not work anddiode of the MOSFET. But body diode of the MOSFET

the MOSFET cannot turn on,

cannot withstand large currents and will accumulate
high degrees of heat that can risk fire.

• In cases when the MCU fails, the MOSFET cannot
be turned on, and the bypass path is through body
Solar Power Optimizer

Bypass circuit using P-Njunction diode or Schottky diode.

Bypass Switch Scheme 1

PLC Comm.

PV +

VO +

MPPT
DC-DC
(Buck)Input
EMI Filter

Solar Panel
PV –

VO –

Solar Power Optimizer
PLC Comm.

Bypass Switch Scheme 2

Bypass circuit using MOSFET.

PV +

VO +

MPPT
DC-DC
(Buck)Input
EMI Filter

Solar PanelMCU control

PV –

VO –

Solar Power Optimizer
PLC Comm.

Bypass Switch Scheme 3

Bypass circuit using MOSFET.

PV +

VO +

Input
EMI Filter

Solar Panel

MPPT
DC-DC
(Buck)

LM746x0-Q1
Controller

PV –

VO –

Figure 3. Typical solutions when using a bypass switch in solar optimizers.

An intelligent way to address the drawbacks of an

However, as solar inverter power levels increase, andMCU-based on or off control scheme is to use a stand-the adoption of higher-voltage PV panels increases, thealone MOSFET controller that can work autonomously

bypass circuit has a few requirements to make it a better

without any external intervention. The LM74610-Q1

solution than traditional ones. It needs to work with afamily of floating-gate ideal diode controllers from

PV panel voltage ranging from 20V to 150V to makeTexas Instruments provides a stand-alone, low-loss

it scalable across multiple platforms, and it should be

bypass switch solution by controlling the external N-

independent from other circuits.

channel MOSFET to emulate series diode behavior.
These controllers have a floating gate-drive architecturethat can operate with an input voltage as low as
the MOSFET’s body diode forward drop (approximately
0.5V).

How to use an ideal diode controller as a scalable input bypass switch in solar
applications

4

Issue 2, 2024

Analog Design Journal
Q1 (Power-Path FET)

A scalable bypass switch solution using a
low-voltage ideal diode controller

PV+

PV–

QD (Depletion FET)The bypass circuit solution uses an ideal diode controller

ANODEwith a floating gate-drive architecture (such as the

CATHODE

LM746x0-Q1

LM74610-Q1) to drive an external MOSFET and emulate

VCAPL

an ideal diode as the bypass circuit so that it is

Equivalent Circuit

independent from other circuits. Its floating gate-drive
architecture can achieve a universal input range, as

GATE

VCAPH

VANODE < VCATHODEVANODE >= VCATHODE
Q1

PV–

PV+

the gate drive does not respect to ground. In addition,

QD

a unusual advantage of this scheme is that it is not

~PV+
ANODE

referenced to ground and thus has zero quiescentGATE

CATHODE

Q1

PV–

PV+

QD in source follower mode

PV– + VT_QD
ANODE

Ideal Diode Controller

GATE

CATHODE

Ideal Diode Controller

current.
Figure 4. Scalable bypass switch solution.

When solar panels and solar equipment operate
voltage equal to the maximum panel voltage appears

Working principle of LM74610-Q1 reversevoltage range extension

from the cathode to the anode pins of the ideal diode

Depletion-mode MOSFETs are by default on whencontroller. However, the reverse voltage (PV+ to PV–)MOSFET VGS is 0V, unlike enhanced-mode MOSFETs

normally, the bypass MOSFET is off, and the reverse

from the cathode to the anode pins of the ideal diodethat require VGS to be greater than the threshold voltage

controller can be very high as the PV panel and stringof the MOSFET. In order to turn off the depletiontransient voltage. In cases where the PV panels are used

MOSFET, VGS needs to be <0V (typical ranges are fromin series with a very large input voltage range, it can be–1V to –4V). To analyze the effect of the depletion-mode

challenging to design the maximum input voltage range

MOSFET in an ideal diode-sense path, let’s look at

for the bypass circuit. The maximum reverse voltage

device operation under these conditions:of the LM74610-Q1 is limited to 45V transient. Thus,• When VPV– VPV+: The ideal diode controller is incurrently available ideal diode controller devices are notforward-condition mode, keeping both the powersuitable for solar panels with a rated input voltage of 80V

MOSFET Q1 and depletion FET QD on. Withor 125V.

these operating conditions, you can calculate theAdding a depletion MOSFET QD in the sense path tooutput voltage as VOUT = VIN – (ID_Q1 RDS(on)_Q1),

extend the reverse voltage range of the ideal diodeapproximated to VPV+.

controller sustains this voltage level for any range, as• When VPV– < VPV+: The ideal diode controller is in theshown in Figure 4. The drain of QD connects to output

reverse current blocking condition, with MOSFET Q1

PV+. The source connects to the cathode and the gate

turned off. MOSFET QD is in regulation mode as aconnects to the anode of the ideal diode controller.

source follower, maintaining VCATHODE above VANODE,VCATHODE = VIN(VANODE)+ (VGSMAX). So the voltage
across VCATHODE to VANODE is within the absolute
maximum rating VGSMAX of QD (usually <5V), which
is far less than the maximum reverse voltage of
45V transient of the LM74610-Q1. The high reverse

How to use an ideal diode controller as a scalable input bypass switch in solar
applications

5

Issue 2, 2024

Analog Design Journal
voltage (VOUT – VIN) is sustained by the drain-tosource voltage (VDS) of QD and Q1.

This enables high-voltage designs using the same lowvoltage controller. Also, extending the input voltage range

Selecting the correct depletion MOSFET and power

can also be useful in enterprise, communication, power

MOSFET depends on these points:

tool and high-voltage battery-management applications.

• Choose a VDS rating of Q1 and QD greater than theConclusion

maximum peak input voltage.

If PV panels or solar equipment connected in a series are• Select RDS(on) such that dissipation across the power-

broen or faulty, it is important to have a design in place

path MOSFET is lowest. The drain current (ID) of theto avoid hot spotting and/or voltage supply interruption.

FET should be higher than the maximum peak current

This responsibility commonly lies with the solar power

demanded by the output load. Selecting a depletion

optimizer or rapid shutdown. While standard rectifier

MOSFET with a drop of 50mV to 100mV across thediodes or Schottky diodes are the simplest solution to

power MOSFET at the full load current is a good

bypass the broken panel, they aren’t preferred given

starting point.

thermal inefficiency. A floating-gate ideal diode controller• RDS(on) can be in the hundreds of ohms range (thealong with an N-channel MOSFET offers less stand-alone

LM74610-Q1’s floating gate-drive architecture has aloss than a bypass switch solution, and an additionallarge impedance of cathode pin to ground, and thesystem workaround with a depletion MOSFET offers a

ICATHODE of the controller is in the microamperes

completely scalable solution to address the wide input

range).

voltage range of PV panels.

Figure 5 shows test results for a 60V bypass switch
solution using the 40V LM74610-Q1 controller.

Additional resources• LM74610-Q1 Zero IQ Reverse Polarity Protection
Smart Diode Controller Data Sheet

Figure 5. Test results for a 60V bypass circuit with the LM74610-

Q1 and depletion MOSFET.

With properly scaled MOSFETs (Q1 and QD), the input
voltage range can extend to the VDS rating of the FETs.

Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard
terms and conditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before
placing orders. TI assumes no liability for applications assistance, customer’s applications or product designs, software performance, or infringementof patents. The publication of information regarding any other company’s products or services does not constitute TI’s approval, warranty or
endorsement thereof.
All trademarks are the property of their respective owners.
© 2024 Texas Instruments Incorporated

SLYT855

Analog Design Journal

Designing 4mA to 20mA loop-poweredtransmitters
Ahmed Noeman
System Engineer
SEM FAC, Freising

Introduction

4mA to 20mA transmitter basics

In any process control system, sensor transmitters

4mA to 20mA transmitters are classified by power andcollate data from pressure and temperature to flow andnumber of wires: four, three and two wire. In this article, I

level, and relay this information to the programmablewill focus on the two-wire type.

logic controller (PLC) or distributed control system.

The two-wire field transmitter in Figure 1 forms a current

These transmitters depend on the 4mA to 20mA signal

loop by connecting to a field supply and analog input

to transmit data to the controller. Despite the emergencemodule. The first subsystem in the field transmitter isof standards such as IO-Link and Profibus, 4mA to 20mA

the sense subsystem, which connects to the physicaloffers resiliency over long distances, reliability, immunity

sensor, conditions its output, and converts the signal

to noise, and universal compatibility with every PLC

to a digital code for processing, including linearization

system.

and calibration. The second subsystem is the transmit
subsystem, which powers the transmitter by extracting

In this article, I will provide an overview of the 4mA to

power from the loop, sends process data by converting

20mA transmitter structure, its operating principles, andthe digital signal back to an analog signal, and controls

design alternatives for implementing this transmitter typethe loop current. The transmitter transmits the signal byusing catalog semiconductor products.

regulating current within the loop, acting as a voltagecontrolled current source.
24V

Loop+

power

I LoopSensor

ADC

uC

DAC

Rshunt

Loop-

Sense
signal conditioning
convert & process

Field
SupplyTransmit
current regulation
power and protect
ADC
Analoginput
Module2-wire 4mA to 20mA
sensor transmitter

Figure 1. Generic two-wire 4mA to 20mA sensor transmitter.

Designing 4mA to 20mA loop-powered transmitters

7

Issue 2, 2024

Analog Design Journal
In Figure 2, an N-channel P-channel N-channel (NPN)• A small footprint.

transistor sources and regulates the current, whose base

• Accuracy and low noise over the entire industrial

is controlled through an amplifier driven by a digital-

temperature range.

to-analog converter (DAC). A wide input voltage low-

• HART protocol support.

dropout (LDO) regulator powers the different components• Low cost.

by stepping down the loop voltage to the transmitter

Design performance metrics

supply level. You can use a voltage reference if
the DAC does not have an integrated reference,

There are several transmitter performance metrics towhile Highway Addressable Remote Transducer (HART)-evaluate:enabled transmitters require a HART modem.

Loop Compliance Voltage is the range of the loop
voltage at which the transmitter is functioning. It is

REF

LDO

mainly determined by LDO limits and affected by series
elements within the loop, including protection devices.
The typical loop compliance voltage range is 12V to 36V.
Resolution is the number of distinct current output
values that the transmitter can generate and is directly

DAC

linked to the DAC native resolution. Commercial 4mA to
20mA transmitters have resolutions between 12 bits andR1

16 bits.
Linearity error is mostly determined by the DAC’s

HART
modem

integral nonlinearity, which is the maximum error (in least

Rsensesignificant bits [LSBs]) over the whole output range.
Noise is measured by the root-mean-square (RMS) of
output noise current. This noise can render some of

Figure 2. Two-wire 4mA to 20mA transmitter circuit.

the output level indistinguishable, reducing the effective

The principle of operation is pretty simple: hold bothresolution. Effective resolution in this context is a

inputs of the operational amplifier at virtual local ground.

measure of noise performance. For 16-bit-resolution

Whatever voltage R1 holds, Rsense also holds. Withsystems, effective resolution between 13 bits and 15 bits

proper scaling, Rsense carries a scaled version of theis expected, depending on signal bandwidth.

R1 current. Given that Rsense current is nearly thewhole current of the field transmitter (even for the sense

Accuracy measures the deviation of the current output

part, not depicted in Figure 2), the DAC output controls

from the ideal current value. This includes the RMS sum

the whole transmitter current. The NPN transistor

of offset errors, gain errors and nonlinearity error, plus theand amplifier loop bypass the necessary current totemperature drifts of these values. Total unadjusted error

complement any current used by the transmitter itself inindicates the level of inaccuracy.

order to achieve the required output current.

Dynamic performance includes signal bandwidth and4mA to 20mA transmitter design aspects

transmitter stability. Bandwidth refers to the maximum
current signal bandwidth that can be transmitted over4mA to 20mA transmitter design considerations include:

the loop. This bandwidth is determined by the DAC• Low-power operation.

Designing 4mA to 20mA loop-powered transmitters

8

Issue 2, 2024

Analog Design Journal

Dedicated loop converter

settling time and amplifier circuit bandwidth, as well as
the transconductance of the bypass transistor. Using

One approach is to use a DAC such as the DAC161S997

a degeneration resistor eliminates the dependence ondata sheet with an integrated voltage reference andvariation of the transistor transconductance (gm). Often,

output amplifier. This solution consists of the DAC, a

the amplifier circuit is externally compensated as well.

wide-input-voltage LDO and an NPN transistor, as shown

Stability is related to the bandwidth of the loop andin Figure 4. This implementation has 130µA of current

compensation capacitor values. Reducing capacitanceconsumption and excellent accuracy without calibration.

on critical nodes of the loop will ensure stability. See

The DAC161S997 has diagnostic functions to detect

the DAC161S997 data sheet for a detailed analysis ofcurrent-loop errors in case of low supply or high current

loop stability and its requirements. For HART-enabled

loads, and signals an error-low current below 4mA.

transmitters, reducing the bandwidth with external
components helps prevent interference with the HART

The design is simple, with a few external components

signal.

to ensure loop stability and limit inrush current. Thisapproach has a maximum operating temperature of

Circuit protection protects the transmitter from abnormal

105°C.

conditions such as reverse loop polarity and surge

LDO

events. Reverse polarity is blocked by a diode. If
operating the transmitter with reverse polarity, use a

VD

rectifier bridge, as shown in Figure 3. Surge protection
requires a transient voltage suppressor diode (such as

VA
Internal
Reference

SCLK
SDI

IN

Sensor

SPI

SDO

16

SPI

 DAC

+
IDAC

–

BASE


COMD

CSB

LOOP
RECEIVER

VD

during high-voltage events. These protection elements

COMA
80k
INT

require some headroom during operation, and increase

ERRB

GND

40

DAC161S997
OUT
NC

the minimum compliance voltage.

C1

C2

C3

LOOP-

ERRLVL

HART Modulator

Loop+

Figure 4. Two-wire 4mA to 20mA transmitter using the

DAC161S997.

Loop transmitter device

TVS

Another implementation uses a low-power DAC such as
the DAC8551, followed by a dedicated loop transmitter
Loop-such as the XTR115 with an integrated LDO, voltage

Figure 3. Typical protection section for two-wire transmitter.

reference and output amplifier. This approach minimizes

Transmitter circuit implementations

noise and has less than 1% gain error.

The difference between the implementations for the

There are a couple of limitations: the XTR115 operating

block diagram in Figure 2 lies in the integration

temperature is limited to 85°C, and the integrated LDO

approach. The bypass transistor is always a discrete

has a maximum input of 36V. As an alternative, thecomponent to enable better thermal management. All

XTR117 comes in a smaller package, consumes lowerof the following implementations can support the HART

quiescent current, and operates at temperatures as highprotocol by adding a HART modem such as theas 125°C. The XTR117’s integrated LDO works up to

DAC8740H.

40V. The XTR117 does not integrate a voltage reference,

Designing 4mA to 20mA loop-powered transmitters

9LOOP
SUPPLY

0-24mA Loop+µC

the TVS3301) and passive elements to limit current

LOOP+

Issue 2, 2024

Analog Design Journal
VREF-

so counting an external reference, the solution becomes

VDD 3.3V

MSPM0G
integrated analog

a three-device solution: an LDO, a DAC and a voltage

VDD

XTR117
VREG

RIN

R3
R5
Q1

7
B
6

DAC8551

R19

M0
DAC12

V+

5V
Regulator

8

VIN

VREF

reference, as shown in Figure 5.
REF3525

TPS7B69-Q1

Q1
R16

IIN
GPAMP

2

0.01µF

A1

D1

E
5

RLIM
IRET
3

R12

R20

IO = 100VIN
R1
2.475kR2
25k

Figure 6. Two-wire 4mA to 20mA transmitter implemented using

RIN

the MSPM0G.

4

Figure 5. Two-wire 4mA to 20mA transmitter using the XTR117.

PWM-based DAC

MCU integrated DAC

A more generic approach using an MCU (without an

Cost-sensitive applications can employ an MCU withintegrated DAC) is to rely on pulse-width modulation

analog resources. The MSPM0G MCU enables a(PWM) to generate DAC outputs. A simple PWM DAC

transmitter stage implementation including an integrated

has a resolution of 10 bits to 12 bits. However, it is12-bit DAC, internal reference and output amplifier. An

possible to realize a 16-bit resolution DAC with more

LDO is the only external device needed, as shown inadvanced techniques such as two-path PWM and active

Figure 6. Given the implementation of analog functions

ripple suppression.

on the MCU’s digital process, they have relatively higher

To achieve a high effective resolution, the PWM

power consumption compared to their dedicated analog

signals are buffered using voltage reference-powered

device counterparts. This approach is attractive forlogic gates; the MCU needs proper bypassing toapplications that require 11 bits of effective resolution

avoid digital noise injection into the loop current. The

at a very low cost. Using the VREF– pin as an internal

implementation depicted in Figure 7 is low power, stablereference negative pin instead of ground can improveover temperature, and achieves greater than 13 bits ofperformance. Separating the VREF– pin isolates digitaleffective resolution at a very low cost.

noise from the analog reference.

D2
VSUP=3V

RH

PWMH

LDO

REF3330

TPS7A1601-Q1

Current
limiter

R19
Loop
Current

Rf

1
RL

2
PWML

RH

Rf

V1

Cs

V2

R3
R5
Q1

TVS3300

RL
Cf

D1

Loop Supply

MSPM0

REF

R16
SN74LVC2G240

PWM scaling &Ripple suppression

2ndorder LPF

OPA2333

R12
R14

ILoop

R20

C5

HART in

Voltage to Loop Current
Converter

D3

Figure 7. Two-wire 4mA to 20mA transmitter implemented using a PWM DAC.

Designing 4mA to 20mA loop-powered transmitters

10

Issue 2, 2024

Analog Design JournalStand-alone low power DAC

digital operation and reduce power further on the MCU
input/output side, as well as reducing electromagnetic

Using a low-power, stand-alone DAC to realize a 4mA toemissions.

20mA transmitter such as the AFE88101 in Figure 8

1.8V

achieves the best resolution and linearity performance.

U3
Q1
TPS7A1601

To reduce power further, a low-power voltage reference

D6

5.1V

REF35125such as the REF35125 can reduce current down

U4

to 180µA. Additionally, the AFE88101 has extensive
R3

diagnostic features, including a 12-bit ADC and a defined
fail-safe mode.

AFE88101

D1

Q2
OPA391U2The AFE881H1 is pin-to-pin compatible with the

R4

U1
R1

AFE88101, with an integrated HART modem for a

R2compact HART-enabled transmitter. The AFE881H1 has

Figure 8. Two-wire 4mA to 20mA transmitter implemented using

low current consumption when HART is enabled. A

the AFE88101.

HART modem typically consumes 10µA during operation,
making it the device of choice for low-power, HART-

A lower-cost variant with the DAC8311 DAC, LDO andenabled transmitters. Another feature of the AFE88101

external low-power reference runs with 130µA of current

is compatibility with 1.8V logic to allow low-voltage

and still achieves reasonable performance.

Implementations Comparison
Table 1 and Table 2 show each of the implementations, their suggested bill of materials (BOM) and their expected
performance. The performance numbers are based on limited measurements.
MSPM0 DAC12

PWM using M0
REF

REF

XTR117
LDO

REF

LDO

LDO

DAC

DAC

MSPM0G

XTR117
HART
modem

HART
modem

HART
modem

PWM (M0) +FLTBOM

MSPM0G, TPS7B69, DAC8740H

TPS7A1601, REF3330, TLV2333, DAC8740H

XTR117, DAC8551A, REF3525

Compliance (volts)

40

60

40

Resolution (bits)

12

16

16

Linearity (LSBs)

2

<6

8

Effective resolution (bits)

11

13.4

14

Accuracy

1% full scale, 6uA

1% full scale, 6uA

0.7% full scale, 20uA

Current (μA)

425

240

440

Temperature (°C)

125

125

105

Advantages

Low cost

Low cost, high resolution, low powerhigh resolution

Table 1. Design options for a 4mA to 20mA transmitter, suggested BOM and performance (MSPM0 DAC12, PWM using M0, XTR117).

Designing 4mA to 20mA loop-powered transmitters

11

Issue 2, 2024

Analog Design Journal
DAC161S997

DAC8311

AFE881H1

REF
REF

LDO
REF

LDO

LDO
AFE881H1

DAC161S997
DAC
DAC

DAC
DAC8311

HART
modem

HART
modem

BOM

DAC161S997, TPS7A1601, DAC8740H (1)DAC8311, REF3525, OPA391, TPS7B69,
DAC8740H

AFE88101 (1), REF35125, OPA391, TPS7A1601

Compliance (volts)

60V

40

60

Resolution (bits)

16

14

16

Linearity (LSBs)

5

4

4

Effective resolution (bits)

13.4

13.4

16

Accuracy

0.01%, 1uA

0.15%

0.07%

Current (μA)

130

130

180 (240 w/intREF)

Temperature (°C)

105

125

125

Compliance (volts)

Ultra-low power, high resolution, high accuracy

Ultra-low power, low costhigh resolution and accuracy, low power, lowvoltage

Table 2. Design options for a 4mA to 20mA transmitter, suggested BOM and performance (DAC161S997, DAC8311, AFE881H1).
(1)

The DAC8740 has maximum power-down current of 180µA, and about 300µA when active with a crystal oscillator. The AFE881H1 HART modem,
however, consumes 10µA on average. Add the corresponding current if enabling HART.

Conclusion
This selection process can help you decide thecorrect implementation when designing a 4mA to 20mA
transmitter:• If you are building a safety system, and need thehighest accuracy and lowest noise performance, or
looking for a HART-enabled transmitter with power
below 200µA, the AFE88101 and AFE881H1 should
be your first choices.
• The DAC161S997 implementation offers the lowest
possible power and footprint, followed by the
DAC8311 implementation, followed by the XTR117
implementation if prioritizing performance over power
consumption.

• For the lowest cost, choose the MSPM0G
implementation. If its performance is not satisfactory,
the next cost-optimized solution would be the PWM
solution.

Related websites• 4mA-20mA Current Loop Transmitter Reference
Design• Dual Sensor Measurement Using Single CurrentLoop with FSK Modulation Reference Design• 2-wire, 4mA-20mA Transmitter, EMC/EMI Tested
Reference Design• High-Performance 16-bit PWM to 4mA to 20mA
DAC for Field Transmitters• Designing High-Performance PWM DACs for Field
Transmitters• Ultra-Low-Power, Low-Voltage, 2-Wire, 4mA to
20mA Loop Transmitter Using AFE881H1• Highly Accurate, Loop-Powered, 4mA to 20mA Field
Transmitter With HART Modem Reference Design

Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard
terms and conditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before
placing orders. TI assumes no liability for applications assistance, customer’s applications or product designs, software performance, or infringementof patents. The publication of information regarding any other company’s products or services does not constitute TI’s approval, warranty or
endorsement thereof.
All trademarks are the property of their respective owners.
© 2024 Texas Instruments Incorporated

SLYT847

Analog Design Journal

How anti-aliasing filter design
techniques improve active RF converter
front ends
Rob Reeder
Application Manager
High-Speed Data Converters
1. Understand the amplifier’s characterized load

Introduction

impedance (RL). In order for the amplifier to perform

Active analog-to-digital (ADC) front ends using a fully

at its best, the amplifier should “see” the correct

differential amplifier (FDA) can offer a host of advantages,

DC load or RL listed in the data sheet for optimum

such as better impedance matching, pass-band flatness

performance. This is the characterized impedanceand signal gain. However, if you require only a portion

typically found at the top of the specification tables.

of the ADC’s band for your next design, it might be

2. Determine a starting point for the correct amountnecessary to use an anti-aliasing filter (AAF) between theof output series resistance to use closest to the

output of the FDA and the input of the ADC. An AAF will

amplifier’s outputs. This helps prevent unwanted

yield better signal-to-noise (SNR) performance and lower

peaking in the pass band. You’ll also typically findspurious or spurious-free dynamic range (SFDR) within

this information in the FDA’s data sheet - LMH5401

your frequency band requirements.

8-GHz, Low-Noise, Low-Power, Fully-Differential

With any kind of AAF filter constructions, you will have

Amplifie Data Sheet.

several trade-offs to consider during the implementation

3. Determine whether to use one or more external

process: filter order and topology, or whether you willparallel resistors to back-terminate the input toneed back termination or series resistances to enhance

the ADC, and the starting value of the input

the interface between the FDA and the ADC. In thisseries resistance to isolate the ADC from the filter.

paper, I’ll discuss these AAF nuances and how to

These series resistors also help reduce unnecessary

circumvent any huddles you might encounter in your next

peaking in the pass band and “kickback” commonly

design.

found in unbuffered ADCs.

AAF design approach
Assuming that you have decided on the correct FDA
for your application and whether to use either a lowpass or band-pass filter in order to achieve optimum
performance (bandwidth, SNR and SFDR) in front of the
ADC, follow these three steps:

How anti-aliasing filter design techniques improve active RF converter front ends

13

Issue 2, 2024

Analog Design Journal
Figure 1 shows an example of the specification table.

Figure 1. Electrical specification table excerpt from the LMH5401 data sheet, where RL = 200Ω.

The generalized circuit shown in Figure 2 and filter parameter list in Table 1 apply to most high-speed differential FDA
and ADC interfaces; you can use both as a basis for the AAF design.
Although not every filter construction will be exactly the same, Figure 2 can serve as a blueprint on how to kick-start
your design. Using this design approach will tend to minimize the insertion loss of the filter by taking advantage of therelatively high input impedance of most high-speed ADCs and the relatively low output impedance of the driving source(the FDA).

RA

RTAMP

ZO

CAAF2

0.1u

ZAL

ADC

RTADC

LAAF2
LAAF1

LAAF1
RA

RKB

LAAF1

LAAF1

Amp
RI

CAAF3

CAAF1

0.1u

RADC ||CADC

CAAF1

CAAF3

ZAAFS

ZAAFL

RKB
ZAL = 2RA + (ZAAFL || RTAMP)ZAAFL = RTADC || (RADC + 2RKB)ZAAFS = RTAMP || (ZO + 2RA)

Figure 2. Generalized FDA and ADC interface with a band-pass filter.
SymbolParameter description

Ri

Amplifier input impedanceZo

Amplifier output impedanceRA

Series output resistance located near the amplifier’s outputs

RTAMP

Back-termination resistance near the amplifier outputs

CAAF1

First AAF capacitor

LAAF1First AAF inductor

CAAF2

Second AAF capacitor

LAAF2

Second AAF inductor

CAAF3

Third AAF capacitor

RTADC

Back-termination resistance near the ADC inputs

RKB

Series kickback resistor located near the ADC’s inputs

ZAL

Aggregate load impedance as seen by the amplifier

ZAAFS

Aggregate source impedance of the AAF

ZAARL

Aggregate load impedance of the AAF

Table 1. Filter parameter definitions.

How anti-aliasing filter design techniques improve active RF converter front ends

14

Issue 2, 2024

Analog Design Journal
the filter is –6.0dB or 10*log(50/200). Also, using

AAF design process and parameters

a bandwidth that is about 10% more or higher

The basic AAF design process and guidelines are:than the desired bandwidth of the application will
ensure that the intended bandwidth is covered per

1. Set the external ADC termination resistor (RTADC)
appropriately. This helps the AAF realize a “real”

the application, and help overcome any second- andimpedance over its desired frequency response.

third-order parasitic losses unrealized during the filter
implementation process.

2. Select RKB based on experience or the ADC
data sheet recommendations; typically, this will be

After running a few preliminary simulations, give thebetween 5Ω and 50Ω.

circuit a quick review for the following items:

3. Use Equation 1 to calculate the filter load impedance

8. The value of CAAF2 & 3 should be sufficiently big

so that the aggregate parallel and series combination

relative to CADC, which minimizes the sensitivity ofof RTADC, RKB and RADC is between 100Ω and 400Ω.

the filter to variations in CADC.

See my recommendation in the previous section.
ZAAFL - RTADC || (RADC + 2RKB)

9. The ratio of ZAAFL to ZAAFS should not be more than
6-to-7, so that the filter is within the limits of most(1)

filter tables and design programs. Ideally, they should
4. Select the amplifier external series resistor (RA).

be the same to minimize loss, but this is not usuallyThis is typically between 5Ω and 50Ω. RA helps

possible.

dampen the amplifier output response and reduce

10. Try to use a value of CAAF2 in the few picofarads

unnecessary peaking in the pass band.

range to minimize sensitivity to parasitic capacitance

5. Use the calculated ZAAFL so that the total load seen

and component variations.

by the amplifier (ZAL) is optimal for the particular

11. Inductors LAAF1 and LAAF2 should be reasonabledifferential amplifier chosen. See Step No. 1 above invalues and in the nanohenries range.

the AAF Design Approach Section and use Equation

12. The value of CAFF2 and LAAF2 should be reasonable2:values; select these two parameters to optimize the
ZAL = 2RA + ZAAFL

filter’s center frequency. Sometimes circuit simulators(2)

can make these values too low or too high. To make
Keep in mind that ZAL is the FDA’s characterized RL;

these values more reasonable, simply ratio these

therefore, using too high or too low a value can havevalues with better standard-value components thatan adverse effect on the amplifier’s linearity.

maintain the same resonant frequency.

6. Calculate the filter source resistance using Equation

13. Use 0201 package styles if possible when designing3:in the gigahertz range to minimize second- and thirdZAAFS = ZO + 2RA

order parasitic effects that could disrupt the filter(3)character shape or outline.

7. Using a filter design program, design the filter using

In some cases, the filter design program may provide

the same source and load impedances, if possible,

more than one unique solution, especially with higher-

ZAAFS and ZAAFL. This helps reduce the amount oforder filters. Always choose the solution that uses theloss in the filter. Any mismatch between the input/

most reasonable set of component values. For filter

output impedance has a loss of 10*log(input Z/output

configurations that end with a shunt capacitor, take theZ). For example, with an input impedance of 50Ω

ADC’s internal input capacitance into consideration as

and an output impedance of 200Ω, the loss of

How anti-aliasing filter design techniques improve active RF converter front ends

15

Issue 2, 2024

Analog Design Journal
well. You may need an iteration or two to set the filter

can have a net positive or net negative affect on AAF

pole and ultimate bandwidth correctly.

bandwidth performance.

AAF design trade-offs

Notice in Figure 3 how the pass-band peaking isenhanced or flattened as the value of the FDA’s output

The parameters in this interface circuit are very

series resistance (RA) changes (the blue dashed curves).

interactive; therefore, it is almost impossible to optimize

As the value of this resistance decreases, there is more

the circuit for the primary specifications (bandwidth,

signal peaking, and the amplifier can drive the signal lessbandwidth flatness, SNR, SFDR and gain) without

to fill the ADC’s full-scale input range at the cost of thesmall trade-offs. However, you can minimize bandwidth

pass-band flatness response near the edge of the AAF

peaking, which often occurs at the tail end of thefrequency response.

bandwidth response, by varying RA, RKB, or both; either

0-5

Amplitude (dBFS)

-10
-15
-20
RA = 8 Series RKB = 5 Series
RA = 8 Series RKB = 10 Series
RA = 8 Series RKB = 15 Series
RA = 8 Series RKB = 30 Series
RA = 2 Series RKB = 15 Series
RA = 18 Series RKB = 15 Series
RA = 24 Series RKB = 15 Series
RA = 36 Series RKB = 15 Series

-25
-30
-35
-40
0

1E+9

2E+9
3E+9
Frequency (Hz)

4E+9

5E+9

Figure 3. Pass-band flatness performance vs. RA and RKB variations.

The value of RA could also affect SNR performance.

When optimizing for the AAF’s rolloff frequency, varying

Smaller values, while enhancing bandwidth peaking,CAAF2 by a small amount allows you to correct fortend to decrease the SNR because of the increased

optimal frequency coverage for the application.

bandwidth and unwanted noise.

Normally, determining the value of the ADC input

It’s also important to select the RKB series resistor on thetermination resistor, RTADC, makes the net ADC

ADC inputs to minimize distortion caused by any residual

input impedance look near typical of most amplifiercharge injection from the internal sampling capacitor

characteristic load (RL) values. Selecting too high or too

within the ADC. However, increasing this resistor also

low a value for RTADC can have an adverse effect on thetends to enhance or reduce bandwidth peaking as well,amplifier’s linearity, which will then be reflected in thedepending on the filter topology.

overall SFDR signal-chain lineup.

How anti-aliasing filter design techniques improve active RF converter front ends

16

Issue 2, 2024

Analog Design Journal

AAF design example

for the final filter passive components (after adjusting for
actual circuit parasitics).

The design example circuit shown in Figure 4 is a
wideband low-pass receiver front end based on the

The AAF was designed as a third-order Butterworth

Texas Instruments (TI) TRF1208, a 10MHz to 11GHz,

filter using a standard filter design program with a

3dB-bandwidth single-ended to differential amplifier anddifferential source impedance (ZAAFS) of 39Ω (2 ´

the TI ADC12DJ5200RF, a radio frequency (RF) sampling18Ω + 3Ω), a differential load impedance of 103Ω

12-bit dual-channel 5.2GSPS ADC. I optimized the third-(ZAAFL) and a cutoff frequency of 2.4GHz. Because

order Butterworth AAF based on the performance andof the higher values of series inductance required ininterface requirements of the amplifier and ADC; thesimulation, I decreased these inductors to 3nH in order

total insertion loss caused by the filter network andto account for the inherent trace inductances in theother components was less than 6dB. In this AC-coupledlayout and proportionally increased the initial 1.8pF

design, the 0.1µF capacitors block the common-mode

capacitors to ground in the simulations to 2.2pF, thereby

voltages between the amplifier, its termination resistors,

helping maintain appropriate rolloff around the 2.4GHz

and the ADC inputs.

requirement.

The 10MHz to 11GHz TRF1208 differential amplifier

The TRF1208 was not back-terminated in this case inaccepts a single-ended input and converts it to aorder to achieve net performance, and the net differential

differential signal operating at a gain of 16dB to

impedance load was 139Ω (ZAL). Implementing thecompensate for the insertion loss of the filter network,18Ω series resistors isolated the filter capacitance fromproviding an overall signal gain of +7.8dB.

the amplifier outputs. For further insight on the FDA’s
impedances, you candownload the S-parameters .

An input signal of –6.8dBm produces a full-scale 800mV

Installing the 15Ω resistors in series with the ADC inputs

peak-to-peak differential signal at the ADC input.

isolated the internal switching transients from the filter

The overall circuit has a bandwidth of 2.34GHz withand the amplifier, as well as providing the necessary

a pass-band flatness of <3dB. The SNR and SFDR

characterized loading to the FDA.

measured with a 534MHz analog input frequency are
52.5dBFS and 71.4dBFS, respectively. The sampling

I used the ADC’s 100Ω input impedance per the data

frequency is 5.2GSPS, thereby creating a wideband low-

sheet. For further insight on the ADC’s impedances,pass filter covering the entire first Nyquist zone between

download the S-parameters.

10MHz and 2.5GHz. Figure 4 shows the values chosen

18

2.2μF

Amp
RI

15

0.1u
3nH

3nH

3nH

3nH

500

ZO
18

RADC ||CADC
15

0.1u
2.2pF

ZAL

ZAAFS

ADC

RADC = 100
CADC = 0.2pF

ZAAFL

Figure 4. FDA, AAF, ADC wideband receiver front-end design (simplified schematic).

How anti-aliasing filter design techniques improve active RF converter front ends

17

Issue 2, 2024

Analog Design Journal
Table 2 summarizes the measured performance of the system, where the total insertion loss of the network is
approximately 5.8dB.
Performance specs at –1dBFS (FS =0.8V peak to peak), sample rate =5.2GSPS, JMODE 3

Final results

Cutoff frequency

2,340MHz

Pass-band flatness (10MHz-2.2GHz)<3.0dB

SNR full scale at 534MHz

52.5dBFSSFDR at 534MHz

71.4dBFS

H2/H3 at 534MHz–71.4dBFS/–73.0dBFS

Overall gain at 534MHz+7.8dB

Input drive at 534MHz-12.8dBm (−6dBFS)

Table 2. Measured performance of the circuit.

Figure 5 shows the resulting combined FDA, AAF and ADC signal chain’s frequency response.

0-2–3dB BW@ 2.34GHz

Amplitude (dBm)

-4
-6
-8
-10
-12
-14

–6dBFS Reference Point
Input Drive Level = –12.8dBm @ 534MHz

-16
-18
-20
1E+7

5.2E+8

1.03E+9 1.54E+9 2.05E+9 2.56E+9 3.01E+9
Frequency (Hz)Figure 5. Pass-band flatness performance vs. frequency.

How anti-aliasing filter design techniques improve active RF converter front ends

18

Issue 2, 2024

Analog Design Journal

SNR/SFDR (dBFS)

Figure 6 shows the SNR and SFDR performance versus frequency, respectively.

80
78
76
74
72
70
68
66
64
62
60
58
56
54
52
50

SFDR
SNR

0

6E+8

1.2E+91.8E+9Frequency (Hz)

2.4E+93E+9Figure 6. SNR/SFDR performance vs. frequency, sample rate = 5.2GSPS.

AAF design conclusion

Additional resources

Understanding all of the different factors, parameters

1. Keysight ADS Simulationand trade-offs involved in designing an AAF between

Software: https://www.keysight.com/us/en/an FDA and RF ADC can be more difficult than it

products/software/pathwave-design-software/

seems. The design example described in this article

pathwave-advanced-design-system.html.

gives each parameter equal weight; therefore, the values

2. Ansys/Nuhertz Technologies, Filter Solutions

chosen represent the interface performance for all of the

Design Program: https://www.ansys.com/products/

design characteristics. In some designs, you may choose

electronics/ansys-nuhertz-filtersolution .

different values to optimize SFDR, SNR or input drive

3. Reeder, Rob. 2022. “Evaluating high-speed RF

level depending on system requirements. Keep all of

converter front-end architectures.” Planet Analog,

these necessary points in mind so that your next AAF

April 7, 2022.

doesn’t go resonant.

4. Reeder, Rob. 2022. “A close look at active vs.
passive RF converter front-ends.” Planet Analog,
January 24, 2022.
5. Bowick, Chris. 1997. “RF Circuit Design.” Boston,
Massachusetts: Newnes.

Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard
terms and conditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before
placing orders. TI assumes no liability for applications assistance, customer’s applications or product designs, software performance, or infringementof patents. The publication of information regarding any other company’s products or services does not constitute TI’s approval, warranty or
endorsement thereof.
All trademarks are the property of their respective owners.
© 2024 Texas Instruments Incorporated

SLYT853

Analog Design Journal

Impact of voltage reference noise on
ADC ENOB and noise-free resolution
Jackson Wightman
Applications Engineer
Voltage References
Shridhar More
Systems Manager
Voltage References

Introduction

In a voltage reference, it is also not possible tofilter out flicker noise (which is noise from 0.1Hz toMultiple systems ranging from thermostats to flight10Hz) without having a major impact on signal chain

control employ an analog-to-digital converter (ADC)

performance because of the size of the resistor-capacitor

to capture real world analog signals which will befilter components you’ll need. Therefore, noise will almost

processed in the digital domain and take necessary

always be present in your system.

actions based off of the digital results. Each ADC
specifies a number of bits to represent the various digital

In addition to the voltage reference noise, there will be

levels it can produce. For a given constant ADC input,

noise from the ADC itself and the ADC driver. Each one

the output of the ADC is not a constant digital valueof these components contributes noise to the circuit that

due to various errors in a typical signal chain. Thus,

generates a digital signal. Figure 1 is a simplified block

it is important to consider the effective number of bits

diagram of this circuit.

(ENOB) or the noise-free resolution of the signal chain
AnalogInput

for better comparison and to also extract maximum

DriverADC

DigitalOutputinformation from the captured data. Higher precisioncalls for higher ENOB and noise free resolution.
Typically, signal-to-noise ratio (SNR), total harmonic

Voltage
Reference

distortion (THD) and noise of the system play animportant role in ENOB calculation. For multiple

Figure 1. Generic ADC circuit configuration with an external

systems like field transmitters or test and measurement

voltage reference.

applications, DC input signal accuracy and precision is

Equation 1 expresses the total noise of this circuit as:

critical. Therefore, the noise specification becomes mostcritical. The voltage reference used with an ADC is a

Total Noise =critical component in the signal chain that can impact the

Noise2Driver + Noise2ADC + Noise2VREF(1)The amount of noise present in your circuit is important

precision and accuracy.

to know when determining your system’s ENOB. In

The impact of the voltage reference on ADC
noise

general, selecting low-noise devices is essential to a lownoise design.

While it is possible to remove some noise by filtering,
you cannot realistically filter out noise at low frequencies.

Impact of voltage reference noise on ADC ENOB and noise-free resolution

20

Issue 2, 2024

Analog Design Journal
In this article, I’ll focus on not only voltage reference

represents these two AC characteristics in one number,selection, but other data processing choices that can

as expressed by Equation 2:

help you maximize ADC performance.

SINAD dB = − 20log 10−SNR/10 + 10THD/10

The impact of the voltage reference on THD(2)

From Equation 2, you can see that as the SNR increases,

Repeated sampling of the voltage reference pin can

SINAD also increases. Thus, the less noise and distortion

cause current transients to appear that may only bepresent, the better the SINAD. Using SINAD, you canseparated by a few nanoseconds. However, for an ADC,

use Equation 3 to easily find the ENOB of your ADC -the external reference must settle or recharge by the end

especially since:of the sample phase in order to avoid a large gain error.
Slowing the sampling speed could fix this issue, but that− 1.76dB
ENOB = SINAD6.02

is not always an option. Typically, the more precise the(3)

ADC, the more current draw required on its reference

Revisiting Equation 1, decreasing the total noise present

input. If a voltage reference does not have high-enoughin the voltage reference would decrease the total noise

bandwidth, or has too high of an output impedance, it

present in the circuit, leading to an increased SNR.

will not be able to recharge the reference input of theWith an increased SNR, the ENOB will also increase.

ADC. This will cause a voltage droop, leading to gain

Additionally, adding a high-bandwidth buffer on theerror and lower ENOB.

output of the voltage reference would also lead to a

For this reason, a high-bandwidth, low-output-

decreased THD of the ADC, allowing the ENOB to

impedance buffer external to the voltage reference isincrease.

sometimes necessary to increase the THD of the ADC

How voltage reference noise affects noisefree resolution

and meet the data-sheet specifications for distortion and
ENOB. Some ADCs have an internal voltage reference

While ENOB valuably represents the resolution of yourbuffer, but not all do. Figure 2 shows where to add an

ADC output, it does not account for DC performance.

external buffer to increase the THD of your circuit.
Analog
Input

DriverADC

To understand the resolution implications of noise from a
DC input to your ADC, consider finding the noise-free

DigitalOutputresolution of your circuit. Using Equation 4 you cancalculate the noise-free resolution by observing the code
spread in number of least-significant bits (LSB) of an

Voltage
Reference

ADC’s digital output while measuring a DC signal:
Buﬀer

Figure 2. Generic ADC circuit configuration with an external

To highlight the impact of reference noise on the system

voltage reference and reference buffer.

precision performance, my colleagues and I conducted

How voltage reference noise and THD affectthe ENOB

DC code spread tests for a given signal chain using the
REF70 (with 0.23ppmp-p flicker noise) and the REF50

ENOB measures how the AC characteristics of your(with 3ppmp-p flicker noise). Both the REF50 and REF70

circuit affect your ADC resolution. The noise and THD

are high-precision voltage references used with high-of your circuit are represented by a term known as

precision ADCs, and have differing DC characteristics.

signal-to-noise ratio and distortion (SINAD). SINAD

Impact of voltage reference noise on ADC ENOB and noise-free resolution(4)

Noise Free Resolution = N − log2 Code Spread

However, in this exercise, the goal was solely to compare

21

Issue 2, 2024

Analog Design Journal
the noise performance of these devices in a signal-chain

bandwidth noise. The difference in the average code

circuit.

value is because of the reference voltage difference –an accuracy specification that you can eliminate throughThe design uses batteries for a stable DC source withcalibration. These results can be seen in Figure 4 anda voltage level close to the full-scale range of the

Figure 5.

ADS8900B 20-bit SAR ADC, which captures data at
20kSPS. OPA2320 is used with a gain = 1 to drive the
ADS8900B inputs. This ADC integrates the reference
buffer driver; therefore, an optional reference buffer is not
required. Placing a simple resistor-capacitor low-passfilter on the output of the voltage reference further lowers
the noise from the voltage reference. Figure 3 shows the
setup used for these tests.
Reference

DC InputfromBattery

OPA2320

Figure 4. Results with REF50 noise = 3ppmp-p.

RC LPF

ADS8900B

OutputFigure 3. The circuit used for the following noise-free resolution

tests.

The signal-chain components beside the voltage
reference also have flicker noise, which will be part of
the final code spread. Because the signal chain remains
the same with different references only, the impact

Figure 5. Results with REF70 noise = 0.23ppmp-p.

on performance numbers must be from the voltage

We used the Octave tool to conduct post-processing ofreference noise only.

the raw data with three different digital filters:

High-precision systems employ data-processing• 1,024-tap moving average filter.

techniques to improve the precision and increase the• 801-tap 17Hz low-pass filter.

overall resolution. In this experiment, we converted the• 455-tap 36Hz low-pass filter.

20-bit raw data from the ADS8900B to a 24-bit length
by multiplying the output by 16. Different finite impulse
response (FIR) filters processed the converted 24-bit
data. FIR filters are easy to implement and settle faster
if there’s a change in the input values. The output data
rate remains at 20kSPS, but with latency as defined by
the filter characteristics.
At a 24-bit level, the noise (and thus the precision) of
REF50 and REF70 are almost similar, with the overallnoise dominated by the signal chain and its wide

Impact of voltage reference noise on ADC ENOB and noise-free resolution

22

Issue 2, 2024

Analog Design Journal
Figure 6 shows the filter response for these filters.

Figure 8. 455-tap filter histogram.
Figure 6. Digital filter response.

Figure 7, Figure 8 and Figure 9 illustrate the impact ofthe digital filter on the code spreads.

Figure 9. 801-tap filter histogram.

Figure 7. 1,024-tap filter histogram.

Using Equation 4,you can easily compare the impact of the REF50 and REF70 with each filter profile on the ADC
resolution. The results from these tests are summarized in Table 1.

Digital filte type

Corner frequency(Hz)

Number of taps

DC code spread(LSB)

Noise-freeresolution (bits)

DC code spread
least significan bit

REF70 at 24 bits

Noise-freeresolution (bits)

REF50 at 24 bits

No filter

N/A

0

448

15.1

496

15.0

1,024 tap moving
average

8

1,024

35

18.8

118

17.1

FIR No. 1

17

801

38

18.7

121

17.0

FIR No. 2

36

455

49

18.3

135

16.9

Table 1. Comparison of DC code spread using different filter profiles and reference devices.

Impact of voltage reference noise on ADC ENOB and noise-free resolution

23

Issue 2, 2024

Analog Design JournalThis comparison shows that in the highest precisionapplications, the REF70 performs better than the REF50
when calculating noise-free resolution, mostly becauseof the devices’ difference in flicker noise levels. The
reduced code spread when using the REF70 shows thatits ultra-low noise can offer nearly a 2-bit resolution
advantage in high-precision applications. Additionally, we
can see that using a low noise reference allows using
a fast 455 tap filter while still being able to maintain ahigh noise free resolution. Low voltage reference flicker
noise will lead to lower code spread, thus enablinghigher noise-free resolution. Like the ENOB, noise is
an important consideration when designing your signal
chain for low noise-free resolution.

Conclusion
As ADCs are used in thousands of applications
and technologies, there will always be a need toobtain better accuracy and higher precision. Whether
you are designing a highly advanced x-ray system,
an exceptionally precise battery test circuit, or any
other world-leading innovation, careful voltage reference
selection and implementation are essential to improve
the precision and accuracy of your ADC signal chain. You
will increase the ENOB and noise-free resolution of your
ADC, enabling more advanced and diverse signal-chain
implementations.

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