ΔΣAD Converter Linearity Test Algorithm using FFT Method

3B-07

Jiang-Lin Wei*, N. Kushita, T. Arai, L. Sha, A. Kuwana, H. Kobayashi, T. Nakatani, K. Hatayama
K. Sato, T. Ishida, T. Okamoto, T. Ichikawa
Division of Electronics and Informatics Gunma University, 1-5-1 Tenjin-cho Kiryu, Japan 376-8515
ROHM Semiconductor Co., Ltd., 2-4-8 Shin Yokohama, Kohoku-ku, Yokohama, Japan 222-0033* Email:t171d601@gunma-u.ac.jp

2. Research Background

1. Research Objective
High resolution, low speed ΔΣ ADCΔΣ ADC

IOT（Internet of things）● Sensor interface key components

Testing of IOT devices● Mass production test

important.

Massproduction

Miniaturization

Our Studies
 Linearity test takes a long time..

AnalogIntegrator+

input

Quantizer

Digitaloutput∑−Digital
FilterHighDigital

Chip priceFeedback

Low speed

Test cost

High reliability requirements

High linearity

ΔΣ Modulator

lowHigh resolution

High speed

Large-scale

Analog<Application>

 Perform its linearity test in a short time Measurement

Mass production shipment of IOT devices requires
high quality & low cost testing.

 Develop its algorithm Audio system4. Calculation of Polynomial Coefficients

3. Proposed Test Method

１- bit output
Analog input

ΔΣ ADmodulator

A cos(ωt)

Digital output
24Digital
Filter32ksps

Digital output

ΔΣ ADC

7sps 24bit

Data decimation
32,000 1-bit data output
per second

ΔΣ ADC

Cosine input :Output characteristic model :𝒙 𝒕 = 𝑨𝟎 𝐜𝐨𝐬 𝝎𝒕𝒚 𝒕 = 𝒂𝟏 𝒙 𝒕 + 𝒂𝟑 𝒙(𝒕)𝟑

I/O characteristics model
Analog input
𝟑Test output pin
3td order model for simplicity :Seven 24-bit data
output per second

FFT analysis

𝒚 𝒕 = 𝒂𝟏 𝒙 𝒕 + 𝒂𝟑 𝒙(𝒕)th5. Modulator 3 -order Nonlinearity Model𝒚 𝒕 = (𝒂𝟏 𝑨𝟎 + 𝟒 𝒂𝟑 𝑨𝟎 𝟑 )𝒄𝒐𝒔𝝎𝟎 𝒕

Fundamental

𝟏+ 𝒂𝟑 𝑨𝟎 𝟑 𝒄𝒐𝒔𝟑𝝎𝟎 𝒕
𝟒3rd harmonics

𝟑6-1. Simulation Verification

20-bit first-order LP case
Modulator output number of 1's

DC Input Simulation Configuration: The number of data ：N=2𝟐𝟎

𝑉𝑚 = E − 𝑘 ∗ E 𝟑 （k>0）

E n = Vin n − Vf n

 Vin：DC= -1.0 ～ +1.0

Vm n = E n − 𝑘 ∗ E n 𝟑 k > 0

 K=0.0001, 0.0005, 0.001

Vin +E−M∑

V0200000-1-0.8-0.6

0.005, 0.01

If Vo n ≥ 0;0-0.2
0-200000

0.2

0.4

0.6

0.8

Else Dout n + 1 = 0; Vf n + 1 = −1

20-bit first-order Low-Pass case

Amplitude
k=0.0001

k=0.0005

k=0.001

k=0.005

k=0.01k
0.00010.0005
0.001
0.005
0.01

a3
104.84524.481050.55282.510643

a2
0.16206
0.16206
0.16206
0.16206
0.16206

a1524180
523760523240519000513610c-0.032331-0.032331-0.032331-0.032331-0.032331

7. Conclusion● High resolution, low speed ΔΣ ADC linearity short time test algorithm

Fundamental estimation error of 20-Bit
0.000160.00014Modeling by polynomial of modulator input / output characteristics

Error

0.00012

Cosine Input Simulation Configuration:

0.00010.00008

FFT of modulator 1-bit output stream for cosine input

0.00006
0.00004
0.00002 The number of data ： N = 2𝟐𝟎

00.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Amplitude
k=0.0001

 Vin ： 𝑨𝟎 𝐜𝐨𝐬 𝝎𝒕𝑨 = 𝟎. 𝟏~𝟏

k=0.0005

k=0.001

k=0.005

k=0.01

Estimate polynomial coefficientsfrom fundamental and harmonic powers

3rd harmonics estimation error of 20-Bit
0.8
0.7● Verified by simulation with a simple model

0.005, 0.01

Error

0.6

 K = 0.0001, 0.0005, 0.001,

0.5
0.4
0.3
0.2
0.1
00.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Amplitude
k=0.0001

k=0.0005

k=0.001

k=0.005

1

Estimated coefficient values in polynomial model of ΔΣAD modulator
DC input/input characteristics

Dout n + 1 = 1; Vf n + 1 = 16-2. Simulation Results-0.4-400000

k=0D𝑜𝑢𝑡Vｆ400000-600000

Vo n = Vo n − 1 + Vm n𝑉𝑚Total number of 1's

3th-order nonlinearity model

600000k=0.01

1● Also verified by experiment, which will be reported.

。