Status of BELLE upgrade
Yoshikazu YAMADA (KEK-IPNS)at 44th KEKB Suishin Iinkai on June 11, 2001••••

Upgrade Points of Inner Tracker
New Beam Pipe for IP
SVD2
Small Cell Chamber

1. Upgrade Points of Inner Tracker•Better impact parameter resolution→ 1.5 cm  σ∆z : 100 µm → 75 µm
Rbp : 2.0 cm→•Larger acceptance for SVD
Ladder length : 22 cm → 46 cm  23º < θ < 139º → 17º < θ < 150º
•Better tracking efficiency
RSVD-outermost : 6.0 cm→→ 8.8 cm  eff. of slow π : 54 % → 77 %•More radiation hardness for SVD
VA1−−0.8 µm → VA1−−0.35 µm  1 MRad → >5 MRad
•Better trigger capability•VA1 → VA1TA (VA1 with trigger)•Introduction of Level−−1.5 trigger in SVD FADC system•Introduction of Small cell chamber•Faster SVD / CDCsmallcell electronics
 trigger rate @ design current : 1400 Hz → 500? Hz•Installation in Summer 2002

Design modification
Beam pipe : Rin = 2.0 cm
SVD1 : R = 3.0, 4.5, 6.0 cm
CDC : 3 layers of Cathode part

Beam pipe : Rin = 1.5 cm
SVD2 : R = 2.0, 4.35, 7.0, 8.8 cm
CDC : 2 layers of small cell chamber

Acceptance
23 º < θ < 139 º

17 º < θ < 150 º

2. New beam pipe for IP•Simulation study on beam background
SVD1.4

SVD1.4

SVD2

SVD2

Rbp=2.0cm@ 0.6/0.8A

Rbp=2.0cm@design current

Rbp=1.5cm@design current

Rbp=1.0cm@design current# of layers/R1st3/3.0cm

3/3.0cm

4/2.0cm

5/1.5cm

SVD 1st layer dose(krad/yr=107s)~40~130~80~660

CDC 1st layer Occup.

≡1~3~1.5~3.6

SVD 1st layer Occup.

≡1~3~ 0.9~8σ∆Z (µµm)~100~100××1.2?

~75~50××1.3?

•BELLE Executive Board discussed background issue and concluded
Rbp=1.5 cm for SVD2 (Rbp=1.0 cm is too risky)•Better cooling capability (He  PF200)•Under final design and will be fabricated by Apr. 2002

BELLE electronics hut

3. SVD2

Timing control
and monitor
FADC/DSP(digitizing system) readout system

Electronics

LadderTTM
128 input channels

Analog signal
In the BELLE complex
Hybrid~2mABCHybrid

total:~80k stripsTrigger rate Max 500Hz

DSSD
FLEX

Support structure

DSSD

~30m

640strip(one hybrid)/ADC-ch~20cm

DSSD

Control signal

RAMBO

REBO

REBO

REBO

REBO
Repeater system
MAMBO
detector bias
electronics
power supply•DSSD (Tokyo) :•delivered for 1st, 2nd and 3rd layers•designed for 4th layer and will be delivered from Sep. 2001
•prototype delivered andtested with DSSD/VA1•VA1TA/Hybrid (Princeton) :•prototype will be delivered and tested end of June

•Ladder assembly (KEK/Melbourne) :•under prototyping and final design•Ladders will be assembled by Apr. 2002

•Support structure (KEK) :•under prototyping and final design

28.4•FLEX (Taiwan) :79.6

Front-end Electronics

Gain vs. rad. dose40•VA1-0.35 : tested with DSSD+FLEX to 5 Mrad
20

VA-0.35
t=500ns
00

1000
2000
3000
4000
radiation dose (krad)
0pF•VA1TA

Semigaussian
slow shaper

S/H
Multiplexer

TA

vdd

Levelsensitive
Discriminator

Monostable(fixed width)

1000

500

ENC(VA)
ENC(leak)H 2(s)
Semigaussian
fast shaper

Total noise vs. Radiation dose (3 DSSD)

1500

ENC (electrons)

analog out

H1(s)ChargeIntegrator(preamp.)

50pF

Expected noise for 3 DSSD ladder•Fast shaper and discriminator•Radiation hardness up to 10 MRad confirmed•2 or 4 analog output from a hybrid•will be delivered and tested end of June

VA1

20pF

5000

vssTrigger
Out

ENC(total)
00

2

4
6
Radiation dose (MRad)810

Backend Electronics•Repeater system (Krakow) : under final design•DC level shift for 2 or 4 analog signals from a hybrid•4 trigger signals from a hybrid•FADC (Vienna) and Trigger (Princeton) : under final design
Backend electronics schematic diagram
Flash-ADC module
AnalogsignalFADC

FPGA

8 hybrids/module(4098ch/module)
30 systems for 60 ladders.

Level-1.5 trigger

Data rate
Online data after sparsification
sparsification <0.3kB/s@1kHz
trigger rate.
Triggerlogicboard•PC farm for SVD DAQ (Taiwan/Frankfurt) : under test

4. CDC : small cell chamber•Prototype is being tested.
•Final one will be fabricated by Dec. 2001.