PLTBEITO Spec

PLTBEITO Specification

VersionV1.0
V1.1
V1.2
V1.3
V1.4
V1.5
V1.6
V1.7

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Note
CreateModify the shape of module
Redefine PWM Port
Redefine PWM Port and ADC Port
Add Power on Reset Sequence
Redefine Electrical Specification
Add Packing Information
Add Certification Information-1-Date2018/09/28
2018/11/09
2018/12/20
2019/01/07
2019/03/28
2019/05/17
2020/01/03
2020/12/28

Suzhou Pairlink Network Technology Ltd.

PLTBEITO SpecThis document contains information that is proprietary to Pairlink . This document is commerciallyconfidential and must NOT be disclosed to third parties without prior consent. The information
provided herein is believed to be reliable. But production testing may not include testing of allparameters. Pairlink reserves the right to change information at any time without notification.

Contents
1.Functional Characteristics.........................................................................................................- 3 1.1.Product Feature............................................................................................................. - 4 1.2. Main Application Domain............................................................................................. - 4 2.Electrical Specifications.............................................................................................................- 5 2.1.Absolute Ratings............................................................................................................ - 5 2.2.Recommended Operating Conditions........................................................................... - 5 2.3.Power Consumption...................................................................................................... - 6 2.4.RF Specifications............................................................................................................ - 6 3.Physical Parameters.................................................................................................................. - 7 3.1.Peripheral Interface....................................................................................................... - 7 4.Hardware design and PCB layout..............................................................................................- 8 4.1.Pin assignment and Pin Descriptionab........................................................................... - 8 4.2.Reference Design........................................................................................................... - 9 4.3.Appearance and Dimensions.......................................................................................- 10 4.4.Recommended Land Pattern....................................................................................... - 11 4.5.Module Layout Guideline............................................................................................ - 12 5.Packing Information................................................................................................................ - 13 5.1.Rolling Information...................................................................................................... - 13 5.2.Master Carton Information..........................................................................................- 14 5.3.Label Information.........................................................................................................- 14 6. Welding Declare..................................................................................................................... - 16 -All rights reserved-2-Suzhou Pairlink Network Technology Ltd.

PLTBEITO Spec

1.Functional Characteristics
PLTBEITO is SOC module developed based on the Bluetooth 5 standards. the internal
integration architecture ARM® Cortex®-M4 processor.It has the advantage of small
volume, low power consumption, long distance transmission, strong anti-jamming
capability, low cost.Specifically applied to Bluetooth low power control area,and
suitable for various occasions short distance wireless communication.
PLTBEITO integral compact, simplifies the design in hardware and institution for user.
The module interface open completely to make the users has more flexible secondary
development space.
The module includes 24Mhz Crystal and 8Mb SPI flash. The module also integrated withIpex connector and ceramic antenna.users can better the expansion of the RFperformance.Circuit block diagram of the module is shown in Figure 1.
Figure 1: PLTBEITO Circuit Block Diagram

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PLTBEITO Spec1.1.Product Feature
1: PLTBEITO under Bluetooth 5 specification.
2: Supports Cypress proprietary data rate up to 2 Mbps.
3: Support SIG Mesh and Multi-link protocol.
4: Easy to extend SPI Flash.The default value is 8Mbit.Memory size is optional.
5: Integrated IPEX connector and Ceramic antenna
6: Support OTA function.

1.2. Main Application Domain
1: Home automation / Intelligent access control system.
2: Industrial telemetry / Industrial data collection.

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PLTBEITO Spec

2.Electrical Specifications

Integration architecture ARM® Cortex®-M4 processor
320KB RAM,2MB ROM, 64KB Patch RAM, 8Mbit Flash
Include 8Mbit SPI FLASH, Memory size is optional
Supports Cypress proprietary data rate up to 2 Mbps
Supports Generic Access Profile (GAP)
Supports Adaptive Frequency Hopping (AFH)
RF Frequency:2400MHz ~ 2483.5 MHz
Channel Spacing:2MHz
Channel Center Frequency:2402MHz~2480MHz
Modulation:GFSK

2.1.Absolute Ratings

Power Supply

Min.
-0.3

Specification
Typical-

Max.
+3.8

Current Consumption--30mA

Storage temperature-40-+150℃

Working temperature-30-+85℃

ESD HBM-2K-+2KV

ESD CDM-500-+500

V

Latch-up-200-mA

Parameter

UnitV

2.2.Recommended Operating Conditions
Parameter

Specification
Typical
3.3

Min.
2.7

Power Supply

Digital I/O Characteristic
Characteristics

SymbolInput Low Voltage

VIL

Min.
-Input High Voltage

VIH

2.0

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Max.
3.6

Specification
Typical-

Max.
0.8
-

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Unit
V

Unit
VVPLTBEITO Spec
Output low Voltage

VOL--0.4

VOutput High Voltage

VOH

VBAT-0.4V--V

2.3.Power Consumption
Current consumption measured in BLE mode with 3.30V power on in VBAT.
Operational ModeConditions

TypicalUnit

Receiving

Receiver and baseband are both operating, 100％ON

8mATransmitting

Transmitter and baseband are both operating, 100％ON

18mA

Flash Operation

Erase and write flash

22mA

18uA

Average

Unit

HIDOFF(Deep Sleep)

Current consumption measured in Pairlink connected mesh mode.
Work Mode
StatusMesh disable

Power on4mA

Discoverable

Broadcast

4.49

mA

Single modeHome id configurated

2.66mA

Connected

IN MESHnet

3.11uA

Note: These data are based on the development board with Demo_SW, only for customer reference.
The actual power consumption according to the customer's application

2.4.RF Specifications
ParameterConditions

Min.

TypicalaMax.

UnitReceiver RF Specifications
Frequency range

-2402

-

2480

MHzRX sensitivityb

--

-91.5

-

dBm

Maximum input

GFSK,1 Mbps

---20

dBm

2402

-

2480

MHz-

10-dBm248dB

Transmitter RF Specifications(TBD)
Frequency range-Class 1: GFSK TX power
Power control step-a.Typical operating conditions are 3.3V operating voltage and 25°C ambienttemperature.
b.The receiver sensitivity is measured at BER of 0.1% on the device interface.

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PLTBEITO Spec

3.Physical Parameters
Parameter

Performance

Note

Crystal

24MHz

Environment: Sunny and open
Antenna: Ceramic antenna,
Airspeed: 1Mbps
Industry Standard

ProtocolBLE4.1/BLE4.2/BLE5

Supported data rates: 1 Mbps, 2 Mbps

Package

Patch

Refer to section 4.4

IC

CYW20735B1

60PIN-QFN

RAM

320KB

ROM

2MB

FLASH

8Mb

Core

ARM Cortex-M4

Dimensions

14.0mm*23.0mm*2.6mm

L*W*H

RF Interface

1:Ceramic antenna
2:Ipex Connector

1:﹢2dBi
2:50ohm impedance matching

Distance60M

3.1.Peripheral Interface




1 x PUART interface with CTS/RTS
1 x HCI UART interface with CTS/RTS
1 x SPI interface with master/slave configurable
1 x I2C interface with master/slave configurable
10 x GPIOs
2 x ADCs input
6 x PWMs interface

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PLTBEITO Spec

4.Hardware design and PCB layout
4.1.Pin assignment and Pin Descriptionab
PLTBEITO Pin definition can refer to Figure 2.
Table 1:Module Pin Description
PinPin NameI/O

NumberPOR

Alternate Function Description

State

10VBATADI/Power Supply

1,2,20GND

GND/Connect to Ground

9RESETDI

INPUT. Reset signal (active Low). Floating if
not used

3

UART_RTS

I,PU

RTS for HCI UART interface. NC if unused.

4

UART_CTS

I,PU

CTS for HCI UART interface: NC if unused.

5

UART_TXD

O,PU

Serial data input for the HCI UART interface.

6

UART_RXD

I

Serial data input for the HCI UART interface.

7

SPI_MISOI

SPI Master In Slave Out. For Test.

8P7

DIO

Floating

GPIO:P7/PUART_CTSPWM511P4/PUART_RX

DIO

Floating

GPIO:P4/PUART_RX

12P5/PUART_TX

DIO

Floating

GPIO:P5/PUART_TX

13P6DIO

Floating

14P0/ADC0DIO

Floating

15P1/ADC1DIO

Floating

16P29/PWM3DIO

Floating

GPIO:P29/PWM317

P28/PWM2DIO

Floating

GPIO:P28/PWM218

P27/PWM1DIO

Floating

GPIO:P27/PWM119P26/PWM0

DIO

Floating

GPIO:P26/PWM0

GPIO:P6/PUART_RTS
PWM4GPIO:P0
ADC0
GPIO:P1ADC1a. All GPIOs are supermux. All GPIOs can be programmed for any alternative functions. For
example, key scan, SPI, I2C, IR_TX, quadrature, peripheral UART, PWM, etc.
b. During power-on reset, all inputs are disabled.

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PLTBEITO Spec

4.2.Reference Design
The latest schematic and design examples, bill of material, and layout file are available fromoriginal developer . Contact us for details.

Figure 2: Module Reference Design

Circuit Description
1:VBAT supply voltage value is 2.70V-3.60V.
2:PIN7(SPI_MOSI) reserved for testing.
3:PIN9(RST_L) is Module Reset_Control (active Low) ,Keep floating if the user not use.
4:Reserve JP1 burning interface if the PCB board has enough space.
5:PLTBEITO support GPIOs supermux, All GPIOs can be defined as SPI /UART/I2C.
6:Only PIN14(P0) and PIN15(P1) support ADC function.
7:PLTBEITO Power on Reset sequence.

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PLTBEITO Spec

4.3.Appearance and Dimensions
Figure 3 shows the size of the module.The components and prominent structure are not allowed
put in this size range(23.0mm*14.0mm*2.60mm).
Figure 3: Module Appearance

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PLTBEITO Spec

4.4.Recommended Land Pattern
The following land pattern size is recommended for user board design. However, user canmodify it according PCB soldering conditions. Sufficient examination is necessary if use themodified land pattern.
Figure 4: Mechanical Information

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PLTBEITO Spec

4.5.Module Layout Guideline
The layout on user PCB should be designed according to the following guideline.
Figure 5: Module Placement

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5.Packing Information
5.1.Rolling Information

Product name

MOQ

Packing method

Single package quantity

PLTBEITO

800PCS

Tape and Reel

800PCSAll rights reserved- 13 -Suzhou Pairlink Network Technology Ltd.

PLTBEITO Spec

5.2.Master Carton Information

5.3.Label InformationA) Label on module
PLTBEITO has passed BQB\FCC\CE\IC\MIC\RoHS\SRRC certificationB) Label on vacuum bag and pizza box.
Product name

PLTBEITO

Model name

Customer Corresponding Item Number

Customer PN

Customer Part Number

Quantity(PCS)

800 pcs

Product date

YY.MM.DD

Product VersionSW Version

Product Type

Bluetooth Module

MFG PNNAAll rights reserved- 14 -

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PLTBEITO SpecC) Label on carton
Product Name

Customer Corresponding Item Number

Customer PN

Customer Part Number

Quantity(PCS)

4000pcs

Produced date

YY.MM.DD

C/N

Cartoon Number

ROHS

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Tigerkin Spec

6. Welding Declare
The PLTBEITO module only supports one reflow soldering , and the module failure caused by multiple
reflow soldering is not responsible.

Figure 6: Standard Operation Procedure (SOP)

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