Digital Delay/Pulse Generator
DG645 — Digital delay and pulse generator (4 or 8 channels)

DG645 Digital Delay/Pulse Generator· 4 pulse, 8 delay outputs (opt.)· <25 ps rms jitter· Trigger rates to 10 MHz· Precision rate generator· Easy synchronization with
80 MHz mode locked lasers· Fast transition times· Ovenized crystal or Rb timebase (opt.)· Ethernet, GPIB and RS-232 interfaces

The DG645 is a versatile digital delay/pulse generator thatprovides precisely defined pulses at repetition rates up to10 MHz. The instrument offers several improvements overolder designs — lower jitter, higher accuracy, faster trigger
rates, and more outputs. The DG645 also has Ethernet, GPIB
and RS-232 interfaces for computer or network control of theinstrument.
Delay Generator Timing
All digital delay generators measure time intervals bycounting cycles of a fast clock (typically 100 MHz). Most
digital delay generators also have short programmable analog
delays to achieve time intervals with finer resolution thanthe clock period. Unfortunately, one clock cycle of timing
indeterminacy (typically 10 ns) can occur if the trigger is notin phase with the clock.
The DG645 eliminates timing indeterminacy by measuring
the timing of triggers with respect to the internal clock andcompensating the analog delays. This approach reduces thejitter by about 100× and allows the internal rate generator
to operate at any rate — not just a sub-multiple of the clock
frequency.
Triggering
The DG645 has many trigger modes. An internal rategenerator, with less than 100 ps period jitter, may be set

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DG645 Digital Delay/Pulse Generator

Front-panel outputs (50 ns/div)

The DG645 supports a number of complex triggering
requirements via a trigger holdoff and prescaling feature.
Trigger holdoff sets the minimum time between successive
triggers. This is useful if a trigger event in your application
generates a significant noise transient that needs time to decay
away before the next trigger is generated. Trigger holdoff canalso be used to trigger the DG645 at a sub-multiple of the
input trigger rate.
Trigger prescaling enables the DG645 to be triggered
synchronously with a much faster source, but at a sub-multipleof the original trigger frequency. For example, the DG645 canbe triggered at 1 kHz, but synchronously with a mode locked
laser running at 80 MHz, by prescaling the trigger input by
80,000. Furthermore, the DG645 also contains a separate
prescaler for each front-panel output, enabling each output tooperate at a sub-multiple of the trigger rate.
Front-Panel Outputs
There are five front-panel outputs: T0, AB, CD, EF andGH. The T0 output is asserted for the duration of the timing
cycle. The leading edge of T0 is the zero time reference. The
programmed delays (A, B, C, D, E, F, G and H) are set from0 s to 2000 s, with 5 ps resolution, to control the timing of theleading and trailing edges of the four pulse outputs.
Each front-panel output can drive a 50 Ω load and has a 50 Ωsource impedance. Output amplitudes can be set from 0.5 to 5.0 V,

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and output offsets can range over ±2 VDC to source virtually
any logic level (NIM, ECL, PECL, CMOS, etc.). Output
transition times are less than 2 ns at any output amplitude.
Rear-Panel Outputs
Optional rear-panel outputs are available to support diverse
applications. Option 01 provides a T0 output and eightprogrammed delays (A, B, C, D, E, F, G and H) at 5 V
logic levels, with transition times less than 1 ns. Option 02
provides these same outputs but as 30 V, 100 ns pulses withless than 5 ns transition times for timing distribution in highnoise environments. Option 03 provides eight combinatorial
outputs which deliver one to four pulses at 5 V logic levels
with less than 1 ns transition times. Each output has a 50 Ωsource impedance.

1 ms

Standard Timebase
OCXO Timebase(opt. 4)100 µsMax. Error (after 1 yr.)from 100 µHz to 10 MHz with 1 µHz resolution. An external
trigger input, with adjustable threshold and slope, can triggera timing cycle, a burst of cycles, or a single shot. A single
shot can be triggered with a key press. A line trigger operates
synchronously with the AC mains. A rear-panel trigger inhibit
input can disable the trigger or any of the pulse outputs during
a timing cycle.

Combinatorial outputs showing 3 ns, 5 ns and 10 nspulses with 1 ns transition times (5 ns/div)

Rubidium Timebase(opt. 05)

10 µs
1 µs

Ideal External Timebase
100 ns
10 ns
1 ns
100 ps10 µs100 µs

1 ms

10 ms

100 ms

1s

10 s

Delay

Timing error vs. programmed delay

100 s

1000 sDG645 Digital Delay/Pulse Generator

10 µsStandard Timebase
1 µs

OCXO Timebase(opt. 4)Jitter (rms)

100 nsRubidium Timebase(opt. 05)
10 ns
Ideal External Timebase

1 ns

100 ps

10 ps
10 µs

100 µs

1 ms

10 ms

100 ms

1s

10 s

100 s

1000

Delay

Jitter vs. programmed delayTimebases
The standard time base has an accuracy of 5 ppm, and a jitterof 10–8, which is suitable for many applications. Optional
timebases are available for users who require better rate anddelay accuracy or reduced rate and delay jitter.
The timing error for a 1 s delay can be as large as 5 µs for the
standard timebase, 200 ns for the OCXO timebase, but is only
500 ps for the rubidium timebase (all 1 year after calibration.)

DG645 (cover removed) with optional Rb timebase.
Rear panel shows the optional eight-channel outputs.

For short delays the jitter is typically 20 ps. However, for a
1 s delay, the standard timebase can contribute up to 10 ns ofjitter, while the optional timebases contribute less than 10 psof additional jitter.
Fast Rise Time Module
The DG645 front-panel outputs have transition times of lessthan 2 ns. The SRD1 is an accessory, built into an in-line BNC
connector, which reduces the rise time of a front-panel output
to less than 100 ps. Up to 5 SRD1s can be attached to the front
panel to reduce the rise time of all of the outputs.

SRD1 Fast Rise Time Module

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Ordering Information
DG645
Option 01
Option 02
Option 03
Option 04
Option 05
SRD1O645RMS
O645RMD

Delay/pulse generator
Eight delay channels (5 V)
Eight delay channels (30 V)
Combinatorial outputs
OCXO timebase
Rubidium timebase
100 ps rise time module
Single rack mount kit
Dual rack mount kit

DG645 Digital Delay/Pulse Generator

SRS
Tech
Note

More About the Outputs
A timing cycle is initiated by an internal or external trigger.
The T0 output, whose leading edge is the zero-time reference,is asserted 85 ns after the trigger. The delay settings (A, B, C,D, E, F, G and H) determine the timing of the front-panel andrear-panel outputs.

Option 02 rear-panel outputs provide 30 V, 100 ns timing
pulses at T0, A, B, C, D, E, F, G and H. Output amplitudes arereduced to 15 V when driving 50 Ω loads.

The front-panel outputs have adjustable amplitude, offset, andpolarity (non-inverted or inverted).

100 ns30 V0VToAABBCCDDEEToABCDEFGHFFAdj.
ABCGGDE

HHFGH

Opt. 02 rear-panel outputs (30 V)
Front-panel outputs (adjustable)

Option 01 rear-panel outputs provide T0 and eight delayoutputs (A, B, C, D, E, F, G and H) to allow the DG645 to be
used as an 8-channel delay generator. The outputs go from0 to 5 V at their programmed delays, and return low 25 ns after
the longest delay.
ToA
B
C
DEF5V0V

Option 03 rear-panel outputs provide outputs T0, AB, CD,EF, GH (with the same definition as the front-panel outputs),and (AB+CD), (EF+GH), (AB+CD+EF), (AB+CD+EF+GH)
which provide two, three, or four pulses per trigger.

5V0VToAABBAB+CDDEFEEFH

EF+GHGGH

H
25 ns

Opt. 01 rear-panel outputs (5 V)

AB+CD+EF
AB+CD+EF+GH

Opt. 03 rear-panel combinatorial outputs (5 V)

DG645 rear panel with Opt. 01 outputs

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DGGHF

B
CCDCADG645 Specifications

DelaysGeneral

Channels

4 independent pulses controlledin position and width. 8 delaychannels available as an option(see Output Options).
0 to 2000 s
5 ps
1 ns + (timebase error × delay)

RangeResolution
Accuracy
Jitter (rms)Ext. trig. to any output 25 ps + (timebase jitter × delay)
T0 to any output
15 ps + (timebase jitter × delay)
Trigger delay
85 ns (ext. trig. to T0 output)

Computer interfaces
Non-volatile memory
PowerDimensions
WeightWarranty

GPIB (IEEE-488.2), RS-232, andEthernet. All instrument functions
can be controlled through the interfaces.
Nine sets of instrument configurations
can be stored and recalled.
<100 W, 90 to 264 VAC, 47 Hz to 63 Hz
8.5" × 3.5" × 13" (WHD)
9 lbs.
One year parts and labor on defects
in materials & workmanship

Output Options

Timebases
Option 01 (8 Delay Outputs on Rear Panel)
Model # Type
Std.
Opt. 4
Opt. 5crystalOCXO
RbJitter(s/s)
10–8
10–11
10–11

External input
OutputStability(20 to 30 °C)
2 × 10–6
1 × 10–9
1 × 10–10

Aging(ppm/yr)
50.2
0.0005

10 MHz ± 10 ppm, sine >0.5 Vpp,
1 kΩ impedance
10 MHz, 2 Vpp sine into 50 Ω

Outputs (BNC)
Source impedanceTransition timeOvershoot
Level
Pulse characteristics
Rising edge
Falling edge

T 0 , A, B, C, D, E, F, G and H
50 Ω<1 ns<100 mV+5 V CMOS logic
At programmed delay
25 ns after longest delay

Option 02 (8 High-Voltage Delay Outputs on Rear Panel)
External Trigger
Rate

DC to 1/(100 ns + longest delay)(maximum of 10 MHz)±3.50 VDC
Trigger on rising or falling edge
1 MΩ + 15 pF

Threshold
Slope
Impedance

Internal Rate Generator
Trigger modes
Rate
Resolution
Accuracy
Jitter (rms)

Continuous, line or single shot
100 µHz to 10 MHz1 µHz
Same as timebase<25 ps (10 MHz/N trigger rate)<100 ps (other trigger rates)

Burst Generator
Trigger to first T0
Range
Resolution
Period between pulses
Range
Resolution
Delay cycles per burst

0 to 2000 s
5 ps
100 ns to 42.9 s
10 ns
1 to 232 – 1

Outputs (T0 , AB, CD, EF, and GH)
Source impedanceTransition timeOvershootOffsetAmplitude
Accuracy

50 Ω
<2 ns
<100 mV + 10 % of pulse amplitude±2 V
0.5 to 5.0 V (level + offset <6.0 V)
100 mV + 5 % of pulse amplitude

Stanford Research SystemsOutputs (BNC)
Source impedanceTransition timeLevels
Pulse Characteristics
Rising Edge
Falling Edge

T 0 , A, B, C, D, E, F, G and H
50 Ω
<5 ns
0 to 30 V into high impedance
0 to 15 V into 50 Ω(amplitude decreases by 1 %/kHz)At programmed delay
100 ns after the rising edge

Option 03 (Combinatorial Outputs on Rear Panel)
Outputs (BNC)

T0, AB, CD, EF, GH, (AB + CD),
(EF + GH), (AB + CD + EF),
(AB + CD + EF + GH)
50 Ω<1 ns<100 mV + 10 % of pulse amplitude

Source impedanceTransition timeOvershootPulse characteristics
T0, AB, CD, EF, GH Logic high for time between delays(AB + CD), (EF + GH) Two pulses created by the logic ORof the given channels(AB + CD + EF)
Three pulses created by the logic ORof the given channels(AB + CD + EF + GH) Four pulses created by the logic ORof the given channels
Option SRD1 (Fast Rise Time Module)
Rise time
Fall time
OffsetAmplitude
Load<100 ps<3 ns
0.8 V to 1.1 V
0.5 V to 5.0 V50 Ω